1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
80 #ifndef REGISTER_MOVE_COST
81 #define REGISTER_MOVE_COST(m, x, y) 2
85 #define LOCAL_REGNO(REGNO) 0
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx *reg_last_reload_reg;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static char *reg_has_output_reload;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload;
100 /* Element N is the constant value to which pseudo reg N is equivalent,
101 or zero if pseudo reg N is not equivalent to a constant.
102 find_reloads looks at this in order to replace pseudo reg N
103 with the constant it stands for. */
104 rtx *reg_equiv_constant;
106 /* Element N is a memory location to which pseudo reg N is equivalent,
107 prior to any register elimination (such as frame pointer to stack
108 pointer). Depending on whether or not it is a valid address, this value
109 is transferred to either reg_equiv_address or reg_equiv_mem. */
110 rtx *reg_equiv_memory_loc;
112 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
113 This is used when the address is not valid as a memory address
114 (because its displacement is too big for the machine.) */
115 rtx *reg_equiv_address;
117 /* Element N is the memory slot to which pseudo reg N is equivalent,
118 or zero if pseudo reg N is not equivalent to a memory slot. */
121 /* Widest width in which each pseudo reg is referred to (via subreg). */
122 static unsigned int *reg_max_ref_width;
124 /* Element N is the list of insns that initialized reg N from its equivalent
125 constant or memory slot. */
126 static rtx *reg_equiv_init;
128 /* Vector to remember old contents of reg_renumber before spilling. */
129 static short *reg_old_renumber;
131 /* During reload_as_needed, element N contains the last pseudo regno reloaded
132 into hard register N. If that pseudo reg occupied more than one register,
133 reg_reloaded_contents points to that pseudo for each spill register in
134 use; all of these must remain set for an inheritance to occur. */
135 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
137 /* During reload_as_needed, element N contains the insn for which
138 hard register N was last used. Its contents are significant only
139 when reg_reloaded_valid is set for this register. */
140 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
142 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
143 static HARD_REG_SET reg_reloaded_valid;
144 /* Indicate if the register was dead at the end of the reload.
145 This is only valid if reg_reloaded_contents is set and valid. */
146 static HARD_REG_SET reg_reloaded_dead;
148 /* Number of spill-regs so far; number of valid elements of spill_regs. */
151 /* In parallel with spill_regs, contains REG rtx's for those regs.
152 Holds the last rtx used for any given reg, or 0 if it has never
153 been used for spilling yet. This rtx is reused, provided it has
155 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
157 /* In parallel with spill_regs, contains nonzero for a spill reg
158 that was stored after the last time it was used.
159 The precise value is the insn generated to do the store. */
160 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
162 /* This is the register that was stored with spill_reg_store. This is a
163 copy of reload_out / reload_out_reg when the value was stored; if
164 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
165 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
167 /* This table is the inverse mapping of spill_regs:
168 indexed by hard reg number,
169 it contains the position of that reg in spill_regs,
170 or -1 for something that is not in spill_regs.
172 ?!? This is no longer accurate. */
173 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
175 /* This reg set indicates registers that can't be used as spill registers for
176 the currently processed insn. These are the hard registers which are live
177 during the insn, but not allocated to pseudos, as well as fixed
179 static HARD_REG_SET bad_spill_regs;
181 /* These are the hard registers that can't be used as spill register for any
182 insn. This includes registers used for user variables and registers that
183 we can't eliminate. A register that appears in this set also can't be used
184 to retry register allocation. */
185 static HARD_REG_SET bad_spill_regs_global;
187 /* Describes order of use of registers for reloading
188 of spilled pseudo-registers. `n_spills' is the number of
189 elements that are actually valid; new ones are added at the end.
191 Both spill_regs and spill_reg_order are used on two occasions:
192 once during find_reload_regs, where they keep track of the spill registers
193 for a single insn, but also during reload_as_needed where they show all
194 the registers ever used by reload. For the latter case, the information
195 is calculated during finish_spills. */
196 static short spill_regs[FIRST_PSEUDO_REGISTER];
198 /* This vector of reg sets indicates, for each pseudo, which hard registers
199 may not be used for retrying global allocation because the register was
200 formerly spilled from one of them. If we allowed reallocating a pseudo to
201 a register that it was already allocated to, reload might not
203 static HARD_REG_SET *pseudo_previous_regs;
205 /* This vector of reg sets indicates, for each pseudo, which hard
206 registers may not be used for retrying global allocation because they
207 are used as spill registers during one of the insns in which the
209 static HARD_REG_SET *pseudo_forbidden_regs;
211 /* All hard regs that have been used as spill registers for any insn are
212 marked in this set. */
213 static HARD_REG_SET used_spill_regs;
215 /* Index of last register assigned as a spill register. We allocate in
216 a round-robin fashion. */
217 static int last_spill_reg;
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset_head spilled_pseudos;
244 /* Used for communication between order_regs_for_reload and count_pseudo.
245 Used to avoid counting one pseudo twice. */
246 static regset_head pseudos_counted;
248 /* First uid used by insns created by reload in this function.
249 Used in find_equiv_reg. */
250 int reload_first_uid;
252 /* Flag set by local-alloc or global-alloc if anything is live in
253 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* Set to 1 while reload_as_needed is operating.
257 Required by some machines to handle any generated moves differently. */
258 int reload_in_progress = 0;
260 /* These arrays record the insn_code of insns that may be needed to
261 perform input and output reloads of special objects. They provide a
262 place to pass a scratch register. */
263 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
264 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
266 /* This obstack is used for allocation of rtl during register elimination.
267 The allocated storage can be freed once find_reloads has processed the
269 struct obstack reload_obstack;
271 /* Points to the beginning of the reload_obstack. All insn_chain structures
272 are allocated first. */
273 char *reload_startobj;
275 /* The point after all insn_chain structures. Used to quickly deallocate
276 memory allocated in copy_reloads during calculate_needs_all_insns. */
277 char *reload_firstobj;
279 /* This points before all local rtl generated by register elimination.
280 Used to quickly free all memory after processing one insn. */
281 static char *reload_insn_firstobj;
283 #define obstack_chunk_alloc xmalloc
284 #define obstack_chunk_free free
286 /* List of insn_chain instructions, one for every insn that reload needs to
288 struct insn_chain *reload_insn_chain;
291 extern tree current_function_decl;
293 extern union tree_node *current_function_decl;
296 /* List of all insns needing reloads. */
297 static struct insn_chain *insns_need_reload;
299 /* This structure is used to record information about register eliminations.
300 Each array entry describes one possible way of eliminating a register
301 in favor of another. If there is more than one way of eliminating a
302 particular register, the most preferred should be specified first. */
306 int from; /* Register number to be eliminated. */
307 int to; /* Register number used as replacement. */
308 int initial_offset; /* Initial difference between values. */
309 int can_eliminate; /* Non-zero if this elimination can be done. */
310 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
311 insns made by reload. */
312 int offset; /* Current offset between the two regs. */
313 int previous_offset; /* Offset at end of previous insn. */
314 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
315 rtx from_rtx; /* REG rtx for the register to be eliminated.
316 We cannot simply compare the number since
317 we might then spuriously replace a hard
318 register corresponding to a pseudo
319 assigned to the reg to be eliminated. */
320 rtx to_rtx; /* REG rtx for the replacement. */
323 static struct elim_table *reg_eliminate = 0;
325 /* This is an intermediate structure to initialize the table. It has
326 exactly the members provided by ELIMINABLE_REGS. */
327 static const struct elim_table_1
331 } reg_eliminate_1[] =
333 /* If a set of eliminable registers was specified, define the table from it.
334 Otherwise, default to the normal case of the frame pointer being
335 replaced by the stack pointer. */
337 #ifdef ELIMINABLE_REGS
340 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
343 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
345 /* Record the number of pending eliminations that have an offset not equal
346 to their initial offset. If non-zero, we use a new copy of each
347 replacement result in any insns encountered. */
348 int num_not_at_initial_offset;
350 /* Count the number of registers that we may be able to eliminate. */
351 static int num_eliminable;
352 /* And the number of registers that are equivalent to a constant that
353 can be eliminated to frame_pointer / arg_pointer + constant. */
354 static int num_eliminable_invariants;
356 /* For each label, we record the offset of each elimination. If we reach
357 a label by more than one path and an offset differs, we cannot do the
358 elimination. This information is indexed by the number of the label.
359 The first table is an array of flags that records whether we have yet
360 encountered a label and the second table is an array of arrays, one
361 entry in the latter array for each elimination. */
363 static char *offsets_known_at;
364 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
366 /* Number of labels in the current function. */
368 static int num_labels;
370 static void replace_pseudos_in_call_usage PARAMS ((rtx *,
373 static void maybe_fix_stack_asms PARAMS ((void));
374 static void copy_reloads PARAMS ((struct insn_chain *));
375 static void calculate_needs_all_insns PARAMS ((int));
376 static int find_reg PARAMS ((struct insn_chain *, int));
377 static void find_reload_regs PARAMS ((struct insn_chain *));
378 static void select_reload_regs PARAMS ((void));
379 static void delete_caller_save_insns PARAMS ((void));
381 static void spill_failure PARAMS ((rtx, enum reg_class));
382 static void count_spilled_pseudo PARAMS ((int, int, int));
383 static void delete_dead_insn PARAMS ((rtx));
384 static void alter_reg PARAMS ((int, int));
385 static void set_label_offsets PARAMS ((rtx, rtx, int));
386 static void check_eliminable_occurrences PARAMS ((rtx));
387 static void elimination_effects PARAMS ((rtx, enum machine_mode));
388 static int eliminate_regs_in_insn PARAMS ((rtx, int));
389 static void update_eliminable_offsets PARAMS ((void));
390 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
391 static void set_initial_elim_offsets PARAMS ((void));
392 static void verify_initial_elim_offsets PARAMS ((void));
393 static void set_initial_label_offsets PARAMS ((void));
394 static void set_offsets_for_label PARAMS ((rtx));
395 static void init_elim_table PARAMS ((void));
396 static void update_eliminables PARAMS ((HARD_REG_SET *));
397 static void spill_hard_reg PARAMS ((unsigned int, int));
398 static int finish_spills PARAMS ((int));
399 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
400 static void scan_paradoxical_subregs PARAMS ((rtx));
401 static void count_pseudo PARAMS ((int));
402 static void order_regs_for_reload PARAMS ((struct insn_chain *));
403 static void reload_as_needed PARAMS ((int));
404 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
405 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
406 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
409 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
412 static int reload_reg_free_p PARAMS ((unsigned int, int,
414 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
416 rtx, rtx, int, int));
417 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
418 enum reload_type, rtx, rtx,
420 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
422 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
424 static int conflicts_with_override PARAMS ((rtx));
425 static void failed_reload PARAMS ((rtx, int));
426 static int set_reload_reg PARAMS ((int, int));
427 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
428 static void choose_reload_regs PARAMS ((struct insn_chain *));
429 static void merge_assigned_reloads PARAMS ((rtx));
430 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
431 struct reload *, rtx, int));
432 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
433 struct reload *, int));
434 static void do_input_reload PARAMS ((struct insn_chain *,
435 struct reload *, int));
436 static void do_output_reload PARAMS ((struct insn_chain *,
437 struct reload *, int));
438 static void emit_reload_insns PARAMS ((struct insn_chain *));
439 static void delete_output_reload PARAMS ((rtx, int, int));
440 static void delete_address_reloads PARAMS ((rtx, rtx));
441 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
442 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
443 static void reload_cse_regs_1 PARAMS ((rtx));
444 static int reload_cse_noop_set_p PARAMS ((rtx));
445 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
446 static int reload_cse_simplify_operands PARAMS ((rtx, rtx));
447 static void reload_combine PARAMS ((void));
448 static void reload_combine_note_use PARAMS ((rtx *, rtx));
449 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
450 static void reload_cse_move2add PARAMS ((rtx));
451 static void move2add_note_store PARAMS ((rtx, rtx, void *));
453 static void add_auto_inc_notes PARAMS ((rtx, rtx));
455 static void copy_eh_notes PARAMS ((rtx, rtx));
456 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
458 static void failed_reload PARAMS ((rtx, int));
459 static int set_reload_reg PARAMS ((int, int));
460 static void reload_cse_simplify PARAMS ((rtx, rtx));
461 void fixup_abnormal_edges PARAMS ((void));
462 extern void dump_needs PARAMS ((struct insn_chain *));
464 /* Initialize the reload pass once per compilation. */
471 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
472 Set spill_indirect_levels to the number of levels such addressing is
473 permitted, zero if it is not permitted at all. */
476 = gen_rtx_MEM (Pmode,
479 LAST_VIRTUAL_REGISTER + 1),
481 spill_indirect_levels = 0;
483 while (memory_address_p (QImode, tem))
485 spill_indirect_levels++;
486 tem = gen_rtx_MEM (Pmode, tem);
489 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
491 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
492 indirect_symref_ok = memory_address_p (QImode, tem);
494 /* See if reg+reg is a valid (and offsettable) address. */
496 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
498 tem = gen_rtx_PLUS (Pmode,
499 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
500 gen_rtx_REG (Pmode, i));
502 /* This way, we make sure that reg+reg is an offsettable address. */
503 tem = plus_constant (tem, 4);
505 if (memory_address_p (QImode, tem))
507 double_reg_address_ok = 1;
512 /* Initialize obstack for our rtl allocation. */
513 gcc_obstack_init (&reload_obstack);
514 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
516 INIT_REG_SET (&spilled_pseudos);
517 INIT_REG_SET (&pseudos_counted);
520 /* List of insn chains that are currently unused. */
521 static struct insn_chain *unused_insn_chains = 0;
523 /* Allocate an empty insn_chain structure. */
527 struct insn_chain *c;
529 if (unused_insn_chains == 0)
531 c = (struct insn_chain *)
532 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
533 INIT_REG_SET (&c->live_throughout);
534 INIT_REG_SET (&c->dead_or_set);
538 c = unused_insn_chains;
539 unused_insn_chains = c->next;
541 c->is_caller_save_insn = 0;
542 c->need_operand_change = 0;
548 /* Small utility function to set all regs in hard reg set TO which are
549 allocated to pseudos in regset FROM. */
552 compute_use_by_pseudos (to, from)
558 EXECUTE_IF_SET_IN_REG_SET
559 (from, FIRST_PSEUDO_REGISTER, regno,
561 int r = reg_renumber[regno];
566 /* reload_combine uses the information from
567 BASIC_BLOCK->global_live_at_start, which might still
568 contain registers that have not actually been allocated
569 since they have an equivalence. */
570 if (! reload_completed)
575 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
577 SET_HARD_REG_BIT (*to, r + nregs);
582 /* Replace all pseudos found in LOC with their corresponding
586 replace_pseudos_in_call_usage (loc, mem_mode, usage)
588 enum machine_mode mem_mode;
602 unsigned int regno = REGNO (x);
604 if (regno < FIRST_PSEUDO_REGISTER)
607 x = eliminate_regs (x, mem_mode, usage);
611 replace_pseudos_in_call_usage (loc, mem_mode, usage);
615 if (reg_equiv_constant[regno])
616 *loc = reg_equiv_constant[regno];
617 else if (reg_equiv_mem[regno])
618 *loc = reg_equiv_mem[regno];
619 else if (reg_equiv_address[regno])
620 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
621 else if (GET_CODE (regno_reg_rtx[regno]) != REG
622 || REGNO (regno_reg_rtx[regno]) != regno)
623 *loc = regno_reg_rtx[regno];
629 else if (code == MEM)
631 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
635 /* Process each of our operands recursively. */
636 fmt = GET_RTX_FORMAT (code);
637 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
639 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
640 else if (*fmt == 'E')
641 for (j = 0; j < XVECLEN (x, i); j++)
642 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
646 /* Global variables used by reload and its subroutines. */
648 /* Set during calculate_needs if an insn needs register elimination. */
649 static int something_needs_elimination;
650 /* Set during calculate_needs if an insn needs an operand changed. */
651 int something_needs_operands_changed;
653 /* Nonzero means we couldn't get enough spill regs. */
656 /* Main entry point for the reload pass.
658 FIRST is the first insn of the function being compiled.
660 GLOBAL nonzero means we were called from global_alloc
661 and should attempt to reallocate any pseudoregs that we
662 displace from hard regs we will use for reloads.
663 If GLOBAL is zero, we do not have enough information to do that,
664 so any pseudo reg that is spilled must go to the stack.
666 Return value is nonzero if reload failed
667 and we must not do any more for this function. */
670 reload (first, global)
676 struct elim_table *ep;
679 /* The two pointers used to track the true location of the memory used
680 for label offsets. */
681 char *real_known_ptr = NULL;
682 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
684 /* Make sure even insns with volatile mem refs are recognizable. */
689 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
691 /* Make sure that the last insn in the chain
692 is not something that needs reloading. */
693 emit_note (NULL, NOTE_INSN_DELETED);
695 /* Enable find_equiv_reg to distinguish insns made by reload. */
696 reload_first_uid = get_max_uid ();
698 #ifdef SECONDARY_MEMORY_NEEDED
699 /* Initialize the secondary memory table. */
700 clear_secondary_mem ();
703 /* We don't have a stack slot for any spill reg yet. */
704 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
705 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
707 /* Initialize the save area information for caller-save, in case some
711 /* Compute which hard registers are now in use
712 as homes for pseudo registers.
713 This is done here rather than (eg) in global_alloc
714 because this point is reached even if not optimizing. */
715 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
718 /* A function that receives a nonlocal goto must save all call-saved
720 if (current_function_has_nonlocal_label)
721 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
722 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
723 regs_ever_live[i] = 1;
725 /* Find all the pseudo registers that didn't get hard regs
726 but do have known equivalent constants or memory slots.
727 These include parameters (known equivalent to parameter slots)
728 and cse'd or loop-moved constant memory addresses.
730 Record constant equivalents in reg_equiv_constant
731 so they will be substituted by find_reloads.
732 Record memory equivalents in reg_mem_equiv so they can
733 be substituted eventually by altering the REG-rtx's. */
735 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
740 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
741 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
742 pseudo_forbidden_regs
743 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
745 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
747 CLEAR_HARD_REG_SET (bad_spill_regs_global);
749 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
750 Also find all paradoxical subregs and find largest such for each pseudo.
751 On machines with small register classes, record hard registers that
752 are used for user variables. These can never be used for spills.
753 Also look for a "constant" REG_SETJMP. This means that all
754 caller-saved registers must be marked live. */
756 num_eliminable_invariants = 0;
757 for (insn = first; insn; insn = NEXT_INSN (insn))
759 rtx set = single_set (insn);
761 /* We may introduce USEs that we want to remove at the end, so
762 we'll mark them with QImode. Make sure there are no
763 previously-marked insns left by say regmove. */
764 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
765 && GET_MODE (insn) != VOIDmode)
766 PUT_MODE (insn, VOIDmode);
768 if (GET_CODE (insn) == CALL_INSN
769 && find_reg_note (insn, REG_SETJMP, NULL))
770 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
771 if (! call_used_regs[i])
772 regs_ever_live[i] = 1;
774 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
776 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
778 #ifdef LEGITIMATE_PIC_OPERAND_P
779 && (! function_invariant_p (XEXP (note, 0))
781 /* A function invariant is often CONSTANT_P but may
782 include a register. We promise to only pass
783 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
784 || (CONSTANT_P (XEXP (note, 0))
785 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
789 rtx x = XEXP (note, 0);
790 i = REGNO (SET_DEST (set));
791 if (i > LAST_VIRTUAL_REGISTER)
793 /* It can happen that a REG_EQUIV note contains a MEM
794 that is not a legitimate memory operand. As later
795 stages of reload assume that all addresses found
796 in the reg_equiv_* arrays were originally legitimate,
797 we ignore such REG_EQUIV notes. */
798 if (memory_operand (x, VOIDmode))
800 /* Always unshare the equivalence, so we can
801 substitute into this insn without touching the
803 reg_equiv_memory_loc[i] = copy_rtx (x);
805 else if (function_invariant_p (x))
807 if (GET_CODE (x) == PLUS)
809 /* This is PLUS of frame pointer and a constant,
810 and might be shared. Unshare it. */
811 reg_equiv_constant[i] = copy_rtx (x);
812 num_eliminable_invariants++;
814 else if (x == frame_pointer_rtx
815 || x == arg_pointer_rtx)
817 reg_equiv_constant[i] = x;
818 num_eliminable_invariants++;
820 else if (LEGITIMATE_CONSTANT_P (x))
821 reg_equiv_constant[i] = x;
823 reg_equiv_memory_loc[i]
824 = force_const_mem (GET_MODE (SET_DEST (set)), x);
829 /* If this register is being made equivalent to a MEM
830 and the MEM is not SET_SRC, the equivalencing insn
831 is one with the MEM as a SET_DEST and it occurs later.
832 So don't mark this insn now. */
833 if (GET_CODE (x) != MEM
834 || rtx_equal_p (SET_SRC (set), x))
836 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
841 /* If this insn is setting a MEM from a register equivalent to it,
842 this is the equivalencing insn. */
843 else if (set && GET_CODE (SET_DEST (set)) == MEM
844 && GET_CODE (SET_SRC (set)) == REG
845 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
846 && rtx_equal_p (SET_DEST (set),
847 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
848 reg_equiv_init[REGNO (SET_SRC (set))]
849 = gen_rtx_INSN_LIST (VOIDmode, insn,
850 reg_equiv_init[REGNO (SET_SRC (set))]);
853 scan_paradoxical_subregs (PATTERN (insn));
858 num_labels = max_label_num () - get_first_label_num ();
860 /* Allocate the tables used to store offset information at labels. */
861 /* We used to use alloca here, but the size of what it would try to
862 allocate would occasionally cause it to exceed the stack limit and
863 cause a core dump. */
864 real_known_ptr = xmalloc (num_labels);
866 = (int (*)[NUM_ELIMINABLE_REGS])
867 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
869 offsets_known_at = real_known_ptr - get_first_label_num ();
871 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
873 /* Alter each pseudo-reg rtx to contain its hard reg number.
874 Assign stack slots to the pseudos that lack hard regs or equivalents.
875 Do not touch virtual registers. */
877 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
880 /* If we have some registers we think can be eliminated, scan all insns to
881 see if there is an insn that sets one of these registers to something
882 other than itself plus a constant. If so, the register cannot be
883 eliminated. Doing this scan here eliminates an extra pass through the
884 main reload loop in the most common case where register elimination
886 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
887 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
888 || GET_CODE (insn) == CALL_INSN)
889 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
891 maybe_fix_stack_asms ();
893 insns_need_reload = 0;
894 something_needs_elimination = 0;
896 /* Initialize to -1, which means take the first spill register. */
899 /* Spill any hard regs that we know we can't eliminate. */
900 CLEAR_HARD_REG_SET (used_spill_regs);
901 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
902 if (! ep->can_eliminate)
903 spill_hard_reg (ep->from, 1);
905 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
906 if (frame_pointer_needed)
907 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
909 finish_spills (global);
911 /* From now on, we may need to generate moves differently. We may also
912 allow modifications of insns which cause them to not be recognized.
913 Any such modifications will be cleaned up during reload itself. */
914 reload_in_progress = 1;
916 /* This loop scans the entire function each go-round
917 and repeats until one repetition spills no additional hard regs. */
920 int something_changed;
923 HOST_WIDE_INT starting_frame_size;
925 /* Round size of stack frame to stack_alignment_needed. This must be done
926 here because the stack size may be a part of the offset computation
927 for register elimination, and there might have been new stack slots
928 created in the last iteration of this loop. */
929 if (cfun->stack_alignment_needed)
930 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
932 starting_frame_size = get_frame_size ();
934 set_initial_elim_offsets ();
935 set_initial_label_offsets ();
937 /* For each pseudo register that has an equivalent location defined,
938 try to eliminate any eliminable registers (such as the frame pointer)
939 assuming initial offsets for the replacement register, which
942 If the resulting location is directly addressable, substitute
943 the MEM we just got directly for the old REG.
945 If it is not addressable but is a constant or the sum of a hard reg
946 and constant, it is probably not addressable because the constant is
947 out of range, in that case record the address; we will generate
948 hairy code to compute the address in a register each time it is
949 needed. Similarly if it is a hard register, but one that is not
950 valid as an address register.
952 If the location is not addressable, but does not have one of the
953 above forms, assign a stack slot. We have to do this to avoid the
954 potential of producing lots of reloads if, e.g., a location involves
955 a pseudo that didn't get a hard register and has an equivalent memory
956 location that also involves a pseudo that didn't get a hard register.
958 Perhaps at some point we will improve reload_when_needed handling
959 so this problem goes away. But that's very hairy. */
961 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
962 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
964 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
966 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
968 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
969 else if (CONSTANT_P (XEXP (x, 0))
970 || (GET_CODE (XEXP (x, 0)) == REG
971 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
972 || (GET_CODE (XEXP (x, 0)) == PLUS
973 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
974 && (REGNO (XEXP (XEXP (x, 0), 0))
975 < FIRST_PSEUDO_REGISTER)
976 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
977 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
980 /* Make a new stack slot. Then indicate that something
981 changed so we go back and recompute offsets for
982 eliminable registers because the allocation of memory
983 below might change some offset. reg_equiv_{mem,address}
984 will be set up for this pseudo on the next pass around
986 reg_equiv_memory_loc[i] = 0;
987 reg_equiv_init[i] = 0;
992 if (caller_save_needed)
995 /* If we allocated another stack slot, redo elimination bookkeeping. */
996 if (starting_frame_size != get_frame_size ())
999 if (caller_save_needed)
1001 save_call_clobbered_regs ();
1002 /* That might have allocated new insn_chain structures. */
1003 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1006 calculate_needs_all_insns (global);
1008 CLEAR_REG_SET (&spilled_pseudos);
1011 something_changed = 0;
1013 /* If we allocated any new memory locations, make another pass
1014 since it might have changed elimination offsets. */
1015 if (starting_frame_size != get_frame_size ())
1016 something_changed = 1;
1019 HARD_REG_SET to_spill;
1020 CLEAR_HARD_REG_SET (to_spill);
1021 update_eliminables (&to_spill);
1022 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1023 if (TEST_HARD_REG_BIT (to_spill, i))
1025 spill_hard_reg (i, 1);
1028 /* Regardless of the state of spills, if we previously had
1029 a register that we thought we could eliminate, but no can
1030 not eliminate, we must run another pass.
1032 Consider pseudos which have an entry in reg_equiv_* which
1033 reference an eliminable register. We must make another pass
1034 to update reg_equiv_* so that we do not substitute in the
1035 old value from when we thought the elimination could be
1037 something_changed = 1;
1041 select_reload_regs ();
1045 if (insns_need_reload != 0 || did_spill)
1046 something_changed |= finish_spills (global);
1048 if (! something_changed)
1051 if (caller_save_needed)
1052 delete_caller_save_insns ();
1054 obstack_free (&reload_obstack, reload_firstobj);
1057 /* If global-alloc was run, notify it of any register eliminations we have
1060 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1061 if (ep->can_eliminate)
1062 mark_elimination (ep->from, ep->to);
1064 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1065 If that insn didn't set the register (i.e., it copied the register to
1066 memory), just delete that insn instead of the equivalencing insn plus
1067 anything now dead. If we call delete_dead_insn on that insn, we may
1068 delete the insn that actually sets the register if the register dies
1069 there and that is incorrect. */
1071 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1073 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1076 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1078 rtx equiv_insn = XEXP (list, 0);
1080 /* If we already deleted the insn or if it may trap, we can't
1081 delete it. The latter case shouldn't happen, but can
1082 if an insn has a variable address, gets a REG_EH_REGION
1083 note added to it, and then gets converted into an load
1084 from a constant address. */
1085 if (GET_CODE (equiv_insn) == NOTE
1086 || can_throw_internal (equiv_insn))
1088 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1089 delete_dead_insn (equiv_insn);
1092 PUT_CODE (equiv_insn, NOTE);
1093 NOTE_SOURCE_FILE (equiv_insn) = 0;
1094 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1100 /* Use the reload registers where necessary
1101 by generating move instructions to move the must-be-register
1102 values into or out of the reload registers. */
1104 if (insns_need_reload != 0 || something_needs_elimination
1105 || something_needs_operands_changed)
1107 HOST_WIDE_INT old_frame_size = get_frame_size ();
1109 reload_as_needed (global);
1111 if (old_frame_size != get_frame_size ())
1115 verify_initial_elim_offsets ();
1118 /* If we were able to eliminate the frame pointer, show that it is no
1119 longer live at the start of any basic block. If it ls live by
1120 virtue of being in a pseudo, that pseudo will be marked live
1121 and hence the frame pointer will be known to be live via that
1124 if (! frame_pointer_needed)
1126 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1127 HARD_FRAME_POINTER_REGNUM);
1129 /* Come here (with failure set nonzero) if we can't get enough spill regs
1130 and we decide not to abort about it. */
1133 CLEAR_REG_SET (&spilled_pseudos);
1134 reload_in_progress = 0;
1136 /* Now eliminate all pseudo regs by modifying them into
1137 their equivalent memory references.
1138 The REG-rtx's for the pseudos are modified in place,
1139 so all insns that used to refer to them now refer to memory.
1141 For a reg that has a reg_equiv_address, all those insns
1142 were changed by reloading so that no insns refer to it any longer;
1143 but the DECL_RTL of a variable decl may refer to it,
1144 and if so this causes the debugging info to mention the variable. */
1146 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1150 if (reg_equiv_mem[i])
1151 addr = XEXP (reg_equiv_mem[i], 0);
1153 if (reg_equiv_address[i])
1154 addr = reg_equiv_address[i];
1158 if (reg_renumber[i] < 0)
1160 rtx reg = regno_reg_rtx[i];
1162 REG_USERVAR_P (reg) = 0;
1163 PUT_CODE (reg, MEM);
1164 XEXP (reg, 0) = addr;
1165 if (reg_equiv_memory_loc[i])
1166 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1169 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1170 = MEM_SCALAR_P (reg) = 0;
1171 MEM_ATTRS (reg) = 0;
1174 else if (reg_equiv_mem[i])
1175 XEXP (reg_equiv_mem[i], 0) = addr;
1179 /* We must set reload_completed now since the cleanup_subreg_operands call
1180 below will re-recognize each insn and reload may have generated insns
1181 which are only valid during and after reload. */
1182 reload_completed = 1;
1184 /* Make a pass over all the insns and delete all USEs which we inserted
1185 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1186 notes. Delete all CLOBBER insns that don't refer to the return value
1187 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1188 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1189 and regenerate REG_INC notes that may have been moved around. */
1191 for (insn = first; insn; insn = NEXT_INSN (insn))
1196 if (GET_CODE (insn) == CALL_INSN)
1197 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1199 CALL_INSN_FUNCTION_USAGE (insn));
1201 if ((GET_CODE (PATTERN (insn)) == USE
1202 /* We mark with QImode USEs introduced by reload itself. */
1203 && (GET_MODE (insn) == QImode
1204 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1205 || (GET_CODE (PATTERN (insn)) == CLOBBER
1206 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1207 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1213 pnote = ®_NOTES (insn);
1216 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1217 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1218 || REG_NOTE_KIND (*pnote) == REG_INC
1219 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1220 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1221 *pnote = XEXP (*pnote, 1);
1223 pnote = &XEXP (*pnote, 1);
1227 add_auto_inc_notes (insn, PATTERN (insn));
1230 /* And simplify (subreg (reg)) if it appears as an operand. */
1231 cleanup_subreg_operands (insn);
1234 /* If we are doing stack checking, give a warning if this function's
1235 frame size is larger than we expect. */
1236 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1238 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1239 static int verbose_warned = 0;
1241 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1242 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1243 size += UNITS_PER_WORD;
1245 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1247 warning ("frame size too large for reliable stack checking");
1248 if (! verbose_warned)
1250 warning ("try reducing the number of local variables");
1256 /* Indicate that we no longer have known memory locations or constants. */
1257 if (reg_equiv_constant)
1258 free (reg_equiv_constant);
1259 reg_equiv_constant = 0;
1260 if (reg_equiv_memory_loc)
1261 free (reg_equiv_memory_loc);
1262 reg_equiv_memory_loc = 0;
1265 free (real_known_ptr);
1269 free (reg_equiv_mem);
1270 free (reg_equiv_init);
1271 free (reg_equiv_address);
1272 free (reg_max_ref_width);
1273 free (reg_old_renumber);
1274 free (pseudo_previous_regs);
1275 free (pseudo_forbidden_regs);
1277 CLEAR_HARD_REG_SET (used_spill_regs);
1278 for (i = 0; i < n_spills; i++)
1279 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1281 /* Free all the insn_chain structures at once. */
1282 obstack_free (&reload_obstack, reload_startobj);
1283 unused_insn_chains = 0;
1284 fixup_abnormal_edges ();
1286 /* Replacing pseudos with their memory equivalents might have
1287 created shared rtx. Subsequent passes would get confused
1288 by this, so unshare everything here. */
1289 unshare_all_rtl_again (first);
1294 /* Yet another special case. Unfortunately, reg-stack forces people to
1295 write incorrect clobbers in asm statements. These clobbers must not
1296 cause the register to appear in bad_spill_regs, otherwise we'll call
1297 fatal_insn later. We clear the corresponding regnos in the live
1298 register sets to avoid this.
1299 The whole thing is rather sick, I'm afraid. */
1302 maybe_fix_stack_asms ()
1305 const char *constraints[MAX_RECOG_OPERANDS];
1306 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1307 struct insn_chain *chain;
1309 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1312 HARD_REG_SET clobbered, allowed;
1315 if (! INSN_P (chain->insn)
1316 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1318 pat = PATTERN (chain->insn);
1319 if (GET_CODE (pat) != PARALLEL)
1322 CLEAR_HARD_REG_SET (clobbered);
1323 CLEAR_HARD_REG_SET (allowed);
1325 /* First, make a mask of all stack regs that are clobbered. */
1326 for (i = 0; i < XVECLEN (pat, 0); i++)
1328 rtx t = XVECEXP (pat, 0, i);
1329 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1330 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1333 /* Get the operand values and constraints out of the insn. */
1334 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1335 constraints, operand_mode);
1337 /* For every operand, see what registers are allowed. */
1338 for (i = 0; i < noperands; i++)
1340 const char *p = constraints[i];
1341 /* For every alternative, we compute the class of registers allowed
1342 for reloading in CLS, and merge its contents into the reg set
1344 int cls = (int) NO_REGS;
1350 if (c == '\0' || c == ',' || c == '#')
1352 /* End of one alternative - mark the regs in the current
1353 class, and reset the class. */
1354 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1359 } while (c != '\0' && c != ',');
1367 case '=': case '+': case '*': case '%': case '?': case '!':
1368 case '0': case '1': case '2': case '3': case '4': case 'm':
1369 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1370 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1371 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1376 cls = (int) reg_class_subunion[cls]
1377 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1382 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1386 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1391 /* Those of the registers which are clobbered, but allowed by the
1392 constraints, must be usable as reload registers. So clear them
1393 out of the life information. */
1394 AND_HARD_REG_SET (allowed, clobbered);
1395 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1396 if (TEST_HARD_REG_BIT (allowed, i))
1398 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1399 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1406 /* Copy the global variables n_reloads and rld into the corresponding elts
1409 copy_reloads (chain)
1410 struct insn_chain *chain;
1412 chain->n_reloads = n_reloads;
1414 = (struct reload *) obstack_alloc (&reload_obstack,
1415 n_reloads * sizeof (struct reload));
1416 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1417 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1420 /* Walk the chain of insns, and determine for each whether it needs reloads
1421 and/or eliminations. Build the corresponding insns_need_reload list, and
1422 set something_needs_elimination as appropriate. */
1424 calculate_needs_all_insns (global)
1427 struct insn_chain **pprev_reload = &insns_need_reload;
1428 struct insn_chain *chain, *next = 0;
1430 something_needs_elimination = 0;
1432 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1433 for (chain = reload_insn_chain; chain != 0; chain = next)
1435 rtx insn = chain->insn;
1439 /* Clear out the shortcuts. */
1440 chain->n_reloads = 0;
1441 chain->need_elim = 0;
1442 chain->need_reload = 0;
1443 chain->need_operand_change = 0;
1445 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1446 include REG_LABEL), we need to see what effects this has on the
1447 known offsets at labels. */
1449 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1450 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1451 set_label_offsets (insn, insn, 0);
1455 rtx old_body = PATTERN (insn);
1456 int old_code = INSN_CODE (insn);
1457 rtx old_notes = REG_NOTES (insn);
1458 int did_elimination = 0;
1459 int operands_changed = 0;
1460 rtx set = single_set (insn);
1462 /* Skip insns that only set an equivalence. */
1463 if (set && GET_CODE (SET_DEST (set)) == REG
1464 && reg_renumber[REGNO (SET_DEST (set))] < 0
1465 && reg_equiv_constant[REGNO (SET_DEST (set))])
1468 /* If needed, eliminate any eliminable registers. */
1469 if (num_eliminable || num_eliminable_invariants)
1470 did_elimination = eliminate_regs_in_insn (insn, 0);
1472 /* Analyze the instruction. */
1473 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1474 global, spill_reg_order);
1476 /* If a no-op set needs more than one reload, this is likely
1477 to be something that needs input address reloads. We
1478 can't get rid of this cleanly later, and it is of no use
1479 anyway, so discard it now.
1480 We only do this when expensive_optimizations is enabled,
1481 since this complements reload inheritance / output
1482 reload deletion, and it can make debugging harder. */
1483 if (flag_expensive_optimizations && n_reloads > 1)
1485 rtx set = single_set (insn);
1487 && SET_SRC (set) == SET_DEST (set)
1488 && GET_CODE (SET_SRC (set)) == REG
1489 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1492 /* Delete it from the reload chain */
1494 chain->prev->next = next;
1496 reload_insn_chain = next;
1498 next->prev = chain->prev;
1499 chain->next = unused_insn_chains;
1500 unused_insn_chains = chain;
1505 update_eliminable_offsets ();
1507 /* Remember for later shortcuts which insns had any reloads or
1508 register eliminations. */
1509 chain->need_elim = did_elimination;
1510 chain->need_reload = n_reloads > 0;
1511 chain->need_operand_change = operands_changed;
1513 /* Discard any register replacements done. */
1514 if (did_elimination)
1516 obstack_free (&reload_obstack, reload_insn_firstobj);
1517 PATTERN (insn) = old_body;
1518 INSN_CODE (insn) = old_code;
1519 REG_NOTES (insn) = old_notes;
1520 something_needs_elimination = 1;
1523 something_needs_operands_changed |= operands_changed;
1527 copy_reloads (chain);
1528 *pprev_reload = chain;
1529 pprev_reload = &chain->next_need_reload;
1536 /* Comparison function for qsort to decide which of two reloads
1537 should be handled first. *P1 and *P2 are the reload numbers. */
1540 reload_reg_class_lower (r1p, r2p)
1544 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1547 /* Consider required reloads before optional ones. */
1548 t = rld[r1].optional - rld[r2].optional;
1552 /* Count all solitary classes before non-solitary ones. */
1553 t = ((reg_class_size[(int) rld[r2].class] == 1)
1554 - (reg_class_size[(int) rld[r1].class] == 1));
1558 /* Aside from solitaires, consider all multi-reg groups first. */
1559 t = rld[r2].nregs - rld[r1].nregs;
1563 /* Consider reloads in order of increasing reg-class number. */
1564 t = (int) rld[r1].class - (int) rld[r2].class;
1568 /* If reloads are equally urgent, sort by reload number,
1569 so that the results of qsort leave nothing to chance. */
1573 /* The cost of spilling each hard reg. */
1574 static int spill_cost[FIRST_PSEUDO_REGISTER];
1576 /* When spilling multiple hard registers, we use SPILL_COST for the first
1577 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1578 only the first hard reg for a multi-reg pseudo. */
1579 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1581 /* Update the spill cost arrays, considering that pseudo REG is live. */
1587 int freq = REG_FREQ (reg);
1588 int r = reg_renumber[reg];
1591 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1592 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1595 SET_REGNO_REG_SET (&pseudos_counted, reg);
1600 spill_add_cost[r] += freq;
1602 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1604 spill_cost[r + nregs] += freq;
1607 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1608 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1611 order_regs_for_reload (chain)
1612 struct insn_chain *chain;
1615 HARD_REG_SET used_by_pseudos;
1616 HARD_REG_SET used_by_pseudos2;
1618 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1620 memset (spill_cost, 0, sizeof spill_cost);
1621 memset (spill_add_cost, 0, sizeof spill_add_cost);
1623 /* Count number of uses of each hard reg by pseudo regs allocated to it
1624 and then order them by decreasing use. First exclude hard registers
1625 that are live in or across this insn. */
1627 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1628 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1629 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1630 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1632 /* Now find out which pseudos are allocated to it, and update
1634 CLEAR_REG_SET (&pseudos_counted);
1636 EXECUTE_IF_SET_IN_REG_SET
1637 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1641 EXECUTE_IF_SET_IN_REG_SET
1642 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1646 CLEAR_REG_SET (&pseudos_counted);
1649 /* Vector of reload-numbers showing the order in which the reloads should
1651 static short reload_order[MAX_RELOADS];
1653 /* This is used to keep track of the spill regs used in one insn. */
1654 static HARD_REG_SET used_spill_regs_local;
1656 /* We decided to spill hard register SPILLED, which has a size of
1657 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1658 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1659 update SPILL_COST/SPILL_ADD_COST. */
1662 count_spilled_pseudo (spilled, spilled_nregs, reg)
1663 int spilled, spilled_nregs, reg;
1665 int r = reg_renumber[reg];
1666 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1668 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1669 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1672 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1674 spill_add_cost[r] -= REG_FREQ (reg);
1676 spill_cost[r + nregs] -= REG_FREQ (reg);
1679 /* Find reload register to use for reload number ORDER. */
1682 find_reg (chain, order)
1683 struct insn_chain *chain;
1686 int rnum = reload_order[order];
1687 struct reload *rl = rld + rnum;
1688 int best_cost = INT_MAX;
1692 HARD_REG_SET not_usable;
1693 HARD_REG_SET used_by_other_reload;
1695 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1696 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1697 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1699 CLEAR_HARD_REG_SET (used_by_other_reload);
1700 for (k = 0; k < order; k++)
1702 int other = reload_order[k];
1704 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1705 for (j = 0; j < rld[other].nregs; j++)
1706 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1709 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1711 unsigned int regno = i;
1713 if (! TEST_HARD_REG_BIT (not_usable, regno)
1714 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1715 && HARD_REGNO_MODE_OK (regno, rl->mode))
1717 int this_cost = spill_cost[regno];
1719 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1721 for (j = 1; j < this_nregs; j++)
1723 this_cost += spill_add_cost[regno + j];
1724 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1725 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1730 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1732 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1734 if (this_cost < best_cost
1735 /* Among registers with equal cost, prefer caller-saved ones, or
1736 use REG_ALLOC_ORDER if it is defined. */
1737 || (this_cost == best_cost
1738 #ifdef REG_ALLOC_ORDER
1739 && (inv_reg_alloc_order[regno]
1740 < inv_reg_alloc_order[best_reg])
1742 && call_used_regs[regno]
1743 && ! call_used_regs[best_reg]
1748 best_cost = this_cost;
1756 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1758 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1759 rl->regno = best_reg;
1761 EXECUTE_IF_SET_IN_REG_SET
1762 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1764 count_spilled_pseudo (best_reg, rl->nregs, j);
1767 EXECUTE_IF_SET_IN_REG_SET
1768 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1770 count_spilled_pseudo (best_reg, rl->nregs, j);
1773 for (i = 0; i < rl->nregs; i++)
1775 if (spill_cost[best_reg + i] != 0
1776 || spill_add_cost[best_reg + i] != 0)
1778 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1783 /* Find more reload regs to satisfy the remaining need of an insn, which
1785 Do it by ascending class number, since otherwise a reg
1786 might be spilled for a big class and might fail to count
1787 for a smaller class even though it belongs to that class. */
1790 find_reload_regs (chain)
1791 struct insn_chain *chain;
1795 /* In order to be certain of getting the registers we need,
1796 we must sort the reloads into order of increasing register class.
1797 Then our grabbing of reload registers will parallel the process
1798 that provided the reload registers. */
1799 for (i = 0; i < chain->n_reloads; i++)
1801 /* Show whether this reload already has a hard reg. */
1802 if (chain->rld[i].reg_rtx)
1804 int regno = REGNO (chain->rld[i].reg_rtx);
1805 chain->rld[i].regno = regno;
1807 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1810 chain->rld[i].regno = -1;
1811 reload_order[i] = i;
1814 n_reloads = chain->n_reloads;
1815 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1817 CLEAR_HARD_REG_SET (used_spill_regs_local);
1820 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1822 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1824 /* Compute the order of preference for hard registers to spill. */
1826 order_regs_for_reload (chain);
1828 for (i = 0; i < n_reloads; i++)
1830 int r = reload_order[i];
1832 /* Ignore reloads that got marked inoperative. */
1833 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1834 && ! rld[r].optional
1835 && rld[r].regno == -1)
1836 if (! find_reg (chain, i))
1838 spill_failure (chain->insn, rld[r].class);
1844 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1845 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1847 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1851 select_reload_regs ()
1853 struct insn_chain *chain;
1855 /* Try to satisfy the needs for each insn. */
1856 for (chain = insns_need_reload; chain != 0;
1857 chain = chain->next_need_reload)
1858 find_reload_regs (chain);
1861 /* Delete all insns that were inserted by emit_caller_save_insns during
1864 delete_caller_save_insns ()
1866 struct insn_chain *c = reload_insn_chain;
1870 while (c != 0 && c->is_caller_save_insn)
1872 struct insn_chain *next = c->next;
1875 if (c == reload_insn_chain)
1876 reload_insn_chain = next;
1880 next->prev = c->prev;
1882 c->prev->next = next;
1883 c->next = unused_insn_chains;
1884 unused_insn_chains = c;
1892 /* Handle the failure to find a register to spill.
1893 INSN should be one of the insns which needed this particular spill reg. */
1896 spill_failure (insn, class)
1898 enum reg_class class;
1900 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1901 if (asm_noperands (PATTERN (insn)) >= 0)
1902 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1903 reg_class_names[class]);
1906 error ("unable to find a register to spill in class `%s'",
1907 reg_class_names[class]);
1908 fatal_insn ("this is the insn:", insn);
1912 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1913 data that is dead in INSN. */
1916 delete_dead_insn (insn)
1919 rtx prev = prev_real_insn (insn);
1922 /* If the previous insn sets a register that dies in our insn, delete it
1924 if (prev && GET_CODE (PATTERN (prev)) == SET
1925 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1926 && reg_mentioned_p (prev_dest, PATTERN (insn))
1927 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1928 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1929 delete_dead_insn (prev);
1931 PUT_CODE (insn, NOTE);
1932 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1933 NOTE_SOURCE_FILE (insn) = 0;
1936 /* Modify the home of pseudo-reg I.
1937 The new home is present in reg_renumber[I].
1939 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1940 or it may be -1, meaning there is none or it is not relevant.
1941 This is used so that all pseudos spilled from a given hard reg
1942 can share one stack slot. */
1945 alter_reg (i, from_reg)
1949 /* When outputting an inline function, this can happen
1950 for a reg that isn't actually used. */
1951 if (regno_reg_rtx[i] == 0)
1954 /* If the reg got changed to a MEM at rtl-generation time,
1956 if (GET_CODE (regno_reg_rtx[i]) != REG)
1959 /* Modify the reg-rtx to contain the new hard reg
1960 number or else to contain its pseudo reg number. */
1961 REGNO (regno_reg_rtx[i])
1962 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1964 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1965 allocate a stack slot for it. */
1967 if (reg_renumber[i] < 0
1968 && REG_N_REFS (i) > 0
1969 && reg_equiv_constant[i] == 0
1970 && reg_equiv_memory_loc[i] == 0)
1973 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1974 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1977 /* Each pseudo reg has an inherent size which comes from its own mode,
1978 and a total size which provides room for paradoxical subregs
1979 which refer to the pseudo reg in wider modes.
1981 We can use a slot already allocated if it provides both
1982 enough inherent space and enough total space.
1983 Otherwise, we allocate a new slot, making sure that it has no less
1984 inherent space, and no less total space, then the previous slot. */
1987 /* No known place to spill from => no slot to reuse. */
1988 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1989 inherent_size == total_size ? 0 : -1);
1990 if (BYTES_BIG_ENDIAN)
1991 /* Cancel the big-endian correction done in assign_stack_local.
1992 Get the address of the beginning of the slot.
1993 This is so we can do a big-endian correction unconditionally
1995 adjust = inherent_size - total_size;
1997 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1999 /* Nothing can alias this slot except this pseudo. */
2000 set_mem_alias_set (x, new_alias_set ());
2003 /* Reuse a stack slot if possible. */
2004 else if (spill_stack_slot[from_reg] != 0
2005 && spill_stack_slot_width[from_reg] >= total_size
2006 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2008 x = spill_stack_slot[from_reg];
2010 /* Allocate a bigger slot. */
2013 /* Compute maximum size needed, both for inherent size
2014 and for total size. */
2015 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2018 if (spill_stack_slot[from_reg])
2020 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2022 mode = GET_MODE (spill_stack_slot[from_reg]);
2023 if (spill_stack_slot_width[from_reg] > total_size)
2024 total_size = spill_stack_slot_width[from_reg];
2027 /* Make a slot with that size. */
2028 x = assign_stack_local (mode, total_size,
2029 inherent_size == total_size ? 0 : -1);
2032 /* All pseudos mapped to this slot can alias each other. */
2033 if (spill_stack_slot[from_reg])
2034 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2036 set_mem_alias_set (x, new_alias_set ());
2038 if (BYTES_BIG_ENDIAN)
2040 /* Cancel the big-endian correction done in assign_stack_local.
2041 Get the address of the beginning of the slot.
2042 This is so we can do a big-endian correction unconditionally
2044 adjust = GET_MODE_SIZE (mode) - total_size;
2047 = adjust_address_nv (x, mode_for_size (total_size
2053 spill_stack_slot[from_reg] = stack_slot;
2054 spill_stack_slot_width[from_reg] = total_size;
2057 /* On a big endian machine, the "address" of the slot
2058 is the address of the low part that fits its inherent mode. */
2059 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2060 adjust += (total_size - inherent_size);
2062 /* If we have any adjustment to make, or if the stack slot is the
2063 wrong mode, make a new stack slot. */
2064 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2066 /* If we have a decl for the original register, set it for the
2067 memory. If this is a shared MEM, make a copy. */
2070 rtx decl = DECL_RTL_IF_SET (REGNO_DECL (i));
2072 /* We can do this only for the DECLs home pseudo, not for
2073 any copies of it, since otherwise when the stack slot
2074 is reused, nonoverlapping_memrefs_p might think they
2076 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2078 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2081 set_mem_expr (x, REGNO_DECL (i));
2085 /* Save the stack slot for later. */
2086 reg_equiv_memory_loc[i] = x;
2090 /* Mark the slots in regs_ever_live for the hard regs
2091 used by pseudo-reg number REGNO. */
2094 mark_home_live (regno)
2099 i = reg_renumber[regno];
2102 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2104 regs_ever_live[i++] = 1;
2107 /* This function handles the tracking of elimination offsets around branches.
2109 X is a piece of RTL being scanned.
2111 INSN is the insn that it came from, if any.
2113 INITIAL_P is non-zero if we are to set the offset to be the initial
2114 offset and zero if we are setting the offset of the label to be the
2118 set_label_offsets (x, insn, initial_p)
2123 enum rtx_code code = GET_CODE (x);
2126 struct elim_table *p;
2131 if (LABEL_REF_NONLOCAL_P (x))
2136 /* ... fall through ... */
2139 /* If we know nothing about this label, set the desired offsets. Note
2140 that this sets the offset at a label to be the offset before a label
2141 if we don't know anything about the label. This is not correct for
2142 the label after a BARRIER, but is the best guess we can make. If
2143 we guessed wrong, we will suppress an elimination that might have
2144 been possible had we been able to guess correctly. */
2146 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2148 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2149 offsets_at[CODE_LABEL_NUMBER (x)][i]
2150 = (initial_p ? reg_eliminate[i].initial_offset
2151 : reg_eliminate[i].offset);
2152 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2155 /* Otherwise, if this is the definition of a label and it is
2156 preceded by a BARRIER, set our offsets to the known offset of
2160 && (tem = prev_nonnote_insn (insn)) != 0
2161 && GET_CODE (tem) == BARRIER)
2162 set_offsets_for_label (insn);
2164 /* If neither of the above cases is true, compare each offset
2165 with those previously recorded and suppress any eliminations
2166 where the offsets disagree. */
2168 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2169 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2170 != (initial_p ? reg_eliminate[i].initial_offset
2171 : reg_eliminate[i].offset))
2172 reg_eliminate[i].can_eliminate = 0;
2177 set_label_offsets (PATTERN (insn), insn, initial_p);
2179 /* ... fall through ... */
2183 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2184 and hence must have all eliminations at their initial offsets. */
2185 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2186 if (REG_NOTE_KIND (tem) == REG_LABEL)
2187 set_label_offsets (XEXP (tem, 0), insn, 1);
2193 /* Each of the labels in the parallel or address vector must be
2194 at their initial offsets. We want the first field for PARALLEL
2195 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2197 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2198 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2203 /* We only care about setting PC. If the source is not RETURN,
2204 IF_THEN_ELSE, or a label, disable any eliminations not at
2205 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2206 isn't one of those possibilities. For branches to a label,
2207 call ourselves recursively.
2209 Note that this can disable elimination unnecessarily when we have
2210 a non-local goto since it will look like a non-constant jump to
2211 someplace in the current function. This isn't a significant
2212 problem since such jumps will normally be when all elimination
2213 pairs are back to their initial offsets. */
2215 if (SET_DEST (x) != pc_rtx)
2218 switch (GET_CODE (SET_SRC (x)))
2225 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2229 tem = XEXP (SET_SRC (x), 1);
2230 if (GET_CODE (tem) == LABEL_REF)
2231 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2232 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2235 tem = XEXP (SET_SRC (x), 2);
2236 if (GET_CODE (tem) == LABEL_REF)
2237 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2238 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2246 /* If we reach here, all eliminations must be at their initial
2247 offset because we are doing a jump to a variable address. */
2248 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2249 if (p->offset != p->initial_offset)
2250 p->can_eliminate = 0;
2258 /* Scan X and replace any eliminable registers (such as fp) with a
2259 replacement (such as sp), plus an offset.
2261 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2262 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2263 MEM, we are allowed to replace a sum of a register and the constant zero
2264 with the register, which we cannot do outside a MEM. In addition, we need
2265 to record the fact that a register is referenced outside a MEM.
2267 If INSN is an insn, it is the insn containing X. If we replace a REG
2268 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2269 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2270 the REG is being modified.
2272 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2273 That's used when we eliminate in expressions stored in notes.
2274 This means, do not set ref_outside_mem even if the reference
2277 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2278 replacements done assuming all offsets are at their initial values. If
2279 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2280 encounter, return the actual location so that find_reloads will do
2281 the proper thing. */
2284 eliminate_regs (x, mem_mode, insn)
2286 enum machine_mode mem_mode;
2289 enum rtx_code code = GET_CODE (x);
2290 struct elim_table *ep;
2297 if (! current_function_decl)
2317 /* This is only for the benefit of the debugging backends, which call
2318 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2319 removed after CSE. */
2320 new = eliminate_regs (XEXP (x, 0), 0, insn);
2321 if (GET_CODE (new) == MEM)
2322 return XEXP (new, 0);
2328 /* First handle the case where we encounter a bare register that
2329 is eliminable. Replace it with a PLUS. */
2330 if (regno < FIRST_PSEUDO_REGISTER)
2332 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2334 if (ep->from_rtx == x && ep->can_eliminate)
2335 return plus_constant (ep->to_rtx, ep->previous_offset);
2338 else if (reg_renumber && reg_renumber[regno] < 0
2339 && reg_equiv_constant && reg_equiv_constant[regno]
2340 && ! CONSTANT_P (reg_equiv_constant[regno]))
2341 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2345 /* You might think handling MINUS in a manner similar to PLUS is a
2346 good idea. It is not. It has been tried multiple times and every
2347 time the change has had to have been reverted.
2349 Other parts of reload know a PLUS is special (gen_reload for example)
2350 and require special code to handle code a reloaded PLUS operand.
2352 Also consider backends where the flags register is clobbered by a
2353 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2354 lea instruction comes to mind). If we try to reload a MINUS, we
2355 may kill the flags register that was holding a useful value.
2357 So, please before trying to handle MINUS, consider reload as a
2358 whole instead of this little section as well as the backend issues. */
2360 /* If this is the sum of an eliminable register and a constant, rework
2362 if (GET_CODE (XEXP (x, 0)) == REG
2363 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2364 && CONSTANT_P (XEXP (x, 1)))
2366 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2368 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2370 /* The only time we want to replace a PLUS with a REG (this
2371 occurs when the constant operand of the PLUS is the negative
2372 of the offset) is when we are inside a MEM. We won't want
2373 to do so at other times because that would change the
2374 structure of the insn in a way that reload can't handle.
2375 We special-case the commonest situation in
2376 eliminate_regs_in_insn, so just replace a PLUS with a
2377 PLUS here, unless inside a MEM. */
2378 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2379 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2382 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2383 plus_constant (XEXP (x, 1),
2384 ep->previous_offset));
2387 /* If the register is not eliminable, we are done since the other
2388 operand is a constant. */
2392 /* If this is part of an address, we want to bring any constant to the
2393 outermost PLUS. We will do this by doing register replacement in
2394 our operands and seeing if a constant shows up in one of them.
2396 Note that there is no risk of modifying the structure of the insn,
2397 since we only get called for its operands, thus we are either
2398 modifying the address inside a MEM, or something like an address
2399 operand of a load-address insn. */
2402 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2403 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2405 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2407 /* If one side is a PLUS and the other side is a pseudo that
2408 didn't get a hard register but has a reg_equiv_constant,
2409 we must replace the constant here since it may no longer
2410 be in the position of any operand. */
2411 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2412 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2413 && reg_renumber[REGNO (new1)] < 0
2414 && reg_equiv_constant != 0
2415 && reg_equiv_constant[REGNO (new1)] != 0)
2416 new1 = reg_equiv_constant[REGNO (new1)];
2417 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2418 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2419 && reg_renumber[REGNO (new0)] < 0
2420 && reg_equiv_constant[REGNO (new0)] != 0)
2421 new0 = reg_equiv_constant[REGNO (new0)];
2423 new = form_sum (new0, new1);
2425 /* As above, if we are not inside a MEM we do not want to
2426 turn a PLUS into something else. We might try to do so here
2427 for an addition of 0 if we aren't optimizing. */
2428 if (! mem_mode && GET_CODE (new) != PLUS)
2429 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2437 /* If this is the product of an eliminable register and a
2438 constant, apply the distribute law and move the constant out
2439 so that we have (plus (mult ..) ..). This is needed in order
2440 to keep load-address insns valid. This case is pathological.
2441 We ignore the possibility of overflow here. */
2442 if (GET_CODE (XEXP (x, 0)) == REG
2443 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2444 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2445 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2447 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2450 /* Refs inside notes don't count for this purpose. */
2451 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2452 || GET_CODE (insn) == INSN_LIST)))
2453 ep->ref_outside_mem = 1;
2456 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2457 ep->previous_offset * INTVAL (XEXP (x, 1)));
2460 /* ... fall through ... */
2464 /* See comments before PLUS about handling MINUS. */
2466 case DIV: case UDIV:
2467 case MOD: case UMOD:
2468 case AND: case IOR: case XOR:
2469 case ROTATERT: case ROTATE:
2470 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2472 case GE: case GT: case GEU: case GTU:
2473 case LE: case LT: case LEU: case LTU:
2475 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2477 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2479 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2480 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2485 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2488 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2489 if (new != XEXP (x, 0))
2491 /* If this is a REG_DEAD note, it is not valid anymore.
2492 Using the eliminated version could result in creating a
2493 REG_DEAD note for the stack or frame pointer. */
2494 if (GET_MODE (x) == REG_DEAD)
2496 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2499 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2503 /* ... fall through ... */
2506 /* Now do eliminations in the rest of the chain. If this was
2507 an EXPR_LIST, this might result in allocating more memory than is
2508 strictly needed, but it simplifies the code. */
2511 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2512 if (new != XEXP (x, 1))
2514 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2522 case STRICT_LOW_PART:
2524 case SIGN_EXTEND: case ZERO_EXTEND:
2525 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2526 case FLOAT: case FIX:
2527 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2531 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2532 if (new != XEXP (x, 0))
2533 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2537 /* Similar to above processing, but preserve SUBREG_BYTE.
2538 Convert (subreg (mem)) to (mem) if not paradoxical.
2539 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2540 pseudo didn't get a hard reg, we must replace this with the
2541 eliminated version of the memory location because push_reloads
2542 may do the replacement in certain circumstances. */
2543 if (GET_CODE (SUBREG_REG (x)) == REG
2544 && (GET_MODE_SIZE (GET_MODE (x))
2545 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2546 && reg_equiv_memory_loc != 0
2547 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2549 new = SUBREG_REG (x);
2552 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2554 if (new != SUBREG_REG (x))
2556 int x_size = GET_MODE_SIZE (GET_MODE (x));
2557 int new_size = GET_MODE_SIZE (GET_MODE (new));
2559 if (GET_CODE (new) == MEM
2560 && ((x_size < new_size
2561 #ifdef WORD_REGISTER_OPERATIONS
2562 /* On these machines, combine can create rtl of the form
2563 (set (subreg:m1 (reg:m2 R) 0) ...)
2564 where m1 < m2, and expects something interesting to
2565 happen to the entire word. Moreover, it will use the
2566 (reg:m2 R) later, expecting all bits to be preserved.
2567 So if the number of words is the same, preserve the
2568 subreg so that push_reloads can see it. */
2569 && ! ((x_size - 1) / UNITS_PER_WORD
2570 == (new_size -1 ) / UNITS_PER_WORD)
2573 || x_size == new_size)
2575 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2577 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2583 /* This is only for the benefit of the debugging backends, which call
2584 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2585 removed after CSE. */
2586 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2587 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2589 /* Our only special processing is to pass the mode of the MEM to our
2590 recursive call and copy the flags. While we are here, handle this
2591 case more efficiently. */
2593 replace_equiv_address_nv (x,
2594 eliminate_regs (XEXP (x, 0),
2595 GET_MODE (x), insn));
2598 /* Handle insn_list USE that a call to a pure function may generate. */
2599 new = eliminate_regs (XEXP (x, 0), 0, insn);
2600 if (new != XEXP (x, 0))
2601 return gen_rtx_USE (GET_MODE (x), new);
2613 /* Process each of our operands recursively. If any have changed, make a
2615 fmt = GET_RTX_FORMAT (code);
2616 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2620 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2621 if (new != XEXP (x, i) && ! copied)
2623 rtx new_x = rtx_alloc (code);
2625 (sizeof (*new_x) - sizeof (new_x->fld)
2626 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2632 else if (*fmt == 'E')
2635 for (j = 0; j < XVECLEN (x, i); j++)
2637 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2638 if (new != XVECEXP (x, i, j) && ! copied_vec)
2640 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2644 rtx new_x = rtx_alloc (code);
2646 (sizeof (*new_x) - sizeof (new_x->fld)
2647 + (sizeof (new_x->fld[0])
2648 * GET_RTX_LENGTH (code))));
2652 XVEC (x, i) = new_v;
2655 XVECEXP (x, i, j) = new;
2663 /* Scan rtx X for modifications of elimination target registers. Update
2664 the table of eliminables to reflect the changed state. MEM_MODE is
2665 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2668 elimination_effects (x, mem_mode)
2670 enum machine_mode mem_mode;
2673 enum rtx_code code = GET_CODE (x);
2674 struct elim_table *ep;
2701 /* First handle the case where we encounter a bare register that
2702 is eliminable. Replace it with a PLUS. */
2703 if (regno < FIRST_PSEUDO_REGISTER)
2705 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2707 if (ep->from_rtx == x && ep->can_eliminate)
2710 ep->ref_outside_mem = 1;
2715 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2716 && reg_equiv_constant[regno]
2717 && ! function_invariant_p (reg_equiv_constant[regno]))
2718 elimination_effects (reg_equiv_constant[regno], mem_mode);
2727 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2728 if (ep->to_rtx == XEXP (x, 0))
2730 int size = GET_MODE_SIZE (mem_mode);
2732 /* If more bytes than MEM_MODE are pushed, account for them. */
2733 #ifdef PUSH_ROUNDING
2734 if (ep->to_rtx == stack_pointer_rtx)
2735 size = PUSH_ROUNDING (size);
2737 if (code == PRE_DEC || code == POST_DEC)
2739 else if (code == PRE_INC || code == POST_INC)
2741 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2742 && GET_CODE (XEXP (x, 1)) == PLUS
2743 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2744 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2745 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2748 /* These two aren't unary operators. */
2749 if (code == POST_MODIFY || code == PRE_MODIFY)
2752 /* Fall through to generic unary operation case. */
2753 case STRICT_LOW_PART:
2755 case SIGN_EXTEND: case ZERO_EXTEND:
2756 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2757 case FLOAT: case FIX:
2758 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2762 elimination_effects (XEXP (x, 0), mem_mode);
2766 if (GET_CODE (SUBREG_REG (x)) == REG
2767 && (GET_MODE_SIZE (GET_MODE (x))
2768 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2769 && reg_equiv_memory_loc != 0
2770 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2773 elimination_effects (SUBREG_REG (x), mem_mode);
2777 /* If using a register that is the source of an eliminate we still
2778 think can be performed, note it cannot be performed since we don't
2779 know how this register is used. */
2780 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2781 if (ep->from_rtx == XEXP (x, 0))
2782 ep->can_eliminate = 0;
2784 elimination_effects (XEXP (x, 0), mem_mode);
2788 /* If clobbering a register that is the replacement register for an
2789 elimination we still think can be performed, note that it cannot
2790 be performed. Otherwise, we need not be concerned about it. */
2791 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2792 if (ep->to_rtx == XEXP (x, 0))
2793 ep->can_eliminate = 0;
2795 elimination_effects (XEXP (x, 0), mem_mode);
2799 /* Check for setting a register that we know about. */
2800 if (GET_CODE (SET_DEST (x)) == REG)
2802 /* See if this is setting the replacement register for an
2805 If DEST is the hard frame pointer, we do nothing because we
2806 assume that all assignments to the frame pointer are for
2807 non-local gotos and are being done at a time when they are valid
2808 and do not disturb anything else. Some machines want to
2809 eliminate a fake argument pointer (or even a fake frame pointer)
2810 with either the real frame or the stack pointer. Assignments to
2811 the hard frame pointer must not prevent this elimination. */
2813 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2815 if (ep->to_rtx == SET_DEST (x)
2816 && SET_DEST (x) != hard_frame_pointer_rtx)
2818 /* If it is being incremented, adjust the offset. Otherwise,
2819 this elimination can't be done. */
2820 rtx src = SET_SRC (x);
2822 if (GET_CODE (src) == PLUS
2823 && XEXP (src, 0) == SET_DEST (x)
2824 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2825 ep->offset -= INTVAL (XEXP (src, 1));
2827 ep->can_eliminate = 0;
2831 elimination_effects (SET_DEST (x), 0);
2832 elimination_effects (SET_SRC (x), 0);
2836 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2839 /* Our only special processing is to pass the mode of the MEM to our
2841 elimination_effects (XEXP (x, 0), GET_MODE (x));
2848 fmt = GET_RTX_FORMAT (code);
2849 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2852 elimination_effects (XEXP (x, i), mem_mode);
2853 else if (*fmt == 'E')
2854 for (j = 0; j < XVECLEN (x, i); j++)
2855 elimination_effects (XVECEXP (x, i, j), mem_mode);
2859 /* Descend through rtx X and verify that no references to eliminable registers
2860 remain. If any do remain, mark the involved register as not
2864 check_eliminable_occurrences (x)
2874 code = GET_CODE (x);
2876 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2878 struct elim_table *ep;
2880 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2881 if (ep->from_rtx == x && ep->can_eliminate)
2882 ep->can_eliminate = 0;
2886 fmt = GET_RTX_FORMAT (code);
2887 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2890 check_eliminable_occurrences (XEXP (x, i));
2891 else if (*fmt == 'E')
2894 for (j = 0; j < XVECLEN (x, i); j++)
2895 check_eliminable_occurrences (XVECEXP (x, i, j));
2900 /* Scan INSN and eliminate all eliminable registers in it.
2902 If REPLACE is nonzero, do the replacement destructively. Also
2903 delete the insn as dead it if it is setting an eliminable register.
2905 If REPLACE is zero, do all our allocations in reload_obstack.
2907 If no eliminations were done and this insn doesn't require any elimination
2908 processing (these are not identical conditions: it might be updating sp,
2909 but not referencing fp; this needs to be seen during reload_as_needed so
2910 that the offset between fp and sp can be taken into consideration), zero
2911 is returned. Otherwise, 1 is returned. */
2914 eliminate_regs_in_insn (insn, replace)
2918 int icode = recog_memoized (insn);
2919 rtx old_body = PATTERN (insn);
2920 int insn_is_asm = asm_noperands (old_body) >= 0;
2921 rtx old_set = single_set (insn);
2925 rtx substed_operand[MAX_RECOG_OPERANDS];
2926 rtx orig_operand[MAX_RECOG_OPERANDS];
2927 struct elim_table *ep;
2929 if (! insn_is_asm && icode < 0)
2931 if (GET_CODE (PATTERN (insn)) == USE
2932 || GET_CODE (PATTERN (insn)) == CLOBBER
2933 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2934 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2935 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2940 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2941 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2943 /* Check for setting an eliminable register. */
2944 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2945 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2947 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2948 /* If this is setting the frame pointer register to the
2949 hardware frame pointer register and this is an elimination
2950 that will be done (tested above), this insn is really
2951 adjusting the frame pointer downward to compensate for
2952 the adjustment done before a nonlocal goto. */
2953 if (ep->from == FRAME_POINTER_REGNUM
2954 && ep->to == HARD_FRAME_POINTER_REGNUM)
2956 rtx base = SET_SRC (old_set);
2957 rtx base_insn = insn;
2960 while (base != ep->to_rtx)
2962 rtx prev_insn, prev_set;
2964 if (GET_CODE (base) == PLUS
2965 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2967 offset += INTVAL (XEXP (base, 1));
2968 base = XEXP (base, 0);
2970 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2971 && (prev_set = single_set (prev_insn)) != 0
2972 && rtx_equal_p (SET_DEST (prev_set), base))
2974 base = SET_SRC (prev_set);
2975 base_insn = prev_insn;
2981 if (base == ep->to_rtx)
2984 = plus_constant (ep->to_rtx, offset - ep->offset);
2986 new_body = old_body;
2989 new_body = copy_insn (old_body);
2990 if (REG_NOTES (insn))
2991 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2993 PATTERN (insn) = new_body;
2994 old_set = single_set (insn);
2996 /* First see if this insn remains valid when we
2997 make the change. If not, keep the INSN_CODE
2998 the same and let reload fit it up. */
2999 validate_change (insn, &SET_SRC (old_set), src, 1);
3000 validate_change (insn, &SET_DEST (old_set),
3002 if (! apply_change_group ())
3004 SET_SRC (old_set) = src;
3005 SET_DEST (old_set) = ep->to_rtx;
3014 /* In this case this insn isn't serving a useful purpose. We
3015 will delete it in reload_as_needed once we know that this
3016 elimination is, in fact, being done.
3018 If REPLACE isn't set, we can't delete this insn, but needn't
3019 process it since it won't be used unless something changes. */
3022 delete_dead_insn (insn);
3030 /* We allow one special case which happens to work on all machines we
3031 currently support: a single set with the source being a PLUS of an
3032 eliminable register and a constant. */
3034 && GET_CODE (SET_DEST (old_set)) == REG
3035 && GET_CODE (SET_SRC (old_set)) == PLUS
3036 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3037 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3038 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3040 rtx reg = XEXP (SET_SRC (old_set), 0);
3041 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3043 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3044 if (ep->from_rtx == reg && ep->can_eliminate)
3046 offset += ep->offset;
3051 /* We assume here that if we need a PARALLEL with
3052 CLOBBERs for this assignment, we can do with the
3053 MATCH_SCRATCHes that add_clobbers allocates.
3054 There's not much we can do if that doesn't work. */
3055 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3059 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3062 rtvec vec = rtvec_alloc (num_clobbers + 1);
3064 vec->elem[0] = PATTERN (insn);
3065 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3066 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3068 if (INSN_CODE (insn) < 0)
3073 new_body = old_body;
3076 new_body = copy_insn (old_body);
3077 if (REG_NOTES (insn))
3078 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3080 PATTERN (insn) = new_body;
3081 old_set = single_set (insn);
3083 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3084 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3087 /* This can't have an effect on elimination offsets, so skip right
3093 /* Determine the effects of this insn on elimination offsets. */
3094 elimination_effects (old_body, 0);
3096 /* Eliminate all eliminable registers occurring in operands that
3097 can be handled by reload. */
3098 extract_insn (insn);
3100 for (i = 0; i < recog_data.n_operands; i++)
3102 orig_operand[i] = recog_data.operand[i];
3103 substed_operand[i] = recog_data.operand[i];
3105 /* For an asm statement, every operand is eliminable. */
3106 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3108 /* Check for setting a register that we know about. */
3109 if (recog_data.operand_type[i] != OP_IN
3110 && GET_CODE (orig_operand[i]) == REG)
3112 /* If we are assigning to a register that can be eliminated, it
3113 must be as part of a PARALLEL, since the code above handles
3114 single SETs. We must indicate that we can no longer
3115 eliminate this reg. */
3116 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3118 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3119 ep->can_eliminate = 0;
3122 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3123 replace ? insn : NULL_RTX);
3124 if (substed_operand[i] != orig_operand[i])
3125 val = any_changes = 1;
3126 /* Terminate the search in check_eliminable_occurrences at
3128 *recog_data.operand_loc[i] = 0;
3130 /* If an output operand changed from a REG to a MEM and INSN is an
3131 insn, write a CLOBBER insn. */
3132 if (recog_data.operand_type[i] != OP_IN
3133 && GET_CODE (orig_operand[i]) == REG
3134 && GET_CODE (substed_operand[i]) == MEM
3136 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3141 for (i = 0; i < recog_data.n_dups; i++)
3142 *recog_data.dup_loc[i]
3143 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3145 /* If any eliminable remain, they aren't eliminable anymore. */
3146 check_eliminable_occurrences (old_body);
3148 /* Substitute the operands; the new values are in the substed_operand
3150 for (i = 0; i < recog_data.n_operands; i++)
3151 *recog_data.operand_loc[i] = substed_operand[i];
3152 for (i = 0; i < recog_data.n_dups; i++)
3153 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3155 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3156 re-recognize the insn. We do this in case we had a simple addition
3157 but now can do this as a load-address. This saves an insn in this
3159 If re-recognition fails, the old insn code number will still be used,
3160 and some register operands may have changed into PLUS expressions.
3161 These will be handled by find_reloads by loading them into a register
3166 /* If we aren't replacing things permanently and we changed something,
3167 make another copy to ensure that all the RTL is new. Otherwise
3168 things can go wrong if find_reload swaps commutative operands
3169 and one is inside RTL that has been copied while the other is not. */
3170 new_body = old_body;
3173 new_body = copy_insn (old_body);
3174 if (REG_NOTES (insn))
3175 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3177 PATTERN (insn) = new_body;
3179 /* If we had a move insn but now we don't, rerecognize it. This will
3180 cause spurious re-recognition if the old move had a PARALLEL since
3181 the new one still will, but we can't call single_set without
3182 having put NEW_BODY into the insn and the re-recognition won't
3183 hurt in this rare case. */
3184 /* ??? Why this huge if statement - why don't we just rerecognize the
3188 && ((GET_CODE (SET_SRC (old_set)) == REG
3189 && (GET_CODE (new_body) != SET
3190 || GET_CODE (SET_SRC (new_body)) != REG))
3191 /* If this was a load from or store to memory, compare
3192 the MEM in recog_data.operand to the one in the insn.
3193 If they are not equal, then rerecognize the insn. */
3195 && ((GET_CODE (SET_SRC (old_set)) == MEM
3196 && SET_SRC (old_set) != recog_data.operand[1])
3197 || (GET_CODE (SET_DEST (old_set)) == MEM
3198 && SET_DEST (old_set) != recog_data.operand[0])))
3199 /* If this was an add insn before, rerecognize. */
3200 || GET_CODE (SET_SRC (old_set)) == PLUS))
3202 int new_icode = recog (PATTERN (insn), insn, 0);
3204 INSN_CODE (insn) = icode;
3208 /* Restore the old body. If there were any changes to it, we made a copy
3209 of it while the changes were still in place, so we'll correctly return
3210 a modified insn below. */
3213 /* Restore the old body. */
3214 for (i = 0; i < recog_data.n_operands; i++)
3215 *recog_data.operand_loc[i] = orig_operand[i];
3216 for (i = 0; i < recog_data.n_dups; i++)
3217 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3220 /* Update all elimination pairs to reflect the status after the current
3221 insn. The changes we make were determined by the earlier call to
3222 elimination_effects.
3224 We also detect a cases where register elimination cannot be done,
3225 namely, if a register would be both changed and referenced outside a MEM
3226 in the resulting insn since such an insn is often undefined and, even if
3227 not, we cannot know what meaning will be given to it. Note that it is
3228 valid to have a register used in an address in an insn that changes it
3229 (presumably with a pre- or post-increment or decrement).
3231 If anything changes, return nonzero. */
3233 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3235 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3236 ep->can_eliminate = 0;
3238 ep->ref_outside_mem = 0;
3240 if (ep->previous_offset != ep->offset)
3245 /* If we changed something, perform elimination in REG_NOTES. This is
3246 needed even when REPLACE is zero because a REG_DEAD note might refer
3247 to a register that we eliminate and could cause a different number
3248 of spill registers to be needed in the final reload pass than in
3250 if (val && REG_NOTES (insn) != 0)
3251 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3256 /* Loop through all elimination pairs.
3257 Recalculate the number not at initial offset.
3259 Compute the maximum offset (minimum offset if the stack does not
3260 grow downward) for each elimination pair. */
3263 update_eliminable_offsets ()
3265 struct elim_table *ep;
3267 num_not_at_initial_offset = 0;
3268 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3270 ep->previous_offset = ep->offset;
3271 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3272 num_not_at_initial_offset++;
3276 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3277 replacement we currently believe is valid, mark it as not eliminable if X
3278 modifies DEST in any way other than by adding a constant integer to it.
3280 If DEST is the frame pointer, we do nothing because we assume that
3281 all assignments to the hard frame pointer are nonlocal gotos and are being
3282 done at a time when they are valid and do not disturb anything else.
3283 Some machines want to eliminate a fake argument pointer with either the
3284 frame or stack pointer. Assignments to the hard frame pointer must not
3285 prevent this elimination.
3287 Called via note_stores from reload before starting its passes to scan
3288 the insns of the function. */
3291 mark_not_eliminable (dest, x, data)
3294 void *data ATTRIBUTE_UNUSED;
3298 /* A SUBREG of a hard register here is just changing its mode. We should
3299 not see a SUBREG of an eliminable hard register, but check just in
3301 if (GET_CODE (dest) == SUBREG)
3302 dest = SUBREG_REG (dest);
3304 if (dest == hard_frame_pointer_rtx)
3307 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3308 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3309 && (GET_CODE (x) != SET
3310 || GET_CODE (SET_SRC (x)) != PLUS
3311 || XEXP (SET_SRC (x), 0) != dest
3312 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3314 reg_eliminate[i].can_eliminate_previous
3315 = reg_eliminate[i].can_eliminate = 0;
3320 /* Verify that the initial elimination offsets did not change since the
3321 last call to set_initial_elim_offsets. This is used to catch cases
3322 where something illegal happened during reload_as_needed that could
3323 cause incorrect code to be generated if we did not check for it. */
3326 verify_initial_elim_offsets ()
3330 #ifdef ELIMINABLE_REGS
3331 struct elim_table *ep;
3333 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3335 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3336 if (t != ep->initial_offset)
3340 INITIAL_FRAME_POINTER_OFFSET (t);
3341 if (t != reg_eliminate[0].initial_offset)
3346 /* Reset all offsets on eliminable registers to their initial values. */
3349 set_initial_elim_offsets ()
3351 struct elim_table *ep = reg_eliminate;
3353 #ifdef ELIMINABLE_REGS
3354 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3356 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3357 ep->previous_offset = ep->offset = ep->initial_offset;
3360 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3361 ep->previous_offset = ep->offset = ep->initial_offset;
3364 num_not_at_initial_offset = 0;
3367 /* Initialize the known label offsets.
3368 Set a known offset for each forced label to be at the initial offset
3369 of each elimination. We do this because we assume that all
3370 computed jumps occur from a location where each elimination is
3371 at its initial offset.
3372 For all other labels, show that we don't know the offsets. */
3375 set_initial_label_offsets ()
3378 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3380 for (x = forced_labels; x; x = XEXP (x, 1))
3382 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3385 /* Set all elimination offsets to the known values for the code label given
3389 set_offsets_for_label (insn)
3393 int label_nr = CODE_LABEL_NUMBER (insn);
3394 struct elim_table *ep;
3396 num_not_at_initial_offset = 0;
3397 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3399 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3400 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3401 num_not_at_initial_offset++;
3405 /* See if anything that happened changes which eliminations are valid.
3406 For example, on the Sparc, whether or not the frame pointer can
3407 be eliminated can depend on what registers have been used. We need
3408 not check some conditions again (such as flag_omit_frame_pointer)
3409 since they can't have changed. */
3412 update_eliminables (pset)
3415 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3416 int previous_frame_pointer_needed = frame_pointer_needed;
3418 struct elim_table *ep;
3420 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3421 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3422 #ifdef ELIMINABLE_REGS
3423 || ! CAN_ELIMINATE (ep->from, ep->to)
3426 ep->can_eliminate = 0;
3428 /* Look for the case where we have discovered that we can't replace
3429 register A with register B and that means that we will now be
3430 trying to replace register A with register C. This means we can
3431 no longer replace register C with register B and we need to disable
3432 such an elimination, if it exists. This occurs often with A == ap,
3433 B == sp, and C == fp. */
3435 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3437 struct elim_table *op;
3440 if (! ep->can_eliminate && ep->can_eliminate_previous)
3442 /* Find the current elimination for ep->from, if there is a
3444 for (op = reg_eliminate;
3445 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3446 if (op->from == ep->from && op->can_eliminate)
3452 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3454 for (op = reg_eliminate;
3455 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3456 if (op->from == new_to && op->to == ep->to)
3457 op->can_eliminate = 0;
3461 /* See if any registers that we thought we could eliminate the previous
3462 time are no longer eliminable. If so, something has changed and we
3463 must spill the register. Also, recompute the number of eliminable
3464 registers and see if the frame pointer is needed; it is if there is
3465 no elimination of the frame pointer that we can perform. */
3467 frame_pointer_needed = 1;
3468 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3470 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3471 && ep->to != HARD_FRAME_POINTER_REGNUM)
3472 frame_pointer_needed = 0;
3474 if (! ep->can_eliminate && ep->can_eliminate_previous)
3476 ep->can_eliminate_previous = 0;
3477 SET_HARD_REG_BIT (*pset, ep->from);
3482 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3483 /* If we didn't need a frame pointer last time, but we do now, spill
3484 the hard frame pointer. */
3485 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3486 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3490 /* Initialize the table of registers to eliminate. */
3495 struct elim_table *ep;
3496 #ifdef ELIMINABLE_REGS
3497 const struct elim_table_1 *ep1;
3501 reg_eliminate = (struct elim_table *)
3502 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3504 /* Does this function require a frame pointer? */
3506 frame_pointer_needed = (! flag_omit_frame_pointer
3507 #ifdef EXIT_IGNORE_STACK
3508 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3509 and restore sp for alloca. So we can't eliminate
3510 the frame pointer in that case. At some point,
3511 we should improve this by emitting the
3512 sp-adjusting insns for this case. */
3513 || (current_function_calls_alloca
3514 && EXIT_IGNORE_STACK)
3516 || FRAME_POINTER_REQUIRED);
3520 #ifdef ELIMINABLE_REGS
3521 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3522 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3524 ep->from = ep1->from;
3526 ep->can_eliminate = ep->can_eliminate_previous
3527 = (CAN_ELIMINATE (ep->from, ep->to)
3528 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3531 reg_eliminate[0].from = reg_eliminate_1[0].from;
3532 reg_eliminate[0].to = reg_eliminate_1[0].to;
3533 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3534 = ! frame_pointer_needed;
3537 /* Count the number of eliminable registers and build the FROM and TO
3538 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3539 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3540 We depend on this. */
3541 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3543 num_eliminable += ep->can_eliminate;
3544 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3545 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3549 /* Kick all pseudos out of hard register REGNO.
3551 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3552 because we found we can't eliminate some register. In the case, no pseudos
3553 are allowed to be in the register, even if they are only in a block that
3554 doesn't require spill registers, unlike the case when we are spilling this
3555 hard reg to produce another spill register.
3557 Return nonzero if any pseudos needed to be kicked out. */
3560 spill_hard_reg (regno, cant_eliminate)
3568 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3569 regs_ever_live[regno] = 1;
3572 /* Spill every pseudo reg that was allocated to this reg
3573 or to something that overlaps this reg. */
3575 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3576 if (reg_renumber[i] >= 0
3577 && (unsigned int) reg_renumber[i] <= regno
3578 && ((unsigned int) reg_renumber[i]
3579 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3580 PSEUDO_REGNO_MODE (i))
3582 SET_REGNO_REG_SET (&spilled_pseudos, i);
3585 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3586 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3589 ior_hard_reg_set (set1, set2)
3590 HARD_REG_SET *set1, *set2;
3592 IOR_HARD_REG_SET (*set1, *set2);
3595 /* After find_reload_regs has been run for all insn that need reloads,
3596 and/or spill_hard_regs was called, this function is used to actually
3597 spill pseudo registers and try to reallocate them. It also sets up the
3598 spill_regs array for use by choose_reload_regs. */
3601 finish_spills (global)
3604 struct insn_chain *chain;
3605 int something_changed = 0;
3608 /* Build the spill_regs array for the function. */
3609 /* If there are some registers still to eliminate and one of the spill regs
3610 wasn't ever used before, additional stack space may have to be
3611 allocated to store this register. Thus, we may have changed the offset
3612 between the stack and frame pointers, so mark that something has changed.
3614 One might think that we need only set VAL to 1 if this is a call-used
3615 register. However, the set of registers that must be saved by the
3616 prologue is not identical to the call-used set. For example, the
3617 register used by the call insn for the return PC is a call-used register,
3618 but must be saved by the prologue. */
3621 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3622 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3624 spill_reg_order[i] = n_spills;
3625 spill_regs[n_spills++] = i;
3626 if (num_eliminable && ! regs_ever_live[i])
3627 something_changed = 1;
3628 regs_ever_live[i] = 1;
3631 spill_reg_order[i] = -1;
3633 EXECUTE_IF_SET_IN_REG_SET
3634 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3636 /* Record the current hard register the pseudo is allocated to in
3637 pseudo_previous_regs so we avoid reallocating it to the same
3638 hard reg in a later pass. */
3639 if (reg_renumber[i] < 0)
3642 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3643 /* Mark it as no longer having a hard register home. */
3644 reg_renumber[i] = -1;
3645 /* We will need to scan everything again. */
3646 something_changed = 1;
3649 /* Retry global register allocation if possible. */
3652 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3653 /* For every insn that needs reloads, set the registers used as spill
3654 regs in pseudo_forbidden_regs for every pseudo live across the
3656 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3658 EXECUTE_IF_SET_IN_REG_SET
3659 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3661 ior_hard_reg_set (pseudo_forbidden_regs + i,
3662 &chain->used_spill_regs);
3664 EXECUTE_IF_SET_IN_REG_SET
3665 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3667 ior_hard_reg_set (pseudo_forbidden_regs + i,
3668 &chain->used_spill_regs);
3672 /* Retry allocating the spilled pseudos. For each reg, merge the
3673 various reg sets that indicate which hard regs can't be used,
3674 and call retry_global_alloc.
3675 We change spill_pseudos here to only contain pseudos that did not
3676 get a new hard register. */
3677 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3678 if (reg_old_renumber[i] != reg_renumber[i])
3680 HARD_REG_SET forbidden;
3681 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3682 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3683 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3684 retry_global_alloc (i, forbidden);
3685 if (reg_renumber[i] >= 0)
3686 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3690 /* Fix up the register information in the insn chain.
3691 This involves deleting those of the spilled pseudos which did not get
3692 a new hard register home from the live_{before,after} sets. */
3693 for (chain = reload_insn_chain; chain; chain = chain->next)
3695 HARD_REG_SET used_by_pseudos;
3696 HARD_REG_SET used_by_pseudos2;
3698 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3699 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3701 /* Mark any unallocated hard regs as available for spills. That
3702 makes inheritance work somewhat better. */
3703 if (chain->need_reload)
3705 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3706 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3707 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3709 /* Save the old value for the sanity test below. */
3710 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3712 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3713 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3714 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3715 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3717 /* Make sure we only enlarge the set. */
3718 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3724 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3725 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3727 int regno = reg_renumber[i];
3728 if (reg_old_renumber[i] == regno)
3731 alter_reg (i, reg_old_renumber[i]);
3732 reg_old_renumber[i] = regno;
3736 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3738 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3739 i, reg_renumber[i]);
3743 return something_changed;
3746 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3747 Also mark any hard registers used to store user variables as
3748 forbidden from being used for spill registers. */
3751 scan_paradoxical_subregs (x)
3756 enum rtx_code code = GET_CODE (x);
3762 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3763 && REG_USERVAR_P (x))
3764 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3773 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3781 if (GET_CODE (SUBREG_REG (x)) == REG
3782 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3783 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3784 = GET_MODE_SIZE (GET_MODE (x));
3791 fmt = GET_RTX_FORMAT (code);
3792 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3795 scan_paradoxical_subregs (XEXP (x, i));
3796 else if (fmt[i] == 'E')
3799 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3800 scan_paradoxical_subregs (XVECEXP (x, i, j));
3805 /* Reload pseudo-registers into hard regs around each insn as needed.
3806 Additional register load insns are output before the insn that needs it
3807 and perhaps store insns after insns that modify the reloaded pseudo reg.
3809 reg_last_reload_reg and reg_reloaded_contents keep track of
3810 which registers are already available in reload registers.
3811 We update these for the reloads that we perform,
3812 as the insns are scanned. */
3815 reload_as_needed (live_known)
3818 struct insn_chain *chain;
3819 #if defined (AUTO_INC_DEC)
3824 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3825 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3826 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3827 reg_has_output_reload = (char *) xmalloc (max_regno);
3828 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3830 set_initial_elim_offsets ();
3832 for (chain = reload_insn_chain; chain; chain = chain->next)
3835 rtx insn = chain->insn;
3836 rtx old_next = NEXT_INSN (insn);
3838 /* If we pass a label, copy the offsets from the label information
3839 into the current offsets of each elimination. */
3840 if (GET_CODE (insn) == CODE_LABEL)
3841 set_offsets_for_label (insn);
3843 else if (INSN_P (insn))
3845 rtx oldpat = PATTERN (insn);
3847 /* If this is a USE and CLOBBER of a MEM, ensure that any
3848 references to eliminable registers have been removed. */
3850 if ((GET_CODE (PATTERN (insn)) == USE
3851 || GET_CODE (PATTERN (insn)) == CLOBBER)
3852 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3853 XEXP (XEXP (PATTERN (insn), 0), 0)
3854 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3855 GET_MODE (XEXP (PATTERN (insn), 0)),
3858 /* If we need to do register elimination processing, do so.
3859 This might delete the insn, in which case we are done. */
3860 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3862 eliminate_regs_in_insn (insn, 1);
3863 if (GET_CODE (insn) == NOTE)
3865 update_eliminable_offsets ();
3870 /* If need_elim is nonzero but need_reload is zero, one might think
3871 that we could simply set n_reloads to 0. However, find_reloads
3872 could have done some manipulation of the insn (such as swapping
3873 commutative operands), and these manipulations are lost during
3874 the first pass for every insn that needs register elimination.
3875 So the actions of find_reloads must be redone here. */
3877 if (! chain->need_elim && ! chain->need_reload
3878 && ! chain->need_operand_change)
3880 /* First find the pseudo regs that must be reloaded for this insn.
3881 This info is returned in the tables reload_... (see reload.h).
3882 Also modify the body of INSN by substituting RELOAD
3883 rtx's for those pseudo regs. */
3886 memset (reg_has_output_reload, 0, max_regno);
3887 CLEAR_HARD_REG_SET (reg_is_output_reload);
3889 find_reloads (insn, 1, spill_indirect_levels, live_known,
3895 rtx next = NEXT_INSN (insn);
3898 prev = PREV_INSN (insn);
3900 /* Now compute which reload regs to reload them into. Perhaps
3901 reusing reload regs from previous insns, or else output
3902 load insns to reload them. Maybe output store insns too.
3903 Record the choices of reload reg in reload_reg_rtx. */
3904 choose_reload_regs (chain);
3906 /* Merge any reloads that we didn't combine for fear of
3907 increasing the number of spill registers needed but now
3908 discover can be safely merged. */
3909 if (SMALL_REGISTER_CLASSES)
3910 merge_assigned_reloads (insn);
3912 /* Generate the insns to reload operands into or out of
3913 their reload regs. */
3914 emit_reload_insns (chain);
3916 /* Substitute the chosen reload regs from reload_reg_rtx
3917 into the insn's body (or perhaps into the bodies of other
3918 load and store insn that we just made for reloading
3919 and that we moved the structure into). */
3920 subst_reloads (insn);
3922 /* If this was an ASM, make sure that all the reload insns
3923 we have generated are valid. If not, give an error
3926 if (asm_noperands (PATTERN (insn)) >= 0)
3927 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3928 if (p != insn && INSN_P (p)
3929 && (recog_memoized (p) < 0
3930 || (extract_insn (p), ! constrain_operands (1))))
3932 error_for_asm (insn,
3933 "`asm' operand requires impossible reload");
3938 if (num_eliminable && chain->need_elim)
3939 update_eliminable_offsets ();
3941 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3942 is no longer validly lying around to save a future reload.
3943 Note that this does not detect pseudos that were reloaded
3944 for this insn in order to be stored in
3945 (obeying register constraints). That is correct; such reload
3946 registers ARE still valid. */
3947 note_stores (oldpat, forget_old_reloads_1, NULL);
3949 /* There may have been CLOBBER insns placed after INSN. So scan
3950 between INSN and NEXT and use them to forget old reloads. */
3951 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3952 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3953 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3956 /* Likewise for regs altered by auto-increment in this insn.
3957 REG_INC notes have been changed by reloading:
3958 find_reloads_address_1 records substitutions for them,
3959 which have been performed by subst_reloads above. */
3960 for (i = n_reloads - 1; i >= 0; i--)
3962 rtx in_reg = rld[i].in_reg;
3965 enum rtx_code code = GET_CODE (in_reg);
3966 /* PRE_INC / PRE_DEC will have the reload register ending up
3967 with the same value as the stack slot, but that doesn't
3968 hold true for POST_INC / POST_DEC. Either we have to
3969 convert the memory access to a true POST_INC / POST_DEC,
3970 or we can't use the reload register for inheritance. */
3971 if ((code == POST_INC || code == POST_DEC)
3972 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3973 REGNO (rld[i].reg_rtx))
3974 /* Make sure it is the inc/dec pseudo, and not
3975 some other (e.g. output operand) pseudo. */
3976 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3977 == REGNO (XEXP (in_reg, 0))))
3980 rtx reload_reg = rld[i].reg_rtx;
3981 enum machine_mode mode = GET_MODE (reload_reg);
3985 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3987 /* We really want to ignore REG_INC notes here, so
3988 use PATTERN (p) as argument to reg_set_p . */
3989 if (reg_set_p (reload_reg, PATTERN (p)))
3991 n = count_occurrences (PATTERN (p), reload_reg, 0);
3996 n = validate_replace_rtx (reload_reg,
3997 gen_rtx (code, mode,
4001 /* We must also verify that the constraints
4002 are met after the replacement. */
4005 n = constrain_operands (1);
4009 /* If the constraints were not met, then
4010 undo the replacement. */
4013 validate_replace_rtx (gen_rtx (code, mode,
4025 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4027 /* Mark this as having an output reload so that the
4028 REG_INC processing code below won't invalidate
4029 the reload for inheritance. */
4030 SET_HARD_REG_BIT (reg_is_output_reload,
4031 REGNO (reload_reg));
4032 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4035 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4038 else if ((code == PRE_INC || code == PRE_DEC)
4039 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4040 REGNO (rld[i].reg_rtx))
4041 /* Make sure it is the inc/dec pseudo, and not
4042 some other (e.g. output operand) pseudo. */
4043 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4044 == REGNO (XEXP (in_reg, 0))))
4046 SET_HARD_REG_BIT (reg_is_output_reload,
4047 REGNO (rld[i].reg_rtx));
4048 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4052 /* If a pseudo that got a hard register is auto-incremented,
4053 we must purge records of copying it into pseudos without
4055 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4056 if (REG_NOTE_KIND (x) == REG_INC)
4058 /* See if this pseudo reg was reloaded in this insn.
4059 If so, its last-reload info is still valid
4060 because it is based on this insn's reload. */
4061 for (i = 0; i < n_reloads; i++)
4062 if (rld[i].out == XEXP (x, 0))
4066 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4070 /* A reload reg's contents are unknown after a label. */
4071 if (GET_CODE (insn) == CODE_LABEL)
4072 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4074 /* Don't assume a reload reg is still good after a call insn
4075 if it is a call-used reg. */
4076 else if (GET_CODE (insn) == CALL_INSN)
4077 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4081 free (reg_last_reload_reg);
4082 free (reg_has_output_reload);
4085 /* Discard all record of any value reloaded from X,
4086 or reloaded in X from someplace else;
4087 unless X is an output reload reg of the current insn.
4089 X may be a hard reg (the reload reg)
4090 or it may be a pseudo reg that was reloaded from. */
4093 forget_old_reloads_1 (x, ignored, data)
4095 rtx ignored ATTRIBUTE_UNUSED;
4096 void *data ATTRIBUTE_UNUSED;
4101 /* note_stores does give us subregs of hard regs,
4102 subreg_regno_offset will abort if it is not a hard reg. */
4103 while (GET_CODE (x) == SUBREG)
4105 /* We ignore the subreg offset when calculating the regno,
4106 because we are using the entire underlying hard register
4111 if (GET_CODE (x) != REG)
4116 if (regno >= FIRST_PSEUDO_REGISTER)
4122 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4123 /* Storing into a spilled-reg invalidates its contents.
4124 This can happen if a block-local pseudo is allocated to that reg
4125 and it wasn't spilled because this block's total need is 0.
4126 Then some insn might have an optional reload and use this reg. */
4127 for (i = 0; i < nr; i++)
4128 /* But don't do this if the reg actually serves as an output
4129 reload reg in the current instruction. */
4131 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4133 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4134 spill_reg_store[regno + i] = 0;
4138 /* Since value of X has changed,
4139 forget any value previously copied from it. */
4142 /* But don't forget a copy if this is the output reload
4143 that establishes the copy's validity. */
4144 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4145 reg_last_reload_reg[regno + nr] = 0;
4148 /* The following HARD_REG_SETs indicate when each hard register is
4149 used for a reload of various parts of the current insn. */
4151 /* If reg is unavailable for all reloads. */
4152 static HARD_REG_SET reload_reg_unavailable;
4153 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4154 static HARD_REG_SET reload_reg_used;
4155 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4156 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4157 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4158 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4159 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4160 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4161 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4162 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4163 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4164 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4165 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4166 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4167 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4168 static HARD_REG_SET reload_reg_used_in_op_addr;
4169 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4170 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4171 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4172 static HARD_REG_SET reload_reg_used_in_insn;
4173 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4174 static HARD_REG_SET reload_reg_used_in_other_addr;
4176 /* If reg is in use as a reload reg for any sort of reload. */
4177 static HARD_REG_SET reload_reg_used_at_all;
4179 /* If reg is use as an inherited reload. We just mark the first register
4181 static HARD_REG_SET reload_reg_used_for_inherit;
4183 /* Records which hard regs are used in any way, either as explicit use or
4184 by being allocated to a pseudo during any point of the current insn. */
4185 static HARD_REG_SET reg_used_in_insn;
4187 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4188 TYPE. MODE is used to indicate how many consecutive regs are
4192 mark_reload_reg_in_use (regno, opnum, type, mode)
4195 enum reload_type type;
4196 enum machine_mode mode;
4198 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4201 for (i = regno; i < nregs + regno; i++)
4206 SET_HARD_REG_BIT (reload_reg_used, i);
4209 case RELOAD_FOR_INPUT_ADDRESS:
4210 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4213 case RELOAD_FOR_INPADDR_ADDRESS:
4214 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4217 case RELOAD_FOR_OUTPUT_ADDRESS:
4218 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4221 case RELOAD_FOR_OUTADDR_ADDRESS:
4222 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4225 case RELOAD_FOR_OPERAND_ADDRESS:
4226 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4229 case RELOAD_FOR_OPADDR_ADDR:
4230 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4233 case RELOAD_FOR_OTHER_ADDRESS:
4234 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4237 case RELOAD_FOR_INPUT:
4238 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4241 case RELOAD_FOR_OUTPUT:
4242 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4245 case RELOAD_FOR_INSN:
4246 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4250 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4254 /* Similarly, but show REGNO is no longer in use for a reload. */
4257 clear_reload_reg_in_use (regno, opnum, type, mode)
4260 enum reload_type type;
4261 enum machine_mode mode;
4263 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4264 unsigned int start_regno, end_regno, r;
4266 /* A complication is that for some reload types, inheritance might
4267 allow multiple reloads of the same types to share a reload register.
4268 We set check_opnum if we have to check only reloads with the same
4269 operand number, and check_any if we have to check all reloads. */
4270 int check_opnum = 0;
4272 HARD_REG_SET *used_in_set;
4277 used_in_set = &reload_reg_used;
4280 case RELOAD_FOR_INPUT_ADDRESS:
4281 used_in_set = &reload_reg_used_in_input_addr[opnum];
4284 case RELOAD_FOR_INPADDR_ADDRESS:
4286 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4289 case RELOAD_FOR_OUTPUT_ADDRESS:
4290 used_in_set = &reload_reg_used_in_output_addr[opnum];
4293 case RELOAD_FOR_OUTADDR_ADDRESS:
4295 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4298 case RELOAD_FOR_OPERAND_ADDRESS:
4299 used_in_set = &reload_reg_used_in_op_addr;
4302 case RELOAD_FOR_OPADDR_ADDR:
4304 used_in_set = &reload_reg_used_in_op_addr_reload;
4307 case RELOAD_FOR_OTHER_ADDRESS:
4308 used_in_set = &reload_reg_used_in_other_addr;
4312 case RELOAD_FOR_INPUT:
4313 used_in_set = &reload_reg_used_in_input[opnum];
4316 case RELOAD_FOR_OUTPUT:
4317 used_in_set = &reload_reg_used_in_output[opnum];
4320 case RELOAD_FOR_INSN:
4321 used_in_set = &reload_reg_used_in_insn;
4326 /* We resolve conflicts with remaining reloads of the same type by
4327 excluding the intervals of of reload registers by them from the
4328 interval of freed reload registers. Since we only keep track of
4329 one set of interval bounds, we might have to exclude somewhat
4330 more than what would be necessary if we used a HARD_REG_SET here.
4331 But this should only happen very infrequently, so there should
4332 be no reason to worry about it. */
4334 start_regno = regno;
4335 end_regno = regno + nregs;
4336 if (check_opnum || check_any)
4338 for (i = n_reloads - 1; i >= 0; i--)
4340 if (rld[i].when_needed == type
4341 && (check_any || rld[i].opnum == opnum)
4344 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4345 unsigned int conflict_end
4347 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4349 /* If there is an overlap with the first to-be-freed register,
4350 adjust the interval start. */
4351 if (conflict_start <= start_regno && conflict_end > start_regno)
4352 start_regno = conflict_end;
4353 /* Otherwise, if there is a conflict with one of the other
4354 to-be-freed registers, adjust the interval end. */
4355 if (conflict_start > start_regno && conflict_start < end_regno)
4356 end_regno = conflict_start;
4361 for (r = start_regno; r < end_regno; r++)
4362 CLEAR_HARD_REG_BIT (*used_in_set, r);
4365 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4366 specified by OPNUM and TYPE. */
4369 reload_reg_free_p (regno, opnum, type)
4372 enum reload_type type;
4376 /* In use for a RELOAD_OTHER means it's not available for anything. */
4377 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4378 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4384 /* In use for anything means we can't use it for RELOAD_OTHER. */
4385 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4386 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4387 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4390 for (i = 0; i < reload_n_operands; i++)
4391 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4392 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4393 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4394 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4395 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4396 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4401 case RELOAD_FOR_INPUT:
4402 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4403 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4409 /* If it is used for some other input, can't use it. */
4410 for (i = 0; i < reload_n_operands; i++)
4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4414 /* If it is used in a later operand's address, can't use it. */
4415 for (i = opnum + 1; i < reload_n_operands; i++)
4416 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4417 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4422 case RELOAD_FOR_INPUT_ADDRESS:
4423 /* Can't use a register if it is used for an input address for this
4424 operand or used as an input in an earlier one. */
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4426 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4429 for (i = 0; i < opnum; i++)
4430 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4435 case RELOAD_FOR_INPADDR_ADDRESS:
4436 /* Can't use a register if it is used for an input address
4437 for this operand or used as an input in an earlier
4439 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4442 for (i = 0; i < opnum; i++)
4443 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4448 case RELOAD_FOR_OUTPUT_ADDRESS:
4449 /* Can't use a register if it is used for an output address for this
4450 operand or used as an output in this or a later operand. Note
4451 that multiple output operands are emitted in reverse order, so
4452 the conflicting ones are those with lower indices. */
4453 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4456 for (i = 0; i <= opnum; i++)
4457 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4462 case RELOAD_FOR_OUTADDR_ADDRESS:
4463 /* Can't use a register if it is used for an output address
4464 for this operand or used as an output in this or a
4465 later operand. Note that multiple output operands are
4466 emitted in reverse order, so the conflicting ones are
4467 those with lower indices. */
4468 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4471 for (i = 0; i <= opnum; i++)
4472 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4477 case RELOAD_FOR_OPERAND_ADDRESS:
4478 for (i = 0; i < reload_n_operands; i++)
4479 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4482 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4483 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4485 case RELOAD_FOR_OPADDR_ADDR:
4486 for (i = 0; i < reload_n_operands; i++)
4487 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4490 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4492 case RELOAD_FOR_OUTPUT:
4493 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4494 outputs, or an operand address for this or an earlier output.
4495 Note that multiple output operands are emitted in reverse order,
4496 so the conflicting ones are those with higher indices. */
4497 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4500 for (i = 0; i < reload_n_operands; i++)
4501 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4504 for (i = opnum; i < reload_n_operands; i++)
4505 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4506 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4511 case RELOAD_FOR_INSN:
4512 for (i = 0; i < reload_n_operands; i++)
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4517 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4518 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4520 case RELOAD_FOR_OTHER_ADDRESS:
4521 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4526 /* Return 1 if the value in reload reg REGNO, as used by a reload
4527 needed for the part of the insn specified by OPNUM and TYPE,
4528 is still available in REGNO at the end of the insn.
4530 We can assume that the reload reg was already tested for availability
4531 at the time it is needed, and we should not check this again,
4532 in case the reg has already been marked in use. */
4535 reload_reg_reaches_end_p (regno, opnum, type)
4538 enum reload_type type;
4545 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4546 its value must reach the end. */
4549 /* If this use is for part of the insn,
4550 its value reaches if no subsequent part uses the same register.
4551 Just like the above function, don't try to do this with lots
4554 case RELOAD_FOR_OTHER_ADDRESS:
4555 /* Here we check for everything else, since these don't conflict
4556 with anything else and everything comes later. */
4558 for (i = 0; i < reload_n_operands; i++)
4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4560 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4561 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4562 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4567 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4568 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4569 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4571 case RELOAD_FOR_INPUT_ADDRESS:
4572 case RELOAD_FOR_INPADDR_ADDRESS:
4573 /* Similar, except that we check only for this and subsequent inputs
4574 and the address of only subsequent inputs and we do not need
4575 to check for RELOAD_OTHER objects since they are known not to
4578 for (i = opnum; i < reload_n_operands; i++)
4579 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4582 for (i = opnum + 1; i < reload_n_operands; i++)
4583 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4584 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4587 for (i = 0; i < reload_n_operands; i++)
4588 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4589 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4590 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4593 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4596 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4597 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4598 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4600 case RELOAD_FOR_INPUT:
4601 /* Similar to input address, except we start at the next operand for
4602 both input and input address and we do not check for
4603 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4606 for (i = opnum + 1; i < reload_n_operands; i++)
4607 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4608 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4612 /* ... fall through ... */
4614 case RELOAD_FOR_OPERAND_ADDRESS:
4615 /* Check outputs and their addresses. */
4617 for (i = 0; i < reload_n_operands; i++)
4618 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4620 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4623 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4625 case RELOAD_FOR_OPADDR_ADDR:
4626 for (i = 0; i < reload_n_operands; i++)
4627 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4628 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4629 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4632 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4633 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4634 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4636 case RELOAD_FOR_INSN:
4637 /* These conflict with other outputs with RELOAD_OTHER. So
4638 we need only check for output addresses. */
4640 opnum = reload_n_operands;
4642 /* ... fall through ... */
4644 case RELOAD_FOR_OUTPUT:
4645 case RELOAD_FOR_OUTPUT_ADDRESS:
4646 case RELOAD_FOR_OUTADDR_ADDRESS:
4647 /* We already know these can't conflict with a later output. So the
4648 only thing to check are later output addresses.
4649 Note that multiple output operands are emitted in reverse order,
4650 so the conflicting ones are those with lower indices. */
4651 for (i = 0; i < opnum; i++)
4652 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4653 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4662 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4665 This function uses the same algorithm as reload_reg_free_p above. */
4668 reloads_conflict (r1, r2)
4671 enum reload_type r1_type = rld[r1].when_needed;
4672 enum reload_type r2_type = rld[r2].when_needed;
4673 int r1_opnum = rld[r1].opnum;
4674 int r2_opnum = rld[r2].opnum;
4676 /* RELOAD_OTHER conflicts with everything. */
4677 if (r2_type == RELOAD_OTHER)
4680 /* Otherwise, check conflicts differently for each type. */
4684 case RELOAD_FOR_INPUT:
4685 return (r2_type == RELOAD_FOR_INSN
4686 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4687 || r2_type == RELOAD_FOR_OPADDR_ADDR
4688 || r2_type == RELOAD_FOR_INPUT
4689 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4690 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4691 && r2_opnum > r1_opnum));
4693 case RELOAD_FOR_INPUT_ADDRESS:
4694 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4695 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4697 case RELOAD_FOR_INPADDR_ADDRESS:
4698 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4699 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4701 case RELOAD_FOR_OUTPUT_ADDRESS:
4702 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4703 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4705 case RELOAD_FOR_OUTADDR_ADDRESS:
4706 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4707 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4709 case RELOAD_FOR_OPERAND_ADDRESS:
4710 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4711 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4713 case RELOAD_FOR_OPADDR_ADDR:
4714 return (r2_type == RELOAD_FOR_INPUT
4715 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4717 case RELOAD_FOR_OUTPUT:
4718 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4719 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4720 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4721 && r2_opnum >= r1_opnum));
4723 case RELOAD_FOR_INSN:
4724 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4725 || r2_type == RELOAD_FOR_INSN
4726 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4728 case RELOAD_FOR_OTHER_ADDRESS:
4729 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4739 /* Indexed by reload number, 1 if incoming value
4740 inherited from previous insns. */
4741 char reload_inherited[MAX_RELOADS];
4743 /* For an inherited reload, this is the insn the reload was inherited from,
4744 if we know it. Otherwise, this is 0. */
4745 rtx reload_inheritance_insn[MAX_RELOADS];
4747 /* If non-zero, this is a place to get the value of the reload,
4748 rather than using reload_in. */
4749 rtx reload_override_in[MAX_RELOADS];
4751 /* For each reload, the hard register number of the register used,
4752 or -1 if we did not need a register for this reload. */
4753 int reload_spill_index[MAX_RELOADS];
4755 /* Subroutine of free_for_value_p, used to check a single register.
4756 START_REGNO is the starting regno of the full reload register
4757 (possibly comprising multiple hard registers) that we are considering. */
4760 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4761 reloadnum, ignore_address_reloads)
4762 int start_regno, regno;
4764 enum reload_type type;
4767 int ignore_address_reloads;
4770 /* Set if we see an input reload that must not share its reload register
4771 with any new earlyclobber, but might otherwise share the reload
4772 register with an output or input-output reload. */
4773 int check_earlyclobber = 0;
4777 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4780 if (out == const0_rtx)
4786 /* We use some pseudo 'time' value to check if the lifetimes of the
4787 new register use would overlap with the one of a previous reload
4788 that is not read-only or uses a different value.
4789 The 'time' used doesn't have to be linear in any shape or form, just
4791 Some reload types use different 'buckets' for each operand.
4792 So there are MAX_RECOG_OPERANDS different time values for each
4794 We compute TIME1 as the time when the register for the prospective
4795 new reload ceases to be live, and TIME2 for each existing
4796 reload as the time when that the reload register of that reload
4798 Where there is little to be gained by exact lifetime calculations,
4799 we just make conservative assumptions, i.e. a longer lifetime;
4800 this is done in the 'default:' cases. */
4803 case RELOAD_FOR_OTHER_ADDRESS:
4804 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4805 time1 = copy ? 0 : 1;
4808 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4810 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4811 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4812 respectively, to the time values for these, we get distinct time
4813 values. To get distinct time values for each operand, we have to
4814 multiply opnum by at least three. We round that up to four because
4815 multiply by four is often cheaper. */
4816 case RELOAD_FOR_INPADDR_ADDRESS:
4817 time1 = opnum * 4 + 2;
4819 case RELOAD_FOR_INPUT_ADDRESS:
4820 time1 = opnum * 4 + 3;
4822 case RELOAD_FOR_INPUT:
4823 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4824 executes (inclusive). */
4825 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4827 case RELOAD_FOR_OPADDR_ADDR:
4829 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4830 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4832 case RELOAD_FOR_OPERAND_ADDRESS:
4833 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4835 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4837 case RELOAD_FOR_OUTADDR_ADDRESS:
4838 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4840 case RELOAD_FOR_OUTPUT_ADDRESS:
4841 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4844 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4847 for (i = 0; i < n_reloads; i++)
4849 rtx reg = rld[i].reg_rtx;
4850 if (reg && GET_CODE (reg) == REG
4851 && ((unsigned) regno - true_regnum (reg)
4852 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4855 rtx other_input = rld[i].in;
4857 /* If the other reload loads the same input value, that
4858 will not cause a conflict only if it's loading it into
4859 the same register. */
4860 if (true_regnum (reg) != start_regno)
4861 other_input = NULL_RTX;
4862 if (! other_input || ! rtx_equal_p (other_input, value)
4863 || rld[i].out || out)
4866 switch (rld[i].when_needed)
4868 case RELOAD_FOR_OTHER_ADDRESS:
4871 case RELOAD_FOR_INPADDR_ADDRESS:
4872 /* find_reloads makes sure that a
4873 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4874 by at most one - the first -
4875 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4876 address reload is inherited, the address address reload
4877 goes away, so we can ignore this conflict. */
4878 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4879 && ignore_address_reloads
4880 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4881 Then the address address is still needed to store
4882 back the new address. */
4883 && ! rld[reloadnum].out)
4885 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4886 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4888 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4889 && ignore_address_reloads
4890 /* Unless we are reloading an auto_inc expression. */
4891 && ! rld[reloadnum].out)
4893 time2 = rld[i].opnum * 4 + 2;
4895 case RELOAD_FOR_INPUT_ADDRESS:
4896 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4897 && ignore_address_reloads
4898 && ! rld[reloadnum].out)
4900 time2 = rld[i].opnum * 4 + 3;
4902 case RELOAD_FOR_INPUT:
4903 time2 = rld[i].opnum * 4 + 4;
4904 check_earlyclobber = 1;
4906 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4907 == MAX_RECOG_OPERAND * 4 */
4908 case RELOAD_FOR_OPADDR_ADDR:
4909 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4910 && ignore_address_reloads
4911 && ! rld[reloadnum].out)
4913 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4915 case RELOAD_FOR_OPERAND_ADDRESS:
4916 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4917 check_earlyclobber = 1;
4919 case RELOAD_FOR_INSN:
4920 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4922 case RELOAD_FOR_OUTPUT:
4923 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4924 instruction is executed. */
4925 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4927 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4928 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4930 case RELOAD_FOR_OUTADDR_ADDRESS:
4931 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4932 && ignore_address_reloads
4933 && ! rld[reloadnum].out)
4935 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4937 case RELOAD_FOR_OUTPUT_ADDRESS:
4938 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4941 /* If there is no conflict in the input part, handle this
4942 like an output reload. */
4943 if (! rld[i].in || rtx_equal_p (other_input, value))
4945 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4946 /* Earlyclobbered outputs must conflict with inputs. */
4947 if (earlyclobber_operand_p (rld[i].out))
4948 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4953 /* RELOAD_OTHER might be live beyond instruction execution,
4954 but this is not obvious when we set time2 = 1. So check
4955 here if there might be a problem with the new reload
4956 clobbering the register used by the RELOAD_OTHER. */
4964 && (! rld[i].in || rld[i].out
4965 || ! rtx_equal_p (other_input, value)))
4966 || (out && rld[reloadnum].out_reg
4967 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4973 /* Earlyclobbered outputs must conflict with inputs. */
4974 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4980 /* Return 1 if the value in reload reg REGNO, as used by a reload
4981 needed for the part of the insn specified by OPNUM and TYPE,
4982 may be used to load VALUE into it.
4984 MODE is the mode in which the register is used, this is needed to
4985 determine how many hard regs to test.
4987 Other read-only reloads with the same value do not conflict
4988 unless OUT is non-zero and these other reloads have to live while
4989 output reloads live.
4990 If OUT is CONST0_RTX, this is a special case: it means that the
4991 test should not be for using register REGNO as reload register, but
4992 for copying from register REGNO into the reload register.
4994 RELOADNUM is the number of the reload we want to load this value for;
4995 a reload does not conflict with itself.
4997 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4998 reloads that load an address for the very reload we are considering.
5000 The caller has to make sure that there is no conflict with the return
5004 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5005 ignore_address_reloads)
5007 enum machine_mode mode;
5009 enum reload_type type;
5012 int ignore_address_reloads;
5014 int nregs = HARD_REGNO_NREGS (regno, mode);
5016 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5017 value, out, reloadnum,
5018 ignore_address_reloads))
5023 /* Determine whether the reload reg X overlaps any rtx'es used for
5024 overriding inheritance. Return nonzero if so. */
5027 conflicts_with_override (x)
5031 for (i = 0; i < n_reloads; i++)
5032 if (reload_override_in[i]
5033 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5038 /* Give an error message saying we failed to find a reload for INSN,
5039 and clear out reload R. */
5041 failed_reload (insn, r)
5045 if (asm_noperands (PATTERN (insn)) < 0)
5046 /* It's the compiler's fault. */
5047 fatal_insn ("could not find a spill register", insn);
5049 /* It's the user's fault; the operand's mode and constraint
5050 don't match. Disable this reload so we don't crash in final. */
5051 error_for_asm (insn,
5052 "`asm' operand constraint incompatible with operand size");
5056 rld[r].optional = 1;
5057 rld[r].secondary_p = 1;
5060 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5061 for reload R. If it's valid, get an rtx for it. Return nonzero if
5064 set_reload_reg (i, r)
5068 rtx reg = spill_reg_rtx[i];
5070 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5071 spill_reg_rtx[i] = reg
5072 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5074 regno = true_regnum (reg);
5076 /* Detect when the reload reg can't hold the reload mode.
5077 This used to be one `if', but Sequent compiler can't handle that. */
5078 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5080 enum machine_mode test_mode = VOIDmode;
5082 test_mode = GET_MODE (rld[r].in);
5083 /* If rld[r].in has VOIDmode, it means we will load it
5084 in whatever mode the reload reg has: to wit, rld[r].mode.
5085 We have already tested that for validity. */
5086 /* Aside from that, we need to test that the expressions
5087 to reload from or into have modes which are valid for this
5088 reload register. Otherwise the reload insns would be invalid. */
5089 if (! (rld[r].in != 0 && test_mode != VOIDmode
5090 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5091 if (! (rld[r].out != 0
5092 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5094 /* The reg is OK. */
5097 /* Mark as in use for this insn the reload regs we use
5099 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5100 rld[r].when_needed, rld[r].mode);
5102 rld[r].reg_rtx = reg;
5103 reload_spill_index[r] = spill_regs[i];
5110 /* Find a spill register to use as a reload register for reload R.
5111 LAST_RELOAD is non-zero if this is the last reload for the insn being
5114 Set rld[R].reg_rtx to the register allocated.
5116 We return 1 if successful, or 0 if we couldn't find a spill reg and
5117 we didn't change anything. */
5120 allocate_reload_reg (chain, r, last_reload)
5121 struct insn_chain *chain ATTRIBUTE_UNUSED;
5127 /* If we put this reload ahead, thinking it is a group,
5128 then insist on finding a group. Otherwise we can grab a
5129 reg that some other reload needs.
5130 (That can happen when we have a 68000 DATA_OR_FP_REG
5131 which is a group of data regs or one fp reg.)
5132 We need not be so restrictive if there are no more reloads
5135 ??? Really it would be nicer to have smarter handling
5136 for that kind of reg class, where a problem like this is normal.
5137 Perhaps those classes should be avoided for reloading
5138 by use of more alternatives. */
5140 int force_group = rld[r].nregs > 1 && ! last_reload;
5142 /* If we want a single register and haven't yet found one,
5143 take any reg in the right class and not in use.
5144 If we want a consecutive group, here is where we look for it.
5146 We use two passes so we can first look for reload regs to
5147 reuse, which are already in use for other reloads in this insn,
5148 and only then use additional registers.
5149 I think that maximizing reuse is needed to make sure we don't
5150 run out of reload regs. Suppose we have three reloads, and
5151 reloads A and B can share regs. These need two regs.
5152 Suppose A and B are given different regs.
5153 That leaves none for C. */
5154 for (pass = 0; pass < 2; pass++)
5156 /* I is the index in spill_regs.
5157 We advance it round-robin between insns to use all spill regs
5158 equally, so that inherited reloads have a chance
5159 of leapfrogging each other. */
5163 for (count = 0; count < n_spills; count++)
5165 int class = (int) rld[r].class;
5171 regnum = spill_regs[i];
5173 if ((reload_reg_free_p (regnum, rld[r].opnum,
5176 /* We check reload_reg_used to make sure we
5177 don't clobber the return register. */
5178 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5179 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5180 rld[r].when_needed, rld[r].in,
5182 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5183 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5184 /* Look first for regs to share, then for unshared. But
5185 don't share regs used for inherited reloads; they are
5186 the ones we want to preserve. */
5188 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5190 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5193 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5194 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5195 (on 68000) got us two FP regs. If NR is 1,
5196 we would reject both of them. */
5199 /* If we need only one reg, we have already won. */
5202 /* But reject a single reg if we demand a group. */
5207 /* Otherwise check that as many consecutive regs as we need
5208 are available here. */
5211 int regno = regnum + nr - 1;
5212 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5213 && spill_reg_order[regno] >= 0
5214 && reload_reg_free_p (regno, rld[r].opnum,
5215 rld[r].when_needed)))
5224 /* If we found something on pass 1, omit pass 2. */
5225 if (count < n_spills)
5229 /* We should have found a spill register by now. */
5230 if (count >= n_spills)
5233 /* I is the index in SPILL_REG_RTX of the reload register we are to
5234 allocate. Get an rtx for it and find its register number. */
5236 return set_reload_reg (i, r);
5239 /* Initialize all the tables needed to allocate reload registers.
5240 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5241 is the array we use to restore the reg_rtx field for every reload. */
5244 choose_reload_regs_init (chain, save_reload_reg_rtx)
5245 struct insn_chain *chain;
5246 rtx *save_reload_reg_rtx;
5250 for (i = 0; i < n_reloads; i++)
5251 rld[i].reg_rtx = save_reload_reg_rtx[i];
5253 memset (reload_inherited, 0, MAX_RELOADS);
5254 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5255 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5257 CLEAR_HARD_REG_SET (reload_reg_used);
5258 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5259 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5260 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5261 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5262 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5264 CLEAR_HARD_REG_SET (reg_used_in_insn);
5267 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5268 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5269 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5270 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5271 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5272 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5275 for (i = 0; i < reload_n_operands; i++)
5277 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5278 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5279 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5280 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5281 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5282 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5285 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5287 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5289 for (i = 0; i < n_reloads; i++)
5290 /* If we have already decided to use a certain register,
5291 don't use it in another way. */
5293 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5294 rld[i].when_needed, rld[i].mode);
5297 /* Assign hard reg targets for the pseudo-registers we must reload
5298 into hard regs for this insn.
5299 Also output the instructions to copy them in and out of the hard regs.
5301 For machines with register classes, we are responsible for
5302 finding a reload reg in the proper class. */
5305 choose_reload_regs (chain)
5306 struct insn_chain *chain;
5308 rtx insn = chain->insn;
5310 unsigned int max_group_size = 1;
5311 enum reg_class group_class = NO_REGS;
5312 int pass, win, inheritance;
5314 rtx save_reload_reg_rtx[MAX_RELOADS];
5316 /* In order to be certain of getting the registers we need,
5317 we must sort the reloads into order of increasing register class.
5318 Then our grabbing of reload registers will parallel the process
5319 that provided the reload registers.
5321 Also note whether any of the reloads wants a consecutive group of regs.
5322 If so, record the maximum size of the group desired and what
5323 register class contains all the groups needed by this insn. */
5325 for (j = 0; j < n_reloads; j++)
5327 reload_order[j] = j;
5328 reload_spill_index[j] = -1;
5330 if (rld[j].nregs > 1)
5332 max_group_size = MAX (rld[j].nregs, max_group_size);
5334 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5337 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5341 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5343 /* If -O, try first with inheritance, then turning it off.
5344 If not -O, don't do inheritance.
5345 Using inheritance when not optimizing leads to paradoxes
5346 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5347 because one side of the comparison might be inherited. */
5349 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5351 choose_reload_regs_init (chain, save_reload_reg_rtx);
5353 /* Process the reloads in order of preference just found.
5354 Beyond this point, subregs can be found in reload_reg_rtx.
5356 This used to look for an existing reloaded home for all of the
5357 reloads, and only then perform any new reloads. But that could lose
5358 if the reloads were done out of reg-class order because a later
5359 reload with a looser constraint might have an old home in a register
5360 needed by an earlier reload with a tighter constraint.
5362 To solve this, we make two passes over the reloads, in the order
5363 described above. In the first pass we try to inherit a reload
5364 from a previous insn. If there is a later reload that needs a
5365 class that is a proper subset of the class being processed, we must
5366 also allocate a spill register during the first pass.
5368 Then make a second pass over the reloads to allocate any reloads
5369 that haven't been given registers yet. */
5371 for (j = 0; j < n_reloads; j++)
5373 int r = reload_order[j];
5374 rtx search_equiv = NULL_RTX;
5376 /* Ignore reloads that got marked inoperative. */
5377 if (rld[r].out == 0 && rld[r].in == 0
5378 && ! rld[r].secondary_p)
5381 /* If find_reloads chose to use reload_in or reload_out as a reload
5382 register, we don't need to chose one. Otherwise, try even if it
5383 found one since we might save an insn if we find the value lying
5385 Try also when reload_in is a pseudo without a hard reg. */
5386 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5387 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5388 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5389 && GET_CODE (rld[r].in) != MEM
5390 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5393 #if 0 /* No longer needed for correct operation.
5394 It might give better code, or might not; worth an experiment? */
5395 /* If this is an optional reload, we can't inherit from earlier insns
5396 until we are sure that any non-optional reloads have been allocated.
5397 The following code takes advantage of the fact that optional reloads
5398 are at the end of reload_order. */
5399 if (rld[r].optional != 0)
5400 for (i = 0; i < j; i++)
5401 if ((rld[reload_order[i]].out != 0
5402 || rld[reload_order[i]].in != 0
5403 || rld[reload_order[i]].secondary_p)
5404 && ! rld[reload_order[i]].optional
5405 && rld[reload_order[i]].reg_rtx == 0)
5406 allocate_reload_reg (chain, reload_order[i], 0);
5409 /* First see if this pseudo is already available as reloaded
5410 for a previous insn. We cannot try to inherit for reloads
5411 that are smaller than the maximum number of registers needed
5412 for groups unless the register we would allocate cannot be used
5415 We could check here to see if this is a secondary reload for
5416 an object that is already in a register of the desired class.
5417 This would avoid the need for the secondary reload register.
5418 But this is complex because we can't easily determine what
5419 objects might want to be loaded via this reload. So let a
5420 register be allocated here. In `emit_reload_insns' we suppress
5421 one of the loads in the case described above. */
5427 enum machine_mode mode = VOIDmode;
5431 else if (GET_CODE (rld[r].in) == REG)
5433 regno = REGNO (rld[r].in);
5434 mode = GET_MODE (rld[r].in);
5436 else if (GET_CODE (rld[r].in_reg) == REG)
5438 regno = REGNO (rld[r].in_reg);
5439 mode = GET_MODE (rld[r].in_reg);
5441 else if (GET_CODE (rld[r].in_reg) == SUBREG
5442 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5444 byte = SUBREG_BYTE (rld[r].in_reg);
5445 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5446 if (regno < FIRST_PSEUDO_REGISTER)
5447 regno = subreg_regno (rld[r].in_reg);
5448 mode = GET_MODE (rld[r].in_reg);
5451 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5452 || GET_CODE (rld[r].in_reg) == PRE_DEC
5453 || GET_CODE (rld[r].in_reg) == POST_INC
5454 || GET_CODE (rld[r].in_reg) == POST_DEC)
5455 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5457 regno = REGNO (XEXP (rld[r].in_reg, 0));
5458 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5459 rld[r].out = rld[r].in;
5463 /* This won't work, since REGNO can be a pseudo reg number.
5464 Also, it takes much more hair to keep track of all the things
5465 that can invalidate an inherited reload of part of a pseudoreg. */
5466 else if (GET_CODE (rld[r].in) == SUBREG
5467 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5468 regno = subreg_regno (rld[r].in);
5471 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5473 enum reg_class class = rld[r].class, last_class;
5474 rtx last_reg = reg_last_reload_reg[regno];
5475 enum machine_mode need_mode;
5477 i = REGNO (last_reg);
5478 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5479 last_class = REGNO_REG_CLASS (i);
5485 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5486 GET_MODE_CLASS (mode));
5489 #ifdef CLASS_CANNOT_CHANGE_MODE
5491 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5492 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5494 : (GET_MODE_SIZE (GET_MODE (last_reg))
5495 >= GET_MODE_SIZE (need_mode)))
5497 (GET_MODE_SIZE (GET_MODE (last_reg))
5498 >= GET_MODE_SIZE (need_mode))
5500 && reg_reloaded_contents[i] == regno
5501 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5502 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5503 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5504 /* Even if we can't use this register as a reload
5505 register, we might use it for reload_override_in,
5506 if copying it to the desired class is cheap
5508 || ((REGISTER_MOVE_COST (mode, last_class, class)
5509 < MEMORY_MOVE_COST (mode, class, 1))
5510 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5511 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5515 #ifdef SECONDARY_MEMORY_NEEDED
5516 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5521 && (rld[r].nregs == max_group_size
5522 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5524 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5525 rld[r].when_needed, rld[r].in,
5528 /* If a group is needed, verify that all the subsequent
5529 registers still have their values intact. */
5530 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5533 for (k = 1; k < nr; k++)
5534 if (reg_reloaded_contents[i + k] != regno
5535 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5543 last_reg = (GET_MODE (last_reg) == mode
5544 ? last_reg : gen_rtx_REG (mode, i));
5547 for (k = 0; k < nr; k++)
5548 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5551 /* We found a register that contains the
5552 value we need. If this register is the
5553 same as an `earlyclobber' operand of the
5554 current insn, just mark it as a place to
5555 reload from since we can't use it as the
5556 reload register itself. */
5558 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5559 if (reg_overlap_mentioned_for_reload_p
5560 (reg_last_reload_reg[regno],
5561 reload_earlyclobbers[i1]))
5564 if (i1 != n_earlyclobbers
5565 || ! (free_for_value_p (i, rld[r].mode,
5567 rld[r].when_needed, rld[r].in,
5569 /* Don't use it if we'd clobber a pseudo reg. */
5570 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5572 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5573 /* Don't clobber the frame pointer. */
5574 || (i == HARD_FRAME_POINTER_REGNUM
5575 && frame_pointer_needed
5577 /* Don't really use the inherited spill reg
5578 if we need it wider than we've got it. */
5579 || (GET_MODE_SIZE (rld[r].mode)
5580 > GET_MODE_SIZE (mode))
5583 /* If find_reloads chose reload_out as reload
5584 register, stay with it - that leaves the
5585 inherited register for subsequent reloads. */
5586 || (rld[r].out && rld[r].reg_rtx
5587 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5589 if (! rld[r].optional)
5591 reload_override_in[r] = last_reg;
5592 reload_inheritance_insn[r]
5593 = reg_reloaded_insn[i];
5599 /* We can use this as a reload reg. */
5600 /* Mark the register as in use for this part of
5602 mark_reload_reg_in_use (i,
5606 rld[r].reg_rtx = last_reg;
5607 reload_inherited[r] = 1;
5608 reload_inheritance_insn[r]
5609 = reg_reloaded_insn[i];
5610 reload_spill_index[r] = i;
5611 for (k = 0; k < nr; k++)
5612 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5620 /* Here's another way to see if the value is already lying around. */
5623 && ! reload_inherited[r]
5625 && (CONSTANT_P (rld[r].in)
5626 || GET_CODE (rld[r].in) == PLUS
5627 || GET_CODE (rld[r].in) == REG
5628 || GET_CODE (rld[r].in) == MEM)
5629 && (rld[r].nregs == max_group_size
5630 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5631 search_equiv = rld[r].in;
5632 /* If this is an output reload from a simple move insn, look
5633 if an equivalence for the input is available. */
5634 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5636 rtx set = single_set (insn);
5639 && rtx_equal_p (rld[r].out, SET_DEST (set))
5640 && CONSTANT_P (SET_SRC (set)))
5641 search_equiv = SET_SRC (set);
5647 = find_equiv_reg (search_equiv, insn, rld[r].class,
5648 -1, NULL, 0, rld[r].mode);
5653 if (GET_CODE (equiv) == REG)
5654 regno = REGNO (equiv);
5655 else if (GET_CODE (equiv) == SUBREG)
5657 /* This must be a SUBREG of a hard register.
5658 Make a new REG since this might be used in an
5659 address and not all machines support SUBREGs
5661 regno = subreg_regno (equiv);
5662 equiv = gen_rtx_REG (rld[r].mode, regno);
5668 /* If we found a spill reg, reject it unless it is free
5669 and of the desired class. */
5671 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5672 && ! free_for_value_p (regno, rld[r].mode,
5673 rld[r].opnum, rld[r].when_needed,
5674 rld[r].in, rld[r].out, r, 1))
5675 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5679 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5682 /* We found a register that contains the value we need.
5683 If this register is the same as an `earlyclobber' operand
5684 of the current insn, just mark it as a place to reload from
5685 since we can't use it as the reload register itself. */
5688 for (i = 0; i < n_earlyclobbers; i++)
5689 if (reg_overlap_mentioned_for_reload_p (equiv,
5690 reload_earlyclobbers[i]))
5692 if (! rld[r].optional)
5693 reload_override_in[r] = equiv;
5698 /* If the equiv register we have found is explicitly clobbered
5699 in the current insn, it depends on the reload type if we
5700 can use it, use it for reload_override_in, or not at all.
5701 In particular, we then can't use EQUIV for a
5702 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5706 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5707 switch (rld[r].when_needed)
5709 case RELOAD_FOR_OTHER_ADDRESS:
5710 case RELOAD_FOR_INPADDR_ADDRESS:
5711 case RELOAD_FOR_INPUT_ADDRESS:
5712 case RELOAD_FOR_OPADDR_ADDR:
5715 case RELOAD_FOR_INPUT:
5716 case RELOAD_FOR_OPERAND_ADDRESS:
5717 if (! rld[r].optional)
5718 reload_override_in[r] = equiv;
5724 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5725 switch (rld[r].when_needed)
5727 case RELOAD_FOR_OTHER_ADDRESS:
5728 case RELOAD_FOR_INPADDR_ADDRESS:
5729 case RELOAD_FOR_INPUT_ADDRESS:
5730 case RELOAD_FOR_OPADDR_ADDR:
5731 case RELOAD_FOR_OPERAND_ADDRESS:
5732 case RELOAD_FOR_INPUT:
5735 if (! rld[r].optional)
5736 reload_override_in[r] = equiv;
5744 /* If we found an equivalent reg, say no code need be generated
5745 to load it, and use it as our reload reg. */
5747 && (regno != HARD_FRAME_POINTER_REGNUM
5748 || !frame_pointer_needed))
5750 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5752 rld[r].reg_rtx = equiv;
5753 reload_inherited[r] = 1;
5755 /* If reg_reloaded_valid is not set for this register,
5756 there might be a stale spill_reg_store lying around.
5757 We must clear it, since otherwise emit_reload_insns
5758 might delete the store. */
5759 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5760 spill_reg_store[regno] = NULL_RTX;
5761 /* If any of the hard registers in EQUIV are spill
5762 registers, mark them as in use for this insn. */
5763 for (k = 0; k < nr; k++)
5765 i = spill_reg_order[regno + k];
5768 mark_reload_reg_in_use (regno, rld[r].opnum,
5771 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5778 /* If we found a register to use already, or if this is an optional
5779 reload, we are done. */
5780 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5784 /* No longer needed for correct operation. Might or might
5785 not give better code on the average. Want to experiment? */
5787 /* See if there is a later reload that has a class different from our
5788 class that intersects our class or that requires less register
5789 than our reload. If so, we must allocate a register to this
5790 reload now, since that reload might inherit a previous reload
5791 and take the only available register in our class. Don't do this
5792 for optional reloads since they will force all previous reloads
5793 to be allocated. Also don't do this for reloads that have been
5796 for (i = j + 1; i < n_reloads; i++)
5798 int s = reload_order[i];
5800 if ((rld[s].in == 0 && rld[s].out == 0
5801 && ! rld[s].secondary_p)
5805 if ((rld[s].class != rld[r].class
5806 && reg_classes_intersect_p (rld[r].class,
5808 || rld[s].nregs < rld[r].nregs)
5815 allocate_reload_reg (chain, r, j == n_reloads - 1);
5819 /* Now allocate reload registers for anything non-optional that
5820 didn't get one yet. */
5821 for (j = 0; j < n_reloads; j++)
5823 int r = reload_order[j];
5825 /* Ignore reloads that got marked inoperative. */
5826 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5829 /* Skip reloads that already have a register allocated or are
5831 if (rld[r].reg_rtx != 0 || rld[r].optional)
5834 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5838 /* If that loop got all the way, we have won. */
5845 /* Loop around and try without any inheritance. */
5850 /* First undo everything done by the failed attempt
5851 to allocate with inheritance. */
5852 choose_reload_regs_init (chain, save_reload_reg_rtx);
5854 /* Some sanity tests to verify that the reloads found in the first
5855 pass are identical to the ones we have now. */
5856 if (chain->n_reloads != n_reloads)
5859 for (i = 0; i < n_reloads; i++)
5861 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5863 if (chain->rld[i].when_needed != rld[i].when_needed)
5865 for (j = 0; j < n_spills; j++)
5866 if (spill_regs[j] == chain->rld[i].regno)
5867 if (! set_reload_reg (j, i))
5868 failed_reload (chain->insn, i);
5872 /* If we thought we could inherit a reload, because it seemed that
5873 nothing else wanted the same reload register earlier in the insn,
5874 verify that assumption, now that all reloads have been assigned.
5875 Likewise for reloads where reload_override_in has been set. */
5877 /* If doing expensive optimizations, do one preliminary pass that doesn't
5878 cancel any inheritance, but removes reloads that have been needed only
5879 for reloads that we know can be inherited. */
5880 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5882 for (j = 0; j < n_reloads; j++)
5884 int r = reload_order[j];
5886 if (reload_inherited[r] && rld[r].reg_rtx)
5887 check_reg = rld[r].reg_rtx;
5888 else if (reload_override_in[r]
5889 && (GET_CODE (reload_override_in[r]) == REG
5890 || GET_CODE (reload_override_in[r]) == SUBREG))
5891 check_reg = reload_override_in[r];
5894 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5895 rld[r].opnum, rld[r].when_needed, rld[r].in,
5896 (reload_inherited[r]
5897 ? rld[r].out : const0_rtx),
5902 reload_inherited[r] = 0;
5903 reload_override_in[r] = 0;
5905 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5906 reload_override_in, then we do not need its related
5907 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5908 likewise for other reload types.
5909 We handle this by removing a reload when its only replacement
5910 is mentioned in reload_in of the reload we are going to inherit.
5911 A special case are auto_inc expressions; even if the input is
5912 inherited, we still need the address for the output. We can
5913 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5914 If we succeeded removing some reload and we are doing a preliminary
5915 pass just to remove such reloads, make another pass, since the
5916 removal of one reload might allow us to inherit another one. */
5918 && rld[r].out != rld[r].in
5919 && remove_address_replacements (rld[r].in) && pass)
5924 /* Now that reload_override_in is known valid,
5925 actually override reload_in. */
5926 for (j = 0; j < n_reloads; j++)
5927 if (reload_override_in[j])
5928 rld[j].in = reload_override_in[j];
5930 /* If this reload won't be done because it has been cancelled or is
5931 optional and not inherited, clear reload_reg_rtx so other
5932 routines (such as subst_reloads) don't get confused. */
5933 for (j = 0; j < n_reloads; j++)
5934 if (rld[j].reg_rtx != 0
5935 && ((rld[j].optional && ! reload_inherited[j])
5936 || (rld[j].in == 0 && rld[j].out == 0
5937 && ! rld[j].secondary_p)))
5939 int regno = true_regnum (rld[j].reg_rtx);
5941 if (spill_reg_order[regno] >= 0)
5942 clear_reload_reg_in_use (regno, rld[j].opnum,
5943 rld[j].when_needed, rld[j].mode);
5945 reload_spill_index[j] = -1;
5948 /* Record which pseudos and which spill regs have output reloads. */
5949 for (j = 0; j < n_reloads; j++)
5951 int r = reload_order[j];
5953 i = reload_spill_index[r];
5955 /* I is nonneg if this reload uses a register.
5956 If rld[r].reg_rtx is 0, this is an optional reload
5957 that we opted to ignore. */
5958 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5959 && rld[r].reg_rtx != 0)
5961 int nregno = REGNO (rld[r].out_reg);
5964 if (nregno < FIRST_PSEUDO_REGISTER)
5965 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5968 reg_has_output_reload[nregno + nr] = 1;
5972 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5974 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5977 if (rld[r].when_needed != RELOAD_OTHER
5978 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5979 && rld[r].when_needed != RELOAD_FOR_INSN)
5985 /* Deallocate the reload register for reload R. This is called from
5986 remove_address_replacements. */
5989 deallocate_reload_reg (r)
5994 if (! rld[r].reg_rtx)
5996 regno = true_regnum (rld[r].reg_rtx);
5998 if (spill_reg_order[regno] >= 0)
5999 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6001 reload_spill_index[r] = -1;
6004 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6005 reloads of the same item for fear that we might not have enough reload
6006 registers. However, normally they will get the same reload register
6007 and hence actually need not be loaded twice.
6009 Here we check for the most common case of this phenomenon: when we have
6010 a number of reloads for the same object, each of which were allocated
6011 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6012 reload, and is not modified in the insn itself. If we find such,
6013 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6014 This will not increase the number of spill registers needed and will
6015 prevent redundant code. */
6018 merge_assigned_reloads (insn)
6023 /* Scan all the reloads looking for ones that only load values and
6024 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6025 assigned and not modified by INSN. */
6027 for (i = 0; i < n_reloads; i++)
6029 int conflicting_input = 0;
6030 int max_input_address_opnum = -1;
6031 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6033 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6034 || rld[i].out != 0 || rld[i].reg_rtx == 0
6035 || reg_set_p (rld[i].reg_rtx, insn))
6038 /* Look at all other reloads. Ensure that the only use of this
6039 reload_reg_rtx is in a reload that just loads the same value
6040 as we do. Note that any secondary reloads must be of the identical
6041 class since the values, modes, and result registers are the
6042 same, so we need not do anything with any secondary reloads. */
6044 for (j = 0; j < n_reloads; j++)
6046 if (i == j || rld[j].reg_rtx == 0
6047 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6051 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6052 && rld[j].opnum > max_input_address_opnum)
6053 max_input_address_opnum = rld[j].opnum;
6055 /* If the reload regs aren't exactly the same (e.g, different modes)
6056 or if the values are different, we can't merge this reload.
6057 But if it is an input reload, we might still merge
6058 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6060 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6061 || rld[j].out != 0 || rld[j].in == 0
6062 || ! rtx_equal_p (rld[i].in, rld[j].in))
6064 if (rld[j].when_needed != RELOAD_FOR_INPUT
6065 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6066 || rld[i].opnum > rld[j].opnum)
6067 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6069 conflicting_input = 1;
6070 if (min_conflicting_input_opnum > rld[j].opnum)
6071 min_conflicting_input_opnum = rld[j].opnum;
6075 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6076 we, in fact, found any matching reloads. */
6079 && max_input_address_opnum <= min_conflicting_input_opnum)
6081 for (j = 0; j < n_reloads; j++)
6082 if (i != j && rld[j].reg_rtx != 0
6083 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6084 && (! conflicting_input
6085 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6086 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6088 rld[i].when_needed = RELOAD_OTHER;
6090 reload_spill_index[j] = -1;
6091 transfer_replacements (i, j);
6094 /* If this is now RELOAD_OTHER, look for any reloads that load
6095 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6096 if they were for inputs, RELOAD_OTHER for outputs. Note that
6097 this test is equivalent to looking for reloads for this operand
6100 if (rld[i].when_needed == RELOAD_OTHER)
6101 for (j = 0; j < n_reloads; j++)
6103 && rld[j].when_needed != RELOAD_OTHER
6104 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6107 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6108 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6109 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6114 /* These arrays are filled by emit_reload_insns and its subroutines. */
6115 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6116 static rtx other_input_address_reload_insns = 0;
6117 static rtx other_input_reload_insns = 0;
6118 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6119 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6120 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6121 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6122 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6123 static rtx operand_reload_insns = 0;
6124 static rtx other_operand_reload_insns = 0;
6125 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6127 /* Values to be put in spill_reg_store are put here first. */
6128 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6129 static HARD_REG_SET reg_reloaded_died;
6131 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6132 has the number J. OLD contains the value to be used as input. */
6135 emit_input_reload_insns (chain, rl, old, j)
6136 struct insn_chain *chain;
6141 rtx insn = chain->insn;
6142 rtx reloadreg = rl->reg_rtx;
6143 rtx oldequiv_reg = 0;
6146 enum machine_mode mode;
6149 /* Determine the mode to reload in.
6150 This is very tricky because we have three to choose from.
6151 There is the mode the insn operand wants (rl->inmode).
6152 There is the mode of the reload register RELOADREG.
6153 There is the intrinsic mode of the operand, which we could find
6154 by stripping some SUBREGs.
6155 It turns out that RELOADREG's mode is irrelevant:
6156 we can change that arbitrarily.
6158 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6159 then the reload reg may not support QImode moves, so use SImode.
6160 If foo is in memory due to spilling a pseudo reg, this is safe,
6161 because the QImode value is in the least significant part of a
6162 slot big enough for a SImode. If foo is some other sort of
6163 memory reference, then it is impossible to reload this case,
6164 so previous passes had better make sure this never happens.
6166 Then consider a one-word union which has SImode and one of its
6167 members is a float, being fetched as (SUBREG:SF union:SI).
6168 We must fetch that as SFmode because we could be loading into
6169 a float-only register. In this case OLD's mode is correct.
6171 Consider an immediate integer: it has VOIDmode. Here we need
6172 to get a mode from something else.
6174 In some cases, there is a fourth mode, the operand's
6175 containing mode. If the insn specifies a containing mode for
6176 this operand, it overrides all others.
6178 I am not sure whether the algorithm here is always right,
6179 but it does the right things in those cases. */
6181 mode = GET_MODE (old);
6182 if (mode == VOIDmode)
6185 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6186 /* If we need a secondary register for this operation, see if
6187 the value is already in a register in that class. Don't
6188 do this if the secondary register will be used as a scratch
6191 if (rl->secondary_in_reload >= 0
6192 && rl->secondary_in_icode == CODE_FOR_nothing
6195 = find_equiv_reg (old, insn,
6196 rld[rl->secondary_in_reload].class,
6200 /* If reloading from memory, see if there is a register
6201 that already holds the same value. If so, reload from there.
6202 We can pass 0 as the reload_reg_p argument because
6203 any other reload has either already been emitted,
6204 in which case find_equiv_reg will see the reload-insn,
6205 or has yet to be emitted, in which case it doesn't matter
6206 because we will use this equiv reg right away. */
6208 if (oldequiv == 0 && optimize
6209 && (GET_CODE (old) == MEM
6210 || (GET_CODE (old) == REG
6211 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6212 && reg_renumber[REGNO (old)] < 0)))
6213 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6217 unsigned int regno = true_regnum (oldequiv);
6219 /* Don't use OLDEQUIV if any other reload changes it at an
6220 earlier stage of this insn or at this stage. */
6221 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6222 rl->in, const0_rtx, j, 0))
6225 /* If it is no cheaper to copy from OLDEQUIV into the
6226 reload register than it would be to move from memory,
6227 don't use it. Likewise, if we need a secondary register
6231 && ((REGNO_REG_CLASS (regno) != rl->class
6232 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6234 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6235 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6236 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6240 #ifdef SECONDARY_MEMORY_NEEDED
6241 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6249 /* delete_output_reload is only invoked properly if old contains
6250 the original pseudo register. Since this is replaced with a
6251 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6252 find the pseudo in RELOAD_IN_REG. */
6254 && reload_override_in[j]
6255 && GET_CODE (rl->in_reg) == REG)
6262 else if (GET_CODE (oldequiv) == REG)
6263 oldequiv_reg = oldequiv;
6264 else if (GET_CODE (oldequiv) == SUBREG)
6265 oldequiv_reg = SUBREG_REG (oldequiv);
6267 /* If we are reloading from a register that was recently stored in
6268 with an output-reload, see if we can prove there was
6269 actually no need to store the old value in it. */
6271 if (optimize && GET_CODE (oldequiv) == REG
6272 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6273 && spill_reg_store[REGNO (oldequiv)]
6274 && GET_CODE (old) == REG
6275 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6276 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6278 delete_output_reload (insn, j, REGNO (oldequiv));
6280 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6281 then load RELOADREG from OLDEQUIV. Note that we cannot use
6282 gen_lowpart_common since it can do the wrong thing when
6283 RELOADREG has a multi-word mode. Note that RELOADREG
6284 must always be a REG here. */
6286 if (GET_MODE (reloadreg) != mode)
6287 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6288 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6289 oldequiv = SUBREG_REG (oldequiv);
6290 if (GET_MODE (oldequiv) != VOIDmode
6291 && mode != GET_MODE (oldequiv))
6292 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6294 /* Switch to the right place to emit the reload insns. */
6295 switch (rl->when_needed)
6298 where = &other_input_reload_insns;
6300 case RELOAD_FOR_INPUT:
6301 where = &input_reload_insns[rl->opnum];
6303 case RELOAD_FOR_INPUT_ADDRESS:
6304 where = &input_address_reload_insns[rl->opnum];
6306 case RELOAD_FOR_INPADDR_ADDRESS:
6307 where = &inpaddr_address_reload_insns[rl->opnum];
6309 case RELOAD_FOR_OUTPUT_ADDRESS:
6310 where = &output_address_reload_insns[rl->opnum];
6312 case RELOAD_FOR_OUTADDR_ADDRESS:
6313 where = &outaddr_address_reload_insns[rl->opnum];
6315 case RELOAD_FOR_OPERAND_ADDRESS:
6316 where = &operand_reload_insns;
6318 case RELOAD_FOR_OPADDR_ADDR:
6319 where = &other_operand_reload_insns;
6321 case RELOAD_FOR_OTHER_ADDRESS:
6322 where = &other_input_address_reload_insns;
6328 push_to_sequence (*where);
6330 /* Auto-increment addresses must be reloaded in a special way. */
6331 if (rl->out && ! rl->out_reg)
6333 /* We are not going to bother supporting the case where a
6334 incremented register can't be copied directly from
6335 OLDEQUIV since this seems highly unlikely. */
6336 if (rl->secondary_in_reload >= 0)
6339 if (reload_inherited[j])
6340 oldequiv = reloadreg;
6342 old = XEXP (rl->in_reg, 0);
6344 if (optimize && GET_CODE (oldequiv) == REG
6345 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6346 && spill_reg_store[REGNO (oldequiv)]
6347 && GET_CODE (old) == REG
6348 && (dead_or_set_p (insn,
6349 spill_reg_stored_to[REGNO (oldequiv)])
6350 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6352 delete_output_reload (insn, j, REGNO (oldequiv));
6354 /* Prevent normal processing of this reload. */
6356 /* Output a special code sequence for this case. */
6357 new_spill_reg_store[REGNO (reloadreg)]
6358 = inc_for_reload (reloadreg, oldequiv, rl->out,
6362 /* If we are reloading a pseudo-register that was set by the previous
6363 insn, see if we can get rid of that pseudo-register entirely
6364 by redirecting the previous insn into our reload register. */
6366 else if (optimize && GET_CODE (old) == REG
6367 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6368 && dead_or_set_p (insn, old)
6369 /* This is unsafe if some other reload
6370 uses the same reg first. */
6371 && ! conflicts_with_override (reloadreg)
6372 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6373 rl->when_needed, old, rl->out, j, 0))
6375 rtx temp = PREV_INSN (insn);
6376 while (temp && GET_CODE (temp) == NOTE)
6377 temp = PREV_INSN (temp);
6379 && GET_CODE (temp) == INSN
6380 && GET_CODE (PATTERN (temp)) == SET
6381 && SET_DEST (PATTERN (temp)) == old
6382 /* Make sure we can access insn_operand_constraint. */
6383 && asm_noperands (PATTERN (temp)) < 0
6384 /* This is unsafe if operand occurs more than once in current
6385 insn. Perhaps some occurrences aren't reloaded. */
6386 && count_occurrences (PATTERN (insn), old, 0) == 1)
6388 rtx old = SET_DEST (PATTERN (temp));
6389 /* Store into the reload register instead of the pseudo. */
6390 SET_DEST (PATTERN (temp)) = reloadreg;
6392 /* Verify that resulting insn is valid. */
6393 extract_insn (temp);
6394 if (constrain_operands (1))
6396 /* If the previous insn is an output reload, the source is
6397 a reload register, and its spill_reg_store entry will
6398 contain the previous destination. This is now
6400 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6401 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6403 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6404 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6407 /* If these are the only uses of the pseudo reg,
6408 pretend for GDB it lives in the reload reg we used. */
6409 if (REG_N_DEATHS (REGNO (old)) == 1
6410 && REG_N_SETS (REGNO (old)) == 1)
6412 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6413 alter_reg (REGNO (old), -1);
6419 SET_DEST (PATTERN (temp)) = old;
6424 /* We can't do that, so output an insn to load RELOADREG. */
6426 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6427 /* If we have a secondary reload, pick up the secondary register
6428 and icode, if any. If OLDEQUIV and OLD are different or
6429 if this is an in-out reload, recompute whether or not we
6430 still need a secondary register and what the icode should
6431 be. If we still need a secondary register and the class or
6432 icode is different, go back to reloading from OLD if using
6433 OLDEQUIV means that we got the wrong type of register. We
6434 cannot have different class or icode due to an in-out reload
6435 because we don't make such reloads when both the input and
6436 output need secondary reload registers. */
6438 if (! special && rl->secondary_in_reload >= 0)
6440 rtx second_reload_reg = 0;
6441 int secondary_reload = rl->secondary_in_reload;
6442 rtx real_oldequiv = oldequiv;
6445 enum insn_code icode;
6447 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6448 and similarly for OLD.
6449 See comments in get_secondary_reload in reload.c. */
6450 /* If it is a pseudo that cannot be replaced with its
6451 equivalent MEM, we must fall back to reload_in, which
6452 will have all the necessary substitutions registered.
6453 Likewise for a pseudo that can't be replaced with its
6454 equivalent constant.
6456 Take extra care for subregs of such pseudos. Note that
6457 we cannot use reg_equiv_mem in this case because it is
6458 not in the right mode. */
6461 if (GET_CODE (tmp) == SUBREG)
6462 tmp = SUBREG_REG (tmp);
6463 if (GET_CODE (tmp) == REG
6464 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6465 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6466 || reg_equiv_constant[REGNO (tmp)] != 0))
6468 if (! reg_equiv_mem[REGNO (tmp)]
6469 || num_not_at_initial_offset
6470 || GET_CODE (oldequiv) == SUBREG)
6471 real_oldequiv = rl->in;
6473 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6477 if (GET_CODE (tmp) == SUBREG)
6478 tmp = SUBREG_REG (tmp);
6479 if (GET_CODE (tmp) == REG
6480 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6481 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6482 || reg_equiv_constant[REGNO (tmp)] != 0))
6484 if (! reg_equiv_mem[REGNO (tmp)]
6485 || num_not_at_initial_offset
6486 || GET_CODE (old) == SUBREG)
6489 real_old = reg_equiv_mem[REGNO (tmp)];
6492 second_reload_reg = rld[secondary_reload].reg_rtx;
6493 icode = rl->secondary_in_icode;
6495 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6496 || (rl->in != 0 && rl->out != 0))
6498 enum reg_class new_class
6499 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6500 mode, real_oldequiv);
6502 if (new_class == NO_REGS)
6503 second_reload_reg = 0;
6506 enum insn_code new_icode;
6507 enum machine_mode new_mode;
6509 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6510 REGNO (second_reload_reg)))
6511 oldequiv = old, real_oldequiv = real_old;
6514 new_icode = reload_in_optab[(int) mode];
6515 if (new_icode != CODE_FOR_nothing
6516 && ((insn_data[(int) new_icode].operand[0].predicate
6517 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6519 || (insn_data[(int) new_icode].operand[1].predicate
6520 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6521 (real_oldequiv, mode)))))
6522 new_icode = CODE_FOR_nothing;
6524 if (new_icode == CODE_FOR_nothing)
6527 new_mode = insn_data[(int) new_icode].operand[2].mode;
6529 if (GET_MODE (second_reload_reg) != new_mode)
6531 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6533 oldequiv = old, real_oldequiv = real_old;
6536 = gen_rtx_REG (new_mode,
6537 REGNO (second_reload_reg));
6543 /* If we still need a secondary reload register, check
6544 to see if it is being used as a scratch or intermediate
6545 register and generate code appropriately. If we need
6546 a scratch register, use REAL_OLDEQUIV since the form of
6547 the insn may depend on the actual address if it is
6550 if (second_reload_reg)
6552 if (icode != CODE_FOR_nothing)
6554 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6555 second_reload_reg));
6560 /* See if we need a scratch register to load the
6561 intermediate register (a tertiary reload). */
6562 enum insn_code tertiary_icode
6563 = rld[secondary_reload].secondary_in_icode;
6565 if (tertiary_icode != CODE_FOR_nothing)
6567 rtx third_reload_reg
6568 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6570 emit_insn ((GEN_FCN (tertiary_icode)
6571 (second_reload_reg, real_oldequiv,
6572 third_reload_reg)));
6575 gen_reload (second_reload_reg, real_oldequiv,
6579 oldequiv = second_reload_reg;
6585 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6587 rtx real_oldequiv = oldequiv;
6589 if ((GET_CODE (oldequiv) == REG
6590 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6591 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6592 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6593 || (GET_CODE (oldequiv) == SUBREG
6594 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6595 && (REGNO (SUBREG_REG (oldequiv))
6596 >= FIRST_PSEUDO_REGISTER)
6597 && ((reg_equiv_memory_loc
6598 [REGNO (SUBREG_REG (oldequiv))] != 0)
6599 || (reg_equiv_constant
6600 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6601 || (CONSTANT_P (oldequiv)
6602 && (PREFERRED_RELOAD_CLASS (oldequiv,
6603 REGNO_REG_CLASS (REGNO (reloadreg)))
6605 real_oldequiv = rl->in;
6606 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6610 if (flag_non_call_exceptions)
6611 copy_eh_notes (insn, get_insns ());
6613 /* End this sequence. */
6614 *where = get_insns ();
6617 /* Update reload_override_in so that delete_address_reloads_1
6618 can see the actual register usage. */
6620 reload_override_in[j] = oldequiv;
6623 /* Generate insns to for the output reload RL, which is for the insn described
6624 by CHAIN and has the number J. */
6626 emit_output_reload_insns (chain, rl, j)
6627 struct insn_chain *chain;
6631 rtx reloadreg = rl->reg_rtx;
6632 rtx insn = chain->insn;
6635 enum machine_mode mode = GET_MODE (old);
6638 if (rl->when_needed == RELOAD_OTHER)
6641 push_to_sequence (output_reload_insns[rl->opnum]);
6643 /* Determine the mode to reload in.
6644 See comments above (for input reloading). */
6646 if (mode == VOIDmode)
6648 /* VOIDmode should never happen for an output. */
6649 if (asm_noperands (PATTERN (insn)) < 0)
6650 /* It's the compiler's fault. */
6651 fatal_insn ("VOIDmode on an output", insn);
6652 error_for_asm (insn, "output operand is constant in `asm'");
6653 /* Prevent crash--use something we know is valid. */
6655 old = gen_rtx_REG (mode, REGNO (reloadreg));
6658 if (GET_MODE (reloadreg) != mode)
6659 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6661 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6663 /* If we need two reload regs, set RELOADREG to the intermediate
6664 one, since it will be stored into OLD. We might need a secondary
6665 register only for an input reload, so check again here. */
6667 if (rl->secondary_out_reload >= 0)
6671 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6672 && reg_equiv_mem[REGNO (old)] != 0)
6673 real_old = reg_equiv_mem[REGNO (old)];
6675 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6679 rtx second_reloadreg = reloadreg;
6680 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6682 /* See if RELOADREG is to be used as a scratch register
6683 or as an intermediate register. */
6684 if (rl->secondary_out_icode != CODE_FOR_nothing)
6686 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6687 (real_old, second_reloadreg, reloadreg)));
6692 /* See if we need both a scratch and intermediate reload
6695 int secondary_reload = rl->secondary_out_reload;
6696 enum insn_code tertiary_icode
6697 = rld[secondary_reload].secondary_out_icode;
6699 if (GET_MODE (reloadreg) != mode)
6700 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6702 if (tertiary_icode != CODE_FOR_nothing)
6705 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6708 /* Copy primary reload reg to secondary reload reg.
6709 (Note that these have been swapped above, then
6710 secondary reload reg to OLD using our insn.) */
6712 /* If REAL_OLD is a paradoxical SUBREG, remove it
6713 and try to put the opposite SUBREG on
6715 if (GET_CODE (real_old) == SUBREG
6716 && (GET_MODE_SIZE (GET_MODE (real_old))
6717 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6718 && 0 != (tem = gen_lowpart_common
6719 (GET_MODE (SUBREG_REG (real_old)),
6721 real_old = SUBREG_REG (real_old), reloadreg = tem;
6723 gen_reload (reloadreg, second_reloadreg,
6724 rl->opnum, rl->when_needed);
6725 emit_insn ((GEN_FCN (tertiary_icode)
6726 (real_old, reloadreg, third_reloadreg)));
6731 /* Copy between the reload regs here and then to
6734 gen_reload (reloadreg, second_reloadreg,
6735 rl->opnum, rl->when_needed);
6741 /* Output the last reload insn. */
6746 /* Don't output the last reload if OLD is not the dest of
6747 INSN and is in the src and is clobbered by INSN. */
6748 if (! flag_expensive_optimizations
6749 || GET_CODE (old) != REG
6750 || !(set = single_set (insn))
6751 || rtx_equal_p (old, SET_DEST (set))
6752 || !reg_mentioned_p (old, SET_SRC (set))
6753 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6754 gen_reload (old, reloadreg, rl->opnum,
6758 /* Look at all insns we emitted, just to be safe. */
6759 for (p = get_insns (); p; p = NEXT_INSN (p))
6762 rtx pat = PATTERN (p);
6764 /* If this output reload doesn't come from a spill reg,
6765 clear any memory of reloaded copies of the pseudo reg.
6766 If this output reload comes from a spill reg,
6767 reg_has_output_reload will make this do nothing. */
6768 note_stores (pat, forget_old_reloads_1, NULL);
6770 if (reg_mentioned_p (rl->reg_rtx, pat))
6772 rtx set = single_set (insn);
6773 if (reload_spill_index[j] < 0
6775 && SET_SRC (set) == rl->reg_rtx)
6777 int src = REGNO (SET_SRC (set));
6779 reload_spill_index[j] = src;
6780 SET_HARD_REG_BIT (reg_is_output_reload, src);
6781 if (find_regno_note (insn, REG_DEAD, src))
6782 SET_HARD_REG_BIT (reg_reloaded_died, src);
6784 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6786 int s = rl->secondary_out_reload;
6787 set = single_set (p);
6788 /* If this reload copies only to the secondary reload
6789 register, the secondary reload does the actual
6791 if (s >= 0 && set == NULL_RTX)
6792 /* We can't tell what function the secondary reload
6793 has and where the actual store to the pseudo is
6794 made; leave new_spill_reg_store alone. */
6797 && SET_SRC (set) == rl->reg_rtx
6798 && SET_DEST (set) == rld[s].reg_rtx)
6800 /* Usually the next instruction will be the
6801 secondary reload insn; if we can confirm
6802 that it is, setting new_spill_reg_store to
6803 that insn will allow an extra optimization. */
6804 rtx s_reg = rld[s].reg_rtx;
6805 rtx next = NEXT_INSN (p);
6806 rld[s].out = rl->out;
6807 rld[s].out_reg = rl->out_reg;
6808 set = single_set (next);
6809 if (set && SET_SRC (set) == s_reg
6810 && ! new_spill_reg_store[REGNO (s_reg)])
6812 SET_HARD_REG_BIT (reg_is_output_reload,
6814 new_spill_reg_store[REGNO (s_reg)] = next;
6818 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6823 if (rl->when_needed == RELOAD_OTHER)
6825 emit_insns (other_output_reload_insns[rl->opnum]);
6826 other_output_reload_insns[rl->opnum] = get_insns ();
6829 output_reload_insns[rl->opnum] = get_insns ();
6831 if (flag_non_call_exceptions)
6832 copy_eh_notes (insn, get_insns ());
6837 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6838 and has the number J. */
6840 do_input_reload (chain, rl, j)
6841 struct insn_chain *chain;
6845 int expect_occurrences = 1;
6846 rtx insn = chain->insn;
6847 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6848 ? rl->in_reg : rl->in);
6851 /* AUTO_INC reloads need to be handled even if inherited. We got an
6852 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6853 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6854 && ! rtx_equal_p (rl->reg_rtx, old)
6855 && rl->reg_rtx != 0)
6856 emit_input_reload_insns (chain, rld + j, old, j);
6858 /* When inheriting a wider reload, we have a MEM in rl->in,
6859 e.g. inheriting a SImode output reload for
6860 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6861 if (optimize && reload_inherited[j] && rl->in
6862 && GET_CODE (rl->in) == MEM
6863 && GET_CODE (rl->in_reg) == MEM
6864 && reload_spill_index[j] >= 0
6865 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6868 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6869 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6872 /* If we are reloading a register that was recently stored in with an
6873 output-reload, see if we can prove there was
6874 actually no need to store the old value in it. */
6877 && (reload_inherited[j] || reload_override_in[j])
6879 && GET_CODE (rl->reg_rtx) == REG
6880 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6882 /* There doesn't seem to be any reason to restrict this to pseudos
6883 and doing so loses in the case where we are copying from a
6884 register of the wrong class. */
6885 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6886 >= FIRST_PSEUDO_REGISTER)
6888 /* The insn might have already some references to stackslots
6889 replaced by MEMs, while reload_out_reg still names the
6891 && (dead_or_set_p (insn,
6892 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6893 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6895 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6898 /* Do output reloading for reload RL, which is for the insn described by
6899 CHAIN and has the number J.
6900 ??? At some point we need to support handling output reloads of
6901 JUMP_INSNs or insns that set cc0. */
6903 do_output_reload (chain, rl, j)
6904 struct insn_chain *chain;
6909 rtx insn = chain->insn;
6910 /* If this is an output reload that stores something that is
6911 not loaded in this same reload, see if we can eliminate a previous
6913 rtx pseudo = rl->out_reg;
6917 && GET_CODE (pseudo) == REG
6918 && ! rtx_equal_p (rl->in_reg, pseudo)
6919 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6920 && reg_last_reload_reg[REGNO (pseudo)])
6922 int pseudo_no = REGNO (pseudo);
6923 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6925 /* We don't need to test full validity of last_regno for
6926 inherit here; we only want to know if the store actually
6927 matches the pseudo. */
6928 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6929 && reg_reloaded_contents[last_regno] == pseudo_no
6930 && spill_reg_store[last_regno]
6931 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6932 delete_output_reload (insn, j, last_regno);
6937 || rl->reg_rtx == old
6938 || rl->reg_rtx == 0)
6941 /* An output operand that dies right away does need a reload,
6942 but need not be copied from it. Show the new location in the
6944 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6945 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6947 XEXP (note, 0) = rl->reg_rtx;
6950 /* Likewise for a SUBREG of an operand that dies. */
6951 else if (GET_CODE (old) == SUBREG
6952 && GET_CODE (SUBREG_REG (old)) == REG
6953 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6956 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6960 else if (GET_CODE (old) == SCRATCH)
6961 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6962 but we don't want to make an output reload. */
6965 /* If is a JUMP_INSN, we can't support output reloads yet. */
6966 if (GET_CODE (insn) == JUMP_INSN)
6969 emit_output_reload_insns (chain, rld + j, j);
6972 /* Output insns to reload values in and out of the chosen reload regs. */
6975 emit_reload_insns (chain)
6976 struct insn_chain *chain;
6978 rtx insn = chain->insn;
6982 CLEAR_HARD_REG_SET (reg_reloaded_died);
6984 for (j = 0; j < reload_n_operands; j++)
6985 input_reload_insns[j] = input_address_reload_insns[j]
6986 = inpaddr_address_reload_insns[j]
6987 = output_reload_insns[j] = output_address_reload_insns[j]
6988 = outaddr_address_reload_insns[j]
6989 = other_output_reload_insns[j] = 0;
6990 other_input_address_reload_insns = 0;
6991 other_input_reload_insns = 0;
6992 operand_reload_insns = 0;
6993 other_operand_reload_insns = 0;
6995 /* Dump reloads into the dump file. */
6998 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6999 debug_reload_to_stream (rtl_dump_file);
7002 /* Now output the instructions to copy the data into and out of the
7003 reload registers. Do these in the order that the reloads were reported,
7004 since reloads of base and index registers precede reloads of operands
7005 and the operands may need the base and index registers reloaded. */
7007 for (j = 0; j < n_reloads; j++)
7010 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7011 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7013 do_input_reload (chain, rld + j, j);
7014 do_output_reload (chain, rld + j, j);
7017 /* Now write all the insns we made for reloads in the order expected by
7018 the allocation functions. Prior to the insn being reloaded, we write
7019 the following reloads:
7021 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7023 RELOAD_OTHER reloads.
7025 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7026 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7027 RELOAD_FOR_INPUT reload for the operand.
7029 RELOAD_FOR_OPADDR_ADDRS reloads.
7031 RELOAD_FOR_OPERAND_ADDRESS reloads.
7033 After the insn being reloaded, we write the following:
7035 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7036 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7037 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7038 reloads for the operand. The RELOAD_OTHER output reloads are
7039 output in descending order by reload number. */
7041 emit_insns_before (other_input_address_reload_insns, insn);
7042 emit_insns_before (other_input_reload_insns, insn);
7044 for (j = 0; j < reload_n_operands; j++)
7046 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7047 emit_insns_before (input_address_reload_insns[j], insn);
7048 emit_insns_before (input_reload_insns[j], insn);
7051 emit_insns_before (other_operand_reload_insns, insn);
7052 emit_insns_before (operand_reload_insns, insn);
7054 for (j = 0; j < reload_n_operands; j++)
7056 rtx x = emit_insns_after (outaddr_address_reload_insns[j], insn);
7057 x = emit_insns_after (output_address_reload_insns[j], x);
7058 x = emit_insns_after (output_reload_insns[j], x);
7059 emit_insns_after (other_output_reload_insns[j], x);
7062 /* For all the spill regs newly reloaded in this instruction,
7063 record what they were reloaded from, so subsequent instructions
7064 can inherit the reloads.
7066 Update spill_reg_store for the reloads of this insn.
7067 Copy the elements that were updated in the loop above. */
7069 for (j = 0; j < n_reloads; j++)
7071 int r = reload_order[j];
7072 int i = reload_spill_index[r];
7074 /* If this is a non-inherited input reload from a pseudo, we must
7075 clear any memory of a previous store to the same pseudo. Only do
7076 something if there will not be an output reload for the pseudo
7078 if (rld[r].in_reg != 0
7079 && ! (reload_inherited[r] || reload_override_in[r]))
7081 rtx reg = rld[r].in_reg;
7083 if (GET_CODE (reg) == SUBREG)
7084 reg = SUBREG_REG (reg);
7086 if (GET_CODE (reg) == REG
7087 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7088 && ! reg_has_output_reload[REGNO (reg)])
7090 int nregno = REGNO (reg);
7092 if (reg_last_reload_reg[nregno])
7094 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7096 if (reg_reloaded_contents[last_regno] == nregno)
7097 spill_reg_store[last_regno] = 0;
7102 /* I is nonneg if this reload used a register.
7103 If rld[r].reg_rtx is 0, this is an optional reload
7104 that we opted to ignore. */
7106 if (i >= 0 && rld[r].reg_rtx != 0)
7108 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7110 int part_reaches_end = 0;
7111 int all_reaches_end = 1;
7113 /* For a multi register reload, we need to check if all or part
7114 of the value lives to the end. */
7115 for (k = 0; k < nr; k++)
7117 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7118 rld[r].when_needed))
7119 part_reaches_end = 1;
7121 all_reaches_end = 0;
7124 /* Ignore reloads that don't reach the end of the insn in
7126 if (all_reaches_end)
7128 /* First, clear out memory of what used to be in this spill reg.
7129 If consecutive registers are used, clear them all. */
7131 for (k = 0; k < nr; k++)
7132 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7134 /* Maybe the spill reg contains a copy of reload_out. */
7136 && (GET_CODE (rld[r].out) == REG
7140 || GET_CODE (rld[r].out_reg) == REG))
7142 rtx out = (GET_CODE (rld[r].out) == REG
7146 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7147 int nregno = REGNO (out);
7148 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7149 : HARD_REGNO_NREGS (nregno,
7150 GET_MODE (rld[r].reg_rtx)));
7152 spill_reg_store[i] = new_spill_reg_store[i];
7153 spill_reg_stored_to[i] = out;
7154 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7156 /* If NREGNO is a hard register, it may occupy more than
7157 one register. If it does, say what is in the
7158 rest of the registers assuming that both registers
7159 agree on how many words the object takes. If not,
7160 invalidate the subsequent registers. */
7162 if (nregno < FIRST_PSEUDO_REGISTER)
7163 for (k = 1; k < nnr; k++)
7164 reg_last_reload_reg[nregno + k]
7166 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7169 /* Now do the inverse operation. */
7170 for (k = 0; k < nr; k++)
7172 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7173 reg_reloaded_contents[i + k]
7174 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7177 reg_reloaded_insn[i + k] = insn;
7178 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7182 /* Maybe the spill reg contains a copy of reload_in. Only do
7183 something if there will not be an output reload for
7184 the register being reloaded. */
7185 else if (rld[r].out_reg == 0
7187 && ((GET_CODE (rld[r].in) == REG
7188 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7189 && ! reg_has_output_reload[REGNO (rld[r].in)])
7190 || (GET_CODE (rld[r].in_reg) == REG
7191 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7192 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7197 if (GET_CODE (rld[r].in) == REG
7198 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7199 nregno = REGNO (rld[r].in);
7200 else if (GET_CODE (rld[r].in_reg) == REG)
7201 nregno = REGNO (rld[r].in_reg);
7203 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7205 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7206 : HARD_REGNO_NREGS (nregno,
7207 GET_MODE (rld[r].reg_rtx)));
7209 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7211 if (nregno < FIRST_PSEUDO_REGISTER)
7212 for (k = 1; k < nnr; k++)
7213 reg_last_reload_reg[nregno + k]
7215 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7218 /* Unless we inherited this reload, show we haven't
7219 recently done a store.
7220 Previous stores of inherited auto_inc expressions
7221 also have to be discarded. */
7222 if (! reload_inherited[r]
7223 || (rld[r].out && ! rld[r].out_reg))
7224 spill_reg_store[i] = 0;
7226 for (k = 0; k < nr; k++)
7228 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7229 reg_reloaded_contents[i + k]
7230 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7233 reg_reloaded_insn[i + k] = insn;
7234 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7239 /* However, if part of the reload reaches the end, then we must
7240 invalidate the old info for the part that survives to the end. */
7241 else if (part_reaches_end)
7243 for (k = 0; k < nr; k++)
7244 if (reload_reg_reaches_end_p (i + k,
7246 rld[r].when_needed))
7247 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7251 /* The following if-statement was #if 0'd in 1.34 (or before...).
7252 It's reenabled in 1.35 because supposedly nothing else
7253 deals with this problem. */
7255 /* If a register gets output-reloaded from a non-spill register,
7256 that invalidates any previous reloaded copy of it.
7257 But forget_old_reloads_1 won't get to see it, because
7258 it thinks only about the original insn. So invalidate it here. */
7259 if (i < 0 && rld[r].out != 0
7260 && (GET_CODE (rld[r].out) == REG
7261 || (GET_CODE (rld[r].out) == MEM
7262 && GET_CODE (rld[r].out_reg) == REG)))
7264 rtx out = (GET_CODE (rld[r].out) == REG
7265 ? rld[r].out : rld[r].out_reg);
7266 int nregno = REGNO (out);
7267 if (nregno >= FIRST_PSEUDO_REGISTER)
7269 rtx src_reg, store_insn = NULL_RTX;
7271 reg_last_reload_reg[nregno] = 0;
7273 /* If we can find a hard register that is stored, record
7274 the storing insn so that we may delete this insn with
7275 delete_output_reload. */
7276 src_reg = rld[r].reg_rtx;
7278 /* If this is an optional reload, try to find the source reg
7279 from an input reload. */
7282 rtx set = single_set (insn);
7283 if (set && SET_DEST (set) == rld[r].out)
7287 src_reg = SET_SRC (set);
7289 for (k = 0; k < n_reloads; k++)
7291 if (rld[k].in == src_reg)
7293 src_reg = rld[k].reg_rtx;
7300 store_insn = new_spill_reg_store[REGNO (src_reg)];
7301 if (src_reg && GET_CODE (src_reg) == REG
7302 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7304 int src_regno = REGNO (src_reg);
7305 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7306 /* The place where to find a death note varies with
7307 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7308 necessarily checked exactly in the code that moves
7309 notes, so just check both locations. */
7310 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7311 if (! note && store_insn)
7312 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7315 spill_reg_store[src_regno + nr] = store_insn;
7316 spill_reg_stored_to[src_regno + nr] = out;
7317 reg_reloaded_contents[src_regno + nr] = nregno;
7318 reg_reloaded_insn[src_regno + nr] = store_insn;
7319 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7320 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7321 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7323 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7325 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7327 reg_last_reload_reg[nregno] = src_reg;
7332 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7334 while (num_regs-- > 0)
7335 reg_last_reload_reg[nregno + num_regs] = 0;
7339 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7342 /* Emit code to perform a reload from IN (which may be a reload register) to
7343 OUT (which may also be a reload register). IN or OUT is from operand
7344 OPNUM with reload type TYPE.
7346 Returns first insn emitted. */
7349 gen_reload (out, in, opnum, type)
7353 enum reload_type type;
7355 rtx last = get_last_insn ();
7358 /* If IN is a paradoxical SUBREG, remove it and try to put the
7359 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7360 if (GET_CODE (in) == SUBREG
7361 && (GET_MODE_SIZE (GET_MODE (in))
7362 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7363 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7364 in = SUBREG_REG (in), out = tem;
7365 else if (GET_CODE (out) == SUBREG
7366 && (GET_MODE_SIZE (GET_MODE (out))
7367 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7368 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7369 out = SUBREG_REG (out), in = tem;
7371 /* How to do this reload can get quite tricky. Normally, we are being
7372 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7373 register that didn't get a hard register. In that case we can just
7374 call emit_move_insn.
7376 We can also be asked to reload a PLUS that adds a register or a MEM to
7377 another register, constant or MEM. This can occur during frame pointer
7378 elimination and while reloading addresses. This case is handled by
7379 trying to emit a single insn to perform the add. If it is not valid,
7380 we use a two insn sequence.
7382 Finally, we could be called to handle an 'o' constraint by putting
7383 an address into a register. In that case, we first try to do this
7384 with a named pattern of "reload_load_address". If no such pattern
7385 exists, we just emit a SET insn and hope for the best (it will normally
7386 be valid on machines that use 'o').
7388 This entire process is made complex because reload will never
7389 process the insns we generate here and so we must ensure that
7390 they will fit their constraints and also by the fact that parts of
7391 IN might be being reloaded separately and replaced with spill registers.
7392 Because of this, we are, in some sense, just guessing the right approach
7393 here. The one listed above seems to work.
7395 ??? At some point, this whole thing needs to be rethought. */
7397 if (GET_CODE (in) == PLUS
7398 && (GET_CODE (XEXP (in, 0)) == REG
7399 || GET_CODE (XEXP (in, 0)) == SUBREG
7400 || GET_CODE (XEXP (in, 0)) == MEM)
7401 && (GET_CODE (XEXP (in, 1)) == REG
7402 || GET_CODE (XEXP (in, 1)) == SUBREG
7403 || CONSTANT_P (XEXP (in, 1))
7404 || GET_CODE (XEXP (in, 1)) == MEM))
7406 /* We need to compute the sum of a register or a MEM and another
7407 register, constant, or MEM, and put it into the reload
7408 register. The best possible way of doing this is if the machine
7409 has a three-operand ADD insn that accepts the required operands.
7411 The simplest approach is to try to generate such an insn and see if it
7412 is recognized and matches its constraints. If so, it can be used.
7414 It might be better not to actually emit the insn unless it is valid,
7415 but we need to pass the insn as an operand to `recog' and
7416 `extract_insn' and it is simpler to emit and then delete the insn if
7417 not valid than to dummy things up. */
7419 rtx op0, op1, tem, insn;
7422 op0 = find_replacement (&XEXP (in, 0));
7423 op1 = find_replacement (&XEXP (in, 1));
7425 /* Since constraint checking is strict, commutativity won't be
7426 checked, so we need to do that here to avoid spurious failure
7427 if the add instruction is two-address and the second operand
7428 of the add is the same as the reload reg, which is frequently
7429 the case. If the insn would be A = B + A, rearrange it so
7430 it will be A = A + B as constrain_operands expects. */
7432 if (GET_CODE (XEXP (in, 1)) == REG
7433 && REGNO (out) == REGNO (XEXP (in, 1)))
7434 tem = op0, op0 = op1, op1 = tem;
7436 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7437 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7439 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7440 code = recog_memoized (insn);
7444 extract_insn (insn);
7445 /* We want constrain operands to treat this insn strictly in
7446 its validity determination, i.e., the way it would after reload
7448 if (constrain_operands (1))
7452 delete_insns_since (last);
7454 /* If that failed, we must use a conservative two-insn sequence.
7456 Use a move to copy one operand into the reload register. Prefer
7457 to reload a constant, MEM or pseudo since the move patterns can
7458 handle an arbitrary operand. If OP1 is not a constant, MEM or
7459 pseudo and OP1 is not a valid operand for an add instruction, then
7462 After reloading one of the operands into the reload register, add
7463 the reload register to the output register.
7465 If there is another way to do this for a specific machine, a
7466 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7469 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7471 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7472 || (GET_CODE (op1) == REG
7473 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7474 || (code != CODE_FOR_nothing
7475 && ! ((*insn_data[code].operand[2].predicate)
7476 (op1, insn_data[code].operand[2].mode))))
7477 tem = op0, op0 = op1, op1 = tem;
7479 gen_reload (out, op0, opnum, type);
7481 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7482 This fixes a problem on the 32K where the stack pointer cannot
7483 be used as an operand of an add insn. */
7485 if (rtx_equal_p (op0, op1))
7488 insn = emit_insn (gen_add2_insn (out, op1));
7490 /* If that failed, copy the address register to the reload register.
7491 Then add the constant to the reload register. */
7493 code = recog_memoized (insn);
7497 extract_insn (insn);
7498 /* We want constrain operands to treat this insn strictly in
7499 its validity determination, i.e., the way it would after reload
7501 if (constrain_operands (1))
7503 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7505 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7510 delete_insns_since (last);
7512 gen_reload (out, op1, opnum, type);
7513 insn = emit_insn (gen_add2_insn (out, op0));
7514 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7517 #ifdef SECONDARY_MEMORY_NEEDED
7518 /* If we need a memory location to do the move, do it that way. */
7519 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7520 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7521 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7522 REGNO_REG_CLASS (REGNO (out)),
7525 /* Get the memory to use and rewrite both registers to its mode. */
7526 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7528 if (GET_MODE (loc) != GET_MODE (out))
7529 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7531 if (GET_MODE (loc) != GET_MODE (in))
7532 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7534 gen_reload (loc, in, opnum, type);
7535 gen_reload (out, loc, opnum, type);
7539 /* If IN is a simple operand, use gen_move_insn. */
7540 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7541 emit_insn (gen_move_insn (out, in));
7543 #ifdef HAVE_reload_load_address
7544 else if (HAVE_reload_load_address)
7545 emit_insn (gen_reload_load_address (out, in));
7548 /* Otherwise, just write (set OUT IN) and hope for the best. */
7550 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7552 /* Return the first insn emitted.
7553 We can not just return get_last_insn, because there may have
7554 been multiple instructions emitted. Also note that gen_move_insn may
7555 emit more than one insn itself, so we can not assume that there is one
7556 insn emitted per emit_insn_before call. */
7558 return last ? NEXT_INSN (last) : get_insns ();
7561 /* Delete a previously made output-reload whose result we now believe
7562 is not needed. First we double-check.
7564 INSN is the insn now being processed.
7565 LAST_RELOAD_REG is the hard register number for which we want to delete
7566 the last output reload.
7567 J is the reload-number that originally used REG. The caller has made
7568 certain that reload J doesn't use REG any longer for input. */
7571 delete_output_reload (insn, j, last_reload_reg)
7574 int last_reload_reg;
7576 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7577 rtx reg = spill_reg_stored_to[last_reload_reg];
7580 int n_inherited = 0;
7584 /* Get the raw pseudo-register referred to. */
7586 while (GET_CODE (reg) == SUBREG)
7587 reg = SUBREG_REG (reg);
7588 substed = reg_equiv_memory_loc[REGNO (reg)];
7590 /* This is unsafe if the operand occurs more often in the current
7591 insn than it is inherited. */
7592 for (k = n_reloads - 1; k >= 0; k--)
7594 rtx reg2 = rld[k].in;
7597 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7598 reg2 = rld[k].in_reg;
7600 if (rld[k].out && ! rld[k].out_reg)
7601 reg2 = XEXP (rld[k].in_reg, 0);
7603 while (GET_CODE (reg2) == SUBREG)
7604 reg2 = SUBREG_REG (reg2);
7605 if (rtx_equal_p (reg2, reg))
7607 if (reload_inherited[k] || reload_override_in[k] || k == j)
7610 reg2 = rld[k].out_reg;
7613 while (GET_CODE (reg2) == SUBREG)
7614 reg2 = XEXP (reg2, 0);
7615 if (rtx_equal_p (reg2, reg))
7622 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7624 n_occurrences += count_occurrences (PATTERN (insn),
7625 eliminate_regs (substed, 0,
7627 if (n_occurrences > n_inherited)
7630 /* If the pseudo-reg we are reloading is no longer referenced
7631 anywhere between the store into it and here,
7632 and no jumps or labels intervene, then the value can get
7633 here through the reload reg alone.
7634 Otherwise, give up--return. */
7635 for (i1 = NEXT_INSN (output_reload_insn);
7636 i1 != insn; i1 = NEXT_INSN (i1))
7638 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7640 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7641 && reg_mentioned_p (reg, PATTERN (i1)))
7643 /* If this is USE in front of INSN, we only have to check that
7644 there are no more references than accounted for by inheritance. */
7645 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7647 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7648 i1 = NEXT_INSN (i1);
7650 if (n_occurrences <= n_inherited && i1 == insn)
7656 /* We will be deleting the insn. Remove the spill reg information. */
7657 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7659 spill_reg_store[last_reload_reg + k] = 0;
7660 spill_reg_stored_to[last_reload_reg + k] = 0;
7663 /* The caller has already checked that REG dies or is set in INSN.
7664 It has also checked that we are optimizing, and thus some
7665 inaccurancies in the debugging information are acceptable.
7666 So we could just delete output_reload_insn. But in some cases
7667 we can improve the debugging information without sacrificing
7668 optimization - maybe even improving the code: See if the pseudo
7669 reg has been completely replaced with reload regs. If so, delete
7670 the store insn and forget we had a stack slot for the pseudo. */
7671 if (rld[j].out != rld[j].in
7672 && REG_N_DEATHS (REGNO (reg)) == 1
7673 && REG_N_SETS (REGNO (reg)) == 1
7674 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7675 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7679 /* We know that it was used only between here and the beginning of
7680 the current basic block. (We also know that the last use before
7681 INSN was the output reload we are thinking of deleting, but never
7682 mind that.) Search that range; see if any ref remains. */
7683 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7685 rtx set = single_set (i2);
7687 /* Uses which just store in the pseudo don't count,
7688 since if they are the only uses, they are dead. */
7689 if (set != 0 && SET_DEST (set) == reg)
7691 if (GET_CODE (i2) == CODE_LABEL
7692 || GET_CODE (i2) == JUMP_INSN)
7694 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7695 && reg_mentioned_p (reg, PATTERN (i2)))
7697 /* Some other ref remains; just delete the output reload we
7699 delete_address_reloads (output_reload_insn, insn);
7700 delete_insn (output_reload_insn);
7705 /* Delete the now-dead stores into this pseudo. Note that this
7706 loop also takes care of deleting output_reload_insn. */
7707 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7709 rtx set = single_set (i2);
7711 if (set != 0 && SET_DEST (set) == reg)
7713 delete_address_reloads (i2, insn);
7716 if (GET_CODE (i2) == CODE_LABEL
7717 || GET_CODE (i2) == JUMP_INSN)
7721 /* For the debugging info, say the pseudo lives in this reload reg. */
7722 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7723 alter_reg (REGNO (reg), -1);
7727 delete_address_reloads (output_reload_insn, insn);
7728 delete_insn (output_reload_insn);
7732 /* We are going to delete DEAD_INSN. Recursively delete loads of
7733 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7734 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7736 delete_address_reloads (dead_insn, current_insn)
7737 rtx dead_insn, current_insn;
7739 rtx set = single_set (dead_insn);
7740 rtx set2, dst, prev, next;
7743 rtx dst = SET_DEST (set);
7744 if (GET_CODE (dst) == MEM)
7745 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7747 /* If we deleted the store from a reloaded post_{in,de}c expression,
7748 we can delete the matching adds. */
7749 prev = PREV_INSN (dead_insn);
7750 next = NEXT_INSN (dead_insn);
7751 if (! prev || ! next)
7753 set = single_set (next);
7754 set2 = single_set (prev);
7756 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7757 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7758 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7760 dst = SET_DEST (set);
7761 if (! rtx_equal_p (dst, SET_DEST (set2))
7762 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7763 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7764 || (INTVAL (XEXP (SET_SRC (set), 1))
7765 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7767 delete_related_insns (prev);
7768 delete_related_insns (next);
7771 /* Subfunction of delete_address_reloads: process registers found in X. */
7773 delete_address_reloads_1 (dead_insn, x, current_insn)
7774 rtx dead_insn, x, current_insn;
7776 rtx prev, set, dst, i2;
7778 enum rtx_code code = GET_CODE (x);
7782 const char *fmt = GET_RTX_FORMAT (code);
7783 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7786 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7787 else if (fmt[i] == 'E')
7789 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7790 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7797 if (spill_reg_order[REGNO (x)] < 0)
7800 /* Scan backwards for the insn that sets x. This might be a way back due
7802 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7804 code = GET_CODE (prev);
7805 if (code == CODE_LABEL || code == JUMP_INSN)
7807 if (GET_RTX_CLASS (code) != 'i')
7809 if (reg_set_p (x, PATTERN (prev)))
7811 if (reg_referenced_p (x, PATTERN (prev)))
7814 if (! prev || INSN_UID (prev) < reload_first_uid)
7816 /* Check that PREV only sets the reload register. */
7817 set = single_set (prev);
7820 dst = SET_DEST (set);
7821 if (GET_CODE (dst) != REG
7822 || ! rtx_equal_p (dst, x))
7824 if (! reg_set_p (dst, PATTERN (dead_insn)))
7826 /* Check if DST was used in a later insn -
7827 it might have been inherited. */
7828 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7830 if (GET_CODE (i2) == CODE_LABEL)
7834 if (reg_referenced_p (dst, PATTERN (i2)))
7836 /* If there is a reference to the register in the current insn,
7837 it might be loaded in a non-inherited reload. If no other
7838 reload uses it, that means the register is set before
7840 if (i2 == current_insn)
7842 for (j = n_reloads - 1; j >= 0; j--)
7843 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7844 || reload_override_in[j] == dst)
7846 for (j = n_reloads - 1; j >= 0; j--)
7847 if (rld[j].in && rld[j].reg_rtx == dst)
7854 if (GET_CODE (i2) == JUMP_INSN)
7856 /* If DST is still live at CURRENT_INSN, check if it is used for
7857 any reload. Note that even if CURRENT_INSN sets DST, we still
7858 have to check the reloads. */
7859 if (i2 == current_insn)
7861 for (j = n_reloads - 1; j >= 0; j--)
7862 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7863 || reload_override_in[j] == dst)
7865 /* ??? We can't finish the loop here, because dst might be
7866 allocated to a pseudo in this block if no reload in this
7867 block needs any of the clsses containing DST - see
7868 spill_hard_reg. There is no easy way to tell this, so we
7869 have to scan till the end of the basic block. */
7871 if (reg_set_p (dst, PATTERN (i2)))
7875 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7876 reg_reloaded_contents[REGNO (dst)] = -1;
7880 /* Output reload-insns to reload VALUE into RELOADREG.
7881 VALUE is an autoincrement or autodecrement RTX whose operand
7882 is a register or memory location;
7883 so reloading involves incrementing that location.
7884 IN is either identical to VALUE, or some cheaper place to reload from.
7886 INC_AMOUNT is the number to increment or decrement by (always positive).
7887 This cannot be deduced from VALUE.
7889 Return the instruction that stores into RELOADREG. */
7892 inc_for_reload (reloadreg, in, value, inc_amount)
7897 /* REG or MEM to be copied and incremented. */
7898 rtx incloc = XEXP (value, 0);
7899 /* Nonzero if increment after copying. */
7900 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7906 rtx real_in = in == value ? XEXP (in, 0) : in;
7908 /* No hard register is equivalent to this register after
7909 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7910 we could inc/dec that register as well (maybe even using it for
7911 the source), but I'm not sure it's worth worrying about. */
7912 if (GET_CODE (incloc) == REG)
7913 reg_last_reload_reg[REGNO (incloc)] = 0;
7915 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7916 inc_amount = -inc_amount;
7918 inc = GEN_INT (inc_amount);
7920 /* If this is post-increment, first copy the location to the reload reg. */
7921 if (post && real_in != reloadreg)
7922 emit_insn (gen_move_insn (reloadreg, real_in));
7926 /* See if we can directly increment INCLOC. Use a method similar to
7927 that in gen_reload. */
7929 last = get_last_insn ();
7930 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7931 gen_rtx_PLUS (GET_MODE (incloc),
7934 code = recog_memoized (add_insn);
7937 extract_insn (add_insn);
7938 if (constrain_operands (1))
7940 /* If this is a pre-increment and we have incremented the value
7941 where it lives, copy the incremented value to RELOADREG to
7942 be used as an address. */
7945 emit_insn (gen_move_insn (reloadreg, incloc));
7950 delete_insns_since (last);
7953 /* If couldn't do the increment directly, must increment in RELOADREG.
7954 The way we do this depends on whether this is pre- or post-increment.
7955 For pre-increment, copy INCLOC to the reload register, increment it
7956 there, then save back. */
7960 if (in != reloadreg)
7961 emit_insn (gen_move_insn (reloadreg, real_in));
7962 emit_insn (gen_add2_insn (reloadreg, inc));
7963 store = emit_insn (gen_move_insn (incloc, reloadreg));
7968 Because this might be a jump insn or a compare, and because RELOADREG
7969 may not be available after the insn in an input reload, we must do
7970 the incrementation before the insn being reloaded for.
7972 We have already copied IN to RELOADREG. Increment the copy in
7973 RELOADREG, save that back, then decrement RELOADREG so it has
7974 the original value. */
7976 emit_insn (gen_add2_insn (reloadreg, inc));
7977 store = emit_insn (gen_move_insn (incloc, reloadreg));
7978 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7985 /* See whether a single set SET is a noop. */
7987 reload_cse_noop_set_p (set)
7990 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7993 /* Try to simplify INSN. */
7995 reload_cse_simplify (insn, testreg)
7999 rtx body = PATTERN (insn);
8001 if (GET_CODE (body) == SET)
8005 /* Simplify even if we may think it is a no-op.
8006 We may think a memory load of a value smaller than WORD_SIZE
8007 is redundant because we haven't taken into account possible
8008 implicit extension. reload_cse_simplify_set() will bring
8009 this out, so it's safer to simplify before we delete. */
8010 count += reload_cse_simplify_set (body, insn);
8012 if (!count && reload_cse_noop_set_p (body))
8014 rtx value = SET_DEST (body);
8016 && ! REG_FUNCTION_VALUE_P (value))
8018 delete_insn_and_edges (insn);
8023 apply_change_group ();
8025 reload_cse_simplify_operands (insn, testreg);
8027 else if (GET_CODE (body) == PARALLEL)
8031 rtx value = NULL_RTX;
8033 /* If every action in a PARALLEL is a noop, we can delete
8034 the entire PARALLEL. */
8035 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8037 rtx part = XVECEXP (body, 0, i);
8038 if (GET_CODE (part) == SET)
8040 if (! reload_cse_noop_set_p (part))
8042 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8046 value = SET_DEST (part);
8049 else if (GET_CODE (part) != CLOBBER)
8055 delete_insn_and_edges (insn);
8056 /* We're done with this insn. */
8060 /* It's not a no-op, but we can try to simplify it. */
8061 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8062 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8063 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8066 apply_change_group ();
8068 reload_cse_simplify_operands (insn, testreg);
8072 /* Do a very simple CSE pass over the hard registers.
8074 This function detects no-op moves where we happened to assign two
8075 different pseudo-registers to the same hard register, and then
8076 copied one to the other. Reload will generate a useless
8077 instruction copying a register to itself.
8079 This function also detects cases where we load a value from memory
8080 into two different registers, and (if memory is more expensive than
8081 registers) changes it to simply copy the first register into the
8084 Another optimization is performed that scans the operands of each
8085 instruction to see whether the value is already available in a
8086 hard register. It then replaces the operand with the hard register
8087 if possible, much like an optional reload would. */
8090 reload_cse_regs_1 (first)
8094 rtx testreg = gen_rtx_REG (VOIDmode, -1);
8097 init_alias_analysis ();
8099 for (insn = first; insn; insn = NEXT_INSN (insn))
8102 reload_cse_simplify (insn, testreg);
8104 cselib_process_insn (insn);
8108 end_alias_analysis ();
8112 /* Call cse / combine like post-reload optimization phases.
8113 FIRST is the first instruction. */
8115 reload_cse_regs (first)
8118 reload_cse_regs_1 (first);
8120 reload_cse_move2add (first);
8121 if (flag_expensive_optimizations)
8122 reload_cse_regs_1 (first);
8125 /* Try to simplify a single SET instruction. SET is the set pattern.
8126 INSN is the instruction it came from.
8127 This function only handles one case: if we set a register to a value
8128 which is not a register, we try to find that value in some other register
8129 and change the set into a register copy. */
8132 reload_cse_simplify_set (set, insn)
8139 enum reg_class dclass;
8142 struct elt_loc_list *l;
8143 #ifdef LOAD_EXTEND_OP
8144 enum rtx_code extend_op = NIL;
8147 dreg = true_regnum (SET_DEST (set));
8151 src = SET_SRC (set);
8152 if (side_effects_p (src) || true_regnum (src) >= 0)
8155 dclass = REGNO_REG_CLASS (dreg);
8157 #ifdef LOAD_EXTEND_OP
8158 /* When replacing a memory with a register, we need to honor assumptions
8159 that combine made wrt the contents of sign bits. We'll do this by
8160 generating an extend instruction instead of a reg->reg copy. Thus
8161 the destination must be a register that we can widen. */
8162 if (GET_CODE (src) == MEM
8163 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8164 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8165 && GET_CODE (SET_DEST (set)) != REG)
8169 /* If memory loads are cheaper than register copies, don't change them. */
8170 if (GET_CODE (src) == MEM)
8171 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8172 else if (CONSTANT_P (src))
8173 old_cost = rtx_cost (src, SET);
8174 else if (GET_CODE (src) == REG)
8175 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8176 REGNO_REG_CLASS (REGNO (src)), dclass);
8179 old_cost = rtx_cost (src, SET);
8181 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8184 for (l = val->locs; l; l = l->next)
8186 rtx this_rtx = l->loc;
8189 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8191 #ifdef LOAD_EXTEND_OP
8192 if (extend_op != NIL)
8194 HOST_WIDE_INT this_val;
8196 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8197 constants, such as SYMBOL_REF, cannot be extended. */
8198 if (GET_CODE (this_rtx) != CONST_INT)
8201 this_val = INTVAL (this_rtx);
8205 this_val &= GET_MODE_MASK (GET_MODE (src));
8208 /* ??? In theory we're already extended. */
8209 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8214 this_rtx = GEN_INT (this_val);
8217 this_cost = rtx_cost (this_rtx, SET);
8219 else if (GET_CODE (this_rtx) == REG)
8221 #ifdef LOAD_EXTEND_OP
8222 if (extend_op != NIL)
8224 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8225 this_cost = rtx_cost (this_rtx, SET);
8229 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8230 REGNO_REG_CLASS (REGNO (this_rtx)),
8236 /* If equal costs, prefer registers over anything else. That
8237 tends to lead to smaller instructions on some machines. */
8238 if (this_cost < old_cost
8239 || (this_cost == old_cost
8240 && GET_CODE (this_rtx) == REG
8241 && GET_CODE (SET_SRC (set)) != REG))
8243 #ifdef LOAD_EXTEND_OP
8244 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8245 && extend_op != NIL)
8247 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8248 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8249 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8253 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8254 old_cost = this_cost, did_change = 1;
8261 /* Try to replace operands in INSN with equivalent values that are already
8262 in registers. This can be viewed as optional reloading.
8264 For each non-register operand in the insn, see if any hard regs are
8265 known to be equivalent to that operand. Record the alternatives which
8266 can accept these hard registers. Among all alternatives, select the
8267 ones which are better or equal to the one currently matching, where
8268 "better" is in terms of '?' and '!' constraints. Among the remaining
8269 alternatives, select the one which replaces most operands with
8273 reload_cse_simplify_operands (insn, testreg)
8279 /* For each operand, all registers that are equivalent to it. */
8280 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8282 const char *constraints[MAX_RECOG_OPERANDS];
8284 /* Vector recording how bad an alternative is. */
8285 int *alternative_reject;
8286 /* Vector recording how many registers can be introduced by choosing
8287 this alternative. */
8288 int *alternative_nregs;
8289 /* Array of vectors recording, for each operand and each alternative,
8290 which hard register to substitute, or -1 if the operand should be
8292 int *op_alt_regno[MAX_RECOG_OPERANDS];
8293 /* Array of alternatives, sorted in order of decreasing desirability. */
8294 int *alternative_order;
8296 extract_insn (insn);
8298 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8301 /* Figure out which alternative currently matches. */
8302 if (! constrain_operands (1))
8303 fatal_insn_not_found (insn);
8305 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8306 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8307 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8308 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8309 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8311 /* For each operand, find out which regs are equivalent. */
8312 for (i = 0; i < recog_data.n_operands; i++)
8315 struct elt_loc_list *l;
8317 CLEAR_HARD_REG_SET (equiv_regs[i]);
8319 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8320 right, so avoid the problem here. Likewise if we have a constant
8321 and the insn pattern doesn't tell us the mode we need. */
8322 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8323 || (CONSTANT_P (recog_data.operand[i])
8324 && recog_data.operand_mode[i] == VOIDmode))
8327 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8331 for (l = v->locs; l; l = l->next)
8332 if (GET_CODE (l->loc) == REG)
8333 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8336 for (i = 0; i < recog_data.n_operands; i++)
8338 enum machine_mode mode;
8342 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8343 for (j = 0; j < recog_data.n_alternatives; j++)
8344 op_alt_regno[i][j] = -1;
8346 p = constraints[i] = recog_data.constraints[i];
8347 mode = recog_data.operand_mode[i];
8349 /* Add the reject values for each alternative given by the constraints
8350 for this operand. */
8358 alternative_reject[j] += 3;
8360 alternative_reject[j] += 300;
8363 /* We won't change operands which are already registers. We
8364 also don't want to modify output operands. */
8365 regno = true_regnum (recog_data.operand[i]);
8367 || constraints[i][0] == '='
8368 || constraints[i][0] == '+')
8371 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8373 int class = (int) NO_REGS;
8375 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8378 REGNO (testreg) = regno;
8379 PUT_MODE (testreg, mode);
8381 /* We found a register equal to this operand. Now look for all
8382 alternatives that can accept this register and have not been
8383 assigned a register they can use yet. */
8392 case '=': case '+': case '?':
8393 case '#': case '&': case '!':
8395 case '0': case '1': case '2': case '3': case '4':
8396 case '5': case '6': case '7': case '8': case '9':
8397 case 'm': case '<': case '>': case 'V': case 'o':
8398 case 'E': case 'F': case 'G': case 'H':
8399 case 's': case 'i': case 'n':
8400 case 'I': case 'J': case 'K': case 'L':
8401 case 'M': case 'N': case 'O': case 'P':
8403 /* These don't say anything we care about. */
8407 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8412 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)];
8415 case ',': case '\0':
8416 /* See if REGNO fits this alternative, and set it up as the
8417 replacement register if we don't have one for this
8418 alternative yet and the operand being replaced is not
8419 a cheap CONST_INT. */
8420 if (op_alt_regno[i][j] == -1
8421 && reg_fits_class_p (testreg, class, 0, mode)
8422 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8423 || (rtx_cost (recog_data.operand[i], SET)
8424 > rtx_cost (testreg, SET))))
8426 alternative_nregs[j]++;
8427 op_alt_regno[i][j] = regno;
8439 /* Record all alternatives which are better or equal to the currently
8440 matching one in the alternative_order array. */
8441 for (i = j = 0; i < recog_data.n_alternatives; i++)
8442 if (alternative_reject[i] <= alternative_reject[which_alternative])
8443 alternative_order[j++] = i;
8444 recog_data.n_alternatives = j;
8446 /* Sort it. Given a small number of alternatives, a dumb algorithm
8447 won't hurt too much. */
8448 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8451 int best_reject = alternative_reject[alternative_order[i]];
8452 int best_nregs = alternative_nregs[alternative_order[i]];
8455 for (j = i + 1; j < recog_data.n_alternatives; j++)
8457 int this_reject = alternative_reject[alternative_order[j]];
8458 int this_nregs = alternative_nregs[alternative_order[j]];
8460 if (this_reject < best_reject
8461 || (this_reject == best_reject && this_nregs < best_nregs))
8464 best_reject = this_reject;
8465 best_nregs = this_nregs;
8469 tmp = alternative_order[best];
8470 alternative_order[best] = alternative_order[i];
8471 alternative_order[i] = tmp;
8474 /* Substitute the operands as determined by op_alt_regno for the best
8476 j = alternative_order[0];
8478 for (i = 0; i < recog_data.n_operands; i++)
8480 enum machine_mode mode = recog_data.operand_mode[i];
8481 if (op_alt_regno[i][j] == -1)
8484 validate_change (insn, recog_data.operand_loc[i],
8485 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8488 for (i = recog_data.n_dups - 1; i >= 0; i--)
8490 int op = recog_data.dup_num[i];
8491 enum machine_mode mode = recog_data.operand_mode[op];
8493 if (op_alt_regno[op][j] == -1)
8496 validate_change (insn, recog_data.dup_loc[i],
8497 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8500 return apply_change_group ();
8503 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8505 This code might also be useful when reload gave up on reg+reg addresssing
8506 because of clashes between the return register and INDEX_REG_CLASS. */
8508 /* The maximum number of uses of a register we can keep track of to
8509 replace them with reg+reg addressing. */
8510 #define RELOAD_COMBINE_MAX_USES 6
8512 /* INSN is the insn where a register has ben used, and USEP points to the
8513 location of the register within the rtl. */
8514 struct reg_use { rtx insn, *usep; };
8516 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8517 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8518 indicates where it becomes live again.
8519 Otherwise, USE_INDEX is the index of the last encountered use of the
8520 register (which is first among these we have seen since we scan backwards),
8521 OFFSET contains the constant offset that is added to the register in
8522 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8523 last, of these uses.
8524 STORE_RUID is always meaningful if we only want to use a value in a
8525 register in a different place: it denotes the next insn in the insn
8526 stream (i.e. the last ecountered) that sets or clobbers the register. */
8529 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8534 } reg_state[FIRST_PSEUDO_REGISTER];
8536 /* Reverse linear uid. This is increased in reload_combine while scanning
8537 the instructions from last to first. It is used to set last_label_ruid
8538 and the store_ruid / use_ruid fields in reg_state. */
8539 static int reload_combine_ruid;
8541 #define LABEL_LIVE(LABEL) \
8542 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8548 int first_index_reg = -1;
8549 int last_index_reg = 0;
8553 int last_label_ruid;
8554 int min_labelno, n_labels;
8555 HARD_REG_SET ever_live_at_start, *label_live;
8557 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8558 reload has already used it where appropriate, so there is no use in
8559 trying to generate it now. */
8560 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8563 /* To avoid wasting too much time later searching for an index register,
8564 determine the minimum and maximum index register numbers. */
8565 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8566 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8568 if (first_index_reg == -1)
8569 first_index_reg = r;
8574 /* If no index register is available, we can quit now. */
8575 if (first_index_reg == -1)
8578 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8579 information is a bit fuzzy immediately after reload, but it's
8580 still good enough to determine which registers are live at a jump
8582 min_labelno = get_first_label_num ();
8583 n_labels = max_label_num () - min_labelno;
8584 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8585 CLEAR_HARD_REG_SET (ever_live_at_start);
8587 FOR_EACH_BB_REVERSE (bb)
8590 if (GET_CODE (insn) == CODE_LABEL)
8594 REG_SET_TO_HARD_REG_SET (live,
8595 bb->global_live_at_start);
8596 compute_use_by_pseudos (&live,
8597 bb->global_live_at_start);
8598 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8599 IOR_HARD_REG_SET (ever_live_at_start, live);
8603 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8604 last_label_ruid = reload_combine_ruid = 0;
8605 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8607 reg_state[r].store_ruid = reload_combine_ruid;
8609 reg_state[r].use_index = -1;
8611 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8614 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8618 /* We cannot do our optimization across labels. Invalidating all the use
8619 information we have would be costly, so we just note where the label
8620 is and then later disable any optimization that would cross it. */
8621 if (GET_CODE (insn) == CODE_LABEL)
8622 last_label_ruid = reload_combine_ruid;
8623 else if (GET_CODE (insn) == BARRIER)
8624 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8625 if (! fixed_regs[r])
8626 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8628 if (! INSN_P (insn))
8631 reload_combine_ruid++;
8633 /* Look for (set (REGX) (CONST_INT))
8634 (set (REGX) (PLUS (REGX) (REGY)))
8636 ... (MEM (REGX)) ...
8638 (set (REGZ) (CONST_INT))
8640 ... (MEM (PLUS (REGZ) (REGY)))... .
8642 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8643 and that we know all uses of REGX before it dies. */
8644 set = single_set (insn);
8646 && GET_CODE (SET_DEST (set)) == REG
8647 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8648 GET_MODE (SET_DEST (set)))
8650 && GET_CODE (SET_SRC (set)) == PLUS
8651 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8652 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8653 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8655 rtx reg = SET_DEST (set);
8656 rtx plus = SET_SRC (set);
8657 rtx base = XEXP (plus, 1);
8658 rtx prev = prev_nonnote_insn (insn);
8659 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8660 unsigned int regno = REGNO (reg);
8661 rtx const_reg = NULL_RTX;
8662 rtx reg_sum = NULL_RTX;
8664 /* Now, we need an index register.
8665 We'll set index_reg to this index register, const_reg to the
8666 register that is to be loaded with the constant
8667 (denoted as REGZ in the substitution illustration above),
8668 and reg_sum to the register-register that we want to use to
8669 substitute uses of REG (typically in MEMs) with.
8670 First check REG and BASE for being index registers;
8671 we can use them even if they are not dead. */
8672 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8673 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8681 /* Otherwise, look for a free index register. Since we have
8682 checked above that neiter REG nor BASE are index registers,
8683 if we find anything at all, it will be different from these
8685 for (i = first_index_reg; i <= last_index_reg; i++)
8687 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8689 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8690 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8691 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8693 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8695 const_reg = index_reg;
8696 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8702 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8703 (REGY), i.e. BASE, is not clobbered before the last use we'll
8706 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8707 && rtx_equal_p (SET_DEST (prev_set), reg)
8708 && reg_state[regno].use_index >= 0
8709 && (reg_state[REGNO (base)].store_ruid
8710 <= reg_state[regno].use_ruid)
8715 /* Change destination register and, if necessary, the
8716 constant value in PREV, the constant loading instruction. */
8717 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8718 if (reg_state[regno].offset != const0_rtx)
8719 validate_change (prev,
8720 &SET_SRC (prev_set),
8721 GEN_INT (INTVAL (SET_SRC (prev_set))
8722 + INTVAL (reg_state[regno].offset)),
8725 /* Now for every use of REG that we have recorded, replace REG
8727 for (i = reg_state[regno].use_index;
8728 i < RELOAD_COMBINE_MAX_USES; i++)
8729 validate_change (reg_state[regno].reg_use[i].insn,
8730 reg_state[regno].reg_use[i].usep,
8731 /* Each change must have its own
8733 copy_rtx (reg_sum), 1);
8735 if (apply_change_group ())
8739 /* Delete the reg-reg addition. */
8742 if (reg_state[regno].offset != const0_rtx)
8743 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8745 for (np = ®_NOTES (prev); *np;)
8747 if (REG_NOTE_KIND (*np) == REG_EQUAL
8748 || REG_NOTE_KIND (*np) == REG_EQUIV)
8749 *np = XEXP (*np, 1);
8751 np = &XEXP (*np, 1);
8754 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8755 reg_state[REGNO (const_reg)].store_ruid
8756 = reload_combine_ruid;
8762 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8764 if (GET_CODE (insn) == CALL_INSN)
8768 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8769 if (call_used_regs[r])
8771 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8772 reg_state[r].store_ruid = reload_combine_ruid;
8775 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8776 link = XEXP (link, 1))
8778 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8779 if (GET_CODE (usage_rtx) == REG)
8782 unsigned int start_reg = REGNO (usage_rtx);
8783 unsigned int num_regs =
8784 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8785 unsigned int end_reg = start_reg + num_regs - 1;
8786 for (i = start_reg; i <= end_reg; i++)
8787 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8789 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8790 reg_state[i].store_ruid = reload_combine_ruid;
8793 reg_state[i].use_index = -1;
8798 else if (GET_CODE (insn) == JUMP_INSN
8799 && GET_CODE (PATTERN (insn)) != RETURN)
8801 /* Non-spill registers might be used at the call destination in
8802 some unknown fashion, so we have to mark the unknown use. */
8805 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8806 && JUMP_LABEL (insn))
8807 live = &LABEL_LIVE (JUMP_LABEL (insn));
8809 live = &ever_live_at_start;
8811 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8812 if (TEST_HARD_REG_BIT (*live, i))
8813 reg_state[i].use_index = -1;
8816 reload_combine_note_use (&PATTERN (insn), insn);
8817 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8819 if (REG_NOTE_KIND (note) == REG_INC
8820 && GET_CODE (XEXP (note, 0)) == REG)
8822 int regno = REGNO (XEXP (note, 0));
8824 reg_state[regno].store_ruid = reload_combine_ruid;
8825 reg_state[regno].use_index = -1;
8833 /* Check if DST is a register or a subreg of a register; if it is,
8834 update reg_state[regno].store_ruid and reg_state[regno].use_index
8835 accordingly. Called via note_stores from reload_combine. */
8838 reload_combine_note_store (dst, set, data)
8840 void *data ATTRIBUTE_UNUSED;
8844 enum machine_mode mode = GET_MODE (dst);
8846 if (GET_CODE (dst) == SUBREG)
8848 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8849 GET_MODE (SUBREG_REG (dst)),
8852 dst = SUBREG_REG (dst);
8854 if (GET_CODE (dst) != REG)
8856 regno += REGNO (dst);
8858 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8859 careful with registers / register parts that are not full words.
8861 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8862 if (GET_CODE (set) != SET
8863 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8864 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8865 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8867 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8869 reg_state[i].use_index = -1;
8870 reg_state[i].store_ruid = reload_combine_ruid;
8875 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8877 reg_state[i].store_ruid = reload_combine_ruid;
8878 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8883 /* XP points to a piece of rtl that has to be checked for any uses of
8885 *XP is the pattern of INSN, or a part of it.
8886 Called from reload_combine, and recursively by itself. */
8888 reload_combine_note_use (xp, insn)
8892 enum rtx_code code = x->code;
8895 rtx offset = const0_rtx; /* For the REG case below. */
8900 if (GET_CODE (SET_DEST (x)) == REG)
8902 reload_combine_note_use (&SET_SRC (x), insn);
8908 /* If this is the USE of a return value, we can't change it. */
8909 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8911 /* Mark the return register as used in an unknown fashion. */
8912 rtx reg = XEXP (x, 0);
8913 int regno = REGNO (reg);
8914 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8916 while (--nregs >= 0)
8917 reg_state[regno + nregs].use_index = -1;
8923 if (GET_CODE (SET_DEST (x)) == REG)
8925 /* No spurious CLOBBERs of pseudo registers may remain. */
8926 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8933 /* We are interested in (plus (reg) (const_int)) . */
8934 if (GET_CODE (XEXP (x, 0)) != REG
8935 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8937 offset = XEXP (x, 1);
8942 int regno = REGNO (x);
8946 /* No spurious USEs of pseudo registers may remain. */
8947 if (regno >= FIRST_PSEUDO_REGISTER)
8950 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8952 /* We can't substitute into multi-hard-reg uses. */
8955 while (--nregs >= 0)
8956 reg_state[regno + nregs].use_index = -1;
8960 /* If this register is already used in some unknown fashion, we
8962 If we decrement the index from zero to -1, we can't store more
8963 uses, so this register becomes used in an unknown fashion. */
8964 use_index = --reg_state[regno].use_index;
8968 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8970 /* We have found another use for a register that is already
8971 used later. Check if the offsets match; if not, mark the
8972 register as used in an unknown fashion. */
8973 if (! rtx_equal_p (offset, reg_state[regno].offset))
8975 reg_state[regno].use_index = -1;
8981 /* This is the first use of this register we have seen since we
8982 marked it as dead. */
8983 reg_state[regno].offset = offset;
8984 reg_state[regno].use_ruid = reload_combine_ruid;
8986 reg_state[regno].reg_use[use_index].insn = insn;
8987 reg_state[regno].reg_use[use_index].usep = xp;
8995 /* Recursively process the components of X. */
8996 fmt = GET_RTX_FORMAT (code);
8997 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9000 reload_combine_note_use (&XEXP (x, i), insn);
9001 else if (fmt[i] == 'E')
9003 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9004 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9009 /* See if we can reduce the cost of a constant by replacing a move
9010 with an add. We track situations in which a register is set to a
9011 constant or to a register plus a constant. */
9012 /* We cannot do our optimization across labels. Invalidating all the
9013 information about register contents we have would be costly, so we
9014 use move2add_last_label_luid to note where the label is and then
9015 later disable any optimization that would cross it.
9016 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9017 reg_set_luid[n] is greater than last_label_luid[n] . */
9018 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9020 /* If reg_base_reg[n] is negative, register n has been set to
9021 reg_offset[n] in mode reg_mode[n] .
9022 If reg_base_reg[n] is non-negative, register n has been set to the
9023 sum of reg_offset[n] and the value of register reg_base_reg[n]
9024 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9025 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9026 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9027 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9029 /* move2add_luid is linearily increased while scanning the instructions
9030 from first to last. It is used to set reg_set_luid in
9031 reload_cse_move2add and move2add_note_store. */
9032 static int move2add_luid;
9034 /* move2add_last_label_luid is set whenever a label is found. Labels
9035 invalidate all previously collected reg_offset data. */
9036 static int move2add_last_label_luid;
9038 /* Generate a CONST_INT and force it in the range of MODE. */
9040 static HOST_WIDE_INT
9041 sext_for_mode (mode, value)
9042 enum machine_mode mode;
9043 HOST_WIDE_INT value;
9045 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9046 int width = GET_MODE_BITSIZE (mode);
9048 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9050 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9051 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9052 cval |= (HOST_WIDE_INT) -1 << width;
9057 /* ??? We don't know how zero / sign extension is handled, hence we
9058 can't go from a narrower to a wider mode. */
9059 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9060 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9061 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9062 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9063 GET_MODE_BITSIZE (INMODE))))
9066 reload_cse_move2add (first)
9072 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9073 reg_set_luid[i] = 0;
9075 move2add_last_label_luid = 0;
9077 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9081 if (GET_CODE (insn) == CODE_LABEL)
9083 move2add_last_label_luid = move2add_luid;
9084 /* We're going to increment move2add_luid twice after a
9085 label, so that we can use move2add_last_label_luid + 1 as
9086 the luid for constants. */
9090 if (! INSN_P (insn))
9092 pat = PATTERN (insn);
9093 /* For simplicity, we only perform this optimization on
9094 straightforward SETs. */
9095 if (GET_CODE (pat) == SET
9096 && GET_CODE (SET_DEST (pat)) == REG)
9098 rtx reg = SET_DEST (pat);
9099 int regno = REGNO (reg);
9100 rtx src = SET_SRC (pat);
9102 /* Check if we have valid information on the contents of this
9103 register in the mode of REG. */
9104 if (reg_set_luid[regno] > move2add_last_label_luid
9105 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9107 /* Try to transform (set (REGX) (CONST_INT A))
9109 (set (REGX) (CONST_INT B))
9111 (set (REGX) (CONST_INT A))
9113 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9115 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9118 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9120 - reg_offset[regno]));
9121 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9122 use (set (reg) (reg)) instead.
9123 We don't delete this insn, nor do we convert it into a
9124 note, to avoid losing register notes or the return
9125 value flag. jump2 already knowns how to get rid of
9127 if (new_src == const0_rtx)
9128 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9129 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9130 && have_add2_insn (reg, new_src))
9131 success = validate_change (insn, &PATTERN (insn),
9132 gen_add2_insn (reg, new_src), 0);
9133 reg_set_luid[regno] = move2add_luid;
9134 reg_mode[regno] = GET_MODE (reg);
9135 reg_offset[regno] = INTVAL (src);
9139 /* Try to transform (set (REGX) (REGY))
9140 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9143 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9146 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9148 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9149 else if (GET_CODE (src) == REG
9150 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9151 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9152 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9153 reg_mode[REGNO (src)]))
9155 rtx next = next_nonnote_insn (insn);
9158 set = single_set (next);
9160 && SET_DEST (set) == reg
9161 && GET_CODE (SET_SRC (set)) == PLUS
9162 && XEXP (SET_SRC (set), 0) == reg
9163 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9165 rtx src3 = XEXP (SET_SRC (set), 1);
9166 HOST_WIDE_INT added_offset = INTVAL (src3);
9167 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9168 HOST_WIDE_INT regno_offset = reg_offset[regno];
9169 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9175 if (new_src == const0_rtx)
9176 /* See above why we create (set (reg) (reg)) here. */
9178 = validate_change (next, &SET_SRC (set), reg, 0);
9179 else if ((rtx_cost (new_src, PLUS)
9180 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9181 && have_add2_insn (reg, new_src))
9183 = validate_change (next, &PATTERN (next),
9184 gen_add2_insn (reg, new_src), 0);
9188 reg_mode[regno] = GET_MODE (reg);
9189 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9198 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9200 if (REG_NOTE_KIND (note) == REG_INC
9201 && GET_CODE (XEXP (note, 0)) == REG)
9203 /* Reset the information about this register. */
9204 int regno = REGNO (XEXP (note, 0));
9205 if (regno < FIRST_PSEUDO_REGISTER)
9206 reg_set_luid[regno] = 0;
9209 note_stores (PATTERN (insn), move2add_note_store, NULL);
9210 /* If this is a CALL_INSN, all call used registers are stored with
9212 if (GET_CODE (insn) == CALL_INSN)
9214 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9216 if (call_used_regs[i])
9217 /* Reset the information about this register. */
9218 reg_set_luid[i] = 0;
9224 /* SET is a SET or CLOBBER that sets DST.
9225 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9226 Called from reload_cse_move2add via note_stores. */
9229 move2add_note_store (dst, set, data)
9231 void *data ATTRIBUTE_UNUSED;
9233 unsigned int regno = 0;
9235 enum machine_mode mode = GET_MODE (dst);
9237 if (GET_CODE (dst) == SUBREG)
9239 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9240 GET_MODE (SUBREG_REG (dst)),
9243 dst = SUBREG_REG (dst);
9246 /* Some targets do argument pushes without adding REG_INC notes. */
9248 if (GET_CODE (dst) == MEM)
9250 dst = XEXP (dst, 0);
9251 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9252 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9253 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9256 if (GET_CODE (dst) != REG)
9259 regno += REGNO (dst);
9261 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9262 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9263 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9264 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9266 rtx src = SET_SRC (set);
9268 HOST_WIDE_INT offset;
9270 /* This may be different from mode, if SET_DEST (set) is a
9272 enum machine_mode dst_mode = GET_MODE (dst);
9274 switch (GET_CODE (src))
9277 if (GET_CODE (XEXP (src, 0)) == REG)
9279 base_reg = XEXP (src, 0);
9281 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9282 offset = INTVAL (XEXP (src, 1));
9283 else if (GET_CODE (XEXP (src, 1)) == REG
9284 && (reg_set_luid[REGNO (XEXP (src, 1))]
9285 > move2add_last_label_luid)
9286 && (MODES_OK_FOR_MOVE2ADD
9287 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9289 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9290 offset = reg_offset[REGNO (XEXP (src, 1))];
9291 /* Maybe the first register is known to be a
9293 else if (reg_set_luid[REGNO (base_reg)]
9294 > move2add_last_label_luid
9295 && (MODES_OK_FOR_MOVE2ADD
9296 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9297 && reg_base_reg[REGNO (base_reg)] < 0)
9299 offset = reg_offset[REGNO (base_reg)];
9300 base_reg = XEXP (src, 1);
9319 /* Start tracking the register as a constant. */
9320 reg_base_reg[regno] = -1;
9321 reg_offset[regno] = INTVAL (SET_SRC (set));
9322 /* We assign the same luid to all registers set to constants. */
9323 reg_set_luid[regno] = move2add_last_label_luid + 1;
9324 reg_mode[regno] = mode;
9329 /* Invalidate the contents of the register. */
9330 reg_set_luid[regno] = 0;
9334 base_regno = REGNO (base_reg);
9335 /* If information about the base register is not valid, set it
9336 up as a new base register, pretending its value is known
9337 starting from the current insn. */
9338 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9340 reg_base_reg[base_regno] = base_regno;
9341 reg_offset[base_regno] = 0;
9342 reg_set_luid[base_regno] = move2add_luid;
9343 reg_mode[base_regno] = mode;
9345 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9346 reg_mode[base_regno]))
9349 reg_mode[regno] = mode;
9351 /* Copy base information from our base register. */
9352 reg_set_luid[regno] = reg_set_luid[base_regno];
9353 reg_base_reg[regno] = reg_base_reg[base_regno];
9355 /* Compute the sum of the offsets or constants. */
9356 reg_offset[regno] = sext_for_mode (dst_mode,
9358 + reg_offset[base_regno]);
9362 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9364 for (i = regno; i < endregno; i++)
9365 /* Reset the information about this register. */
9366 reg_set_luid[i] = 0;
9372 add_auto_inc_notes (insn, x)
9376 enum rtx_code code = GET_CODE (x);
9380 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9383 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9387 /* Scan all the operand sub-expressions. */
9388 fmt = GET_RTX_FORMAT (code);
9389 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9392 add_auto_inc_notes (insn, XEXP (x, i));
9393 else if (fmt[i] == 'E')
9394 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9395 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9400 /* Copy EH notes from an insn to its reloads. */
9402 copy_eh_notes (insn, x)
9406 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9409 for (; x != 0; x = NEXT_INSN (x))
9411 if (may_trap_p (PATTERN (x)))
9413 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9419 /* This is used by reload pass, that does emit some instructions after
9420 abnormal calls moving basic block end, but in fact it wants to emit
9421 them on the edge. Looks for abnormal call edges, find backward the
9422 proper call and fix the damage.
9424 Similar handle instructions throwing exceptions internally. */
9426 fixup_abnormal_edges ()
9428 bool inserted = false;
9435 /* Look for cases we are interested in - an calls or instructions causing
9437 for (e = bb->succ; e; e = e->succ_next)
9439 if (e->flags & EDGE_ABNORMAL_CALL)
9441 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9442 == (EDGE_ABNORMAL | EDGE_EH))
9445 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9447 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9449 for (e = bb->succ; e; e = e->succ_next)
9450 if (e->flags & EDGE_FALLTHRU)
9452 /* Get past the new insns generated. Allow notes, as the insns may
9453 be already deleted. */
9454 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9455 && !can_throw_internal (insn)
9456 && insn != bb->head)
9457 insn = PREV_INSN (insn);
9458 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9462 insn = NEXT_INSN (insn);
9463 while (insn && insn != stop)
9465 next = NEXT_INSN (insn);
9472 /* We're not deleting it, we're moving it. */
9473 INSN_DELETED_P (insn) = 0;
9475 /* Emit a sequence, rather than scarfing the pattern, so
9476 that we don't lose REG_NOTES etc. */
9477 /* ??? Could copy the test from gen_sequence, but don't
9478 think it's worth the bother. */
9479 seq = gen_rtx_SEQUENCE (VOIDmode, gen_rtvec (1, insn));
9480 insert_insn_on_edge (seq, e);
9487 commit_edge_insertions ();
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