1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 struct target_reload default_target_reload;
87 struct target_reload *this_target_reload = &default_target_reload;
90 #define spill_indirect_levels \
91 (this_target_reload->x_spill_indirect_levels)
93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
94 into which reg N has been reloaded (perhaps for a previous insn). */
95 static rtx *reg_last_reload_reg;
97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
98 for an output reload that stores into reg N. */
99 static regset_head reg_has_output_reload;
101 /* Indicates which hard regs are reload-registers for an output reload
102 in the current insn. */
103 static HARD_REG_SET reg_is_output_reload;
105 /* Widest width in which each pseudo reg is referred to (via subreg). */
106 static unsigned int *reg_max_ref_width;
108 /* Vector to remember old contents of reg_renumber before spilling. */
109 static short *reg_old_renumber;
111 /* During reload_as_needed, element N contains the last pseudo regno reloaded
112 into hard register N. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
117 /* During reload_as_needed, element N contains the insn for which
118 hard register N was last used. Its contents are significant only
119 when reg_reloaded_valid is set for this register. */
120 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
122 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
123 static HARD_REG_SET reg_reloaded_valid;
124 /* Indicate if the register was dead at the end of the reload.
125 This is only valid if reg_reloaded_contents is set and valid. */
126 static HARD_REG_SET reg_reloaded_dead;
128 /* Indicate whether the register's current value is one that is not
129 safe to retain across a call, even for registers that are normally
130 call-saved. This is only meaningful for members of reg_reloaded_valid. */
131 static HARD_REG_SET reg_reloaded_call_part_clobbered;
133 /* Number of spill-regs so far; number of valid elements of spill_regs. */
136 /* In parallel with spill_regs, contains REG rtx's for those regs.
137 Holds the last rtx used for any given reg, or 0 if it has never
138 been used for spilling yet. This rtx is reused, provided it has
140 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
142 /* In parallel with spill_regs, contains nonzero for a spill reg
143 that was stored after the last time it was used.
144 The precise value is the insn generated to do the store. */
145 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
147 /* This is the register that was stored with spill_reg_store. This is a
148 copy of reload_out / reload_out_reg when the value was stored; if
149 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
150 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
152 /* This table is the inverse mapping of spill_regs:
153 indexed by hard reg number,
154 it contains the position of that reg in spill_regs,
155 or -1 for something that is not in spill_regs.
157 ?!? This is no longer accurate. */
158 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
160 /* This reg set indicates registers that can't be used as spill registers for
161 the currently processed insn. These are the hard registers which are live
162 during the insn, but not allocated to pseudos, as well as fixed
164 static HARD_REG_SET bad_spill_regs;
166 /* These are the hard registers that can't be used as spill register for any
167 insn. This includes registers used for user variables and registers that
168 we can't eliminate. A register that appears in this set also can't be used
169 to retry register allocation. */
170 static HARD_REG_SET bad_spill_regs_global;
172 /* Describes order of use of registers for reloading
173 of spilled pseudo-registers. `n_spills' is the number of
174 elements that are actually valid; new ones are added at the end.
176 Both spill_regs and spill_reg_order are used on two occasions:
177 once during find_reload_regs, where they keep track of the spill registers
178 for a single insn, but also during reload_as_needed where they show all
179 the registers ever used by reload. For the latter case, the information
180 is calculated during finish_spills. */
181 static short spill_regs[FIRST_PSEUDO_REGISTER];
183 /* This vector of reg sets indicates, for each pseudo, which hard registers
184 may not be used for retrying global allocation because the register was
185 formerly spilled from one of them. If we allowed reallocating a pseudo to
186 a register that it was already allocated to, reload might not
188 static HARD_REG_SET *pseudo_previous_regs;
190 /* This vector of reg sets indicates, for each pseudo, which hard
191 registers may not be used for retrying global allocation because they
192 are used as spill registers during one of the insns in which the
194 static HARD_REG_SET *pseudo_forbidden_regs;
196 /* All hard regs that have been used as spill registers for any insn are
197 marked in this set. */
198 static HARD_REG_SET used_spill_regs;
200 /* Index of last register assigned as a spill register. We allocate in
201 a round-robin fashion. */
202 static int last_spill_reg;
204 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
207 /* Width allocated so far for that stack slot. */
208 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
210 /* Record which pseudos needed to be spilled. */
211 static regset_head spilled_pseudos;
213 /* Record which pseudos changed their allocation in finish_spills. */
214 static regset_head changed_allocation_pseudos;
216 /* Used for communication between order_regs_for_reload and count_pseudo.
217 Used to avoid counting one pseudo twice. */
218 static regset_head pseudos_counted;
220 /* First uid used by insns created by reload in this function.
221 Used in find_equiv_reg. */
222 int reload_first_uid;
224 /* Flag set by local-alloc or global-alloc if anything is live in
225 a call-clobbered reg across calls. */
226 int caller_save_needed;
228 /* Set to 1 while reload_as_needed is operating.
229 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress = 0;
232 /* This obstack is used for allocation of rtl during register elimination.
233 The allocated storage can be freed once find_reloads has processed the
235 static struct obstack reload_obstack;
237 /* Points to the beginning of the reload_obstack. All insn_chain structures
238 are allocated first. */
239 static char *reload_startobj;
241 /* The point after all insn_chain structures. Used to quickly deallocate
242 memory allocated in copy_reloads during calculate_needs_all_insns. */
243 static char *reload_firstobj;
245 /* This points before all local rtl generated by register elimination.
246 Used to quickly free all memory after processing one insn. */
247 static char *reload_insn_firstobj;
249 /* List of insn_chain instructions, one for every insn that reload needs to
251 struct insn_chain *reload_insn_chain;
253 /* TRUE if we potentially left dead insns in the insn stream and want to
254 run DCE immediately after reload, FALSE otherwise. */
255 static bool need_dce;
257 /* List of all insns needing reloads. */
258 static struct insn_chain *insns_need_reload;
260 /* This structure is used to record information about register eliminations.
261 Each array entry describes one possible way of eliminating a register
262 in favor of another. If there is more than one way of eliminating a
263 particular register, the most preferred should be specified first. */
267 int from; /* Register number to be eliminated. */
268 int to; /* Register number used as replacement. */
269 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
270 int can_eliminate; /* Nonzero if this elimination can be done. */
271 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
272 target hook in previous scan over insns
274 HOST_WIDE_INT offset; /* Current offset between the two regs. */
275 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
276 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
277 rtx from_rtx; /* REG rtx for the register to be eliminated.
278 We cannot simply compare the number since
279 we might then spuriously replace a hard
280 register corresponding to a pseudo
281 assigned to the reg to be eliminated. */
282 rtx to_rtx; /* REG rtx for the replacement. */
285 static struct elim_table *reg_eliminate = 0;
287 /* This is an intermediate structure to initialize the table. It has
288 exactly the members provided by ELIMINABLE_REGS. */
289 static const struct elim_table_1
293 } reg_eliminate_1[] =
295 /* If a set of eliminable registers was specified, define the table from it.
296 Otherwise, default to the normal case of the frame pointer being
297 replaced by the stack pointer. */
299 #ifdef ELIMINABLE_REGS
302 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
305 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
307 /* Record the number of pending eliminations that have an offset not equal
308 to their initial offset. If nonzero, we use a new copy of each
309 replacement result in any insns encountered. */
310 int num_not_at_initial_offset;
312 /* Count the number of registers that we may be able to eliminate. */
313 static int num_eliminable;
314 /* And the number of registers that are equivalent to a constant that
315 can be eliminated to frame_pointer / arg_pointer + constant. */
316 static int num_eliminable_invariants;
318 /* For each label, we record the offset of each elimination. If we reach
319 a label by more than one path and an offset differs, we cannot do the
320 elimination. This information is indexed by the difference of the
321 number of the label and the first label number. We can't offset the
322 pointer itself as this can cause problems on machines with segmented
323 memory. The first table is an array of flags that records whether we
324 have yet encountered a label and the second table is an array of arrays,
325 one entry in the latter array for each elimination. */
327 static int first_label_num;
328 static char *offsets_known_at;
329 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
331 VEC(reg_equivs_t,gc) *reg_equivs;
333 /* Stack of addresses where an rtx has been changed. We can undo the
334 changes by popping items off the stack and restoring the original
335 value at each location.
337 We use this simplistic undo capability rather than copy_rtx as copy_rtx
338 will not make a deep copy of a normally sharable rtx, such as
339 (const (plus (symbol_ref) (const_int))). If such an expression appears
340 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
341 rtx expression would be changed. See PR 42431. */
345 DEF_VEC_ALLOC_P(rtx_p,heap);
346 static VEC(rtx_p,heap) *substitute_stack;
348 /* Number of labels in the current function. */
350 static int num_labels;
352 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
353 static void maybe_fix_stack_asms (void);
354 static void copy_reloads (struct insn_chain *);
355 static void calculate_needs_all_insns (int);
356 static int find_reg (struct insn_chain *, int);
357 static void find_reload_regs (struct insn_chain *);
358 static void select_reload_regs (void);
359 static void delete_caller_save_insns (void);
361 static void spill_failure (rtx, enum reg_class);
362 static void count_spilled_pseudo (int, int, int);
363 static void delete_dead_insn (rtx);
364 static void alter_reg (int, int, bool);
365 static void set_label_offsets (rtx, rtx, int);
366 static void check_eliminable_occurrences (rtx);
367 static void elimination_effects (rtx, enum machine_mode);
368 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
369 static int eliminate_regs_in_insn (rtx, int);
370 static void update_eliminable_offsets (void);
371 static void mark_not_eliminable (rtx, const_rtx, void *);
372 static void set_initial_elim_offsets (void);
373 static bool verify_initial_elim_offsets (void);
374 static void set_initial_label_offsets (void);
375 static void set_offsets_for_label (rtx);
376 static void init_eliminable_invariants (rtx, bool);
377 static void init_elim_table (void);
378 static void free_reg_equiv (void);
379 static void update_eliminables (HARD_REG_SET *);
380 static void elimination_costs_in_insn (rtx);
381 static void spill_hard_reg (unsigned int, int);
382 static int finish_spills (int);
383 static void scan_paradoxical_subregs (rtx);
384 static void count_pseudo (int);
385 static void order_regs_for_reload (struct insn_chain *);
386 static void reload_as_needed (int);
387 static void forget_old_reloads_1 (rtx, const_rtx, void *);
388 static void forget_marked_reloads (regset);
389 static int reload_reg_class_lower (const void *, const void *);
390 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
392 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
394 static int reload_reg_free_p (unsigned int, int, enum reload_type);
395 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
397 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
399 static int allocate_reload_reg (struct insn_chain *, int, int);
400 static int conflicts_with_override (rtx);
401 static void failed_reload (rtx, int);
402 static int set_reload_reg (int, int);
403 static void choose_reload_regs_init (struct insn_chain *, rtx *);
404 static void choose_reload_regs (struct insn_chain *);
405 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
407 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
409 static void do_input_reload (struct insn_chain *, struct reload *, int);
410 static void do_output_reload (struct insn_chain *, struct reload *, int);
411 static void emit_reload_insns (struct insn_chain *);
412 static void delete_output_reload (rtx, int, int, rtx);
413 static void delete_address_reloads (rtx, rtx);
414 static void delete_address_reloads_1 (rtx, rtx, rtx);
415 static void inc_for_reload (rtx, rtx, rtx, int);
417 static void add_auto_inc_notes (rtx, rtx);
419 static void substitute (rtx *, const_rtx, rtx);
420 static bool gen_reload_chain_without_interm_reg_p (int, int);
421 static int reloads_conflict (int, int);
422 static rtx gen_reload (rtx, rtx, int, enum reload_type);
423 static rtx emit_insn_if_valid_for_reload (rtx);
425 /* Initialize the reload pass. This is called at the beginning of compilation
426 and may be called again if the target is reinitialized. */
433 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
434 Set spill_indirect_levels to the number of levels such addressing is
435 permitted, zero if it is not permitted at all. */
438 = gen_rtx_MEM (Pmode,
441 LAST_VIRTUAL_REGISTER + 1),
443 spill_indirect_levels = 0;
445 while (memory_address_p (QImode, tem))
447 spill_indirect_levels++;
448 tem = gen_rtx_MEM (Pmode, tem);
451 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
453 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
454 indirect_symref_ok = memory_address_p (QImode, tem);
456 /* See if reg+reg is a valid (and offsettable) address. */
458 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
460 tem = gen_rtx_PLUS (Pmode,
461 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
462 gen_rtx_REG (Pmode, i));
464 /* This way, we make sure that reg+reg is an offsettable address. */
465 tem = plus_constant (tem, 4);
467 if (memory_address_p (QImode, tem))
469 double_reg_address_ok = 1;
474 /* Initialize obstack for our rtl allocation. */
475 gcc_obstack_init (&reload_obstack);
476 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
478 INIT_REG_SET (&spilled_pseudos);
479 INIT_REG_SET (&changed_allocation_pseudos);
480 INIT_REG_SET (&pseudos_counted);
483 /* List of insn chains that are currently unused. */
484 static struct insn_chain *unused_insn_chains = 0;
486 /* Allocate an empty insn_chain structure. */
488 new_insn_chain (void)
490 struct insn_chain *c;
492 if (unused_insn_chains == 0)
494 c = XOBNEW (&reload_obstack, struct insn_chain);
495 INIT_REG_SET (&c->live_throughout);
496 INIT_REG_SET (&c->dead_or_set);
500 c = unused_insn_chains;
501 unused_insn_chains = c->next;
503 c->is_caller_save_insn = 0;
504 c->need_operand_change = 0;
510 /* Small utility function to set all regs in hard reg set TO which are
511 allocated to pseudos in regset FROM. */
514 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
517 reg_set_iterator rsi;
519 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
521 int r = reg_renumber[regno];
525 /* reload_combine uses the information from DF_LIVE_IN,
526 which might still contain registers that have not
527 actually been allocated since they have an
529 gcc_assert (ira_conflicts_p || reload_completed);
532 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
536 /* Replace all pseudos found in LOC with their corresponding
540 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
553 unsigned int regno = REGNO (x);
555 if (regno < FIRST_PSEUDO_REGISTER)
558 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
562 replace_pseudos_in (loc, mem_mode, usage);
566 if (reg_equiv_constant (regno))
567 *loc = reg_equiv_constant (regno);
568 else if (reg_equiv_invariant (regno))
569 *loc = reg_equiv_invariant (regno);
570 else if (reg_equiv_mem (regno))
571 *loc = reg_equiv_mem (regno);
572 else if (reg_equiv_address (regno))
573 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
576 gcc_assert (!REG_P (regno_reg_rtx[regno])
577 || REGNO (regno_reg_rtx[regno]) != regno);
578 *loc = regno_reg_rtx[regno];
583 else if (code == MEM)
585 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
589 /* Process each of our operands recursively. */
590 fmt = GET_RTX_FORMAT (code);
591 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
593 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
594 else if (*fmt == 'E')
595 for (j = 0; j < XVECLEN (x, i); j++)
596 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
599 /* Determine if the current function has an exception receiver block
600 that reaches the exit block via non-exceptional edges */
603 has_nonexceptional_receiver (void)
607 basic_block *tos, *worklist, bb;
609 /* If we're not optimizing, then just err on the safe side. */
613 /* First determine which blocks can reach exit via normal paths. */
614 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
617 bb->flags &= ~BB_REACHABLE;
619 /* Place the exit block on our worklist. */
620 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
621 *tos++ = EXIT_BLOCK_PTR;
623 /* Iterate: find everything reachable from what we've already seen. */
624 while (tos != worklist)
628 FOR_EACH_EDGE (e, ei, bb->preds)
629 if (!(e->flags & EDGE_ABNORMAL))
631 basic_block src = e->src;
633 if (!(src->flags & BB_REACHABLE))
635 src->flags |= BB_REACHABLE;
642 /* Now see if there's a reachable block with an exceptional incoming
645 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
648 /* No exceptional block reached exit unexceptionally. */
652 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
653 zero elements) to MAX_REG_NUM elements.
655 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
657 grow_reg_equivs (void)
659 int old_size = VEC_length (reg_equivs_t, reg_equivs);
660 int max_regno = max_reg_num ();
663 VEC_reserve (reg_equivs_t, gc, reg_equivs, max_regno);
664 for (i = old_size; i < max_regno; i++)
666 VEC_quick_insert (reg_equivs_t, reg_equivs, i, 0);
667 memset (VEC_index (reg_equivs_t, reg_equivs, i), 0, sizeof (reg_equivs_t));
673 /* Global variables used by reload and its subroutines. */
675 /* The current basic block while in calculate_elim_costs_all_insns. */
676 static basic_block elim_bb;
678 /* Set during calculate_needs if an insn needs register elimination. */
679 static int something_needs_elimination;
680 /* Set during calculate_needs if an insn needs an operand changed. */
681 static int something_needs_operands_changed;
682 /* Set by alter_regs if we spilled a register to the stack. */
683 static bool something_was_spilled;
685 /* Nonzero means we couldn't get enough spill regs. */
688 /* Temporary array of pseudo-register number. */
689 static int *temp_pseudo_reg_arr;
691 /* Main entry point for the reload pass.
693 FIRST is the first insn of the function being compiled.
695 GLOBAL nonzero means we were called from global_alloc
696 and should attempt to reallocate any pseudoregs that we
697 displace from hard regs we will use for reloads.
698 If GLOBAL is zero, we do not have enough information to do that,
699 so any pseudo reg that is spilled must go to the stack.
701 Return value is TRUE if reload likely left dead insns in the
702 stream and a DCE pass should be run to elimiante them. Else the
703 return value is FALSE. */
706 reload (rtx first, int global)
710 struct elim_table *ep;
714 /* Make sure even insns with volatile mem refs are recognizable. */
719 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
721 /* Make sure that the last insn in the chain
722 is not something that needs reloading. */
723 emit_note (NOTE_INSN_DELETED);
725 /* Enable find_equiv_reg to distinguish insns made by reload. */
726 reload_first_uid = get_max_uid ();
728 #ifdef SECONDARY_MEMORY_NEEDED
729 /* Initialize the secondary memory table. */
730 clear_secondary_mem ();
733 /* We don't have a stack slot for any spill reg yet. */
734 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
735 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
737 /* Initialize the save area information for caller-save, in case some
741 /* Compute which hard registers are now in use
742 as homes for pseudo registers.
743 This is done here rather than (eg) in global_alloc
744 because this point is reached even if not optimizing. */
745 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
748 /* A function that has a nonlocal label that can reach the exit
749 block via non-exceptional paths must save all call-saved
751 if (cfun->has_nonlocal_label
752 && has_nonexceptional_receiver ())
753 crtl->saves_all_registers = 1;
755 if (crtl->saves_all_registers)
756 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
757 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
758 df_set_regs_ever_live (i, true);
760 /* Find all the pseudo registers that didn't get hard regs
761 but do have known equivalent constants or memory slots.
762 These include parameters (known equivalent to parameter slots)
763 and cse'd or loop-moved constant memory addresses.
765 Record constant equivalents in reg_equiv_constant
766 so they will be substituted by find_reloads.
767 Record memory equivalents in reg_mem_equiv so they can
768 be substituted eventually by altering the REG-rtx's. */
771 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
772 reg_old_renumber = XCNEWVEC (short, max_regno);
773 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
774 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
775 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
777 CLEAR_HARD_REG_SET (bad_spill_regs_global);
779 init_eliminable_invariants (first, true);
782 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
783 stack slots to the pseudos that lack hard regs or equivalents.
784 Do not touch virtual registers. */
786 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
787 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
788 temp_pseudo_reg_arr[n++] = i;
791 /* Ask IRA to order pseudo-registers for better stack slot
793 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
795 for (i = 0; i < n; i++)
796 alter_reg (temp_pseudo_reg_arr[i], -1, false);
798 /* If we have some registers we think can be eliminated, scan all insns to
799 see if there is an insn that sets one of these registers to something
800 other than itself plus a constant. If so, the register cannot be
801 eliminated. Doing this scan here eliminates an extra pass through the
802 main reload loop in the most common case where register elimination
804 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
806 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
808 maybe_fix_stack_asms ();
810 insns_need_reload = 0;
811 something_needs_elimination = 0;
813 /* Initialize to -1, which means take the first spill register. */
816 /* Spill any hard regs that we know we can't eliminate. */
817 CLEAR_HARD_REG_SET (used_spill_regs);
818 /* There can be multiple ways to eliminate a register;
819 they should be listed adjacently.
820 Elimination for any register fails only if all possible ways fail. */
821 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
824 int can_eliminate = 0;
827 can_eliminate |= ep->can_eliminate;
830 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
832 spill_hard_reg (from, 1);
835 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
836 if (frame_pointer_needed)
837 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
839 finish_spills (global);
841 /* From now on, we may need to generate moves differently. We may also
842 allow modifications of insns which cause them to not be recognized.
843 Any such modifications will be cleaned up during reload itself. */
844 reload_in_progress = 1;
846 /* This loop scans the entire function each go-round
847 and repeats until one repetition spills no additional hard regs. */
850 int something_changed;
852 HOST_WIDE_INT starting_frame_size;
854 starting_frame_size = get_frame_size ();
855 something_was_spilled = false;
857 set_initial_elim_offsets ();
858 set_initial_label_offsets ();
860 /* For each pseudo register that has an equivalent location defined,
861 try to eliminate any eliminable registers (such as the frame pointer)
862 assuming initial offsets for the replacement register, which
865 If the resulting location is directly addressable, substitute
866 the MEM we just got directly for the old REG.
868 If it is not addressable but is a constant or the sum of a hard reg
869 and constant, it is probably not addressable because the constant is
870 out of range, in that case record the address; we will generate
871 hairy code to compute the address in a register each time it is
872 needed. Similarly if it is a hard register, but one that is not
873 valid as an address register.
875 If the location is not addressable, but does not have one of the
876 above forms, assign a stack slot. We have to do this to avoid the
877 potential of producing lots of reloads if, e.g., a location involves
878 a pseudo that didn't get a hard register and has an equivalent memory
879 location that also involves a pseudo that didn't get a hard register.
881 Perhaps at some point we will improve reload_when_needed handling
882 so this problem goes away. But that's very hairy. */
884 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
885 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
887 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
890 if (strict_memory_address_addr_space_p
891 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
893 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
894 else if (CONSTANT_P (XEXP (x, 0))
895 || (REG_P (XEXP (x, 0))
896 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
897 || (GET_CODE (XEXP (x, 0)) == PLUS
898 && REG_P (XEXP (XEXP (x, 0), 0))
899 && (REGNO (XEXP (XEXP (x, 0), 0))
900 < FIRST_PSEUDO_REGISTER)
901 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
902 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
905 /* Make a new stack slot. Then indicate that something
906 changed so we go back and recompute offsets for
907 eliminable registers because the allocation of memory
908 below might change some offset. reg_equiv_{mem,address}
909 will be set up for this pseudo on the next pass around
911 reg_equiv_memory_loc (i) = 0;
912 reg_equiv_init (i) = 0;
913 alter_reg (i, -1, true);
917 if (caller_save_needed)
920 /* If we allocated another stack slot, redo elimination bookkeeping. */
921 if (something_was_spilled || starting_frame_size != get_frame_size ())
923 if (starting_frame_size && crtl->stack_alignment_needed)
925 /* If we have a stack frame, we must align it now. The
926 stack size may be a part of the offset computation for
927 register elimination. So if this changes the stack size,
928 then repeat the elimination bookkeeping. We don't
929 realign when there is no stack, as that will cause a
930 stack frame when none is needed should
931 STARTING_FRAME_OFFSET not be already aligned to
933 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
934 if (starting_frame_size != get_frame_size ())
938 if (caller_save_needed)
940 save_call_clobbered_regs ();
941 /* That might have allocated new insn_chain structures. */
942 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
945 calculate_needs_all_insns (global);
947 if (! ira_conflicts_p)
948 /* Don't do it for IRA. We need this info because we don't
949 change live_throughout and dead_or_set for chains when IRA
951 CLEAR_REG_SET (&spilled_pseudos);
955 something_changed = 0;
957 /* If we allocated any new memory locations, make another pass
958 since it might have changed elimination offsets. */
959 if (something_was_spilled || starting_frame_size != get_frame_size ())
960 something_changed = 1;
962 /* Even if the frame size remained the same, we might still have
963 changed elimination offsets, e.g. if find_reloads called
964 force_const_mem requiring the back end to allocate a constant
965 pool base register that needs to be saved on the stack. */
966 else if (!verify_initial_elim_offsets ())
967 something_changed = 1;
970 HARD_REG_SET to_spill;
971 CLEAR_HARD_REG_SET (to_spill);
972 update_eliminables (&to_spill);
973 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
975 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
976 if (TEST_HARD_REG_BIT (to_spill, i))
978 spill_hard_reg (i, 1);
981 /* Regardless of the state of spills, if we previously had
982 a register that we thought we could eliminate, but now can
983 not eliminate, we must run another pass.
985 Consider pseudos which have an entry in reg_equiv_* which
986 reference an eliminable register. We must make another pass
987 to update reg_equiv_* so that we do not substitute in the
988 old value from when we thought the elimination could be
990 something_changed = 1;
994 select_reload_regs ();
998 if (insns_need_reload != 0 || did_spill)
999 something_changed |= finish_spills (global);
1001 if (! something_changed)
1004 if (caller_save_needed)
1005 delete_caller_save_insns ();
1007 obstack_free (&reload_obstack, reload_firstobj);
1010 /* If global-alloc was run, notify it of any register eliminations we have
1013 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1014 if (ep->can_eliminate)
1015 mark_elimination (ep->from, ep->to);
1017 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1018 If that insn didn't set the register (i.e., it copied the register to
1019 memory), just delete that insn instead of the equivalencing insn plus
1020 anything now dead. If we call delete_dead_insn on that insn, we may
1021 delete the insn that actually sets the register if the register dies
1022 there and that is incorrect. */
1024 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1026 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
1029 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
1031 rtx equiv_insn = XEXP (list, 0);
1033 /* If we already deleted the insn or if it may trap, we can't
1034 delete it. The latter case shouldn't happen, but can
1035 if an insn has a variable address, gets a REG_EH_REGION
1036 note added to it, and then gets converted into a load
1037 from a constant address. */
1038 if (NOTE_P (equiv_insn)
1039 || can_throw_internal (equiv_insn))
1041 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1042 delete_dead_insn (equiv_insn);
1044 SET_INSN_DELETED (equiv_insn);
1049 /* Use the reload registers where necessary
1050 by generating move instructions to move the must-be-register
1051 values into or out of the reload registers. */
1053 if (insns_need_reload != 0 || something_needs_elimination
1054 || something_needs_operands_changed)
1056 HOST_WIDE_INT old_frame_size = get_frame_size ();
1058 reload_as_needed (global);
1060 gcc_assert (old_frame_size == get_frame_size ());
1062 gcc_assert (verify_initial_elim_offsets ());
1065 /* If we were able to eliminate the frame pointer, show that it is no
1066 longer live at the start of any basic block. If it ls live by
1067 virtue of being in a pseudo, that pseudo will be marked live
1068 and hence the frame pointer will be known to be live via that
1071 if (! frame_pointer_needed)
1073 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1075 /* Come here (with failure set nonzero) if we can't get enough spill
1079 CLEAR_REG_SET (&changed_allocation_pseudos);
1080 CLEAR_REG_SET (&spilled_pseudos);
1081 reload_in_progress = 0;
1083 /* Now eliminate all pseudo regs by modifying them into
1084 their equivalent memory references.
1085 The REG-rtx's for the pseudos are modified in place,
1086 so all insns that used to refer to them now refer to memory.
1088 For a reg that has a reg_equiv_address, all those insns
1089 were changed by reloading so that no insns refer to it any longer;
1090 but the DECL_RTL of a variable decl may refer to it,
1091 and if so this causes the debugging info to mention the variable. */
1093 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1097 if (reg_equiv_mem (i))
1098 addr = XEXP (reg_equiv_mem (i), 0);
1100 if (reg_equiv_address (i))
1101 addr = reg_equiv_address (i);
1105 if (reg_renumber[i] < 0)
1107 rtx reg = regno_reg_rtx[i];
1109 REG_USERVAR_P (reg) = 0;
1110 PUT_CODE (reg, MEM);
1111 XEXP (reg, 0) = addr;
1112 if (reg_equiv_memory_loc (i))
1113 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1116 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1117 MEM_ATTRS (reg) = 0;
1119 MEM_NOTRAP_P (reg) = 1;
1121 else if (reg_equiv_mem (i))
1122 XEXP (reg_equiv_mem (i), 0) = addr;
1125 /* We don't want complex addressing modes in debug insns
1126 if simpler ones will do, so delegitimize equivalences
1128 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1130 rtx reg = regno_reg_rtx[i];
1134 if (reg_equiv_constant (i))
1135 equiv = reg_equiv_constant (i);
1136 else if (reg_equiv_invariant (i))
1137 equiv = reg_equiv_invariant (i);
1138 else if (reg && MEM_P (reg))
1139 equiv = targetm.delegitimize_address (reg);
1140 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1146 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1148 insn = DF_REF_INSN (use);
1150 /* Make sure the next ref is for a different instruction,
1151 so that we're not affected by the rescan. */
1152 next = DF_REF_NEXT_REG (use);
1153 while (next && DF_REF_INSN (next) == insn)
1154 next = DF_REF_NEXT_REG (next);
1156 if (DEBUG_INSN_P (insn))
1160 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1161 df_insn_rescan_debug_internal (insn);
1164 INSN_VAR_LOCATION_LOC (insn)
1165 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1172 /* We must set reload_completed now since the cleanup_subreg_operands call
1173 below will re-recognize each insn and reload may have generated insns
1174 which are only valid during and after reload. */
1175 reload_completed = 1;
1177 /* Make a pass over all the insns and delete all USEs which we inserted
1178 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1179 notes. Delete all CLOBBER insns, except those that refer to the return
1180 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1181 from misarranging variable-array code, and simplify (subreg (reg))
1182 operands. Strip and regenerate REG_INC notes that may have been moved
1185 for (insn = first; insn; insn = NEXT_INSN (insn))
1191 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1192 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1194 if ((GET_CODE (PATTERN (insn)) == USE
1195 /* We mark with QImode USEs introduced by reload itself. */
1196 && (GET_MODE (insn) == QImode
1197 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1198 || (GET_CODE (PATTERN (insn)) == CLOBBER
1199 && (!MEM_P (XEXP (PATTERN (insn), 0))
1200 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1201 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1202 && XEXP (XEXP (PATTERN (insn), 0), 0)
1203 != stack_pointer_rtx))
1204 && (!REG_P (XEXP (PATTERN (insn), 0))
1205 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1211 /* Some CLOBBERs may survive until here and still reference unassigned
1212 pseudos with const equivalent, which may in turn cause ICE in later
1213 passes if the reference remains in place. */
1214 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1215 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1216 VOIDmode, PATTERN (insn));
1218 /* Discard obvious no-ops, even without -O. This optimization
1219 is fast and doesn't interfere with debugging. */
1220 if (NONJUMP_INSN_P (insn)
1221 && GET_CODE (PATTERN (insn)) == SET
1222 && REG_P (SET_SRC (PATTERN (insn)))
1223 && REG_P (SET_DEST (PATTERN (insn)))
1224 && (REGNO (SET_SRC (PATTERN (insn)))
1225 == REGNO (SET_DEST (PATTERN (insn)))))
1231 pnote = ®_NOTES (insn);
1234 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1235 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1236 || REG_NOTE_KIND (*pnote) == REG_INC)
1237 *pnote = XEXP (*pnote, 1);
1239 pnote = &XEXP (*pnote, 1);
1243 add_auto_inc_notes (insn, PATTERN (insn));
1246 /* Simplify (subreg (reg)) if it appears as an operand. */
1247 cleanup_subreg_operands (insn);
1249 /* Clean up invalid ASMs so that they don't confuse later passes.
1251 if (asm_noperands (PATTERN (insn)) >= 0)
1253 extract_insn (insn);
1254 if (!constrain_operands (1))
1256 error_for_asm (insn,
1257 "%<asm%> operand has impossible constraints");
1264 /* If we are doing generic stack checking, give a warning if this
1265 function's frame size is larger than we expect. */
1266 if (flag_stack_check == GENERIC_STACK_CHECK)
1268 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1269 static int verbose_warned = 0;
1271 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1272 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1273 size += UNITS_PER_WORD;
1275 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1277 warning (0, "frame size too large for reliable stack checking");
1278 if (! verbose_warned)
1280 warning (0, "try reducing the number of local variables");
1286 free (temp_pseudo_reg_arr);
1288 /* Indicate that we no longer have known memory locations or constants. */
1291 free (reg_max_ref_width);
1292 free (reg_old_renumber);
1293 free (pseudo_previous_regs);
1294 free (pseudo_forbidden_regs);
1296 CLEAR_HARD_REG_SET (used_spill_regs);
1297 for (i = 0; i < n_spills; i++)
1298 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1300 /* Free all the insn_chain structures at once. */
1301 obstack_free (&reload_obstack, reload_startobj);
1302 unused_insn_chains = 0;
1304 inserted = fixup_abnormal_edges ();
1306 /* We've possibly turned single trapping insn into multiple ones. */
1307 if (cfun->can_throw_non_call_exceptions)
1310 blocks = sbitmap_alloc (last_basic_block);
1311 sbitmap_ones (blocks);
1312 find_many_sub_basic_blocks (blocks);
1313 sbitmap_free (blocks);
1317 commit_edge_insertions ();
1319 /* Replacing pseudos with their memory equivalents might have
1320 created shared rtx. Subsequent passes would get confused
1321 by this, so unshare everything here. */
1322 unshare_all_rtl_again (first);
1324 #ifdef STACK_BOUNDARY
1325 /* init_emit has set the alignment of the hard frame pointer
1326 to STACK_BOUNDARY. It is very likely no longer valid if
1327 the hard frame pointer was used for register allocation. */
1328 if (!frame_pointer_needed)
1329 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1332 VEC_free (rtx_p, heap, substitute_stack);
1334 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1336 reload_completed = !failure;
1341 /* Yet another special case. Unfortunately, reg-stack forces people to
1342 write incorrect clobbers in asm statements. These clobbers must not
1343 cause the register to appear in bad_spill_regs, otherwise we'll call
1344 fatal_insn later. We clear the corresponding regnos in the live
1345 register sets to avoid this.
1346 The whole thing is rather sick, I'm afraid. */
1349 maybe_fix_stack_asms (void)
1352 const char *constraints[MAX_RECOG_OPERANDS];
1353 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1354 struct insn_chain *chain;
1356 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1359 HARD_REG_SET clobbered, allowed;
1362 if (! INSN_P (chain->insn)
1363 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1365 pat = PATTERN (chain->insn);
1366 if (GET_CODE (pat) != PARALLEL)
1369 CLEAR_HARD_REG_SET (clobbered);
1370 CLEAR_HARD_REG_SET (allowed);
1372 /* First, make a mask of all stack regs that are clobbered. */
1373 for (i = 0; i < XVECLEN (pat, 0); i++)
1375 rtx t = XVECEXP (pat, 0, i);
1376 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1377 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1380 /* Get the operand values and constraints out of the insn. */
1381 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1382 constraints, operand_mode, NULL);
1384 /* For every operand, see what registers are allowed. */
1385 for (i = 0; i < noperands; i++)
1387 const char *p = constraints[i];
1388 /* For every alternative, we compute the class of registers allowed
1389 for reloading in CLS, and merge its contents into the reg set
1391 int cls = (int) NO_REGS;
1397 if (c == '\0' || c == ',' || c == '#')
1399 /* End of one alternative - mark the regs in the current
1400 class, and reset the class. */
1401 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1407 } while (c != '\0' && c != ',');
1415 case '=': case '+': case '*': case '%': case '?': case '!':
1416 case '0': case '1': case '2': case '3': case '4': case '<':
1417 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1418 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1419 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1420 case TARGET_MEM_CONSTRAINT:
1424 cls = (int) reg_class_subunion[cls]
1425 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1430 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1434 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1435 cls = (int) reg_class_subunion[cls]
1436 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1438 cls = (int) reg_class_subunion[cls]
1439 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1441 p += CONSTRAINT_LEN (c, p);
1444 /* Those of the registers which are clobbered, but allowed by the
1445 constraints, must be usable as reload registers. So clear them
1446 out of the life information. */
1447 AND_HARD_REG_SET (allowed, clobbered);
1448 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1449 if (TEST_HARD_REG_BIT (allowed, i))
1451 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1452 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1459 /* Copy the global variables n_reloads and rld into the corresponding elts
1462 copy_reloads (struct insn_chain *chain)
1464 chain->n_reloads = n_reloads;
1465 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1466 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1467 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1470 /* Walk the chain of insns, and determine for each whether it needs reloads
1471 and/or eliminations. Build the corresponding insns_need_reload list, and
1472 set something_needs_elimination as appropriate. */
1474 calculate_needs_all_insns (int global)
1476 struct insn_chain **pprev_reload = &insns_need_reload;
1477 struct insn_chain *chain, *next = 0;
1479 something_needs_elimination = 0;
1481 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1482 for (chain = reload_insn_chain; chain != 0; chain = next)
1484 rtx insn = chain->insn;
1488 /* Clear out the shortcuts. */
1489 chain->n_reloads = 0;
1490 chain->need_elim = 0;
1491 chain->need_reload = 0;
1492 chain->need_operand_change = 0;
1494 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1495 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1496 what effects this has on the known offsets at labels. */
1498 if (LABEL_P (insn) || JUMP_P (insn)
1499 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1500 set_label_offsets (insn, insn, 0);
1504 rtx old_body = PATTERN (insn);
1505 int old_code = INSN_CODE (insn);
1506 rtx old_notes = REG_NOTES (insn);
1507 int did_elimination = 0;
1508 int operands_changed = 0;
1509 rtx set = single_set (insn);
1511 /* Skip insns that only set an equivalence. */
1512 if (set && REG_P (SET_DEST (set))
1513 && reg_renumber[REGNO (SET_DEST (set))] < 0
1514 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1515 || (reg_equiv_invariant (REGNO (SET_DEST (set)))))
1516 && reg_equiv_init (REGNO (SET_DEST (set))))
1519 /* If needed, eliminate any eliminable registers. */
1520 if (num_eliminable || num_eliminable_invariants)
1521 did_elimination = eliminate_regs_in_insn (insn, 0);
1523 /* Analyze the instruction. */
1524 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1525 global, spill_reg_order);
1527 /* If a no-op set needs more than one reload, this is likely
1528 to be something that needs input address reloads. We
1529 can't get rid of this cleanly later, and it is of no use
1530 anyway, so discard it now.
1531 We only do this when expensive_optimizations is enabled,
1532 since this complements reload inheritance / output
1533 reload deletion, and it can make debugging harder. */
1534 if (flag_expensive_optimizations && n_reloads > 1)
1536 rtx set = single_set (insn);
1539 ((SET_SRC (set) == SET_DEST (set)
1540 && REG_P (SET_SRC (set))
1541 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1542 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1543 && reg_renumber[REGNO (SET_SRC (set))] < 0
1544 && reg_renumber[REGNO (SET_DEST (set))] < 0
1545 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1546 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1547 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1548 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1550 if (ira_conflicts_p)
1551 /* Inform IRA about the insn deletion. */
1552 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1553 REGNO (SET_SRC (set)));
1555 /* Delete it from the reload chain. */
1557 chain->prev->next = next;
1559 reload_insn_chain = next;
1561 next->prev = chain->prev;
1562 chain->next = unused_insn_chains;
1563 unused_insn_chains = chain;
1568 update_eliminable_offsets ();
1570 /* Remember for later shortcuts which insns had any reloads or
1571 register eliminations. */
1572 chain->need_elim = did_elimination;
1573 chain->need_reload = n_reloads > 0;
1574 chain->need_operand_change = operands_changed;
1576 /* Discard any register replacements done. */
1577 if (did_elimination)
1579 obstack_free (&reload_obstack, reload_insn_firstobj);
1580 PATTERN (insn) = old_body;
1581 INSN_CODE (insn) = old_code;
1582 REG_NOTES (insn) = old_notes;
1583 something_needs_elimination = 1;
1586 something_needs_operands_changed |= operands_changed;
1590 copy_reloads (chain);
1591 *pprev_reload = chain;
1592 pprev_reload = &chain->next_need_reload;
1599 /* This function is called from the register allocator to set up estimates
1600 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1601 an invariant. The structure is similar to calculate_needs_all_insns. */
1604 calculate_elim_costs_all_insns (void)
1606 int *reg_equiv_init_cost;
1610 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1612 init_eliminable_invariants (get_insns (), false);
1614 set_initial_elim_offsets ();
1615 set_initial_label_offsets ();
1622 FOR_BB_INSNS (bb, insn)
1624 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1625 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1626 what effects this has on the known offsets at labels. */
1628 if (LABEL_P (insn) || JUMP_P (insn)
1629 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1630 set_label_offsets (insn, insn, 0);
1634 rtx set = single_set (insn);
1636 /* Skip insns that only set an equivalence. */
1637 if (set && REG_P (SET_DEST (set))
1638 && reg_renumber[REGNO (SET_DEST (set))] < 0
1639 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1640 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1642 unsigned regno = REGNO (SET_DEST (set));
1643 rtx init = reg_equiv_init (regno);
1646 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1648 int cost = set_src_cost (t, optimize_bb_for_speed_p (bb));
1649 int freq = REG_FREQ_FROM_BB (bb);
1651 reg_equiv_init_cost[regno] = cost * freq;
1655 /* If needed, eliminate any eliminable registers. */
1656 if (num_eliminable || num_eliminable_invariants)
1657 elimination_costs_in_insn (insn);
1660 update_eliminable_offsets ();
1664 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1666 if (reg_equiv_invariant (i))
1668 if (reg_equiv_init (i))
1670 int cost = reg_equiv_init_cost[i];
1673 "Reg %d has equivalence, initial gains %d\n", i, cost);
1675 ira_adjust_equiv_reg_cost (i, cost);
1681 "Reg %d had equivalence, but can't be eliminated\n",
1683 ira_adjust_equiv_reg_cost (i, 0);
1688 free (reg_equiv_init_cost);
1691 /* Comparison function for qsort to decide which of two reloads
1692 should be handled first. *P1 and *P2 are the reload numbers. */
1695 reload_reg_class_lower (const void *r1p, const void *r2p)
1697 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1700 /* Consider required reloads before optional ones. */
1701 t = rld[r1].optional - rld[r2].optional;
1705 /* Count all solitary classes before non-solitary ones. */
1706 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1707 - (reg_class_size[(int) rld[r1].rclass] == 1));
1711 /* Aside from solitaires, consider all multi-reg groups first. */
1712 t = rld[r2].nregs - rld[r1].nregs;
1716 /* Consider reloads in order of increasing reg-class number. */
1717 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1721 /* If reloads are equally urgent, sort by reload number,
1722 so that the results of qsort leave nothing to chance. */
1726 /* The cost of spilling each hard reg. */
1727 static int spill_cost[FIRST_PSEUDO_REGISTER];
1729 /* When spilling multiple hard registers, we use SPILL_COST for the first
1730 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1731 only the first hard reg for a multi-reg pseudo. */
1732 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1734 /* Map of hard regno to pseudo regno currently occupying the hard
1736 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1738 /* Update the spill cost arrays, considering that pseudo REG is live. */
1741 count_pseudo (int reg)
1743 int freq = REG_FREQ (reg);
1744 int r = reg_renumber[reg];
1747 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1748 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1749 /* Ignore spilled pseudo-registers which can be here only if IRA
1751 || (ira_conflicts_p && r < 0))
1754 SET_REGNO_REG_SET (&pseudos_counted, reg);
1756 gcc_assert (r >= 0);
1758 spill_add_cost[r] += freq;
1759 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1762 hard_regno_to_pseudo_regno[r + nregs] = reg;
1763 spill_cost[r + nregs] += freq;
1767 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1768 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1771 order_regs_for_reload (struct insn_chain *chain)
1774 HARD_REG_SET used_by_pseudos;
1775 HARD_REG_SET used_by_pseudos2;
1776 reg_set_iterator rsi;
1778 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1780 memset (spill_cost, 0, sizeof spill_cost);
1781 memset (spill_add_cost, 0, sizeof spill_add_cost);
1782 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1783 hard_regno_to_pseudo_regno[i] = -1;
1785 /* Count number of uses of each hard reg by pseudo regs allocated to it
1786 and then order them by decreasing use. First exclude hard registers
1787 that are live in or across this insn. */
1789 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1790 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1791 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1792 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1794 /* Now find out which pseudos are allocated to it, and update
1796 CLEAR_REG_SET (&pseudos_counted);
1798 EXECUTE_IF_SET_IN_REG_SET
1799 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1803 EXECUTE_IF_SET_IN_REG_SET
1804 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1808 CLEAR_REG_SET (&pseudos_counted);
1811 /* Vector of reload-numbers showing the order in which the reloads should
1813 static short reload_order[MAX_RELOADS];
1815 /* This is used to keep track of the spill regs used in one insn. */
1816 static HARD_REG_SET used_spill_regs_local;
1818 /* We decided to spill hard register SPILLED, which has a size of
1819 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1820 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1821 update SPILL_COST/SPILL_ADD_COST. */
1824 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1826 int freq = REG_FREQ (reg);
1827 int r = reg_renumber[reg];
1828 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1830 /* Ignore spilled pseudo-registers which can be here only if IRA is
1832 if ((ira_conflicts_p && r < 0)
1833 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1834 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1837 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1839 spill_add_cost[r] -= freq;
1842 hard_regno_to_pseudo_regno[r + nregs] = -1;
1843 spill_cost[r + nregs] -= freq;
1847 /* Find reload register to use for reload number ORDER. */
1850 find_reg (struct insn_chain *chain, int order)
1852 int rnum = reload_order[order];
1853 struct reload *rl = rld + rnum;
1854 int best_cost = INT_MAX;
1856 unsigned int i, j, n;
1858 HARD_REG_SET not_usable;
1859 HARD_REG_SET used_by_other_reload;
1860 reg_set_iterator rsi;
1861 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1862 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1864 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1865 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1866 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1868 CLEAR_HARD_REG_SET (used_by_other_reload);
1869 for (k = 0; k < order; k++)
1871 int other = reload_order[k];
1873 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1874 for (j = 0; j < rld[other].nregs; j++)
1875 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1878 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1880 #ifdef REG_ALLOC_ORDER
1881 unsigned int regno = reg_alloc_order[i];
1883 unsigned int regno = i;
1886 if (! TEST_HARD_REG_BIT (not_usable, regno)
1887 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1888 && HARD_REGNO_MODE_OK (regno, rl->mode))
1890 int this_cost = spill_cost[regno];
1892 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1894 for (j = 1; j < this_nregs; j++)
1896 this_cost += spill_add_cost[regno + j];
1897 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1898 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1904 if (ira_conflicts_p)
1906 /* Ask IRA to find a better pseudo-register for
1908 for (n = j = 0; j < this_nregs; j++)
1910 int r = hard_regno_to_pseudo_regno[regno + j];
1914 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1915 regno_pseudo_regs[n++] = r;
1917 regno_pseudo_regs[n++] = -1;
1919 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1920 best_regno_pseudo_regs,
1927 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1928 if (regno_pseudo_regs[j] < 0)
1935 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1937 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1939 if (this_cost < best_cost
1940 /* Among registers with equal cost, prefer caller-saved ones, or
1941 use REG_ALLOC_ORDER if it is defined. */
1942 || (this_cost == best_cost
1943 #ifdef REG_ALLOC_ORDER
1944 && (inv_reg_alloc_order[regno]
1945 < inv_reg_alloc_order[best_reg])
1947 && call_used_regs[regno]
1948 && ! call_used_regs[best_reg]
1953 best_cost = this_cost;
1961 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1963 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1964 rl->regno = best_reg;
1966 EXECUTE_IF_SET_IN_REG_SET
1967 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1969 count_spilled_pseudo (best_reg, rl->nregs, j);
1972 EXECUTE_IF_SET_IN_REG_SET
1973 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1975 count_spilled_pseudo (best_reg, rl->nregs, j);
1978 for (i = 0; i < rl->nregs; i++)
1980 gcc_assert (spill_cost[best_reg + i] == 0);
1981 gcc_assert (spill_add_cost[best_reg + i] == 0);
1982 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1983 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1988 /* Find more reload regs to satisfy the remaining need of an insn, which
1990 Do it by ascending class number, since otherwise a reg
1991 might be spilled for a big class and might fail to count
1992 for a smaller class even though it belongs to that class. */
1995 find_reload_regs (struct insn_chain *chain)
1999 /* In order to be certain of getting the registers we need,
2000 we must sort the reloads into order of increasing register class.
2001 Then our grabbing of reload registers will parallel the process
2002 that provided the reload registers. */
2003 for (i = 0; i < chain->n_reloads; i++)
2005 /* Show whether this reload already has a hard reg. */
2006 if (chain->rld[i].reg_rtx)
2008 int regno = REGNO (chain->rld[i].reg_rtx);
2009 chain->rld[i].regno = regno;
2011 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2014 chain->rld[i].regno = -1;
2015 reload_order[i] = i;
2018 n_reloads = chain->n_reloads;
2019 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2021 CLEAR_HARD_REG_SET (used_spill_regs_local);
2024 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2026 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2028 /* Compute the order of preference for hard registers to spill. */
2030 order_regs_for_reload (chain);
2032 for (i = 0; i < n_reloads; i++)
2034 int r = reload_order[i];
2036 /* Ignore reloads that got marked inoperative. */
2037 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2038 && ! rld[r].optional
2039 && rld[r].regno == -1)
2040 if (! find_reg (chain, i))
2043 fprintf (dump_file, "reload failure for reload %d\n", r);
2044 spill_failure (chain->insn, rld[r].rclass);
2050 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2051 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2053 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2057 select_reload_regs (void)
2059 struct insn_chain *chain;
2061 /* Try to satisfy the needs for each insn. */
2062 for (chain = insns_need_reload; chain != 0;
2063 chain = chain->next_need_reload)
2064 find_reload_regs (chain);
2067 /* Delete all insns that were inserted by emit_caller_save_insns during
2070 delete_caller_save_insns (void)
2072 struct insn_chain *c = reload_insn_chain;
2076 while (c != 0 && c->is_caller_save_insn)
2078 struct insn_chain *next = c->next;
2081 if (c == reload_insn_chain)
2082 reload_insn_chain = next;
2086 next->prev = c->prev;
2088 c->prev->next = next;
2089 c->next = unused_insn_chains;
2090 unused_insn_chains = c;
2098 /* Handle the failure to find a register to spill.
2099 INSN should be one of the insns which needed this particular spill reg. */
2102 spill_failure (rtx insn, enum reg_class rclass)
2104 if (asm_noperands (PATTERN (insn)) >= 0)
2105 error_for_asm (insn, "can%'t find a register in class %qs while "
2106 "reloading %<asm%>",
2107 reg_class_names[rclass]);
2110 error ("unable to find a register to spill in class %qs",
2111 reg_class_names[rclass]);
2115 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2116 debug_reload_to_stream (dump_file);
2118 fatal_insn ("this is the insn:", insn);
2122 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2123 data that is dead in INSN. */
2126 delete_dead_insn (rtx insn)
2128 rtx prev = prev_active_insn (insn);
2131 /* If the previous insn sets a register that dies in our insn make
2132 a note that we want to run DCE immediately after reload.
2134 We used to delete the previous insn & recurse, but that's wrong for
2135 block local equivalences. Instead of trying to figure out the exact
2136 circumstances where we can delete the potentially dead insns, just
2137 let DCE do the job. */
2138 if (prev && GET_CODE (PATTERN (prev)) == SET
2139 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2140 && reg_mentioned_p (prev_dest, PATTERN (insn))
2141 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2142 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2145 SET_INSN_DELETED (insn);
2148 /* Modify the home of pseudo-reg I.
2149 The new home is present in reg_renumber[I].
2151 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2152 or it may be -1, meaning there is none or it is not relevant.
2153 This is used so that all pseudos spilled from a given hard reg
2154 can share one stack slot. */
2157 alter_reg (int i, int from_reg, bool dont_share_p)
2159 /* When outputting an inline function, this can happen
2160 for a reg that isn't actually used. */
2161 if (regno_reg_rtx[i] == 0)
2164 /* If the reg got changed to a MEM at rtl-generation time,
2166 if (!REG_P (regno_reg_rtx[i]))
2169 /* Modify the reg-rtx to contain the new hard reg
2170 number or else to contain its pseudo reg number. */
2171 SET_REGNO (regno_reg_rtx[i],
2172 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2174 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2175 allocate a stack slot for it. */
2177 if (reg_renumber[i] < 0
2178 && REG_N_REFS (i) > 0
2179 && reg_equiv_constant (i) == 0
2180 && (reg_equiv_invariant (i) == 0
2181 || reg_equiv_init (i) == 0)
2182 && reg_equiv_memory_loc (i) == 0)
2185 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2186 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2187 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2188 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2189 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2192 something_was_spilled = true;
2194 if (ira_conflicts_p)
2196 /* Mark the spill for IRA. */
2197 SET_REGNO_REG_SET (&spilled_pseudos, i);
2199 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2205 /* Each pseudo reg has an inherent size which comes from its own mode,
2206 and a total size which provides room for paradoxical subregs
2207 which refer to the pseudo reg in wider modes.
2209 We can use a slot already allocated if it provides both
2210 enough inherent space and enough total space.
2211 Otherwise, we allocate a new slot, making sure that it has no less
2212 inherent space, and no less total space, then the previous slot. */
2213 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2217 /* No known place to spill from => no slot to reuse. */
2218 x = assign_stack_local (mode, total_size,
2219 min_align > inherent_align
2220 || total_size > inherent_size ? -1 : 0);
2224 /* Cancel the big-endian correction done in assign_stack_local.
2225 Get the address of the beginning of the slot. This is so we
2226 can do a big-endian correction unconditionally below. */
2227 if (BYTES_BIG_ENDIAN)
2229 adjust = inherent_size - total_size;
2232 = adjust_address_nv (x, mode_for_size (total_size
2238 if (! dont_share_p && ira_conflicts_p)
2239 /* Inform IRA about allocation a new stack slot. */
2240 ira_mark_new_stack_slot (stack_slot, i, total_size);
2243 /* Reuse a stack slot if possible. */
2244 else if (spill_stack_slot[from_reg] != 0
2245 && spill_stack_slot_width[from_reg] >= total_size
2246 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2248 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2249 x = spill_stack_slot[from_reg];
2251 /* Allocate a bigger slot. */
2254 /* Compute maximum size needed, both for inherent size
2255 and for total size. */
2258 if (spill_stack_slot[from_reg])
2260 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2262 mode = GET_MODE (spill_stack_slot[from_reg]);
2263 if (spill_stack_slot_width[from_reg] > total_size)
2264 total_size = spill_stack_slot_width[from_reg];
2265 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2266 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2269 /* Make a slot with that size. */
2270 x = assign_stack_local (mode, total_size,
2271 min_align > inherent_align
2272 || total_size > inherent_size ? -1 : 0);
2275 /* Cancel the big-endian correction done in assign_stack_local.
2276 Get the address of the beginning of the slot. This is so we
2277 can do a big-endian correction unconditionally below. */
2278 if (BYTES_BIG_ENDIAN)
2280 adjust = GET_MODE_SIZE (mode) - total_size;
2283 = adjust_address_nv (x, mode_for_size (total_size
2289 spill_stack_slot[from_reg] = stack_slot;
2290 spill_stack_slot_width[from_reg] = total_size;
2293 /* On a big endian machine, the "address" of the slot
2294 is the address of the low part that fits its inherent mode. */
2295 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2296 adjust += (total_size - inherent_size);
2298 /* If we have any adjustment to make, or if the stack slot is the
2299 wrong mode, make a new stack slot. */
2300 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2302 /* Set all of the memory attributes as appropriate for a spill. */
2303 set_mem_attrs_for_spill (x);
2305 /* Save the stack slot for later. */
2306 reg_equiv_memory_loc (i) = x;
2310 /* Mark the slots in regs_ever_live for the hard regs used by
2311 pseudo-reg number REGNO, accessed in MODE. */
2314 mark_home_live_1 (int regno, enum machine_mode mode)
2318 i = reg_renumber[regno];
2321 lim = end_hard_regno (mode, i);
2323 df_set_regs_ever_live(i++, true);
2326 /* Mark the slots in regs_ever_live for the hard regs
2327 used by pseudo-reg number REGNO. */
2330 mark_home_live (int regno)
2332 if (reg_renumber[regno] >= 0)
2333 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2336 /* This function handles the tracking of elimination offsets around branches.
2338 X is a piece of RTL being scanned.
2340 INSN is the insn that it came from, if any.
2342 INITIAL_P is nonzero if we are to set the offset to be the initial
2343 offset and zero if we are setting the offset of the label to be the
2347 set_label_offsets (rtx x, rtx insn, int initial_p)
2349 enum rtx_code code = GET_CODE (x);
2352 struct elim_table *p;
2357 if (LABEL_REF_NONLOCAL_P (x))
2362 /* ... fall through ... */
2365 /* If we know nothing about this label, set the desired offsets. Note
2366 that this sets the offset at a label to be the offset before a label
2367 if we don't know anything about the label. This is not correct for
2368 the label after a BARRIER, but is the best guess we can make. If
2369 we guessed wrong, we will suppress an elimination that might have
2370 been possible had we been able to guess correctly. */
2372 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2374 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2375 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2376 = (initial_p ? reg_eliminate[i].initial_offset
2377 : reg_eliminate[i].offset);
2378 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2381 /* Otherwise, if this is the definition of a label and it is
2382 preceded by a BARRIER, set our offsets to the known offset of
2386 && (tem = prev_nonnote_insn (insn)) != 0
2388 set_offsets_for_label (insn);
2390 /* If neither of the above cases is true, compare each offset
2391 with those previously recorded and suppress any eliminations
2392 where the offsets disagree. */
2394 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2395 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2396 != (initial_p ? reg_eliminate[i].initial_offset
2397 : reg_eliminate[i].offset))
2398 reg_eliminate[i].can_eliminate = 0;
2403 set_label_offsets (PATTERN (insn), insn, initial_p);
2405 /* ... fall through ... */
2409 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2410 to indirectly and hence must have all eliminations at their
2412 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2413 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2414 set_label_offsets (XEXP (tem, 0), insn, 1);
2420 /* Each of the labels in the parallel or address vector must be
2421 at their initial offsets. We want the first field for PARALLEL
2422 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2424 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2425 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2430 /* We only care about setting PC. If the source is not RETURN,
2431 IF_THEN_ELSE, or a label, disable any eliminations not at
2432 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2433 isn't one of those possibilities. For branches to a label,
2434 call ourselves recursively.
2436 Note that this can disable elimination unnecessarily when we have
2437 a non-local goto since it will look like a non-constant jump to
2438 someplace in the current function. This isn't a significant
2439 problem since such jumps will normally be when all elimination
2440 pairs are back to their initial offsets. */
2442 if (SET_DEST (x) != pc_rtx)
2445 switch (GET_CODE (SET_SRC (x)))
2452 set_label_offsets (SET_SRC (x), insn, initial_p);
2456 tem = XEXP (SET_SRC (x), 1);
2457 if (GET_CODE (tem) == LABEL_REF)
2458 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2459 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2462 tem = XEXP (SET_SRC (x), 2);
2463 if (GET_CODE (tem) == LABEL_REF)
2464 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2465 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2473 /* If we reach here, all eliminations must be at their initial
2474 offset because we are doing a jump to a variable address. */
2475 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2476 if (p->offset != p->initial_offset)
2477 p->can_eliminate = 0;
2485 /* Called through for_each_rtx, this function examines every reg that occurs
2486 in PX and adjusts the costs for its elimination which are gathered by IRA.
2487 DATA is the insn in which PX occurs. We do not recurse into MEM
2491 note_reg_elim_costly (rtx *px, void *data)
2493 rtx insn = (rtx)data;
2500 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2501 && reg_equiv_init (REGNO (x))
2502 && reg_equiv_invariant (REGNO (x)))
2504 rtx t = reg_equiv_invariant (REGNO (x));
2505 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2506 int cost = set_src_cost (new_rtx, optimize_bb_for_speed_p (elim_bb));
2507 int freq = REG_FREQ_FROM_BB (elim_bb);
2510 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2515 /* Scan X and replace any eliminable registers (such as fp) with a
2516 replacement (such as sp), plus an offset.
2518 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2519 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2520 MEM, we are allowed to replace a sum of a register and the constant zero
2521 with the register, which we cannot do outside a MEM. In addition, we need
2522 to record the fact that a register is referenced outside a MEM.
2524 If INSN is an insn, it is the insn containing X. If we replace a REG
2525 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2526 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2527 the REG is being modified.
2529 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2530 That's used when we eliminate in expressions stored in notes.
2531 This means, do not set ref_outside_mem even if the reference
2534 If FOR_COSTS is true, we are being called before reload in order to
2535 estimate the costs of keeping registers with an equivalence unallocated.
2537 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2538 replacements done assuming all offsets are at their initial values. If
2539 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2540 encounter, return the actual location so that find_reloads will do
2541 the proper thing. */
2544 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2545 bool may_use_invariant, bool for_costs)
2547 enum rtx_code code = GET_CODE (x);
2548 struct elim_table *ep;
2555 if (! current_function_decl)
2578 /* First handle the case where we encounter a bare register that
2579 is eliminable. Replace it with a PLUS. */
2580 if (regno < FIRST_PSEUDO_REGISTER)
2582 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2584 if (ep->from_rtx == x && ep->can_eliminate)
2585 return plus_constant (ep->to_rtx, ep->previous_offset);
2588 else if (reg_renumber && reg_renumber[regno] < 0
2590 && reg_equiv_invariant (regno))
2592 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2593 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2594 mem_mode, insn, true, for_costs);
2595 /* There exists at least one use of REGNO that cannot be
2596 eliminated. Prevent the defining insn from being deleted. */
2597 reg_equiv_init (regno) = NULL_RTX;
2599 alter_reg (regno, -1, true);
2603 /* You might think handling MINUS in a manner similar to PLUS is a
2604 good idea. It is not. It has been tried multiple times and every
2605 time the change has had to have been reverted.
2607 Other parts of reload know a PLUS is special (gen_reload for example)
2608 and require special code to handle code a reloaded PLUS operand.
2610 Also consider backends where the flags register is clobbered by a
2611 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2612 lea instruction comes to mind). If we try to reload a MINUS, we
2613 may kill the flags register that was holding a useful value.
2615 So, please before trying to handle MINUS, consider reload as a
2616 whole instead of this little section as well as the backend issues. */
2618 /* If this is the sum of an eliminable register and a constant, rework
2620 if (REG_P (XEXP (x, 0))
2621 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2622 && CONSTANT_P (XEXP (x, 1)))
2624 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2626 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2628 /* The only time we want to replace a PLUS with a REG (this
2629 occurs when the constant operand of the PLUS is the negative
2630 of the offset) is when we are inside a MEM. We won't want
2631 to do so at other times because that would change the
2632 structure of the insn in a way that reload can't handle.
2633 We special-case the commonest situation in
2634 eliminate_regs_in_insn, so just replace a PLUS with a
2635 PLUS here, unless inside a MEM. */
2636 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2637 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2640 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2641 plus_constant (XEXP (x, 1),
2642 ep->previous_offset));
2645 /* If the register is not eliminable, we are done since the other
2646 operand is a constant. */
2650 /* If this is part of an address, we want to bring any constant to the
2651 outermost PLUS. We will do this by doing register replacement in
2652 our operands and seeing if a constant shows up in one of them.
2654 Note that there is no risk of modifying the structure of the insn,
2655 since we only get called for its operands, thus we are either
2656 modifying the address inside a MEM, or something like an address
2657 operand of a load-address insn. */
2660 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2662 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2665 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2667 /* If one side is a PLUS and the other side is a pseudo that
2668 didn't get a hard register but has a reg_equiv_constant,
2669 we must replace the constant here since it may no longer
2670 be in the position of any operand. */
2671 if (GET_CODE (new0) == PLUS && REG_P (new1)
2672 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2673 && reg_renumber[REGNO (new1)] < 0
2675 && reg_equiv_constant (REGNO (new1)) != 0)
2676 new1 = reg_equiv_constant (REGNO (new1));
2677 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2678 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2679 && reg_renumber[REGNO (new0)] < 0
2680 && reg_equiv_constant (REGNO (new0)) != 0)
2681 new0 = reg_equiv_constant (REGNO (new0));
2683 new_rtx = form_sum (GET_MODE (x), new0, new1);
2685 /* As above, if we are not inside a MEM we do not want to
2686 turn a PLUS into something else. We might try to do so here
2687 for an addition of 0 if we aren't optimizing. */
2688 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2689 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2697 /* If this is the product of an eliminable register and a
2698 constant, apply the distribute law and move the constant out
2699 so that we have (plus (mult ..) ..). This is needed in order
2700 to keep load-address insns valid. This case is pathological.
2701 We ignore the possibility of overflow here. */
2702 if (REG_P (XEXP (x, 0))
2703 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2704 && CONST_INT_P (XEXP (x, 1)))
2705 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2707 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2710 /* Refs inside notes or in DEBUG_INSNs don't count for
2712 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2713 || GET_CODE (insn) == INSN_LIST
2714 || DEBUG_INSN_P (insn))))
2715 ep->ref_outside_mem = 1;
2718 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2719 ep->previous_offset * INTVAL (XEXP (x, 1)));
2722 /* ... fall through ... */
2726 /* See comments before PLUS about handling MINUS. */
2728 case DIV: case UDIV:
2729 case MOD: case UMOD:
2730 case AND: case IOR: case XOR:
2731 case ROTATERT: case ROTATE:
2732 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2734 case GE: case GT: case GEU: case GTU:
2735 case LE: case LT: case LEU: case LTU:
2737 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2739 rtx new1 = XEXP (x, 1)
2740 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2743 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2744 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2749 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2752 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2754 if (new_rtx != XEXP (x, 0))
2756 /* If this is a REG_DEAD note, it is not valid anymore.
2757 Using the eliminated version could result in creating a
2758 REG_DEAD note for the stack or frame pointer. */
2759 if (REG_NOTE_KIND (x) == REG_DEAD)
2761 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2765 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2769 /* ... fall through ... */
2772 /* Now do eliminations in the rest of the chain. If this was
2773 an EXPR_LIST, this might result in allocating more memory than is
2774 strictly needed, but it simplifies the code. */
2777 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2779 if (new_rtx != XEXP (x, 1))
2781 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2789 /* We do not support elimination of a register that is modified.
2790 elimination_effects has already make sure that this does not
2796 /* We do not support elimination of a register that is modified.
2797 elimination_effects has already make sure that this does not
2798 happen. The only remaining case we need to consider here is
2799 that the increment value may be an eliminable register. */
2800 if (GET_CODE (XEXP (x, 1)) == PLUS
2801 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2803 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2804 insn, true, for_costs);
2806 if (new_rtx != XEXP (XEXP (x, 1), 1))
2807 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2808 gen_rtx_PLUS (GET_MODE (x),
2809 XEXP (x, 0), new_rtx));
2813 case STRICT_LOW_PART:
2815 case SIGN_EXTEND: case ZERO_EXTEND:
2816 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2817 case FLOAT: case FIX:
2818 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2827 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2829 if (new_rtx != XEXP (x, 0))
2830 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2834 /* Similar to above processing, but preserve SUBREG_BYTE.
2835 Convert (subreg (mem)) to (mem) if not paradoxical.
2836 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2837 pseudo didn't get a hard reg, we must replace this with the
2838 eliminated version of the memory location because push_reload
2839 may do the replacement in certain circumstances. */
2840 if (REG_P (SUBREG_REG (x))
2841 && !paradoxical_subreg_p (x)
2843 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2845 new_rtx = SUBREG_REG (x);
2848 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2850 if (new_rtx != SUBREG_REG (x))
2852 int x_size = GET_MODE_SIZE (GET_MODE (x));
2853 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2856 && ((x_size < new_size
2857 #ifdef WORD_REGISTER_OPERATIONS
2858 /* On these machines, combine can create rtl of the form
2859 (set (subreg:m1 (reg:m2 R) 0) ...)
2860 where m1 < m2, and expects something interesting to
2861 happen to the entire word. Moreover, it will use the
2862 (reg:m2 R) later, expecting all bits to be preserved.
2863 So if the number of words is the same, preserve the
2864 subreg so that push_reload can see it. */
2865 && ! ((x_size - 1) / UNITS_PER_WORD
2866 == (new_size -1 ) / UNITS_PER_WORD)
2869 || x_size == new_size)
2871 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2873 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2879 /* Our only special processing is to pass the mode of the MEM to our
2880 recursive call and copy the flags. While we are here, handle this
2881 case more efficiently. */
2883 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2886 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2887 && !memory_address_p (GET_MODE (x), new_rtx))
2888 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2890 return replace_equiv_address_nv (x, new_rtx);
2893 /* Handle insn_list USE that a call to a pure function may generate. */
2894 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2896 if (new_rtx != XEXP (x, 0))
2897 return gen_rtx_USE (GET_MODE (x), new_rtx);
2902 gcc_assert (insn && DEBUG_INSN_P (insn));
2912 /* Process each of our operands recursively. If any have changed, make a
2914 fmt = GET_RTX_FORMAT (code);
2915 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2919 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2921 if (new_rtx != XEXP (x, i) && ! copied)
2923 x = shallow_copy_rtx (x);
2926 XEXP (x, i) = new_rtx;
2928 else if (*fmt == 'E')
2931 for (j = 0; j < XVECLEN (x, i); j++)
2933 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2935 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2937 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2941 x = shallow_copy_rtx (x);
2944 XVEC (x, i) = new_v;
2947 XVECEXP (x, i, j) = new_rtx;
2956 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2958 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2961 /* Scan rtx X for modifications of elimination target registers. Update
2962 the table of eliminables to reflect the changed state. MEM_MODE is
2963 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2966 elimination_effects (rtx x, enum machine_mode mem_mode)
2968 enum rtx_code code = GET_CODE (x);
2969 struct elim_table *ep;
2994 /* First handle the case where we encounter a bare register that
2995 is eliminable. Replace it with a PLUS. */
2996 if (regno < FIRST_PSEUDO_REGISTER)
2998 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3000 if (ep->from_rtx == x && ep->can_eliminate)
3003 ep->ref_outside_mem = 1;
3008 else if (reg_renumber[regno] < 0
3010 && reg_equiv_constant (regno)
3011 && ! function_invariant_p (reg_equiv_constant (regno)))
3012 elimination_effects (reg_equiv_constant (regno), mem_mode);
3021 /* If we modify the source of an elimination rule, disable it. */
3022 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3023 if (ep->from_rtx == XEXP (x, 0))
3024 ep->can_eliminate = 0;
3026 /* If we modify the target of an elimination rule by adding a constant,
3027 update its offset. If we modify the target in any other way, we'll
3028 have to disable the rule as well. */
3029 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3030 if (ep->to_rtx == XEXP (x, 0))
3032 int size = GET_MODE_SIZE (mem_mode);
3034 /* If more bytes than MEM_MODE are pushed, account for them. */
3035 #ifdef PUSH_ROUNDING
3036 if (ep->to_rtx == stack_pointer_rtx)
3037 size = PUSH_ROUNDING (size);
3039 if (code == PRE_DEC || code == POST_DEC)
3041 else if (code == PRE_INC || code == POST_INC)
3043 else if (code == PRE_MODIFY || code == POST_MODIFY)
3045 if (GET_CODE (XEXP (x, 1)) == PLUS
3046 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3047 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3048 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3050 ep->can_eliminate = 0;
3054 /* These two aren't unary operators. */
3055 if (code == POST_MODIFY || code == PRE_MODIFY)
3058 /* Fall through to generic unary operation case. */
3059 case STRICT_LOW_PART:
3061 case SIGN_EXTEND: case ZERO_EXTEND:
3062 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3063 case FLOAT: case FIX:
3064 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3073 elimination_effects (XEXP (x, 0), mem_mode);
3077 if (REG_P (SUBREG_REG (x))
3078 && (GET_MODE_SIZE (GET_MODE (x))
3079 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3081 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3084 elimination_effects (SUBREG_REG (x), mem_mode);
3088 /* If using a register that is the source of an eliminate we still
3089 think can be performed, note it cannot be performed since we don't
3090 know how this register is used. */
3091 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3092 if (ep->from_rtx == XEXP (x, 0))
3093 ep->can_eliminate = 0;
3095 elimination_effects (XEXP (x, 0), mem_mode);
3099 /* If clobbering a register that is the replacement register for an
3100 elimination we still think can be performed, note that it cannot
3101 be performed. Otherwise, we need not be concerned about it. */
3102 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3103 if (ep->to_rtx == XEXP (x, 0))
3104 ep->can_eliminate = 0;
3106 elimination_effects (XEXP (x, 0), mem_mode);
3110 /* Check for setting a register that we know about. */
3111 if (REG_P (SET_DEST (x)))
3113 /* See if this is setting the replacement register for an
3116 If DEST is the hard frame pointer, we do nothing because we
3117 assume that all assignments to the frame pointer are for
3118 non-local gotos and are being done at a time when they are valid
3119 and do not disturb anything else. Some machines want to
3120 eliminate a fake argument pointer (or even a fake frame pointer)
3121 with either the real frame or the stack pointer. Assignments to
3122 the hard frame pointer must not prevent this elimination. */
3124 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3126 if (ep->to_rtx == SET_DEST (x)
3127 && SET_DEST (x) != hard_frame_pointer_rtx)
3129 /* If it is being incremented, adjust the offset. Otherwise,
3130 this elimination can't be done. */
3131 rtx src = SET_SRC (x);
3133 if (GET_CODE (src) == PLUS
3134 && XEXP (src, 0) == SET_DEST (x)
3135 && CONST_INT_P (XEXP (src, 1)))
3136 ep->offset -= INTVAL (XEXP (src, 1));
3138 ep->can_eliminate = 0;
3142 elimination_effects (SET_DEST (x), VOIDmode);
3143 elimination_effects (SET_SRC (x), VOIDmode);
3147 /* Our only special processing is to pass the mode of the MEM to our
3149 elimination_effects (XEXP (x, 0), GET_MODE (x));
3156 fmt = GET_RTX_FORMAT (code);
3157 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3160 elimination_effects (XEXP (x, i), mem_mode);
3161 else if (*fmt == 'E')
3162 for (j = 0; j < XVECLEN (x, i); j++)
3163 elimination_effects (XVECEXP (x, i, j), mem_mode);
3167 /* Descend through rtx X and verify that no references to eliminable registers
3168 remain. If any do remain, mark the involved register as not
3172 check_eliminable_occurrences (rtx x)
3181 code = GET_CODE (x);
3183 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3185 struct elim_table *ep;
3187 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3188 if (ep->from_rtx == x)
3189 ep->can_eliminate = 0;
3193 fmt = GET_RTX_FORMAT (code);
3194 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3197 check_eliminable_occurrences (XEXP (x, i));
3198 else if (*fmt == 'E')
3201 for (j = 0; j < XVECLEN (x, i); j++)
3202 check_eliminable_occurrences (XVECEXP (x, i, j));
3207 /* Scan INSN and eliminate all eliminable registers in it.
3209 If REPLACE is nonzero, do the replacement destructively. Also
3210 delete the insn as dead it if it is setting an eliminable register.
3212 If REPLACE is zero, do all our allocations in reload_obstack.
3214 If no eliminations were done and this insn doesn't require any elimination
3215 processing (these are not identical conditions: it might be updating sp,
3216 but not referencing fp; this needs to be seen during reload_as_needed so
3217 that the offset between fp and sp can be taken into consideration), zero
3218 is returned. Otherwise, 1 is returned. */
3221 eliminate_regs_in_insn (rtx insn, int replace)
3223 int icode = recog_memoized (insn);
3224 rtx old_body = PATTERN (insn);
3225 int insn_is_asm = asm_noperands (old_body) >= 0;
3226 rtx old_set = single_set (insn);
3230 rtx substed_operand[MAX_RECOG_OPERANDS];
3231 rtx orig_operand[MAX_RECOG_OPERANDS];
3232 struct elim_table *ep;
3233 rtx plus_src, plus_cst_src;
3235 if (! insn_is_asm && icode < 0)
3237 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3238 || GET_CODE (PATTERN (insn)) == CLOBBER
3239 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3240 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3241 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3242 || DEBUG_INSN_P (insn));
3243 if (DEBUG_INSN_P (insn))
3244 INSN_VAR_LOCATION_LOC (insn)
3245 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3249 if (old_set != 0 && REG_P (SET_DEST (old_set))
3250 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3252 /* Check for setting an eliminable register. */
3253 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3254 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3256 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3257 /* If this is setting the frame pointer register to the
3258 hardware frame pointer register and this is an elimination
3259 that will be done (tested above), this insn is really
3260 adjusting the frame pointer downward to compensate for
3261 the adjustment done before a nonlocal goto. */
3262 if (ep->from == FRAME_POINTER_REGNUM
3263 && ep->to == HARD_FRAME_POINTER_REGNUM)
3265 rtx base = SET_SRC (old_set);
3266 rtx base_insn = insn;
3267 HOST_WIDE_INT offset = 0;
3269 while (base != ep->to_rtx)
3271 rtx prev_insn, prev_set;
3273 if (GET_CODE (base) == PLUS
3274 && CONST_INT_P (XEXP (base, 1)))
3276 offset += INTVAL (XEXP (base, 1));
3277 base = XEXP (base, 0);
3279 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3280 && (prev_set = single_set (prev_insn)) != 0
3281 && rtx_equal_p (SET_DEST (prev_set), base))
3283 base = SET_SRC (prev_set);
3284 base_insn = prev_insn;
3290 if (base == ep->to_rtx)
3293 = plus_constant (ep->to_rtx, offset - ep->offset);
3295 new_body = old_body;
3298 new_body = copy_insn (old_body);
3299 if (REG_NOTES (insn))
3300 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3302 PATTERN (insn) = new_body;
3303 old_set = single_set (insn);
3305 /* First see if this insn remains valid when we
3306 make the change. If not, keep the INSN_CODE
3307 the same and let reload fit it up. */
3308 validate_change (insn, &SET_SRC (old_set), src, 1);
3309 validate_change (insn, &SET_DEST (old_set),
3311 if (! apply_change_group ())
3313 SET_SRC (old_set) = src;
3314 SET_DEST (old_set) = ep->to_rtx;
3323 /* In this case this insn isn't serving a useful purpose. We
3324 will delete it in reload_as_needed once we know that this
3325 elimination is, in fact, being done.
3327 If REPLACE isn't set, we can't delete this insn, but needn't
3328 process it since it won't be used unless something changes. */
3331 delete_dead_insn (insn);
3339 /* We allow one special case which happens to work on all machines we
3340 currently support: a single set with the source or a REG_EQUAL
3341 note being a PLUS of an eliminable register and a constant. */
3342 plus_src = plus_cst_src = 0;
3343 if (old_set && REG_P (SET_DEST (old_set)))
3345 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3346 plus_src = SET_SRC (old_set);
3347 /* First see if the source is of the form (plus (...) CST). */
3349 && CONST_INT_P (XEXP (plus_src, 1)))
3350 plus_cst_src = plus_src;
3351 else if (REG_P (SET_SRC (old_set))
3354 /* Otherwise, see if we have a REG_EQUAL note of the form
3355 (plus (...) CST). */
3357 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3359 if ((REG_NOTE_KIND (links) == REG_EQUAL
3360 || REG_NOTE_KIND (links) == REG_EQUIV)
3361 && GET_CODE (XEXP (links, 0)) == PLUS
3362 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3364 plus_cst_src = XEXP (links, 0);
3370 /* Check that the first operand of the PLUS is a hard reg or
3371 the lowpart subreg of one. */
3374 rtx reg = XEXP (plus_cst_src, 0);
3375 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3376 reg = SUBREG_REG (reg);
3378 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3384 rtx reg = XEXP (plus_cst_src, 0);
3385 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3387 if (GET_CODE (reg) == SUBREG)
3388 reg = SUBREG_REG (reg);
3390 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3391 if (ep->from_rtx == reg && ep->can_eliminate)
3393 rtx to_rtx = ep->to_rtx;
3394 offset += ep->offset;
3395 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3397 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3398 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3400 /* If we have a nonzero offset, and the source is already
3401 a simple REG, the following transformation would
3402 increase the cost of the insn by replacing a simple REG
3403 with (plus (reg sp) CST). So try only when we already
3404 had a PLUS before. */
3405 if (offset == 0 || plus_src)
3407 rtx new_src = plus_constant (to_rtx, offset);
3409 new_body = old_body;
3412 new_body = copy_insn (old_body);
3413 if (REG_NOTES (insn))
3414 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3416 PATTERN (insn) = new_body;
3417 old_set = single_set (insn);
3419 /* First see if this insn remains valid when we make the
3420 change. If not, try to replace the whole pattern with
3421 a simple set (this may help if the original insn was a
3422 PARALLEL that was only recognized as single_set due to
3423 REG_UNUSED notes). If this isn't valid either, keep
3424 the INSN_CODE the same and let reload fix it up. */
3425 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3427 rtx new_pat = gen_rtx_SET (VOIDmode,
3428 SET_DEST (old_set), new_src);
3430 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3431 SET_SRC (old_set) = new_src;
3438 /* This can't have an effect on elimination offsets, so skip right
3444 /* Determine the effects of this insn on elimination offsets. */
3445 elimination_effects (old_body, VOIDmode);
3447 /* Eliminate all eliminable registers occurring in operands that
3448 can be handled by reload. */
3449 extract_insn (insn);
3450 for (i = 0; i < recog_data.n_operands; i++)
3452 orig_operand[i] = recog_data.operand[i];
3453 substed_operand[i] = recog_data.operand[i];
3455 /* For an asm statement, every operand is eliminable. */
3456 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3458 bool is_set_src, in_plus;
3460 /* Check for setting a register that we know about. */
3461 if (recog_data.operand_type[i] != OP_IN
3462 && REG_P (orig_operand[i]))
3464 /* If we are assigning to a register that can be eliminated, it
3465 must be as part of a PARALLEL, since the code above handles
3466 single SETs. We must indicate that we can no longer
3467 eliminate this reg. */
3468 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3470 if (ep->from_rtx == orig_operand[i])
3471 ep->can_eliminate = 0;
3474 /* Companion to the above plus substitution, we can allow
3475 invariants as the source of a plain move. */
3478 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3482 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3483 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3487 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3488 replace ? insn : NULL_RTX,
3489 is_set_src || in_plus, false);
3490 if (substed_operand[i] != orig_operand[i])
3492 /* Terminate the search in check_eliminable_occurrences at
3494 *recog_data.operand_loc[i] = 0;
3496 /* If an output operand changed from a REG to a MEM and INSN is an
3497 insn, write a CLOBBER insn. */
3498 if (recog_data.operand_type[i] != OP_IN
3499 && REG_P (orig_operand[i])
3500 && MEM_P (substed_operand[i])
3502 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3506 for (i = 0; i < recog_data.n_dups; i++)
3507 *recog_data.dup_loc[i]
3508 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3510 /* If any eliminable remain, they aren't eliminable anymore. */
3511 check_eliminable_occurrences (old_body);
3513 /* Substitute the operands; the new values are in the substed_operand
3515 for (i = 0; i < recog_data.n_operands; i++)
3516 *recog_data.operand_loc[i] = substed_operand[i];
3517 for (i = 0; i < recog_data.n_dups; i++)
3518 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3520 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3521 re-recognize the insn. We do this in case we had a simple addition
3522 but now can do this as a load-address. This saves an insn in this
3524 If re-recognition fails, the old insn code number will still be used,
3525 and some register operands may have changed into PLUS expressions.
3526 These will be handled by find_reloads by loading them into a register
3531 /* If we aren't replacing things permanently and we changed something,
3532 make another copy to ensure that all the RTL is new. Otherwise
3533 things can go wrong if find_reload swaps commutative operands
3534 and one is inside RTL that has been copied while the other is not. */
3535 new_body = old_body;
3538 new_body = copy_insn (old_body);
3539 if (REG_NOTES (insn))
3540 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3542 PATTERN (insn) = new_body;
3544 /* If we had a move insn but now we don't, rerecognize it. This will
3545 cause spurious re-recognition if the old move had a PARALLEL since
3546 the new one still will, but we can't call single_set without
3547 having put NEW_BODY into the insn and the re-recognition won't
3548 hurt in this rare case. */
3549 /* ??? Why this huge if statement - why don't we just rerecognize the
3553 && ((REG_P (SET_SRC (old_set))
3554 && (GET_CODE (new_body) != SET
3555 || !REG_P (SET_SRC (new_body))))
3556 /* If this was a load from or store to memory, compare
3557 the MEM in recog_data.operand to the one in the insn.
3558 If they are not equal, then rerecognize the insn. */
3560 && ((MEM_P (SET_SRC (old_set))
3561 && SET_SRC (old_set) != recog_data.operand[1])
3562 || (MEM_P (SET_DEST (old_set))
3563 && SET_DEST (old_set) != recog_data.operand[0])))
3564 /* If this was an add insn before, rerecognize. */
3565 || GET_CODE (SET_SRC (old_set)) == PLUS))
3567 int new_icode = recog (PATTERN (insn), insn, 0);
3569 INSN_CODE (insn) = new_icode;
3573 /* Restore the old body. If there were any changes to it, we made a copy
3574 of it while the changes were still in place, so we'll correctly return
3575 a modified insn below. */
3578 /* Restore the old body. */
3579 for (i = 0; i < recog_data.n_operands; i++)
3580 /* Restoring a top-level match_parallel would clobber the new_body
3581 we installed in the insn. */
3582 if (recog_data.operand_loc[i] != &PATTERN (insn))
3583 *recog_data.operand_loc[i] = orig_operand[i];
3584 for (i = 0; i < recog_data.n_dups; i++)
3585 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3588 /* Update all elimination pairs to reflect the status after the current
3589 insn. The changes we make were determined by the earlier call to
3590 elimination_effects.
3592 We also detect cases where register elimination cannot be done,
3593 namely, if a register would be both changed and referenced outside a MEM
3594 in the resulting insn since such an insn is often undefined and, even if
3595 not, we cannot know what meaning will be given to it. Note that it is
3596 valid to have a register used in an address in an insn that changes it
3597 (presumably with a pre- or post-increment or decrement).
3599 If anything changes, return nonzero. */
3601 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3603 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3604 ep->can_eliminate = 0;
3606 ep->ref_outside_mem = 0;
3608 if (ep->previous_offset != ep->offset)
3613 /* If we changed something, perform elimination in REG_NOTES. This is
3614 needed even when REPLACE is zero because a REG_DEAD note might refer
3615 to a register that we eliminate and could cause a different number
3616 of spill registers to be needed in the final reload pass than in
3618 if (val && REG_NOTES (insn) != 0)
3620 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3626 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3627 register allocator. INSN is the instruction we need to examine, we perform
3628 eliminations in its operands and record cases where eliminating a reg with
3629 an invariant equivalence would add extra cost. */
3632 elimination_costs_in_insn (rtx insn)
3634 int icode = recog_memoized (insn);
3635 rtx old_body = PATTERN (insn);
3636 int insn_is_asm = asm_noperands (old_body) >= 0;
3637 rtx old_set = single_set (insn);
3639 rtx orig_operand[MAX_RECOG_OPERANDS];
3640 rtx orig_dup[MAX_RECOG_OPERANDS];
3641 struct elim_table *ep;
3642 rtx plus_src, plus_cst_src;
3645 if (! insn_is_asm && icode < 0)
3647 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3648 || GET_CODE (PATTERN (insn)) == CLOBBER
3649 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3650 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3651 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3652 || DEBUG_INSN_P (insn));
3656 if (old_set != 0 && REG_P (SET_DEST (old_set))
3657 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3659 /* Check for setting an eliminable register. */
3660 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3661 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3665 /* We allow one special case which happens to work on all machines we
3666 currently support: a single set with the source or a REG_EQUAL
3667 note being a PLUS of an eliminable register and a constant. */
3668 plus_src = plus_cst_src = 0;
3670 if (old_set && REG_P (SET_DEST (old_set)))
3673 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3674 plus_src = SET_SRC (old_set);
3675 /* First see if the source is of the form (plus (...) CST). */
3677 && CONST_INT_P (XEXP (plus_src, 1)))
3678 plus_cst_src = plus_src;
3679 else if (REG_P (SET_SRC (old_set))
3682 /* Otherwise, see if we have a REG_EQUAL note of the form
3683 (plus (...) CST). */
3685 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3687 if ((REG_NOTE_KIND (links) == REG_EQUAL
3688 || REG_NOTE_KIND (links) == REG_EQUIV)
3689 && GET_CODE (XEXP (links, 0)) == PLUS
3690 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3692 plus_cst_src = XEXP (links, 0);
3699 /* Determine the effects of this insn on elimination offsets. */
3700 elimination_effects (old_body, VOIDmode);
3702 /* Eliminate all eliminable registers occurring in operands that
3703 can be handled by reload. */
3704 extract_insn (insn);
3705 for (i = 0; i < recog_data.n_dups; i++)
3706 orig_dup[i] = *recog_data.dup_loc[i];
3708 for (i = 0; i < recog_data.n_operands; i++)
3710 orig_operand[i] = recog_data.operand[i];
3712 /* For an asm statement, every operand is eliminable. */
3713 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3715 bool is_set_src, in_plus;
3717 /* Check for setting a register that we know about. */
3718 if (recog_data.operand_type[i] != OP_IN
3719 && REG_P (orig_operand[i]))
3721 /* If we are assigning to a register that can be eliminated, it
3722 must be as part of a PARALLEL, since the code above handles
3723 single SETs. We must indicate that we can no longer
3724 eliminate this reg. */
3725 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3727 if (ep->from_rtx == orig_operand[i])
3728 ep->can_eliminate = 0;
3731 /* Companion to the above plus substitution, we can allow
3732 invariants as the source of a plain move. */
3734 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3736 if (is_set_src && !sets_reg_p)
3737 note_reg_elim_costly (&SET_SRC (old_set), insn);
3739 if (plus_src && sets_reg_p
3740 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3741 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3744 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3746 is_set_src || in_plus, true);
3747 /* Terminate the search in check_eliminable_occurrences at
3749 *recog_data.operand_loc[i] = 0;
3753 for (i = 0; i < recog_data.n_dups; i++)
3754 *recog_data.dup_loc[i]
3755 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3757 /* If any eliminable remain, they aren't eliminable anymore. */
3758 check_eliminable_occurrences (old_body);
3760 /* Restore the old body. */
3761 for (i = 0; i < recog_data.n_operands; i++)
3762 *recog_data.operand_loc[i] = orig_operand[i];
3763 for (i = 0; i < recog_data.n_dups; i++)
3764 *recog_data.dup_loc[i] = orig_dup[i];
3766 /* Update all elimination pairs to reflect the status after the current
3767 insn. The changes we make were determined by the earlier call to
3768 elimination_effects. */
3770 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3772 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3773 ep->can_eliminate = 0;
3775 ep->ref_outside_mem = 0;
3781 /* Loop through all elimination pairs.
3782 Recalculate the number not at initial offset.
3784 Compute the maximum offset (minimum offset if the stack does not
3785 grow downward) for each elimination pair. */
3788 update_eliminable_offsets (void)
3790 struct elim_table *ep;
3792 num_not_at_initial_offset = 0;
3793 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3795 ep->previous_offset = ep->offset;
3796 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3797 num_not_at_initial_offset++;
3801 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3802 replacement we currently believe is valid, mark it as not eliminable if X
3803 modifies DEST in any way other than by adding a constant integer to it.
3805 If DEST is the frame pointer, we do nothing because we assume that
3806 all assignments to the hard frame pointer are nonlocal gotos and are being
3807 done at a time when they are valid and do not disturb anything else.
3808 Some machines want to eliminate a fake argument pointer with either the
3809 frame or stack pointer. Assignments to the hard frame pointer must not
3810 prevent this elimination.
3812 Called via note_stores from reload before starting its passes to scan
3813 the insns of the function. */
3816 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3820 /* A SUBREG of a hard register here is just changing its mode. We should
3821 not see a SUBREG of an eliminable hard register, but check just in
3823 if (GET_CODE (dest) == SUBREG)
3824 dest = SUBREG_REG (dest);
3826 if (dest == hard_frame_pointer_rtx)
3829 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3830 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3831 && (GET_CODE (x) != SET
3832 || GET_CODE (SET_SRC (x)) != PLUS
3833 || XEXP (SET_SRC (x), 0) != dest
3834 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3836 reg_eliminate[i].can_eliminate_previous
3837 = reg_eliminate[i].can_eliminate = 0;
3842 /* Verify that the initial elimination offsets did not change since the
3843 last call to set_initial_elim_offsets. This is used to catch cases
3844 where something illegal happened during reload_as_needed that could
3845 cause incorrect code to be generated if we did not check for it. */
3848 verify_initial_elim_offsets (void)
3852 if (!num_eliminable)
3855 #ifdef ELIMINABLE_REGS
3857 struct elim_table *ep;
3859 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3861 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3862 if (t != ep->initial_offset)
3867 INITIAL_FRAME_POINTER_OFFSET (t);
3868 if (t != reg_eliminate[0].initial_offset)
3875 /* Reset all offsets on eliminable registers to their initial values. */
3878 set_initial_elim_offsets (void)
3880 struct elim_table *ep = reg_eliminate;
3882 #ifdef ELIMINABLE_REGS
3883 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3885 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3886 ep->previous_offset = ep->offset = ep->initial_offset;
3889 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3890 ep->previous_offset = ep->offset = ep->initial_offset;
3893 num_not_at_initial_offset = 0;
3896 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3899 set_initial_eh_label_offset (rtx label)
3901 set_label_offsets (label, NULL_RTX, 1);
3904 /* Initialize the known label offsets.
3905 Set a known offset for each forced label to be at the initial offset
3906 of each elimination. We do this because we assume that all
3907 computed jumps occur from a location where each elimination is
3908 at its initial offset.
3909 For all other labels, show that we don't know the offsets. */
3912 set_initial_label_offsets (void)
3915 memset (offsets_known_at, 0, num_labels);
3917 for (x = forced_labels; x; x = XEXP (x, 1))
3919 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3921 for (x = nonlocal_goto_handler_labels; x; x = XEXP (x, 1))
3923 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3925 for_each_eh_label (set_initial_eh_label_offset);
3928 /* Set all elimination offsets to the known values for the code label given
3932 set_offsets_for_label (rtx insn)
3935 int label_nr = CODE_LABEL_NUMBER (insn);
3936 struct elim_table *ep;
3938 num_not_at_initial_offset = 0;
3939 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3941 ep->offset = ep->previous_offset
3942 = offsets_at[label_nr - first_label_num][i];
3943 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3944 num_not_at_initial_offset++;
3948 /* See if anything that happened changes which eliminations are valid.
3949 For example, on the SPARC, whether or not the frame pointer can
3950 be eliminated can depend on what registers have been used. We need
3951 not check some conditions again (such as flag_omit_frame_pointer)
3952 since they can't have changed. */
3955 update_eliminables (HARD_REG_SET *pset)
3957 int previous_frame_pointer_needed = frame_pointer_needed;
3958 struct elim_table *ep;
3960 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3961 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3962 && targetm.frame_pointer_required ())
3963 #ifdef ELIMINABLE_REGS
3964 || ! targetm.can_eliminate (ep->from, ep->to)
3967 ep->can_eliminate = 0;
3969 /* Look for the case where we have discovered that we can't replace
3970 register A with register B and that means that we will now be
3971 trying to replace register A with register C. This means we can
3972 no longer replace register C with register B and we need to disable
3973 such an elimination, if it exists. This occurs often with A == ap,
3974 B == sp, and C == fp. */
3976 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3978 struct elim_table *op;
3981 if (! ep->can_eliminate && ep->can_eliminate_previous)
3983 /* Find the current elimination for ep->from, if there is a
3985 for (op = reg_eliminate;
3986 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3987 if (op->from == ep->from && op->can_eliminate)
3993 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3995 for (op = reg_eliminate;
3996 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3997 if (op->from == new_to && op->to == ep->to)
3998 op->can_eliminate = 0;
4002 /* See if any registers that we thought we could eliminate the previous
4003 time are no longer eliminable. If so, something has changed and we
4004 must spill the register. Also, recompute the number of eliminable
4005 registers and see if the frame pointer is needed; it is if there is
4006 no elimination of the frame pointer that we can perform. */
4008 frame_pointer_needed = 1;
4009 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4011 if (ep->can_eliminate
4012 && ep->from == FRAME_POINTER_REGNUM
4013 && ep->to != HARD_FRAME_POINTER_REGNUM
4014 && (! SUPPORTS_STACK_ALIGNMENT
4015 || ! crtl->stack_realign_needed))
4016 frame_pointer_needed = 0;
4018 if (! ep->can_eliminate && ep->can_eliminate_previous)
4020 ep->can_eliminate_previous = 0;
4021 SET_HARD_REG_BIT (*pset, ep->from);
4026 /* If we didn't need a frame pointer last time, but we do now, spill
4027 the hard frame pointer. */
4028 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4029 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4032 /* Return true if X is used as the target register of an elimination. */
4035 elimination_target_reg_p (rtx x)
4037 struct elim_table *ep;
4039 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4040 if (ep->to_rtx == x && ep->can_eliminate)
4046 /* Initialize the table of registers to eliminate.
4047 Pre-condition: global flag frame_pointer_needed has been set before
4048 calling this function. */
4051 init_elim_table (void)
4053 struct elim_table *ep;
4054 #ifdef ELIMINABLE_REGS
4055 const struct elim_table_1 *ep1;
4059 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4063 #ifdef ELIMINABLE_REGS
4064 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4065 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4067 ep->from = ep1->from;
4069 ep->can_eliminate = ep->can_eliminate_previous
4070 = (targetm.can_eliminate (ep->from, ep->to)
4071 && ! (ep->to == STACK_POINTER_REGNUM
4072 && frame_pointer_needed
4073 && (! SUPPORTS_STACK_ALIGNMENT
4074 || ! stack_realign_fp)));
4077 reg_eliminate[0].from = reg_eliminate_1[0].from;
4078 reg_eliminate[0].to = reg_eliminate_1[0].to;
4079 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4080 = ! frame_pointer_needed;
4083 /* Count the number of eliminable registers and build the FROM and TO
4084 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4085 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4086 We depend on this. */
4087 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4089 num_eliminable += ep->can_eliminate;
4090 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4091 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4095 /* Find all the pseudo registers that didn't get hard regs
4096 but do have known equivalent constants or memory slots.
4097 These include parameters (known equivalent to parameter slots)
4098 and cse'd or loop-moved constant memory addresses.
4100 Record constant equivalents in reg_equiv_constant
4101 so they will be substituted by find_reloads.
4102 Record memory equivalents in reg_mem_equiv so they can
4103 be substituted eventually by altering the REG-rtx's. */
4106 init_eliminable_invariants (rtx first, bool do_subregs)
4113 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4115 reg_max_ref_width = NULL;
4117 num_eliminable_invariants = 0;
4119 first_label_num = get_first_label_num ();
4120 num_labels = max_label_num () - first_label_num;
4122 /* Allocate the tables used to store offset information at labels. */
4123 offsets_known_at = XNEWVEC (char, num_labels);
4124 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4126 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4127 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4128 find largest such for each pseudo. FIRST is the head of the insn
4131 for (insn = first; insn; insn = NEXT_INSN (insn))
4133 rtx set = single_set (insn);
4135 /* We may introduce USEs that we want to remove at the end, so
4136 we'll mark them with QImode. Make sure there are no
4137 previously-marked insns left by say regmove. */
4138 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4139 && GET_MODE (insn) != VOIDmode)
4140 PUT_MODE (insn, VOIDmode);
4142 if (do_subregs && NONDEBUG_INSN_P (insn))
4143 scan_paradoxical_subregs (PATTERN (insn));
4145 if (set != 0 && REG_P (SET_DEST (set)))
4147 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4153 i = REGNO (SET_DEST (set));
4156 if (i <= LAST_VIRTUAL_REGISTER)
4159 /* If flag_pic and we have constant, verify it's legitimate. */
4161 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4163 /* It can happen that a REG_EQUIV note contains a MEM
4164 that is not a legitimate memory operand. As later
4165 stages of reload assume that all addresses found
4166 in the reg_equiv_* arrays were originally legitimate,
4167 we ignore such REG_EQUIV notes. */
4168 if (memory_operand (x, VOIDmode))
4170 /* Always unshare the equivalence, so we can
4171 substitute into this insn without touching the
4173 reg_equiv_memory_loc (i) = copy_rtx (x);
4175 else if (function_invariant_p (x))
4177 enum machine_mode mode;
4179 mode = GET_MODE (SET_DEST (set));
4180 if (GET_CODE (x) == PLUS)
4182 /* This is PLUS of frame pointer and a constant,
4183 and might be shared. Unshare it. */
4184 reg_equiv_invariant (i) = copy_rtx (x);
4185 num_eliminable_invariants++;
4187 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4189 reg_equiv_invariant (i) = x;
4190 num_eliminable_invariants++;
4192 else if (targetm.legitimate_constant_p (mode, x))
4193 reg_equiv_constant (i) = x;
4196 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4197 if (! reg_equiv_memory_loc (i))
4198 reg_equiv_init (i) = NULL_RTX;
4203 reg_equiv_init (i) = NULL_RTX;
4208 reg_equiv_init (i) = NULL_RTX;
4213 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4214 if (reg_equiv_init (i))
4216 fprintf (dump_file, "init_insns for %u: ", i);
4217 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4218 fprintf (dump_file, "\n");
4222 /* Indicate that we no longer have known memory locations or constants.
4223 Free all data involved in tracking these. */
4226 free_reg_equiv (void)
4231 free (offsets_known_at);
4234 offsets_known_at = 0;
4236 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4237 if (reg_equiv_alt_mem_list (i))
4238 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4239 VEC_free (reg_equivs_t, gc, reg_equivs);
4244 /* Kick all pseudos out of hard register REGNO.
4246 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4247 because we found we can't eliminate some register. In the case, no pseudos
4248 are allowed to be in the register, even if they are only in a block that
4249 doesn't require spill registers, unlike the case when we are spilling this
4250 hard reg to produce another spill register.
4252 Return nonzero if any pseudos needed to be kicked out. */
4255 spill_hard_reg (unsigned int regno, int cant_eliminate)
4261 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4262 df_set_regs_ever_live (regno, true);
4265 /* Spill every pseudo reg that was allocated to this reg
4266 or to something that overlaps this reg. */
4268 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4269 if (reg_renumber[i] >= 0
4270 && (unsigned int) reg_renumber[i] <= regno
4271 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4272 SET_REGNO_REG_SET (&spilled_pseudos, i);
4275 /* After find_reload_regs has been run for all insn that need reloads,
4276 and/or spill_hard_regs was called, this function is used to actually
4277 spill pseudo registers and try to reallocate them. It also sets up the
4278 spill_regs array for use by choose_reload_regs. */
4281 finish_spills (int global)
4283 struct insn_chain *chain;
4284 int something_changed = 0;
4286 reg_set_iterator rsi;
4288 /* Build the spill_regs array for the function. */
4289 /* If there are some registers still to eliminate and one of the spill regs
4290 wasn't ever used before, additional stack space may have to be
4291 allocated to store this register. Thus, we may have changed the offset
4292 between the stack and frame pointers, so mark that something has changed.
4294 One might think that we need only set VAL to 1 if this is a call-used
4295 register. However, the set of registers that must be saved by the
4296 prologue is not identical to the call-used set. For example, the
4297 register used by the call insn for the return PC is a call-used register,
4298 but must be saved by the prologue. */
4301 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4302 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4304 spill_reg_order[i] = n_spills;
4305 spill_regs[n_spills++] = i;
4306 if (num_eliminable && ! df_regs_ever_live_p (i))
4307 something_changed = 1;
4308 df_set_regs_ever_live (i, true);
4311 spill_reg_order[i] = -1;
4313 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4314 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4316 /* Record the current hard register the pseudo is allocated to
4317 in pseudo_previous_regs so we avoid reallocating it to the
4318 same hard reg in a later pass. */
4319 gcc_assert (reg_renumber[i] >= 0);
4321 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4322 /* Mark it as no longer having a hard register home. */
4323 reg_renumber[i] = -1;
4324 if (ira_conflicts_p)
4325 /* Inform IRA about the change. */
4326 ira_mark_allocation_change (i);
4327 /* We will need to scan everything again. */
4328 something_changed = 1;
4331 /* Retry global register allocation if possible. */
4332 if (global && ira_conflicts_p)
4336 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4337 /* For every insn that needs reloads, set the registers used as spill
4338 regs in pseudo_forbidden_regs for every pseudo live across the
4340 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4342 EXECUTE_IF_SET_IN_REG_SET
4343 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4345 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4346 chain->used_spill_regs);
4348 EXECUTE_IF_SET_IN_REG_SET
4349 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4351 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4352 chain->used_spill_regs);
4356 /* Retry allocating the pseudos spilled in IRA and the
4357 reload. For each reg, merge the various reg sets that
4358 indicate which hard regs can't be used, and call
4359 ira_reassign_pseudos. */
4360 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4361 if (reg_old_renumber[i] != reg_renumber[i])
4363 if (reg_renumber[i] < 0)
4364 temp_pseudo_reg_arr[n++] = i;
4366 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4368 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4369 bad_spill_regs_global,
4370 pseudo_forbidden_regs, pseudo_previous_regs,
4372 something_changed = 1;
4374 /* Fix up the register information in the insn chain.
4375 This involves deleting those of the spilled pseudos which did not get
4376 a new hard register home from the live_{before,after} sets. */
4377 for (chain = reload_insn_chain; chain; chain = chain->next)
4379 HARD_REG_SET used_by_pseudos;
4380 HARD_REG_SET used_by_pseudos2;
4382 if (! ira_conflicts_p)
4384 /* Don't do it for IRA because IRA and the reload still can
4385 assign hard registers to the spilled pseudos on next
4386 reload iterations. */
4387 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4388 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4390 /* Mark any unallocated hard regs as available for spills. That
4391 makes inheritance work somewhat better. */
4392 if (chain->need_reload)
4394 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4395 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4396 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4398 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4399 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4400 /* Value of chain->used_spill_regs from previous iteration
4401 may be not included in the value calculated here because
4402 of possible removing caller-saves insns (see function
4403 delete_caller_save_insns. */
4404 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4405 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4409 CLEAR_REG_SET (&changed_allocation_pseudos);
4410 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4411 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4413 int regno = reg_renumber[i];
4414 if (reg_old_renumber[i] == regno)
4417 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4419 alter_reg (i, reg_old_renumber[i], false);
4420 reg_old_renumber[i] = regno;
4424 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4426 fprintf (dump_file, " Register %d now in %d.\n\n",
4427 i, reg_renumber[i]);
4431 return something_changed;
4434 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4437 scan_paradoxical_subregs (rtx x)
4441 enum rtx_code code = GET_CODE (x);
4452 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4460 if (REG_P (SUBREG_REG (x))
4461 && (GET_MODE_SIZE (GET_MODE (x))
4462 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4464 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4465 = GET_MODE_SIZE (GET_MODE (x));
4466 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4474 fmt = GET_RTX_FORMAT (code);
4475 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4478 scan_paradoxical_subregs (XEXP (x, i));
4479 else if (fmt[i] == 'E')
4482 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4483 scan_paradoxical_subregs (XVECEXP (x, i, j));
4488 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4489 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4490 and apply the corresponding narrowing subreg to *OTHER_PTR.
4491 Return true if the operands were changed, false otherwise. */
4494 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4496 rtx op, inner, other, tem;
4499 if (!paradoxical_subreg_p (op))
4501 inner = SUBREG_REG (op);
4504 tem = gen_lowpart_common (GET_MODE (inner), other);
4508 /* If the lowpart operation turned a hard register into a subreg,
4509 rather than simplifying it to another hard register, then the
4510 mode change cannot be properly represented. For example, OTHER
4511 might be valid in its current mode, but not in the new one. */
4512 if (GET_CODE (tem) == SUBREG
4514 && HARD_REGISTER_P (other))
4522 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4523 examine all of the reload insns between PREV and NEXT exclusive, and
4524 annotate all that may trap. */
4527 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4529 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4532 if (!insn_could_throw_p (insn))
4533 remove_note (insn, note);
4534 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4537 /* Reload pseudo-registers into hard regs around each insn as needed.
4538 Additional register load insns are output before the insn that needs it
4539 and perhaps store insns after insns that modify the reloaded pseudo reg.
4541 reg_last_reload_reg and reg_reloaded_contents keep track of
4542 which registers are already available in reload registers.
4543 We update these for the reloads that we perform,
4544 as the insns are scanned. */
4547 reload_as_needed (int live_known)
4549 struct insn_chain *chain;
4550 #if defined (AUTO_INC_DEC)
4555 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4556 memset (spill_reg_store, 0, sizeof spill_reg_store);
4557 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4558 INIT_REG_SET (®_has_output_reload);
4559 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4560 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4562 set_initial_elim_offsets ();
4564 /* Generate a marker insn that we will move around. */
4565 marker = emit_note (NOTE_INSN_DELETED);
4566 unlink_insn_chain (marker, marker);
4568 for (chain = reload_insn_chain; chain; chain = chain->next)
4571 rtx insn = chain->insn;
4572 rtx old_next = NEXT_INSN (insn);
4574 rtx old_prev = PREV_INSN (insn);
4577 /* If we pass a label, copy the offsets from the label information
4578 into the current offsets of each elimination. */
4580 set_offsets_for_label (insn);
4582 else if (INSN_P (insn))
4584 regset_head regs_to_forget;
4585 INIT_REG_SET (®s_to_forget);
4586 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4588 /* If this is a USE and CLOBBER of a MEM, ensure that any
4589 references to eliminable registers have been removed. */
4591 if ((GET_CODE (PATTERN (insn)) == USE
4592 || GET_CODE (PATTERN (insn)) == CLOBBER)
4593 && MEM_P (XEXP (PATTERN (insn), 0)))
4594 XEXP (XEXP (PATTERN (insn), 0), 0)
4595 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4596 GET_MODE (XEXP (PATTERN (insn), 0)),
4599 /* If we need to do register elimination processing, do so.
4600 This might delete the insn, in which case we are done. */
4601 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4603 eliminate_regs_in_insn (insn, 1);
4606 update_eliminable_offsets ();
4607 CLEAR_REG_SET (®s_to_forget);
4612 /* If need_elim is nonzero but need_reload is zero, one might think
4613 that we could simply set n_reloads to 0. However, find_reloads
4614 could have done some manipulation of the insn (such as swapping
4615 commutative operands), and these manipulations are lost during
4616 the first pass for every insn that needs register elimination.
4617 So the actions of find_reloads must be redone here. */
4619 if (! chain->need_elim && ! chain->need_reload
4620 && ! chain->need_operand_change)
4622 /* First find the pseudo regs that must be reloaded for this insn.
4623 This info is returned in the tables reload_... (see reload.h).
4624 Also modify the body of INSN by substituting RELOAD
4625 rtx's for those pseudo regs. */
4628 CLEAR_REG_SET (®_has_output_reload);
4629 CLEAR_HARD_REG_SET (reg_is_output_reload);
4631 find_reloads (insn, 1, spill_indirect_levels, live_known,
4637 rtx next = NEXT_INSN (insn);
4640 /* ??? PREV can get deleted by reload inheritance.
4641 Work around this by emitting a marker note. */
4642 prev = PREV_INSN (insn);
4643 reorder_insns_nobb (marker, marker, prev);
4645 /* Now compute which reload regs to reload them into. Perhaps
4646 reusing reload regs from previous insns, or else output
4647 load insns to reload them. Maybe output store insns too.
4648 Record the choices of reload reg in reload_reg_rtx. */
4649 choose_reload_regs (chain);
4651 /* Generate the insns to reload operands into or out of
4652 their reload regs. */
4653 emit_reload_insns (chain);
4655 /* Substitute the chosen reload regs from reload_reg_rtx
4656 into the insn's body (or perhaps into the bodies of other
4657 load and store insn that we just made for reloading
4658 and that we moved the structure into). */
4659 subst_reloads (insn);
4661 prev = PREV_INSN (marker);
4662 unlink_insn_chain (marker, marker);
4664 /* Adjust the exception region notes for loads and stores. */
4665 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4666 fixup_eh_region_note (insn, prev, next);
4668 /* Adjust the location of REG_ARGS_SIZE. */
4669 p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4672 remove_note (insn, p);
4673 fixup_args_size_notes (prev, PREV_INSN (next),
4674 INTVAL (XEXP (p, 0)));
4677 /* If this was an ASM, make sure that all the reload insns
4678 we have generated are valid. If not, give an error
4680 if (asm_noperands (PATTERN (insn)) >= 0)
4681 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4682 if (p != insn && INSN_P (p)
4683 && GET_CODE (PATTERN (p)) != USE
4684 && (recog_memoized (p) < 0
4685 || (extract_insn (p), ! constrain_operands (1))))
4687 error_for_asm (insn,
4688 "%<asm%> operand requires "
4689 "impossible reload");
4694 if (num_eliminable && chain->need_elim)
4695 update_eliminable_offsets ();
4697 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4698 is no longer validly lying around to save a future reload.
4699 Note that this does not detect pseudos that were reloaded
4700 for this insn in order to be stored in
4701 (obeying register constraints). That is correct; such reload
4702 registers ARE still valid. */
4703 forget_marked_reloads (®s_to_forget);
4704 CLEAR_REG_SET (®s_to_forget);
4706 /* There may have been CLOBBER insns placed after INSN. So scan
4707 between INSN and NEXT and use them to forget old reloads. */
4708 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4709 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4710 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4713 /* Likewise for regs altered by auto-increment in this insn.
4714 REG_INC notes have been changed by reloading:
4715 find_reloads_address_1 records substitutions for them,
4716 which have been performed by subst_reloads above. */
4717 for (i = n_reloads - 1; i >= 0; i--)
4719 rtx in_reg = rld[i].in_reg;
4722 enum rtx_code code = GET_CODE (in_reg);
4723 /* PRE_INC / PRE_DEC will have the reload register ending up
4724 with the same value as the stack slot, but that doesn't
4725 hold true for POST_INC / POST_DEC. Either we have to
4726 convert the memory access to a true POST_INC / POST_DEC,
4727 or we can't use the reload register for inheritance. */
4728 if ((code == POST_INC || code == POST_DEC)
4729 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4730 REGNO (rld[i].reg_rtx))
4731 /* Make sure it is the inc/dec pseudo, and not
4732 some other (e.g. output operand) pseudo. */
4733 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4734 == REGNO (XEXP (in_reg, 0))))
4737 rtx reload_reg = rld[i].reg_rtx;
4738 enum machine_mode mode = GET_MODE (reload_reg);
4742 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4744 /* We really want to ignore REG_INC notes here, so
4745 use PATTERN (p) as argument to reg_set_p . */
4746 if (reg_set_p (reload_reg, PATTERN (p)))
4748 n = count_occurrences (PATTERN (p), reload_reg, 0);
4754 = gen_rtx_fmt_e (code, mode, reload_reg);
4756 validate_replace_rtx_group (reload_reg,
4758 n = verify_changes (0);
4760 /* We must also verify that the constraints
4761 are met after the replacement. Make sure
4762 extract_insn is only called for an insn
4763 where the replacements were found to be
4768 n = constrain_operands (1);
4771 /* If the constraints were not met, then
4772 undo the replacement, else confirm it. */
4776 confirm_change_group ();
4782 add_reg_note (p, REG_INC, reload_reg);
4783 /* Mark this as having an output reload so that the
4784 REG_INC processing code below won't invalidate
4785 the reload for inheritance. */
4786 SET_HARD_REG_BIT (reg_is_output_reload,
4787 REGNO (reload_reg));
4788 SET_REGNO_REG_SET (®_has_output_reload,
4789 REGNO (XEXP (in_reg, 0)));
4792 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4795 else if ((code == PRE_INC || code == PRE_DEC)
4796 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4797 REGNO (rld[i].reg_rtx))
4798 /* Make sure it is the inc/dec pseudo, and not
4799 some other (e.g. output operand) pseudo. */
4800 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4801 == REGNO (XEXP (in_reg, 0))))
4803 SET_HARD_REG_BIT (reg_is_output_reload,
4804 REGNO (rld[i].reg_rtx));
4805 SET_REGNO_REG_SET (®_has_output_reload,
4806 REGNO (XEXP (in_reg, 0)));
4808 else if (code == PRE_INC || code == PRE_DEC
4809 || code == POST_INC || code == POST_DEC)
4811 int in_regno = REGNO (XEXP (in_reg, 0));
4813 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4816 bool forget_p = true;
4818 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4819 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4822 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4825 if (x == reg_reloaded_insn[in_hard_regno])
4831 /* If for some reasons, we didn't set up
4832 reg_last_reload_reg in this insn,
4833 invalidate inheritance from previous
4834 insns for the incremented/decremented
4835 register. Such registers will be not in
4836 reg_has_output_reload. Invalidate it
4837 also if the corresponding element in
4838 reg_reloaded_insn is also
4841 forget_old_reloads_1 (XEXP (in_reg, 0),
4847 /* If a pseudo that got a hard register is auto-incremented,
4848 we must purge records of copying it into pseudos without
4850 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4851 if (REG_NOTE_KIND (x) == REG_INC)
4853 /* See if this pseudo reg was reloaded in this insn.
4854 If so, its last-reload info is still valid
4855 because it is based on this insn's reload. */
4856 for (i = 0; i < n_reloads; i++)
4857 if (rld[i].out == XEXP (x, 0))
4861 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4865 /* A reload reg's contents are unknown after a label. */
4867 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4869 /* Don't assume a reload reg is still good after a call insn
4870 if it is a call-used reg, or if it contains a value that will
4871 be partially clobbered by the call. */
4872 else if (CALL_P (insn))
4874 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4875 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4877 /* If this is a call to a setjmp-type function, we must not
4878 reuse any reload reg contents across the call; that will
4879 just be clobbered by other uses of the register in later
4880 code, before the longjmp. */
4881 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4882 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4887 free (reg_last_reload_reg);
4888 CLEAR_REG_SET (®_has_output_reload);
4891 /* Discard all record of any value reloaded from X,
4892 or reloaded in X from someplace else;
4893 unless X is an output reload reg of the current insn.
4895 X may be a hard reg (the reload reg)
4896 or it may be a pseudo reg that was reloaded from.
4898 When DATA is non-NULL just mark the registers in regset
4899 to be forgotten later. */
4902 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4907 regset regs = (regset) data;
4909 /* note_stores does give us subregs of hard regs,
4910 subreg_regno_offset requires a hard reg. */
4911 while (GET_CODE (x) == SUBREG)
4913 /* We ignore the subreg offset when calculating the regno,
4914 because we are using the entire underlying hard register
4924 if (regno >= FIRST_PSEUDO_REGISTER)
4930 nr = hard_regno_nregs[regno][GET_MODE (x)];
4931 /* Storing into a spilled-reg invalidates its contents.
4932 This can happen if a block-local pseudo is allocated to that reg
4933 and it wasn't spilled because this block's total need is 0.
4934 Then some insn might have an optional reload and use this reg. */
4936 for (i = 0; i < nr; i++)
4937 /* But don't do this if the reg actually serves as an output
4938 reload reg in the current instruction. */
4940 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4942 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4943 spill_reg_store[regno + i] = 0;
4949 SET_REGNO_REG_SET (regs, regno + nr);
4952 /* Since value of X has changed,
4953 forget any value previously copied from it. */
4956 /* But don't forget a copy if this is the output reload
4957 that establishes the copy's validity. */
4959 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4960 reg_last_reload_reg[regno + nr] = 0;
4964 /* Forget the reloads marked in regset by previous function. */
4966 forget_marked_reloads (regset regs)
4969 reg_set_iterator rsi;
4970 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4972 if (reg < FIRST_PSEUDO_REGISTER
4973 /* But don't do this if the reg actually serves as an output
4974 reload reg in the current instruction. */
4976 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4978 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4979 spill_reg_store[reg] = 0;
4982 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4983 reg_last_reload_reg[reg] = 0;
4987 /* The following HARD_REG_SETs indicate when each hard register is
4988 used for a reload of various parts of the current insn. */
4990 /* If reg is unavailable for all reloads. */
4991 static HARD_REG_SET reload_reg_unavailable;
4992 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4993 static HARD_REG_SET reload_reg_used;
4994 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4995 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4996 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4997 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4998 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4999 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5000 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5001 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5002 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5003 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5004 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5005 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5006 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5007 static HARD_REG_SET reload_reg_used_in_op_addr;
5008 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5009 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5010 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5011 static HARD_REG_SET reload_reg_used_in_insn;
5012 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5013 static HARD_REG_SET reload_reg_used_in_other_addr;
5015 /* If reg is in use as a reload reg for any sort of reload. */
5016 static HARD_REG_SET reload_reg_used_at_all;
5018 /* If reg is use as an inherited reload. We just mark the first register
5020 static HARD_REG_SET reload_reg_used_for_inherit;
5022 /* Records which hard regs are used in any way, either as explicit use or
5023 by being allocated to a pseudo during any point of the current insn. */
5024 static HARD_REG_SET reg_used_in_insn;
5026 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5027 TYPE. MODE is used to indicate how many consecutive regs are
5031 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5032 enum machine_mode mode)
5037 add_to_hard_reg_set (&reload_reg_used, mode, regno);
5040 case RELOAD_FOR_INPUT_ADDRESS:
5041 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5044 case RELOAD_FOR_INPADDR_ADDRESS:
5045 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5048 case RELOAD_FOR_OUTPUT_ADDRESS:
5049 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5052 case RELOAD_FOR_OUTADDR_ADDRESS:
5053 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5056 case RELOAD_FOR_OPERAND_ADDRESS:
5057 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5060 case RELOAD_FOR_OPADDR_ADDR:
5061 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5064 case RELOAD_FOR_OTHER_ADDRESS:
5065 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5068 case RELOAD_FOR_INPUT:
5069 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5072 case RELOAD_FOR_OUTPUT:
5073 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5076 case RELOAD_FOR_INSN:
5077 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5081 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5084 /* Similarly, but show REGNO is no longer in use for a reload. */
5087 clear_reload_reg_in_use (unsigned int regno, int opnum,
5088 enum reload_type type, enum machine_mode mode)
5090 unsigned int nregs = hard_regno_nregs[regno][mode];
5091 unsigned int start_regno, end_regno, r;
5093 /* A complication is that for some reload types, inheritance might
5094 allow multiple reloads of the same types to share a reload register.
5095 We set check_opnum if we have to check only reloads with the same
5096 operand number, and check_any if we have to check all reloads. */
5097 int check_opnum = 0;
5099 HARD_REG_SET *used_in_set;
5104 used_in_set = &reload_reg_used;
5107 case RELOAD_FOR_INPUT_ADDRESS:
5108 used_in_set = &reload_reg_used_in_input_addr[opnum];
5111 case RELOAD_FOR_INPADDR_ADDRESS:
5113 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5116 case RELOAD_FOR_OUTPUT_ADDRESS:
5117 used_in_set = &reload_reg_used_in_output_addr[opnum];
5120 case RELOAD_FOR_OUTADDR_ADDRESS:
5122 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5125 case RELOAD_FOR_OPERAND_ADDRESS:
5126 used_in_set = &reload_reg_used_in_op_addr;
5129 case RELOAD_FOR_OPADDR_ADDR:
5131 used_in_set = &reload_reg_used_in_op_addr_reload;
5134 case RELOAD_FOR_OTHER_ADDRESS:
5135 used_in_set = &reload_reg_used_in_other_addr;
5139 case RELOAD_FOR_INPUT:
5140 used_in_set = &reload_reg_used_in_input[opnum];
5143 case RELOAD_FOR_OUTPUT:
5144 used_in_set = &reload_reg_used_in_output[opnum];
5147 case RELOAD_FOR_INSN:
5148 used_in_set = &reload_reg_used_in_insn;
5153 /* We resolve conflicts with remaining reloads of the same type by
5154 excluding the intervals of reload registers by them from the
5155 interval of freed reload registers. Since we only keep track of
5156 one set of interval bounds, we might have to exclude somewhat
5157 more than what would be necessary if we used a HARD_REG_SET here.
5158 But this should only happen very infrequently, so there should
5159 be no reason to worry about it. */
5161 start_regno = regno;
5162 end_regno = regno + nregs;
5163 if (check_opnum || check_any)
5165 for (i = n_reloads - 1; i >= 0; i--)
5167 if (rld[i].when_needed == type
5168 && (check_any || rld[i].opnum == opnum)
5171 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5172 unsigned int conflict_end
5173 = end_hard_regno (rld[i].mode, conflict_start);
5175 /* If there is an overlap with the first to-be-freed register,
5176 adjust the interval start. */
5177 if (conflict_start <= start_regno && conflict_end > start_regno)
5178 start_regno = conflict_end;
5179 /* Otherwise, if there is a conflict with one of the other
5180 to-be-freed registers, adjust the interval end. */
5181 if (conflict_start > start_regno && conflict_start < end_regno)
5182 end_regno = conflict_start;
5187 for (r = start_regno; r < end_regno; r++)
5188 CLEAR_HARD_REG_BIT (*used_in_set, r);
5191 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5192 specified by OPNUM and TYPE. */
5195 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5199 /* In use for a RELOAD_OTHER means it's not available for anything. */
5200 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5201 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5207 /* In use for anything means we can't use it for RELOAD_OTHER. */
5208 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5209 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5210 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5211 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5214 for (i = 0; i < reload_n_operands; i++)
5215 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5216 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5217 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5218 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5219 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5220 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5225 case RELOAD_FOR_INPUT:
5226 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5227 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5230 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5233 /* If it is used for some other input, can't use it. */
5234 for (i = 0; i < reload_n_operands; i++)
5235 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5238 /* If it is used in a later operand's address, can't use it. */
5239 for (i = opnum + 1; i < reload_n_operands; i++)
5240 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5241 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5246 case RELOAD_FOR_INPUT_ADDRESS:
5247 /* Can't use a register if it is used for an input address for this
5248 operand or used as an input in an earlier one. */
5249 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5250 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5253 for (i = 0; i < opnum; i++)
5254 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5259 case RELOAD_FOR_INPADDR_ADDRESS:
5260 /* Can't use a register if it is used for an input address
5261 for this operand or used as an input in an earlier
5263 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5266 for (i = 0; i < opnum; i++)
5267 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5272 case RELOAD_FOR_OUTPUT_ADDRESS:
5273 /* Can't use a register if it is used for an output address for this
5274 operand or used as an output in this or a later operand. Note
5275 that multiple output operands are emitted in reverse order, so
5276 the conflicting ones are those with lower indices. */
5277 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5280 for (i = 0; i <= opnum; i++)
5281 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5286 case RELOAD_FOR_OUTADDR_ADDRESS:
5287 /* Can't use a register if it is used for an output address
5288 for this operand or used as an output in this or a
5289 later operand. Note that multiple output operands are
5290 emitted in reverse order, so the conflicting ones are
5291 those with lower indices. */
5292 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5295 for (i = 0; i <= opnum; i++)
5296 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5301 case RELOAD_FOR_OPERAND_ADDRESS:
5302 for (i = 0; i < reload_n_operands; i++)
5303 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5306 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5307 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5309 case RELOAD_FOR_OPADDR_ADDR:
5310 for (i = 0; i < reload_n_operands; i++)
5311 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5314 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5316 case RELOAD_FOR_OUTPUT:
5317 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5318 outputs, or an operand address for this or an earlier output.
5319 Note that multiple output operands are emitted in reverse order,
5320 so the conflicting ones are those with higher indices. */
5321 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5324 for (i = 0; i < reload_n_operands; i++)
5325 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5328 for (i = opnum; i < reload_n_operands; i++)
5329 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5330 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5335 case RELOAD_FOR_INSN:
5336 for (i = 0; i < reload_n_operands; i++)
5337 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5338 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5341 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5342 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5344 case RELOAD_FOR_OTHER_ADDRESS:
5345 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5352 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5353 the number RELOADNUM, is still available in REGNO at the end of the insn.
5355 We can assume that the reload reg was already tested for availability
5356 at the time it is needed, and we should not check this again,
5357 in case the reg has already been marked in use. */
5360 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5362 int opnum = rld[reloadnum].opnum;
5363 enum reload_type type = rld[reloadnum].when_needed;
5366 /* See if there is a reload with the same type for this operand, using
5367 the same register. This case is not handled by the code below. */
5368 for (i = reloadnum + 1; i < n_reloads; i++)
5373 if (rld[i].opnum != opnum || rld[i].when_needed != type)
5375 reg = rld[i].reg_rtx;
5376 if (reg == NULL_RTX)
5378 nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5379 if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5386 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5387 its value must reach the end. */
5390 /* If this use is for part of the insn,
5391 its value reaches if no subsequent part uses the same register.
5392 Just like the above function, don't try to do this with lots
5395 case RELOAD_FOR_OTHER_ADDRESS:
5396 /* Here we check for everything else, since these don't conflict
5397 with anything else and everything comes later. */
5399 for (i = 0; i < reload_n_operands; i++)
5400 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5401 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5402 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5403 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5404 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5405 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5408 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5409 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5410 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5411 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5413 case RELOAD_FOR_INPUT_ADDRESS:
5414 case RELOAD_FOR_INPADDR_ADDRESS:
5415 /* Similar, except that we check only for this and subsequent inputs
5416 and the address of only subsequent inputs and we do not need
5417 to check for RELOAD_OTHER objects since they are known not to
5420 for (i = opnum; i < reload_n_operands; i++)
5421 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5424 for (i = opnum + 1; i < reload_n_operands; i++)
5425 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5426 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5429 for (i = 0; i < reload_n_operands; i++)
5430 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5431 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5432 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5435 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5438 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5439 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5440 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5442 case RELOAD_FOR_INPUT:
5443 /* Similar to input address, except we start at the next operand for
5444 both input and input address and we do not check for
5445 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5448 for (i = opnum + 1; i < reload_n_operands; i++)
5449 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5450 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5451 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5454 /* ... fall through ... */
5456 case RELOAD_FOR_OPERAND_ADDRESS:
5457 /* Check outputs and their addresses. */
5459 for (i = 0; i < reload_n_operands; i++)
5460 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5461 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5462 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5465 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5467 case RELOAD_FOR_OPADDR_ADDR:
5468 for (i = 0; i < reload_n_operands; i++)
5469 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5470 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5471 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5474 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5475 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5476 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5478 case RELOAD_FOR_INSN:
5479 /* These conflict with other outputs with RELOAD_OTHER. So
5480 we need only check for output addresses. */
5482 opnum = reload_n_operands;
5484 /* ... fall through ... */
5486 case RELOAD_FOR_OUTPUT:
5487 case RELOAD_FOR_OUTPUT_ADDRESS:
5488 case RELOAD_FOR_OUTADDR_ADDRESS:
5489 /* We already know these can't conflict with a later output. So the
5490 only thing to check are later output addresses.
5491 Note that multiple output operands are emitted in reverse order,
5492 so the conflicting ones are those with lower indices. */
5493 for (i = 0; i < opnum; i++)
5494 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5495 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5505 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5506 every register in the range [REGNO, REGNO + NREGS). */
5509 reload_regs_reach_end_p (unsigned int regno, int nregs, int reloadnum)
5513 for (i = 0; i < nregs; i++)
5514 if (!reload_reg_reaches_end_p (regno + i, reloadnum))
5520 /* Returns whether R1 and R2 are uniquely chained: the value of one
5521 is used by the other, and that value is not used by any other
5522 reload for this insn. This is used to partially undo the decision
5523 made in find_reloads when in the case of multiple
5524 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5525 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5526 reloads. This code tries to avoid the conflict created by that
5527 change. It might be cleaner to explicitly keep track of which
5528 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5529 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5530 this after the fact. */
5532 reloads_unique_chain_p (int r1, int r2)
5536 /* We only check input reloads. */
5537 if (! rld[r1].in || ! rld[r2].in)
5540 /* Avoid anything with output reloads. */
5541 if (rld[r1].out || rld[r2].out)
5544 /* "chained" means one reload is a component of the other reload,
5545 not the same as the other reload. */
5546 if (rld[r1].opnum != rld[r2].opnum
5547 || rtx_equal_p (rld[r1].in, rld[r2].in)
5548 || rld[r1].optional || rld[r2].optional
5549 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5550 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5553 for (i = 0; i < n_reloads; i ++)
5554 /* Look for input reloads that aren't our two */
5555 if (i != r1 && i != r2 && rld[i].in)
5557 /* If our reload is mentioned at all, it isn't a simple chain. */
5558 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5564 /* The recursive function change all occurrences of WHAT in *WHERE
5567 substitute (rtx *where, const_rtx what, rtx repl)
5576 if (*where == what || rtx_equal_p (*where, what))
5578 /* Record the location of the changed rtx. */
5579 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5584 code = GET_CODE (*where);
5585 fmt = GET_RTX_FORMAT (code);
5586 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5592 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5593 substitute (&XVECEXP (*where, i, j), what, repl);
5595 else if (fmt[i] == 'e')
5596 substitute (&XEXP (*where, i), what, repl);
5600 /* The function returns TRUE if chain of reload R1 and R2 (in any
5601 order) can be evaluated without usage of intermediate register for
5602 the reload containing another reload. It is important to see
5603 gen_reload to understand what the function is trying to do. As an
5604 example, let us have reload chain
5607 r1: <something> + const
5609 and reload R2 got reload reg HR. The function returns true if
5610 there is a correct insn HR = HR + <something>. Otherwise,
5611 gen_reload will use intermediate register (and this is the reload
5612 reg for R1) to reload <something>.
5614 We need this function to find a conflict for chain reloads. In our
5615 example, if HR = HR + <something> is incorrect insn, then we cannot
5616 use HR as a reload register for R2. If we do use it then we get a
5625 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5627 /* Assume other cases in gen_reload are not possible for
5628 chain reloads or do need an intermediate hard registers. */
5632 rtx last = get_last_insn ();
5634 /* Make r2 a component of r1. */
5635 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5641 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5642 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5643 gcc_assert (regno >= 0);
5644 out = gen_rtx_REG (rld[r1].mode, regno);
5646 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5648 /* If IN is a paradoxical SUBREG, remove it and try to put the
5649 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5650 strip_paradoxical_subreg (&in, &out);
5652 if (GET_CODE (in) == PLUS
5653 && (REG_P (XEXP (in, 0))
5654 || GET_CODE (XEXP (in, 0)) == SUBREG
5655 || MEM_P (XEXP (in, 0)))
5656 && (REG_P (XEXP (in, 1))
5657 || GET_CODE (XEXP (in, 1)) == SUBREG
5658 || CONSTANT_P (XEXP (in, 1))
5659 || MEM_P (XEXP (in, 1))))
5661 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5662 code = recog_memoized (insn);
5667 extract_insn (insn);
5668 /* We want constrain operands to treat this insn strictly in
5669 its validity determination, i.e., the way it would after
5670 reload has completed. */
5671 result = constrain_operands (1);
5674 delete_insns_since (last);
5677 /* Restore the original value at each changed address within R1. */
5678 while (!VEC_empty (rtx_p, substitute_stack))
5680 rtx *where = VEC_pop (rtx_p, substitute_stack);
5681 *where = rld[r2].in;
5687 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5690 This function uses the same algorithm as reload_reg_free_p above. */
5693 reloads_conflict (int r1, int r2)
5695 enum reload_type r1_type = rld[r1].when_needed;
5696 enum reload_type r2_type = rld[r2].when_needed;
5697 int r1_opnum = rld[r1].opnum;
5698 int r2_opnum = rld[r2].opnum;
5700 /* RELOAD_OTHER conflicts with everything. */
5701 if (r2_type == RELOAD_OTHER)
5704 /* Otherwise, check conflicts differently for each type. */
5708 case RELOAD_FOR_INPUT:
5709 return (r2_type == RELOAD_FOR_INSN
5710 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5711 || r2_type == RELOAD_FOR_OPADDR_ADDR
5712 || r2_type == RELOAD_FOR_INPUT
5713 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5714 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5715 && r2_opnum > r1_opnum));
5717 case RELOAD_FOR_INPUT_ADDRESS:
5718 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5719 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5721 case RELOAD_FOR_INPADDR_ADDRESS:
5722 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5723 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5725 case RELOAD_FOR_OUTPUT_ADDRESS:
5726 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5727 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5729 case RELOAD_FOR_OUTADDR_ADDRESS:
5730 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5731 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5733 case RELOAD_FOR_OPERAND_ADDRESS:
5734 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5735 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5736 && (!reloads_unique_chain_p (r1, r2)
5737 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5739 case RELOAD_FOR_OPADDR_ADDR:
5740 return (r2_type == RELOAD_FOR_INPUT
5741 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5743 case RELOAD_FOR_OUTPUT:
5744 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5745 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5746 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5747 && r2_opnum >= r1_opnum));
5749 case RELOAD_FOR_INSN:
5750 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5751 || r2_type == RELOAD_FOR_INSN
5752 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5754 case RELOAD_FOR_OTHER_ADDRESS:
5755 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5765 /* Indexed by reload number, 1 if incoming value
5766 inherited from previous insns. */
5767 static char reload_inherited[MAX_RELOADS];
5769 /* For an inherited reload, this is the insn the reload was inherited from,
5770 if we know it. Otherwise, this is 0. */
5771 static rtx reload_inheritance_insn[MAX_RELOADS];
5773 /* If nonzero, this is a place to get the value of the reload,
5774 rather than using reload_in. */
5775 static rtx reload_override_in[MAX_RELOADS];
5777 /* For each reload, the hard register number of the register used,
5778 or -1 if we did not need a register for this reload. */
5779 static int reload_spill_index[MAX_RELOADS];
5781 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5782 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5784 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5785 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5787 /* Subroutine of free_for_value_p, used to check a single register.
5788 START_REGNO is the starting regno of the full reload register
5789 (possibly comprising multiple hard registers) that we are considering. */
5792 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5793 enum reload_type type, rtx value, rtx out,
5794 int reloadnum, int ignore_address_reloads)
5797 /* Set if we see an input reload that must not share its reload register
5798 with any new earlyclobber, but might otherwise share the reload
5799 register with an output or input-output reload. */
5800 int check_earlyclobber = 0;
5804 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5807 if (out == const0_rtx)
5813 /* We use some pseudo 'time' value to check if the lifetimes of the
5814 new register use would overlap with the one of a previous reload
5815 that is not read-only or uses a different value.
5816 The 'time' used doesn't have to be linear in any shape or form, just
5818 Some reload types use different 'buckets' for each operand.
5819 So there are MAX_RECOG_OPERANDS different time values for each
5821 We compute TIME1 as the time when the register for the prospective
5822 new reload ceases to be live, and TIME2 for each existing
5823 reload as the time when that the reload register of that reload
5825 Where there is little to be gained by exact lifetime calculations,
5826 we just make conservative assumptions, i.e. a longer lifetime;
5827 this is done in the 'default:' cases. */
5830 case RELOAD_FOR_OTHER_ADDRESS:
5831 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5832 time1 = copy ? 0 : 1;
5835 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5837 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5838 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5839 respectively, to the time values for these, we get distinct time
5840 values. To get distinct time values for each operand, we have to
5841 multiply opnum by at least three. We round that up to four because
5842 multiply by four is often cheaper. */
5843 case RELOAD_FOR_INPADDR_ADDRESS:
5844 time1 = opnum * 4 + 2;
5846 case RELOAD_FOR_INPUT_ADDRESS:
5847 time1 = opnum * 4 + 3;
5849 case RELOAD_FOR_INPUT:
5850 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5851 executes (inclusive). */
5852 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5854 case RELOAD_FOR_OPADDR_ADDR:
5856 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5857 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5859 case RELOAD_FOR_OPERAND_ADDRESS:
5860 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5862 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5864 case RELOAD_FOR_OUTADDR_ADDRESS:
5865 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5867 case RELOAD_FOR_OUTPUT_ADDRESS:
5868 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5871 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5874 for (i = 0; i < n_reloads; i++)
5876 rtx reg = rld[i].reg_rtx;
5877 if (reg && REG_P (reg)
5878 && ((unsigned) regno - true_regnum (reg)
5879 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5882 rtx other_input = rld[i].in;
5884 /* If the other reload loads the same input value, that
5885 will not cause a conflict only if it's loading it into
5886 the same register. */
5887 if (true_regnum (reg) != start_regno)
5888 other_input = NULL_RTX;
5889 if (! other_input || ! rtx_equal_p (other_input, value)
5890 || rld[i].out || out)
5893 switch (rld[i].when_needed)
5895 case RELOAD_FOR_OTHER_ADDRESS:
5898 case RELOAD_FOR_INPADDR_ADDRESS:
5899 /* find_reloads makes sure that a
5900 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5901 by at most one - the first -
5902 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5903 address reload is inherited, the address address reload
5904 goes away, so we can ignore this conflict. */
5905 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5906 && ignore_address_reloads
5907 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5908 Then the address address is still needed to store
5909 back the new address. */
5910 && ! rld[reloadnum].out)
5912 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5913 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5915 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5916 && ignore_address_reloads
5917 /* Unless we are reloading an auto_inc expression. */
5918 && ! rld[reloadnum].out)
5920 time2 = rld[i].opnum * 4 + 2;
5922 case RELOAD_FOR_INPUT_ADDRESS:
5923 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5924 && ignore_address_reloads
5925 && ! rld[reloadnum].out)
5927 time2 = rld[i].opnum * 4 + 3;
5929 case RELOAD_FOR_INPUT:
5930 time2 = rld[i].opnum * 4 + 4;
5931 check_earlyclobber = 1;
5933 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5934 == MAX_RECOG_OPERAND * 4 */
5935 case RELOAD_FOR_OPADDR_ADDR:
5936 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5937 && ignore_address_reloads
5938 && ! rld[reloadnum].out)
5940 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5942 case RELOAD_FOR_OPERAND_ADDRESS:
5943 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5944 check_earlyclobber = 1;
5946 case RELOAD_FOR_INSN:
5947 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5949 case RELOAD_FOR_OUTPUT:
5950 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5951 instruction is executed. */
5952 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5954 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5955 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5957 case RELOAD_FOR_OUTADDR_ADDRESS:
5958 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5959 && ignore_address_reloads
5960 && ! rld[reloadnum].out)
5962 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5964 case RELOAD_FOR_OUTPUT_ADDRESS:
5965 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5968 /* If there is no conflict in the input part, handle this
5969 like an output reload. */
5970 if (! rld[i].in || rtx_equal_p (other_input, value))
5972 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5973 /* Earlyclobbered outputs must conflict with inputs. */
5974 if (earlyclobber_operand_p (rld[i].out))
5975 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5980 /* RELOAD_OTHER might be live beyond instruction execution,
5981 but this is not obvious when we set time2 = 1. So check
5982 here if there might be a problem with the new reload
5983 clobbering the register used by the RELOAD_OTHER. */
5991 && (! rld[i].in || rld[i].out
5992 || ! rtx_equal_p (other_input, value)))
5993 || (out && rld[reloadnum].out_reg
5994 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
6000 /* Earlyclobbered outputs must conflict with inputs. */
6001 if (check_earlyclobber && out && earlyclobber_operand_p (out))
6007 /* Return 1 if the value in reload reg REGNO, as used by a reload
6008 needed for the part of the insn specified by OPNUM and TYPE,
6009 may be used to load VALUE into it.
6011 MODE is the mode in which the register is used, this is needed to
6012 determine how many hard regs to test.
6014 Other read-only reloads with the same value do not conflict
6015 unless OUT is nonzero and these other reloads have to live while
6016 output reloads live.
6017 If OUT is CONST0_RTX, this is a special case: it means that the
6018 test should not be for using register REGNO as reload register, but
6019 for copying from register REGNO into the reload register.
6021 RELOADNUM is the number of the reload we want to load this value for;
6022 a reload does not conflict with itself.
6024 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6025 reloads that load an address for the very reload we are considering.
6027 The caller has to make sure that there is no conflict with the return
6031 free_for_value_p (int regno, enum machine_mode mode, int opnum,
6032 enum reload_type type, rtx value, rtx out, int reloadnum,
6033 int ignore_address_reloads)
6035 int nregs = hard_regno_nregs[regno][mode];
6037 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6038 value, out, reloadnum,
6039 ignore_address_reloads))
6044 /* Return nonzero if the rtx X is invariant over the current function. */
6045 /* ??? Actually, the places where we use this expect exactly what is
6046 tested here, and not everything that is function invariant. In
6047 particular, the frame pointer and arg pointer are special cased;
6048 pic_offset_table_rtx is not, and we must not spill these things to
6052 function_invariant_p (const_rtx x)
6056 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6058 if (GET_CODE (x) == PLUS
6059 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6060 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6065 /* Determine whether the reload reg X overlaps any rtx'es used for
6066 overriding inheritance. Return nonzero if so. */
6069 conflicts_with_override (rtx x)
6072 for (i = 0; i < n_reloads; i++)
6073 if (reload_override_in[i]
6074 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6079 /* Give an error message saying we failed to find a reload for INSN,
6080 and clear out reload R. */
6082 failed_reload (rtx insn, int r)
6084 if (asm_noperands (PATTERN (insn)) < 0)
6085 /* It's the compiler's fault. */
6086 fatal_insn ("could not find a spill register", insn);
6088 /* It's the user's fault; the operand's mode and constraint
6089 don't match. Disable this reload so we don't crash in final. */
6090 error_for_asm (insn,
6091 "%<asm%> operand constraint incompatible with operand size");
6095 rld[r].optional = 1;
6096 rld[r].secondary_p = 1;
6099 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6100 for reload R. If it's valid, get an rtx for it. Return nonzero if
6103 set_reload_reg (int i, int r)
6105 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6107 int regno ATTRIBUTE_UNUSED;
6108 rtx reg = spill_reg_rtx[i];
6110 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6111 spill_reg_rtx[i] = reg
6112 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6114 regno = true_regnum (reg);
6116 /* Detect when the reload reg can't hold the reload mode.
6117 This used to be one `if', but Sequent compiler can't handle that. */
6118 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6120 enum machine_mode test_mode = VOIDmode;
6122 test_mode = GET_MODE (rld[r].in);
6123 /* If rld[r].in has VOIDmode, it means we will load it
6124 in whatever mode the reload reg has: to wit, rld[r].mode.
6125 We have already tested that for validity. */
6126 /* Aside from that, we need to test that the expressions
6127 to reload from or into have modes which are valid for this
6128 reload register. Otherwise the reload insns would be invalid. */
6129 if (! (rld[r].in != 0 && test_mode != VOIDmode
6130 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6131 if (! (rld[r].out != 0
6132 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6134 /* The reg is OK. */
6137 /* Mark as in use for this insn the reload regs we use
6139 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6140 rld[r].when_needed, rld[r].mode);
6142 rld[r].reg_rtx = reg;
6143 reload_spill_index[r] = spill_regs[i];
6150 /* Find a spill register to use as a reload register for reload R.
6151 LAST_RELOAD is nonzero if this is the last reload for the insn being
6154 Set rld[R].reg_rtx to the register allocated.
6156 We return 1 if successful, or 0 if we couldn't find a spill reg and
6157 we didn't change anything. */
6160 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6165 /* If we put this reload ahead, thinking it is a group,
6166 then insist on finding a group. Otherwise we can grab a
6167 reg that some other reload needs.
6168 (That can happen when we have a 68000 DATA_OR_FP_REG
6169 which is a group of data regs or one fp reg.)
6170 We need not be so restrictive if there are no more reloads
6173 ??? Really it would be nicer to have smarter handling
6174 for that kind of reg class, where a problem like this is normal.
6175 Perhaps those classes should be avoided for reloading
6176 by use of more alternatives. */
6178 int force_group = rld[r].nregs > 1 && ! last_reload;
6180 /* If we want a single register and haven't yet found one,
6181 take any reg in the right class and not in use.
6182 If we want a consecutive group, here is where we look for it.
6184 We use three passes so we can first look for reload regs to
6185 reuse, which are already in use for other reloads in this insn,
6186 and only then use additional registers which are not "bad", then
6187 finally any register.
6189 I think that maximizing reuse is needed to make sure we don't
6190 run out of reload regs. Suppose we have three reloads, and
6191 reloads A and B can share regs. These need two regs.
6192 Suppose A and B are given different regs.
6193 That leaves none for C. */
6194 for (pass = 0; pass < 3; pass++)
6196 /* I is the index in spill_regs.
6197 We advance it round-robin between insns to use all spill regs
6198 equally, so that inherited reloads have a chance
6199 of leapfrogging each other. */
6203 for (count = 0; count < n_spills; count++)
6205 int rclass = (int) rld[r].rclass;
6211 regnum = spill_regs[i];
6213 if ((reload_reg_free_p (regnum, rld[r].opnum,
6216 /* We check reload_reg_used to make sure we
6217 don't clobber the return register. */
6218 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6219 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6220 rld[r].when_needed, rld[r].in,
6222 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6223 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6224 /* Look first for regs to share, then for unshared. But
6225 don't share regs used for inherited reloads; they are
6226 the ones we want to preserve. */
6228 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6230 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6233 int nr = hard_regno_nregs[regnum][rld[r].mode];
6235 /* During the second pass we want to avoid reload registers
6236 which are "bad" for this reload. */
6238 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6241 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6242 (on 68000) got us two FP regs. If NR is 1,
6243 we would reject both of them. */
6246 /* If we need only one reg, we have already won. */
6249 /* But reject a single reg if we demand a group. */
6254 /* Otherwise check that as many consecutive regs as we need
6255 are available here. */
6258 int regno = regnum + nr - 1;
6259 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6260 && spill_reg_order[regno] >= 0
6261 && reload_reg_free_p (regno, rld[r].opnum,
6262 rld[r].when_needed)))
6271 /* If we found something on the current pass, omit later passes. */
6272 if (count < n_spills)
6276 /* We should have found a spill register by now. */
6277 if (count >= n_spills)
6280 /* I is the index in SPILL_REG_RTX of the reload register we are to
6281 allocate. Get an rtx for it and find its register number. */
6283 return set_reload_reg (i, r);
6286 /* Initialize all the tables needed to allocate reload registers.
6287 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6288 is the array we use to restore the reg_rtx field for every reload. */
6291 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6295 for (i = 0; i < n_reloads; i++)
6296 rld[i].reg_rtx = save_reload_reg_rtx[i];
6298 memset (reload_inherited, 0, MAX_RELOADS);
6299 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6300 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6302 CLEAR_HARD_REG_SET (reload_reg_used);
6303 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6304 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6305 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6306 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6307 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6309 CLEAR_HARD_REG_SET (reg_used_in_insn);
6312 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6313 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6314 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6315 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6316 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6317 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6320 for (i = 0; i < reload_n_operands; i++)
6322 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6323 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6324 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6325 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6326 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6327 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6330 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6332 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6334 for (i = 0; i < n_reloads; i++)
6335 /* If we have already decided to use a certain register,
6336 don't use it in another way. */
6338 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6339 rld[i].when_needed, rld[i].mode);
6342 /* Assign hard reg targets for the pseudo-registers we must reload
6343 into hard regs for this insn.
6344 Also output the instructions to copy them in and out of the hard regs.
6346 For machines with register classes, we are responsible for
6347 finding a reload reg in the proper class. */
6350 choose_reload_regs (struct insn_chain *chain)
6352 rtx insn = chain->insn;
6354 unsigned int max_group_size = 1;
6355 enum reg_class group_class = NO_REGS;
6356 int pass, win, inheritance;
6358 rtx save_reload_reg_rtx[MAX_RELOADS];
6360 /* In order to be certain of getting the registers we need,
6361 we must sort the reloads into order of increasing register class.
6362 Then our grabbing of reload registers will parallel the process
6363 that provided the reload registers.
6365 Also note whether any of the reloads wants a consecutive group of regs.
6366 If so, record the maximum size of the group desired and what
6367 register class contains all the groups needed by this insn. */
6369 for (j = 0; j < n_reloads; j++)
6371 reload_order[j] = j;
6372 if (rld[j].reg_rtx != NULL_RTX)
6374 gcc_assert (REG_P (rld[j].reg_rtx)
6375 && HARD_REGISTER_P (rld[j].reg_rtx));
6376 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6379 reload_spill_index[j] = -1;
6381 if (rld[j].nregs > 1)
6383 max_group_size = MAX (rld[j].nregs, max_group_size);
6385 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6388 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6392 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6394 /* If -O, try first with inheritance, then turning it off.
6395 If not -O, don't do inheritance.
6396 Using inheritance when not optimizing leads to paradoxes
6397 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6398 because one side of the comparison might be inherited. */
6400 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6402 choose_reload_regs_init (chain, save_reload_reg_rtx);
6404 /* Process the reloads in order of preference just found.
6405 Beyond this point, subregs can be found in reload_reg_rtx.
6407 This used to look for an existing reloaded home for all of the
6408 reloads, and only then perform any new reloads. But that could lose
6409 if the reloads were done out of reg-class order because a later
6410 reload with a looser constraint might have an old home in a register
6411 needed by an earlier reload with a tighter constraint.
6413 To solve this, we make two passes over the reloads, in the order
6414 described above. In the first pass we try to inherit a reload
6415 from a previous insn. If there is a later reload that needs a
6416 class that is a proper subset of the class being processed, we must
6417 also allocate a spill register during the first pass.
6419 Then make a second pass over the reloads to allocate any reloads
6420 that haven't been given registers yet. */
6422 for (j = 0; j < n_reloads; j++)
6424 int r = reload_order[j];
6425 rtx search_equiv = NULL_RTX;
6427 /* Ignore reloads that got marked inoperative. */
6428 if (rld[r].out == 0 && rld[r].in == 0
6429 && ! rld[r].secondary_p)
6432 /* If find_reloads chose to use reload_in or reload_out as a reload
6433 register, we don't need to chose one. Otherwise, try even if it
6434 found one since we might save an insn if we find the value lying
6436 Try also when reload_in is a pseudo without a hard reg. */
6437 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6438 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6439 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6440 && !MEM_P (rld[r].in)
6441 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6444 #if 0 /* No longer needed for correct operation.
6445 It might give better code, or might not; worth an experiment? */
6446 /* If this is an optional reload, we can't inherit from earlier insns
6447 until we are sure that any non-optional reloads have been allocated.
6448 The following code takes advantage of the fact that optional reloads
6449 are at the end of reload_order. */
6450 if (rld[r].optional != 0)
6451 for (i = 0; i < j; i++)
6452 if ((rld[reload_order[i]].out != 0
6453 || rld[reload_order[i]].in != 0
6454 || rld[reload_order[i]].secondary_p)
6455 && ! rld[reload_order[i]].optional
6456 && rld[reload_order[i]].reg_rtx == 0)
6457 allocate_reload_reg (chain, reload_order[i], 0);
6460 /* First see if this pseudo is already available as reloaded
6461 for a previous insn. We cannot try to inherit for reloads
6462 that are smaller than the maximum number of registers needed
6463 for groups unless the register we would allocate cannot be used
6466 We could check here to see if this is a secondary reload for
6467 an object that is already in a register of the desired class.
6468 This would avoid the need for the secondary reload register.
6469 But this is complex because we can't easily determine what
6470 objects might want to be loaded via this reload. So let a
6471 register be allocated here. In `emit_reload_insns' we suppress
6472 one of the loads in the case described above. */
6478 enum machine_mode mode = VOIDmode;
6482 else if (REG_P (rld[r].in))
6484 regno = REGNO (rld[r].in);
6485 mode = GET_MODE (rld[r].in);
6487 else if (REG_P (rld[r].in_reg))
6489 regno = REGNO (rld[r].in_reg);
6490 mode = GET_MODE (rld[r].in_reg);
6492 else if (GET_CODE (rld[r].in_reg) == SUBREG
6493 && REG_P (SUBREG_REG (rld[r].in_reg)))
6495 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6496 if (regno < FIRST_PSEUDO_REGISTER)
6497 regno = subreg_regno (rld[r].in_reg);
6499 byte = SUBREG_BYTE (rld[r].in_reg);
6500 mode = GET_MODE (rld[r].in_reg);
6503 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6504 && REG_P (XEXP (rld[r].in_reg, 0)))
6506 regno = REGNO (XEXP (rld[r].in_reg, 0));
6507 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6508 rld[r].out = rld[r].in;
6512 /* This won't work, since REGNO can be a pseudo reg number.
6513 Also, it takes much more hair to keep track of all the things
6514 that can invalidate an inherited reload of part of a pseudoreg. */
6515 else if (GET_CODE (rld[r].in) == SUBREG
6516 && REG_P (SUBREG_REG (rld[r].in)))
6517 regno = subreg_regno (rld[r].in);
6521 && reg_last_reload_reg[regno] != 0
6522 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6523 >= GET_MODE_SIZE (mode) + byte)
6524 #ifdef CANNOT_CHANGE_MODE_CLASS
6525 /* Verify that the register it's in can be used in
6527 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6528 GET_MODE (reg_last_reload_reg[regno]),
6533 enum reg_class rclass = rld[r].rclass, last_class;
6534 rtx last_reg = reg_last_reload_reg[regno];
6536 i = REGNO (last_reg);
6537 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6538 last_class = REGNO_REG_CLASS (i);
6540 if (reg_reloaded_contents[i] == regno
6541 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6542 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6543 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6544 /* Even if we can't use this register as a reload
6545 register, we might use it for reload_override_in,
6546 if copying it to the desired class is cheap
6548 || ((register_move_cost (mode, last_class, rclass)
6549 < memory_move_cost (mode, rclass, true))
6550 && (secondary_reload_class (1, rclass, mode,
6553 #ifdef SECONDARY_MEMORY_NEEDED
6554 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6559 && (rld[r].nregs == max_group_size
6560 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6562 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6563 rld[r].when_needed, rld[r].in,
6566 /* If a group is needed, verify that all the subsequent
6567 registers still have their values intact. */
6568 int nr = hard_regno_nregs[i][rld[r].mode];
6571 for (k = 1; k < nr; k++)
6572 if (reg_reloaded_contents[i + k] != regno
6573 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6581 last_reg = (GET_MODE (last_reg) == mode
6582 ? last_reg : gen_rtx_REG (mode, i));
6585 for (k = 0; k < nr; k++)
6586 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6589 /* We found a register that contains the
6590 value we need. If this register is the
6591 same as an `earlyclobber' operand of the
6592 current insn, just mark it as a place to
6593 reload from since we can't use it as the
6594 reload register itself. */
6596 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6597 if (reg_overlap_mentioned_for_reload_p
6598 (reg_last_reload_reg[regno],
6599 reload_earlyclobbers[i1]))
6602 if (i1 != n_earlyclobbers
6603 || ! (free_for_value_p (i, rld[r].mode,
6605 rld[r].when_needed, rld[r].in,
6607 /* Don't use it if we'd clobber a pseudo reg. */
6608 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6610 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6611 /* Don't clobber the frame pointer. */
6612 || (i == HARD_FRAME_POINTER_REGNUM
6613 && frame_pointer_needed
6615 /* Don't really use the inherited spill reg
6616 if we need it wider than we've got it. */
6617 || (GET_MODE_SIZE (rld[r].mode)
6618 > GET_MODE_SIZE (mode))
6621 /* If find_reloads chose reload_out as reload
6622 register, stay with it - that leaves the
6623 inherited register for subsequent reloads. */
6624 || (rld[r].out && rld[r].reg_rtx
6625 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6627 if (! rld[r].optional)
6629 reload_override_in[r] = last_reg;
6630 reload_inheritance_insn[r]
6631 = reg_reloaded_insn[i];
6637 /* We can use this as a reload reg. */
6638 /* Mark the register as in use for this part of
6640 mark_reload_reg_in_use (i,
6644 rld[r].reg_rtx = last_reg;
6645 reload_inherited[r] = 1;
6646 reload_inheritance_insn[r]
6647 = reg_reloaded_insn[i];
6648 reload_spill_index[r] = i;
6649 for (k = 0; k < nr; k++)
6650 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6658 /* Here's another way to see if the value is already lying around. */
6661 && ! reload_inherited[r]
6663 && (CONSTANT_P (rld[r].in)
6664 || GET_CODE (rld[r].in) == PLUS
6665 || REG_P (rld[r].in)
6666 || MEM_P (rld[r].in))
6667 && (rld[r].nregs == max_group_size
6668 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6669 search_equiv = rld[r].in;
6674 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6675 -1, NULL, 0, rld[r].mode);
6681 regno = REGNO (equiv);
6684 /* This must be a SUBREG of a hard register.
6685 Make a new REG since this might be used in an
6686 address and not all machines support SUBREGs
6688 gcc_assert (GET_CODE (equiv) == SUBREG);
6689 regno = subreg_regno (equiv);
6690 equiv = gen_rtx_REG (rld[r].mode, regno);
6691 /* If we choose EQUIV as the reload register, but the
6692 loop below decides to cancel the inheritance, we'll
6693 end up reloading EQUIV in rld[r].mode, not the mode
6694 it had originally. That isn't safe when EQUIV isn't
6695 available as a spill register since its value might
6696 still be live at this point. */
6697 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6698 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6703 /* If we found a spill reg, reject it unless it is free
6704 and of the desired class. */
6708 int bad_for_class = 0;
6709 int max_regno = regno + rld[r].nregs;
6711 for (i = regno; i < max_regno; i++)
6713 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6715 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6720 && ! free_for_value_p (regno, rld[r].mode,
6721 rld[r].opnum, rld[r].when_needed,
6722 rld[r].in, rld[r].out, r, 1))
6727 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6730 /* We found a register that contains the value we need.
6731 If this register is the same as an `earlyclobber' operand
6732 of the current insn, just mark it as a place to reload from
6733 since we can't use it as the reload register itself. */
6736 for (i = 0; i < n_earlyclobbers; i++)
6737 if (reg_overlap_mentioned_for_reload_p (equiv,
6738 reload_earlyclobbers[i]))
6740 if (! rld[r].optional)
6741 reload_override_in[r] = equiv;
6746 /* If the equiv register we have found is explicitly clobbered
6747 in the current insn, it depends on the reload type if we
6748 can use it, use it for reload_override_in, or not at all.
6749 In particular, we then can't use EQUIV for a
6750 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6754 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6755 switch (rld[r].when_needed)
6757 case RELOAD_FOR_OTHER_ADDRESS:
6758 case RELOAD_FOR_INPADDR_ADDRESS:
6759 case RELOAD_FOR_INPUT_ADDRESS:
6760 case RELOAD_FOR_OPADDR_ADDR:
6763 case RELOAD_FOR_INPUT:
6764 case RELOAD_FOR_OPERAND_ADDRESS:
6765 if (! rld[r].optional)
6766 reload_override_in[r] = equiv;
6772 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6773 switch (rld[r].when_needed)
6775 case RELOAD_FOR_OTHER_ADDRESS:
6776 case RELOAD_FOR_INPADDR_ADDRESS:
6777 case RELOAD_FOR_INPUT_ADDRESS:
6778 case RELOAD_FOR_OPADDR_ADDR:
6779 case RELOAD_FOR_OPERAND_ADDRESS:
6780 case RELOAD_FOR_INPUT:
6783 if (! rld[r].optional)
6784 reload_override_in[r] = equiv;
6792 /* If we found an equivalent reg, say no code need be generated
6793 to load it, and use it as our reload reg. */
6795 && (regno != HARD_FRAME_POINTER_REGNUM
6796 || !frame_pointer_needed))
6798 int nr = hard_regno_nregs[regno][rld[r].mode];
6800 rld[r].reg_rtx = equiv;
6801 reload_spill_index[r] = regno;
6802 reload_inherited[r] = 1;
6804 /* If reg_reloaded_valid is not set for this register,
6805 there might be a stale spill_reg_store lying around.
6806 We must clear it, since otherwise emit_reload_insns
6807 might delete the store. */
6808 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6809 spill_reg_store[regno] = NULL_RTX;
6810 /* If any of the hard registers in EQUIV are spill
6811 registers, mark them as in use for this insn. */
6812 for (k = 0; k < nr; k++)
6814 i = spill_reg_order[regno + k];
6817 mark_reload_reg_in_use (regno, rld[r].opnum,
6820 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6827 /* If we found a register to use already, or if this is an optional
6828 reload, we are done. */
6829 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6833 /* No longer needed for correct operation. Might or might
6834 not give better code on the average. Want to experiment? */
6836 /* See if there is a later reload that has a class different from our
6837 class that intersects our class or that requires less register
6838 than our reload. If so, we must allocate a register to this
6839 reload now, since that reload might inherit a previous reload
6840 and take the only available register in our class. Don't do this
6841 for optional reloads since they will force all previous reloads
6842 to be allocated. Also don't do this for reloads that have been
6845 for (i = j + 1; i < n_reloads; i++)
6847 int s = reload_order[i];
6849 if ((rld[s].in == 0 && rld[s].out == 0
6850 && ! rld[s].secondary_p)
6854 if ((rld[s].rclass != rld[r].rclass
6855 && reg_classes_intersect_p (rld[r].rclass,
6857 || rld[s].nregs < rld[r].nregs)
6864 allocate_reload_reg (chain, r, j == n_reloads - 1);
6868 /* Now allocate reload registers for anything non-optional that
6869 didn't get one yet. */
6870 for (j = 0; j < n_reloads; j++)
6872 int r = reload_order[j];
6874 /* Ignore reloads that got marked inoperative. */
6875 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6878 /* Skip reloads that already have a register allocated or are
6880 if (rld[r].reg_rtx != 0 || rld[r].optional)
6883 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6887 /* If that loop got all the way, we have won. */
6894 /* Loop around and try without any inheritance. */
6899 /* First undo everything done by the failed attempt
6900 to allocate with inheritance. */
6901 choose_reload_regs_init (chain, save_reload_reg_rtx);
6903 /* Some sanity tests to verify that the reloads found in the first
6904 pass are identical to the ones we have now. */
6905 gcc_assert (chain->n_reloads == n_reloads);
6907 for (i = 0; i < n_reloads; i++)
6909 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6911 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6912 for (j = 0; j < n_spills; j++)
6913 if (spill_regs[j] == chain->rld[i].regno)
6914 if (! set_reload_reg (j, i))
6915 failed_reload (chain->insn, i);
6919 /* If we thought we could inherit a reload, because it seemed that
6920 nothing else wanted the same reload register earlier in the insn,
6921 verify that assumption, now that all reloads have been assigned.
6922 Likewise for reloads where reload_override_in has been set. */
6924 /* If doing expensive optimizations, do one preliminary pass that doesn't
6925 cancel any inheritance, but removes reloads that have been needed only
6926 for reloads that we know can be inherited. */
6927 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6929 for (j = 0; j < n_reloads; j++)
6931 int r = reload_order[j];
6933 if (reload_inherited[r] && rld[r].reg_rtx)
6934 check_reg = rld[r].reg_rtx;
6935 else if (reload_override_in[r]
6936 && (REG_P (reload_override_in[r])
6937 || GET_CODE (reload_override_in[r]) == SUBREG))
6938 check_reg = reload_override_in[r];
6941 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6942 rld[r].opnum, rld[r].when_needed, rld[r].in,
6943 (reload_inherited[r]
6944 ? rld[r].out : const0_rtx),
6949 reload_inherited[r] = 0;
6950 reload_override_in[r] = 0;
6952 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6953 reload_override_in, then we do not need its related
6954 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6955 likewise for other reload types.
6956 We handle this by removing a reload when its only replacement
6957 is mentioned in reload_in of the reload we are going to inherit.
6958 A special case are auto_inc expressions; even if the input is
6959 inherited, we still need the address for the output. We can
6960 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6961 If we succeeded removing some reload and we are doing a preliminary
6962 pass just to remove such reloads, make another pass, since the
6963 removal of one reload might allow us to inherit another one. */
6965 && rld[r].out != rld[r].in
6966 && remove_address_replacements (rld[r].in) && pass)
6971 /* Now that reload_override_in is known valid,
6972 actually override reload_in. */
6973 for (j = 0; j < n_reloads; j++)
6974 if (reload_override_in[j])
6975 rld[j].in = reload_override_in[j];
6977 /* If this reload won't be done because it has been canceled or is
6978 optional and not inherited, clear reload_reg_rtx so other
6979 routines (such as subst_reloads) don't get confused. */
6980 for (j = 0; j < n_reloads; j++)
6981 if (rld[j].reg_rtx != 0
6982 && ((rld[j].optional && ! reload_inherited[j])
6983 || (rld[j].in == 0 && rld[j].out == 0
6984 && ! rld[j].secondary_p)))
6986 int regno = true_regnum (rld[j].reg_rtx);
6988 if (spill_reg_order[regno] >= 0)
6989 clear_reload_reg_in_use (regno, rld[j].opnum,
6990 rld[j].when_needed, rld[j].mode);
6992 reload_spill_index[j] = -1;
6995 /* Record which pseudos and which spill regs have output reloads. */
6996 for (j = 0; j < n_reloads; j++)
6998 int r = reload_order[j];
7000 i = reload_spill_index[r];
7002 /* I is nonneg if this reload uses a register.
7003 If rld[r].reg_rtx is 0, this is an optional reload
7004 that we opted to ignore. */
7005 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7006 && rld[r].reg_rtx != 0)
7008 int nregno = REGNO (rld[r].out_reg);
7011 if (nregno < FIRST_PSEUDO_REGISTER)
7012 nr = hard_regno_nregs[nregno][rld[r].mode];
7015 SET_REGNO_REG_SET (®_has_output_reload,
7019 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
7021 gcc_assert (rld[r].when_needed == RELOAD_OTHER
7022 || rld[r].when_needed == RELOAD_FOR_OUTPUT
7023 || rld[r].when_needed == RELOAD_FOR_INSN);
7028 /* Deallocate the reload register for reload R. This is called from
7029 remove_address_replacements. */
7032 deallocate_reload_reg (int r)
7036 if (! rld[r].reg_rtx)
7038 regno = true_regnum (rld[r].reg_rtx);
7040 if (spill_reg_order[regno] >= 0)
7041 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7043 reload_spill_index[r] = -1;
7046 /* These arrays are filled by emit_reload_insns and its subroutines. */
7047 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
7048 static rtx other_input_address_reload_insns = 0;
7049 static rtx other_input_reload_insns = 0;
7050 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
7051 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7052 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7053 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7054 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7055 static rtx operand_reload_insns = 0;
7056 static rtx other_operand_reload_insns = 0;
7057 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7059 /* Values to be put in spill_reg_store are put here first. */
7060 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7061 static HARD_REG_SET reg_reloaded_died;
7063 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7064 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7065 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7066 adjusted register, and return true. Otherwise, return false. */
7068 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7069 enum reg_class new_class,
7070 enum machine_mode new_mode)
7075 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7077 unsigned regno = REGNO (reg);
7079 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7081 if (GET_MODE (reg) != new_mode)
7083 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7085 if (hard_regno_nregs[regno][new_mode]
7086 > hard_regno_nregs[regno][GET_MODE (reg)])
7088 reg = reload_adjust_reg_for_mode (reg, new_mode);
7096 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7097 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7098 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7099 adjusted register, and return true. Otherwise, return false. */
7101 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7102 enum insn_code icode)
7105 enum reg_class new_class = scratch_reload_class (icode);
7106 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7108 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7109 new_class, new_mode);
7112 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7113 has the number J. OLD contains the value to be used as input. */
7116 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7119 rtx insn = chain->insn;
7121 rtx oldequiv_reg = 0;
7124 enum machine_mode mode;
7127 /* delete_output_reload is only invoked properly if old contains
7128 the original pseudo register. Since this is replaced with a
7129 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7130 find the pseudo in RELOAD_IN_REG. */
7131 if (reload_override_in[j]
7132 && REG_P (rl->in_reg))
7139 else if (REG_P (oldequiv))
7140 oldequiv_reg = oldequiv;
7141 else if (GET_CODE (oldequiv) == SUBREG)
7142 oldequiv_reg = SUBREG_REG (oldequiv);
7144 reloadreg = reload_reg_rtx_for_input[j];
7145 mode = GET_MODE (reloadreg);
7147 /* If we are reloading from a register that was recently stored in
7148 with an output-reload, see if we can prove there was
7149 actually no need to store the old value in it. */
7151 if (optimize && REG_P (oldequiv)
7152 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7153 && spill_reg_store[REGNO (oldequiv)]
7155 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7156 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7158 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7160 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7163 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7164 oldequiv = SUBREG_REG (oldequiv);
7165 if (GET_MODE (oldequiv) != VOIDmode
7166 && mode != GET_MODE (oldequiv))
7167 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7169 /* Switch to the right place to emit the reload insns. */
7170 switch (rl->when_needed)
7173 where = &other_input_reload_insns;
7175 case RELOAD_FOR_INPUT:
7176 where = &input_reload_insns[rl->opnum];
7178 case RELOAD_FOR_INPUT_ADDRESS:
7179 where = &input_address_reload_insns[rl->opnum];
7181 case RELOAD_FOR_INPADDR_ADDRESS:
7182 where = &inpaddr_address_reload_insns[rl->opnum];
7184 case RELOAD_FOR_OUTPUT_ADDRESS:
7185 where = &output_address_reload_insns[rl->opnum];
7187 case RELOAD_FOR_OUTADDR_ADDRESS:
7188 where = &outaddr_address_reload_insns[rl->opnum];
7190 case RELOAD_FOR_OPERAND_ADDRESS:
7191 where = &operand_reload_insns;
7193 case RELOAD_FOR_OPADDR_ADDR:
7194 where = &other_operand_reload_insns;
7196 case RELOAD_FOR_OTHER_ADDRESS:
7197 where = &other_input_address_reload_insns;
7203 push_to_sequence (*where);
7205 /* Auto-increment addresses must be reloaded in a special way. */
7206 if (rl->out && ! rl->out_reg)
7208 /* We are not going to bother supporting the case where a
7209 incremented register can't be copied directly from
7210 OLDEQUIV since this seems highly unlikely. */
7211 gcc_assert (rl->secondary_in_reload < 0);
7213 if (reload_inherited[j])
7214 oldequiv = reloadreg;
7216 old = XEXP (rl->in_reg, 0);
7218 /* Prevent normal processing of this reload. */
7220 /* Output a special code sequence for this case, and forget about
7221 spill reg information. */
7222 new_spill_reg_store[REGNO (reloadreg)] = NULL;
7223 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7226 /* If we are reloading a pseudo-register that was set by the previous
7227 insn, see if we can get rid of that pseudo-register entirely
7228 by redirecting the previous insn into our reload register. */
7230 else if (optimize && REG_P (old)
7231 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7232 && dead_or_set_p (insn, old)
7233 /* This is unsafe if some other reload
7234 uses the same reg first. */
7235 && ! conflicts_with_override (reloadreg)
7236 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7237 rl->when_needed, old, rl->out, j, 0))
7239 rtx temp = PREV_INSN (insn);
7240 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7241 temp = PREV_INSN (temp);
7243 && NONJUMP_INSN_P (temp)
7244 && GET_CODE (PATTERN (temp)) == SET
7245 && SET_DEST (PATTERN (temp)) == old
7246 /* Make sure we can access insn_operand_constraint. */
7247 && asm_noperands (PATTERN (temp)) < 0
7248 /* This is unsafe if operand occurs more than once in current
7249 insn. Perhaps some occurrences aren't reloaded. */
7250 && count_occurrences (PATTERN (insn), old, 0) == 1)
7252 rtx old = SET_DEST (PATTERN (temp));
7253 /* Store into the reload register instead of the pseudo. */
7254 SET_DEST (PATTERN (temp)) = reloadreg;
7256 /* Verify that resulting insn is valid. */
7257 extract_insn (temp);
7258 if (constrain_operands (1))
7260 /* If the previous insn is an output reload, the source is
7261 a reload register, and its spill_reg_store entry will
7262 contain the previous destination. This is now
7264 if (REG_P (SET_SRC (PATTERN (temp)))
7265 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7267 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7268 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7271 /* If these are the only uses of the pseudo reg,
7272 pretend for GDB it lives in the reload reg we used. */
7273 if (REG_N_DEATHS (REGNO (old)) == 1
7274 && REG_N_SETS (REGNO (old)) == 1)
7276 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7277 if (ira_conflicts_p)
7278 /* Inform IRA about the change. */
7279 ira_mark_allocation_change (REGNO (old));
7280 alter_reg (REGNO (old), -1, false);
7284 /* Adjust any debug insns between temp and insn. */
7285 while ((temp = NEXT_INSN (temp)) != insn)
7286 if (DEBUG_INSN_P (temp))
7287 replace_rtx (PATTERN (temp), old, reloadreg);
7289 gcc_assert (NOTE_P (temp));
7293 SET_DEST (PATTERN (temp)) = old;
7298 /* We can't do that, so output an insn to load RELOADREG. */
7300 /* If we have a secondary reload, pick up the secondary register
7301 and icode, if any. If OLDEQUIV and OLD are different or
7302 if this is an in-out reload, recompute whether or not we
7303 still need a secondary register and what the icode should
7304 be. If we still need a secondary register and the class or
7305 icode is different, go back to reloading from OLD if using
7306 OLDEQUIV means that we got the wrong type of register. We
7307 cannot have different class or icode due to an in-out reload
7308 because we don't make such reloads when both the input and
7309 output need secondary reload registers. */
7311 if (! special && rl->secondary_in_reload >= 0)
7313 rtx second_reload_reg = 0;
7314 rtx third_reload_reg = 0;
7315 int secondary_reload = rl->secondary_in_reload;
7316 rtx real_oldequiv = oldequiv;
7319 enum insn_code icode;
7320 enum insn_code tertiary_icode = CODE_FOR_nothing;
7322 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7323 and similarly for OLD.
7324 See comments in get_secondary_reload in reload.c. */
7325 /* If it is a pseudo that cannot be replaced with its
7326 equivalent MEM, we must fall back to reload_in, which
7327 will have all the necessary substitutions registered.
7328 Likewise for a pseudo that can't be replaced with its
7329 equivalent constant.
7331 Take extra care for subregs of such pseudos. Note that
7332 we cannot use reg_equiv_mem in this case because it is
7333 not in the right mode. */
7336 if (GET_CODE (tmp) == SUBREG)
7337 tmp = SUBREG_REG (tmp);
7339 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7340 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7341 || reg_equiv_constant (REGNO (tmp)) != 0))
7343 if (! reg_equiv_mem (REGNO (tmp))
7344 || num_not_at_initial_offset
7345 || GET_CODE (oldequiv) == SUBREG)
7346 real_oldequiv = rl->in;
7348 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7352 if (GET_CODE (tmp) == SUBREG)
7353 tmp = SUBREG_REG (tmp);
7355 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7356 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7357 || reg_equiv_constant (REGNO (tmp)) != 0))
7359 if (! reg_equiv_mem (REGNO (tmp))
7360 || num_not_at_initial_offset
7361 || GET_CODE (old) == SUBREG)
7364 real_old = reg_equiv_mem (REGNO (tmp));
7367 second_reload_reg = rld[secondary_reload].reg_rtx;
7368 if (rld[secondary_reload].secondary_in_reload >= 0)
7370 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7372 third_reload_reg = rld[tertiary_reload].reg_rtx;
7373 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7374 /* We'd have to add more code for quartary reloads. */
7375 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7377 icode = rl->secondary_in_icode;
7379 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7380 || (rl->in != 0 && rl->out != 0))
7382 secondary_reload_info sri, sri2;
7383 enum reg_class new_class, new_t_class;
7385 sri.icode = CODE_FOR_nothing;
7386 sri.prev_sri = NULL;
7388 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7392 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7393 second_reload_reg = 0;
7394 else if (new_class == NO_REGS)
7396 if (reload_adjust_reg_for_icode (&second_reload_reg,
7398 (enum insn_code) sri.icode))
7400 icode = (enum insn_code) sri.icode;
7401 third_reload_reg = 0;
7406 real_oldequiv = real_old;
7409 else if (sri.icode != CODE_FOR_nothing)
7410 /* We currently lack a way to express this in reloads. */
7414 sri2.icode = CODE_FOR_nothing;
7415 sri2.prev_sri = &sri;
7417 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7420 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7422 if (reload_adjust_reg_for_temp (&second_reload_reg,
7426 third_reload_reg = 0;
7427 tertiary_icode = (enum insn_code) sri2.icode;
7432 real_oldequiv = real_old;
7435 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7437 rtx intermediate = second_reload_reg;
7439 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7441 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7445 second_reload_reg = intermediate;
7446 tertiary_icode = (enum insn_code) sri2.icode;
7451 real_oldequiv = real_old;
7454 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7456 rtx intermediate = second_reload_reg;
7458 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7460 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7463 second_reload_reg = intermediate;
7464 tertiary_icode = (enum insn_code) sri2.icode;
7469 real_oldequiv = real_old;
7474 /* This could be handled more intelligently too. */
7476 real_oldequiv = real_old;
7481 /* If we still need a secondary reload register, check
7482 to see if it is being used as a scratch or intermediate
7483 register and generate code appropriately. If we need
7484 a scratch register, use REAL_OLDEQUIV since the form of
7485 the insn may depend on the actual address if it is
7488 if (second_reload_reg)
7490 if (icode != CODE_FOR_nothing)
7492 /* We'd have to add extra code to handle this case. */
7493 gcc_assert (!third_reload_reg);
7495 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7496 second_reload_reg));
7501 /* See if we need a scratch register to load the
7502 intermediate register (a tertiary reload). */
7503 if (tertiary_icode != CODE_FOR_nothing)
7505 emit_insn ((GEN_FCN (tertiary_icode)
7506 (second_reload_reg, real_oldequiv,
7507 third_reload_reg)));
7509 else if (third_reload_reg)
7511 gen_reload (third_reload_reg, real_oldequiv,
7514 gen_reload (second_reload_reg, third_reload_reg,
7519 gen_reload (second_reload_reg, real_oldequiv,
7523 oldequiv = second_reload_reg;
7528 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7530 rtx real_oldequiv = oldequiv;
7532 if ((REG_P (oldequiv)
7533 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7534 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7535 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7536 || (GET_CODE (oldequiv) == SUBREG
7537 && REG_P (SUBREG_REG (oldequiv))
7538 && (REGNO (SUBREG_REG (oldequiv))
7539 >= FIRST_PSEUDO_REGISTER)
7540 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7541 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7542 || (CONSTANT_P (oldequiv)
7543 && (targetm.preferred_reload_class (oldequiv,
7544 REGNO_REG_CLASS (REGNO (reloadreg)))
7546 real_oldequiv = rl->in;
7547 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7551 if (cfun->can_throw_non_call_exceptions)
7552 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7554 /* End this sequence. */
7555 *where = get_insns ();
7558 /* Update reload_override_in so that delete_address_reloads_1
7559 can see the actual register usage. */
7561 reload_override_in[j] = oldequiv;
7564 /* Generate insns to for the output reload RL, which is for the insn described
7565 by CHAIN and has the number J. */
7567 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7571 rtx insn = chain->insn;
7574 enum machine_mode mode;
7578 if (rl->when_needed == RELOAD_OTHER)
7581 push_to_sequence (output_reload_insns[rl->opnum]);
7583 rl_reg_rtx = reload_reg_rtx_for_output[j];
7584 mode = GET_MODE (rl_reg_rtx);
7586 reloadreg = rl_reg_rtx;
7588 /* If we need two reload regs, set RELOADREG to the intermediate
7589 one, since it will be stored into OLD. We might need a secondary
7590 register only for an input reload, so check again here. */
7592 if (rl->secondary_out_reload >= 0)
7595 int secondary_reload = rl->secondary_out_reload;
7596 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7598 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7599 && reg_equiv_mem (REGNO (old)) != 0)
7600 real_old = reg_equiv_mem (REGNO (old));
7602 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7604 rtx second_reloadreg = reloadreg;
7605 reloadreg = rld[secondary_reload].reg_rtx;
7607 /* See if RELOADREG is to be used as a scratch register
7608 or as an intermediate register. */
7609 if (rl->secondary_out_icode != CODE_FOR_nothing)
7611 /* We'd have to add extra code to handle this case. */
7612 gcc_assert (tertiary_reload < 0);
7614 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7615 (real_old, second_reloadreg, reloadreg)));
7620 /* See if we need both a scratch and intermediate reload
7623 enum insn_code tertiary_icode
7624 = rld[secondary_reload].secondary_out_icode;
7626 /* We'd have to add more code for quartary reloads. */
7627 gcc_assert (tertiary_reload < 0
7628 || rld[tertiary_reload].secondary_out_reload < 0);
7630 if (GET_MODE (reloadreg) != mode)
7631 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7633 if (tertiary_icode != CODE_FOR_nothing)
7635 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7637 /* Copy primary reload reg to secondary reload reg.
7638 (Note that these have been swapped above, then
7639 secondary reload reg to OLD using our insn.) */
7641 /* If REAL_OLD is a paradoxical SUBREG, remove it
7642 and try to put the opposite SUBREG on
7644 strip_paradoxical_subreg (&real_old, &reloadreg);
7646 gen_reload (reloadreg, second_reloadreg,
7647 rl->opnum, rl->when_needed);
7648 emit_insn ((GEN_FCN (tertiary_icode)
7649 (real_old, reloadreg, third_reloadreg)));
7655 /* Copy between the reload regs here and then to
7658 gen_reload (reloadreg, second_reloadreg,
7659 rl->opnum, rl->when_needed);
7660 if (tertiary_reload >= 0)
7662 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7664 gen_reload (third_reloadreg, reloadreg,
7665 rl->opnum, rl->when_needed);
7666 reloadreg = third_reloadreg;
7673 /* Output the last reload insn. */
7678 /* Don't output the last reload if OLD is not the dest of
7679 INSN and is in the src and is clobbered by INSN. */
7680 if (! flag_expensive_optimizations
7682 || !(set = single_set (insn))
7683 || rtx_equal_p (old, SET_DEST (set))
7684 || !reg_mentioned_p (old, SET_SRC (set))
7685 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7686 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7687 gen_reload (old, reloadreg, rl->opnum,
7691 /* Look at all insns we emitted, just to be safe. */
7692 for (p = get_insns (); p; p = NEXT_INSN (p))
7695 rtx pat = PATTERN (p);
7697 /* If this output reload doesn't come from a spill reg,
7698 clear any memory of reloaded copies of the pseudo reg.
7699 If this output reload comes from a spill reg,
7700 reg_has_output_reload will make this do nothing. */
7701 note_stores (pat, forget_old_reloads_1, NULL);
7703 if (reg_mentioned_p (rl_reg_rtx, pat))
7705 rtx set = single_set (insn);
7706 if (reload_spill_index[j] < 0
7708 && SET_SRC (set) == rl_reg_rtx)
7710 int src = REGNO (SET_SRC (set));
7712 reload_spill_index[j] = src;
7713 SET_HARD_REG_BIT (reg_is_output_reload, src);
7714 if (find_regno_note (insn, REG_DEAD, src))
7715 SET_HARD_REG_BIT (reg_reloaded_died, src);
7717 if (HARD_REGISTER_P (rl_reg_rtx))
7719 int s = rl->secondary_out_reload;
7720 set = single_set (p);
7721 /* If this reload copies only to the secondary reload
7722 register, the secondary reload does the actual
7724 if (s >= 0 && set == NULL_RTX)
7725 /* We can't tell what function the secondary reload
7726 has and where the actual store to the pseudo is
7727 made; leave new_spill_reg_store alone. */
7730 && SET_SRC (set) == rl_reg_rtx
7731 && SET_DEST (set) == rld[s].reg_rtx)
7733 /* Usually the next instruction will be the
7734 secondary reload insn; if we can confirm
7735 that it is, setting new_spill_reg_store to
7736 that insn will allow an extra optimization. */
7737 rtx s_reg = rld[s].reg_rtx;
7738 rtx next = NEXT_INSN (p);
7739 rld[s].out = rl->out;
7740 rld[s].out_reg = rl->out_reg;
7741 set = single_set (next);
7742 if (set && SET_SRC (set) == s_reg
7743 && ! new_spill_reg_store[REGNO (s_reg)])
7745 SET_HARD_REG_BIT (reg_is_output_reload,
7747 new_spill_reg_store[REGNO (s_reg)] = next;
7751 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7756 if (rl->when_needed == RELOAD_OTHER)
7758 emit_insn (other_output_reload_insns[rl->opnum]);
7759 other_output_reload_insns[rl->opnum] = get_insns ();
7762 output_reload_insns[rl->opnum] = get_insns ();
7764 if (cfun->can_throw_non_call_exceptions)
7765 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7770 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7771 and has the number J. */
7773 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7775 rtx insn = chain->insn;
7776 rtx old = (rl->in && MEM_P (rl->in)
7777 ? rl->in_reg : rl->in);
7778 rtx reg_rtx = rl->reg_rtx;
7782 enum machine_mode mode;
7784 /* Determine the mode to reload in.
7785 This is very tricky because we have three to choose from.
7786 There is the mode the insn operand wants (rl->inmode).
7787 There is the mode of the reload register RELOADREG.
7788 There is the intrinsic mode of the operand, which we could find
7789 by stripping some SUBREGs.
7790 It turns out that RELOADREG's mode is irrelevant:
7791 we can change that arbitrarily.
7793 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7794 then the reload reg may not support QImode moves, so use SImode.
7795 If foo is in memory due to spilling a pseudo reg, this is safe,
7796 because the QImode value is in the least significant part of a
7797 slot big enough for a SImode. If foo is some other sort of
7798 memory reference, then it is impossible to reload this case,
7799 so previous passes had better make sure this never happens.
7801 Then consider a one-word union which has SImode and one of its
7802 members is a float, being fetched as (SUBREG:SF union:SI).
7803 We must fetch that as SFmode because we could be loading into
7804 a float-only register. In this case OLD's mode is correct.
7806 Consider an immediate integer: it has VOIDmode. Here we need
7807 to get a mode from something else.
7809 In some cases, there is a fourth mode, the operand's
7810 containing mode. If the insn specifies a containing mode for
7811 this operand, it overrides all others.
7813 I am not sure whether the algorithm here is always right,
7814 but it does the right things in those cases. */
7816 mode = GET_MODE (old);
7817 if (mode == VOIDmode)
7820 /* We cannot use gen_lowpart_common since it can do the wrong thing
7821 when REG_RTX has a multi-word mode. Note that REG_RTX must
7822 always be a REG here. */
7823 if (GET_MODE (reg_rtx) != mode)
7824 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7826 reload_reg_rtx_for_input[j] = reg_rtx;
7829 /* AUTO_INC reloads need to be handled even if inherited. We got an
7830 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7831 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7832 && ! rtx_equal_p (reg_rtx, old)
7834 emit_input_reload_insns (chain, rld + j, old, j);
7836 /* When inheriting a wider reload, we have a MEM in rl->in,
7837 e.g. inheriting a SImode output reload for
7838 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7839 if (optimize && reload_inherited[j] && rl->in
7841 && MEM_P (rl->in_reg)
7842 && reload_spill_index[j] >= 0
7843 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7844 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7846 /* If we are reloading a register that was recently stored in with an
7847 output-reload, see if we can prove there was
7848 actually no need to store the old value in it. */
7851 && (reload_inherited[j] || reload_override_in[j])
7854 && spill_reg_store[REGNO (reg_rtx)] != 0
7856 /* There doesn't seem to be any reason to restrict this to pseudos
7857 and doing so loses in the case where we are copying from a
7858 register of the wrong class. */
7859 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7861 /* The insn might have already some references to stackslots
7862 replaced by MEMs, while reload_out_reg still names the
7864 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7865 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7866 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7869 /* Do output reloading for reload RL, which is for the insn described by
7870 CHAIN and has the number J.
7871 ??? At some point we need to support handling output reloads of
7872 JUMP_INSNs or insns that set cc0. */
7874 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7877 rtx insn = chain->insn;
7878 /* If this is an output reload that stores something that is
7879 not loaded in this same reload, see if we can eliminate a previous
7881 rtx pseudo = rl->out_reg;
7882 rtx reg_rtx = rl->reg_rtx;
7884 if (rl->out && reg_rtx)
7886 enum machine_mode mode;
7888 /* Determine the mode to reload in.
7889 See comments above (for input reloading). */
7890 mode = GET_MODE (rl->out);
7891 if (mode == VOIDmode)
7893 /* VOIDmode should never happen for an output. */
7894 if (asm_noperands (PATTERN (insn)) < 0)
7895 /* It's the compiler's fault. */
7896 fatal_insn ("VOIDmode on an output", insn);
7897 error_for_asm (insn, "output operand is constant in %<asm%>");
7898 /* Prevent crash--use something we know is valid. */
7900 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7902 if (GET_MODE (reg_rtx) != mode)
7903 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7905 reload_reg_rtx_for_output[j] = reg_rtx;
7910 && ! rtx_equal_p (rl->in_reg, pseudo)
7911 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7912 && reg_last_reload_reg[REGNO (pseudo)])
7914 int pseudo_no = REGNO (pseudo);
7915 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7917 /* We don't need to test full validity of last_regno for
7918 inherit here; we only want to know if the store actually
7919 matches the pseudo. */
7920 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7921 && reg_reloaded_contents[last_regno] == pseudo_no
7922 && spill_reg_store[last_regno]
7923 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7924 delete_output_reload (insn, j, last_regno, reg_rtx);
7930 || rtx_equal_p (old, reg_rtx))
7933 /* An output operand that dies right away does need a reload,
7934 but need not be copied from it. Show the new location in the
7936 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7937 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7939 XEXP (note, 0) = reg_rtx;
7942 /* Likewise for a SUBREG of an operand that dies. */
7943 else if (GET_CODE (old) == SUBREG
7944 && REG_P (SUBREG_REG (old))
7945 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7948 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7951 else if (GET_CODE (old) == SCRATCH)
7952 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7953 but we don't want to make an output reload. */
7956 /* If is a JUMP_INSN, we can't support output reloads yet. */
7957 gcc_assert (NONJUMP_INSN_P (insn));
7959 emit_output_reload_insns (chain, rld + j, j);
7962 /* A reload copies values of MODE from register SRC to register DEST.
7963 Return true if it can be treated for inheritance purposes like a
7964 group of reloads, each one reloading a single hard register. The
7965 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7966 occupy the same number of hard registers. */
7969 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7970 int src ATTRIBUTE_UNUSED,
7971 enum machine_mode mode ATTRIBUTE_UNUSED)
7973 #ifdef CANNOT_CHANGE_MODE_CLASS
7974 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7975 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7981 /* Output insns to reload values in and out of the chosen reload regs. */
7984 emit_reload_insns (struct insn_chain *chain)
7986 rtx insn = chain->insn;
7990 CLEAR_HARD_REG_SET (reg_reloaded_died);
7992 for (j = 0; j < reload_n_operands; j++)
7993 input_reload_insns[j] = input_address_reload_insns[j]
7994 = inpaddr_address_reload_insns[j]
7995 = output_reload_insns[j] = output_address_reload_insns[j]
7996 = outaddr_address_reload_insns[j]
7997 = other_output_reload_insns[j] = 0;
7998 other_input_address_reload_insns = 0;
7999 other_input_reload_insns = 0;
8000 operand_reload_insns = 0;
8001 other_operand_reload_insns = 0;
8003 /* Dump reloads into the dump file. */
8006 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8007 debug_reload_to_stream (dump_file);
8010 /* Now output the instructions to copy the data into and out of the
8011 reload registers. Do these in the order that the reloads were reported,
8012 since reloads of base and index registers precede reloads of operands
8013 and the operands may need the base and index registers reloaded. */
8015 for (j = 0; j < n_reloads; j++)
8017 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8021 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8022 new_spill_reg_store[i] = 0;
8025 do_input_reload (chain, rld + j, j);
8026 do_output_reload (chain, rld + j, j);
8029 /* Now write all the insns we made for reloads in the order expected by
8030 the allocation functions. Prior to the insn being reloaded, we write
8031 the following reloads:
8033 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8035 RELOAD_OTHER reloads.
8037 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8038 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8039 RELOAD_FOR_INPUT reload for the operand.
8041 RELOAD_FOR_OPADDR_ADDRS reloads.
8043 RELOAD_FOR_OPERAND_ADDRESS reloads.
8045 After the insn being reloaded, we write the following:
8047 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8048 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8049 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8050 reloads for the operand. The RELOAD_OTHER output reloads are
8051 output in descending order by reload number. */
8053 emit_insn_before (other_input_address_reload_insns, insn);
8054 emit_insn_before (other_input_reload_insns, insn);
8056 for (j = 0; j < reload_n_operands; j++)
8058 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8059 emit_insn_before (input_address_reload_insns[j], insn);
8060 emit_insn_before (input_reload_insns[j], insn);
8063 emit_insn_before (other_operand_reload_insns, insn);
8064 emit_insn_before (operand_reload_insns, insn);
8066 for (j = 0; j < reload_n_operands; j++)
8068 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8069 x = emit_insn_after (output_address_reload_insns[j], x);
8070 x = emit_insn_after (output_reload_insns[j], x);
8071 emit_insn_after (other_output_reload_insns[j], x);
8074 /* For all the spill regs newly reloaded in this instruction,
8075 record what they were reloaded from, so subsequent instructions
8076 can inherit the reloads.
8078 Update spill_reg_store for the reloads of this insn.
8079 Copy the elements that were updated in the loop above. */
8081 for (j = 0; j < n_reloads; j++)
8083 int r = reload_order[j];
8084 int i = reload_spill_index[r];
8086 /* If this is a non-inherited input reload from a pseudo, we must
8087 clear any memory of a previous store to the same pseudo. Only do
8088 something if there will not be an output reload for the pseudo
8090 if (rld[r].in_reg != 0
8091 && ! (reload_inherited[r] || reload_override_in[r]))
8093 rtx reg = rld[r].in_reg;
8095 if (GET_CODE (reg) == SUBREG)
8096 reg = SUBREG_REG (reg);
8099 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8100 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8102 int nregno = REGNO (reg);
8104 if (reg_last_reload_reg[nregno])
8106 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8108 if (reg_reloaded_contents[last_regno] == nregno)
8109 spill_reg_store[last_regno] = 0;
8114 /* I is nonneg if this reload used a register.
8115 If rld[r].reg_rtx is 0, this is an optional reload
8116 that we opted to ignore. */
8118 if (i >= 0 && rld[r].reg_rtx != 0)
8120 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8123 /* For a multi register reload, we need to check if all or part
8124 of the value lives to the end. */
8125 for (k = 0; k < nr; k++)
8126 if (reload_reg_reaches_end_p (i + k, r))
8127 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8129 /* Maybe the spill reg contains a copy of reload_out. */
8131 && (REG_P (rld[r].out)
8133 ? REG_P (rld[r].out_reg)
8134 /* The reload value is an auto-modification of
8135 some kind. For PRE_INC, POST_INC, PRE_DEC
8136 and POST_DEC, we record an equivalence
8137 between the reload register and the operand
8138 on the optimistic assumption that we can make
8139 the equivalence hold. reload_as_needed must
8140 then either make it hold or invalidate the
8143 PRE_MODIFY and POST_MODIFY addresses are reloaded
8144 somewhat differently, and allowing them here leads
8146 : (GET_CODE (rld[r].out) != POST_MODIFY
8147 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8150 enum machine_mode mode;
8153 reg = reload_reg_rtx_for_output[r];
8154 mode = GET_MODE (reg);
8155 regno = REGNO (reg);
8156 nregs = hard_regno_nregs[regno][mode];
8157 if (reload_regs_reach_end_p (regno, nregs, r))
8159 rtx out = (REG_P (rld[r].out)
8163 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8164 int out_regno = REGNO (out);
8165 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8166 : hard_regno_nregs[out_regno][mode]);
8169 spill_reg_store[regno] = new_spill_reg_store[regno];
8170 spill_reg_stored_to[regno] = out;
8171 reg_last_reload_reg[out_regno] = reg;
8173 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8174 && nregs == out_nregs
8175 && inherit_piecemeal_p (out_regno, regno, mode));
8177 /* If OUT_REGNO is a hard register, it may occupy more than
8178 one register. If it does, say what is in the
8179 rest of the registers assuming that both registers
8180 agree on how many words the object takes. If not,
8181 invalidate the subsequent registers. */
8183 if (HARD_REGISTER_NUM_P (out_regno))
8184 for (k = 1; k < out_nregs; k++)
8185 reg_last_reload_reg[out_regno + k]
8186 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8188 /* Now do the inverse operation. */
8189 for (k = 0; k < nregs; k++)
8191 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8192 reg_reloaded_contents[regno + k]
8193 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8196 reg_reloaded_insn[regno + k] = insn;
8197 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8198 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8199 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8202 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8207 /* Maybe the spill reg contains a copy of reload_in. Only do
8208 something if there will not be an output reload for
8209 the register being reloaded. */
8210 else if (rld[r].out_reg == 0
8212 && ((REG_P (rld[r].in)
8213 && !HARD_REGISTER_P (rld[r].in)
8214 && !REGNO_REG_SET_P (®_has_output_reload,
8216 || (REG_P (rld[r].in_reg)
8217 && !REGNO_REG_SET_P (®_has_output_reload,
8218 REGNO (rld[r].in_reg))))
8219 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8222 enum machine_mode mode;
8225 reg = reload_reg_rtx_for_input[r];
8226 mode = GET_MODE (reg);
8227 regno = REGNO (reg);
8228 nregs = hard_regno_nregs[regno][mode];
8229 if (reload_regs_reach_end_p (regno, nregs, r))
8236 if (REG_P (rld[r].in)
8237 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8239 else if (REG_P (rld[r].in_reg))
8242 in = XEXP (rld[r].in_reg, 0);
8243 in_regno = REGNO (in);
8245 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8246 : hard_regno_nregs[in_regno][mode]);
8248 reg_last_reload_reg[in_regno] = reg;
8250 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8251 && nregs == in_nregs
8252 && inherit_piecemeal_p (regno, in_regno, mode));
8254 if (HARD_REGISTER_NUM_P (in_regno))
8255 for (k = 1; k < in_nregs; k++)
8256 reg_last_reload_reg[in_regno + k]
8257 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8259 /* Unless we inherited this reload, show we haven't
8260 recently done a store.
8261 Previous stores of inherited auto_inc expressions
8262 also have to be discarded. */
8263 if (! reload_inherited[r]
8264 || (rld[r].out && ! rld[r].out_reg))
8265 spill_reg_store[regno] = 0;
8267 for (k = 0; k < nregs; k++)
8269 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8270 reg_reloaded_contents[regno + k]
8271 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8274 reg_reloaded_insn[regno + k] = insn;
8275 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8276 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8277 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8280 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8287 /* The following if-statement was #if 0'd in 1.34 (or before...).
8288 It's reenabled in 1.35 because supposedly nothing else
8289 deals with this problem. */
8291 /* If a register gets output-reloaded from a non-spill register,
8292 that invalidates any previous reloaded copy of it.
8293 But forget_old_reloads_1 won't get to see it, because
8294 it thinks only about the original insn. So invalidate it here.
8295 Also do the same thing for RELOAD_OTHER constraints where the
8296 output is discarded. */
8298 && ((rld[r].out != 0
8299 && (REG_P (rld[r].out)
8300 || (MEM_P (rld[r].out)
8301 && REG_P (rld[r].out_reg))))
8302 || (rld[r].out == 0 && rld[r].out_reg
8303 && REG_P (rld[r].out_reg))))
8305 rtx out = ((rld[r].out && REG_P (rld[r].out))
8306 ? rld[r].out : rld[r].out_reg);
8307 int out_regno = REGNO (out);
8308 enum machine_mode mode = GET_MODE (out);
8310 /* REG_RTX is now set or clobbered by the main instruction.
8311 As the comment above explains, forget_old_reloads_1 only
8312 sees the original instruction, and there is no guarantee
8313 that the original instruction also clobbered REG_RTX.
8314 For example, if find_reloads sees that the input side of
8315 a matched operand pair dies in this instruction, it may
8316 use the input register as the reload register.
8318 Calling forget_old_reloads_1 is a waste of effort if
8319 REG_RTX is also the output register.
8321 If we know that REG_RTX holds the value of a pseudo
8322 register, the code after the call will record that fact. */
8323 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8324 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8326 if (!HARD_REGISTER_NUM_P (out_regno))
8328 rtx src_reg, store_insn = NULL_RTX;
8330 reg_last_reload_reg[out_regno] = 0;
8332 /* If we can find a hard register that is stored, record
8333 the storing insn so that we may delete this insn with
8334 delete_output_reload. */
8335 src_reg = reload_reg_rtx_for_output[r];
8337 /* If this is an optional reload, try to find the source reg
8338 from an input reload. */
8341 rtx set = single_set (insn);
8342 if (set && SET_DEST (set) == rld[r].out)
8346 src_reg = SET_SRC (set);
8348 for (k = 0; k < n_reloads; k++)
8350 if (rld[k].in == src_reg)
8352 src_reg = reload_reg_rtx_for_input[k];
8359 store_insn = new_spill_reg_store[REGNO (src_reg)];
8360 if (src_reg && REG_P (src_reg)
8361 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8363 int src_regno, src_nregs, k;
8366 gcc_assert (GET_MODE (src_reg) == mode);
8367 src_regno = REGNO (src_reg);
8368 src_nregs = hard_regno_nregs[src_regno][mode];
8369 /* The place where to find a death note varies with
8370 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8371 necessarily checked exactly in the code that moves
8372 notes, so just check both locations. */
8373 note = find_regno_note (insn, REG_DEAD, src_regno);
8374 if (! note && store_insn)
8375 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8376 for (k = 0; k < src_nregs; k++)
8378 spill_reg_store[src_regno + k] = store_insn;
8379 spill_reg_stored_to[src_regno + k] = out;
8380 reg_reloaded_contents[src_regno + k] = out_regno;
8381 reg_reloaded_insn[src_regno + k] = store_insn;
8382 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8383 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8384 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8386 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8389 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8391 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8393 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8395 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8397 reg_last_reload_reg[out_regno] = src_reg;
8398 /* We have to set reg_has_output_reload here, or else
8399 forget_old_reloads_1 will clear reg_last_reload_reg
8401 SET_REGNO_REG_SET (®_has_output_reload,
8407 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8409 for (k = 0; k < out_nregs; k++)
8410 reg_last_reload_reg[out_regno + k] = 0;
8414 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8417 /* Go through the motions to emit INSN and test if it is strictly valid.
8418 Return the emitted insn if valid, else return NULL. */
8421 emit_insn_if_valid_for_reload (rtx insn)
8423 rtx last = get_last_insn ();
8426 insn = emit_insn (insn);
8427 code = recog_memoized (insn);
8431 extract_insn (insn);
8432 /* We want constrain operands to treat this insn strictly in its
8433 validity determination, i.e., the way it would after reload has
8435 if (constrain_operands (1))
8439 delete_insns_since (last);
8443 /* Emit code to perform a reload from IN (which may be a reload register) to
8444 OUT (which may also be a reload register). IN or OUT is from operand
8445 OPNUM with reload type TYPE.
8447 Returns first insn emitted. */
8450 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8452 rtx last = get_last_insn ();
8455 /* If IN is a paradoxical SUBREG, remove it and try to put the
8456 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8457 if (!strip_paradoxical_subreg (&in, &out))
8458 strip_paradoxical_subreg (&out, &in);
8460 /* How to do this reload can get quite tricky. Normally, we are being
8461 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8462 register that didn't get a hard register. In that case we can just
8463 call emit_move_insn.
8465 We can also be asked to reload a PLUS that adds a register or a MEM to
8466 another register, constant or MEM. This can occur during frame pointer
8467 elimination and while reloading addresses. This case is handled by
8468 trying to emit a single insn to perform the add. If it is not valid,
8469 we use a two insn sequence.
8471 Or we can be asked to reload an unary operand that was a fragment of
8472 an addressing mode, into a register. If it isn't recognized as-is,
8473 we try making the unop operand and the reload-register the same:
8474 (set reg:X (unop:X expr:Y))
8475 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8477 Finally, we could be called to handle an 'o' constraint by putting
8478 an address into a register. In that case, we first try to do this
8479 with a named pattern of "reload_load_address". If no such pattern
8480 exists, we just emit a SET insn and hope for the best (it will normally
8481 be valid on machines that use 'o').
8483 This entire process is made complex because reload will never
8484 process the insns we generate here and so we must ensure that
8485 they will fit their constraints and also by the fact that parts of
8486 IN might be being reloaded separately and replaced with spill registers.
8487 Because of this, we are, in some sense, just guessing the right approach
8488 here. The one listed above seems to work.
8490 ??? At some point, this whole thing needs to be rethought. */
8492 if (GET_CODE (in) == PLUS
8493 && (REG_P (XEXP (in, 0))
8494 || GET_CODE (XEXP (in, 0)) == SUBREG
8495 || MEM_P (XEXP (in, 0)))
8496 && (REG_P (XEXP (in, 1))
8497 || GET_CODE (XEXP (in, 1)) == SUBREG
8498 || CONSTANT_P (XEXP (in, 1))
8499 || MEM_P (XEXP (in, 1))))
8501 /* We need to compute the sum of a register or a MEM and another
8502 register, constant, or MEM, and put it into the reload
8503 register. The best possible way of doing this is if the machine
8504 has a three-operand ADD insn that accepts the required operands.
8506 The simplest approach is to try to generate such an insn and see if it
8507 is recognized and matches its constraints. If so, it can be used.
8509 It might be better not to actually emit the insn unless it is valid,
8510 but we need to pass the insn as an operand to `recog' and
8511 `extract_insn' and it is simpler to emit and then delete the insn if
8512 not valid than to dummy things up. */
8514 rtx op0, op1, tem, insn;
8515 enum insn_code code;
8517 op0 = find_replacement (&XEXP (in, 0));
8518 op1 = find_replacement (&XEXP (in, 1));
8520 /* Since constraint checking is strict, commutativity won't be
8521 checked, so we need to do that here to avoid spurious failure
8522 if the add instruction is two-address and the second operand
8523 of the add is the same as the reload reg, which is frequently
8524 the case. If the insn would be A = B + A, rearrange it so
8525 it will be A = A + B as constrain_operands expects. */
8527 if (REG_P (XEXP (in, 1))
8528 && REGNO (out) == REGNO (XEXP (in, 1)))
8529 tem = op0, op0 = op1, op1 = tem;
8531 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8532 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8534 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8538 /* If that failed, we must use a conservative two-insn sequence.
8540 Use a move to copy one operand into the reload register. Prefer
8541 to reload a constant, MEM or pseudo since the move patterns can
8542 handle an arbitrary operand. If OP1 is not a constant, MEM or
8543 pseudo and OP1 is not a valid operand for an add instruction, then
8546 After reloading one of the operands into the reload register, add
8547 the reload register to the output register.
8549 If there is another way to do this for a specific machine, a
8550 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8553 code = optab_handler (add_optab, GET_MODE (out));
8555 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8557 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8558 || (code != CODE_FOR_nothing
8559 && !insn_operand_matches (code, 2, op1)))
8560 tem = op0, op0 = op1, op1 = tem;
8562 gen_reload (out, op0, opnum, type);
8564 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8565 This fixes a problem on the 32K where the stack pointer cannot
8566 be used as an operand of an add insn. */
8568 if (rtx_equal_p (op0, op1))
8571 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8574 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8575 set_unique_reg_note (insn, REG_EQUIV, in);
8579 /* If that failed, copy the address register to the reload register.
8580 Then add the constant to the reload register. */
8582 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8583 gen_reload (out, op1, opnum, type);
8584 insn = emit_insn (gen_add2_insn (out, op0));
8585 set_unique_reg_note (insn, REG_EQUIV, in);
8588 #ifdef SECONDARY_MEMORY_NEEDED
8589 /* If we need a memory location to do the move, do it that way. */
8590 else if ((REG_P (in)
8591 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8592 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8594 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8595 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8596 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8597 REGNO_REG_CLASS (reg_or_subregno (out)),
8600 /* Get the memory to use and rewrite both registers to its mode. */
8601 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8603 if (GET_MODE (loc) != GET_MODE (out))
8604 out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8606 if (GET_MODE (loc) != GET_MODE (in))
8607 in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8609 gen_reload (loc, in, opnum, type);
8610 gen_reload (out, loc, opnum, type);
8613 else if (REG_P (out) && UNARY_P (in))
8620 op1 = find_replacement (&XEXP (in, 0));
8621 if (op1 != XEXP (in, 0))
8622 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8624 /* First, try a plain SET. */
8625 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8629 /* If that failed, move the inner operand to the reload
8630 register, and try the same unop with the inner expression
8631 replaced with the reload register. */
8633 if (GET_MODE (op1) != GET_MODE (out))
8634 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8638 gen_reload (out_moded, op1, opnum, type);
8641 = gen_rtx_SET (VOIDmode, out,
8642 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8644 insn = emit_insn_if_valid_for_reload (insn);
8647 set_unique_reg_note (insn, REG_EQUIV, in);
8651 fatal_insn ("failure trying to reload:", set);
8653 /* If IN is a simple operand, use gen_move_insn. */
8654 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8656 tem = emit_insn (gen_move_insn (out, in));
8657 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8658 mark_jump_label (in, tem, 0);
8661 #ifdef HAVE_reload_load_address
8662 else if (HAVE_reload_load_address)
8663 emit_insn (gen_reload_load_address (out, in));
8666 /* Otherwise, just write (set OUT IN) and hope for the best. */
8668 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8670 /* Return the first insn emitted.
8671 We can not just return get_last_insn, because there may have
8672 been multiple instructions emitted. Also note that gen_move_insn may
8673 emit more than one insn itself, so we can not assume that there is one
8674 insn emitted per emit_insn_before call. */
8676 return last ? NEXT_INSN (last) : get_insns ();
8679 /* Delete a previously made output-reload whose result we now believe
8680 is not needed. First we double-check.
8682 INSN is the insn now being processed.
8683 LAST_RELOAD_REG is the hard register number for which we want to delete
8684 the last output reload.
8685 J is the reload-number that originally used REG. The caller has made
8686 certain that reload J doesn't use REG any longer for input.
8687 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8690 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8692 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8693 rtx reg = spill_reg_stored_to[last_reload_reg];
8696 int n_inherited = 0;
8702 /* It is possible that this reload has been only used to set another reload
8703 we eliminated earlier and thus deleted this instruction too. */
8704 if (INSN_DELETED_P (output_reload_insn))
8707 /* Get the raw pseudo-register referred to. */
8709 while (GET_CODE (reg) == SUBREG)
8710 reg = SUBREG_REG (reg);
8711 substed = reg_equiv_memory_loc (REGNO (reg));
8713 /* This is unsafe if the operand occurs more often in the current
8714 insn than it is inherited. */
8715 for (k = n_reloads - 1; k >= 0; k--)
8717 rtx reg2 = rld[k].in;
8720 if (MEM_P (reg2) || reload_override_in[k])
8721 reg2 = rld[k].in_reg;
8723 if (rld[k].out && ! rld[k].out_reg)
8724 reg2 = XEXP (rld[k].in_reg, 0);
8726 while (GET_CODE (reg2) == SUBREG)
8727 reg2 = SUBREG_REG (reg2);
8728 if (rtx_equal_p (reg2, reg))
8730 if (reload_inherited[k] || reload_override_in[k] || k == j)
8736 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8737 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8738 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8741 n_occurrences += count_occurrences (PATTERN (insn),
8742 eliminate_regs (substed, VOIDmode,
8744 for (i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8746 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8747 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8749 if (n_occurrences > n_inherited)
8752 regno = REGNO (reg);
8753 if (regno >= FIRST_PSEUDO_REGISTER)
8756 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8758 /* If the pseudo-reg we are reloading is no longer referenced
8759 anywhere between the store into it and here,
8760 and we're within the same basic block, then the value can only
8761 pass through the reload reg and end up here.
8762 Otherwise, give up--return. */
8763 for (i1 = NEXT_INSN (output_reload_insn);
8764 i1 != insn; i1 = NEXT_INSN (i1))
8766 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8768 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8769 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8771 /* If this is USE in front of INSN, we only have to check that
8772 there are no more references than accounted for by inheritance. */
8773 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8775 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8776 i1 = NEXT_INSN (i1);
8778 if (n_occurrences <= n_inherited && i1 == insn)
8784 /* We will be deleting the insn. Remove the spill reg information. */
8785 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8787 spill_reg_store[last_reload_reg + k] = 0;
8788 spill_reg_stored_to[last_reload_reg + k] = 0;
8791 /* The caller has already checked that REG dies or is set in INSN.
8792 It has also checked that we are optimizing, and thus some
8793 inaccuracies in the debugging information are acceptable.
8794 So we could just delete output_reload_insn. But in some cases
8795 we can improve the debugging information without sacrificing
8796 optimization - maybe even improving the code: See if the pseudo
8797 reg has been completely replaced with reload regs. If so, delete
8798 the store insn and forget we had a stack slot for the pseudo. */
8799 if (rld[j].out != rld[j].in
8800 && REG_N_DEATHS (REGNO (reg)) == 1
8801 && REG_N_SETS (REGNO (reg)) == 1
8802 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8803 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8807 /* We know that it was used only between here and the beginning of
8808 the current basic block. (We also know that the last use before
8809 INSN was the output reload we are thinking of deleting, but never
8810 mind that.) Search that range; see if any ref remains. */
8811 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8813 rtx set = single_set (i2);
8815 /* Uses which just store in the pseudo don't count,
8816 since if they are the only uses, they are dead. */
8817 if (set != 0 && SET_DEST (set) == reg)
8822 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8823 && reg_mentioned_p (reg, PATTERN (i2)))
8825 /* Some other ref remains; just delete the output reload we
8827 delete_address_reloads (output_reload_insn, insn);
8828 delete_insn (output_reload_insn);
8833 /* Delete the now-dead stores into this pseudo. Note that this
8834 loop also takes care of deleting output_reload_insn. */
8835 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8837 rtx set = single_set (i2);
8839 if (set != 0 && SET_DEST (set) == reg)
8841 delete_address_reloads (i2, insn);
8849 /* For the debugging info, say the pseudo lives in this reload reg. */
8850 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8851 if (ira_conflicts_p)
8852 /* Inform IRA about the change. */
8853 ira_mark_allocation_change (REGNO (reg));
8854 alter_reg (REGNO (reg), -1, false);
8858 delete_address_reloads (output_reload_insn, insn);
8859 delete_insn (output_reload_insn);
8863 /* We are going to delete DEAD_INSN. Recursively delete loads of
8864 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8865 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8867 delete_address_reloads (rtx dead_insn, rtx current_insn)
8869 rtx set = single_set (dead_insn);
8870 rtx set2, dst, prev, next;
8873 rtx dst = SET_DEST (set);
8875 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8877 /* If we deleted the store from a reloaded post_{in,de}c expression,
8878 we can delete the matching adds. */
8879 prev = PREV_INSN (dead_insn);
8880 next = NEXT_INSN (dead_insn);
8881 if (! prev || ! next)
8883 set = single_set (next);
8884 set2 = single_set (prev);
8886 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8887 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8888 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8890 dst = SET_DEST (set);
8891 if (! rtx_equal_p (dst, SET_DEST (set2))
8892 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8893 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8894 || (INTVAL (XEXP (SET_SRC (set), 1))
8895 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8897 delete_related_insns (prev);
8898 delete_related_insns (next);
8901 /* Subfunction of delete_address_reloads: process registers found in X. */
8903 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8905 rtx prev, set, dst, i2;
8907 enum rtx_code code = GET_CODE (x);
8911 const char *fmt = GET_RTX_FORMAT (code);
8912 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8915 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8916 else if (fmt[i] == 'E')
8918 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8919 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8926 if (spill_reg_order[REGNO (x)] < 0)
8929 /* Scan backwards for the insn that sets x. This might be a way back due
8931 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8933 code = GET_CODE (prev);
8934 if (code == CODE_LABEL || code == JUMP_INSN)
8938 if (reg_set_p (x, PATTERN (prev)))
8940 if (reg_referenced_p (x, PATTERN (prev)))
8943 if (! prev || INSN_UID (prev) < reload_first_uid)
8945 /* Check that PREV only sets the reload register. */
8946 set = single_set (prev);
8949 dst = SET_DEST (set);
8951 || ! rtx_equal_p (dst, x))
8953 if (! reg_set_p (dst, PATTERN (dead_insn)))
8955 /* Check if DST was used in a later insn -
8956 it might have been inherited. */
8957 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8963 if (reg_referenced_p (dst, PATTERN (i2)))
8965 /* If there is a reference to the register in the current insn,
8966 it might be loaded in a non-inherited reload. If no other
8967 reload uses it, that means the register is set before
8969 if (i2 == current_insn)
8971 for (j = n_reloads - 1; j >= 0; j--)
8972 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8973 || reload_override_in[j] == dst)
8975 for (j = n_reloads - 1; j >= 0; j--)
8976 if (rld[j].in && rld[j].reg_rtx == dst)
8985 /* If DST is still live at CURRENT_INSN, check if it is used for
8986 any reload. Note that even if CURRENT_INSN sets DST, we still
8987 have to check the reloads. */
8988 if (i2 == current_insn)
8990 for (j = n_reloads - 1; j >= 0; j--)
8991 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8992 || reload_override_in[j] == dst)
8994 /* ??? We can't finish the loop here, because dst might be
8995 allocated to a pseudo in this block if no reload in this
8996 block needs any of the classes containing DST - see
8997 spill_hard_reg. There is no easy way to tell this, so we
8998 have to scan till the end of the basic block. */
9000 if (reg_set_p (dst, PATTERN (i2)))
9004 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9005 reg_reloaded_contents[REGNO (dst)] = -1;
9009 /* Output reload-insns to reload VALUE into RELOADREG.
9010 VALUE is an autoincrement or autodecrement RTX whose operand
9011 is a register or memory location;
9012 so reloading involves incrementing that location.
9013 IN is either identical to VALUE, or some cheaper place to reload from.
9015 INC_AMOUNT is the number to increment or decrement by (always positive).
9016 This cannot be deduced from VALUE. */
9019 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9021 /* REG or MEM to be copied and incremented. */
9022 rtx incloc = find_replacement (&XEXP (value, 0));
9023 /* Nonzero if increment after copying. */
9024 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9025 || GET_CODE (value) == POST_MODIFY);
9030 rtx real_in = in == value ? incloc : in;
9032 /* No hard register is equivalent to this register after
9033 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9034 we could inc/dec that register as well (maybe even using it for
9035 the source), but I'm not sure it's worth worrying about. */
9037 reg_last_reload_reg[REGNO (incloc)] = 0;
9039 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9041 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9042 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9046 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9047 inc_amount = -inc_amount;
9049 inc = GEN_INT (inc_amount);
9052 /* If this is post-increment, first copy the location to the reload reg. */
9053 if (post && real_in != reloadreg)
9054 emit_insn (gen_move_insn (reloadreg, real_in));
9058 /* See if we can directly increment INCLOC. Use a method similar to
9059 that in gen_reload. */
9061 last = get_last_insn ();
9062 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9063 gen_rtx_PLUS (GET_MODE (incloc),
9066 code = recog_memoized (add_insn);
9069 extract_insn (add_insn);
9070 if (constrain_operands (1))
9072 /* If this is a pre-increment and we have incremented the value
9073 where it lives, copy the incremented value to RELOADREG to
9074 be used as an address. */
9077 emit_insn (gen_move_insn (reloadreg, incloc));
9081 delete_insns_since (last);
9084 /* If couldn't do the increment directly, must increment in RELOADREG.
9085 The way we do this depends on whether this is pre- or post-increment.
9086 For pre-increment, copy INCLOC to the reload register, increment it
9087 there, then save back. */
9091 if (in != reloadreg)
9092 emit_insn (gen_move_insn (reloadreg, real_in));
9093 emit_insn (gen_add2_insn (reloadreg, inc));
9094 emit_insn (gen_move_insn (incloc, reloadreg));
9099 Because this might be a jump insn or a compare, and because RELOADREG
9100 may not be available after the insn in an input reload, we must do
9101 the incrementation before the insn being reloaded for.
9103 We have already copied IN to RELOADREG. Increment the copy in
9104 RELOADREG, save that back, then decrement RELOADREG so it has
9105 the original value. */
9107 emit_insn (gen_add2_insn (reloadreg, inc));
9108 emit_insn (gen_move_insn (incloc, reloadreg));
9109 if (CONST_INT_P (inc))
9110 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9112 emit_insn (gen_sub2_insn (reloadreg, inc));
9118 add_auto_inc_notes (rtx insn, rtx x)
9120 enum rtx_code code = GET_CODE (x);
9124 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9126 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9130 /* Scan all the operand sub-expressions. */
9131 fmt = GET_RTX_FORMAT (code);
9132 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9135 add_auto_inc_notes (insn, XEXP (x, i));
9136 else if (fmt[i] == 'E')
9137 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9138 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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