1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
45 /* This file contains the reload pass of the compiler, which is
46 run after register allocation has been done. It checks that
47 each insn is valid (operands required to be in registers really
48 are in registers of the proper class) and fixes up invalid ones
49 by copying values temporarily into registers for the insns
52 The results of register allocation are described by the vector
53 reg_renumber; the insns still contain pseudo regs, but reg_renumber
54 can be used to find which hard reg, if any, a pseudo reg is in.
56 The technique we always use is to free up a few hard regs that are
57 called ``reload regs'', and for each place where a pseudo reg
58 must be in a hard reg, copy it temporarily into one of the reload regs.
60 Reload regs are allocated locally for every instruction that needs
61 reloads. When there are pseudos which are allocated to a register that
62 has been chosen as a reload reg, such pseudos must be ``spilled''.
63 This means that they go to other hard regs, or to stack slots if no other
64 available hard regs can be found. Spilling can invalidate more
65 insns, requiring additional need for reloads, so we must keep checking
66 until the process stabilizes.
68 For machines with different classes of registers, we must keep track
69 of the register class needed for each reload, and make sure that
70 we allocate enough reload registers of each class.
72 The file reload.c contains the code that checks one insn for
73 validity and reports the reloads that it needs. This file
74 is in charge of scanning the entire rtl code, accumulating the
75 reload needs, spilling, assigning reload registers to use for
76 fixing up each insn, and generating the new insns to copy values
77 into the reload registers. */
79 #ifndef REGISTER_MOVE_COST
80 #define REGISTER_MOVE_COST(m, x, y) 2
84 #define LOCAL_REGNO(REGNO) 0
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static unsigned int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Nonzero if indirect addressing is supported on the machine; this means
219 that spilling (REG n) does not require reloading it into a register in
220 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
221 value indicates the level of indirect addressing supported, e.g., two
222 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
224 static char spill_indirect_levels;
226 /* Nonzero if indirect addressing is supported when the innermost MEM is
227 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
228 which these are valid is the same as spill_indirect_levels, above. */
229 char indirect_symref_ok;
231 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
232 char double_reg_address_ok;
234 /* Record the stack slot for each spilled hard register. */
235 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
237 /* Width allocated so far for that stack slot. */
238 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Record which pseudos needed to be spilled. */
241 static regset_head spilled_pseudos;
243 /* Used for communication between order_regs_for_reload and count_pseudo.
244 Used to avoid counting one pseudo twice. */
245 static regset_head pseudos_counted;
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
253 int caller_save_needed;
255 /* Set to 1 while reload_as_needed is operating.
256 Required by some machines to handle any generated moves differently. */
257 int reload_in_progress = 0;
259 /* These arrays record the insn_code of insns that may be needed to
260 perform input and output reloads of special objects. They provide a
261 place to pass a scratch register. */
262 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
263 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
265 /* This obstack is used for allocation of rtl during register elimination.
266 The allocated storage can be freed once find_reloads has processed the
268 struct obstack reload_obstack;
270 /* Points to the beginning of the reload_obstack. All insn_chain structures
271 are allocated first. */
272 char *reload_startobj;
274 /* The point after all insn_chain structures. Used to quickly deallocate
275 memory allocated in copy_reloads during calculate_needs_all_insns. */
276 char *reload_firstobj;
278 /* This points before all local rtl generated by register elimination.
279 Used to quickly free all memory after processing one insn. */
280 static char *reload_insn_firstobj;
282 #define obstack_chunk_alloc xmalloc
283 #define obstack_chunk_free free
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Non-zero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If non-zero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 static void replace_pseudos_in_call_usage PARAMS ((rtx *,
372 static void maybe_fix_stack_asms PARAMS ((void));
373 static void copy_reloads PARAMS ((struct insn_chain *));
374 static void calculate_needs_all_insns PARAMS ((int));
375 static int find_reg PARAMS ((struct insn_chain *, int));
376 static void find_reload_regs PARAMS ((struct insn_chain *));
377 static void select_reload_regs PARAMS ((void));
378 static void delete_caller_save_insns PARAMS ((void));
380 static void spill_failure PARAMS ((rtx, enum reg_class));
381 static void count_spilled_pseudo PARAMS ((int, int, int));
382 static void delete_dead_insn PARAMS ((rtx));
383 static void alter_reg PARAMS ((int, int));
384 static void set_label_offsets PARAMS ((rtx, rtx, int));
385 static void check_eliminable_occurrences PARAMS ((rtx));
386 static void elimination_effects PARAMS ((rtx, enum machine_mode));
387 static int eliminate_regs_in_insn PARAMS ((rtx, int));
388 static void update_eliminable_offsets PARAMS ((void));
389 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
390 static void set_initial_elim_offsets PARAMS ((void));
391 static void verify_initial_elim_offsets PARAMS ((void));
392 static void set_initial_label_offsets PARAMS ((void));
393 static void set_offsets_for_label PARAMS ((rtx));
394 static void init_elim_table PARAMS ((void));
395 static void update_eliminables PARAMS ((HARD_REG_SET *));
396 static void spill_hard_reg PARAMS ((unsigned int, int));
397 static int finish_spills PARAMS ((int));
398 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
399 static void scan_paradoxical_subregs PARAMS ((rtx));
400 static void count_pseudo PARAMS ((int));
401 static void order_regs_for_reload PARAMS ((struct insn_chain *));
402 static void reload_as_needed PARAMS ((int));
403 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
404 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
405 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
411 static int reload_reg_free_p PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
415 rtx, rtx, int, int));
416 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
417 enum reload_type, rtx, rtx,
419 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
421 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
423 static int conflicts_with_override PARAMS ((rtx));
424 static void failed_reload PARAMS ((rtx, int));
425 static int set_reload_reg PARAMS ((int, int));
426 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
427 static void choose_reload_regs PARAMS ((struct insn_chain *));
428 static void merge_assigned_reloads PARAMS ((rtx));
429 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
430 struct reload *, rtx, int));
431 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void do_input_reload PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_output_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void emit_reload_insns PARAMS ((struct insn_chain *));
438 static void delete_output_reload PARAMS ((rtx, int, int));
439 static void delete_address_reloads PARAMS ((rtx, rtx));
440 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
441 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
442 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
443 static void reload_cse_regs_1 PARAMS ((rtx));
444 static int reload_cse_noop_set_p PARAMS ((rtx));
445 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
446 static int reload_cse_simplify_operands PARAMS ((rtx));
447 static void reload_combine PARAMS ((void));
448 static void reload_combine_note_use PARAMS ((rtx *, rtx));
449 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
450 static void reload_cse_move2add PARAMS ((rtx));
451 static void move2add_note_store PARAMS ((rtx, rtx, void *));
453 static void add_auto_inc_notes PARAMS ((rtx, rtx));
455 static void copy_eh_notes PARAMS ((rtx, rtx));
456 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
458 static void failed_reload PARAMS ((rtx, int));
459 static int set_reload_reg PARAMS ((int, int));
460 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
461 static void reload_cse_simplify PARAMS ((rtx));
462 void fixup_abnormal_edges PARAMS ((void));
463 extern void dump_needs PARAMS ((struct insn_chain *));
465 /* Initialize the reload pass once per compilation. */
472 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
473 Set spill_indirect_levels to the number of levels such addressing is
474 permitted, zero if it is not permitted at all. */
477 = gen_rtx_MEM (Pmode,
480 LAST_VIRTUAL_REGISTER + 1),
482 spill_indirect_levels = 0;
484 while (memory_address_p (QImode, tem))
486 spill_indirect_levels++;
487 tem = gen_rtx_MEM (Pmode, tem);
490 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
492 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
493 indirect_symref_ok = memory_address_p (QImode, tem);
495 /* See if reg+reg is a valid (and offsettable) address. */
497 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
499 tem = gen_rtx_PLUS (Pmode,
500 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
501 gen_rtx_REG (Pmode, i));
503 /* This way, we make sure that reg+reg is an offsettable address. */
504 tem = plus_constant (tem, 4);
506 if (memory_address_p (QImode, tem))
508 double_reg_address_ok = 1;
513 /* Initialize obstack for our rtl allocation. */
514 gcc_obstack_init (&reload_obstack);
515 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
517 INIT_REG_SET (&spilled_pseudos);
518 INIT_REG_SET (&pseudos_counted);
521 /* List of insn chains that are currently unused. */
522 static struct insn_chain *unused_insn_chains = 0;
524 /* Allocate an empty insn_chain structure. */
528 struct insn_chain *c;
530 if (unused_insn_chains == 0)
532 c = (struct insn_chain *)
533 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
534 INIT_REG_SET (&c->live_throughout);
535 INIT_REG_SET (&c->dead_or_set);
539 c = unused_insn_chains;
540 unused_insn_chains = c->next;
542 c->is_caller_save_insn = 0;
543 c->need_operand_change = 0;
549 /* Small utility function to set all regs in hard reg set TO which are
550 allocated to pseudos in regset FROM. */
553 compute_use_by_pseudos (to, from)
559 EXECUTE_IF_SET_IN_REG_SET
560 (from, FIRST_PSEUDO_REGISTER, regno,
562 int r = reg_renumber[regno];
567 /* reload_combine uses the information from
568 BASIC_BLOCK->global_live_at_start, which might still
569 contain registers that have not actually been allocated
570 since they have an equivalence. */
571 if (! reload_completed)
576 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
578 SET_HARD_REG_BIT (*to, r + nregs);
583 /* Replace all pseudos found in LOC with their corresponding
587 replace_pseudos_in_call_usage (loc, mem_mode, usage)
589 enum machine_mode mem_mode;
603 unsigned int regno = REGNO (x);
605 if (regno < FIRST_PSEUDO_REGISTER)
608 x = eliminate_regs (x, mem_mode, usage);
612 replace_pseudos_in_call_usage (loc, mem_mode, usage);
616 if (reg_equiv_constant[regno])
617 *loc = reg_equiv_constant[regno];
618 else if (reg_equiv_mem[regno])
619 *loc = reg_equiv_mem[regno];
620 else if (reg_equiv_address[regno])
621 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
622 else if (GET_CODE (regno_reg_rtx[regno]) != REG
623 || REGNO (regno_reg_rtx[regno]) != regno)
624 *loc = regno_reg_rtx[regno];
630 else if (code == MEM)
632 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
636 /* Process each of our operands recursively. */
637 fmt = GET_RTX_FORMAT (code);
638 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
640 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
641 else if (*fmt == 'E')
642 for (j = 0; j < XVECLEN (x, i); j++)
643 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
647 /* Global variables used by reload and its subroutines. */
649 /* Set during calculate_needs if an insn needs register elimination. */
650 static int something_needs_elimination;
651 /* Set during calculate_needs if an insn needs an operand changed. */
652 int something_needs_operands_changed;
654 /* Nonzero means we couldn't get enough spill regs. */
657 /* Main entry point for the reload pass.
659 FIRST is the first insn of the function being compiled.
661 GLOBAL nonzero means we were called from global_alloc
662 and should attempt to reallocate any pseudoregs that we
663 displace from hard regs we will use for reloads.
664 If GLOBAL is zero, we do not have enough information to do that,
665 so any pseudo reg that is spilled must go to the stack.
667 Return value is nonzero if reload failed
668 and we must not do any more for this function. */
671 reload (first, global)
677 struct elim_table *ep;
679 /* The two pointers used to track the true location of the memory used
680 for label offsets. */
681 char *real_known_ptr = NULL;
682 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
684 /* Make sure even insns with volatile mem refs are recognizable. */
689 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
691 /* Make sure that the last insn in the chain
692 is not something that needs reloading. */
693 emit_note (NULL, NOTE_INSN_DELETED);
695 /* Enable find_equiv_reg to distinguish insns made by reload. */
696 reload_first_uid = get_max_uid ();
698 #ifdef SECONDARY_MEMORY_NEEDED
699 /* Initialize the secondary memory table. */
700 clear_secondary_mem ();
703 /* We don't have a stack slot for any spill reg yet. */
704 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
705 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
707 /* Initialize the save area information for caller-save, in case some
711 /* Compute which hard registers are now in use
712 as homes for pseudo registers.
713 This is done here rather than (eg) in global_alloc
714 because this point is reached even if not optimizing. */
715 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
718 /* A function that receives a nonlocal goto must save all call-saved
720 if (current_function_has_nonlocal_label)
721 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
722 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
723 regs_ever_live[i] = 1;
725 /* Find all the pseudo registers that didn't get hard regs
726 but do have known equivalent constants or memory slots.
727 These include parameters (known equivalent to parameter slots)
728 and cse'd or loop-moved constant memory addresses.
730 Record constant equivalents in reg_equiv_constant
731 so they will be substituted by find_reloads.
732 Record memory equivalents in reg_mem_equiv so they can
733 be substituted eventually by altering the REG-rtx's. */
735 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
740 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
741 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
742 pseudo_forbidden_regs
743 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
745 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
747 CLEAR_HARD_REG_SET (bad_spill_regs_global);
749 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
750 Also find all paradoxical subregs and find largest such for each pseudo.
751 On machines with small register classes, record hard registers that
752 are used for user variables. These can never be used for spills.
753 Also look for a "constant" REG_SETJMP. This means that all
754 caller-saved registers must be marked live. */
756 num_eliminable_invariants = 0;
757 for (insn = first; insn; insn = NEXT_INSN (insn))
759 rtx set = single_set (insn);
761 /* We may introduce USEs that we want to remove at the end, so
762 we'll mark them with QImode. Make sure there are no
763 previously-marked insns left by say regmove. */
764 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
765 && GET_MODE (insn) != VOIDmode)
766 PUT_MODE (insn, VOIDmode);
768 if (GET_CODE (insn) == CALL_INSN
769 && find_reg_note (insn, REG_SETJMP, NULL))
770 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
771 if (! call_used_regs[i])
772 regs_ever_live[i] = 1;
774 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
776 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
778 #ifdef LEGITIMATE_PIC_OPERAND_P
779 && (! function_invariant_p (XEXP (note, 0))
781 /* A function invariant is often CONSTANT_P but may
782 include a register. We promise to only pass
783 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
784 || (CONSTANT_P (XEXP (note, 0))
785 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
789 rtx x = XEXP (note, 0);
790 i = REGNO (SET_DEST (set));
791 if (i > LAST_VIRTUAL_REGISTER)
793 /* It can happen that a REG_EQUIV note contains a MEM
794 that is not a legitimate memory operand. As later
795 stages of reload assume that all addresses found
796 in the reg_equiv_* arrays were originally legitimate,
797 we ignore such REG_EQUIV notes. */
798 if (memory_operand (x, VOIDmode))
800 /* Always unshare the equivalence, so we can
801 substitute into this insn without touching the
803 reg_equiv_memory_loc[i] = copy_rtx (x);
805 else if (function_invariant_p (x))
807 if (GET_CODE (x) == PLUS)
809 /* This is PLUS of frame pointer and a constant,
810 and might be shared. Unshare it. */
811 reg_equiv_constant[i] = copy_rtx (x);
812 num_eliminable_invariants++;
814 else if (x == frame_pointer_rtx
815 || x == arg_pointer_rtx)
817 reg_equiv_constant[i] = x;
818 num_eliminable_invariants++;
820 else if (LEGITIMATE_CONSTANT_P (x))
821 reg_equiv_constant[i] = x;
823 reg_equiv_memory_loc[i]
824 = force_const_mem (GET_MODE (SET_DEST (set)), x);
829 /* If this register is being made equivalent to a MEM
830 and the MEM is not SET_SRC, the equivalencing insn
831 is one with the MEM as a SET_DEST and it occurs later.
832 So don't mark this insn now. */
833 if (GET_CODE (x) != MEM
834 || rtx_equal_p (SET_SRC (set), x))
836 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
841 /* If this insn is setting a MEM from a register equivalent to it,
842 this is the equivalencing insn. */
843 else if (set && GET_CODE (SET_DEST (set)) == MEM
844 && GET_CODE (SET_SRC (set)) == REG
845 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
846 && rtx_equal_p (SET_DEST (set),
847 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
848 reg_equiv_init[REGNO (SET_SRC (set))]
849 = gen_rtx_INSN_LIST (VOIDmode, insn,
850 reg_equiv_init[REGNO (SET_SRC (set))]);
853 scan_paradoxical_subregs (PATTERN (insn));
858 num_labels = max_label_num () - get_first_label_num ();
860 /* Allocate the tables used to store offset information at labels. */
861 /* We used to use alloca here, but the size of what it would try to
862 allocate would occasionally cause it to exceed the stack limit and
863 cause a core dump. */
864 real_known_ptr = xmalloc (num_labels);
866 = (int (*)[NUM_ELIMINABLE_REGS])
867 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
869 offsets_known_at = real_known_ptr - get_first_label_num ();
871 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
873 /* Alter each pseudo-reg rtx to contain its hard reg number.
874 Assign stack slots to the pseudos that lack hard regs or equivalents.
875 Do not touch virtual registers. */
877 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
880 /* If we have some registers we think can be eliminated, scan all insns to
881 see if there is an insn that sets one of these registers to something
882 other than itself plus a constant. If so, the register cannot be
883 eliminated. Doing this scan here eliminates an extra pass through the
884 main reload loop in the most common case where register elimination
886 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
887 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
888 || GET_CODE (insn) == CALL_INSN)
889 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
891 maybe_fix_stack_asms ();
893 insns_need_reload = 0;
894 something_needs_elimination = 0;
896 /* Initialize to -1, which means take the first spill register. */
899 /* Spill any hard regs that we know we can't eliminate. */
900 CLEAR_HARD_REG_SET (used_spill_regs);
901 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
902 if (! ep->can_eliminate)
903 spill_hard_reg (ep->from, 1);
905 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
906 if (frame_pointer_needed)
907 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
909 finish_spills (global);
911 /* From now on, we may need to generate moves differently. We may also
912 allow modifications of insns which cause them to not be recognized.
913 Any such modifications will be cleaned up during reload itself. */
914 reload_in_progress = 1;
916 /* This loop scans the entire function each go-round
917 and repeats until one repetition spills no additional hard regs. */
920 int something_changed;
923 HOST_WIDE_INT starting_frame_size;
925 /* Round size of stack frame to stack_alignment_needed. This must be done
926 here because the stack size may be a part of the offset computation
927 for register elimination, and there might have been new stack slots
928 created in the last iteration of this loop. */
929 if (cfun->stack_alignment_needed)
930 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
932 starting_frame_size = get_frame_size ();
934 set_initial_elim_offsets ();
935 set_initial_label_offsets ();
937 /* For each pseudo register that has an equivalent location defined,
938 try to eliminate any eliminable registers (such as the frame pointer)
939 assuming initial offsets for the replacement register, which
942 If the resulting location is directly addressable, substitute
943 the MEM we just got directly for the old REG.
945 If it is not addressable but is a constant or the sum of a hard reg
946 and constant, it is probably not addressable because the constant is
947 out of range, in that case record the address; we will generate
948 hairy code to compute the address in a register each time it is
949 needed. Similarly if it is a hard register, but one that is not
950 valid as an address register.
952 If the location is not addressable, but does not have one of the
953 above forms, assign a stack slot. We have to do this to avoid the
954 potential of producing lots of reloads if, e.g., a location involves
955 a pseudo that didn't get a hard register and has an equivalent memory
956 location that also involves a pseudo that didn't get a hard register.
958 Perhaps at some point we will improve reload_when_needed handling
959 so this problem goes away. But that's very hairy. */
961 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
962 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
964 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
966 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
968 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
969 else if (CONSTANT_P (XEXP (x, 0))
970 || (GET_CODE (XEXP (x, 0)) == REG
971 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
972 || (GET_CODE (XEXP (x, 0)) == PLUS
973 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
974 && (REGNO (XEXP (XEXP (x, 0), 0))
975 < FIRST_PSEUDO_REGISTER)
976 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
977 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
980 /* Make a new stack slot. Then indicate that something
981 changed so we go back and recompute offsets for
982 eliminable registers because the allocation of memory
983 below might change some offset. reg_equiv_{mem,address}
984 will be set up for this pseudo on the next pass around
986 reg_equiv_memory_loc[i] = 0;
987 reg_equiv_init[i] = 0;
992 if (caller_save_needed)
995 /* If we allocated another stack slot, redo elimination bookkeeping. */
996 if (starting_frame_size != get_frame_size ())
999 if (caller_save_needed)
1001 save_call_clobbered_regs ();
1002 /* That might have allocated new insn_chain structures. */
1003 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1006 calculate_needs_all_insns (global);
1008 CLEAR_REG_SET (&spilled_pseudos);
1011 something_changed = 0;
1013 /* If we allocated any new memory locations, make another pass
1014 since it might have changed elimination offsets. */
1015 if (starting_frame_size != get_frame_size ())
1016 something_changed = 1;
1019 HARD_REG_SET to_spill;
1020 CLEAR_HARD_REG_SET (to_spill);
1021 update_eliminables (&to_spill);
1022 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1023 if (TEST_HARD_REG_BIT (to_spill, i))
1025 spill_hard_reg (i, 1);
1028 /* Regardless of the state of spills, if we previously had
1029 a register that we thought we could eliminate, but no can
1030 not eliminate, we must run another pass.
1032 Consider pseudos which have an entry in reg_equiv_* which
1033 reference an eliminable register. We must make another pass
1034 to update reg_equiv_* so that we do not substitute in the
1035 old value from when we thought the elimination could be
1037 something_changed = 1;
1041 select_reload_regs ();
1045 if (insns_need_reload != 0 || did_spill)
1046 something_changed |= finish_spills (global);
1048 if (! something_changed)
1051 if (caller_save_needed)
1052 delete_caller_save_insns ();
1054 obstack_free (&reload_obstack, reload_firstobj);
1057 /* If global-alloc was run, notify it of any register eliminations we have
1060 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1061 if (ep->can_eliminate)
1062 mark_elimination (ep->from, ep->to);
1064 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1065 If that insn didn't set the register (i.e., it copied the register to
1066 memory), just delete that insn instead of the equivalencing insn plus
1067 anything now dead. If we call delete_dead_insn on that insn, we may
1068 delete the insn that actually sets the register if the register dies
1069 there and that is incorrect. */
1071 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1073 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1076 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1078 rtx equiv_insn = XEXP (list, 0);
1080 /* If we already deleted the insn or if it may trap, we can't
1081 delete it. The latter case shouldn't happen, but can
1082 if an insn has a variable address, gets a REG_EH_REGION
1083 note added to it, and then gets converted into an load
1084 from a constant address. */
1085 if (GET_CODE (equiv_insn) == NOTE
1086 || can_throw_internal (equiv_insn))
1088 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1089 delete_dead_insn (equiv_insn);
1092 PUT_CODE (equiv_insn, NOTE);
1093 NOTE_SOURCE_FILE (equiv_insn) = 0;
1094 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1100 /* Use the reload registers where necessary
1101 by generating move instructions to move the must-be-register
1102 values into or out of the reload registers. */
1104 if (insns_need_reload != 0 || something_needs_elimination
1105 || something_needs_operands_changed)
1107 HOST_WIDE_INT old_frame_size = get_frame_size ();
1109 reload_as_needed (global);
1111 if (old_frame_size != get_frame_size ())
1115 verify_initial_elim_offsets ();
1118 /* If we were able to eliminate the frame pointer, show that it is no
1119 longer live at the start of any basic block. If it ls live by
1120 virtue of being in a pseudo, that pseudo will be marked live
1121 and hence the frame pointer will be known to be live via that
1124 if (! frame_pointer_needed)
1125 for (i = 0; i < n_basic_blocks; i++)
1126 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1127 HARD_FRAME_POINTER_REGNUM);
1129 /* Come here (with failure set nonzero) if we can't get enough spill regs
1130 and we decide not to abort about it. */
1133 CLEAR_REG_SET (&spilled_pseudos);
1134 reload_in_progress = 0;
1136 /* Now eliminate all pseudo regs by modifying them into
1137 their equivalent memory references.
1138 The REG-rtx's for the pseudos are modified in place,
1139 so all insns that used to refer to them now refer to memory.
1141 For a reg that has a reg_equiv_address, all those insns
1142 were changed by reloading so that no insns refer to it any longer;
1143 but the DECL_RTL of a variable decl may refer to it,
1144 and if so this causes the debugging info to mention the variable. */
1146 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1150 if (reg_equiv_mem[i])
1151 addr = XEXP (reg_equiv_mem[i], 0);
1153 if (reg_equiv_address[i])
1154 addr = reg_equiv_address[i];
1158 if (reg_renumber[i] < 0)
1160 rtx reg = regno_reg_rtx[i];
1162 PUT_CODE (reg, MEM);
1163 XEXP (reg, 0) = addr;
1164 REG_USERVAR_P (reg) = 0;
1165 if (reg_equiv_memory_loc[i])
1166 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1169 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1170 = MEM_SCALAR_P (reg) = 0;
1171 MEM_ATTRS (reg) = 0;
1174 else if (reg_equiv_mem[i])
1175 XEXP (reg_equiv_mem[i], 0) = addr;
1179 /* We must set reload_completed now since the cleanup_subreg_operands call
1180 below will re-recognize each insn and reload may have generated insns
1181 which are only valid during and after reload. */
1182 reload_completed = 1;
1184 /* Make a pass over all the insns and delete all USEs which we inserted
1185 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1186 notes. Delete all CLOBBER insns that don't refer to the return value
1187 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1188 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1189 and regenerate REG_INC notes that may have been moved around. */
1191 for (insn = first; insn; insn = NEXT_INSN (insn))
1196 if (GET_CODE (insn) == CALL_INSN)
1197 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1199 CALL_INSN_FUNCTION_USAGE (insn));
1201 if ((GET_CODE (PATTERN (insn)) == USE
1202 /* We mark with QImode USEs introduced by reload itself. */
1203 && (GET_MODE (insn) == QImode
1204 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1205 || (GET_CODE (PATTERN (insn)) == CLOBBER
1206 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1207 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1213 pnote = ®_NOTES (insn);
1216 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1217 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1218 || REG_NOTE_KIND (*pnote) == REG_INC
1219 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1220 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1221 *pnote = XEXP (*pnote, 1);
1223 pnote = &XEXP (*pnote, 1);
1227 add_auto_inc_notes (insn, PATTERN (insn));
1230 /* And simplify (subreg (reg)) if it appears as an operand. */
1231 cleanup_subreg_operands (insn);
1234 /* If we are doing stack checking, give a warning if this function's
1235 frame size is larger than we expect. */
1236 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1238 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1239 static int verbose_warned = 0;
1241 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1242 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1243 size += UNITS_PER_WORD;
1245 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1247 warning ("frame size too large for reliable stack checking");
1248 if (! verbose_warned)
1250 warning ("try reducing the number of local variables");
1256 /* Indicate that we no longer have known memory locations or constants. */
1257 if (reg_equiv_constant)
1258 free (reg_equiv_constant);
1259 reg_equiv_constant = 0;
1260 if (reg_equiv_memory_loc)
1261 free (reg_equiv_memory_loc);
1262 reg_equiv_memory_loc = 0;
1265 free (real_known_ptr);
1269 free (reg_equiv_mem);
1270 free (reg_equiv_init);
1271 free (reg_equiv_address);
1272 free (reg_max_ref_width);
1273 free (reg_old_renumber);
1274 free (pseudo_previous_regs);
1275 free (pseudo_forbidden_regs);
1277 CLEAR_HARD_REG_SET (used_spill_regs);
1278 for (i = 0; i < n_spills; i++)
1279 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1281 /* Free all the insn_chain structures at once. */
1282 obstack_free (&reload_obstack, reload_startobj);
1283 unused_insn_chains = 0;
1284 fixup_abnormal_edges ();
1286 /* Replacing pseudos with their memory equivalents might have
1287 created shared rtx. Subsequent passes would get confused
1288 by this, so unshare everything here. */
1289 unshare_all_rtl_again (first);
1294 /* Yet another special case. Unfortunately, reg-stack forces people to
1295 write incorrect clobbers in asm statements. These clobbers must not
1296 cause the register to appear in bad_spill_regs, otherwise we'll call
1297 fatal_insn later. We clear the corresponding regnos in the live
1298 register sets to avoid this.
1299 The whole thing is rather sick, I'm afraid. */
1302 maybe_fix_stack_asms ()
1305 const char *constraints[MAX_RECOG_OPERANDS];
1306 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1307 struct insn_chain *chain;
1309 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1312 HARD_REG_SET clobbered, allowed;
1315 if (! INSN_P (chain->insn)
1316 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1318 pat = PATTERN (chain->insn);
1319 if (GET_CODE (pat) != PARALLEL)
1322 CLEAR_HARD_REG_SET (clobbered);
1323 CLEAR_HARD_REG_SET (allowed);
1325 /* First, make a mask of all stack regs that are clobbered. */
1326 for (i = 0; i < XVECLEN (pat, 0); i++)
1328 rtx t = XVECEXP (pat, 0, i);
1329 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1330 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1333 /* Get the operand values and constraints out of the insn. */
1334 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1335 constraints, operand_mode);
1337 /* For every operand, see what registers are allowed. */
1338 for (i = 0; i < noperands; i++)
1340 const char *p = constraints[i];
1341 /* For every alternative, we compute the class of registers allowed
1342 for reloading in CLS, and merge its contents into the reg set
1344 int cls = (int) NO_REGS;
1350 if (c == '\0' || c == ',' || c == '#')
1352 /* End of one alternative - mark the regs in the current
1353 class, and reset the class. */
1354 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1359 } while (c != '\0' && c != ',');
1367 case '=': case '+': case '*': case '%': case '?': case '!':
1368 case '0': case '1': case '2': case '3': case '4': case 'm':
1369 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1370 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1371 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1376 cls = (int) reg_class_subunion[cls]
1377 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1382 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1386 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1391 /* Those of the registers which are clobbered, but allowed by the
1392 constraints, must be usable as reload registers. So clear them
1393 out of the life information. */
1394 AND_HARD_REG_SET (allowed, clobbered);
1395 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1396 if (TEST_HARD_REG_BIT (allowed, i))
1398 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1399 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1406 /* Copy the global variables n_reloads and rld into the corresponding elts
1409 copy_reloads (chain)
1410 struct insn_chain *chain;
1412 chain->n_reloads = n_reloads;
1414 = (struct reload *) obstack_alloc (&reload_obstack,
1415 n_reloads * sizeof (struct reload));
1416 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1417 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1420 /* Walk the chain of insns, and determine for each whether it needs reloads
1421 and/or eliminations. Build the corresponding insns_need_reload list, and
1422 set something_needs_elimination as appropriate. */
1424 calculate_needs_all_insns (global)
1427 struct insn_chain **pprev_reload = &insns_need_reload;
1428 struct insn_chain *chain, *next = 0;
1430 something_needs_elimination = 0;
1432 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1433 for (chain = reload_insn_chain; chain != 0; chain = next)
1435 rtx insn = chain->insn;
1439 /* Clear out the shortcuts. */
1440 chain->n_reloads = 0;
1441 chain->need_elim = 0;
1442 chain->need_reload = 0;
1443 chain->need_operand_change = 0;
1445 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1446 include REG_LABEL), we need to see what effects this has on the
1447 known offsets at labels. */
1449 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1450 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1451 set_label_offsets (insn, insn, 0);
1455 rtx old_body = PATTERN (insn);
1456 int old_code = INSN_CODE (insn);
1457 rtx old_notes = REG_NOTES (insn);
1458 int did_elimination = 0;
1459 int operands_changed = 0;
1460 rtx set = single_set (insn);
1462 /* Skip insns that only set an equivalence. */
1463 if (set && GET_CODE (SET_DEST (set)) == REG
1464 && reg_renumber[REGNO (SET_DEST (set))] < 0
1465 && reg_equiv_constant[REGNO (SET_DEST (set))])
1468 /* If needed, eliminate any eliminable registers. */
1469 if (num_eliminable || num_eliminable_invariants)
1470 did_elimination = eliminate_regs_in_insn (insn, 0);
1472 /* Analyze the instruction. */
1473 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1474 global, spill_reg_order);
1476 /* If a no-op set needs more than one reload, this is likely
1477 to be something that needs input address reloads. We
1478 can't get rid of this cleanly later, and it is of no use
1479 anyway, so discard it now.
1480 We only do this when expensive_optimizations is enabled,
1481 since this complements reload inheritance / output
1482 reload deletion, and it can make debugging harder. */
1483 if (flag_expensive_optimizations && n_reloads > 1)
1485 rtx set = single_set (insn);
1487 && SET_SRC (set) == SET_DEST (set)
1488 && GET_CODE (SET_SRC (set)) == REG
1489 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1492 /* Delete it from the reload chain */
1494 chain->prev->next = next;
1496 reload_insn_chain = next;
1498 next->prev = chain->prev;
1499 chain->next = unused_insn_chains;
1500 unused_insn_chains = chain;
1505 update_eliminable_offsets ();
1507 /* Remember for later shortcuts which insns had any reloads or
1508 register eliminations. */
1509 chain->need_elim = did_elimination;
1510 chain->need_reload = n_reloads > 0;
1511 chain->need_operand_change = operands_changed;
1513 /* Discard any register replacements done. */
1514 if (did_elimination)
1516 obstack_free (&reload_obstack, reload_insn_firstobj);
1517 PATTERN (insn) = old_body;
1518 INSN_CODE (insn) = old_code;
1519 REG_NOTES (insn) = old_notes;
1520 something_needs_elimination = 1;
1523 something_needs_operands_changed |= operands_changed;
1527 copy_reloads (chain);
1528 *pprev_reload = chain;
1529 pprev_reload = &chain->next_need_reload;
1536 /* Comparison function for qsort to decide which of two reloads
1537 should be handled first. *P1 and *P2 are the reload numbers. */
1540 reload_reg_class_lower (r1p, r2p)
1544 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1547 /* Consider required reloads before optional ones. */
1548 t = rld[r1].optional - rld[r2].optional;
1552 /* Count all solitary classes before non-solitary ones. */
1553 t = ((reg_class_size[(int) rld[r2].class] == 1)
1554 - (reg_class_size[(int) rld[r1].class] == 1));
1558 /* Aside from solitaires, consider all multi-reg groups first. */
1559 t = rld[r2].nregs - rld[r1].nregs;
1563 /* Consider reloads in order of increasing reg-class number. */
1564 t = (int) rld[r1].class - (int) rld[r2].class;
1568 /* If reloads are equally urgent, sort by reload number,
1569 so that the results of qsort leave nothing to chance. */
1573 /* The cost of spilling each hard reg. */
1574 static int spill_cost[FIRST_PSEUDO_REGISTER];
1576 /* When spilling multiple hard registers, we use SPILL_COST for the first
1577 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1578 only the first hard reg for a multi-reg pseudo. */
1579 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1581 /* Update the spill cost arrays, considering that pseudo REG is live. */
1587 int freq = REG_FREQ (reg);
1588 int r = reg_renumber[reg];
1591 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1592 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1595 SET_REGNO_REG_SET (&pseudos_counted, reg);
1600 spill_add_cost[r] += freq;
1602 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1604 spill_cost[r + nregs] += freq;
1607 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1608 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1611 order_regs_for_reload (chain)
1612 struct insn_chain *chain;
1615 HARD_REG_SET used_by_pseudos;
1616 HARD_REG_SET used_by_pseudos2;
1618 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1620 memset (spill_cost, 0, sizeof spill_cost);
1621 memset (spill_add_cost, 0, sizeof spill_add_cost);
1623 /* Count number of uses of each hard reg by pseudo regs allocated to it
1624 and then order them by decreasing use. First exclude hard registers
1625 that are live in or across this insn. */
1627 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1628 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1629 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1630 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1632 /* Now find out which pseudos are allocated to it, and update
1634 CLEAR_REG_SET (&pseudos_counted);
1636 EXECUTE_IF_SET_IN_REG_SET
1637 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1641 EXECUTE_IF_SET_IN_REG_SET
1642 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1646 CLEAR_REG_SET (&pseudos_counted);
1649 /* Vector of reload-numbers showing the order in which the reloads should
1651 static short reload_order[MAX_RELOADS];
1653 /* This is used to keep track of the spill regs used in one insn. */
1654 static HARD_REG_SET used_spill_regs_local;
1656 /* We decided to spill hard register SPILLED, which has a size of
1657 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1658 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1659 update SPILL_COST/SPILL_ADD_COST. */
1662 count_spilled_pseudo (spilled, spilled_nregs, reg)
1663 int spilled, spilled_nregs, reg;
1665 int r = reg_renumber[reg];
1666 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1668 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1669 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1672 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1674 spill_add_cost[r] -= REG_FREQ (reg);
1676 spill_cost[r + nregs] -= REG_FREQ (reg);
1679 /* Find reload register to use for reload number ORDER. */
1682 find_reg (chain, order)
1683 struct insn_chain *chain;
1686 int rnum = reload_order[order];
1687 struct reload *rl = rld + rnum;
1688 int best_cost = INT_MAX;
1692 HARD_REG_SET not_usable;
1693 HARD_REG_SET used_by_other_reload;
1695 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1696 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1697 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1699 CLEAR_HARD_REG_SET (used_by_other_reload);
1700 for (k = 0; k < order; k++)
1702 int other = reload_order[k];
1704 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1705 for (j = 0; j < rld[other].nregs; j++)
1706 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1709 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1711 unsigned int regno = i;
1713 if (! TEST_HARD_REG_BIT (not_usable, regno)
1714 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1715 && HARD_REGNO_MODE_OK (regno, rl->mode))
1717 int this_cost = spill_cost[regno];
1719 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1721 for (j = 1; j < this_nregs; j++)
1723 this_cost += spill_add_cost[regno + j];
1724 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1725 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1730 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1732 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1734 if (this_cost < best_cost
1735 /* Among registers with equal cost, prefer caller-saved ones, or
1736 use REG_ALLOC_ORDER if it is defined. */
1737 || (this_cost == best_cost
1738 #ifdef REG_ALLOC_ORDER
1739 && (inv_reg_alloc_order[regno]
1740 < inv_reg_alloc_order[best_reg])
1742 && call_used_regs[regno]
1743 && ! call_used_regs[best_reg]
1748 best_cost = this_cost;
1756 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1758 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1759 rl->regno = best_reg;
1761 EXECUTE_IF_SET_IN_REG_SET
1762 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1764 count_spilled_pseudo (best_reg, rl->nregs, j);
1767 EXECUTE_IF_SET_IN_REG_SET
1768 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1770 count_spilled_pseudo (best_reg, rl->nregs, j);
1773 for (i = 0; i < rl->nregs; i++)
1775 if (spill_cost[best_reg + i] != 0
1776 || spill_add_cost[best_reg + i] != 0)
1778 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1783 /* Find more reload regs to satisfy the remaining need of an insn, which
1785 Do it by ascending class number, since otherwise a reg
1786 might be spilled for a big class and might fail to count
1787 for a smaller class even though it belongs to that class. */
1790 find_reload_regs (chain)
1791 struct insn_chain *chain;
1795 /* In order to be certain of getting the registers we need,
1796 we must sort the reloads into order of increasing register class.
1797 Then our grabbing of reload registers will parallel the process
1798 that provided the reload registers. */
1799 for (i = 0; i < chain->n_reloads; i++)
1801 /* Show whether this reload already has a hard reg. */
1802 if (chain->rld[i].reg_rtx)
1804 int regno = REGNO (chain->rld[i].reg_rtx);
1805 chain->rld[i].regno = regno;
1807 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1810 chain->rld[i].regno = -1;
1811 reload_order[i] = i;
1814 n_reloads = chain->n_reloads;
1815 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1817 CLEAR_HARD_REG_SET (used_spill_regs_local);
1820 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1822 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1824 /* Compute the order of preference for hard registers to spill. */
1826 order_regs_for_reload (chain);
1828 for (i = 0; i < n_reloads; i++)
1830 int r = reload_order[i];
1832 /* Ignore reloads that got marked inoperative. */
1833 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1834 && ! rld[r].optional
1835 && rld[r].regno == -1)
1836 if (! find_reg (chain, i))
1838 spill_failure (chain->insn, rld[r].class);
1844 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1845 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1847 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1851 select_reload_regs ()
1853 struct insn_chain *chain;
1855 /* Try to satisfy the needs for each insn. */
1856 for (chain = insns_need_reload; chain != 0;
1857 chain = chain->next_need_reload)
1858 find_reload_regs (chain);
1861 /* Delete all insns that were inserted by emit_caller_save_insns during
1864 delete_caller_save_insns ()
1866 struct insn_chain *c = reload_insn_chain;
1870 while (c != 0 && c->is_caller_save_insn)
1872 struct insn_chain *next = c->next;
1875 if (c == reload_insn_chain)
1876 reload_insn_chain = next;
1880 next->prev = c->prev;
1882 c->prev->next = next;
1883 c->next = unused_insn_chains;
1884 unused_insn_chains = c;
1892 /* Handle the failure to find a register to spill.
1893 INSN should be one of the insns which needed this particular spill reg. */
1896 spill_failure (insn, class)
1898 enum reg_class class;
1900 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1901 if (asm_noperands (PATTERN (insn)) >= 0)
1902 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1903 reg_class_names[class]);
1906 error ("unable to find a register to spill in class `%s'",
1907 reg_class_names[class]);
1908 fatal_insn ("this is the insn:", insn);
1912 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1913 data that is dead in INSN. */
1916 delete_dead_insn (insn)
1919 rtx prev = prev_real_insn (insn);
1922 /* If the previous insn sets a register that dies in our insn, delete it
1924 if (prev && GET_CODE (PATTERN (prev)) == SET
1925 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1926 && reg_mentioned_p (prev_dest, PATTERN (insn))
1927 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1928 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1929 delete_dead_insn (prev);
1931 PUT_CODE (insn, NOTE);
1932 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1933 NOTE_SOURCE_FILE (insn) = 0;
1936 /* Modify the home of pseudo-reg I.
1937 The new home is present in reg_renumber[I].
1939 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1940 or it may be -1, meaning there is none or it is not relevant.
1941 This is used so that all pseudos spilled from a given hard reg
1942 can share one stack slot. */
1945 alter_reg (i, from_reg)
1949 /* When outputting an inline function, this can happen
1950 for a reg that isn't actually used. */
1951 if (regno_reg_rtx[i] == 0)
1954 /* If the reg got changed to a MEM at rtl-generation time,
1956 if (GET_CODE (regno_reg_rtx[i]) != REG)
1959 /* Modify the reg-rtx to contain the new hard reg
1960 number or else to contain its pseudo reg number. */
1961 REGNO (regno_reg_rtx[i])
1962 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1964 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1965 allocate a stack slot for it. */
1967 if (reg_renumber[i] < 0
1968 && REG_N_REFS (i) > 0
1969 && reg_equiv_constant[i] == 0
1970 && reg_equiv_memory_loc[i] == 0)
1973 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1974 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1977 /* Each pseudo reg has an inherent size which comes from its own mode,
1978 and a total size which provides room for paradoxical subregs
1979 which refer to the pseudo reg in wider modes.
1981 We can use a slot already allocated if it provides both
1982 enough inherent space and enough total space.
1983 Otherwise, we allocate a new slot, making sure that it has no less
1984 inherent space, and no less total space, then the previous slot. */
1987 /* No known place to spill from => no slot to reuse. */
1988 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1989 inherent_size == total_size ? 0 : -1);
1990 if (BYTES_BIG_ENDIAN)
1991 /* Cancel the big-endian correction done in assign_stack_local.
1992 Get the address of the beginning of the slot.
1993 This is so we can do a big-endian correction unconditionally
1995 adjust = inherent_size - total_size;
1997 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1999 /* Nothing can alias this slot except this pseudo. */
2000 set_mem_alias_set (x, new_alias_set ());
2003 /* Reuse a stack slot if possible. */
2004 else if (spill_stack_slot[from_reg] != 0
2005 && spill_stack_slot_width[from_reg] >= total_size
2006 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2008 x = spill_stack_slot[from_reg];
2010 /* Allocate a bigger slot. */
2013 /* Compute maximum size needed, both for inherent size
2014 and for total size. */
2015 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2018 if (spill_stack_slot[from_reg])
2020 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2022 mode = GET_MODE (spill_stack_slot[from_reg]);
2023 if (spill_stack_slot_width[from_reg] > total_size)
2024 total_size = spill_stack_slot_width[from_reg];
2027 /* Make a slot with that size. */
2028 x = assign_stack_local (mode, total_size,
2029 inherent_size == total_size ? 0 : -1);
2032 /* All pseudos mapped to this slot can alias each other. */
2033 if (spill_stack_slot[from_reg])
2034 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2036 set_mem_alias_set (x, new_alias_set ());
2038 if (BYTES_BIG_ENDIAN)
2040 /* Cancel the big-endian correction done in assign_stack_local.
2041 Get the address of the beginning of the slot.
2042 This is so we can do a big-endian correction unconditionally
2044 adjust = GET_MODE_SIZE (mode) - total_size;
2047 = adjust_address_nv (x, mode_for_size (total_size
2053 spill_stack_slot[from_reg] = stack_slot;
2054 spill_stack_slot_width[from_reg] = total_size;
2057 /* On a big endian machine, the "address" of the slot
2058 is the address of the low part that fits its inherent mode. */
2059 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2060 adjust += (total_size - inherent_size);
2062 /* If we have any adjustment to make, or if the stack slot is the
2063 wrong mode, make a new stack slot. */
2064 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2066 /* If we have a decl for the original register, set it for the
2067 memory. If this is a shared MEM, make a copy. */
2070 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2073 set_mem_expr (x, REGNO_DECL (i));
2076 /* Save the stack slot for later. */
2077 reg_equiv_memory_loc[i] = x;
2081 /* Mark the slots in regs_ever_live for the hard regs
2082 used by pseudo-reg number REGNO. */
2085 mark_home_live (regno)
2090 i = reg_renumber[regno];
2093 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2095 regs_ever_live[i++] = 1;
2098 /* This function handles the tracking of elimination offsets around branches.
2100 X is a piece of RTL being scanned.
2102 INSN is the insn that it came from, if any.
2104 INITIAL_P is non-zero if we are to set the offset to be the initial
2105 offset and zero if we are setting the offset of the label to be the
2109 set_label_offsets (x, insn, initial_p)
2114 enum rtx_code code = GET_CODE (x);
2117 struct elim_table *p;
2122 if (LABEL_REF_NONLOCAL_P (x))
2127 /* ... fall through ... */
2130 /* If we know nothing about this label, set the desired offsets. Note
2131 that this sets the offset at a label to be the offset before a label
2132 if we don't know anything about the label. This is not correct for
2133 the label after a BARRIER, but is the best guess we can make. If
2134 we guessed wrong, we will suppress an elimination that might have
2135 been possible had we been able to guess correctly. */
2137 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2139 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2140 offsets_at[CODE_LABEL_NUMBER (x)][i]
2141 = (initial_p ? reg_eliminate[i].initial_offset
2142 : reg_eliminate[i].offset);
2143 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2146 /* Otherwise, if this is the definition of a label and it is
2147 preceded by a BARRIER, set our offsets to the known offset of
2151 && (tem = prev_nonnote_insn (insn)) != 0
2152 && GET_CODE (tem) == BARRIER)
2153 set_offsets_for_label (insn);
2155 /* If neither of the above cases is true, compare each offset
2156 with those previously recorded and suppress any eliminations
2157 where the offsets disagree. */
2159 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2160 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2161 != (initial_p ? reg_eliminate[i].initial_offset
2162 : reg_eliminate[i].offset))
2163 reg_eliminate[i].can_eliminate = 0;
2168 set_label_offsets (PATTERN (insn), insn, initial_p);
2170 /* ... fall through ... */
2174 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2175 and hence must have all eliminations at their initial offsets. */
2176 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2177 if (REG_NOTE_KIND (tem) == REG_LABEL)
2178 set_label_offsets (XEXP (tem, 0), insn, 1);
2184 /* Each of the labels in the parallel or address vector must be
2185 at their initial offsets. We want the first field for PARALLEL
2186 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2188 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2189 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2194 /* We only care about setting PC. If the source is not RETURN,
2195 IF_THEN_ELSE, or a label, disable any eliminations not at
2196 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2197 isn't one of those possibilities. For branches to a label,
2198 call ourselves recursively.
2200 Note that this can disable elimination unnecessarily when we have
2201 a non-local goto since it will look like a non-constant jump to
2202 someplace in the current function. This isn't a significant
2203 problem since such jumps will normally be when all elimination
2204 pairs are back to their initial offsets. */
2206 if (SET_DEST (x) != pc_rtx)
2209 switch (GET_CODE (SET_SRC (x)))
2216 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2220 tem = XEXP (SET_SRC (x), 1);
2221 if (GET_CODE (tem) == LABEL_REF)
2222 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2223 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2226 tem = XEXP (SET_SRC (x), 2);
2227 if (GET_CODE (tem) == LABEL_REF)
2228 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2229 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2237 /* If we reach here, all eliminations must be at their initial
2238 offset because we are doing a jump to a variable address. */
2239 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2240 if (p->offset != p->initial_offset)
2241 p->can_eliminate = 0;
2249 /* Scan X and replace any eliminable registers (such as fp) with a
2250 replacement (such as sp), plus an offset.
2252 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2253 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2254 MEM, we are allowed to replace a sum of a register and the constant zero
2255 with the register, which we cannot do outside a MEM. In addition, we need
2256 to record the fact that a register is referenced outside a MEM.
2258 If INSN is an insn, it is the insn containing X. If we replace a REG
2259 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2260 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2261 the REG is being modified.
2263 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2264 That's used when we eliminate in expressions stored in notes.
2265 This means, do not set ref_outside_mem even if the reference
2268 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2269 replacements done assuming all offsets are at their initial values. If
2270 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2271 encounter, return the actual location so that find_reloads will do
2272 the proper thing. */
2275 eliminate_regs (x, mem_mode, insn)
2277 enum machine_mode mem_mode;
2280 enum rtx_code code = GET_CODE (x);
2281 struct elim_table *ep;
2288 if (! current_function_decl)
2308 /* This is only for the benefit of the debugging backends, which call
2309 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2310 removed after CSE. */
2311 new = eliminate_regs (XEXP (x, 0), 0, insn);
2312 if (GET_CODE (new) == MEM)
2313 return XEXP (new, 0);
2319 /* First handle the case where we encounter a bare register that
2320 is eliminable. Replace it with a PLUS. */
2321 if (regno < FIRST_PSEUDO_REGISTER)
2323 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2325 if (ep->from_rtx == x && ep->can_eliminate)
2326 return plus_constant (ep->to_rtx, ep->previous_offset);
2329 else if (reg_renumber && reg_renumber[regno] < 0
2330 && reg_equiv_constant && reg_equiv_constant[regno]
2331 && ! CONSTANT_P (reg_equiv_constant[regno]))
2332 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2336 /* You might think handling MINUS in a manner similar to PLUS is a
2337 good idea. It is not. It has been tried multiple times and every
2338 time the change has had to have been reverted.
2340 Other parts of reload know a PLUS is special (gen_reload for example)
2341 and require special code to handle code a reloaded PLUS operand.
2343 Also consider backends where the flags register is clobbered by a
2344 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2345 lea instruction comes to mind). If we try to reload a MINUS, we
2346 may kill the flags register that was holding a useful value.
2348 So, please before trying to handle MINUS, consider reload as a
2349 whole instead of this little section as well as the backend issues. */
2351 /* If this is the sum of an eliminable register and a constant, rework
2353 if (GET_CODE (XEXP (x, 0)) == REG
2354 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2355 && CONSTANT_P (XEXP (x, 1)))
2357 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2359 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2361 /* The only time we want to replace a PLUS with a REG (this
2362 occurs when the constant operand of the PLUS is the negative
2363 of the offset) is when we are inside a MEM. We won't want
2364 to do so at other times because that would change the
2365 structure of the insn in a way that reload can't handle.
2366 We special-case the commonest situation in
2367 eliminate_regs_in_insn, so just replace a PLUS with a
2368 PLUS here, unless inside a MEM. */
2369 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2370 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2373 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2374 plus_constant (XEXP (x, 1),
2375 ep->previous_offset));
2378 /* If the register is not eliminable, we are done since the other
2379 operand is a constant. */
2383 /* If this is part of an address, we want to bring any constant to the
2384 outermost PLUS. We will do this by doing register replacement in
2385 our operands and seeing if a constant shows up in one of them.
2387 Note that there is no risk of modifying the structure of the insn,
2388 since we only get called for its operands, thus we are either
2389 modifying the address inside a MEM, or something like an address
2390 operand of a load-address insn. */
2393 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2394 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2396 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2398 /* If one side is a PLUS and the other side is a pseudo that
2399 didn't get a hard register but has a reg_equiv_constant,
2400 we must replace the constant here since it may no longer
2401 be in the position of any operand. */
2402 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2403 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2404 && reg_renumber[REGNO (new1)] < 0
2405 && reg_equiv_constant != 0
2406 && reg_equiv_constant[REGNO (new1)] != 0)
2407 new1 = reg_equiv_constant[REGNO (new1)];
2408 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2409 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2410 && reg_renumber[REGNO (new0)] < 0
2411 && reg_equiv_constant[REGNO (new0)] != 0)
2412 new0 = reg_equiv_constant[REGNO (new0)];
2414 new = form_sum (new0, new1);
2416 /* As above, if we are not inside a MEM we do not want to
2417 turn a PLUS into something else. We might try to do so here
2418 for an addition of 0 if we aren't optimizing. */
2419 if (! mem_mode && GET_CODE (new) != PLUS)
2420 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2428 /* If this is the product of an eliminable register and a
2429 constant, apply the distribute law and move the constant out
2430 so that we have (plus (mult ..) ..). This is needed in order
2431 to keep load-address insns valid. This case is pathological.
2432 We ignore the possibility of overflow here. */
2433 if (GET_CODE (XEXP (x, 0)) == REG
2434 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2435 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2436 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2438 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2441 /* Refs inside notes don't count for this purpose. */
2442 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2443 || GET_CODE (insn) == INSN_LIST)))
2444 ep->ref_outside_mem = 1;
2447 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2448 ep->previous_offset * INTVAL (XEXP (x, 1)));
2451 /* ... fall through ... */
2455 /* See comments before PLUS about handling MINUS. */
2457 case DIV: case UDIV:
2458 case MOD: case UMOD:
2459 case AND: case IOR: case XOR:
2460 case ROTATERT: case ROTATE:
2461 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2463 case GE: case GT: case GEU: case GTU:
2464 case LE: case LT: case LEU: case LTU:
2466 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2468 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2470 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2471 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2476 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2479 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2480 if (new != XEXP (x, 0))
2482 /* If this is a REG_DEAD note, it is not valid anymore.
2483 Using the eliminated version could result in creating a
2484 REG_DEAD note for the stack or frame pointer. */
2485 if (GET_MODE (x) == REG_DEAD)
2487 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2490 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2494 /* ... fall through ... */
2497 /* Now do eliminations in the rest of the chain. If this was
2498 an EXPR_LIST, this might result in allocating more memory than is
2499 strictly needed, but it simplifies the code. */
2502 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2503 if (new != XEXP (x, 1))
2505 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2513 case STRICT_LOW_PART:
2515 case SIGN_EXTEND: case ZERO_EXTEND:
2516 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2517 case FLOAT: case FIX:
2518 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2522 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2523 if (new != XEXP (x, 0))
2524 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2528 /* Similar to above processing, but preserve SUBREG_BYTE.
2529 Convert (subreg (mem)) to (mem) if not paradoxical.
2530 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2531 pseudo didn't get a hard reg, we must replace this with the
2532 eliminated version of the memory location because push_reloads
2533 may do the replacement in certain circumstances. */
2534 if (GET_CODE (SUBREG_REG (x)) == REG
2535 && (GET_MODE_SIZE (GET_MODE (x))
2536 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2537 && reg_equiv_memory_loc != 0
2538 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2540 new = SUBREG_REG (x);
2543 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2545 if (new != SUBREG_REG (x))
2547 int x_size = GET_MODE_SIZE (GET_MODE (x));
2548 int new_size = GET_MODE_SIZE (GET_MODE (new));
2550 if (GET_CODE (new) == MEM
2551 && ((x_size < new_size
2552 #ifdef WORD_REGISTER_OPERATIONS
2553 /* On these machines, combine can create rtl of the form
2554 (set (subreg:m1 (reg:m2 R) 0) ...)
2555 where m1 < m2, and expects something interesting to
2556 happen to the entire word. Moreover, it will use the
2557 (reg:m2 R) later, expecting all bits to be preserved.
2558 So if the number of words is the same, preserve the
2559 subreg so that push_reloads can see it. */
2560 && ! ((x_size - 1) / UNITS_PER_WORD
2561 == (new_size -1 ) / UNITS_PER_WORD)
2564 || x_size == new_size)
2566 return adjust_address_nv (x, GET_MODE (x), SUBREG_BYTE (x));
2568 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2574 /* This is only for the benefit of the debugging backends, which call
2575 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2576 removed after CSE. */
2577 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2578 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2580 /* Our only special processing is to pass the mode of the MEM to our
2581 recursive call and copy the flags. While we are here, handle this
2582 case more efficiently. */
2584 replace_equiv_address_nv (x,
2585 eliminate_regs (XEXP (x, 0),
2586 GET_MODE (x), insn));
2589 /* Handle insn_list USE that a call to a pure function may generate. */
2590 new = eliminate_regs (XEXP (x, 0), 0, insn);
2591 if (new != XEXP (x, 0))
2592 return gen_rtx_USE (GET_MODE (x), new);
2604 /* Process each of our operands recursively. If any have changed, make a
2606 fmt = GET_RTX_FORMAT (code);
2607 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2611 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2612 if (new != XEXP (x, i) && ! copied)
2614 rtx new_x = rtx_alloc (code);
2616 (sizeof (*new_x) - sizeof (new_x->fld)
2617 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2623 else if (*fmt == 'E')
2626 for (j = 0; j < XVECLEN (x, i); j++)
2628 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2629 if (new != XVECEXP (x, i, j) && ! copied_vec)
2631 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2635 rtx new_x = rtx_alloc (code);
2637 (sizeof (*new_x) - sizeof (new_x->fld)
2638 + (sizeof (new_x->fld[0])
2639 * GET_RTX_LENGTH (code))));
2643 XVEC (x, i) = new_v;
2646 XVECEXP (x, i, j) = new;
2654 /* Scan rtx X for modifications of elimination target registers. Update
2655 the table of eliminables to reflect the changed state. MEM_MODE is
2656 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2659 elimination_effects (x, mem_mode)
2661 enum machine_mode mem_mode;
2664 enum rtx_code code = GET_CODE (x);
2665 struct elim_table *ep;
2692 /* First handle the case where we encounter a bare register that
2693 is eliminable. Replace it with a PLUS. */
2694 if (regno < FIRST_PSEUDO_REGISTER)
2696 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2698 if (ep->from_rtx == x && ep->can_eliminate)
2701 ep->ref_outside_mem = 1;
2706 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2707 && reg_equiv_constant[regno]
2708 && ! function_invariant_p (reg_equiv_constant[regno]))
2709 elimination_effects (reg_equiv_constant[regno], mem_mode);
2718 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2719 if (ep->to_rtx == XEXP (x, 0))
2721 int size = GET_MODE_SIZE (mem_mode);
2723 /* If more bytes than MEM_MODE are pushed, account for them. */
2724 #ifdef PUSH_ROUNDING
2725 if (ep->to_rtx == stack_pointer_rtx)
2726 size = PUSH_ROUNDING (size);
2728 if (code == PRE_DEC || code == POST_DEC)
2730 else if (code == PRE_INC || code == POST_INC)
2732 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2733 && GET_CODE (XEXP (x, 1)) == PLUS
2734 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2735 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2736 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2739 /* These two aren't unary operators. */
2740 if (code == POST_MODIFY || code == PRE_MODIFY)
2743 /* Fall through to generic unary operation case. */
2744 case STRICT_LOW_PART:
2746 case SIGN_EXTEND: case ZERO_EXTEND:
2747 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2748 case FLOAT: case FIX:
2749 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2753 elimination_effects (XEXP (x, 0), mem_mode);
2757 if (GET_CODE (SUBREG_REG (x)) == REG
2758 && (GET_MODE_SIZE (GET_MODE (x))
2759 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2760 && reg_equiv_memory_loc != 0
2761 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2764 elimination_effects (SUBREG_REG (x), mem_mode);
2768 /* If using a register that is the source of an eliminate we still
2769 think can be performed, note it cannot be performed since we don't
2770 know how this register is used. */
2771 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2772 if (ep->from_rtx == XEXP (x, 0))
2773 ep->can_eliminate = 0;
2775 elimination_effects (XEXP (x, 0), mem_mode);
2779 /* If clobbering a register that is the replacement register for an
2780 elimination we still think can be performed, note that it cannot
2781 be performed. Otherwise, we need not be concerned about it. */
2782 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2783 if (ep->to_rtx == XEXP (x, 0))
2784 ep->can_eliminate = 0;
2786 elimination_effects (XEXP (x, 0), mem_mode);
2790 /* Check for setting a register that we know about. */
2791 if (GET_CODE (SET_DEST (x)) == REG)
2793 /* See if this is setting the replacement register for an
2796 If DEST is the hard frame pointer, we do nothing because we
2797 assume that all assignments to the frame pointer are for
2798 non-local gotos and are being done at a time when they are valid
2799 and do not disturb anything else. Some machines want to
2800 eliminate a fake argument pointer (or even a fake frame pointer)
2801 with either the real frame or the stack pointer. Assignments to
2802 the hard frame pointer must not prevent this elimination. */
2804 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2806 if (ep->to_rtx == SET_DEST (x)
2807 && SET_DEST (x) != hard_frame_pointer_rtx)
2809 /* If it is being incremented, adjust the offset. Otherwise,
2810 this elimination can't be done. */
2811 rtx src = SET_SRC (x);
2813 if (GET_CODE (src) == PLUS
2814 && XEXP (src, 0) == SET_DEST (x)
2815 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2816 ep->offset -= INTVAL (XEXP (src, 1));
2818 ep->can_eliminate = 0;
2822 elimination_effects (SET_DEST (x), 0);
2823 elimination_effects (SET_SRC (x), 0);
2827 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2830 /* Our only special processing is to pass the mode of the MEM to our
2832 elimination_effects (XEXP (x, 0), GET_MODE (x));
2839 fmt = GET_RTX_FORMAT (code);
2840 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2843 elimination_effects (XEXP (x, i), mem_mode);
2844 else if (*fmt == 'E')
2845 for (j = 0; j < XVECLEN (x, i); j++)
2846 elimination_effects (XVECEXP (x, i, j), mem_mode);
2850 /* Descend through rtx X and verify that no references to eliminable registers
2851 remain. If any do remain, mark the involved register as not
2855 check_eliminable_occurrences (x)
2865 code = GET_CODE (x);
2867 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2869 struct elim_table *ep;
2871 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2872 if (ep->from_rtx == x && ep->can_eliminate)
2873 ep->can_eliminate = 0;
2877 fmt = GET_RTX_FORMAT (code);
2878 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2881 check_eliminable_occurrences (XEXP (x, i));
2882 else if (*fmt == 'E')
2885 for (j = 0; j < XVECLEN (x, i); j++)
2886 check_eliminable_occurrences (XVECEXP (x, i, j));
2891 /* Scan INSN and eliminate all eliminable registers in it.
2893 If REPLACE is nonzero, do the replacement destructively. Also
2894 delete the insn as dead it if it is setting an eliminable register.
2896 If REPLACE is zero, do all our allocations in reload_obstack.
2898 If no eliminations were done and this insn doesn't require any elimination
2899 processing (these are not identical conditions: it might be updating sp,
2900 but not referencing fp; this needs to be seen during reload_as_needed so
2901 that the offset between fp and sp can be taken into consideration), zero
2902 is returned. Otherwise, 1 is returned. */
2905 eliminate_regs_in_insn (insn, replace)
2909 int icode = recog_memoized (insn);
2910 rtx old_body = PATTERN (insn);
2911 int insn_is_asm = asm_noperands (old_body) >= 0;
2912 rtx old_set = single_set (insn);
2916 rtx substed_operand[MAX_RECOG_OPERANDS];
2917 rtx orig_operand[MAX_RECOG_OPERANDS];
2918 struct elim_table *ep;
2920 if (! insn_is_asm && icode < 0)
2922 if (GET_CODE (PATTERN (insn)) == USE
2923 || GET_CODE (PATTERN (insn)) == CLOBBER
2924 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2925 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2926 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2931 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2932 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2934 /* Check for setting an eliminable register. */
2935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2936 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2938 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2939 /* If this is setting the frame pointer register to the
2940 hardware frame pointer register and this is an elimination
2941 that will be done (tested above), this insn is really
2942 adjusting the frame pointer downward to compensate for
2943 the adjustment done before a nonlocal goto. */
2944 if (ep->from == FRAME_POINTER_REGNUM
2945 && ep->to == HARD_FRAME_POINTER_REGNUM)
2947 rtx base = SET_SRC (old_set);
2948 rtx base_insn = insn;
2951 while (base != ep->to_rtx)
2953 rtx prev_insn, prev_set;
2955 if (GET_CODE (base) == PLUS
2956 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2958 offset += INTVAL (XEXP (base, 1));
2959 base = XEXP (base, 0);
2961 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2962 && (prev_set = single_set (prev_insn)) != 0
2963 && rtx_equal_p (SET_DEST (prev_set), base))
2965 base = SET_SRC (prev_set);
2966 base_insn = prev_insn;
2972 if (base == ep->to_rtx)
2975 = plus_constant (ep->to_rtx, offset - ep->offset);
2977 new_body = old_body;
2980 new_body = copy_insn (old_body);
2981 if (REG_NOTES (insn))
2982 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2984 PATTERN (insn) = new_body;
2985 old_set = single_set (insn);
2987 /* First see if this insn remains valid when we
2988 make the change. If not, keep the INSN_CODE
2989 the same and let reload fit it up. */
2990 validate_change (insn, &SET_SRC (old_set), src, 1);
2991 validate_change (insn, &SET_DEST (old_set),
2993 if (! apply_change_group ())
2995 SET_SRC (old_set) = src;
2996 SET_DEST (old_set) = ep->to_rtx;
3005 /* In this case this insn isn't serving a useful purpose. We
3006 will delete it in reload_as_needed once we know that this
3007 elimination is, in fact, being done.
3009 If REPLACE isn't set, we can't delete this insn, but needn't
3010 process it since it won't be used unless something changes. */
3013 delete_dead_insn (insn);
3021 /* We allow one special case which happens to work on all machines we
3022 currently support: a single set with the source being a PLUS of an
3023 eliminable register and a constant. */
3025 && GET_CODE (SET_DEST (old_set)) == REG
3026 && GET_CODE (SET_SRC (old_set)) == PLUS
3027 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3028 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3029 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3031 rtx reg = XEXP (SET_SRC (old_set), 0);
3032 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3034 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3035 if (ep->from_rtx == reg && ep->can_eliminate)
3037 offset += ep->offset;
3042 /* We assume here that if we need a PARALLEL with
3043 CLOBBERs for this assignment, we can do with the
3044 MATCH_SCRATCHes that add_clobbers allocates.
3045 There's not much we can do if that doesn't work. */
3046 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3050 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3053 rtvec vec = rtvec_alloc (num_clobbers + 1);
3055 vec->elem[0] = PATTERN (insn);
3056 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3057 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3059 if (INSN_CODE (insn) < 0)
3064 new_body = old_body;
3067 new_body = copy_insn (old_body);
3068 if (REG_NOTES (insn))
3069 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3071 PATTERN (insn) = new_body;
3072 old_set = single_set (insn);
3074 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3075 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3078 /* This can't have an effect on elimination offsets, so skip right
3084 /* Determine the effects of this insn on elimination offsets. */
3085 elimination_effects (old_body, 0);
3087 /* Eliminate all eliminable registers occurring in operands that
3088 can be handled by reload. */
3089 extract_insn (insn);
3091 for (i = 0; i < recog_data.n_operands; i++)
3093 orig_operand[i] = recog_data.operand[i];
3094 substed_operand[i] = recog_data.operand[i];
3096 /* For an asm statement, every operand is eliminable. */
3097 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3099 /* Check for setting a register that we know about. */
3100 if (recog_data.operand_type[i] != OP_IN
3101 && GET_CODE (orig_operand[i]) == REG)
3103 /* If we are assigning to a register that can be eliminated, it
3104 must be as part of a PARALLEL, since the code above handles
3105 single SETs. We must indicate that we can no longer
3106 eliminate this reg. */
3107 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3109 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3110 ep->can_eliminate = 0;
3113 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3114 replace ? insn : NULL_RTX);
3115 if (substed_operand[i] != orig_operand[i])
3116 val = any_changes = 1;
3117 /* Terminate the search in check_eliminable_occurrences at
3119 *recog_data.operand_loc[i] = 0;
3121 /* If an output operand changed from a REG to a MEM and INSN is an
3122 insn, write a CLOBBER insn. */
3123 if (recog_data.operand_type[i] != OP_IN
3124 && GET_CODE (orig_operand[i]) == REG
3125 && GET_CODE (substed_operand[i]) == MEM
3127 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3132 for (i = 0; i < recog_data.n_dups; i++)
3133 *recog_data.dup_loc[i]
3134 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3136 /* If any eliminable remain, they aren't eliminable anymore. */
3137 check_eliminable_occurrences (old_body);
3139 /* Substitute the operands; the new values are in the substed_operand
3141 for (i = 0; i < recog_data.n_operands; i++)
3142 *recog_data.operand_loc[i] = substed_operand[i];
3143 for (i = 0; i < recog_data.n_dups; i++)
3144 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3146 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3147 re-recognize the insn. We do this in case we had a simple addition
3148 but now can do this as a load-address. This saves an insn in this
3150 If re-recognition fails, the old insn code number will still be used,
3151 and some register operands may have changed into PLUS expressions.
3152 These will be handled by find_reloads by loading them into a register
3157 /* If we aren't replacing things permanently and we changed something,
3158 make another copy to ensure that all the RTL is new. Otherwise
3159 things can go wrong if find_reload swaps commutative operands
3160 and one is inside RTL that has been copied while the other is not. */
3161 new_body = old_body;
3164 new_body = copy_insn (old_body);
3165 if (REG_NOTES (insn))
3166 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3168 PATTERN (insn) = new_body;
3170 /* If we had a move insn but now we don't, rerecognize it. This will
3171 cause spurious re-recognition if the old move had a PARALLEL since
3172 the new one still will, but we can't call single_set without
3173 having put NEW_BODY into the insn and the re-recognition won't
3174 hurt in this rare case. */
3175 /* ??? Why this huge if statement - why don't we just rerecognize the
3179 && ((GET_CODE (SET_SRC (old_set)) == REG
3180 && (GET_CODE (new_body) != SET
3181 || GET_CODE (SET_SRC (new_body)) != REG))
3182 /* If this was a load from or store to memory, compare
3183 the MEM in recog_data.operand to the one in the insn.
3184 If they are not equal, then rerecognize the insn. */
3186 && ((GET_CODE (SET_SRC (old_set)) == MEM
3187 && SET_SRC (old_set) != recog_data.operand[1])
3188 || (GET_CODE (SET_DEST (old_set)) == MEM
3189 && SET_DEST (old_set) != recog_data.operand[0])))
3190 /* If this was an add insn before, rerecognize. */
3191 || GET_CODE (SET_SRC (old_set)) == PLUS))
3193 int new_icode = recog (PATTERN (insn), insn, 0);
3195 INSN_CODE (insn) = icode;
3199 /* Restore the old body. If there were any changes to it, we made a copy
3200 of it while the changes were still in place, so we'll correctly return
3201 a modified insn below. */
3204 /* Restore the old body. */
3205 for (i = 0; i < recog_data.n_operands; i++)
3206 *recog_data.operand_loc[i] = orig_operand[i];
3207 for (i = 0; i < recog_data.n_dups; i++)
3208 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3211 /* Update all elimination pairs to reflect the status after the current
3212 insn. The changes we make were determined by the earlier call to
3213 elimination_effects.
3215 We also detect a cases where register elimination cannot be done,
3216 namely, if a register would be both changed and referenced outside a MEM
3217 in the resulting insn since such an insn is often undefined and, even if
3218 not, we cannot know what meaning will be given to it. Note that it is
3219 valid to have a register used in an address in an insn that changes it
3220 (presumably with a pre- or post-increment or decrement).
3222 If anything changes, return nonzero. */
3224 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3226 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3227 ep->can_eliminate = 0;
3229 ep->ref_outside_mem = 0;
3231 if (ep->previous_offset != ep->offset)
3236 /* If we changed something, perform elimination in REG_NOTES. This is
3237 needed even when REPLACE is zero because a REG_DEAD note might refer
3238 to a register that we eliminate and could cause a different number
3239 of spill registers to be needed in the final reload pass than in
3241 if (val && REG_NOTES (insn) != 0)
3242 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3247 /* Loop through all elimination pairs.
3248 Recalculate the number not at initial offset.
3250 Compute the maximum offset (minimum offset if the stack does not
3251 grow downward) for each elimination pair. */
3254 update_eliminable_offsets ()
3256 struct elim_table *ep;
3258 num_not_at_initial_offset = 0;
3259 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3261 ep->previous_offset = ep->offset;
3262 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3263 num_not_at_initial_offset++;
3267 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3268 replacement we currently believe is valid, mark it as not eliminable if X
3269 modifies DEST in any way other than by adding a constant integer to it.
3271 If DEST is the frame pointer, we do nothing because we assume that
3272 all assignments to the hard frame pointer are nonlocal gotos and are being
3273 done at a time when they are valid and do not disturb anything else.
3274 Some machines want to eliminate a fake argument pointer with either the
3275 frame or stack pointer. Assignments to the hard frame pointer must not
3276 prevent this elimination.
3278 Called via note_stores from reload before starting its passes to scan
3279 the insns of the function. */
3282 mark_not_eliminable (dest, x, data)
3285 void *data ATTRIBUTE_UNUSED;
3289 /* A SUBREG of a hard register here is just changing its mode. We should
3290 not see a SUBREG of an eliminable hard register, but check just in
3292 if (GET_CODE (dest) == SUBREG)
3293 dest = SUBREG_REG (dest);
3295 if (dest == hard_frame_pointer_rtx)
3298 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3299 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3300 && (GET_CODE (x) != SET
3301 || GET_CODE (SET_SRC (x)) != PLUS
3302 || XEXP (SET_SRC (x), 0) != dest
3303 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3305 reg_eliminate[i].can_eliminate_previous
3306 = reg_eliminate[i].can_eliminate = 0;
3311 /* Verify that the initial elimination offsets did not change since the
3312 last call to set_initial_elim_offsets. This is used to catch cases
3313 where something illegal happened during reload_as_needed that could
3314 cause incorrect code to be generated if we did not check for it. */
3317 verify_initial_elim_offsets ()
3321 #ifdef ELIMINABLE_REGS
3322 struct elim_table *ep;
3324 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3326 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3327 if (t != ep->initial_offset)
3331 INITIAL_FRAME_POINTER_OFFSET (t);
3332 if (t != reg_eliminate[0].initial_offset)
3337 /* Reset all offsets on eliminable registers to their initial values. */
3340 set_initial_elim_offsets ()
3342 struct elim_table *ep = reg_eliminate;
3344 #ifdef ELIMINABLE_REGS
3345 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3347 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3348 ep->previous_offset = ep->offset = ep->initial_offset;
3351 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3352 ep->previous_offset = ep->offset = ep->initial_offset;
3355 num_not_at_initial_offset = 0;
3358 /* Initialize the known label offsets.
3359 Set a known offset for each forced label to be at the initial offset
3360 of each elimination. We do this because we assume that all
3361 computed jumps occur from a location where each elimination is
3362 at its initial offset.
3363 For all other labels, show that we don't know the offsets. */
3366 set_initial_label_offsets ()
3369 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3371 for (x = forced_labels; x; x = XEXP (x, 1))
3373 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3376 /* Set all elimination offsets to the known values for the code label given
3380 set_offsets_for_label (insn)
3384 int label_nr = CODE_LABEL_NUMBER (insn);
3385 struct elim_table *ep;
3387 num_not_at_initial_offset = 0;
3388 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3390 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3391 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3392 num_not_at_initial_offset++;
3396 /* See if anything that happened changes which eliminations are valid.
3397 For example, on the Sparc, whether or not the frame pointer can
3398 be eliminated can depend on what registers have been used. We need
3399 not check some conditions again (such as flag_omit_frame_pointer)
3400 since they can't have changed. */
3403 update_eliminables (pset)
3406 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3407 int previous_frame_pointer_needed = frame_pointer_needed;
3409 struct elim_table *ep;
3411 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3412 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3413 #ifdef ELIMINABLE_REGS
3414 || ! CAN_ELIMINATE (ep->from, ep->to)
3417 ep->can_eliminate = 0;
3419 /* Look for the case where we have discovered that we can't replace
3420 register A with register B and that means that we will now be
3421 trying to replace register A with register C. This means we can
3422 no longer replace register C with register B and we need to disable
3423 such an elimination, if it exists. This occurs often with A == ap,
3424 B == sp, and C == fp. */
3426 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3428 struct elim_table *op;
3431 if (! ep->can_eliminate && ep->can_eliminate_previous)
3433 /* Find the current elimination for ep->from, if there is a
3435 for (op = reg_eliminate;
3436 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3437 if (op->from == ep->from && op->can_eliminate)
3443 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3445 for (op = reg_eliminate;
3446 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3447 if (op->from == new_to && op->to == ep->to)
3448 op->can_eliminate = 0;
3452 /* See if any registers that we thought we could eliminate the previous
3453 time are no longer eliminable. If so, something has changed and we
3454 must spill the register. Also, recompute the number of eliminable
3455 registers and see if the frame pointer is needed; it is if there is
3456 no elimination of the frame pointer that we can perform. */
3458 frame_pointer_needed = 1;
3459 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3461 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3462 && ep->to != HARD_FRAME_POINTER_REGNUM)
3463 frame_pointer_needed = 0;
3465 if (! ep->can_eliminate && ep->can_eliminate_previous)
3467 ep->can_eliminate_previous = 0;
3468 SET_HARD_REG_BIT (*pset, ep->from);
3473 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3474 /* If we didn't need a frame pointer last time, but we do now, spill
3475 the hard frame pointer. */
3476 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3477 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3481 /* Initialize the table of registers to eliminate. */
3486 struct elim_table *ep;
3487 #ifdef ELIMINABLE_REGS
3488 const struct elim_table_1 *ep1;
3492 reg_eliminate = (struct elim_table *)
3493 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3495 /* Does this function require a frame pointer? */
3497 frame_pointer_needed = (! flag_omit_frame_pointer
3498 #ifdef EXIT_IGNORE_STACK
3499 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3500 and restore sp for alloca. So we can't eliminate
3501 the frame pointer in that case. At some point,
3502 we should improve this by emitting the
3503 sp-adjusting insns for this case. */
3504 || (current_function_calls_alloca
3505 && EXIT_IGNORE_STACK)
3507 || FRAME_POINTER_REQUIRED);
3511 #ifdef ELIMINABLE_REGS
3512 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3513 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3515 ep->from = ep1->from;
3517 ep->can_eliminate = ep->can_eliminate_previous
3518 = (CAN_ELIMINATE (ep->from, ep->to)
3519 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3522 reg_eliminate[0].from = reg_eliminate_1[0].from;
3523 reg_eliminate[0].to = reg_eliminate_1[0].to;
3524 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3525 = ! frame_pointer_needed;
3528 /* Count the number of eliminable registers and build the FROM and TO
3529 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3530 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3531 We depend on this. */
3532 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3534 num_eliminable += ep->can_eliminate;
3535 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3536 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3540 /* Kick all pseudos out of hard register REGNO.
3542 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3543 because we found we can't eliminate some register. In the case, no pseudos
3544 are allowed to be in the register, even if they are only in a block that
3545 doesn't require spill registers, unlike the case when we are spilling this
3546 hard reg to produce another spill register.
3548 Return nonzero if any pseudos needed to be kicked out. */
3551 spill_hard_reg (regno, cant_eliminate)
3559 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3560 regs_ever_live[regno] = 1;
3563 /* Spill every pseudo reg that was allocated to this reg
3564 or to something that overlaps this reg. */
3566 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3567 if (reg_renumber[i] >= 0
3568 && (unsigned int) reg_renumber[i] <= regno
3569 && ((unsigned int) reg_renumber[i]
3570 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3571 PSEUDO_REGNO_MODE (i))
3573 SET_REGNO_REG_SET (&spilled_pseudos, i);
3576 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3577 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3580 ior_hard_reg_set (set1, set2)
3581 HARD_REG_SET *set1, *set2;
3583 IOR_HARD_REG_SET (*set1, *set2);
3586 /* After find_reload_regs has been run for all insn that need reloads,
3587 and/or spill_hard_regs was called, this function is used to actually
3588 spill pseudo registers and try to reallocate them. It also sets up the
3589 spill_regs array for use by choose_reload_regs. */
3592 finish_spills (global)
3595 struct insn_chain *chain;
3596 int something_changed = 0;
3599 /* Build the spill_regs array for the function. */
3600 /* If there are some registers still to eliminate and one of the spill regs
3601 wasn't ever used before, additional stack space may have to be
3602 allocated to store this register. Thus, we may have changed the offset
3603 between the stack and frame pointers, so mark that something has changed.
3605 One might think that we need only set VAL to 1 if this is a call-used
3606 register. However, the set of registers that must be saved by the
3607 prologue is not identical to the call-used set. For example, the
3608 register used by the call insn for the return PC is a call-used register,
3609 but must be saved by the prologue. */
3612 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3613 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3615 spill_reg_order[i] = n_spills;
3616 spill_regs[n_spills++] = i;
3617 if (num_eliminable && ! regs_ever_live[i])
3618 something_changed = 1;
3619 regs_ever_live[i] = 1;
3622 spill_reg_order[i] = -1;
3624 EXECUTE_IF_SET_IN_REG_SET
3625 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3627 /* Record the current hard register the pseudo is allocated to in
3628 pseudo_previous_regs so we avoid reallocating it to the same
3629 hard reg in a later pass. */
3630 if (reg_renumber[i] < 0)
3633 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3634 /* Mark it as no longer having a hard register home. */
3635 reg_renumber[i] = -1;
3636 /* We will need to scan everything again. */
3637 something_changed = 1;
3640 /* Retry global register allocation if possible. */
3643 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3644 /* For every insn that needs reloads, set the registers used as spill
3645 regs in pseudo_forbidden_regs for every pseudo live across the
3647 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3649 EXECUTE_IF_SET_IN_REG_SET
3650 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3652 ior_hard_reg_set (pseudo_forbidden_regs + i,
3653 &chain->used_spill_regs);
3655 EXECUTE_IF_SET_IN_REG_SET
3656 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3658 ior_hard_reg_set (pseudo_forbidden_regs + i,
3659 &chain->used_spill_regs);
3663 /* Retry allocating the spilled pseudos. For each reg, merge the
3664 various reg sets that indicate which hard regs can't be used,
3665 and call retry_global_alloc.
3666 We change spill_pseudos here to only contain pseudos that did not
3667 get a new hard register. */
3668 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3669 if (reg_old_renumber[i] != reg_renumber[i])
3671 HARD_REG_SET forbidden;
3672 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3673 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3674 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3675 retry_global_alloc (i, forbidden);
3676 if (reg_renumber[i] >= 0)
3677 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3681 /* Fix up the register information in the insn chain.
3682 This involves deleting those of the spilled pseudos which did not get
3683 a new hard register home from the live_{before,after} sets. */
3684 for (chain = reload_insn_chain; chain; chain = chain->next)
3686 HARD_REG_SET used_by_pseudos;
3687 HARD_REG_SET used_by_pseudos2;
3689 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3690 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3692 /* Mark any unallocated hard regs as available for spills. That
3693 makes inheritance work somewhat better. */
3694 if (chain->need_reload)
3696 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3697 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3698 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3700 /* Save the old value for the sanity test below. */
3701 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3703 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3704 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3705 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3706 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3708 /* Make sure we only enlarge the set. */
3709 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3715 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3716 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3718 int regno = reg_renumber[i];
3719 if (reg_old_renumber[i] == regno)
3722 alter_reg (i, reg_old_renumber[i]);
3723 reg_old_renumber[i] = regno;
3727 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3729 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3730 i, reg_renumber[i]);
3734 return something_changed;
3737 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3738 Also mark any hard registers used to store user variables as
3739 forbidden from being used for spill registers. */
3742 scan_paradoxical_subregs (x)
3747 enum rtx_code code = GET_CODE (x);
3753 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3754 && REG_USERVAR_P (x))
3755 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3764 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3772 if (GET_CODE (SUBREG_REG (x)) == REG
3773 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3774 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3775 = GET_MODE_SIZE (GET_MODE (x));
3782 fmt = GET_RTX_FORMAT (code);
3783 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3786 scan_paradoxical_subregs (XEXP (x, i));
3787 else if (fmt[i] == 'E')
3790 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3791 scan_paradoxical_subregs (XVECEXP (x, i, j));
3796 /* Reload pseudo-registers into hard regs around each insn as needed.
3797 Additional register load insns are output before the insn that needs it
3798 and perhaps store insns after insns that modify the reloaded pseudo reg.
3800 reg_last_reload_reg and reg_reloaded_contents keep track of
3801 which registers are already available in reload registers.
3802 We update these for the reloads that we perform,
3803 as the insns are scanned. */
3806 reload_as_needed (live_known)
3809 struct insn_chain *chain;
3810 #if defined (AUTO_INC_DEC)
3815 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3816 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3817 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3818 reg_has_output_reload = (char *) xmalloc (max_regno);
3819 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3821 set_initial_elim_offsets ();
3823 for (chain = reload_insn_chain; chain; chain = chain->next)
3826 rtx insn = chain->insn;
3827 rtx old_next = NEXT_INSN (insn);
3829 /* If we pass a label, copy the offsets from the label information
3830 into the current offsets of each elimination. */
3831 if (GET_CODE (insn) == CODE_LABEL)
3832 set_offsets_for_label (insn);
3834 else if (INSN_P (insn))
3836 rtx oldpat = PATTERN (insn);
3838 /* If this is a USE and CLOBBER of a MEM, ensure that any
3839 references to eliminable registers have been removed. */
3841 if ((GET_CODE (PATTERN (insn)) == USE
3842 || GET_CODE (PATTERN (insn)) == CLOBBER)
3843 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3844 XEXP (XEXP (PATTERN (insn), 0), 0)
3845 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3846 GET_MODE (XEXP (PATTERN (insn), 0)),
3849 /* If we need to do register elimination processing, do so.
3850 This might delete the insn, in which case we are done. */
3851 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3853 eliminate_regs_in_insn (insn, 1);
3854 if (GET_CODE (insn) == NOTE)
3856 update_eliminable_offsets ();
3861 /* If need_elim is nonzero but need_reload is zero, one might think
3862 that we could simply set n_reloads to 0. However, find_reloads
3863 could have done some manipulation of the insn (such as swapping
3864 commutative operands), and these manipulations are lost during
3865 the first pass for every insn that needs register elimination.
3866 So the actions of find_reloads must be redone here. */
3868 if (! chain->need_elim && ! chain->need_reload
3869 && ! chain->need_operand_change)
3871 /* First find the pseudo regs that must be reloaded for this insn.
3872 This info is returned in the tables reload_... (see reload.h).
3873 Also modify the body of INSN by substituting RELOAD
3874 rtx's for those pseudo regs. */
3877 memset (reg_has_output_reload, 0, max_regno);
3878 CLEAR_HARD_REG_SET (reg_is_output_reload);
3880 find_reloads (insn, 1, spill_indirect_levels, live_known,
3886 rtx next = NEXT_INSN (insn);
3889 prev = PREV_INSN (insn);
3891 /* Now compute which reload regs to reload them into. Perhaps
3892 reusing reload regs from previous insns, or else output
3893 load insns to reload them. Maybe output store insns too.
3894 Record the choices of reload reg in reload_reg_rtx. */
3895 choose_reload_regs (chain);
3897 /* Merge any reloads that we didn't combine for fear of
3898 increasing the number of spill registers needed but now
3899 discover can be safely merged. */
3900 if (SMALL_REGISTER_CLASSES)
3901 merge_assigned_reloads (insn);
3903 /* Generate the insns to reload operands into or out of
3904 their reload regs. */
3905 emit_reload_insns (chain);
3907 /* Substitute the chosen reload regs from reload_reg_rtx
3908 into the insn's body (or perhaps into the bodies of other
3909 load and store insn that we just made for reloading
3910 and that we moved the structure into). */
3911 subst_reloads (insn);
3913 /* If this was an ASM, make sure that all the reload insns
3914 we have generated are valid. If not, give an error
3917 if (asm_noperands (PATTERN (insn)) >= 0)
3918 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3919 if (p != insn && INSN_P (p)
3920 && (recog_memoized (p) < 0
3921 || (extract_insn (p), ! constrain_operands (1))))
3923 error_for_asm (insn,
3924 "`asm' operand requires impossible reload");
3929 if (num_eliminable && chain->need_elim)
3930 update_eliminable_offsets ();
3932 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3933 is no longer validly lying around to save a future reload.
3934 Note that this does not detect pseudos that were reloaded
3935 for this insn in order to be stored in
3936 (obeying register constraints). That is correct; such reload
3937 registers ARE still valid. */
3938 note_stores (oldpat, forget_old_reloads_1, NULL);
3940 /* There may have been CLOBBER insns placed after INSN. So scan
3941 between INSN and NEXT and use them to forget old reloads. */
3942 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3943 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3944 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3947 /* Likewise for regs altered by auto-increment in this insn.
3948 REG_INC notes have been changed by reloading:
3949 find_reloads_address_1 records substitutions for them,
3950 which have been performed by subst_reloads above. */
3951 for (i = n_reloads - 1; i >= 0; i--)
3953 rtx in_reg = rld[i].in_reg;
3956 enum rtx_code code = GET_CODE (in_reg);
3957 /* PRE_INC / PRE_DEC will have the reload register ending up
3958 with the same value as the stack slot, but that doesn't
3959 hold true for POST_INC / POST_DEC. Either we have to
3960 convert the memory access to a true POST_INC / POST_DEC,
3961 or we can't use the reload register for inheritance. */
3962 if ((code == POST_INC || code == POST_DEC)
3963 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3964 REGNO (rld[i].reg_rtx))
3965 /* Make sure it is the inc/dec pseudo, and not
3966 some other (e.g. output operand) pseudo. */
3967 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3968 == REGNO (XEXP (in_reg, 0))))
3971 rtx reload_reg = rld[i].reg_rtx;
3972 enum machine_mode mode = GET_MODE (reload_reg);
3976 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3978 /* We really want to ignore REG_INC notes here, so
3979 use PATTERN (p) as argument to reg_set_p . */
3980 if (reg_set_p (reload_reg, PATTERN (p)))
3982 n = count_occurrences (PATTERN (p), reload_reg, 0);
3987 n = validate_replace_rtx (reload_reg,
3988 gen_rtx (code, mode,
3992 /* We must also verify that the constraints
3993 are met after the replacement. */
3996 n = constrain_operands (1);
4000 /* If the constraints were not met, then
4001 undo the replacement. */
4004 validate_replace_rtx (gen_rtx (code, mode,
4016 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4018 /* Mark this as having an output reload so that the
4019 REG_INC processing code below won't invalidate
4020 the reload for inheritance. */
4021 SET_HARD_REG_BIT (reg_is_output_reload,
4022 REGNO (reload_reg));
4023 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4026 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4029 else if ((code == PRE_INC || code == PRE_DEC)
4030 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4031 REGNO (rld[i].reg_rtx))
4032 /* Make sure it is the inc/dec pseudo, and not
4033 some other (e.g. output operand) pseudo. */
4034 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4035 == REGNO (XEXP (in_reg, 0))))
4037 SET_HARD_REG_BIT (reg_is_output_reload,
4038 REGNO (rld[i].reg_rtx));
4039 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4043 /* If a pseudo that got a hard register is auto-incremented,
4044 we must purge records of copying it into pseudos without
4046 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4047 if (REG_NOTE_KIND (x) == REG_INC)
4049 /* See if this pseudo reg was reloaded in this insn.
4050 If so, its last-reload info is still valid
4051 because it is based on this insn's reload. */
4052 for (i = 0; i < n_reloads; i++)
4053 if (rld[i].out == XEXP (x, 0))
4057 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4061 /* A reload reg's contents are unknown after a label. */
4062 if (GET_CODE (insn) == CODE_LABEL)
4063 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4065 /* Don't assume a reload reg is still good after a call insn
4066 if it is a call-used reg. */
4067 else if (GET_CODE (insn) == CALL_INSN)
4068 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4072 free (reg_last_reload_reg);
4073 free (reg_has_output_reload);
4076 /* Discard all record of any value reloaded from X,
4077 or reloaded in X from someplace else;
4078 unless X is an output reload reg of the current insn.
4080 X may be a hard reg (the reload reg)
4081 or it may be a pseudo reg that was reloaded from. */
4084 forget_old_reloads_1 (x, ignored, data)
4086 rtx ignored ATTRIBUTE_UNUSED;
4087 void *data ATTRIBUTE_UNUSED;
4093 /* note_stores does give us subregs of hard regs,
4094 subreg_regno_offset will abort if it is not a hard reg. */
4095 while (GET_CODE (x) == SUBREG)
4097 offset += subreg_regno_offset (REGNO (SUBREG_REG (x)),
4098 GET_MODE (SUBREG_REG (x)),
4104 if (GET_CODE (x) != REG)
4107 regno = REGNO (x) + offset;
4109 if (regno >= FIRST_PSEUDO_REGISTER)
4115 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4116 /* Storing into a spilled-reg invalidates its contents.
4117 This can happen if a block-local pseudo is allocated to that reg
4118 and it wasn't spilled because this block's total need is 0.
4119 Then some insn might have an optional reload and use this reg. */
4120 for (i = 0; i < nr; i++)
4121 /* But don't do this if the reg actually serves as an output
4122 reload reg in the current instruction. */
4124 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4126 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4127 spill_reg_store[regno + i] = 0;
4131 /* Since value of X has changed,
4132 forget any value previously copied from it. */
4135 /* But don't forget a copy if this is the output reload
4136 that establishes the copy's validity. */
4137 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4138 reg_last_reload_reg[regno + nr] = 0;
4141 /* The following HARD_REG_SETs indicate when each hard register is
4142 used for a reload of various parts of the current insn. */
4144 /* If reg is unavailable for all reloads. */
4145 static HARD_REG_SET reload_reg_unavailable;
4146 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4147 static HARD_REG_SET reload_reg_used;
4148 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4149 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4150 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4151 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4152 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4153 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4154 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4155 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4156 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4157 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4158 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4159 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4160 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4161 static HARD_REG_SET reload_reg_used_in_op_addr;
4162 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4163 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4164 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4165 static HARD_REG_SET reload_reg_used_in_insn;
4166 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4167 static HARD_REG_SET reload_reg_used_in_other_addr;
4169 /* If reg is in use as a reload reg for any sort of reload. */
4170 static HARD_REG_SET reload_reg_used_at_all;
4172 /* If reg is use as an inherited reload. We just mark the first register
4174 static HARD_REG_SET reload_reg_used_for_inherit;
4176 /* Records which hard regs are used in any way, either as explicit use or
4177 by being allocated to a pseudo during any point of the current insn. */
4178 static HARD_REG_SET reg_used_in_insn;
4180 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4181 TYPE. MODE is used to indicate how many consecutive regs are
4185 mark_reload_reg_in_use (regno, opnum, type, mode)
4188 enum reload_type type;
4189 enum machine_mode mode;
4191 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4194 for (i = regno; i < nregs + regno; i++)
4199 SET_HARD_REG_BIT (reload_reg_used, i);
4202 case RELOAD_FOR_INPUT_ADDRESS:
4203 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4206 case RELOAD_FOR_INPADDR_ADDRESS:
4207 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4210 case RELOAD_FOR_OUTPUT_ADDRESS:
4211 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4214 case RELOAD_FOR_OUTADDR_ADDRESS:
4215 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4218 case RELOAD_FOR_OPERAND_ADDRESS:
4219 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4222 case RELOAD_FOR_OPADDR_ADDR:
4223 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4226 case RELOAD_FOR_OTHER_ADDRESS:
4227 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4230 case RELOAD_FOR_INPUT:
4231 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4234 case RELOAD_FOR_OUTPUT:
4235 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4238 case RELOAD_FOR_INSN:
4239 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4243 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4247 /* Similarly, but show REGNO is no longer in use for a reload. */
4250 clear_reload_reg_in_use (regno, opnum, type, mode)
4253 enum reload_type type;
4254 enum machine_mode mode;
4256 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4257 unsigned int start_regno, end_regno, r;
4259 /* A complication is that for some reload types, inheritance might
4260 allow multiple reloads of the same types to share a reload register.
4261 We set check_opnum if we have to check only reloads with the same
4262 operand number, and check_any if we have to check all reloads. */
4263 int check_opnum = 0;
4265 HARD_REG_SET *used_in_set;
4270 used_in_set = &reload_reg_used;
4273 case RELOAD_FOR_INPUT_ADDRESS:
4274 used_in_set = &reload_reg_used_in_input_addr[opnum];
4277 case RELOAD_FOR_INPADDR_ADDRESS:
4279 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4282 case RELOAD_FOR_OUTPUT_ADDRESS:
4283 used_in_set = &reload_reg_used_in_output_addr[opnum];
4286 case RELOAD_FOR_OUTADDR_ADDRESS:
4288 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4291 case RELOAD_FOR_OPERAND_ADDRESS:
4292 used_in_set = &reload_reg_used_in_op_addr;
4295 case RELOAD_FOR_OPADDR_ADDR:
4297 used_in_set = &reload_reg_used_in_op_addr_reload;
4300 case RELOAD_FOR_OTHER_ADDRESS:
4301 used_in_set = &reload_reg_used_in_other_addr;
4305 case RELOAD_FOR_INPUT:
4306 used_in_set = &reload_reg_used_in_input[opnum];
4309 case RELOAD_FOR_OUTPUT:
4310 used_in_set = &reload_reg_used_in_output[opnum];
4313 case RELOAD_FOR_INSN:
4314 used_in_set = &reload_reg_used_in_insn;
4319 /* We resolve conflicts with remaining reloads of the same type by
4320 excluding the intervals of of reload registers by them from the
4321 interval of freed reload registers. Since we only keep track of
4322 one set of interval bounds, we might have to exclude somewhat
4323 more than what would be necessary if we used a HARD_REG_SET here.
4324 But this should only happen very infrequently, so there should
4325 be no reason to worry about it. */
4327 start_regno = regno;
4328 end_regno = regno + nregs;
4329 if (check_opnum || check_any)
4331 for (i = n_reloads - 1; i >= 0; i--)
4333 if (rld[i].when_needed == type
4334 && (check_any || rld[i].opnum == opnum)
4337 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4338 unsigned int conflict_end
4340 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4342 /* If there is an overlap with the first to-be-freed register,
4343 adjust the interval start. */
4344 if (conflict_start <= start_regno && conflict_end > start_regno)
4345 start_regno = conflict_end;
4346 /* Otherwise, if there is a conflict with one of the other
4347 to-be-freed registers, adjust the interval end. */
4348 if (conflict_start > start_regno && conflict_start < end_regno)
4349 end_regno = conflict_start;
4354 for (r = start_regno; r < end_regno; r++)
4355 CLEAR_HARD_REG_BIT (*used_in_set, r);
4358 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4359 specified by OPNUM and TYPE. */
4362 reload_reg_free_p (regno, opnum, type)
4365 enum reload_type type;
4369 /* In use for a RELOAD_OTHER means it's not available for anything. */
4370 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4371 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4377 /* In use for anything means we can't use it for RELOAD_OTHER. */
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4380 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4383 for (i = 0; i < reload_n_operands; i++)
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4385 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4386 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4387 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4388 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4389 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4394 case RELOAD_FOR_INPUT:
4395 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4396 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4399 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4402 /* If it is used for some other input, can't use it. */
4403 for (i = 0; i < reload_n_operands; i++)
4404 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4407 /* If it is used in a later operand's address, can't use it. */
4408 for (i = opnum + 1; i < reload_n_operands; i++)
4409 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4410 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4415 case RELOAD_FOR_INPUT_ADDRESS:
4416 /* Can't use a register if it is used for an input address for this
4417 operand or used as an input in an earlier one. */
4418 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4419 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4422 for (i = 0; i < opnum; i++)
4423 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4428 case RELOAD_FOR_INPADDR_ADDRESS:
4429 /* Can't use a register if it is used for an input address
4430 for this operand or used as an input in an earlier
4432 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4435 for (i = 0; i < opnum; i++)
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4441 case RELOAD_FOR_OUTPUT_ADDRESS:
4442 /* Can't use a register if it is used for an output address for this
4443 operand or used as an output in this or a later operand. Note
4444 that multiple output operands are emitted in reverse order, so
4445 the conflicting ones are those with lower indices. */
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4449 for (i = 0; i <= opnum; i++)
4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4455 case RELOAD_FOR_OUTADDR_ADDRESS:
4456 /* Can't use a register if it is used for an output address
4457 for this operand or used as an output in this or a
4458 later operand. Note that multiple output operands are
4459 emitted in reverse order, so the conflicting ones are
4460 those with lower indices. */
4461 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4464 for (i = 0; i <= opnum; i++)
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4470 case RELOAD_FOR_OPERAND_ADDRESS:
4471 for (i = 0; i < reload_n_operands; i++)
4472 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4475 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4476 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4478 case RELOAD_FOR_OPADDR_ADDR:
4479 for (i = 0; i < reload_n_operands; i++)
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4483 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4485 case RELOAD_FOR_OUTPUT:
4486 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4487 outputs, or an operand address for this or an earlier output.
4488 Note that multiple output operands are emitted in reverse order,
4489 so the conflicting ones are those with higher indices. */
4490 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4493 for (i = 0; i < reload_n_operands; i++)
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4497 for (i = opnum; i < reload_n_operands; i++)
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4499 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4504 case RELOAD_FOR_INSN:
4505 for (i = 0; i < reload_n_operands; i++)
4506 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4507 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4510 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4511 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4513 case RELOAD_FOR_OTHER_ADDRESS:
4514 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4519 /* Return 1 if the value in reload reg REGNO, as used by a reload
4520 needed for the part of the insn specified by OPNUM and TYPE,
4521 is still available in REGNO at the end of the insn.
4523 We can assume that the reload reg was already tested for availability
4524 at the time it is needed, and we should not check this again,
4525 in case the reg has already been marked in use. */
4528 reload_reg_reaches_end_p (regno, opnum, type)
4531 enum reload_type type;
4538 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4539 its value must reach the end. */
4542 /* If this use is for part of the insn,
4543 its value reaches if no subsequent part uses the same register.
4544 Just like the above function, don't try to do this with lots
4547 case RELOAD_FOR_OTHER_ADDRESS:
4548 /* Here we check for everything else, since these don't conflict
4549 with anything else and everything comes later. */
4551 for (i = 0; i < reload_n_operands; i++)
4552 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4553 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4554 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4555 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4556 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4560 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4561 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4562 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4564 case RELOAD_FOR_INPUT_ADDRESS:
4565 case RELOAD_FOR_INPADDR_ADDRESS:
4566 /* Similar, except that we check only for this and subsequent inputs
4567 and the address of only subsequent inputs and we do not need
4568 to check for RELOAD_OTHER objects since they are known not to
4571 for (i = opnum; i < reload_n_operands; i++)
4572 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4575 for (i = opnum + 1; i < reload_n_operands; i++)
4576 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4577 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4580 for (i = 0; i < reload_n_operands; i++)
4581 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4582 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4583 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4589 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4590 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4591 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4593 case RELOAD_FOR_INPUT:
4594 /* Similar to input address, except we start at the next operand for
4595 both input and input address and we do not check for
4596 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4599 for (i = opnum + 1; i < reload_n_operands; i++)
4600 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4601 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4602 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4605 /* ... fall through ... */
4607 case RELOAD_FOR_OPERAND_ADDRESS:
4608 /* Check outputs and their addresses. */
4610 for (i = 0; i < reload_n_operands; i++)
4611 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4612 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4613 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4616 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4618 case RELOAD_FOR_OPADDR_ADDR:
4619 for (i = 0; i < reload_n_operands; i++)
4620 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4621 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4622 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4625 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4626 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4627 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4629 case RELOAD_FOR_INSN:
4630 /* These conflict with other outputs with RELOAD_OTHER. So
4631 we need only check for output addresses. */
4633 opnum = reload_n_operands;
4635 /* ... fall through ... */
4637 case RELOAD_FOR_OUTPUT:
4638 case RELOAD_FOR_OUTPUT_ADDRESS:
4639 case RELOAD_FOR_OUTADDR_ADDRESS:
4640 /* We already know these can't conflict with a later output. So the
4641 only thing to check are later output addresses.
4642 Note that multiple output operands are emitted in reverse order,
4643 so the conflicting ones are those with lower indices. */
4644 for (i = 0; i < opnum; i++)
4645 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4646 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4655 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4658 This function uses the same algorithm as reload_reg_free_p above. */
4661 reloads_conflict (r1, r2)
4664 enum reload_type r1_type = rld[r1].when_needed;
4665 enum reload_type r2_type = rld[r2].when_needed;
4666 int r1_opnum = rld[r1].opnum;
4667 int r2_opnum = rld[r2].opnum;
4669 /* RELOAD_OTHER conflicts with everything. */
4670 if (r2_type == RELOAD_OTHER)
4673 /* Otherwise, check conflicts differently for each type. */
4677 case RELOAD_FOR_INPUT:
4678 return (r2_type == RELOAD_FOR_INSN
4679 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4680 || r2_type == RELOAD_FOR_OPADDR_ADDR
4681 || r2_type == RELOAD_FOR_INPUT
4682 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4683 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4684 && r2_opnum > r1_opnum));
4686 case RELOAD_FOR_INPUT_ADDRESS:
4687 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4688 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4690 case RELOAD_FOR_INPADDR_ADDRESS:
4691 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4692 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4694 case RELOAD_FOR_OUTPUT_ADDRESS:
4695 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4696 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4698 case RELOAD_FOR_OUTADDR_ADDRESS:
4699 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4700 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4702 case RELOAD_FOR_OPERAND_ADDRESS:
4703 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4704 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4706 case RELOAD_FOR_OPADDR_ADDR:
4707 return (r2_type == RELOAD_FOR_INPUT
4708 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4710 case RELOAD_FOR_OUTPUT:
4711 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4712 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4713 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4714 && r2_opnum >= r1_opnum));
4716 case RELOAD_FOR_INSN:
4717 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4718 || r2_type == RELOAD_FOR_INSN
4719 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4721 case RELOAD_FOR_OTHER_ADDRESS:
4722 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4732 /* Indexed by reload number, 1 if incoming value
4733 inherited from previous insns. */
4734 char reload_inherited[MAX_RELOADS];
4736 /* For an inherited reload, this is the insn the reload was inherited from,
4737 if we know it. Otherwise, this is 0. */
4738 rtx reload_inheritance_insn[MAX_RELOADS];
4740 /* If non-zero, this is a place to get the value of the reload,
4741 rather than using reload_in. */
4742 rtx reload_override_in[MAX_RELOADS];
4744 /* For each reload, the hard register number of the register used,
4745 or -1 if we did not need a register for this reload. */
4746 int reload_spill_index[MAX_RELOADS];
4748 /* Subroutine of free_for_value_p, used to check a single register.
4749 START_REGNO is the starting regno of the full reload register
4750 (possibly comprising multiple hard registers) that we are considering. */
4753 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4754 reloadnum, ignore_address_reloads)
4755 int start_regno, regno;
4757 enum reload_type type;
4760 int ignore_address_reloads;
4763 /* Set if we see an input reload that must not share its reload register
4764 with any new earlyclobber, but might otherwise share the reload
4765 register with an output or input-output reload. */
4766 int check_earlyclobber = 0;
4770 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4773 if (out == const0_rtx)
4779 /* We use some pseudo 'time' value to check if the lifetimes of the
4780 new register use would overlap with the one of a previous reload
4781 that is not read-only or uses a different value.
4782 The 'time' used doesn't have to be linear in any shape or form, just
4784 Some reload types use different 'buckets' for each operand.
4785 So there are MAX_RECOG_OPERANDS different time values for each
4787 We compute TIME1 as the time when the register for the prospective
4788 new reload ceases to be live, and TIME2 for each existing
4789 reload as the time when that the reload register of that reload
4791 Where there is little to be gained by exact lifetime calculations,
4792 we just make conservative assumptions, i.e. a longer lifetime;
4793 this is done in the 'default:' cases. */
4796 case RELOAD_FOR_OTHER_ADDRESS:
4797 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4798 time1 = copy ? 0 : 1;
4801 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4803 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4804 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4805 respectively, to the time values for these, we get distinct time
4806 values. To get distinct time values for each operand, we have to
4807 multiply opnum by at least three. We round that up to four because
4808 multiply by four is often cheaper. */
4809 case RELOAD_FOR_INPADDR_ADDRESS:
4810 time1 = opnum * 4 + 2;
4812 case RELOAD_FOR_INPUT_ADDRESS:
4813 time1 = opnum * 4 + 3;
4815 case RELOAD_FOR_INPUT:
4816 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4817 executes (inclusive). */
4818 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4820 case RELOAD_FOR_OPADDR_ADDR:
4822 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4823 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4825 case RELOAD_FOR_OPERAND_ADDRESS:
4826 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4828 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4830 case RELOAD_FOR_OUTADDR_ADDRESS:
4831 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4833 case RELOAD_FOR_OUTPUT_ADDRESS:
4834 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4837 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4840 for (i = 0; i < n_reloads; i++)
4842 rtx reg = rld[i].reg_rtx;
4843 if (reg && GET_CODE (reg) == REG
4844 && ((unsigned) regno - true_regnum (reg)
4845 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4848 rtx other_input = rld[i].in;
4850 /* If the other reload loads the same input value, that
4851 will not cause a conflict only if it's loading it into
4852 the same register. */
4853 if (true_regnum (reg) != start_regno)
4854 other_input = NULL_RTX;
4855 if (! other_input || ! rtx_equal_p (other_input, value)
4856 || rld[i].out || out)
4859 switch (rld[i].when_needed)
4861 case RELOAD_FOR_OTHER_ADDRESS:
4864 case RELOAD_FOR_INPADDR_ADDRESS:
4865 /* find_reloads makes sure that a
4866 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4867 by at most one - the first -
4868 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4869 address reload is inherited, the address address reload
4870 goes away, so we can ignore this conflict. */
4871 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4872 && ignore_address_reloads
4873 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4874 Then the address address is still needed to store
4875 back the new address. */
4876 && ! rld[reloadnum].out)
4878 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4879 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4881 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4882 && ignore_address_reloads
4883 /* Unless we are reloading an auto_inc expression. */
4884 && ! rld[reloadnum].out)
4886 time2 = rld[i].opnum * 4 + 2;
4888 case RELOAD_FOR_INPUT_ADDRESS:
4889 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4890 && ignore_address_reloads
4891 && ! rld[reloadnum].out)
4893 time2 = rld[i].opnum * 4 + 3;
4895 case RELOAD_FOR_INPUT:
4896 time2 = rld[i].opnum * 4 + 4;
4897 check_earlyclobber = 1;
4899 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4900 == MAX_RECOG_OPERAND * 4 */
4901 case RELOAD_FOR_OPADDR_ADDR:
4902 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4903 && ignore_address_reloads
4904 && ! rld[reloadnum].out)
4906 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4908 case RELOAD_FOR_OPERAND_ADDRESS:
4909 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4910 check_earlyclobber = 1;
4912 case RELOAD_FOR_INSN:
4913 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4915 case RELOAD_FOR_OUTPUT:
4916 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4917 instruction is executed. */
4918 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4920 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4921 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4923 case RELOAD_FOR_OUTADDR_ADDRESS:
4924 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4925 && ignore_address_reloads
4926 && ! rld[reloadnum].out)
4928 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4930 case RELOAD_FOR_OUTPUT_ADDRESS:
4931 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4934 /* If there is no conflict in the input part, handle this
4935 like an output reload. */
4936 if (! rld[i].in || rtx_equal_p (other_input, value))
4938 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4939 /* Earlyclobbered outputs must conflict with inputs. */
4940 if (earlyclobber_operand_p (rld[i].out))
4941 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4946 /* RELOAD_OTHER might be live beyond instruction execution,
4947 but this is not obvious when we set time2 = 1. So check
4948 here if there might be a problem with the new reload
4949 clobbering the register used by the RELOAD_OTHER. */
4957 && (! rld[i].in || rld[i].out
4958 || ! rtx_equal_p (other_input, value)))
4959 || (out && rld[reloadnum].out_reg
4960 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4966 /* Earlyclobbered outputs must conflict with inputs. */
4967 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4973 /* Return 1 if the value in reload reg REGNO, as used by a reload
4974 needed for the part of the insn specified by OPNUM and TYPE,
4975 may be used to load VALUE into it.
4977 MODE is the mode in which the register is used, this is needed to
4978 determine how many hard regs to test.
4980 Other read-only reloads with the same value do not conflict
4981 unless OUT is non-zero and these other reloads have to live while
4982 output reloads live.
4983 If OUT is CONST0_RTX, this is a special case: it means that the
4984 test should not be for using register REGNO as reload register, but
4985 for copying from register REGNO into the reload register.
4987 RELOADNUM is the number of the reload we want to load this value for;
4988 a reload does not conflict with itself.
4990 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4991 reloads that load an address for the very reload we are considering.
4993 The caller has to make sure that there is no conflict with the return
4997 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4998 ignore_address_reloads)
5000 enum machine_mode mode;
5002 enum reload_type type;
5005 int ignore_address_reloads;
5007 int nregs = HARD_REGNO_NREGS (regno, mode);
5009 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5010 value, out, reloadnum,
5011 ignore_address_reloads))
5016 /* Determine whether the reload reg X overlaps any rtx'es used for
5017 overriding inheritance. Return nonzero if so. */
5020 conflicts_with_override (x)
5024 for (i = 0; i < n_reloads; i++)
5025 if (reload_override_in[i]
5026 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5031 /* Give an error message saying we failed to find a reload for INSN,
5032 and clear out reload R. */
5034 failed_reload (insn, r)
5038 if (asm_noperands (PATTERN (insn)) < 0)
5039 /* It's the compiler's fault. */
5040 fatal_insn ("could not find a spill register", insn);
5042 /* It's the user's fault; the operand's mode and constraint
5043 don't match. Disable this reload so we don't crash in final. */
5044 error_for_asm (insn,
5045 "`asm' operand constraint incompatible with operand size");
5049 rld[r].optional = 1;
5050 rld[r].secondary_p = 1;
5053 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5054 for reload R. If it's valid, get an rtx for it. Return nonzero if
5057 set_reload_reg (i, r)
5061 rtx reg = spill_reg_rtx[i];
5063 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5064 spill_reg_rtx[i] = reg
5065 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5067 regno = true_regnum (reg);
5069 /* Detect when the reload reg can't hold the reload mode.
5070 This used to be one `if', but Sequent compiler can't handle that. */
5071 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5073 enum machine_mode test_mode = VOIDmode;
5075 test_mode = GET_MODE (rld[r].in);
5076 /* If rld[r].in has VOIDmode, it means we will load it
5077 in whatever mode the reload reg has: to wit, rld[r].mode.
5078 We have already tested that for validity. */
5079 /* Aside from that, we need to test that the expressions
5080 to reload from or into have modes which are valid for this
5081 reload register. Otherwise the reload insns would be invalid. */
5082 if (! (rld[r].in != 0 && test_mode != VOIDmode
5083 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5084 if (! (rld[r].out != 0
5085 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5087 /* The reg is OK. */
5090 /* Mark as in use for this insn the reload regs we use
5092 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5093 rld[r].when_needed, rld[r].mode);
5095 rld[r].reg_rtx = reg;
5096 reload_spill_index[r] = spill_regs[i];
5103 /* Find a spill register to use as a reload register for reload R.
5104 LAST_RELOAD is non-zero if this is the last reload for the insn being
5107 Set rld[R].reg_rtx to the register allocated.
5109 We return 1 if successful, or 0 if we couldn't find a spill reg and
5110 we didn't change anything. */
5113 allocate_reload_reg (chain, r, last_reload)
5114 struct insn_chain *chain ATTRIBUTE_UNUSED;
5120 /* If we put this reload ahead, thinking it is a group,
5121 then insist on finding a group. Otherwise we can grab a
5122 reg that some other reload needs.
5123 (That can happen when we have a 68000 DATA_OR_FP_REG
5124 which is a group of data regs or one fp reg.)
5125 We need not be so restrictive if there are no more reloads
5128 ??? Really it would be nicer to have smarter handling
5129 for that kind of reg class, where a problem like this is normal.
5130 Perhaps those classes should be avoided for reloading
5131 by use of more alternatives. */
5133 int force_group = rld[r].nregs > 1 && ! last_reload;
5135 /* If we want a single register and haven't yet found one,
5136 take any reg in the right class and not in use.
5137 If we want a consecutive group, here is where we look for it.
5139 We use two passes so we can first look for reload regs to
5140 reuse, which are already in use for other reloads in this insn,
5141 and only then use additional registers.
5142 I think that maximizing reuse is needed to make sure we don't
5143 run out of reload regs. Suppose we have three reloads, and
5144 reloads A and B can share regs. These need two regs.
5145 Suppose A and B are given different regs.
5146 That leaves none for C. */
5147 for (pass = 0; pass < 2; pass++)
5149 /* I is the index in spill_regs.
5150 We advance it round-robin between insns to use all spill regs
5151 equally, so that inherited reloads have a chance
5152 of leapfrogging each other. */
5156 for (count = 0; count < n_spills; count++)
5158 int class = (int) rld[r].class;
5164 regnum = spill_regs[i];
5166 if ((reload_reg_free_p (regnum, rld[r].opnum,
5169 /* We check reload_reg_used to make sure we
5170 don't clobber the return register. */
5171 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5172 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5173 rld[r].when_needed, rld[r].in,
5175 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5176 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5177 /* Look first for regs to share, then for unshared. But
5178 don't share regs used for inherited reloads; they are
5179 the ones we want to preserve. */
5181 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5183 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5186 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5187 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5188 (on 68000) got us two FP regs. If NR is 1,
5189 we would reject both of them. */
5192 /* If we need only one reg, we have already won. */
5195 /* But reject a single reg if we demand a group. */
5200 /* Otherwise check that as many consecutive regs as we need
5201 are available here. */
5204 int regno = regnum + nr - 1;
5205 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5206 && spill_reg_order[regno] >= 0
5207 && reload_reg_free_p (regno, rld[r].opnum,
5208 rld[r].when_needed)))
5217 /* If we found something on pass 1, omit pass 2. */
5218 if (count < n_spills)
5222 /* We should have found a spill register by now. */
5223 if (count >= n_spills)
5226 /* I is the index in SPILL_REG_RTX of the reload register we are to
5227 allocate. Get an rtx for it and find its register number. */
5229 return set_reload_reg (i, r);
5232 /* Initialize all the tables needed to allocate reload registers.
5233 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5234 is the array we use to restore the reg_rtx field for every reload. */
5237 choose_reload_regs_init (chain, save_reload_reg_rtx)
5238 struct insn_chain *chain;
5239 rtx *save_reload_reg_rtx;
5243 for (i = 0; i < n_reloads; i++)
5244 rld[i].reg_rtx = save_reload_reg_rtx[i];
5246 memset (reload_inherited, 0, MAX_RELOADS);
5247 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5248 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5250 CLEAR_HARD_REG_SET (reload_reg_used);
5251 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5252 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5253 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5254 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5255 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5257 CLEAR_HARD_REG_SET (reg_used_in_insn);
5260 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5261 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5262 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5263 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5264 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5265 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5268 for (i = 0; i < reload_n_operands; i++)
5270 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5271 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5272 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5273 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5274 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5275 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5278 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5280 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5282 for (i = 0; i < n_reloads; i++)
5283 /* If we have already decided to use a certain register,
5284 don't use it in another way. */
5286 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5287 rld[i].when_needed, rld[i].mode);
5290 /* Assign hard reg targets for the pseudo-registers we must reload
5291 into hard regs for this insn.
5292 Also output the instructions to copy them in and out of the hard regs.
5294 For machines with register classes, we are responsible for
5295 finding a reload reg in the proper class. */
5298 choose_reload_regs (chain)
5299 struct insn_chain *chain;
5301 rtx insn = chain->insn;
5303 unsigned int max_group_size = 1;
5304 enum reg_class group_class = NO_REGS;
5305 int pass, win, inheritance;
5307 rtx save_reload_reg_rtx[MAX_RELOADS];
5309 /* In order to be certain of getting the registers we need,
5310 we must sort the reloads into order of increasing register class.
5311 Then our grabbing of reload registers will parallel the process
5312 that provided the reload registers.
5314 Also note whether any of the reloads wants a consecutive group of regs.
5315 If so, record the maximum size of the group desired and what
5316 register class contains all the groups needed by this insn. */
5318 for (j = 0; j < n_reloads; j++)
5320 reload_order[j] = j;
5321 reload_spill_index[j] = -1;
5323 if (rld[j].nregs > 1)
5325 max_group_size = MAX (rld[j].nregs, max_group_size);
5327 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5330 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5334 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5336 /* If -O, try first with inheritance, then turning it off.
5337 If not -O, don't do inheritance.
5338 Using inheritance when not optimizing leads to paradoxes
5339 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5340 because one side of the comparison might be inherited. */
5342 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5344 choose_reload_regs_init (chain, save_reload_reg_rtx);
5346 /* Process the reloads in order of preference just found.
5347 Beyond this point, subregs can be found in reload_reg_rtx.
5349 This used to look for an existing reloaded home for all of the
5350 reloads, and only then perform any new reloads. But that could lose
5351 if the reloads were done out of reg-class order because a later
5352 reload with a looser constraint might have an old home in a register
5353 needed by an earlier reload with a tighter constraint.
5355 To solve this, we make two passes over the reloads, in the order
5356 described above. In the first pass we try to inherit a reload
5357 from a previous insn. If there is a later reload that needs a
5358 class that is a proper subset of the class being processed, we must
5359 also allocate a spill register during the first pass.
5361 Then make a second pass over the reloads to allocate any reloads
5362 that haven't been given registers yet. */
5364 for (j = 0; j < n_reloads; j++)
5366 int r = reload_order[j];
5367 rtx search_equiv = NULL_RTX;
5369 /* Ignore reloads that got marked inoperative. */
5370 if (rld[r].out == 0 && rld[r].in == 0
5371 && ! rld[r].secondary_p)
5374 /* If find_reloads chose to use reload_in or reload_out as a reload
5375 register, we don't need to chose one. Otherwise, try even if it
5376 found one since we might save an insn if we find the value lying
5378 Try also when reload_in is a pseudo without a hard reg. */
5379 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5380 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5381 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5382 && GET_CODE (rld[r].in) != MEM
5383 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5386 #if 0 /* No longer needed for correct operation.
5387 It might give better code, or might not; worth an experiment? */
5388 /* If this is an optional reload, we can't inherit from earlier insns
5389 until we are sure that any non-optional reloads have been allocated.
5390 The following code takes advantage of the fact that optional reloads
5391 are at the end of reload_order. */
5392 if (rld[r].optional != 0)
5393 for (i = 0; i < j; i++)
5394 if ((rld[reload_order[i]].out != 0
5395 || rld[reload_order[i]].in != 0
5396 || rld[reload_order[i]].secondary_p)
5397 && ! rld[reload_order[i]].optional
5398 && rld[reload_order[i]].reg_rtx == 0)
5399 allocate_reload_reg (chain, reload_order[i], 0);
5402 /* First see if this pseudo is already available as reloaded
5403 for a previous insn. We cannot try to inherit for reloads
5404 that are smaller than the maximum number of registers needed
5405 for groups unless the register we would allocate cannot be used
5408 We could check here to see if this is a secondary reload for
5409 an object that is already in a register of the desired class.
5410 This would avoid the need for the secondary reload register.
5411 But this is complex because we can't easily determine what
5412 objects might want to be loaded via this reload. So let a
5413 register be allocated here. In `emit_reload_insns' we suppress
5414 one of the loads in the case described above. */
5420 enum machine_mode mode = VOIDmode;
5424 else if (GET_CODE (rld[r].in) == REG)
5426 regno = REGNO (rld[r].in);
5427 mode = GET_MODE (rld[r].in);
5429 else if (GET_CODE (rld[r].in_reg) == REG)
5431 regno = REGNO (rld[r].in_reg);
5432 mode = GET_MODE (rld[r].in_reg);
5434 else if (GET_CODE (rld[r].in_reg) == SUBREG
5435 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5437 byte = SUBREG_BYTE (rld[r].in_reg);
5438 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5439 if (regno < FIRST_PSEUDO_REGISTER)
5440 regno = subreg_regno (rld[r].in_reg);
5441 mode = GET_MODE (rld[r].in_reg);
5444 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5445 || GET_CODE (rld[r].in_reg) == PRE_DEC
5446 || GET_CODE (rld[r].in_reg) == POST_INC
5447 || GET_CODE (rld[r].in_reg) == POST_DEC)
5448 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5450 regno = REGNO (XEXP (rld[r].in_reg, 0));
5451 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5452 rld[r].out = rld[r].in;
5456 /* This won't work, since REGNO can be a pseudo reg number.
5457 Also, it takes much more hair to keep track of all the things
5458 that can invalidate an inherited reload of part of a pseudoreg. */
5459 else if (GET_CODE (rld[r].in) == SUBREG
5460 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5461 regno = subreg_regno (rld[r].in);
5464 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5466 enum reg_class class = rld[r].class, last_class;
5467 rtx last_reg = reg_last_reload_reg[regno];
5468 enum machine_mode need_mode;
5470 i = REGNO (last_reg);
5471 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5472 last_class = REGNO_REG_CLASS (i);
5478 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5479 GET_MODE_CLASS (mode));
5482 #ifdef CLASS_CANNOT_CHANGE_MODE
5484 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5485 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5487 : (GET_MODE_SIZE (GET_MODE (last_reg))
5488 >= GET_MODE_SIZE (need_mode)))
5490 (GET_MODE_SIZE (GET_MODE (last_reg))
5491 >= GET_MODE_SIZE (need_mode))
5493 && reg_reloaded_contents[i] == regno
5494 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5495 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5496 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5497 /* Even if we can't use this register as a reload
5498 register, we might use it for reload_override_in,
5499 if copying it to the desired class is cheap
5501 || ((REGISTER_MOVE_COST (mode, last_class, class)
5502 < MEMORY_MOVE_COST (mode, class, 1))
5503 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5504 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5508 #ifdef SECONDARY_MEMORY_NEEDED
5509 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5514 && (rld[r].nregs == max_group_size
5515 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5517 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5518 rld[r].when_needed, rld[r].in,
5521 /* If a group is needed, verify that all the subsequent
5522 registers still have their values intact. */
5523 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5526 for (k = 1; k < nr; k++)
5527 if (reg_reloaded_contents[i + k] != regno
5528 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5536 last_reg = (GET_MODE (last_reg) == mode
5537 ? last_reg : gen_rtx_REG (mode, i));
5540 for (k = 0; k < nr; k++)
5541 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5544 /* We found a register that contains the
5545 value we need. If this register is the
5546 same as an `earlyclobber' operand of the
5547 current insn, just mark it as a place to
5548 reload from since we can't use it as the
5549 reload register itself. */
5551 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5552 if (reg_overlap_mentioned_for_reload_p
5553 (reg_last_reload_reg[regno],
5554 reload_earlyclobbers[i1]))
5557 if (i1 != n_earlyclobbers
5558 || ! (free_for_value_p (i, rld[r].mode,
5560 rld[r].when_needed, rld[r].in,
5562 /* Don't use it if we'd clobber a pseudo reg. */
5563 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5565 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5566 /* Don't clobber the frame pointer. */
5567 || (i == HARD_FRAME_POINTER_REGNUM
5569 /* Don't really use the inherited spill reg
5570 if we need it wider than we've got it. */
5571 || (GET_MODE_SIZE (rld[r].mode)
5572 > GET_MODE_SIZE (mode))
5575 /* If find_reloads chose reload_out as reload
5576 register, stay with it - that leaves the
5577 inherited register for subsequent reloads. */
5578 || (rld[r].out && rld[r].reg_rtx
5579 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5581 if (! rld[r].optional)
5583 reload_override_in[r] = last_reg;
5584 reload_inheritance_insn[r]
5585 = reg_reloaded_insn[i];
5591 /* We can use this as a reload reg. */
5592 /* Mark the register as in use for this part of
5594 mark_reload_reg_in_use (i,
5598 rld[r].reg_rtx = last_reg;
5599 reload_inherited[r] = 1;
5600 reload_inheritance_insn[r]
5601 = reg_reloaded_insn[i];
5602 reload_spill_index[r] = i;
5603 for (k = 0; k < nr; k++)
5604 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5612 /* Here's another way to see if the value is already lying around. */
5615 && ! reload_inherited[r]
5617 && (CONSTANT_P (rld[r].in)
5618 || GET_CODE (rld[r].in) == PLUS
5619 || GET_CODE (rld[r].in) == REG
5620 || GET_CODE (rld[r].in) == MEM)
5621 && (rld[r].nregs == max_group_size
5622 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5623 search_equiv = rld[r].in;
5624 /* If this is an output reload from a simple move insn, look
5625 if an equivalence for the input is available. */
5626 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5628 rtx set = single_set (insn);
5631 && rtx_equal_p (rld[r].out, SET_DEST (set))
5632 && CONSTANT_P (SET_SRC (set)))
5633 search_equiv = SET_SRC (set);
5639 = find_equiv_reg (search_equiv, insn, rld[r].class,
5640 -1, NULL, 0, rld[r].mode);
5645 if (GET_CODE (equiv) == REG)
5646 regno = REGNO (equiv);
5647 else if (GET_CODE (equiv) == SUBREG)
5649 /* This must be a SUBREG of a hard register.
5650 Make a new REG since this might be used in an
5651 address and not all machines support SUBREGs
5653 regno = subreg_regno (equiv);
5654 equiv = gen_rtx_REG (rld[r].mode, regno);
5660 /* If we found a spill reg, reject it unless it is free
5661 and of the desired class. */
5663 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5664 && ! free_for_value_p (regno, rld[r].mode,
5665 rld[r].opnum, rld[r].when_needed,
5666 rld[r].in, rld[r].out, r, 1))
5667 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5671 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5674 /* We found a register that contains the value we need.
5675 If this register is the same as an `earlyclobber' operand
5676 of the current insn, just mark it as a place to reload from
5677 since we can't use it as the reload register itself. */
5680 for (i = 0; i < n_earlyclobbers; i++)
5681 if (reg_overlap_mentioned_for_reload_p (equiv,
5682 reload_earlyclobbers[i]))
5684 if (! rld[r].optional)
5685 reload_override_in[r] = equiv;
5690 /* If the equiv register we have found is explicitly clobbered
5691 in the current insn, it depends on the reload type if we
5692 can use it, use it for reload_override_in, or not at all.
5693 In particular, we then can't use EQUIV for a
5694 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5698 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5699 switch (rld[r].when_needed)
5701 case RELOAD_FOR_OTHER_ADDRESS:
5702 case RELOAD_FOR_INPADDR_ADDRESS:
5703 case RELOAD_FOR_INPUT_ADDRESS:
5704 case RELOAD_FOR_OPADDR_ADDR:
5707 case RELOAD_FOR_INPUT:
5708 case RELOAD_FOR_OPERAND_ADDRESS:
5709 if (! rld[r].optional)
5710 reload_override_in[r] = equiv;
5716 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5717 switch (rld[r].when_needed)
5719 case RELOAD_FOR_OTHER_ADDRESS:
5720 case RELOAD_FOR_INPADDR_ADDRESS:
5721 case RELOAD_FOR_INPUT_ADDRESS:
5722 case RELOAD_FOR_OPADDR_ADDR:
5723 case RELOAD_FOR_OPERAND_ADDRESS:
5724 case RELOAD_FOR_INPUT:
5727 if (! rld[r].optional)
5728 reload_override_in[r] = equiv;
5736 /* If we found an equivalent reg, say no code need be generated
5737 to load it, and use it as our reload reg. */
5738 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5740 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5742 rld[r].reg_rtx = equiv;
5743 reload_inherited[r] = 1;
5745 /* If reg_reloaded_valid is not set for this register,
5746 there might be a stale spill_reg_store lying around.
5747 We must clear it, since otherwise emit_reload_insns
5748 might delete the store. */
5749 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5750 spill_reg_store[regno] = NULL_RTX;
5751 /* If any of the hard registers in EQUIV are spill
5752 registers, mark them as in use for this insn. */
5753 for (k = 0; k < nr; k++)
5755 i = spill_reg_order[regno + k];
5758 mark_reload_reg_in_use (regno, rld[r].opnum,
5761 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5768 /* If we found a register to use already, or if this is an optional
5769 reload, we are done. */
5770 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5774 /* No longer needed for correct operation. Might or might
5775 not give better code on the average. Want to experiment? */
5777 /* See if there is a later reload that has a class different from our
5778 class that intersects our class or that requires less register
5779 than our reload. If so, we must allocate a register to this
5780 reload now, since that reload might inherit a previous reload
5781 and take the only available register in our class. Don't do this
5782 for optional reloads since they will force all previous reloads
5783 to be allocated. Also don't do this for reloads that have been
5786 for (i = j + 1; i < n_reloads; i++)
5788 int s = reload_order[i];
5790 if ((rld[s].in == 0 && rld[s].out == 0
5791 && ! rld[s].secondary_p)
5795 if ((rld[s].class != rld[r].class
5796 && reg_classes_intersect_p (rld[r].class,
5798 || rld[s].nregs < rld[r].nregs)
5805 allocate_reload_reg (chain, r, j == n_reloads - 1);
5809 /* Now allocate reload registers for anything non-optional that
5810 didn't get one yet. */
5811 for (j = 0; j < n_reloads; j++)
5813 int r = reload_order[j];
5815 /* Ignore reloads that got marked inoperative. */
5816 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5819 /* Skip reloads that already have a register allocated or are
5821 if (rld[r].reg_rtx != 0 || rld[r].optional)
5824 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5828 /* If that loop got all the way, we have won. */
5835 /* Loop around and try without any inheritance. */
5840 /* First undo everything done by the failed attempt
5841 to allocate with inheritance. */
5842 choose_reload_regs_init (chain, save_reload_reg_rtx);
5844 /* Some sanity tests to verify that the reloads found in the first
5845 pass are identical to the ones we have now. */
5846 if (chain->n_reloads != n_reloads)
5849 for (i = 0; i < n_reloads; i++)
5851 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5853 if (chain->rld[i].when_needed != rld[i].when_needed)
5855 for (j = 0; j < n_spills; j++)
5856 if (spill_regs[j] == chain->rld[i].regno)
5857 if (! set_reload_reg (j, i))
5858 failed_reload (chain->insn, i);
5862 /* If we thought we could inherit a reload, because it seemed that
5863 nothing else wanted the same reload register earlier in the insn,
5864 verify that assumption, now that all reloads have been assigned.
5865 Likewise for reloads where reload_override_in has been set. */
5867 /* If doing expensive optimizations, do one preliminary pass that doesn't
5868 cancel any inheritance, but removes reloads that have been needed only
5869 for reloads that we know can be inherited. */
5870 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5872 for (j = 0; j < n_reloads; j++)
5874 int r = reload_order[j];
5876 if (reload_inherited[r] && rld[r].reg_rtx)
5877 check_reg = rld[r].reg_rtx;
5878 else if (reload_override_in[r]
5879 && (GET_CODE (reload_override_in[r]) == REG
5880 || GET_CODE (reload_override_in[r]) == SUBREG))
5881 check_reg = reload_override_in[r];
5884 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5885 rld[r].opnum, rld[r].when_needed, rld[r].in,
5886 (reload_inherited[r]
5887 ? rld[r].out : const0_rtx),
5892 reload_inherited[r] = 0;
5893 reload_override_in[r] = 0;
5895 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5896 reload_override_in, then we do not need its related
5897 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5898 likewise for other reload types.
5899 We handle this by removing a reload when its only replacement
5900 is mentioned in reload_in of the reload we are going to inherit.
5901 A special case are auto_inc expressions; even if the input is
5902 inherited, we still need the address for the output. We can
5903 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5904 If we succeeded removing some reload and we are doing a preliminary
5905 pass just to remove such reloads, make another pass, since the
5906 removal of one reload might allow us to inherit another one. */
5908 && rld[r].out != rld[r].in
5909 && remove_address_replacements (rld[r].in) && pass)
5914 /* Now that reload_override_in is known valid,
5915 actually override reload_in. */
5916 for (j = 0; j < n_reloads; j++)
5917 if (reload_override_in[j])
5918 rld[j].in = reload_override_in[j];
5920 /* If this reload won't be done because it has been cancelled or is
5921 optional and not inherited, clear reload_reg_rtx so other
5922 routines (such as subst_reloads) don't get confused. */
5923 for (j = 0; j < n_reloads; j++)
5924 if (rld[j].reg_rtx != 0
5925 && ((rld[j].optional && ! reload_inherited[j])
5926 || (rld[j].in == 0 && rld[j].out == 0
5927 && ! rld[j].secondary_p)))
5929 int regno = true_regnum (rld[j].reg_rtx);
5931 if (spill_reg_order[regno] >= 0)
5932 clear_reload_reg_in_use (regno, rld[j].opnum,
5933 rld[j].when_needed, rld[j].mode);
5935 reload_spill_index[j] = -1;
5938 /* Record which pseudos and which spill regs have output reloads. */
5939 for (j = 0; j < n_reloads; j++)
5941 int r = reload_order[j];
5943 i = reload_spill_index[r];
5945 /* I is nonneg if this reload uses a register.
5946 If rld[r].reg_rtx is 0, this is an optional reload
5947 that we opted to ignore. */
5948 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5949 && rld[r].reg_rtx != 0)
5951 int nregno = REGNO (rld[r].out_reg);
5954 if (nregno < FIRST_PSEUDO_REGISTER)
5955 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5958 reg_has_output_reload[nregno + nr] = 1;
5962 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5964 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5967 if (rld[r].when_needed != RELOAD_OTHER
5968 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5969 && rld[r].when_needed != RELOAD_FOR_INSN)
5975 /* Deallocate the reload register for reload R. This is called from
5976 remove_address_replacements. */
5979 deallocate_reload_reg (r)
5984 if (! rld[r].reg_rtx)
5986 regno = true_regnum (rld[r].reg_rtx);
5988 if (spill_reg_order[regno] >= 0)
5989 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5991 reload_spill_index[r] = -1;
5994 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5995 reloads of the same item for fear that we might not have enough reload
5996 registers. However, normally they will get the same reload register
5997 and hence actually need not be loaded twice.
5999 Here we check for the most common case of this phenomenon: when we have
6000 a number of reloads for the same object, each of which were allocated
6001 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6002 reload, and is not modified in the insn itself. If we find such,
6003 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6004 This will not increase the number of spill registers needed and will
6005 prevent redundant code. */
6008 merge_assigned_reloads (insn)
6013 /* Scan all the reloads looking for ones that only load values and
6014 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6015 assigned and not modified by INSN. */
6017 for (i = 0; i < n_reloads; i++)
6019 int conflicting_input = 0;
6020 int max_input_address_opnum = -1;
6021 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6023 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6024 || rld[i].out != 0 || rld[i].reg_rtx == 0
6025 || reg_set_p (rld[i].reg_rtx, insn))
6028 /* Look at all other reloads. Ensure that the only use of this
6029 reload_reg_rtx is in a reload that just loads the same value
6030 as we do. Note that any secondary reloads must be of the identical
6031 class since the values, modes, and result registers are the
6032 same, so we need not do anything with any secondary reloads. */
6034 for (j = 0; j < n_reloads; j++)
6036 if (i == j || rld[j].reg_rtx == 0
6037 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6041 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6042 && rld[j].opnum > max_input_address_opnum)
6043 max_input_address_opnum = rld[j].opnum;
6045 /* If the reload regs aren't exactly the same (e.g, different modes)
6046 or if the values are different, we can't merge this reload.
6047 But if it is an input reload, we might still merge
6048 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6050 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6051 || rld[j].out != 0 || rld[j].in == 0
6052 || ! rtx_equal_p (rld[i].in, rld[j].in))
6054 if (rld[j].when_needed != RELOAD_FOR_INPUT
6055 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6056 || rld[i].opnum > rld[j].opnum)
6057 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6059 conflicting_input = 1;
6060 if (min_conflicting_input_opnum > rld[j].opnum)
6061 min_conflicting_input_opnum = rld[j].opnum;
6065 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6066 we, in fact, found any matching reloads. */
6069 && max_input_address_opnum <= min_conflicting_input_opnum)
6071 for (j = 0; j < n_reloads; j++)
6072 if (i != j && rld[j].reg_rtx != 0
6073 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6074 && (! conflicting_input
6075 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6076 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6078 rld[i].when_needed = RELOAD_OTHER;
6080 reload_spill_index[j] = -1;
6081 transfer_replacements (i, j);
6084 /* If this is now RELOAD_OTHER, look for any reloads that load
6085 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6086 if they were for inputs, RELOAD_OTHER for outputs. Note that
6087 this test is equivalent to looking for reloads for this operand
6090 if (rld[i].when_needed == RELOAD_OTHER)
6091 for (j = 0; j < n_reloads; j++)
6093 && rld[j].when_needed != RELOAD_OTHER
6094 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6097 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6098 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6099 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6104 /* These arrays are filled by emit_reload_insns and its subroutines. */
6105 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6106 static rtx other_input_address_reload_insns = 0;
6107 static rtx other_input_reload_insns = 0;
6108 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6109 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6110 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6111 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6112 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6113 static rtx operand_reload_insns = 0;
6114 static rtx other_operand_reload_insns = 0;
6115 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6117 /* Values to be put in spill_reg_store are put here first. */
6118 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6119 static HARD_REG_SET reg_reloaded_died;
6121 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6122 has the number J. OLD contains the value to be used as input. */
6125 emit_input_reload_insns (chain, rl, old, j)
6126 struct insn_chain *chain;
6131 rtx insn = chain->insn;
6132 rtx reloadreg = rl->reg_rtx;
6133 rtx oldequiv_reg = 0;
6136 enum machine_mode mode;
6139 /* Determine the mode to reload in.
6140 This is very tricky because we have three to choose from.
6141 There is the mode the insn operand wants (rl->inmode).
6142 There is the mode of the reload register RELOADREG.
6143 There is the intrinsic mode of the operand, which we could find
6144 by stripping some SUBREGs.
6145 It turns out that RELOADREG's mode is irrelevant:
6146 we can change that arbitrarily.
6148 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6149 then the reload reg may not support QImode moves, so use SImode.
6150 If foo is in memory due to spilling a pseudo reg, this is safe,
6151 because the QImode value is in the least significant part of a
6152 slot big enough for a SImode. If foo is some other sort of
6153 memory reference, then it is impossible to reload this case,
6154 so previous passes had better make sure this never happens.
6156 Then consider a one-word union which has SImode and one of its
6157 members is a float, being fetched as (SUBREG:SF union:SI).
6158 We must fetch that as SFmode because we could be loading into
6159 a float-only register. In this case OLD's mode is correct.
6161 Consider an immediate integer: it has VOIDmode. Here we need
6162 to get a mode from something else.
6164 In some cases, there is a fourth mode, the operand's
6165 containing mode. If the insn specifies a containing mode for
6166 this operand, it overrides all others.
6168 I am not sure whether the algorithm here is always right,
6169 but it does the right things in those cases. */
6171 mode = GET_MODE (old);
6172 if (mode == VOIDmode)
6175 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6176 /* If we need a secondary register for this operation, see if
6177 the value is already in a register in that class. Don't
6178 do this if the secondary register will be used as a scratch
6181 if (rl->secondary_in_reload >= 0
6182 && rl->secondary_in_icode == CODE_FOR_nothing
6185 = find_equiv_reg (old, insn,
6186 rld[rl->secondary_in_reload].class,
6190 /* If reloading from memory, see if there is a register
6191 that already holds the same value. If so, reload from there.
6192 We can pass 0 as the reload_reg_p argument because
6193 any other reload has either already been emitted,
6194 in which case find_equiv_reg will see the reload-insn,
6195 or has yet to be emitted, in which case it doesn't matter
6196 because we will use this equiv reg right away. */
6198 if (oldequiv == 0 && optimize
6199 && (GET_CODE (old) == MEM
6200 || (GET_CODE (old) == REG
6201 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6202 && reg_renumber[REGNO (old)] < 0)))
6203 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6207 unsigned int regno = true_regnum (oldequiv);
6209 /* Don't use OLDEQUIV if any other reload changes it at an
6210 earlier stage of this insn or at this stage. */
6211 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6212 rl->in, const0_rtx, j, 0))
6215 /* If it is no cheaper to copy from OLDEQUIV into the
6216 reload register than it would be to move from memory,
6217 don't use it. Likewise, if we need a secondary register
6221 && ((REGNO_REG_CLASS (regno) != rl->class
6222 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6224 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6225 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6226 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6230 #ifdef SECONDARY_MEMORY_NEEDED
6231 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6239 /* delete_output_reload is only invoked properly if old contains
6240 the original pseudo register. Since this is replaced with a
6241 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6242 find the pseudo in RELOAD_IN_REG. */
6244 && reload_override_in[j]
6245 && GET_CODE (rl->in_reg) == REG)
6252 else if (GET_CODE (oldequiv) == REG)
6253 oldequiv_reg = oldequiv;
6254 else if (GET_CODE (oldequiv) == SUBREG)
6255 oldequiv_reg = SUBREG_REG (oldequiv);
6257 /* If we are reloading from a register that was recently stored in
6258 with an output-reload, see if we can prove there was
6259 actually no need to store the old value in it. */
6261 if (optimize && GET_CODE (oldequiv) == REG
6262 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6263 && spill_reg_store[REGNO (oldequiv)]
6264 && GET_CODE (old) == REG
6265 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6266 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6268 delete_output_reload (insn, j, REGNO (oldequiv));
6270 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6271 then load RELOADREG from OLDEQUIV. Note that we cannot use
6272 gen_lowpart_common since it can do the wrong thing when
6273 RELOADREG has a multi-word mode. Note that RELOADREG
6274 must always be a REG here. */
6276 if (GET_MODE (reloadreg) != mode)
6277 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6278 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6279 oldequiv = SUBREG_REG (oldequiv);
6280 if (GET_MODE (oldequiv) != VOIDmode
6281 && mode != GET_MODE (oldequiv))
6282 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6284 /* Switch to the right place to emit the reload insns. */
6285 switch (rl->when_needed)
6288 where = &other_input_reload_insns;
6290 case RELOAD_FOR_INPUT:
6291 where = &input_reload_insns[rl->opnum];
6293 case RELOAD_FOR_INPUT_ADDRESS:
6294 where = &input_address_reload_insns[rl->opnum];
6296 case RELOAD_FOR_INPADDR_ADDRESS:
6297 where = &inpaddr_address_reload_insns[rl->opnum];
6299 case RELOAD_FOR_OUTPUT_ADDRESS:
6300 where = &output_address_reload_insns[rl->opnum];
6302 case RELOAD_FOR_OUTADDR_ADDRESS:
6303 where = &outaddr_address_reload_insns[rl->opnum];
6305 case RELOAD_FOR_OPERAND_ADDRESS:
6306 where = &operand_reload_insns;
6308 case RELOAD_FOR_OPADDR_ADDR:
6309 where = &other_operand_reload_insns;
6311 case RELOAD_FOR_OTHER_ADDRESS:
6312 where = &other_input_address_reload_insns;
6318 push_to_sequence (*where);
6320 /* Auto-increment addresses must be reloaded in a special way. */
6321 if (rl->out && ! rl->out_reg)
6323 /* We are not going to bother supporting the case where a
6324 incremented register can't be copied directly from
6325 OLDEQUIV since this seems highly unlikely. */
6326 if (rl->secondary_in_reload >= 0)
6329 if (reload_inherited[j])
6330 oldequiv = reloadreg;
6332 old = XEXP (rl->in_reg, 0);
6334 if (optimize && GET_CODE (oldequiv) == REG
6335 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6336 && spill_reg_store[REGNO (oldequiv)]
6337 && GET_CODE (old) == REG
6338 && (dead_or_set_p (insn,
6339 spill_reg_stored_to[REGNO (oldequiv)])
6340 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6342 delete_output_reload (insn, j, REGNO (oldequiv));
6344 /* Prevent normal processing of this reload. */
6346 /* Output a special code sequence for this case. */
6347 new_spill_reg_store[REGNO (reloadreg)]
6348 = inc_for_reload (reloadreg, oldequiv, rl->out,
6352 /* If we are reloading a pseudo-register that was set by the previous
6353 insn, see if we can get rid of that pseudo-register entirely
6354 by redirecting the previous insn into our reload register. */
6356 else if (optimize && GET_CODE (old) == REG
6357 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6358 && dead_or_set_p (insn, old)
6359 /* This is unsafe if some other reload
6360 uses the same reg first. */
6361 && ! conflicts_with_override (reloadreg)
6362 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6363 rl->when_needed, old, rl->out, j, 0))
6365 rtx temp = PREV_INSN (insn);
6366 while (temp && GET_CODE (temp) == NOTE)
6367 temp = PREV_INSN (temp);
6369 && GET_CODE (temp) == INSN
6370 && GET_CODE (PATTERN (temp)) == SET
6371 && SET_DEST (PATTERN (temp)) == old
6372 /* Make sure we can access insn_operand_constraint. */
6373 && asm_noperands (PATTERN (temp)) < 0
6374 /* This is unsafe if prev insn rejects our reload reg. */
6375 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6377 /* This is unsafe if operand occurs more than once in current
6378 insn. Perhaps some occurrences aren't reloaded. */
6379 && count_occurrences (PATTERN (insn), old, 0) == 1
6380 /* Don't risk splitting a matching pair of operands. */
6381 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6383 /* Store into the reload register instead of the pseudo. */
6384 SET_DEST (PATTERN (temp)) = reloadreg;
6386 /* If the previous insn is an output reload, the source is
6387 a reload register, and its spill_reg_store entry will
6388 contain the previous destination. This is now
6390 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6391 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6393 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6394 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6397 /* If these are the only uses of the pseudo reg,
6398 pretend for GDB it lives in the reload reg we used. */
6399 if (REG_N_DEATHS (REGNO (old)) == 1
6400 && REG_N_SETS (REGNO (old)) == 1)
6402 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6403 alter_reg (REGNO (old), -1);
6409 /* We can't do that, so output an insn to load RELOADREG. */
6411 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6412 /* If we have a secondary reload, pick up the secondary register
6413 and icode, if any. If OLDEQUIV and OLD are different or
6414 if this is an in-out reload, recompute whether or not we
6415 still need a secondary register and what the icode should
6416 be. If we still need a secondary register and the class or
6417 icode is different, go back to reloading from OLD if using
6418 OLDEQUIV means that we got the wrong type of register. We
6419 cannot have different class or icode due to an in-out reload
6420 because we don't make such reloads when both the input and
6421 output need secondary reload registers. */
6423 if (! special && rl->secondary_in_reload >= 0)
6425 rtx second_reload_reg = 0;
6426 int secondary_reload = rl->secondary_in_reload;
6427 rtx real_oldequiv = oldequiv;
6430 enum insn_code icode;
6432 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6433 and similarly for OLD.
6434 See comments in get_secondary_reload in reload.c. */
6435 /* If it is a pseudo that cannot be replaced with its
6436 equivalent MEM, we must fall back to reload_in, which
6437 will have all the necessary substitutions registered.
6438 Likewise for a pseudo that can't be replaced with its
6439 equivalent constant.
6441 Take extra care for subregs of such pseudos. Note that
6442 we cannot use reg_equiv_mem in this case because it is
6443 not in the right mode. */
6446 if (GET_CODE (tmp) == SUBREG)
6447 tmp = SUBREG_REG (tmp);
6448 if (GET_CODE (tmp) == REG
6449 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6450 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6451 || reg_equiv_constant[REGNO (tmp)] != 0))
6453 if (! reg_equiv_mem[REGNO (tmp)]
6454 || num_not_at_initial_offset
6455 || GET_CODE (oldequiv) == SUBREG)
6456 real_oldequiv = rl->in;
6458 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6462 if (GET_CODE (tmp) == SUBREG)
6463 tmp = SUBREG_REG (tmp);
6464 if (GET_CODE (tmp) == REG
6465 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6466 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6467 || reg_equiv_constant[REGNO (tmp)] != 0))
6469 if (! reg_equiv_mem[REGNO (tmp)]
6470 || num_not_at_initial_offset
6471 || GET_CODE (old) == SUBREG)
6474 real_old = reg_equiv_mem[REGNO (tmp)];
6477 second_reload_reg = rld[secondary_reload].reg_rtx;
6478 icode = rl->secondary_in_icode;
6480 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6481 || (rl->in != 0 && rl->out != 0))
6483 enum reg_class new_class
6484 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6485 mode, real_oldequiv);
6487 if (new_class == NO_REGS)
6488 second_reload_reg = 0;
6491 enum insn_code new_icode;
6492 enum machine_mode new_mode;
6494 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6495 REGNO (second_reload_reg)))
6496 oldequiv = old, real_oldequiv = real_old;
6499 new_icode = reload_in_optab[(int) mode];
6500 if (new_icode != CODE_FOR_nothing
6501 && ((insn_data[(int) new_icode].operand[0].predicate
6502 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6504 || (insn_data[(int) new_icode].operand[1].predicate
6505 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6506 (real_oldequiv, mode)))))
6507 new_icode = CODE_FOR_nothing;
6509 if (new_icode == CODE_FOR_nothing)
6512 new_mode = insn_data[(int) new_icode].operand[2].mode;
6514 if (GET_MODE (second_reload_reg) != new_mode)
6516 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6518 oldequiv = old, real_oldequiv = real_old;
6521 = gen_rtx_REG (new_mode,
6522 REGNO (second_reload_reg));
6528 /* If we still need a secondary reload register, check
6529 to see if it is being used as a scratch or intermediate
6530 register and generate code appropriately. If we need
6531 a scratch register, use REAL_OLDEQUIV since the form of
6532 the insn may depend on the actual address if it is
6535 if (second_reload_reg)
6537 if (icode != CODE_FOR_nothing)
6539 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6540 second_reload_reg));
6545 /* See if we need a scratch register to load the
6546 intermediate register (a tertiary reload). */
6547 enum insn_code tertiary_icode
6548 = rld[secondary_reload].secondary_in_icode;
6550 if (tertiary_icode != CODE_FOR_nothing)
6552 rtx third_reload_reg
6553 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6555 emit_insn ((GEN_FCN (tertiary_icode)
6556 (second_reload_reg, real_oldequiv,
6557 third_reload_reg)));
6560 gen_reload (second_reload_reg, real_oldequiv,
6564 oldequiv = second_reload_reg;
6570 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6572 rtx real_oldequiv = oldequiv;
6574 if ((GET_CODE (oldequiv) == REG
6575 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6576 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6577 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6578 || (GET_CODE (oldequiv) == SUBREG
6579 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6580 && (REGNO (SUBREG_REG (oldequiv))
6581 >= FIRST_PSEUDO_REGISTER)
6582 && ((reg_equiv_memory_loc
6583 [REGNO (SUBREG_REG (oldequiv))] != 0)
6584 || (reg_equiv_constant
6585 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6586 || (CONSTANT_P (oldequiv)
6587 && (PREFERRED_RELOAD_CLASS (oldequiv,
6588 REGNO_REG_CLASS (REGNO (reloadreg)))
6590 real_oldequiv = rl->in;
6591 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6595 if (flag_non_call_exceptions)
6596 copy_eh_notes (insn, get_insns ());
6598 /* End this sequence. */
6599 *where = get_insns ();
6602 /* Update reload_override_in so that delete_address_reloads_1
6603 can see the actual register usage. */
6605 reload_override_in[j] = oldequiv;
6608 /* Generate insns to for the output reload RL, which is for the insn described
6609 by CHAIN and has the number J. */
6611 emit_output_reload_insns (chain, rl, j)
6612 struct insn_chain *chain;
6616 rtx reloadreg = rl->reg_rtx;
6617 rtx insn = chain->insn;
6620 enum machine_mode mode = GET_MODE (old);
6623 if (rl->when_needed == RELOAD_OTHER)
6626 push_to_sequence (output_reload_insns[rl->opnum]);
6628 /* Determine the mode to reload in.
6629 See comments above (for input reloading). */
6631 if (mode == VOIDmode)
6633 /* VOIDmode should never happen for an output. */
6634 if (asm_noperands (PATTERN (insn)) < 0)
6635 /* It's the compiler's fault. */
6636 fatal_insn ("VOIDmode on an output", insn);
6637 error_for_asm (insn, "output operand is constant in `asm'");
6638 /* Prevent crash--use something we know is valid. */
6640 old = gen_rtx_REG (mode, REGNO (reloadreg));
6643 if (GET_MODE (reloadreg) != mode)
6644 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6646 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6648 /* If we need two reload regs, set RELOADREG to the intermediate
6649 one, since it will be stored into OLD. We might need a secondary
6650 register only for an input reload, so check again here. */
6652 if (rl->secondary_out_reload >= 0)
6656 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6657 && reg_equiv_mem[REGNO (old)] != 0)
6658 real_old = reg_equiv_mem[REGNO (old)];
6660 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6664 rtx second_reloadreg = reloadreg;
6665 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6667 /* See if RELOADREG is to be used as a scratch register
6668 or as an intermediate register. */
6669 if (rl->secondary_out_icode != CODE_FOR_nothing)
6671 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6672 (real_old, second_reloadreg, reloadreg)));
6677 /* See if we need both a scratch and intermediate reload
6680 int secondary_reload = rl->secondary_out_reload;
6681 enum insn_code tertiary_icode
6682 = rld[secondary_reload].secondary_out_icode;
6684 if (GET_MODE (reloadreg) != mode)
6685 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6687 if (tertiary_icode != CODE_FOR_nothing)
6690 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6693 /* Copy primary reload reg to secondary reload reg.
6694 (Note that these have been swapped above, then
6695 secondary reload reg to OLD using our insn.) */
6697 /* If REAL_OLD is a paradoxical SUBREG, remove it
6698 and try to put the opposite SUBREG on
6700 if (GET_CODE (real_old) == SUBREG
6701 && (GET_MODE_SIZE (GET_MODE (real_old))
6702 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6703 && 0 != (tem = gen_lowpart_common
6704 (GET_MODE (SUBREG_REG (real_old)),
6706 real_old = SUBREG_REG (real_old), reloadreg = tem;
6708 gen_reload (reloadreg, second_reloadreg,
6709 rl->opnum, rl->when_needed);
6710 emit_insn ((GEN_FCN (tertiary_icode)
6711 (real_old, reloadreg, third_reloadreg)));
6716 /* Copy between the reload regs here and then to
6719 gen_reload (reloadreg, second_reloadreg,
6720 rl->opnum, rl->when_needed);
6726 /* Output the last reload insn. */
6731 /* Don't output the last reload if OLD is not the dest of
6732 INSN and is in the src and is clobbered by INSN. */
6733 if (! flag_expensive_optimizations
6734 || GET_CODE (old) != REG
6735 || !(set = single_set (insn))
6736 || rtx_equal_p (old, SET_DEST (set))
6737 || !reg_mentioned_p (old, SET_SRC (set))
6738 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6739 gen_reload (old, reloadreg, rl->opnum,
6743 /* Look at all insns we emitted, just to be safe. */
6744 for (p = get_insns (); p; p = NEXT_INSN (p))
6747 rtx pat = PATTERN (p);
6749 /* If this output reload doesn't come from a spill reg,
6750 clear any memory of reloaded copies of the pseudo reg.
6751 If this output reload comes from a spill reg,
6752 reg_has_output_reload will make this do nothing. */
6753 note_stores (pat, forget_old_reloads_1, NULL);
6755 if (reg_mentioned_p (rl->reg_rtx, pat))
6757 rtx set = single_set (insn);
6758 if (reload_spill_index[j] < 0
6760 && SET_SRC (set) == rl->reg_rtx)
6762 int src = REGNO (SET_SRC (set));
6764 reload_spill_index[j] = src;
6765 SET_HARD_REG_BIT (reg_is_output_reload, src);
6766 if (find_regno_note (insn, REG_DEAD, src))
6767 SET_HARD_REG_BIT (reg_reloaded_died, src);
6769 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6771 int s = rl->secondary_out_reload;
6772 set = single_set (p);
6773 /* If this reload copies only to the secondary reload
6774 register, the secondary reload does the actual
6776 if (s >= 0 && set == NULL_RTX)
6777 /* We can't tell what function the secondary reload
6778 has and where the actual store to the pseudo is
6779 made; leave new_spill_reg_store alone. */
6782 && SET_SRC (set) == rl->reg_rtx
6783 && SET_DEST (set) == rld[s].reg_rtx)
6785 /* Usually the next instruction will be the
6786 secondary reload insn; if we can confirm
6787 that it is, setting new_spill_reg_store to
6788 that insn will allow an extra optimization. */
6789 rtx s_reg = rld[s].reg_rtx;
6790 rtx next = NEXT_INSN (p);
6791 rld[s].out = rl->out;
6792 rld[s].out_reg = rl->out_reg;
6793 set = single_set (next);
6794 if (set && SET_SRC (set) == s_reg
6795 && ! new_spill_reg_store[REGNO (s_reg)])
6797 SET_HARD_REG_BIT (reg_is_output_reload,
6799 new_spill_reg_store[REGNO (s_reg)] = next;
6803 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6808 if (rl->when_needed == RELOAD_OTHER)
6810 emit_insns (other_output_reload_insns[rl->opnum]);
6811 other_output_reload_insns[rl->opnum] = get_insns ();
6814 output_reload_insns[rl->opnum] = get_insns ();
6816 if (flag_non_call_exceptions)
6817 copy_eh_notes (insn, get_insns ());
6822 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6823 and has the number J. */
6825 do_input_reload (chain, rl, j)
6826 struct insn_chain *chain;
6830 int expect_occurrences = 1;
6831 rtx insn = chain->insn;
6832 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6833 ? rl->in_reg : rl->in);
6836 /* AUTO_INC reloads need to be handled even if inherited. We got an
6837 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6838 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6839 && ! rtx_equal_p (rl->reg_rtx, old)
6840 && rl->reg_rtx != 0)
6841 emit_input_reload_insns (chain, rld + j, old, j);
6843 /* When inheriting a wider reload, we have a MEM in rl->in,
6844 e.g. inheriting a SImode output reload for
6845 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6846 if (optimize && reload_inherited[j] && rl->in
6847 && GET_CODE (rl->in) == MEM
6848 && GET_CODE (rl->in_reg) == MEM
6849 && reload_spill_index[j] >= 0
6850 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6853 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6854 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6857 /* If we are reloading a register that was recently stored in with an
6858 output-reload, see if we can prove there was
6859 actually no need to store the old value in it. */
6862 && (reload_inherited[j] || reload_override_in[j])
6864 && GET_CODE (rl->reg_rtx) == REG
6865 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6867 /* There doesn't seem to be any reason to restrict this to pseudos
6868 and doing so loses in the case where we are copying from a
6869 register of the wrong class. */
6870 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6871 >= FIRST_PSEUDO_REGISTER)
6873 /* The insn might have already some references to stackslots
6874 replaced by MEMs, while reload_out_reg still names the
6876 && (dead_or_set_p (insn,
6877 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6878 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6880 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6883 /* Do output reloading for reload RL, which is for the insn described by
6884 CHAIN and has the number J.
6885 ??? At some point we need to support handling output reloads of
6886 JUMP_INSNs or insns that set cc0. */
6888 do_output_reload (chain, rl, j)
6889 struct insn_chain *chain;
6894 rtx insn = chain->insn;
6895 /* If this is an output reload that stores something that is
6896 not loaded in this same reload, see if we can eliminate a previous
6898 rtx pseudo = rl->out_reg;
6901 && GET_CODE (pseudo) == REG
6902 && ! rtx_equal_p (rl->in_reg, pseudo)
6903 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6904 && reg_last_reload_reg[REGNO (pseudo)])
6906 int pseudo_no = REGNO (pseudo);
6907 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6909 /* We don't need to test full validity of last_regno for
6910 inherit here; we only want to know if the store actually
6911 matches the pseudo. */
6912 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6913 && reg_reloaded_contents[last_regno] == pseudo_no
6914 && spill_reg_store[last_regno]
6915 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6916 delete_output_reload (insn, j, last_regno);
6921 || rl->reg_rtx == old
6922 || rl->reg_rtx == 0)
6925 /* An output operand that dies right away does need a reload,
6926 but need not be copied from it. Show the new location in the
6928 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6929 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6931 XEXP (note, 0) = rl->reg_rtx;
6934 /* Likewise for a SUBREG of an operand that dies. */
6935 else if (GET_CODE (old) == SUBREG
6936 && GET_CODE (SUBREG_REG (old)) == REG
6937 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6940 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6944 else if (GET_CODE (old) == SCRATCH)
6945 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6946 but we don't want to make an output reload. */
6949 /* If is a JUMP_INSN, we can't support output reloads yet. */
6950 if (GET_CODE (insn) == JUMP_INSN)
6953 emit_output_reload_insns (chain, rld + j, j);
6956 /* Output insns to reload values in and out of the chosen reload regs. */
6959 emit_reload_insns (chain)
6960 struct insn_chain *chain;
6962 rtx insn = chain->insn;
6966 CLEAR_HARD_REG_SET (reg_reloaded_died);
6968 for (j = 0; j < reload_n_operands; j++)
6969 input_reload_insns[j] = input_address_reload_insns[j]
6970 = inpaddr_address_reload_insns[j]
6971 = output_reload_insns[j] = output_address_reload_insns[j]
6972 = outaddr_address_reload_insns[j]
6973 = other_output_reload_insns[j] = 0;
6974 other_input_address_reload_insns = 0;
6975 other_input_reload_insns = 0;
6976 operand_reload_insns = 0;
6977 other_operand_reload_insns = 0;
6979 /* Dump reloads into the dump file. */
6982 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6983 debug_reload_to_stream (rtl_dump_file);
6986 /* Now output the instructions to copy the data into and out of the
6987 reload registers. Do these in the order that the reloads were reported,
6988 since reloads of base and index registers precede reloads of operands
6989 and the operands may need the base and index registers reloaded. */
6991 for (j = 0; j < n_reloads; j++)
6994 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6995 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6997 do_input_reload (chain, rld + j, j);
6998 do_output_reload (chain, rld + j, j);
7001 /* Now write all the insns we made for reloads in the order expected by
7002 the allocation functions. Prior to the insn being reloaded, we write
7003 the following reloads:
7005 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7007 RELOAD_OTHER reloads.
7009 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7010 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7011 RELOAD_FOR_INPUT reload for the operand.
7013 RELOAD_FOR_OPADDR_ADDRS reloads.
7015 RELOAD_FOR_OPERAND_ADDRESS reloads.
7017 After the insn being reloaded, we write the following:
7019 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7020 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7021 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7022 reloads for the operand. The RELOAD_OTHER output reloads are
7023 output in descending order by reload number. */
7025 emit_insns_before (other_input_address_reload_insns, insn);
7026 emit_insns_before (other_input_reload_insns, insn);
7028 for (j = 0; j < reload_n_operands; j++)
7030 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7031 emit_insns_before (input_address_reload_insns[j], insn);
7032 emit_insns_before (input_reload_insns[j], insn);
7035 emit_insns_before (other_operand_reload_insns, insn);
7036 emit_insns_before (operand_reload_insns, insn);
7038 for (j = 0; j < reload_n_operands; j++)
7040 rtx x = emit_insns_after (outaddr_address_reload_insns[j], insn);
7041 x = emit_insns_after (output_address_reload_insns[j], x);
7042 x = emit_insns_after (output_reload_insns[j], x);
7043 emit_insns_after (other_output_reload_insns[j], x);
7046 /* For all the spill regs newly reloaded in this instruction,
7047 record what they were reloaded from, so subsequent instructions
7048 can inherit the reloads.
7050 Update spill_reg_store for the reloads of this insn.
7051 Copy the elements that were updated in the loop above. */
7053 for (j = 0; j < n_reloads; j++)
7055 int r = reload_order[j];
7056 int i = reload_spill_index[r];
7058 /* If this is a non-inherited input reload from a pseudo, we must
7059 clear any memory of a previous store to the same pseudo. Only do
7060 something if there will not be an output reload for the pseudo
7062 if (rld[r].in_reg != 0
7063 && ! (reload_inherited[r] || reload_override_in[r]))
7065 rtx reg = rld[r].in_reg;
7067 if (GET_CODE (reg) == SUBREG)
7068 reg = SUBREG_REG (reg);
7070 if (GET_CODE (reg) == REG
7071 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7072 && ! reg_has_output_reload[REGNO (reg)])
7074 int nregno = REGNO (reg);
7076 if (reg_last_reload_reg[nregno])
7078 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7080 if (reg_reloaded_contents[last_regno] == nregno)
7081 spill_reg_store[last_regno] = 0;
7086 /* I is nonneg if this reload used a register.
7087 If rld[r].reg_rtx is 0, this is an optional reload
7088 that we opted to ignore. */
7090 if (i >= 0 && rld[r].reg_rtx != 0)
7092 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7094 int part_reaches_end = 0;
7095 int all_reaches_end = 1;
7097 /* For a multi register reload, we need to check if all or part
7098 of the value lives to the end. */
7099 for (k = 0; k < nr; k++)
7101 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7102 rld[r].when_needed))
7103 part_reaches_end = 1;
7105 all_reaches_end = 0;
7108 /* Ignore reloads that don't reach the end of the insn in
7110 if (all_reaches_end)
7112 /* First, clear out memory of what used to be in this spill reg.
7113 If consecutive registers are used, clear them all. */
7115 for (k = 0; k < nr; k++)
7116 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7118 /* Maybe the spill reg contains a copy of reload_out. */
7120 && (GET_CODE (rld[r].out) == REG
7124 || GET_CODE (rld[r].out_reg) == REG))
7126 rtx out = (GET_CODE (rld[r].out) == REG
7130 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7131 int nregno = REGNO (out);
7132 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7133 : HARD_REGNO_NREGS (nregno,
7134 GET_MODE (rld[r].reg_rtx)));
7136 spill_reg_store[i] = new_spill_reg_store[i];
7137 spill_reg_stored_to[i] = out;
7138 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7140 /* If NREGNO is a hard register, it may occupy more than
7141 one register. If it does, say what is in the
7142 rest of the registers assuming that both registers
7143 agree on how many words the object takes. If not,
7144 invalidate the subsequent registers. */
7146 if (nregno < FIRST_PSEUDO_REGISTER)
7147 for (k = 1; k < nnr; k++)
7148 reg_last_reload_reg[nregno + k]
7150 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7151 REGNO (rld[r].reg_rtx) + k)
7154 /* Now do the inverse operation. */
7155 for (k = 0; k < nr; k++)
7157 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7158 reg_reloaded_contents[i + k]
7159 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7162 reg_reloaded_insn[i + k] = insn;
7163 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7167 /* Maybe the spill reg contains a copy of reload_in. Only do
7168 something if there will not be an output reload for
7169 the register being reloaded. */
7170 else if (rld[r].out_reg == 0
7172 && ((GET_CODE (rld[r].in) == REG
7173 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7174 && ! reg_has_output_reload[REGNO (rld[r].in)])
7175 || (GET_CODE (rld[r].in_reg) == REG
7176 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7177 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7182 if (GET_CODE (rld[r].in) == REG
7183 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7184 nregno = REGNO (rld[r].in);
7185 else if (GET_CODE (rld[r].in_reg) == REG)
7186 nregno = REGNO (rld[r].in_reg);
7188 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7190 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7191 : HARD_REGNO_NREGS (nregno,
7192 GET_MODE (rld[r].reg_rtx)));
7194 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7196 if (nregno < FIRST_PSEUDO_REGISTER)
7197 for (k = 1; k < nnr; k++)
7198 reg_last_reload_reg[nregno + k]
7200 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7201 REGNO (rld[r].reg_rtx) + k)
7204 /* Unless we inherited this reload, show we haven't
7205 recently done a store.
7206 Previous stores of inherited auto_inc expressions
7207 also have to be discarded. */
7208 if (! reload_inherited[r]
7209 || (rld[r].out && ! rld[r].out_reg))
7210 spill_reg_store[i] = 0;
7212 for (k = 0; k < nr; k++)
7214 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7215 reg_reloaded_contents[i + k]
7216 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7219 reg_reloaded_insn[i + k] = insn;
7220 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7225 /* However, if part of the reload reaches the end, then we must
7226 invalidate the old info for the part that survives to the end. */
7227 else if (part_reaches_end)
7229 for (k = 0; k < nr; k++)
7230 if (reload_reg_reaches_end_p (i + k,
7232 rld[r].when_needed))
7233 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7237 /* The following if-statement was #if 0'd in 1.34 (or before...).
7238 It's reenabled in 1.35 because supposedly nothing else
7239 deals with this problem. */
7241 /* If a register gets output-reloaded from a non-spill register,
7242 that invalidates any previous reloaded copy of it.
7243 But forget_old_reloads_1 won't get to see it, because
7244 it thinks only about the original insn. So invalidate it here. */
7245 if (i < 0 && rld[r].out != 0
7246 && (GET_CODE (rld[r].out) == REG
7247 || (GET_CODE (rld[r].out) == MEM
7248 && GET_CODE (rld[r].out_reg) == REG)))
7250 rtx out = (GET_CODE (rld[r].out) == REG
7251 ? rld[r].out : rld[r].out_reg);
7252 int nregno = REGNO (out);
7253 if (nregno >= FIRST_PSEUDO_REGISTER)
7255 rtx src_reg, store_insn = NULL_RTX;
7257 reg_last_reload_reg[nregno] = 0;
7259 /* If we can find a hard register that is stored, record
7260 the storing insn so that we may delete this insn with
7261 delete_output_reload. */
7262 src_reg = rld[r].reg_rtx;
7264 /* If this is an optional reload, try to find the source reg
7265 from an input reload. */
7268 rtx set = single_set (insn);
7269 if (set && SET_DEST (set) == rld[r].out)
7273 src_reg = SET_SRC (set);
7275 for (k = 0; k < n_reloads; k++)
7277 if (rld[k].in == src_reg)
7279 src_reg = rld[k].reg_rtx;
7286 store_insn = new_spill_reg_store[REGNO (src_reg)];
7287 if (src_reg && GET_CODE (src_reg) == REG
7288 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7290 int src_regno = REGNO (src_reg);
7291 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7292 /* The place where to find a death note varies with
7293 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7294 necessarily checked exactly in the code that moves
7295 notes, so just check both locations. */
7296 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7297 if (! note && store_insn)
7298 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7301 spill_reg_store[src_regno + nr] = store_insn;
7302 spill_reg_stored_to[src_regno + nr] = out;
7303 reg_reloaded_contents[src_regno + nr] = nregno;
7304 reg_reloaded_insn[src_regno + nr] = store_insn;
7305 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7306 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7307 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7309 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7311 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7313 reg_last_reload_reg[nregno] = src_reg;
7318 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7320 while (num_regs-- > 0)
7321 reg_last_reload_reg[nregno + num_regs] = 0;
7325 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7328 /* Emit code to perform a reload from IN (which may be a reload register) to
7329 OUT (which may also be a reload register). IN or OUT is from operand
7330 OPNUM with reload type TYPE.
7332 Returns first insn emitted. */
7335 gen_reload (out, in, opnum, type)
7339 enum reload_type type;
7341 rtx last = get_last_insn ();
7344 /* If IN is a paradoxical SUBREG, remove it and try to put the
7345 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7346 if (GET_CODE (in) == SUBREG
7347 && (GET_MODE_SIZE (GET_MODE (in))
7348 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7349 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7350 in = SUBREG_REG (in), out = tem;
7351 else if (GET_CODE (out) == SUBREG
7352 && (GET_MODE_SIZE (GET_MODE (out))
7353 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7354 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7355 out = SUBREG_REG (out), in = tem;
7357 /* How to do this reload can get quite tricky. Normally, we are being
7358 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7359 register that didn't get a hard register. In that case we can just
7360 call emit_move_insn.
7362 We can also be asked to reload a PLUS that adds a register or a MEM to
7363 another register, constant or MEM. This can occur during frame pointer
7364 elimination and while reloading addresses. This case is handled by
7365 trying to emit a single insn to perform the add. If it is not valid,
7366 we use a two insn sequence.
7368 Finally, we could be called to handle an 'o' constraint by putting
7369 an address into a register. In that case, we first try to do this
7370 with a named pattern of "reload_load_address". If no such pattern
7371 exists, we just emit a SET insn and hope for the best (it will normally
7372 be valid on machines that use 'o').
7374 This entire process is made complex because reload will never
7375 process the insns we generate here and so we must ensure that
7376 they will fit their constraints and also by the fact that parts of
7377 IN might be being reloaded separately and replaced with spill registers.
7378 Because of this, we are, in some sense, just guessing the right approach
7379 here. The one listed above seems to work.
7381 ??? At some point, this whole thing needs to be rethought. */
7383 if (GET_CODE (in) == PLUS
7384 && (GET_CODE (XEXP (in, 0)) == REG
7385 || GET_CODE (XEXP (in, 0)) == SUBREG
7386 || GET_CODE (XEXP (in, 0)) == MEM)
7387 && (GET_CODE (XEXP (in, 1)) == REG
7388 || GET_CODE (XEXP (in, 1)) == SUBREG
7389 || CONSTANT_P (XEXP (in, 1))
7390 || GET_CODE (XEXP (in, 1)) == MEM))
7392 /* We need to compute the sum of a register or a MEM and another
7393 register, constant, or MEM, and put it into the reload
7394 register. The best possible way of doing this is if the machine
7395 has a three-operand ADD insn that accepts the required operands.
7397 The simplest approach is to try to generate such an insn and see if it
7398 is recognized and matches its constraints. If so, it can be used.
7400 It might be better not to actually emit the insn unless it is valid,
7401 but we need to pass the insn as an operand to `recog' and
7402 `extract_insn' and it is simpler to emit and then delete the insn if
7403 not valid than to dummy things up. */
7405 rtx op0, op1, tem, insn;
7408 op0 = find_replacement (&XEXP (in, 0));
7409 op1 = find_replacement (&XEXP (in, 1));
7411 /* Since constraint checking is strict, commutativity won't be
7412 checked, so we need to do that here to avoid spurious failure
7413 if the add instruction is two-address and the second operand
7414 of the add is the same as the reload reg, which is frequently
7415 the case. If the insn would be A = B + A, rearrange it so
7416 it will be A = A + B as constrain_operands expects. */
7418 if (GET_CODE (XEXP (in, 1)) == REG
7419 && REGNO (out) == REGNO (XEXP (in, 1)))
7420 tem = op0, op0 = op1, op1 = tem;
7422 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7423 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7425 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7426 code = recog_memoized (insn);
7430 extract_insn (insn);
7431 /* We want constrain operands to treat this insn strictly in
7432 its validity determination, i.e., the way it would after reload
7434 if (constrain_operands (1))
7438 delete_insns_since (last);
7440 /* If that failed, we must use a conservative two-insn sequence.
7442 Use a move to copy one operand into the reload register. Prefer
7443 to reload a constant, MEM or pseudo since the move patterns can
7444 handle an arbitrary operand. If OP1 is not a constant, MEM or
7445 pseudo and OP1 is not a valid operand for an add instruction, then
7448 After reloading one of the operands into the reload register, add
7449 the reload register to the output register.
7451 If there is another way to do this for a specific machine, a
7452 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7455 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7457 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7458 || (GET_CODE (op1) == REG
7459 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7460 || (code != CODE_FOR_nothing
7461 && ! ((*insn_data[code].operand[2].predicate)
7462 (op1, insn_data[code].operand[2].mode))))
7463 tem = op0, op0 = op1, op1 = tem;
7465 gen_reload (out, op0, opnum, type);
7467 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7468 This fixes a problem on the 32K where the stack pointer cannot
7469 be used as an operand of an add insn. */
7471 if (rtx_equal_p (op0, op1))
7474 insn = emit_insn (gen_add2_insn (out, op1));
7476 /* If that failed, copy the address register to the reload register.
7477 Then add the constant to the reload register. */
7479 code = recog_memoized (insn);
7483 extract_insn (insn);
7484 /* We want constrain operands to treat this insn strictly in
7485 its validity determination, i.e., the way it would after reload
7487 if (constrain_operands (1))
7489 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7491 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7496 delete_insns_since (last);
7498 gen_reload (out, op1, opnum, type);
7499 insn = emit_insn (gen_add2_insn (out, op0));
7500 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7503 #ifdef SECONDARY_MEMORY_NEEDED
7504 /* If we need a memory location to do the move, do it that way. */
7505 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7506 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7507 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7508 REGNO_REG_CLASS (REGNO (out)),
7511 /* Get the memory to use and rewrite both registers to its mode. */
7512 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7514 if (GET_MODE (loc) != GET_MODE (out))
7515 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7517 if (GET_MODE (loc) != GET_MODE (in))
7518 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7520 gen_reload (loc, in, opnum, type);
7521 gen_reload (out, loc, opnum, type);
7525 /* If IN is a simple operand, use gen_move_insn. */
7526 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7527 emit_insn (gen_move_insn (out, in));
7529 #ifdef HAVE_reload_load_address
7530 else if (HAVE_reload_load_address)
7531 emit_insn (gen_reload_load_address (out, in));
7534 /* Otherwise, just write (set OUT IN) and hope for the best. */
7536 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7538 /* Return the first insn emitted.
7539 We can not just return get_last_insn, because there may have
7540 been multiple instructions emitted. Also note that gen_move_insn may
7541 emit more than one insn itself, so we can not assume that there is one
7542 insn emitted per emit_insn_before call. */
7544 return last ? NEXT_INSN (last) : get_insns ();
7547 /* Delete a previously made output-reload whose result we now believe
7548 is not needed. First we double-check.
7550 INSN is the insn now being processed.
7551 LAST_RELOAD_REG is the hard register number for which we want to delete
7552 the last output reload.
7553 J is the reload-number that originally used REG. The caller has made
7554 certain that reload J doesn't use REG any longer for input. */
7557 delete_output_reload (insn, j, last_reload_reg)
7560 int last_reload_reg;
7562 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7563 rtx reg = spill_reg_stored_to[last_reload_reg];
7566 int n_inherited = 0;
7570 /* Get the raw pseudo-register referred to. */
7572 while (GET_CODE (reg) == SUBREG)
7573 reg = SUBREG_REG (reg);
7574 substed = reg_equiv_memory_loc[REGNO (reg)];
7576 /* This is unsafe if the operand occurs more often in the current
7577 insn than it is inherited. */
7578 for (k = n_reloads - 1; k >= 0; k--)
7580 rtx reg2 = rld[k].in;
7583 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7584 reg2 = rld[k].in_reg;
7586 if (rld[k].out && ! rld[k].out_reg)
7587 reg2 = XEXP (rld[k].in_reg, 0);
7589 while (GET_CODE (reg2) == SUBREG)
7590 reg2 = SUBREG_REG (reg2);
7591 if (rtx_equal_p (reg2, reg))
7593 if (reload_inherited[k] || reload_override_in[k] || k == j)
7596 reg2 = rld[k].out_reg;
7599 while (GET_CODE (reg2) == SUBREG)
7600 reg2 = XEXP (reg2, 0);
7601 if (rtx_equal_p (reg2, reg))
7608 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7610 n_occurrences += count_occurrences (PATTERN (insn),
7611 eliminate_regs (substed, 0,
7613 if (n_occurrences > n_inherited)
7616 /* If the pseudo-reg we are reloading is no longer referenced
7617 anywhere between the store into it and here,
7618 and no jumps or labels intervene, then the value can get
7619 here through the reload reg alone.
7620 Otherwise, give up--return. */
7621 for (i1 = NEXT_INSN (output_reload_insn);
7622 i1 != insn; i1 = NEXT_INSN (i1))
7624 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7626 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7627 && reg_mentioned_p (reg, PATTERN (i1)))
7629 /* If this is USE in front of INSN, we only have to check that
7630 there are no more references than accounted for by inheritance. */
7631 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7633 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7634 i1 = NEXT_INSN (i1);
7636 if (n_occurrences <= n_inherited && i1 == insn)
7642 /* We will be deleting the insn. Remove the spill reg information. */
7643 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7645 spill_reg_store[last_reload_reg + k] = 0;
7646 spill_reg_stored_to[last_reload_reg + k] = 0;
7649 /* The caller has already checked that REG dies or is set in INSN.
7650 It has also checked that we are optimizing, and thus some
7651 inaccurancies in the debugging information are acceptable.
7652 So we could just delete output_reload_insn. But in some cases
7653 we can improve the debugging information without sacrificing
7654 optimization - maybe even improving the code: See if the pseudo
7655 reg has been completely replaced with reload regs. If so, delete
7656 the store insn and forget we had a stack slot for the pseudo. */
7657 if (rld[j].out != rld[j].in
7658 && REG_N_DEATHS (REGNO (reg)) == 1
7659 && REG_N_SETS (REGNO (reg)) == 1
7660 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7661 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7665 /* We know that it was used only between here and the beginning of
7666 the current basic block. (We also know that the last use before
7667 INSN was the output reload we are thinking of deleting, but never
7668 mind that.) Search that range; see if any ref remains. */
7669 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7671 rtx set = single_set (i2);
7673 /* Uses which just store in the pseudo don't count,
7674 since if they are the only uses, they are dead. */
7675 if (set != 0 && SET_DEST (set) == reg)
7677 if (GET_CODE (i2) == CODE_LABEL
7678 || GET_CODE (i2) == JUMP_INSN)
7680 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7681 && reg_mentioned_p (reg, PATTERN (i2)))
7683 /* Some other ref remains; just delete the output reload we
7685 delete_address_reloads (output_reload_insn, insn);
7686 delete_insn (output_reload_insn);
7691 /* Delete the now-dead stores into this pseudo. Note that this
7692 loop also takes care of deleting output_reload_insn. */
7693 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7695 rtx set = single_set (i2);
7697 if (set != 0 && SET_DEST (set) == reg)
7699 delete_address_reloads (i2, insn);
7702 if (GET_CODE (i2) == CODE_LABEL
7703 || GET_CODE (i2) == JUMP_INSN)
7707 /* For the debugging info, say the pseudo lives in this reload reg. */
7708 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7709 alter_reg (REGNO (reg), -1);
7713 delete_address_reloads (output_reload_insn, insn);
7714 delete_insn (output_reload_insn);
7718 /* We are going to delete DEAD_INSN. Recursively delete loads of
7719 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7720 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7722 delete_address_reloads (dead_insn, current_insn)
7723 rtx dead_insn, current_insn;
7725 rtx set = single_set (dead_insn);
7726 rtx set2, dst, prev, next;
7729 rtx dst = SET_DEST (set);
7730 if (GET_CODE (dst) == MEM)
7731 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7733 /* If we deleted the store from a reloaded post_{in,de}c expression,
7734 we can delete the matching adds. */
7735 prev = PREV_INSN (dead_insn);
7736 next = NEXT_INSN (dead_insn);
7737 if (! prev || ! next)
7739 set = single_set (next);
7740 set2 = single_set (prev);
7742 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7743 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7744 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7746 dst = SET_DEST (set);
7747 if (! rtx_equal_p (dst, SET_DEST (set2))
7748 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7749 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7750 || (INTVAL (XEXP (SET_SRC (set), 1))
7751 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7753 delete_related_insns (prev);
7754 delete_related_insns (next);
7757 /* Subfunction of delete_address_reloads: process registers found in X. */
7759 delete_address_reloads_1 (dead_insn, x, current_insn)
7760 rtx dead_insn, x, current_insn;
7762 rtx prev, set, dst, i2;
7764 enum rtx_code code = GET_CODE (x);
7768 const char *fmt = GET_RTX_FORMAT (code);
7769 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7772 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7773 else if (fmt[i] == 'E')
7775 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7776 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7783 if (spill_reg_order[REGNO (x)] < 0)
7786 /* Scan backwards for the insn that sets x. This might be a way back due
7788 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7790 code = GET_CODE (prev);
7791 if (code == CODE_LABEL || code == JUMP_INSN)
7793 if (GET_RTX_CLASS (code) != 'i')
7795 if (reg_set_p (x, PATTERN (prev)))
7797 if (reg_referenced_p (x, PATTERN (prev)))
7800 if (! prev || INSN_UID (prev) < reload_first_uid)
7802 /* Check that PREV only sets the reload register. */
7803 set = single_set (prev);
7806 dst = SET_DEST (set);
7807 if (GET_CODE (dst) != REG
7808 || ! rtx_equal_p (dst, x))
7810 if (! reg_set_p (dst, PATTERN (dead_insn)))
7812 /* Check if DST was used in a later insn -
7813 it might have been inherited. */
7814 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7816 if (GET_CODE (i2) == CODE_LABEL)
7820 if (reg_referenced_p (dst, PATTERN (i2)))
7822 /* If there is a reference to the register in the current insn,
7823 it might be loaded in a non-inherited reload. If no other
7824 reload uses it, that means the register is set before
7826 if (i2 == current_insn)
7828 for (j = n_reloads - 1; j >= 0; j--)
7829 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7830 || reload_override_in[j] == dst)
7832 for (j = n_reloads - 1; j >= 0; j--)
7833 if (rld[j].in && rld[j].reg_rtx == dst)
7840 if (GET_CODE (i2) == JUMP_INSN)
7842 /* If DST is still live at CURRENT_INSN, check if it is used for
7843 any reload. Note that even if CURRENT_INSN sets DST, we still
7844 have to check the reloads. */
7845 if (i2 == current_insn)
7847 for (j = n_reloads - 1; j >= 0; j--)
7848 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7849 || reload_override_in[j] == dst)
7851 /* ??? We can't finish the loop here, because dst might be
7852 allocated to a pseudo in this block if no reload in this
7853 block needs any of the clsses containing DST - see
7854 spill_hard_reg. There is no easy way to tell this, so we
7855 have to scan till the end of the basic block. */
7857 if (reg_set_p (dst, PATTERN (i2)))
7861 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7862 reg_reloaded_contents[REGNO (dst)] = -1;
7866 /* Output reload-insns to reload VALUE into RELOADREG.
7867 VALUE is an autoincrement or autodecrement RTX whose operand
7868 is a register or memory location;
7869 so reloading involves incrementing that location.
7870 IN is either identical to VALUE, or some cheaper place to reload from.
7872 INC_AMOUNT is the number to increment or decrement by (always positive).
7873 This cannot be deduced from VALUE.
7875 Return the instruction that stores into RELOADREG. */
7878 inc_for_reload (reloadreg, in, value, inc_amount)
7883 /* REG or MEM to be copied and incremented. */
7884 rtx incloc = XEXP (value, 0);
7885 /* Nonzero if increment after copying. */
7886 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7892 rtx real_in = in == value ? XEXP (in, 0) : in;
7894 /* No hard register is equivalent to this register after
7895 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7896 we could inc/dec that register as well (maybe even using it for
7897 the source), but I'm not sure it's worth worrying about. */
7898 if (GET_CODE (incloc) == REG)
7899 reg_last_reload_reg[REGNO (incloc)] = 0;
7901 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7902 inc_amount = -inc_amount;
7904 inc = GEN_INT (inc_amount);
7906 /* If this is post-increment, first copy the location to the reload reg. */
7907 if (post && real_in != reloadreg)
7908 emit_insn (gen_move_insn (reloadreg, real_in));
7912 /* See if we can directly increment INCLOC. Use a method similar to
7913 that in gen_reload. */
7915 last = get_last_insn ();
7916 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7917 gen_rtx_PLUS (GET_MODE (incloc),
7920 code = recog_memoized (add_insn);
7923 extract_insn (add_insn);
7924 if (constrain_operands (1))
7926 /* If this is a pre-increment and we have incremented the value
7927 where it lives, copy the incremented value to RELOADREG to
7928 be used as an address. */
7931 emit_insn (gen_move_insn (reloadreg, incloc));
7936 delete_insns_since (last);
7939 /* If couldn't do the increment directly, must increment in RELOADREG.
7940 The way we do this depends on whether this is pre- or post-increment.
7941 For pre-increment, copy INCLOC to the reload register, increment it
7942 there, then save back. */
7946 if (in != reloadreg)
7947 emit_insn (gen_move_insn (reloadreg, real_in));
7948 emit_insn (gen_add2_insn (reloadreg, inc));
7949 store = emit_insn (gen_move_insn (incloc, reloadreg));
7954 Because this might be a jump insn or a compare, and because RELOADREG
7955 may not be available after the insn in an input reload, we must do
7956 the incrementation before the insn being reloaded for.
7958 We have already copied IN to RELOADREG. Increment the copy in
7959 RELOADREG, save that back, then decrement RELOADREG so it has
7960 the original value. */
7962 emit_insn (gen_add2_insn (reloadreg, inc));
7963 store = emit_insn (gen_move_insn (incloc, reloadreg));
7964 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7970 /* Return 1 if we are certain that the constraint-string STRING allows
7971 the hard register REG. Return 0 if we can't be sure of this. */
7974 constraint_accepts_reg_p (string, reg)
7979 int regno = true_regnum (reg);
7982 /* Initialize for first alternative. */
7984 /* Check that each alternative contains `g' or `r'. */
7986 switch (c = *string++)
7989 /* If an alternative lacks `g' or `r', we lose. */
7992 /* If an alternative lacks `g' or `r', we lose. */
7995 /* Initialize for next alternative. */
8000 /* Any general reg wins for this alternative. */
8001 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8005 /* Any reg in specified class wins for this alternative. */
8007 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8009 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8015 /* INSN is a no-op; delete it.
8016 If this sets the return value of the function, we must keep a USE around,
8017 in case this is in a different basic block than the final USE. Otherwise,
8018 we could loose important register lifeness information on
8019 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8020 spills: subsequent passes assume that spill registers are dead at the end
8022 VALUE must be the return value in such a case, NULL otherwise. */
8024 reload_cse_delete_noop_set (insn, value)
8027 bool purge = BLOCK_FOR_INSN (insn)->end == insn;
8030 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8031 INSN_CODE (insn) = -1;
8032 REG_NOTES (insn) = NULL_RTX;
8037 purge_dead_edges (BLOCK_FOR_INSN (insn));
8040 /* See whether a single set SET is a noop. */
8042 reload_cse_noop_set_p (set)
8045 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8048 /* Try to simplify INSN. */
8050 reload_cse_simplify (insn)
8053 rtx body = PATTERN (insn);
8055 if (GET_CODE (body) == SET)
8059 /* Simplify even if we may think it is a no-op.
8060 We may think a memory load of a value smaller than WORD_SIZE
8061 is redundant because we haven't taken into account possible
8062 implicit extension. reload_cse_simplify_set() will bring
8063 this out, so it's safer to simplify before we delete. */
8064 count += reload_cse_simplify_set (body, insn);
8066 if (!count && reload_cse_noop_set_p (body))
8068 rtx value = SET_DEST (body);
8069 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8071 reload_cse_delete_noop_set (insn, value);
8076 apply_change_group ();
8078 reload_cse_simplify_operands (insn);
8080 else if (GET_CODE (body) == PARALLEL)
8084 rtx value = NULL_RTX;
8086 /* If every action in a PARALLEL is a noop, we can delete
8087 the entire PARALLEL. */
8088 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8090 rtx part = XVECEXP (body, 0, i);
8091 if (GET_CODE (part) == SET)
8093 if (! reload_cse_noop_set_p (part))
8095 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8099 value = SET_DEST (part);
8102 else if (GET_CODE (part) != CLOBBER)
8108 reload_cse_delete_noop_set (insn, value);
8109 /* We're done with this insn. */
8113 /* It's not a no-op, but we can try to simplify it. */
8114 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8115 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8116 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8119 apply_change_group ();
8121 reload_cse_simplify_operands (insn);
8125 /* Do a very simple CSE pass over the hard registers.
8127 This function detects no-op moves where we happened to assign two
8128 different pseudo-registers to the same hard register, and then
8129 copied one to the other. Reload will generate a useless
8130 instruction copying a register to itself.
8132 This function also detects cases where we load a value from memory
8133 into two different registers, and (if memory is more expensive than
8134 registers) changes it to simply copy the first register into the
8137 Another optimization is performed that scans the operands of each
8138 instruction to see whether the value is already available in a
8139 hard register. It then replaces the operand with the hard register
8140 if possible, much like an optional reload would. */
8143 reload_cse_regs_1 (first)
8149 init_alias_analysis ();
8151 for (insn = first; insn; insn = NEXT_INSN (insn))
8154 reload_cse_simplify (insn);
8156 cselib_process_insn (insn);
8160 end_alias_analysis ();
8164 /* Call cse / combine like post-reload optimization phases.
8165 FIRST is the first instruction. */
8167 reload_cse_regs (first)
8170 reload_cse_regs_1 (first);
8172 reload_cse_move2add (first);
8173 if (flag_expensive_optimizations)
8174 reload_cse_regs_1 (first);
8177 /* Try to simplify a single SET instruction. SET is the set pattern.
8178 INSN is the instruction it came from.
8179 This function only handles one case: if we set a register to a value
8180 which is not a register, we try to find that value in some other register
8181 and change the set into a register copy. */
8184 reload_cse_simplify_set (set, insn)
8191 enum reg_class dclass;
8194 struct elt_loc_list *l;
8195 #ifdef LOAD_EXTEND_OP
8196 enum rtx_code extend_op = NIL;
8199 dreg = true_regnum (SET_DEST (set));
8203 src = SET_SRC (set);
8204 if (side_effects_p (src) || true_regnum (src) >= 0)
8207 dclass = REGNO_REG_CLASS (dreg);
8209 #ifdef LOAD_EXTEND_OP
8210 /* When replacing a memory with a register, we need to honor assumptions
8211 that combine made wrt the contents of sign bits. We'll do this by
8212 generating an extend instruction instead of a reg->reg copy. Thus
8213 the destination must be a register that we can widen. */
8214 if (GET_CODE (src) == MEM
8215 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8216 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8217 && GET_CODE (SET_DEST (set)) != REG)
8221 /* If memory loads are cheaper than register copies, don't change them. */
8222 if (GET_CODE (src) == MEM)
8223 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8224 else if (CONSTANT_P (src))
8225 old_cost = rtx_cost (src, SET);
8226 else if (GET_CODE (src) == REG)
8227 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8228 REGNO_REG_CLASS (REGNO (src)), dclass);
8231 old_cost = rtx_cost (src, SET);
8233 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8236 for (l = val->locs; l; l = l->next)
8238 rtx this_rtx = l->loc;
8241 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8243 #ifdef LOAD_EXTEND_OP
8244 if (extend_op != NIL)
8246 HOST_WIDE_INT this_val;
8248 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8249 constants, such as SYMBOL_REF, cannot be extended. */
8250 if (GET_CODE (this_rtx) != CONST_INT)
8253 this_val = INTVAL (this_rtx);
8257 this_val &= GET_MODE_MASK (GET_MODE (src));
8260 /* ??? In theory we're already extended. */
8261 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8266 this_rtx = GEN_INT (this_val);
8269 this_cost = rtx_cost (this_rtx, SET);
8271 else if (GET_CODE (this_rtx) == REG)
8273 #ifdef LOAD_EXTEND_OP
8274 if (extend_op != NIL)
8276 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8277 this_cost = rtx_cost (this_rtx, SET);
8281 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8282 REGNO_REG_CLASS (REGNO (this_rtx)),
8288 /* If equal costs, prefer registers over anything else. That
8289 tends to lead to smaller instructions on some machines. */
8290 if (this_cost < old_cost
8291 || (this_cost == old_cost
8292 && GET_CODE (this_rtx) == REG
8293 && GET_CODE (SET_SRC (set)) != REG))
8295 #ifdef LOAD_EXTEND_OP
8296 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8297 && extend_op != NIL)
8299 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8300 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8301 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8305 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8306 old_cost = this_cost, did_change = 1;
8313 /* Try to replace operands in INSN with equivalent values that are already
8314 in registers. This can be viewed as optional reloading.
8316 For each non-register operand in the insn, see if any hard regs are
8317 known to be equivalent to that operand. Record the alternatives which
8318 can accept these hard registers. Among all alternatives, select the
8319 ones which are better or equal to the one currently matching, where
8320 "better" is in terms of '?' and '!' constraints. Among the remaining
8321 alternatives, select the one which replaces most operands with
8325 reload_cse_simplify_operands (insn)
8330 /* For each operand, all registers that are equivalent to it. */
8331 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8333 const char *constraints[MAX_RECOG_OPERANDS];
8335 /* Vector recording how bad an alternative is. */
8336 int *alternative_reject;
8337 /* Vector recording how many registers can be introduced by choosing
8338 this alternative. */
8339 int *alternative_nregs;
8340 /* Array of vectors recording, for each operand and each alternative,
8341 which hard register to substitute, or -1 if the operand should be
8343 int *op_alt_regno[MAX_RECOG_OPERANDS];
8344 /* Array of alternatives, sorted in order of decreasing desirability. */
8345 int *alternative_order;
8346 rtx reg = gen_rtx_REG (VOIDmode, -1);
8348 extract_insn (insn);
8350 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8353 /* Figure out which alternative currently matches. */
8354 if (! constrain_operands (1))
8355 fatal_insn_not_found (insn);
8357 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8358 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8359 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8360 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8361 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8363 /* For each operand, find out which regs are equivalent. */
8364 for (i = 0; i < recog_data.n_operands; i++)
8367 struct elt_loc_list *l;
8369 CLEAR_HARD_REG_SET (equiv_regs[i]);
8371 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8372 right, so avoid the problem here. Likewise if we have a constant
8373 and the insn pattern doesn't tell us the mode we need. */
8374 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8375 || (CONSTANT_P (recog_data.operand[i])
8376 && recog_data.operand_mode[i] == VOIDmode))
8379 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8383 for (l = v->locs; l; l = l->next)
8384 if (GET_CODE (l->loc) == REG)
8385 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8388 for (i = 0; i < recog_data.n_operands; i++)
8390 enum machine_mode mode;
8394 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8395 for (j = 0; j < recog_data.n_alternatives; j++)
8396 op_alt_regno[i][j] = -1;
8398 p = constraints[i] = recog_data.constraints[i];
8399 mode = recog_data.operand_mode[i];
8401 /* Add the reject values for each alternative given by the constraints
8402 for this operand. */
8410 alternative_reject[j] += 3;
8412 alternative_reject[j] += 300;
8415 /* We won't change operands which are already registers. We
8416 also don't want to modify output operands. */
8417 regno = true_regnum (recog_data.operand[i]);
8419 || constraints[i][0] == '='
8420 || constraints[i][0] == '+')
8423 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8425 int class = (int) NO_REGS;
8427 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8430 REGNO (reg) = regno;
8431 PUT_MODE (reg, mode);
8433 /* We found a register equal to this operand. Now look for all
8434 alternatives that can accept this register and have not been
8435 assigned a register they can use yet. */
8444 case '=': case '+': case '?':
8445 case '#': case '&': case '!':
8447 case '0': case '1': case '2': case '3': case '4':
8448 case '5': case '6': case '7': case '8': case '9':
8449 case 'm': case '<': case '>': case 'V': case 'o':
8450 case 'E': case 'F': case 'G': case 'H':
8451 case 's': case 'i': case 'n':
8452 case 'I': case 'J': case 'K': case 'L':
8453 case 'M': case 'N': case 'O': case 'P':
8455 /* These don't say anything we care about. */
8459 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8464 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)];
8467 case ',': case '\0':
8468 /* See if REGNO fits this alternative, and set it up as the
8469 replacement register if we don't have one for this
8470 alternative yet and the operand being replaced is not
8471 a cheap CONST_INT. */
8472 if (op_alt_regno[i][j] == -1
8473 && reg_fits_class_p (reg, class, 0, mode)
8474 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8475 || (rtx_cost (recog_data.operand[i], SET)
8476 > rtx_cost (reg, SET))))
8478 alternative_nregs[j]++;
8479 op_alt_regno[i][j] = regno;
8491 /* Record all alternatives which are better or equal to the currently
8492 matching one in the alternative_order array. */
8493 for (i = j = 0; i < recog_data.n_alternatives; i++)
8494 if (alternative_reject[i] <= alternative_reject[which_alternative])
8495 alternative_order[j++] = i;
8496 recog_data.n_alternatives = j;
8498 /* Sort it. Given a small number of alternatives, a dumb algorithm
8499 won't hurt too much. */
8500 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8503 int best_reject = alternative_reject[alternative_order[i]];
8504 int best_nregs = alternative_nregs[alternative_order[i]];
8507 for (j = i + 1; j < recog_data.n_alternatives; j++)
8509 int this_reject = alternative_reject[alternative_order[j]];
8510 int this_nregs = alternative_nregs[alternative_order[j]];
8512 if (this_reject < best_reject
8513 || (this_reject == best_reject && this_nregs < best_nregs))
8516 best_reject = this_reject;
8517 best_nregs = this_nregs;
8521 tmp = alternative_order[best];
8522 alternative_order[best] = alternative_order[i];
8523 alternative_order[i] = tmp;
8526 /* Substitute the operands as determined by op_alt_regno for the best
8528 j = alternative_order[0];
8530 for (i = 0; i < recog_data.n_operands; i++)
8532 enum machine_mode mode = recog_data.operand_mode[i];
8533 if (op_alt_regno[i][j] == -1)
8536 validate_change (insn, recog_data.operand_loc[i],
8537 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8540 for (i = recog_data.n_dups - 1; i >= 0; i--)
8542 int op = recog_data.dup_num[i];
8543 enum machine_mode mode = recog_data.operand_mode[op];
8545 if (op_alt_regno[op][j] == -1)
8548 validate_change (insn, recog_data.dup_loc[i],
8549 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8552 return apply_change_group ();
8555 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8557 This code might also be useful when reload gave up on reg+reg addresssing
8558 because of clashes between the return register and INDEX_REG_CLASS. */
8560 /* The maximum number of uses of a register we can keep track of to
8561 replace them with reg+reg addressing. */
8562 #define RELOAD_COMBINE_MAX_USES 6
8564 /* INSN is the insn where a register has ben used, and USEP points to the
8565 location of the register within the rtl. */
8566 struct reg_use { rtx insn, *usep; };
8568 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8569 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8570 indicates where it becomes live again.
8571 Otherwise, USE_INDEX is the index of the last encountered use of the
8572 register (which is first among these we have seen since we scan backwards),
8573 OFFSET contains the constant offset that is added to the register in
8574 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8575 last, of these uses.
8576 STORE_RUID is always meaningful if we only want to use a value in a
8577 register in a different place: it denotes the next insn in the insn
8578 stream (i.e. the last ecountered) that sets or clobbers the register. */
8581 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8586 } reg_state[FIRST_PSEUDO_REGISTER];
8588 /* Reverse linear uid. This is increased in reload_combine while scanning
8589 the instructions from last to first. It is used to set last_label_ruid
8590 and the store_ruid / use_ruid fields in reg_state. */
8591 static int reload_combine_ruid;
8593 #define LABEL_LIVE(LABEL) \
8594 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8600 int first_index_reg = -1;
8601 int last_index_reg = 0;
8604 int last_label_ruid;
8605 int min_labelno, n_labels;
8606 HARD_REG_SET ever_live_at_start, *label_live;
8608 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8609 reload has already used it where appropriate, so there is no use in
8610 trying to generate it now. */
8611 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8614 /* To avoid wasting too much time later searching for an index register,
8615 determine the minimum and maximum index register numbers. */
8616 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8617 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8619 if (first_index_reg == -1)
8620 first_index_reg = r;
8625 /* If no index register is available, we can quit now. */
8626 if (first_index_reg == -1)
8629 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8630 information is a bit fuzzy immediately after reload, but it's
8631 still good enough to determine which registers are live at a jump
8633 min_labelno = get_first_label_num ();
8634 n_labels = max_label_num () - min_labelno;
8635 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8636 CLEAR_HARD_REG_SET (ever_live_at_start);
8638 for (i = n_basic_blocks - 1; i >= 0; i--)
8640 insn = BLOCK_HEAD (i);
8641 if (GET_CODE (insn) == CODE_LABEL)
8645 REG_SET_TO_HARD_REG_SET (live,
8646 BASIC_BLOCK (i)->global_live_at_start);
8647 compute_use_by_pseudos (&live,
8648 BASIC_BLOCK (i)->global_live_at_start);
8649 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8650 IOR_HARD_REG_SET (ever_live_at_start, live);
8654 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8655 last_label_ruid = reload_combine_ruid = 0;
8656 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8658 reg_state[r].store_ruid = reload_combine_ruid;
8660 reg_state[r].use_index = -1;
8662 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8665 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8669 /* We cannot do our optimization across labels. Invalidating all the use
8670 information we have would be costly, so we just note where the label
8671 is and then later disable any optimization that would cross it. */
8672 if (GET_CODE (insn) == CODE_LABEL)
8673 last_label_ruid = reload_combine_ruid;
8674 else if (GET_CODE (insn) == BARRIER)
8675 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8676 if (! fixed_regs[r])
8677 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8679 if (! INSN_P (insn))
8682 reload_combine_ruid++;
8684 /* Look for (set (REGX) (CONST_INT))
8685 (set (REGX) (PLUS (REGX) (REGY)))
8687 ... (MEM (REGX)) ...
8689 (set (REGZ) (CONST_INT))
8691 ... (MEM (PLUS (REGZ) (REGY)))... .
8693 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8694 and that we know all uses of REGX before it dies. */
8695 set = single_set (insn);
8697 && GET_CODE (SET_DEST (set)) == REG
8698 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8699 GET_MODE (SET_DEST (set)))
8701 && GET_CODE (SET_SRC (set)) == PLUS
8702 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8703 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8704 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8706 rtx reg = SET_DEST (set);
8707 rtx plus = SET_SRC (set);
8708 rtx base = XEXP (plus, 1);
8709 rtx prev = prev_nonnote_insn (insn);
8710 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8711 unsigned int regno = REGNO (reg);
8712 rtx const_reg = NULL_RTX;
8713 rtx reg_sum = NULL_RTX;
8715 /* Now, we need an index register.
8716 We'll set index_reg to this index register, const_reg to the
8717 register that is to be loaded with the constant
8718 (denoted as REGZ in the substitution illustration above),
8719 and reg_sum to the register-register that we want to use to
8720 substitute uses of REG (typically in MEMs) with.
8721 First check REG and BASE for being index registers;
8722 we can use them even if they are not dead. */
8723 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8724 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8732 /* Otherwise, look for a free index register. Since we have
8733 checked above that neiter REG nor BASE are index registers,
8734 if we find anything at all, it will be different from these
8736 for (i = first_index_reg; i <= last_index_reg; i++)
8738 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8740 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8741 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8742 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8744 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8746 const_reg = index_reg;
8747 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8753 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8754 (REGY), i.e. BASE, is not clobbered before the last use we'll
8757 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8758 && rtx_equal_p (SET_DEST (prev_set), reg)
8759 && reg_state[regno].use_index >= 0
8760 && (reg_state[REGNO (base)].store_ruid
8761 <= reg_state[regno].use_ruid)
8766 /* Change destination register and, if necessary, the
8767 constant value in PREV, the constant loading instruction. */
8768 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8769 if (reg_state[regno].offset != const0_rtx)
8770 validate_change (prev,
8771 &SET_SRC (prev_set),
8772 GEN_INT (INTVAL (SET_SRC (prev_set))
8773 + INTVAL (reg_state[regno].offset)),
8776 /* Now for every use of REG that we have recorded, replace REG
8778 for (i = reg_state[regno].use_index;
8779 i < RELOAD_COMBINE_MAX_USES; i++)
8780 validate_change (reg_state[regno].reg_use[i].insn,
8781 reg_state[regno].reg_use[i].usep,
8782 /* Each change must have its own
8784 copy_rtx (reg_sum), 1);
8786 if (apply_change_group ())
8790 /* Delete the reg-reg addition. */
8793 if (reg_state[regno].offset != const0_rtx)
8794 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8796 for (np = ®_NOTES (prev); *np;)
8798 if (REG_NOTE_KIND (*np) == REG_EQUAL
8799 || REG_NOTE_KIND (*np) == REG_EQUIV)
8800 *np = XEXP (*np, 1);
8802 np = &XEXP (*np, 1);
8805 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8806 reg_state[REGNO (const_reg)].store_ruid
8807 = reload_combine_ruid;
8813 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8815 if (GET_CODE (insn) == CALL_INSN)
8819 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8820 if (call_used_regs[r])
8822 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8823 reg_state[r].store_ruid = reload_combine_ruid;
8826 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8827 link = XEXP (link, 1))
8829 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8830 if (GET_CODE (usage_rtx) == REG)
8833 unsigned int start_reg = REGNO (usage_rtx);
8834 unsigned int num_regs =
8835 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8836 unsigned int end_reg = start_reg + num_regs - 1;
8837 for (i = start_reg; i <= end_reg; i++)
8838 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8840 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8841 reg_state[i].store_ruid = reload_combine_ruid;
8844 reg_state[i].use_index = -1;
8849 else if (GET_CODE (insn) == JUMP_INSN
8850 && GET_CODE (PATTERN (insn)) != RETURN)
8852 /* Non-spill registers might be used at the call destination in
8853 some unknown fashion, so we have to mark the unknown use. */
8856 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8857 && JUMP_LABEL (insn))
8858 live = &LABEL_LIVE (JUMP_LABEL (insn));
8860 live = &ever_live_at_start;
8862 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8863 if (TEST_HARD_REG_BIT (*live, i))
8864 reg_state[i].use_index = -1;
8867 reload_combine_note_use (&PATTERN (insn), insn);
8868 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8870 if (REG_NOTE_KIND (note) == REG_INC
8871 && GET_CODE (XEXP (note, 0)) == REG)
8873 int regno = REGNO (XEXP (note, 0));
8875 reg_state[regno].store_ruid = reload_combine_ruid;
8876 reg_state[regno].use_index = -1;
8884 /* Check if DST is a register or a subreg of a register; if it is,
8885 update reg_state[regno].store_ruid and reg_state[regno].use_index
8886 accordingly. Called via note_stores from reload_combine. */
8889 reload_combine_note_store (dst, set, data)
8891 void *data ATTRIBUTE_UNUSED;
8895 enum machine_mode mode = GET_MODE (dst);
8897 if (GET_CODE (dst) == SUBREG)
8899 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8900 GET_MODE (SUBREG_REG (dst)),
8903 dst = SUBREG_REG (dst);
8905 if (GET_CODE (dst) != REG)
8907 regno += REGNO (dst);
8909 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8910 careful with registers / register parts that are not full words.
8912 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8913 if (GET_CODE (set) != SET
8914 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8915 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8916 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8918 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8920 reg_state[i].use_index = -1;
8921 reg_state[i].store_ruid = reload_combine_ruid;
8926 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8928 reg_state[i].store_ruid = reload_combine_ruid;
8929 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8934 /* XP points to a piece of rtl that has to be checked for any uses of
8936 *XP is the pattern of INSN, or a part of it.
8937 Called from reload_combine, and recursively by itself. */
8939 reload_combine_note_use (xp, insn)
8943 enum rtx_code code = x->code;
8946 rtx offset = const0_rtx; /* For the REG case below. */
8951 if (GET_CODE (SET_DEST (x)) == REG)
8953 reload_combine_note_use (&SET_SRC (x), insn);
8959 /* If this is the USE of a return value, we can't change it. */
8960 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8962 /* Mark the return register as used in an unknown fashion. */
8963 rtx reg = XEXP (x, 0);
8964 int regno = REGNO (reg);
8965 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8967 while (--nregs >= 0)
8968 reg_state[regno + nregs].use_index = -1;
8974 if (GET_CODE (SET_DEST (x)) == REG)
8976 /* No spurious CLOBBERs of pseudo registers may remain. */
8977 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8984 /* We are interested in (plus (reg) (const_int)) . */
8985 if (GET_CODE (XEXP (x, 0)) != REG
8986 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8988 offset = XEXP (x, 1);
8993 int regno = REGNO (x);
8997 /* No spurious USEs of pseudo registers may remain. */
8998 if (regno >= FIRST_PSEUDO_REGISTER)
9001 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
9003 /* We can't substitute into multi-hard-reg uses. */
9006 while (--nregs >= 0)
9007 reg_state[regno + nregs].use_index = -1;
9011 /* If this register is already used in some unknown fashion, we
9013 If we decrement the index from zero to -1, we can't store more
9014 uses, so this register becomes used in an unknown fashion. */
9015 use_index = --reg_state[regno].use_index;
9019 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9021 /* We have found another use for a register that is already
9022 used later. Check if the offsets match; if not, mark the
9023 register as used in an unknown fashion. */
9024 if (! rtx_equal_p (offset, reg_state[regno].offset))
9026 reg_state[regno].use_index = -1;
9032 /* This is the first use of this register we have seen since we
9033 marked it as dead. */
9034 reg_state[regno].offset = offset;
9035 reg_state[regno].use_ruid = reload_combine_ruid;
9037 reg_state[regno].reg_use[use_index].insn = insn;
9038 reg_state[regno].reg_use[use_index].usep = xp;
9046 /* Recursively process the components of X. */
9047 fmt = GET_RTX_FORMAT (code);
9048 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9051 reload_combine_note_use (&XEXP (x, i), insn);
9052 else if (fmt[i] == 'E')
9054 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9055 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9060 /* See if we can reduce the cost of a constant by replacing a move
9061 with an add. We track situations in which a register is set to a
9062 constant or to a register plus a constant. */
9063 /* We cannot do our optimization across labels. Invalidating all the
9064 information about register contents we have would be costly, so we
9065 use move2add_last_label_luid to note where the label is and then
9066 later disable any optimization that would cross it.
9067 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9068 reg_set_luid[n] is greater than last_label_luid[n] . */
9069 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9071 /* If reg_base_reg[n] is negative, register n has been set to
9072 reg_offset[n] in mode reg_mode[n] .
9073 If reg_base_reg[n] is non-negative, register n has been set to the
9074 sum of reg_offset[n] and the value of register reg_base_reg[n]
9075 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9076 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9077 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9078 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9080 /* move2add_luid is linearily increased while scanning the instructions
9081 from first to last. It is used to set reg_set_luid in
9082 reload_cse_move2add and move2add_note_store. */
9083 static int move2add_luid;
9085 /* move2add_last_label_luid is set whenever a label is found. Labels
9086 invalidate all previously collected reg_offset data. */
9087 static int move2add_last_label_luid;
9089 /* Generate a CONST_INT and force it in the range of MODE. */
9091 static HOST_WIDE_INT
9092 sext_for_mode (mode, value)
9093 enum machine_mode mode;
9094 HOST_WIDE_INT value;
9096 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9097 int width = GET_MODE_BITSIZE (mode);
9099 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9101 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9102 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9103 cval |= (HOST_WIDE_INT) -1 << width;
9108 /* ??? We don't know how zero / sign extension is handled, hence we
9109 can't go from a narrower to a wider mode. */
9110 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9111 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9112 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9113 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9114 GET_MODE_BITSIZE (INMODE))))
9117 reload_cse_move2add (first)
9123 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9124 reg_set_luid[i] = 0;
9126 move2add_last_label_luid = 0;
9128 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9132 if (GET_CODE (insn) == CODE_LABEL)
9134 move2add_last_label_luid = move2add_luid;
9135 /* We're going to increment move2add_luid twice after a
9136 label, so that we can use move2add_last_label_luid + 1 as
9137 the luid for constants. */
9141 if (! INSN_P (insn))
9143 pat = PATTERN (insn);
9144 /* For simplicity, we only perform this optimization on
9145 straightforward SETs. */
9146 if (GET_CODE (pat) == SET
9147 && GET_CODE (SET_DEST (pat)) == REG)
9149 rtx reg = SET_DEST (pat);
9150 int regno = REGNO (reg);
9151 rtx src = SET_SRC (pat);
9153 /* Check if we have valid information on the contents of this
9154 register in the mode of REG. */
9155 if (reg_set_luid[regno] > move2add_last_label_luid
9156 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9158 /* Try to transform (set (REGX) (CONST_INT A))
9160 (set (REGX) (CONST_INT B))
9162 (set (REGX) (CONST_INT A))
9164 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9166 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9169 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9171 - reg_offset[regno]));
9172 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9173 use (set (reg) (reg)) instead.
9174 We don't delete this insn, nor do we convert it into a
9175 note, to avoid losing register notes or the return
9176 value flag. jump2 already knowns how to get rid of
9178 if (new_src == const0_rtx)
9179 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9180 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9181 && have_add2_insn (reg, new_src))
9182 success = validate_change (insn, &PATTERN (insn),
9183 gen_add2_insn (reg, new_src), 0);
9184 reg_set_luid[regno] = move2add_luid;
9185 reg_mode[regno] = GET_MODE (reg);
9186 reg_offset[regno] = INTVAL (src);
9190 /* Try to transform (set (REGX) (REGY))
9191 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9194 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9197 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9199 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9200 else if (GET_CODE (src) == REG
9201 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9202 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9203 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9204 reg_mode[REGNO (src)]))
9206 rtx next = next_nonnote_insn (insn);
9209 set = single_set (next);
9211 && SET_DEST (set) == reg
9212 && GET_CODE (SET_SRC (set)) == PLUS
9213 && XEXP (SET_SRC (set), 0) == reg
9214 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9216 rtx src3 = XEXP (SET_SRC (set), 1);
9217 HOST_WIDE_INT added_offset = INTVAL (src3);
9218 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9219 HOST_WIDE_INT regno_offset = reg_offset[regno];
9220 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9226 if (new_src == const0_rtx)
9227 /* See above why we create (set (reg) (reg)) here. */
9229 = validate_change (next, &SET_SRC (set), reg, 0);
9230 else if ((rtx_cost (new_src, PLUS)
9231 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9232 && have_add2_insn (reg, new_src))
9234 = validate_change (next, &PATTERN (next),
9235 gen_add2_insn (reg, new_src), 0);
9239 reg_mode[regno] = GET_MODE (reg);
9240 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9249 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9251 if (REG_NOTE_KIND (note) == REG_INC
9252 && GET_CODE (XEXP (note, 0)) == REG)
9254 /* Reset the information about this register. */
9255 int regno = REGNO (XEXP (note, 0));
9256 if (regno < FIRST_PSEUDO_REGISTER)
9257 reg_set_luid[regno] = 0;
9260 note_stores (PATTERN (insn), move2add_note_store, NULL);
9261 /* If this is a CALL_INSN, all call used registers are stored with
9263 if (GET_CODE (insn) == CALL_INSN)
9265 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9267 if (call_used_regs[i])
9268 /* Reset the information about this register. */
9269 reg_set_luid[i] = 0;
9275 /* SET is a SET or CLOBBER that sets DST.
9276 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9277 Called from reload_cse_move2add via note_stores. */
9280 move2add_note_store (dst, set, data)
9282 void *data ATTRIBUTE_UNUSED;
9284 unsigned int regno = 0;
9286 enum machine_mode mode = GET_MODE (dst);
9288 if (GET_CODE (dst) == SUBREG)
9290 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9291 GET_MODE (SUBREG_REG (dst)),
9294 dst = SUBREG_REG (dst);
9297 /* Some targets do argument pushes without adding REG_INC notes. */
9299 if (GET_CODE (dst) == MEM)
9301 dst = XEXP (dst, 0);
9302 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9303 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9304 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9307 if (GET_CODE (dst) != REG)
9310 regno += REGNO (dst);
9312 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9313 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9314 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9315 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9317 rtx src = SET_SRC (set);
9319 HOST_WIDE_INT offset;
9321 /* This may be different from mode, if SET_DEST (set) is a
9323 enum machine_mode dst_mode = GET_MODE (dst);
9325 switch (GET_CODE (src))
9328 if (GET_CODE (XEXP (src, 0)) == REG)
9330 base_reg = XEXP (src, 0);
9332 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9333 offset = INTVAL (XEXP (src, 1));
9334 else if (GET_CODE (XEXP (src, 1)) == REG
9335 && (reg_set_luid[REGNO (XEXP (src, 1))]
9336 > move2add_last_label_luid)
9337 && (MODES_OK_FOR_MOVE2ADD
9338 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9340 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9341 offset = reg_offset[REGNO (XEXP (src, 1))];
9342 /* Maybe the first register is known to be a
9344 else if (reg_set_luid[REGNO (base_reg)]
9345 > move2add_last_label_luid
9346 && (MODES_OK_FOR_MOVE2ADD
9347 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9348 && reg_base_reg[REGNO (base_reg)] < 0)
9350 offset = reg_offset[REGNO (base_reg)];
9351 base_reg = XEXP (src, 1);
9370 /* Start tracking the register as a constant. */
9371 reg_base_reg[regno] = -1;
9372 reg_offset[regno] = INTVAL (SET_SRC (set));
9373 /* We assign the same luid to all registers set to constants. */
9374 reg_set_luid[regno] = move2add_last_label_luid + 1;
9375 reg_mode[regno] = mode;
9380 /* Invalidate the contents of the register. */
9381 reg_set_luid[regno] = 0;
9385 base_regno = REGNO (base_reg);
9386 /* If information about the base register is not valid, set it
9387 up as a new base register, pretending its value is known
9388 starting from the current insn. */
9389 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9391 reg_base_reg[base_regno] = base_regno;
9392 reg_offset[base_regno] = 0;
9393 reg_set_luid[base_regno] = move2add_luid;
9394 reg_mode[base_regno] = mode;
9396 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9397 reg_mode[base_regno]))
9400 reg_mode[regno] = mode;
9402 /* Copy base information from our base register. */
9403 reg_set_luid[regno] = reg_set_luid[base_regno];
9404 reg_base_reg[regno] = reg_base_reg[base_regno];
9406 /* Compute the sum of the offsets or constants. */
9407 reg_offset[regno] = sext_for_mode (dst_mode,
9409 + reg_offset[base_regno]);
9413 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9415 for (i = regno; i < endregno; i++)
9416 /* Reset the information about this register. */
9417 reg_set_luid[i] = 0;
9423 add_auto_inc_notes (insn, x)
9427 enum rtx_code code = GET_CODE (x);
9431 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9434 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9438 /* Scan all the operand sub-expressions. */
9439 fmt = GET_RTX_FORMAT (code);
9440 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9443 add_auto_inc_notes (insn, XEXP (x, i));
9444 else if (fmt[i] == 'E')
9445 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9446 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9451 /* Copy EH notes from an insn to its reloads. */
9453 copy_eh_notes (insn, x)
9457 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9460 for (; x != 0; x = NEXT_INSN (x))
9462 if (may_trap_p (PATTERN (x)))
9464 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9470 /* This is used by reload pass, that does emit some instructions after
9471 abnormal calls moving basic block end, but in fact it wants to emit
9472 them on the edge. Looks for abnormal call edges, find backward the
9473 proper call and fix the damage.
9475 Similar handle instructions throwing exceptions internally. */
9477 fixup_abnormal_edges ()
9480 bool inserted = false;
9482 for (i = 0; i < n_basic_blocks; i++)
9484 basic_block bb = BASIC_BLOCK (i);
9487 /* Look for cases we are interested in - an calls or instructions causing
9489 for (e = bb->succ; e; e = e->succ_next)
9491 if (e->flags & EDGE_ABNORMAL_CALL)
9493 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9494 == (EDGE_ABNORMAL | EDGE_EH))
9497 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9499 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9501 for (e = bb->succ; e; e = e->succ_next)
9502 if (e->flags & EDGE_FALLTHRU)
9504 /* Get past the new insns generated. Allow notes, as the insns may
9505 be already deleted. */
9506 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9507 && !can_throw_internal (insn)
9508 && insn != bb->head)
9509 insn = PREV_INSN (insn);
9510 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9514 insn = NEXT_INSN (insn);
9515 while (insn && insn != stop)
9517 next = NEXT_INSN (insn);
9524 /* We're not deleting it, we're moving it. */
9525 INSN_DELETED_P (insn) = 0;
9527 /* Emit a sequence, rather than scarfing the pattern, so
9528 that we don't lose REG_NOTES etc. */
9529 /* ??? Could copy the test from gen_sequence, but don't
9530 think it's worth the bother. */
9531 seq = gen_rtx_SEQUENCE (VOIDmode, gen_rtvec (1, insn));
9532 insert_insn_on_edge (seq, e);
9539 commit_edge_insertions ();
OSDN Git Service
