1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 #ifndef REGISTER_MOVE_COST
83 #define REGISTER_MOVE_COST(m, x, y) 2
87 #define LOCAL_REGNO(REGNO) 0
90 /* During reload_as_needed, element N contains a REG rtx for the hard reg
91 into which reg N has been reloaded (perhaps for a previous insn). */
92 static rtx *reg_last_reload_reg;
94 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
95 for an output reload that stores into reg N. */
96 static char *reg_has_output_reload;
98 /* Indicates which hard regs are reload-registers for an output reload
99 in the current insn. */
100 static HARD_REG_SET reg_is_output_reload;
102 /* Element N is the constant value to which pseudo reg N is equivalent,
103 or zero if pseudo reg N is not equivalent to a constant.
104 find_reloads looks at this in order to replace pseudo reg N
105 with the constant it stands for. */
106 rtx *reg_equiv_constant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx *reg_equiv_address;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
128 static rtx *reg_equiv_init;
130 /* Vector to remember old contents of reg_renumber before spilling. */
131 static short *reg_old_renumber;
133 /* During reload_as_needed, element N contains the last pseudo regno reloaded
134 into hard register N. If that pseudo reg occupied more than one register,
135 reg_reloaded_contents points to that pseudo for each spill register in
136 use; all of these must remain set for an inheritance to occur. */
137 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
139 /* During reload_as_needed, element N contains the insn for which
140 hard register N was last used. Its contents are significant only
141 when reg_reloaded_valid is set for this register. */
142 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
144 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
145 static HARD_REG_SET reg_reloaded_valid;
146 /* Indicate if the register was dead at the end of the reload.
147 This is only valid if reg_reloaded_contents is set and valid. */
148 static HARD_REG_SET reg_reloaded_dead;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Nonzero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If nonzero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 static void replace_pseudos_in_call_usage PARAMS ((rtx *,
372 static void maybe_fix_stack_asms PARAMS ((void));
373 static void copy_reloads PARAMS ((struct insn_chain *));
374 static void calculate_needs_all_insns PARAMS ((int));
375 static int find_reg PARAMS ((struct insn_chain *, int));
376 static void find_reload_regs PARAMS ((struct insn_chain *));
377 static void select_reload_regs PARAMS ((void));
378 static void delete_caller_save_insns PARAMS ((void));
380 static void spill_failure PARAMS ((rtx, enum reg_class));
381 static void count_spilled_pseudo PARAMS ((int, int, int));
382 static void delete_dead_insn PARAMS ((rtx));
383 static void alter_reg PARAMS ((int, int));
384 static void set_label_offsets PARAMS ((rtx, rtx, int));
385 static void check_eliminable_occurrences PARAMS ((rtx));
386 static void elimination_effects PARAMS ((rtx, enum machine_mode));
387 static int eliminate_regs_in_insn PARAMS ((rtx, int));
388 static void update_eliminable_offsets PARAMS ((void));
389 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
390 static void set_initial_elim_offsets PARAMS ((void));
391 static void verify_initial_elim_offsets PARAMS ((void));
392 static void set_initial_label_offsets PARAMS ((void));
393 static void set_offsets_for_label PARAMS ((rtx));
394 static void init_elim_table PARAMS ((void));
395 static void update_eliminables PARAMS ((HARD_REG_SET *));
396 static void spill_hard_reg PARAMS ((unsigned int, int));
397 static int finish_spills PARAMS ((int));
398 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
399 static void scan_paradoxical_subregs PARAMS ((rtx));
400 static void count_pseudo PARAMS ((int));
401 static void order_regs_for_reload PARAMS ((struct insn_chain *));
402 static void reload_as_needed PARAMS ((int));
403 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
404 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
405 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
411 static int reload_reg_free_p PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
415 rtx, rtx, int, int));
416 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
417 enum reload_type, rtx, rtx,
419 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
421 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
423 static int conflicts_with_override PARAMS ((rtx));
424 static void failed_reload PARAMS ((rtx, int));
425 static int set_reload_reg PARAMS ((int, int));
426 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
427 static void choose_reload_regs PARAMS ((struct insn_chain *));
428 static void merge_assigned_reloads PARAMS ((rtx));
429 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
430 struct reload *, rtx, int));
431 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void do_input_reload PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_output_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void emit_reload_insns PARAMS ((struct insn_chain *));
438 static void delete_output_reload PARAMS ((rtx, int, int));
439 static void delete_address_reloads PARAMS ((rtx, rtx));
440 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
441 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
442 static void reload_cse_regs_1 PARAMS ((rtx));
443 static int reload_cse_noop_set_p PARAMS ((rtx));
444 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
445 static int reload_cse_simplify_operands PARAMS ((rtx, rtx));
446 static void reload_combine PARAMS ((void));
447 static void reload_combine_note_use PARAMS ((rtx *, rtx));
448 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
449 static void reload_cse_move2add PARAMS ((rtx));
450 static void move2add_note_store PARAMS ((rtx, rtx, void *));
452 static void add_auto_inc_notes PARAMS ((rtx, rtx));
454 static void copy_eh_notes PARAMS ((rtx, rtx));
455 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
457 static void failed_reload PARAMS ((rtx, int));
458 static int set_reload_reg PARAMS ((int, int));
459 static void reload_cse_simplify PARAMS ((rtx, rtx));
460 void fixup_abnormal_edges PARAMS ((void));
461 extern void dump_needs PARAMS ((struct insn_chain *));
463 /* Initialize the reload pass once per compilation. */
470 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
471 Set spill_indirect_levels to the number of levels such addressing is
472 permitted, zero if it is not permitted at all. */
475 = gen_rtx_MEM (Pmode,
478 LAST_VIRTUAL_REGISTER + 1),
480 spill_indirect_levels = 0;
482 while (memory_address_p (QImode, tem))
484 spill_indirect_levels++;
485 tem = gen_rtx_MEM (Pmode, tem);
488 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
490 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
491 indirect_symref_ok = memory_address_p (QImode, tem);
493 /* See if reg+reg is a valid (and offsettable) address. */
495 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
497 tem = gen_rtx_PLUS (Pmode,
498 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
499 gen_rtx_REG (Pmode, i));
501 /* This way, we make sure that reg+reg is an offsettable address. */
502 tem = plus_constant (tem, 4);
504 if (memory_address_p (QImode, tem))
506 double_reg_address_ok = 1;
511 /* Initialize obstack for our rtl allocation. */
512 gcc_obstack_init (&reload_obstack);
513 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
515 INIT_REG_SET (&spilled_pseudos);
516 INIT_REG_SET (&pseudos_counted);
519 /* List of insn chains that are currently unused. */
520 static struct insn_chain *unused_insn_chains = 0;
522 /* Allocate an empty insn_chain structure. */
526 struct insn_chain *c;
528 if (unused_insn_chains == 0)
530 c = (struct insn_chain *)
531 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
532 INIT_REG_SET (&c->live_throughout);
533 INIT_REG_SET (&c->dead_or_set);
537 c = unused_insn_chains;
538 unused_insn_chains = c->next;
540 c->is_caller_save_insn = 0;
541 c->need_operand_change = 0;
547 /* Small utility function to set all regs in hard reg set TO which are
548 allocated to pseudos in regset FROM. */
551 compute_use_by_pseudos (to, from)
557 EXECUTE_IF_SET_IN_REG_SET
558 (from, FIRST_PSEUDO_REGISTER, regno,
560 int r = reg_renumber[regno];
565 /* reload_combine uses the information from
566 BASIC_BLOCK->global_live_at_start, which might still
567 contain registers that have not actually been allocated
568 since they have an equivalence. */
569 if (! reload_completed)
574 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
576 SET_HARD_REG_BIT (*to, r + nregs);
581 /* Replace all pseudos found in LOC with their corresponding
585 replace_pseudos_in_call_usage (loc, mem_mode, usage)
587 enum machine_mode mem_mode;
601 unsigned int regno = REGNO (x);
603 if (regno < FIRST_PSEUDO_REGISTER)
606 x = eliminate_regs (x, mem_mode, usage);
610 replace_pseudos_in_call_usage (loc, mem_mode, usage);
614 if (reg_equiv_constant[regno])
615 *loc = reg_equiv_constant[regno];
616 else if (reg_equiv_mem[regno])
617 *loc = reg_equiv_mem[regno];
618 else if (reg_equiv_address[regno])
619 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
620 else if (GET_CODE (regno_reg_rtx[regno]) != REG
621 || REGNO (regno_reg_rtx[regno]) != regno)
622 *loc = regno_reg_rtx[regno];
628 else if (code == MEM)
630 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
634 /* Process each of our operands recursively. */
635 fmt = GET_RTX_FORMAT (code);
636 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
638 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
639 else if (*fmt == 'E')
640 for (j = 0; j < XVECLEN (x, i); j++)
641 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
645 /* Global variables used by reload and its subroutines. */
647 /* Set during calculate_needs if an insn needs register elimination. */
648 static int something_needs_elimination;
649 /* Set during calculate_needs if an insn needs an operand changed. */
650 int something_needs_operands_changed;
652 /* Nonzero means we couldn't get enough spill regs. */
655 /* Main entry point for the reload pass.
657 FIRST is the first insn of the function being compiled.
659 GLOBAL nonzero means we were called from global_alloc
660 and should attempt to reallocate any pseudoregs that we
661 displace from hard regs we will use for reloads.
662 If GLOBAL is zero, we do not have enough information to do that,
663 so any pseudo reg that is spilled must go to the stack.
665 Return value is nonzero if reload failed
666 and we must not do any more for this function. */
669 reload (first, global)
675 struct elim_table *ep;
678 /* The two pointers used to track the true location of the memory used
679 for label offsets. */
680 char *real_known_ptr = NULL;
681 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
683 /* Make sure even insns with volatile mem refs are recognizable. */
688 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
690 /* Make sure that the last insn in the chain
691 is not something that needs reloading. */
692 emit_note (NULL, NOTE_INSN_DELETED);
694 /* Enable find_equiv_reg to distinguish insns made by reload. */
695 reload_first_uid = get_max_uid ();
697 #ifdef SECONDARY_MEMORY_NEEDED
698 /* Initialize the secondary memory table. */
699 clear_secondary_mem ();
702 /* We don't have a stack slot for any spill reg yet. */
703 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
704 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
706 /* Initialize the save area information for caller-save, in case some
710 /* Compute which hard registers are now in use
711 as homes for pseudo registers.
712 This is done here rather than (eg) in global_alloc
713 because this point is reached even if not optimizing. */
714 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
717 /* A function that receives a nonlocal goto must save all call-saved
719 if (current_function_has_nonlocal_label)
720 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
721 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
722 regs_ever_live[i] = 1;
724 /* Find all the pseudo registers that didn't get hard regs
725 but do have known equivalent constants or memory slots.
726 These include parameters (known equivalent to parameter slots)
727 and cse'd or loop-moved constant memory addresses.
729 Record constant equivalents in reg_equiv_constant
730 so they will be substituted by find_reloads.
731 Record memory equivalents in reg_mem_equiv so they can
732 be substituted eventually by altering the REG-rtx's. */
734 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
735 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
739 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
740 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
741 pseudo_forbidden_regs
742 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
744 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
746 CLEAR_HARD_REG_SET (bad_spill_regs_global);
748 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
749 Also find all paradoxical subregs and find largest such for each pseudo.
750 On machines with small register classes, record hard registers that
751 are used for user variables. These can never be used for spills.
752 Also look for a "constant" REG_SETJMP. This means that all
753 caller-saved registers must be marked live. */
755 num_eliminable_invariants = 0;
756 for (insn = first; insn; insn = NEXT_INSN (insn))
758 rtx set = single_set (insn);
760 /* We may introduce USEs that we want to remove at the end, so
761 we'll mark them with QImode. Make sure there are no
762 previously-marked insns left by say regmove. */
763 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
764 && GET_MODE (insn) != VOIDmode)
765 PUT_MODE (insn, VOIDmode);
767 if (GET_CODE (insn) == CALL_INSN
768 && find_reg_note (insn, REG_SETJMP, NULL))
769 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
770 if (! call_used_regs[i])
771 regs_ever_live[i] = 1;
773 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
775 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
777 #ifdef LEGITIMATE_PIC_OPERAND_P
778 && (! function_invariant_p (XEXP (note, 0))
780 /* A function invariant is often CONSTANT_P but may
781 include a register. We promise to only pass
782 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
783 || (CONSTANT_P (XEXP (note, 0))
784 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
788 rtx x = XEXP (note, 0);
789 i = REGNO (SET_DEST (set));
790 if (i > LAST_VIRTUAL_REGISTER)
792 /* It can happen that a REG_EQUIV note contains a MEM
793 that is not a legitimate memory operand. As later
794 stages of reload assume that all addresses found
795 in the reg_equiv_* arrays were originally legitimate,
796 we ignore such REG_EQUIV notes. */
797 if (memory_operand (x, VOIDmode))
799 /* Always unshare the equivalence, so we can
800 substitute into this insn without touching the
802 reg_equiv_memory_loc[i] = copy_rtx (x);
804 else if (function_invariant_p (x))
806 if (GET_CODE (x) == PLUS)
808 /* This is PLUS of frame pointer and a constant,
809 and might be shared. Unshare it. */
810 reg_equiv_constant[i] = copy_rtx (x);
811 num_eliminable_invariants++;
813 else if (x == frame_pointer_rtx
814 || x == arg_pointer_rtx)
816 reg_equiv_constant[i] = x;
817 num_eliminable_invariants++;
819 else if (LEGITIMATE_CONSTANT_P (x))
820 reg_equiv_constant[i] = x;
823 reg_equiv_memory_loc[i]
824 = force_const_mem (GET_MODE (SET_DEST (set)), x);
825 if (!reg_equiv_memory_loc[i])
832 /* If this register is being made equivalent to a MEM
833 and the MEM is not SET_SRC, the equivalencing insn
834 is one with the MEM as a SET_DEST and it occurs later.
835 So don't mark this insn now. */
836 if (GET_CODE (x) != MEM
837 || rtx_equal_p (SET_SRC (set), x))
839 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
844 /* If this insn is setting a MEM from a register equivalent to it,
845 this is the equivalencing insn. */
846 else if (set && GET_CODE (SET_DEST (set)) == MEM
847 && GET_CODE (SET_SRC (set)) == REG
848 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
849 && rtx_equal_p (SET_DEST (set),
850 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
851 reg_equiv_init[REGNO (SET_SRC (set))]
852 = gen_rtx_INSN_LIST (VOIDmode, insn,
853 reg_equiv_init[REGNO (SET_SRC (set))]);
856 scan_paradoxical_subregs (PATTERN (insn));
861 num_labels = max_label_num () - get_first_label_num ();
863 /* Allocate the tables used to store offset information at labels. */
864 /* We used to use alloca here, but the size of what it would try to
865 allocate would occasionally cause it to exceed the stack limit and
866 cause a core dump. */
867 real_known_ptr = xmalloc (num_labels);
869 = (int (*)[NUM_ELIMINABLE_REGS])
870 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
872 offsets_known_at = real_known_ptr - get_first_label_num ();
874 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
876 /* Alter each pseudo-reg rtx to contain its hard reg number.
877 Assign stack slots to the pseudos that lack hard regs or equivalents.
878 Do not touch virtual registers. */
880 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
883 /* If we have some registers we think can be eliminated, scan all insns to
884 see if there is an insn that sets one of these registers to something
885 other than itself plus a constant. If so, the register cannot be
886 eliminated. Doing this scan here eliminates an extra pass through the
887 main reload loop in the most common case where register elimination
889 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
890 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
891 || GET_CODE (insn) == CALL_INSN)
892 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
894 maybe_fix_stack_asms ();
896 insns_need_reload = 0;
897 something_needs_elimination = 0;
899 /* Initialize to -1, which means take the first spill register. */
902 /* Spill any hard regs that we know we can't eliminate. */
903 CLEAR_HARD_REG_SET (used_spill_regs);
904 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
905 if (! ep->can_eliminate)
906 spill_hard_reg (ep->from, 1);
908 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
909 if (frame_pointer_needed)
910 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
912 finish_spills (global);
914 /* From now on, we may need to generate moves differently. We may also
915 allow modifications of insns which cause them to not be recognized.
916 Any such modifications will be cleaned up during reload itself. */
917 reload_in_progress = 1;
919 /* This loop scans the entire function each go-round
920 and repeats until one repetition spills no additional hard regs. */
923 int something_changed;
926 HOST_WIDE_INT starting_frame_size;
928 /* Round size of stack frame to stack_alignment_needed. This must be done
929 here because the stack size may be a part of the offset computation
930 for register elimination, and there might have been new stack slots
931 created in the last iteration of this loop. */
932 if (cfun->stack_alignment_needed)
933 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
935 starting_frame_size = get_frame_size ();
937 set_initial_elim_offsets ();
938 set_initial_label_offsets ();
940 /* For each pseudo register that has an equivalent location defined,
941 try to eliminate any eliminable registers (such as the frame pointer)
942 assuming initial offsets for the replacement register, which
945 If the resulting location is directly addressable, substitute
946 the MEM we just got directly for the old REG.
948 If it is not addressable but is a constant or the sum of a hard reg
949 and constant, it is probably not addressable because the constant is
950 out of range, in that case record the address; we will generate
951 hairy code to compute the address in a register each time it is
952 needed. Similarly if it is a hard register, but one that is not
953 valid as an address register.
955 If the location is not addressable, but does not have one of the
956 above forms, assign a stack slot. We have to do this to avoid the
957 potential of producing lots of reloads if, e.g., a location involves
958 a pseudo that didn't get a hard register and has an equivalent memory
959 location that also involves a pseudo that didn't get a hard register.
961 Perhaps at some point we will improve reload_when_needed handling
962 so this problem goes away. But that's very hairy. */
964 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
965 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
967 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
969 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
971 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
972 else if (CONSTANT_P (XEXP (x, 0))
973 || (GET_CODE (XEXP (x, 0)) == REG
974 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
975 || (GET_CODE (XEXP (x, 0)) == PLUS
976 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
977 && (REGNO (XEXP (XEXP (x, 0), 0))
978 < FIRST_PSEUDO_REGISTER)
979 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
980 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
983 /* Make a new stack slot. Then indicate that something
984 changed so we go back and recompute offsets for
985 eliminable registers because the allocation of memory
986 below might change some offset. reg_equiv_{mem,address}
987 will be set up for this pseudo on the next pass around
989 reg_equiv_memory_loc[i] = 0;
990 reg_equiv_init[i] = 0;
995 if (caller_save_needed)
998 /* If we allocated another stack slot, redo elimination bookkeeping. */
999 if (starting_frame_size != get_frame_size ())
1002 if (caller_save_needed)
1004 save_call_clobbered_regs ();
1005 /* That might have allocated new insn_chain structures. */
1006 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1009 calculate_needs_all_insns (global);
1011 CLEAR_REG_SET (&spilled_pseudos);
1014 something_changed = 0;
1016 /* If we allocated any new memory locations, make another pass
1017 since it might have changed elimination offsets. */
1018 if (starting_frame_size != get_frame_size ())
1019 something_changed = 1;
1022 HARD_REG_SET to_spill;
1023 CLEAR_HARD_REG_SET (to_spill);
1024 update_eliminables (&to_spill);
1025 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1026 if (TEST_HARD_REG_BIT (to_spill, i))
1028 spill_hard_reg (i, 1);
1031 /* Regardless of the state of spills, if we previously had
1032 a register that we thought we could eliminate, but now can
1033 not eliminate, we must run another pass.
1035 Consider pseudos which have an entry in reg_equiv_* which
1036 reference an eliminable register. We must make another pass
1037 to update reg_equiv_* so that we do not substitute in the
1038 old value from when we thought the elimination could be
1040 something_changed = 1;
1044 select_reload_regs ();
1048 if (insns_need_reload != 0 || did_spill)
1049 something_changed |= finish_spills (global);
1051 if (! something_changed)
1054 if (caller_save_needed)
1055 delete_caller_save_insns ();
1057 obstack_free (&reload_obstack, reload_firstobj);
1060 /* If global-alloc was run, notify it of any register eliminations we have
1063 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1064 if (ep->can_eliminate)
1065 mark_elimination (ep->from, ep->to);
1067 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1068 If that insn didn't set the register (i.e., it copied the register to
1069 memory), just delete that insn instead of the equivalencing insn plus
1070 anything now dead. If we call delete_dead_insn on that insn, we may
1071 delete the insn that actually sets the register if the register dies
1072 there and that is incorrect. */
1074 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1076 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1079 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1081 rtx equiv_insn = XEXP (list, 0);
1083 /* If we already deleted the insn or if it may trap, we can't
1084 delete it. The latter case shouldn't happen, but can
1085 if an insn has a variable address, gets a REG_EH_REGION
1086 note added to it, and then gets converted into an load
1087 from a constant address. */
1088 if (GET_CODE (equiv_insn) == NOTE
1089 || can_throw_internal (equiv_insn))
1091 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1092 delete_dead_insn (equiv_insn);
1095 PUT_CODE (equiv_insn, NOTE);
1096 NOTE_SOURCE_FILE (equiv_insn) = 0;
1097 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1103 /* Use the reload registers where necessary
1104 by generating move instructions to move the must-be-register
1105 values into or out of the reload registers. */
1107 if (insns_need_reload != 0 || something_needs_elimination
1108 || something_needs_operands_changed)
1110 HOST_WIDE_INT old_frame_size = get_frame_size ();
1112 reload_as_needed (global);
1114 if (old_frame_size != get_frame_size ())
1118 verify_initial_elim_offsets ();
1121 /* If we were able to eliminate the frame pointer, show that it is no
1122 longer live at the start of any basic block. If it ls live by
1123 virtue of being in a pseudo, that pseudo will be marked live
1124 and hence the frame pointer will be known to be live via that
1127 if (! frame_pointer_needed)
1129 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1130 HARD_FRAME_POINTER_REGNUM);
1132 /* Come here (with failure set nonzero) if we can't get enough spill regs
1133 and we decide not to abort about it. */
1136 CLEAR_REG_SET (&spilled_pseudos);
1137 reload_in_progress = 0;
1139 /* Now eliminate all pseudo regs by modifying them into
1140 their equivalent memory references.
1141 The REG-rtx's for the pseudos are modified in place,
1142 so all insns that used to refer to them now refer to memory.
1144 For a reg that has a reg_equiv_address, all those insns
1145 were changed by reloading so that no insns refer to it any longer;
1146 but the DECL_RTL of a variable decl may refer to it,
1147 and if so this causes the debugging info to mention the variable. */
1149 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1153 if (reg_equiv_mem[i])
1154 addr = XEXP (reg_equiv_mem[i], 0);
1156 if (reg_equiv_address[i])
1157 addr = reg_equiv_address[i];
1161 if (reg_renumber[i] < 0)
1163 rtx reg = regno_reg_rtx[i];
1165 REG_USERVAR_P (reg) = 0;
1166 PUT_CODE (reg, MEM);
1167 XEXP (reg, 0) = addr;
1168 if (reg_equiv_memory_loc[i])
1169 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1172 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1173 = MEM_SCALAR_P (reg) = 0;
1174 MEM_ATTRS (reg) = 0;
1177 else if (reg_equiv_mem[i])
1178 XEXP (reg_equiv_mem[i], 0) = addr;
1182 /* We must set reload_completed now since the cleanup_subreg_operands call
1183 below will re-recognize each insn and reload may have generated insns
1184 which are only valid during and after reload. */
1185 reload_completed = 1;
1187 /* Make a pass over all the insns and delete all USEs which we inserted
1188 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1189 notes. Delete all CLOBBER insns, except those that refer to the return
1190 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1191 from misarranging variable-array code, and simplify (subreg (reg))
1192 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1193 are no longer useful or accurate. Strip and regenerate REG_INC notes
1194 that may have been moved around. */
1196 for (insn = first; insn; insn = NEXT_INSN (insn))
1201 if (GET_CODE (insn) == CALL_INSN)
1202 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1204 CALL_INSN_FUNCTION_USAGE (insn));
1206 if ((GET_CODE (PATTERN (insn)) == USE
1207 /* We mark with QImode USEs introduced by reload itself. */
1208 && (GET_MODE (insn) == QImode
1209 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1210 || (GET_CODE (PATTERN (insn)) == CLOBBER
1211 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1212 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1213 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1214 && XEXP (XEXP (PATTERN (insn), 0), 0)
1215 != stack_pointer_rtx))
1216 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1217 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1223 pnote = ®_NOTES (insn);
1226 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1227 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1228 || REG_NOTE_KIND (*pnote) == REG_INC
1229 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1230 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1231 *pnote = XEXP (*pnote, 1);
1233 pnote = &XEXP (*pnote, 1);
1237 add_auto_inc_notes (insn, PATTERN (insn));
1240 /* And simplify (subreg (reg)) if it appears as an operand. */
1241 cleanup_subreg_operands (insn);
1244 /* If we are doing stack checking, give a warning if this function's
1245 frame size is larger than we expect. */
1246 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1248 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1249 static int verbose_warned = 0;
1251 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1252 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1253 size += UNITS_PER_WORD;
1255 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1257 warning ("frame size too large for reliable stack checking");
1258 if (! verbose_warned)
1260 warning ("try reducing the number of local variables");
1266 /* Indicate that we no longer have known memory locations or constants. */
1267 if (reg_equiv_constant)
1268 free (reg_equiv_constant);
1269 reg_equiv_constant = 0;
1270 if (reg_equiv_memory_loc)
1271 free (reg_equiv_memory_loc);
1272 reg_equiv_memory_loc = 0;
1275 free (real_known_ptr);
1279 free (reg_equiv_mem);
1280 free (reg_equiv_init);
1281 free (reg_equiv_address);
1282 free (reg_max_ref_width);
1283 free (reg_old_renumber);
1284 free (pseudo_previous_regs);
1285 free (pseudo_forbidden_regs);
1287 CLEAR_HARD_REG_SET (used_spill_regs);
1288 for (i = 0; i < n_spills; i++)
1289 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1291 /* Free all the insn_chain structures at once. */
1292 obstack_free (&reload_obstack, reload_startobj);
1293 unused_insn_chains = 0;
1294 fixup_abnormal_edges ();
1296 /* Replacing pseudos with their memory equivalents might have
1297 created shared rtx. Subsequent passes would get confused
1298 by this, so unshare everything here. */
1299 unshare_all_rtl_again (first);
1304 /* Yet another special case. Unfortunately, reg-stack forces people to
1305 write incorrect clobbers in asm statements. These clobbers must not
1306 cause the register to appear in bad_spill_regs, otherwise we'll call
1307 fatal_insn later. We clear the corresponding regnos in the live
1308 register sets to avoid this.
1309 The whole thing is rather sick, I'm afraid. */
1312 maybe_fix_stack_asms ()
1315 const char *constraints[MAX_RECOG_OPERANDS];
1316 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1317 struct insn_chain *chain;
1319 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1322 HARD_REG_SET clobbered, allowed;
1325 if (! INSN_P (chain->insn)
1326 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1328 pat = PATTERN (chain->insn);
1329 if (GET_CODE (pat) != PARALLEL)
1332 CLEAR_HARD_REG_SET (clobbered);
1333 CLEAR_HARD_REG_SET (allowed);
1335 /* First, make a mask of all stack regs that are clobbered. */
1336 for (i = 0; i < XVECLEN (pat, 0); i++)
1338 rtx t = XVECEXP (pat, 0, i);
1339 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1340 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1343 /* Get the operand values and constraints out of the insn. */
1344 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1345 constraints, operand_mode);
1347 /* For every operand, see what registers are allowed. */
1348 for (i = 0; i < noperands; i++)
1350 const char *p = constraints[i];
1351 /* For every alternative, we compute the class of registers allowed
1352 for reloading in CLS, and merge its contents into the reg set
1354 int cls = (int) NO_REGS;
1360 if (c == '\0' || c == ',' || c == '#')
1362 /* End of one alternative - mark the regs in the current
1363 class, and reset the class. */
1364 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1369 } while (c != '\0' && c != ',');
1377 case '=': case '+': case '*': case '%': case '?': case '!':
1378 case '0': case '1': case '2': case '3': case '4': case 'm':
1379 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1380 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1381 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1386 cls = (int) reg_class_subunion[cls]
1387 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1392 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1396 if (EXTRA_ADDRESS_CONSTRAINT (c))
1397 cls = (int) reg_class_subunion[cls]
1398 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1400 cls = (int) reg_class_subunion[cls]
1401 [(int) REG_CLASS_FROM_LETTER (c)];
1405 /* Those of the registers which are clobbered, but allowed by the
1406 constraints, must be usable as reload registers. So clear them
1407 out of the life information. */
1408 AND_HARD_REG_SET (allowed, clobbered);
1409 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1410 if (TEST_HARD_REG_BIT (allowed, i))
1412 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1413 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1420 /* Copy the global variables n_reloads and rld into the corresponding elts
1423 copy_reloads (chain)
1424 struct insn_chain *chain;
1426 chain->n_reloads = n_reloads;
1428 = (struct reload *) obstack_alloc (&reload_obstack,
1429 n_reloads * sizeof (struct reload));
1430 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1431 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1434 /* Walk the chain of insns, and determine for each whether it needs reloads
1435 and/or eliminations. Build the corresponding insns_need_reload list, and
1436 set something_needs_elimination as appropriate. */
1438 calculate_needs_all_insns (global)
1441 struct insn_chain **pprev_reload = &insns_need_reload;
1442 struct insn_chain *chain, *next = 0;
1444 something_needs_elimination = 0;
1446 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1447 for (chain = reload_insn_chain; chain != 0; chain = next)
1449 rtx insn = chain->insn;
1453 /* Clear out the shortcuts. */
1454 chain->n_reloads = 0;
1455 chain->need_elim = 0;
1456 chain->need_reload = 0;
1457 chain->need_operand_change = 0;
1459 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1460 include REG_LABEL), we need to see what effects this has on the
1461 known offsets at labels. */
1463 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1464 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1465 set_label_offsets (insn, insn, 0);
1469 rtx old_body = PATTERN (insn);
1470 int old_code = INSN_CODE (insn);
1471 rtx old_notes = REG_NOTES (insn);
1472 int did_elimination = 0;
1473 int operands_changed = 0;
1474 rtx set = single_set (insn);
1476 /* Skip insns that only set an equivalence. */
1477 if (set && GET_CODE (SET_DEST (set)) == REG
1478 && reg_renumber[REGNO (SET_DEST (set))] < 0
1479 && reg_equiv_constant[REGNO (SET_DEST (set))])
1482 /* If needed, eliminate any eliminable registers. */
1483 if (num_eliminable || num_eliminable_invariants)
1484 did_elimination = eliminate_regs_in_insn (insn, 0);
1486 /* Analyze the instruction. */
1487 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1488 global, spill_reg_order);
1490 /* If a no-op set needs more than one reload, this is likely
1491 to be something that needs input address reloads. We
1492 can't get rid of this cleanly later, and it is of no use
1493 anyway, so discard it now.
1494 We only do this when expensive_optimizations is enabled,
1495 since this complements reload inheritance / output
1496 reload deletion, and it can make debugging harder. */
1497 if (flag_expensive_optimizations && n_reloads > 1)
1499 rtx set = single_set (insn);
1501 && SET_SRC (set) == SET_DEST (set)
1502 && GET_CODE (SET_SRC (set)) == REG
1503 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1506 /* Delete it from the reload chain. */
1508 chain->prev->next = next;
1510 reload_insn_chain = next;
1512 next->prev = chain->prev;
1513 chain->next = unused_insn_chains;
1514 unused_insn_chains = chain;
1519 update_eliminable_offsets ();
1521 /* Remember for later shortcuts which insns had any reloads or
1522 register eliminations. */
1523 chain->need_elim = did_elimination;
1524 chain->need_reload = n_reloads > 0;
1525 chain->need_operand_change = operands_changed;
1527 /* Discard any register replacements done. */
1528 if (did_elimination)
1530 obstack_free (&reload_obstack, reload_insn_firstobj);
1531 PATTERN (insn) = old_body;
1532 INSN_CODE (insn) = old_code;
1533 REG_NOTES (insn) = old_notes;
1534 something_needs_elimination = 1;
1537 something_needs_operands_changed |= operands_changed;
1541 copy_reloads (chain);
1542 *pprev_reload = chain;
1543 pprev_reload = &chain->next_need_reload;
1550 /* Comparison function for qsort to decide which of two reloads
1551 should be handled first. *P1 and *P2 are the reload numbers. */
1554 reload_reg_class_lower (r1p, r2p)
1558 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1561 /* Consider required reloads before optional ones. */
1562 t = rld[r1].optional - rld[r2].optional;
1566 /* Count all solitary classes before non-solitary ones. */
1567 t = ((reg_class_size[(int) rld[r2].class] == 1)
1568 - (reg_class_size[(int) rld[r1].class] == 1));
1572 /* Aside from solitaires, consider all multi-reg groups first. */
1573 t = rld[r2].nregs - rld[r1].nregs;
1577 /* Consider reloads in order of increasing reg-class number. */
1578 t = (int) rld[r1].class - (int) rld[r2].class;
1582 /* If reloads are equally urgent, sort by reload number,
1583 so that the results of qsort leave nothing to chance. */
1587 /* The cost of spilling each hard reg. */
1588 static int spill_cost[FIRST_PSEUDO_REGISTER];
1590 /* When spilling multiple hard registers, we use SPILL_COST for the first
1591 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1592 only the first hard reg for a multi-reg pseudo. */
1593 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1595 /* Update the spill cost arrays, considering that pseudo REG is live. */
1601 int freq = REG_FREQ (reg);
1602 int r = reg_renumber[reg];
1605 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1606 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1609 SET_REGNO_REG_SET (&pseudos_counted, reg);
1614 spill_add_cost[r] += freq;
1616 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1618 spill_cost[r + nregs] += freq;
1621 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1622 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1625 order_regs_for_reload (chain)
1626 struct insn_chain *chain;
1629 HARD_REG_SET used_by_pseudos;
1630 HARD_REG_SET used_by_pseudos2;
1632 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1634 memset (spill_cost, 0, sizeof spill_cost);
1635 memset (spill_add_cost, 0, sizeof spill_add_cost);
1637 /* Count number of uses of each hard reg by pseudo regs allocated to it
1638 and then order them by decreasing use. First exclude hard registers
1639 that are live in or across this insn. */
1641 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1642 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1643 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1644 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1646 /* Now find out which pseudos are allocated to it, and update
1648 CLEAR_REG_SET (&pseudos_counted);
1650 EXECUTE_IF_SET_IN_REG_SET
1651 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1655 EXECUTE_IF_SET_IN_REG_SET
1656 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1660 CLEAR_REG_SET (&pseudos_counted);
1663 /* Vector of reload-numbers showing the order in which the reloads should
1665 static short reload_order[MAX_RELOADS];
1667 /* This is used to keep track of the spill regs used in one insn. */
1668 static HARD_REG_SET used_spill_regs_local;
1670 /* We decided to spill hard register SPILLED, which has a size of
1671 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1672 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1673 update SPILL_COST/SPILL_ADD_COST. */
1676 count_spilled_pseudo (spilled, spilled_nregs, reg)
1677 int spilled, spilled_nregs, reg;
1679 int r = reg_renumber[reg];
1680 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1682 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1683 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1686 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1688 spill_add_cost[r] -= REG_FREQ (reg);
1690 spill_cost[r + nregs] -= REG_FREQ (reg);
1693 /* Find reload register to use for reload number ORDER. */
1696 find_reg (chain, order)
1697 struct insn_chain *chain;
1700 int rnum = reload_order[order];
1701 struct reload *rl = rld + rnum;
1702 int best_cost = INT_MAX;
1706 HARD_REG_SET not_usable;
1707 HARD_REG_SET used_by_other_reload;
1709 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1710 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1711 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1713 CLEAR_HARD_REG_SET (used_by_other_reload);
1714 for (k = 0; k < order; k++)
1716 int other = reload_order[k];
1718 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1719 for (j = 0; j < rld[other].nregs; j++)
1720 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1723 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1725 unsigned int regno = i;
1727 if (! TEST_HARD_REG_BIT (not_usable, regno)
1728 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1729 && HARD_REGNO_MODE_OK (regno, rl->mode))
1731 int this_cost = spill_cost[regno];
1733 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1735 for (j = 1; j < this_nregs; j++)
1737 this_cost += spill_add_cost[regno + j];
1738 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1739 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1744 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1746 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1748 if (this_cost < best_cost
1749 /* Among registers with equal cost, prefer caller-saved ones, or
1750 use REG_ALLOC_ORDER if it is defined. */
1751 || (this_cost == best_cost
1752 #ifdef REG_ALLOC_ORDER
1753 && (inv_reg_alloc_order[regno]
1754 < inv_reg_alloc_order[best_reg])
1756 && call_used_regs[regno]
1757 && ! call_used_regs[best_reg]
1762 best_cost = this_cost;
1770 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1772 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1773 rl->regno = best_reg;
1775 EXECUTE_IF_SET_IN_REG_SET
1776 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1778 count_spilled_pseudo (best_reg, rl->nregs, j);
1781 EXECUTE_IF_SET_IN_REG_SET
1782 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1784 count_spilled_pseudo (best_reg, rl->nregs, j);
1787 for (i = 0; i < rl->nregs; i++)
1789 if (spill_cost[best_reg + i] != 0
1790 || spill_add_cost[best_reg + i] != 0)
1792 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1797 /* Find more reload regs to satisfy the remaining need of an insn, which
1799 Do it by ascending class number, since otherwise a reg
1800 might be spilled for a big class and might fail to count
1801 for a smaller class even though it belongs to that class. */
1804 find_reload_regs (chain)
1805 struct insn_chain *chain;
1809 /* In order to be certain of getting the registers we need,
1810 we must sort the reloads into order of increasing register class.
1811 Then our grabbing of reload registers will parallel the process
1812 that provided the reload registers. */
1813 for (i = 0; i < chain->n_reloads; i++)
1815 /* Show whether this reload already has a hard reg. */
1816 if (chain->rld[i].reg_rtx)
1818 int regno = REGNO (chain->rld[i].reg_rtx);
1819 chain->rld[i].regno = regno;
1821 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1824 chain->rld[i].regno = -1;
1825 reload_order[i] = i;
1828 n_reloads = chain->n_reloads;
1829 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1831 CLEAR_HARD_REG_SET (used_spill_regs_local);
1834 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1836 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1838 /* Compute the order of preference for hard registers to spill. */
1840 order_regs_for_reload (chain);
1842 for (i = 0; i < n_reloads; i++)
1844 int r = reload_order[i];
1846 /* Ignore reloads that got marked inoperative. */
1847 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1848 && ! rld[r].optional
1849 && rld[r].regno == -1)
1850 if (! find_reg (chain, i))
1852 spill_failure (chain->insn, rld[r].class);
1858 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1859 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1861 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1865 select_reload_regs ()
1867 struct insn_chain *chain;
1869 /* Try to satisfy the needs for each insn. */
1870 for (chain = insns_need_reload; chain != 0;
1871 chain = chain->next_need_reload)
1872 find_reload_regs (chain);
1875 /* Delete all insns that were inserted by emit_caller_save_insns during
1878 delete_caller_save_insns ()
1880 struct insn_chain *c = reload_insn_chain;
1884 while (c != 0 && c->is_caller_save_insn)
1886 struct insn_chain *next = c->next;
1889 if (c == reload_insn_chain)
1890 reload_insn_chain = next;
1894 next->prev = c->prev;
1896 c->prev->next = next;
1897 c->next = unused_insn_chains;
1898 unused_insn_chains = c;
1906 /* Handle the failure to find a register to spill.
1907 INSN should be one of the insns which needed this particular spill reg. */
1910 spill_failure (insn, class)
1912 enum reg_class class;
1914 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1915 if (asm_noperands (PATTERN (insn)) >= 0)
1916 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1917 reg_class_names[class]);
1920 error ("unable to find a register to spill in class `%s'",
1921 reg_class_names[class]);
1922 fatal_insn ("this is the insn:", insn);
1926 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1927 data that is dead in INSN. */
1930 delete_dead_insn (insn)
1933 rtx prev = prev_real_insn (insn);
1936 /* If the previous insn sets a register that dies in our insn, delete it
1938 if (prev && GET_CODE (PATTERN (prev)) == SET
1939 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1940 && reg_mentioned_p (prev_dest, PATTERN (insn))
1941 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1942 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1943 delete_dead_insn (prev);
1945 PUT_CODE (insn, NOTE);
1946 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1947 NOTE_SOURCE_FILE (insn) = 0;
1950 /* Modify the home of pseudo-reg I.
1951 The new home is present in reg_renumber[I].
1953 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1954 or it may be -1, meaning there is none or it is not relevant.
1955 This is used so that all pseudos spilled from a given hard reg
1956 can share one stack slot. */
1959 alter_reg (i, from_reg)
1963 /* When outputting an inline function, this can happen
1964 for a reg that isn't actually used. */
1965 if (regno_reg_rtx[i] == 0)
1968 /* If the reg got changed to a MEM at rtl-generation time,
1970 if (GET_CODE (regno_reg_rtx[i]) != REG)
1973 /* Modify the reg-rtx to contain the new hard reg
1974 number or else to contain its pseudo reg number. */
1975 REGNO (regno_reg_rtx[i])
1976 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1978 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1979 allocate a stack slot for it. */
1981 if (reg_renumber[i] < 0
1982 && REG_N_REFS (i) > 0
1983 && reg_equiv_constant[i] == 0
1984 && reg_equiv_memory_loc[i] == 0)
1987 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1988 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1991 /* Each pseudo reg has an inherent size which comes from its own mode,
1992 and a total size which provides room for paradoxical subregs
1993 which refer to the pseudo reg in wider modes.
1995 We can use a slot already allocated if it provides both
1996 enough inherent space and enough total space.
1997 Otherwise, we allocate a new slot, making sure that it has no less
1998 inherent space, and no less total space, then the previous slot. */
2001 /* No known place to spill from => no slot to reuse. */
2002 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2003 inherent_size == total_size ? 0 : -1);
2004 if (BYTES_BIG_ENDIAN)
2005 /* Cancel the big-endian correction done in assign_stack_local.
2006 Get the address of the beginning of the slot.
2007 This is so we can do a big-endian correction unconditionally
2009 adjust = inherent_size - total_size;
2011 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2013 /* Nothing can alias this slot except this pseudo. */
2014 set_mem_alias_set (x, new_alias_set ());
2017 /* Reuse a stack slot if possible. */
2018 else if (spill_stack_slot[from_reg] != 0
2019 && spill_stack_slot_width[from_reg] >= total_size
2020 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2022 x = spill_stack_slot[from_reg];
2024 /* Allocate a bigger slot. */
2027 /* Compute maximum size needed, both for inherent size
2028 and for total size. */
2029 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2032 if (spill_stack_slot[from_reg])
2034 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2036 mode = GET_MODE (spill_stack_slot[from_reg]);
2037 if (spill_stack_slot_width[from_reg] > total_size)
2038 total_size = spill_stack_slot_width[from_reg];
2041 /* Make a slot with that size. */
2042 x = assign_stack_local (mode, total_size,
2043 inherent_size == total_size ? 0 : -1);
2046 /* All pseudos mapped to this slot can alias each other. */
2047 if (spill_stack_slot[from_reg])
2048 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2050 set_mem_alias_set (x, new_alias_set ());
2052 if (BYTES_BIG_ENDIAN)
2054 /* Cancel the big-endian correction done in assign_stack_local.
2055 Get the address of the beginning of the slot.
2056 This is so we can do a big-endian correction unconditionally
2058 adjust = GET_MODE_SIZE (mode) - total_size;
2061 = adjust_address_nv (x, mode_for_size (total_size
2067 spill_stack_slot[from_reg] = stack_slot;
2068 spill_stack_slot_width[from_reg] = total_size;
2071 /* On a big endian machine, the "address" of the slot
2072 is the address of the low part that fits its inherent mode. */
2073 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2074 adjust += (total_size - inherent_size);
2076 /* If we have any adjustment to make, or if the stack slot is the
2077 wrong mode, make a new stack slot. */
2078 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2080 /* If we have a decl for the original register, set it for the
2081 memory. If this is a shared MEM, make a copy. */
2084 rtx decl = DECL_RTL_IF_SET (REGNO_DECL (i));
2086 /* We can do this only for the DECLs home pseudo, not for
2087 any copies of it, since otherwise when the stack slot
2088 is reused, nonoverlapping_memrefs_p might think they
2090 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2092 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2095 set_mem_expr (x, REGNO_DECL (i));
2099 /* Save the stack slot for later. */
2100 reg_equiv_memory_loc[i] = x;
2104 /* Mark the slots in regs_ever_live for the hard regs
2105 used by pseudo-reg number REGNO. */
2108 mark_home_live (regno)
2113 i = reg_renumber[regno];
2116 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2118 regs_ever_live[i++] = 1;
2121 /* This function handles the tracking of elimination offsets around branches.
2123 X is a piece of RTL being scanned.
2125 INSN is the insn that it came from, if any.
2127 INITIAL_P is nonzero if we are to set the offset to be the initial
2128 offset and zero if we are setting the offset of the label to be the
2132 set_label_offsets (x, insn, initial_p)
2137 enum rtx_code code = GET_CODE (x);
2140 struct elim_table *p;
2145 if (LABEL_REF_NONLOCAL_P (x))
2150 /* ... fall through ... */
2153 /* If we know nothing about this label, set the desired offsets. Note
2154 that this sets the offset at a label to be the offset before a label
2155 if we don't know anything about the label. This is not correct for
2156 the label after a BARRIER, but is the best guess we can make. If
2157 we guessed wrong, we will suppress an elimination that might have
2158 been possible had we been able to guess correctly. */
2160 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2162 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2163 offsets_at[CODE_LABEL_NUMBER (x)][i]
2164 = (initial_p ? reg_eliminate[i].initial_offset
2165 : reg_eliminate[i].offset);
2166 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2169 /* Otherwise, if this is the definition of a label and it is
2170 preceded by a BARRIER, set our offsets to the known offset of
2174 && (tem = prev_nonnote_insn (insn)) != 0
2175 && GET_CODE (tem) == BARRIER)
2176 set_offsets_for_label (insn);
2178 /* If neither of the above cases is true, compare each offset
2179 with those previously recorded and suppress any eliminations
2180 where the offsets disagree. */
2182 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2183 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2184 != (initial_p ? reg_eliminate[i].initial_offset
2185 : reg_eliminate[i].offset))
2186 reg_eliminate[i].can_eliminate = 0;
2191 set_label_offsets (PATTERN (insn), insn, initial_p);
2193 /* ... fall through ... */
2197 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2198 and hence must have all eliminations at their initial offsets. */
2199 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2200 if (REG_NOTE_KIND (tem) == REG_LABEL)
2201 set_label_offsets (XEXP (tem, 0), insn, 1);
2207 /* Each of the labels in the parallel or address vector must be
2208 at their initial offsets. We want the first field for PARALLEL
2209 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2211 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2212 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2217 /* We only care about setting PC. If the source is not RETURN,
2218 IF_THEN_ELSE, or a label, disable any eliminations not at
2219 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2220 isn't one of those possibilities. For branches to a label,
2221 call ourselves recursively.
2223 Note that this can disable elimination unnecessarily when we have
2224 a non-local goto since it will look like a non-constant jump to
2225 someplace in the current function. This isn't a significant
2226 problem since such jumps will normally be when all elimination
2227 pairs are back to their initial offsets. */
2229 if (SET_DEST (x) != pc_rtx)
2232 switch (GET_CODE (SET_SRC (x)))
2239 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2243 tem = XEXP (SET_SRC (x), 1);
2244 if (GET_CODE (tem) == LABEL_REF)
2245 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2246 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2249 tem = XEXP (SET_SRC (x), 2);
2250 if (GET_CODE (tem) == LABEL_REF)
2251 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2252 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2260 /* If we reach here, all eliminations must be at their initial
2261 offset because we are doing a jump to a variable address. */
2262 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2263 if (p->offset != p->initial_offset)
2264 p->can_eliminate = 0;
2272 /* Scan X and replace any eliminable registers (such as fp) with a
2273 replacement (such as sp), plus an offset.
2275 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2276 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2277 MEM, we are allowed to replace a sum of a register and the constant zero
2278 with the register, which we cannot do outside a MEM. In addition, we need
2279 to record the fact that a register is referenced outside a MEM.
2281 If INSN is an insn, it is the insn containing X. If we replace a REG
2282 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2283 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2284 the REG is being modified.
2286 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2287 That's used when we eliminate in expressions stored in notes.
2288 This means, do not set ref_outside_mem even if the reference
2291 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2292 replacements done assuming all offsets are at their initial values. If
2293 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2294 encounter, return the actual location so that find_reloads will do
2295 the proper thing. */
2298 eliminate_regs (x, mem_mode, insn)
2300 enum machine_mode mem_mode;
2303 enum rtx_code code = GET_CODE (x);
2304 struct elim_table *ep;
2311 if (! current_function_decl)
2331 /* This is only for the benefit of the debugging backends, which call
2332 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2333 removed after CSE. */
2334 new = eliminate_regs (XEXP (x, 0), 0, insn);
2335 if (GET_CODE (new) == MEM)
2336 return XEXP (new, 0);
2342 /* First handle the case where we encounter a bare register that
2343 is eliminable. Replace it with a PLUS. */
2344 if (regno < FIRST_PSEUDO_REGISTER)
2346 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2348 if (ep->from_rtx == x && ep->can_eliminate)
2349 return plus_constant (ep->to_rtx, ep->previous_offset);
2352 else if (reg_renumber && reg_renumber[regno] < 0
2353 && reg_equiv_constant && reg_equiv_constant[regno]
2354 && ! CONSTANT_P (reg_equiv_constant[regno]))
2355 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2359 /* You might think handling MINUS in a manner similar to PLUS is a
2360 good idea. It is not. It has been tried multiple times and every
2361 time the change has had to have been reverted.
2363 Other parts of reload know a PLUS is special (gen_reload for example)
2364 and require special code to handle code a reloaded PLUS operand.
2366 Also consider backends where the flags register is clobbered by a
2367 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2368 lea instruction comes to mind). If we try to reload a MINUS, we
2369 may kill the flags register that was holding a useful value.
2371 So, please before trying to handle MINUS, consider reload as a
2372 whole instead of this little section as well as the backend issues. */
2374 /* If this is the sum of an eliminable register and a constant, rework
2376 if (GET_CODE (XEXP (x, 0)) == REG
2377 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2378 && CONSTANT_P (XEXP (x, 1)))
2380 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2382 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2384 /* The only time we want to replace a PLUS with a REG (this
2385 occurs when the constant operand of the PLUS is the negative
2386 of the offset) is when we are inside a MEM. We won't want
2387 to do so at other times because that would change the
2388 structure of the insn in a way that reload can't handle.
2389 We special-case the commonest situation in
2390 eliminate_regs_in_insn, so just replace a PLUS with a
2391 PLUS here, unless inside a MEM. */
2392 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2393 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2396 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2397 plus_constant (XEXP (x, 1),
2398 ep->previous_offset));
2401 /* If the register is not eliminable, we are done since the other
2402 operand is a constant. */
2406 /* If this is part of an address, we want to bring any constant to the
2407 outermost PLUS. We will do this by doing register replacement in
2408 our operands and seeing if a constant shows up in one of them.
2410 Note that there is no risk of modifying the structure of the insn,
2411 since we only get called for its operands, thus we are either
2412 modifying the address inside a MEM, or something like an address
2413 operand of a load-address insn. */
2416 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2417 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2419 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2421 /* If one side is a PLUS and the other side is a pseudo that
2422 didn't get a hard register but has a reg_equiv_constant,
2423 we must replace the constant here since it may no longer
2424 be in the position of any operand. */
2425 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2426 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2427 && reg_renumber[REGNO (new1)] < 0
2428 && reg_equiv_constant != 0
2429 && reg_equiv_constant[REGNO (new1)] != 0)
2430 new1 = reg_equiv_constant[REGNO (new1)];
2431 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2432 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2433 && reg_renumber[REGNO (new0)] < 0
2434 && reg_equiv_constant[REGNO (new0)] != 0)
2435 new0 = reg_equiv_constant[REGNO (new0)];
2437 new = form_sum (new0, new1);
2439 /* As above, if we are not inside a MEM we do not want to
2440 turn a PLUS into something else. We might try to do so here
2441 for an addition of 0 if we aren't optimizing. */
2442 if (! mem_mode && GET_CODE (new) != PLUS)
2443 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2451 /* If this is the product of an eliminable register and a
2452 constant, apply the distribute law and move the constant out
2453 so that we have (plus (mult ..) ..). This is needed in order
2454 to keep load-address insns valid. This case is pathological.
2455 We ignore the possibility of overflow here. */
2456 if (GET_CODE (XEXP (x, 0)) == REG
2457 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2458 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2459 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2461 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2464 /* Refs inside notes don't count for this purpose. */
2465 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2466 || GET_CODE (insn) == INSN_LIST)))
2467 ep->ref_outside_mem = 1;
2470 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2471 ep->previous_offset * INTVAL (XEXP (x, 1)));
2474 /* ... fall through ... */
2478 /* See comments before PLUS about handling MINUS. */
2480 case DIV: case UDIV:
2481 case MOD: case UMOD:
2482 case AND: case IOR: case XOR:
2483 case ROTATERT: case ROTATE:
2484 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2486 case GE: case GT: case GEU: case GTU:
2487 case LE: case LT: case LEU: case LTU:
2489 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2491 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2493 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2494 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2499 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2502 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2503 if (new != XEXP (x, 0))
2505 /* If this is a REG_DEAD note, it is not valid anymore.
2506 Using the eliminated version could result in creating a
2507 REG_DEAD note for the stack or frame pointer. */
2508 if (GET_MODE (x) == REG_DEAD)
2510 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2513 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2517 /* ... fall through ... */
2520 /* Now do eliminations in the rest of the chain. If this was
2521 an EXPR_LIST, this might result in allocating more memory than is
2522 strictly needed, but it simplifies the code. */
2525 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2526 if (new != XEXP (x, 1))
2528 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2536 case STRICT_LOW_PART:
2538 case SIGN_EXTEND: case ZERO_EXTEND:
2539 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2540 case FLOAT: case FIX:
2541 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2545 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2546 if (new != XEXP (x, 0))
2547 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2551 /* Similar to above processing, but preserve SUBREG_BYTE.
2552 Convert (subreg (mem)) to (mem) if not paradoxical.
2553 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2554 pseudo didn't get a hard reg, we must replace this with the
2555 eliminated version of the memory location because push_reloads
2556 may do the replacement in certain circumstances. */
2557 if (GET_CODE (SUBREG_REG (x)) == REG
2558 && (GET_MODE_SIZE (GET_MODE (x))
2559 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2560 && reg_equiv_memory_loc != 0
2561 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2563 new = SUBREG_REG (x);
2566 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2568 if (new != SUBREG_REG (x))
2570 int x_size = GET_MODE_SIZE (GET_MODE (x));
2571 int new_size = GET_MODE_SIZE (GET_MODE (new));
2573 if (GET_CODE (new) == MEM
2574 && ((x_size < new_size
2575 #ifdef WORD_REGISTER_OPERATIONS
2576 /* On these machines, combine can create rtl of the form
2577 (set (subreg:m1 (reg:m2 R) 0) ...)
2578 where m1 < m2, and expects something interesting to
2579 happen to the entire word. Moreover, it will use the
2580 (reg:m2 R) later, expecting all bits to be preserved.
2581 So if the number of words is the same, preserve the
2582 subreg so that push_reloads can see it. */
2583 && ! ((x_size - 1) / UNITS_PER_WORD
2584 == (new_size -1 ) / UNITS_PER_WORD)
2587 || x_size == new_size)
2589 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2591 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2597 /* This is only for the benefit of the debugging backends, which call
2598 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2599 removed after CSE. */
2600 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2601 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2603 /* Our only special processing is to pass the mode of the MEM to our
2604 recursive call and copy the flags. While we are here, handle this
2605 case more efficiently. */
2607 replace_equiv_address_nv (x,
2608 eliminate_regs (XEXP (x, 0),
2609 GET_MODE (x), insn));
2612 /* Handle insn_list USE that a call to a pure function may generate. */
2613 new = eliminate_regs (XEXP (x, 0), 0, insn);
2614 if (new != XEXP (x, 0))
2615 return gen_rtx_USE (GET_MODE (x), new);
2627 /* Process each of our operands recursively. If any have changed, make a
2629 fmt = GET_RTX_FORMAT (code);
2630 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2634 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2635 if (new != XEXP (x, i) && ! copied)
2637 rtx new_x = rtx_alloc (code);
2639 (sizeof (*new_x) - sizeof (new_x->fld)
2640 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2646 else if (*fmt == 'E')
2649 for (j = 0; j < XVECLEN (x, i); j++)
2651 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2652 if (new != XVECEXP (x, i, j) && ! copied_vec)
2654 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2658 rtx new_x = rtx_alloc (code);
2660 (sizeof (*new_x) - sizeof (new_x->fld)
2661 + (sizeof (new_x->fld[0])
2662 * GET_RTX_LENGTH (code))));
2666 XVEC (x, i) = new_v;
2669 XVECEXP (x, i, j) = new;
2677 /* Scan rtx X for modifications of elimination target registers. Update
2678 the table of eliminables to reflect the changed state. MEM_MODE is
2679 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2682 elimination_effects (x, mem_mode)
2684 enum machine_mode mem_mode;
2687 enum rtx_code code = GET_CODE (x);
2688 struct elim_table *ep;
2715 /* First handle the case where we encounter a bare register that
2716 is eliminable. Replace it with a PLUS. */
2717 if (regno < FIRST_PSEUDO_REGISTER)
2719 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2721 if (ep->from_rtx == x && ep->can_eliminate)
2724 ep->ref_outside_mem = 1;
2729 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2730 && reg_equiv_constant[regno]
2731 && ! function_invariant_p (reg_equiv_constant[regno]))
2732 elimination_effects (reg_equiv_constant[regno], mem_mode);
2741 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2742 if (ep->to_rtx == XEXP (x, 0))
2744 int size = GET_MODE_SIZE (mem_mode);
2746 /* If more bytes than MEM_MODE are pushed, account for them. */
2747 #ifdef PUSH_ROUNDING
2748 if (ep->to_rtx == stack_pointer_rtx)
2749 size = PUSH_ROUNDING (size);
2751 if (code == PRE_DEC || code == POST_DEC)
2753 else if (code == PRE_INC || code == POST_INC)
2755 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2756 && GET_CODE (XEXP (x, 1)) == PLUS
2757 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2758 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2759 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2762 /* These two aren't unary operators. */
2763 if (code == POST_MODIFY || code == PRE_MODIFY)
2766 /* Fall through to generic unary operation case. */
2767 case STRICT_LOW_PART:
2769 case SIGN_EXTEND: case ZERO_EXTEND:
2770 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2771 case FLOAT: case FIX:
2772 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2776 elimination_effects (XEXP (x, 0), mem_mode);
2780 if (GET_CODE (SUBREG_REG (x)) == REG
2781 && (GET_MODE_SIZE (GET_MODE (x))
2782 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2783 && reg_equiv_memory_loc != 0
2784 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2787 elimination_effects (SUBREG_REG (x), mem_mode);
2791 /* If using a register that is the source of an eliminate we still
2792 think can be performed, note it cannot be performed since we don't
2793 know how this register is used. */
2794 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2795 if (ep->from_rtx == XEXP (x, 0))
2796 ep->can_eliminate = 0;
2798 elimination_effects (XEXP (x, 0), mem_mode);
2802 /* If clobbering a register that is the replacement register for an
2803 elimination we still think can be performed, note that it cannot
2804 be performed. Otherwise, we need not be concerned about it. */
2805 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2806 if (ep->to_rtx == XEXP (x, 0))
2807 ep->can_eliminate = 0;
2809 elimination_effects (XEXP (x, 0), mem_mode);
2813 /* Check for setting a register that we know about. */
2814 if (GET_CODE (SET_DEST (x)) == REG)
2816 /* See if this is setting the replacement register for an
2819 If DEST is the hard frame pointer, we do nothing because we
2820 assume that all assignments to the frame pointer are for
2821 non-local gotos and are being done at a time when they are valid
2822 and do not disturb anything else. Some machines want to
2823 eliminate a fake argument pointer (or even a fake frame pointer)
2824 with either the real frame or the stack pointer. Assignments to
2825 the hard frame pointer must not prevent this elimination. */
2827 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2829 if (ep->to_rtx == SET_DEST (x)
2830 && SET_DEST (x) != hard_frame_pointer_rtx)
2832 /* If it is being incremented, adjust the offset. Otherwise,
2833 this elimination can't be done. */
2834 rtx src = SET_SRC (x);
2836 if (GET_CODE (src) == PLUS
2837 && XEXP (src, 0) == SET_DEST (x)
2838 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2839 ep->offset -= INTVAL (XEXP (src, 1));
2841 ep->can_eliminate = 0;
2845 elimination_effects (SET_DEST (x), 0);
2846 elimination_effects (SET_SRC (x), 0);
2850 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2853 /* Our only special processing is to pass the mode of the MEM to our
2855 elimination_effects (XEXP (x, 0), GET_MODE (x));
2862 fmt = GET_RTX_FORMAT (code);
2863 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2866 elimination_effects (XEXP (x, i), mem_mode);
2867 else if (*fmt == 'E')
2868 for (j = 0; j < XVECLEN (x, i); j++)
2869 elimination_effects (XVECEXP (x, i, j), mem_mode);
2873 /* Descend through rtx X and verify that no references to eliminable registers
2874 remain. If any do remain, mark the involved register as not
2878 check_eliminable_occurrences (x)
2888 code = GET_CODE (x);
2890 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2892 struct elim_table *ep;
2894 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2895 if (ep->from_rtx == x && ep->can_eliminate)
2896 ep->can_eliminate = 0;
2900 fmt = GET_RTX_FORMAT (code);
2901 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2904 check_eliminable_occurrences (XEXP (x, i));
2905 else if (*fmt == 'E')
2908 for (j = 0; j < XVECLEN (x, i); j++)
2909 check_eliminable_occurrences (XVECEXP (x, i, j));
2914 /* Scan INSN and eliminate all eliminable registers in it.
2916 If REPLACE is nonzero, do the replacement destructively. Also
2917 delete the insn as dead it if it is setting an eliminable register.
2919 If REPLACE is zero, do all our allocations in reload_obstack.
2921 If no eliminations were done and this insn doesn't require any elimination
2922 processing (these are not identical conditions: it might be updating sp,
2923 but not referencing fp; this needs to be seen during reload_as_needed so
2924 that the offset between fp and sp can be taken into consideration), zero
2925 is returned. Otherwise, 1 is returned. */
2928 eliminate_regs_in_insn (insn, replace)
2932 int icode = recog_memoized (insn);
2933 rtx old_body = PATTERN (insn);
2934 int insn_is_asm = asm_noperands (old_body) >= 0;
2935 rtx old_set = single_set (insn);
2939 rtx substed_operand[MAX_RECOG_OPERANDS];
2940 rtx orig_operand[MAX_RECOG_OPERANDS];
2941 struct elim_table *ep;
2943 if (! insn_is_asm && icode < 0)
2945 if (GET_CODE (PATTERN (insn)) == USE
2946 || GET_CODE (PATTERN (insn)) == CLOBBER
2947 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2948 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2949 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2954 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2955 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2957 /* Check for setting an eliminable register. */
2958 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2959 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2961 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2962 /* If this is setting the frame pointer register to the
2963 hardware frame pointer register and this is an elimination
2964 that will be done (tested above), this insn is really
2965 adjusting the frame pointer downward to compensate for
2966 the adjustment done before a nonlocal goto. */
2967 if (ep->from == FRAME_POINTER_REGNUM
2968 && ep->to == HARD_FRAME_POINTER_REGNUM)
2970 rtx base = SET_SRC (old_set);
2971 rtx base_insn = insn;
2974 while (base != ep->to_rtx)
2976 rtx prev_insn, prev_set;
2978 if (GET_CODE (base) == PLUS
2979 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2981 offset += INTVAL (XEXP (base, 1));
2982 base = XEXP (base, 0);
2984 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2985 && (prev_set = single_set (prev_insn)) != 0
2986 && rtx_equal_p (SET_DEST (prev_set), base))
2988 base = SET_SRC (prev_set);
2989 base_insn = prev_insn;
2995 if (base == ep->to_rtx)
2998 = plus_constant (ep->to_rtx, offset - ep->offset);
3000 new_body = old_body;
3003 new_body = copy_insn (old_body);
3004 if (REG_NOTES (insn))
3005 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3007 PATTERN (insn) = new_body;
3008 old_set = single_set (insn);
3010 /* First see if this insn remains valid when we
3011 make the change. If not, keep the INSN_CODE
3012 the same and let reload fit it up. */
3013 validate_change (insn, &SET_SRC (old_set), src, 1);
3014 validate_change (insn, &SET_DEST (old_set),
3016 if (! apply_change_group ())
3018 SET_SRC (old_set) = src;
3019 SET_DEST (old_set) = ep->to_rtx;
3028 /* In this case this insn isn't serving a useful purpose. We
3029 will delete it in reload_as_needed once we know that this
3030 elimination is, in fact, being done.
3032 If REPLACE isn't set, we can't delete this insn, but needn't
3033 process it since it won't be used unless something changes. */
3036 delete_dead_insn (insn);
3044 /* We allow one special case which happens to work on all machines we
3045 currently support: a single set with the source being a PLUS of an
3046 eliminable register and a constant. */
3048 && GET_CODE (SET_DEST (old_set)) == REG
3049 && GET_CODE (SET_SRC (old_set)) == PLUS
3050 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3051 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3052 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3054 rtx reg = XEXP (SET_SRC (old_set), 0);
3055 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3057 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3058 if (ep->from_rtx == reg && ep->can_eliminate)
3060 offset += ep->offset;
3065 /* We assume here that if we need a PARALLEL with
3066 CLOBBERs for this assignment, we can do with the
3067 MATCH_SCRATCHes that add_clobbers allocates.
3068 There's not much we can do if that doesn't work. */
3069 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3073 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3076 rtvec vec = rtvec_alloc (num_clobbers + 1);
3078 vec->elem[0] = PATTERN (insn);
3079 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3080 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3082 if (INSN_CODE (insn) < 0)
3087 new_body = old_body;
3090 new_body = copy_insn (old_body);
3091 if (REG_NOTES (insn))
3092 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3094 PATTERN (insn) = new_body;
3095 old_set = single_set (insn);
3097 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3098 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3101 /* This can't have an effect on elimination offsets, so skip right
3107 /* Determine the effects of this insn on elimination offsets. */
3108 elimination_effects (old_body, 0);
3110 /* Eliminate all eliminable registers occurring in operands that
3111 can be handled by reload. */
3112 extract_insn (insn);
3113 for (i = 0; i < recog_data.n_operands; i++)
3115 orig_operand[i] = recog_data.operand[i];
3116 substed_operand[i] = recog_data.operand[i];
3118 /* For an asm statement, every operand is eliminable. */
3119 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3121 /* Check for setting a register that we know about. */
3122 if (recog_data.operand_type[i] != OP_IN
3123 && GET_CODE (orig_operand[i]) == REG)
3125 /* If we are assigning to a register that can be eliminated, it
3126 must be as part of a PARALLEL, since the code above handles
3127 single SETs. We must indicate that we can no longer
3128 eliminate this reg. */
3129 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3131 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3132 ep->can_eliminate = 0;
3135 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3136 replace ? insn : NULL_RTX);
3137 if (substed_operand[i] != orig_operand[i])
3139 /* Terminate the search in check_eliminable_occurrences at
3141 *recog_data.operand_loc[i] = 0;
3143 /* If an output operand changed from a REG to a MEM and INSN is an
3144 insn, write a CLOBBER insn. */
3145 if (recog_data.operand_type[i] != OP_IN
3146 && GET_CODE (orig_operand[i]) == REG
3147 && GET_CODE (substed_operand[i]) == MEM
3149 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3154 for (i = 0; i < recog_data.n_dups; i++)
3155 *recog_data.dup_loc[i]
3156 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3158 /* If any eliminable remain, they aren't eliminable anymore. */
3159 check_eliminable_occurrences (old_body);
3161 /* Substitute the operands; the new values are in the substed_operand
3163 for (i = 0; i < recog_data.n_operands; i++)
3164 *recog_data.operand_loc[i] = substed_operand[i];
3165 for (i = 0; i < recog_data.n_dups; i++)
3166 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3168 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3169 re-recognize the insn. We do this in case we had a simple addition
3170 but now can do this as a load-address. This saves an insn in this
3172 If re-recognition fails, the old insn code number will still be used,
3173 and some register operands may have changed into PLUS expressions.
3174 These will be handled by find_reloads by loading them into a register
3179 /* If we aren't replacing things permanently and we changed something,
3180 make another copy to ensure that all the RTL is new. Otherwise
3181 things can go wrong if find_reload swaps commutative operands
3182 and one is inside RTL that has been copied while the other is not. */
3183 new_body = old_body;
3186 new_body = copy_insn (old_body);
3187 if (REG_NOTES (insn))
3188 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3190 PATTERN (insn) = new_body;
3192 /* If we had a move insn but now we don't, rerecognize it. This will
3193 cause spurious re-recognition if the old move had a PARALLEL since
3194 the new one still will, but we can't call single_set without
3195 having put NEW_BODY into the insn and the re-recognition won't
3196 hurt in this rare case. */
3197 /* ??? Why this huge if statement - why don't we just rerecognize the
3201 && ((GET_CODE (SET_SRC (old_set)) == REG
3202 && (GET_CODE (new_body) != SET
3203 || GET_CODE (SET_SRC (new_body)) != REG))
3204 /* If this was a load from or store to memory, compare
3205 the MEM in recog_data.operand to the one in the insn.
3206 If they are not equal, then rerecognize the insn. */
3208 && ((GET_CODE (SET_SRC (old_set)) == MEM
3209 && SET_SRC (old_set) != recog_data.operand[1])
3210 || (GET_CODE (SET_DEST (old_set)) == MEM
3211 && SET_DEST (old_set) != recog_data.operand[0])))
3212 /* If this was an add insn before, rerecognize. */
3213 || GET_CODE (SET_SRC (old_set)) == PLUS))
3215 int new_icode = recog (PATTERN (insn), insn, 0);
3217 INSN_CODE (insn) = icode;
3221 /* Restore the old body. If there were any changes to it, we made a copy
3222 of it while the changes were still in place, so we'll correctly return
3223 a modified insn below. */
3226 /* Restore the old body. */
3227 for (i = 0; i < recog_data.n_operands; i++)
3228 *recog_data.operand_loc[i] = orig_operand[i];
3229 for (i = 0; i < recog_data.n_dups; i++)
3230 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3233 /* Update all elimination pairs to reflect the status after the current
3234 insn. The changes we make were determined by the earlier call to
3235 elimination_effects.
3237 We also detect cases where register elimination cannot be done,
3238 namely, if a register would be both changed and referenced outside a MEM
3239 in the resulting insn since such an insn is often undefined and, even if
3240 not, we cannot know what meaning will be given to it. Note that it is
3241 valid to have a register used in an address in an insn that changes it
3242 (presumably with a pre- or post-increment or decrement).
3244 If anything changes, return nonzero. */
3246 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3248 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3249 ep->can_eliminate = 0;
3251 ep->ref_outside_mem = 0;
3253 if (ep->previous_offset != ep->offset)
3258 /* If we changed something, perform elimination in REG_NOTES. This is
3259 needed even when REPLACE is zero because a REG_DEAD note might refer
3260 to a register that we eliminate and could cause a different number
3261 of spill registers to be needed in the final reload pass than in
3263 if (val && REG_NOTES (insn) != 0)
3264 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3269 /* Loop through all elimination pairs.
3270 Recalculate the number not at initial offset.
3272 Compute the maximum offset (minimum offset if the stack does not
3273 grow downward) for each elimination pair. */
3276 update_eliminable_offsets ()
3278 struct elim_table *ep;
3280 num_not_at_initial_offset = 0;
3281 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3283 ep->previous_offset = ep->offset;
3284 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3285 num_not_at_initial_offset++;
3289 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3290 replacement we currently believe is valid, mark it as not eliminable if X
3291 modifies DEST in any way other than by adding a constant integer to it.
3293 If DEST is the frame pointer, we do nothing because we assume that
3294 all assignments to the hard frame pointer are nonlocal gotos and are being
3295 done at a time when they are valid and do not disturb anything else.
3296 Some machines want to eliminate a fake argument pointer with either the
3297 frame or stack pointer. Assignments to the hard frame pointer must not
3298 prevent this elimination.
3300 Called via note_stores from reload before starting its passes to scan
3301 the insns of the function. */
3304 mark_not_eliminable (dest, x, data)
3307 void *data ATTRIBUTE_UNUSED;
3311 /* A SUBREG of a hard register here is just changing its mode. We should
3312 not see a SUBREG of an eliminable hard register, but check just in
3314 if (GET_CODE (dest) == SUBREG)
3315 dest = SUBREG_REG (dest);
3317 if (dest == hard_frame_pointer_rtx)
3320 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3321 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3322 && (GET_CODE (x) != SET
3323 || GET_CODE (SET_SRC (x)) != PLUS
3324 || XEXP (SET_SRC (x), 0) != dest
3325 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3327 reg_eliminate[i].can_eliminate_previous
3328 = reg_eliminate[i].can_eliminate = 0;
3333 /* Verify that the initial elimination offsets did not change since the
3334 last call to set_initial_elim_offsets. This is used to catch cases
3335 where something illegal happened during reload_as_needed that could
3336 cause incorrect code to be generated if we did not check for it. */
3339 verify_initial_elim_offsets ()
3343 #ifdef ELIMINABLE_REGS
3344 struct elim_table *ep;
3346 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3348 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3349 if (t != ep->initial_offset)
3353 INITIAL_FRAME_POINTER_OFFSET (t);
3354 if (t != reg_eliminate[0].initial_offset)
3359 /* Reset all offsets on eliminable registers to their initial values. */
3362 set_initial_elim_offsets ()
3364 struct elim_table *ep = reg_eliminate;
3366 #ifdef ELIMINABLE_REGS
3367 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3369 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3370 ep->previous_offset = ep->offset = ep->initial_offset;
3373 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3374 ep->previous_offset = ep->offset = ep->initial_offset;
3377 num_not_at_initial_offset = 0;
3380 /* Initialize the known label offsets.
3381 Set a known offset for each forced label to be at the initial offset
3382 of each elimination. We do this because we assume that all
3383 computed jumps occur from a location where each elimination is
3384 at its initial offset.
3385 For all other labels, show that we don't know the offsets. */
3388 set_initial_label_offsets ()
3391 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3393 for (x = forced_labels; x; x = XEXP (x, 1))
3395 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3398 /* Set all elimination offsets to the known values for the code label given
3402 set_offsets_for_label (insn)
3406 int label_nr = CODE_LABEL_NUMBER (insn);
3407 struct elim_table *ep;
3409 num_not_at_initial_offset = 0;
3410 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3412 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3413 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3414 num_not_at_initial_offset++;
3418 /* See if anything that happened changes which eliminations are valid.
3419 For example, on the SPARC, whether or not the frame pointer can
3420 be eliminated can depend on what registers have been used. We need
3421 not check some conditions again (such as flag_omit_frame_pointer)
3422 since they can't have changed. */
3425 update_eliminables (pset)
3428 int previous_frame_pointer_needed = frame_pointer_needed;
3429 struct elim_table *ep;
3431 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3432 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3433 #ifdef ELIMINABLE_REGS
3434 || ! CAN_ELIMINATE (ep->from, ep->to)
3437 ep->can_eliminate = 0;
3439 /* Look for the case where we have discovered that we can't replace
3440 register A with register B and that means that we will now be
3441 trying to replace register A with register C. This means we can
3442 no longer replace register C with register B and we need to disable
3443 such an elimination, if it exists. This occurs often with A == ap,
3444 B == sp, and C == fp. */
3446 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3448 struct elim_table *op;
3451 if (! ep->can_eliminate && ep->can_eliminate_previous)
3453 /* Find the current elimination for ep->from, if there is a
3455 for (op = reg_eliminate;
3456 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3457 if (op->from == ep->from && op->can_eliminate)
3463 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3465 for (op = reg_eliminate;
3466 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3467 if (op->from == new_to && op->to == ep->to)
3468 op->can_eliminate = 0;
3472 /* See if any registers that we thought we could eliminate the previous
3473 time are no longer eliminable. If so, something has changed and we
3474 must spill the register. Also, recompute the number of eliminable
3475 registers and see if the frame pointer is needed; it is if there is
3476 no elimination of the frame pointer that we can perform. */
3478 frame_pointer_needed = 1;
3479 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3481 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3482 && ep->to != HARD_FRAME_POINTER_REGNUM)
3483 frame_pointer_needed = 0;
3485 if (! ep->can_eliminate && ep->can_eliminate_previous)
3487 ep->can_eliminate_previous = 0;
3488 SET_HARD_REG_BIT (*pset, ep->from);
3493 /* If we didn't need a frame pointer last time, but we do now, spill
3494 the hard frame pointer. */
3495 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3496 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3499 /* Initialize the table of registers to eliminate. */
3504 struct elim_table *ep;
3505 #ifdef ELIMINABLE_REGS
3506 const struct elim_table_1 *ep1;
3510 reg_eliminate = (struct elim_table *)
3511 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3513 /* Does this function require a frame pointer? */
3515 frame_pointer_needed = (! flag_omit_frame_pointer
3516 #ifdef EXIT_IGNORE_STACK
3517 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3518 and restore sp for alloca. So we can't eliminate
3519 the frame pointer in that case. At some point,
3520 we should improve this by emitting the
3521 sp-adjusting insns for this case. */
3522 || (current_function_calls_alloca
3523 && EXIT_IGNORE_STACK)
3525 || FRAME_POINTER_REQUIRED);
3529 #ifdef ELIMINABLE_REGS
3530 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3531 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3533 ep->from = ep1->from;
3535 ep->can_eliminate = ep->can_eliminate_previous
3536 = (CAN_ELIMINATE (ep->from, ep->to)
3537 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3540 reg_eliminate[0].from = reg_eliminate_1[0].from;
3541 reg_eliminate[0].to = reg_eliminate_1[0].to;
3542 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3543 = ! frame_pointer_needed;
3546 /* Count the number of eliminable registers and build the FROM and TO
3547 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3548 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3549 We depend on this. */
3550 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3552 num_eliminable += ep->can_eliminate;
3553 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3554 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3558 /* Kick all pseudos out of hard register REGNO.
3560 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3561 because we found we can't eliminate some register. In the case, no pseudos
3562 are allowed to be in the register, even if they are only in a block that
3563 doesn't require spill registers, unlike the case when we are spilling this
3564 hard reg to produce another spill register.
3566 Return nonzero if any pseudos needed to be kicked out. */
3569 spill_hard_reg (regno, cant_eliminate)
3577 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3578 regs_ever_live[regno] = 1;
3581 /* Spill every pseudo reg that was allocated to this reg
3582 or to something that overlaps this reg. */
3584 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3585 if (reg_renumber[i] >= 0
3586 && (unsigned int) reg_renumber[i] <= regno
3587 && ((unsigned int) reg_renumber[i]
3588 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3589 PSEUDO_REGNO_MODE (i))
3591 SET_REGNO_REG_SET (&spilled_pseudos, i);
3594 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3595 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3598 ior_hard_reg_set (set1, set2)
3599 HARD_REG_SET *set1, *set2;
3601 IOR_HARD_REG_SET (*set1, *set2);
3604 /* After find_reload_regs has been run for all insn that need reloads,
3605 and/or spill_hard_regs was called, this function is used to actually
3606 spill pseudo registers and try to reallocate them. It also sets up the
3607 spill_regs array for use by choose_reload_regs. */
3610 finish_spills (global)
3613 struct insn_chain *chain;
3614 int something_changed = 0;
3617 /* Build the spill_regs array for the function. */
3618 /* If there are some registers still to eliminate and one of the spill regs
3619 wasn't ever used before, additional stack space may have to be
3620 allocated to store this register. Thus, we may have changed the offset
3621 between the stack and frame pointers, so mark that something has changed.
3623 One might think that we need only set VAL to 1 if this is a call-used
3624 register. However, the set of registers that must be saved by the
3625 prologue is not identical to the call-used set. For example, the
3626 register used by the call insn for the return PC is a call-used register,
3627 but must be saved by the prologue. */
3630 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3631 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3633 spill_reg_order[i] = n_spills;
3634 spill_regs[n_spills++] = i;
3635 if (num_eliminable && ! regs_ever_live[i])
3636 something_changed = 1;
3637 regs_ever_live[i] = 1;
3640 spill_reg_order[i] = -1;
3642 EXECUTE_IF_SET_IN_REG_SET
3643 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3645 /* Record the current hard register the pseudo is allocated to in
3646 pseudo_previous_regs so we avoid reallocating it to the same
3647 hard reg in a later pass. */
3648 if (reg_renumber[i] < 0)
3651 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3652 /* Mark it as no longer having a hard register home. */
3653 reg_renumber[i] = -1;
3654 /* We will need to scan everything again. */
3655 something_changed = 1;
3658 /* Retry global register allocation if possible. */
3661 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3662 /* For every insn that needs reloads, set the registers used as spill
3663 regs in pseudo_forbidden_regs for every pseudo live across the
3665 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3667 EXECUTE_IF_SET_IN_REG_SET
3668 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3670 ior_hard_reg_set (pseudo_forbidden_regs + i,
3671 &chain->used_spill_regs);
3673 EXECUTE_IF_SET_IN_REG_SET
3674 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3676 ior_hard_reg_set (pseudo_forbidden_regs + i,
3677 &chain->used_spill_regs);
3681 /* Retry allocating the spilled pseudos. For each reg, merge the
3682 various reg sets that indicate which hard regs can't be used,
3683 and call retry_global_alloc.
3684 We change spill_pseudos here to only contain pseudos that did not
3685 get a new hard register. */
3686 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3687 if (reg_old_renumber[i] != reg_renumber[i])
3689 HARD_REG_SET forbidden;
3690 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3691 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3692 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3693 retry_global_alloc (i, forbidden);
3694 if (reg_renumber[i] >= 0)
3695 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3699 /* Fix up the register information in the insn chain.
3700 This involves deleting those of the spilled pseudos which did not get
3701 a new hard register home from the live_{before,after} sets. */
3702 for (chain = reload_insn_chain; chain; chain = chain->next)
3704 HARD_REG_SET used_by_pseudos;
3705 HARD_REG_SET used_by_pseudos2;
3707 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3708 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3710 /* Mark any unallocated hard regs as available for spills. That
3711 makes inheritance work somewhat better. */
3712 if (chain->need_reload)
3714 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3715 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3716 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3718 /* Save the old value for the sanity test below. */
3719 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3721 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3722 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3723 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3724 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3726 /* Make sure we only enlarge the set. */
3727 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3733 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3734 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3736 int regno = reg_renumber[i];
3737 if (reg_old_renumber[i] == regno)
3740 alter_reg (i, reg_old_renumber[i]);
3741 reg_old_renumber[i] = regno;
3745 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3747 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3748 i, reg_renumber[i]);
3752 return something_changed;
3755 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3756 Also mark any hard registers used to store user variables as
3757 forbidden from being used for spill registers. */
3760 scan_paradoxical_subregs (x)
3765 enum rtx_code code = GET_CODE (x);
3771 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3772 && REG_USERVAR_P (x))
3773 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3782 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3790 if (GET_CODE (SUBREG_REG (x)) == REG
3791 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3792 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3793 = GET_MODE_SIZE (GET_MODE (x));
3800 fmt = GET_RTX_FORMAT (code);
3801 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3804 scan_paradoxical_subregs (XEXP (x, i));
3805 else if (fmt[i] == 'E')
3808 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3809 scan_paradoxical_subregs (XVECEXP (x, i, j));
3814 /* Reload pseudo-registers into hard regs around each insn as needed.
3815 Additional register load insns are output before the insn that needs it
3816 and perhaps store insns after insns that modify the reloaded pseudo reg.
3818 reg_last_reload_reg and reg_reloaded_contents keep track of
3819 which registers are already available in reload registers.
3820 We update these for the reloads that we perform,
3821 as the insns are scanned. */
3824 reload_as_needed (live_known)
3827 struct insn_chain *chain;
3828 #if defined (AUTO_INC_DEC)
3833 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3834 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3835 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3836 reg_has_output_reload = (char *) xmalloc (max_regno);
3837 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3839 set_initial_elim_offsets ();
3841 for (chain = reload_insn_chain; chain; chain = chain->next)
3844 rtx insn = chain->insn;
3845 rtx old_next = NEXT_INSN (insn);
3847 /* If we pass a label, copy the offsets from the label information
3848 into the current offsets of each elimination. */
3849 if (GET_CODE (insn) == CODE_LABEL)
3850 set_offsets_for_label (insn);
3852 else if (INSN_P (insn))
3854 rtx oldpat = copy_rtx (PATTERN (insn));
3856 /* If this is a USE and CLOBBER of a MEM, ensure that any
3857 references to eliminable registers have been removed. */
3859 if ((GET_CODE (PATTERN (insn)) == USE
3860 || GET_CODE (PATTERN (insn)) == CLOBBER)
3861 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3862 XEXP (XEXP (PATTERN (insn), 0), 0)
3863 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3864 GET_MODE (XEXP (PATTERN (insn), 0)),
3867 /* If we need to do register elimination processing, do so.
3868 This might delete the insn, in which case we are done. */
3869 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3871 eliminate_regs_in_insn (insn, 1);
3872 if (GET_CODE (insn) == NOTE)
3874 update_eliminable_offsets ();
3879 /* If need_elim is nonzero but need_reload is zero, one might think
3880 that we could simply set n_reloads to 0. However, find_reloads
3881 could have done some manipulation of the insn (such as swapping
3882 commutative operands), and these manipulations are lost during
3883 the first pass for every insn that needs register elimination.
3884 So the actions of find_reloads must be redone here. */
3886 if (! chain->need_elim && ! chain->need_reload
3887 && ! chain->need_operand_change)
3889 /* First find the pseudo regs that must be reloaded for this insn.
3890 This info is returned in the tables reload_... (see reload.h).
3891 Also modify the body of INSN by substituting RELOAD
3892 rtx's for those pseudo regs. */
3895 memset (reg_has_output_reload, 0, max_regno);
3896 CLEAR_HARD_REG_SET (reg_is_output_reload);
3898 find_reloads (insn, 1, spill_indirect_levels, live_known,
3904 rtx next = NEXT_INSN (insn);
3907 prev = PREV_INSN (insn);
3909 /* Now compute which reload regs to reload them into. Perhaps
3910 reusing reload regs from previous insns, or else output
3911 load insns to reload them. Maybe output store insns too.
3912 Record the choices of reload reg in reload_reg_rtx. */
3913 choose_reload_regs (chain);
3915 /* Merge any reloads that we didn't combine for fear of
3916 increasing the number of spill registers needed but now
3917 discover can be safely merged. */
3918 if (SMALL_REGISTER_CLASSES)
3919 merge_assigned_reloads (insn);
3921 /* Generate the insns to reload operands into or out of
3922 their reload regs. */
3923 emit_reload_insns (chain);
3925 /* Substitute the chosen reload regs from reload_reg_rtx
3926 into the insn's body (or perhaps into the bodies of other
3927 load and store insn that we just made for reloading
3928 and that we moved the structure into). */
3929 subst_reloads (insn);
3931 /* If this was an ASM, make sure that all the reload insns
3932 we have generated are valid. If not, give an error
3935 if (asm_noperands (PATTERN (insn)) >= 0)
3936 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3937 if (p != insn && INSN_P (p)
3938 && (recog_memoized (p) < 0
3939 || (extract_insn (p), ! constrain_operands (1))))
3941 error_for_asm (insn,
3942 "`asm' operand requires impossible reload");
3947 if (num_eliminable && chain->need_elim)
3948 update_eliminable_offsets ();
3950 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3951 is no longer validly lying around to save a future reload.
3952 Note that this does not detect pseudos that were reloaded
3953 for this insn in order to be stored in
3954 (obeying register constraints). That is correct; such reload
3955 registers ARE still valid. */
3956 note_stores (oldpat, forget_old_reloads_1, NULL);
3958 /* There may have been CLOBBER insns placed after INSN. So scan
3959 between INSN and NEXT and use them to forget old reloads. */
3960 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3961 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3962 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3965 /* Likewise for regs altered by auto-increment in this insn.
3966 REG_INC notes have been changed by reloading:
3967 find_reloads_address_1 records substitutions for them,
3968 which have been performed by subst_reloads above. */
3969 for (i = n_reloads - 1; i >= 0; i--)
3971 rtx in_reg = rld[i].in_reg;
3974 enum rtx_code code = GET_CODE (in_reg);
3975 /* PRE_INC / PRE_DEC will have the reload register ending up
3976 with the same value as the stack slot, but that doesn't
3977 hold true for POST_INC / POST_DEC. Either we have to
3978 convert the memory access to a true POST_INC / POST_DEC,
3979 or we can't use the reload register for inheritance. */
3980 if ((code == POST_INC || code == POST_DEC)
3981 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3982 REGNO (rld[i].reg_rtx))
3983 /* Make sure it is the inc/dec pseudo, and not
3984 some other (e.g. output operand) pseudo. */
3985 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3986 == REGNO (XEXP (in_reg, 0))))
3989 rtx reload_reg = rld[i].reg_rtx;
3990 enum machine_mode mode = GET_MODE (reload_reg);
3994 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3996 /* We really want to ignore REG_INC notes here, so
3997 use PATTERN (p) as argument to reg_set_p . */
3998 if (reg_set_p (reload_reg, PATTERN (p)))
4000 n = count_occurrences (PATTERN (p), reload_reg, 0);
4005 n = validate_replace_rtx (reload_reg,
4006 gen_rtx (code, mode,
4010 /* We must also verify that the constraints
4011 are met after the replacement. */
4014 n = constrain_operands (1);
4018 /* If the constraints were not met, then
4019 undo the replacement. */
4022 validate_replace_rtx (gen_rtx (code, mode,
4034 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4036 /* Mark this as having an output reload so that the
4037 REG_INC processing code below won't invalidate
4038 the reload for inheritance. */
4039 SET_HARD_REG_BIT (reg_is_output_reload,
4040 REGNO (reload_reg));
4041 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4044 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4047 else if ((code == PRE_INC || code == PRE_DEC)
4048 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4049 REGNO (rld[i].reg_rtx))
4050 /* Make sure it is the inc/dec pseudo, and not
4051 some other (e.g. output operand) pseudo. */
4052 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4053 == REGNO (XEXP (in_reg, 0))))
4055 SET_HARD_REG_BIT (reg_is_output_reload,
4056 REGNO (rld[i].reg_rtx));
4057 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4061 /* If a pseudo that got a hard register is auto-incremented,
4062 we must purge records of copying it into pseudos without
4064 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4065 if (REG_NOTE_KIND (x) == REG_INC)
4067 /* See if this pseudo reg was reloaded in this insn.
4068 If so, its last-reload info is still valid
4069 because it is based on this insn's reload. */
4070 for (i = 0; i < n_reloads; i++)
4071 if (rld[i].out == XEXP (x, 0))
4075 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4079 /* A reload reg's contents are unknown after a label. */
4080 if (GET_CODE (insn) == CODE_LABEL)
4081 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4083 /* Don't assume a reload reg is still good after a call insn
4084 if it is a call-used reg. */
4085 else if (GET_CODE (insn) == CALL_INSN)
4086 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4090 free (reg_last_reload_reg);
4091 free (reg_has_output_reload);
4094 /* Discard all record of any value reloaded from X,
4095 or reloaded in X from someplace else;
4096 unless X is an output reload reg of the current insn.
4098 X may be a hard reg (the reload reg)
4099 or it may be a pseudo reg that was reloaded from. */
4102 forget_old_reloads_1 (x, ignored, data)
4104 rtx ignored ATTRIBUTE_UNUSED;
4105 void *data ATTRIBUTE_UNUSED;
4110 /* note_stores does give us subregs of hard regs,
4111 subreg_regno_offset will abort if it is not a hard reg. */
4112 while (GET_CODE (x) == SUBREG)
4114 /* We ignore the subreg offset when calculating the regno,
4115 because we are using the entire underlying hard register
4120 if (GET_CODE (x) != REG)
4125 if (regno >= FIRST_PSEUDO_REGISTER)
4131 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4132 /* Storing into a spilled-reg invalidates its contents.
4133 This can happen if a block-local pseudo is allocated to that reg
4134 and it wasn't spilled because this block's total need is 0.
4135 Then some insn might have an optional reload and use this reg. */
4136 for (i = 0; i < nr; i++)
4137 /* But don't do this if the reg actually serves as an output
4138 reload reg in the current instruction. */
4140 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4142 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4143 spill_reg_store[regno + i] = 0;
4147 /* Since value of X has changed,
4148 forget any value previously copied from it. */
4151 /* But don't forget a copy if this is the output reload
4152 that establishes the copy's validity. */
4153 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4154 reg_last_reload_reg[regno + nr] = 0;
4157 /* The following HARD_REG_SETs indicate when each hard register is
4158 used for a reload of various parts of the current insn. */
4160 /* If reg is unavailable for all reloads. */
4161 static HARD_REG_SET reload_reg_unavailable;
4162 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4163 static HARD_REG_SET reload_reg_used;
4164 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4165 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4166 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4167 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4168 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4169 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4170 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4171 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4172 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4173 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4174 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4175 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4176 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4177 static HARD_REG_SET reload_reg_used_in_op_addr;
4178 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4179 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4180 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4181 static HARD_REG_SET reload_reg_used_in_insn;
4182 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4183 static HARD_REG_SET reload_reg_used_in_other_addr;
4185 /* If reg is in use as a reload reg for any sort of reload. */
4186 static HARD_REG_SET reload_reg_used_at_all;
4188 /* If reg is use as an inherited reload. We just mark the first register
4190 static HARD_REG_SET reload_reg_used_for_inherit;
4192 /* Records which hard regs are used in any way, either as explicit use or
4193 by being allocated to a pseudo during any point of the current insn. */
4194 static HARD_REG_SET reg_used_in_insn;
4196 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4197 TYPE. MODE is used to indicate how many consecutive regs are
4201 mark_reload_reg_in_use (regno, opnum, type, mode)
4204 enum reload_type type;
4205 enum machine_mode mode;
4207 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4210 for (i = regno; i < nregs + regno; i++)
4215 SET_HARD_REG_BIT (reload_reg_used, i);
4218 case RELOAD_FOR_INPUT_ADDRESS:
4219 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4222 case RELOAD_FOR_INPADDR_ADDRESS:
4223 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4226 case RELOAD_FOR_OUTPUT_ADDRESS:
4227 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4230 case RELOAD_FOR_OUTADDR_ADDRESS:
4231 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4234 case RELOAD_FOR_OPERAND_ADDRESS:
4235 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4238 case RELOAD_FOR_OPADDR_ADDR:
4239 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4242 case RELOAD_FOR_OTHER_ADDRESS:
4243 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4246 case RELOAD_FOR_INPUT:
4247 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4250 case RELOAD_FOR_OUTPUT:
4251 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4254 case RELOAD_FOR_INSN:
4255 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4259 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4263 /* Similarly, but show REGNO is no longer in use for a reload. */
4266 clear_reload_reg_in_use (regno, opnum, type, mode)
4269 enum reload_type type;
4270 enum machine_mode mode;
4272 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4273 unsigned int start_regno, end_regno, r;
4275 /* A complication is that for some reload types, inheritance might
4276 allow multiple reloads of the same types to share a reload register.
4277 We set check_opnum if we have to check only reloads with the same
4278 operand number, and check_any if we have to check all reloads. */
4279 int check_opnum = 0;
4281 HARD_REG_SET *used_in_set;
4286 used_in_set = &reload_reg_used;
4289 case RELOAD_FOR_INPUT_ADDRESS:
4290 used_in_set = &reload_reg_used_in_input_addr[opnum];
4293 case RELOAD_FOR_INPADDR_ADDRESS:
4295 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4298 case RELOAD_FOR_OUTPUT_ADDRESS:
4299 used_in_set = &reload_reg_used_in_output_addr[opnum];
4302 case RELOAD_FOR_OUTADDR_ADDRESS:
4304 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4307 case RELOAD_FOR_OPERAND_ADDRESS:
4308 used_in_set = &reload_reg_used_in_op_addr;
4311 case RELOAD_FOR_OPADDR_ADDR:
4313 used_in_set = &reload_reg_used_in_op_addr_reload;
4316 case RELOAD_FOR_OTHER_ADDRESS:
4317 used_in_set = &reload_reg_used_in_other_addr;
4321 case RELOAD_FOR_INPUT:
4322 used_in_set = &reload_reg_used_in_input[opnum];
4325 case RELOAD_FOR_OUTPUT:
4326 used_in_set = &reload_reg_used_in_output[opnum];
4329 case RELOAD_FOR_INSN:
4330 used_in_set = &reload_reg_used_in_insn;
4335 /* We resolve conflicts with remaining reloads of the same type by
4336 excluding the intervals of reload registers by them from the
4337 interval of freed reload registers. Since we only keep track of
4338 one set of interval bounds, we might have to exclude somewhat
4339 more than what would be necessary if we used a HARD_REG_SET here.
4340 But this should only happen very infrequently, so there should
4341 be no reason to worry about it. */
4343 start_regno = regno;
4344 end_regno = regno + nregs;
4345 if (check_opnum || check_any)
4347 for (i = n_reloads - 1; i >= 0; i--)
4349 if (rld[i].when_needed == type
4350 && (check_any || rld[i].opnum == opnum)
4353 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4354 unsigned int conflict_end
4356 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4358 /* If there is an overlap with the first to-be-freed register,
4359 adjust the interval start. */
4360 if (conflict_start <= start_regno && conflict_end > start_regno)
4361 start_regno = conflict_end;
4362 /* Otherwise, if there is a conflict with one of the other
4363 to-be-freed registers, adjust the interval end. */
4364 if (conflict_start > start_regno && conflict_start < end_regno)
4365 end_regno = conflict_start;
4370 for (r = start_regno; r < end_regno; r++)
4371 CLEAR_HARD_REG_BIT (*used_in_set, r);
4374 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4375 specified by OPNUM and TYPE. */
4378 reload_reg_free_p (regno, opnum, type)
4381 enum reload_type type;
4385 /* In use for a RELOAD_OTHER means it's not available for anything. */
4386 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4387 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4393 /* In use for anything means we can't use it for RELOAD_OTHER. */
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4395 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4396 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4399 for (i = 0; i < reload_n_operands; i++)
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4401 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4402 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4403 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4404 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4405 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4410 case RELOAD_FOR_INPUT:
4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4412 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4418 /* If it is used for some other input, can't use it. */
4419 for (i = 0; i < reload_n_operands; i++)
4420 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4423 /* If it is used in a later operand's address, can't use it. */
4424 for (i = opnum + 1; i < reload_n_operands; i++)
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4426 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4431 case RELOAD_FOR_INPUT_ADDRESS:
4432 /* Can't use a register if it is used for an input address for this
4433 operand or used as an input in an earlier one. */
4434 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4435 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4438 for (i = 0; i < opnum; i++)
4439 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4444 case RELOAD_FOR_INPADDR_ADDRESS:
4445 /* Can't use a register if it is used for an input address
4446 for this operand or used as an input in an earlier
4448 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4451 for (i = 0; i < opnum; i++)
4452 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4457 case RELOAD_FOR_OUTPUT_ADDRESS:
4458 /* Can't use a register if it is used for an output address for this
4459 operand or used as an output in this or a later operand. Note
4460 that multiple output operands are emitted in reverse order, so
4461 the conflicting ones are those with lower indices. */
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4465 for (i = 0; i <= opnum; i++)
4466 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4471 case RELOAD_FOR_OUTADDR_ADDRESS:
4472 /* Can't use a register if it is used for an output address
4473 for this operand or used as an output in this or a
4474 later operand. Note that multiple output operands are
4475 emitted in reverse order, so the conflicting ones are
4476 those with lower indices. */
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4480 for (i = 0; i <= opnum; i++)
4481 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4486 case RELOAD_FOR_OPERAND_ADDRESS:
4487 for (i = 0; i < reload_n_operands; i++)
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4491 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4492 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4494 case RELOAD_FOR_OPADDR_ADDR:
4495 for (i = 0; i < reload_n_operands; i++)
4496 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4499 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4501 case RELOAD_FOR_OUTPUT:
4502 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4503 outputs, or an operand address for this or an earlier output.
4504 Note that multiple output operands are emitted in reverse order,
4505 so the conflicting ones are those with higher indices. */
4506 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4509 for (i = 0; i < reload_n_operands; i++)
4510 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4513 for (i = opnum; i < reload_n_operands; i++)
4514 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4520 case RELOAD_FOR_INSN:
4521 for (i = 0; i < reload_n_operands; i++)
4522 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4523 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4526 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4527 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4529 case RELOAD_FOR_OTHER_ADDRESS:
4530 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4535 /* Return 1 if the value in reload reg REGNO, as used by a reload
4536 needed for the part of the insn specified by OPNUM and TYPE,
4537 is still available in REGNO at the end of the insn.
4539 We can assume that the reload reg was already tested for availability
4540 at the time it is needed, and we should not check this again,
4541 in case the reg has already been marked in use. */
4544 reload_reg_reaches_end_p (regno, opnum, type)
4547 enum reload_type type;
4554 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4555 its value must reach the end. */
4558 /* If this use is for part of the insn,
4559 its value reaches if no subsequent part uses the same register.
4560 Just like the above function, don't try to do this with lots
4563 case RELOAD_FOR_OTHER_ADDRESS:
4564 /* Here we check for everything else, since these don't conflict
4565 with anything else and everything comes later. */
4567 for (i = 0; i < reload_n_operands; i++)
4568 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4569 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4573 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4576 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4577 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4578 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4580 case RELOAD_FOR_INPUT_ADDRESS:
4581 case RELOAD_FOR_INPADDR_ADDRESS:
4582 /* Similar, except that we check only for this and subsequent inputs
4583 and the address of only subsequent inputs and we do not need
4584 to check for RELOAD_OTHER objects since they are known not to
4587 for (i = opnum; i < reload_n_operands; i++)
4588 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4591 for (i = opnum + 1; i < reload_n_operands; i++)
4592 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4593 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4596 for (i = 0; i < reload_n_operands; i++)
4597 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4598 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4599 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4602 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4605 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4606 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4607 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4609 case RELOAD_FOR_INPUT:
4610 /* Similar to input address, except we start at the next operand for
4611 both input and input address and we do not check for
4612 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4615 for (i = opnum + 1; i < reload_n_operands; i++)
4616 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4617 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4618 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4621 /* ... fall through ... */
4623 case RELOAD_FOR_OPERAND_ADDRESS:
4624 /* Check outputs and their addresses. */
4626 for (i = 0; i < reload_n_operands; i++)
4627 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4628 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4629 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4632 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4634 case RELOAD_FOR_OPADDR_ADDR:
4635 for (i = 0; i < reload_n_operands; i++)
4636 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4637 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4638 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4641 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4642 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4643 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4645 case RELOAD_FOR_INSN:
4646 /* These conflict with other outputs with RELOAD_OTHER. So
4647 we need only check for output addresses. */
4649 opnum = reload_n_operands;
4651 /* ... fall through ... */
4653 case RELOAD_FOR_OUTPUT:
4654 case RELOAD_FOR_OUTPUT_ADDRESS:
4655 case RELOAD_FOR_OUTADDR_ADDRESS:
4656 /* We already know these can't conflict with a later output. So the
4657 only thing to check are later output addresses.
4658 Note that multiple output operands are emitted in reverse order,
4659 so the conflicting ones are those with lower indices. */
4660 for (i = 0; i < opnum; i++)
4661 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4662 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4671 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4674 This function uses the same algorithm as reload_reg_free_p above. */
4677 reloads_conflict (r1, r2)
4680 enum reload_type r1_type = rld[r1].when_needed;
4681 enum reload_type r2_type = rld[r2].when_needed;
4682 int r1_opnum = rld[r1].opnum;
4683 int r2_opnum = rld[r2].opnum;
4685 /* RELOAD_OTHER conflicts with everything. */
4686 if (r2_type == RELOAD_OTHER)
4689 /* Otherwise, check conflicts differently for each type. */
4693 case RELOAD_FOR_INPUT:
4694 return (r2_type == RELOAD_FOR_INSN
4695 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4696 || r2_type == RELOAD_FOR_OPADDR_ADDR
4697 || r2_type == RELOAD_FOR_INPUT
4698 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4699 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4700 && r2_opnum > r1_opnum));
4702 case RELOAD_FOR_INPUT_ADDRESS:
4703 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4704 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4706 case RELOAD_FOR_INPADDR_ADDRESS:
4707 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4708 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4710 case RELOAD_FOR_OUTPUT_ADDRESS:
4711 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4712 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4714 case RELOAD_FOR_OUTADDR_ADDRESS:
4715 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4716 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4718 case RELOAD_FOR_OPERAND_ADDRESS:
4719 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4720 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4722 case RELOAD_FOR_OPADDR_ADDR:
4723 return (r2_type == RELOAD_FOR_INPUT
4724 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4726 case RELOAD_FOR_OUTPUT:
4727 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4728 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4729 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4730 && r2_opnum >= r1_opnum));
4732 case RELOAD_FOR_INSN:
4733 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4734 || r2_type == RELOAD_FOR_INSN
4735 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4737 case RELOAD_FOR_OTHER_ADDRESS:
4738 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4748 /* Indexed by reload number, 1 if incoming value
4749 inherited from previous insns. */
4750 char reload_inherited[MAX_RELOADS];
4752 /* For an inherited reload, this is the insn the reload was inherited from,
4753 if we know it. Otherwise, this is 0. */
4754 rtx reload_inheritance_insn[MAX_RELOADS];
4756 /* If nonzero, this is a place to get the value of the reload,
4757 rather than using reload_in. */
4758 rtx reload_override_in[MAX_RELOADS];
4760 /* For each reload, the hard register number of the register used,
4761 or -1 if we did not need a register for this reload. */
4762 int reload_spill_index[MAX_RELOADS];
4764 /* Subroutine of free_for_value_p, used to check a single register.
4765 START_REGNO is the starting regno of the full reload register
4766 (possibly comprising multiple hard registers) that we are considering. */
4769 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4770 reloadnum, ignore_address_reloads)
4771 int start_regno, regno;
4773 enum reload_type type;
4776 int ignore_address_reloads;
4779 /* Set if we see an input reload that must not share its reload register
4780 with any new earlyclobber, but might otherwise share the reload
4781 register with an output or input-output reload. */
4782 int check_earlyclobber = 0;
4786 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4789 if (out == const0_rtx)
4795 /* We use some pseudo 'time' value to check if the lifetimes of the
4796 new register use would overlap with the one of a previous reload
4797 that is not read-only or uses a different value.
4798 The 'time' used doesn't have to be linear in any shape or form, just
4800 Some reload types use different 'buckets' for each operand.
4801 So there are MAX_RECOG_OPERANDS different time values for each
4803 We compute TIME1 as the time when the register for the prospective
4804 new reload ceases to be live, and TIME2 for each existing
4805 reload as the time when that the reload register of that reload
4807 Where there is little to be gained by exact lifetime calculations,
4808 we just make conservative assumptions, i.e. a longer lifetime;
4809 this is done in the 'default:' cases. */
4812 case RELOAD_FOR_OTHER_ADDRESS:
4813 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4814 time1 = copy ? 0 : 1;
4817 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4819 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4820 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4821 respectively, to the time values for these, we get distinct time
4822 values. To get distinct time values for each operand, we have to
4823 multiply opnum by at least three. We round that up to four because
4824 multiply by four is often cheaper. */
4825 case RELOAD_FOR_INPADDR_ADDRESS:
4826 time1 = opnum * 4 + 2;
4828 case RELOAD_FOR_INPUT_ADDRESS:
4829 time1 = opnum * 4 + 3;
4831 case RELOAD_FOR_INPUT:
4832 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4833 executes (inclusive). */
4834 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4836 case RELOAD_FOR_OPADDR_ADDR:
4838 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4839 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4841 case RELOAD_FOR_OPERAND_ADDRESS:
4842 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4844 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4846 case RELOAD_FOR_OUTADDR_ADDRESS:
4847 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4849 case RELOAD_FOR_OUTPUT_ADDRESS:
4850 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4853 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4856 for (i = 0; i < n_reloads; i++)
4858 rtx reg = rld[i].reg_rtx;
4859 if (reg && GET_CODE (reg) == REG
4860 && ((unsigned) regno - true_regnum (reg)
4861 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4864 rtx other_input = rld[i].in;
4866 /* If the other reload loads the same input value, that
4867 will not cause a conflict only if it's loading it into
4868 the same register. */
4869 if (true_regnum (reg) != start_regno)
4870 other_input = NULL_RTX;
4871 if (! other_input || ! rtx_equal_p (other_input, value)
4872 || rld[i].out || out)
4875 switch (rld[i].when_needed)
4877 case RELOAD_FOR_OTHER_ADDRESS:
4880 case RELOAD_FOR_INPADDR_ADDRESS:
4881 /* find_reloads makes sure that a
4882 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4883 by at most one - the first -
4884 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4885 address reload is inherited, the address address reload
4886 goes away, so we can ignore this conflict. */
4887 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4888 && ignore_address_reloads
4889 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4890 Then the address address is still needed to store
4891 back the new address. */
4892 && ! rld[reloadnum].out)
4894 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4895 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4897 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4898 && ignore_address_reloads
4899 /* Unless we are reloading an auto_inc expression. */
4900 && ! rld[reloadnum].out)
4902 time2 = rld[i].opnum * 4 + 2;
4904 case RELOAD_FOR_INPUT_ADDRESS:
4905 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4906 && ignore_address_reloads
4907 && ! rld[reloadnum].out)
4909 time2 = rld[i].opnum * 4 + 3;
4911 case RELOAD_FOR_INPUT:
4912 time2 = rld[i].opnum * 4 + 4;
4913 check_earlyclobber = 1;
4915 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4916 == MAX_RECOG_OPERAND * 4 */
4917 case RELOAD_FOR_OPADDR_ADDR:
4918 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4919 && ignore_address_reloads
4920 && ! rld[reloadnum].out)
4922 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4924 case RELOAD_FOR_OPERAND_ADDRESS:
4925 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4926 check_earlyclobber = 1;
4928 case RELOAD_FOR_INSN:
4929 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4931 case RELOAD_FOR_OUTPUT:
4932 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4933 instruction is executed. */
4934 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4936 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4937 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4939 case RELOAD_FOR_OUTADDR_ADDRESS:
4940 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4941 && ignore_address_reloads
4942 && ! rld[reloadnum].out)
4944 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4946 case RELOAD_FOR_OUTPUT_ADDRESS:
4947 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4950 /* If there is no conflict in the input part, handle this
4951 like an output reload. */
4952 if (! rld[i].in || rtx_equal_p (other_input, value))
4954 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4955 /* Earlyclobbered outputs must conflict with inputs. */
4956 if (earlyclobber_operand_p (rld[i].out))
4957 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4962 /* RELOAD_OTHER might be live beyond instruction execution,
4963 but this is not obvious when we set time2 = 1. So check
4964 here if there might be a problem with the new reload
4965 clobbering the register used by the RELOAD_OTHER. */
4973 && (! rld[i].in || rld[i].out
4974 || ! rtx_equal_p (other_input, value)))
4975 || (out && rld[reloadnum].out_reg
4976 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4982 /* Earlyclobbered outputs must conflict with inputs. */
4983 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4989 /* Return 1 if the value in reload reg REGNO, as used by a reload
4990 needed for the part of the insn specified by OPNUM and TYPE,
4991 may be used to load VALUE into it.
4993 MODE is the mode in which the register is used, this is needed to
4994 determine how many hard regs to test.
4996 Other read-only reloads with the same value do not conflict
4997 unless OUT is nonzero and these other reloads have to live while
4998 output reloads live.
4999 If OUT is CONST0_RTX, this is a special case: it means that the
5000 test should not be for using register REGNO as reload register, but
5001 for copying from register REGNO into the reload register.
5003 RELOADNUM is the number of the reload we want to load this value for;
5004 a reload does not conflict with itself.
5006 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5007 reloads that load an address for the very reload we are considering.
5009 The caller has to make sure that there is no conflict with the return
5013 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5014 ignore_address_reloads)
5016 enum machine_mode mode;
5018 enum reload_type type;
5021 int ignore_address_reloads;
5023 int nregs = HARD_REGNO_NREGS (regno, mode);
5025 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5026 value, out, reloadnum,
5027 ignore_address_reloads))
5032 /* Determine whether the reload reg X overlaps any rtx'es used for
5033 overriding inheritance. Return nonzero if so. */
5036 conflicts_with_override (x)
5040 for (i = 0; i < n_reloads; i++)
5041 if (reload_override_in[i]
5042 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5047 /* Give an error message saying we failed to find a reload for INSN,
5048 and clear out reload R. */
5050 failed_reload (insn, r)
5054 if (asm_noperands (PATTERN (insn)) < 0)
5055 /* It's the compiler's fault. */
5056 fatal_insn ("could not find a spill register", insn);
5058 /* It's the user's fault; the operand's mode and constraint
5059 don't match. Disable this reload so we don't crash in final. */
5060 error_for_asm (insn,
5061 "`asm' operand constraint incompatible with operand size");
5065 rld[r].optional = 1;
5066 rld[r].secondary_p = 1;
5069 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5070 for reload R. If it's valid, get an rtx for it. Return nonzero if
5073 set_reload_reg (i, r)
5077 rtx reg = spill_reg_rtx[i];
5079 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5080 spill_reg_rtx[i] = reg
5081 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5083 regno = true_regnum (reg);
5085 /* Detect when the reload reg can't hold the reload mode.
5086 This used to be one `if', but Sequent compiler can't handle that. */
5087 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5089 enum machine_mode test_mode = VOIDmode;
5091 test_mode = GET_MODE (rld[r].in);
5092 /* If rld[r].in has VOIDmode, it means we will load it
5093 in whatever mode the reload reg has: to wit, rld[r].mode.
5094 We have already tested that for validity. */
5095 /* Aside from that, we need to test that the expressions
5096 to reload from or into have modes which are valid for this
5097 reload register. Otherwise the reload insns would be invalid. */
5098 if (! (rld[r].in != 0 && test_mode != VOIDmode
5099 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5100 if (! (rld[r].out != 0
5101 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5103 /* The reg is OK. */
5106 /* Mark as in use for this insn the reload regs we use
5108 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5109 rld[r].when_needed, rld[r].mode);
5111 rld[r].reg_rtx = reg;
5112 reload_spill_index[r] = spill_regs[i];
5119 /* Find a spill register to use as a reload register for reload R.
5120 LAST_RELOAD is nonzero if this is the last reload for the insn being
5123 Set rld[R].reg_rtx to the register allocated.
5125 We return 1 if successful, or 0 if we couldn't find a spill reg and
5126 we didn't change anything. */
5129 allocate_reload_reg (chain, r, last_reload)
5130 struct insn_chain *chain ATTRIBUTE_UNUSED;
5136 /* If we put this reload ahead, thinking it is a group,
5137 then insist on finding a group. Otherwise we can grab a
5138 reg that some other reload needs.
5139 (That can happen when we have a 68000 DATA_OR_FP_REG
5140 which is a group of data regs or one fp reg.)
5141 We need not be so restrictive if there are no more reloads
5144 ??? Really it would be nicer to have smarter handling
5145 for that kind of reg class, where a problem like this is normal.
5146 Perhaps those classes should be avoided for reloading
5147 by use of more alternatives. */
5149 int force_group = rld[r].nregs > 1 && ! last_reload;
5151 /* If we want a single register and haven't yet found one,
5152 take any reg in the right class and not in use.
5153 If we want a consecutive group, here is where we look for it.
5155 We use two passes so we can first look for reload regs to
5156 reuse, which are already in use for other reloads in this insn,
5157 and only then use additional registers.
5158 I think that maximizing reuse is needed to make sure we don't
5159 run out of reload regs. Suppose we have three reloads, and
5160 reloads A and B can share regs. These need two regs.
5161 Suppose A and B are given different regs.
5162 That leaves none for C. */
5163 for (pass = 0; pass < 2; pass++)
5165 /* I is the index in spill_regs.
5166 We advance it round-robin between insns to use all spill regs
5167 equally, so that inherited reloads have a chance
5168 of leapfrogging each other. */
5172 for (count = 0; count < n_spills; count++)
5174 int class = (int) rld[r].class;
5180 regnum = spill_regs[i];
5182 if ((reload_reg_free_p (regnum, rld[r].opnum,
5185 /* We check reload_reg_used to make sure we
5186 don't clobber the return register. */
5187 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5188 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5189 rld[r].when_needed, rld[r].in,
5191 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5192 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5193 /* Look first for regs to share, then for unshared. But
5194 don't share regs used for inherited reloads; they are
5195 the ones we want to preserve. */
5197 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5199 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5202 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5203 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5204 (on 68000) got us two FP regs. If NR is 1,
5205 we would reject both of them. */
5208 /* If we need only one reg, we have already won. */
5211 /* But reject a single reg if we demand a group. */
5216 /* Otherwise check that as many consecutive regs as we need
5217 are available here. */
5220 int regno = regnum + nr - 1;
5221 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5222 && spill_reg_order[regno] >= 0
5223 && reload_reg_free_p (regno, rld[r].opnum,
5224 rld[r].when_needed)))
5233 /* If we found something on pass 1, omit pass 2. */
5234 if (count < n_spills)
5238 /* We should have found a spill register by now. */
5239 if (count >= n_spills)
5242 /* I is the index in SPILL_REG_RTX of the reload register we are to
5243 allocate. Get an rtx for it and find its register number. */
5245 return set_reload_reg (i, r);
5248 /* Initialize all the tables needed to allocate reload registers.
5249 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5250 is the array we use to restore the reg_rtx field for every reload. */
5253 choose_reload_regs_init (chain, save_reload_reg_rtx)
5254 struct insn_chain *chain;
5255 rtx *save_reload_reg_rtx;
5259 for (i = 0; i < n_reloads; i++)
5260 rld[i].reg_rtx = save_reload_reg_rtx[i];
5262 memset (reload_inherited, 0, MAX_RELOADS);
5263 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5264 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5266 CLEAR_HARD_REG_SET (reload_reg_used);
5267 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5268 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5269 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5270 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5271 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5273 CLEAR_HARD_REG_SET (reg_used_in_insn);
5276 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5277 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5278 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5279 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5280 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5281 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5284 for (i = 0; i < reload_n_operands; i++)
5286 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5287 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5288 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5289 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5290 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5291 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5294 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5296 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5298 for (i = 0; i < n_reloads; i++)
5299 /* If we have already decided to use a certain register,
5300 don't use it in another way. */
5302 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5303 rld[i].when_needed, rld[i].mode);
5306 /* Assign hard reg targets for the pseudo-registers we must reload
5307 into hard regs for this insn.
5308 Also output the instructions to copy them in and out of the hard regs.
5310 For machines with register classes, we are responsible for
5311 finding a reload reg in the proper class. */
5314 choose_reload_regs (chain)
5315 struct insn_chain *chain;
5317 rtx insn = chain->insn;
5319 unsigned int max_group_size = 1;
5320 enum reg_class group_class = NO_REGS;
5321 int pass, win, inheritance;
5323 rtx save_reload_reg_rtx[MAX_RELOADS];
5325 /* In order to be certain of getting the registers we need,
5326 we must sort the reloads into order of increasing register class.
5327 Then our grabbing of reload registers will parallel the process
5328 that provided the reload registers.
5330 Also note whether any of the reloads wants a consecutive group of regs.
5331 If so, record the maximum size of the group desired and what
5332 register class contains all the groups needed by this insn. */
5334 for (j = 0; j < n_reloads; j++)
5336 reload_order[j] = j;
5337 reload_spill_index[j] = -1;
5339 if (rld[j].nregs > 1)
5341 max_group_size = MAX (rld[j].nregs, max_group_size);
5343 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5346 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5350 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5352 /* If -O, try first with inheritance, then turning it off.
5353 If not -O, don't do inheritance.
5354 Using inheritance when not optimizing leads to paradoxes
5355 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5356 because one side of the comparison might be inherited. */
5358 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5360 choose_reload_regs_init (chain, save_reload_reg_rtx);
5362 /* Process the reloads in order of preference just found.
5363 Beyond this point, subregs can be found in reload_reg_rtx.
5365 This used to look for an existing reloaded home for all of the
5366 reloads, and only then perform any new reloads. But that could lose
5367 if the reloads were done out of reg-class order because a later
5368 reload with a looser constraint might have an old home in a register
5369 needed by an earlier reload with a tighter constraint.
5371 To solve this, we make two passes over the reloads, in the order
5372 described above. In the first pass we try to inherit a reload
5373 from a previous insn. If there is a later reload that needs a
5374 class that is a proper subset of the class being processed, we must
5375 also allocate a spill register during the first pass.
5377 Then make a second pass over the reloads to allocate any reloads
5378 that haven't been given registers yet. */
5380 for (j = 0; j < n_reloads; j++)
5382 int r = reload_order[j];
5383 rtx search_equiv = NULL_RTX;
5385 /* Ignore reloads that got marked inoperative. */
5386 if (rld[r].out == 0 && rld[r].in == 0
5387 && ! rld[r].secondary_p)
5390 /* If find_reloads chose to use reload_in or reload_out as a reload
5391 register, we don't need to chose one. Otherwise, try even if it
5392 found one since we might save an insn if we find the value lying
5394 Try also when reload_in is a pseudo without a hard reg. */
5395 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5396 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5397 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5398 && GET_CODE (rld[r].in) != MEM
5399 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5402 #if 0 /* No longer needed for correct operation.
5403 It might give better code, or might not; worth an experiment? */
5404 /* If this is an optional reload, we can't inherit from earlier insns
5405 until we are sure that any non-optional reloads have been allocated.
5406 The following code takes advantage of the fact that optional reloads
5407 are at the end of reload_order. */
5408 if (rld[r].optional != 0)
5409 for (i = 0; i < j; i++)
5410 if ((rld[reload_order[i]].out != 0
5411 || rld[reload_order[i]].in != 0
5412 || rld[reload_order[i]].secondary_p)
5413 && ! rld[reload_order[i]].optional
5414 && rld[reload_order[i]].reg_rtx == 0)
5415 allocate_reload_reg (chain, reload_order[i], 0);
5418 /* First see if this pseudo is already available as reloaded
5419 for a previous insn. We cannot try to inherit for reloads
5420 that are smaller than the maximum number of registers needed
5421 for groups unless the register we would allocate cannot be used
5424 We could check here to see if this is a secondary reload for
5425 an object that is already in a register of the desired class.
5426 This would avoid the need for the secondary reload register.
5427 But this is complex because we can't easily determine what
5428 objects might want to be loaded via this reload. So let a
5429 register be allocated here. In `emit_reload_insns' we suppress
5430 one of the loads in the case described above. */
5436 enum machine_mode mode = VOIDmode;
5440 else if (GET_CODE (rld[r].in) == REG)
5442 regno = REGNO (rld[r].in);
5443 mode = GET_MODE (rld[r].in);
5445 else if (GET_CODE (rld[r].in_reg) == REG)
5447 regno = REGNO (rld[r].in_reg);
5448 mode = GET_MODE (rld[r].in_reg);
5450 else if (GET_CODE (rld[r].in_reg) == SUBREG
5451 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5453 byte = SUBREG_BYTE (rld[r].in_reg);
5454 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5455 if (regno < FIRST_PSEUDO_REGISTER)
5456 regno = subreg_regno (rld[r].in_reg);
5457 mode = GET_MODE (rld[r].in_reg);
5460 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5461 || GET_CODE (rld[r].in_reg) == PRE_DEC
5462 || GET_CODE (rld[r].in_reg) == POST_INC
5463 || GET_CODE (rld[r].in_reg) == POST_DEC)
5464 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5466 regno = REGNO (XEXP (rld[r].in_reg, 0));
5467 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5468 rld[r].out = rld[r].in;
5472 /* This won't work, since REGNO can be a pseudo reg number.
5473 Also, it takes much more hair to keep track of all the things
5474 that can invalidate an inherited reload of part of a pseudoreg. */
5475 else if (GET_CODE (rld[r].in) == SUBREG
5476 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5477 regno = subreg_regno (rld[r].in);
5480 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5482 enum reg_class class = rld[r].class, last_class;
5483 rtx last_reg = reg_last_reload_reg[regno];
5484 enum machine_mode need_mode;
5486 i = REGNO (last_reg);
5487 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5488 last_class = REGNO_REG_CLASS (i);
5494 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5495 GET_MODE_CLASS (mode));
5498 #ifdef CANNOT_CHANGE_MODE_CLASS
5499 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5503 (GET_MODE_SIZE (GET_MODE (last_reg))
5504 >= GET_MODE_SIZE (need_mode))
5505 #ifdef CANNOT_CHANGE_MODE_CLASS
5508 && reg_reloaded_contents[i] == regno
5509 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5510 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5511 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5512 /* Even if we can't use this register as a reload
5513 register, we might use it for reload_override_in,
5514 if copying it to the desired class is cheap
5516 || ((REGISTER_MOVE_COST (mode, last_class, class)
5517 < MEMORY_MOVE_COST (mode, class, 1))
5518 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5519 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5523 #ifdef SECONDARY_MEMORY_NEEDED
5524 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5529 && (rld[r].nregs == max_group_size
5530 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5532 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5533 rld[r].when_needed, rld[r].in,
5536 /* If a group is needed, verify that all the subsequent
5537 registers still have their values intact. */
5538 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5541 for (k = 1; k < nr; k++)
5542 if (reg_reloaded_contents[i + k] != regno
5543 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5551 last_reg = (GET_MODE (last_reg) == mode
5552 ? last_reg : gen_rtx_REG (mode, i));
5555 for (k = 0; k < nr; k++)
5556 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5559 /* We found a register that contains the
5560 value we need. If this register is the
5561 same as an `earlyclobber' operand of the
5562 current insn, just mark it as a place to
5563 reload from since we can't use it as the
5564 reload register itself. */
5566 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5567 if (reg_overlap_mentioned_for_reload_p
5568 (reg_last_reload_reg[regno],
5569 reload_earlyclobbers[i1]))
5572 if (i1 != n_earlyclobbers
5573 || ! (free_for_value_p (i, rld[r].mode,
5575 rld[r].when_needed, rld[r].in,
5577 /* Don't use it if we'd clobber a pseudo reg. */
5578 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5580 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5581 /* Don't clobber the frame pointer. */
5582 || (i == HARD_FRAME_POINTER_REGNUM
5583 && frame_pointer_needed
5585 /* Don't really use the inherited spill reg
5586 if we need it wider than we've got it. */
5587 || (GET_MODE_SIZE (rld[r].mode)
5588 > GET_MODE_SIZE (mode))
5591 /* If find_reloads chose reload_out as reload
5592 register, stay with it - that leaves the
5593 inherited register for subsequent reloads. */
5594 || (rld[r].out && rld[r].reg_rtx
5595 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5597 if (! rld[r].optional)
5599 reload_override_in[r] = last_reg;
5600 reload_inheritance_insn[r]
5601 = reg_reloaded_insn[i];
5607 /* We can use this as a reload reg. */
5608 /* Mark the register as in use for this part of
5610 mark_reload_reg_in_use (i,
5614 rld[r].reg_rtx = last_reg;
5615 reload_inherited[r] = 1;
5616 reload_inheritance_insn[r]
5617 = reg_reloaded_insn[i];
5618 reload_spill_index[r] = i;
5619 for (k = 0; k < nr; k++)
5620 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5628 /* Here's another way to see if the value is already lying around. */
5631 && ! reload_inherited[r]
5633 && (CONSTANT_P (rld[r].in)
5634 || GET_CODE (rld[r].in) == PLUS
5635 || GET_CODE (rld[r].in) == REG
5636 || GET_CODE (rld[r].in) == MEM)
5637 && (rld[r].nregs == max_group_size
5638 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5639 search_equiv = rld[r].in;
5640 /* If this is an output reload from a simple move insn, look
5641 if an equivalence for the input is available. */
5642 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5644 rtx set = single_set (insn);
5647 && rtx_equal_p (rld[r].out, SET_DEST (set))
5648 && CONSTANT_P (SET_SRC (set)))
5649 search_equiv = SET_SRC (set);
5655 = find_equiv_reg (search_equiv, insn, rld[r].class,
5656 -1, NULL, 0, rld[r].mode);
5661 if (GET_CODE (equiv) == REG)
5662 regno = REGNO (equiv);
5663 else if (GET_CODE (equiv) == SUBREG)
5665 /* This must be a SUBREG of a hard register.
5666 Make a new REG since this might be used in an
5667 address and not all machines support SUBREGs
5669 regno = subreg_regno (equiv);
5670 equiv = gen_rtx_REG (rld[r].mode, regno);
5676 /* If we found a spill reg, reject it unless it is free
5677 and of the desired class. */
5679 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5680 && ! free_for_value_p (regno, rld[r].mode,
5681 rld[r].opnum, rld[r].when_needed,
5682 rld[r].in, rld[r].out, r, 1))
5683 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5687 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5690 /* We found a register that contains the value we need.
5691 If this register is the same as an `earlyclobber' operand
5692 of the current insn, just mark it as a place to reload from
5693 since we can't use it as the reload register itself. */
5696 for (i = 0; i < n_earlyclobbers; i++)
5697 if (reg_overlap_mentioned_for_reload_p (equiv,
5698 reload_earlyclobbers[i]))
5700 if (! rld[r].optional)
5701 reload_override_in[r] = equiv;
5706 /* If the equiv register we have found is explicitly clobbered
5707 in the current insn, it depends on the reload type if we
5708 can use it, use it for reload_override_in, or not at all.
5709 In particular, we then can't use EQUIV for a
5710 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5714 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5715 switch (rld[r].when_needed)
5717 case RELOAD_FOR_OTHER_ADDRESS:
5718 case RELOAD_FOR_INPADDR_ADDRESS:
5719 case RELOAD_FOR_INPUT_ADDRESS:
5720 case RELOAD_FOR_OPADDR_ADDR:
5723 case RELOAD_FOR_INPUT:
5724 case RELOAD_FOR_OPERAND_ADDRESS:
5725 if (! rld[r].optional)
5726 reload_override_in[r] = equiv;
5732 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5733 switch (rld[r].when_needed)
5735 case RELOAD_FOR_OTHER_ADDRESS:
5736 case RELOAD_FOR_INPADDR_ADDRESS:
5737 case RELOAD_FOR_INPUT_ADDRESS:
5738 case RELOAD_FOR_OPADDR_ADDR:
5739 case RELOAD_FOR_OPERAND_ADDRESS:
5740 case RELOAD_FOR_INPUT:
5743 if (! rld[r].optional)
5744 reload_override_in[r] = equiv;
5752 /* If we found an equivalent reg, say no code need be generated
5753 to load it, and use it as our reload reg. */
5755 && (regno != HARD_FRAME_POINTER_REGNUM
5756 || !frame_pointer_needed))
5758 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5760 rld[r].reg_rtx = equiv;
5761 reload_inherited[r] = 1;
5763 /* If reg_reloaded_valid is not set for this register,
5764 there might be a stale spill_reg_store lying around.
5765 We must clear it, since otherwise emit_reload_insns
5766 might delete the store. */
5767 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5768 spill_reg_store[regno] = NULL_RTX;
5769 /* If any of the hard registers in EQUIV are spill
5770 registers, mark them as in use for this insn. */
5771 for (k = 0; k < nr; k++)
5773 i = spill_reg_order[regno + k];
5776 mark_reload_reg_in_use (regno, rld[r].opnum,
5779 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5786 /* If we found a register to use already, or if this is an optional
5787 reload, we are done. */
5788 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5792 /* No longer needed for correct operation. Might or might
5793 not give better code on the average. Want to experiment? */
5795 /* See if there is a later reload that has a class different from our
5796 class that intersects our class or that requires less register
5797 than our reload. If so, we must allocate a register to this
5798 reload now, since that reload might inherit a previous reload
5799 and take the only available register in our class. Don't do this
5800 for optional reloads since they will force all previous reloads
5801 to be allocated. Also don't do this for reloads that have been
5804 for (i = j + 1; i < n_reloads; i++)
5806 int s = reload_order[i];
5808 if ((rld[s].in == 0 && rld[s].out == 0
5809 && ! rld[s].secondary_p)
5813 if ((rld[s].class != rld[r].class
5814 && reg_classes_intersect_p (rld[r].class,
5816 || rld[s].nregs < rld[r].nregs)
5823 allocate_reload_reg (chain, r, j == n_reloads - 1);
5827 /* Now allocate reload registers for anything non-optional that
5828 didn't get one yet. */
5829 for (j = 0; j < n_reloads; j++)
5831 int r = reload_order[j];
5833 /* Ignore reloads that got marked inoperative. */
5834 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5837 /* Skip reloads that already have a register allocated or are
5839 if (rld[r].reg_rtx != 0 || rld[r].optional)
5842 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5846 /* If that loop got all the way, we have won. */
5853 /* Loop around and try without any inheritance. */
5858 /* First undo everything done by the failed attempt
5859 to allocate with inheritance. */
5860 choose_reload_regs_init (chain, save_reload_reg_rtx);
5862 /* Some sanity tests to verify that the reloads found in the first
5863 pass are identical to the ones we have now. */
5864 if (chain->n_reloads != n_reloads)
5867 for (i = 0; i < n_reloads; i++)
5869 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5871 if (chain->rld[i].when_needed != rld[i].when_needed)
5873 for (j = 0; j < n_spills; j++)
5874 if (spill_regs[j] == chain->rld[i].regno)
5875 if (! set_reload_reg (j, i))
5876 failed_reload (chain->insn, i);
5880 /* If we thought we could inherit a reload, because it seemed that
5881 nothing else wanted the same reload register earlier in the insn,
5882 verify that assumption, now that all reloads have been assigned.
5883 Likewise for reloads where reload_override_in has been set. */
5885 /* If doing expensive optimizations, do one preliminary pass that doesn't
5886 cancel any inheritance, but removes reloads that have been needed only
5887 for reloads that we know can be inherited. */
5888 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5890 for (j = 0; j < n_reloads; j++)
5892 int r = reload_order[j];
5894 if (reload_inherited[r] && rld[r].reg_rtx)
5895 check_reg = rld[r].reg_rtx;
5896 else if (reload_override_in[r]
5897 && (GET_CODE (reload_override_in[r]) == REG
5898 || GET_CODE (reload_override_in[r]) == SUBREG))
5899 check_reg = reload_override_in[r];
5902 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5903 rld[r].opnum, rld[r].when_needed, rld[r].in,
5904 (reload_inherited[r]
5905 ? rld[r].out : const0_rtx),
5910 reload_inherited[r] = 0;
5911 reload_override_in[r] = 0;
5913 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5914 reload_override_in, then we do not need its related
5915 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5916 likewise for other reload types.
5917 We handle this by removing a reload when its only replacement
5918 is mentioned in reload_in of the reload we are going to inherit.
5919 A special case are auto_inc expressions; even if the input is
5920 inherited, we still need the address for the output. We can
5921 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5922 If we succeeded removing some reload and we are doing a preliminary
5923 pass just to remove such reloads, make another pass, since the
5924 removal of one reload might allow us to inherit another one. */
5926 && rld[r].out != rld[r].in
5927 && remove_address_replacements (rld[r].in) && pass)
5932 /* Now that reload_override_in is known valid,
5933 actually override reload_in. */
5934 for (j = 0; j < n_reloads; j++)
5935 if (reload_override_in[j])
5936 rld[j].in = reload_override_in[j];
5938 /* If this reload won't be done because it has been canceled or is
5939 optional and not inherited, clear reload_reg_rtx so other
5940 routines (such as subst_reloads) don't get confused. */
5941 for (j = 0; j < n_reloads; j++)
5942 if (rld[j].reg_rtx != 0
5943 && ((rld[j].optional && ! reload_inherited[j])
5944 || (rld[j].in == 0 && rld[j].out == 0
5945 && ! rld[j].secondary_p)))
5947 int regno = true_regnum (rld[j].reg_rtx);
5949 if (spill_reg_order[regno] >= 0)
5950 clear_reload_reg_in_use (regno, rld[j].opnum,
5951 rld[j].when_needed, rld[j].mode);
5953 reload_spill_index[j] = -1;
5956 /* Record which pseudos and which spill regs have output reloads. */
5957 for (j = 0; j < n_reloads; j++)
5959 int r = reload_order[j];
5961 i = reload_spill_index[r];
5963 /* I is nonneg if this reload uses a register.
5964 If rld[r].reg_rtx is 0, this is an optional reload
5965 that we opted to ignore. */
5966 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5967 && rld[r].reg_rtx != 0)
5969 int nregno = REGNO (rld[r].out_reg);
5972 if (nregno < FIRST_PSEUDO_REGISTER)
5973 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5976 reg_has_output_reload[nregno + nr] = 1;
5980 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5982 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5985 if (rld[r].when_needed != RELOAD_OTHER
5986 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5987 && rld[r].when_needed != RELOAD_FOR_INSN)
5993 /* Deallocate the reload register for reload R. This is called from
5994 remove_address_replacements. */
5997 deallocate_reload_reg (r)
6002 if (! rld[r].reg_rtx)
6004 regno = true_regnum (rld[r].reg_rtx);
6006 if (spill_reg_order[regno] >= 0)
6007 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6009 reload_spill_index[r] = -1;
6012 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6013 reloads of the same item for fear that we might not have enough reload
6014 registers. However, normally they will get the same reload register
6015 and hence actually need not be loaded twice.
6017 Here we check for the most common case of this phenomenon: when we have
6018 a number of reloads for the same object, each of which were allocated
6019 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6020 reload, and is not modified in the insn itself. If we find such,
6021 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6022 This will not increase the number of spill registers needed and will
6023 prevent redundant code. */
6026 merge_assigned_reloads (insn)
6031 /* Scan all the reloads looking for ones that only load values and
6032 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6033 assigned and not modified by INSN. */
6035 for (i = 0; i < n_reloads; i++)
6037 int conflicting_input = 0;
6038 int max_input_address_opnum = -1;
6039 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6041 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6042 || rld[i].out != 0 || rld[i].reg_rtx == 0
6043 || reg_set_p (rld[i].reg_rtx, insn))
6046 /* Look at all other reloads. Ensure that the only use of this
6047 reload_reg_rtx is in a reload that just loads the same value
6048 as we do. Note that any secondary reloads must be of the identical
6049 class since the values, modes, and result registers are the
6050 same, so we need not do anything with any secondary reloads. */
6052 for (j = 0; j < n_reloads; j++)
6054 if (i == j || rld[j].reg_rtx == 0
6055 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6059 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6060 && rld[j].opnum > max_input_address_opnum)
6061 max_input_address_opnum = rld[j].opnum;
6063 /* If the reload regs aren't exactly the same (e.g, different modes)
6064 or if the values are different, we can't merge this reload.
6065 But if it is an input reload, we might still merge
6066 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6068 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6069 || rld[j].out != 0 || rld[j].in == 0
6070 || ! rtx_equal_p (rld[i].in, rld[j].in))
6072 if (rld[j].when_needed != RELOAD_FOR_INPUT
6073 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6074 || rld[i].opnum > rld[j].opnum)
6075 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6077 conflicting_input = 1;
6078 if (min_conflicting_input_opnum > rld[j].opnum)
6079 min_conflicting_input_opnum = rld[j].opnum;
6083 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6084 we, in fact, found any matching reloads. */
6087 && max_input_address_opnum <= min_conflicting_input_opnum)
6089 for (j = 0; j < n_reloads; j++)
6090 if (i != j && rld[j].reg_rtx != 0
6091 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6092 && (! conflicting_input
6093 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6094 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6096 rld[i].when_needed = RELOAD_OTHER;
6098 reload_spill_index[j] = -1;
6099 transfer_replacements (i, j);
6102 /* If this is now RELOAD_OTHER, look for any reloads that load
6103 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6104 if they were for inputs, RELOAD_OTHER for outputs. Note that
6105 this test is equivalent to looking for reloads for this operand
6107 /* We must take special care when there are two or more reloads to
6108 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6109 same value or a part of it; we must not change its type if there
6110 is a conflicting input. */
6112 if (rld[i].when_needed == RELOAD_OTHER)
6113 for (j = 0; j < n_reloads; j++)
6115 && rld[j].when_needed != RELOAD_OTHER
6116 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6117 && (! conflicting_input
6118 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6119 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6120 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6126 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6127 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6128 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6130 /* Check to see if we accidentally converted two reloads
6131 that use the same reload register to the same type.
6132 If so, the resulting code won't work, so abort. */
6134 for (k = 0; k < j; k++)
6135 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6136 && rld[k].when_needed == rld[j].when_needed
6137 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx))
6144 /* These arrays are filled by emit_reload_insns and its subroutines. */
6145 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6146 static rtx other_input_address_reload_insns = 0;
6147 static rtx other_input_reload_insns = 0;
6148 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6149 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6150 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6151 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6152 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6153 static rtx operand_reload_insns = 0;
6154 static rtx other_operand_reload_insns = 0;
6155 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6157 /* Values to be put in spill_reg_store are put here first. */
6158 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6159 static HARD_REG_SET reg_reloaded_died;
6161 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6162 has the number J. OLD contains the value to be used as input. */
6165 emit_input_reload_insns (chain, rl, old, j)
6166 struct insn_chain *chain;
6171 rtx insn = chain->insn;
6172 rtx reloadreg = rl->reg_rtx;
6173 rtx oldequiv_reg = 0;
6176 enum machine_mode mode;
6179 /* Determine the mode to reload in.
6180 This is very tricky because we have three to choose from.
6181 There is the mode the insn operand wants (rl->inmode).
6182 There is the mode of the reload register RELOADREG.
6183 There is the intrinsic mode of the operand, which we could find
6184 by stripping some SUBREGs.
6185 It turns out that RELOADREG's mode is irrelevant:
6186 we can change that arbitrarily.
6188 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6189 then the reload reg may not support QImode moves, so use SImode.
6190 If foo is in memory due to spilling a pseudo reg, this is safe,
6191 because the QImode value is in the least significant part of a
6192 slot big enough for a SImode. If foo is some other sort of
6193 memory reference, then it is impossible to reload this case,
6194 so previous passes had better make sure this never happens.
6196 Then consider a one-word union which has SImode and one of its
6197 members is a float, being fetched as (SUBREG:SF union:SI).
6198 We must fetch that as SFmode because we could be loading into
6199 a float-only register. In this case OLD's mode is correct.
6201 Consider an immediate integer: it has VOIDmode. Here we need
6202 to get a mode from something else.
6204 In some cases, there is a fourth mode, the operand's
6205 containing mode. If the insn specifies a containing mode for
6206 this operand, it overrides all others.
6208 I am not sure whether the algorithm here is always right,
6209 but it does the right things in those cases. */
6211 mode = GET_MODE (old);
6212 if (mode == VOIDmode)
6215 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6216 /* If we need a secondary register for this operation, see if
6217 the value is already in a register in that class. Don't
6218 do this if the secondary register will be used as a scratch
6221 if (rl->secondary_in_reload >= 0
6222 && rl->secondary_in_icode == CODE_FOR_nothing
6225 = find_equiv_reg (old, insn,
6226 rld[rl->secondary_in_reload].class,
6230 /* If reloading from memory, see if there is a register
6231 that already holds the same value. If so, reload from there.
6232 We can pass 0 as the reload_reg_p argument because
6233 any other reload has either already been emitted,
6234 in which case find_equiv_reg will see the reload-insn,
6235 or has yet to be emitted, in which case it doesn't matter
6236 because we will use this equiv reg right away. */
6238 if (oldequiv == 0 && optimize
6239 && (GET_CODE (old) == MEM
6240 || (GET_CODE (old) == REG
6241 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6242 && reg_renumber[REGNO (old)] < 0)))
6243 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6247 unsigned int regno = true_regnum (oldequiv);
6249 /* Don't use OLDEQUIV if any other reload changes it at an
6250 earlier stage of this insn or at this stage. */
6251 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6252 rl->in, const0_rtx, j, 0))
6255 /* If it is no cheaper to copy from OLDEQUIV into the
6256 reload register than it would be to move from memory,
6257 don't use it. Likewise, if we need a secondary register
6261 && ((REGNO_REG_CLASS (regno) != rl->class
6262 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6264 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6265 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6266 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6270 #ifdef SECONDARY_MEMORY_NEEDED
6271 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6279 /* delete_output_reload is only invoked properly if old contains
6280 the original pseudo register. Since this is replaced with a
6281 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6282 find the pseudo in RELOAD_IN_REG. */
6284 && reload_override_in[j]
6285 && GET_CODE (rl->in_reg) == REG)
6292 else if (GET_CODE (oldequiv) == REG)
6293 oldequiv_reg = oldequiv;
6294 else if (GET_CODE (oldequiv) == SUBREG)
6295 oldequiv_reg = SUBREG_REG (oldequiv);
6297 /* If we are reloading from a register that was recently stored in
6298 with an output-reload, see if we can prove there was
6299 actually no need to store the old value in it. */
6301 if (optimize && GET_CODE (oldequiv) == REG
6302 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6303 && spill_reg_store[REGNO (oldequiv)]
6304 && GET_CODE (old) == REG
6305 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6306 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6308 delete_output_reload (insn, j, REGNO (oldequiv));
6310 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6311 then load RELOADREG from OLDEQUIV. Note that we cannot use
6312 gen_lowpart_common since it can do the wrong thing when
6313 RELOADREG has a multi-word mode. Note that RELOADREG
6314 must always be a REG here. */
6316 if (GET_MODE (reloadreg) != mode)
6317 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6318 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6319 oldequiv = SUBREG_REG (oldequiv);
6320 if (GET_MODE (oldequiv) != VOIDmode
6321 && mode != GET_MODE (oldequiv))
6322 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6324 /* Switch to the right place to emit the reload insns. */
6325 switch (rl->when_needed)
6328 where = &other_input_reload_insns;
6330 case RELOAD_FOR_INPUT:
6331 where = &input_reload_insns[rl->opnum];
6333 case RELOAD_FOR_INPUT_ADDRESS:
6334 where = &input_address_reload_insns[rl->opnum];
6336 case RELOAD_FOR_INPADDR_ADDRESS:
6337 where = &inpaddr_address_reload_insns[rl->opnum];
6339 case RELOAD_FOR_OUTPUT_ADDRESS:
6340 where = &output_address_reload_insns[rl->opnum];
6342 case RELOAD_FOR_OUTADDR_ADDRESS:
6343 where = &outaddr_address_reload_insns[rl->opnum];
6345 case RELOAD_FOR_OPERAND_ADDRESS:
6346 where = &operand_reload_insns;
6348 case RELOAD_FOR_OPADDR_ADDR:
6349 where = &other_operand_reload_insns;
6351 case RELOAD_FOR_OTHER_ADDRESS:
6352 where = &other_input_address_reload_insns;
6358 push_to_sequence (*where);
6360 /* Auto-increment addresses must be reloaded in a special way. */
6361 if (rl->out && ! rl->out_reg)
6363 /* We are not going to bother supporting the case where a
6364 incremented register can't be copied directly from
6365 OLDEQUIV since this seems highly unlikely. */
6366 if (rl->secondary_in_reload >= 0)
6369 if (reload_inherited[j])
6370 oldequiv = reloadreg;
6372 old = XEXP (rl->in_reg, 0);
6374 if (optimize && GET_CODE (oldequiv) == REG
6375 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6376 && spill_reg_store[REGNO (oldequiv)]
6377 && GET_CODE (old) == REG
6378 && (dead_or_set_p (insn,
6379 spill_reg_stored_to[REGNO (oldequiv)])
6380 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6382 delete_output_reload (insn, j, REGNO (oldequiv));
6384 /* Prevent normal processing of this reload. */
6386 /* Output a special code sequence for this case. */
6387 new_spill_reg_store[REGNO (reloadreg)]
6388 = inc_for_reload (reloadreg, oldequiv, rl->out,
6392 /* If we are reloading a pseudo-register that was set by the previous
6393 insn, see if we can get rid of that pseudo-register entirely
6394 by redirecting the previous insn into our reload register. */
6396 else if (optimize && GET_CODE (old) == REG
6397 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6398 && dead_or_set_p (insn, old)
6399 /* This is unsafe if some other reload
6400 uses the same reg first. */
6401 && ! conflicts_with_override (reloadreg)
6402 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6403 rl->when_needed, old, rl->out, j, 0))
6405 rtx temp = PREV_INSN (insn);
6406 while (temp && GET_CODE (temp) == NOTE)
6407 temp = PREV_INSN (temp);
6409 && GET_CODE (temp) == INSN
6410 && GET_CODE (PATTERN (temp)) == SET
6411 && SET_DEST (PATTERN (temp)) == old
6412 /* Make sure we can access insn_operand_constraint. */
6413 && asm_noperands (PATTERN (temp)) < 0
6414 /* This is unsafe if operand occurs more than once in current
6415 insn. Perhaps some occurrences aren't reloaded. */
6416 && count_occurrences (PATTERN (insn), old, 0) == 1)
6418 rtx old = SET_DEST (PATTERN (temp));
6419 /* Store into the reload register instead of the pseudo. */
6420 SET_DEST (PATTERN (temp)) = reloadreg;
6422 /* Verify that resulting insn is valid. */
6423 extract_insn (temp);
6424 if (constrain_operands (1))
6426 /* If the previous insn is an output reload, the source is
6427 a reload register, and its spill_reg_store entry will
6428 contain the previous destination. This is now
6430 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6431 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6433 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6434 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6437 /* If these are the only uses of the pseudo reg,
6438 pretend for GDB it lives in the reload reg we used. */
6439 if (REG_N_DEATHS (REGNO (old)) == 1
6440 && REG_N_SETS (REGNO (old)) == 1)
6442 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6443 alter_reg (REGNO (old), -1);
6449 SET_DEST (PATTERN (temp)) = old;
6454 /* We can't do that, so output an insn to load RELOADREG. */
6456 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6457 /* If we have a secondary reload, pick up the secondary register
6458 and icode, if any. If OLDEQUIV and OLD are different or
6459 if this is an in-out reload, recompute whether or not we
6460 still need a secondary register and what the icode should
6461 be. If we still need a secondary register and the class or
6462 icode is different, go back to reloading from OLD if using
6463 OLDEQUIV means that we got the wrong type of register. We
6464 cannot have different class or icode due to an in-out reload
6465 because we don't make such reloads when both the input and
6466 output need secondary reload registers. */
6468 if (! special && rl->secondary_in_reload >= 0)
6470 rtx second_reload_reg = 0;
6471 int secondary_reload = rl->secondary_in_reload;
6472 rtx real_oldequiv = oldequiv;
6475 enum insn_code icode;
6477 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6478 and similarly for OLD.
6479 See comments in get_secondary_reload in reload.c. */
6480 /* If it is a pseudo that cannot be replaced with its
6481 equivalent MEM, we must fall back to reload_in, which
6482 will have all the necessary substitutions registered.
6483 Likewise for a pseudo that can't be replaced with its
6484 equivalent constant.
6486 Take extra care for subregs of such pseudos. Note that
6487 we cannot use reg_equiv_mem in this case because it is
6488 not in the right mode. */
6491 if (GET_CODE (tmp) == SUBREG)
6492 tmp = SUBREG_REG (tmp);
6493 if (GET_CODE (tmp) == REG
6494 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6495 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6496 || reg_equiv_constant[REGNO (tmp)] != 0))
6498 if (! reg_equiv_mem[REGNO (tmp)]
6499 || num_not_at_initial_offset
6500 || GET_CODE (oldequiv) == SUBREG)
6501 real_oldequiv = rl->in;
6503 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6507 if (GET_CODE (tmp) == SUBREG)
6508 tmp = SUBREG_REG (tmp);
6509 if (GET_CODE (tmp) == REG
6510 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6511 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6512 || reg_equiv_constant[REGNO (tmp)] != 0))
6514 if (! reg_equiv_mem[REGNO (tmp)]
6515 || num_not_at_initial_offset
6516 || GET_CODE (old) == SUBREG)
6519 real_old = reg_equiv_mem[REGNO (tmp)];
6522 second_reload_reg = rld[secondary_reload].reg_rtx;
6523 icode = rl->secondary_in_icode;
6525 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6526 || (rl->in != 0 && rl->out != 0))
6528 enum reg_class new_class
6529 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6530 mode, real_oldequiv);
6532 if (new_class == NO_REGS)
6533 second_reload_reg = 0;
6536 enum insn_code new_icode;
6537 enum machine_mode new_mode;
6539 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6540 REGNO (second_reload_reg)))
6541 oldequiv = old, real_oldequiv = real_old;
6544 new_icode = reload_in_optab[(int) mode];
6545 if (new_icode != CODE_FOR_nothing
6546 && ((insn_data[(int) new_icode].operand[0].predicate
6547 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6549 || (insn_data[(int) new_icode].operand[1].predicate
6550 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6551 (real_oldequiv, mode)))))
6552 new_icode = CODE_FOR_nothing;
6554 if (new_icode == CODE_FOR_nothing)
6557 new_mode = insn_data[(int) new_icode].operand[2].mode;
6559 if (GET_MODE (second_reload_reg) != new_mode)
6561 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6563 oldequiv = old, real_oldequiv = real_old;
6566 = gen_rtx_REG (new_mode,
6567 REGNO (second_reload_reg));
6573 /* If we still need a secondary reload register, check
6574 to see if it is being used as a scratch or intermediate
6575 register and generate code appropriately. If we need
6576 a scratch register, use REAL_OLDEQUIV since the form of
6577 the insn may depend on the actual address if it is
6580 if (second_reload_reg)
6582 if (icode != CODE_FOR_nothing)
6584 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6585 second_reload_reg));
6590 /* See if we need a scratch register to load the
6591 intermediate register (a tertiary reload). */
6592 enum insn_code tertiary_icode
6593 = rld[secondary_reload].secondary_in_icode;
6595 if (tertiary_icode != CODE_FOR_nothing)
6597 rtx third_reload_reg
6598 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6600 emit_insn ((GEN_FCN (tertiary_icode)
6601 (second_reload_reg, real_oldequiv,
6602 third_reload_reg)));
6605 gen_reload (second_reload_reg, real_oldequiv,
6609 oldequiv = second_reload_reg;
6615 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6617 rtx real_oldequiv = oldequiv;
6619 if ((GET_CODE (oldequiv) == REG
6620 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6621 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6622 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6623 || (GET_CODE (oldequiv) == SUBREG
6624 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6625 && (REGNO (SUBREG_REG (oldequiv))
6626 >= FIRST_PSEUDO_REGISTER)
6627 && ((reg_equiv_memory_loc
6628 [REGNO (SUBREG_REG (oldequiv))] != 0)
6629 || (reg_equiv_constant
6630 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6631 || (CONSTANT_P (oldequiv)
6632 && (PREFERRED_RELOAD_CLASS (oldequiv,
6633 REGNO_REG_CLASS (REGNO (reloadreg)))
6635 real_oldequiv = rl->in;
6636 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6640 if (flag_non_call_exceptions)
6641 copy_eh_notes (insn, get_insns ());
6643 /* End this sequence. */
6644 *where = get_insns ();
6647 /* Update reload_override_in so that delete_address_reloads_1
6648 can see the actual register usage. */
6650 reload_override_in[j] = oldequiv;
6653 /* Generate insns to for the output reload RL, which is for the insn described
6654 by CHAIN and has the number J. */
6656 emit_output_reload_insns (chain, rl, j)
6657 struct insn_chain *chain;
6661 rtx reloadreg = rl->reg_rtx;
6662 rtx insn = chain->insn;
6665 enum machine_mode mode = GET_MODE (old);
6668 if (rl->when_needed == RELOAD_OTHER)
6671 push_to_sequence (output_reload_insns[rl->opnum]);
6673 /* Determine the mode to reload in.
6674 See comments above (for input reloading). */
6676 if (mode == VOIDmode)
6678 /* VOIDmode should never happen for an output. */
6679 if (asm_noperands (PATTERN (insn)) < 0)
6680 /* It's the compiler's fault. */
6681 fatal_insn ("VOIDmode on an output", insn);
6682 error_for_asm (insn, "output operand is constant in `asm'");
6683 /* Prevent crash--use something we know is valid. */
6685 old = gen_rtx_REG (mode, REGNO (reloadreg));
6688 if (GET_MODE (reloadreg) != mode)
6689 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6691 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6693 /* If we need two reload regs, set RELOADREG to the intermediate
6694 one, since it will be stored into OLD. We might need a secondary
6695 register only for an input reload, so check again here. */
6697 if (rl->secondary_out_reload >= 0)
6701 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6702 && reg_equiv_mem[REGNO (old)] != 0)
6703 real_old = reg_equiv_mem[REGNO (old)];
6705 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6709 rtx second_reloadreg = reloadreg;
6710 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6712 /* See if RELOADREG is to be used as a scratch register
6713 or as an intermediate register. */
6714 if (rl->secondary_out_icode != CODE_FOR_nothing)
6716 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6717 (real_old, second_reloadreg, reloadreg)));
6722 /* See if we need both a scratch and intermediate reload
6725 int secondary_reload = rl->secondary_out_reload;
6726 enum insn_code tertiary_icode
6727 = rld[secondary_reload].secondary_out_icode;
6729 if (GET_MODE (reloadreg) != mode)
6730 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6732 if (tertiary_icode != CODE_FOR_nothing)
6735 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6738 /* Copy primary reload reg to secondary reload reg.
6739 (Note that these have been swapped above, then
6740 secondary reload reg to OLD using our insn.) */
6742 /* If REAL_OLD is a paradoxical SUBREG, remove it
6743 and try to put the opposite SUBREG on
6745 if (GET_CODE (real_old) == SUBREG
6746 && (GET_MODE_SIZE (GET_MODE (real_old))
6747 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6748 && 0 != (tem = gen_lowpart_common
6749 (GET_MODE (SUBREG_REG (real_old)),
6751 real_old = SUBREG_REG (real_old), reloadreg = tem;
6753 gen_reload (reloadreg, second_reloadreg,
6754 rl->opnum, rl->when_needed);
6755 emit_insn ((GEN_FCN (tertiary_icode)
6756 (real_old, reloadreg, third_reloadreg)));
6761 /* Copy between the reload regs here and then to
6764 gen_reload (reloadreg, second_reloadreg,
6765 rl->opnum, rl->when_needed);
6771 /* Output the last reload insn. */
6776 /* Don't output the last reload if OLD is not the dest of
6777 INSN and is in the src and is clobbered by INSN. */
6778 if (! flag_expensive_optimizations
6779 || GET_CODE (old) != REG
6780 || !(set = single_set (insn))
6781 || rtx_equal_p (old, SET_DEST (set))
6782 || !reg_mentioned_p (old, SET_SRC (set))
6783 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6784 gen_reload (old, reloadreg, rl->opnum,
6788 /* Look at all insns we emitted, just to be safe. */
6789 for (p = get_insns (); p; p = NEXT_INSN (p))
6792 rtx pat = PATTERN (p);
6794 /* If this output reload doesn't come from a spill reg,
6795 clear any memory of reloaded copies of the pseudo reg.
6796 If this output reload comes from a spill reg,
6797 reg_has_output_reload will make this do nothing. */
6798 note_stores (pat, forget_old_reloads_1, NULL);
6800 if (reg_mentioned_p (rl->reg_rtx, pat))
6802 rtx set = single_set (insn);
6803 if (reload_spill_index[j] < 0
6805 && SET_SRC (set) == rl->reg_rtx)
6807 int src = REGNO (SET_SRC (set));
6809 reload_spill_index[j] = src;
6810 SET_HARD_REG_BIT (reg_is_output_reload, src);
6811 if (find_regno_note (insn, REG_DEAD, src))
6812 SET_HARD_REG_BIT (reg_reloaded_died, src);
6814 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6816 int s = rl->secondary_out_reload;
6817 set = single_set (p);
6818 /* If this reload copies only to the secondary reload
6819 register, the secondary reload does the actual
6821 if (s >= 0 && set == NULL_RTX)
6822 /* We can't tell what function the secondary reload
6823 has and where the actual store to the pseudo is
6824 made; leave new_spill_reg_store alone. */
6827 && SET_SRC (set) == rl->reg_rtx
6828 && SET_DEST (set) == rld[s].reg_rtx)
6830 /* Usually the next instruction will be the
6831 secondary reload insn; if we can confirm
6832 that it is, setting new_spill_reg_store to
6833 that insn will allow an extra optimization. */
6834 rtx s_reg = rld[s].reg_rtx;
6835 rtx next = NEXT_INSN (p);
6836 rld[s].out = rl->out;
6837 rld[s].out_reg = rl->out_reg;
6838 set = single_set (next);
6839 if (set && SET_SRC (set) == s_reg
6840 && ! new_spill_reg_store[REGNO (s_reg)])
6842 SET_HARD_REG_BIT (reg_is_output_reload,
6844 new_spill_reg_store[REGNO (s_reg)] = next;
6848 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6853 if (rl->when_needed == RELOAD_OTHER)
6855 emit_insn (other_output_reload_insns[rl->opnum]);
6856 other_output_reload_insns[rl->opnum] = get_insns ();
6859 output_reload_insns[rl->opnum] = get_insns ();
6861 if (flag_non_call_exceptions)
6862 copy_eh_notes (insn, get_insns ());
6867 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6868 and has the number J. */
6870 do_input_reload (chain, rl, j)
6871 struct insn_chain *chain;
6875 rtx insn = chain->insn;
6876 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6877 ? rl->in_reg : rl->in);
6880 /* AUTO_INC reloads need to be handled even if inherited. We got an
6881 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6882 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6883 && ! rtx_equal_p (rl->reg_rtx, old)
6884 && rl->reg_rtx != 0)
6885 emit_input_reload_insns (chain, rld + j, old, j);
6887 /* When inheriting a wider reload, we have a MEM in rl->in,
6888 e.g. inheriting a SImode output reload for
6889 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6890 if (optimize && reload_inherited[j] && rl->in
6891 && GET_CODE (rl->in) == MEM
6892 && GET_CODE (rl->in_reg) == MEM
6893 && reload_spill_index[j] >= 0
6894 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6895 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6897 /* If we are reloading a register that was recently stored in with an
6898 output-reload, see if we can prove there was
6899 actually no need to store the old value in it. */
6902 && (reload_inherited[j] || reload_override_in[j])
6904 && GET_CODE (rl->reg_rtx) == REG
6905 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6907 /* There doesn't seem to be any reason to restrict this to pseudos
6908 and doing so loses in the case where we are copying from a
6909 register of the wrong class. */
6910 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6911 >= FIRST_PSEUDO_REGISTER)
6913 /* The insn might have already some references to stackslots
6914 replaced by MEMs, while reload_out_reg still names the
6916 && (dead_or_set_p (insn,
6917 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6918 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6920 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6923 /* Do output reloading for reload RL, which is for the insn described by
6924 CHAIN and has the number J.
6925 ??? At some point we need to support handling output reloads of
6926 JUMP_INSNs or insns that set cc0. */
6928 do_output_reload (chain, rl, j)
6929 struct insn_chain *chain;
6934 rtx insn = chain->insn;
6935 /* If this is an output reload that stores something that is
6936 not loaded in this same reload, see if we can eliminate a previous
6938 rtx pseudo = rl->out_reg;
6942 && GET_CODE (pseudo) == REG
6943 && ! rtx_equal_p (rl->in_reg, pseudo)
6944 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6945 && reg_last_reload_reg[REGNO (pseudo)])
6947 int pseudo_no = REGNO (pseudo);
6948 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6950 /* We don't need to test full validity of last_regno for
6951 inherit here; we only want to know if the store actually
6952 matches the pseudo. */
6953 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6954 && reg_reloaded_contents[last_regno] == pseudo_no
6955 && spill_reg_store[last_regno]
6956 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6957 delete_output_reload (insn, j, last_regno);
6962 || rl->reg_rtx == old
6963 || rl->reg_rtx == 0)
6966 /* An output operand that dies right away does need a reload,
6967 but need not be copied from it. Show the new location in the
6969 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6970 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6972 XEXP (note, 0) = rl->reg_rtx;
6975 /* Likewise for a SUBREG of an operand that dies. */
6976 else if (GET_CODE (old) == SUBREG
6977 && GET_CODE (SUBREG_REG (old)) == REG
6978 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6981 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6985 else if (GET_CODE (old) == SCRATCH)
6986 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6987 but we don't want to make an output reload. */
6990 /* If is a JUMP_INSN, we can't support output reloads yet. */
6991 if (GET_CODE (insn) == JUMP_INSN)
6994 emit_output_reload_insns (chain, rld + j, j);
6997 /* Output insns to reload values in and out of the chosen reload regs. */
7000 emit_reload_insns (chain)
7001 struct insn_chain *chain;
7003 rtx insn = chain->insn;
7007 CLEAR_HARD_REG_SET (reg_reloaded_died);
7009 for (j = 0; j < reload_n_operands; j++)
7010 input_reload_insns[j] = input_address_reload_insns[j]
7011 = inpaddr_address_reload_insns[j]
7012 = output_reload_insns[j] = output_address_reload_insns[j]
7013 = outaddr_address_reload_insns[j]
7014 = other_output_reload_insns[j] = 0;
7015 other_input_address_reload_insns = 0;
7016 other_input_reload_insns = 0;
7017 operand_reload_insns = 0;
7018 other_operand_reload_insns = 0;
7020 /* Dump reloads into the dump file. */
7023 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7024 debug_reload_to_stream (rtl_dump_file);
7027 /* Now output the instructions to copy the data into and out of the
7028 reload registers. Do these in the order that the reloads were reported,
7029 since reloads of base and index registers precede reloads of operands
7030 and the operands may need the base and index registers reloaded. */
7032 for (j = 0; j < n_reloads; j++)
7035 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7036 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7038 do_input_reload (chain, rld + j, j);
7039 do_output_reload (chain, rld + j, j);
7042 /* Now write all the insns we made for reloads in the order expected by
7043 the allocation functions. Prior to the insn being reloaded, we write
7044 the following reloads:
7046 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7048 RELOAD_OTHER reloads.
7050 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7051 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7052 RELOAD_FOR_INPUT reload for the operand.
7054 RELOAD_FOR_OPADDR_ADDRS reloads.
7056 RELOAD_FOR_OPERAND_ADDRESS reloads.
7058 After the insn being reloaded, we write the following:
7060 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7061 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7062 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7063 reloads for the operand. The RELOAD_OTHER output reloads are
7064 output in descending order by reload number. */
7066 emit_insn_before (other_input_address_reload_insns, insn);
7067 emit_insn_before (other_input_reload_insns, insn);
7069 for (j = 0; j < reload_n_operands; j++)
7071 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7072 emit_insn_before (input_address_reload_insns[j], insn);
7073 emit_insn_before (input_reload_insns[j], insn);
7076 emit_insn_before (other_operand_reload_insns, insn);
7077 emit_insn_before (operand_reload_insns, insn);
7079 for (j = 0; j < reload_n_operands; j++)
7081 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7082 x = emit_insn_after (output_address_reload_insns[j], x);
7083 x = emit_insn_after (output_reload_insns[j], x);
7084 emit_insn_after (other_output_reload_insns[j], x);
7087 /* For all the spill regs newly reloaded in this instruction,
7088 record what they were reloaded from, so subsequent instructions
7089 can inherit the reloads.
7091 Update spill_reg_store for the reloads of this insn.
7092 Copy the elements that were updated in the loop above. */
7094 for (j = 0; j < n_reloads; j++)
7096 int r = reload_order[j];
7097 int i = reload_spill_index[r];
7099 /* If this is a non-inherited input reload from a pseudo, we must
7100 clear any memory of a previous store to the same pseudo. Only do
7101 something if there will not be an output reload for the pseudo
7103 if (rld[r].in_reg != 0
7104 && ! (reload_inherited[r] || reload_override_in[r]))
7106 rtx reg = rld[r].in_reg;
7108 if (GET_CODE (reg) == SUBREG)
7109 reg = SUBREG_REG (reg);
7111 if (GET_CODE (reg) == REG
7112 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7113 && ! reg_has_output_reload[REGNO (reg)])
7115 int nregno = REGNO (reg);
7117 if (reg_last_reload_reg[nregno])
7119 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7121 if (reg_reloaded_contents[last_regno] == nregno)
7122 spill_reg_store[last_regno] = 0;
7127 /* I is nonneg if this reload used a register.
7128 If rld[r].reg_rtx is 0, this is an optional reload
7129 that we opted to ignore. */
7131 if (i >= 0 && rld[r].reg_rtx != 0)
7133 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7135 int part_reaches_end = 0;
7136 int all_reaches_end = 1;
7138 /* For a multi register reload, we need to check if all or part
7139 of the value lives to the end. */
7140 for (k = 0; k < nr; k++)
7142 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7143 rld[r].when_needed))
7144 part_reaches_end = 1;
7146 all_reaches_end = 0;
7149 /* Ignore reloads that don't reach the end of the insn in
7151 if (all_reaches_end)
7153 /* First, clear out memory of what used to be in this spill reg.
7154 If consecutive registers are used, clear them all. */
7156 for (k = 0; k < nr; k++)
7157 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7159 /* Maybe the spill reg contains a copy of reload_out. */
7161 && (GET_CODE (rld[r].out) == REG
7165 || GET_CODE (rld[r].out_reg) == REG))
7167 rtx out = (GET_CODE (rld[r].out) == REG
7171 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7172 int nregno = REGNO (out);
7173 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7174 : HARD_REGNO_NREGS (nregno,
7175 GET_MODE (rld[r].reg_rtx)));
7177 spill_reg_store[i] = new_spill_reg_store[i];
7178 spill_reg_stored_to[i] = out;
7179 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7181 /* If NREGNO is a hard register, it may occupy more than
7182 one register. If it does, say what is in the
7183 rest of the registers assuming that both registers
7184 agree on how many words the object takes. If not,
7185 invalidate the subsequent registers. */
7187 if (nregno < FIRST_PSEUDO_REGISTER)
7188 for (k = 1; k < nnr; k++)
7189 reg_last_reload_reg[nregno + k]
7191 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7194 /* Now do the inverse operation. */
7195 for (k = 0; k < nr; k++)
7197 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7198 reg_reloaded_contents[i + k]
7199 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7202 reg_reloaded_insn[i + k] = insn;
7203 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7207 /* Maybe the spill reg contains a copy of reload_in. Only do
7208 something if there will not be an output reload for
7209 the register being reloaded. */
7210 else if (rld[r].out_reg == 0
7212 && ((GET_CODE (rld[r].in) == REG
7213 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7214 && ! reg_has_output_reload[REGNO (rld[r].in)])
7215 || (GET_CODE (rld[r].in_reg) == REG
7216 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7217 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7222 if (GET_CODE (rld[r].in) == REG
7223 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7224 nregno = REGNO (rld[r].in);
7225 else if (GET_CODE (rld[r].in_reg) == REG)
7226 nregno = REGNO (rld[r].in_reg);
7228 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7230 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7231 : HARD_REGNO_NREGS (nregno,
7232 GET_MODE (rld[r].reg_rtx)));
7234 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7236 if (nregno < FIRST_PSEUDO_REGISTER)
7237 for (k = 1; k < nnr; k++)
7238 reg_last_reload_reg[nregno + k]
7240 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7243 /* Unless we inherited this reload, show we haven't
7244 recently done a store.
7245 Previous stores of inherited auto_inc expressions
7246 also have to be discarded. */
7247 if (! reload_inherited[r]
7248 || (rld[r].out && ! rld[r].out_reg))
7249 spill_reg_store[i] = 0;
7251 for (k = 0; k < nr; k++)
7253 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7254 reg_reloaded_contents[i + k]
7255 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7258 reg_reloaded_insn[i + k] = insn;
7259 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7264 /* However, if part of the reload reaches the end, then we must
7265 invalidate the old info for the part that survives to the end. */
7266 else if (part_reaches_end)
7268 for (k = 0; k < nr; k++)
7269 if (reload_reg_reaches_end_p (i + k,
7271 rld[r].when_needed))
7272 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7276 /* The following if-statement was #if 0'd in 1.34 (or before...).
7277 It's reenabled in 1.35 because supposedly nothing else
7278 deals with this problem. */
7280 /* If a register gets output-reloaded from a non-spill register,
7281 that invalidates any previous reloaded copy of it.
7282 But forget_old_reloads_1 won't get to see it, because
7283 it thinks only about the original insn. So invalidate it here. */
7284 if (i < 0 && rld[r].out != 0
7285 && (GET_CODE (rld[r].out) == REG
7286 || (GET_CODE (rld[r].out) == MEM
7287 && GET_CODE (rld[r].out_reg) == REG)))
7289 rtx out = (GET_CODE (rld[r].out) == REG
7290 ? rld[r].out : rld[r].out_reg);
7291 int nregno = REGNO (out);
7292 if (nregno >= FIRST_PSEUDO_REGISTER)
7294 rtx src_reg, store_insn = NULL_RTX;
7296 reg_last_reload_reg[nregno] = 0;
7298 /* If we can find a hard register that is stored, record
7299 the storing insn so that we may delete this insn with
7300 delete_output_reload. */
7301 src_reg = rld[r].reg_rtx;
7303 /* If this is an optional reload, try to find the source reg
7304 from an input reload. */
7307 rtx set = single_set (insn);
7308 if (set && SET_DEST (set) == rld[r].out)
7312 src_reg = SET_SRC (set);
7314 for (k = 0; k < n_reloads; k++)
7316 if (rld[k].in == src_reg)
7318 src_reg = rld[k].reg_rtx;
7325 store_insn = new_spill_reg_store[REGNO (src_reg)];
7326 if (src_reg && GET_CODE (src_reg) == REG
7327 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7329 int src_regno = REGNO (src_reg);
7330 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7331 /* The place where to find a death note varies with
7332 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7333 necessarily checked exactly in the code that moves
7334 notes, so just check both locations. */
7335 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7336 if (! note && store_insn)
7337 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7340 spill_reg_store[src_regno + nr] = store_insn;
7341 spill_reg_stored_to[src_regno + nr] = out;
7342 reg_reloaded_contents[src_regno + nr] = nregno;
7343 reg_reloaded_insn[src_regno + nr] = store_insn;
7344 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7345 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7346 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7348 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7350 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7352 reg_last_reload_reg[nregno] = src_reg;
7357 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7359 while (num_regs-- > 0)
7360 reg_last_reload_reg[nregno + num_regs] = 0;
7364 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7367 /* Emit code to perform a reload from IN (which may be a reload register) to
7368 OUT (which may also be a reload register). IN or OUT is from operand
7369 OPNUM with reload type TYPE.
7371 Returns first insn emitted. */
7374 gen_reload (out, in, opnum, type)
7378 enum reload_type type;
7380 rtx last = get_last_insn ();
7383 /* If IN is a paradoxical SUBREG, remove it and try to put the
7384 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7385 if (GET_CODE (in) == SUBREG
7386 && (GET_MODE_SIZE (GET_MODE (in))
7387 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7388 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7389 in = SUBREG_REG (in), out = tem;
7390 else if (GET_CODE (out) == SUBREG
7391 && (GET_MODE_SIZE (GET_MODE (out))
7392 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7393 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7394 out = SUBREG_REG (out), in = tem;
7396 /* How to do this reload can get quite tricky. Normally, we are being
7397 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7398 register that didn't get a hard register. In that case we can just
7399 call emit_move_insn.
7401 We can also be asked to reload a PLUS that adds a register or a MEM to
7402 another register, constant or MEM. This can occur during frame pointer
7403 elimination and while reloading addresses. This case is handled by
7404 trying to emit a single insn to perform the add. If it is not valid,
7405 we use a two insn sequence.
7407 Finally, we could be called to handle an 'o' constraint by putting
7408 an address into a register. In that case, we first try to do this
7409 with a named pattern of "reload_load_address". If no such pattern
7410 exists, we just emit a SET insn and hope for the best (it will normally
7411 be valid on machines that use 'o').
7413 This entire process is made complex because reload will never
7414 process the insns we generate here and so we must ensure that
7415 they will fit their constraints and also by the fact that parts of
7416 IN might be being reloaded separately and replaced with spill registers.
7417 Because of this, we are, in some sense, just guessing the right approach
7418 here. The one listed above seems to work.
7420 ??? At some point, this whole thing needs to be rethought. */
7422 if (GET_CODE (in) == PLUS
7423 && (GET_CODE (XEXP (in, 0)) == REG
7424 || GET_CODE (XEXP (in, 0)) == SUBREG
7425 || GET_CODE (XEXP (in, 0)) == MEM)
7426 && (GET_CODE (XEXP (in, 1)) == REG
7427 || GET_CODE (XEXP (in, 1)) == SUBREG
7428 || CONSTANT_P (XEXP (in, 1))
7429 || GET_CODE (XEXP (in, 1)) == MEM))
7431 /* We need to compute the sum of a register or a MEM and another
7432 register, constant, or MEM, and put it into the reload
7433 register. The best possible way of doing this is if the machine
7434 has a three-operand ADD insn that accepts the required operands.
7436 The simplest approach is to try to generate such an insn and see if it
7437 is recognized and matches its constraints. If so, it can be used.
7439 It might be better not to actually emit the insn unless it is valid,
7440 but we need to pass the insn as an operand to `recog' and
7441 `extract_insn' and it is simpler to emit and then delete the insn if
7442 not valid than to dummy things up. */
7444 rtx op0, op1, tem, insn;
7447 op0 = find_replacement (&XEXP (in, 0));
7448 op1 = find_replacement (&XEXP (in, 1));
7450 /* Since constraint checking is strict, commutativity won't be
7451 checked, so we need to do that here to avoid spurious failure
7452 if the add instruction is two-address and the second operand
7453 of the add is the same as the reload reg, which is frequently
7454 the case. If the insn would be A = B + A, rearrange it so
7455 it will be A = A + B as constrain_operands expects. */
7457 if (GET_CODE (XEXP (in, 1)) == REG
7458 && REGNO (out) == REGNO (XEXP (in, 1)))
7459 tem = op0, op0 = op1, op1 = tem;
7461 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7462 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7464 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7465 code = recog_memoized (insn);
7469 extract_insn (insn);
7470 /* We want constrain operands to treat this insn strictly in
7471 its validity determination, i.e., the way it would after reload
7473 if (constrain_operands (1))
7477 delete_insns_since (last);
7479 /* If that failed, we must use a conservative two-insn sequence.
7481 Use a move to copy one operand into the reload register. Prefer
7482 to reload a constant, MEM or pseudo since the move patterns can
7483 handle an arbitrary operand. If OP1 is not a constant, MEM or
7484 pseudo and OP1 is not a valid operand for an add instruction, then
7487 After reloading one of the operands into the reload register, add
7488 the reload register to the output register.
7490 If there is another way to do this for a specific machine, a
7491 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7494 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7496 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7497 || (GET_CODE (op1) == REG
7498 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7499 || (code != CODE_FOR_nothing
7500 && ! ((*insn_data[code].operand[2].predicate)
7501 (op1, insn_data[code].operand[2].mode))))
7502 tem = op0, op0 = op1, op1 = tem;
7504 gen_reload (out, op0, opnum, type);
7506 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7507 This fixes a problem on the 32K where the stack pointer cannot
7508 be used as an operand of an add insn. */
7510 if (rtx_equal_p (op0, op1))
7513 insn = emit_insn (gen_add2_insn (out, op1));
7515 /* If that failed, copy the address register to the reload register.
7516 Then add the constant to the reload register. */
7518 code = recog_memoized (insn);
7522 extract_insn (insn);
7523 /* We want constrain operands to treat this insn strictly in
7524 its validity determination, i.e., the way it would after reload
7526 if (constrain_operands (1))
7528 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7530 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7535 delete_insns_since (last);
7537 gen_reload (out, op1, opnum, type);
7538 insn = emit_insn (gen_add2_insn (out, op0));
7539 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7542 #ifdef SECONDARY_MEMORY_NEEDED
7543 /* If we need a memory location to do the move, do it that way. */
7544 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7545 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7546 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7547 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7548 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7549 REGNO_REG_CLASS (reg_or_subregno (out)),
7552 /* Get the memory to use and rewrite both registers to its mode. */
7553 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7555 if (GET_MODE (loc) != GET_MODE (out))
7556 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7558 if (GET_MODE (loc) != GET_MODE (in))
7559 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7561 gen_reload (loc, in, opnum, type);
7562 gen_reload (out, loc, opnum, type);
7566 /* If IN is a simple operand, use gen_move_insn. */
7567 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7568 emit_insn (gen_move_insn (out, in));
7570 #ifdef HAVE_reload_load_address
7571 else if (HAVE_reload_load_address)
7572 emit_insn (gen_reload_load_address (out, in));
7575 /* Otherwise, just write (set OUT IN) and hope for the best. */
7577 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7579 /* Return the first insn emitted.
7580 We can not just return get_last_insn, because there may have
7581 been multiple instructions emitted. Also note that gen_move_insn may
7582 emit more than one insn itself, so we can not assume that there is one
7583 insn emitted per emit_insn_before call. */
7585 return last ? NEXT_INSN (last) : get_insns ();
7588 /* Delete a previously made output-reload whose result we now believe
7589 is not needed. First we double-check.
7591 INSN is the insn now being processed.
7592 LAST_RELOAD_REG is the hard register number for which we want to delete
7593 the last output reload.
7594 J is the reload-number that originally used REG. The caller has made
7595 certain that reload J doesn't use REG any longer for input. */
7598 delete_output_reload (insn, j, last_reload_reg)
7601 int last_reload_reg;
7603 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7604 rtx reg = spill_reg_stored_to[last_reload_reg];
7607 int n_inherited = 0;
7611 /* Get the raw pseudo-register referred to. */
7613 while (GET_CODE (reg) == SUBREG)
7614 reg = SUBREG_REG (reg);
7615 substed = reg_equiv_memory_loc[REGNO (reg)];
7617 /* This is unsafe if the operand occurs more often in the current
7618 insn than it is inherited. */
7619 for (k = n_reloads - 1; k >= 0; k--)
7621 rtx reg2 = rld[k].in;
7624 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7625 reg2 = rld[k].in_reg;
7627 if (rld[k].out && ! rld[k].out_reg)
7628 reg2 = XEXP (rld[k].in_reg, 0);
7630 while (GET_CODE (reg2) == SUBREG)
7631 reg2 = SUBREG_REG (reg2);
7632 if (rtx_equal_p (reg2, reg))
7634 if (reload_inherited[k] || reload_override_in[k] || k == j)
7637 reg2 = rld[k].out_reg;
7640 while (GET_CODE (reg2) == SUBREG)
7641 reg2 = XEXP (reg2, 0);
7642 if (rtx_equal_p (reg2, reg))
7649 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7651 n_occurrences += count_occurrences (PATTERN (insn),
7652 eliminate_regs (substed, 0,
7654 if (n_occurrences > n_inherited)
7657 /* If the pseudo-reg we are reloading is no longer referenced
7658 anywhere between the store into it and here,
7659 and no jumps or labels intervene, then the value can get
7660 here through the reload reg alone.
7661 Otherwise, give up--return. */
7662 for (i1 = NEXT_INSN (output_reload_insn);
7663 i1 != insn; i1 = NEXT_INSN (i1))
7665 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7667 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7668 && reg_mentioned_p (reg, PATTERN (i1)))
7670 /* If this is USE in front of INSN, we only have to check that
7671 there are no more references than accounted for by inheritance. */
7672 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7674 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7675 i1 = NEXT_INSN (i1);
7677 if (n_occurrences <= n_inherited && i1 == insn)
7683 /* We will be deleting the insn. Remove the spill reg information. */
7684 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7686 spill_reg_store[last_reload_reg + k] = 0;
7687 spill_reg_stored_to[last_reload_reg + k] = 0;
7690 /* The caller has already checked that REG dies or is set in INSN.
7691 It has also checked that we are optimizing, and thus some
7692 inaccuracies in the debugging information are acceptable.
7693 So we could just delete output_reload_insn. But in some cases
7694 we can improve the debugging information without sacrificing
7695 optimization - maybe even improving the code: See if the pseudo
7696 reg has been completely replaced with reload regs. If so, delete
7697 the store insn and forget we had a stack slot for the pseudo. */
7698 if (rld[j].out != rld[j].in
7699 && REG_N_DEATHS (REGNO (reg)) == 1
7700 && REG_N_SETS (REGNO (reg)) == 1
7701 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7702 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7706 /* We know that it was used only between here and the beginning of
7707 the current basic block. (We also know that the last use before
7708 INSN was the output reload we are thinking of deleting, but never
7709 mind that.) Search that range; see if any ref remains. */
7710 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7712 rtx set = single_set (i2);
7714 /* Uses which just store in the pseudo don't count,
7715 since if they are the only uses, they are dead. */
7716 if (set != 0 && SET_DEST (set) == reg)
7718 if (GET_CODE (i2) == CODE_LABEL
7719 || GET_CODE (i2) == JUMP_INSN)
7721 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7722 && reg_mentioned_p (reg, PATTERN (i2)))
7724 /* Some other ref remains; just delete the output reload we
7726 delete_address_reloads (output_reload_insn, insn);
7727 delete_insn (output_reload_insn);
7732 /* Delete the now-dead stores into this pseudo. Note that this
7733 loop also takes care of deleting output_reload_insn. */
7734 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7736 rtx set = single_set (i2);
7738 if (set != 0 && SET_DEST (set) == reg)
7740 delete_address_reloads (i2, insn);
7743 if (GET_CODE (i2) == CODE_LABEL
7744 || GET_CODE (i2) == JUMP_INSN)
7748 /* For the debugging info, say the pseudo lives in this reload reg. */
7749 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7750 alter_reg (REGNO (reg), -1);
7754 delete_address_reloads (output_reload_insn, insn);
7755 delete_insn (output_reload_insn);
7759 /* We are going to delete DEAD_INSN. Recursively delete loads of
7760 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7761 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7763 delete_address_reloads (dead_insn, current_insn)
7764 rtx dead_insn, current_insn;
7766 rtx set = single_set (dead_insn);
7767 rtx set2, dst, prev, next;
7770 rtx dst = SET_DEST (set);
7771 if (GET_CODE (dst) == MEM)
7772 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7774 /* If we deleted the store from a reloaded post_{in,de}c expression,
7775 we can delete the matching adds. */
7776 prev = PREV_INSN (dead_insn);
7777 next = NEXT_INSN (dead_insn);
7778 if (! prev || ! next)
7780 set = single_set (next);
7781 set2 = single_set (prev);
7783 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7784 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7785 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7787 dst = SET_DEST (set);
7788 if (! rtx_equal_p (dst, SET_DEST (set2))
7789 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7790 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7791 || (INTVAL (XEXP (SET_SRC (set), 1))
7792 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7794 delete_related_insns (prev);
7795 delete_related_insns (next);
7798 /* Subfunction of delete_address_reloads: process registers found in X. */
7800 delete_address_reloads_1 (dead_insn, x, current_insn)
7801 rtx dead_insn, x, current_insn;
7803 rtx prev, set, dst, i2;
7805 enum rtx_code code = GET_CODE (x);
7809 const char *fmt = GET_RTX_FORMAT (code);
7810 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7813 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7814 else if (fmt[i] == 'E')
7816 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7817 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7824 if (spill_reg_order[REGNO (x)] < 0)
7827 /* Scan backwards for the insn that sets x. This might be a way back due
7829 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7831 code = GET_CODE (prev);
7832 if (code == CODE_LABEL || code == JUMP_INSN)
7834 if (GET_RTX_CLASS (code) != 'i')
7836 if (reg_set_p (x, PATTERN (prev)))
7838 if (reg_referenced_p (x, PATTERN (prev)))
7841 if (! prev || INSN_UID (prev) < reload_first_uid)
7843 /* Check that PREV only sets the reload register. */
7844 set = single_set (prev);
7847 dst = SET_DEST (set);
7848 if (GET_CODE (dst) != REG
7849 || ! rtx_equal_p (dst, x))
7851 if (! reg_set_p (dst, PATTERN (dead_insn)))
7853 /* Check if DST was used in a later insn -
7854 it might have been inherited. */
7855 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7857 if (GET_CODE (i2) == CODE_LABEL)
7861 if (reg_referenced_p (dst, PATTERN (i2)))
7863 /* If there is a reference to the register in the current insn,
7864 it might be loaded in a non-inherited reload. If no other
7865 reload uses it, that means the register is set before
7867 if (i2 == current_insn)
7869 for (j = n_reloads - 1; j >= 0; j--)
7870 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7871 || reload_override_in[j] == dst)
7873 for (j = n_reloads - 1; j >= 0; j--)
7874 if (rld[j].in && rld[j].reg_rtx == dst)
7881 if (GET_CODE (i2) == JUMP_INSN)
7883 /* If DST is still live at CURRENT_INSN, check if it is used for
7884 any reload. Note that even if CURRENT_INSN sets DST, we still
7885 have to check the reloads. */
7886 if (i2 == current_insn)
7888 for (j = n_reloads - 1; j >= 0; j--)
7889 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7890 || reload_override_in[j] == dst)
7892 /* ??? We can't finish the loop here, because dst might be
7893 allocated to a pseudo in this block if no reload in this
7894 block needs any of the classes containing DST - see
7895 spill_hard_reg. There is no easy way to tell this, so we
7896 have to scan till the end of the basic block. */
7898 if (reg_set_p (dst, PATTERN (i2)))
7902 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7903 reg_reloaded_contents[REGNO (dst)] = -1;
7907 /* Output reload-insns to reload VALUE into RELOADREG.
7908 VALUE is an autoincrement or autodecrement RTX whose operand
7909 is a register or memory location;
7910 so reloading involves incrementing that location.
7911 IN is either identical to VALUE, or some cheaper place to reload from.
7913 INC_AMOUNT is the number to increment or decrement by (always positive).
7914 This cannot be deduced from VALUE.
7916 Return the instruction that stores into RELOADREG. */
7919 inc_for_reload (reloadreg, in, value, inc_amount)
7924 /* REG or MEM to be copied and incremented. */
7925 rtx incloc = XEXP (value, 0);
7926 /* Nonzero if increment after copying. */
7927 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7933 rtx real_in = in == value ? XEXP (in, 0) : in;
7935 /* No hard register is equivalent to this register after
7936 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7937 we could inc/dec that register as well (maybe even using it for
7938 the source), but I'm not sure it's worth worrying about. */
7939 if (GET_CODE (incloc) == REG)
7940 reg_last_reload_reg[REGNO (incloc)] = 0;
7942 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7943 inc_amount = -inc_amount;
7945 inc = GEN_INT (inc_amount);
7947 /* If this is post-increment, first copy the location to the reload reg. */
7948 if (post && real_in != reloadreg)
7949 emit_insn (gen_move_insn (reloadreg, real_in));
7953 /* See if we can directly increment INCLOC. Use a method similar to
7954 that in gen_reload. */
7956 last = get_last_insn ();
7957 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7958 gen_rtx_PLUS (GET_MODE (incloc),
7961 code = recog_memoized (add_insn);
7964 extract_insn (add_insn);
7965 if (constrain_operands (1))
7967 /* If this is a pre-increment and we have incremented the value
7968 where it lives, copy the incremented value to RELOADREG to
7969 be used as an address. */
7972 emit_insn (gen_move_insn (reloadreg, incloc));
7977 delete_insns_since (last);
7980 /* If couldn't do the increment directly, must increment in RELOADREG.
7981 The way we do this depends on whether this is pre- or post-increment.
7982 For pre-increment, copy INCLOC to the reload register, increment it
7983 there, then save back. */
7987 if (in != reloadreg)
7988 emit_insn (gen_move_insn (reloadreg, real_in));
7989 emit_insn (gen_add2_insn (reloadreg, inc));
7990 store = emit_insn (gen_move_insn (incloc, reloadreg));
7995 Because this might be a jump insn or a compare, and because RELOADREG
7996 may not be available after the insn in an input reload, we must do
7997 the incrementation before the insn being reloaded for.
7999 We have already copied IN to RELOADREG. Increment the copy in
8000 RELOADREG, save that back, then decrement RELOADREG so it has
8001 the original value. */
8003 emit_insn (gen_add2_insn (reloadreg, inc));
8004 store = emit_insn (gen_move_insn (incloc, reloadreg));
8005 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8012 /* See whether a single set SET is a noop. */
8014 reload_cse_noop_set_p (set)
8017 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8020 /* Try to simplify INSN. */
8022 reload_cse_simplify (insn, testreg)
8026 rtx body = PATTERN (insn);
8028 if (GET_CODE (body) == SET)
8032 /* Simplify even if we may think it is a no-op.
8033 We may think a memory load of a value smaller than WORD_SIZE
8034 is redundant because we haven't taken into account possible
8035 implicit extension. reload_cse_simplify_set() will bring
8036 this out, so it's safer to simplify before we delete. */
8037 count += reload_cse_simplify_set (body, insn);
8039 if (!count && reload_cse_noop_set_p (body))
8041 rtx value = SET_DEST (body);
8043 && ! REG_FUNCTION_VALUE_P (value))
8045 delete_insn_and_edges (insn);
8050 apply_change_group ();
8052 reload_cse_simplify_operands (insn, testreg);
8054 else if (GET_CODE (body) == PARALLEL)
8058 rtx value = NULL_RTX;
8060 /* If every action in a PARALLEL is a noop, we can delete
8061 the entire PARALLEL. */
8062 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8064 rtx part = XVECEXP (body, 0, i);
8065 if (GET_CODE (part) == SET)
8067 if (! reload_cse_noop_set_p (part))
8069 if (REG_P (SET_DEST (part))
8070 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
8074 value = SET_DEST (part);
8077 else if (GET_CODE (part) != CLOBBER)
8083 delete_insn_and_edges (insn);
8084 /* We're done with this insn. */
8088 /* It's not a no-op, but we can try to simplify it. */
8089 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8090 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8091 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8094 apply_change_group ();
8096 reload_cse_simplify_operands (insn, testreg);
8100 /* Do a very simple CSE pass over the hard registers.
8102 This function detects no-op moves where we happened to assign two
8103 different pseudo-registers to the same hard register, and then
8104 copied one to the other. Reload will generate a useless
8105 instruction copying a register to itself.
8107 This function also detects cases where we load a value from memory
8108 into two different registers, and (if memory is more expensive than
8109 registers) changes it to simply copy the first register into the
8112 Another optimization is performed that scans the operands of each
8113 instruction to see whether the value is already available in a
8114 hard register. It then replaces the operand with the hard register
8115 if possible, much like an optional reload would. */
8118 reload_cse_regs_1 (first)
8122 rtx testreg = gen_rtx_REG (VOIDmode, -1);
8125 init_alias_analysis ();
8127 for (insn = first; insn; insn = NEXT_INSN (insn))
8130 reload_cse_simplify (insn, testreg);
8132 cselib_process_insn (insn);
8136 end_alias_analysis ();
8140 /* Call cse / combine like post-reload optimization phases.
8141 FIRST is the first instruction. */
8143 reload_cse_regs (first)
8146 reload_cse_regs_1 (first);
8148 reload_cse_move2add (first);
8149 if (flag_expensive_optimizations)
8150 reload_cse_regs_1 (first);
8153 /* Try to simplify a single SET instruction. SET is the set pattern.
8154 INSN is the instruction it came from.
8155 This function only handles one case: if we set a register to a value
8156 which is not a register, we try to find that value in some other register
8157 and change the set into a register copy. */
8160 reload_cse_simplify_set (set, insn)
8167 enum reg_class dclass;
8170 struct elt_loc_list *l;
8171 #ifdef LOAD_EXTEND_OP
8172 enum rtx_code extend_op = NIL;
8175 dreg = true_regnum (SET_DEST (set));
8179 src = SET_SRC (set);
8180 if (side_effects_p (src) || true_regnum (src) >= 0)
8183 dclass = REGNO_REG_CLASS (dreg);
8185 #ifdef LOAD_EXTEND_OP
8186 /* When replacing a memory with a register, we need to honor assumptions
8187 that combine made wrt the contents of sign bits. We'll do this by
8188 generating an extend instruction instead of a reg->reg copy. Thus
8189 the destination must be a register that we can widen. */
8190 if (GET_CODE (src) == MEM
8191 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8192 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8193 && GET_CODE (SET_DEST (set)) != REG)
8197 /* If memory loads are cheaper than register copies, don't change them. */
8198 if (GET_CODE (src) == MEM)
8199 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8200 else if (CONSTANT_P (src))
8201 old_cost = rtx_cost (src, SET);
8202 else if (GET_CODE (src) == REG)
8203 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8204 REGNO_REG_CLASS (REGNO (src)), dclass);
8207 old_cost = rtx_cost (src, SET);
8209 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8212 for (l = val->locs; l; l = l->next)
8214 rtx this_rtx = l->loc;
8217 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8219 #ifdef LOAD_EXTEND_OP
8220 if (extend_op != NIL)
8222 HOST_WIDE_INT this_val;
8224 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8225 constants, such as SYMBOL_REF, cannot be extended. */
8226 if (GET_CODE (this_rtx) != CONST_INT)
8229 this_val = INTVAL (this_rtx);
8233 this_val &= GET_MODE_MASK (GET_MODE (src));
8236 /* ??? In theory we're already extended. */
8237 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8242 this_rtx = GEN_INT (this_val);
8245 this_cost = rtx_cost (this_rtx, SET);
8247 else if (GET_CODE (this_rtx) == REG)
8249 #ifdef LOAD_EXTEND_OP
8250 if (extend_op != NIL)
8252 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8253 this_cost = rtx_cost (this_rtx, SET);
8257 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8258 REGNO_REG_CLASS (REGNO (this_rtx)),
8264 /* If equal costs, prefer registers over anything else. That
8265 tends to lead to smaller instructions on some machines. */
8266 if (this_cost < old_cost
8267 || (this_cost == old_cost
8268 && GET_CODE (this_rtx) == REG
8269 && GET_CODE (SET_SRC (set)) != REG))
8271 #ifdef LOAD_EXTEND_OP
8272 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8273 && extend_op != NIL)
8275 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8276 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8277 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8281 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8282 old_cost = this_cost, did_change = 1;
8289 /* Try to replace operands in INSN with equivalent values that are already
8290 in registers. This can be viewed as optional reloading.
8292 For each non-register operand in the insn, see if any hard regs are
8293 known to be equivalent to that operand. Record the alternatives which
8294 can accept these hard registers. Among all alternatives, select the
8295 ones which are better or equal to the one currently matching, where
8296 "better" is in terms of '?' and '!' constraints. Among the remaining
8297 alternatives, select the one which replaces most operands with
8301 reload_cse_simplify_operands (insn, testreg)
8307 /* For each operand, all registers that are equivalent to it. */
8308 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8310 const char *constraints[MAX_RECOG_OPERANDS];
8312 /* Vector recording how bad an alternative is. */
8313 int *alternative_reject;
8314 /* Vector recording how many registers can be introduced by choosing
8315 this alternative. */
8316 int *alternative_nregs;
8317 /* Array of vectors recording, for each operand and each alternative,
8318 which hard register to substitute, or -1 if the operand should be
8320 int *op_alt_regno[MAX_RECOG_OPERANDS];
8321 /* Array of alternatives, sorted in order of decreasing desirability. */
8322 int *alternative_order;
8324 extract_insn (insn);
8326 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8329 /* Figure out which alternative currently matches. */
8330 if (! constrain_operands (1))
8331 fatal_insn_not_found (insn);
8333 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8334 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8335 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8336 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8337 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8339 /* For each operand, find out which regs are equivalent. */
8340 for (i = 0; i < recog_data.n_operands; i++)
8343 struct elt_loc_list *l;
8345 CLEAR_HARD_REG_SET (equiv_regs[i]);
8347 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8348 right, so avoid the problem here. Likewise if we have a constant
8349 and the insn pattern doesn't tell us the mode we need. */
8350 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8351 || (CONSTANT_P (recog_data.operand[i])
8352 && recog_data.operand_mode[i] == VOIDmode))
8355 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8359 for (l = v->locs; l; l = l->next)
8360 if (GET_CODE (l->loc) == REG)
8361 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8364 for (i = 0; i < recog_data.n_operands; i++)
8366 enum machine_mode mode;
8370 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8371 for (j = 0; j < recog_data.n_alternatives; j++)
8372 op_alt_regno[i][j] = -1;
8374 p = constraints[i] = recog_data.constraints[i];
8375 mode = recog_data.operand_mode[i];
8377 /* Add the reject values for each alternative given by the constraints
8378 for this operand. */
8386 alternative_reject[j] += 3;
8388 alternative_reject[j] += 300;
8391 /* We won't change operands which are already registers. We
8392 also don't want to modify output operands. */
8393 regno = true_regnum (recog_data.operand[i]);
8395 || constraints[i][0] == '='
8396 || constraints[i][0] == '+')
8399 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8401 int class = (int) NO_REGS;
8403 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8406 REGNO (testreg) = regno;
8407 PUT_MODE (testreg, mode);
8409 /* We found a register equal to this operand. Now look for all
8410 alternatives that can accept this register and have not been
8411 assigned a register they can use yet. */
8420 case '=': case '+': case '?':
8421 case '#': case '&': case '!':
8423 case '0': case '1': case '2': case '3': case '4':
8424 case '5': case '6': case '7': case '8': case '9':
8425 case 'm': case '<': case '>': case 'V': case 'o':
8426 case 'E': case 'F': case 'G': case 'H':
8427 case 's': case 'i': case 'n':
8428 case 'I': case 'J': case 'K': case 'L':
8429 case 'M': case 'N': case 'O': case 'P':
8431 /* These don't say anything we care about. */
8435 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8440 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)];
8443 case ',': case '\0':
8444 /* See if REGNO fits this alternative, and set it up as the
8445 replacement register if we don't have one for this
8446 alternative yet and the operand being replaced is not
8447 a cheap CONST_INT. */
8448 if (op_alt_regno[i][j] == -1
8449 && reg_fits_class_p (testreg, class, 0, mode)
8450 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8451 || (rtx_cost (recog_data.operand[i], SET)
8452 > rtx_cost (testreg, SET))))
8454 alternative_nregs[j]++;
8455 op_alt_regno[i][j] = regno;
8467 /* Record all alternatives which are better or equal to the currently
8468 matching one in the alternative_order array. */
8469 for (i = j = 0; i < recog_data.n_alternatives; i++)
8470 if (alternative_reject[i] <= alternative_reject[which_alternative])
8471 alternative_order[j++] = i;
8472 recog_data.n_alternatives = j;
8474 /* Sort it. Given a small number of alternatives, a dumb algorithm
8475 won't hurt too much. */
8476 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8479 int best_reject = alternative_reject[alternative_order[i]];
8480 int best_nregs = alternative_nregs[alternative_order[i]];
8483 for (j = i + 1; j < recog_data.n_alternatives; j++)
8485 int this_reject = alternative_reject[alternative_order[j]];
8486 int this_nregs = alternative_nregs[alternative_order[j]];
8488 if (this_reject < best_reject
8489 || (this_reject == best_reject && this_nregs < best_nregs))
8492 best_reject = this_reject;
8493 best_nregs = this_nregs;
8497 tmp = alternative_order[best];
8498 alternative_order[best] = alternative_order[i];
8499 alternative_order[i] = tmp;
8502 /* Substitute the operands as determined by op_alt_regno for the best
8504 j = alternative_order[0];
8506 for (i = 0; i < recog_data.n_operands; i++)
8508 enum machine_mode mode = recog_data.operand_mode[i];
8509 if (op_alt_regno[i][j] == -1)
8512 validate_change (insn, recog_data.operand_loc[i],
8513 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8516 for (i = recog_data.n_dups - 1; i >= 0; i--)
8518 int op = recog_data.dup_num[i];
8519 enum machine_mode mode = recog_data.operand_mode[op];
8521 if (op_alt_regno[op][j] == -1)
8524 validate_change (insn, recog_data.dup_loc[i],
8525 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8528 return apply_change_group ();
8531 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8533 This code might also be useful when reload gave up on reg+reg addressing
8534 because of clashes between the return register and INDEX_REG_CLASS. */
8536 /* The maximum number of uses of a register we can keep track of to
8537 replace them with reg+reg addressing. */
8538 #define RELOAD_COMBINE_MAX_USES 6
8540 /* INSN is the insn where a register has ben used, and USEP points to the
8541 location of the register within the rtl. */
8542 struct reg_use { rtx insn, *usep; };
8544 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8545 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8546 indicates where it becomes live again.
8547 Otherwise, USE_INDEX is the index of the last encountered use of the
8548 register (which is first among these we have seen since we scan backwards),
8549 OFFSET contains the constant offset that is added to the register in
8550 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8551 last, of these uses.
8552 STORE_RUID is always meaningful if we only want to use a value in a
8553 register in a different place: it denotes the next insn in the insn
8554 stream (i.e. the last encountered) that sets or clobbers the register. */
8557 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8562 } reg_state[FIRST_PSEUDO_REGISTER];
8564 /* Reverse linear uid. This is increased in reload_combine while scanning
8565 the instructions from last to first. It is used to set last_label_ruid
8566 and the store_ruid / use_ruid fields in reg_state. */
8567 static int reload_combine_ruid;
8569 #define LABEL_LIVE(LABEL) \
8570 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8576 int first_index_reg = -1;
8577 int last_index_reg = 0;
8581 int last_label_ruid;
8582 int min_labelno, n_labels;
8583 HARD_REG_SET ever_live_at_start, *label_live;
8585 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8586 reload has already used it where appropriate, so there is no use in
8587 trying to generate it now. */
8588 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8591 /* To avoid wasting too much time later searching for an index register,
8592 determine the minimum and maximum index register numbers. */
8593 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8594 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8596 if (first_index_reg == -1)
8597 first_index_reg = r;
8602 /* If no index register is available, we can quit now. */
8603 if (first_index_reg == -1)
8606 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8607 information is a bit fuzzy immediately after reload, but it's
8608 still good enough to determine which registers are live at a jump
8610 min_labelno = get_first_label_num ();
8611 n_labels = max_label_num () - min_labelno;
8612 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8613 CLEAR_HARD_REG_SET (ever_live_at_start);
8615 FOR_EACH_BB_REVERSE (bb)
8618 if (GET_CODE (insn) == CODE_LABEL)
8622 REG_SET_TO_HARD_REG_SET (live,
8623 bb->global_live_at_start);
8624 compute_use_by_pseudos (&live,
8625 bb->global_live_at_start);
8626 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8627 IOR_HARD_REG_SET (ever_live_at_start, live);
8631 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8632 last_label_ruid = reload_combine_ruid = 0;
8633 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8635 reg_state[r].store_ruid = reload_combine_ruid;
8637 reg_state[r].use_index = -1;
8639 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8642 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8646 /* We cannot do our optimization across labels. Invalidating all the use
8647 information we have would be costly, so we just note where the label
8648 is and then later disable any optimization that would cross it. */
8649 if (GET_CODE (insn) == CODE_LABEL)
8650 last_label_ruid = reload_combine_ruid;
8651 else if (GET_CODE (insn) == BARRIER)
8652 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8653 if (! fixed_regs[r])
8654 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8656 if (! INSN_P (insn))
8659 reload_combine_ruid++;
8661 /* Look for (set (REGX) (CONST_INT))
8662 (set (REGX) (PLUS (REGX) (REGY)))
8664 ... (MEM (REGX)) ...
8666 (set (REGZ) (CONST_INT))
8668 ... (MEM (PLUS (REGZ) (REGY)))... .
8670 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8671 and that we know all uses of REGX before it dies. */
8672 set = single_set (insn);
8674 && GET_CODE (SET_DEST (set)) == REG
8675 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8676 GET_MODE (SET_DEST (set)))
8678 && GET_CODE (SET_SRC (set)) == PLUS
8679 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8680 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8681 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8683 rtx reg = SET_DEST (set);
8684 rtx plus = SET_SRC (set);
8685 rtx base = XEXP (plus, 1);
8686 rtx prev = prev_nonnote_insn (insn);
8687 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8688 unsigned int regno = REGNO (reg);
8689 rtx const_reg = NULL_RTX;
8690 rtx reg_sum = NULL_RTX;
8692 /* Now, we need an index register.
8693 We'll set index_reg to this index register, const_reg to the
8694 register that is to be loaded with the constant
8695 (denoted as REGZ in the substitution illustration above),
8696 and reg_sum to the register-register that we want to use to
8697 substitute uses of REG (typically in MEMs) with.
8698 First check REG and BASE for being index registers;
8699 we can use them even if they are not dead. */
8700 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8701 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8709 /* Otherwise, look for a free index register. Since we have
8710 checked above that neiter REG nor BASE are index registers,
8711 if we find anything at all, it will be different from these
8713 for (i = first_index_reg; i <= last_index_reg; i++)
8715 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8717 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8718 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8719 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8721 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8723 const_reg = index_reg;
8724 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8730 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8731 (REGY), i.e. BASE, is not clobbered before the last use we'll
8734 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8735 && rtx_equal_p (SET_DEST (prev_set), reg)
8736 && reg_state[regno].use_index >= 0
8737 && (reg_state[REGNO (base)].store_ruid
8738 <= reg_state[regno].use_ruid)
8743 /* Change destination register and, if necessary, the
8744 constant value in PREV, the constant loading instruction. */
8745 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8746 if (reg_state[regno].offset != const0_rtx)
8747 validate_change (prev,
8748 &SET_SRC (prev_set),
8749 GEN_INT (INTVAL (SET_SRC (prev_set))
8750 + INTVAL (reg_state[regno].offset)),
8753 /* Now for every use of REG that we have recorded, replace REG
8755 for (i = reg_state[regno].use_index;
8756 i < RELOAD_COMBINE_MAX_USES; i++)
8757 validate_change (reg_state[regno].reg_use[i].insn,
8758 reg_state[regno].reg_use[i].usep,
8759 /* Each change must have its own
8761 copy_rtx (reg_sum), 1);
8763 if (apply_change_group ())
8767 /* Delete the reg-reg addition. */
8770 if (reg_state[regno].offset != const0_rtx)
8771 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8773 for (np = ®_NOTES (prev); *np;)
8775 if (REG_NOTE_KIND (*np) == REG_EQUAL
8776 || REG_NOTE_KIND (*np) == REG_EQUIV)
8777 *np = XEXP (*np, 1);
8779 np = &XEXP (*np, 1);
8782 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8783 reg_state[REGNO (const_reg)].store_ruid
8784 = reload_combine_ruid;
8790 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8792 if (GET_CODE (insn) == CALL_INSN)
8796 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8797 if (call_used_regs[r])
8799 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8800 reg_state[r].store_ruid = reload_combine_ruid;
8803 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8804 link = XEXP (link, 1))
8806 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8807 if (GET_CODE (usage_rtx) == REG)
8810 unsigned int start_reg = REGNO (usage_rtx);
8811 unsigned int num_regs =
8812 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8813 unsigned int end_reg = start_reg + num_regs - 1;
8814 for (i = start_reg; i <= end_reg; i++)
8815 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8817 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8818 reg_state[i].store_ruid = reload_combine_ruid;
8821 reg_state[i].use_index = -1;
8826 else if (GET_CODE (insn) == JUMP_INSN
8827 && GET_CODE (PATTERN (insn)) != RETURN)
8829 /* Non-spill registers might be used at the call destination in
8830 some unknown fashion, so we have to mark the unknown use. */
8833 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8834 && JUMP_LABEL (insn))
8835 live = &LABEL_LIVE (JUMP_LABEL (insn));
8837 live = &ever_live_at_start;
8839 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8840 if (TEST_HARD_REG_BIT (*live, i))
8841 reg_state[i].use_index = -1;
8844 reload_combine_note_use (&PATTERN (insn), insn);
8845 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8847 if (REG_NOTE_KIND (note) == REG_INC
8848 && GET_CODE (XEXP (note, 0)) == REG)
8850 int regno = REGNO (XEXP (note, 0));
8852 reg_state[regno].store_ruid = reload_combine_ruid;
8853 reg_state[regno].use_index = -1;
8861 /* Check if DST is a register or a subreg of a register; if it is,
8862 update reg_state[regno].store_ruid and reg_state[regno].use_index
8863 accordingly. Called via note_stores from reload_combine. */
8866 reload_combine_note_store (dst, set, data)
8868 void *data ATTRIBUTE_UNUSED;
8872 enum machine_mode mode = GET_MODE (dst);
8874 if (GET_CODE (dst) == SUBREG)
8876 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8877 GET_MODE (SUBREG_REG (dst)),
8880 dst = SUBREG_REG (dst);
8882 if (GET_CODE (dst) != REG)
8884 regno += REGNO (dst);
8886 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8887 careful with registers / register parts that are not full words.
8889 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8890 if (GET_CODE (set) != SET
8891 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8892 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8893 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8895 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8897 reg_state[i].use_index = -1;
8898 reg_state[i].store_ruid = reload_combine_ruid;
8903 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8905 reg_state[i].store_ruid = reload_combine_ruid;
8906 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8911 /* XP points to a piece of rtl that has to be checked for any uses of
8913 *XP is the pattern of INSN, or a part of it.
8914 Called from reload_combine, and recursively by itself. */
8916 reload_combine_note_use (xp, insn)
8920 enum rtx_code code = x->code;
8923 rtx offset = const0_rtx; /* For the REG case below. */
8928 if (GET_CODE (SET_DEST (x)) == REG)
8930 reload_combine_note_use (&SET_SRC (x), insn);
8936 /* If this is the USE of a return value, we can't change it. */
8937 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8939 /* Mark the return register as used in an unknown fashion. */
8940 rtx reg = XEXP (x, 0);
8941 int regno = REGNO (reg);
8942 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8944 while (--nregs >= 0)
8945 reg_state[regno + nregs].use_index = -1;
8951 if (GET_CODE (SET_DEST (x)) == REG)
8953 /* No spurious CLOBBERs of pseudo registers may remain. */
8954 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8961 /* We are interested in (plus (reg) (const_int)) . */
8962 if (GET_CODE (XEXP (x, 0)) != REG
8963 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8965 offset = XEXP (x, 1);
8970 int regno = REGNO (x);
8974 /* No spurious USEs of pseudo registers may remain. */
8975 if (regno >= FIRST_PSEUDO_REGISTER)
8978 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8980 /* We can't substitute into multi-hard-reg uses. */
8983 while (--nregs >= 0)
8984 reg_state[regno + nregs].use_index = -1;
8988 /* If this register is already used in some unknown fashion, we
8990 If we decrement the index from zero to -1, we can't store more
8991 uses, so this register becomes used in an unknown fashion. */
8992 use_index = --reg_state[regno].use_index;
8996 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8998 /* We have found another use for a register that is already
8999 used later. Check if the offsets match; if not, mark the
9000 register as used in an unknown fashion. */
9001 if (! rtx_equal_p (offset, reg_state[regno].offset))
9003 reg_state[regno].use_index = -1;
9009 /* This is the first use of this register we have seen since we
9010 marked it as dead. */
9011 reg_state[regno].offset = offset;
9012 reg_state[regno].use_ruid = reload_combine_ruid;
9014 reg_state[regno].reg_use[use_index].insn = insn;
9015 reg_state[regno].reg_use[use_index].usep = xp;
9023 /* Recursively process the components of X. */
9024 fmt = GET_RTX_FORMAT (code);
9025 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9028 reload_combine_note_use (&XEXP (x, i), insn);
9029 else if (fmt[i] == 'E')
9031 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9032 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9037 /* See if we can reduce the cost of a constant by replacing a move
9038 with an add. We track situations in which a register is set to a
9039 constant or to a register plus a constant. */
9040 /* We cannot do our optimization across labels. Invalidating all the
9041 information about register contents we have would be costly, so we
9042 use move2add_last_label_luid to note where the label is and then
9043 later disable any optimization that would cross it.
9044 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9045 reg_set_luid[n] is greater than last_label_luid[n] . */
9046 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9048 /* If reg_base_reg[n] is negative, register n has been set to
9049 reg_offset[n] in mode reg_mode[n] .
9050 If reg_base_reg[n] is non-negative, register n has been set to the
9051 sum of reg_offset[n] and the value of register reg_base_reg[n]
9052 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9053 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9054 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9055 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9057 /* move2add_luid is linearly increased while scanning the instructions
9058 from first to last. It is used to set reg_set_luid in
9059 reload_cse_move2add and move2add_note_store. */
9060 static int move2add_luid;
9062 /* move2add_last_label_luid is set whenever a label is found. Labels
9063 invalidate all previously collected reg_offset data. */
9064 static int move2add_last_label_luid;
9066 /* Generate a CONST_INT and force it in the range of MODE. */
9068 static HOST_WIDE_INT
9069 sext_for_mode (mode, value)
9070 enum machine_mode mode;
9071 HOST_WIDE_INT value;
9073 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9074 int width = GET_MODE_BITSIZE (mode);
9076 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9078 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9079 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9080 cval |= (HOST_WIDE_INT) -1 << width;
9085 /* ??? We don't know how zero / sign extension is handled, hence we
9086 can't go from a narrower to a wider mode. */
9087 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9088 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9089 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9090 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9091 GET_MODE_BITSIZE (INMODE))))
9094 reload_cse_move2add (first)
9100 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9101 reg_set_luid[i] = 0;
9103 move2add_last_label_luid = 0;
9105 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9109 if (GET_CODE (insn) == CODE_LABEL)
9111 move2add_last_label_luid = move2add_luid;
9112 /* We're going to increment move2add_luid twice after a
9113 label, so that we can use move2add_last_label_luid + 1 as
9114 the luid for constants. */
9118 if (! INSN_P (insn))
9120 pat = PATTERN (insn);
9121 /* For simplicity, we only perform this optimization on
9122 straightforward SETs. */
9123 if (GET_CODE (pat) == SET
9124 && GET_CODE (SET_DEST (pat)) == REG)
9126 rtx reg = SET_DEST (pat);
9127 int regno = REGNO (reg);
9128 rtx src = SET_SRC (pat);
9130 /* Check if we have valid information on the contents of this
9131 register in the mode of REG. */
9132 if (reg_set_luid[regno] > move2add_last_label_luid
9133 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9135 /* Try to transform (set (REGX) (CONST_INT A))
9137 (set (REGX) (CONST_INT B))
9139 (set (REGX) (CONST_INT A))
9141 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9143 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9146 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9148 - reg_offset[regno]));
9149 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9150 use (set (reg) (reg)) instead.
9151 We don't delete this insn, nor do we convert it into a
9152 note, to avoid losing register notes or the return
9153 value flag. jump2 already knows how to get rid of
9155 if (new_src == const0_rtx)
9156 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9157 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9158 && have_add2_insn (reg, new_src))
9159 success = validate_change (insn, &PATTERN (insn),
9160 gen_add2_insn (reg, new_src), 0);
9161 reg_set_luid[regno] = move2add_luid;
9162 reg_mode[regno] = GET_MODE (reg);
9163 reg_offset[regno] = INTVAL (src);
9167 /* Try to transform (set (REGX) (REGY))
9168 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9171 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9174 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9176 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9177 else if (GET_CODE (src) == REG
9178 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9179 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9180 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9181 reg_mode[REGNO (src)]))
9183 rtx next = next_nonnote_insn (insn);
9186 set = single_set (next);
9188 && SET_DEST (set) == reg
9189 && GET_CODE (SET_SRC (set)) == PLUS
9190 && XEXP (SET_SRC (set), 0) == reg
9191 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9193 rtx src3 = XEXP (SET_SRC (set), 1);
9194 HOST_WIDE_INT added_offset = INTVAL (src3);
9195 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9196 HOST_WIDE_INT regno_offset = reg_offset[regno];
9197 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9203 if (new_src == const0_rtx)
9204 /* See above why we create (set (reg) (reg)) here. */
9206 = validate_change (next, &SET_SRC (set), reg, 0);
9207 else if ((rtx_cost (new_src, PLUS)
9208 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9209 && have_add2_insn (reg, new_src))
9211 = validate_change (next, &PATTERN (next),
9212 gen_add2_insn (reg, new_src), 0);
9216 reg_mode[regno] = GET_MODE (reg);
9217 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9226 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9228 if (REG_NOTE_KIND (note) == REG_INC
9229 && GET_CODE (XEXP (note, 0)) == REG)
9231 /* Reset the information about this register. */
9232 int regno = REGNO (XEXP (note, 0));
9233 if (regno < FIRST_PSEUDO_REGISTER)
9234 reg_set_luid[regno] = 0;
9237 note_stores (PATTERN (insn), move2add_note_store, NULL);
9238 /* If this is a CALL_INSN, all call used registers are stored with
9240 if (GET_CODE (insn) == CALL_INSN)
9242 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9244 if (call_used_regs[i])
9245 /* Reset the information about this register. */
9246 reg_set_luid[i] = 0;
9252 /* SET is a SET or CLOBBER that sets DST.
9253 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9254 Called from reload_cse_move2add via note_stores. */
9257 move2add_note_store (dst, set, data)
9259 void *data ATTRIBUTE_UNUSED;
9261 unsigned int regno = 0;
9263 enum machine_mode mode = GET_MODE (dst);
9265 if (GET_CODE (dst) == SUBREG)
9267 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9268 GET_MODE (SUBREG_REG (dst)),
9271 dst = SUBREG_REG (dst);
9274 /* Some targets do argument pushes without adding REG_INC notes. */
9276 if (GET_CODE (dst) == MEM)
9278 dst = XEXP (dst, 0);
9279 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9280 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9281 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9284 if (GET_CODE (dst) != REG)
9287 regno += REGNO (dst);
9289 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9290 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9291 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9292 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9294 rtx src = SET_SRC (set);
9296 HOST_WIDE_INT offset;
9298 /* This may be different from mode, if SET_DEST (set) is a
9300 enum machine_mode dst_mode = GET_MODE (dst);
9302 switch (GET_CODE (src))
9305 if (GET_CODE (XEXP (src, 0)) == REG)
9307 base_reg = XEXP (src, 0);
9309 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9310 offset = INTVAL (XEXP (src, 1));
9311 else if (GET_CODE (XEXP (src, 1)) == REG
9312 && (reg_set_luid[REGNO (XEXP (src, 1))]
9313 > move2add_last_label_luid)
9314 && (MODES_OK_FOR_MOVE2ADD
9315 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9317 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9318 offset = reg_offset[REGNO (XEXP (src, 1))];
9319 /* Maybe the first register is known to be a
9321 else if (reg_set_luid[REGNO (base_reg)]
9322 > move2add_last_label_luid
9323 && (MODES_OK_FOR_MOVE2ADD
9324 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9325 && reg_base_reg[REGNO (base_reg)] < 0)
9327 offset = reg_offset[REGNO (base_reg)];
9328 base_reg = XEXP (src, 1);
9347 /* Start tracking the register as a constant. */
9348 reg_base_reg[regno] = -1;
9349 reg_offset[regno] = INTVAL (SET_SRC (set));
9350 /* We assign the same luid to all registers set to constants. */
9351 reg_set_luid[regno] = move2add_last_label_luid + 1;
9352 reg_mode[regno] = mode;
9357 /* Invalidate the contents of the register. */
9358 reg_set_luid[regno] = 0;
9362 base_regno = REGNO (base_reg);
9363 /* If information about the base register is not valid, set it
9364 up as a new base register, pretending its value is known
9365 starting from the current insn. */
9366 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9368 reg_base_reg[base_regno] = base_regno;
9369 reg_offset[base_regno] = 0;
9370 reg_set_luid[base_regno] = move2add_luid;
9371 reg_mode[base_regno] = mode;
9373 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9374 reg_mode[base_regno]))
9377 reg_mode[regno] = mode;
9379 /* Copy base information from our base register. */
9380 reg_set_luid[regno] = reg_set_luid[base_regno];
9381 reg_base_reg[regno] = reg_base_reg[base_regno];
9383 /* Compute the sum of the offsets or constants. */
9384 reg_offset[regno] = sext_for_mode (dst_mode,
9386 + reg_offset[base_regno]);
9390 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9392 for (i = regno; i < endregno; i++)
9393 /* Reset the information about this register. */
9394 reg_set_luid[i] = 0;
9400 add_auto_inc_notes (insn, x)
9404 enum rtx_code code = GET_CODE (x);
9408 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9411 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9415 /* Scan all the operand sub-expressions. */
9416 fmt = GET_RTX_FORMAT (code);
9417 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9420 add_auto_inc_notes (insn, XEXP (x, i));
9421 else if (fmt[i] == 'E')
9422 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9423 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9428 /* Copy EH notes from an insn to its reloads. */
9430 copy_eh_notes (insn, x)
9434 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9437 for (; x != 0; x = NEXT_INSN (x))
9439 if (may_trap_p (PATTERN (x)))
9441 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9447 /* This is used by reload pass, that does emit some instructions after
9448 abnormal calls moving basic block end, but in fact it wants to emit
9449 them on the edge. Looks for abnormal call edges, find backward the
9450 proper call and fix the damage.
9452 Similar handle instructions throwing exceptions internally. */
9454 fixup_abnormal_edges ()
9456 bool inserted = false;
9463 /* Look for cases we are interested in - calls or instructions causing
9465 for (e = bb->succ; e; e = e->succ_next)
9467 if (e->flags & EDGE_ABNORMAL_CALL)
9469 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9470 == (EDGE_ABNORMAL | EDGE_EH))
9473 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9475 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9477 for (e = bb->succ; e; e = e->succ_next)
9478 if (e->flags & EDGE_FALLTHRU)
9480 /* Get past the new insns generated. Allow notes, as the insns may
9481 be already deleted. */
9482 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9483 && !can_throw_internal (insn)
9484 && insn != bb->head)
9485 insn = PREV_INSN (insn);
9486 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9490 insn = NEXT_INSN (insn);
9491 while (insn && insn != stop)
9493 next = NEXT_INSN (insn);
9498 /* Sometimes there's still the return value USE.
9499 If it's placed after a trapping call (i.e. that
9500 call is the last insn anyway), we have no fallthru
9501 edge. Simply delete this use and don't try to insert
9502 on the non-existent edge. */
9503 if (GET_CODE (PATTERN (insn)) != USE)
9505 /* We're not deleting it, we're moving it. */
9506 INSN_DELETED_P (insn) = 0;
9507 PREV_INSN (insn) = NULL_RTX;
9508 NEXT_INSN (insn) = NULL_RTX;
9510 insert_insn_on_edge (insn, e);
9518 commit_edge_insertions ();
OSDN Git Service
