1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
80 #ifndef REGISTER_MOVE_COST
81 #define REGISTER_MOVE_COST(m, x, y) 2
85 #define LOCAL_REGNO(REGNO) 0
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx *reg_last_reload_reg;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static char *reg_has_output_reload;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload;
100 /* Element N is the constant value to which pseudo reg N is equivalent,
101 or zero if pseudo reg N is not equivalent to a constant.
102 find_reloads looks at this in order to replace pseudo reg N
103 with the constant it stands for. */
104 rtx *reg_equiv_constant;
106 /* Element N is a memory location to which pseudo reg N is equivalent,
107 prior to any register elimination (such as frame pointer to stack
108 pointer). Depending on whether or not it is a valid address, this value
109 is transferred to either reg_equiv_address or reg_equiv_mem. */
110 rtx *reg_equiv_memory_loc;
112 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
113 This is used when the address is not valid as a memory address
114 (because its displacement is too big for the machine.) */
115 rtx *reg_equiv_address;
117 /* Element N is the memory slot to which pseudo reg N is equivalent,
118 or zero if pseudo reg N is not equivalent to a memory slot. */
121 /* Widest width in which each pseudo reg is referred to (via subreg). */
122 static unsigned int *reg_max_ref_width;
124 /* Element N is the list of insns that initialized reg N from its equivalent
125 constant or memory slot. */
126 static rtx *reg_equiv_init;
128 /* Vector to remember old contents of reg_renumber before spilling. */
129 static short *reg_old_renumber;
131 /* During reload_as_needed, element N contains the last pseudo regno reloaded
132 into hard register N. If that pseudo reg occupied more than one register,
133 reg_reloaded_contents points to that pseudo for each spill register in
134 use; all of these must remain set for an inheritance to occur. */
135 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
137 /* During reload_as_needed, element N contains the insn for which
138 hard register N was last used. Its contents are significant only
139 when reg_reloaded_valid is set for this register. */
140 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
142 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
143 static HARD_REG_SET reg_reloaded_valid;
144 /* Indicate if the register was dead at the end of the reload.
145 This is only valid if reg_reloaded_contents is set and valid. */
146 static HARD_REG_SET reg_reloaded_dead;
148 /* Number of spill-regs so far; number of valid elements of spill_regs. */
151 /* In parallel with spill_regs, contains REG rtx's for those regs.
152 Holds the last rtx used for any given reg, or 0 if it has never
153 been used for spilling yet. This rtx is reused, provided it has
155 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
157 /* In parallel with spill_regs, contains nonzero for a spill reg
158 that was stored after the last time it was used.
159 The precise value is the insn generated to do the store. */
160 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
162 /* This is the register that was stored with spill_reg_store. This is a
163 copy of reload_out / reload_out_reg when the value was stored; if
164 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
165 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
167 /* This table is the inverse mapping of spill_regs:
168 indexed by hard reg number,
169 it contains the position of that reg in spill_regs,
170 or -1 for something that is not in spill_regs.
172 ?!? This is no longer accurate. */
173 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
175 /* This reg set indicates registers that can't be used as spill registers for
176 the currently processed insn. These are the hard registers which are live
177 during the insn, but not allocated to pseudos, as well as fixed
179 static HARD_REG_SET bad_spill_regs;
181 /* These are the hard registers that can't be used as spill register for any
182 insn. This includes registers used for user variables and registers that
183 we can't eliminate. A register that appears in this set also can't be used
184 to retry register allocation. */
185 static HARD_REG_SET bad_spill_regs_global;
187 /* Describes order of use of registers for reloading
188 of spilled pseudo-registers. `n_spills' is the number of
189 elements that are actually valid; new ones are added at the end.
191 Both spill_regs and spill_reg_order are used on two occasions:
192 once during find_reload_regs, where they keep track of the spill registers
193 for a single insn, but also during reload_as_needed where they show all
194 the registers ever used by reload. For the latter case, the information
195 is calculated during finish_spills. */
196 static short spill_regs[FIRST_PSEUDO_REGISTER];
198 /* This vector of reg sets indicates, for each pseudo, which hard registers
199 may not be used for retrying global allocation because the register was
200 formerly spilled from one of them. If we allowed reallocating a pseudo to
201 a register that it was already allocated to, reload might not
203 static HARD_REG_SET *pseudo_previous_regs;
205 /* This vector of reg sets indicates, for each pseudo, which hard
206 registers may not be used for retrying global allocation because they
207 are used as spill registers during one of the insns in which the
209 static HARD_REG_SET *pseudo_forbidden_regs;
211 /* All hard regs that have been used as spill registers for any insn are
212 marked in this set. */
213 static HARD_REG_SET used_spill_regs;
215 /* Index of last register assigned as a spill register. We allocate in
216 a round-robin fashion. */
217 static int last_spill_reg;
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
238 /* Width allocated so far for that stack slot. */
239 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
241 /* Record which pseudos needed to be spilled. */
242 static regset_head spilled_pseudos;
244 /* Used for communication between order_regs_for_reload and count_pseudo.
245 Used to avoid counting one pseudo twice. */
246 static regset_head pseudos_counted;
248 /* First uid used by insns created by reload in this function.
249 Used in find_equiv_reg. */
250 int reload_first_uid;
252 /* Flag set by local-alloc or global-alloc if anything is live in
253 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* Set to 1 while reload_as_needed is operating.
257 Required by some machines to handle any generated moves differently. */
258 int reload_in_progress = 0;
260 /* These arrays record the insn_code of insns that may be needed to
261 perform input and output reloads of special objects. They provide a
262 place to pass a scratch register. */
263 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
264 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
266 /* This obstack is used for allocation of rtl during register elimination.
267 The allocated storage can be freed once find_reloads has processed the
269 struct obstack reload_obstack;
271 /* Points to the beginning of the reload_obstack. All insn_chain structures
272 are allocated first. */
273 char *reload_startobj;
275 /* The point after all insn_chain structures. Used to quickly deallocate
276 memory allocated in copy_reloads during calculate_needs_all_insns. */
277 char *reload_firstobj;
279 /* This points before all local rtl generated by register elimination.
280 Used to quickly free all memory after processing one insn. */
281 static char *reload_insn_firstobj;
283 /* List of insn_chain instructions, one for every insn that reload needs to
285 struct insn_chain *reload_insn_chain;
288 extern tree current_function_decl;
290 extern union tree_node *current_function_decl;
293 /* List of all insns needing reloads. */
294 static struct insn_chain *insns_need_reload;
296 /* This structure is used to record information about register eliminations.
297 Each array entry describes one possible way of eliminating a register
298 in favor of another. If there is more than one way of eliminating a
299 particular register, the most preferred should be specified first. */
303 int from; /* Register number to be eliminated. */
304 int to; /* Register number used as replacement. */
305 int initial_offset; /* Initial difference between values. */
306 int can_eliminate; /* Non-zero if this elimination can be done. */
307 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
308 insns made by reload. */
309 int offset; /* Current offset between the two regs. */
310 int previous_offset; /* Offset at end of previous insn. */
311 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
312 rtx from_rtx; /* REG rtx for the register to be eliminated.
313 We cannot simply compare the number since
314 we might then spuriously replace a hard
315 register corresponding to a pseudo
316 assigned to the reg to be eliminated. */
317 rtx to_rtx; /* REG rtx for the replacement. */
320 static struct elim_table *reg_eliminate = 0;
322 /* This is an intermediate structure to initialize the table. It has
323 exactly the members provided by ELIMINABLE_REGS. */
324 static const struct elim_table_1
328 } reg_eliminate_1[] =
330 /* If a set of eliminable registers was specified, define the table from it.
331 Otherwise, default to the normal case of the frame pointer being
332 replaced by the stack pointer. */
334 #ifdef ELIMINABLE_REGS
337 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
340 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
342 /* Record the number of pending eliminations that have an offset not equal
343 to their initial offset. If non-zero, we use a new copy of each
344 replacement result in any insns encountered. */
345 int num_not_at_initial_offset;
347 /* Count the number of registers that we may be able to eliminate. */
348 static int num_eliminable;
349 /* And the number of registers that are equivalent to a constant that
350 can be eliminated to frame_pointer / arg_pointer + constant. */
351 static int num_eliminable_invariants;
353 /* For each label, we record the offset of each elimination. If we reach
354 a label by more than one path and an offset differs, we cannot do the
355 elimination. This information is indexed by the number of the label.
356 The first table is an array of flags that records whether we have yet
357 encountered a label and the second table is an array of arrays, one
358 entry in the latter array for each elimination. */
360 static char *offsets_known_at;
361 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
363 /* Number of labels in the current function. */
365 static int num_labels;
367 static void replace_pseudos_in_call_usage PARAMS ((rtx *,
370 static void maybe_fix_stack_asms PARAMS ((void));
371 static void copy_reloads PARAMS ((struct insn_chain *));
372 static void calculate_needs_all_insns PARAMS ((int));
373 static int find_reg PARAMS ((struct insn_chain *, int));
374 static void find_reload_regs PARAMS ((struct insn_chain *));
375 static void select_reload_regs PARAMS ((void));
376 static void delete_caller_save_insns PARAMS ((void));
378 static void spill_failure PARAMS ((rtx, enum reg_class));
379 static void count_spilled_pseudo PARAMS ((int, int, int));
380 static void delete_dead_insn PARAMS ((rtx));
381 static void alter_reg PARAMS ((int, int));
382 static void set_label_offsets PARAMS ((rtx, rtx, int));
383 static void check_eliminable_occurrences PARAMS ((rtx));
384 static void elimination_effects PARAMS ((rtx, enum machine_mode));
385 static int eliminate_regs_in_insn PARAMS ((rtx, int));
386 static void update_eliminable_offsets PARAMS ((void));
387 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
388 static void set_initial_elim_offsets PARAMS ((void));
389 static void verify_initial_elim_offsets PARAMS ((void));
390 static void set_initial_label_offsets PARAMS ((void));
391 static void set_offsets_for_label PARAMS ((rtx));
392 static void init_elim_table PARAMS ((void));
393 static void update_eliminables PARAMS ((HARD_REG_SET *));
394 static void spill_hard_reg PARAMS ((unsigned int, int));
395 static int finish_spills PARAMS ((int));
396 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
397 static void scan_paradoxical_subregs PARAMS ((rtx));
398 static void count_pseudo PARAMS ((int));
399 static void order_regs_for_reload PARAMS ((struct insn_chain *));
400 static void reload_as_needed PARAMS ((int));
401 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
402 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
403 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
406 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
409 static int reload_reg_free_p PARAMS ((unsigned int, int,
411 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
413 rtx, rtx, int, int));
414 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
415 enum reload_type, rtx, rtx,
417 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
419 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
421 static int conflicts_with_override PARAMS ((rtx));
422 static void failed_reload PARAMS ((rtx, int));
423 static int set_reload_reg PARAMS ((int, int));
424 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
425 static void choose_reload_regs PARAMS ((struct insn_chain *));
426 static void merge_assigned_reloads PARAMS ((rtx));
427 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
428 struct reload *, rtx, int));
429 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
430 struct reload *, int));
431 static void do_input_reload PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void do_output_reload PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void emit_reload_insns PARAMS ((struct insn_chain *));
436 static void delete_output_reload PARAMS ((rtx, int, int));
437 static void delete_address_reloads PARAMS ((rtx, rtx));
438 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
439 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
440 static void reload_cse_regs_1 PARAMS ((rtx));
441 static int reload_cse_noop_set_p PARAMS ((rtx));
442 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
443 static int reload_cse_simplify_operands PARAMS ((rtx, rtx));
444 static void reload_combine PARAMS ((void));
445 static void reload_combine_note_use PARAMS ((rtx *, rtx));
446 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
447 static void reload_cse_move2add PARAMS ((rtx));
448 static void move2add_note_store PARAMS ((rtx, rtx, void *));
450 static void add_auto_inc_notes PARAMS ((rtx, rtx));
452 static void copy_eh_notes PARAMS ((rtx, rtx));
453 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
455 static void failed_reload PARAMS ((rtx, int));
456 static int set_reload_reg PARAMS ((int, int));
457 static void reload_cse_simplify PARAMS ((rtx, rtx));
458 void fixup_abnormal_edges PARAMS ((void));
459 extern void dump_needs PARAMS ((struct insn_chain *));
461 /* Initialize the reload pass once per compilation. */
468 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
469 Set spill_indirect_levels to the number of levels such addressing is
470 permitted, zero if it is not permitted at all. */
473 = gen_rtx_MEM (Pmode,
476 LAST_VIRTUAL_REGISTER + 1),
478 spill_indirect_levels = 0;
480 while (memory_address_p (QImode, tem))
482 spill_indirect_levels++;
483 tem = gen_rtx_MEM (Pmode, tem);
486 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
488 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
489 indirect_symref_ok = memory_address_p (QImode, tem);
491 /* See if reg+reg is a valid (and offsettable) address. */
493 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
495 tem = gen_rtx_PLUS (Pmode,
496 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
497 gen_rtx_REG (Pmode, i));
499 /* This way, we make sure that reg+reg is an offsettable address. */
500 tem = plus_constant (tem, 4);
502 if (memory_address_p (QImode, tem))
504 double_reg_address_ok = 1;
509 /* Initialize obstack for our rtl allocation. */
510 gcc_obstack_init (&reload_obstack);
511 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
513 INIT_REG_SET (&spilled_pseudos);
514 INIT_REG_SET (&pseudos_counted);
517 /* List of insn chains that are currently unused. */
518 static struct insn_chain *unused_insn_chains = 0;
520 /* Allocate an empty insn_chain structure. */
524 struct insn_chain *c;
526 if (unused_insn_chains == 0)
528 c = (struct insn_chain *)
529 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
530 INIT_REG_SET (&c->live_throughout);
531 INIT_REG_SET (&c->dead_or_set);
535 c = unused_insn_chains;
536 unused_insn_chains = c->next;
538 c->is_caller_save_insn = 0;
539 c->need_operand_change = 0;
545 /* Small utility function to set all regs in hard reg set TO which are
546 allocated to pseudos in regset FROM. */
549 compute_use_by_pseudos (to, from)
555 EXECUTE_IF_SET_IN_REG_SET
556 (from, FIRST_PSEUDO_REGISTER, regno,
558 int r = reg_renumber[regno];
563 /* reload_combine uses the information from
564 BASIC_BLOCK->global_live_at_start, which might still
565 contain registers that have not actually been allocated
566 since they have an equivalence. */
567 if (! reload_completed)
572 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
574 SET_HARD_REG_BIT (*to, r + nregs);
579 /* Replace all pseudos found in LOC with their corresponding
583 replace_pseudos_in_call_usage (loc, mem_mode, usage)
585 enum machine_mode mem_mode;
599 unsigned int regno = REGNO (x);
601 if (regno < FIRST_PSEUDO_REGISTER)
604 x = eliminate_regs (x, mem_mode, usage);
608 replace_pseudos_in_call_usage (loc, mem_mode, usage);
612 if (reg_equiv_constant[regno])
613 *loc = reg_equiv_constant[regno];
614 else if (reg_equiv_mem[regno])
615 *loc = reg_equiv_mem[regno];
616 else if (reg_equiv_address[regno])
617 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
618 else if (GET_CODE (regno_reg_rtx[regno]) != REG
619 || REGNO (regno_reg_rtx[regno]) != regno)
620 *loc = regno_reg_rtx[regno];
626 else if (code == MEM)
628 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
632 /* Process each of our operands recursively. */
633 fmt = GET_RTX_FORMAT (code);
634 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
636 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
637 else if (*fmt == 'E')
638 for (j = 0; j < XVECLEN (x, i); j++)
639 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
643 /* Global variables used by reload and its subroutines. */
645 /* Set during calculate_needs if an insn needs register elimination. */
646 static int something_needs_elimination;
647 /* Set during calculate_needs if an insn needs an operand changed. */
648 int something_needs_operands_changed;
650 /* Nonzero means we couldn't get enough spill regs. */
653 /* Main entry point for the reload pass.
655 FIRST is the first insn of the function being compiled.
657 GLOBAL nonzero means we were called from global_alloc
658 and should attempt to reallocate any pseudoregs that we
659 displace from hard regs we will use for reloads.
660 If GLOBAL is zero, we do not have enough information to do that,
661 so any pseudo reg that is spilled must go to the stack.
663 Return value is nonzero if reload failed
664 and we must not do any more for this function. */
667 reload (first, global)
673 struct elim_table *ep;
676 /* The two pointers used to track the true location of the memory used
677 for label offsets. */
678 char *real_known_ptr = NULL;
679 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
681 /* Make sure even insns with volatile mem refs are recognizable. */
686 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
688 /* Make sure that the last insn in the chain
689 is not something that needs reloading. */
690 emit_note (NULL, NOTE_INSN_DELETED);
692 /* Enable find_equiv_reg to distinguish insns made by reload. */
693 reload_first_uid = get_max_uid ();
695 #ifdef SECONDARY_MEMORY_NEEDED
696 /* Initialize the secondary memory table. */
697 clear_secondary_mem ();
700 /* We don't have a stack slot for any spill reg yet. */
701 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
702 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
704 /* Initialize the save area information for caller-save, in case some
708 /* Compute which hard registers are now in use
709 as homes for pseudo registers.
710 This is done here rather than (eg) in global_alloc
711 because this point is reached even if not optimizing. */
712 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
715 /* A function that receives a nonlocal goto must save all call-saved
717 if (current_function_has_nonlocal_label)
718 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
719 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
720 regs_ever_live[i] = 1;
722 /* Find all the pseudo registers that didn't get hard regs
723 but do have known equivalent constants or memory slots.
724 These include parameters (known equivalent to parameter slots)
725 and cse'd or loop-moved constant memory addresses.
727 Record constant equivalents in reg_equiv_constant
728 so they will be substituted by find_reloads.
729 Record memory equivalents in reg_mem_equiv so they can
730 be substituted eventually by altering the REG-rtx's. */
732 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
733 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
734 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
735 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
737 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
738 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
739 pseudo_forbidden_regs
740 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
742 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
744 CLEAR_HARD_REG_SET (bad_spill_regs_global);
746 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
747 Also find all paradoxical subregs and find largest such for each pseudo.
748 On machines with small register classes, record hard registers that
749 are used for user variables. These can never be used for spills.
750 Also look for a "constant" REG_SETJMP. This means that all
751 caller-saved registers must be marked live. */
753 num_eliminable_invariants = 0;
754 for (insn = first; insn; insn = NEXT_INSN (insn))
756 rtx set = single_set (insn);
758 /* We may introduce USEs that we want to remove at the end, so
759 we'll mark them with QImode. Make sure there are no
760 previously-marked insns left by say regmove. */
761 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
762 && GET_MODE (insn) != VOIDmode)
763 PUT_MODE (insn, VOIDmode);
765 if (GET_CODE (insn) == CALL_INSN
766 && find_reg_note (insn, REG_SETJMP, NULL))
767 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
768 if (! call_used_regs[i])
769 regs_ever_live[i] = 1;
771 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
773 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
775 #ifdef LEGITIMATE_PIC_OPERAND_P
776 && (! function_invariant_p (XEXP (note, 0))
778 /* A function invariant is often CONSTANT_P but may
779 include a register. We promise to only pass
780 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
781 || (CONSTANT_P (XEXP (note, 0))
782 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
786 rtx x = XEXP (note, 0);
787 i = REGNO (SET_DEST (set));
788 if (i > LAST_VIRTUAL_REGISTER)
790 /* It can happen that a REG_EQUIV note contains a MEM
791 that is not a legitimate memory operand. As later
792 stages of reload assume that all addresses found
793 in the reg_equiv_* arrays were originally legitimate,
794 we ignore such REG_EQUIV notes. */
795 if (memory_operand (x, VOIDmode))
797 /* Always unshare the equivalence, so we can
798 substitute into this insn without touching the
800 reg_equiv_memory_loc[i] = copy_rtx (x);
802 else if (function_invariant_p (x))
804 if (GET_CODE (x) == PLUS)
806 /* This is PLUS of frame pointer and a constant,
807 and might be shared. Unshare it. */
808 reg_equiv_constant[i] = copy_rtx (x);
809 num_eliminable_invariants++;
811 else if (x == frame_pointer_rtx
812 || x == arg_pointer_rtx)
814 reg_equiv_constant[i] = x;
815 num_eliminable_invariants++;
817 else if (LEGITIMATE_CONSTANT_P (x))
818 reg_equiv_constant[i] = x;
820 reg_equiv_memory_loc[i]
821 = force_const_mem (GET_MODE (SET_DEST (set)), x);
826 /* If this register is being made equivalent to a MEM
827 and the MEM is not SET_SRC, the equivalencing insn
828 is one with the MEM as a SET_DEST and it occurs later.
829 So don't mark this insn now. */
830 if (GET_CODE (x) != MEM
831 || rtx_equal_p (SET_SRC (set), x))
833 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
838 /* If this insn is setting a MEM from a register equivalent to it,
839 this is the equivalencing insn. */
840 else if (set && GET_CODE (SET_DEST (set)) == MEM
841 && GET_CODE (SET_SRC (set)) == REG
842 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
843 && rtx_equal_p (SET_DEST (set),
844 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
845 reg_equiv_init[REGNO (SET_SRC (set))]
846 = gen_rtx_INSN_LIST (VOIDmode, insn,
847 reg_equiv_init[REGNO (SET_SRC (set))]);
850 scan_paradoxical_subregs (PATTERN (insn));
855 num_labels = max_label_num () - get_first_label_num ();
857 /* Allocate the tables used to store offset information at labels. */
858 /* We used to use alloca here, but the size of what it would try to
859 allocate would occasionally cause it to exceed the stack limit and
860 cause a core dump. */
861 real_known_ptr = xmalloc (num_labels);
863 = (int (*)[NUM_ELIMINABLE_REGS])
864 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
866 offsets_known_at = real_known_ptr - get_first_label_num ();
868 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
870 /* Alter each pseudo-reg rtx to contain its hard reg number.
871 Assign stack slots to the pseudos that lack hard regs or equivalents.
872 Do not touch virtual registers. */
874 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
877 /* If we have some registers we think can be eliminated, scan all insns to
878 see if there is an insn that sets one of these registers to something
879 other than itself plus a constant. If so, the register cannot be
880 eliminated. Doing this scan here eliminates an extra pass through the
881 main reload loop in the most common case where register elimination
883 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
884 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
885 || GET_CODE (insn) == CALL_INSN)
886 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
888 maybe_fix_stack_asms ();
890 insns_need_reload = 0;
891 something_needs_elimination = 0;
893 /* Initialize to -1, which means take the first spill register. */
896 /* Spill any hard regs that we know we can't eliminate. */
897 CLEAR_HARD_REG_SET (used_spill_regs);
898 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
899 if (! ep->can_eliminate)
900 spill_hard_reg (ep->from, 1);
902 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
903 if (frame_pointer_needed)
904 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
906 finish_spills (global);
908 /* From now on, we may need to generate moves differently. We may also
909 allow modifications of insns which cause them to not be recognized.
910 Any such modifications will be cleaned up during reload itself. */
911 reload_in_progress = 1;
913 /* This loop scans the entire function each go-round
914 and repeats until one repetition spills no additional hard regs. */
917 int something_changed;
920 HOST_WIDE_INT starting_frame_size;
922 /* Round size of stack frame to stack_alignment_needed. This must be done
923 here because the stack size may be a part of the offset computation
924 for register elimination, and there might have been new stack slots
925 created in the last iteration of this loop. */
926 if (cfun->stack_alignment_needed)
927 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
929 starting_frame_size = get_frame_size ();
931 set_initial_elim_offsets ();
932 set_initial_label_offsets ();
934 /* For each pseudo register that has an equivalent location defined,
935 try to eliminate any eliminable registers (such as the frame pointer)
936 assuming initial offsets for the replacement register, which
939 If the resulting location is directly addressable, substitute
940 the MEM we just got directly for the old REG.
942 If it is not addressable but is a constant or the sum of a hard reg
943 and constant, it is probably not addressable because the constant is
944 out of range, in that case record the address; we will generate
945 hairy code to compute the address in a register each time it is
946 needed. Similarly if it is a hard register, but one that is not
947 valid as an address register.
949 If the location is not addressable, but does not have one of the
950 above forms, assign a stack slot. We have to do this to avoid the
951 potential of producing lots of reloads if, e.g., a location involves
952 a pseudo that didn't get a hard register and has an equivalent memory
953 location that also involves a pseudo that didn't get a hard register.
955 Perhaps at some point we will improve reload_when_needed handling
956 so this problem goes away. But that's very hairy. */
958 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
959 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
961 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
963 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
965 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
966 else if (CONSTANT_P (XEXP (x, 0))
967 || (GET_CODE (XEXP (x, 0)) == REG
968 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
969 || (GET_CODE (XEXP (x, 0)) == PLUS
970 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
971 && (REGNO (XEXP (XEXP (x, 0), 0))
972 < FIRST_PSEUDO_REGISTER)
973 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
974 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
977 /* Make a new stack slot. Then indicate that something
978 changed so we go back and recompute offsets for
979 eliminable registers because the allocation of memory
980 below might change some offset. reg_equiv_{mem,address}
981 will be set up for this pseudo on the next pass around
983 reg_equiv_memory_loc[i] = 0;
984 reg_equiv_init[i] = 0;
989 if (caller_save_needed)
992 /* If we allocated another stack slot, redo elimination bookkeeping. */
993 if (starting_frame_size != get_frame_size ())
996 if (caller_save_needed)
998 save_call_clobbered_regs ();
999 /* That might have allocated new insn_chain structures. */
1000 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1003 calculate_needs_all_insns (global);
1005 CLEAR_REG_SET (&spilled_pseudos);
1008 something_changed = 0;
1010 /* If we allocated any new memory locations, make another pass
1011 since it might have changed elimination offsets. */
1012 if (starting_frame_size != get_frame_size ())
1013 something_changed = 1;
1016 HARD_REG_SET to_spill;
1017 CLEAR_HARD_REG_SET (to_spill);
1018 update_eliminables (&to_spill);
1019 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1020 if (TEST_HARD_REG_BIT (to_spill, i))
1022 spill_hard_reg (i, 1);
1025 /* Regardless of the state of spills, if we previously had
1026 a register that we thought we could eliminate, but no can
1027 not eliminate, we must run another pass.
1029 Consider pseudos which have an entry in reg_equiv_* which
1030 reference an eliminable register. We must make another pass
1031 to update reg_equiv_* so that we do not substitute in the
1032 old value from when we thought the elimination could be
1034 something_changed = 1;
1038 select_reload_regs ();
1042 if (insns_need_reload != 0 || did_spill)
1043 something_changed |= finish_spills (global);
1045 if (! something_changed)
1048 if (caller_save_needed)
1049 delete_caller_save_insns ();
1051 obstack_free (&reload_obstack, reload_firstobj);
1054 /* If global-alloc was run, notify it of any register eliminations we have
1057 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1058 if (ep->can_eliminate)
1059 mark_elimination (ep->from, ep->to);
1061 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1062 If that insn didn't set the register (i.e., it copied the register to
1063 memory), just delete that insn instead of the equivalencing insn plus
1064 anything now dead. If we call delete_dead_insn on that insn, we may
1065 delete the insn that actually sets the register if the register dies
1066 there and that is incorrect. */
1068 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1070 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1073 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1075 rtx equiv_insn = XEXP (list, 0);
1077 /* If we already deleted the insn or if it may trap, we can't
1078 delete it. The latter case shouldn't happen, but can
1079 if an insn has a variable address, gets a REG_EH_REGION
1080 note added to it, and then gets converted into an load
1081 from a constant address. */
1082 if (GET_CODE (equiv_insn) == NOTE
1083 || can_throw_internal (equiv_insn))
1085 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1086 delete_dead_insn (equiv_insn);
1089 PUT_CODE (equiv_insn, NOTE);
1090 NOTE_SOURCE_FILE (equiv_insn) = 0;
1091 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1097 /* Use the reload registers where necessary
1098 by generating move instructions to move the must-be-register
1099 values into or out of the reload registers. */
1101 if (insns_need_reload != 0 || something_needs_elimination
1102 || something_needs_operands_changed)
1104 HOST_WIDE_INT old_frame_size = get_frame_size ();
1106 reload_as_needed (global);
1108 if (old_frame_size != get_frame_size ())
1112 verify_initial_elim_offsets ();
1115 /* If we were able to eliminate the frame pointer, show that it is no
1116 longer live at the start of any basic block. If it ls live by
1117 virtue of being in a pseudo, that pseudo will be marked live
1118 and hence the frame pointer will be known to be live via that
1121 if (! frame_pointer_needed)
1123 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1124 HARD_FRAME_POINTER_REGNUM);
1126 /* Come here (with failure set nonzero) if we can't get enough spill regs
1127 and we decide not to abort about it. */
1130 CLEAR_REG_SET (&spilled_pseudos);
1131 reload_in_progress = 0;
1133 /* Now eliminate all pseudo regs by modifying them into
1134 their equivalent memory references.
1135 The REG-rtx's for the pseudos are modified in place,
1136 so all insns that used to refer to them now refer to memory.
1138 For a reg that has a reg_equiv_address, all those insns
1139 were changed by reloading so that no insns refer to it any longer;
1140 but the DECL_RTL of a variable decl may refer to it,
1141 and if so this causes the debugging info to mention the variable. */
1143 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1147 if (reg_equiv_mem[i])
1148 addr = XEXP (reg_equiv_mem[i], 0);
1150 if (reg_equiv_address[i])
1151 addr = reg_equiv_address[i];
1155 if (reg_renumber[i] < 0)
1157 rtx reg = regno_reg_rtx[i];
1159 REG_USERVAR_P (reg) = 0;
1160 PUT_CODE (reg, MEM);
1161 XEXP (reg, 0) = addr;
1162 if (reg_equiv_memory_loc[i])
1163 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1166 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1167 = MEM_SCALAR_P (reg) = 0;
1168 MEM_ATTRS (reg) = 0;
1171 else if (reg_equiv_mem[i])
1172 XEXP (reg_equiv_mem[i], 0) = addr;
1176 /* We must set reload_completed now since the cleanup_subreg_operands call
1177 below will re-recognize each insn and reload may have generated insns
1178 which are only valid during and after reload. */
1179 reload_completed = 1;
1181 /* Make a pass over all the insns and delete all USEs which we inserted
1182 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1183 notes. Delete all CLOBBER insns, except those that refer to the return
1184 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1185 from misarranging variable-array code, and simplify (subreg (reg))
1186 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1187 are no longer useful or accurate. Strip and regenerate REG_INC notes
1188 that may have been moved around. */
1190 for (insn = first; insn; insn = NEXT_INSN (insn))
1195 if (GET_CODE (insn) == CALL_INSN)
1196 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1198 CALL_INSN_FUNCTION_USAGE (insn));
1200 if ((GET_CODE (PATTERN (insn)) == USE
1201 /* We mark with QImode USEs introduced by reload itself. */
1202 && (GET_MODE (insn) == QImode
1203 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1204 || (GET_CODE (PATTERN (insn)) == CLOBBER
1205 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1206 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1207 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1208 && XEXP (XEXP (PATTERN (insn), 0), 0)
1209 != stack_pointer_rtx))
1210 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1211 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1217 pnote = ®_NOTES (insn);
1220 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1221 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1222 || REG_NOTE_KIND (*pnote) == REG_INC
1223 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1224 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1225 *pnote = XEXP (*pnote, 1);
1227 pnote = &XEXP (*pnote, 1);
1231 add_auto_inc_notes (insn, PATTERN (insn));
1234 /* And simplify (subreg (reg)) if it appears as an operand. */
1235 cleanup_subreg_operands (insn);
1238 /* If we are doing stack checking, give a warning if this function's
1239 frame size is larger than we expect. */
1240 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1242 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1243 static int verbose_warned = 0;
1245 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1246 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1247 size += UNITS_PER_WORD;
1249 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1251 warning ("frame size too large for reliable stack checking");
1252 if (! verbose_warned)
1254 warning ("try reducing the number of local variables");
1260 /* Indicate that we no longer have known memory locations or constants. */
1261 if (reg_equiv_constant)
1262 free (reg_equiv_constant);
1263 reg_equiv_constant = 0;
1264 if (reg_equiv_memory_loc)
1265 free (reg_equiv_memory_loc);
1266 reg_equiv_memory_loc = 0;
1269 free (real_known_ptr);
1273 free (reg_equiv_mem);
1274 free (reg_equiv_init);
1275 free (reg_equiv_address);
1276 free (reg_max_ref_width);
1277 free (reg_old_renumber);
1278 free (pseudo_previous_regs);
1279 free (pseudo_forbidden_regs);
1281 CLEAR_HARD_REG_SET (used_spill_regs);
1282 for (i = 0; i < n_spills; i++)
1283 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1285 /* Free all the insn_chain structures at once. */
1286 obstack_free (&reload_obstack, reload_startobj);
1287 unused_insn_chains = 0;
1288 fixup_abnormal_edges ();
1290 /* Replacing pseudos with their memory equivalents might have
1291 created shared rtx. Subsequent passes would get confused
1292 by this, so unshare everything here. */
1293 unshare_all_rtl_again (first);
1298 /* Yet another special case. Unfortunately, reg-stack forces people to
1299 write incorrect clobbers in asm statements. These clobbers must not
1300 cause the register to appear in bad_spill_regs, otherwise we'll call
1301 fatal_insn later. We clear the corresponding regnos in the live
1302 register sets to avoid this.
1303 The whole thing is rather sick, I'm afraid. */
1306 maybe_fix_stack_asms ()
1309 const char *constraints[MAX_RECOG_OPERANDS];
1310 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1311 struct insn_chain *chain;
1313 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1316 HARD_REG_SET clobbered, allowed;
1319 if (! INSN_P (chain->insn)
1320 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1322 pat = PATTERN (chain->insn);
1323 if (GET_CODE (pat) != PARALLEL)
1326 CLEAR_HARD_REG_SET (clobbered);
1327 CLEAR_HARD_REG_SET (allowed);
1329 /* First, make a mask of all stack regs that are clobbered. */
1330 for (i = 0; i < XVECLEN (pat, 0); i++)
1332 rtx t = XVECEXP (pat, 0, i);
1333 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1334 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1337 /* Get the operand values and constraints out of the insn. */
1338 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1339 constraints, operand_mode);
1341 /* For every operand, see what registers are allowed. */
1342 for (i = 0; i < noperands; i++)
1344 const char *p = constraints[i];
1345 /* For every alternative, we compute the class of registers allowed
1346 for reloading in CLS, and merge its contents into the reg set
1348 int cls = (int) NO_REGS;
1354 if (c == '\0' || c == ',' || c == '#')
1356 /* End of one alternative - mark the regs in the current
1357 class, and reset the class. */
1358 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1363 } while (c != '\0' && c != ',');
1371 case '=': case '+': case '*': case '%': case '?': case '!':
1372 case '0': case '1': case '2': case '3': case '4': case 'm':
1373 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1374 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1375 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1380 cls = (int) reg_class_subunion[cls]
1381 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1386 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1390 if (EXTRA_ADDRESS_CONSTRAINT (c))
1391 cls = (int) reg_class_subunion[cls]
1392 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1394 cls = (int) reg_class_subunion[cls]
1395 [(int) REG_CLASS_FROM_LETTER (c)];
1399 /* Those of the registers which are clobbered, but allowed by the
1400 constraints, must be usable as reload registers. So clear them
1401 out of the life information. */
1402 AND_HARD_REG_SET (allowed, clobbered);
1403 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1404 if (TEST_HARD_REG_BIT (allowed, i))
1406 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1407 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1414 /* Copy the global variables n_reloads and rld into the corresponding elts
1417 copy_reloads (chain)
1418 struct insn_chain *chain;
1420 chain->n_reloads = n_reloads;
1422 = (struct reload *) obstack_alloc (&reload_obstack,
1423 n_reloads * sizeof (struct reload));
1424 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1425 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1428 /* Walk the chain of insns, and determine for each whether it needs reloads
1429 and/or eliminations. Build the corresponding insns_need_reload list, and
1430 set something_needs_elimination as appropriate. */
1432 calculate_needs_all_insns (global)
1435 struct insn_chain **pprev_reload = &insns_need_reload;
1436 struct insn_chain *chain, *next = 0;
1438 something_needs_elimination = 0;
1440 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1441 for (chain = reload_insn_chain; chain != 0; chain = next)
1443 rtx insn = chain->insn;
1447 /* Clear out the shortcuts. */
1448 chain->n_reloads = 0;
1449 chain->need_elim = 0;
1450 chain->need_reload = 0;
1451 chain->need_operand_change = 0;
1453 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1454 include REG_LABEL), we need to see what effects this has on the
1455 known offsets at labels. */
1457 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1458 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1459 set_label_offsets (insn, insn, 0);
1463 rtx old_body = PATTERN (insn);
1464 int old_code = INSN_CODE (insn);
1465 rtx old_notes = REG_NOTES (insn);
1466 int did_elimination = 0;
1467 int operands_changed = 0;
1468 rtx set = single_set (insn);
1470 /* Skip insns that only set an equivalence. */
1471 if (set && GET_CODE (SET_DEST (set)) == REG
1472 && reg_renumber[REGNO (SET_DEST (set))] < 0
1473 && reg_equiv_constant[REGNO (SET_DEST (set))])
1476 /* If needed, eliminate any eliminable registers. */
1477 if (num_eliminable || num_eliminable_invariants)
1478 did_elimination = eliminate_regs_in_insn (insn, 0);
1480 /* Analyze the instruction. */
1481 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1482 global, spill_reg_order);
1484 /* If a no-op set needs more than one reload, this is likely
1485 to be something that needs input address reloads. We
1486 can't get rid of this cleanly later, and it is of no use
1487 anyway, so discard it now.
1488 We only do this when expensive_optimizations is enabled,
1489 since this complements reload inheritance / output
1490 reload deletion, and it can make debugging harder. */
1491 if (flag_expensive_optimizations && n_reloads > 1)
1493 rtx set = single_set (insn);
1495 && SET_SRC (set) == SET_DEST (set)
1496 && GET_CODE (SET_SRC (set)) == REG
1497 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1500 /* Delete it from the reload chain */
1502 chain->prev->next = next;
1504 reload_insn_chain = next;
1506 next->prev = chain->prev;
1507 chain->next = unused_insn_chains;
1508 unused_insn_chains = chain;
1513 update_eliminable_offsets ();
1515 /* Remember for later shortcuts which insns had any reloads or
1516 register eliminations. */
1517 chain->need_elim = did_elimination;
1518 chain->need_reload = n_reloads > 0;
1519 chain->need_operand_change = operands_changed;
1521 /* Discard any register replacements done. */
1522 if (did_elimination)
1524 obstack_free (&reload_obstack, reload_insn_firstobj);
1525 PATTERN (insn) = old_body;
1526 INSN_CODE (insn) = old_code;
1527 REG_NOTES (insn) = old_notes;
1528 something_needs_elimination = 1;
1531 something_needs_operands_changed |= operands_changed;
1535 copy_reloads (chain);
1536 *pprev_reload = chain;
1537 pprev_reload = &chain->next_need_reload;
1544 /* Comparison function for qsort to decide which of two reloads
1545 should be handled first. *P1 and *P2 are the reload numbers. */
1548 reload_reg_class_lower (r1p, r2p)
1552 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1555 /* Consider required reloads before optional ones. */
1556 t = rld[r1].optional - rld[r2].optional;
1560 /* Count all solitary classes before non-solitary ones. */
1561 t = ((reg_class_size[(int) rld[r2].class] == 1)
1562 - (reg_class_size[(int) rld[r1].class] == 1));
1566 /* Aside from solitaires, consider all multi-reg groups first. */
1567 t = rld[r2].nregs - rld[r1].nregs;
1571 /* Consider reloads in order of increasing reg-class number. */
1572 t = (int) rld[r1].class - (int) rld[r2].class;
1576 /* If reloads are equally urgent, sort by reload number,
1577 so that the results of qsort leave nothing to chance. */
1581 /* The cost of spilling each hard reg. */
1582 static int spill_cost[FIRST_PSEUDO_REGISTER];
1584 /* When spilling multiple hard registers, we use SPILL_COST for the first
1585 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1586 only the first hard reg for a multi-reg pseudo. */
1587 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1589 /* Update the spill cost arrays, considering that pseudo REG is live. */
1595 int freq = REG_FREQ (reg);
1596 int r = reg_renumber[reg];
1599 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1600 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1603 SET_REGNO_REG_SET (&pseudos_counted, reg);
1608 spill_add_cost[r] += freq;
1610 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1612 spill_cost[r + nregs] += freq;
1615 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1616 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1619 order_regs_for_reload (chain)
1620 struct insn_chain *chain;
1623 HARD_REG_SET used_by_pseudos;
1624 HARD_REG_SET used_by_pseudos2;
1626 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1628 memset (spill_cost, 0, sizeof spill_cost);
1629 memset (spill_add_cost, 0, sizeof spill_add_cost);
1631 /* Count number of uses of each hard reg by pseudo regs allocated to it
1632 and then order them by decreasing use. First exclude hard registers
1633 that are live in or across this insn. */
1635 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1636 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1637 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1638 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1640 /* Now find out which pseudos are allocated to it, and update
1642 CLEAR_REG_SET (&pseudos_counted);
1644 EXECUTE_IF_SET_IN_REG_SET
1645 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1649 EXECUTE_IF_SET_IN_REG_SET
1650 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1654 CLEAR_REG_SET (&pseudos_counted);
1657 /* Vector of reload-numbers showing the order in which the reloads should
1659 static short reload_order[MAX_RELOADS];
1661 /* This is used to keep track of the spill regs used in one insn. */
1662 static HARD_REG_SET used_spill_regs_local;
1664 /* We decided to spill hard register SPILLED, which has a size of
1665 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1666 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1667 update SPILL_COST/SPILL_ADD_COST. */
1670 count_spilled_pseudo (spilled, spilled_nregs, reg)
1671 int spilled, spilled_nregs, reg;
1673 int r = reg_renumber[reg];
1674 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1676 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1677 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1680 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1682 spill_add_cost[r] -= REG_FREQ (reg);
1684 spill_cost[r + nregs] -= REG_FREQ (reg);
1687 /* Find reload register to use for reload number ORDER. */
1690 find_reg (chain, order)
1691 struct insn_chain *chain;
1694 int rnum = reload_order[order];
1695 struct reload *rl = rld + rnum;
1696 int best_cost = INT_MAX;
1700 HARD_REG_SET not_usable;
1701 HARD_REG_SET used_by_other_reload;
1703 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1704 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1705 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1707 CLEAR_HARD_REG_SET (used_by_other_reload);
1708 for (k = 0; k < order; k++)
1710 int other = reload_order[k];
1712 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1713 for (j = 0; j < rld[other].nregs; j++)
1714 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1717 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1719 unsigned int regno = i;
1721 if (! TEST_HARD_REG_BIT (not_usable, regno)
1722 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1723 && HARD_REGNO_MODE_OK (regno, rl->mode))
1725 int this_cost = spill_cost[regno];
1727 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1729 for (j = 1; j < this_nregs; j++)
1731 this_cost += spill_add_cost[regno + j];
1732 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1733 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1738 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1740 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1742 if (this_cost < best_cost
1743 /* Among registers with equal cost, prefer caller-saved ones, or
1744 use REG_ALLOC_ORDER if it is defined. */
1745 || (this_cost == best_cost
1746 #ifdef REG_ALLOC_ORDER
1747 && (inv_reg_alloc_order[regno]
1748 < inv_reg_alloc_order[best_reg])
1750 && call_used_regs[regno]
1751 && ! call_used_regs[best_reg]
1756 best_cost = this_cost;
1764 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1766 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1767 rl->regno = best_reg;
1769 EXECUTE_IF_SET_IN_REG_SET
1770 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1772 count_spilled_pseudo (best_reg, rl->nregs, j);
1775 EXECUTE_IF_SET_IN_REG_SET
1776 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1778 count_spilled_pseudo (best_reg, rl->nregs, j);
1781 for (i = 0; i < rl->nregs; i++)
1783 if (spill_cost[best_reg + i] != 0
1784 || spill_add_cost[best_reg + i] != 0)
1786 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1791 /* Find more reload regs to satisfy the remaining need of an insn, which
1793 Do it by ascending class number, since otherwise a reg
1794 might be spilled for a big class and might fail to count
1795 for a smaller class even though it belongs to that class. */
1798 find_reload_regs (chain)
1799 struct insn_chain *chain;
1803 /* In order to be certain of getting the registers we need,
1804 we must sort the reloads into order of increasing register class.
1805 Then our grabbing of reload registers will parallel the process
1806 that provided the reload registers. */
1807 for (i = 0; i < chain->n_reloads; i++)
1809 /* Show whether this reload already has a hard reg. */
1810 if (chain->rld[i].reg_rtx)
1812 int regno = REGNO (chain->rld[i].reg_rtx);
1813 chain->rld[i].regno = regno;
1815 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1818 chain->rld[i].regno = -1;
1819 reload_order[i] = i;
1822 n_reloads = chain->n_reloads;
1823 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1825 CLEAR_HARD_REG_SET (used_spill_regs_local);
1828 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1830 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1832 /* Compute the order of preference for hard registers to spill. */
1834 order_regs_for_reload (chain);
1836 for (i = 0; i < n_reloads; i++)
1838 int r = reload_order[i];
1840 /* Ignore reloads that got marked inoperative. */
1841 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1842 && ! rld[r].optional
1843 && rld[r].regno == -1)
1844 if (! find_reg (chain, i))
1846 spill_failure (chain->insn, rld[r].class);
1852 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1853 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1855 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1859 select_reload_regs ()
1861 struct insn_chain *chain;
1863 /* Try to satisfy the needs for each insn. */
1864 for (chain = insns_need_reload; chain != 0;
1865 chain = chain->next_need_reload)
1866 find_reload_regs (chain);
1869 /* Delete all insns that were inserted by emit_caller_save_insns during
1872 delete_caller_save_insns ()
1874 struct insn_chain *c = reload_insn_chain;
1878 while (c != 0 && c->is_caller_save_insn)
1880 struct insn_chain *next = c->next;
1883 if (c == reload_insn_chain)
1884 reload_insn_chain = next;
1888 next->prev = c->prev;
1890 c->prev->next = next;
1891 c->next = unused_insn_chains;
1892 unused_insn_chains = c;
1900 /* Handle the failure to find a register to spill.
1901 INSN should be one of the insns which needed this particular spill reg. */
1904 spill_failure (insn, class)
1906 enum reg_class class;
1908 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1909 if (asm_noperands (PATTERN (insn)) >= 0)
1910 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1911 reg_class_names[class]);
1914 error ("unable to find a register to spill in class `%s'",
1915 reg_class_names[class]);
1916 fatal_insn ("this is the insn:", insn);
1920 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1921 data that is dead in INSN. */
1924 delete_dead_insn (insn)
1927 rtx prev = prev_real_insn (insn);
1930 /* If the previous insn sets a register that dies in our insn, delete it
1932 if (prev && GET_CODE (PATTERN (prev)) == SET
1933 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1934 && reg_mentioned_p (prev_dest, PATTERN (insn))
1935 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1936 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1937 delete_dead_insn (prev);
1939 PUT_CODE (insn, NOTE);
1940 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1941 NOTE_SOURCE_FILE (insn) = 0;
1944 /* Modify the home of pseudo-reg I.
1945 The new home is present in reg_renumber[I].
1947 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1948 or it may be -1, meaning there is none or it is not relevant.
1949 This is used so that all pseudos spilled from a given hard reg
1950 can share one stack slot. */
1953 alter_reg (i, from_reg)
1957 /* When outputting an inline function, this can happen
1958 for a reg that isn't actually used. */
1959 if (regno_reg_rtx[i] == 0)
1962 /* If the reg got changed to a MEM at rtl-generation time,
1964 if (GET_CODE (regno_reg_rtx[i]) != REG)
1967 /* Modify the reg-rtx to contain the new hard reg
1968 number or else to contain its pseudo reg number. */
1969 REGNO (regno_reg_rtx[i])
1970 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1972 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1973 allocate a stack slot for it. */
1975 if (reg_renumber[i] < 0
1976 && REG_N_REFS (i) > 0
1977 && reg_equiv_constant[i] == 0
1978 && reg_equiv_memory_loc[i] == 0)
1981 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1982 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1985 /* Each pseudo reg has an inherent size which comes from its own mode,
1986 and a total size which provides room for paradoxical subregs
1987 which refer to the pseudo reg in wider modes.
1989 We can use a slot already allocated if it provides both
1990 enough inherent space and enough total space.
1991 Otherwise, we allocate a new slot, making sure that it has no less
1992 inherent space, and no less total space, then the previous slot. */
1995 /* No known place to spill from => no slot to reuse. */
1996 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1997 inherent_size == total_size ? 0 : -1);
1998 if (BYTES_BIG_ENDIAN)
1999 /* Cancel the big-endian correction done in assign_stack_local.
2000 Get the address of the beginning of the slot.
2001 This is so we can do a big-endian correction unconditionally
2003 adjust = inherent_size - total_size;
2005 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2007 /* Nothing can alias this slot except this pseudo. */
2008 set_mem_alias_set (x, new_alias_set ());
2011 /* Reuse a stack slot if possible. */
2012 else if (spill_stack_slot[from_reg] != 0
2013 && spill_stack_slot_width[from_reg] >= total_size
2014 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2016 x = spill_stack_slot[from_reg];
2018 /* Allocate a bigger slot. */
2021 /* Compute maximum size needed, both for inherent size
2022 and for total size. */
2023 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2026 if (spill_stack_slot[from_reg])
2028 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2030 mode = GET_MODE (spill_stack_slot[from_reg]);
2031 if (spill_stack_slot_width[from_reg] > total_size)
2032 total_size = spill_stack_slot_width[from_reg];
2035 /* Make a slot with that size. */
2036 x = assign_stack_local (mode, total_size,
2037 inherent_size == total_size ? 0 : -1);
2040 /* All pseudos mapped to this slot can alias each other. */
2041 if (spill_stack_slot[from_reg])
2042 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2044 set_mem_alias_set (x, new_alias_set ());
2046 if (BYTES_BIG_ENDIAN)
2048 /* Cancel the big-endian correction done in assign_stack_local.
2049 Get the address of the beginning of the slot.
2050 This is so we can do a big-endian correction unconditionally
2052 adjust = GET_MODE_SIZE (mode) - total_size;
2055 = adjust_address_nv (x, mode_for_size (total_size
2061 spill_stack_slot[from_reg] = stack_slot;
2062 spill_stack_slot_width[from_reg] = total_size;
2065 /* On a big endian machine, the "address" of the slot
2066 is the address of the low part that fits its inherent mode. */
2067 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2068 adjust += (total_size - inherent_size);
2070 /* If we have any adjustment to make, or if the stack slot is the
2071 wrong mode, make a new stack slot. */
2072 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2074 /* If we have a decl for the original register, set it for the
2075 memory. If this is a shared MEM, make a copy. */
2078 rtx decl = DECL_RTL_IF_SET (REGNO_DECL (i));
2080 /* We can do this only for the DECLs home pseudo, not for
2081 any copies of it, since otherwise when the stack slot
2082 is reused, nonoverlapping_memrefs_p might think they
2084 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2086 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2089 set_mem_expr (x, REGNO_DECL (i));
2093 /* Save the stack slot for later. */
2094 reg_equiv_memory_loc[i] = x;
2098 /* Mark the slots in regs_ever_live for the hard regs
2099 used by pseudo-reg number REGNO. */
2102 mark_home_live (regno)
2107 i = reg_renumber[regno];
2110 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2112 regs_ever_live[i++] = 1;
2115 /* This function handles the tracking of elimination offsets around branches.
2117 X is a piece of RTL being scanned.
2119 INSN is the insn that it came from, if any.
2121 INITIAL_P is non-zero if we are to set the offset to be the initial
2122 offset and zero if we are setting the offset of the label to be the
2126 set_label_offsets (x, insn, initial_p)
2131 enum rtx_code code = GET_CODE (x);
2134 struct elim_table *p;
2139 if (LABEL_REF_NONLOCAL_P (x))
2144 /* ... fall through ... */
2147 /* If we know nothing about this label, set the desired offsets. Note
2148 that this sets the offset at a label to be the offset before a label
2149 if we don't know anything about the label. This is not correct for
2150 the label after a BARRIER, but is the best guess we can make. If
2151 we guessed wrong, we will suppress an elimination that might have
2152 been possible had we been able to guess correctly. */
2154 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2156 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2157 offsets_at[CODE_LABEL_NUMBER (x)][i]
2158 = (initial_p ? reg_eliminate[i].initial_offset
2159 : reg_eliminate[i].offset);
2160 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2163 /* Otherwise, if this is the definition of a label and it is
2164 preceded by a BARRIER, set our offsets to the known offset of
2168 && (tem = prev_nonnote_insn (insn)) != 0
2169 && GET_CODE (tem) == BARRIER)
2170 set_offsets_for_label (insn);
2172 /* If neither of the above cases is true, compare each offset
2173 with those previously recorded and suppress any eliminations
2174 where the offsets disagree. */
2176 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2177 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2178 != (initial_p ? reg_eliminate[i].initial_offset
2179 : reg_eliminate[i].offset))
2180 reg_eliminate[i].can_eliminate = 0;
2185 set_label_offsets (PATTERN (insn), insn, initial_p);
2187 /* ... fall through ... */
2191 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2192 and hence must have all eliminations at their initial offsets. */
2193 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2194 if (REG_NOTE_KIND (tem) == REG_LABEL)
2195 set_label_offsets (XEXP (tem, 0), insn, 1);
2201 /* Each of the labels in the parallel or address vector must be
2202 at their initial offsets. We want the first field for PARALLEL
2203 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2205 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2206 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2211 /* We only care about setting PC. If the source is not RETURN,
2212 IF_THEN_ELSE, or a label, disable any eliminations not at
2213 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2214 isn't one of those possibilities. For branches to a label,
2215 call ourselves recursively.
2217 Note that this can disable elimination unnecessarily when we have
2218 a non-local goto since it will look like a non-constant jump to
2219 someplace in the current function. This isn't a significant
2220 problem since such jumps will normally be when all elimination
2221 pairs are back to their initial offsets. */
2223 if (SET_DEST (x) != pc_rtx)
2226 switch (GET_CODE (SET_SRC (x)))
2233 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2237 tem = XEXP (SET_SRC (x), 1);
2238 if (GET_CODE (tem) == LABEL_REF)
2239 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2240 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2243 tem = XEXP (SET_SRC (x), 2);
2244 if (GET_CODE (tem) == LABEL_REF)
2245 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2246 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2254 /* If we reach here, all eliminations must be at their initial
2255 offset because we are doing a jump to a variable address. */
2256 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2257 if (p->offset != p->initial_offset)
2258 p->can_eliminate = 0;
2266 /* Scan X and replace any eliminable registers (such as fp) with a
2267 replacement (such as sp), plus an offset.
2269 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2270 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2271 MEM, we are allowed to replace a sum of a register and the constant zero
2272 with the register, which we cannot do outside a MEM. In addition, we need
2273 to record the fact that a register is referenced outside a MEM.
2275 If INSN is an insn, it is the insn containing X. If we replace a REG
2276 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2277 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2278 the REG is being modified.
2280 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2281 That's used when we eliminate in expressions stored in notes.
2282 This means, do not set ref_outside_mem even if the reference
2285 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2286 replacements done assuming all offsets are at their initial values. If
2287 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2288 encounter, return the actual location so that find_reloads will do
2289 the proper thing. */
2292 eliminate_regs (x, mem_mode, insn)
2294 enum machine_mode mem_mode;
2297 enum rtx_code code = GET_CODE (x);
2298 struct elim_table *ep;
2305 if (! current_function_decl)
2325 /* This is only for the benefit of the debugging backends, which call
2326 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2327 removed after CSE. */
2328 new = eliminate_regs (XEXP (x, 0), 0, insn);
2329 if (GET_CODE (new) == MEM)
2330 return XEXP (new, 0);
2336 /* First handle the case where we encounter a bare register that
2337 is eliminable. Replace it with a PLUS. */
2338 if (regno < FIRST_PSEUDO_REGISTER)
2340 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2342 if (ep->from_rtx == x && ep->can_eliminate)
2343 return plus_constant (ep->to_rtx, ep->previous_offset);
2346 else if (reg_renumber && reg_renumber[regno] < 0
2347 && reg_equiv_constant && reg_equiv_constant[regno]
2348 && ! CONSTANT_P (reg_equiv_constant[regno]))
2349 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2353 /* You might think handling MINUS in a manner similar to PLUS is a
2354 good idea. It is not. It has been tried multiple times and every
2355 time the change has had to have been reverted.
2357 Other parts of reload know a PLUS is special (gen_reload for example)
2358 and require special code to handle code a reloaded PLUS operand.
2360 Also consider backends where the flags register is clobbered by a
2361 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2362 lea instruction comes to mind). If we try to reload a MINUS, we
2363 may kill the flags register that was holding a useful value.
2365 So, please before trying to handle MINUS, consider reload as a
2366 whole instead of this little section as well as the backend issues. */
2368 /* If this is the sum of an eliminable register and a constant, rework
2370 if (GET_CODE (XEXP (x, 0)) == REG
2371 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2372 && CONSTANT_P (XEXP (x, 1)))
2374 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2376 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2378 /* The only time we want to replace a PLUS with a REG (this
2379 occurs when the constant operand of the PLUS is the negative
2380 of the offset) is when we are inside a MEM. We won't want
2381 to do so at other times because that would change the
2382 structure of the insn in a way that reload can't handle.
2383 We special-case the commonest situation in
2384 eliminate_regs_in_insn, so just replace a PLUS with a
2385 PLUS here, unless inside a MEM. */
2386 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2387 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2390 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2391 plus_constant (XEXP (x, 1),
2392 ep->previous_offset));
2395 /* If the register is not eliminable, we are done since the other
2396 operand is a constant. */
2400 /* If this is part of an address, we want to bring any constant to the
2401 outermost PLUS. We will do this by doing register replacement in
2402 our operands and seeing if a constant shows up in one of them.
2404 Note that there is no risk of modifying the structure of the insn,
2405 since we only get called for its operands, thus we are either
2406 modifying the address inside a MEM, or something like an address
2407 operand of a load-address insn. */
2410 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2411 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2413 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2415 /* If one side is a PLUS and the other side is a pseudo that
2416 didn't get a hard register but has a reg_equiv_constant,
2417 we must replace the constant here since it may no longer
2418 be in the position of any operand. */
2419 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2420 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2421 && reg_renumber[REGNO (new1)] < 0
2422 && reg_equiv_constant != 0
2423 && reg_equiv_constant[REGNO (new1)] != 0)
2424 new1 = reg_equiv_constant[REGNO (new1)];
2425 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2426 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2427 && reg_renumber[REGNO (new0)] < 0
2428 && reg_equiv_constant[REGNO (new0)] != 0)
2429 new0 = reg_equiv_constant[REGNO (new0)];
2431 new = form_sum (new0, new1);
2433 /* As above, if we are not inside a MEM we do not want to
2434 turn a PLUS into something else. We might try to do so here
2435 for an addition of 0 if we aren't optimizing. */
2436 if (! mem_mode && GET_CODE (new) != PLUS)
2437 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2445 /* If this is the product of an eliminable register and a
2446 constant, apply the distribute law and move the constant out
2447 so that we have (plus (mult ..) ..). This is needed in order
2448 to keep load-address insns valid. This case is pathological.
2449 We ignore the possibility of overflow here. */
2450 if (GET_CODE (XEXP (x, 0)) == REG
2451 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2452 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2453 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2455 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2458 /* Refs inside notes don't count for this purpose. */
2459 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2460 || GET_CODE (insn) == INSN_LIST)))
2461 ep->ref_outside_mem = 1;
2464 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2465 ep->previous_offset * INTVAL (XEXP (x, 1)));
2468 /* ... fall through ... */
2472 /* See comments before PLUS about handling MINUS. */
2474 case DIV: case UDIV:
2475 case MOD: case UMOD:
2476 case AND: case IOR: case XOR:
2477 case ROTATERT: case ROTATE:
2478 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2480 case GE: case GT: case GEU: case GTU:
2481 case LE: case LT: case LEU: case LTU:
2483 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2485 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2487 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2488 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2493 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2496 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2497 if (new != XEXP (x, 0))
2499 /* If this is a REG_DEAD note, it is not valid anymore.
2500 Using the eliminated version could result in creating a
2501 REG_DEAD note for the stack or frame pointer. */
2502 if (GET_MODE (x) == REG_DEAD)
2504 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2507 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2511 /* ... fall through ... */
2514 /* Now do eliminations in the rest of the chain. If this was
2515 an EXPR_LIST, this might result in allocating more memory than is
2516 strictly needed, but it simplifies the code. */
2519 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2520 if (new != XEXP (x, 1))
2522 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2530 case STRICT_LOW_PART:
2532 case SIGN_EXTEND: case ZERO_EXTEND:
2533 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2534 case FLOAT: case FIX:
2535 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2539 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2540 if (new != XEXP (x, 0))
2541 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2545 /* Similar to above processing, but preserve SUBREG_BYTE.
2546 Convert (subreg (mem)) to (mem) if not paradoxical.
2547 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2548 pseudo didn't get a hard reg, we must replace this with the
2549 eliminated version of the memory location because push_reloads
2550 may do the replacement in certain circumstances. */
2551 if (GET_CODE (SUBREG_REG (x)) == REG
2552 && (GET_MODE_SIZE (GET_MODE (x))
2553 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2554 && reg_equiv_memory_loc != 0
2555 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2557 new = SUBREG_REG (x);
2560 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2562 if (new != SUBREG_REG (x))
2564 int x_size = GET_MODE_SIZE (GET_MODE (x));
2565 int new_size = GET_MODE_SIZE (GET_MODE (new));
2567 if (GET_CODE (new) == MEM
2568 && ((x_size < new_size
2569 #ifdef WORD_REGISTER_OPERATIONS
2570 /* On these machines, combine can create rtl of the form
2571 (set (subreg:m1 (reg:m2 R) 0) ...)
2572 where m1 < m2, and expects something interesting to
2573 happen to the entire word. Moreover, it will use the
2574 (reg:m2 R) later, expecting all bits to be preserved.
2575 So if the number of words is the same, preserve the
2576 subreg so that push_reloads can see it. */
2577 && ! ((x_size - 1) / UNITS_PER_WORD
2578 == (new_size -1 ) / UNITS_PER_WORD)
2581 || x_size == new_size)
2583 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2585 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2591 /* This is only for the benefit of the debugging backends, which call
2592 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2593 removed after CSE. */
2594 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2595 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2597 /* Our only special processing is to pass the mode of the MEM to our
2598 recursive call and copy the flags. While we are here, handle this
2599 case more efficiently. */
2601 replace_equiv_address_nv (x,
2602 eliminate_regs (XEXP (x, 0),
2603 GET_MODE (x), insn));
2606 /* Handle insn_list USE that a call to a pure function may generate. */
2607 new = eliminate_regs (XEXP (x, 0), 0, insn);
2608 if (new != XEXP (x, 0))
2609 return gen_rtx_USE (GET_MODE (x), new);
2621 /* Process each of our operands recursively. If any have changed, make a
2623 fmt = GET_RTX_FORMAT (code);
2624 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2628 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2629 if (new != XEXP (x, i) && ! copied)
2631 rtx new_x = rtx_alloc (code);
2633 (sizeof (*new_x) - sizeof (new_x->fld)
2634 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2640 else if (*fmt == 'E')
2643 for (j = 0; j < XVECLEN (x, i); j++)
2645 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2646 if (new != XVECEXP (x, i, j) && ! copied_vec)
2648 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2652 rtx new_x = rtx_alloc (code);
2654 (sizeof (*new_x) - sizeof (new_x->fld)
2655 + (sizeof (new_x->fld[0])
2656 * GET_RTX_LENGTH (code))));
2660 XVEC (x, i) = new_v;
2663 XVECEXP (x, i, j) = new;
2671 /* Scan rtx X for modifications of elimination target registers. Update
2672 the table of eliminables to reflect the changed state. MEM_MODE is
2673 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2676 elimination_effects (x, mem_mode)
2678 enum machine_mode mem_mode;
2681 enum rtx_code code = GET_CODE (x);
2682 struct elim_table *ep;
2709 /* First handle the case where we encounter a bare register that
2710 is eliminable. Replace it with a PLUS. */
2711 if (regno < FIRST_PSEUDO_REGISTER)
2713 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2715 if (ep->from_rtx == x && ep->can_eliminate)
2718 ep->ref_outside_mem = 1;
2723 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2724 && reg_equiv_constant[regno]
2725 && ! function_invariant_p (reg_equiv_constant[regno]))
2726 elimination_effects (reg_equiv_constant[regno], mem_mode);
2735 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2736 if (ep->to_rtx == XEXP (x, 0))
2738 int size = GET_MODE_SIZE (mem_mode);
2740 /* If more bytes than MEM_MODE are pushed, account for them. */
2741 #ifdef PUSH_ROUNDING
2742 if (ep->to_rtx == stack_pointer_rtx)
2743 size = PUSH_ROUNDING (size);
2745 if (code == PRE_DEC || code == POST_DEC)
2747 else if (code == PRE_INC || code == POST_INC)
2749 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2750 && GET_CODE (XEXP (x, 1)) == PLUS
2751 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2752 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2753 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2756 /* These two aren't unary operators. */
2757 if (code == POST_MODIFY || code == PRE_MODIFY)
2760 /* Fall through to generic unary operation case. */
2761 case STRICT_LOW_PART:
2763 case SIGN_EXTEND: case ZERO_EXTEND:
2764 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2765 case FLOAT: case FIX:
2766 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2770 elimination_effects (XEXP (x, 0), mem_mode);
2774 if (GET_CODE (SUBREG_REG (x)) == REG
2775 && (GET_MODE_SIZE (GET_MODE (x))
2776 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2777 && reg_equiv_memory_loc != 0
2778 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2781 elimination_effects (SUBREG_REG (x), mem_mode);
2785 /* If using a register that is the source of an eliminate we still
2786 think can be performed, note it cannot be performed since we don't
2787 know how this register is used. */
2788 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2789 if (ep->from_rtx == XEXP (x, 0))
2790 ep->can_eliminate = 0;
2792 elimination_effects (XEXP (x, 0), mem_mode);
2796 /* If clobbering a register that is the replacement register for an
2797 elimination we still think can be performed, note that it cannot
2798 be performed. Otherwise, we need not be concerned about it. */
2799 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2800 if (ep->to_rtx == XEXP (x, 0))
2801 ep->can_eliminate = 0;
2803 elimination_effects (XEXP (x, 0), mem_mode);
2807 /* Check for setting a register that we know about. */
2808 if (GET_CODE (SET_DEST (x)) == REG)
2810 /* See if this is setting the replacement register for an
2813 If DEST is the hard frame pointer, we do nothing because we
2814 assume that all assignments to the frame pointer are for
2815 non-local gotos and are being done at a time when they are valid
2816 and do not disturb anything else. Some machines want to
2817 eliminate a fake argument pointer (or even a fake frame pointer)
2818 with either the real frame or the stack pointer. Assignments to
2819 the hard frame pointer must not prevent this elimination. */
2821 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2823 if (ep->to_rtx == SET_DEST (x)
2824 && SET_DEST (x) != hard_frame_pointer_rtx)
2826 /* If it is being incremented, adjust the offset. Otherwise,
2827 this elimination can't be done. */
2828 rtx src = SET_SRC (x);
2830 if (GET_CODE (src) == PLUS
2831 && XEXP (src, 0) == SET_DEST (x)
2832 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2833 ep->offset -= INTVAL (XEXP (src, 1));
2835 ep->can_eliminate = 0;
2839 elimination_effects (SET_DEST (x), 0);
2840 elimination_effects (SET_SRC (x), 0);
2844 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2847 /* Our only special processing is to pass the mode of the MEM to our
2849 elimination_effects (XEXP (x, 0), GET_MODE (x));
2856 fmt = GET_RTX_FORMAT (code);
2857 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2860 elimination_effects (XEXP (x, i), mem_mode);
2861 else if (*fmt == 'E')
2862 for (j = 0; j < XVECLEN (x, i); j++)
2863 elimination_effects (XVECEXP (x, i, j), mem_mode);
2867 /* Descend through rtx X and verify that no references to eliminable registers
2868 remain. If any do remain, mark the involved register as not
2872 check_eliminable_occurrences (x)
2882 code = GET_CODE (x);
2884 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2886 struct elim_table *ep;
2888 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2889 if (ep->from_rtx == x && ep->can_eliminate)
2890 ep->can_eliminate = 0;
2894 fmt = GET_RTX_FORMAT (code);
2895 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2898 check_eliminable_occurrences (XEXP (x, i));
2899 else if (*fmt == 'E')
2902 for (j = 0; j < XVECLEN (x, i); j++)
2903 check_eliminable_occurrences (XVECEXP (x, i, j));
2908 /* Scan INSN and eliminate all eliminable registers in it.
2910 If REPLACE is nonzero, do the replacement destructively. Also
2911 delete the insn as dead it if it is setting an eliminable register.
2913 If REPLACE is zero, do all our allocations in reload_obstack.
2915 If no eliminations were done and this insn doesn't require any elimination
2916 processing (these are not identical conditions: it might be updating sp,
2917 but not referencing fp; this needs to be seen during reload_as_needed so
2918 that the offset between fp and sp can be taken into consideration), zero
2919 is returned. Otherwise, 1 is returned. */
2922 eliminate_regs_in_insn (insn, replace)
2926 int icode = recog_memoized (insn);
2927 rtx old_body = PATTERN (insn);
2928 int insn_is_asm = asm_noperands (old_body) >= 0;
2929 rtx old_set = single_set (insn);
2933 rtx substed_operand[MAX_RECOG_OPERANDS];
2934 rtx orig_operand[MAX_RECOG_OPERANDS];
2935 struct elim_table *ep;
2937 if (! insn_is_asm && icode < 0)
2939 if (GET_CODE (PATTERN (insn)) == USE
2940 || GET_CODE (PATTERN (insn)) == CLOBBER
2941 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2942 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2943 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2948 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2949 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2951 /* Check for setting an eliminable register. */
2952 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2953 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2955 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2956 /* If this is setting the frame pointer register to the
2957 hardware frame pointer register and this is an elimination
2958 that will be done (tested above), this insn is really
2959 adjusting the frame pointer downward to compensate for
2960 the adjustment done before a nonlocal goto. */
2961 if (ep->from == FRAME_POINTER_REGNUM
2962 && ep->to == HARD_FRAME_POINTER_REGNUM)
2964 rtx base = SET_SRC (old_set);
2965 rtx base_insn = insn;
2968 while (base != ep->to_rtx)
2970 rtx prev_insn, prev_set;
2972 if (GET_CODE (base) == PLUS
2973 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2975 offset += INTVAL (XEXP (base, 1));
2976 base = XEXP (base, 0);
2978 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2979 && (prev_set = single_set (prev_insn)) != 0
2980 && rtx_equal_p (SET_DEST (prev_set), base))
2982 base = SET_SRC (prev_set);
2983 base_insn = prev_insn;
2989 if (base == ep->to_rtx)
2992 = plus_constant (ep->to_rtx, offset - ep->offset);
2994 new_body = old_body;
2997 new_body = copy_insn (old_body);
2998 if (REG_NOTES (insn))
2999 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3001 PATTERN (insn) = new_body;
3002 old_set = single_set (insn);
3004 /* First see if this insn remains valid when we
3005 make the change. If not, keep the INSN_CODE
3006 the same and let reload fit it up. */
3007 validate_change (insn, &SET_SRC (old_set), src, 1);
3008 validate_change (insn, &SET_DEST (old_set),
3010 if (! apply_change_group ())
3012 SET_SRC (old_set) = src;
3013 SET_DEST (old_set) = ep->to_rtx;
3022 /* In this case this insn isn't serving a useful purpose. We
3023 will delete it in reload_as_needed once we know that this
3024 elimination is, in fact, being done.
3026 If REPLACE isn't set, we can't delete this insn, but needn't
3027 process it since it won't be used unless something changes. */
3030 delete_dead_insn (insn);
3038 /* We allow one special case which happens to work on all machines we
3039 currently support: a single set with the source being a PLUS of an
3040 eliminable register and a constant. */
3042 && GET_CODE (SET_DEST (old_set)) == REG
3043 && GET_CODE (SET_SRC (old_set)) == PLUS
3044 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3045 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3046 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3048 rtx reg = XEXP (SET_SRC (old_set), 0);
3049 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3051 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3052 if (ep->from_rtx == reg && ep->can_eliminate)
3054 offset += ep->offset;
3059 /* We assume here that if we need a PARALLEL with
3060 CLOBBERs for this assignment, we can do with the
3061 MATCH_SCRATCHes that add_clobbers allocates.
3062 There's not much we can do if that doesn't work. */
3063 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3067 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3070 rtvec vec = rtvec_alloc (num_clobbers + 1);
3072 vec->elem[0] = PATTERN (insn);
3073 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3074 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3076 if (INSN_CODE (insn) < 0)
3081 new_body = old_body;
3084 new_body = copy_insn (old_body);
3085 if (REG_NOTES (insn))
3086 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3088 PATTERN (insn) = new_body;
3089 old_set = single_set (insn);
3091 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3092 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3095 /* This can't have an effect on elimination offsets, so skip right
3101 /* Determine the effects of this insn on elimination offsets. */
3102 elimination_effects (old_body, 0);
3104 /* Eliminate all eliminable registers occurring in operands that
3105 can be handled by reload. */
3106 extract_insn (insn);
3108 for (i = 0; i < recog_data.n_operands; i++)
3110 orig_operand[i] = recog_data.operand[i];
3111 substed_operand[i] = recog_data.operand[i];
3113 /* For an asm statement, every operand is eliminable. */
3114 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3116 /* Check for setting a register that we know about. */
3117 if (recog_data.operand_type[i] != OP_IN
3118 && GET_CODE (orig_operand[i]) == REG)
3120 /* If we are assigning to a register that can be eliminated, it
3121 must be as part of a PARALLEL, since the code above handles
3122 single SETs. We must indicate that we can no longer
3123 eliminate this reg. */
3124 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3126 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3127 ep->can_eliminate = 0;
3130 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3131 replace ? insn : NULL_RTX);
3132 if (substed_operand[i] != orig_operand[i])
3133 val = any_changes = 1;
3134 /* Terminate the search in check_eliminable_occurrences at
3136 *recog_data.operand_loc[i] = 0;
3138 /* If an output operand changed from a REG to a MEM and INSN is an
3139 insn, write a CLOBBER insn. */
3140 if (recog_data.operand_type[i] != OP_IN
3141 && GET_CODE (orig_operand[i]) == REG
3142 && GET_CODE (substed_operand[i]) == MEM
3144 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3149 for (i = 0; i < recog_data.n_dups; i++)
3150 *recog_data.dup_loc[i]
3151 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3153 /* If any eliminable remain, they aren't eliminable anymore. */
3154 check_eliminable_occurrences (old_body);
3156 /* Substitute the operands; the new values are in the substed_operand
3158 for (i = 0; i < recog_data.n_operands; i++)
3159 *recog_data.operand_loc[i] = substed_operand[i];
3160 for (i = 0; i < recog_data.n_dups; i++)
3161 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3163 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3164 re-recognize the insn. We do this in case we had a simple addition
3165 but now can do this as a load-address. This saves an insn in this
3167 If re-recognition fails, the old insn code number will still be used,
3168 and some register operands may have changed into PLUS expressions.
3169 These will be handled by find_reloads by loading them into a register
3174 /* If we aren't replacing things permanently and we changed something,
3175 make another copy to ensure that all the RTL is new. Otherwise
3176 things can go wrong if find_reload swaps commutative operands
3177 and one is inside RTL that has been copied while the other is not. */
3178 new_body = old_body;
3181 new_body = copy_insn (old_body);
3182 if (REG_NOTES (insn))
3183 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3185 PATTERN (insn) = new_body;
3187 /* If we had a move insn but now we don't, rerecognize it. This will
3188 cause spurious re-recognition if the old move had a PARALLEL since
3189 the new one still will, but we can't call single_set without
3190 having put NEW_BODY into the insn and the re-recognition won't
3191 hurt in this rare case. */
3192 /* ??? Why this huge if statement - why don't we just rerecognize the
3196 && ((GET_CODE (SET_SRC (old_set)) == REG
3197 && (GET_CODE (new_body) != SET
3198 || GET_CODE (SET_SRC (new_body)) != REG))
3199 /* If this was a load from or store to memory, compare
3200 the MEM in recog_data.operand to the one in the insn.
3201 If they are not equal, then rerecognize the insn. */
3203 && ((GET_CODE (SET_SRC (old_set)) == MEM
3204 && SET_SRC (old_set) != recog_data.operand[1])
3205 || (GET_CODE (SET_DEST (old_set)) == MEM
3206 && SET_DEST (old_set) != recog_data.operand[0])))
3207 /* If this was an add insn before, rerecognize. */
3208 || GET_CODE (SET_SRC (old_set)) == PLUS))
3210 int new_icode = recog (PATTERN (insn), insn, 0);
3212 INSN_CODE (insn) = icode;
3216 /* Restore the old body. If there were any changes to it, we made a copy
3217 of it while the changes were still in place, so we'll correctly return
3218 a modified insn below. */
3221 /* Restore the old body. */
3222 for (i = 0; i < recog_data.n_operands; i++)
3223 *recog_data.operand_loc[i] = orig_operand[i];
3224 for (i = 0; i < recog_data.n_dups; i++)
3225 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3228 /* Update all elimination pairs to reflect the status after the current
3229 insn. The changes we make were determined by the earlier call to
3230 elimination_effects.
3232 We also detect a cases where register elimination cannot be done,
3233 namely, if a register would be both changed and referenced outside a MEM
3234 in the resulting insn since such an insn is often undefined and, even if
3235 not, we cannot know what meaning will be given to it. Note that it is
3236 valid to have a register used in an address in an insn that changes it
3237 (presumably with a pre- or post-increment or decrement).
3239 If anything changes, return nonzero. */
3241 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3243 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3244 ep->can_eliminate = 0;
3246 ep->ref_outside_mem = 0;
3248 if (ep->previous_offset != ep->offset)
3253 /* If we changed something, perform elimination in REG_NOTES. This is
3254 needed even when REPLACE is zero because a REG_DEAD note might refer
3255 to a register that we eliminate and could cause a different number
3256 of spill registers to be needed in the final reload pass than in
3258 if (val && REG_NOTES (insn) != 0)
3259 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3264 /* Loop through all elimination pairs.
3265 Recalculate the number not at initial offset.
3267 Compute the maximum offset (minimum offset if the stack does not
3268 grow downward) for each elimination pair. */
3271 update_eliminable_offsets ()
3273 struct elim_table *ep;
3275 num_not_at_initial_offset = 0;
3276 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3278 ep->previous_offset = ep->offset;
3279 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3280 num_not_at_initial_offset++;
3284 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3285 replacement we currently believe is valid, mark it as not eliminable if X
3286 modifies DEST in any way other than by adding a constant integer to it.
3288 If DEST is the frame pointer, we do nothing because we assume that
3289 all assignments to the hard frame pointer are nonlocal gotos and are being
3290 done at a time when they are valid and do not disturb anything else.
3291 Some machines want to eliminate a fake argument pointer with either the
3292 frame or stack pointer. Assignments to the hard frame pointer must not
3293 prevent this elimination.
3295 Called via note_stores from reload before starting its passes to scan
3296 the insns of the function. */
3299 mark_not_eliminable (dest, x, data)
3302 void *data ATTRIBUTE_UNUSED;
3306 /* A SUBREG of a hard register here is just changing its mode. We should
3307 not see a SUBREG of an eliminable hard register, but check just in
3309 if (GET_CODE (dest) == SUBREG)
3310 dest = SUBREG_REG (dest);
3312 if (dest == hard_frame_pointer_rtx)
3315 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3316 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3317 && (GET_CODE (x) != SET
3318 || GET_CODE (SET_SRC (x)) != PLUS
3319 || XEXP (SET_SRC (x), 0) != dest
3320 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3322 reg_eliminate[i].can_eliminate_previous
3323 = reg_eliminate[i].can_eliminate = 0;
3328 /* Verify that the initial elimination offsets did not change since the
3329 last call to set_initial_elim_offsets. This is used to catch cases
3330 where something illegal happened during reload_as_needed that could
3331 cause incorrect code to be generated if we did not check for it. */
3334 verify_initial_elim_offsets ()
3338 #ifdef ELIMINABLE_REGS
3339 struct elim_table *ep;
3341 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3343 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3344 if (t != ep->initial_offset)
3348 INITIAL_FRAME_POINTER_OFFSET (t);
3349 if (t != reg_eliminate[0].initial_offset)
3354 /* Reset all offsets on eliminable registers to their initial values. */
3357 set_initial_elim_offsets ()
3359 struct elim_table *ep = reg_eliminate;
3361 #ifdef ELIMINABLE_REGS
3362 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3364 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3365 ep->previous_offset = ep->offset = ep->initial_offset;
3368 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3369 ep->previous_offset = ep->offset = ep->initial_offset;
3372 num_not_at_initial_offset = 0;
3375 /* Initialize the known label offsets.
3376 Set a known offset for each forced label to be at the initial offset
3377 of each elimination. We do this because we assume that all
3378 computed jumps occur from a location where each elimination is
3379 at its initial offset.
3380 For all other labels, show that we don't know the offsets. */
3383 set_initial_label_offsets ()
3386 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3388 for (x = forced_labels; x; x = XEXP (x, 1))
3390 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3393 /* Set all elimination offsets to the known values for the code label given
3397 set_offsets_for_label (insn)
3401 int label_nr = CODE_LABEL_NUMBER (insn);
3402 struct elim_table *ep;
3404 num_not_at_initial_offset = 0;
3405 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3407 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3408 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3409 num_not_at_initial_offset++;
3413 /* See if anything that happened changes which eliminations are valid.
3414 For example, on the Sparc, whether or not the frame pointer can
3415 be eliminated can depend on what registers have been used. We need
3416 not check some conditions again (such as flag_omit_frame_pointer)
3417 since they can't have changed. */
3420 update_eliminables (pset)
3423 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3424 int previous_frame_pointer_needed = frame_pointer_needed;
3426 struct elim_table *ep;
3428 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3429 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3430 #ifdef ELIMINABLE_REGS
3431 || ! CAN_ELIMINATE (ep->from, ep->to)
3434 ep->can_eliminate = 0;
3436 /* Look for the case where we have discovered that we can't replace
3437 register A with register B and that means that we will now be
3438 trying to replace register A with register C. This means we can
3439 no longer replace register C with register B and we need to disable
3440 such an elimination, if it exists. This occurs often with A == ap,
3441 B == sp, and C == fp. */
3443 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3445 struct elim_table *op;
3448 if (! ep->can_eliminate && ep->can_eliminate_previous)
3450 /* Find the current elimination for ep->from, if there is a
3452 for (op = reg_eliminate;
3453 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3454 if (op->from == ep->from && op->can_eliminate)
3460 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3462 for (op = reg_eliminate;
3463 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3464 if (op->from == new_to && op->to == ep->to)
3465 op->can_eliminate = 0;
3469 /* See if any registers that we thought we could eliminate the previous
3470 time are no longer eliminable. If so, something has changed and we
3471 must spill the register. Also, recompute the number of eliminable
3472 registers and see if the frame pointer is needed; it is if there is
3473 no elimination of the frame pointer that we can perform. */
3475 frame_pointer_needed = 1;
3476 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3478 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3479 && ep->to != HARD_FRAME_POINTER_REGNUM)
3480 frame_pointer_needed = 0;
3482 if (! ep->can_eliminate && ep->can_eliminate_previous)
3484 ep->can_eliminate_previous = 0;
3485 SET_HARD_REG_BIT (*pset, ep->from);
3490 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3491 /* If we didn't need a frame pointer last time, but we do now, spill
3492 the hard frame pointer. */
3493 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3494 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3498 /* Initialize the table of registers to eliminate. */
3503 struct elim_table *ep;
3504 #ifdef ELIMINABLE_REGS
3505 const struct elim_table_1 *ep1;
3509 reg_eliminate = (struct elim_table *)
3510 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3512 /* Does this function require a frame pointer? */
3514 frame_pointer_needed = (! flag_omit_frame_pointer
3515 #ifdef EXIT_IGNORE_STACK
3516 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3517 and restore sp for alloca. So we can't eliminate
3518 the frame pointer in that case. At some point,
3519 we should improve this by emitting the
3520 sp-adjusting insns for this case. */
3521 || (current_function_calls_alloca
3522 && EXIT_IGNORE_STACK)
3524 || FRAME_POINTER_REQUIRED);
3528 #ifdef ELIMINABLE_REGS
3529 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3530 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3532 ep->from = ep1->from;
3534 ep->can_eliminate = ep->can_eliminate_previous
3535 = (CAN_ELIMINATE (ep->from, ep->to)
3536 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3539 reg_eliminate[0].from = reg_eliminate_1[0].from;
3540 reg_eliminate[0].to = reg_eliminate_1[0].to;
3541 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3542 = ! frame_pointer_needed;
3545 /* Count the number of eliminable registers and build the FROM and TO
3546 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3547 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3548 We depend on this. */
3549 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3551 num_eliminable += ep->can_eliminate;
3552 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3553 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3557 /* Kick all pseudos out of hard register REGNO.
3559 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3560 because we found we can't eliminate some register. In the case, no pseudos
3561 are allowed to be in the register, even if they are only in a block that
3562 doesn't require spill registers, unlike the case when we are spilling this
3563 hard reg to produce another spill register.
3565 Return nonzero if any pseudos needed to be kicked out. */
3568 spill_hard_reg (regno, cant_eliminate)
3576 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3577 regs_ever_live[regno] = 1;
3580 /* Spill every pseudo reg that was allocated to this reg
3581 or to something that overlaps this reg. */
3583 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3584 if (reg_renumber[i] >= 0
3585 && (unsigned int) reg_renumber[i] <= regno
3586 && ((unsigned int) reg_renumber[i]
3587 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3588 PSEUDO_REGNO_MODE (i))
3590 SET_REGNO_REG_SET (&spilled_pseudos, i);
3593 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3594 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3597 ior_hard_reg_set (set1, set2)
3598 HARD_REG_SET *set1, *set2;
3600 IOR_HARD_REG_SET (*set1, *set2);
3603 /* After find_reload_regs has been run for all insn that need reloads,
3604 and/or spill_hard_regs was called, this function is used to actually
3605 spill pseudo registers and try to reallocate them. It also sets up the
3606 spill_regs array for use by choose_reload_regs. */
3609 finish_spills (global)
3612 struct insn_chain *chain;
3613 int something_changed = 0;
3616 /* Build the spill_regs array for the function. */
3617 /* If there are some registers still to eliminate and one of the spill regs
3618 wasn't ever used before, additional stack space may have to be
3619 allocated to store this register. Thus, we may have changed the offset
3620 between the stack and frame pointers, so mark that something has changed.
3622 One might think that we need only set VAL to 1 if this is a call-used
3623 register. However, the set of registers that must be saved by the
3624 prologue is not identical to the call-used set. For example, the
3625 register used by the call insn for the return PC is a call-used register,
3626 but must be saved by the prologue. */
3629 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3630 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3632 spill_reg_order[i] = n_spills;
3633 spill_regs[n_spills++] = i;
3634 if (num_eliminable && ! regs_ever_live[i])
3635 something_changed = 1;
3636 regs_ever_live[i] = 1;
3639 spill_reg_order[i] = -1;
3641 EXECUTE_IF_SET_IN_REG_SET
3642 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3644 /* Record the current hard register the pseudo is allocated to in
3645 pseudo_previous_regs so we avoid reallocating it to the same
3646 hard reg in a later pass. */
3647 if (reg_renumber[i] < 0)
3650 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3651 /* Mark it as no longer having a hard register home. */
3652 reg_renumber[i] = -1;
3653 /* We will need to scan everything again. */
3654 something_changed = 1;
3657 /* Retry global register allocation if possible. */
3660 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3661 /* For every insn that needs reloads, set the registers used as spill
3662 regs in pseudo_forbidden_regs for every pseudo live across the
3664 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3666 EXECUTE_IF_SET_IN_REG_SET
3667 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3669 ior_hard_reg_set (pseudo_forbidden_regs + i,
3670 &chain->used_spill_regs);
3672 EXECUTE_IF_SET_IN_REG_SET
3673 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3675 ior_hard_reg_set (pseudo_forbidden_regs + i,
3676 &chain->used_spill_regs);
3680 /* Retry allocating the spilled pseudos. For each reg, merge the
3681 various reg sets that indicate which hard regs can't be used,
3682 and call retry_global_alloc.
3683 We change spill_pseudos here to only contain pseudos that did not
3684 get a new hard register. */
3685 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3686 if (reg_old_renumber[i] != reg_renumber[i])
3688 HARD_REG_SET forbidden;
3689 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3690 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3691 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3692 retry_global_alloc (i, forbidden);
3693 if (reg_renumber[i] >= 0)
3694 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3698 /* Fix up the register information in the insn chain.
3699 This involves deleting those of the spilled pseudos which did not get
3700 a new hard register home from the live_{before,after} sets. */
3701 for (chain = reload_insn_chain; chain; chain = chain->next)
3703 HARD_REG_SET used_by_pseudos;
3704 HARD_REG_SET used_by_pseudos2;
3706 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3707 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3709 /* Mark any unallocated hard regs as available for spills. That
3710 makes inheritance work somewhat better. */
3711 if (chain->need_reload)
3713 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3714 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3715 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3717 /* Save the old value for the sanity test below. */
3718 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3720 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3721 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3722 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3723 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3725 /* Make sure we only enlarge the set. */
3726 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3732 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3733 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3735 int regno = reg_renumber[i];
3736 if (reg_old_renumber[i] == regno)
3739 alter_reg (i, reg_old_renumber[i]);
3740 reg_old_renumber[i] = regno;
3744 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3746 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3747 i, reg_renumber[i]);
3751 return something_changed;
3754 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3755 Also mark any hard registers used to store user variables as
3756 forbidden from being used for spill registers. */
3759 scan_paradoxical_subregs (x)
3764 enum rtx_code code = GET_CODE (x);
3770 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3771 && REG_USERVAR_P (x))
3772 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3781 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3789 if (GET_CODE (SUBREG_REG (x)) == REG
3790 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3791 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3792 = GET_MODE_SIZE (GET_MODE (x));
3799 fmt = GET_RTX_FORMAT (code);
3800 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3803 scan_paradoxical_subregs (XEXP (x, i));
3804 else if (fmt[i] == 'E')
3807 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3808 scan_paradoxical_subregs (XVECEXP (x, i, j));
3813 /* Reload pseudo-registers into hard regs around each insn as needed.
3814 Additional register load insns are output before the insn that needs it
3815 and perhaps store insns after insns that modify the reloaded pseudo reg.
3817 reg_last_reload_reg and reg_reloaded_contents keep track of
3818 which registers are already available in reload registers.
3819 We update these for the reloads that we perform,
3820 as the insns are scanned. */
3823 reload_as_needed (live_known)
3826 struct insn_chain *chain;
3827 #if defined (AUTO_INC_DEC)
3832 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3833 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3834 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3835 reg_has_output_reload = (char *) xmalloc (max_regno);
3836 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3838 set_initial_elim_offsets ();
3840 for (chain = reload_insn_chain; chain; chain = chain->next)
3843 rtx insn = chain->insn;
3844 rtx old_next = NEXT_INSN (insn);
3846 /* If we pass a label, copy the offsets from the label information
3847 into the current offsets of each elimination. */
3848 if (GET_CODE (insn) == CODE_LABEL)
3849 set_offsets_for_label (insn);
3851 else if (INSN_P (insn))
3853 rtx oldpat = copy_rtx (PATTERN (insn));
3855 /* If this is a USE and CLOBBER of a MEM, ensure that any
3856 references to eliminable registers have been removed. */
3858 if ((GET_CODE (PATTERN (insn)) == USE
3859 || GET_CODE (PATTERN (insn)) == CLOBBER)
3860 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3861 XEXP (XEXP (PATTERN (insn), 0), 0)
3862 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3863 GET_MODE (XEXP (PATTERN (insn), 0)),
3866 /* If we need to do register elimination processing, do so.
3867 This might delete the insn, in which case we are done. */
3868 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3870 eliminate_regs_in_insn (insn, 1);
3871 if (GET_CODE (insn) == NOTE)
3873 update_eliminable_offsets ();
3878 /* If need_elim is nonzero but need_reload is zero, one might think
3879 that we could simply set n_reloads to 0. However, find_reloads
3880 could have done some manipulation of the insn (such as swapping
3881 commutative operands), and these manipulations are lost during
3882 the first pass for every insn that needs register elimination.
3883 So the actions of find_reloads must be redone here. */
3885 if (! chain->need_elim && ! chain->need_reload
3886 && ! chain->need_operand_change)
3888 /* First find the pseudo regs that must be reloaded for this insn.
3889 This info is returned in the tables reload_... (see reload.h).
3890 Also modify the body of INSN by substituting RELOAD
3891 rtx's for those pseudo regs. */
3894 memset (reg_has_output_reload, 0, max_regno);
3895 CLEAR_HARD_REG_SET (reg_is_output_reload);
3897 find_reloads (insn, 1, spill_indirect_levels, live_known,
3903 rtx next = NEXT_INSN (insn);
3906 prev = PREV_INSN (insn);
3908 /* Now compute which reload regs to reload them into. Perhaps
3909 reusing reload regs from previous insns, or else output
3910 load insns to reload them. Maybe output store insns too.
3911 Record the choices of reload reg in reload_reg_rtx. */
3912 choose_reload_regs (chain);
3914 /* Merge any reloads that we didn't combine for fear of
3915 increasing the number of spill registers needed but now
3916 discover can be safely merged. */
3917 if (SMALL_REGISTER_CLASSES)
3918 merge_assigned_reloads (insn);
3920 /* Generate the insns to reload operands into or out of
3921 their reload regs. */
3922 emit_reload_insns (chain);
3924 /* Substitute the chosen reload regs from reload_reg_rtx
3925 into the insn's body (or perhaps into the bodies of other
3926 load and store insn that we just made for reloading
3927 and that we moved the structure into). */
3928 subst_reloads (insn);
3930 /* If this was an ASM, make sure that all the reload insns
3931 we have generated are valid. If not, give an error
3934 if (asm_noperands (PATTERN (insn)) >= 0)
3935 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3936 if (p != insn && INSN_P (p)
3937 && (recog_memoized (p) < 0
3938 || (extract_insn (p), ! constrain_operands (1))))
3940 error_for_asm (insn,
3941 "`asm' operand requires impossible reload");
3946 if (num_eliminable && chain->need_elim)
3947 update_eliminable_offsets ();
3949 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3950 is no longer validly lying around to save a future reload.
3951 Note that this does not detect pseudos that were reloaded
3952 for this insn in order to be stored in
3953 (obeying register constraints). That is correct; such reload
3954 registers ARE still valid. */
3955 note_stores (oldpat, forget_old_reloads_1, NULL);
3957 /* There may have been CLOBBER insns placed after INSN. So scan
3958 between INSN and NEXT and use them to forget old reloads. */
3959 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3960 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3961 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3964 /* Likewise for regs altered by auto-increment in this insn.
3965 REG_INC notes have been changed by reloading:
3966 find_reloads_address_1 records substitutions for them,
3967 which have been performed by subst_reloads above. */
3968 for (i = n_reloads - 1; i >= 0; i--)
3970 rtx in_reg = rld[i].in_reg;
3973 enum rtx_code code = GET_CODE (in_reg);
3974 /* PRE_INC / PRE_DEC will have the reload register ending up
3975 with the same value as the stack slot, but that doesn't
3976 hold true for POST_INC / POST_DEC. Either we have to
3977 convert the memory access to a true POST_INC / POST_DEC,
3978 or we can't use the reload register for inheritance. */
3979 if ((code == POST_INC || code == POST_DEC)
3980 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3981 REGNO (rld[i].reg_rtx))
3982 /* Make sure it is the inc/dec pseudo, and not
3983 some other (e.g. output operand) pseudo. */
3984 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3985 == REGNO (XEXP (in_reg, 0))))
3988 rtx reload_reg = rld[i].reg_rtx;
3989 enum machine_mode mode = GET_MODE (reload_reg);
3993 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3995 /* We really want to ignore REG_INC notes here, so
3996 use PATTERN (p) as argument to reg_set_p . */
3997 if (reg_set_p (reload_reg, PATTERN (p)))
3999 n = count_occurrences (PATTERN (p), reload_reg, 0);
4004 n = validate_replace_rtx (reload_reg,
4005 gen_rtx (code, mode,
4009 /* We must also verify that the constraints
4010 are met after the replacement. */
4013 n = constrain_operands (1);
4017 /* If the constraints were not met, then
4018 undo the replacement. */
4021 validate_replace_rtx (gen_rtx (code, mode,
4033 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4035 /* Mark this as having an output reload so that the
4036 REG_INC processing code below won't invalidate
4037 the reload for inheritance. */
4038 SET_HARD_REG_BIT (reg_is_output_reload,
4039 REGNO (reload_reg));
4040 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4043 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4046 else if ((code == PRE_INC || code == PRE_DEC)
4047 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4048 REGNO (rld[i].reg_rtx))
4049 /* Make sure it is the inc/dec pseudo, and not
4050 some other (e.g. output operand) pseudo. */
4051 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4052 == REGNO (XEXP (in_reg, 0))))
4054 SET_HARD_REG_BIT (reg_is_output_reload,
4055 REGNO (rld[i].reg_rtx));
4056 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4060 /* If a pseudo that got a hard register is auto-incremented,
4061 we must purge records of copying it into pseudos without
4063 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4064 if (REG_NOTE_KIND (x) == REG_INC)
4066 /* See if this pseudo reg was reloaded in this insn.
4067 If so, its last-reload info is still valid
4068 because it is based on this insn's reload. */
4069 for (i = 0; i < n_reloads; i++)
4070 if (rld[i].out == XEXP (x, 0))
4074 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4078 /* A reload reg's contents are unknown after a label. */
4079 if (GET_CODE (insn) == CODE_LABEL)
4080 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4082 /* Don't assume a reload reg is still good after a call insn
4083 if it is a call-used reg. */
4084 else if (GET_CODE (insn) == CALL_INSN)
4085 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4089 free (reg_last_reload_reg);
4090 free (reg_has_output_reload);
4093 /* Discard all record of any value reloaded from X,
4094 or reloaded in X from someplace else;
4095 unless X is an output reload reg of the current insn.
4097 X may be a hard reg (the reload reg)
4098 or it may be a pseudo reg that was reloaded from. */
4101 forget_old_reloads_1 (x, ignored, data)
4103 rtx ignored ATTRIBUTE_UNUSED;
4104 void *data ATTRIBUTE_UNUSED;
4109 /* note_stores does give us subregs of hard regs,
4110 subreg_regno_offset will abort if it is not a hard reg. */
4111 while (GET_CODE (x) == SUBREG)
4113 /* We ignore the subreg offset when calculating the regno,
4114 because we are using the entire underlying hard register
4119 if (GET_CODE (x) != REG)
4124 if (regno >= FIRST_PSEUDO_REGISTER)
4130 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4131 /* Storing into a spilled-reg invalidates its contents.
4132 This can happen if a block-local pseudo is allocated to that reg
4133 and it wasn't spilled because this block's total need is 0.
4134 Then some insn might have an optional reload and use this reg. */
4135 for (i = 0; i < nr; i++)
4136 /* But don't do this if the reg actually serves as an output
4137 reload reg in the current instruction. */
4139 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4141 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4142 spill_reg_store[regno + i] = 0;
4146 /* Since value of X has changed,
4147 forget any value previously copied from it. */
4150 /* But don't forget a copy if this is the output reload
4151 that establishes the copy's validity. */
4152 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4153 reg_last_reload_reg[regno + nr] = 0;
4156 /* The following HARD_REG_SETs indicate when each hard register is
4157 used for a reload of various parts of the current insn. */
4159 /* If reg is unavailable for all reloads. */
4160 static HARD_REG_SET reload_reg_unavailable;
4161 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4162 static HARD_REG_SET reload_reg_used;
4163 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4164 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4165 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4166 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4167 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4168 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4169 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4170 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4171 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4172 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4173 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4174 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4175 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4176 static HARD_REG_SET reload_reg_used_in_op_addr;
4177 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4178 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4179 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4180 static HARD_REG_SET reload_reg_used_in_insn;
4181 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4182 static HARD_REG_SET reload_reg_used_in_other_addr;
4184 /* If reg is in use as a reload reg for any sort of reload. */
4185 static HARD_REG_SET reload_reg_used_at_all;
4187 /* If reg is use as an inherited reload. We just mark the first register
4189 static HARD_REG_SET reload_reg_used_for_inherit;
4191 /* Records which hard regs are used in any way, either as explicit use or
4192 by being allocated to a pseudo during any point of the current insn. */
4193 static HARD_REG_SET reg_used_in_insn;
4195 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4196 TYPE. MODE is used to indicate how many consecutive regs are
4200 mark_reload_reg_in_use (regno, opnum, type, mode)
4203 enum reload_type type;
4204 enum machine_mode mode;
4206 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4209 for (i = regno; i < nregs + regno; i++)
4214 SET_HARD_REG_BIT (reload_reg_used, i);
4217 case RELOAD_FOR_INPUT_ADDRESS:
4218 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4221 case RELOAD_FOR_INPADDR_ADDRESS:
4222 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4225 case RELOAD_FOR_OUTPUT_ADDRESS:
4226 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4229 case RELOAD_FOR_OUTADDR_ADDRESS:
4230 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4233 case RELOAD_FOR_OPERAND_ADDRESS:
4234 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4237 case RELOAD_FOR_OPADDR_ADDR:
4238 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4241 case RELOAD_FOR_OTHER_ADDRESS:
4242 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4245 case RELOAD_FOR_INPUT:
4246 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4249 case RELOAD_FOR_OUTPUT:
4250 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4253 case RELOAD_FOR_INSN:
4254 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4258 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4262 /* Similarly, but show REGNO is no longer in use for a reload. */
4265 clear_reload_reg_in_use (regno, opnum, type, mode)
4268 enum reload_type type;
4269 enum machine_mode mode;
4271 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4272 unsigned int start_regno, end_regno, r;
4274 /* A complication is that for some reload types, inheritance might
4275 allow multiple reloads of the same types to share a reload register.
4276 We set check_opnum if we have to check only reloads with the same
4277 operand number, and check_any if we have to check all reloads. */
4278 int check_opnum = 0;
4280 HARD_REG_SET *used_in_set;
4285 used_in_set = &reload_reg_used;
4288 case RELOAD_FOR_INPUT_ADDRESS:
4289 used_in_set = &reload_reg_used_in_input_addr[opnum];
4292 case RELOAD_FOR_INPADDR_ADDRESS:
4294 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4297 case RELOAD_FOR_OUTPUT_ADDRESS:
4298 used_in_set = &reload_reg_used_in_output_addr[opnum];
4301 case RELOAD_FOR_OUTADDR_ADDRESS:
4303 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4306 case RELOAD_FOR_OPERAND_ADDRESS:
4307 used_in_set = &reload_reg_used_in_op_addr;
4310 case RELOAD_FOR_OPADDR_ADDR:
4312 used_in_set = &reload_reg_used_in_op_addr_reload;
4315 case RELOAD_FOR_OTHER_ADDRESS:
4316 used_in_set = &reload_reg_used_in_other_addr;
4320 case RELOAD_FOR_INPUT:
4321 used_in_set = &reload_reg_used_in_input[opnum];
4324 case RELOAD_FOR_OUTPUT:
4325 used_in_set = &reload_reg_used_in_output[opnum];
4328 case RELOAD_FOR_INSN:
4329 used_in_set = &reload_reg_used_in_insn;
4334 /* We resolve conflicts with remaining reloads of the same type by
4335 excluding the intervals of reload registers by them from the
4336 interval of freed reload registers. Since we only keep track of
4337 one set of interval bounds, we might have to exclude somewhat
4338 more than what would be necessary if we used a HARD_REG_SET here.
4339 But this should only happen very infrequently, so there should
4340 be no reason to worry about it. */
4342 start_regno = regno;
4343 end_regno = regno + nregs;
4344 if (check_opnum || check_any)
4346 for (i = n_reloads - 1; i >= 0; i--)
4348 if (rld[i].when_needed == type
4349 && (check_any || rld[i].opnum == opnum)
4352 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4353 unsigned int conflict_end
4355 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4357 /* If there is an overlap with the first to-be-freed register,
4358 adjust the interval start. */
4359 if (conflict_start <= start_regno && conflict_end > start_regno)
4360 start_regno = conflict_end;
4361 /* Otherwise, if there is a conflict with one of the other
4362 to-be-freed registers, adjust the interval end. */
4363 if (conflict_start > start_regno && conflict_start < end_regno)
4364 end_regno = conflict_start;
4369 for (r = start_regno; r < end_regno; r++)
4370 CLEAR_HARD_REG_BIT (*used_in_set, r);
4373 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4374 specified by OPNUM and TYPE. */
4377 reload_reg_free_p (regno, opnum, type)
4380 enum reload_type type;
4384 /* In use for a RELOAD_OTHER means it's not available for anything. */
4385 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4386 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4392 /* In use for anything means we can't use it for RELOAD_OTHER. */
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4394 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4395 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4398 for (i = 0; i < reload_n_operands; i++)
4399 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4400 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4401 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4402 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4403 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4404 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4409 case RELOAD_FOR_INPUT:
4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4411 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4414 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4417 /* If it is used for some other input, can't use it. */
4418 for (i = 0; i < reload_n_operands; i++)
4419 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4422 /* If it is used in a later operand's address, can't use it. */
4423 for (i = opnum + 1; i < reload_n_operands; i++)
4424 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4425 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4430 case RELOAD_FOR_INPUT_ADDRESS:
4431 /* Can't use a register if it is used for an input address for this
4432 operand or used as an input in an earlier one. */
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4434 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4437 for (i = 0; i < opnum; i++)
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4443 case RELOAD_FOR_INPADDR_ADDRESS:
4444 /* Can't use a register if it is used for an input address
4445 for this operand or used as an input in an earlier
4447 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4450 for (i = 0; i < opnum; i++)
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4456 case RELOAD_FOR_OUTPUT_ADDRESS:
4457 /* Can't use a register if it is used for an output address for this
4458 operand or used as an output in this or a later operand. Note
4459 that multiple output operands are emitted in reverse order, so
4460 the conflicting ones are those with lower indices. */
4461 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4464 for (i = 0; i <= opnum; i++)
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4470 case RELOAD_FOR_OUTADDR_ADDRESS:
4471 /* Can't use a register if it is used for an output address
4472 for this operand or used as an output in this or a
4473 later operand. Note that multiple output operands are
4474 emitted in reverse order, so the conflicting ones are
4475 those with lower indices. */
4476 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4479 for (i = 0; i <= opnum; i++)
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4485 case RELOAD_FOR_OPERAND_ADDRESS:
4486 for (i = 0; i < reload_n_operands; i++)
4487 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4490 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4491 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4493 case RELOAD_FOR_OPADDR_ADDR:
4494 for (i = 0; i < reload_n_operands; i++)
4495 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4498 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4500 case RELOAD_FOR_OUTPUT:
4501 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4502 outputs, or an operand address for this or an earlier output.
4503 Note that multiple output operands are emitted in reverse order,
4504 so the conflicting ones are those with higher indices. */
4505 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4508 for (i = 0; i < reload_n_operands; i++)
4509 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4512 for (i = opnum; i < reload_n_operands; i++)
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4519 case RELOAD_FOR_INSN:
4520 for (i = 0; i < reload_n_operands; i++)
4521 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4522 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4525 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4526 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4528 case RELOAD_FOR_OTHER_ADDRESS:
4529 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4534 /* Return 1 if the value in reload reg REGNO, as used by a reload
4535 needed for the part of the insn specified by OPNUM and TYPE,
4536 is still available in REGNO at the end of the insn.
4538 We can assume that the reload reg was already tested for availability
4539 at the time it is needed, and we should not check this again,
4540 in case the reg has already been marked in use. */
4543 reload_reg_reaches_end_p (regno, opnum, type)
4546 enum reload_type type;
4553 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4554 its value must reach the end. */
4557 /* If this use is for part of the insn,
4558 its value reaches if no subsequent part uses the same register.
4559 Just like the above function, don't try to do this with lots
4562 case RELOAD_FOR_OTHER_ADDRESS:
4563 /* Here we check for everything else, since these don't conflict
4564 with anything else and everything comes later. */
4566 for (i = 0; i < reload_n_operands; i++)
4567 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4568 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4569 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4575 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4576 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4577 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4579 case RELOAD_FOR_INPUT_ADDRESS:
4580 case RELOAD_FOR_INPADDR_ADDRESS:
4581 /* Similar, except that we check only for this and subsequent inputs
4582 and the address of only subsequent inputs and we do not need
4583 to check for RELOAD_OTHER objects since they are known not to
4586 for (i = opnum; i < reload_n_operands; i++)
4587 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4590 for (i = opnum + 1; i < reload_n_operands; i++)
4591 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4592 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4595 for (i = 0; i < reload_n_operands; i++)
4596 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4597 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4598 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4601 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4604 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4605 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4606 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4608 case RELOAD_FOR_INPUT:
4609 /* Similar to input address, except we start at the next operand for
4610 both input and input address and we do not check for
4611 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4614 for (i = opnum + 1; i < reload_n_operands; i++)
4615 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4616 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4617 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4620 /* ... fall through ... */
4622 case RELOAD_FOR_OPERAND_ADDRESS:
4623 /* Check outputs and their addresses. */
4625 for (i = 0; i < reload_n_operands; i++)
4626 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4627 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4628 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4631 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4633 case RELOAD_FOR_OPADDR_ADDR:
4634 for (i = 0; i < reload_n_operands; i++)
4635 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4636 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4637 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4640 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4641 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4642 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4644 case RELOAD_FOR_INSN:
4645 /* These conflict with other outputs with RELOAD_OTHER. So
4646 we need only check for output addresses. */
4648 opnum = reload_n_operands;
4650 /* ... fall through ... */
4652 case RELOAD_FOR_OUTPUT:
4653 case RELOAD_FOR_OUTPUT_ADDRESS:
4654 case RELOAD_FOR_OUTADDR_ADDRESS:
4655 /* We already know these can't conflict with a later output. So the
4656 only thing to check are later output addresses.
4657 Note that multiple output operands are emitted in reverse order,
4658 so the conflicting ones are those with lower indices. */
4659 for (i = 0; i < opnum; i++)
4660 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4661 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4670 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4673 This function uses the same algorithm as reload_reg_free_p above. */
4676 reloads_conflict (r1, r2)
4679 enum reload_type r1_type = rld[r1].when_needed;
4680 enum reload_type r2_type = rld[r2].when_needed;
4681 int r1_opnum = rld[r1].opnum;
4682 int r2_opnum = rld[r2].opnum;
4684 /* RELOAD_OTHER conflicts with everything. */
4685 if (r2_type == RELOAD_OTHER)
4688 /* Otherwise, check conflicts differently for each type. */
4692 case RELOAD_FOR_INPUT:
4693 return (r2_type == RELOAD_FOR_INSN
4694 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4695 || r2_type == RELOAD_FOR_OPADDR_ADDR
4696 || r2_type == RELOAD_FOR_INPUT
4697 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4698 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4699 && r2_opnum > r1_opnum));
4701 case RELOAD_FOR_INPUT_ADDRESS:
4702 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4703 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4705 case RELOAD_FOR_INPADDR_ADDRESS:
4706 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4707 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4709 case RELOAD_FOR_OUTPUT_ADDRESS:
4710 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4711 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4713 case RELOAD_FOR_OUTADDR_ADDRESS:
4714 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4715 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4717 case RELOAD_FOR_OPERAND_ADDRESS:
4718 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4719 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4721 case RELOAD_FOR_OPADDR_ADDR:
4722 return (r2_type == RELOAD_FOR_INPUT
4723 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4725 case RELOAD_FOR_OUTPUT:
4726 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4727 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4728 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4729 && r2_opnum >= r1_opnum));
4731 case RELOAD_FOR_INSN:
4732 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4733 || r2_type == RELOAD_FOR_INSN
4734 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4736 case RELOAD_FOR_OTHER_ADDRESS:
4737 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4747 /* Indexed by reload number, 1 if incoming value
4748 inherited from previous insns. */
4749 char reload_inherited[MAX_RELOADS];
4751 /* For an inherited reload, this is the insn the reload was inherited from,
4752 if we know it. Otherwise, this is 0. */
4753 rtx reload_inheritance_insn[MAX_RELOADS];
4755 /* If non-zero, this is a place to get the value of the reload,
4756 rather than using reload_in. */
4757 rtx reload_override_in[MAX_RELOADS];
4759 /* For each reload, the hard register number of the register used,
4760 or -1 if we did not need a register for this reload. */
4761 int reload_spill_index[MAX_RELOADS];
4763 /* Subroutine of free_for_value_p, used to check a single register.
4764 START_REGNO is the starting regno of the full reload register
4765 (possibly comprising multiple hard registers) that we are considering. */
4768 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4769 reloadnum, ignore_address_reloads)
4770 int start_regno, regno;
4772 enum reload_type type;
4775 int ignore_address_reloads;
4778 /* Set if we see an input reload that must not share its reload register
4779 with any new earlyclobber, but might otherwise share the reload
4780 register with an output or input-output reload. */
4781 int check_earlyclobber = 0;
4785 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4788 if (out == const0_rtx)
4794 /* We use some pseudo 'time' value to check if the lifetimes of the
4795 new register use would overlap with the one of a previous reload
4796 that is not read-only or uses a different value.
4797 The 'time' used doesn't have to be linear in any shape or form, just
4799 Some reload types use different 'buckets' for each operand.
4800 So there are MAX_RECOG_OPERANDS different time values for each
4802 We compute TIME1 as the time when the register for the prospective
4803 new reload ceases to be live, and TIME2 for each existing
4804 reload as the time when that the reload register of that reload
4806 Where there is little to be gained by exact lifetime calculations,
4807 we just make conservative assumptions, i.e. a longer lifetime;
4808 this is done in the 'default:' cases. */
4811 case RELOAD_FOR_OTHER_ADDRESS:
4812 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4813 time1 = copy ? 0 : 1;
4816 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4818 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4819 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4820 respectively, to the time values for these, we get distinct time
4821 values. To get distinct time values for each operand, we have to
4822 multiply opnum by at least three. We round that up to four because
4823 multiply by four is often cheaper. */
4824 case RELOAD_FOR_INPADDR_ADDRESS:
4825 time1 = opnum * 4 + 2;
4827 case RELOAD_FOR_INPUT_ADDRESS:
4828 time1 = opnum * 4 + 3;
4830 case RELOAD_FOR_INPUT:
4831 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4832 executes (inclusive). */
4833 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4835 case RELOAD_FOR_OPADDR_ADDR:
4837 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4838 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4840 case RELOAD_FOR_OPERAND_ADDRESS:
4841 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4843 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4845 case RELOAD_FOR_OUTADDR_ADDRESS:
4846 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4848 case RELOAD_FOR_OUTPUT_ADDRESS:
4849 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4852 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4855 for (i = 0; i < n_reloads; i++)
4857 rtx reg = rld[i].reg_rtx;
4858 if (reg && GET_CODE (reg) == REG
4859 && ((unsigned) regno - true_regnum (reg)
4860 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4863 rtx other_input = rld[i].in;
4865 /* If the other reload loads the same input value, that
4866 will not cause a conflict only if it's loading it into
4867 the same register. */
4868 if (true_regnum (reg) != start_regno)
4869 other_input = NULL_RTX;
4870 if (! other_input || ! rtx_equal_p (other_input, value)
4871 || rld[i].out || out)
4874 switch (rld[i].when_needed)
4876 case RELOAD_FOR_OTHER_ADDRESS:
4879 case RELOAD_FOR_INPADDR_ADDRESS:
4880 /* find_reloads makes sure that a
4881 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4882 by at most one - the first -
4883 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4884 address reload is inherited, the address address reload
4885 goes away, so we can ignore this conflict. */
4886 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4887 && ignore_address_reloads
4888 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4889 Then the address address is still needed to store
4890 back the new address. */
4891 && ! rld[reloadnum].out)
4893 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4894 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4896 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4897 && ignore_address_reloads
4898 /* Unless we are reloading an auto_inc expression. */
4899 && ! rld[reloadnum].out)
4901 time2 = rld[i].opnum * 4 + 2;
4903 case RELOAD_FOR_INPUT_ADDRESS:
4904 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4905 && ignore_address_reloads
4906 && ! rld[reloadnum].out)
4908 time2 = rld[i].opnum * 4 + 3;
4910 case RELOAD_FOR_INPUT:
4911 time2 = rld[i].opnum * 4 + 4;
4912 check_earlyclobber = 1;
4914 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4915 == MAX_RECOG_OPERAND * 4 */
4916 case RELOAD_FOR_OPADDR_ADDR:
4917 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4918 && ignore_address_reloads
4919 && ! rld[reloadnum].out)
4921 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4923 case RELOAD_FOR_OPERAND_ADDRESS:
4924 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4925 check_earlyclobber = 1;
4927 case RELOAD_FOR_INSN:
4928 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4930 case RELOAD_FOR_OUTPUT:
4931 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4932 instruction is executed. */
4933 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4935 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4936 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4938 case RELOAD_FOR_OUTADDR_ADDRESS:
4939 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4940 && ignore_address_reloads
4941 && ! rld[reloadnum].out)
4943 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4945 case RELOAD_FOR_OUTPUT_ADDRESS:
4946 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4949 /* If there is no conflict in the input part, handle this
4950 like an output reload. */
4951 if (! rld[i].in || rtx_equal_p (other_input, value))
4953 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4954 /* Earlyclobbered outputs must conflict with inputs. */
4955 if (earlyclobber_operand_p (rld[i].out))
4956 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4961 /* RELOAD_OTHER might be live beyond instruction execution,
4962 but this is not obvious when we set time2 = 1. So check
4963 here if there might be a problem with the new reload
4964 clobbering the register used by the RELOAD_OTHER. */
4972 && (! rld[i].in || rld[i].out
4973 || ! rtx_equal_p (other_input, value)))
4974 || (out && rld[reloadnum].out_reg
4975 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4981 /* Earlyclobbered outputs must conflict with inputs. */
4982 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4988 /* Return 1 if the value in reload reg REGNO, as used by a reload
4989 needed for the part of the insn specified by OPNUM and TYPE,
4990 may be used to load VALUE into it.
4992 MODE is the mode in which the register is used, this is needed to
4993 determine how many hard regs to test.
4995 Other read-only reloads with the same value do not conflict
4996 unless OUT is non-zero and these other reloads have to live while
4997 output reloads live.
4998 If OUT is CONST0_RTX, this is a special case: it means that the
4999 test should not be for using register REGNO as reload register, but
5000 for copying from register REGNO into the reload register.
5002 RELOADNUM is the number of the reload we want to load this value for;
5003 a reload does not conflict with itself.
5005 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5006 reloads that load an address for the very reload we are considering.
5008 The caller has to make sure that there is no conflict with the return
5012 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5013 ignore_address_reloads)
5015 enum machine_mode mode;
5017 enum reload_type type;
5020 int ignore_address_reloads;
5022 int nregs = HARD_REGNO_NREGS (regno, mode);
5024 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5025 value, out, reloadnum,
5026 ignore_address_reloads))
5031 /* Determine whether the reload reg X overlaps any rtx'es used for
5032 overriding inheritance. Return nonzero if so. */
5035 conflicts_with_override (x)
5039 for (i = 0; i < n_reloads; i++)
5040 if (reload_override_in[i]
5041 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5046 /* Give an error message saying we failed to find a reload for INSN,
5047 and clear out reload R. */
5049 failed_reload (insn, r)
5053 if (asm_noperands (PATTERN (insn)) < 0)
5054 /* It's the compiler's fault. */
5055 fatal_insn ("could not find a spill register", insn);
5057 /* It's the user's fault; the operand's mode and constraint
5058 don't match. Disable this reload so we don't crash in final. */
5059 error_for_asm (insn,
5060 "`asm' operand constraint incompatible with operand size");
5064 rld[r].optional = 1;
5065 rld[r].secondary_p = 1;
5068 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5069 for reload R. If it's valid, get an rtx for it. Return nonzero if
5072 set_reload_reg (i, r)
5076 rtx reg = spill_reg_rtx[i];
5078 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5079 spill_reg_rtx[i] = reg
5080 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5082 regno = true_regnum (reg);
5084 /* Detect when the reload reg can't hold the reload mode.
5085 This used to be one `if', but Sequent compiler can't handle that. */
5086 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5088 enum machine_mode test_mode = VOIDmode;
5090 test_mode = GET_MODE (rld[r].in);
5091 /* If rld[r].in has VOIDmode, it means we will load it
5092 in whatever mode the reload reg has: to wit, rld[r].mode.
5093 We have already tested that for validity. */
5094 /* Aside from that, we need to test that the expressions
5095 to reload from or into have modes which are valid for this
5096 reload register. Otherwise the reload insns would be invalid. */
5097 if (! (rld[r].in != 0 && test_mode != VOIDmode
5098 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5099 if (! (rld[r].out != 0
5100 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5102 /* The reg is OK. */
5105 /* Mark as in use for this insn the reload regs we use
5107 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5108 rld[r].when_needed, rld[r].mode);
5110 rld[r].reg_rtx = reg;
5111 reload_spill_index[r] = spill_regs[i];
5118 /* Find a spill register to use as a reload register for reload R.
5119 LAST_RELOAD is non-zero if this is the last reload for the insn being
5122 Set rld[R].reg_rtx to the register allocated.
5124 We return 1 if successful, or 0 if we couldn't find a spill reg and
5125 we didn't change anything. */
5128 allocate_reload_reg (chain, r, last_reload)
5129 struct insn_chain *chain ATTRIBUTE_UNUSED;
5135 /* If we put this reload ahead, thinking it is a group,
5136 then insist on finding a group. Otherwise we can grab a
5137 reg that some other reload needs.
5138 (That can happen when we have a 68000 DATA_OR_FP_REG
5139 which is a group of data regs or one fp reg.)
5140 We need not be so restrictive if there are no more reloads
5143 ??? Really it would be nicer to have smarter handling
5144 for that kind of reg class, where a problem like this is normal.
5145 Perhaps those classes should be avoided for reloading
5146 by use of more alternatives. */
5148 int force_group = rld[r].nregs > 1 && ! last_reload;
5150 /* If we want a single register and haven't yet found one,
5151 take any reg in the right class and not in use.
5152 If we want a consecutive group, here is where we look for it.
5154 We use two passes so we can first look for reload regs to
5155 reuse, which are already in use for other reloads in this insn,
5156 and only then use additional registers.
5157 I think that maximizing reuse is needed to make sure we don't
5158 run out of reload regs. Suppose we have three reloads, and
5159 reloads A and B can share regs. These need two regs.
5160 Suppose A and B are given different regs.
5161 That leaves none for C. */
5162 for (pass = 0; pass < 2; pass++)
5164 /* I is the index in spill_regs.
5165 We advance it round-robin between insns to use all spill regs
5166 equally, so that inherited reloads have a chance
5167 of leapfrogging each other. */
5171 for (count = 0; count < n_spills; count++)
5173 int class = (int) rld[r].class;
5179 regnum = spill_regs[i];
5181 if ((reload_reg_free_p (regnum, rld[r].opnum,
5184 /* We check reload_reg_used to make sure we
5185 don't clobber the return register. */
5186 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5187 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5188 rld[r].when_needed, rld[r].in,
5190 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5191 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5192 /* Look first for regs to share, then for unshared. But
5193 don't share regs used for inherited reloads; they are
5194 the ones we want to preserve. */
5196 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5198 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5201 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5202 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5203 (on 68000) got us two FP regs. If NR is 1,
5204 we would reject both of them. */
5207 /* If we need only one reg, we have already won. */
5210 /* But reject a single reg if we demand a group. */
5215 /* Otherwise check that as many consecutive regs as we need
5216 are available here. */
5219 int regno = regnum + nr - 1;
5220 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5221 && spill_reg_order[regno] >= 0
5222 && reload_reg_free_p (regno, rld[r].opnum,
5223 rld[r].when_needed)))
5232 /* If we found something on pass 1, omit pass 2. */
5233 if (count < n_spills)
5237 /* We should have found a spill register by now. */
5238 if (count >= n_spills)
5241 /* I is the index in SPILL_REG_RTX of the reload register we are to
5242 allocate. Get an rtx for it and find its register number. */
5244 return set_reload_reg (i, r);
5247 /* Initialize all the tables needed to allocate reload registers.
5248 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5249 is the array we use to restore the reg_rtx field for every reload. */
5252 choose_reload_regs_init (chain, save_reload_reg_rtx)
5253 struct insn_chain *chain;
5254 rtx *save_reload_reg_rtx;
5258 for (i = 0; i < n_reloads; i++)
5259 rld[i].reg_rtx = save_reload_reg_rtx[i];
5261 memset (reload_inherited, 0, MAX_RELOADS);
5262 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5263 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5265 CLEAR_HARD_REG_SET (reload_reg_used);
5266 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5267 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5268 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5269 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5270 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5272 CLEAR_HARD_REG_SET (reg_used_in_insn);
5275 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5276 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5277 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5278 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5279 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5280 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5283 for (i = 0; i < reload_n_operands; i++)
5285 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5286 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5287 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5288 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5289 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5290 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5293 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5295 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5297 for (i = 0; i < n_reloads; i++)
5298 /* If we have already decided to use a certain register,
5299 don't use it in another way. */
5301 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5302 rld[i].when_needed, rld[i].mode);
5305 /* Assign hard reg targets for the pseudo-registers we must reload
5306 into hard regs for this insn.
5307 Also output the instructions to copy them in and out of the hard regs.
5309 For machines with register classes, we are responsible for
5310 finding a reload reg in the proper class. */
5313 choose_reload_regs (chain)
5314 struct insn_chain *chain;
5316 rtx insn = chain->insn;
5318 unsigned int max_group_size = 1;
5319 enum reg_class group_class = NO_REGS;
5320 int pass, win, inheritance;
5322 rtx save_reload_reg_rtx[MAX_RELOADS];
5324 /* In order to be certain of getting the registers we need,
5325 we must sort the reloads into order of increasing register class.
5326 Then our grabbing of reload registers will parallel the process
5327 that provided the reload registers.
5329 Also note whether any of the reloads wants a consecutive group of regs.
5330 If so, record the maximum size of the group desired and what
5331 register class contains all the groups needed by this insn. */
5333 for (j = 0; j < n_reloads; j++)
5335 reload_order[j] = j;
5336 reload_spill_index[j] = -1;
5338 if (rld[j].nregs > 1)
5340 max_group_size = MAX (rld[j].nregs, max_group_size);
5342 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5345 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5349 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5351 /* If -O, try first with inheritance, then turning it off.
5352 If not -O, don't do inheritance.
5353 Using inheritance when not optimizing leads to paradoxes
5354 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5355 because one side of the comparison might be inherited. */
5357 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5359 choose_reload_regs_init (chain, save_reload_reg_rtx);
5361 /* Process the reloads in order of preference just found.
5362 Beyond this point, subregs can be found in reload_reg_rtx.
5364 This used to look for an existing reloaded home for all of the
5365 reloads, and only then perform any new reloads. But that could lose
5366 if the reloads were done out of reg-class order because a later
5367 reload with a looser constraint might have an old home in a register
5368 needed by an earlier reload with a tighter constraint.
5370 To solve this, we make two passes over the reloads, in the order
5371 described above. In the first pass we try to inherit a reload
5372 from a previous insn. If there is a later reload that needs a
5373 class that is a proper subset of the class being processed, we must
5374 also allocate a spill register during the first pass.
5376 Then make a second pass over the reloads to allocate any reloads
5377 that haven't been given registers yet. */
5379 for (j = 0; j < n_reloads; j++)
5381 int r = reload_order[j];
5382 rtx search_equiv = NULL_RTX;
5384 /* Ignore reloads that got marked inoperative. */
5385 if (rld[r].out == 0 && rld[r].in == 0
5386 && ! rld[r].secondary_p)
5389 /* If find_reloads chose to use reload_in or reload_out as a reload
5390 register, we don't need to chose one. Otherwise, try even if it
5391 found one since we might save an insn if we find the value lying
5393 Try also when reload_in is a pseudo without a hard reg. */
5394 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5395 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5396 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5397 && GET_CODE (rld[r].in) != MEM
5398 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5401 #if 0 /* No longer needed for correct operation.
5402 It might give better code, or might not; worth an experiment? */
5403 /* If this is an optional reload, we can't inherit from earlier insns
5404 until we are sure that any non-optional reloads have been allocated.
5405 The following code takes advantage of the fact that optional reloads
5406 are at the end of reload_order. */
5407 if (rld[r].optional != 0)
5408 for (i = 0; i < j; i++)
5409 if ((rld[reload_order[i]].out != 0
5410 || rld[reload_order[i]].in != 0
5411 || rld[reload_order[i]].secondary_p)
5412 && ! rld[reload_order[i]].optional
5413 && rld[reload_order[i]].reg_rtx == 0)
5414 allocate_reload_reg (chain, reload_order[i], 0);
5417 /* First see if this pseudo is already available as reloaded
5418 for a previous insn. We cannot try to inherit for reloads
5419 that are smaller than the maximum number of registers needed
5420 for groups unless the register we would allocate cannot be used
5423 We could check here to see if this is a secondary reload for
5424 an object that is already in a register of the desired class.
5425 This would avoid the need for the secondary reload register.
5426 But this is complex because we can't easily determine what
5427 objects might want to be loaded via this reload. So let a
5428 register be allocated here. In `emit_reload_insns' we suppress
5429 one of the loads in the case described above. */
5435 enum machine_mode mode = VOIDmode;
5439 else if (GET_CODE (rld[r].in) == REG)
5441 regno = REGNO (rld[r].in);
5442 mode = GET_MODE (rld[r].in);
5444 else if (GET_CODE (rld[r].in_reg) == REG)
5446 regno = REGNO (rld[r].in_reg);
5447 mode = GET_MODE (rld[r].in_reg);
5449 else if (GET_CODE (rld[r].in_reg) == SUBREG
5450 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5452 byte = SUBREG_BYTE (rld[r].in_reg);
5453 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5454 if (regno < FIRST_PSEUDO_REGISTER)
5455 regno = subreg_regno (rld[r].in_reg);
5456 mode = GET_MODE (rld[r].in_reg);
5459 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5460 || GET_CODE (rld[r].in_reg) == PRE_DEC
5461 || GET_CODE (rld[r].in_reg) == POST_INC
5462 || GET_CODE (rld[r].in_reg) == POST_DEC)
5463 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5465 regno = REGNO (XEXP (rld[r].in_reg, 0));
5466 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5467 rld[r].out = rld[r].in;
5471 /* This won't work, since REGNO can be a pseudo reg number.
5472 Also, it takes much more hair to keep track of all the things
5473 that can invalidate an inherited reload of part of a pseudoreg. */
5474 else if (GET_CODE (rld[r].in) == SUBREG
5475 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5476 regno = subreg_regno (rld[r].in);
5479 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5481 enum reg_class class = rld[r].class, last_class;
5482 rtx last_reg = reg_last_reload_reg[regno];
5483 enum machine_mode need_mode;
5485 i = REGNO (last_reg);
5486 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5487 last_class = REGNO_REG_CLASS (i);
5493 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5494 GET_MODE_CLASS (mode));
5497 #ifdef CLASS_CANNOT_CHANGE_MODE
5499 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5500 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5502 : (GET_MODE_SIZE (GET_MODE (last_reg))
5503 >= GET_MODE_SIZE (need_mode)))
5505 (GET_MODE_SIZE (GET_MODE (last_reg))
5506 >= GET_MODE_SIZE (need_mode))
5508 && reg_reloaded_contents[i] == regno
5509 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5510 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5511 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5512 /* Even if we can't use this register as a reload
5513 register, we might use it for reload_override_in,
5514 if copying it to the desired class is cheap
5516 || ((REGISTER_MOVE_COST (mode, last_class, class)
5517 < MEMORY_MOVE_COST (mode, class, 1))
5518 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5519 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5523 #ifdef SECONDARY_MEMORY_NEEDED
5524 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5529 && (rld[r].nregs == max_group_size
5530 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5532 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5533 rld[r].when_needed, rld[r].in,
5536 /* If a group is needed, verify that all the subsequent
5537 registers still have their values intact. */
5538 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5541 for (k = 1; k < nr; k++)
5542 if (reg_reloaded_contents[i + k] != regno
5543 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5551 last_reg = (GET_MODE (last_reg) == mode
5552 ? last_reg : gen_rtx_REG (mode, i));
5555 for (k = 0; k < nr; k++)
5556 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5559 /* We found a register that contains the
5560 value we need. If this register is the
5561 same as an `earlyclobber' operand of the
5562 current insn, just mark it as a place to
5563 reload from since we can't use it as the
5564 reload register itself. */
5566 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5567 if (reg_overlap_mentioned_for_reload_p
5568 (reg_last_reload_reg[regno],
5569 reload_earlyclobbers[i1]))
5572 if (i1 != n_earlyclobbers
5573 || ! (free_for_value_p (i, rld[r].mode,
5575 rld[r].when_needed, rld[r].in,
5577 /* Don't use it if we'd clobber a pseudo reg. */
5578 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5580 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5581 /* Don't clobber the frame pointer. */
5582 || (i == HARD_FRAME_POINTER_REGNUM
5583 && frame_pointer_needed
5585 /* Don't really use the inherited spill reg
5586 if we need it wider than we've got it. */
5587 || (GET_MODE_SIZE (rld[r].mode)
5588 > GET_MODE_SIZE (mode))
5591 /* If find_reloads chose reload_out as reload
5592 register, stay with it - that leaves the
5593 inherited register for subsequent reloads. */
5594 || (rld[r].out && rld[r].reg_rtx
5595 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5597 if (! rld[r].optional)
5599 reload_override_in[r] = last_reg;
5600 reload_inheritance_insn[r]
5601 = reg_reloaded_insn[i];
5607 /* We can use this as a reload reg. */
5608 /* Mark the register as in use for this part of
5610 mark_reload_reg_in_use (i,
5614 rld[r].reg_rtx = last_reg;
5615 reload_inherited[r] = 1;
5616 reload_inheritance_insn[r]
5617 = reg_reloaded_insn[i];
5618 reload_spill_index[r] = i;
5619 for (k = 0; k < nr; k++)
5620 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5628 /* Here's another way to see if the value is already lying around. */
5631 && ! reload_inherited[r]
5633 && (CONSTANT_P (rld[r].in)
5634 || GET_CODE (rld[r].in) == PLUS
5635 || GET_CODE (rld[r].in) == REG
5636 || GET_CODE (rld[r].in) == MEM)
5637 && (rld[r].nregs == max_group_size
5638 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5639 search_equiv = rld[r].in;
5640 /* If this is an output reload from a simple move insn, look
5641 if an equivalence for the input is available. */
5642 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5644 rtx set = single_set (insn);
5647 && rtx_equal_p (rld[r].out, SET_DEST (set))
5648 && CONSTANT_P (SET_SRC (set)))
5649 search_equiv = SET_SRC (set);
5655 = find_equiv_reg (search_equiv, insn, rld[r].class,
5656 -1, NULL, 0, rld[r].mode);
5661 if (GET_CODE (equiv) == REG)
5662 regno = REGNO (equiv);
5663 else if (GET_CODE (equiv) == SUBREG)
5665 /* This must be a SUBREG of a hard register.
5666 Make a new REG since this might be used in an
5667 address and not all machines support SUBREGs
5669 regno = subreg_regno (equiv);
5670 equiv = gen_rtx_REG (rld[r].mode, regno);
5676 /* If we found a spill reg, reject it unless it is free
5677 and of the desired class. */
5679 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5680 && ! free_for_value_p (regno, rld[r].mode,
5681 rld[r].opnum, rld[r].when_needed,
5682 rld[r].in, rld[r].out, r, 1))
5683 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5687 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5690 /* We found a register that contains the value we need.
5691 If this register is the same as an `earlyclobber' operand
5692 of the current insn, just mark it as a place to reload from
5693 since we can't use it as the reload register itself. */
5696 for (i = 0; i < n_earlyclobbers; i++)
5697 if (reg_overlap_mentioned_for_reload_p (equiv,
5698 reload_earlyclobbers[i]))
5700 if (! rld[r].optional)
5701 reload_override_in[r] = equiv;
5706 /* If the equiv register we have found is explicitly clobbered
5707 in the current insn, it depends on the reload type if we
5708 can use it, use it for reload_override_in, or not at all.
5709 In particular, we then can't use EQUIV for a
5710 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5714 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5715 switch (rld[r].when_needed)
5717 case RELOAD_FOR_OTHER_ADDRESS:
5718 case RELOAD_FOR_INPADDR_ADDRESS:
5719 case RELOAD_FOR_INPUT_ADDRESS:
5720 case RELOAD_FOR_OPADDR_ADDR:
5723 case RELOAD_FOR_INPUT:
5724 case RELOAD_FOR_OPERAND_ADDRESS:
5725 if (! rld[r].optional)
5726 reload_override_in[r] = equiv;
5732 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5733 switch (rld[r].when_needed)
5735 case RELOAD_FOR_OTHER_ADDRESS:
5736 case RELOAD_FOR_INPADDR_ADDRESS:
5737 case RELOAD_FOR_INPUT_ADDRESS:
5738 case RELOAD_FOR_OPADDR_ADDR:
5739 case RELOAD_FOR_OPERAND_ADDRESS:
5740 case RELOAD_FOR_INPUT:
5743 if (! rld[r].optional)
5744 reload_override_in[r] = equiv;
5752 /* If we found an equivalent reg, say no code need be generated
5753 to load it, and use it as our reload reg. */
5755 && (regno != HARD_FRAME_POINTER_REGNUM
5756 || !frame_pointer_needed))
5758 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5760 rld[r].reg_rtx = equiv;
5761 reload_inherited[r] = 1;
5763 /* If reg_reloaded_valid is not set for this register,
5764 there might be a stale spill_reg_store lying around.
5765 We must clear it, since otherwise emit_reload_insns
5766 might delete the store. */
5767 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5768 spill_reg_store[regno] = NULL_RTX;
5769 /* If any of the hard registers in EQUIV are spill
5770 registers, mark them as in use for this insn. */
5771 for (k = 0; k < nr; k++)
5773 i = spill_reg_order[regno + k];
5776 mark_reload_reg_in_use (regno, rld[r].opnum,
5779 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5786 /* If we found a register to use already, or if this is an optional
5787 reload, we are done. */
5788 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5792 /* No longer needed for correct operation. Might or might
5793 not give better code on the average. Want to experiment? */
5795 /* See if there is a later reload that has a class different from our
5796 class that intersects our class or that requires less register
5797 than our reload. If so, we must allocate a register to this
5798 reload now, since that reload might inherit a previous reload
5799 and take the only available register in our class. Don't do this
5800 for optional reloads since they will force all previous reloads
5801 to be allocated. Also don't do this for reloads that have been
5804 for (i = j + 1; i < n_reloads; i++)
5806 int s = reload_order[i];
5808 if ((rld[s].in == 0 && rld[s].out == 0
5809 && ! rld[s].secondary_p)
5813 if ((rld[s].class != rld[r].class
5814 && reg_classes_intersect_p (rld[r].class,
5816 || rld[s].nregs < rld[r].nregs)
5823 allocate_reload_reg (chain, r, j == n_reloads - 1);
5827 /* Now allocate reload registers for anything non-optional that
5828 didn't get one yet. */
5829 for (j = 0; j < n_reloads; j++)
5831 int r = reload_order[j];
5833 /* Ignore reloads that got marked inoperative. */
5834 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5837 /* Skip reloads that already have a register allocated or are
5839 if (rld[r].reg_rtx != 0 || rld[r].optional)
5842 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5846 /* If that loop got all the way, we have won. */
5853 /* Loop around and try without any inheritance. */
5858 /* First undo everything done by the failed attempt
5859 to allocate with inheritance. */
5860 choose_reload_regs_init (chain, save_reload_reg_rtx);
5862 /* Some sanity tests to verify that the reloads found in the first
5863 pass are identical to the ones we have now. */
5864 if (chain->n_reloads != n_reloads)
5867 for (i = 0; i < n_reloads; i++)
5869 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5871 if (chain->rld[i].when_needed != rld[i].when_needed)
5873 for (j = 0; j < n_spills; j++)
5874 if (spill_regs[j] == chain->rld[i].regno)
5875 if (! set_reload_reg (j, i))
5876 failed_reload (chain->insn, i);
5880 /* If we thought we could inherit a reload, because it seemed that
5881 nothing else wanted the same reload register earlier in the insn,
5882 verify that assumption, now that all reloads have been assigned.
5883 Likewise for reloads where reload_override_in has been set. */
5885 /* If doing expensive optimizations, do one preliminary pass that doesn't
5886 cancel any inheritance, but removes reloads that have been needed only
5887 for reloads that we know can be inherited. */
5888 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5890 for (j = 0; j < n_reloads; j++)
5892 int r = reload_order[j];
5894 if (reload_inherited[r] && rld[r].reg_rtx)
5895 check_reg = rld[r].reg_rtx;
5896 else if (reload_override_in[r]
5897 && (GET_CODE (reload_override_in[r]) == REG
5898 || GET_CODE (reload_override_in[r]) == SUBREG))
5899 check_reg = reload_override_in[r];
5902 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5903 rld[r].opnum, rld[r].when_needed, rld[r].in,
5904 (reload_inherited[r]
5905 ? rld[r].out : const0_rtx),
5910 reload_inherited[r] = 0;
5911 reload_override_in[r] = 0;
5913 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5914 reload_override_in, then we do not need its related
5915 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5916 likewise for other reload types.
5917 We handle this by removing a reload when its only replacement
5918 is mentioned in reload_in of the reload we are going to inherit.
5919 A special case are auto_inc expressions; even if the input is
5920 inherited, we still need the address for the output. We can
5921 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5922 If we succeeded removing some reload and we are doing a preliminary
5923 pass just to remove such reloads, make another pass, since the
5924 removal of one reload might allow us to inherit another one. */
5926 && rld[r].out != rld[r].in
5927 && remove_address_replacements (rld[r].in) && pass)
5932 /* Now that reload_override_in is known valid,
5933 actually override reload_in. */
5934 for (j = 0; j < n_reloads; j++)
5935 if (reload_override_in[j])
5936 rld[j].in = reload_override_in[j];
5938 /* If this reload won't be done because it has been cancelled or is
5939 optional and not inherited, clear reload_reg_rtx so other
5940 routines (such as subst_reloads) don't get confused. */
5941 for (j = 0; j < n_reloads; j++)
5942 if (rld[j].reg_rtx != 0
5943 && ((rld[j].optional && ! reload_inherited[j])
5944 || (rld[j].in == 0 && rld[j].out == 0
5945 && ! rld[j].secondary_p)))
5947 int regno = true_regnum (rld[j].reg_rtx);
5949 if (spill_reg_order[regno] >= 0)
5950 clear_reload_reg_in_use (regno, rld[j].opnum,
5951 rld[j].when_needed, rld[j].mode);
5953 reload_spill_index[j] = -1;
5956 /* Record which pseudos and which spill regs have output reloads. */
5957 for (j = 0; j < n_reloads; j++)
5959 int r = reload_order[j];
5961 i = reload_spill_index[r];
5963 /* I is nonneg if this reload uses a register.
5964 If rld[r].reg_rtx is 0, this is an optional reload
5965 that we opted to ignore. */
5966 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5967 && rld[r].reg_rtx != 0)
5969 int nregno = REGNO (rld[r].out_reg);
5972 if (nregno < FIRST_PSEUDO_REGISTER)
5973 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5976 reg_has_output_reload[nregno + nr] = 1;
5980 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5982 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5985 if (rld[r].when_needed != RELOAD_OTHER
5986 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5987 && rld[r].when_needed != RELOAD_FOR_INSN)
5993 /* Deallocate the reload register for reload R. This is called from
5994 remove_address_replacements. */
5997 deallocate_reload_reg (r)
6002 if (! rld[r].reg_rtx)
6004 regno = true_regnum (rld[r].reg_rtx);
6006 if (spill_reg_order[regno] >= 0)
6007 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6009 reload_spill_index[r] = -1;
6012 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6013 reloads of the same item for fear that we might not have enough reload
6014 registers. However, normally they will get the same reload register
6015 and hence actually need not be loaded twice.
6017 Here we check for the most common case of this phenomenon: when we have
6018 a number of reloads for the same object, each of which were allocated
6019 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6020 reload, and is not modified in the insn itself. If we find such,
6021 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6022 This will not increase the number of spill registers needed and will
6023 prevent redundant code. */
6026 merge_assigned_reloads (insn)
6031 /* Scan all the reloads looking for ones that only load values and
6032 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6033 assigned and not modified by INSN. */
6035 for (i = 0; i < n_reloads; i++)
6037 int conflicting_input = 0;
6038 int max_input_address_opnum = -1;
6039 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6041 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6042 || rld[i].out != 0 || rld[i].reg_rtx == 0
6043 || reg_set_p (rld[i].reg_rtx, insn))
6046 /* Look at all other reloads. Ensure that the only use of this
6047 reload_reg_rtx is in a reload that just loads the same value
6048 as we do. Note that any secondary reloads must be of the identical
6049 class since the values, modes, and result registers are the
6050 same, so we need not do anything with any secondary reloads. */
6052 for (j = 0; j < n_reloads; j++)
6054 if (i == j || rld[j].reg_rtx == 0
6055 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6059 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6060 && rld[j].opnum > max_input_address_opnum)
6061 max_input_address_opnum = rld[j].opnum;
6063 /* If the reload regs aren't exactly the same (e.g, different modes)
6064 or if the values are different, we can't merge this reload.
6065 But if it is an input reload, we might still merge
6066 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6068 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6069 || rld[j].out != 0 || rld[j].in == 0
6070 || ! rtx_equal_p (rld[i].in, rld[j].in))
6072 if (rld[j].when_needed != RELOAD_FOR_INPUT
6073 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6074 || rld[i].opnum > rld[j].opnum)
6075 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6077 conflicting_input = 1;
6078 if (min_conflicting_input_opnum > rld[j].opnum)
6079 min_conflicting_input_opnum = rld[j].opnum;
6083 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6084 we, in fact, found any matching reloads. */
6087 && max_input_address_opnum <= min_conflicting_input_opnum)
6089 for (j = 0; j < n_reloads; j++)
6090 if (i != j && rld[j].reg_rtx != 0
6091 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6092 && (! conflicting_input
6093 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6094 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6096 rld[i].when_needed = RELOAD_OTHER;
6098 reload_spill_index[j] = -1;
6099 transfer_replacements (i, j);
6102 /* If this is now RELOAD_OTHER, look for any reloads that load
6103 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6104 if they were for inputs, RELOAD_OTHER for outputs. Note that
6105 this test is equivalent to looking for reloads for this operand
6107 /* We must take special care when there are two or more reloads to
6108 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6109 same value or a part of it; we must not change its type if there
6110 is a conflicting input. */
6112 if (rld[i].when_needed == RELOAD_OTHER)
6113 for (j = 0; j < n_reloads; j++)
6115 && rld[j].when_needed != RELOAD_OTHER
6116 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6117 && (! conflicting_input
6118 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6119 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6120 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6123 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6124 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6125 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6130 /* These arrays are filled by emit_reload_insns and its subroutines. */
6131 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6132 static rtx other_input_address_reload_insns = 0;
6133 static rtx other_input_reload_insns = 0;
6134 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6135 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6136 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6137 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6138 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6139 static rtx operand_reload_insns = 0;
6140 static rtx other_operand_reload_insns = 0;
6141 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6143 /* Values to be put in spill_reg_store are put here first. */
6144 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6145 static HARD_REG_SET reg_reloaded_died;
6147 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6148 has the number J. OLD contains the value to be used as input. */
6151 emit_input_reload_insns (chain, rl, old, j)
6152 struct insn_chain *chain;
6157 rtx insn = chain->insn;
6158 rtx reloadreg = rl->reg_rtx;
6159 rtx oldequiv_reg = 0;
6162 enum machine_mode mode;
6165 /* Determine the mode to reload in.
6166 This is very tricky because we have three to choose from.
6167 There is the mode the insn operand wants (rl->inmode).
6168 There is the mode of the reload register RELOADREG.
6169 There is the intrinsic mode of the operand, which we could find
6170 by stripping some SUBREGs.
6171 It turns out that RELOADREG's mode is irrelevant:
6172 we can change that arbitrarily.
6174 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6175 then the reload reg may not support QImode moves, so use SImode.
6176 If foo is in memory due to spilling a pseudo reg, this is safe,
6177 because the QImode value is in the least significant part of a
6178 slot big enough for a SImode. If foo is some other sort of
6179 memory reference, then it is impossible to reload this case,
6180 so previous passes had better make sure this never happens.
6182 Then consider a one-word union which has SImode and one of its
6183 members is a float, being fetched as (SUBREG:SF union:SI).
6184 We must fetch that as SFmode because we could be loading into
6185 a float-only register. In this case OLD's mode is correct.
6187 Consider an immediate integer: it has VOIDmode. Here we need
6188 to get a mode from something else.
6190 In some cases, there is a fourth mode, the operand's
6191 containing mode. If the insn specifies a containing mode for
6192 this operand, it overrides all others.
6194 I am not sure whether the algorithm here is always right,
6195 but it does the right things in those cases. */
6197 mode = GET_MODE (old);
6198 if (mode == VOIDmode)
6201 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6202 /* If we need a secondary register for this operation, see if
6203 the value is already in a register in that class. Don't
6204 do this if the secondary register will be used as a scratch
6207 if (rl->secondary_in_reload >= 0
6208 && rl->secondary_in_icode == CODE_FOR_nothing
6211 = find_equiv_reg (old, insn,
6212 rld[rl->secondary_in_reload].class,
6216 /* If reloading from memory, see if there is a register
6217 that already holds the same value. If so, reload from there.
6218 We can pass 0 as the reload_reg_p argument because
6219 any other reload has either already been emitted,
6220 in which case find_equiv_reg will see the reload-insn,
6221 or has yet to be emitted, in which case it doesn't matter
6222 because we will use this equiv reg right away. */
6224 if (oldequiv == 0 && optimize
6225 && (GET_CODE (old) == MEM
6226 || (GET_CODE (old) == REG
6227 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6228 && reg_renumber[REGNO (old)] < 0)))
6229 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6233 unsigned int regno = true_regnum (oldequiv);
6235 /* Don't use OLDEQUIV if any other reload changes it at an
6236 earlier stage of this insn or at this stage. */
6237 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6238 rl->in, const0_rtx, j, 0))
6241 /* If it is no cheaper to copy from OLDEQUIV into the
6242 reload register than it would be to move from memory,
6243 don't use it. Likewise, if we need a secondary register
6247 && ((REGNO_REG_CLASS (regno) != rl->class
6248 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6250 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6251 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6252 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6256 #ifdef SECONDARY_MEMORY_NEEDED
6257 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6265 /* delete_output_reload is only invoked properly if old contains
6266 the original pseudo register. Since this is replaced with a
6267 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6268 find the pseudo in RELOAD_IN_REG. */
6270 && reload_override_in[j]
6271 && GET_CODE (rl->in_reg) == REG)
6278 else if (GET_CODE (oldequiv) == REG)
6279 oldequiv_reg = oldequiv;
6280 else if (GET_CODE (oldequiv) == SUBREG)
6281 oldequiv_reg = SUBREG_REG (oldequiv);
6283 /* If we are reloading from a register that was recently stored in
6284 with an output-reload, see if we can prove there was
6285 actually no need to store the old value in it. */
6287 if (optimize && GET_CODE (oldequiv) == REG
6288 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6289 && spill_reg_store[REGNO (oldequiv)]
6290 && GET_CODE (old) == REG
6291 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6292 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6294 delete_output_reload (insn, j, REGNO (oldequiv));
6296 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6297 then load RELOADREG from OLDEQUIV. Note that we cannot use
6298 gen_lowpart_common since it can do the wrong thing when
6299 RELOADREG has a multi-word mode. Note that RELOADREG
6300 must always be a REG here. */
6302 if (GET_MODE (reloadreg) != mode)
6303 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6304 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6305 oldequiv = SUBREG_REG (oldequiv);
6306 if (GET_MODE (oldequiv) != VOIDmode
6307 && mode != GET_MODE (oldequiv))
6308 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6310 /* Switch to the right place to emit the reload insns. */
6311 switch (rl->when_needed)
6314 where = &other_input_reload_insns;
6316 case RELOAD_FOR_INPUT:
6317 where = &input_reload_insns[rl->opnum];
6319 case RELOAD_FOR_INPUT_ADDRESS:
6320 where = &input_address_reload_insns[rl->opnum];
6322 case RELOAD_FOR_INPADDR_ADDRESS:
6323 where = &inpaddr_address_reload_insns[rl->opnum];
6325 case RELOAD_FOR_OUTPUT_ADDRESS:
6326 where = &output_address_reload_insns[rl->opnum];
6328 case RELOAD_FOR_OUTADDR_ADDRESS:
6329 where = &outaddr_address_reload_insns[rl->opnum];
6331 case RELOAD_FOR_OPERAND_ADDRESS:
6332 where = &operand_reload_insns;
6334 case RELOAD_FOR_OPADDR_ADDR:
6335 where = &other_operand_reload_insns;
6337 case RELOAD_FOR_OTHER_ADDRESS:
6338 where = &other_input_address_reload_insns;
6344 push_to_sequence (*where);
6346 /* Auto-increment addresses must be reloaded in a special way. */
6347 if (rl->out && ! rl->out_reg)
6349 /* We are not going to bother supporting the case where a
6350 incremented register can't be copied directly from
6351 OLDEQUIV since this seems highly unlikely. */
6352 if (rl->secondary_in_reload >= 0)
6355 if (reload_inherited[j])
6356 oldequiv = reloadreg;
6358 old = XEXP (rl->in_reg, 0);
6360 if (optimize && GET_CODE (oldequiv) == REG
6361 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6362 && spill_reg_store[REGNO (oldequiv)]
6363 && GET_CODE (old) == REG
6364 && (dead_or_set_p (insn,
6365 spill_reg_stored_to[REGNO (oldequiv)])
6366 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6368 delete_output_reload (insn, j, REGNO (oldequiv));
6370 /* Prevent normal processing of this reload. */
6372 /* Output a special code sequence for this case. */
6373 new_spill_reg_store[REGNO (reloadreg)]
6374 = inc_for_reload (reloadreg, oldequiv, rl->out,
6378 /* If we are reloading a pseudo-register that was set by the previous
6379 insn, see if we can get rid of that pseudo-register entirely
6380 by redirecting the previous insn into our reload register. */
6382 else if (optimize && GET_CODE (old) == REG
6383 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6384 && dead_or_set_p (insn, old)
6385 /* This is unsafe if some other reload
6386 uses the same reg first. */
6387 && ! conflicts_with_override (reloadreg)
6388 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6389 rl->when_needed, old, rl->out, j, 0))
6391 rtx temp = PREV_INSN (insn);
6392 while (temp && GET_CODE (temp) == NOTE)
6393 temp = PREV_INSN (temp);
6395 && GET_CODE (temp) == INSN
6396 && GET_CODE (PATTERN (temp)) == SET
6397 && SET_DEST (PATTERN (temp)) == old
6398 /* Make sure we can access insn_operand_constraint. */
6399 && asm_noperands (PATTERN (temp)) < 0
6400 /* This is unsafe if operand occurs more than once in current
6401 insn. Perhaps some occurrences aren't reloaded. */
6402 && count_occurrences (PATTERN (insn), old, 0) == 1)
6404 rtx old = SET_DEST (PATTERN (temp));
6405 /* Store into the reload register instead of the pseudo. */
6406 SET_DEST (PATTERN (temp)) = reloadreg;
6408 /* Verify that resulting insn is valid. */
6409 extract_insn (temp);
6410 if (constrain_operands (1))
6412 /* If the previous insn is an output reload, the source is
6413 a reload register, and its spill_reg_store entry will
6414 contain the previous destination. This is now
6416 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6417 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6419 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6420 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6423 /* If these are the only uses of the pseudo reg,
6424 pretend for GDB it lives in the reload reg we used. */
6425 if (REG_N_DEATHS (REGNO (old)) == 1
6426 && REG_N_SETS (REGNO (old)) == 1)
6428 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6429 alter_reg (REGNO (old), -1);
6435 SET_DEST (PATTERN (temp)) = old;
6440 /* We can't do that, so output an insn to load RELOADREG. */
6442 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6443 /* If we have a secondary reload, pick up the secondary register
6444 and icode, if any. If OLDEQUIV and OLD are different or
6445 if this is an in-out reload, recompute whether or not we
6446 still need a secondary register and what the icode should
6447 be. If we still need a secondary register and the class or
6448 icode is different, go back to reloading from OLD if using
6449 OLDEQUIV means that we got the wrong type of register. We
6450 cannot have different class or icode due to an in-out reload
6451 because we don't make such reloads when both the input and
6452 output need secondary reload registers. */
6454 if (! special && rl->secondary_in_reload >= 0)
6456 rtx second_reload_reg = 0;
6457 int secondary_reload = rl->secondary_in_reload;
6458 rtx real_oldequiv = oldequiv;
6461 enum insn_code icode;
6463 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6464 and similarly for OLD.
6465 See comments in get_secondary_reload in reload.c. */
6466 /* If it is a pseudo that cannot be replaced with its
6467 equivalent MEM, we must fall back to reload_in, which
6468 will have all the necessary substitutions registered.
6469 Likewise for a pseudo that can't be replaced with its
6470 equivalent constant.
6472 Take extra care for subregs of such pseudos. Note that
6473 we cannot use reg_equiv_mem in this case because it is
6474 not in the right mode. */
6477 if (GET_CODE (tmp) == SUBREG)
6478 tmp = SUBREG_REG (tmp);
6479 if (GET_CODE (tmp) == REG
6480 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6481 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6482 || reg_equiv_constant[REGNO (tmp)] != 0))
6484 if (! reg_equiv_mem[REGNO (tmp)]
6485 || num_not_at_initial_offset
6486 || GET_CODE (oldequiv) == SUBREG)
6487 real_oldequiv = rl->in;
6489 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6493 if (GET_CODE (tmp) == SUBREG)
6494 tmp = SUBREG_REG (tmp);
6495 if (GET_CODE (tmp) == REG
6496 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6497 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6498 || reg_equiv_constant[REGNO (tmp)] != 0))
6500 if (! reg_equiv_mem[REGNO (tmp)]
6501 || num_not_at_initial_offset
6502 || GET_CODE (old) == SUBREG)
6505 real_old = reg_equiv_mem[REGNO (tmp)];
6508 second_reload_reg = rld[secondary_reload].reg_rtx;
6509 icode = rl->secondary_in_icode;
6511 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6512 || (rl->in != 0 && rl->out != 0))
6514 enum reg_class new_class
6515 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6516 mode, real_oldequiv);
6518 if (new_class == NO_REGS)
6519 second_reload_reg = 0;
6522 enum insn_code new_icode;
6523 enum machine_mode new_mode;
6525 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6526 REGNO (second_reload_reg)))
6527 oldequiv = old, real_oldequiv = real_old;
6530 new_icode = reload_in_optab[(int) mode];
6531 if (new_icode != CODE_FOR_nothing
6532 && ((insn_data[(int) new_icode].operand[0].predicate
6533 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6535 || (insn_data[(int) new_icode].operand[1].predicate
6536 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6537 (real_oldequiv, mode)))))
6538 new_icode = CODE_FOR_nothing;
6540 if (new_icode == CODE_FOR_nothing)
6543 new_mode = insn_data[(int) new_icode].operand[2].mode;
6545 if (GET_MODE (second_reload_reg) != new_mode)
6547 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6549 oldequiv = old, real_oldequiv = real_old;
6552 = gen_rtx_REG (new_mode,
6553 REGNO (second_reload_reg));
6559 /* If we still need a secondary reload register, check
6560 to see if it is being used as a scratch or intermediate
6561 register and generate code appropriately. If we need
6562 a scratch register, use REAL_OLDEQUIV since the form of
6563 the insn may depend on the actual address if it is
6566 if (second_reload_reg)
6568 if (icode != CODE_FOR_nothing)
6570 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6571 second_reload_reg));
6576 /* See if we need a scratch register to load the
6577 intermediate register (a tertiary reload). */
6578 enum insn_code tertiary_icode
6579 = rld[secondary_reload].secondary_in_icode;
6581 if (tertiary_icode != CODE_FOR_nothing)
6583 rtx third_reload_reg
6584 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6586 emit_insn ((GEN_FCN (tertiary_icode)
6587 (second_reload_reg, real_oldequiv,
6588 third_reload_reg)));
6591 gen_reload (second_reload_reg, real_oldequiv,
6595 oldequiv = second_reload_reg;
6601 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6603 rtx real_oldequiv = oldequiv;
6605 if ((GET_CODE (oldequiv) == REG
6606 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6607 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6608 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6609 || (GET_CODE (oldequiv) == SUBREG
6610 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6611 && (REGNO (SUBREG_REG (oldequiv))
6612 >= FIRST_PSEUDO_REGISTER)
6613 && ((reg_equiv_memory_loc
6614 [REGNO (SUBREG_REG (oldequiv))] != 0)
6615 || (reg_equiv_constant
6616 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6617 || (CONSTANT_P (oldequiv)
6618 && (PREFERRED_RELOAD_CLASS (oldequiv,
6619 REGNO_REG_CLASS (REGNO (reloadreg)))
6621 real_oldequiv = rl->in;
6622 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6626 if (flag_non_call_exceptions)
6627 copy_eh_notes (insn, get_insns ());
6629 /* End this sequence. */
6630 *where = get_insns ();
6633 /* Update reload_override_in so that delete_address_reloads_1
6634 can see the actual register usage. */
6636 reload_override_in[j] = oldequiv;
6639 /* Generate insns to for the output reload RL, which is for the insn described
6640 by CHAIN and has the number J. */
6642 emit_output_reload_insns (chain, rl, j)
6643 struct insn_chain *chain;
6647 rtx reloadreg = rl->reg_rtx;
6648 rtx insn = chain->insn;
6651 enum machine_mode mode = GET_MODE (old);
6654 if (rl->when_needed == RELOAD_OTHER)
6657 push_to_sequence (output_reload_insns[rl->opnum]);
6659 /* Determine the mode to reload in.
6660 See comments above (for input reloading). */
6662 if (mode == VOIDmode)
6664 /* VOIDmode should never happen for an output. */
6665 if (asm_noperands (PATTERN (insn)) < 0)
6666 /* It's the compiler's fault. */
6667 fatal_insn ("VOIDmode on an output", insn);
6668 error_for_asm (insn, "output operand is constant in `asm'");
6669 /* Prevent crash--use something we know is valid. */
6671 old = gen_rtx_REG (mode, REGNO (reloadreg));
6674 if (GET_MODE (reloadreg) != mode)
6675 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6677 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6679 /* If we need two reload regs, set RELOADREG to the intermediate
6680 one, since it will be stored into OLD. We might need a secondary
6681 register only for an input reload, so check again here. */
6683 if (rl->secondary_out_reload >= 0)
6687 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6688 && reg_equiv_mem[REGNO (old)] != 0)
6689 real_old = reg_equiv_mem[REGNO (old)];
6691 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6695 rtx second_reloadreg = reloadreg;
6696 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6698 /* See if RELOADREG is to be used as a scratch register
6699 or as an intermediate register. */
6700 if (rl->secondary_out_icode != CODE_FOR_nothing)
6702 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6703 (real_old, second_reloadreg, reloadreg)));
6708 /* See if we need both a scratch and intermediate reload
6711 int secondary_reload = rl->secondary_out_reload;
6712 enum insn_code tertiary_icode
6713 = rld[secondary_reload].secondary_out_icode;
6715 if (GET_MODE (reloadreg) != mode)
6716 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6718 if (tertiary_icode != CODE_FOR_nothing)
6721 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6724 /* Copy primary reload reg to secondary reload reg.
6725 (Note that these have been swapped above, then
6726 secondary reload reg to OLD using our insn.) */
6728 /* If REAL_OLD is a paradoxical SUBREG, remove it
6729 and try to put the opposite SUBREG on
6731 if (GET_CODE (real_old) == SUBREG
6732 && (GET_MODE_SIZE (GET_MODE (real_old))
6733 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6734 && 0 != (tem = gen_lowpart_common
6735 (GET_MODE (SUBREG_REG (real_old)),
6737 real_old = SUBREG_REG (real_old), reloadreg = tem;
6739 gen_reload (reloadreg, second_reloadreg,
6740 rl->opnum, rl->when_needed);
6741 emit_insn ((GEN_FCN (tertiary_icode)
6742 (real_old, reloadreg, third_reloadreg)));
6747 /* Copy between the reload regs here and then to
6750 gen_reload (reloadreg, second_reloadreg,
6751 rl->opnum, rl->when_needed);
6757 /* Output the last reload insn. */
6762 /* Don't output the last reload if OLD is not the dest of
6763 INSN and is in the src and is clobbered by INSN. */
6764 if (! flag_expensive_optimizations
6765 || GET_CODE (old) != REG
6766 || !(set = single_set (insn))
6767 || rtx_equal_p (old, SET_DEST (set))
6768 || !reg_mentioned_p (old, SET_SRC (set))
6769 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6770 gen_reload (old, reloadreg, rl->opnum,
6774 /* Look at all insns we emitted, just to be safe. */
6775 for (p = get_insns (); p; p = NEXT_INSN (p))
6778 rtx pat = PATTERN (p);
6780 /* If this output reload doesn't come from a spill reg,
6781 clear any memory of reloaded copies of the pseudo reg.
6782 If this output reload comes from a spill reg,
6783 reg_has_output_reload will make this do nothing. */
6784 note_stores (pat, forget_old_reloads_1, NULL);
6786 if (reg_mentioned_p (rl->reg_rtx, pat))
6788 rtx set = single_set (insn);
6789 if (reload_spill_index[j] < 0
6791 && SET_SRC (set) == rl->reg_rtx)
6793 int src = REGNO (SET_SRC (set));
6795 reload_spill_index[j] = src;
6796 SET_HARD_REG_BIT (reg_is_output_reload, src);
6797 if (find_regno_note (insn, REG_DEAD, src))
6798 SET_HARD_REG_BIT (reg_reloaded_died, src);
6800 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6802 int s = rl->secondary_out_reload;
6803 set = single_set (p);
6804 /* If this reload copies only to the secondary reload
6805 register, the secondary reload does the actual
6807 if (s >= 0 && set == NULL_RTX)
6808 /* We can't tell what function the secondary reload
6809 has and where the actual store to the pseudo is
6810 made; leave new_spill_reg_store alone. */
6813 && SET_SRC (set) == rl->reg_rtx
6814 && SET_DEST (set) == rld[s].reg_rtx)
6816 /* Usually the next instruction will be the
6817 secondary reload insn; if we can confirm
6818 that it is, setting new_spill_reg_store to
6819 that insn will allow an extra optimization. */
6820 rtx s_reg = rld[s].reg_rtx;
6821 rtx next = NEXT_INSN (p);
6822 rld[s].out = rl->out;
6823 rld[s].out_reg = rl->out_reg;
6824 set = single_set (next);
6825 if (set && SET_SRC (set) == s_reg
6826 && ! new_spill_reg_store[REGNO (s_reg)])
6828 SET_HARD_REG_BIT (reg_is_output_reload,
6830 new_spill_reg_store[REGNO (s_reg)] = next;
6834 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6839 if (rl->when_needed == RELOAD_OTHER)
6841 emit_insn (other_output_reload_insns[rl->opnum]);
6842 other_output_reload_insns[rl->opnum] = get_insns ();
6845 output_reload_insns[rl->opnum] = get_insns ();
6847 if (flag_non_call_exceptions)
6848 copy_eh_notes (insn, get_insns ());
6853 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6854 and has the number J. */
6856 do_input_reload (chain, rl, j)
6857 struct insn_chain *chain;
6861 int expect_occurrences = 1;
6862 rtx insn = chain->insn;
6863 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6864 ? rl->in_reg : rl->in);
6867 /* AUTO_INC reloads need to be handled even if inherited. We got an
6868 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6869 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6870 && ! rtx_equal_p (rl->reg_rtx, old)
6871 && rl->reg_rtx != 0)
6872 emit_input_reload_insns (chain, rld + j, old, j);
6874 /* When inheriting a wider reload, we have a MEM in rl->in,
6875 e.g. inheriting a SImode output reload for
6876 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6877 if (optimize && reload_inherited[j] && rl->in
6878 && GET_CODE (rl->in) == MEM
6879 && GET_CODE (rl->in_reg) == MEM
6880 && reload_spill_index[j] >= 0
6881 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6884 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6885 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6888 /* If we are reloading a register that was recently stored in with an
6889 output-reload, see if we can prove there was
6890 actually no need to store the old value in it. */
6893 && (reload_inherited[j] || reload_override_in[j])
6895 && GET_CODE (rl->reg_rtx) == REG
6896 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6898 /* There doesn't seem to be any reason to restrict this to pseudos
6899 and doing so loses in the case where we are copying from a
6900 register of the wrong class. */
6901 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6902 >= FIRST_PSEUDO_REGISTER)
6904 /* The insn might have already some references to stackslots
6905 replaced by MEMs, while reload_out_reg still names the
6907 && (dead_or_set_p (insn,
6908 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6909 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6911 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6914 /* Do output reloading for reload RL, which is for the insn described by
6915 CHAIN and has the number J.
6916 ??? At some point we need to support handling output reloads of
6917 JUMP_INSNs or insns that set cc0. */
6919 do_output_reload (chain, rl, j)
6920 struct insn_chain *chain;
6925 rtx insn = chain->insn;
6926 /* If this is an output reload that stores something that is
6927 not loaded in this same reload, see if we can eliminate a previous
6929 rtx pseudo = rl->out_reg;
6933 && GET_CODE (pseudo) == REG
6934 && ! rtx_equal_p (rl->in_reg, pseudo)
6935 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6936 && reg_last_reload_reg[REGNO (pseudo)])
6938 int pseudo_no = REGNO (pseudo);
6939 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6941 /* We don't need to test full validity of last_regno for
6942 inherit here; we only want to know if the store actually
6943 matches the pseudo. */
6944 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6945 && reg_reloaded_contents[last_regno] == pseudo_no
6946 && spill_reg_store[last_regno]
6947 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6948 delete_output_reload (insn, j, last_regno);
6953 || rl->reg_rtx == old
6954 || rl->reg_rtx == 0)
6957 /* An output operand that dies right away does need a reload,
6958 but need not be copied from it. Show the new location in the
6960 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6961 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6963 XEXP (note, 0) = rl->reg_rtx;
6966 /* Likewise for a SUBREG of an operand that dies. */
6967 else if (GET_CODE (old) == SUBREG
6968 && GET_CODE (SUBREG_REG (old)) == REG
6969 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6972 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6976 else if (GET_CODE (old) == SCRATCH)
6977 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6978 but we don't want to make an output reload. */
6981 /* If is a JUMP_INSN, we can't support output reloads yet. */
6982 if (GET_CODE (insn) == JUMP_INSN)
6985 emit_output_reload_insns (chain, rld + j, j);
6988 /* Output insns to reload values in and out of the chosen reload regs. */
6991 emit_reload_insns (chain)
6992 struct insn_chain *chain;
6994 rtx insn = chain->insn;
6998 CLEAR_HARD_REG_SET (reg_reloaded_died);
7000 for (j = 0; j < reload_n_operands; j++)
7001 input_reload_insns[j] = input_address_reload_insns[j]
7002 = inpaddr_address_reload_insns[j]
7003 = output_reload_insns[j] = output_address_reload_insns[j]
7004 = outaddr_address_reload_insns[j]
7005 = other_output_reload_insns[j] = 0;
7006 other_input_address_reload_insns = 0;
7007 other_input_reload_insns = 0;
7008 operand_reload_insns = 0;
7009 other_operand_reload_insns = 0;
7011 /* Dump reloads into the dump file. */
7014 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7015 debug_reload_to_stream (rtl_dump_file);
7018 /* Now output the instructions to copy the data into and out of the
7019 reload registers. Do these in the order that the reloads were reported,
7020 since reloads of base and index registers precede reloads of operands
7021 and the operands may need the base and index registers reloaded. */
7023 for (j = 0; j < n_reloads; j++)
7026 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7027 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7029 do_input_reload (chain, rld + j, j);
7030 do_output_reload (chain, rld + j, j);
7033 /* Now write all the insns we made for reloads in the order expected by
7034 the allocation functions. Prior to the insn being reloaded, we write
7035 the following reloads:
7037 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7039 RELOAD_OTHER reloads.
7041 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7042 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7043 RELOAD_FOR_INPUT reload for the operand.
7045 RELOAD_FOR_OPADDR_ADDRS reloads.
7047 RELOAD_FOR_OPERAND_ADDRESS reloads.
7049 After the insn being reloaded, we write the following:
7051 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7052 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7053 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7054 reloads for the operand. The RELOAD_OTHER output reloads are
7055 output in descending order by reload number. */
7057 emit_insn_before (other_input_address_reload_insns, insn);
7058 emit_insn_before (other_input_reload_insns, insn);
7060 for (j = 0; j < reload_n_operands; j++)
7062 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7063 emit_insn_before (input_address_reload_insns[j], insn);
7064 emit_insn_before (input_reload_insns[j], insn);
7067 emit_insn_before (other_operand_reload_insns, insn);
7068 emit_insn_before (operand_reload_insns, insn);
7070 for (j = 0; j < reload_n_operands; j++)
7072 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7073 x = emit_insn_after (output_address_reload_insns[j], x);
7074 x = emit_insn_after (output_reload_insns[j], x);
7075 emit_insn_after (other_output_reload_insns[j], x);
7078 /* For all the spill regs newly reloaded in this instruction,
7079 record what they were reloaded from, so subsequent instructions
7080 can inherit the reloads.
7082 Update spill_reg_store for the reloads of this insn.
7083 Copy the elements that were updated in the loop above. */
7085 for (j = 0; j < n_reloads; j++)
7087 int r = reload_order[j];
7088 int i = reload_spill_index[r];
7090 /* If this is a non-inherited input reload from a pseudo, we must
7091 clear any memory of a previous store to the same pseudo. Only do
7092 something if there will not be an output reload for the pseudo
7094 if (rld[r].in_reg != 0
7095 && ! (reload_inherited[r] || reload_override_in[r]))
7097 rtx reg = rld[r].in_reg;
7099 if (GET_CODE (reg) == SUBREG)
7100 reg = SUBREG_REG (reg);
7102 if (GET_CODE (reg) == REG
7103 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7104 && ! reg_has_output_reload[REGNO (reg)])
7106 int nregno = REGNO (reg);
7108 if (reg_last_reload_reg[nregno])
7110 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7112 if (reg_reloaded_contents[last_regno] == nregno)
7113 spill_reg_store[last_regno] = 0;
7118 /* I is nonneg if this reload used a register.
7119 If rld[r].reg_rtx is 0, this is an optional reload
7120 that we opted to ignore. */
7122 if (i >= 0 && rld[r].reg_rtx != 0)
7124 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7126 int part_reaches_end = 0;
7127 int all_reaches_end = 1;
7129 /* For a multi register reload, we need to check if all or part
7130 of the value lives to the end. */
7131 for (k = 0; k < nr; k++)
7133 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7134 rld[r].when_needed))
7135 part_reaches_end = 1;
7137 all_reaches_end = 0;
7140 /* Ignore reloads that don't reach the end of the insn in
7142 if (all_reaches_end)
7144 /* First, clear out memory of what used to be in this spill reg.
7145 If consecutive registers are used, clear them all. */
7147 for (k = 0; k < nr; k++)
7148 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7150 /* Maybe the spill reg contains a copy of reload_out. */
7152 && (GET_CODE (rld[r].out) == REG
7156 || GET_CODE (rld[r].out_reg) == REG))
7158 rtx out = (GET_CODE (rld[r].out) == REG
7162 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7163 int nregno = REGNO (out);
7164 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7165 : HARD_REGNO_NREGS (nregno,
7166 GET_MODE (rld[r].reg_rtx)));
7168 spill_reg_store[i] = new_spill_reg_store[i];
7169 spill_reg_stored_to[i] = out;
7170 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7172 /* If NREGNO is a hard register, it may occupy more than
7173 one register. If it does, say what is in the
7174 rest of the registers assuming that both registers
7175 agree on how many words the object takes. If not,
7176 invalidate the subsequent registers. */
7178 if (nregno < FIRST_PSEUDO_REGISTER)
7179 for (k = 1; k < nnr; k++)
7180 reg_last_reload_reg[nregno + k]
7182 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7185 /* Now do the inverse operation. */
7186 for (k = 0; k < nr; k++)
7188 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7189 reg_reloaded_contents[i + k]
7190 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7193 reg_reloaded_insn[i + k] = insn;
7194 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7198 /* Maybe the spill reg contains a copy of reload_in. Only do
7199 something if there will not be an output reload for
7200 the register being reloaded. */
7201 else if (rld[r].out_reg == 0
7203 && ((GET_CODE (rld[r].in) == REG
7204 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7205 && ! reg_has_output_reload[REGNO (rld[r].in)])
7206 || (GET_CODE (rld[r].in_reg) == REG
7207 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7208 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7213 if (GET_CODE (rld[r].in) == REG
7214 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7215 nregno = REGNO (rld[r].in);
7216 else if (GET_CODE (rld[r].in_reg) == REG)
7217 nregno = REGNO (rld[r].in_reg);
7219 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7221 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7222 : HARD_REGNO_NREGS (nregno,
7223 GET_MODE (rld[r].reg_rtx)));
7225 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7227 if (nregno < FIRST_PSEUDO_REGISTER)
7228 for (k = 1; k < nnr; k++)
7229 reg_last_reload_reg[nregno + k]
7231 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7234 /* Unless we inherited this reload, show we haven't
7235 recently done a store.
7236 Previous stores of inherited auto_inc expressions
7237 also have to be discarded. */
7238 if (! reload_inherited[r]
7239 || (rld[r].out && ! rld[r].out_reg))
7240 spill_reg_store[i] = 0;
7242 for (k = 0; k < nr; k++)
7244 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7245 reg_reloaded_contents[i + k]
7246 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7249 reg_reloaded_insn[i + k] = insn;
7250 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7255 /* However, if part of the reload reaches the end, then we must
7256 invalidate the old info for the part that survives to the end. */
7257 else if (part_reaches_end)
7259 for (k = 0; k < nr; k++)
7260 if (reload_reg_reaches_end_p (i + k,
7262 rld[r].when_needed))
7263 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7267 /* The following if-statement was #if 0'd in 1.34 (or before...).
7268 It's reenabled in 1.35 because supposedly nothing else
7269 deals with this problem. */
7271 /* If a register gets output-reloaded from a non-spill register,
7272 that invalidates any previous reloaded copy of it.
7273 But forget_old_reloads_1 won't get to see it, because
7274 it thinks only about the original insn. So invalidate it here. */
7275 if (i < 0 && rld[r].out != 0
7276 && (GET_CODE (rld[r].out) == REG
7277 || (GET_CODE (rld[r].out) == MEM
7278 && GET_CODE (rld[r].out_reg) == REG)))
7280 rtx out = (GET_CODE (rld[r].out) == REG
7281 ? rld[r].out : rld[r].out_reg);
7282 int nregno = REGNO (out);
7283 if (nregno >= FIRST_PSEUDO_REGISTER)
7285 rtx src_reg, store_insn = NULL_RTX;
7287 reg_last_reload_reg[nregno] = 0;
7289 /* If we can find a hard register that is stored, record
7290 the storing insn so that we may delete this insn with
7291 delete_output_reload. */
7292 src_reg = rld[r].reg_rtx;
7294 /* If this is an optional reload, try to find the source reg
7295 from an input reload. */
7298 rtx set = single_set (insn);
7299 if (set && SET_DEST (set) == rld[r].out)
7303 src_reg = SET_SRC (set);
7305 for (k = 0; k < n_reloads; k++)
7307 if (rld[k].in == src_reg)
7309 src_reg = rld[k].reg_rtx;
7316 store_insn = new_spill_reg_store[REGNO (src_reg)];
7317 if (src_reg && GET_CODE (src_reg) == REG
7318 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7320 int src_regno = REGNO (src_reg);
7321 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7322 /* The place where to find a death note varies with
7323 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7324 necessarily checked exactly in the code that moves
7325 notes, so just check both locations. */
7326 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7327 if (! note && store_insn)
7328 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7331 spill_reg_store[src_regno + nr] = store_insn;
7332 spill_reg_stored_to[src_regno + nr] = out;
7333 reg_reloaded_contents[src_regno + nr] = nregno;
7334 reg_reloaded_insn[src_regno + nr] = store_insn;
7335 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7336 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7337 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7339 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7341 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7343 reg_last_reload_reg[nregno] = src_reg;
7348 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7350 while (num_regs-- > 0)
7351 reg_last_reload_reg[nregno + num_regs] = 0;
7355 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7358 /* Emit code to perform a reload from IN (which may be a reload register) to
7359 OUT (which may also be a reload register). IN or OUT is from operand
7360 OPNUM with reload type TYPE.
7362 Returns first insn emitted. */
7365 gen_reload (out, in, opnum, type)
7369 enum reload_type type;
7371 rtx last = get_last_insn ();
7374 /* If IN is a paradoxical SUBREG, remove it and try to put the
7375 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7376 if (GET_CODE (in) == SUBREG
7377 && (GET_MODE_SIZE (GET_MODE (in))
7378 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7379 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7380 in = SUBREG_REG (in), out = tem;
7381 else if (GET_CODE (out) == SUBREG
7382 && (GET_MODE_SIZE (GET_MODE (out))
7383 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7384 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7385 out = SUBREG_REG (out), in = tem;
7387 /* How to do this reload can get quite tricky. Normally, we are being
7388 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7389 register that didn't get a hard register. In that case we can just
7390 call emit_move_insn.
7392 We can also be asked to reload a PLUS that adds a register or a MEM to
7393 another register, constant or MEM. This can occur during frame pointer
7394 elimination and while reloading addresses. This case is handled by
7395 trying to emit a single insn to perform the add. If it is not valid,
7396 we use a two insn sequence.
7398 Finally, we could be called to handle an 'o' constraint by putting
7399 an address into a register. In that case, we first try to do this
7400 with a named pattern of "reload_load_address". If no such pattern
7401 exists, we just emit a SET insn and hope for the best (it will normally
7402 be valid on machines that use 'o').
7404 This entire process is made complex because reload will never
7405 process the insns we generate here and so we must ensure that
7406 they will fit their constraints and also by the fact that parts of
7407 IN might be being reloaded separately and replaced with spill registers.
7408 Because of this, we are, in some sense, just guessing the right approach
7409 here. The one listed above seems to work.
7411 ??? At some point, this whole thing needs to be rethought. */
7413 if (GET_CODE (in) == PLUS
7414 && (GET_CODE (XEXP (in, 0)) == REG
7415 || GET_CODE (XEXP (in, 0)) == SUBREG
7416 || GET_CODE (XEXP (in, 0)) == MEM)
7417 && (GET_CODE (XEXP (in, 1)) == REG
7418 || GET_CODE (XEXP (in, 1)) == SUBREG
7419 || CONSTANT_P (XEXP (in, 1))
7420 || GET_CODE (XEXP (in, 1)) == MEM))
7422 /* We need to compute the sum of a register or a MEM and another
7423 register, constant, or MEM, and put it into the reload
7424 register. The best possible way of doing this is if the machine
7425 has a three-operand ADD insn that accepts the required operands.
7427 The simplest approach is to try to generate such an insn and see if it
7428 is recognized and matches its constraints. If so, it can be used.
7430 It might be better not to actually emit the insn unless it is valid,
7431 but we need to pass the insn as an operand to `recog' and
7432 `extract_insn' and it is simpler to emit and then delete the insn if
7433 not valid than to dummy things up. */
7435 rtx op0, op1, tem, insn;
7438 op0 = find_replacement (&XEXP (in, 0));
7439 op1 = find_replacement (&XEXP (in, 1));
7441 /* Since constraint checking is strict, commutativity won't be
7442 checked, so we need to do that here to avoid spurious failure
7443 if the add instruction is two-address and the second operand
7444 of the add is the same as the reload reg, which is frequently
7445 the case. If the insn would be A = B + A, rearrange it so
7446 it will be A = A + B as constrain_operands expects. */
7448 if (GET_CODE (XEXP (in, 1)) == REG
7449 && REGNO (out) == REGNO (XEXP (in, 1)))
7450 tem = op0, op0 = op1, op1 = tem;
7452 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7453 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7455 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7456 code = recog_memoized (insn);
7460 extract_insn (insn);
7461 /* We want constrain operands to treat this insn strictly in
7462 its validity determination, i.e., the way it would after reload
7464 if (constrain_operands (1))
7468 delete_insns_since (last);
7470 /* If that failed, we must use a conservative two-insn sequence.
7472 Use a move to copy one operand into the reload register. Prefer
7473 to reload a constant, MEM or pseudo since the move patterns can
7474 handle an arbitrary operand. If OP1 is not a constant, MEM or
7475 pseudo and OP1 is not a valid operand for an add instruction, then
7478 After reloading one of the operands into the reload register, add
7479 the reload register to the output register.
7481 If there is another way to do this for a specific machine, a
7482 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7485 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7487 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7488 || (GET_CODE (op1) == REG
7489 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7490 || (code != CODE_FOR_nothing
7491 && ! ((*insn_data[code].operand[2].predicate)
7492 (op1, insn_data[code].operand[2].mode))))
7493 tem = op0, op0 = op1, op1 = tem;
7495 gen_reload (out, op0, opnum, type);
7497 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7498 This fixes a problem on the 32K where the stack pointer cannot
7499 be used as an operand of an add insn. */
7501 if (rtx_equal_p (op0, op1))
7504 insn = emit_insn (gen_add2_insn (out, op1));
7506 /* If that failed, copy the address register to the reload register.
7507 Then add the constant to the reload register. */
7509 code = recog_memoized (insn);
7513 extract_insn (insn);
7514 /* We want constrain operands to treat this insn strictly in
7515 its validity determination, i.e., the way it would after reload
7517 if (constrain_operands (1))
7519 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7521 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7526 delete_insns_since (last);
7528 gen_reload (out, op1, opnum, type);
7529 insn = emit_insn (gen_add2_insn (out, op0));
7530 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7533 #ifdef SECONDARY_MEMORY_NEEDED
7534 /* If we need a memory location to do the move, do it that way. */
7535 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7536 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7537 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7538 REGNO_REG_CLASS (REGNO (out)),
7541 /* Get the memory to use and rewrite both registers to its mode. */
7542 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7544 if (GET_MODE (loc) != GET_MODE (out))
7545 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7547 if (GET_MODE (loc) != GET_MODE (in))
7548 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7550 gen_reload (loc, in, opnum, type);
7551 gen_reload (out, loc, opnum, type);
7555 /* If IN is a simple operand, use gen_move_insn. */
7556 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7557 emit_insn (gen_move_insn (out, in));
7559 #ifdef HAVE_reload_load_address
7560 else if (HAVE_reload_load_address)
7561 emit_insn (gen_reload_load_address (out, in));
7564 /* Otherwise, just write (set OUT IN) and hope for the best. */
7566 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7568 /* Return the first insn emitted.
7569 We can not just return get_last_insn, because there may have
7570 been multiple instructions emitted. Also note that gen_move_insn may
7571 emit more than one insn itself, so we can not assume that there is one
7572 insn emitted per emit_insn_before call. */
7574 return last ? NEXT_INSN (last) : get_insns ();
7577 /* Delete a previously made output-reload whose result we now believe
7578 is not needed. First we double-check.
7580 INSN is the insn now being processed.
7581 LAST_RELOAD_REG is the hard register number for which we want to delete
7582 the last output reload.
7583 J is the reload-number that originally used REG. The caller has made
7584 certain that reload J doesn't use REG any longer for input. */
7587 delete_output_reload (insn, j, last_reload_reg)
7590 int last_reload_reg;
7592 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7593 rtx reg = spill_reg_stored_to[last_reload_reg];
7596 int n_inherited = 0;
7600 /* Get the raw pseudo-register referred to. */
7602 while (GET_CODE (reg) == SUBREG)
7603 reg = SUBREG_REG (reg);
7604 substed = reg_equiv_memory_loc[REGNO (reg)];
7606 /* This is unsafe if the operand occurs more often in the current
7607 insn than it is inherited. */
7608 for (k = n_reloads - 1; k >= 0; k--)
7610 rtx reg2 = rld[k].in;
7613 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7614 reg2 = rld[k].in_reg;
7616 if (rld[k].out && ! rld[k].out_reg)
7617 reg2 = XEXP (rld[k].in_reg, 0);
7619 while (GET_CODE (reg2) == SUBREG)
7620 reg2 = SUBREG_REG (reg2);
7621 if (rtx_equal_p (reg2, reg))
7623 if (reload_inherited[k] || reload_override_in[k] || k == j)
7626 reg2 = rld[k].out_reg;
7629 while (GET_CODE (reg2) == SUBREG)
7630 reg2 = XEXP (reg2, 0);
7631 if (rtx_equal_p (reg2, reg))
7638 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7640 n_occurrences += count_occurrences (PATTERN (insn),
7641 eliminate_regs (substed, 0,
7643 if (n_occurrences > n_inherited)
7646 /* If the pseudo-reg we are reloading is no longer referenced
7647 anywhere between the store into it and here,
7648 and no jumps or labels intervene, then the value can get
7649 here through the reload reg alone.
7650 Otherwise, give up--return. */
7651 for (i1 = NEXT_INSN (output_reload_insn);
7652 i1 != insn; i1 = NEXT_INSN (i1))
7654 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7656 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7657 && reg_mentioned_p (reg, PATTERN (i1)))
7659 /* If this is USE in front of INSN, we only have to check that
7660 there are no more references than accounted for by inheritance. */
7661 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7663 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7664 i1 = NEXT_INSN (i1);
7666 if (n_occurrences <= n_inherited && i1 == insn)
7672 /* We will be deleting the insn. Remove the spill reg information. */
7673 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7675 spill_reg_store[last_reload_reg + k] = 0;
7676 spill_reg_stored_to[last_reload_reg + k] = 0;
7679 /* The caller has already checked that REG dies or is set in INSN.
7680 It has also checked that we are optimizing, and thus some
7681 inaccurancies in the debugging information are acceptable.
7682 So we could just delete output_reload_insn. But in some cases
7683 we can improve the debugging information without sacrificing
7684 optimization - maybe even improving the code: See if the pseudo
7685 reg has been completely replaced with reload regs. If so, delete
7686 the store insn and forget we had a stack slot for the pseudo. */
7687 if (rld[j].out != rld[j].in
7688 && REG_N_DEATHS (REGNO (reg)) == 1
7689 && REG_N_SETS (REGNO (reg)) == 1
7690 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7691 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7695 /* We know that it was used only between here and the beginning of
7696 the current basic block. (We also know that the last use before
7697 INSN was the output reload we are thinking of deleting, but never
7698 mind that.) Search that range; see if any ref remains. */
7699 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7701 rtx set = single_set (i2);
7703 /* Uses which just store in the pseudo don't count,
7704 since if they are the only uses, they are dead. */
7705 if (set != 0 && SET_DEST (set) == reg)
7707 if (GET_CODE (i2) == CODE_LABEL
7708 || GET_CODE (i2) == JUMP_INSN)
7710 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7711 && reg_mentioned_p (reg, PATTERN (i2)))
7713 /* Some other ref remains; just delete the output reload we
7715 delete_address_reloads (output_reload_insn, insn);
7716 delete_insn (output_reload_insn);
7721 /* Delete the now-dead stores into this pseudo. Note that this
7722 loop also takes care of deleting output_reload_insn. */
7723 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7725 rtx set = single_set (i2);
7727 if (set != 0 && SET_DEST (set) == reg)
7729 delete_address_reloads (i2, insn);
7732 if (GET_CODE (i2) == CODE_LABEL
7733 || GET_CODE (i2) == JUMP_INSN)
7737 /* For the debugging info, say the pseudo lives in this reload reg. */
7738 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7739 alter_reg (REGNO (reg), -1);
7743 delete_address_reloads (output_reload_insn, insn);
7744 delete_insn (output_reload_insn);
7748 /* We are going to delete DEAD_INSN. Recursively delete loads of
7749 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7750 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7752 delete_address_reloads (dead_insn, current_insn)
7753 rtx dead_insn, current_insn;
7755 rtx set = single_set (dead_insn);
7756 rtx set2, dst, prev, next;
7759 rtx dst = SET_DEST (set);
7760 if (GET_CODE (dst) == MEM)
7761 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7763 /* If we deleted the store from a reloaded post_{in,de}c expression,
7764 we can delete the matching adds. */
7765 prev = PREV_INSN (dead_insn);
7766 next = NEXT_INSN (dead_insn);
7767 if (! prev || ! next)
7769 set = single_set (next);
7770 set2 = single_set (prev);
7772 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7773 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7774 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7776 dst = SET_DEST (set);
7777 if (! rtx_equal_p (dst, SET_DEST (set2))
7778 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7779 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7780 || (INTVAL (XEXP (SET_SRC (set), 1))
7781 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7783 delete_related_insns (prev);
7784 delete_related_insns (next);
7787 /* Subfunction of delete_address_reloads: process registers found in X. */
7789 delete_address_reloads_1 (dead_insn, x, current_insn)
7790 rtx dead_insn, x, current_insn;
7792 rtx prev, set, dst, i2;
7794 enum rtx_code code = GET_CODE (x);
7798 const char *fmt = GET_RTX_FORMAT (code);
7799 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7802 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7803 else if (fmt[i] == 'E')
7805 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7806 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7813 if (spill_reg_order[REGNO (x)] < 0)
7816 /* Scan backwards for the insn that sets x. This might be a way back due
7818 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7820 code = GET_CODE (prev);
7821 if (code == CODE_LABEL || code == JUMP_INSN)
7823 if (GET_RTX_CLASS (code) != 'i')
7825 if (reg_set_p (x, PATTERN (prev)))
7827 if (reg_referenced_p (x, PATTERN (prev)))
7830 if (! prev || INSN_UID (prev) < reload_first_uid)
7832 /* Check that PREV only sets the reload register. */
7833 set = single_set (prev);
7836 dst = SET_DEST (set);
7837 if (GET_CODE (dst) != REG
7838 || ! rtx_equal_p (dst, x))
7840 if (! reg_set_p (dst, PATTERN (dead_insn)))
7842 /* Check if DST was used in a later insn -
7843 it might have been inherited. */
7844 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7846 if (GET_CODE (i2) == CODE_LABEL)
7850 if (reg_referenced_p (dst, PATTERN (i2)))
7852 /* If there is a reference to the register in the current insn,
7853 it might be loaded in a non-inherited reload. If no other
7854 reload uses it, that means the register is set before
7856 if (i2 == current_insn)
7858 for (j = n_reloads - 1; j >= 0; j--)
7859 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7860 || reload_override_in[j] == dst)
7862 for (j = n_reloads - 1; j >= 0; j--)
7863 if (rld[j].in && rld[j].reg_rtx == dst)
7870 if (GET_CODE (i2) == JUMP_INSN)
7872 /* If DST is still live at CURRENT_INSN, check if it is used for
7873 any reload. Note that even if CURRENT_INSN sets DST, we still
7874 have to check the reloads. */
7875 if (i2 == current_insn)
7877 for (j = n_reloads - 1; j >= 0; j--)
7878 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7879 || reload_override_in[j] == dst)
7881 /* ??? We can't finish the loop here, because dst might be
7882 allocated to a pseudo in this block if no reload in this
7883 block needs any of the clsses containing DST - see
7884 spill_hard_reg. There is no easy way to tell this, so we
7885 have to scan till the end of the basic block. */
7887 if (reg_set_p (dst, PATTERN (i2)))
7891 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7892 reg_reloaded_contents[REGNO (dst)] = -1;
7896 /* Output reload-insns to reload VALUE into RELOADREG.
7897 VALUE is an autoincrement or autodecrement RTX whose operand
7898 is a register or memory location;
7899 so reloading involves incrementing that location.
7900 IN is either identical to VALUE, or some cheaper place to reload from.
7902 INC_AMOUNT is the number to increment or decrement by (always positive).
7903 This cannot be deduced from VALUE.
7905 Return the instruction that stores into RELOADREG. */
7908 inc_for_reload (reloadreg, in, value, inc_amount)
7913 /* REG or MEM to be copied and incremented. */
7914 rtx incloc = XEXP (value, 0);
7915 /* Nonzero if increment after copying. */
7916 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7922 rtx real_in = in == value ? XEXP (in, 0) : in;
7924 /* No hard register is equivalent to this register after
7925 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7926 we could inc/dec that register as well (maybe even using it for
7927 the source), but I'm not sure it's worth worrying about. */
7928 if (GET_CODE (incloc) == REG)
7929 reg_last_reload_reg[REGNO (incloc)] = 0;
7931 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7932 inc_amount = -inc_amount;
7934 inc = GEN_INT (inc_amount);
7936 /* If this is post-increment, first copy the location to the reload reg. */
7937 if (post && real_in != reloadreg)
7938 emit_insn (gen_move_insn (reloadreg, real_in));
7942 /* See if we can directly increment INCLOC. Use a method similar to
7943 that in gen_reload. */
7945 last = get_last_insn ();
7946 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7947 gen_rtx_PLUS (GET_MODE (incloc),
7950 code = recog_memoized (add_insn);
7953 extract_insn (add_insn);
7954 if (constrain_operands (1))
7956 /* If this is a pre-increment and we have incremented the value
7957 where it lives, copy the incremented value to RELOADREG to
7958 be used as an address. */
7961 emit_insn (gen_move_insn (reloadreg, incloc));
7966 delete_insns_since (last);
7969 /* If couldn't do the increment directly, must increment in RELOADREG.
7970 The way we do this depends on whether this is pre- or post-increment.
7971 For pre-increment, copy INCLOC to the reload register, increment it
7972 there, then save back. */
7976 if (in != reloadreg)
7977 emit_insn (gen_move_insn (reloadreg, real_in));
7978 emit_insn (gen_add2_insn (reloadreg, inc));
7979 store = emit_insn (gen_move_insn (incloc, reloadreg));
7984 Because this might be a jump insn or a compare, and because RELOADREG
7985 may not be available after the insn in an input reload, we must do
7986 the incrementation before the insn being reloaded for.
7988 We have already copied IN to RELOADREG. Increment the copy in
7989 RELOADREG, save that back, then decrement RELOADREG so it has
7990 the original value. */
7992 emit_insn (gen_add2_insn (reloadreg, inc));
7993 store = emit_insn (gen_move_insn (incloc, reloadreg));
7994 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8001 /* See whether a single set SET is a noop. */
8003 reload_cse_noop_set_p (set)
8006 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8009 /* Try to simplify INSN. */
8011 reload_cse_simplify (insn, testreg)
8015 rtx body = PATTERN (insn);
8017 if (GET_CODE (body) == SET)
8021 /* Simplify even if we may think it is a no-op.
8022 We may think a memory load of a value smaller than WORD_SIZE
8023 is redundant because we haven't taken into account possible
8024 implicit extension. reload_cse_simplify_set() will bring
8025 this out, so it's safer to simplify before we delete. */
8026 count += reload_cse_simplify_set (body, insn);
8028 if (!count && reload_cse_noop_set_p (body))
8030 rtx value = SET_DEST (body);
8032 && ! REG_FUNCTION_VALUE_P (value))
8034 delete_insn_and_edges (insn);
8039 apply_change_group ();
8041 reload_cse_simplify_operands (insn, testreg);
8043 else if (GET_CODE (body) == PARALLEL)
8047 rtx value = NULL_RTX;
8049 /* If every action in a PARALLEL is a noop, we can delete
8050 the entire PARALLEL. */
8051 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8053 rtx part = XVECEXP (body, 0, i);
8054 if (GET_CODE (part) == SET)
8056 if (! reload_cse_noop_set_p (part))
8058 if (REG_P (SET_DEST (part))
8059 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
8063 value = SET_DEST (part);
8066 else if (GET_CODE (part) != CLOBBER)
8072 delete_insn_and_edges (insn);
8073 /* We're done with this insn. */
8077 /* It's not a no-op, but we can try to simplify it. */
8078 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8079 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8080 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8083 apply_change_group ();
8085 reload_cse_simplify_operands (insn, testreg);
8089 /* Do a very simple CSE pass over the hard registers.
8091 This function detects no-op moves where we happened to assign two
8092 different pseudo-registers to the same hard register, and then
8093 copied one to the other. Reload will generate a useless
8094 instruction copying a register to itself.
8096 This function also detects cases where we load a value from memory
8097 into two different registers, and (if memory is more expensive than
8098 registers) changes it to simply copy the first register into the
8101 Another optimization is performed that scans the operands of each
8102 instruction to see whether the value is already available in a
8103 hard register. It then replaces the operand with the hard register
8104 if possible, much like an optional reload would. */
8107 reload_cse_regs_1 (first)
8111 rtx testreg = gen_rtx_REG (VOIDmode, -1);
8114 init_alias_analysis ();
8116 for (insn = first; insn; insn = NEXT_INSN (insn))
8119 reload_cse_simplify (insn, testreg);
8121 cselib_process_insn (insn);
8125 end_alias_analysis ();
8129 /* Call cse / combine like post-reload optimization phases.
8130 FIRST is the first instruction. */
8132 reload_cse_regs (first)
8135 reload_cse_regs_1 (first);
8137 reload_cse_move2add (first);
8138 if (flag_expensive_optimizations)
8139 reload_cse_regs_1 (first);
8142 /* Try to simplify a single SET instruction. SET is the set pattern.
8143 INSN is the instruction it came from.
8144 This function only handles one case: if we set a register to a value
8145 which is not a register, we try to find that value in some other register
8146 and change the set into a register copy. */
8149 reload_cse_simplify_set (set, insn)
8156 enum reg_class dclass;
8159 struct elt_loc_list *l;
8160 #ifdef LOAD_EXTEND_OP
8161 enum rtx_code extend_op = NIL;
8164 dreg = true_regnum (SET_DEST (set));
8168 src = SET_SRC (set);
8169 if (side_effects_p (src) || true_regnum (src) >= 0)
8172 dclass = REGNO_REG_CLASS (dreg);
8174 #ifdef LOAD_EXTEND_OP
8175 /* When replacing a memory with a register, we need to honor assumptions
8176 that combine made wrt the contents of sign bits. We'll do this by
8177 generating an extend instruction instead of a reg->reg copy. Thus
8178 the destination must be a register that we can widen. */
8179 if (GET_CODE (src) == MEM
8180 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8181 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8182 && GET_CODE (SET_DEST (set)) != REG)
8186 /* If memory loads are cheaper than register copies, don't change them. */
8187 if (GET_CODE (src) == MEM)
8188 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8189 else if (CONSTANT_P (src))
8190 old_cost = rtx_cost (src, SET);
8191 else if (GET_CODE (src) == REG)
8192 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8193 REGNO_REG_CLASS (REGNO (src)), dclass);
8196 old_cost = rtx_cost (src, SET);
8198 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8201 for (l = val->locs; l; l = l->next)
8203 rtx this_rtx = l->loc;
8206 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8208 #ifdef LOAD_EXTEND_OP
8209 if (extend_op != NIL)
8211 HOST_WIDE_INT this_val;
8213 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8214 constants, such as SYMBOL_REF, cannot be extended. */
8215 if (GET_CODE (this_rtx) != CONST_INT)
8218 this_val = INTVAL (this_rtx);
8222 this_val &= GET_MODE_MASK (GET_MODE (src));
8225 /* ??? In theory we're already extended. */
8226 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8231 this_rtx = GEN_INT (this_val);
8234 this_cost = rtx_cost (this_rtx, SET);
8236 else if (GET_CODE (this_rtx) == REG)
8238 #ifdef LOAD_EXTEND_OP
8239 if (extend_op != NIL)
8241 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8242 this_cost = rtx_cost (this_rtx, SET);
8246 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8247 REGNO_REG_CLASS (REGNO (this_rtx)),
8253 /* If equal costs, prefer registers over anything else. That
8254 tends to lead to smaller instructions on some machines. */
8255 if (this_cost < old_cost
8256 || (this_cost == old_cost
8257 && GET_CODE (this_rtx) == REG
8258 && GET_CODE (SET_SRC (set)) != REG))
8260 #ifdef LOAD_EXTEND_OP
8261 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8262 && extend_op != NIL)
8264 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8265 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8266 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8270 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8271 old_cost = this_cost, did_change = 1;
8278 /* Try to replace operands in INSN with equivalent values that are already
8279 in registers. This can be viewed as optional reloading.
8281 For each non-register operand in the insn, see if any hard regs are
8282 known to be equivalent to that operand. Record the alternatives which
8283 can accept these hard registers. Among all alternatives, select the
8284 ones which are better or equal to the one currently matching, where
8285 "better" is in terms of '?' and '!' constraints. Among the remaining
8286 alternatives, select the one which replaces most operands with
8290 reload_cse_simplify_operands (insn, testreg)
8296 /* For each operand, all registers that are equivalent to it. */
8297 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8299 const char *constraints[MAX_RECOG_OPERANDS];
8301 /* Vector recording how bad an alternative is. */
8302 int *alternative_reject;
8303 /* Vector recording how many registers can be introduced by choosing
8304 this alternative. */
8305 int *alternative_nregs;
8306 /* Array of vectors recording, for each operand and each alternative,
8307 which hard register to substitute, or -1 if the operand should be
8309 int *op_alt_regno[MAX_RECOG_OPERANDS];
8310 /* Array of alternatives, sorted in order of decreasing desirability. */
8311 int *alternative_order;
8313 extract_insn (insn);
8315 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8318 /* Figure out which alternative currently matches. */
8319 if (! constrain_operands (1))
8320 fatal_insn_not_found (insn);
8322 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8323 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8324 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8325 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8326 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8328 /* For each operand, find out which regs are equivalent. */
8329 for (i = 0; i < recog_data.n_operands; i++)
8332 struct elt_loc_list *l;
8334 CLEAR_HARD_REG_SET (equiv_regs[i]);
8336 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8337 right, so avoid the problem here. Likewise if we have a constant
8338 and the insn pattern doesn't tell us the mode we need. */
8339 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8340 || (CONSTANT_P (recog_data.operand[i])
8341 && recog_data.operand_mode[i] == VOIDmode))
8344 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8348 for (l = v->locs; l; l = l->next)
8349 if (GET_CODE (l->loc) == REG)
8350 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8353 for (i = 0; i < recog_data.n_operands; i++)
8355 enum machine_mode mode;
8359 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8360 for (j = 0; j < recog_data.n_alternatives; j++)
8361 op_alt_regno[i][j] = -1;
8363 p = constraints[i] = recog_data.constraints[i];
8364 mode = recog_data.operand_mode[i];
8366 /* Add the reject values for each alternative given by the constraints
8367 for this operand. */
8375 alternative_reject[j] += 3;
8377 alternative_reject[j] += 300;
8380 /* We won't change operands which are already registers. We
8381 also don't want to modify output operands. */
8382 regno = true_regnum (recog_data.operand[i]);
8384 || constraints[i][0] == '='
8385 || constraints[i][0] == '+')
8388 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8390 int class = (int) NO_REGS;
8392 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8395 REGNO (testreg) = regno;
8396 PUT_MODE (testreg, mode);
8398 /* We found a register equal to this operand. Now look for all
8399 alternatives that can accept this register and have not been
8400 assigned a register they can use yet. */
8409 case '=': case '+': case '?':
8410 case '#': case '&': case '!':
8412 case '0': case '1': case '2': case '3': case '4':
8413 case '5': case '6': case '7': case '8': case '9':
8414 case 'm': case '<': case '>': case 'V': case 'o':
8415 case 'E': case 'F': case 'G': case 'H':
8416 case 's': case 'i': case 'n':
8417 case 'I': case 'J': case 'K': case 'L':
8418 case 'M': case 'N': case 'O': case 'P':
8420 /* These don't say anything we care about. */
8424 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8429 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)];
8432 case ',': case '\0':
8433 /* See if REGNO fits this alternative, and set it up as the
8434 replacement register if we don't have one for this
8435 alternative yet and the operand being replaced is not
8436 a cheap CONST_INT. */
8437 if (op_alt_regno[i][j] == -1
8438 && reg_fits_class_p (testreg, class, 0, mode)
8439 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8440 || (rtx_cost (recog_data.operand[i], SET)
8441 > rtx_cost (testreg, SET))))
8443 alternative_nregs[j]++;
8444 op_alt_regno[i][j] = regno;
8456 /* Record all alternatives which are better or equal to the currently
8457 matching one in the alternative_order array. */
8458 for (i = j = 0; i < recog_data.n_alternatives; i++)
8459 if (alternative_reject[i] <= alternative_reject[which_alternative])
8460 alternative_order[j++] = i;
8461 recog_data.n_alternatives = j;
8463 /* Sort it. Given a small number of alternatives, a dumb algorithm
8464 won't hurt too much. */
8465 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8468 int best_reject = alternative_reject[alternative_order[i]];
8469 int best_nregs = alternative_nregs[alternative_order[i]];
8472 for (j = i + 1; j < recog_data.n_alternatives; j++)
8474 int this_reject = alternative_reject[alternative_order[j]];
8475 int this_nregs = alternative_nregs[alternative_order[j]];
8477 if (this_reject < best_reject
8478 || (this_reject == best_reject && this_nregs < best_nregs))
8481 best_reject = this_reject;
8482 best_nregs = this_nregs;
8486 tmp = alternative_order[best];
8487 alternative_order[best] = alternative_order[i];
8488 alternative_order[i] = tmp;
8491 /* Substitute the operands as determined by op_alt_regno for the best
8493 j = alternative_order[0];
8495 for (i = 0; i < recog_data.n_operands; i++)
8497 enum machine_mode mode = recog_data.operand_mode[i];
8498 if (op_alt_regno[i][j] == -1)
8501 validate_change (insn, recog_data.operand_loc[i],
8502 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8505 for (i = recog_data.n_dups - 1; i >= 0; i--)
8507 int op = recog_data.dup_num[i];
8508 enum machine_mode mode = recog_data.operand_mode[op];
8510 if (op_alt_regno[op][j] == -1)
8513 validate_change (insn, recog_data.dup_loc[i],
8514 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8517 return apply_change_group ();
8520 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8522 This code might also be useful when reload gave up on reg+reg addresssing
8523 because of clashes between the return register and INDEX_REG_CLASS. */
8525 /* The maximum number of uses of a register we can keep track of to
8526 replace them with reg+reg addressing. */
8527 #define RELOAD_COMBINE_MAX_USES 6
8529 /* INSN is the insn where a register has ben used, and USEP points to the
8530 location of the register within the rtl. */
8531 struct reg_use { rtx insn, *usep; };
8533 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8534 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8535 indicates where it becomes live again.
8536 Otherwise, USE_INDEX is the index of the last encountered use of the
8537 register (which is first among these we have seen since we scan backwards),
8538 OFFSET contains the constant offset that is added to the register in
8539 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8540 last, of these uses.
8541 STORE_RUID is always meaningful if we only want to use a value in a
8542 register in a different place: it denotes the next insn in the insn
8543 stream (i.e. the last ecountered) that sets or clobbers the register. */
8546 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8551 } reg_state[FIRST_PSEUDO_REGISTER];
8553 /* Reverse linear uid. This is increased in reload_combine while scanning
8554 the instructions from last to first. It is used to set last_label_ruid
8555 and the store_ruid / use_ruid fields in reg_state. */
8556 static int reload_combine_ruid;
8558 #define LABEL_LIVE(LABEL) \
8559 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8565 int first_index_reg = -1;
8566 int last_index_reg = 0;
8570 int last_label_ruid;
8571 int min_labelno, n_labels;
8572 HARD_REG_SET ever_live_at_start, *label_live;
8574 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8575 reload has already used it where appropriate, so there is no use in
8576 trying to generate it now. */
8577 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8580 /* To avoid wasting too much time later searching for an index register,
8581 determine the minimum and maximum index register numbers. */
8582 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8583 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8585 if (first_index_reg == -1)
8586 first_index_reg = r;
8591 /* If no index register is available, we can quit now. */
8592 if (first_index_reg == -1)
8595 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8596 information is a bit fuzzy immediately after reload, but it's
8597 still good enough to determine which registers are live at a jump
8599 min_labelno = get_first_label_num ();
8600 n_labels = max_label_num () - min_labelno;
8601 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8602 CLEAR_HARD_REG_SET (ever_live_at_start);
8604 FOR_EACH_BB_REVERSE (bb)
8607 if (GET_CODE (insn) == CODE_LABEL)
8611 REG_SET_TO_HARD_REG_SET (live,
8612 bb->global_live_at_start);
8613 compute_use_by_pseudos (&live,
8614 bb->global_live_at_start);
8615 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8616 IOR_HARD_REG_SET (ever_live_at_start, live);
8620 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8621 last_label_ruid = reload_combine_ruid = 0;
8622 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8624 reg_state[r].store_ruid = reload_combine_ruid;
8626 reg_state[r].use_index = -1;
8628 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8631 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8635 /* We cannot do our optimization across labels. Invalidating all the use
8636 information we have would be costly, so we just note where the label
8637 is and then later disable any optimization that would cross it. */
8638 if (GET_CODE (insn) == CODE_LABEL)
8639 last_label_ruid = reload_combine_ruid;
8640 else if (GET_CODE (insn) == BARRIER)
8641 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8642 if (! fixed_regs[r])
8643 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8645 if (! INSN_P (insn))
8648 reload_combine_ruid++;
8650 /* Look for (set (REGX) (CONST_INT))
8651 (set (REGX) (PLUS (REGX) (REGY)))
8653 ... (MEM (REGX)) ...
8655 (set (REGZ) (CONST_INT))
8657 ... (MEM (PLUS (REGZ) (REGY)))... .
8659 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8660 and that we know all uses of REGX before it dies. */
8661 set = single_set (insn);
8663 && GET_CODE (SET_DEST (set)) == REG
8664 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8665 GET_MODE (SET_DEST (set)))
8667 && GET_CODE (SET_SRC (set)) == PLUS
8668 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8669 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8670 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8672 rtx reg = SET_DEST (set);
8673 rtx plus = SET_SRC (set);
8674 rtx base = XEXP (plus, 1);
8675 rtx prev = prev_nonnote_insn (insn);
8676 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8677 unsigned int regno = REGNO (reg);
8678 rtx const_reg = NULL_RTX;
8679 rtx reg_sum = NULL_RTX;
8681 /* Now, we need an index register.
8682 We'll set index_reg to this index register, const_reg to the
8683 register that is to be loaded with the constant
8684 (denoted as REGZ in the substitution illustration above),
8685 and reg_sum to the register-register that we want to use to
8686 substitute uses of REG (typically in MEMs) with.
8687 First check REG and BASE for being index registers;
8688 we can use them even if they are not dead. */
8689 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8690 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8698 /* Otherwise, look for a free index register. Since we have
8699 checked above that neiter REG nor BASE are index registers,
8700 if we find anything at all, it will be different from these
8702 for (i = first_index_reg; i <= last_index_reg; i++)
8704 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8706 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8707 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8708 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8710 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8712 const_reg = index_reg;
8713 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8719 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8720 (REGY), i.e. BASE, is not clobbered before the last use we'll
8723 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8724 && rtx_equal_p (SET_DEST (prev_set), reg)
8725 && reg_state[regno].use_index >= 0
8726 && (reg_state[REGNO (base)].store_ruid
8727 <= reg_state[regno].use_ruid)
8732 /* Change destination register and, if necessary, the
8733 constant value in PREV, the constant loading instruction. */
8734 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8735 if (reg_state[regno].offset != const0_rtx)
8736 validate_change (prev,
8737 &SET_SRC (prev_set),
8738 GEN_INT (INTVAL (SET_SRC (prev_set))
8739 + INTVAL (reg_state[regno].offset)),
8742 /* Now for every use of REG that we have recorded, replace REG
8744 for (i = reg_state[regno].use_index;
8745 i < RELOAD_COMBINE_MAX_USES; i++)
8746 validate_change (reg_state[regno].reg_use[i].insn,
8747 reg_state[regno].reg_use[i].usep,
8748 /* Each change must have its own
8750 copy_rtx (reg_sum), 1);
8752 if (apply_change_group ())
8756 /* Delete the reg-reg addition. */
8759 if (reg_state[regno].offset != const0_rtx)
8760 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8762 for (np = ®_NOTES (prev); *np;)
8764 if (REG_NOTE_KIND (*np) == REG_EQUAL
8765 || REG_NOTE_KIND (*np) == REG_EQUIV)
8766 *np = XEXP (*np, 1);
8768 np = &XEXP (*np, 1);
8771 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8772 reg_state[REGNO (const_reg)].store_ruid
8773 = reload_combine_ruid;
8779 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8781 if (GET_CODE (insn) == CALL_INSN)
8785 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8786 if (call_used_regs[r])
8788 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8789 reg_state[r].store_ruid = reload_combine_ruid;
8792 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8793 link = XEXP (link, 1))
8795 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8796 if (GET_CODE (usage_rtx) == REG)
8799 unsigned int start_reg = REGNO (usage_rtx);
8800 unsigned int num_regs =
8801 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8802 unsigned int end_reg = start_reg + num_regs - 1;
8803 for (i = start_reg; i <= end_reg; i++)
8804 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8806 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8807 reg_state[i].store_ruid = reload_combine_ruid;
8810 reg_state[i].use_index = -1;
8815 else if (GET_CODE (insn) == JUMP_INSN
8816 && GET_CODE (PATTERN (insn)) != RETURN)
8818 /* Non-spill registers might be used at the call destination in
8819 some unknown fashion, so we have to mark the unknown use. */
8822 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8823 && JUMP_LABEL (insn))
8824 live = &LABEL_LIVE (JUMP_LABEL (insn));
8826 live = &ever_live_at_start;
8828 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8829 if (TEST_HARD_REG_BIT (*live, i))
8830 reg_state[i].use_index = -1;
8833 reload_combine_note_use (&PATTERN (insn), insn);
8834 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8836 if (REG_NOTE_KIND (note) == REG_INC
8837 && GET_CODE (XEXP (note, 0)) == REG)
8839 int regno = REGNO (XEXP (note, 0));
8841 reg_state[regno].store_ruid = reload_combine_ruid;
8842 reg_state[regno].use_index = -1;
8850 /* Check if DST is a register or a subreg of a register; if it is,
8851 update reg_state[regno].store_ruid and reg_state[regno].use_index
8852 accordingly. Called via note_stores from reload_combine. */
8855 reload_combine_note_store (dst, set, data)
8857 void *data ATTRIBUTE_UNUSED;
8861 enum machine_mode mode = GET_MODE (dst);
8863 if (GET_CODE (dst) == SUBREG)
8865 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8866 GET_MODE (SUBREG_REG (dst)),
8869 dst = SUBREG_REG (dst);
8871 if (GET_CODE (dst) != REG)
8873 regno += REGNO (dst);
8875 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8876 careful with registers / register parts that are not full words.
8878 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8879 if (GET_CODE (set) != SET
8880 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8881 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8882 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8884 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8886 reg_state[i].use_index = -1;
8887 reg_state[i].store_ruid = reload_combine_ruid;
8892 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8894 reg_state[i].store_ruid = reload_combine_ruid;
8895 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8900 /* XP points to a piece of rtl that has to be checked for any uses of
8902 *XP is the pattern of INSN, or a part of it.
8903 Called from reload_combine, and recursively by itself. */
8905 reload_combine_note_use (xp, insn)
8909 enum rtx_code code = x->code;
8912 rtx offset = const0_rtx; /* For the REG case below. */
8917 if (GET_CODE (SET_DEST (x)) == REG)
8919 reload_combine_note_use (&SET_SRC (x), insn);
8925 /* If this is the USE of a return value, we can't change it. */
8926 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8928 /* Mark the return register as used in an unknown fashion. */
8929 rtx reg = XEXP (x, 0);
8930 int regno = REGNO (reg);
8931 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8933 while (--nregs >= 0)
8934 reg_state[regno + nregs].use_index = -1;
8940 if (GET_CODE (SET_DEST (x)) == REG)
8942 /* No spurious CLOBBERs of pseudo registers may remain. */
8943 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8950 /* We are interested in (plus (reg) (const_int)) . */
8951 if (GET_CODE (XEXP (x, 0)) != REG
8952 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8954 offset = XEXP (x, 1);
8959 int regno = REGNO (x);
8963 /* No spurious USEs of pseudo registers may remain. */
8964 if (regno >= FIRST_PSEUDO_REGISTER)
8967 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8969 /* We can't substitute into multi-hard-reg uses. */
8972 while (--nregs >= 0)
8973 reg_state[regno + nregs].use_index = -1;
8977 /* If this register is already used in some unknown fashion, we
8979 If we decrement the index from zero to -1, we can't store more
8980 uses, so this register becomes used in an unknown fashion. */
8981 use_index = --reg_state[regno].use_index;
8985 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8987 /* We have found another use for a register that is already
8988 used later. Check if the offsets match; if not, mark the
8989 register as used in an unknown fashion. */
8990 if (! rtx_equal_p (offset, reg_state[regno].offset))
8992 reg_state[regno].use_index = -1;
8998 /* This is the first use of this register we have seen since we
8999 marked it as dead. */
9000 reg_state[regno].offset = offset;
9001 reg_state[regno].use_ruid = reload_combine_ruid;
9003 reg_state[regno].reg_use[use_index].insn = insn;
9004 reg_state[regno].reg_use[use_index].usep = xp;
9012 /* Recursively process the components of X. */
9013 fmt = GET_RTX_FORMAT (code);
9014 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9017 reload_combine_note_use (&XEXP (x, i), insn);
9018 else if (fmt[i] == 'E')
9020 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9021 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9026 /* See if we can reduce the cost of a constant by replacing a move
9027 with an add. We track situations in which a register is set to a
9028 constant or to a register plus a constant. */
9029 /* We cannot do our optimization across labels. Invalidating all the
9030 information about register contents we have would be costly, so we
9031 use move2add_last_label_luid to note where the label is and then
9032 later disable any optimization that would cross it.
9033 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9034 reg_set_luid[n] is greater than last_label_luid[n] . */
9035 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9037 /* If reg_base_reg[n] is negative, register n has been set to
9038 reg_offset[n] in mode reg_mode[n] .
9039 If reg_base_reg[n] is non-negative, register n has been set to the
9040 sum of reg_offset[n] and the value of register reg_base_reg[n]
9041 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9042 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9043 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9044 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9046 /* move2add_luid is linearily increased while scanning the instructions
9047 from first to last. It is used to set reg_set_luid in
9048 reload_cse_move2add and move2add_note_store. */
9049 static int move2add_luid;
9051 /* move2add_last_label_luid is set whenever a label is found. Labels
9052 invalidate all previously collected reg_offset data. */
9053 static int move2add_last_label_luid;
9055 /* Generate a CONST_INT and force it in the range of MODE. */
9057 static HOST_WIDE_INT
9058 sext_for_mode (mode, value)
9059 enum machine_mode mode;
9060 HOST_WIDE_INT value;
9062 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9063 int width = GET_MODE_BITSIZE (mode);
9065 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9067 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9068 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9069 cval |= (HOST_WIDE_INT) -1 << width;
9074 /* ??? We don't know how zero / sign extension is handled, hence we
9075 can't go from a narrower to a wider mode. */
9076 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9077 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9078 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9079 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9080 GET_MODE_BITSIZE (INMODE))))
9083 reload_cse_move2add (first)
9089 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9090 reg_set_luid[i] = 0;
9092 move2add_last_label_luid = 0;
9094 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9098 if (GET_CODE (insn) == CODE_LABEL)
9100 move2add_last_label_luid = move2add_luid;
9101 /* We're going to increment move2add_luid twice after a
9102 label, so that we can use move2add_last_label_luid + 1 as
9103 the luid for constants. */
9107 if (! INSN_P (insn))
9109 pat = PATTERN (insn);
9110 /* For simplicity, we only perform this optimization on
9111 straightforward SETs. */
9112 if (GET_CODE (pat) == SET
9113 && GET_CODE (SET_DEST (pat)) == REG)
9115 rtx reg = SET_DEST (pat);
9116 int regno = REGNO (reg);
9117 rtx src = SET_SRC (pat);
9119 /* Check if we have valid information on the contents of this
9120 register in the mode of REG. */
9121 if (reg_set_luid[regno] > move2add_last_label_luid
9122 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9124 /* Try to transform (set (REGX) (CONST_INT A))
9126 (set (REGX) (CONST_INT B))
9128 (set (REGX) (CONST_INT A))
9130 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9132 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9135 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9137 - reg_offset[regno]));
9138 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9139 use (set (reg) (reg)) instead.
9140 We don't delete this insn, nor do we convert it into a
9141 note, to avoid losing register notes or the return
9142 value flag. jump2 already knowns how to get rid of
9144 if (new_src == const0_rtx)
9145 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9146 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9147 && have_add2_insn (reg, new_src))
9148 success = validate_change (insn, &PATTERN (insn),
9149 gen_add2_insn (reg, new_src), 0);
9150 reg_set_luid[regno] = move2add_luid;
9151 reg_mode[regno] = GET_MODE (reg);
9152 reg_offset[regno] = INTVAL (src);
9156 /* Try to transform (set (REGX) (REGY))
9157 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9160 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9163 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9165 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9166 else if (GET_CODE (src) == REG
9167 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9168 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9169 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9170 reg_mode[REGNO (src)]))
9172 rtx next = next_nonnote_insn (insn);
9175 set = single_set (next);
9177 && SET_DEST (set) == reg
9178 && GET_CODE (SET_SRC (set)) == PLUS
9179 && XEXP (SET_SRC (set), 0) == reg
9180 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9182 rtx src3 = XEXP (SET_SRC (set), 1);
9183 HOST_WIDE_INT added_offset = INTVAL (src3);
9184 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9185 HOST_WIDE_INT regno_offset = reg_offset[regno];
9186 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9192 if (new_src == const0_rtx)
9193 /* See above why we create (set (reg) (reg)) here. */
9195 = validate_change (next, &SET_SRC (set), reg, 0);
9196 else if ((rtx_cost (new_src, PLUS)
9197 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9198 && have_add2_insn (reg, new_src))
9200 = validate_change (next, &PATTERN (next),
9201 gen_add2_insn (reg, new_src), 0);
9205 reg_mode[regno] = GET_MODE (reg);
9206 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9215 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9217 if (REG_NOTE_KIND (note) == REG_INC
9218 && GET_CODE (XEXP (note, 0)) == REG)
9220 /* Reset the information about this register. */
9221 int regno = REGNO (XEXP (note, 0));
9222 if (regno < FIRST_PSEUDO_REGISTER)
9223 reg_set_luid[regno] = 0;
9226 note_stores (PATTERN (insn), move2add_note_store, NULL);
9227 /* If this is a CALL_INSN, all call used registers are stored with
9229 if (GET_CODE (insn) == CALL_INSN)
9231 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9233 if (call_used_regs[i])
9234 /* Reset the information about this register. */
9235 reg_set_luid[i] = 0;
9241 /* SET is a SET or CLOBBER that sets DST.
9242 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9243 Called from reload_cse_move2add via note_stores. */
9246 move2add_note_store (dst, set, data)
9248 void *data ATTRIBUTE_UNUSED;
9250 unsigned int regno = 0;
9252 enum machine_mode mode = GET_MODE (dst);
9254 if (GET_CODE (dst) == SUBREG)
9256 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9257 GET_MODE (SUBREG_REG (dst)),
9260 dst = SUBREG_REG (dst);
9263 /* Some targets do argument pushes without adding REG_INC notes. */
9265 if (GET_CODE (dst) == MEM)
9267 dst = XEXP (dst, 0);
9268 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9269 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9270 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9273 if (GET_CODE (dst) != REG)
9276 regno += REGNO (dst);
9278 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9279 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9280 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9281 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9283 rtx src = SET_SRC (set);
9285 HOST_WIDE_INT offset;
9287 /* This may be different from mode, if SET_DEST (set) is a
9289 enum machine_mode dst_mode = GET_MODE (dst);
9291 switch (GET_CODE (src))
9294 if (GET_CODE (XEXP (src, 0)) == REG)
9296 base_reg = XEXP (src, 0);
9298 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9299 offset = INTVAL (XEXP (src, 1));
9300 else if (GET_CODE (XEXP (src, 1)) == REG
9301 && (reg_set_luid[REGNO (XEXP (src, 1))]
9302 > move2add_last_label_luid)
9303 && (MODES_OK_FOR_MOVE2ADD
9304 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9306 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9307 offset = reg_offset[REGNO (XEXP (src, 1))];
9308 /* Maybe the first register is known to be a
9310 else if (reg_set_luid[REGNO (base_reg)]
9311 > move2add_last_label_luid
9312 && (MODES_OK_FOR_MOVE2ADD
9313 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9314 && reg_base_reg[REGNO (base_reg)] < 0)
9316 offset = reg_offset[REGNO (base_reg)];
9317 base_reg = XEXP (src, 1);
9336 /* Start tracking the register as a constant. */
9337 reg_base_reg[regno] = -1;
9338 reg_offset[regno] = INTVAL (SET_SRC (set));
9339 /* We assign the same luid to all registers set to constants. */
9340 reg_set_luid[regno] = move2add_last_label_luid + 1;
9341 reg_mode[regno] = mode;
9346 /* Invalidate the contents of the register. */
9347 reg_set_luid[regno] = 0;
9351 base_regno = REGNO (base_reg);
9352 /* If information about the base register is not valid, set it
9353 up as a new base register, pretending its value is known
9354 starting from the current insn. */
9355 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9357 reg_base_reg[base_regno] = base_regno;
9358 reg_offset[base_regno] = 0;
9359 reg_set_luid[base_regno] = move2add_luid;
9360 reg_mode[base_regno] = mode;
9362 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9363 reg_mode[base_regno]))
9366 reg_mode[regno] = mode;
9368 /* Copy base information from our base register. */
9369 reg_set_luid[regno] = reg_set_luid[base_regno];
9370 reg_base_reg[regno] = reg_base_reg[base_regno];
9372 /* Compute the sum of the offsets or constants. */
9373 reg_offset[regno] = sext_for_mode (dst_mode,
9375 + reg_offset[base_regno]);
9379 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9381 for (i = regno; i < endregno; i++)
9382 /* Reset the information about this register. */
9383 reg_set_luid[i] = 0;
9389 add_auto_inc_notes (insn, x)
9393 enum rtx_code code = GET_CODE (x);
9397 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9400 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9404 /* Scan all the operand sub-expressions. */
9405 fmt = GET_RTX_FORMAT (code);
9406 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9409 add_auto_inc_notes (insn, XEXP (x, i));
9410 else if (fmt[i] == 'E')
9411 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9412 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9417 /* Copy EH notes from an insn to its reloads. */
9419 copy_eh_notes (insn, x)
9423 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9426 for (; x != 0; x = NEXT_INSN (x))
9428 if (may_trap_p (PATTERN (x)))
9430 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9436 /* This is used by reload pass, that does emit some instructions after
9437 abnormal calls moving basic block end, but in fact it wants to emit
9438 them on the edge. Looks for abnormal call edges, find backward the
9439 proper call and fix the damage.
9441 Similar handle instructions throwing exceptions internally. */
9443 fixup_abnormal_edges ()
9445 bool inserted = false;
9452 /* Look for cases we are interested in - an calls or instructions causing
9454 for (e = bb->succ; e; e = e->succ_next)
9456 if (e->flags & EDGE_ABNORMAL_CALL)
9458 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9459 == (EDGE_ABNORMAL | EDGE_EH))
9462 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9464 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9466 for (e = bb->succ; e; e = e->succ_next)
9467 if (e->flags & EDGE_FALLTHRU)
9469 /* Get past the new insns generated. Allow notes, as the insns may
9470 be already deleted. */
9471 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9472 && !can_throw_internal (insn)
9473 && insn != bb->head)
9474 insn = PREV_INSN (insn);
9475 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9479 insn = NEXT_INSN (insn);
9480 while (insn && insn != stop)
9482 next = NEXT_INSN (insn);
9487 /* Sometimes there's still the return value USE.
9488 If it's placed after a trapping call (i.e. that
9489 call is the last insn anyway), we have no fallthru
9490 edge. Simply delete this use and don't try to insert
9491 on the non-existant edge. */
9492 if (GET_CODE (PATTERN (insn)) != USE)
9494 /* We're not deleting it, we're moving it. */
9495 INSN_DELETED_P (insn) = 0;
9496 PREV_INSN (insn) = NULL_RTX;
9497 NEXT_INSN (insn) = NULL_RTX;
9499 insert_insn_on_edge (insn, e);
9507 commit_edge_insertions ();
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