1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static void verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
394 static void scan_paradoxical_subregs (rtx);
395 static void count_pseudo (int);
396 static void order_regs_for_reload (struct insn_chain *);
397 static void reload_as_needed (int);
398 static void forget_old_reloads_1 (rtx, rtx, void *);
399 static int reload_reg_class_lower (const void *, const void *);
400 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
402 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
404 static int reload_reg_free_p (unsigned int, int, enum reload_type);
405 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
407 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
409 static int function_invariant_p (rtx);
410 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
411 static int allocate_reload_reg (struct insn_chain *, int, int);
412 static int conflicts_with_override (rtx);
413 static void failed_reload (rtx, int);
414 static int set_reload_reg (int, int);
415 static void choose_reload_regs_init (struct insn_chain *, rtx *);
416 static void choose_reload_regs (struct insn_chain *);
417 static void merge_assigned_reloads (rtx);
418 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
420 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
422 static void do_input_reload (struct insn_chain *, struct reload *, int);
423 static void do_output_reload (struct insn_chain *, struct reload *, int);
424 static bool inherit_piecemeal_p (int, int);
425 static void emit_reload_insns (struct insn_chain *);
426 static void delete_output_reload (rtx, int, int);
427 static void delete_address_reloads (rtx, rtx);
428 static void delete_address_reloads_1 (rtx, rtx, rtx);
429 static rtx inc_for_reload (rtx, rtx, rtx, int);
431 static void add_auto_inc_notes (rtx, rtx);
433 static void copy_eh_notes (rtx, rtx);
435 /* Initialize the reload pass once per compilation. */
442 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
443 Set spill_indirect_levels to the number of levels such addressing is
444 permitted, zero if it is not permitted at all. */
447 = gen_rtx_MEM (Pmode,
450 LAST_VIRTUAL_REGISTER + 1),
452 spill_indirect_levels = 0;
454 while (memory_address_p (QImode, tem))
456 spill_indirect_levels++;
457 tem = gen_rtx_MEM (Pmode, tem);
460 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
462 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
463 indirect_symref_ok = memory_address_p (QImode, tem);
465 /* See if reg+reg is a valid (and offsettable) address. */
467 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
469 tem = gen_rtx_PLUS (Pmode,
470 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
471 gen_rtx_REG (Pmode, i));
473 /* This way, we make sure that reg+reg is an offsettable address. */
474 tem = plus_constant (tem, 4);
476 if (memory_address_p (QImode, tem))
478 double_reg_address_ok = 1;
483 /* Initialize obstack for our rtl allocation. */
484 gcc_obstack_init (&reload_obstack);
485 reload_startobj = obstack_alloc (&reload_obstack, 0);
487 INIT_REG_SET (&spilled_pseudos);
488 INIT_REG_SET (&pseudos_counted);
489 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
492 /* List of insn chains that are currently unused. */
493 static struct insn_chain *unused_insn_chains = 0;
495 /* Allocate an empty insn_chain structure. */
497 new_insn_chain (void)
499 struct insn_chain *c;
501 if (unused_insn_chains == 0)
503 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
504 INIT_REG_SET (&c->live_throughout);
505 INIT_REG_SET (&c->dead_or_set);
509 c = unused_insn_chains;
510 unused_insn_chains = c->next;
512 c->is_caller_save_insn = 0;
513 c->need_operand_change = 0;
519 /* Small utility function to set all regs in hard reg set TO which are
520 allocated to pseudos in regset FROM. */
523 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 EXECUTE_IF_SET_IN_REG_SET
528 (from, FIRST_PSEUDO_REGISTER, regno,
530 int r = reg_renumber[regno];
535 /* reload_combine uses the information from
536 BASIC_BLOCK->global_live_at_start, which might still
537 contain registers that have not actually been allocated
538 since they have an equivalence. */
539 if (! reload_completed)
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
587 else if (!REG_P (regno_reg_rtx[regno])
588 || REGNO (regno_reg_rtx[regno]) != regno)
589 *loc = regno_reg_rtx[regno];
595 else if (code == MEM)
597 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
601 /* Process each of our operands recursively. */
602 fmt = GET_RTX_FORMAT (code);
603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
605 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
606 else if (*fmt == 'E')
607 for (j = 0; j < XVECLEN (x, i); j++)
608 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
612 /* Global variables used by reload and its subroutines. */
614 /* Set during calculate_needs if an insn needs register elimination. */
615 static int something_needs_elimination;
616 /* Set during calculate_needs if an insn needs an operand changed. */
617 int something_needs_operands_changed;
619 /* Nonzero means we couldn't get enough spill regs. */
622 /* Main entry point for the reload pass.
624 FIRST is the first insn of the function being compiled.
626 GLOBAL nonzero means we were called from global_alloc
627 and should attempt to reallocate any pseudoregs that we
628 displace from hard regs we will use for reloads.
629 If GLOBAL is zero, we do not have enough information to do that,
630 so any pseudo reg that is spilled must go to the stack.
632 Return value is nonzero if reload failed
633 and we must not do any more for this function. */
636 reload (rtx first, int global)
640 struct elim_table *ep;
643 /* Make sure even insns with volatile mem refs are recognizable. */
648 reload_firstobj = obstack_alloc (&reload_obstack, 0);
650 /* Make sure that the last insn in the chain
651 is not something that needs reloading. */
652 emit_note (NOTE_INSN_DELETED);
654 /* Enable find_equiv_reg to distinguish insns made by reload. */
655 reload_first_uid = get_max_uid ();
657 #ifdef SECONDARY_MEMORY_NEEDED
658 /* Initialize the secondary memory table. */
659 clear_secondary_mem ();
662 /* We don't have a stack slot for any spill reg yet. */
663 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
664 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
666 /* Initialize the save area information for caller-save, in case some
670 /* Compute which hard registers are now in use
671 as homes for pseudo registers.
672 This is done here rather than (eg) in global_alloc
673 because this point is reached even if not optimizing. */
674 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
677 /* A function that receives a nonlocal goto must save all call-saved
679 if (current_function_has_nonlocal_label)
680 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
681 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
682 regs_ever_live[i] = 1;
684 #ifdef NON_SAVING_SETJMP
685 /* A function that calls setjmp should save and restore all the
686 call-saved registers on a system where longjmp clobbers them. */
687 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
690 if (! call_used_regs[i])
691 regs_ever_live[i] = 1;
695 /* Find all the pseudo registers that didn't get hard regs
696 but do have known equivalent constants or memory slots.
697 These include parameters (known equivalent to parameter slots)
698 and cse'd or loop-moved constant memory addresses.
700 Record constant equivalents in reg_equiv_constant
701 so they will be substituted by find_reloads.
702 Record memory equivalents in reg_mem_equiv so they can
703 be substituted eventually by altering the REG-rtx's. */
705 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
706 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
707 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
708 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
709 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
710 reg_old_renumber = xcalloc (max_regno, sizeof (short));
711 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
712 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
713 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
715 CLEAR_HARD_REG_SET (bad_spill_regs_global);
717 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
718 to. Also find all paradoxical subregs and find largest such for
721 num_eliminable_invariants = 0;
722 for (insn = first; insn; insn = NEXT_INSN (insn))
724 rtx set = single_set (insn);
726 /* We may introduce USEs that we want to remove at the end, so
727 we'll mark them with QImode. Make sure there are no
728 previously-marked insns left by say regmove. */
729 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
730 && GET_MODE (insn) != VOIDmode)
731 PUT_MODE (insn, VOIDmode);
733 if (set != 0 && REG_P (SET_DEST (set)))
735 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
737 #ifdef LEGITIMATE_PIC_OPERAND_P
738 && (! function_invariant_p (XEXP (note, 0))
740 /* A function invariant is often CONSTANT_P but may
741 include a register. We promise to only pass
742 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
743 || (CONSTANT_P (XEXP (note, 0))
744 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
748 rtx x = XEXP (note, 0);
749 i = REGNO (SET_DEST (set));
750 if (i > LAST_VIRTUAL_REGISTER)
752 /* It can happen that a REG_EQUIV note contains a MEM
753 that is not a legitimate memory operand. As later
754 stages of reload assume that all addresses found
755 in the reg_equiv_* arrays were originally legitimate,
756 we ignore such REG_EQUIV notes. */
757 if (memory_operand (x, VOIDmode))
759 /* Always unshare the equivalence, so we can
760 substitute into this insn without touching the
762 reg_equiv_memory_loc[i] = copy_rtx (x);
764 else if (function_invariant_p (x))
766 if (GET_CODE (x) == PLUS)
768 /* This is PLUS of frame pointer and a constant,
769 and might be shared. Unshare it. */
770 reg_equiv_constant[i] = copy_rtx (x);
771 num_eliminable_invariants++;
773 else if (x == frame_pointer_rtx
774 || x == arg_pointer_rtx)
776 reg_equiv_constant[i] = x;
777 num_eliminable_invariants++;
779 else if (LEGITIMATE_CONSTANT_P (x))
780 reg_equiv_constant[i] = x;
783 reg_equiv_memory_loc[i]
784 = force_const_mem (GET_MODE (SET_DEST (set)), x);
785 if (!reg_equiv_memory_loc[i])
792 /* If this register is being made equivalent to a MEM
793 and the MEM is not SET_SRC, the equivalencing insn
794 is one with the MEM as a SET_DEST and it occurs later.
795 So don't mark this insn now. */
797 || rtx_equal_p (SET_SRC (set), x))
799 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
804 /* If this insn is setting a MEM from a register equivalent to it,
805 this is the equivalencing insn. */
806 else if (set && MEM_P (SET_DEST (set))
807 && REG_P (SET_SRC (set))
808 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
809 && rtx_equal_p (SET_DEST (set),
810 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
811 reg_equiv_init[REGNO (SET_SRC (set))]
812 = gen_rtx_INSN_LIST (VOIDmode, insn,
813 reg_equiv_init[REGNO (SET_SRC (set))]);
816 scan_paradoxical_subregs (PATTERN (insn));
821 first_label_num = get_first_label_num ();
822 num_labels = max_label_num () - first_label_num;
824 /* Allocate the tables used to store offset information at labels. */
825 /* We used to use alloca here, but the size of what it would try to
826 allocate would occasionally cause it to exceed the stack limit and
827 cause a core dump. */
828 offsets_known_at = xmalloc (num_labels);
829 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
831 /* Alter each pseudo-reg rtx to contain its hard reg number.
832 Assign stack slots to the pseudos that lack hard regs or equivalents.
833 Do not touch virtual registers. */
835 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
838 /* If we have some registers we think can be eliminated, scan all insns to
839 see if there is an insn that sets one of these registers to something
840 other than itself plus a constant. If so, the register cannot be
841 eliminated. Doing this scan here eliminates an extra pass through the
842 main reload loop in the most common case where register elimination
844 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
846 || GET_CODE (insn) == CALL_INSN)
847 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
849 maybe_fix_stack_asms ();
851 insns_need_reload = 0;
852 something_needs_elimination = 0;
854 /* Initialize to -1, which means take the first spill register. */
857 /* Spill any hard regs that we know we can't eliminate. */
858 CLEAR_HARD_REG_SET (used_spill_regs);
859 /* There can be multiple ways to eliminate a register;
860 they should be listed adjacently.
861 Elimination for any register fails only if all possible ways fail. */
862 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
865 int can_eliminate = 0;
868 can_eliminate |= ep->can_eliminate;
871 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
873 spill_hard_reg (from, 1);
876 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
877 if (frame_pointer_needed)
878 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
880 finish_spills (global);
882 /* From now on, we may need to generate moves differently. We may also
883 allow modifications of insns which cause them to not be recognized.
884 Any such modifications will be cleaned up during reload itself. */
885 reload_in_progress = 1;
887 /* This loop scans the entire function each go-round
888 and repeats until one repetition spills no additional hard regs. */
891 int something_changed;
894 HOST_WIDE_INT starting_frame_size;
896 /* Round size of stack frame to stack_alignment_needed. This must be done
897 here because the stack size may be a part of the offset computation
898 for register elimination, and there might have been new stack slots
899 created in the last iteration of this loop. */
900 if (cfun->stack_alignment_needed)
901 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
903 starting_frame_size = get_frame_size ();
905 set_initial_elim_offsets ();
906 set_initial_label_offsets ();
908 /* For each pseudo register that has an equivalent location defined,
909 try to eliminate any eliminable registers (such as the frame pointer)
910 assuming initial offsets for the replacement register, which
913 If the resulting location is directly addressable, substitute
914 the MEM we just got directly for the old REG.
916 If it is not addressable but is a constant or the sum of a hard reg
917 and constant, it is probably not addressable because the constant is
918 out of range, in that case record the address; we will generate
919 hairy code to compute the address in a register each time it is
920 needed. Similarly if it is a hard register, but one that is not
921 valid as an address register.
923 If the location is not addressable, but does not have one of the
924 above forms, assign a stack slot. We have to do this to avoid the
925 potential of producing lots of reloads if, e.g., a location involves
926 a pseudo that didn't get a hard register and has an equivalent memory
927 location that also involves a pseudo that didn't get a hard register.
929 Perhaps at some point we will improve reload_when_needed handling
930 so this problem goes away. But that's very hairy. */
932 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
933 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
935 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
937 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
939 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
940 else if (CONSTANT_P (XEXP (x, 0))
941 || (REG_P (XEXP (x, 0))
942 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
943 || (GET_CODE (XEXP (x, 0)) == PLUS
944 && REG_P (XEXP (XEXP (x, 0), 0))
945 && (REGNO (XEXP (XEXP (x, 0), 0))
946 < FIRST_PSEUDO_REGISTER)
947 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
948 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
951 /* Make a new stack slot. Then indicate that something
952 changed so we go back and recompute offsets for
953 eliminable registers because the allocation of memory
954 below might change some offset. reg_equiv_{mem,address}
955 will be set up for this pseudo on the next pass around
957 reg_equiv_memory_loc[i] = 0;
958 reg_equiv_init[i] = 0;
963 if (caller_save_needed)
966 /* If we allocated another stack slot, redo elimination bookkeeping. */
967 if (starting_frame_size != get_frame_size ())
970 if (caller_save_needed)
972 save_call_clobbered_regs ();
973 /* That might have allocated new insn_chain structures. */
974 reload_firstobj = obstack_alloc (&reload_obstack, 0);
977 calculate_needs_all_insns (global);
979 CLEAR_REG_SET (&spilled_pseudos);
982 something_changed = 0;
984 /* If we allocated any new memory locations, make another pass
985 since it might have changed elimination offsets. */
986 if (starting_frame_size != get_frame_size ())
987 something_changed = 1;
990 HARD_REG_SET to_spill;
991 CLEAR_HARD_REG_SET (to_spill);
992 update_eliminables (&to_spill);
993 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
994 if (TEST_HARD_REG_BIT (to_spill, i))
996 spill_hard_reg (i, 1);
999 /* Regardless of the state of spills, if we previously had
1000 a register that we thought we could eliminate, but now can
1001 not eliminate, we must run another pass.
1003 Consider pseudos which have an entry in reg_equiv_* which
1004 reference an eliminable register. We must make another pass
1005 to update reg_equiv_* so that we do not substitute in the
1006 old value from when we thought the elimination could be
1008 something_changed = 1;
1012 select_reload_regs ();
1016 if (insns_need_reload != 0 || did_spill)
1017 something_changed |= finish_spills (global);
1019 if (! something_changed)
1022 if (caller_save_needed)
1023 delete_caller_save_insns ();
1025 obstack_free (&reload_obstack, reload_firstobj);
1028 /* If global-alloc was run, notify it of any register eliminations we have
1031 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1032 if (ep->can_eliminate)
1033 mark_elimination (ep->from, ep->to);
1035 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1036 If that insn didn't set the register (i.e., it copied the register to
1037 memory), just delete that insn instead of the equivalencing insn plus
1038 anything now dead. If we call delete_dead_insn on that insn, we may
1039 delete the insn that actually sets the register if the register dies
1040 there and that is incorrect. */
1042 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1044 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1047 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1049 rtx equiv_insn = XEXP (list, 0);
1051 /* If we already deleted the insn or if it may trap, we can't
1052 delete it. The latter case shouldn't happen, but can
1053 if an insn has a variable address, gets a REG_EH_REGION
1054 note added to it, and then gets converted into an load
1055 from a constant address. */
1056 if (GET_CODE (equiv_insn) == NOTE
1057 || can_throw_internal (equiv_insn))
1059 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1060 delete_dead_insn (equiv_insn);
1062 SET_INSN_DELETED (equiv_insn);
1067 /* Use the reload registers where necessary
1068 by generating move instructions to move the must-be-register
1069 values into or out of the reload registers. */
1071 if (insns_need_reload != 0 || something_needs_elimination
1072 || something_needs_operands_changed)
1074 HOST_WIDE_INT old_frame_size = get_frame_size ();
1076 reload_as_needed (global);
1078 if (old_frame_size != get_frame_size ())
1082 verify_initial_elim_offsets ();
1085 /* If we were able to eliminate the frame pointer, show that it is no
1086 longer live at the start of any basic block. If it ls live by
1087 virtue of being in a pseudo, that pseudo will be marked live
1088 and hence the frame pointer will be known to be live via that
1091 if (! frame_pointer_needed)
1093 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1094 HARD_FRAME_POINTER_REGNUM);
1096 /* Come here (with failure set nonzero) if we can't get enough spill regs
1097 and we decide not to abort about it. */
1100 CLEAR_REG_SET (&spilled_pseudos);
1101 reload_in_progress = 0;
1103 /* Now eliminate all pseudo regs by modifying them into
1104 their equivalent memory references.
1105 The REG-rtx's for the pseudos are modified in place,
1106 so all insns that used to refer to them now refer to memory.
1108 For a reg that has a reg_equiv_address, all those insns
1109 were changed by reloading so that no insns refer to it any longer;
1110 but the DECL_RTL of a variable decl may refer to it,
1111 and if so this causes the debugging info to mention the variable. */
1113 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1117 if (reg_equiv_mem[i])
1118 addr = XEXP (reg_equiv_mem[i], 0);
1120 if (reg_equiv_address[i])
1121 addr = reg_equiv_address[i];
1125 if (reg_renumber[i] < 0)
1127 rtx reg = regno_reg_rtx[i];
1129 REG_USERVAR_P (reg) = 0;
1130 PUT_CODE (reg, MEM);
1131 XEXP (reg, 0) = addr;
1132 if (reg_equiv_memory_loc[i])
1133 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1136 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1137 = MEM_SCALAR_P (reg) = 0;
1138 MEM_ATTRS (reg) = 0;
1141 else if (reg_equiv_mem[i])
1142 XEXP (reg_equiv_mem[i], 0) = addr;
1146 /* We must set reload_completed now since the cleanup_subreg_operands call
1147 below will re-recognize each insn and reload may have generated insns
1148 which are only valid during and after reload. */
1149 reload_completed = 1;
1151 /* Make a pass over all the insns and delete all USEs which we inserted
1152 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1153 notes. Delete all CLOBBER insns, except those that refer to the return
1154 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1155 from misarranging variable-array code, and simplify (subreg (reg))
1156 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1157 are no longer useful or accurate. Strip and regenerate REG_INC notes
1158 that may have been moved around. */
1160 for (insn = first; insn; insn = NEXT_INSN (insn))
1165 if (GET_CODE (insn) == CALL_INSN)
1166 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1167 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1169 if ((GET_CODE (PATTERN (insn)) == USE
1170 /* We mark with QImode USEs introduced by reload itself. */
1171 && (GET_MODE (insn) == QImode
1172 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1173 || (GET_CODE (PATTERN (insn)) == CLOBBER
1174 && (!MEM_P (XEXP (PATTERN (insn), 0))
1175 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1176 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1177 && XEXP (XEXP (PATTERN (insn), 0), 0)
1178 != stack_pointer_rtx))
1179 && (!REG_P (XEXP (PATTERN (insn), 0))
1180 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1186 /* Some CLOBBERs may survive until here and still reference unassigned
1187 pseudos with const equivalent, which may in turn cause ICE in later
1188 passes if the reference remains in place. */
1189 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1190 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1191 VOIDmode, PATTERN (insn));
1193 pnote = ®_NOTES (insn);
1196 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1197 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1198 || REG_NOTE_KIND (*pnote) == REG_INC
1199 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1200 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1201 *pnote = XEXP (*pnote, 1);
1203 pnote = &XEXP (*pnote, 1);
1207 add_auto_inc_notes (insn, PATTERN (insn));
1210 /* And simplify (subreg (reg)) if it appears as an operand. */
1211 cleanup_subreg_operands (insn);
1214 /* If we are doing stack checking, give a warning if this function's
1215 frame size is larger than we expect. */
1216 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1218 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1219 static int verbose_warned = 0;
1221 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1222 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1223 size += UNITS_PER_WORD;
1225 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1227 warning ("frame size too large for reliable stack checking");
1228 if (! verbose_warned)
1230 warning ("try reducing the number of local variables");
1236 /* Indicate that we no longer have known memory locations or constants. */
1237 if (reg_equiv_constant)
1238 free (reg_equiv_constant);
1239 reg_equiv_constant = 0;
1240 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1241 reg_equiv_memory_loc = 0;
1243 if (offsets_known_at)
1244 free (offsets_known_at);
1248 free (reg_equiv_mem);
1249 free (reg_equiv_init);
1250 free (reg_equiv_address);
1251 free (reg_max_ref_width);
1252 free (reg_old_renumber);
1253 free (pseudo_previous_regs);
1254 free (pseudo_forbidden_regs);
1256 CLEAR_HARD_REG_SET (used_spill_regs);
1257 for (i = 0; i < n_spills; i++)
1258 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1260 /* Free all the insn_chain structures at once. */
1261 obstack_free (&reload_obstack, reload_startobj);
1262 unused_insn_chains = 0;
1263 fixup_abnormal_edges ();
1265 /* Replacing pseudos with their memory equivalents might have
1266 created shared rtx. Subsequent passes would get confused
1267 by this, so unshare everything here. */
1268 unshare_all_rtl_again (first);
1270 #ifdef STACK_BOUNDARY
1271 /* init_emit has set the alignment of the hard frame pointer
1272 to STACK_BOUNDARY. It is very likely no longer valid if
1273 the hard frame pointer was used for register allocation. */
1274 if (!frame_pointer_needed)
1275 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1281 /* Yet another special case. Unfortunately, reg-stack forces people to
1282 write incorrect clobbers in asm statements. These clobbers must not
1283 cause the register to appear in bad_spill_regs, otherwise we'll call
1284 fatal_insn later. We clear the corresponding regnos in the live
1285 register sets to avoid this.
1286 The whole thing is rather sick, I'm afraid. */
1289 maybe_fix_stack_asms (void)
1292 const char *constraints[MAX_RECOG_OPERANDS];
1293 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1294 struct insn_chain *chain;
1296 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1299 HARD_REG_SET clobbered, allowed;
1302 if (! INSN_P (chain->insn)
1303 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1305 pat = PATTERN (chain->insn);
1306 if (GET_CODE (pat) != PARALLEL)
1309 CLEAR_HARD_REG_SET (clobbered);
1310 CLEAR_HARD_REG_SET (allowed);
1312 /* First, make a mask of all stack regs that are clobbered. */
1313 for (i = 0; i < XVECLEN (pat, 0); i++)
1315 rtx t = XVECEXP (pat, 0, i);
1316 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1317 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1320 /* Get the operand values and constraints out of the insn. */
1321 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1322 constraints, operand_mode);
1324 /* For every operand, see what registers are allowed. */
1325 for (i = 0; i < noperands; i++)
1327 const char *p = constraints[i];
1328 /* For every alternative, we compute the class of registers allowed
1329 for reloading in CLS, and merge its contents into the reg set
1331 int cls = (int) NO_REGS;
1337 if (c == '\0' || c == ',' || c == '#')
1339 /* End of one alternative - mark the regs in the current
1340 class, and reset the class. */
1341 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1347 } while (c != '\0' && c != ',');
1355 case '=': case '+': case '*': case '%': case '?': case '!':
1356 case '0': case '1': case '2': case '3': case '4': case 'm':
1357 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1358 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1359 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1364 cls = (int) reg_class_subunion[cls]
1365 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1370 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1374 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1375 cls = (int) reg_class_subunion[cls]
1376 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1378 cls = (int) reg_class_subunion[cls]
1379 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1381 p += CONSTRAINT_LEN (c, p);
1384 /* Those of the registers which are clobbered, but allowed by the
1385 constraints, must be usable as reload registers. So clear them
1386 out of the life information. */
1387 AND_HARD_REG_SET (allowed, clobbered);
1388 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1389 if (TEST_HARD_REG_BIT (allowed, i))
1391 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1392 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1399 /* Copy the global variables n_reloads and rld into the corresponding elts
1402 copy_reloads (struct insn_chain *chain)
1404 chain->n_reloads = n_reloads;
1405 chain->rld = obstack_alloc (&reload_obstack,
1406 n_reloads * sizeof (struct reload));
1407 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1408 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1411 /* Walk the chain of insns, and determine for each whether it needs reloads
1412 and/or eliminations. Build the corresponding insns_need_reload list, and
1413 set something_needs_elimination as appropriate. */
1415 calculate_needs_all_insns (int global)
1417 struct insn_chain **pprev_reload = &insns_need_reload;
1418 struct insn_chain *chain, *next = 0;
1420 something_needs_elimination = 0;
1422 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1423 for (chain = reload_insn_chain; chain != 0; chain = next)
1425 rtx insn = chain->insn;
1429 /* Clear out the shortcuts. */
1430 chain->n_reloads = 0;
1431 chain->need_elim = 0;
1432 chain->need_reload = 0;
1433 chain->need_operand_change = 0;
1435 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1436 include REG_LABEL), we need to see what effects this has on the
1437 known offsets at labels. */
1439 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1440 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1441 set_label_offsets (insn, insn, 0);
1445 rtx old_body = PATTERN (insn);
1446 int old_code = INSN_CODE (insn);
1447 rtx old_notes = REG_NOTES (insn);
1448 int did_elimination = 0;
1449 int operands_changed = 0;
1450 rtx set = single_set (insn);
1452 /* Skip insns that only set an equivalence. */
1453 if (set && REG_P (SET_DEST (set))
1454 && reg_renumber[REGNO (SET_DEST (set))] < 0
1455 && reg_equiv_constant[REGNO (SET_DEST (set))])
1458 /* If needed, eliminate any eliminable registers. */
1459 if (num_eliminable || num_eliminable_invariants)
1460 did_elimination = eliminate_regs_in_insn (insn, 0);
1462 /* Analyze the instruction. */
1463 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1464 global, spill_reg_order);
1466 /* If a no-op set needs more than one reload, this is likely
1467 to be something that needs input address reloads. We
1468 can't get rid of this cleanly later, and it is of no use
1469 anyway, so discard it now.
1470 We only do this when expensive_optimizations is enabled,
1471 since this complements reload inheritance / output
1472 reload deletion, and it can make debugging harder. */
1473 if (flag_expensive_optimizations && n_reloads > 1)
1475 rtx set = single_set (insn);
1477 && SET_SRC (set) == SET_DEST (set)
1478 && REG_P (SET_SRC (set))
1479 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1482 /* Delete it from the reload chain. */
1484 chain->prev->next = next;
1486 reload_insn_chain = next;
1488 next->prev = chain->prev;
1489 chain->next = unused_insn_chains;
1490 unused_insn_chains = chain;
1495 update_eliminable_offsets ();
1497 /* Remember for later shortcuts which insns had any reloads or
1498 register eliminations. */
1499 chain->need_elim = did_elimination;
1500 chain->need_reload = n_reloads > 0;
1501 chain->need_operand_change = operands_changed;
1503 /* Discard any register replacements done. */
1504 if (did_elimination)
1506 obstack_free (&reload_obstack, reload_insn_firstobj);
1507 PATTERN (insn) = old_body;
1508 INSN_CODE (insn) = old_code;
1509 REG_NOTES (insn) = old_notes;
1510 something_needs_elimination = 1;
1513 something_needs_operands_changed |= operands_changed;
1517 copy_reloads (chain);
1518 *pprev_reload = chain;
1519 pprev_reload = &chain->next_need_reload;
1526 /* Comparison function for qsort to decide which of two reloads
1527 should be handled first. *P1 and *P2 are the reload numbers. */
1530 reload_reg_class_lower (const void *r1p, const void *r2p)
1532 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1535 /* Consider required reloads before optional ones. */
1536 t = rld[r1].optional - rld[r2].optional;
1540 /* Count all solitary classes before non-solitary ones. */
1541 t = ((reg_class_size[(int) rld[r2].class] == 1)
1542 - (reg_class_size[(int) rld[r1].class] == 1));
1546 /* Aside from solitaires, consider all multi-reg groups first. */
1547 t = rld[r2].nregs - rld[r1].nregs;
1551 /* Consider reloads in order of increasing reg-class number. */
1552 t = (int) rld[r1].class - (int) rld[r2].class;
1556 /* If reloads are equally urgent, sort by reload number,
1557 so that the results of qsort leave nothing to chance. */
1561 /* The cost of spilling each hard reg. */
1562 static int spill_cost[FIRST_PSEUDO_REGISTER];
1564 /* When spilling multiple hard registers, we use SPILL_COST for the first
1565 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1566 only the first hard reg for a multi-reg pseudo. */
1567 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1569 /* Update the spill cost arrays, considering that pseudo REG is live. */
1572 count_pseudo (int reg)
1574 int freq = REG_FREQ (reg);
1575 int r = reg_renumber[reg];
1578 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1579 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1582 SET_REGNO_REG_SET (&pseudos_counted, reg);
1587 spill_add_cost[r] += freq;
1589 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1591 spill_cost[r + nregs] += freq;
1594 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1595 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1598 order_regs_for_reload (struct insn_chain *chain)
1601 HARD_REG_SET used_by_pseudos;
1602 HARD_REG_SET used_by_pseudos2;
1604 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1606 memset (spill_cost, 0, sizeof spill_cost);
1607 memset (spill_add_cost, 0, sizeof spill_add_cost);
1609 /* Count number of uses of each hard reg by pseudo regs allocated to it
1610 and then order them by decreasing use. First exclude hard registers
1611 that are live in or across this insn. */
1613 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1614 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1615 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1616 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1618 /* Now find out which pseudos are allocated to it, and update
1620 CLEAR_REG_SET (&pseudos_counted);
1622 EXECUTE_IF_SET_IN_REG_SET
1623 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1627 EXECUTE_IF_SET_IN_REG_SET
1628 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1632 CLEAR_REG_SET (&pseudos_counted);
1635 /* Vector of reload-numbers showing the order in which the reloads should
1637 static short reload_order[MAX_RELOADS];
1639 /* This is used to keep track of the spill regs used in one insn. */
1640 static HARD_REG_SET used_spill_regs_local;
1642 /* We decided to spill hard register SPILLED, which has a size of
1643 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1644 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1645 update SPILL_COST/SPILL_ADD_COST. */
1648 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1650 int r = reg_renumber[reg];
1651 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1653 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1654 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1657 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1659 spill_add_cost[r] -= REG_FREQ (reg);
1661 spill_cost[r + nregs] -= REG_FREQ (reg);
1664 /* Find reload register to use for reload number ORDER. */
1667 find_reg (struct insn_chain *chain, int order)
1669 int rnum = reload_order[order];
1670 struct reload *rl = rld + rnum;
1671 int best_cost = INT_MAX;
1675 HARD_REG_SET not_usable;
1676 HARD_REG_SET used_by_other_reload;
1678 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1679 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1680 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1682 CLEAR_HARD_REG_SET (used_by_other_reload);
1683 for (k = 0; k < order; k++)
1685 int other = reload_order[k];
1687 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1688 for (j = 0; j < rld[other].nregs; j++)
1689 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1692 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1694 unsigned int regno = i;
1696 if (! TEST_HARD_REG_BIT (not_usable, regno)
1697 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1698 && HARD_REGNO_MODE_OK (regno, rl->mode))
1700 int this_cost = spill_cost[regno];
1702 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1704 for (j = 1; j < this_nregs; j++)
1706 this_cost += spill_add_cost[regno + j];
1707 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1708 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1713 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1715 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1717 if (this_cost < best_cost
1718 /* Among registers with equal cost, prefer caller-saved ones, or
1719 use REG_ALLOC_ORDER if it is defined. */
1720 || (this_cost == best_cost
1721 #ifdef REG_ALLOC_ORDER
1722 && (inv_reg_alloc_order[regno]
1723 < inv_reg_alloc_order[best_reg])
1725 && call_used_regs[regno]
1726 && ! call_used_regs[best_reg]
1731 best_cost = this_cost;
1739 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1741 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1742 rl->regno = best_reg;
1744 EXECUTE_IF_SET_IN_REG_SET
1745 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1747 count_spilled_pseudo (best_reg, rl->nregs, j);
1750 EXECUTE_IF_SET_IN_REG_SET
1751 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1753 count_spilled_pseudo (best_reg, rl->nregs, j);
1756 for (i = 0; i < rl->nregs; i++)
1758 if (spill_cost[best_reg + i] != 0
1759 || spill_add_cost[best_reg + i] != 0)
1761 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1766 /* Find more reload regs to satisfy the remaining need of an insn, which
1768 Do it by ascending class number, since otherwise a reg
1769 might be spilled for a big class and might fail to count
1770 for a smaller class even though it belongs to that class. */
1773 find_reload_regs (struct insn_chain *chain)
1777 /* In order to be certain of getting the registers we need,
1778 we must sort the reloads into order of increasing register class.
1779 Then our grabbing of reload registers will parallel the process
1780 that provided the reload registers. */
1781 for (i = 0; i < chain->n_reloads; i++)
1783 /* Show whether this reload already has a hard reg. */
1784 if (chain->rld[i].reg_rtx)
1786 int regno = REGNO (chain->rld[i].reg_rtx);
1787 chain->rld[i].regno = regno;
1789 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1792 chain->rld[i].regno = -1;
1793 reload_order[i] = i;
1796 n_reloads = chain->n_reloads;
1797 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1799 CLEAR_HARD_REG_SET (used_spill_regs_local);
1802 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1804 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1806 /* Compute the order of preference for hard registers to spill. */
1808 order_regs_for_reload (chain);
1810 for (i = 0; i < n_reloads; i++)
1812 int r = reload_order[i];
1814 /* Ignore reloads that got marked inoperative. */
1815 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1816 && ! rld[r].optional
1817 && rld[r].regno == -1)
1818 if (! find_reg (chain, i))
1820 spill_failure (chain->insn, rld[r].class);
1826 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1827 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1829 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1833 select_reload_regs (void)
1835 struct insn_chain *chain;
1837 /* Try to satisfy the needs for each insn. */
1838 for (chain = insns_need_reload; chain != 0;
1839 chain = chain->next_need_reload)
1840 find_reload_regs (chain);
1843 /* Delete all insns that were inserted by emit_caller_save_insns during
1846 delete_caller_save_insns (void)
1848 struct insn_chain *c = reload_insn_chain;
1852 while (c != 0 && c->is_caller_save_insn)
1854 struct insn_chain *next = c->next;
1857 if (c == reload_insn_chain)
1858 reload_insn_chain = next;
1862 next->prev = c->prev;
1864 c->prev->next = next;
1865 c->next = unused_insn_chains;
1866 unused_insn_chains = c;
1874 /* Handle the failure to find a register to spill.
1875 INSN should be one of the insns which needed this particular spill reg. */
1878 spill_failure (rtx insn, enum reg_class class)
1880 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1881 if (asm_noperands (PATTERN (insn)) >= 0)
1882 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1883 reg_class_names[class]);
1886 error ("unable to find a register to spill in class `%s'",
1887 reg_class_names[class]);
1888 fatal_insn ("this is the insn:", insn);
1892 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1893 data that is dead in INSN. */
1896 delete_dead_insn (rtx insn)
1898 rtx prev = prev_real_insn (insn);
1901 /* If the previous insn sets a register that dies in our insn, delete it
1903 if (prev && GET_CODE (PATTERN (prev)) == SET
1904 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1905 && reg_mentioned_p (prev_dest, PATTERN (insn))
1906 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1907 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1908 delete_dead_insn (prev);
1910 SET_INSN_DELETED (insn);
1913 /* Modify the home of pseudo-reg I.
1914 The new home is present in reg_renumber[I].
1916 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1917 or it may be -1, meaning there is none or it is not relevant.
1918 This is used so that all pseudos spilled from a given hard reg
1919 can share one stack slot. */
1922 alter_reg (int i, int from_reg)
1924 /* When outputting an inline function, this can happen
1925 for a reg that isn't actually used. */
1926 if (regno_reg_rtx[i] == 0)
1929 /* If the reg got changed to a MEM at rtl-generation time,
1931 if (!REG_P (regno_reg_rtx[i]))
1934 /* Modify the reg-rtx to contain the new hard reg
1935 number or else to contain its pseudo reg number. */
1936 REGNO (regno_reg_rtx[i])
1937 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1939 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1940 allocate a stack slot for it. */
1942 if (reg_renumber[i] < 0
1943 && REG_N_REFS (i) > 0
1944 && reg_equiv_constant[i] == 0
1945 && reg_equiv_memory_loc[i] == 0)
1948 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1949 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1952 /* Each pseudo reg has an inherent size which comes from its own mode,
1953 and a total size which provides room for paradoxical subregs
1954 which refer to the pseudo reg in wider modes.
1956 We can use a slot already allocated if it provides both
1957 enough inherent space and enough total space.
1958 Otherwise, we allocate a new slot, making sure that it has no less
1959 inherent space, and no less total space, then the previous slot. */
1962 /* No known place to spill from => no slot to reuse. */
1963 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1964 inherent_size == total_size ? 0 : -1);
1965 if (BYTES_BIG_ENDIAN)
1966 /* Cancel the big-endian correction done in assign_stack_local.
1967 Get the address of the beginning of the slot.
1968 This is so we can do a big-endian correction unconditionally
1970 adjust = inherent_size - total_size;
1972 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1974 /* Nothing can alias this slot except this pseudo. */
1975 set_mem_alias_set (x, new_alias_set ());
1978 /* Reuse a stack slot if possible. */
1979 else if (spill_stack_slot[from_reg] != 0
1980 && spill_stack_slot_width[from_reg] >= total_size
1981 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1983 x = spill_stack_slot[from_reg];
1985 /* Allocate a bigger slot. */
1988 /* Compute maximum size needed, both for inherent size
1989 and for total size. */
1990 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1993 if (spill_stack_slot[from_reg])
1995 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1997 mode = GET_MODE (spill_stack_slot[from_reg]);
1998 if (spill_stack_slot_width[from_reg] > total_size)
1999 total_size = spill_stack_slot_width[from_reg];
2002 /* Make a slot with that size. */
2003 x = assign_stack_local (mode, total_size,
2004 inherent_size == total_size ? 0 : -1);
2007 /* All pseudos mapped to this slot can alias each other. */
2008 if (spill_stack_slot[from_reg])
2009 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2011 set_mem_alias_set (x, new_alias_set ());
2013 if (BYTES_BIG_ENDIAN)
2015 /* Cancel the big-endian correction done in assign_stack_local.
2016 Get the address of the beginning of the slot.
2017 This is so we can do a big-endian correction unconditionally
2019 adjust = GET_MODE_SIZE (mode) - total_size;
2022 = adjust_address_nv (x, mode_for_size (total_size
2028 spill_stack_slot[from_reg] = stack_slot;
2029 spill_stack_slot_width[from_reg] = total_size;
2032 /* On a big endian machine, the "address" of the slot
2033 is the address of the low part that fits its inherent mode. */
2034 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2035 adjust += (total_size - inherent_size);
2037 /* If we have any adjustment to make, or if the stack slot is the
2038 wrong mode, make a new stack slot. */
2039 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2041 /* If we have a decl for the original register, set it for the
2042 memory. If this is a shared MEM, make a copy. */
2043 if (REG_EXPR (regno_reg_rtx[i])
2044 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2046 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2048 /* We can do this only for the DECLs home pseudo, not for
2049 any copies of it, since otherwise when the stack slot
2050 is reused, nonoverlapping_memrefs_p might think they
2052 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2054 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2057 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2061 /* Save the stack slot for later. */
2062 reg_equiv_memory_loc[i] = x;
2066 /* Mark the slots in regs_ever_live for the hard regs
2067 used by pseudo-reg number REGNO. */
2070 mark_home_live (int regno)
2074 i = reg_renumber[regno];
2077 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2079 regs_ever_live[i++] = 1;
2082 /* This function handles the tracking of elimination offsets around branches.
2084 X is a piece of RTL being scanned.
2086 INSN is the insn that it came from, if any.
2088 INITIAL_P is nonzero if we are to set the offset to be the initial
2089 offset and zero if we are setting the offset of the label to be the
2093 set_label_offsets (rtx x, rtx insn, int initial_p)
2095 enum rtx_code code = GET_CODE (x);
2098 struct elim_table *p;
2103 if (LABEL_REF_NONLOCAL_P (x))
2108 /* ... fall through ... */
2111 /* If we know nothing about this label, set the desired offsets. Note
2112 that this sets the offset at a label to be the offset before a label
2113 if we don't know anything about the label. This is not correct for
2114 the label after a BARRIER, but is the best guess we can make. If
2115 we guessed wrong, we will suppress an elimination that might have
2116 been possible had we been able to guess correctly. */
2118 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2120 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2121 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2122 = (initial_p ? reg_eliminate[i].initial_offset
2123 : reg_eliminate[i].offset);
2124 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2127 /* Otherwise, if this is the definition of a label and it is
2128 preceded by a BARRIER, set our offsets to the known offset of
2132 && (tem = prev_nonnote_insn (insn)) != 0
2133 && GET_CODE (tem) == BARRIER)
2134 set_offsets_for_label (insn);
2136 /* If neither of the above cases is true, compare each offset
2137 with those previously recorded and suppress any eliminations
2138 where the offsets disagree. */
2140 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2141 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2142 != (initial_p ? reg_eliminate[i].initial_offset
2143 : reg_eliminate[i].offset))
2144 reg_eliminate[i].can_eliminate = 0;
2149 set_label_offsets (PATTERN (insn), insn, initial_p);
2151 /* ... fall through ... */
2155 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2156 and hence must have all eliminations at their initial offsets. */
2157 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2158 if (REG_NOTE_KIND (tem) == REG_LABEL)
2159 set_label_offsets (XEXP (tem, 0), insn, 1);
2165 /* Each of the labels in the parallel or address vector must be
2166 at their initial offsets. We want the first field for PARALLEL
2167 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2169 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2170 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2175 /* We only care about setting PC. If the source is not RETURN,
2176 IF_THEN_ELSE, or a label, disable any eliminations not at
2177 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2178 isn't one of those possibilities. For branches to a label,
2179 call ourselves recursively.
2181 Note that this can disable elimination unnecessarily when we have
2182 a non-local goto since it will look like a non-constant jump to
2183 someplace in the current function. This isn't a significant
2184 problem since such jumps will normally be when all elimination
2185 pairs are back to their initial offsets. */
2187 if (SET_DEST (x) != pc_rtx)
2190 switch (GET_CODE (SET_SRC (x)))
2197 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2201 tem = XEXP (SET_SRC (x), 1);
2202 if (GET_CODE (tem) == LABEL_REF)
2203 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2204 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2207 tem = XEXP (SET_SRC (x), 2);
2208 if (GET_CODE (tem) == LABEL_REF)
2209 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2210 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2218 /* If we reach here, all eliminations must be at their initial
2219 offset because we are doing a jump to a variable address. */
2220 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2221 if (p->offset != p->initial_offset)
2222 p->can_eliminate = 0;
2230 /* Scan X and replace any eliminable registers (such as fp) with a
2231 replacement (such as sp), plus an offset.
2233 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2234 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2235 MEM, we are allowed to replace a sum of a register and the constant zero
2236 with the register, which we cannot do outside a MEM. In addition, we need
2237 to record the fact that a register is referenced outside a MEM.
2239 If INSN is an insn, it is the insn containing X. If we replace a REG
2240 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2241 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2242 the REG is being modified.
2244 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2245 That's used when we eliminate in expressions stored in notes.
2246 This means, do not set ref_outside_mem even if the reference
2249 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2250 replacements done assuming all offsets are at their initial values. If
2251 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2252 encounter, return the actual location so that find_reloads will do
2253 the proper thing. */
2256 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2258 enum rtx_code code = GET_CODE (x);
2259 struct elim_table *ep;
2266 if (! current_function_decl)
2286 /* This is only for the benefit of the debugging backends, which call
2287 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2288 removed after CSE. */
2289 new = eliminate_regs (XEXP (x, 0), 0, insn);
2291 return XEXP (new, 0);
2297 /* First handle the case where we encounter a bare register that
2298 is eliminable. Replace it with a PLUS. */
2299 if (regno < FIRST_PSEUDO_REGISTER)
2301 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2303 if (ep->from_rtx == x && ep->can_eliminate)
2304 return plus_constant (ep->to_rtx, ep->previous_offset);
2307 else if (reg_renumber && reg_renumber[regno] < 0
2308 && reg_equiv_constant && reg_equiv_constant[regno]
2309 && ! CONSTANT_P (reg_equiv_constant[regno]))
2310 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2314 /* You might think handling MINUS in a manner similar to PLUS is a
2315 good idea. It is not. It has been tried multiple times and every
2316 time the change has had to have been reverted.
2318 Other parts of reload know a PLUS is special (gen_reload for example)
2319 and require special code to handle code a reloaded PLUS operand.
2321 Also consider backends where the flags register is clobbered by a
2322 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2323 lea instruction comes to mind). If we try to reload a MINUS, we
2324 may kill the flags register that was holding a useful value.
2326 So, please before trying to handle MINUS, consider reload as a
2327 whole instead of this little section as well as the backend issues. */
2329 /* If this is the sum of an eliminable register and a constant, rework
2331 if (REG_P (XEXP (x, 0))
2332 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2333 && CONSTANT_P (XEXP (x, 1)))
2335 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2337 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2339 /* The only time we want to replace a PLUS with a REG (this
2340 occurs when the constant operand of the PLUS is the negative
2341 of the offset) is when we are inside a MEM. We won't want
2342 to do so at other times because that would change the
2343 structure of the insn in a way that reload can't handle.
2344 We special-case the commonest situation in
2345 eliminate_regs_in_insn, so just replace a PLUS with a
2346 PLUS here, unless inside a MEM. */
2347 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2348 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2351 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2352 plus_constant (XEXP (x, 1),
2353 ep->previous_offset));
2356 /* If the register is not eliminable, we are done since the other
2357 operand is a constant. */
2361 /* If this is part of an address, we want to bring any constant to the
2362 outermost PLUS. We will do this by doing register replacement in
2363 our operands and seeing if a constant shows up in one of them.
2365 Note that there is no risk of modifying the structure of the insn,
2366 since we only get called for its operands, thus we are either
2367 modifying the address inside a MEM, or something like an address
2368 operand of a load-address insn. */
2371 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2372 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2374 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2376 /* If one side is a PLUS and the other side is a pseudo that
2377 didn't get a hard register but has a reg_equiv_constant,
2378 we must replace the constant here since it may no longer
2379 be in the position of any operand. */
2380 if (GET_CODE (new0) == PLUS && REG_P (new1)
2381 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2382 && reg_renumber[REGNO (new1)] < 0
2383 && reg_equiv_constant != 0
2384 && reg_equiv_constant[REGNO (new1)] != 0)
2385 new1 = reg_equiv_constant[REGNO (new1)];
2386 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2387 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2388 && reg_renumber[REGNO (new0)] < 0
2389 && reg_equiv_constant[REGNO (new0)] != 0)
2390 new0 = reg_equiv_constant[REGNO (new0)];
2392 new = form_sum (new0, new1);
2394 /* As above, if we are not inside a MEM we do not want to
2395 turn a PLUS into something else. We might try to do so here
2396 for an addition of 0 if we aren't optimizing. */
2397 if (! mem_mode && GET_CODE (new) != PLUS)
2398 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2406 /* If this is the product of an eliminable register and a
2407 constant, apply the distribute law and move the constant out
2408 so that we have (plus (mult ..) ..). This is needed in order
2409 to keep load-address insns valid. This case is pathological.
2410 We ignore the possibility of overflow here. */
2411 if (REG_P (XEXP (x, 0))
2412 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2413 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2414 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2416 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2419 /* Refs inside notes don't count for this purpose. */
2420 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2421 || GET_CODE (insn) == INSN_LIST)))
2422 ep->ref_outside_mem = 1;
2425 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2426 ep->previous_offset * INTVAL (XEXP (x, 1)));
2429 /* ... fall through ... */
2433 /* See comments before PLUS about handling MINUS. */
2435 case DIV: case UDIV:
2436 case MOD: case UMOD:
2437 case AND: case IOR: case XOR:
2438 case ROTATERT: case ROTATE:
2439 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2441 case GE: case GT: case GEU: case GTU:
2442 case LE: case LT: case LEU: case LTU:
2444 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2446 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2448 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2449 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2454 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2457 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2458 if (new != XEXP (x, 0))
2460 /* If this is a REG_DEAD note, it is not valid anymore.
2461 Using the eliminated version could result in creating a
2462 REG_DEAD note for the stack or frame pointer. */
2463 if (GET_MODE (x) == REG_DEAD)
2465 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2468 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2472 /* ... fall through ... */
2475 /* Now do eliminations in the rest of the chain. If this was
2476 an EXPR_LIST, this might result in allocating more memory than is
2477 strictly needed, but it simplifies the code. */
2480 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2481 if (new != XEXP (x, 1))
2483 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2491 case STRICT_LOW_PART:
2493 case SIGN_EXTEND: case ZERO_EXTEND:
2494 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2495 case FLOAT: case FIX:
2496 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2504 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2505 if (new != XEXP (x, 0))
2506 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2510 /* Similar to above processing, but preserve SUBREG_BYTE.
2511 Convert (subreg (mem)) to (mem) if not paradoxical.
2512 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2513 pseudo didn't get a hard reg, we must replace this with the
2514 eliminated version of the memory location because push_reload
2515 may do the replacement in certain circumstances. */
2516 if (REG_P (SUBREG_REG (x))
2517 && (GET_MODE_SIZE (GET_MODE (x))
2518 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2519 && reg_equiv_memory_loc != 0
2520 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2522 new = SUBREG_REG (x);
2525 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2527 if (new != SUBREG_REG (x))
2529 int x_size = GET_MODE_SIZE (GET_MODE (x));
2530 int new_size = GET_MODE_SIZE (GET_MODE (new));
2533 && ((x_size < new_size
2534 #ifdef WORD_REGISTER_OPERATIONS
2535 /* On these machines, combine can create rtl of the form
2536 (set (subreg:m1 (reg:m2 R) 0) ...)
2537 where m1 < m2, and expects something interesting to
2538 happen to the entire word. Moreover, it will use the
2539 (reg:m2 R) later, expecting all bits to be preserved.
2540 So if the number of words is the same, preserve the
2541 subreg so that push_reload can see it. */
2542 && ! ((x_size - 1) / UNITS_PER_WORD
2543 == (new_size -1 ) / UNITS_PER_WORD)
2546 || x_size == new_size)
2548 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2550 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2556 /* This is only for the benefit of the debugging backends, which call
2557 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2558 removed after CSE. */
2559 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2560 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2562 /* Our only special processing is to pass the mode of the MEM to our
2563 recursive call and copy the flags. While we are here, handle this
2564 case more efficiently. */
2566 replace_equiv_address_nv (x,
2567 eliminate_regs (XEXP (x, 0),
2568 GET_MODE (x), insn));
2571 /* Handle insn_list USE that a call to a pure function may generate. */
2572 new = eliminate_regs (XEXP (x, 0), 0, insn);
2573 if (new != XEXP (x, 0))
2574 return gen_rtx_USE (GET_MODE (x), new);
2586 /* Process each of our operands recursively. If any have changed, make a
2588 fmt = GET_RTX_FORMAT (code);
2589 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2593 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2594 if (new != XEXP (x, i) && ! copied)
2596 rtx new_x = rtx_alloc (code);
2597 memcpy (new_x, x, RTX_SIZE (code));
2603 else if (*fmt == 'E')
2606 for (j = 0; j < XVECLEN (x, i); j++)
2608 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2609 if (new != XVECEXP (x, i, j) && ! copied_vec)
2611 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2615 rtx new_x = rtx_alloc (code);
2616 memcpy (new_x, x, RTX_SIZE (code));
2620 XVEC (x, i) = new_v;
2623 XVECEXP (x, i, j) = new;
2631 /* Scan rtx X for modifications of elimination target registers. Update
2632 the table of eliminables to reflect the changed state. MEM_MODE is
2633 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2636 elimination_effects (rtx x, enum machine_mode mem_mode)
2638 enum rtx_code code = GET_CODE (x);
2639 struct elim_table *ep;
2666 /* First handle the case where we encounter a bare register that
2667 is eliminable. Replace it with a PLUS. */
2668 if (regno < FIRST_PSEUDO_REGISTER)
2670 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2672 if (ep->from_rtx == x && ep->can_eliminate)
2675 ep->ref_outside_mem = 1;
2680 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2681 && reg_equiv_constant[regno]
2682 && ! function_invariant_p (reg_equiv_constant[regno]))
2683 elimination_effects (reg_equiv_constant[regno], mem_mode);
2692 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2693 if (ep->to_rtx == XEXP (x, 0))
2695 int size = GET_MODE_SIZE (mem_mode);
2697 /* If more bytes than MEM_MODE are pushed, account for them. */
2698 #ifdef PUSH_ROUNDING
2699 if (ep->to_rtx == stack_pointer_rtx)
2700 size = PUSH_ROUNDING (size);
2702 if (code == PRE_DEC || code == POST_DEC)
2704 else if (code == PRE_INC || code == POST_INC)
2706 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2707 && GET_CODE (XEXP (x, 1)) == PLUS
2708 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2709 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2710 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2713 /* These two aren't unary operators. */
2714 if (code == POST_MODIFY || code == PRE_MODIFY)
2717 /* Fall through to generic unary operation case. */
2718 case STRICT_LOW_PART:
2720 case SIGN_EXTEND: case ZERO_EXTEND:
2721 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2722 case FLOAT: case FIX:
2723 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2731 elimination_effects (XEXP (x, 0), mem_mode);
2735 if (REG_P (SUBREG_REG (x))
2736 && (GET_MODE_SIZE (GET_MODE (x))
2737 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2738 && reg_equiv_memory_loc != 0
2739 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2742 elimination_effects (SUBREG_REG (x), mem_mode);
2746 /* If using a register that is the source of an eliminate we still
2747 think can be performed, note it cannot be performed since we don't
2748 know how this register is used. */
2749 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2750 if (ep->from_rtx == XEXP (x, 0))
2751 ep->can_eliminate = 0;
2753 elimination_effects (XEXP (x, 0), mem_mode);
2757 /* If clobbering a register that is the replacement register for an
2758 elimination we still think can be performed, note that it cannot
2759 be performed. Otherwise, we need not be concerned about it. */
2760 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2761 if (ep->to_rtx == XEXP (x, 0))
2762 ep->can_eliminate = 0;
2764 elimination_effects (XEXP (x, 0), mem_mode);
2768 /* Check for setting a register that we know about. */
2769 if (REG_P (SET_DEST (x)))
2771 /* See if this is setting the replacement register for an
2774 If DEST is the hard frame pointer, we do nothing because we
2775 assume that all assignments to the frame pointer are for
2776 non-local gotos and are being done at a time when they are valid
2777 and do not disturb anything else. Some machines want to
2778 eliminate a fake argument pointer (or even a fake frame pointer)
2779 with either the real frame or the stack pointer. Assignments to
2780 the hard frame pointer must not prevent this elimination. */
2782 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2784 if (ep->to_rtx == SET_DEST (x)
2785 && SET_DEST (x) != hard_frame_pointer_rtx)
2787 /* If it is being incremented, adjust the offset. Otherwise,
2788 this elimination can't be done. */
2789 rtx src = SET_SRC (x);
2791 if (GET_CODE (src) == PLUS
2792 && XEXP (src, 0) == SET_DEST (x)
2793 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2794 ep->offset -= INTVAL (XEXP (src, 1));
2796 ep->can_eliminate = 0;
2800 elimination_effects (SET_DEST (x), 0);
2801 elimination_effects (SET_SRC (x), 0);
2805 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2808 /* Our only special processing is to pass the mode of the MEM to our
2810 elimination_effects (XEXP (x, 0), GET_MODE (x));
2817 fmt = GET_RTX_FORMAT (code);
2818 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2821 elimination_effects (XEXP (x, i), mem_mode);
2822 else if (*fmt == 'E')
2823 for (j = 0; j < XVECLEN (x, i); j++)
2824 elimination_effects (XVECEXP (x, i, j), mem_mode);
2828 /* Descend through rtx X and verify that no references to eliminable registers
2829 remain. If any do remain, mark the involved register as not
2833 check_eliminable_occurrences (rtx x)
2842 code = GET_CODE (x);
2844 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2846 struct elim_table *ep;
2848 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2849 if (ep->from_rtx == x)
2850 ep->can_eliminate = 0;
2854 fmt = GET_RTX_FORMAT (code);
2855 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2858 check_eliminable_occurrences (XEXP (x, i));
2859 else if (*fmt == 'E')
2862 for (j = 0; j < XVECLEN (x, i); j++)
2863 check_eliminable_occurrences (XVECEXP (x, i, j));
2868 /* Scan INSN and eliminate all eliminable registers in it.
2870 If REPLACE is nonzero, do the replacement destructively. Also
2871 delete the insn as dead it if it is setting an eliminable register.
2873 If REPLACE is zero, do all our allocations in reload_obstack.
2875 If no eliminations were done and this insn doesn't require any elimination
2876 processing (these are not identical conditions: it might be updating sp,
2877 but not referencing fp; this needs to be seen during reload_as_needed so
2878 that the offset between fp and sp can be taken into consideration), zero
2879 is returned. Otherwise, 1 is returned. */
2882 eliminate_regs_in_insn (rtx insn, int replace)
2884 int icode = recog_memoized (insn);
2885 rtx old_body = PATTERN (insn);
2886 int insn_is_asm = asm_noperands (old_body) >= 0;
2887 rtx old_set = single_set (insn);
2891 rtx substed_operand[MAX_RECOG_OPERANDS];
2892 rtx orig_operand[MAX_RECOG_OPERANDS];
2893 struct elim_table *ep;
2896 if (! insn_is_asm && icode < 0)
2898 if (GET_CODE (PATTERN (insn)) == USE
2899 || GET_CODE (PATTERN (insn)) == CLOBBER
2900 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2901 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2902 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2907 if (old_set != 0 && REG_P (SET_DEST (old_set))
2908 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2910 /* Check for setting an eliminable register. */
2911 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2912 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2914 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2915 /* If this is setting the frame pointer register to the
2916 hardware frame pointer register and this is an elimination
2917 that will be done (tested above), this insn is really
2918 adjusting the frame pointer downward to compensate for
2919 the adjustment done before a nonlocal goto. */
2920 if (ep->from == FRAME_POINTER_REGNUM
2921 && ep->to == HARD_FRAME_POINTER_REGNUM)
2923 rtx base = SET_SRC (old_set);
2924 rtx base_insn = insn;
2925 HOST_WIDE_INT offset = 0;
2927 while (base != ep->to_rtx)
2929 rtx prev_insn, prev_set;
2931 if (GET_CODE (base) == PLUS
2932 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2934 offset += INTVAL (XEXP (base, 1));
2935 base = XEXP (base, 0);
2937 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2938 && (prev_set = single_set (prev_insn)) != 0
2939 && rtx_equal_p (SET_DEST (prev_set), base))
2941 base = SET_SRC (prev_set);
2942 base_insn = prev_insn;
2948 if (base == ep->to_rtx)
2951 = plus_constant (ep->to_rtx, offset - ep->offset);
2953 new_body = old_body;
2956 new_body = copy_insn (old_body);
2957 if (REG_NOTES (insn))
2958 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2960 PATTERN (insn) = new_body;
2961 old_set = single_set (insn);
2963 /* First see if this insn remains valid when we
2964 make the change. If not, keep the INSN_CODE
2965 the same and let reload fit it up. */
2966 validate_change (insn, &SET_SRC (old_set), src, 1);
2967 validate_change (insn, &SET_DEST (old_set),
2969 if (! apply_change_group ())
2971 SET_SRC (old_set) = src;
2972 SET_DEST (old_set) = ep->to_rtx;
2981 /* In this case this insn isn't serving a useful purpose. We
2982 will delete it in reload_as_needed once we know that this
2983 elimination is, in fact, being done.
2985 If REPLACE isn't set, we can't delete this insn, but needn't
2986 process it since it won't be used unless something changes. */
2989 delete_dead_insn (insn);
2997 /* We allow one special case which happens to work on all machines we
2998 currently support: a single set with the source or a REG_EQUAL
2999 note being a PLUS of an eliminable register and a constant. */
3001 if (old_set && REG_P (SET_DEST (old_set)))
3003 /* First see if the source is of the form (plus (reg) CST). */
3004 if (GET_CODE (SET_SRC (old_set)) == PLUS
3005 && REG_P (XEXP (SET_SRC (old_set), 0))
3006 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3007 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3008 plus_src = SET_SRC (old_set);
3009 else if (REG_P (SET_SRC (old_set)))
3011 /* Otherwise, see if we have a REG_EQUAL note of the form
3012 (plus (reg) CST). */
3014 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3016 if (REG_NOTE_KIND (links) == REG_EQUAL
3017 && GET_CODE (XEXP (links, 0)) == PLUS
3018 && REG_P (XEXP (XEXP (links, 0), 0))
3019 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
3020 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
3022 plus_src = XEXP (links, 0);
3030 rtx reg = XEXP (plus_src, 0);
3031 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3033 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3034 if (ep->from_rtx == reg && ep->can_eliminate)
3036 offset += ep->offset;
3041 /* We assume here that if we need a PARALLEL with
3042 CLOBBERs for this assignment, we can do with the
3043 MATCH_SCRATCHes that add_clobbers allocates.
3044 There's not much we can do if that doesn't work. */
3045 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3049 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3052 rtvec vec = rtvec_alloc (num_clobbers + 1);
3054 vec->elem[0] = PATTERN (insn);
3055 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3056 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3058 if (INSN_CODE (insn) < 0)
3061 /* If we have a nonzero offset, and the source is already
3062 a simple REG, the following transformation would
3063 increase the cost of the insn by replacing a simple REG
3064 with (plus (reg sp) CST). So try only when plus_src
3065 comes from old_set proper, not REG_NOTES. */
3066 else if (SET_SRC (old_set) == plus_src)
3068 new_body = old_body;
3071 new_body = copy_insn (old_body);
3072 if (REG_NOTES (insn))
3073 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3075 PATTERN (insn) = new_body;
3076 old_set = single_set (insn);
3078 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3079 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3085 /* This can't have an effect on elimination offsets, so skip right
3091 /* Determine the effects of this insn on elimination offsets. */
3092 elimination_effects (old_body, 0);
3094 /* Eliminate all eliminable registers occurring in operands that
3095 can be handled by reload. */
3096 extract_insn (insn);
3097 for (i = 0; i < recog_data.n_operands; i++)
3099 orig_operand[i] = recog_data.operand[i];
3100 substed_operand[i] = recog_data.operand[i];
3102 /* For an asm statement, every operand is eliminable. */
3103 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3105 /* Check for setting a register that we know about. */
3106 if (recog_data.operand_type[i] != OP_IN
3107 && REG_P (orig_operand[i]))
3109 /* If we are assigning to a register that can be eliminated, it
3110 must be as part of a PARALLEL, since the code above handles
3111 single SETs. We must indicate that we can no longer
3112 eliminate this reg. */
3113 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3115 if (ep->from_rtx == orig_operand[i])
3116 ep->can_eliminate = 0;
3119 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3120 replace ? insn : NULL_RTX);
3121 if (substed_operand[i] != orig_operand[i])
3123 /* Terminate the search in check_eliminable_occurrences at
3125 *recog_data.operand_loc[i] = 0;
3127 /* If an output operand changed from a REG to a MEM and INSN is an
3128 insn, write a CLOBBER insn. */
3129 if (recog_data.operand_type[i] != OP_IN
3130 && REG_P (orig_operand[i])
3131 && MEM_P (substed_operand[i])
3133 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3138 for (i = 0; i < recog_data.n_dups; i++)
3139 *recog_data.dup_loc[i]
3140 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3142 /* If any eliminable remain, they aren't eliminable anymore. */
3143 check_eliminable_occurrences (old_body);
3145 /* Substitute the operands; the new values are in the substed_operand
3147 for (i = 0; i < recog_data.n_operands; i++)
3148 *recog_data.operand_loc[i] = substed_operand[i];
3149 for (i = 0; i < recog_data.n_dups; i++)
3150 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3152 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3153 re-recognize the insn. We do this in case we had a simple addition
3154 but now can do this as a load-address. This saves an insn in this
3156 If re-recognition fails, the old insn code number will still be used,
3157 and some register operands may have changed into PLUS expressions.
3158 These will be handled by find_reloads by loading them into a register
3163 /* If we aren't replacing things permanently and we changed something,
3164 make another copy to ensure that all the RTL is new. Otherwise
3165 things can go wrong if find_reload swaps commutative operands
3166 and one is inside RTL that has been copied while the other is not. */
3167 new_body = old_body;
3170 new_body = copy_insn (old_body);
3171 if (REG_NOTES (insn))
3172 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3174 PATTERN (insn) = new_body;
3176 /* If we had a move insn but now we don't, rerecognize it. This will
3177 cause spurious re-recognition if the old move had a PARALLEL since
3178 the new one still will, but we can't call single_set without
3179 having put NEW_BODY into the insn and the re-recognition won't
3180 hurt in this rare case. */
3181 /* ??? Why this huge if statement - why don't we just rerecognize the
3185 && ((REG_P (SET_SRC (old_set))
3186 && (GET_CODE (new_body) != SET
3187 || !REG_P (SET_SRC (new_body))))
3188 /* If this was a load from or store to memory, compare
3189 the MEM in recog_data.operand to the one in the insn.
3190 If they are not equal, then rerecognize the insn. */
3192 && ((MEM_P (SET_SRC (old_set))
3193 && SET_SRC (old_set) != recog_data.operand[1])
3194 || (MEM_P (SET_DEST (old_set))
3195 && SET_DEST (old_set) != recog_data.operand[0])))
3196 /* If this was an add insn before, rerecognize. */
3197 || GET_CODE (SET_SRC (old_set)) == PLUS))
3199 int new_icode = recog (PATTERN (insn), insn, 0);
3201 INSN_CODE (insn) = icode;
3205 /* Restore the old body. If there were any changes to it, we made a copy
3206 of it while the changes were still in place, so we'll correctly return
3207 a modified insn below. */
3210 /* Restore the old body. */
3211 for (i = 0; i < recog_data.n_operands; i++)
3212 *recog_data.operand_loc[i] = orig_operand[i];
3213 for (i = 0; i < recog_data.n_dups; i++)
3214 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3217 /* Update all elimination pairs to reflect the status after the current
3218 insn. The changes we make were determined by the earlier call to
3219 elimination_effects.
3221 We also detect cases where register elimination cannot be done,
3222 namely, if a register would be both changed and referenced outside a MEM
3223 in the resulting insn since such an insn is often undefined and, even if
3224 not, we cannot know what meaning will be given to it. Note that it is
3225 valid to have a register used in an address in an insn that changes it
3226 (presumably with a pre- or post-increment or decrement).
3228 If anything changes, return nonzero. */
3230 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3232 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3233 ep->can_eliminate = 0;
3235 ep->ref_outside_mem = 0;
3237 if (ep->previous_offset != ep->offset)
3242 /* If we changed something, perform elimination in REG_NOTES. This is
3243 needed even when REPLACE is zero because a REG_DEAD note might refer
3244 to a register that we eliminate and could cause a different number
3245 of spill registers to be needed in the final reload pass than in
3247 if (val && REG_NOTES (insn) != 0)
3248 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3253 /* Loop through all elimination pairs.
3254 Recalculate the number not at initial offset.
3256 Compute the maximum offset (minimum offset if the stack does not
3257 grow downward) for each elimination pair. */
3260 update_eliminable_offsets (void)
3262 struct elim_table *ep;
3264 num_not_at_initial_offset = 0;
3265 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3267 ep->previous_offset = ep->offset;
3268 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3269 num_not_at_initial_offset++;
3273 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3274 replacement we currently believe is valid, mark it as not eliminable if X
3275 modifies DEST in any way other than by adding a constant integer to it.
3277 If DEST is the frame pointer, we do nothing because we assume that
3278 all assignments to the hard frame pointer are nonlocal gotos and are being
3279 done at a time when they are valid and do not disturb anything else.
3280 Some machines want to eliminate a fake argument pointer with either the
3281 frame or stack pointer. Assignments to the hard frame pointer must not
3282 prevent this elimination.
3284 Called via note_stores from reload before starting its passes to scan
3285 the insns of the function. */
3288 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3292 /* A SUBREG of a hard register here is just changing its mode. We should
3293 not see a SUBREG of an eliminable hard register, but check just in
3295 if (GET_CODE (dest) == SUBREG)
3296 dest = SUBREG_REG (dest);
3298 if (dest == hard_frame_pointer_rtx)
3301 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3302 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3303 && (GET_CODE (x) != SET
3304 || GET_CODE (SET_SRC (x)) != PLUS
3305 || XEXP (SET_SRC (x), 0) != dest
3306 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3308 reg_eliminate[i].can_eliminate_previous
3309 = reg_eliminate[i].can_eliminate = 0;
3314 /* Verify that the initial elimination offsets did not change since the
3315 last call to set_initial_elim_offsets. This is used to catch cases
3316 where something illegal happened during reload_as_needed that could
3317 cause incorrect code to be generated if we did not check for it. */
3320 verify_initial_elim_offsets (void)
3324 #ifdef ELIMINABLE_REGS
3325 struct elim_table *ep;
3327 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3329 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3330 if (t != ep->initial_offset)
3334 INITIAL_FRAME_POINTER_OFFSET (t);
3335 if (t != reg_eliminate[0].initial_offset)
3340 /* Reset all offsets on eliminable registers to their initial values. */
3343 set_initial_elim_offsets (void)
3345 struct elim_table *ep = reg_eliminate;
3347 #ifdef ELIMINABLE_REGS
3348 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3350 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3351 ep->previous_offset = ep->offset = ep->initial_offset;
3354 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3355 ep->previous_offset = ep->offset = ep->initial_offset;
3358 num_not_at_initial_offset = 0;
3361 /* Initialize the known label offsets.
3362 Set a known offset for each forced label to be at the initial offset
3363 of each elimination. We do this because we assume that all
3364 computed jumps occur from a location where each elimination is
3365 at its initial offset.
3366 For all other labels, show that we don't know the offsets. */
3369 set_initial_label_offsets (void)
3372 memset (offsets_known_at, 0, num_labels);
3374 for (x = forced_labels; x; x = XEXP (x, 1))
3376 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3379 /* Set all elimination offsets to the known values for the code label given
3383 set_offsets_for_label (rtx insn)
3386 int label_nr = CODE_LABEL_NUMBER (insn);
3387 struct elim_table *ep;
3389 num_not_at_initial_offset = 0;
3390 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3392 ep->offset = ep->previous_offset
3393 = offsets_at[label_nr - first_label_num][i];
3394 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3395 num_not_at_initial_offset++;
3399 /* See if anything that happened changes which eliminations are valid.
3400 For example, on the SPARC, whether or not the frame pointer can
3401 be eliminated can depend on what registers have been used. We need
3402 not check some conditions again (such as flag_omit_frame_pointer)
3403 since they can't have changed. */
3406 update_eliminables (HARD_REG_SET *pset)
3408 int previous_frame_pointer_needed = frame_pointer_needed;
3409 struct elim_table *ep;
3411 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3412 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3413 #ifdef ELIMINABLE_REGS
3414 || ! CAN_ELIMINATE (ep->from, ep->to)
3417 ep->can_eliminate = 0;
3419 /* Look for the case where we have discovered that we can't replace
3420 register A with register B and that means that we will now be
3421 trying to replace register A with register C. This means we can
3422 no longer replace register C with register B and we need to disable
3423 such an elimination, if it exists. This occurs often with A == ap,
3424 B == sp, and C == fp. */
3426 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3428 struct elim_table *op;
3431 if (! ep->can_eliminate && ep->can_eliminate_previous)
3433 /* Find the current elimination for ep->from, if there is a
3435 for (op = reg_eliminate;
3436 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3437 if (op->from == ep->from && op->can_eliminate)
3443 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3445 for (op = reg_eliminate;
3446 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3447 if (op->from == new_to && op->to == ep->to)
3448 op->can_eliminate = 0;
3452 /* See if any registers that we thought we could eliminate the previous
3453 time are no longer eliminable. If so, something has changed and we
3454 must spill the register. Also, recompute the number of eliminable
3455 registers and see if the frame pointer is needed; it is if there is
3456 no elimination of the frame pointer that we can perform. */
3458 frame_pointer_needed = 1;
3459 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3461 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3462 && ep->to != HARD_FRAME_POINTER_REGNUM)
3463 frame_pointer_needed = 0;
3465 if (! ep->can_eliminate && ep->can_eliminate_previous)
3467 ep->can_eliminate_previous = 0;
3468 SET_HARD_REG_BIT (*pset, ep->from);
3473 /* If we didn't need a frame pointer last time, but we do now, spill
3474 the hard frame pointer. */
3475 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3476 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3479 /* Initialize the table of registers to eliminate. */
3482 init_elim_table (void)
3484 struct elim_table *ep;
3485 #ifdef ELIMINABLE_REGS
3486 const struct elim_table_1 *ep1;
3490 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3492 /* Does this function require a frame pointer? */
3494 frame_pointer_needed = (! flag_omit_frame_pointer
3495 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3496 and restore sp for alloca. So we can't eliminate
3497 the frame pointer in that case. At some point,
3498 we should improve this by emitting the
3499 sp-adjusting insns for this case. */
3500 || (current_function_calls_alloca
3501 && EXIT_IGNORE_STACK)
3502 || FRAME_POINTER_REQUIRED);
3506 #ifdef ELIMINABLE_REGS
3507 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3508 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3510 ep->from = ep1->from;
3512 ep->can_eliminate = ep->can_eliminate_previous
3513 = (CAN_ELIMINATE (ep->from, ep->to)
3514 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3517 reg_eliminate[0].from = reg_eliminate_1[0].from;
3518 reg_eliminate[0].to = reg_eliminate_1[0].to;
3519 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3520 = ! frame_pointer_needed;
3523 /* Count the number of eliminable registers and build the FROM and TO
3524 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3525 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3526 We depend on this. */
3527 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3529 num_eliminable += ep->can_eliminate;
3530 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3531 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3535 /* Kick all pseudos out of hard register REGNO.
3537 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3538 because we found we can't eliminate some register. In the case, no pseudos
3539 are allowed to be in the register, even if they are only in a block that
3540 doesn't require spill registers, unlike the case when we are spilling this
3541 hard reg to produce another spill register.
3543 Return nonzero if any pseudos needed to be kicked out. */
3546 spill_hard_reg (unsigned int regno, int cant_eliminate)
3552 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3553 regs_ever_live[regno] = 1;
3556 /* Spill every pseudo reg that was allocated to this reg
3557 or to something that overlaps this reg. */
3559 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3560 if (reg_renumber[i] >= 0
3561 && (unsigned int) reg_renumber[i] <= regno
3562 && ((unsigned int) reg_renumber[i]
3563 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3564 [PSEUDO_REGNO_MODE (i)]
3566 SET_REGNO_REG_SET (&spilled_pseudos, i);
3569 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3570 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3573 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3575 IOR_HARD_REG_SET (*set1, *set2);
3578 /* After find_reload_regs has been run for all insn that need reloads,
3579 and/or spill_hard_regs was called, this function is used to actually
3580 spill pseudo registers and try to reallocate them. It also sets up the
3581 spill_regs array for use by choose_reload_regs. */
3584 finish_spills (int global)
3586 struct insn_chain *chain;
3587 int something_changed = 0;
3590 /* Build the spill_regs array for the function. */
3591 /* If there are some registers still to eliminate and one of the spill regs
3592 wasn't ever used before, additional stack space may have to be
3593 allocated to store this register. Thus, we may have changed the offset
3594 between the stack and frame pointers, so mark that something has changed.
3596 One might think that we need only set VAL to 1 if this is a call-used
3597 register. However, the set of registers that must be saved by the
3598 prologue is not identical to the call-used set. For example, the
3599 register used by the call insn for the return PC is a call-used register,
3600 but must be saved by the prologue. */
3603 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3604 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3606 spill_reg_order[i] = n_spills;
3607 spill_regs[n_spills++] = i;
3608 if (num_eliminable && ! regs_ever_live[i])
3609 something_changed = 1;
3610 regs_ever_live[i] = 1;
3613 spill_reg_order[i] = -1;
3615 EXECUTE_IF_SET_IN_REG_SET
3616 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3618 /* Record the current hard register the pseudo is allocated to in
3619 pseudo_previous_regs so we avoid reallocating it to the same
3620 hard reg in a later pass. */
3621 if (reg_renumber[i] < 0)
3624 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3625 /* Mark it as no longer having a hard register home. */
3626 reg_renumber[i] = -1;
3627 /* We will need to scan everything again. */
3628 something_changed = 1;
3631 /* Retry global register allocation if possible. */
3634 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3635 /* For every insn that needs reloads, set the registers used as spill
3636 regs in pseudo_forbidden_regs for every pseudo live across the
3638 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3640 EXECUTE_IF_SET_IN_REG_SET
3641 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3643 ior_hard_reg_set (pseudo_forbidden_regs + i,
3644 &chain->used_spill_regs);
3646 EXECUTE_IF_SET_IN_REG_SET
3647 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3649 ior_hard_reg_set (pseudo_forbidden_regs + i,
3650 &chain->used_spill_regs);
3654 /* Retry allocating the spilled pseudos. For each reg, merge the
3655 various reg sets that indicate which hard regs can't be used,
3656 and call retry_global_alloc.
3657 We change spill_pseudos here to only contain pseudos that did not
3658 get a new hard register. */
3659 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3660 if (reg_old_renumber[i] != reg_renumber[i])
3662 HARD_REG_SET forbidden;
3663 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3664 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3665 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3666 retry_global_alloc (i, forbidden);
3667 if (reg_renumber[i] >= 0)
3668 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3672 /* Fix up the register information in the insn chain.
3673 This involves deleting those of the spilled pseudos which did not get
3674 a new hard register home from the live_{before,after} sets. */
3675 for (chain = reload_insn_chain; chain; chain = chain->next)
3677 HARD_REG_SET used_by_pseudos;
3678 HARD_REG_SET used_by_pseudos2;
3680 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3681 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3683 /* Mark any unallocated hard regs as available for spills. That
3684 makes inheritance work somewhat better. */
3685 if (chain->need_reload)
3687 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3688 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3689 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3691 /* Save the old value for the sanity test below. */
3692 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3694 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3695 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3696 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3697 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3699 /* Make sure we only enlarge the set. */
3700 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3706 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3707 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3709 int regno = reg_renumber[i];
3710 if (reg_old_renumber[i] == regno)
3713 alter_reg (i, reg_old_renumber[i]);
3714 reg_old_renumber[i] = regno;
3718 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3720 fprintf (dump_file, " Register %d now in %d.\n\n",
3721 i, reg_renumber[i]);
3725 return something_changed;
3728 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3731 scan_paradoxical_subregs (rtx x)
3735 enum rtx_code code = GET_CODE (x);
3745 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3753 if (REG_P (SUBREG_REG (x))
3754 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3755 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3756 = GET_MODE_SIZE (GET_MODE (x));
3763 fmt = GET_RTX_FORMAT (code);
3764 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3767 scan_paradoxical_subregs (XEXP (x, i));
3768 else if (fmt[i] == 'E')
3771 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3772 scan_paradoxical_subregs (XVECEXP (x, i, j));
3777 /* Reload pseudo-registers into hard regs around each insn as needed.
3778 Additional register load insns are output before the insn that needs it
3779 and perhaps store insns after insns that modify the reloaded pseudo reg.
3781 reg_last_reload_reg and reg_reloaded_contents keep track of
3782 which registers are already available in reload registers.
3783 We update these for the reloads that we perform,
3784 as the insns are scanned. */
3787 reload_as_needed (int live_known)
3789 struct insn_chain *chain;
3790 #if defined (AUTO_INC_DEC)
3795 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3796 memset (spill_reg_store, 0, sizeof spill_reg_store);
3797 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3798 reg_has_output_reload = xmalloc (max_regno);
3799 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3800 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3802 set_initial_elim_offsets ();
3804 for (chain = reload_insn_chain; chain; chain = chain->next)
3807 rtx insn = chain->insn;
3808 rtx old_next = NEXT_INSN (insn);
3810 /* If we pass a label, copy the offsets from the label information
3811 into the current offsets of each elimination. */
3812 if (GET_CODE (insn) == CODE_LABEL)
3813 set_offsets_for_label (insn);
3815 else if (INSN_P (insn))
3817 rtx oldpat = copy_rtx (PATTERN (insn));
3819 /* If this is a USE and CLOBBER of a MEM, ensure that any
3820 references to eliminable registers have been removed. */
3822 if ((GET_CODE (PATTERN (insn)) == USE
3823 || GET_CODE (PATTERN (insn)) == CLOBBER)
3824 && MEM_P (XEXP (PATTERN (insn), 0)))
3825 XEXP (XEXP (PATTERN (insn), 0), 0)
3826 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3827 GET_MODE (XEXP (PATTERN (insn), 0)),
3830 /* If we need to do register elimination processing, do so.
3831 This might delete the insn, in which case we are done. */
3832 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3834 eliminate_regs_in_insn (insn, 1);
3835 if (GET_CODE (insn) == NOTE)
3837 update_eliminable_offsets ();
3842 /* If need_elim is nonzero but need_reload is zero, one might think
3843 that we could simply set n_reloads to 0. However, find_reloads
3844 could have done some manipulation of the insn (such as swapping
3845 commutative operands), and these manipulations are lost during
3846 the first pass for every insn that needs register elimination.
3847 So the actions of find_reloads must be redone here. */
3849 if (! chain->need_elim && ! chain->need_reload
3850 && ! chain->need_operand_change)
3852 /* First find the pseudo regs that must be reloaded for this insn.
3853 This info is returned in the tables reload_... (see reload.h).
3854 Also modify the body of INSN by substituting RELOAD
3855 rtx's for those pseudo regs. */
3858 memset (reg_has_output_reload, 0, max_regno);
3859 CLEAR_HARD_REG_SET (reg_is_output_reload);
3861 find_reloads (insn, 1, spill_indirect_levels, live_known,
3867 rtx next = NEXT_INSN (insn);
3870 prev = PREV_INSN (insn);
3872 /* Now compute which reload regs to reload them into. Perhaps
3873 reusing reload regs from previous insns, or else output
3874 load insns to reload them. Maybe output store insns too.
3875 Record the choices of reload reg in reload_reg_rtx. */
3876 choose_reload_regs (chain);
3878 /* Merge any reloads that we didn't combine for fear of
3879 increasing the number of spill registers needed but now
3880 discover can be safely merged. */
3881 if (SMALL_REGISTER_CLASSES)
3882 merge_assigned_reloads (insn);
3884 /* Generate the insns to reload operands into or out of
3885 their reload regs. */
3886 emit_reload_insns (chain);
3888 /* Substitute the chosen reload regs from reload_reg_rtx
3889 into the insn's body (or perhaps into the bodies of other
3890 load and store insn that we just made for reloading
3891 and that we moved the structure into). */
3892 subst_reloads (insn);
3894 /* If this was an ASM, make sure that all the reload insns
3895 we have generated are valid. If not, give an error
3898 if (asm_noperands (PATTERN (insn)) >= 0)
3899 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3900 if (p != insn && INSN_P (p)
3901 && GET_CODE (PATTERN (p)) != USE
3902 && (recog_memoized (p) < 0
3903 || (extract_insn (p), ! constrain_operands (1))))
3905 error_for_asm (insn,
3906 "`asm' operand requires impossible reload");
3911 if (num_eliminable && chain->need_elim)
3912 update_eliminable_offsets ();
3914 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3915 is no longer validly lying around to save a future reload.
3916 Note that this does not detect pseudos that were reloaded
3917 for this insn in order to be stored in
3918 (obeying register constraints). That is correct; such reload
3919 registers ARE still valid. */
3920 note_stores (oldpat, forget_old_reloads_1, NULL);
3922 /* There may have been CLOBBER insns placed after INSN. So scan
3923 between INSN and NEXT and use them to forget old reloads. */
3924 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3925 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3926 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3929 /* Likewise for regs altered by auto-increment in this insn.
3930 REG_INC notes have been changed by reloading:
3931 find_reloads_address_1 records substitutions for them,
3932 which have been performed by subst_reloads above. */
3933 for (i = n_reloads - 1; i >= 0; i--)
3935 rtx in_reg = rld[i].in_reg;
3938 enum rtx_code code = GET_CODE (in_reg);
3939 /* PRE_INC / PRE_DEC will have the reload register ending up
3940 with the same value as the stack slot, but that doesn't
3941 hold true for POST_INC / POST_DEC. Either we have to
3942 convert the memory access to a true POST_INC / POST_DEC,
3943 or we can't use the reload register for inheritance. */
3944 if ((code == POST_INC || code == POST_DEC)
3945 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3946 REGNO (rld[i].reg_rtx))
3947 /* Make sure it is the inc/dec pseudo, and not
3948 some other (e.g. output operand) pseudo. */
3949 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3950 == REGNO (XEXP (in_reg, 0))))
3953 rtx reload_reg = rld[i].reg_rtx;
3954 enum machine_mode mode = GET_MODE (reload_reg);
3958 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3960 /* We really want to ignore REG_INC notes here, so
3961 use PATTERN (p) as argument to reg_set_p . */
3962 if (reg_set_p (reload_reg, PATTERN (p)))
3964 n = count_occurrences (PATTERN (p), reload_reg, 0);
3969 n = validate_replace_rtx (reload_reg,
3970 gen_rtx_fmt_e (code,
3975 /* We must also verify that the constraints
3976 are met after the replacement. */
3979 n = constrain_operands (1);
3983 /* If the constraints were not met, then
3984 undo the replacement. */
3987 validate_replace_rtx (gen_rtx_fmt_e (code,
4000 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4002 /* Mark this as having an output reload so that the
4003 REG_INC processing code below won't invalidate
4004 the reload for inheritance. */
4005 SET_HARD_REG_BIT (reg_is_output_reload,
4006 REGNO (reload_reg));
4007 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4010 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4013 else if ((code == PRE_INC || code == PRE_DEC)
4014 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4015 REGNO (rld[i].reg_rtx))
4016 /* Make sure it is the inc/dec pseudo, and not
4017 some other (e.g. output operand) pseudo. */
4018 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4019 == REGNO (XEXP (in_reg, 0))))
4021 SET_HARD_REG_BIT (reg_is_output_reload,
4022 REGNO (rld[i].reg_rtx));
4023 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4027 /* If a pseudo that got a hard register is auto-incremented,
4028 we must purge records of copying it into pseudos without
4030 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4031 if (REG_NOTE_KIND (x) == REG_INC)
4033 /* See if this pseudo reg was reloaded in this insn.
4034 If so, its last-reload info is still valid
4035 because it is based on this insn's reload. */
4036 for (i = 0; i < n_reloads; i++)
4037 if (rld[i].out == XEXP (x, 0))
4041 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4045 /* A reload reg's contents are unknown after a label. */
4046 if (GET_CODE (insn) == CODE_LABEL)
4047 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4049 /* Don't assume a reload reg is still good after a call insn
4050 if it is a call-used reg, or if it contains a value that will
4051 be partially clobbered by the call. */
4052 else if (GET_CODE (insn) == CALL_INSN)
4054 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4055 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4060 free (reg_last_reload_reg);
4061 free (reg_has_output_reload);
4064 /* Discard all record of any value reloaded from X,
4065 or reloaded in X from someplace else;
4066 unless X is an output reload reg of the current insn.
4068 X may be a hard reg (the reload reg)
4069 or it may be a pseudo reg that was reloaded from. */
4072 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4073 void *data ATTRIBUTE_UNUSED)
4078 /* note_stores does give us subregs of hard regs,
4079 subreg_regno_offset will abort if it is not a hard reg. */
4080 while (GET_CODE (x) == SUBREG)
4082 /* We ignore the subreg offset when calculating the regno,
4083 because we are using the entire underlying hard register
4093 if (regno >= FIRST_PSEUDO_REGISTER)
4099 nr = hard_regno_nregs[regno][GET_MODE (x)];
4100 /* Storing into a spilled-reg invalidates its contents.
4101 This can happen if a block-local pseudo is allocated to that reg
4102 and it wasn't spilled because this block's total need is 0.
4103 Then some insn might have an optional reload and use this reg. */
4104 for (i = 0; i < nr; i++)
4105 /* But don't do this if the reg actually serves as an output
4106 reload reg in the current instruction. */
4108 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4110 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4111 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4112 spill_reg_store[regno + i] = 0;
4116 /* Since value of X has changed,
4117 forget any value previously copied from it. */
4120 /* But don't forget a copy if this is the output reload
4121 that establishes the copy's validity. */
4122 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4123 reg_last_reload_reg[regno + nr] = 0;
4126 /* The following HARD_REG_SETs indicate when each hard register is
4127 used for a reload of various parts of the current insn. */
4129 /* If reg is unavailable for all reloads. */
4130 static HARD_REG_SET reload_reg_unavailable;
4131 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4132 static HARD_REG_SET reload_reg_used;
4133 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4134 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4135 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4136 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4137 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4138 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4139 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4140 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4141 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4142 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4143 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4144 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4145 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4146 static HARD_REG_SET reload_reg_used_in_op_addr;
4147 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4148 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4149 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4150 static HARD_REG_SET reload_reg_used_in_insn;
4151 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4152 static HARD_REG_SET reload_reg_used_in_other_addr;
4154 /* If reg is in use as a reload reg for any sort of reload. */
4155 static HARD_REG_SET reload_reg_used_at_all;
4157 /* If reg is use as an inherited reload. We just mark the first register
4159 static HARD_REG_SET reload_reg_used_for_inherit;
4161 /* Records which hard regs are used in any way, either as explicit use or
4162 by being allocated to a pseudo during any point of the current insn. */
4163 static HARD_REG_SET reg_used_in_insn;
4165 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4166 TYPE. MODE is used to indicate how many consecutive regs are
4170 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4171 enum machine_mode mode)
4173 unsigned int nregs = hard_regno_nregs[regno][mode];
4176 for (i = regno; i < nregs + regno; i++)
4181 SET_HARD_REG_BIT (reload_reg_used, i);
4184 case RELOAD_FOR_INPUT_ADDRESS:
4185 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4188 case RELOAD_FOR_INPADDR_ADDRESS:
4189 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4192 case RELOAD_FOR_OUTPUT_ADDRESS:
4193 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4196 case RELOAD_FOR_OUTADDR_ADDRESS:
4197 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4200 case RELOAD_FOR_OPERAND_ADDRESS:
4201 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4204 case RELOAD_FOR_OPADDR_ADDR:
4205 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4208 case RELOAD_FOR_OTHER_ADDRESS:
4209 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4212 case RELOAD_FOR_INPUT:
4213 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4216 case RELOAD_FOR_OUTPUT:
4217 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4220 case RELOAD_FOR_INSN:
4221 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4225 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4229 /* Similarly, but show REGNO is no longer in use for a reload. */
4232 clear_reload_reg_in_use (unsigned int regno, int opnum,
4233 enum reload_type type, enum machine_mode mode)
4235 unsigned int nregs = hard_regno_nregs[regno][mode];
4236 unsigned int start_regno, end_regno, r;
4238 /* A complication is that for some reload types, inheritance might
4239 allow multiple reloads of the same types to share a reload register.
4240 We set check_opnum if we have to check only reloads with the same
4241 operand number, and check_any if we have to check all reloads. */
4242 int check_opnum = 0;
4244 HARD_REG_SET *used_in_set;
4249 used_in_set = &reload_reg_used;
4252 case RELOAD_FOR_INPUT_ADDRESS:
4253 used_in_set = &reload_reg_used_in_input_addr[opnum];
4256 case RELOAD_FOR_INPADDR_ADDRESS:
4258 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4261 case RELOAD_FOR_OUTPUT_ADDRESS:
4262 used_in_set = &reload_reg_used_in_output_addr[opnum];
4265 case RELOAD_FOR_OUTADDR_ADDRESS:
4267 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4270 case RELOAD_FOR_OPERAND_ADDRESS:
4271 used_in_set = &reload_reg_used_in_op_addr;
4274 case RELOAD_FOR_OPADDR_ADDR:
4276 used_in_set = &reload_reg_used_in_op_addr_reload;
4279 case RELOAD_FOR_OTHER_ADDRESS:
4280 used_in_set = &reload_reg_used_in_other_addr;
4284 case RELOAD_FOR_INPUT:
4285 used_in_set = &reload_reg_used_in_input[opnum];
4288 case RELOAD_FOR_OUTPUT:
4289 used_in_set = &reload_reg_used_in_output[opnum];
4292 case RELOAD_FOR_INSN:
4293 used_in_set = &reload_reg_used_in_insn;
4298 /* We resolve conflicts with remaining reloads of the same type by
4299 excluding the intervals of reload registers by them from the
4300 interval of freed reload registers. Since we only keep track of
4301 one set of interval bounds, we might have to exclude somewhat
4302 more than what would be necessary if we used a HARD_REG_SET here.
4303 But this should only happen very infrequently, so there should
4304 be no reason to worry about it. */
4306 start_regno = regno;
4307 end_regno = regno + nregs;
4308 if (check_opnum || check_any)
4310 for (i = n_reloads - 1; i >= 0; i--)
4312 if (rld[i].when_needed == type
4313 && (check_any || rld[i].opnum == opnum)
4316 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4317 unsigned int conflict_end
4319 + hard_regno_nregs[conflict_start][rld[i].mode]);
4321 /* If there is an overlap with the first to-be-freed register,
4322 adjust the interval start. */
4323 if (conflict_start <= start_regno && conflict_end > start_regno)
4324 start_regno = conflict_end;
4325 /* Otherwise, if there is a conflict with one of the other
4326 to-be-freed registers, adjust the interval end. */
4327 if (conflict_start > start_regno && conflict_start < end_regno)
4328 end_regno = conflict_start;
4333 for (r = start_regno; r < end_regno; r++)
4334 CLEAR_HARD_REG_BIT (*used_in_set, r);
4337 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4338 specified by OPNUM and TYPE. */
4341 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4345 /* In use for a RELOAD_OTHER means it's not available for anything. */
4346 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4347 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4353 /* In use for anything means we can't use it for RELOAD_OTHER. */
4354 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4355 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4356 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4357 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4360 for (i = 0; i < reload_n_operands; i++)
4361 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4362 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4363 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4364 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4365 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4366 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4371 case RELOAD_FOR_INPUT:
4372 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4373 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4379 /* If it is used for some other input, can't use it. */
4380 for (i = 0; i < reload_n_operands; i++)
4381 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4384 /* If it is used in a later operand's address, can't use it. */
4385 for (i = opnum + 1; i < reload_n_operands; i++)
4386 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4387 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4392 case RELOAD_FOR_INPUT_ADDRESS:
4393 /* Can't use a register if it is used for an input address for this
4394 operand or used as an input in an earlier one. */
4395 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4396 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4399 for (i = 0; i < opnum; i++)
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4405 case RELOAD_FOR_INPADDR_ADDRESS:
4406 /* Can't use a register if it is used for an input address
4407 for this operand or used as an input in an earlier
4409 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4412 for (i = 0; i < opnum; i++)
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4418 case RELOAD_FOR_OUTPUT_ADDRESS:
4419 /* Can't use a register if it is used for an output address for this
4420 operand or used as an output in this or a later operand. Note
4421 that multiple output operands are emitted in reverse order, so
4422 the conflicting ones are those with lower indices. */
4423 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4426 for (i = 0; i <= opnum; i++)
4427 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4432 case RELOAD_FOR_OUTADDR_ADDRESS:
4433 /* Can't use a register if it is used for an output address
4434 for this operand or used as an output in this or a
4435 later operand. Note that multiple output operands are
4436 emitted in reverse order, so the conflicting ones are
4437 those with lower indices. */
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4441 for (i = 0; i <= opnum; i++)
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4447 case RELOAD_FOR_OPERAND_ADDRESS:
4448 for (i = 0; i < reload_n_operands; i++)
4449 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4452 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4453 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4455 case RELOAD_FOR_OPADDR_ADDR:
4456 for (i = 0; i < reload_n_operands; i++)
4457 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4460 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4462 case RELOAD_FOR_OUTPUT:
4463 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4464 outputs, or an operand address for this or an earlier output.
4465 Note that multiple output operands are emitted in reverse order,
4466 so the conflicting ones are those with higher indices. */
4467 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4470 for (i = 0; i < reload_n_operands; i++)
4471 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4474 for (i = opnum; i < reload_n_operands; i++)
4475 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4476 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4481 case RELOAD_FOR_INSN:
4482 for (i = 0; i < reload_n_operands; i++)
4483 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4484 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4487 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4488 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4490 case RELOAD_FOR_OTHER_ADDRESS:
4491 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4496 /* Return 1 if the value in reload reg REGNO, as used by a reload
4497 needed for the part of the insn specified by OPNUM and TYPE,
4498 is still available in REGNO at the end of the insn.
4500 We can assume that the reload reg was already tested for availability
4501 at the time it is needed, and we should not check this again,
4502 in case the reg has already been marked in use. */
4505 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4512 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4513 its value must reach the end. */
4516 /* If this use is for part of the insn,
4517 its value reaches if no subsequent part uses the same register.
4518 Just like the above function, don't try to do this with lots
4521 case RELOAD_FOR_OTHER_ADDRESS:
4522 /* Here we check for everything else, since these don't conflict
4523 with anything else and everything comes later. */
4525 for (i = 0; i < reload_n_operands; i++)
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4529 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4531 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4534 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4535 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4536 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4537 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4539 case RELOAD_FOR_INPUT_ADDRESS:
4540 case RELOAD_FOR_INPADDR_ADDRESS:
4541 /* Similar, except that we check only for this and subsequent inputs
4542 and the address of only subsequent inputs and we do not need
4543 to check for RELOAD_OTHER objects since they are known not to
4546 for (i = opnum; i < reload_n_operands; i++)
4547 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4550 for (i = opnum + 1; i < reload_n_operands; i++)
4551 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4552 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4555 for (i = 0; i < reload_n_operands; i++)
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4558 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4561 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4564 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4565 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4566 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4568 case RELOAD_FOR_INPUT:
4569 /* Similar to input address, except we start at the next operand for
4570 both input and input address and we do not check for
4571 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4574 for (i = opnum + 1; i < reload_n_operands; i++)
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4577 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4580 /* ... fall through ... */
4582 case RELOAD_FOR_OPERAND_ADDRESS:
4583 /* Check outputs and their addresses. */
4585 for (i = 0; i < reload_n_operands; i++)
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4587 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4588 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4591 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4593 case RELOAD_FOR_OPADDR_ADDR:
4594 for (i = 0; i < reload_n_operands; i++)
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4597 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4600 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4601 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4602 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4604 case RELOAD_FOR_INSN:
4605 /* These conflict with other outputs with RELOAD_OTHER. So
4606 we need only check for output addresses. */
4608 opnum = reload_n_operands;
4610 /* ... fall through ... */
4612 case RELOAD_FOR_OUTPUT:
4613 case RELOAD_FOR_OUTPUT_ADDRESS:
4614 case RELOAD_FOR_OUTADDR_ADDRESS:
4615 /* We already know these can't conflict with a later output. So the
4616 only thing to check are later output addresses.
4617 Note that multiple output operands are emitted in reverse order,
4618 so the conflicting ones are those with lower indices. */
4619 for (i = 0; i < opnum; i++)
4620 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4621 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4630 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4633 This function uses the same algorithm as reload_reg_free_p above. */
4636 reloads_conflict (int r1, int r2)
4638 enum reload_type r1_type = rld[r1].when_needed;
4639 enum reload_type r2_type = rld[r2].when_needed;
4640 int r1_opnum = rld[r1].opnum;
4641 int r2_opnum = rld[r2].opnum;
4643 /* RELOAD_OTHER conflicts with everything. */
4644 if (r2_type == RELOAD_OTHER)
4647 /* Otherwise, check conflicts differently for each type. */
4651 case RELOAD_FOR_INPUT:
4652 return (r2_type == RELOAD_FOR_INSN
4653 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4654 || r2_type == RELOAD_FOR_OPADDR_ADDR
4655 || r2_type == RELOAD_FOR_INPUT
4656 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4657 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4658 && r2_opnum > r1_opnum));
4660 case RELOAD_FOR_INPUT_ADDRESS:
4661 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4662 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4664 case RELOAD_FOR_INPADDR_ADDRESS:
4665 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4666 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4668 case RELOAD_FOR_OUTPUT_ADDRESS:
4669 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4670 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4672 case RELOAD_FOR_OUTADDR_ADDRESS:
4673 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4674 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4676 case RELOAD_FOR_OPERAND_ADDRESS:
4677 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4678 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4680 case RELOAD_FOR_OPADDR_ADDR:
4681 return (r2_type == RELOAD_FOR_INPUT
4682 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4684 case RELOAD_FOR_OUTPUT:
4685 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4686 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4687 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4688 && r2_opnum >= r1_opnum));
4690 case RELOAD_FOR_INSN:
4691 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4692 || r2_type == RELOAD_FOR_INSN
4693 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4695 case RELOAD_FOR_OTHER_ADDRESS:
4696 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4706 /* Indexed by reload number, 1 if incoming value
4707 inherited from previous insns. */
4708 char reload_inherited[MAX_RELOADS];
4710 /* For an inherited reload, this is the insn the reload was inherited from,
4711 if we know it. Otherwise, this is 0. */
4712 rtx reload_inheritance_insn[MAX_RELOADS];
4714 /* If nonzero, this is a place to get the value of the reload,
4715 rather than using reload_in. */
4716 rtx reload_override_in[MAX_RELOADS];
4718 /* For each reload, the hard register number of the register used,
4719 or -1 if we did not need a register for this reload. */
4720 int reload_spill_index[MAX_RELOADS];
4722 /* Subroutine of free_for_value_p, used to check a single register.
4723 START_REGNO is the starting regno of the full reload register
4724 (possibly comprising multiple hard registers) that we are considering. */
4727 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4728 enum reload_type type, rtx value, rtx out,
4729 int reloadnum, int ignore_address_reloads)
4732 /* Set if we see an input reload that must not share its reload register
4733 with any new earlyclobber, but might otherwise share the reload
4734 register with an output or input-output reload. */
4735 int check_earlyclobber = 0;
4739 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4742 if (out == const0_rtx)
4748 /* We use some pseudo 'time' value to check if the lifetimes of the
4749 new register use would overlap with the one of a previous reload
4750 that is not read-only or uses a different value.
4751 The 'time' used doesn't have to be linear in any shape or form, just
4753 Some reload types use different 'buckets' for each operand.
4754 So there are MAX_RECOG_OPERANDS different time values for each
4756 We compute TIME1 as the time when the register for the prospective
4757 new reload ceases to be live, and TIME2 for each existing
4758 reload as the time when that the reload register of that reload
4760 Where there is little to be gained by exact lifetime calculations,
4761 we just make conservative assumptions, i.e. a longer lifetime;
4762 this is done in the 'default:' cases. */
4765 case RELOAD_FOR_OTHER_ADDRESS:
4766 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4767 time1 = copy ? 0 : 1;
4770 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4772 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4773 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4774 respectively, to the time values for these, we get distinct time
4775 values. To get distinct time values for each operand, we have to
4776 multiply opnum by at least three. We round that up to four because
4777 multiply by four is often cheaper. */
4778 case RELOAD_FOR_INPADDR_ADDRESS:
4779 time1 = opnum * 4 + 2;
4781 case RELOAD_FOR_INPUT_ADDRESS:
4782 time1 = opnum * 4 + 3;
4784 case RELOAD_FOR_INPUT:
4785 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4786 executes (inclusive). */
4787 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4789 case RELOAD_FOR_OPADDR_ADDR:
4791 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4792 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4794 case RELOAD_FOR_OPERAND_ADDRESS:
4795 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4797 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4799 case RELOAD_FOR_OUTADDR_ADDRESS:
4800 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4802 case RELOAD_FOR_OUTPUT_ADDRESS:
4803 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4806 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4809 for (i = 0; i < n_reloads; i++)
4811 rtx reg = rld[i].reg_rtx;
4812 if (reg && REG_P (reg)
4813 && ((unsigned) regno - true_regnum (reg)
4814 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4817 rtx other_input = rld[i].in;
4819 /* If the other reload loads the same input value, that
4820 will not cause a conflict only if it's loading it into
4821 the same register. */
4822 if (true_regnum (reg) != start_regno)
4823 other_input = NULL_RTX;
4824 if (! other_input || ! rtx_equal_p (other_input, value)
4825 || rld[i].out || out)
4828 switch (rld[i].when_needed)
4830 case RELOAD_FOR_OTHER_ADDRESS:
4833 case RELOAD_FOR_INPADDR_ADDRESS:
4834 /* find_reloads makes sure that a
4835 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4836 by at most one - the first -
4837 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4838 address reload is inherited, the address address reload
4839 goes away, so we can ignore this conflict. */
4840 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4841 && ignore_address_reloads
4842 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4843 Then the address address is still needed to store
4844 back the new address. */
4845 && ! rld[reloadnum].out)
4847 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4848 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4850 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4851 && ignore_address_reloads
4852 /* Unless we are reloading an auto_inc expression. */
4853 && ! rld[reloadnum].out)
4855 time2 = rld[i].opnum * 4 + 2;
4857 case RELOAD_FOR_INPUT_ADDRESS:
4858 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4859 && ignore_address_reloads
4860 && ! rld[reloadnum].out)
4862 time2 = rld[i].opnum * 4 + 3;
4864 case RELOAD_FOR_INPUT:
4865 time2 = rld[i].opnum * 4 + 4;
4866 check_earlyclobber = 1;
4868 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4869 == MAX_RECOG_OPERAND * 4 */
4870 case RELOAD_FOR_OPADDR_ADDR:
4871 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4872 && ignore_address_reloads
4873 && ! rld[reloadnum].out)
4875 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4877 case RELOAD_FOR_OPERAND_ADDRESS:
4878 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4879 check_earlyclobber = 1;
4881 case RELOAD_FOR_INSN:
4882 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4884 case RELOAD_FOR_OUTPUT:
4885 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4886 instruction is executed. */
4887 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4889 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4890 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4892 case RELOAD_FOR_OUTADDR_ADDRESS:
4893 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4894 && ignore_address_reloads
4895 && ! rld[reloadnum].out)
4897 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4899 case RELOAD_FOR_OUTPUT_ADDRESS:
4900 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4903 /* If there is no conflict in the input part, handle this
4904 like an output reload. */
4905 if (! rld[i].in || rtx_equal_p (other_input, value))
4907 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4908 /* Earlyclobbered outputs must conflict with inputs. */
4909 if (earlyclobber_operand_p (rld[i].out))
4910 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4915 /* RELOAD_OTHER might be live beyond instruction execution,
4916 but this is not obvious when we set time2 = 1. So check
4917 here if there might be a problem with the new reload
4918 clobbering the register used by the RELOAD_OTHER. */
4926 && (! rld[i].in || rld[i].out
4927 || ! rtx_equal_p (other_input, value)))
4928 || (out && rld[reloadnum].out_reg
4929 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4935 /* Earlyclobbered outputs must conflict with inputs. */
4936 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4942 /* Return 1 if the value in reload reg REGNO, as used by a reload
4943 needed for the part of the insn specified by OPNUM and TYPE,
4944 may be used to load VALUE into it.
4946 MODE is the mode in which the register is used, this is needed to
4947 determine how many hard regs to test.
4949 Other read-only reloads with the same value do not conflict
4950 unless OUT is nonzero and these other reloads have to live while
4951 output reloads live.
4952 If OUT is CONST0_RTX, this is a special case: it means that the
4953 test should not be for using register REGNO as reload register, but
4954 for copying from register REGNO into the reload register.
4956 RELOADNUM is the number of the reload we want to load this value for;
4957 a reload does not conflict with itself.
4959 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4960 reloads that load an address for the very reload we are considering.
4962 The caller has to make sure that there is no conflict with the return
4966 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4967 enum reload_type type, rtx value, rtx out, int reloadnum,
4968 int ignore_address_reloads)
4970 int nregs = hard_regno_nregs[regno][mode];
4972 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4973 value, out, reloadnum,
4974 ignore_address_reloads))
4979 /* Return nonzero if the rtx X is invariant over the current function. */
4980 /* ??? Actually, the places where we use this expect exactly what
4981 * is tested here, and not everything that is function invariant. In
4982 * particular, the frame pointer and arg pointer are special cased;
4983 * pic_offset_table_rtx is not, and this will cause aborts when we
4984 * go to spill these things to memory. */
4987 function_invariant_p (rtx x)
4991 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4993 if (GET_CODE (x) == PLUS
4994 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4995 && CONSTANT_P (XEXP (x, 1)))
5000 /* Determine whether the reload reg X overlaps any rtx'es used for
5001 overriding inheritance. Return nonzero if so. */
5004 conflicts_with_override (rtx x)
5007 for (i = 0; i < n_reloads; i++)
5008 if (reload_override_in[i]
5009 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5014 /* Give an error message saying we failed to find a reload for INSN,
5015 and clear out reload R. */
5017 failed_reload (rtx insn, int r)
5019 if (asm_noperands (PATTERN (insn)) < 0)
5020 /* It's the compiler's fault. */
5021 fatal_insn ("could not find a spill register", insn);
5023 /* It's the user's fault; the operand's mode and constraint
5024 don't match. Disable this reload so we don't crash in final. */
5025 error_for_asm (insn,
5026 "`asm' operand constraint incompatible with operand size");
5030 rld[r].optional = 1;
5031 rld[r].secondary_p = 1;
5034 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5035 for reload R. If it's valid, get an rtx for it. Return nonzero if
5038 set_reload_reg (int i, int r)
5041 rtx reg = spill_reg_rtx[i];
5043 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5044 spill_reg_rtx[i] = reg
5045 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5047 regno = true_regnum (reg);
5049 /* Detect when the reload reg can't hold the reload mode.
5050 This used to be one `if', but Sequent compiler can't handle that. */
5051 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5053 enum machine_mode test_mode = VOIDmode;
5055 test_mode = GET_MODE (rld[r].in);
5056 /* If rld[r].in has VOIDmode, it means we will load it
5057 in whatever mode the reload reg has: to wit, rld[r].mode.
5058 We have already tested that for validity. */
5059 /* Aside from that, we need to test that the expressions
5060 to reload from or into have modes which are valid for this
5061 reload register. Otherwise the reload insns would be invalid. */
5062 if (! (rld[r].in != 0 && test_mode != VOIDmode
5063 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5064 if (! (rld[r].out != 0
5065 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5067 /* The reg is OK. */
5070 /* Mark as in use for this insn the reload regs we use
5072 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5073 rld[r].when_needed, rld[r].mode);
5075 rld[r].reg_rtx = reg;
5076 reload_spill_index[r] = spill_regs[i];
5083 /* Find a spill register to use as a reload register for reload R.
5084 LAST_RELOAD is nonzero if this is the last reload for the insn being
5087 Set rld[R].reg_rtx to the register allocated.
5089 We return 1 if successful, or 0 if we couldn't find a spill reg and
5090 we didn't change anything. */
5093 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5098 /* If we put this reload ahead, thinking it is a group,
5099 then insist on finding a group. Otherwise we can grab a
5100 reg that some other reload needs.
5101 (That can happen when we have a 68000 DATA_OR_FP_REG
5102 which is a group of data regs or one fp reg.)
5103 We need not be so restrictive if there are no more reloads
5106 ??? Really it would be nicer to have smarter handling
5107 for that kind of reg class, where a problem like this is normal.
5108 Perhaps those classes should be avoided for reloading
5109 by use of more alternatives. */
5111 int force_group = rld[r].nregs > 1 && ! last_reload;
5113 /* If we want a single register and haven't yet found one,
5114 take any reg in the right class and not in use.
5115 If we want a consecutive group, here is where we look for it.
5117 We use two passes so we can first look for reload regs to
5118 reuse, which are already in use for other reloads in this insn,
5119 and only then use additional registers.
5120 I think that maximizing reuse is needed to make sure we don't
5121 run out of reload regs. Suppose we have three reloads, and
5122 reloads A and B can share regs. These need two regs.
5123 Suppose A and B are given different regs.
5124 That leaves none for C. */
5125 for (pass = 0; pass < 2; pass++)
5127 /* I is the index in spill_regs.
5128 We advance it round-robin between insns to use all spill regs
5129 equally, so that inherited reloads have a chance
5130 of leapfrogging each other. */
5134 for (count = 0; count < n_spills; count++)
5136 int class = (int) rld[r].class;
5142 regnum = spill_regs[i];
5144 if ((reload_reg_free_p (regnum, rld[r].opnum,
5147 /* We check reload_reg_used to make sure we
5148 don't clobber the return register. */
5149 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5150 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5151 rld[r].when_needed, rld[r].in,
5153 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5154 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5155 /* Look first for regs to share, then for unshared. But
5156 don't share regs used for inherited reloads; they are
5157 the ones we want to preserve. */
5159 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5161 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5164 int nr = hard_regno_nregs[regnum][rld[r].mode];
5165 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5166 (on 68000) got us two FP regs. If NR is 1,
5167 we would reject both of them. */
5170 /* If we need only one reg, we have already won. */
5173 /* But reject a single reg if we demand a group. */
5178 /* Otherwise check that as many consecutive regs as we need
5179 are available here. */
5182 int regno = regnum + nr - 1;
5183 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5184 && spill_reg_order[regno] >= 0
5185 && reload_reg_free_p (regno, rld[r].opnum,
5186 rld[r].when_needed)))
5195 /* If we found something on pass 1, omit pass 2. */
5196 if (count < n_spills)
5200 /* We should have found a spill register by now. */
5201 if (count >= n_spills)
5204 /* I is the index in SPILL_REG_RTX of the reload register we are to
5205 allocate. Get an rtx for it and find its register number. */
5207 return set_reload_reg (i, r);
5210 /* Initialize all the tables needed to allocate reload registers.
5211 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5212 is the array we use to restore the reg_rtx field for every reload. */
5215 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5219 for (i = 0; i < n_reloads; i++)
5220 rld[i].reg_rtx = save_reload_reg_rtx[i];
5222 memset (reload_inherited, 0, MAX_RELOADS);
5223 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5224 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5226 CLEAR_HARD_REG_SET (reload_reg_used);
5227 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5228 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5229 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5230 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5231 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5233 CLEAR_HARD_REG_SET (reg_used_in_insn);
5236 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5237 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5238 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5239 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5240 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5241 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5244 for (i = 0; i < reload_n_operands; i++)
5246 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5247 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5248 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5249 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5250 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5251 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5254 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5256 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5258 for (i = 0; i < n_reloads; i++)
5259 /* If we have already decided to use a certain register,
5260 don't use it in another way. */
5262 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5263 rld[i].when_needed, rld[i].mode);
5266 /* Assign hard reg targets for the pseudo-registers we must reload
5267 into hard regs for this insn.
5268 Also output the instructions to copy them in and out of the hard regs.
5270 For machines with register classes, we are responsible for
5271 finding a reload reg in the proper class. */
5274 choose_reload_regs (struct insn_chain *chain)
5276 rtx insn = chain->insn;
5278 unsigned int max_group_size = 1;
5279 enum reg_class group_class = NO_REGS;
5280 int pass, win, inheritance;
5282 rtx save_reload_reg_rtx[MAX_RELOADS];
5284 /* In order to be certain of getting the registers we need,
5285 we must sort the reloads into order of increasing register class.
5286 Then our grabbing of reload registers will parallel the process
5287 that provided the reload registers.
5289 Also note whether any of the reloads wants a consecutive group of regs.
5290 If so, record the maximum size of the group desired and what
5291 register class contains all the groups needed by this insn. */
5293 for (j = 0; j < n_reloads; j++)
5295 reload_order[j] = j;
5296 reload_spill_index[j] = -1;
5298 if (rld[j].nregs > 1)
5300 max_group_size = MAX (rld[j].nregs, max_group_size);
5302 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5305 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5309 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5311 /* If -O, try first with inheritance, then turning it off.
5312 If not -O, don't do inheritance.
5313 Using inheritance when not optimizing leads to paradoxes
5314 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5315 because one side of the comparison might be inherited. */
5317 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5319 choose_reload_regs_init (chain, save_reload_reg_rtx);
5321 /* Process the reloads in order of preference just found.
5322 Beyond this point, subregs can be found in reload_reg_rtx.
5324 This used to look for an existing reloaded home for all of the
5325 reloads, and only then perform any new reloads. But that could lose
5326 if the reloads were done out of reg-class order because a later
5327 reload with a looser constraint might have an old home in a register
5328 needed by an earlier reload with a tighter constraint.
5330 To solve this, we make two passes over the reloads, in the order
5331 described above. In the first pass we try to inherit a reload
5332 from a previous insn. If there is a later reload that needs a
5333 class that is a proper subset of the class being processed, we must
5334 also allocate a spill register during the first pass.
5336 Then make a second pass over the reloads to allocate any reloads
5337 that haven't been given registers yet. */
5339 for (j = 0; j < n_reloads; j++)
5341 int r = reload_order[j];
5342 rtx search_equiv = NULL_RTX;
5344 /* Ignore reloads that got marked inoperative. */
5345 if (rld[r].out == 0 && rld[r].in == 0
5346 && ! rld[r].secondary_p)
5349 /* If find_reloads chose to use reload_in or reload_out as a reload
5350 register, we don't need to chose one. Otherwise, try even if it
5351 found one since we might save an insn if we find the value lying
5353 Try also when reload_in is a pseudo without a hard reg. */
5354 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5355 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5356 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5357 && !MEM_P (rld[r].in)
5358 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5361 #if 0 /* No longer needed for correct operation.
5362 It might give better code, or might not; worth an experiment? */
5363 /* If this is an optional reload, we can't inherit from earlier insns
5364 until we are sure that any non-optional reloads have been allocated.
5365 The following code takes advantage of the fact that optional reloads
5366 are at the end of reload_order. */
5367 if (rld[r].optional != 0)
5368 for (i = 0; i < j; i++)
5369 if ((rld[reload_order[i]].out != 0
5370 || rld[reload_order[i]].in != 0
5371 || rld[reload_order[i]].secondary_p)
5372 && ! rld[reload_order[i]].optional
5373 && rld[reload_order[i]].reg_rtx == 0)
5374 allocate_reload_reg (chain, reload_order[i], 0);
5377 /* First see if this pseudo is already available as reloaded
5378 for a previous insn. We cannot try to inherit for reloads
5379 that are smaller than the maximum number of registers needed
5380 for groups unless the register we would allocate cannot be used
5383 We could check here to see if this is a secondary reload for
5384 an object that is already in a register of the desired class.
5385 This would avoid the need for the secondary reload register.
5386 But this is complex because we can't easily determine what
5387 objects might want to be loaded via this reload. So let a
5388 register be allocated here. In `emit_reload_insns' we suppress
5389 one of the loads in the case described above. */
5395 enum machine_mode mode = VOIDmode;
5399 else if (REG_P (rld[r].in))
5401 regno = REGNO (rld[r].in);
5402 mode = GET_MODE (rld[r].in);
5404 else if (REG_P (rld[r].in_reg))
5406 regno = REGNO (rld[r].in_reg);
5407 mode = GET_MODE (rld[r].in_reg);
5409 else if (GET_CODE (rld[r].in_reg) == SUBREG
5410 && REG_P (SUBREG_REG (rld[r].in_reg)))
5412 byte = SUBREG_BYTE (rld[r].in_reg);
5413 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5414 if (regno < FIRST_PSEUDO_REGISTER)
5415 regno = subreg_regno (rld[r].in_reg);
5416 mode = GET_MODE (rld[r].in_reg);
5419 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5420 || GET_CODE (rld[r].in_reg) == PRE_DEC
5421 || GET_CODE (rld[r].in_reg) == POST_INC
5422 || GET_CODE (rld[r].in_reg) == POST_DEC)
5423 && REG_P (XEXP (rld[r].in_reg, 0)))
5425 regno = REGNO (XEXP (rld[r].in_reg, 0));
5426 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5427 rld[r].out = rld[r].in;
5431 /* This won't work, since REGNO can be a pseudo reg number.
5432 Also, it takes much more hair to keep track of all the things
5433 that can invalidate an inherited reload of part of a pseudoreg. */
5434 else if (GET_CODE (rld[r].in) == SUBREG
5435 && REG_P (SUBREG_REG (rld[r].in)))
5436 regno = subreg_regno (rld[r].in);
5439 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5441 enum reg_class class = rld[r].class, last_class;
5442 rtx last_reg = reg_last_reload_reg[regno];
5443 enum machine_mode need_mode;
5445 i = REGNO (last_reg);
5446 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5447 last_class = REGNO_REG_CLASS (i);
5453 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5454 GET_MODE_CLASS (mode));
5457 #ifdef CANNOT_CHANGE_MODE_CLASS
5458 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5462 (GET_MODE_SIZE (GET_MODE (last_reg))
5463 >= GET_MODE_SIZE (need_mode))
5464 #ifdef CANNOT_CHANGE_MODE_CLASS
5467 && reg_reloaded_contents[i] == regno
5468 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5469 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5470 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5471 /* Even if we can't use this register as a reload
5472 register, we might use it for reload_override_in,
5473 if copying it to the desired class is cheap
5475 || ((REGISTER_MOVE_COST (mode, last_class, class)
5476 < MEMORY_MOVE_COST (mode, class, 1))
5477 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5478 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5482 #ifdef SECONDARY_MEMORY_NEEDED
5483 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5488 && (rld[r].nregs == max_group_size
5489 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5491 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5492 rld[r].when_needed, rld[r].in,
5495 /* If a group is needed, verify that all the subsequent
5496 registers still have their values intact. */
5497 int nr = hard_regno_nregs[i][rld[r].mode];
5500 for (k = 1; k < nr; k++)
5501 if (reg_reloaded_contents[i + k] != regno
5502 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5510 last_reg = (GET_MODE (last_reg) == mode
5511 ? last_reg : gen_rtx_REG (mode, i));
5514 for (k = 0; k < nr; k++)
5515 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5518 /* We found a register that contains the
5519 value we need. If this register is the
5520 same as an `earlyclobber' operand of the
5521 current insn, just mark it as a place to
5522 reload from since we can't use it as the
5523 reload register itself. */
5525 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5526 if (reg_overlap_mentioned_for_reload_p
5527 (reg_last_reload_reg[regno],
5528 reload_earlyclobbers[i1]))
5531 if (i1 != n_earlyclobbers
5532 || ! (free_for_value_p (i, rld[r].mode,
5534 rld[r].when_needed, rld[r].in,
5536 /* Don't use it if we'd clobber a pseudo reg. */
5537 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5539 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5540 /* Don't clobber the frame pointer. */
5541 || (i == HARD_FRAME_POINTER_REGNUM
5542 && frame_pointer_needed
5544 /* Don't really use the inherited spill reg
5545 if we need it wider than we've got it. */
5546 || (GET_MODE_SIZE (rld[r].mode)
5547 > GET_MODE_SIZE (mode))
5550 /* If find_reloads chose reload_out as reload
5551 register, stay with it - that leaves the
5552 inherited register for subsequent reloads. */
5553 || (rld[r].out && rld[r].reg_rtx
5554 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5556 if (! rld[r].optional)
5558 reload_override_in[r] = last_reg;
5559 reload_inheritance_insn[r]
5560 = reg_reloaded_insn[i];
5566 /* We can use this as a reload reg. */
5567 /* Mark the register as in use for this part of
5569 mark_reload_reg_in_use (i,
5573 rld[r].reg_rtx = last_reg;
5574 reload_inherited[r] = 1;
5575 reload_inheritance_insn[r]
5576 = reg_reloaded_insn[i];
5577 reload_spill_index[r] = i;
5578 for (k = 0; k < nr; k++)
5579 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5587 /* Here's another way to see if the value is already lying around. */
5590 && ! reload_inherited[r]
5592 && (CONSTANT_P (rld[r].in)
5593 || GET_CODE (rld[r].in) == PLUS
5594 || REG_P (rld[r].in)
5595 || MEM_P (rld[r].in))
5596 && (rld[r].nregs == max_group_size
5597 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5598 search_equiv = rld[r].in;
5599 /* If this is an output reload from a simple move insn, look
5600 if an equivalence for the input is available. */
5601 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5603 rtx set = single_set (insn);
5606 && rtx_equal_p (rld[r].out, SET_DEST (set))
5607 && CONSTANT_P (SET_SRC (set)))
5608 search_equiv = SET_SRC (set);
5614 = find_equiv_reg (search_equiv, insn, rld[r].class,
5615 -1, NULL, 0, rld[r].mode);
5621 regno = REGNO (equiv);
5622 else if (GET_CODE (equiv) == SUBREG)
5624 /* This must be a SUBREG of a hard register.
5625 Make a new REG since this might be used in an
5626 address and not all machines support SUBREGs
5628 regno = subreg_regno (equiv);
5629 equiv = gen_rtx_REG (rld[r].mode, regno);
5635 /* If we found a spill reg, reject it unless it is free
5636 and of the desired class. */
5640 int bad_for_class = 0;
5641 int max_regno = regno + rld[r].nregs;
5643 for (i = regno; i < max_regno; i++)
5645 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5647 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5652 && ! free_for_value_p (regno, rld[r].mode,
5653 rld[r].opnum, rld[r].when_needed,
5654 rld[r].in, rld[r].out, r, 1))
5659 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5662 /* We found a register that contains the value we need.
5663 If this register is the same as an `earlyclobber' operand
5664 of the current insn, just mark it as a place to reload from
5665 since we can't use it as the reload register itself. */
5668 for (i = 0; i < n_earlyclobbers; i++)
5669 if (reg_overlap_mentioned_for_reload_p (equiv,
5670 reload_earlyclobbers[i]))
5672 if (! rld[r].optional)
5673 reload_override_in[r] = equiv;
5678 /* If the equiv register we have found is explicitly clobbered
5679 in the current insn, it depends on the reload type if we
5680 can use it, use it for reload_override_in, or not at all.
5681 In particular, we then can't use EQUIV for a
5682 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5686 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5687 switch (rld[r].when_needed)
5689 case RELOAD_FOR_OTHER_ADDRESS:
5690 case RELOAD_FOR_INPADDR_ADDRESS:
5691 case RELOAD_FOR_INPUT_ADDRESS:
5692 case RELOAD_FOR_OPADDR_ADDR:
5695 case RELOAD_FOR_INPUT:
5696 case RELOAD_FOR_OPERAND_ADDRESS:
5697 if (! rld[r].optional)
5698 reload_override_in[r] = equiv;
5704 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5705 switch (rld[r].when_needed)
5707 case RELOAD_FOR_OTHER_ADDRESS:
5708 case RELOAD_FOR_INPADDR_ADDRESS:
5709 case RELOAD_FOR_INPUT_ADDRESS:
5710 case RELOAD_FOR_OPADDR_ADDR:
5711 case RELOAD_FOR_OPERAND_ADDRESS:
5712 case RELOAD_FOR_INPUT:
5715 if (! rld[r].optional)
5716 reload_override_in[r] = equiv;
5724 /* If we found an equivalent reg, say no code need be generated
5725 to load it, and use it as our reload reg. */
5727 && (regno != HARD_FRAME_POINTER_REGNUM
5728 || !frame_pointer_needed))
5730 int nr = hard_regno_nregs[regno][rld[r].mode];
5732 rld[r].reg_rtx = equiv;
5733 reload_inherited[r] = 1;
5735 /* If reg_reloaded_valid is not set for this register,
5736 there might be a stale spill_reg_store lying around.
5737 We must clear it, since otherwise emit_reload_insns
5738 might delete the store. */
5739 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5740 spill_reg_store[regno] = NULL_RTX;
5741 /* If any of the hard registers in EQUIV are spill
5742 registers, mark them as in use for this insn. */
5743 for (k = 0; k < nr; k++)
5745 i = spill_reg_order[regno + k];
5748 mark_reload_reg_in_use (regno, rld[r].opnum,
5751 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5758 /* If we found a register to use already, or if this is an optional
5759 reload, we are done. */
5760 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5764 /* No longer needed for correct operation. Might or might
5765 not give better code on the average. Want to experiment? */
5767 /* See if there is a later reload that has a class different from our
5768 class that intersects our class or that requires less register
5769 than our reload. If so, we must allocate a register to this
5770 reload now, since that reload might inherit a previous reload
5771 and take the only available register in our class. Don't do this
5772 for optional reloads since they will force all previous reloads
5773 to be allocated. Also don't do this for reloads that have been
5776 for (i = j + 1; i < n_reloads; i++)
5778 int s = reload_order[i];
5780 if ((rld[s].in == 0 && rld[s].out == 0
5781 && ! rld[s].secondary_p)
5785 if ((rld[s].class != rld[r].class
5786 && reg_classes_intersect_p (rld[r].class,
5788 || rld[s].nregs < rld[r].nregs)
5795 allocate_reload_reg (chain, r, j == n_reloads - 1);
5799 /* Now allocate reload registers for anything non-optional that
5800 didn't get one yet. */
5801 for (j = 0; j < n_reloads; j++)
5803 int r = reload_order[j];
5805 /* Ignore reloads that got marked inoperative. */
5806 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5809 /* Skip reloads that already have a register allocated or are
5811 if (rld[r].reg_rtx != 0 || rld[r].optional)
5814 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5818 /* If that loop got all the way, we have won. */
5825 /* Loop around and try without any inheritance. */
5830 /* First undo everything done by the failed attempt
5831 to allocate with inheritance. */
5832 choose_reload_regs_init (chain, save_reload_reg_rtx);
5834 /* Some sanity tests to verify that the reloads found in the first
5835 pass are identical to the ones we have now. */
5836 if (chain->n_reloads != n_reloads)
5839 for (i = 0; i < n_reloads; i++)
5841 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5843 if (chain->rld[i].when_needed != rld[i].when_needed)
5845 for (j = 0; j < n_spills; j++)
5846 if (spill_regs[j] == chain->rld[i].regno)
5847 if (! set_reload_reg (j, i))
5848 failed_reload (chain->insn, i);
5852 /* If we thought we could inherit a reload, because it seemed that
5853 nothing else wanted the same reload register earlier in the insn,
5854 verify that assumption, now that all reloads have been assigned.
5855 Likewise for reloads where reload_override_in has been set. */
5857 /* If doing expensive optimizations, do one preliminary pass that doesn't
5858 cancel any inheritance, but removes reloads that have been needed only
5859 for reloads that we know can be inherited. */
5860 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5862 for (j = 0; j < n_reloads; j++)
5864 int r = reload_order[j];
5866 if (reload_inherited[r] && rld[r].reg_rtx)
5867 check_reg = rld[r].reg_rtx;
5868 else if (reload_override_in[r]
5869 && (REG_P (reload_override_in[r])
5870 || GET_CODE (reload_override_in[r]) == SUBREG))
5871 check_reg = reload_override_in[r];
5874 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5875 rld[r].opnum, rld[r].when_needed, rld[r].in,
5876 (reload_inherited[r]
5877 ? rld[r].out : const0_rtx),
5882 reload_inherited[r] = 0;
5883 reload_override_in[r] = 0;
5885 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5886 reload_override_in, then we do not need its related
5887 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5888 likewise for other reload types.
5889 We handle this by removing a reload when its only replacement
5890 is mentioned in reload_in of the reload we are going to inherit.
5891 A special case are auto_inc expressions; even if the input is
5892 inherited, we still need the address for the output. We can
5893 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5894 If we succeeded removing some reload and we are doing a preliminary
5895 pass just to remove such reloads, make another pass, since the
5896 removal of one reload might allow us to inherit another one. */
5898 && rld[r].out != rld[r].in
5899 && remove_address_replacements (rld[r].in) && pass)
5904 /* Now that reload_override_in is known valid,
5905 actually override reload_in. */
5906 for (j = 0; j < n_reloads; j++)
5907 if (reload_override_in[j])
5908 rld[j].in = reload_override_in[j];
5910 /* If this reload won't be done because it has been canceled or is
5911 optional and not inherited, clear reload_reg_rtx so other
5912 routines (such as subst_reloads) don't get confused. */
5913 for (j = 0; j < n_reloads; j++)
5914 if (rld[j].reg_rtx != 0
5915 && ((rld[j].optional && ! reload_inherited[j])
5916 || (rld[j].in == 0 && rld[j].out == 0
5917 && ! rld[j].secondary_p)))
5919 int regno = true_regnum (rld[j].reg_rtx);
5921 if (spill_reg_order[regno] >= 0)
5922 clear_reload_reg_in_use (regno, rld[j].opnum,
5923 rld[j].when_needed, rld[j].mode);
5925 reload_spill_index[j] = -1;
5928 /* Record which pseudos and which spill regs have output reloads. */
5929 for (j = 0; j < n_reloads; j++)
5931 int r = reload_order[j];
5933 i = reload_spill_index[r];
5935 /* I is nonneg if this reload uses a register.
5936 If rld[r].reg_rtx is 0, this is an optional reload
5937 that we opted to ignore. */
5938 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5939 && rld[r].reg_rtx != 0)
5941 int nregno = REGNO (rld[r].out_reg);
5944 if (nregno < FIRST_PSEUDO_REGISTER)
5945 nr = hard_regno_nregs[nregno][rld[r].mode];
5948 reg_has_output_reload[nregno + nr] = 1;
5952 nr = hard_regno_nregs[i][rld[r].mode];
5954 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5957 if (rld[r].when_needed != RELOAD_OTHER
5958 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5959 && rld[r].when_needed != RELOAD_FOR_INSN)
5965 /* Deallocate the reload register for reload R. This is called from
5966 remove_address_replacements. */
5969 deallocate_reload_reg (int r)
5973 if (! rld[r].reg_rtx)
5975 regno = true_regnum (rld[r].reg_rtx);
5977 if (spill_reg_order[regno] >= 0)
5978 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5980 reload_spill_index[r] = -1;
5983 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5984 reloads of the same item for fear that we might not have enough reload
5985 registers. However, normally they will get the same reload register
5986 and hence actually need not be loaded twice.
5988 Here we check for the most common case of this phenomenon: when we have
5989 a number of reloads for the same object, each of which were allocated
5990 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5991 reload, and is not modified in the insn itself. If we find such,
5992 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5993 This will not increase the number of spill registers needed and will
5994 prevent redundant code. */
5997 merge_assigned_reloads (rtx insn)
6001 /* Scan all the reloads looking for ones that only load values and
6002 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6003 assigned and not modified by INSN. */
6005 for (i = 0; i < n_reloads; i++)
6007 int conflicting_input = 0;
6008 int max_input_address_opnum = -1;
6009 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6011 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6012 || rld[i].out != 0 || rld[i].reg_rtx == 0
6013 || reg_set_p (rld[i].reg_rtx, insn))
6016 /* Look at all other reloads. Ensure that the only use of this
6017 reload_reg_rtx is in a reload that just loads the same value
6018 as we do. Note that any secondary reloads must be of the identical
6019 class since the values, modes, and result registers are the
6020 same, so we need not do anything with any secondary reloads. */
6022 for (j = 0; j < n_reloads; j++)
6024 if (i == j || rld[j].reg_rtx == 0
6025 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6029 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6030 && rld[j].opnum > max_input_address_opnum)
6031 max_input_address_opnum = rld[j].opnum;
6033 /* If the reload regs aren't exactly the same (e.g, different modes)
6034 or if the values are different, we can't merge this reload.
6035 But if it is an input reload, we might still merge
6036 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6038 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6039 || rld[j].out != 0 || rld[j].in == 0
6040 || ! rtx_equal_p (rld[i].in, rld[j].in))
6042 if (rld[j].when_needed != RELOAD_FOR_INPUT
6043 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6044 || rld[i].opnum > rld[j].opnum)
6045 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6047 conflicting_input = 1;
6048 if (min_conflicting_input_opnum > rld[j].opnum)
6049 min_conflicting_input_opnum = rld[j].opnum;
6053 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6054 we, in fact, found any matching reloads. */
6057 && max_input_address_opnum <= min_conflicting_input_opnum)
6059 for (j = 0; j < n_reloads; j++)
6060 if (i != j && rld[j].reg_rtx != 0
6061 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6062 && (! conflicting_input
6063 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6064 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6066 rld[i].when_needed = RELOAD_OTHER;
6068 reload_spill_index[j] = -1;
6069 transfer_replacements (i, j);
6072 /* If this is now RELOAD_OTHER, look for any reloads that load
6073 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6074 if they were for inputs, RELOAD_OTHER for outputs. Note that
6075 this test is equivalent to looking for reloads for this operand
6077 /* We must take special care when there are two or more reloads to
6078 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6079 same value or a part of it; we must not change its type if there
6080 is a conflicting input. */
6082 if (rld[i].when_needed == RELOAD_OTHER)
6083 for (j = 0; j < n_reloads; j++)
6085 && rld[j].when_needed != RELOAD_OTHER
6086 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6087 && (! conflicting_input
6088 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6089 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6090 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6096 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6097 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6098 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6100 /* Check to see if we accidentally converted two reloads
6101 that use the same reload register with different inputs
6102 to the same type. If so, the resulting code won't work,
6105 for (k = 0; k < j; k++)
6106 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6107 && rld[k].when_needed == rld[j].when_needed
6108 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6109 && ! rtx_equal_p (rld[k].in, rld[j].in))
6116 /* These arrays are filled by emit_reload_insns and its subroutines. */
6117 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6118 static rtx other_input_address_reload_insns = 0;
6119 static rtx other_input_reload_insns = 0;
6120 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6121 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6122 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6123 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6124 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6125 static rtx operand_reload_insns = 0;
6126 static rtx other_operand_reload_insns = 0;
6127 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6129 /* Values to be put in spill_reg_store are put here first. */
6130 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6131 static HARD_REG_SET reg_reloaded_died;
6133 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6134 has the number J. OLD contains the value to be used as input. */
6137 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6140 rtx insn = chain->insn;
6141 rtx reloadreg = rl->reg_rtx;
6142 rtx oldequiv_reg = 0;
6145 enum machine_mode mode;
6148 /* Determine the mode to reload in.
6149 This is very tricky because we have three to choose from.
6150 There is the mode the insn operand wants (rl->inmode).
6151 There is the mode of the reload register RELOADREG.
6152 There is the intrinsic mode of the operand, which we could find
6153 by stripping some SUBREGs.
6154 It turns out that RELOADREG's mode is irrelevant:
6155 we can change that arbitrarily.
6157 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6158 then the reload reg may not support QImode moves, so use SImode.
6159 If foo is in memory due to spilling a pseudo reg, this is safe,
6160 because the QImode value is in the least significant part of a
6161 slot big enough for a SImode. If foo is some other sort of
6162 memory reference, then it is impossible to reload this case,
6163 so previous passes had better make sure this never happens.
6165 Then consider a one-word union which has SImode and one of its
6166 members is a float, being fetched as (SUBREG:SF union:SI).
6167 We must fetch that as SFmode because we could be loading into
6168 a float-only register. In this case OLD's mode is correct.
6170 Consider an immediate integer: it has VOIDmode. Here we need
6171 to get a mode from something else.
6173 In some cases, there is a fourth mode, the operand's
6174 containing mode. If the insn specifies a containing mode for
6175 this operand, it overrides all others.
6177 I am not sure whether the algorithm here is always right,
6178 but it does the right things in those cases. */
6180 mode = GET_MODE (old);
6181 if (mode == VOIDmode)
6184 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6185 /* If we need a secondary register for this operation, see if
6186 the value is already in a register in that class. Don't
6187 do this if the secondary register will be used as a scratch
6190 if (rl->secondary_in_reload >= 0
6191 && rl->secondary_in_icode == CODE_FOR_nothing
6194 = find_equiv_reg (old, insn,
6195 rld[rl->secondary_in_reload].class,
6199 /* If reloading from memory, see if there is a register
6200 that already holds the same value. If so, reload from there.
6201 We can pass 0 as the reload_reg_p argument because
6202 any other reload has either already been emitted,
6203 in which case find_equiv_reg will see the reload-insn,
6204 or has yet to be emitted, in which case it doesn't matter
6205 because we will use this equiv reg right away. */
6207 if (oldequiv == 0 && optimize
6210 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6211 && reg_renumber[REGNO (old)] < 0)))
6212 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6216 unsigned int regno = true_regnum (oldequiv);
6218 /* Don't use OLDEQUIV if any other reload changes it at an
6219 earlier stage of this insn or at this stage. */
6220 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6221 rl->in, const0_rtx, j, 0))
6224 /* If it is no cheaper to copy from OLDEQUIV into the
6225 reload register than it would be to move from memory,
6226 don't use it. Likewise, if we need a secondary register
6230 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6231 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6233 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6234 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6235 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6239 #ifdef SECONDARY_MEMORY_NEEDED
6240 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6248 /* delete_output_reload is only invoked properly if old contains
6249 the original pseudo register. Since this is replaced with a
6250 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6251 find the pseudo in RELOAD_IN_REG. */
6253 && reload_override_in[j]
6254 && REG_P (rl->in_reg))
6261 else if (REG_P (oldequiv))
6262 oldequiv_reg = oldequiv;
6263 else if (GET_CODE (oldequiv) == SUBREG)
6264 oldequiv_reg = SUBREG_REG (oldequiv);
6266 /* If we are reloading from a register that was recently stored in
6267 with an output-reload, see if we can prove there was
6268 actually no need to store the old value in it. */
6270 if (optimize && REG_P (oldequiv)
6271 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6272 && spill_reg_store[REGNO (oldequiv)]
6274 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6275 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6277 delete_output_reload (insn, j, REGNO (oldequiv));
6279 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6280 then load RELOADREG from OLDEQUIV. Note that we cannot use
6281 gen_lowpart_common since it can do the wrong thing when
6282 RELOADREG has a multi-word mode. Note that RELOADREG
6283 must always be a REG here. */
6285 if (GET_MODE (reloadreg) != mode)
6286 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6287 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6288 oldequiv = SUBREG_REG (oldequiv);
6289 if (GET_MODE (oldequiv) != VOIDmode
6290 && mode != GET_MODE (oldequiv))
6291 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6293 /* Switch to the right place to emit the reload insns. */
6294 switch (rl->when_needed)
6297 where = &other_input_reload_insns;
6299 case RELOAD_FOR_INPUT:
6300 where = &input_reload_insns[rl->opnum];
6302 case RELOAD_FOR_INPUT_ADDRESS:
6303 where = &input_address_reload_insns[rl->opnum];
6305 case RELOAD_FOR_INPADDR_ADDRESS:
6306 where = &inpaddr_address_reload_insns[rl->opnum];
6308 case RELOAD_FOR_OUTPUT_ADDRESS:
6309 where = &output_address_reload_insns[rl->opnum];
6311 case RELOAD_FOR_OUTADDR_ADDRESS:
6312 where = &outaddr_address_reload_insns[rl->opnum];
6314 case RELOAD_FOR_OPERAND_ADDRESS:
6315 where = &operand_reload_insns;
6317 case RELOAD_FOR_OPADDR_ADDR:
6318 where = &other_operand_reload_insns;
6320 case RELOAD_FOR_OTHER_ADDRESS:
6321 where = &other_input_address_reload_insns;
6327 push_to_sequence (*where);
6329 /* Auto-increment addresses must be reloaded in a special way. */
6330 if (rl->out && ! rl->out_reg)
6332 /* We are not going to bother supporting the case where a
6333 incremented register can't be copied directly from
6334 OLDEQUIV since this seems highly unlikely. */
6335 if (rl->secondary_in_reload >= 0)
6338 if (reload_inherited[j])
6339 oldequiv = reloadreg;
6341 old = XEXP (rl->in_reg, 0);
6343 if (optimize && REG_P (oldequiv)
6344 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6345 && spill_reg_store[REGNO (oldequiv)]
6347 && (dead_or_set_p (insn,
6348 spill_reg_stored_to[REGNO (oldequiv)])
6349 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6351 delete_output_reload (insn, j, REGNO (oldequiv));
6353 /* Prevent normal processing of this reload. */
6355 /* Output a special code sequence for this case. */
6356 new_spill_reg_store[REGNO (reloadreg)]
6357 = inc_for_reload (reloadreg, oldequiv, rl->out,
6361 /* If we are reloading a pseudo-register that was set by the previous
6362 insn, see if we can get rid of that pseudo-register entirely
6363 by redirecting the previous insn into our reload register. */
6365 else if (optimize && REG_P (old)
6366 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6367 && dead_or_set_p (insn, old)
6368 /* This is unsafe if some other reload
6369 uses the same reg first. */
6370 && ! conflicts_with_override (reloadreg)
6371 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6372 rl->when_needed, old, rl->out, j, 0))
6374 rtx temp = PREV_INSN (insn);
6375 while (temp && GET_CODE (temp) == NOTE)
6376 temp = PREV_INSN (temp);
6378 && GET_CODE (temp) == INSN
6379 && GET_CODE (PATTERN (temp)) == SET
6380 && SET_DEST (PATTERN (temp)) == old
6381 /* Make sure we can access insn_operand_constraint. */
6382 && asm_noperands (PATTERN (temp)) < 0
6383 /* This is unsafe if operand occurs more than once in current
6384 insn. Perhaps some occurrences aren't reloaded. */
6385 && count_occurrences (PATTERN (insn), old, 0) == 1)
6387 rtx old = SET_DEST (PATTERN (temp));
6388 /* Store into the reload register instead of the pseudo. */
6389 SET_DEST (PATTERN (temp)) = reloadreg;
6391 /* Verify that resulting insn is valid. */
6392 extract_insn (temp);
6393 if (constrain_operands (1))
6395 /* If the previous insn is an output reload, the source is
6396 a reload register, and its spill_reg_store entry will
6397 contain the previous destination. This is now
6399 if (REG_P (SET_SRC (PATTERN (temp)))
6400 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6402 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6403 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6406 /* If these are the only uses of the pseudo reg,
6407 pretend for GDB it lives in the reload reg we used. */
6408 if (REG_N_DEATHS (REGNO (old)) == 1
6409 && REG_N_SETS (REGNO (old)) == 1)
6411 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6412 alter_reg (REGNO (old), -1);
6418 SET_DEST (PATTERN (temp)) = old;
6423 /* We can't do that, so output an insn to load RELOADREG. */
6425 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6426 /* If we have a secondary reload, pick up the secondary register
6427 and icode, if any. If OLDEQUIV and OLD are different or
6428 if this is an in-out reload, recompute whether or not we
6429 still need a secondary register and what the icode should
6430 be. If we still need a secondary register and the class or
6431 icode is different, go back to reloading from OLD if using
6432 OLDEQUIV means that we got the wrong type of register. We
6433 cannot have different class or icode due to an in-out reload
6434 because we don't make such reloads when both the input and
6435 output need secondary reload registers. */
6437 if (! special && rl->secondary_in_reload >= 0)
6439 rtx second_reload_reg = 0;
6440 int secondary_reload = rl->secondary_in_reload;
6441 rtx real_oldequiv = oldequiv;
6444 enum insn_code icode;
6446 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6447 and similarly for OLD.
6448 See comments in get_secondary_reload in reload.c. */
6449 /* If it is a pseudo that cannot be replaced with its
6450 equivalent MEM, we must fall back to reload_in, which
6451 will have all the necessary substitutions registered.
6452 Likewise for a pseudo that can't be replaced with its
6453 equivalent constant.
6455 Take extra care for subregs of such pseudos. Note that
6456 we cannot use reg_equiv_mem in this case because it is
6457 not in the right mode. */
6460 if (GET_CODE (tmp) == SUBREG)
6461 tmp = SUBREG_REG (tmp);
6463 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6464 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6465 || reg_equiv_constant[REGNO (tmp)] != 0))
6467 if (! reg_equiv_mem[REGNO (tmp)]
6468 || num_not_at_initial_offset
6469 || GET_CODE (oldequiv) == SUBREG)
6470 real_oldequiv = rl->in;
6472 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6476 if (GET_CODE (tmp) == SUBREG)
6477 tmp = SUBREG_REG (tmp);
6479 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6480 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6481 || reg_equiv_constant[REGNO (tmp)] != 0))
6483 if (! reg_equiv_mem[REGNO (tmp)]
6484 || num_not_at_initial_offset
6485 || GET_CODE (old) == SUBREG)
6488 real_old = reg_equiv_mem[REGNO (tmp)];
6491 second_reload_reg = rld[secondary_reload].reg_rtx;
6492 icode = rl->secondary_in_icode;
6494 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6495 || (rl->in != 0 && rl->out != 0))
6497 enum reg_class new_class
6498 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6499 mode, real_oldequiv);
6501 if (new_class == NO_REGS)
6502 second_reload_reg = 0;
6505 enum insn_code new_icode;
6506 enum machine_mode new_mode;
6508 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6509 REGNO (second_reload_reg)))
6510 oldequiv = old, real_oldequiv = real_old;
6513 new_icode = reload_in_optab[(int) mode];
6514 if (new_icode != CODE_FOR_nothing
6515 && ((insn_data[(int) new_icode].operand[0].predicate
6516 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6518 || (insn_data[(int) new_icode].operand[1].predicate
6519 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6520 (real_oldequiv, mode)))))
6521 new_icode = CODE_FOR_nothing;
6523 if (new_icode == CODE_FOR_nothing)
6526 new_mode = insn_data[(int) new_icode].operand[2].mode;
6528 if (GET_MODE (second_reload_reg) != new_mode)
6530 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6532 oldequiv = old, real_oldequiv = real_old;
6535 = reload_adjust_reg_for_mode (second_reload_reg,
6542 /* If we still need a secondary reload register, check
6543 to see if it is being used as a scratch or intermediate
6544 register and generate code appropriately. If we need
6545 a scratch register, use REAL_OLDEQUIV since the form of
6546 the insn may depend on the actual address if it is
6549 if (second_reload_reg)
6551 if (icode != CODE_FOR_nothing)
6553 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6554 second_reload_reg));
6559 /* See if we need a scratch register to load the
6560 intermediate register (a tertiary reload). */
6561 enum insn_code tertiary_icode
6562 = rld[secondary_reload].secondary_in_icode;
6564 if (tertiary_icode != CODE_FOR_nothing)
6566 rtx third_reload_reg
6567 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6569 emit_insn ((GEN_FCN (tertiary_icode)
6570 (second_reload_reg, real_oldequiv,
6571 third_reload_reg)));
6574 gen_reload (second_reload_reg, real_oldequiv,
6578 oldequiv = second_reload_reg;
6584 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6586 rtx real_oldequiv = oldequiv;
6588 if ((REG_P (oldequiv)
6589 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6590 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6591 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6592 || (GET_CODE (oldequiv) == SUBREG
6593 && REG_P (SUBREG_REG (oldequiv))
6594 && (REGNO (SUBREG_REG (oldequiv))
6595 >= FIRST_PSEUDO_REGISTER)
6596 && ((reg_equiv_memory_loc
6597 [REGNO (SUBREG_REG (oldequiv))] != 0)
6598 || (reg_equiv_constant
6599 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6600 || (CONSTANT_P (oldequiv)
6601 && (PREFERRED_RELOAD_CLASS (oldequiv,
6602 REGNO_REG_CLASS (REGNO (reloadreg)))
6604 real_oldequiv = rl->in;
6605 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6609 if (flag_non_call_exceptions)
6610 copy_eh_notes (insn, get_insns ());
6612 /* End this sequence. */
6613 *where = get_insns ();
6616 /* Update reload_override_in so that delete_address_reloads_1
6617 can see the actual register usage. */
6619 reload_override_in[j] = oldequiv;
6622 /* Generate insns to for the output reload RL, which is for the insn described
6623 by CHAIN and has the number J. */
6625 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6628 rtx reloadreg = rl->reg_rtx;
6629 rtx insn = chain->insn;
6632 enum machine_mode mode = GET_MODE (old);
6635 if (rl->when_needed == RELOAD_OTHER)
6638 push_to_sequence (output_reload_insns[rl->opnum]);
6640 /* Determine the mode to reload in.
6641 See comments above (for input reloading). */
6643 if (mode == VOIDmode)
6645 /* VOIDmode should never happen for an output. */
6646 if (asm_noperands (PATTERN (insn)) < 0)
6647 /* It's the compiler's fault. */
6648 fatal_insn ("VOIDmode on an output", insn);
6649 error_for_asm (insn, "output operand is constant in `asm'");
6650 /* Prevent crash--use something we know is valid. */
6652 old = gen_rtx_REG (mode, REGNO (reloadreg));
6655 if (GET_MODE (reloadreg) != mode)
6656 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6658 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6660 /* If we need two reload regs, set RELOADREG to the intermediate
6661 one, since it will be stored into OLD. We might need a secondary
6662 register only for an input reload, so check again here. */
6664 if (rl->secondary_out_reload >= 0)
6668 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6669 && reg_equiv_mem[REGNO (old)] != 0)
6670 real_old = reg_equiv_mem[REGNO (old)];
6672 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6676 rtx second_reloadreg = reloadreg;
6677 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6679 /* See if RELOADREG is to be used as a scratch register
6680 or as an intermediate register. */
6681 if (rl->secondary_out_icode != CODE_FOR_nothing)
6683 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6684 (real_old, second_reloadreg, reloadreg)));
6689 /* See if we need both a scratch and intermediate reload
6692 int secondary_reload = rl->secondary_out_reload;
6693 enum insn_code tertiary_icode
6694 = rld[secondary_reload].secondary_out_icode;
6696 if (GET_MODE (reloadreg) != mode)
6697 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6699 if (tertiary_icode != CODE_FOR_nothing)
6702 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6705 /* Copy primary reload reg to secondary reload reg.
6706 (Note that these have been swapped above, then
6707 secondary reload reg to OLD using our insn.) */
6709 /* If REAL_OLD is a paradoxical SUBREG, remove it
6710 and try to put the opposite SUBREG on
6712 if (GET_CODE (real_old) == SUBREG
6713 && (GET_MODE_SIZE (GET_MODE (real_old))
6714 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6715 && 0 != (tem = gen_lowpart_common
6716 (GET_MODE (SUBREG_REG (real_old)),
6718 real_old = SUBREG_REG (real_old), reloadreg = tem;
6720 gen_reload (reloadreg, second_reloadreg,
6721 rl->opnum, rl->when_needed);
6722 emit_insn ((GEN_FCN (tertiary_icode)
6723 (real_old, reloadreg, third_reloadreg)));
6728 /* Copy between the reload regs here and then to
6731 gen_reload (reloadreg, second_reloadreg,
6732 rl->opnum, rl->when_needed);
6738 /* Output the last reload insn. */
6743 /* Don't output the last reload if OLD is not the dest of
6744 INSN and is in the src and is clobbered by INSN. */
6745 if (! flag_expensive_optimizations
6747 || !(set = single_set (insn))
6748 || rtx_equal_p (old, SET_DEST (set))
6749 || !reg_mentioned_p (old, SET_SRC (set))
6750 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6751 gen_reload (old, reloadreg, rl->opnum,
6755 /* Look at all insns we emitted, just to be safe. */
6756 for (p = get_insns (); p; p = NEXT_INSN (p))
6759 rtx pat = PATTERN (p);
6761 /* If this output reload doesn't come from a spill reg,
6762 clear any memory of reloaded copies of the pseudo reg.
6763 If this output reload comes from a spill reg,
6764 reg_has_output_reload will make this do nothing. */
6765 note_stores (pat, forget_old_reloads_1, NULL);
6767 if (reg_mentioned_p (rl->reg_rtx, pat))
6769 rtx set = single_set (insn);
6770 if (reload_spill_index[j] < 0
6772 && SET_SRC (set) == rl->reg_rtx)
6774 int src = REGNO (SET_SRC (set));
6776 reload_spill_index[j] = src;
6777 SET_HARD_REG_BIT (reg_is_output_reload, src);
6778 if (find_regno_note (insn, REG_DEAD, src))
6779 SET_HARD_REG_BIT (reg_reloaded_died, src);
6781 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6783 int s = rl->secondary_out_reload;
6784 set = single_set (p);
6785 /* If this reload copies only to the secondary reload
6786 register, the secondary reload does the actual
6788 if (s >= 0 && set == NULL_RTX)
6789 /* We can't tell what function the secondary reload
6790 has and where the actual store to the pseudo is
6791 made; leave new_spill_reg_store alone. */
6794 && SET_SRC (set) == rl->reg_rtx
6795 && SET_DEST (set) == rld[s].reg_rtx)
6797 /* Usually the next instruction will be the
6798 secondary reload insn; if we can confirm
6799 that it is, setting new_spill_reg_store to
6800 that insn will allow an extra optimization. */
6801 rtx s_reg = rld[s].reg_rtx;
6802 rtx next = NEXT_INSN (p);
6803 rld[s].out = rl->out;
6804 rld[s].out_reg = rl->out_reg;
6805 set = single_set (next);
6806 if (set && SET_SRC (set) == s_reg
6807 && ! new_spill_reg_store[REGNO (s_reg)])
6809 SET_HARD_REG_BIT (reg_is_output_reload,
6811 new_spill_reg_store[REGNO (s_reg)] = next;
6815 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6820 if (rl->when_needed == RELOAD_OTHER)
6822 emit_insn (other_output_reload_insns[rl->opnum]);
6823 other_output_reload_insns[rl->opnum] = get_insns ();
6826 output_reload_insns[rl->opnum] = get_insns ();
6828 if (flag_non_call_exceptions)
6829 copy_eh_notes (insn, get_insns ());
6834 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6835 and has the number J. */
6837 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6839 rtx insn = chain->insn;
6840 rtx old = (rl->in && MEM_P (rl->in)
6841 ? rl->in_reg : rl->in);
6844 /* AUTO_INC reloads need to be handled even if inherited. We got an
6845 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6846 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6847 && ! rtx_equal_p (rl->reg_rtx, old)
6848 && rl->reg_rtx != 0)
6849 emit_input_reload_insns (chain, rld + j, old, j);
6851 /* When inheriting a wider reload, we have a MEM in rl->in,
6852 e.g. inheriting a SImode output reload for
6853 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6854 if (optimize && reload_inherited[j] && rl->in
6856 && MEM_P (rl->in_reg)
6857 && reload_spill_index[j] >= 0
6858 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6859 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6861 /* If we are reloading a register that was recently stored in with an
6862 output-reload, see if we can prove there was
6863 actually no need to store the old value in it. */
6866 && (reload_inherited[j] || reload_override_in[j])
6868 && REG_P (rl->reg_rtx)
6869 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6871 /* There doesn't seem to be any reason to restrict this to pseudos
6872 and doing so loses in the case where we are copying from a
6873 register of the wrong class. */
6874 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6875 >= FIRST_PSEUDO_REGISTER)
6877 /* The insn might have already some references to stackslots
6878 replaced by MEMs, while reload_out_reg still names the
6880 && (dead_or_set_p (insn,
6881 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6882 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6884 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6887 /* Do output reloading for reload RL, which is for the insn described by
6888 CHAIN and has the number J.
6889 ??? At some point we need to support handling output reloads of
6890 JUMP_INSNs or insns that set cc0. */
6892 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6895 rtx insn = chain->insn;
6896 /* If this is an output reload that stores something that is
6897 not loaded in this same reload, see if we can eliminate a previous
6899 rtx pseudo = rl->out_reg;
6904 && ! rtx_equal_p (rl->in_reg, pseudo)
6905 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6906 && reg_last_reload_reg[REGNO (pseudo)])
6908 int pseudo_no = REGNO (pseudo);
6909 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6911 /* We don't need to test full validity of last_regno for
6912 inherit here; we only want to know if the store actually
6913 matches the pseudo. */
6914 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6915 && reg_reloaded_contents[last_regno] == pseudo_no
6916 && spill_reg_store[last_regno]
6917 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6918 delete_output_reload (insn, j, last_regno);
6923 || rl->reg_rtx == old
6924 || rl->reg_rtx == 0)
6927 /* An output operand that dies right away does need a reload,
6928 but need not be copied from it. Show the new location in the
6930 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6931 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6933 XEXP (note, 0) = rl->reg_rtx;
6936 /* Likewise for a SUBREG of an operand that dies. */
6937 else if (GET_CODE (old) == SUBREG
6938 && REG_P (SUBREG_REG (old))
6939 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6942 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6946 else if (GET_CODE (old) == SCRATCH)
6947 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6948 but we don't want to make an output reload. */
6951 /* If is a JUMP_INSN, we can't support output reloads yet. */
6952 if (GET_CODE (insn) == JUMP_INSN)
6955 emit_output_reload_insns (chain, rld + j, j);
6958 /* Reload number R reloads from or to a group of hard registers starting at
6959 register REGNO. Return true if it can be treated for inheritance purposes
6960 like a group of reloads, each one reloading a single hard register.
6961 The caller has already checked that the spill register and REGNO use
6962 the same number of registers to store the reload value. */
6965 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6967 #ifdef CANNOT_CHANGE_MODE_CLASS
6968 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6969 GET_MODE (rld[r].reg_rtx),
6970 reg_raw_mode[reload_spill_index[r]])
6971 && !REG_CANNOT_CHANGE_MODE_P (regno,
6972 GET_MODE (rld[r].reg_rtx),
6973 reg_raw_mode[regno]));
6979 /* Output insns to reload values in and out of the chosen reload regs. */
6982 emit_reload_insns (struct insn_chain *chain)
6984 rtx insn = chain->insn;
6988 CLEAR_HARD_REG_SET (reg_reloaded_died);
6990 for (j = 0; j < reload_n_operands; j++)
6991 input_reload_insns[j] = input_address_reload_insns[j]
6992 = inpaddr_address_reload_insns[j]
6993 = output_reload_insns[j] = output_address_reload_insns[j]
6994 = outaddr_address_reload_insns[j]
6995 = other_output_reload_insns[j] = 0;
6996 other_input_address_reload_insns = 0;
6997 other_input_reload_insns = 0;
6998 operand_reload_insns = 0;
6999 other_operand_reload_insns = 0;
7001 /* Dump reloads into the dump file. */
7004 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7005 debug_reload_to_stream (dump_file);
7008 /* Now output the instructions to copy the data into and out of the
7009 reload registers. Do these in the order that the reloads were reported,
7010 since reloads of base and index registers precede reloads of operands
7011 and the operands may need the base and index registers reloaded. */
7013 for (j = 0; j < n_reloads; j++)
7016 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7017 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7019 do_input_reload (chain, rld + j, j);
7020 do_output_reload (chain, rld + j, j);
7023 /* Now write all the insns we made for reloads in the order expected by
7024 the allocation functions. Prior to the insn being reloaded, we write
7025 the following reloads:
7027 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7029 RELOAD_OTHER reloads.
7031 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7032 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7033 RELOAD_FOR_INPUT reload for the operand.
7035 RELOAD_FOR_OPADDR_ADDRS reloads.
7037 RELOAD_FOR_OPERAND_ADDRESS reloads.
7039 After the insn being reloaded, we write the following:
7041 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7042 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7043 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7044 reloads for the operand. The RELOAD_OTHER output reloads are
7045 output in descending order by reload number. */
7047 emit_insn_before_sameloc (other_input_address_reload_insns, insn);
7048 emit_insn_before_sameloc (other_input_reload_insns, insn);
7050 for (j = 0; j < reload_n_operands; j++)
7052 emit_insn_before_sameloc (inpaddr_address_reload_insns[j], insn);
7053 emit_insn_before_sameloc (input_address_reload_insns[j], insn);
7054 emit_insn_before_sameloc (input_reload_insns[j], insn);
7057 emit_insn_before_sameloc (other_operand_reload_insns, insn);
7058 emit_insn_before_sameloc (operand_reload_insns, insn);
7060 for (j = 0; j < reload_n_operands; j++)
7062 rtx x = emit_insn_after_sameloc (outaddr_address_reload_insns[j], insn);
7063 x = emit_insn_after_sameloc (output_address_reload_insns[j], x);
7064 x = emit_insn_after_sameloc (output_reload_insns[j], x);
7065 emit_insn_after_sameloc (other_output_reload_insns[j], x);
7068 /* For all the spill regs newly reloaded in this instruction,
7069 record what they were reloaded from, so subsequent instructions
7070 can inherit the reloads.
7072 Update spill_reg_store for the reloads of this insn.
7073 Copy the elements that were updated in the loop above. */
7075 for (j = 0; j < n_reloads; j++)
7077 int r = reload_order[j];
7078 int i = reload_spill_index[r];
7080 /* If this is a non-inherited input reload from a pseudo, we must
7081 clear any memory of a previous store to the same pseudo. Only do
7082 something if there will not be an output reload for the pseudo
7084 if (rld[r].in_reg != 0
7085 && ! (reload_inherited[r] || reload_override_in[r]))
7087 rtx reg = rld[r].in_reg;
7089 if (GET_CODE (reg) == SUBREG)
7090 reg = SUBREG_REG (reg);
7093 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7094 && ! reg_has_output_reload[REGNO (reg)])
7096 int nregno = REGNO (reg);
7098 if (reg_last_reload_reg[nregno])
7100 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7102 if (reg_reloaded_contents[last_regno] == nregno)
7103 spill_reg_store[last_regno] = 0;
7108 /* I is nonneg if this reload used a register.
7109 If rld[r].reg_rtx is 0, this is an optional reload
7110 that we opted to ignore. */
7112 if (i >= 0 && rld[r].reg_rtx != 0)
7114 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7116 int part_reaches_end = 0;
7117 int all_reaches_end = 1;
7119 /* For a multi register reload, we need to check if all or part
7120 of the value lives to the end. */
7121 for (k = 0; k < nr; k++)
7123 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7124 rld[r].when_needed))
7125 part_reaches_end = 1;
7127 all_reaches_end = 0;
7130 /* Ignore reloads that don't reach the end of the insn in
7132 if (all_reaches_end)
7134 /* First, clear out memory of what used to be in this spill reg.
7135 If consecutive registers are used, clear them all. */
7137 for (k = 0; k < nr; k++)
7139 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7140 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7143 /* Maybe the spill reg contains a copy of reload_out. */
7145 && (REG_P (rld[r].out)
7149 || REG_P (rld[r].out_reg)))
7151 rtx out = (REG_P (rld[r].out)
7155 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7156 int nregno = REGNO (out);
7157 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7158 : hard_regno_nregs[nregno]
7159 [GET_MODE (rld[r].reg_rtx)]);
7162 spill_reg_store[i] = new_spill_reg_store[i];
7163 spill_reg_stored_to[i] = out;
7164 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7166 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7168 && inherit_piecemeal_p (r, nregno));
7170 /* If NREGNO is a hard register, it may occupy more than
7171 one register. If it does, say what is in the
7172 rest of the registers assuming that both registers
7173 agree on how many words the object takes. If not,
7174 invalidate the subsequent registers. */
7176 if (nregno < FIRST_PSEUDO_REGISTER)
7177 for (k = 1; k < nnr; k++)
7178 reg_last_reload_reg[nregno + k]
7180 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7183 /* Now do the inverse operation. */
7184 for (k = 0; k < nr; k++)
7186 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7187 reg_reloaded_contents[i + k]
7188 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7191 reg_reloaded_insn[i + k] = insn;
7192 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7193 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7194 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7198 /* Maybe the spill reg contains a copy of reload_in. Only do
7199 something if there will not be an output reload for
7200 the register being reloaded. */
7201 else if (rld[r].out_reg == 0
7203 && ((REG_P (rld[r].in)
7204 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7205 && ! reg_has_output_reload[REGNO (rld[r].in)])
7206 || (REG_P (rld[r].in_reg)
7207 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7208 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7215 if (REG_P (rld[r].in)
7216 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7218 else if (REG_P (rld[r].in_reg))
7221 in = XEXP (rld[r].in_reg, 0);
7222 nregno = REGNO (in);
7224 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7225 : hard_regno_nregs[nregno]
7226 [GET_MODE (rld[r].reg_rtx)]);
7228 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7230 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7232 && inherit_piecemeal_p (r, nregno));
7234 if (nregno < FIRST_PSEUDO_REGISTER)
7235 for (k = 1; k < nnr; k++)
7236 reg_last_reload_reg[nregno + k]
7238 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7241 /* Unless we inherited this reload, show we haven't
7242 recently done a store.
7243 Previous stores of inherited auto_inc expressions
7244 also have to be discarded. */
7245 if (! reload_inherited[r]
7246 || (rld[r].out && ! rld[r].out_reg))
7247 spill_reg_store[i] = 0;
7249 for (k = 0; k < nr; k++)
7251 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7252 reg_reloaded_contents[i + k]
7253 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7256 reg_reloaded_insn[i + k] = insn;
7257 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7258 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7259 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7264 /* However, if part of the reload reaches the end, then we must
7265 invalidate the old info for the part that survives to the end. */
7266 else if (part_reaches_end)
7268 for (k = 0; k < nr; k++)
7269 if (reload_reg_reaches_end_p (i + k,
7271 rld[r].when_needed))
7272 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7276 /* The following if-statement was #if 0'd in 1.34 (or before...).
7277 It's reenabled in 1.35 because supposedly nothing else
7278 deals with this problem. */
7280 /* If a register gets output-reloaded from a non-spill register,
7281 that invalidates any previous reloaded copy of it.
7282 But forget_old_reloads_1 won't get to see it, because
7283 it thinks only about the original insn. So invalidate it here. */
7284 if (i < 0 && rld[r].out != 0
7285 && (REG_P (rld[r].out)
7286 || (MEM_P (rld[r].out)
7287 && REG_P (rld[r].out_reg))))
7289 rtx out = (REG_P (rld[r].out)
7290 ? rld[r].out : rld[r].out_reg);
7291 int nregno = REGNO (out);
7292 if (nregno >= FIRST_PSEUDO_REGISTER)
7294 rtx src_reg, store_insn = NULL_RTX;
7296 reg_last_reload_reg[nregno] = 0;
7298 /* If we can find a hard register that is stored, record
7299 the storing insn so that we may delete this insn with
7300 delete_output_reload. */
7301 src_reg = rld[r].reg_rtx;
7303 /* If this is an optional reload, try to find the source reg
7304 from an input reload. */
7307 rtx set = single_set (insn);
7308 if (set && SET_DEST (set) == rld[r].out)
7312 src_reg = SET_SRC (set);
7314 for (k = 0; k < n_reloads; k++)
7316 if (rld[k].in == src_reg)
7318 src_reg = rld[k].reg_rtx;
7325 store_insn = new_spill_reg_store[REGNO (src_reg)];
7326 if (src_reg && REG_P (src_reg)
7327 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7329 int src_regno = REGNO (src_reg);
7330 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7331 /* The place where to find a death note varies with
7332 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7333 necessarily checked exactly in the code that moves
7334 notes, so just check both locations. */
7335 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7336 if (! note && store_insn)
7337 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7340 spill_reg_store[src_regno + nr] = store_insn;
7341 spill_reg_stored_to[src_regno + nr] = out;
7342 reg_reloaded_contents[src_regno + nr] = nregno;
7343 reg_reloaded_insn[src_regno + nr] = store_insn;
7344 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7345 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7346 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7347 GET_MODE (src_reg)))
7348 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7350 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7352 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7354 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7356 reg_last_reload_reg[nregno] = src_reg;
7357 /* We have to set reg_has_output_reload here, or else
7358 forget_old_reloads_1 will clear reg_last_reload_reg
7360 reg_has_output_reload[nregno] = 1;
7365 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7367 while (num_regs-- > 0)
7368 reg_last_reload_reg[nregno + num_regs] = 0;
7372 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7375 /* Emit code to perform a reload from IN (which may be a reload register) to
7376 OUT (which may also be a reload register). IN or OUT is from operand
7377 OPNUM with reload type TYPE.
7379 Returns first insn emitted. */
7382 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7384 rtx last = get_last_insn ();
7387 /* If IN is a paradoxical SUBREG, remove it and try to put the
7388 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7389 if (GET_CODE (in) == SUBREG
7390 && (GET_MODE_SIZE (GET_MODE (in))
7391 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7392 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7393 in = SUBREG_REG (in), out = tem;
7394 else if (GET_CODE (out) == SUBREG
7395 && (GET_MODE_SIZE (GET_MODE (out))
7396 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7397 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7398 out = SUBREG_REG (out), in = tem;
7400 /* How to do this reload can get quite tricky. Normally, we are being
7401 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7402 register that didn't get a hard register. In that case we can just
7403 call emit_move_insn.
7405 We can also be asked to reload a PLUS that adds a register or a MEM to
7406 another register, constant or MEM. This can occur during frame pointer
7407 elimination and while reloading addresses. This case is handled by
7408 trying to emit a single insn to perform the add. If it is not valid,
7409 we use a two insn sequence.
7411 Finally, we could be called to handle an 'o' constraint by putting
7412 an address into a register. In that case, we first try to do this
7413 with a named pattern of "reload_load_address". If no such pattern
7414 exists, we just emit a SET insn and hope for the best (it will normally
7415 be valid on machines that use 'o').
7417 This entire process is made complex because reload will never
7418 process the insns we generate here and so we must ensure that
7419 they will fit their constraints and also by the fact that parts of
7420 IN might be being reloaded separately and replaced with spill registers.
7421 Because of this, we are, in some sense, just guessing the right approach
7422 here. The one listed above seems to work.
7424 ??? At some point, this whole thing needs to be rethought. */
7426 if (GET_CODE (in) == PLUS
7427 && (REG_P (XEXP (in, 0))
7428 || GET_CODE (XEXP (in, 0)) == SUBREG
7429 || MEM_P (XEXP (in, 0)))
7430 && (REG_P (XEXP (in, 1))
7431 || GET_CODE (XEXP (in, 1)) == SUBREG
7432 || CONSTANT_P (XEXP (in, 1))
7433 || MEM_P (XEXP (in, 1))))
7435 /* We need to compute the sum of a register or a MEM and another
7436 register, constant, or MEM, and put it into the reload
7437 register. The best possible way of doing this is if the machine
7438 has a three-operand ADD insn that accepts the required operands.
7440 The simplest approach is to try to generate such an insn and see if it
7441 is recognized and matches its constraints. If so, it can be used.
7443 It might be better not to actually emit the insn unless it is valid,
7444 but we need to pass the insn as an operand to `recog' and
7445 `extract_insn' and it is simpler to emit and then delete the insn if
7446 not valid than to dummy things up. */
7448 rtx op0, op1, tem, insn;
7451 op0 = find_replacement (&XEXP (in, 0));
7452 op1 = find_replacement (&XEXP (in, 1));
7454 /* Since constraint checking is strict, commutativity won't be
7455 checked, so we need to do that here to avoid spurious failure
7456 if the add instruction is two-address and the second operand
7457 of the add is the same as the reload reg, which is frequently
7458 the case. If the insn would be A = B + A, rearrange it so
7459 it will be A = A + B as constrain_operands expects. */
7461 if (REG_P (XEXP (in, 1))
7462 && REGNO (out) == REGNO (XEXP (in, 1)))
7463 tem = op0, op0 = op1, op1 = tem;
7465 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7466 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7468 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7469 code = recog_memoized (insn);
7473 extract_insn (insn);
7474 /* We want constrain operands to treat this insn strictly in
7475 its validity determination, i.e., the way it would after reload
7477 if (constrain_operands (1))
7481 delete_insns_since (last);
7483 /* If that failed, we must use a conservative two-insn sequence.
7485 Use a move to copy one operand into the reload register. Prefer
7486 to reload a constant, MEM or pseudo since the move patterns can
7487 handle an arbitrary operand. If OP1 is not a constant, MEM or
7488 pseudo and OP1 is not a valid operand for an add instruction, then
7491 After reloading one of the operands into the reload register, add
7492 the reload register to the output register.
7494 If there is another way to do this for a specific machine, a
7495 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7498 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7500 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7502 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7503 || (code != CODE_FOR_nothing
7504 && ! ((*insn_data[code].operand[2].predicate)
7505 (op1, insn_data[code].operand[2].mode))))
7506 tem = op0, op0 = op1, op1 = tem;
7508 gen_reload (out, op0, opnum, type);
7510 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7511 This fixes a problem on the 32K where the stack pointer cannot
7512 be used as an operand of an add insn. */
7514 if (rtx_equal_p (op0, op1))
7517 insn = emit_insn (gen_add2_insn (out, op1));
7519 /* If that failed, copy the address register to the reload register.
7520 Then add the constant to the reload register. */
7522 code = recog_memoized (insn);
7526 extract_insn (insn);
7527 /* We want constrain operands to treat this insn strictly in
7528 its validity determination, i.e., the way it would after reload
7530 if (constrain_operands (1))
7532 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7534 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7539 delete_insns_since (last);
7541 gen_reload (out, op1, opnum, type);
7542 insn = emit_insn (gen_add2_insn (out, op0));
7543 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7546 #ifdef SECONDARY_MEMORY_NEEDED
7547 /* If we need a memory location to do the move, do it that way. */
7548 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7549 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7550 && (REG_P (out) || GET_CODE (out) == SUBREG)
7551 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7552 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7553 REGNO_REG_CLASS (reg_or_subregno (out)),
7556 /* Get the memory to use and rewrite both registers to its mode. */
7557 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7559 if (GET_MODE (loc) != GET_MODE (out))
7560 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7562 if (GET_MODE (loc) != GET_MODE (in))
7563 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7565 gen_reload (loc, in, opnum, type);
7566 gen_reload (out, loc, opnum, type);
7570 /* If IN is a simple operand, use gen_move_insn. */
7571 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7572 emit_insn (gen_move_insn (out, in));
7574 #ifdef HAVE_reload_load_address
7575 else if (HAVE_reload_load_address)
7576 emit_insn (gen_reload_load_address (out, in));
7579 /* Otherwise, just write (set OUT IN) and hope for the best. */
7581 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7583 /* Return the first insn emitted.
7584 We can not just return get_last_insn, because there may have
7585 been multiple instructions emitted. Also note that gen_move_insn may
7586 emit more than one insn itself, so we can not assume that there is one
7587 insn emitted per emit_insn_before call. */
7589 return last ? NEXT_INSN (last) : get_insns ();
7592 /* Delete a previously made output-reload whose result we now believe
7593 is not needed. First we double-check.
7595 INSN is the insn now being processed.
7596 LAST_RELOAD_REG is the hard register number for which we want to delete
7597 the last output reload.
7598 J is the reload-number that originally used REG. The caller has made
7599 certain that reload J doesn't use REG any longer for input. */
7602 delete_output_reload (rtx insn, int j, int last_reload_reg)
7604 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7605 rtx reg = spill_reg_stored_to[last_reload_reg];
7608 int n_inherited = 0;
7612 /* It is possible that this reload has been only used to set another reload
7613 we eliminated earlier and thus deleted this instruction too. */
7614 if (INSN_DELETED_P (output_reload_insn))
7617 /* Get the raw pseudo-register referred to. */
7619 while (GET_CODE (reg) == SUBREG)
7620 reg = SUBREG_REG (reg);
7621 substed = reg_equiv_memory_loc[REGNO (reg)];
7623 /* This is unsafe if the operand occurs more often in the current
7624 insn than it is inherited. */
7625 for (k = n_reloads - 1; k >= 0; k--)
7627 rtx reg2 = rld[k].in;
7630 if (MEM_P (reg2) || reload_override_in[k])
7631 reg2 = rld[k].in_reg;
7633 if (rld[k].out && ! rld[k].out_reg)
7634 reg2 = XEXP (rld[k].in_reg, 0);
7636 while (GET_CODE (reg2) == SUBREG)
7637 reg2 = SUBREG_REG (reg2);
7638 if (rtx_equal_p (reg2, reg))
7640 if (reload_inherited[k] || reload_override_in[k] || k == j)
7643 reg2 = rld[k].out_reg;
7646 while (GET_CODE (reg2) == SUBREG)
7647 reg2 = XEXP (reg2, 0);
7648 if (rtx_equal_p (reg2, reg))
7655 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7657 n_occurrences += count_occurrences (PATTERN (insn),
7658 eliminate_regs (substed, 0,
7660 if (n_occurrences > n_inherited)
7663 /* If the pseudo-reg we are reloading is no longer referenced
7664 anywhere between the store into it and here,
7665 and no jumps or labels intervene, then the value can get
7666 here through the reload reg alone.
7667 Otherwise, give up--return. */
7668 for (i1 = NEXT_INSN (output_reload_insn);
7669 i1 != insn; i1 = NEXT_INSN (i1))
7671 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7673 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7674 && reg_mentioned_p (reg, PATTERN (i1)))
7676 /* If this is USE in front of INSN, we only have to check that
7677 there are no more references than accounted for by inheritance. */
7678 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7680 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7681 i1 = NEXT_INSN (i1);
7683 if (n_occurrences <= n_inherited && i1 == insn)
7689 /* We will be deleting the insn. Remove the spill reg information. */
7690 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7692 spill_reg_store[last_reload_reg + k] = 0;
7693 spill_reg_stored_to[last_reload_reg + k] = 0;
7696 /* The caller has already checked that REG dies or is set in INSN.
7697 It has also checked that we are optimizing, and thus some
7698 inaccuracies in the debugging information are acceptable.
7699 So we could just delete output_reload_insn. But in some cases
7700 we can improve the debugging information without sacrificing
7701 optimization - maybe even improving the code: See if the pseudo
7702 reg has been completely replaced with reload regs. If so, delete
7703 the store insn and forget we had a stack slot for the pseudo. */
7704 if (rld[j].out != rld[j].in
7705 && REG_N_DEATHS (REGNO (reg)) == 1
7706 && REG_N_SETS (REGNO (reg)) == 1
7707 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7708 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7712 /* We know that it was used only between here and the beginning of
7713 the current basic block. (We also know that the last use before
7714 INSN was the output reload we are thinking of deleting, but never
7715 mind that.) Search that range; see if any ref remains. */
7716 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7718 rtx set = single_set (i2);
7720 /* Uses which just store in the pseudo don't count,
7721 since if they are the only uses, they are dead. */
7722 if (set != 0 && SET_DEST (set) == reg)
7724 if (GET_CODE (i2) == CODE_LABEL
7725 || GET_CODE (i2) == JUMP_INSN)
7727 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7728 && reg_mentioned_p (reg, PATTERN (i2)))
7730 /* Some other ref remains; just delete the output reload we
7732 delete_address_reloads (output_reload_insn, insn);
7733 delete_insn (output_reload_insn);
7738 /* Delete the now-dead stores into this pseudo. Note that this
7739 loop also takes care of deleting output_reload_insn. */
7740 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7742 rtx set = single_set (i2);
7744 if (set != 0 && SET_DEST (set) == reg)
7746 delete_address_reloads (i2, insn);
7749 if (GET_CODE (i2) == CODE_LABEL
7750 || GET_CODE (i2) == JUMP_INSN)
7754 /* For the debugging info, say the pseudo lives in this reload reg. */
7755 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7756 alter_reg (REGNO (reg), -1);
7760 delete_address_reloads (output_reload_insn, insn);
7761 delete_insn (output_reload_insn);
7765 /* We are going to delete DEAD_INSN. Recursively delete loads of
7766 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7767 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7769 delete_address_reloads (rtx dead_insn, rtx current_insn)
7771 rtx set = single_set (dead_insn);
7772 rtx set2, dst, prev, next;
7775 rtx dst = SET_DEST (set);
7777 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7779 /* If we deleted the store from a reloaded post_{in,de}c expression,
7780 we can delete the matching adds. */
7781 prev = PREV_INSN (dead_insn);
7782 next = NEXT_INSN (dead_insn);
7783 if (! prev || ! next)
7785 set = single_set (next);
7786 set2 = single_set (prev);
7788 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7789 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7790 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7792 dst = SET_DEST (set);
7793 if (! rtx_equal_p (dst, SET_DEST (set2))
7794 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7795 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7796 || (INTVAL (XEXP (SET_SRC (set), 1))
7797 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7799 delete_related_insns (prev);
7800 delete_related_insns (next);
7803 /* Subfunction of delete_address_reloads: process registers found in X. */
7805 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7807 rtx prev, set, dst, i2;
7809 enum rtx_code code = GET_CODE (x);
7813 const char *fmt = GET_RTX_FORMAT (code);
7814 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7817 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7818 else if (fmt[i] == 'E')
7820 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7821 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7828 if (spill_reg_order[REGNO (x)] < 0)
7831 /* Scan backwards for the insn that sets x. This might be a way back due
7833 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7835 code = GET_CODE (prev);
7836 if (code == CODE_LABEL || code == JUMP_INSN)
7840 if (reg_set_p (x, PATTERN (prev)))
7842 if (reg_referenced_p (x, PATTERN (prev)))
7845 if (! prev || INSN_UID (prev) < reload_first_uid)
7847 /* Check that PREV only sets the reload register. */
7848 set = single_set (prev);
7851 dst = SET_DEST (set);
7853 || ! rtx_equal_p (dst, x))
7855 if (! reg_set_p (dst, PATTERN (dead_insn)))
7857 /* Check if DST was used in a later insn -
7858 it might have been inherited. */
7859 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7861 if (GET_CODE (i2) == CODE_LABEL)
7865 if (reg_referenced_p (dst, PATTERN (i2)))
7867 /* If there is a reference to the register in the current insn,
7868 it might be loaded in a non-inherited reload. If no other
7869 reload uses it, that means the register is set before
7871 if (i2 == current_insn)
7873 for (j = n_reloads - 1; j >= 0; j--)
7874 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7875 || reload_override_in[j] == dst)
7877 for (j = n_reloads - 1; j >= 0; j--)
7878 if (rld[j].in && rld[j].reg_rtx == dst)
7885 if (GET_CODE (i2) == JUMP_INSN)
7887 /* If DST is still live at CURRENT_INSN, check if it is used for
7888 any reload. Note that even if CURRENT_INSN sets DST, we still
7889 have to check the reloads. */
7890 if (i2 == current_insn)
7892 for (j = n_reloads - 1; j >= 0; j--)
7893 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7894 || reload_override_in[j] == dst)
7896 /* ??? We can't finish the loop here, because dst might be
7897 allocated to a pseudo in this block if no reload in this
7898 block needs any of the classes containing DST - see
7899 spill_hard_reg. There is no easy way to tell this, so we
7900 have to scan till the end of the basic block. */
7902 if (reg_set_p (dst, PATTERN (i2)))
7906 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7907 reg_reloaded_contents[REGNO (dst)] = -1;
7911 /* Output reload-insns to reload VALUE into RELOADREG.
7912 VALUE is an autoincrement or autodecrement RTX whose operand
7913 is a register or memory location;
7914 so reloading involves incrementing that location.
7915 IN is either identical to VALUE, or some cheaper place to reload from.
7917 INC_AMOUNT is the number to increment or decrement by (always positive).
7918 This cannot be deduced from VALUE.
7920 Return the instruction that stores into RELOADREG. */
7923 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7925 /* REG or MEM to be copied and incremented. */
7926 rtx incloc = XEXP (value, 0);
7927 /* Nonzero if increment after copying. */
7928 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7934 rtx real_in = in == value ? XEXP (in, 0) : in;
7936 /* No hard register is equivalent to this register after
7937 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7938 we could inc/dec that register as well (maybe even using it for
7939 the source), but I'm not sure it's worth worrying about. */
7941 reg_last_reload_reg[REGNO (incloc)] = 0;
7943 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7944 inc_amount = -inc_amount;
7946 inc = GEN_INT (inc_amount);
7948 /* If this is post-increment, first copy the location to the reload reg. */
7949 if (post && real_in != reloadreg)
7950 emit_insn (gen_move_insn (reloadreg, real_in));
7954 /* See if we can directly increment INCLOC. Use a method similar to
7955 that in gen_reload. */
7957 last = get_last_insn ();
7958 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7959 gen_rtx_PLUS (GET_MODE (incloc),
7962 code = recog_memoized (add_insn);
7965 extract_insn (add_insn);
7966 if (constrain_operands (1))
7968 /* If this is a pre-increment and we have incremented the value
7969 where it lives, copy the incremented value to RELOADREG to
7970 be used as an address. */
7973 emit_insn (gen_move_insn (reloadreg, incloc));
7978 delete_insns_since (last);
7981 /* If couldn't do the increment directly, must increment in RELOADREG.
7982 The way we do this depends on whether this is pre- or post-increment.
7983 For pre-increment, copy INCLOC to the reload register, increment it
7984 there, then save back. */
7988 if (in != reloadreg)
7989 emit_insn (gen_move_insn (reloadreg, real_in));
7990 emit_insn (gen_add2_insn (reloadreg, inc));
7991 store = emit_insn (gen_move_insn (incloc, reloadreg));
7996 Because this might be a jump insn or a compare, and because RELOADREG
7997 may not be available after the insn in an input reload, we must do
7998 the incrementation before the insn being reloaded for.
8000 We have already copied IN to RELOADREG. Increment the copy in
8001 RELOADREG, save that back, then decrement RELOADREG so it has
8002 the original value. */
8004 emit_insn (gen_add2_insn (reloadreg, inc));
8005 store = emit_insn (gen_move_insn (incloc, reloadreg));
8006 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8014 add_auto_inc_notes (rtx insn, rtx x)
8016 enum rtx_code code = GET_CODE (x);
8020 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8023 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8027 /* Scan all the operand sub-expressions. */
8028 fmt = GET_RTX_FORMAT (code);
8029 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8032 add_auto_inc_notes (insn, XEXP (x, i));
8033 else if (fmt[i] == 'E')
8034 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8035 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8040 /* Copy EH notes from an insn to its reloads. */
8042 copy_eh_notes (rtx insn, rtx x)
8044 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8047 for (; x != 0; x = NEXT_INSN (x))
8049 if (may_trap_p (PATTERN (x)))
8051 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8057 /* This is used by reload pass, that does emit some instructions after
8058 abnormal calls moving basic block end, but in fact it wants to emit
8059 them on the edge. Looks for abnormal call edges, find backward the
8060 proper call and fix the damage.
8062 Similar handle instructions throwing exceptions internally. */
8064 fixup_abnormal_edges (void)
8066 bool inserted = false;
8073 /* Look for cases we are interested in - calls or instructions causing
8075 for (e = bb->succ; e; e = e->succ_next)
8077 if (e->flags & EDGE_ABNORMAL_CALL)
8079 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8080 == (EDGE_ABNORMAL | EDGE_EH))
8083 if (e && GET_CODE (BB_END (bb)) != CALL_INSN
8084 && !can_throw_internal (BB_END (bb)))
8086 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8088 for (e = bb->succ; e; e = e->succ_next)
8089 if (e->flags & EDGE_FALLTHRU)
8091 /* Get past the new insns generated. Allow notes, as the insns may
8092 be already deleted. */
8093 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
8094 && !can_throw_internal (insn)
8095 && insn != BB_HEAD (bb))
8096 insn = PREV_INSN (insn);
8097 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
8101 insn = NEXT_INSN (insn);
8102 while (insn && insn != stop)
8104 next = NEXT_INSN (insn);
8109 /* Sometimes there's still the return value USE.
8110 If it's placed after a trapping call (i.e. that
8111 call is the last insn anyway), we have no fallthru
8112 edge. Simply delete this use and don't try to insert
8113 on the non-existent edge. */
8114 if (GET_CODE (PATTERN (insn)) != USE)
8116 /* We're not deleting it, we're moving it. */
8117 INSN_DELETED_P (insn) = 0;
8118 PREV_INSN (insn) = NULL_RTX;
8119 NEXT_INSN (insn) = NULL_RTX;
8121 insert_insn_on_edge (insn, e);
8128 /* We've possibly turned single trapping insn into multiple ones. */
8129 if (flag_non_call_exceptions)
8132 blocks = sbitmap_alloc (last_basic_block);
8133 sbitmap_ones (blocks);
8134 find_many_sub_basic_blocks (blocks);
8137 commit_edge_insertions ();
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