1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-5, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
32 #include "hard-reg-set.h"
35 #include "basic-block.h"
39 /* This file contains the reload pass of the compiler, which is
40 run after register allocation has been done. It checks that
41 each insn is valid (operands required to be in registers really
42 are in registers of the proper class) and fixes up invalid ones
43 by copying values temporarily into registers for the insns
46 The results of register allocation are described by the vector
47 reg_renumber; the insns still contain pseudo regs, but reg_renumber
48 can be used to find which hard reg, if any, a pseudo reg is in.
50 The technique we always use is to free up a few hard regs that are
51 called ``reload regs'', and for each place where a pseudo reg
52 must be in a hard reg, copy it temporarily into one of the reload regs.
54 All the pseudos that were formerly allocated to the hard regs that
55 are now in use as reload regs must be ``spilled''. This means
56 that they go to other hard regs, or to stack slots if no other
57 available hard regs can be found. Spilling can invalidate more
58 insns, requiring additional need for reloads, so we must keep checking
59 until the process stabilizes.
61 For machines with different classes of registers, we must keep track
62 of the register class needed for each reload, and make sure that
63 we allocate enough reload registers of each class.
65 The file reload.c contains the code that checks one insn for
66 validity and reports the reloads that it needs. This file
67 is in charge of scanning the entire rtl code, accumulating the
68 reload needs, spilling, assigning reload registers to use for
69 fixing up each insn, and generating the new insns to copy values
70 into the reload registers. */
73 #ifndef REGISTER_MOVE_COST
74 #define REGISTER_MOVE_COST(x, y) 2
77 #ifndef MEMORY_MOVE_COST
78 #define MEMORY_MOVE_COST(x) 4
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width;
117 /* Element N is the insn that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* During reload_as_needed, element N contains the last pseudo regno
122 reloaded into the Nth reload register. This vector is in parallel
123 with spill_regs. If that pseudo reg occupied more than one register,
124 reg_reloaded_contents points to that pseudo for each spill register in
125 use; all of these must remain set for an inheritance to occur. */
126 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
128 /* During reload_as_needed, element N contains the insn for which
129 the Nth reload register was last used. This vector is in parallel
130 with spill_regs, and its contents are significant only when
131 reg_reloaded_contents is significant. */
132 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
134 /* Number of spill-regs so far; number of valid elements of spill_regs. */
137 /* In parallel with spill_regs, contains REG rtx's for those regs.
138 Holds the last rtx used for any given reg, or 0 if it has never
139 been used for spilling yet. This rtx is reused, provided it has
141 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
143 /* In parallel with spill_regs, contains nonzero for a spill reg
144 that was stored after the last time it was used.
145 The precise value is the insn generated to do the store. */
146 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
148 /* This table is the inverse mapping of spill_regs:
149 indexed by hard reg number,
150 it contains the position of that reg in spill_regs,
151 or -1 for something that is not in spill_regs. */
152 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
154 /* This reg set indicates registers that may not be used for retrying global
155 allocation. The registers that may not be used include all spill registers
156 and the frame pointer (if we are using one). */
157 HARD_REG_SET forbidden_regs;
159 /* This reg set indicates registers that are not good for spill registers.
160 They will not be used to complete groups of spill registers. This includes
161 all fixed registers, registers that may be eliminated, and, if
162 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
164 (spill_reg_order prevents these registers from being used to start a
166 static HARD_REG_SET bad_spill_regs;
168 /* Describes order of use of registers for reloading
169 of spilled pseudo-registers. `spills' is the number of
170 elements that are actually valid; new ones are added at the end. */
171 static short spill_regs[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates those registers that have been used a spill
174 registers. This information is used in reorg.c, to help figure out
175 what registers are live at any point. It is assumed that all spill_regs
176 are dead at every CODE_LABEL. */
178 HARD_REG_SET used_spill_regs;
180 /* Index of last register assigned as a spill register. We allocate in
181 a round-robin fashion. */
183 static int last_spill_reg;
185 /* Describes order of preference for putting regs into spill_regs.
186 Contains the numbers of all the hard regs, in order most preferred first.
187 This order is different for each function.
188 It is set up by order_regs_for_reload.
189 Empty elements at the end contain -1. */
190 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
192 /* 1 for a hard register that appears explicitly in the rtl
193 (for example, function value registers, special registers
194 used by insns, structure value pointer registers). */
195 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
197 /* Indicates if a register was counted against the need for
198 groups. 0 means it can count against max_nongroup instead. */
199 static HARD_REG_SET counted_for_groups;
201 /* Indicates if a register was counted against the need for
202 non-groups. 0 means it can become part of a new group.
203 During choose_reload_regs, 1 here means don't use this reg
204 as part of a group, even if it seems to be otherwise ok. */
205 static HARD_REG_SET counted_for_nongroups;
207 /* Indexed by pseudo reg number N,
208 says may not delete stores into the real (memory) home of pseudo N.
209 This is set if we already substituted a memory equivalent in some uses,
210 which happens when we have to eliminate the fp from it. */
211 static char *cannot_omit_stores;
213 /* Nonzero if indirect addressing is supported on the machine; this means
214 that spilling (REG n) does not require reloading it into a register in
215 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
216 value indicates the level of indirect addressing supported, e.g., two
217 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
220 static char spill_indirect_levels;
222 /* Nonzero if indirect addressing is supported when the innermost MEM is
223 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
224 which these are valid is the same as spill_indirect_levels, above. */
226 char indirect_symref_ok;
228 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
234 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
236 /* Width allocated so far for that stack slot. */
238 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Indexed by register class and basic block number, nonzero if there is
241 any need for a spill register of that class in that basic block.
242 The pointer is 0 if we did stupid allocation and don't know
243 the structure of basic blocks. */
245 char *basic_block_needs[N_REG_CLASSES];
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
254 int caller_save_needed;
256 /* Set to 1 while reload_as_needed is operating.
257 Required by some machines to handle any generated moves differently. */
259 int reload_in_progress = 0;
261 /* These arrays record the insn_code of insns that may be needed to
262 perform input and output reloads of special objects. They provide a
263 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
272 struct obstack reload_obstack;
273 char *reload_firstobj;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels;
281 /* Allocation number table from global register allocation. */
282 extern int *reg_allocno;
284 /* This structure is used to record information about register eliminations.
285 Each array entry describes one possible way of eliminating a register
286 in favor of another. If there is more than one way of eliminating a
287 particular register, the most preferred should be specified first. */
289 static struct elim_table
291 int from; /* Register number to be eliminated. */
292 int to; /* Register number used as replacement. */
293 int initial_offset; /* Initial difference between values. */
294 int can_eliminate; /* Non-zero if this elimination can be done. */
295 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
296 insns made by reload. */
297 int offset; /* Current offset between the two regs. */
298 int max_offset; /* Maximum offset between the two regs. */
299 int previous_offset; /* Offset at end of previous insn. */
300 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
301 rtx from_rtx; /* REG rtx for the register to be eliminated.
302 We cannot simply compare the number since
303 we might then spuriously replace a hard
304 register corresponding to a pseudo
305 assigned to the reg to be eliminated. */
306 rtx to_rtx; /* REG rtx for the replacement. */
309 /* If a set of eliminable registers was specified, define the table from it.
310 Otherwise, default to the normal case of the frame pointer being
311 replaced by the stack pointer. */
313 #ifdef ELIMINABLE_REGS
316 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
319 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
321 /* Record the number of pending eliminations that have an offset not equal
322 to their initial offset. If non-zero, we use a new copy of each
323 replacement result in any insns encountered. */
324 static int num_not_at_initial_offset;
326 /* Count the number of registers that we may be able to eliminate. */
327 static int num_eliminable;
329 /* For each label, we record the offset of each elimination. If we reach
330 a label by more than one path and an offset differs, we cannot do the
331 elimination. This information is indexed by the number of the label.
332 The first table is an array of flags that records whether we have yet
333 encountered a label and the second table is an array of arrays, one
334 entry in the latter array for each elimination. */
336 static char *offsets_known_at;
337 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
339 /* Number of labels in the current function. */
341 static int num_labels;
343 struct hard_reg_n_uses { int regno; int uses; };
345 static int possible_group_p PROTO((int, int *));
346 static void count_possible_groups PROTO((int *, enum machine_mode *,
348 static int modes_equiv_for_class_p PROTO((enum machine_mode,
351 static void spill_failure PROTO((rtx));
352 static int new_spill_reg PROTO((int, int, int *, int *, int,
354 static void delete_dead_insn PROTO((rtx));
355 static void alter_reg PROTO((int, int));
356 static void mark_scratch_live PROTO((rtx));
357 static void set_label_offsets PROTO((rtx, rtx, int));
358 static int eliminate_regs_in_insn PROTO((rtx, int));
359 static void mark_not_eliminable PROTO((rtx, rtx));
360 static int spill_hard_reg PROTO((int, int, FILE *, int));
361 static void scan_paradoxical_subregs PROTO((rtx));
362 static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
363 static void order_regs_for_reload PROTO((int));
364 static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR));
365 static void reload_as_needed PROTO((rtx, int));
366 static void forget_old_reloads_1 PROTO((rtx, rtx));
367 static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
368 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
370 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
372 static int reload_reg_free_p PROTO((int, int, enum reload_type));
373 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
374 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
375 static int reloads_conflict PROTO((int, int));
376 static int allocate_reload_reg PROTO((int, rtx, int, int));
377 static void choose_reload_regs PROTO((rtx, rtx));
378 static void merge_assigned_reloads PROTO((rtx));
379 static void emit_reload_insns PROTO((rtx));
380 static void delete_output_reload PROTO((rtx, int, rtx));
381 static void inc_for_reload PROTO((rtx, rtx, int));
382 static int constraint_accepts_reg_p PROTO((char *, rtx));
383 static int count_occurrences PROTO((rtx, rtx));
385 /* Initialize the reload pass once per compilation. */
392 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
393 Set spill_indirect_levels to the number of levels such addressing is
394 permitted, zero if it is not permitted at all. */
397 = gen_rtx (MEM, Pmode,
398 gen_rtx (PLUS, Pmode,
399 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
401 spill_indirect_levels = 0;
403 while (memory_address_p (QImode, tem))
405 spill_indirect_levels++;
406 tem = gen_rtx (MEM, Pmode, tem);
409 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
411 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
412 indirect_symref_ok = memory_address_p (QImode, tem);
414 /* See if reg+reg is a valid (and offsettable) address. */
416 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
418 tem = gen_rtx (PLUS, Pmode,
419 gen_rtx (REG, Pmode, HARD_FRAME_POINTER_REGNUM),
420 gen_rtx (REG, Pmode, i));
421 /* This way, we make sure that reg+reg is an offsettable address. */
422 tem = plus_constant (tem, 4);
424 if (memory_address_p (QImode, tem))
426 double_reg_address_ok = 1;
431 /* Initialize obstack for our rtl allocation. */
432 gcc_obstack_init (&reload_obstack);
433 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
436 /* Main entry point for the reload pass.
438 FIRST is the first insn of the function being compiled.
440 GLOBAL nonzero means we were called from global_alloc
441 and should attempt to reallocate any pseudoregs that we
442 displace from hard regs we will use for reloads.
443 If GLOBAL is zero, we do not have enough information to do that,
444 so any pseudo reg that is spilled must go to the stack.
446 DUMPFILE is the global-reg debugging dump file stream, or 0.
447 If it is nonzero, messages are written to it to describe
448 which registers are seized as reload regs, which pseudo regs
449 are spilled from them, and where the pseudo regs are reallocated to.
451 Return value is nonzero if reload failed
452 and we must not do any more for this function. */
455 reload (first, global, dumpfile)
461 register int i, j, k;
463 register struct elim_table *ep;
465 int something_changed;
466 int something_needs_reloads;
467 int something_needs_elimination;
468 int new_basic_block_needs;
469 enum reg_class caller_save_spill_class = NO_REGS;
470 int caller_save_group_size = 1;
472 /* Nonzero means we couldn't get enough spill regs. */
475 /* The basic block number currently being processed for INSN. */
478 /* Make sure even insns with volatile mem refs are recognizable. */
481 /* Enable find_equiv_reg to distinguish insns made by reload. */
482 reload_first_uid = get_max_uid ();
484 for (i = 0; i < N_REG_CLASSES; i++)
485 basic_block_needs[i] = 0;
487 #ifdef SECONDARY_MEMORY_NEEDED
488 /* Initialize the secondary memory table. */
489 clear_secondary_mem ();
492 /* Remember which hard regs appear explicitly
493 before we merge into `regs_ever_live' the ones in which
494 pseudo regs have been allocated. */
495 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
497 /* We don't have a stack slot for any spill reg yet. */
498 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
499 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
501 /* Initialize the save area information for caller-save, in case some
505 /* Compute which hard registers are now in use
506 as homes for pseudo registers.
507 This is done here rather than (eg) in global_alloc
508 because this point is reached even if not optimizing. */
510 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
513 for (i = 0; i < scratch_list_length; i++)
515 mark_scratch_live (scratch_list[i]);
517 /* Make sure that the last insn in the chain
518 is not something that needs reloading. */
519 emit_note (NULL_PTR, NOTE_INSN_DELETED);
521 /* Find all the pseudo registers that didn't get hard regs
522 but do have known equivalent constants or memory slots.
523 These include parameters (known equivalent to parameter slots)
524 and cse'd or loop-moved constant memory addresses.
526 Record constant equivalents in reg_equiv_constant
527 so they will be substituted by find_reloads.
528 Record memory equivalents in reg_mem_equiv so they can
529 be substituted eventually by altering the REG-rtx's. */
531 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
532 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
533 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
534 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
535 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
536 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
537 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
538 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
539 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
540 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
541 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
542 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
543 cannot_omit_stores = (char *) alloca (max_regno);
544 bzero (cannot_omit_stores, max_regno);
546 #ifdef SMALL_REGISTER_CLASSES
547 CLEAR_HARD_REG_SET (forbidden_regs);
550 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
551 Also find all paradoxical subregs and find largest such for each pseudo.
552 On machines with small register classes, record hard registers that
553 are used for user variables. These can never be used for spills.
554 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
555 caller-saved registers must be marked live. */
557 for (insn = first; insn; insn = NEXT_INSN (insn))
559 rtx set = single_set (insn);
561 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
562 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
563 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
564 if (! call_used_regs[i])
565 regs_ever_live[i] = 1;
567 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
569 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
571 #ifdef LEGITIMATE_PIC_OPERAND_P
572 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
573 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
577 rtx x = XEXP (note, 0);
578 i = REGNO (SET_DEST (set));
579 if (i > LAST_VIRTUAL_REGISTER)
581 if (GET_CODE (x) == MEM)
582 reg_equiv_memory_loc[i] = x;
583 else if (CONSTANT_P (x))
585 if (LEGITIMATE_CONSTANT_P (x))
586 reg_equiv_constant[i] = x;
588 reg_equiv_memory_loc[i]
589 = force_const_mem (GET_MODE (SET_DEST (set)), x);
594 /* If this register is being made equivalent to a MEM
595 and the MEM is not SET_SRC, the equivalencing insn
596 is one with the MEM as a SET_DEST and it occurs later.
597 So don't mark this insn now. */
598 if (GET_CODE (x) != MEM
599 || rtx_equal_p (SET_SRC (set), x))
600 reg_equiv_init[i] = insn;
605 /* If this insn is setting a MEM from a register equivalent to it,
606 this is the equivalencing insn. */
607 else if (set && GET_CODE (SET_DEST (set)) == MEM
608 && GET_CODE (SET_SRC (set)) == REG
609 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
610 && rtx_equal_p (SET_DEST (set),
611 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
612 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
614 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
615 scan_paradoxical_subregs (PATTERN (insn));
618 /* Does this function require a frame pointer? */
620 frame_pointer_needed = (! flag_omit_frame_pointer
621 #ifdef EXIT_IGNORE_STACK
622 /* ?? If EXIT_IGNORE_STACK is set, we will not save
623 and restore sp for alloca. So we can't eliminate
624 the frame pointer in that case. At some point,
625 we should improve this by emitting the
626 sp-adjusting insns for this case. */
627 || (current_function_calls_alloca
628 && EXIT_IGNORE_STACK)
630 || FRAME_POINTER_REQUIRED);
634 /* Initialize the table of registers to eliminate. The way we do this
635 depends on how the eliminable registers were defined. */
636 #ifdef ELIMINABLE_REGS
637 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
639 ep->can_eliminate = ep->can_eliminate_previous
640 = (CAN_ELIMINATE (ep->from, ep->to)
641 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
644 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
645 = ! frame_pointer_needed;
648 /* Count the number of eliminable registers and build the FROM and TO
649 REG rtx's. Note that code in gen_rtx will cause, e.g.,
650 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
651 We depend on this. */
652 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
654 num_eliminable += ep->can_eliminate;
655 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
656 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
659 num_labels = max_label_num () - get_first_label_num ();
661 /* Allocate the tables used to store offset information at labels. */
662 offsets_known_at = (char *) alloca (num_labels);
664 = (int (*)[NUM_ELIMINABLE_REGS])
665 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
667 offsets_known_at -= get_first_label_num ();
668 offsets_at -= get_first_label_num ();
670 /* Alter each pseudo-reg rtx to contain its hard reg number.
671 Assign stack slots to the pseudos that lack hard regs or equivalents.
672 Do not touch virtual registers. */
674 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
677 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
678 because the stack size may be a part of the offset computation for
679 register elimination. */
680 assign_stack_local (BLKmode, 0, 0);
682 /* If we have some registers we think can be eliminated, scan all insns to
683 see if there is an insn that sets one of these registers to something
684 other than itself plus a constant. If so, the register cannot be
685 eliminated. Doing this scan here eliminates an extra pass through the
686 main reload loop in the most common case where register elimination
688 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
689 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
690 || GET_CODE (insn) == CALL_INSN)
691 note_stores (PATTERN (insn), mark_not_eliminable);
693 #ifndef REGISTER_CONSTRAINTS
694 /* If all the pseudo regs have hard regs,
695 except for those that are never referenced,
696 we know that no reloads are needed. */
697 /* But that is not true if there are register constraints, since
698 in that case some pseudos might be in the wrong kind of hard reg. */
700 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
701 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
704 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
708 /* Compute the order of preference for hard registers to spill.
709 Store them by decreasing preference in potential_reload_regs. */
711 order_regs_for_reload (global);
713 /* So far, no hard regs have been spilled. */
715 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
716 spill_reg_order[i] = -1;
718 /* Initialize to -1, which means take the first spill register. */
721 /* On most machines, we can't use any register explicitly used in the
722 rtl as a spill register. But on some, we have to. Those will have
723 taken care to keep the life of hard regs as short as possible. */
725 #ifndef SMALL_REGISTER_CLASSES
726 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
729 /* Spill any hard regs that we know we can't eliminate. */
730 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
731 if (! ep->can_eliminate)
732 spill_hard_reg (ep->from, global, dumpfile, 1);
734 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
735 if (frame_pointer_needed)
736 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
740 for (i = 0; i < N_REG_CLASSES; i++)
742 basic_block_needs[i] = (char *) alloca (n_basic_blocks);
743 bzero (basic_block_needs[i], n_basic_blocks);
746 /* From now on, we need to emit any moves without making new pseudos. */
747 reload_in_progress = 1;
749 /* This loop scans the entire function each go-round
750 and repeats until one repetition spills no additional hard regs. */
752 /* This flag is set when a pseudo reg is spilled,
753 to require another pass. Note that getting an additional reload
754 reg does not necessarily imply any pseudo reg was spilled;
755 sometimes we find a reload reg that no pseudo reg was allocated in. */
756 something_changed = 1;
757 /* This flag is set if there are any insns that require reloading. */
758 something_needs_reloads = 0;
759 /* This flag is set if there are any insns that require register
761 something_needs_elimination = 0;
762 while (something_changed)
766 /* For each class, number of reload regs needed in that class.
767 This is the maximum over all insns of the needs in that class
768 of the individual insn. */
769 int max_needs[N_REG_CLASSES];
770 /* For each class, size of group of consecutive regs
771 that is needed for the reloads of this class. */
772 int group_size[N_REG_CLASSES];
773 /* For each class, max number of consecutive groups needed.
774 (Each group contains group_size[CLASS] consecutive registers.) */
775 int max_groups[N_REG_CLASSES];
776 /* For each class, max number needed of regs that don't belong
777 to any of the groups. */
778 int max_nongroups[N_REG_CLASSES];
779 /* For each class, the machine mode which requires consecutive
780 groups of regs of that class.
781 If two different modes ever require groups of one class,
782 they must be the same size and equally restrictive for that class,
783 otherwise we can't handle the complexity. */
784 enum machine_mode group_mode[N_REG_CLASSES];
785 /* Record the insn where each maximum need is first found. */
786 rtx max_needs_insn[N_REG_CLASSES];
787 rtx max_groups_insn[N_REG_CLASSES];
788 rtx max_nongroups_insn[N_REG_CLASSES];
790 int starting_frame_size = get_frame_size ();
791 int previous_frame_pointer_needed = frame_pointer_needed;
792 static char *reg_class_names[] = REG_CLASS_NAMES;
794 something_changed = 0;
795 bzero ((char *) max_needs, sizeof max_needs);
796 bzero ((char *) max_groups, sizeof max_groups);
797 bzero ((char *) max_nongroups, sizeof max_nongroups);
798 bzero ((char *) max_needs_insn, sizeof max_needs_insn);
799 bzero ((char *) max_groups_insn, sizeof max_groups_insn);
800 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn);
801 bzero ((char *) group_size, sizeof group_size);
802 for (i = 0; i < N_REG_CLASSES; i++)
803 group_mode[i] = VOIDmode;
805 /* Keep track of which basic blocks are needing the reloads. */
808 /* Remember whether any element of basic_block_needs
809 changes from 0 to 1 in this pass. */
810 new_basic_block_needs = 0;
812 /* Reset all offsets on eliminable registers to their initial values. */
813 #ifdef ELIMINABLE_REGS
814 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
816 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
817 ep->previous_offset = ep->offset
818 = ep->max_offset = ep->initial_offset;
821 #ifdef INITIAL_FRAME_POINTER_OFFSET
822 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
824 if (!FRAME_POINTER_REQUIRED)
826 reg_eliminate[0].initial_offset = 0;
828 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
829 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
832 num_not_at_initial_offset = 0;
834 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
836 /* Set a known offset for each forced label to be at the initial offset
837 of each elimination. We do this because we assume that all
838 computed jumps occur from a location where each elimination is
839 at its initial offset. */
841 for (x = forced_labels; x; x = XEXP (x, 1))
843 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
845 /* For each pseudo register that has an equivalent location defined,
846 try to eliminate any eliminable registers (such as the frame pointer)
847 assuming initial offsets for the replacement register, which
850 If the resulting location is directly addressable, substitute
851 the MEM we just got directly for the old REG.
853 If it is not addressable but is a constant or the sum of a hard reg
854 and constant, it is probably not addressable because the constant is
855 out of range, in that case record the address; we will generate
856 hairy code to compute the address in a register each time it is
857 needed. Similarly if it is a hard register, but one that is not
858 valid as an address register.
860 If the location is not addressable, but does not have one of the
861 above forms, assign a stack slot. We have to do this to avoid the
862 potential of producing lots of reloads if, e.g., a location involves
863 a pseudo that didn't get a hard register and has an equivalent memory
864 location that also involves a pseudo that didn't get a hard register.
866 Perhaps at some point we will improve reload_when_needed handling
867 so this problem goes away. But that's very hairy. */
869 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
870 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
872 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
874 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
876 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
877 else if (CONSTANT_P (XEXP (x, 0))
878 || (GET_CODE (XEXP (x, 0)) == REG
879 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
880 || (GET_CODE (XEXP (x, 0)) == PLUS
881 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
882 && (REGNO (XEXP (XEXP (x, 0), 0))
883 < FIRST_PSEUDO_REGISTER)
884 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
885 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
888 /* Make a new stack slot. Then indicate that something
889 changed so we go back and recompute offsets for
890 eliminable registers because the allocation of memory
891 below might change some offset. reg_equiv_{mem,address}
892 will be set up for this pseudo on the next pass around
894 reg_equiv_memory_loc[i] = 0;
895 reg_equiv_init[i] = 0;
897 something_changed = 1;
901 /* If we allocated another pseudo to the stack, redo elimination
903 if (something_changed)
906 /* If caller-saves needs a group, initialize the group to include
907 the size and mode required for caller-saves. */
909 if (caller_save_group_size > 1)
911 group_mode[(int) caller_save_spill_class] = Pmode;
912 group_size[(int) caller_save_spill_class] = caller_save_group_size;
915 /* Compute the most additional registers needed by any instruction.
916 Collect information separately for each class of regs. */
918 for (insn = first; insn; insn = NEXT_INSN (insn))
920 if (global && this_block + 1 < n_basic_blocks
921 && insn == basic_block_head[this_block+1])
924 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
925 might include REG_LABEL), we need to see what effects this
926 has on the known offsets at labels. */
928 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
929 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
930 && REG_NOTES (insn) != 0))
931 set_label_offsets (insn, insn, 0);
933 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
935 /* Nonzero means don't use a reload reg that overlaps
936 the place where a function value can be returned. */
937 rtx avoid_return_reg = 0;
939 rtx old_body = PATTERN (insn);
940 int old_code = INSN_CODE (insn);
941 rtx old_notes = REG_NOTES (insn);
942 int did_elimination = 0;
944 /* To compute the number of reload registers of each class
945 needed for an insn, we must simulate what choose_reload_regs
946 can do. We do this by splitting an insn into an "input" and
947 an "output" part. RELOAD_OTHER reloads are used in both.
948 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
949 which must be live over the entire input section of reloads,
950 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
951 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
954 The registers needed for output are RELOAD_OTHER and
955 RELOAD_FOR_OUTPUT, which are live for the entire output
956 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
957 reloads for each operand.
959 The total number of registers needed is the maximum of the
960 inputs and outputs. */
964 /* [0] is normal, [1] is nongroup. */
965 int regs[2][N_REG_CLASSES];
966 int groups[N_REG_CLASSES];
969 /* Each `struct needs' corresponds to one RELOAD_... type. */
975 struct needs other_addr;
976 struct needs op_addr;
977 struct needs op_addr_reload;
978 struct needs in_addr[MAX_RECOG_OPERANDS];
979 struct needs out_addr[MAX_RECOG_OPERANDS];
982 /* If needed, eliminate any eliminable registers. */
984 did_elimination = eliminate_regs_in_insn (insn, 0);
986 #ifdef SMALL_REGISTER_CLASSES
987 /* Set avoid_return_reg if this is an insn
988 that might use the value of a function call. */
989 if (GET_CODE (insn) == CALL_INSN)
991 if (GET_CODE (PATTERN (insn)) == SET)
992 after_call = SET_DEST (PATTERN (insn));
993 else if (GET_CODE (PATTERN (insn)) == PARALLEL
994 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
995 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
999 else if (after_call != 0
1000 && !(GET_CODE (PATTERN (insn)) == SET
1001 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1003 if (reg_referenced_p (after_call, PATTERN (insn)))
1004 avoid_return_reg = after_call;
1007 #endif /* SMALL_REGISTER_CLASSES */
1009 /* Analyze the instruction. */
1010 find_reloads (insn, 0, spill_indirect_levels, global,
1013 /* Remember for later shortcuts which insns had any reloads or
1014 register eliminations.
1016 One might think that it would be worthwhile to mark insns
1017 that need register replacements but not reloads, but this is
1018 not safe because find_reloads may do some manipulation of
1019 the insn (such as swapping commutative operands), which would
1020 be lost when we restore the old pattern after register
1021 replacement. So the actions of find_reloads must be redone in
1022 subsequent passes or in reload_as_needed.
1024 However, it is safe to mark insns that need reloads
1025 but not register replacement. */
1027 PUT_MODE (insn, (did_elimination ? QImode
1028 : n_reloads ? HImode
1029 : GET_MODE (insn) == DImode ? DImode
1032 /* Discard any register replacements done. */
1033 if (did_elimination)
1035 obstack_free (&reload_obstack, reload_firstobj);
1036 PATTERN (insn) = old_body;
1037 INSN_CODE (insn) = old_code;
1038 REG_NOTES (insn) = old_notes;
1039 something_needs_elimination = 1;
1042 /* If this insn has no reloads, we need not do anything except
1043 in the case of a CALL_INSN when we have caller-saves and
1044 caller-save needs reloads. */
1047 && ! (GET_CODE (insn) == CALL_INSN
1048 && caller_save_spill_class != NO_REGS))
1051 something_needs_reloads = 1;
1052 bzero ((char *) &insn_needs, sizeof insn_needs);
1054 /* Count each reload once in every class
1055 containing the reload's own class. */
1057 for (i = 0; i < n_reloads; i++)
1059 register enum reg_class *p;
1060 enum reg_class class = reload_reg_class[i];
1062 enum machine_mode mode;
1064 struct needs *this_needs;
1066 /* Don't count the dummy reloads, for which one of the
1067 regs mentioned in the insn can be used for reloading.
1068 Don't count optional reloads.
1069 Don't count reloads that got combined with others. */
1070 if (reload_reg_rtx[i] != 0
1071 || reload_optional[i] != 0
1072 || (reload_out[i] == 0 && reload_in[i] == 0
1073 && ! reload_secondary_p[i]))
1076 /* Show that a reload register of this class is needed
1077 in this basic block. We do not use insn_needs and
1078 insn_groups because they are overly conservative for
1080 if (global && ! basic_block_needs[(int) class][this_block])
1082 basic_block_needs[(int) class][this_block] = 1;
1083 new_basic_block_needs = 1;
1087 mode = reload_inmode[i];
1088 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1089 mode = reload_outmode[i];
1090 size = CLASS_MAX_NREGS (class, mode);
1092 /* If this class doesn't want a group, determine if we have
1093 a nongroup need or a regular need. We have a nongroup
1094 need if this reload conflicts with a group reload whose
1095 class intersects with this reload's class. */
1099 for (j = 0; j < n_reloads; j++)
1100 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1101 (GET_MODE_SIZE (reload_outmode[j])
1102 > GET_MODE_SIZE (reload_inmode[j]))
1106 && (!reload_optional[j])
1107 && (reload_in[j] != 0 || reload_out[j] != 0
1108 || reload_secondary_p[j])
1109 && reloads_conflict (i, j)
1110 && reg_classes_intersect_p (class,
1111 reload_reg_class[j]))
1117 /* Decide which time-of-use to count this reload for. */
1118 switch (reload_when_needed[i])
1121 this_needs = &insn_needs.other;
1123 case RELOAD_FOR_INPUT:
1124 this_needs = &insn_needs.input;
1126 case RELOAD_FOR_OUTPUT:
1127 this_needs = &insn_needs.output;
1129 case RELOAD_FOR_INSN:
1130 this_needs = &insn_needs.insn;
1132 case RELOAD_FOR_OTHER_ADDRESS:
1133 this_needs = &insn_needs.other_addr;
1135 case RELOAD_FOR_INPUT_ADDRESS:
1136 this_needs = &insn_needs.in_addr[reload_opnum[i]];
1138 case RELOAD_FOR_OUTPUT_ADDRESS:
1139 this_needs = &insn_needs.out_addr[reload_opnum[i]];
1141 case RELOAD_FOR_OPERAND_ADDRESS:
1142 this_needs = &insn_needs.op_addr;
1144 case RELOAD_FOR_OPADDR_ADDR:
1145 this_needs = &insn_needs.op_addr_reload;
1151 enum machine_mode other_mode, allocate_mode;
1153 /* Count number of groups needed separately from
1154 number of individual regs needed. */
1155 this_needs->groups[(int) class]++;
1156 p = reg_class_superclasses[(int) class];
1157 while (*p != LIM_REG_CLASSES)
1158 this_needs->groups[(int) *p++]++;
1160 /* Record size and mode of a group of this class. */
1161 /* If more than one size group is needed,
1162 make all groups the largest needed size. */
1163 if (group_size[(int) class] < size)
1165 other_mode = group_mode[(int) class];
1166 allocate_mode = mode;
1168 group_size[(int) class] = size;
1169 group_mode[(int) class] = mode;
1174 allocate_mode = group_mode[(int) class];
1177 /* Crash if two dissimilar machine modes both need
1178 groups of consecutive regs of the same class. */
1180 if (other_mode != VOIDmode && other_mode != allocate_mode
1181 && ! modes_equiv_for_class_p (allocate_mode,
1183 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1188 this_needs->regs[nongroup_need][(int) class] += 1;
1189 p = reg_class_superclasses[(int) class];
1190 while (*p != LIM_REG_CLASSES)
1191 this_needs->regs[nongroup_need][(int) *p++] += 1;
1197 /* All reloads have been counted for this insn;
1198 now merge the various times of use.
1199 This sets insn_needs, etc., to the maximum total number
1200 of registers needed at any point in this insn. */
1202 for (i = 0; i < N_REG_CLASSES; i++)
1204 int in_max, out_max;
1206 /* Compute normal and nongroup needs. */
1207 for (j = 0; j <= 1; j++)
1209 for (in_max = 0, out_max = 0, k = 0;
1210 k < reload_n_operands; k++)
1213 = MAX (in_max, insn_needs.in_addr[k].regs[j][i]);
1215 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]);
1218 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1219 and operand addresses but not things used to reload
1220 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1221 don't conflict with things needed to reload inputs or
1224 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i],
1225 insn_needs.op_addr_reload.regs[j][i]),
1228 out_max = MAX (out_max, insn_needs.insn.regs[j][i]);
1230 insn_needs.input.regs[j][i]
1231 = MAX (insn_needs.input.regs[j][i]
1232 + insn_needs.op_addr.regs[j][i]
1233 + insn_needs.insn.regs[j][i],
1234 in_max + insn_needs.input.regs[j][i]);
1236 insn_needs.output.regs[j][i] += out_max;
1237 insn_needs.other.regs[j][i]
1238 += MAX (MAX (insn_needs.input.regs[j][i],
1239 insn_needs.output.regs[j][i]),
1240 insn_needs.other_addr.regs[j][i]);
1244 /* Now compute group needs. */
1245 for (in_max = 0, out_max = 0, j = 0;
1246 j < reload_n_operands; j++)
1248 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]);
1250 = MAX (out_max, insn_needs.out_addr[j].groups[i]);
1253 in_max = MAX (MAX (insn_needs.op_addr.groups[i],
1254 insn_needs.op_addr_reload.groups[i]),
1256 out_max = MAX (out_max, insn_needs.insn.groups[i]);
1258 insn_needs.input.groups[i]
1259 = MAX (insn_needs.input.groups[i]
1260 + insn_needs.op_addr.groups[i]
1261 + insn_needs.insn.groups[i],
1262 in_max + insn_needs.input.groups[i]);
1264 insn_needs.output.groups[i] += out_max;
1265 insn_needs.other.groups[i]
1266 += MAX (MAX (insn_needs.input.groups[i],
1267 insn_needs.output.groups[i]),
1268 insn_needs.other_addr.groups[i]);
1271 /* If this is a CALL_INSN and caller-saves will need
1272 a spill register, act as if the spill register is
1273 needed for this insn. However, the spill register
1274 can be used by any reload of this insn, so we only
1275 need do something if no need for that class has
1278 The assumption that every CALL_INSN will trigger a
1279 caller-save is highly conservative, however, the number
1280 of cases where caller-saves will need a spill register but
1281 a block containing a CALL_INSN won't need a spill register
1282 of that class should be quite rare.
1284 If a group is needed, the size and mode of the group will
1285 have been set up at the beginning of this loop. */
1287 if (GET_CODE (insn) == CALL_INSN
1288 && caller_save_spill_class != NO_REGS)
1290 /* See if this register would conflict with any reload
1291 that needs a group. */
1292 int nongroup_need = 0;
1293 int *caller_save_needs;
1295 for (j = 0; j < n_reloads; j++)
1296 if ((CLASS_MAX_NREGS (reload_reg_class[j],
1297 (GET_MODE_SIZE (reload_outmode[j])
1298 > GET_MODE_SIZE (reload_inmode[j]))
1302 && reg_classes_intersect_p (caller_save_spill_class,
1303 reload_reg_class[j]))
1310 = (caller_save_group_size > 1
1311 ? insn_needs.other.groups
1312 : insn_needs.other.regs[nongroup_need]);
1314 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1316 register enum reg_class *p
1317 = reg_class_superclasses[(int) caller_save_spill_class];
1319 caller_save_needs[(int) caller_save_spill_class]++;
1321 while (*p != LIM_REG_CLASSES)
1322 caller_save_needs[(int) *p++] += 1;
1325 /* Show that this basic block will need a register of
1329 && ! (basic_block_needs[(int) caller_save_spill_class]
1332 basic_block_needs[(int) caller_save_spill_class]
1334 new_basic_block_needs = 1;
1338 #ifdef SMALL_REGISTER_CLASSES
1339 /* If this insn stores the value of a function call,
1340 and that value is in a register that has been spilled,
1341 and if the insn needs a reload in a class
1342 that might use that register as the reload register,
1343 then add add an extra need in that class.
1344 This makes sure we have a register available that does
1345 not overlap the return value. */
1347 if (avoid_return_reg)
1349 int regno = REGNO (avoid_return_reg);
1351 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1353 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1355 /* First compute the "basic needs", which counts a
1356 need only in the smallest class in which it
1359 bcopy ((char *) insn_needs.other.regs[0],
1360 (char *) basic_needs, sizeof basic_needs);
1361 bcopy ((char *) insn_needs.other.groups,
1362 (char *) basic_groups, sizeof basic_groups);
1364 for (i = 0; i < N_REG_CLASSES; i++)
1368 if (basic_needs[i] >= 0)
1369 for (p = reg_class_superclasses[i];
1370 *p != LIM_REG_CLASSES; p++)
1371 basic_needs[(int) *p] -= basic_needs[i];
1373 if (basic_groups[i] >= 0)
1374 for (p = reg_class_superclasses[i];
1375 *p != LIM_REG_CLASSES; p++)
1376 basic_groups[(int) *p] -= basic_groups[i];
1379 /* Now count extra regs if there might be a conflict with
1380 the return value register. */
1382 for (r = regno; r < regno + nregs; r++)
1383 if (spill_reg_order[r] >= 0)
1384 for (i = 0; i < N_REG_CLASSES; i++)
1385 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1387 if (basic_needs[i] > 0)
1391 insn_needs.other.regs[0][i]++;
1392 p = reg_class_superclasses[i];
1393 while (*p != LIM_REG_CLASSES)
1394 insn_needs.other.regs[0][(int) *p++]++;
1396 if (basic_groups[i] > 0)
1400 insn_needs.other.groups[i]++;
1401 p = reg_class_superclasses[i];
1402 while (*p != LIM_REG_CLASSES)
1403 insn_needs.other.groups[(int) *p++]++;
1407 #endif /* SMALL_REGISTER_CLASSES */
1409 /* For each class, collect maximum need of any insn. */
1411 for (i = 0; i < N_REG_CLASSES; i++)
1413 if (max_needs[i] < insn_needs.other.regs[0][i])
1415 max_needs[i] = insn_needs.other.regs[0][i];
1416 max_needs_insn[i] = insn;
1418 if (max_groups[i] < insn_needs.other.groups[i])
1420 max_groups[i] = insn_needs.other.groups[i];
1421 max_groups_insn[i] = insn;
1423 if (max_nongroups[i] < insn_needs.other.regs[1][i])
1425 max_nongroups[i] = insn_needs.other.regs[1][i];
1426 max_nongroups_insn[i] = insn;
1430 /* Note that there is a continue statement above. */
1433 /* If we allocated any new memory locations, make another pass
1434 since it might have changed elimination offsets. */
1435 if (starting_frame_size != get_frame_size ())
1436 something_changed = 1;
1439 for (i = 0; i < N_REG_CLASSES; i++)
1441 if (max_needs[i] > 0)
1443 ";; Need %d reg%s of class %s (for insn %d).\n",
1444 max_needs[i], max_needs[i] == 1 ? "" : "s",
1445 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1446 if (max_nongroups[i] > 0)
1448 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1449 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1450 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1451 if (max_groups[i] > 0)
1453 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1454 max_groups[i], max_groups[i] == 1 ? "" : "s",
1455 mode_name[(int) group_mode[i]],
1456 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1459 /* If we have caller-saves, set up the save areas and see if caller-save
1460 will need a spill register. */
1462 if (caller_save_needed)
1464 /* Set the offsets for setup_save_areas. */
1465 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
1467 ep->previous_offset = ep->max_offset;
1469 if ( ! setup_save_areas (&something_changed)
1470 && caller_save_spill_class == NO_REGS)
1472 /* The class we will need depends on whether the machine
1473 supports the sum of two registers for an address; see
1474 find_address_reloads for details. */
1476 caller_save_spill_class
1477 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1478 caller_save_group_size
1479 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1480 something_changed = 1;
1484 /* See if anything that happened changes which eliminations are valid.
1485 For example, on the Sparc, whether or not the frame pointer can
1486 be eliminated can depend on what registers have been used. We need
1487 not check some conditions again (such as flag_omit_frame_pointer)
1488 since they can't have changed. */
1490 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1491 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1492 #ifdef ELIMINABLE_REGS
1493 || ! CAN_ELIMINATE (ep->from, ep->to)
1496 ep->can_eliminate = 0;
1498 /* Look for the case where we have discovered that we can't replace
1499 register A with register B and that means that we will now be
1500 trying to replace register A with register C. This means we can
1501 no longer replace register C with register B and we need to disable
1502 such an elimination, if it exists. This occurs often with A == ap,
1503 B == sp, and C == fp. */
1505 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1507 struct elim_table *op;
1508 register int new_to = -1;
1510 if (! ep->can_eliminate && ep->can_eliminate_previous)
1512 /* Find the current elimination for ep->from, if there is a
1514 for (op = reg_eliminate;
1515 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1516 if (op->from == ep->from && op->can_eliminate)
1522 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1524 for (op = reg_eliminate;
1525 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1526 if (op->from == new_to && op->to == ep->to)
1527 op->can_eliminate = 0;
1531 /* See if any registers that we thought we could eliminate the previous
1532 time are no longer eliminable. If so, something has changed and we
1533 must spill the register. Also, recompute the number of eliminable
1534 registers and see if the frame pointer is needed; it is if there is
1535 no elimination of the frame pointer that we can perform. */
1537 frame_pointer_needed = 1;
1538 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1540 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
1541 && ep->to != HARD_FRAME_POINTER_REGNUM)
1542 frame_pointer_needed = 0;
1544 if (! ep->can_eliminate && ep->can_eliminate_previous)
1546 ep->can_eliminate_previous = 0;
1547 spill_hard_reg (ep->from, global, dumpfile, 1);
1548 something_changed = 1;
1553 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1554 /* If we didn't need a frame pointer last time, but we do now, spill
1555 the hard frame pointer. */
1556 if (frame_pointer_needed && ! previous_frame_pointer_needed)
1558 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1);
1559 something_changed = 1;
1563 /* If all needs are met, we win. */
1565 for (i = 0; i < N_REG_CLASSES; i++)
1566 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1568 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1571 /* Not all needs are met; must spill some hard regs. */
1573 /* Put all registers spilled so far back in potential_reload_regs, but
1574 put them at the front, since we've already spilled most of the
1575 pseudos in them (we might have left some pseudos unspilled if they
1576 were in a block that didn't need any spill registers of a conflicting
1577 class. We used to try to mark off the need for those registers,
1578 but doing so properly is very complex and reallocating them is the
1579 simpler approach. First, "pack" potential_reload_regs by pushing
1580 any nonnegative entries towards the end. That will leave room
1581 for the registers we already spilled.
1583 Also, undo the marking of the spill registers from the last time
1584 around in FORBIDDEN_REGS since we will be probably be allocating
1587 ??? It is theoretically possible that we might end up not using one
1588 of our previously-spilled registers in this allocation, even though
1589 they are at the head of the list. It's not clear what to do about
1590 this, but it was no better before, when we marked off the needs met
1591 by the previously-spilled registers. With the current code, globals
1592 can be allocated into these registers, but locals cannot. */
1596 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1597 if (potential_reload_regs[i] != -1)
1598 potential_reload_regs[j--] = potential_reload_regs[i];
1600 for (i = 0; i < n_spills; i++)
1602 potential_reload_regs[i] = spill_regs[i];
1603 spill_reg_order[spill_regs[i]] = -1;
1604 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1610 /* Now find more reload regs to satisfy the remaining need
1611 Do it by ascending class number, since otherwise a reg
1612 might be spilled for a big class and might fail to count
1613 for a smaller class even though it belongs to that class.
1615 Count spilled regs in `spills', and add entries to
1616 `spill_regs' and `spill_reg_order'.
1618 ??? Note there is a problem here.
1619 When there is a need for a group in a high-numbered class,
1620 and also need for non-group regs that come from a lower class,
1621 the non-group regs are chosen first. If there aren't many regs,
1622 they might leave no room for a group.
1624 This was happening on the 386. To fix it, we added the code
1625 that calls possible_group_p, so that the lower class won't
1626 break up the last possible group.
1628 Really fixing the problem would require changes above
1629 in counting the regs already spilled, and in choose_reload_regs.
1630 It might be hard to avoid introducing bugs there. */
1632 CLEAR_HARD_REG_SET (counted_for_groups);
1633 CLEAR_HARD_REG_SET (counted_for_nongroups);
1635 for (class = 0; class < N_REG_CLASSES; class++)
1637 /* First get the groups of registers.
1638 If we got single registers first, we might fragment
1640 while (max_groups[class] > 0)
1642 /* If any single spilled regs happen to form groups,
1643 count them now. Maybe we don't really need
1644 to spill another group. */
1645 count_possible_groups (group_size, group_mode, max_groups,
1648 if (max_groups[class] <= 0)
1651 /* Groups of size 2 (the only groups used on most machines)
1652 are treated specially. */
1653 if (group_size[class] == 2)
1655 /* First, look for a register that will complete a group. */
1656 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1660 j = potential_reload_regs[i];
1661 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1663 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1664 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1665 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1666 && HARD_REGNO_MODE_OK (other, group_mode[class])
1667 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1669 /* We don't want one part of another group.
1670 We could get "two groups" that overlap! */
1671 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1673 (j < FIRST_PSEUDO_REGISTER - 1
1674 && (other = j + 1, spill_reg_order[other] >= 0)
1675 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1676 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1677 && HARD_REGNO_MODE_OK (j, group_mode[class])
1678 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1680 && ! TEST_HARD_REG_BIT (counted_for_groups,
1683 register enum reg_class *p;
1685 /* We have found one that will complete a group,
1686 so count off one group as provided. */
1687 max_groups[class]--;
1688 p = reg_class_superclasses[class];
1689 while (*p != LIM_REG_CLASSES)
1691 if (group_size [(int) *p] <= group_size [class])
1692 max_groups[(int) *p]--;
1696 /* Indicate both these regs are part of a group. */
1697 SET_HARD_REG_BIT (counted_for_groups, j);
1698 SET_HARD_REG_BIT (counted_for_groups, other);
1702 /* We can't complete a group, so start one. */
1703 #ifdef SMALL_REGISTER_CLASSES
1704 /* Look for a pair neither of which is explicitly used. */
1705 if (i == FIRST_PSEUDO_REGISTER)
1706 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1709 j = potential_reload_regs[i];
1710 /* Verify that J+1 is a potential reload reg. */
1711 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1712 if (potential_reload_regs[k] == j + 1)
1714 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1715 && k < FIRST_PSEUDO_REGISTER
1716 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1717 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1718 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1719 && HARD_REGNO_MODE_OK (j, group_mode[class])
1720 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1722 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)
1723 /* Reject J at this stage
1724 if J+1 was explicitly used. */
1725 && ! regs_explicitly_used[j + 1])
1729 /* Now try any group at all
1730 whose registers are not in bad_spill_regs. */
1731 if (i == FIRST_PSEUDO_REGISTER)
1732 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1735 j = potential_reload_regs[i];
1736 /* Verify that J+1 is a potential reload reg. */
1737 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1738 if (potential_reload_regs[k] == j + 1)
1740 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1741 && k < FIRST_PSEUDO_REGISTER
1742 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1743 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1744 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1745 && HARD_REGNO_MODE_OK (j, group_mode[class])
1746 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1748 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1752 /* I should be the index in potential_reload_regs
1753 of the new reload reg we have found. */
1755 if (i >= FIRST_PSEUDO_REGISTER)
1757 /* There are no groups left to spill. */
1758 spill_failure (max_groups_insn[class]);
1764 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1769 /* For groups of more than 2 registers,
1770 look for a sufficient sequence of unspilled registers,
1771 and spill them all at once. */
1772 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1776 j = potential_reload_regs[i];
1778 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1779 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1781 /* Check each reg in the sequence. */
1782 for (k = 0; k < group_size[class]; k++)
1783 if (! (spill_reg_order[j + k] < 0
1784 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1785 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1787 /* We got a full sequence, so spill them all. */
1788 if (k == group_size[class])
1790 register enum reg_class *p;
1791 for (k = 0; k < group_size[class]; k++)
1794 SET_HARD_REG_BIT (counted_for_groups, j + k);
1795 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1796 if (potential_reload_regs[idx] == j + k)
1799 |= new_spill_reg (idx, class,
1800 max_needs, NULL_PTR,
1804 /* We have found one that will complete a group,
1805 so count off one group as provided. */
1806 max_groups[class]--;
1807 p = reg_class_superclasses[class];
1808 while (*p != LIM_REG_CLASSES)
1810 if (group_size [(int) *p]
1811 <= group_size [class])
1812 max_groups[(int) *p]--;
1819 /* We couldn't find any registers for this reload.
1820 Avoid going into an infinite loop. */
1821 if (i >= FIRST_PSEUDO_REGISTER)
1823 /* There are no groups left. */
1824 spill_failure (max_groups_insn[class]);
1831 /* Now similarly satisfy all need for single registers. */
1833 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1835 /* If we spilled enough regs, but they weren't counted
1836 against the non-group need, see if we can count them now.
1837 If so, we can avoid some actual spilling. */
1838 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1839 for (i = 0; i < n_spills; i++)
1840 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1842 && !TEST_HARD_REG_BIT (counted_for_groups,
1844 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1846 && max_nongroups[class] > 0)
1848 register enum reg_class *p;
1850 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1851 max_nongroups[class]--;
1852 p = reg_class_superclasses[class];
1853 while (*p != LIM_REG_CLASSES)
1854 max_nongroups[(int) *p++]--;
1856 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1859 /* Consider the potential reload regs that aren't
1860 yet in use as reload regs, in order of preference.
1861 Find the most preferred one that's in this class. */
1863 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1864 if (potential_reload_regs[i] >= 0
1865 && TEST_HARD_REG_BIT (reg_class_contents[class],
1866 potential_reload_regs[i])
1867 /* If this reg will not be available for groups,
1868 pick one that does not foreclose possible groups.
1869 This is a kludge, and not very general,
1870 but it should be sufficient to make the 386 work,
1871 and the problem should not occur on machines with
1873 && (max_nongroups[class] == 0
1874 || possible_group_p (potential_reload_regs[i], max_groups)))
1877 /* If we couldn't get a register, try to get one even if we
1878 might foreclose possible groups. This may cause problems
1879 later, but that's better than aborting now, since it is
1880 possible that we will, in fact, be able to form the needed
1881 group even with this allocation. */
1883 if (i >= FIRST_PSEUDO_REGISTER
1884 && (asm_noperands (max_needs[class] > 0
1885 ? max_needs_insn[class]
1886 : max_nongroups_insn[class])
1888 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1889 if (potential_reload_regs[i] >= 0
1890 && TEST_HARD_REG_BIT (reg_class_contents[class],
1891 potential_reload_regs[i]))
1894 /* I should be the index in potential_reload_regs
1895 of the new reload reg we have found. */
1897 if (i >= FIRST_PSEUDO_REGISTER)
1899 /* There are no possible registers left to spill. */
1900 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1901 : max_nongroups_insn[class]);
1907 |= new_spill_reg (i, class, max_needs, max_nongroups,
1913 /* If global-alloc was run, notify it of any register eliminations we have
1916 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1917 if (ep->can_eliminate)
1918 mark_elimination (ep->from, ep->to);
1920 /* Insert code to save and restore call-clobbered hard regs
1921 around calls. Tell if what mode to use so that we will process
1922 those insns in reload_as_needed if we have to. */
1924 if (caller_save_needed)
1925 save_call_clobbered_regs (num_eliminable ? QImode
1926 : caller_save_spill_class != NO_REGS ? HImode
1929 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1930 If that insn didn't set the register (i.e., it copied the register to
1931 memory), just delete that insn instead of the equivalencing insn plus
1932 anything now dead. If we call delete_dead_insn on that insn, we may
1933 delete the insn that actually sets the register if the register die
1934 there and that is incorrect. */
1936 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1937 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1938 && GET_CODE (reg_equiv_init[i]) != NOTE)
1940 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1941 delete_dead_insn (reg_equiv_init[i]);
1944 PUT_CODE (reg_equiv_init[i], NOTE);
1945 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1946 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1950 /* Use the reload registers where necessary
1951 by generating move instructions to move the must-be-register
1952 values into or out of the reload registers. */
1954 if (something_needs_reloads || something_needs_elimination
1955 || (caller_save_needed && num_eliminable)
1956 || caller_save_spill_class != NO_REGS)
1957 reload_as_needed (first, global);
1959 /* If we were able to eliminate the frame pointer, show that it is no
1960 longer live at the start of any basic block. If it ls live by
1961 virtue of being in a pseudo, that pseudo will be marked live
1962 and hence the frame pointer will be known to be live via that
1965 if (! frame_pointer_needed)
1966 for (i = 0; i < n_basic_blocks; i++)
1967 basic_block_live_at_start[i][HARD_FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
1968 &= ~ ((REGSET_ELT_TYPE) 1 << (HARD_FRAME_POINTER_REGNUM
1969 % REGSET_ELT_BITS));
1971 /* Come here (with failure set nonzero) if we can't get enough spill regs
1972 and we decide not to abort about it. */
1975 reload_in_progress = 0;
1977 /* Now eliminate all pseudo regs by modifying them into
1978 their equivalent memory references.
1979 The REG-rtx's for the pseudos are modified in place,
1980 so all insns that used to refer to them now refer to memory.
1982 For a reg that has a reg_equiv_address, all those insns
1983 were changed by reloading so that no insns refer to it any longer;
1984 but the DECL_RTL of a variable decl may refer to it,
1985 and if so this causes the debugging info to mention the variable. */
1987 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1991 if (reg_equiv_mem[i])
1993 addr = XEXP (reg_equiv_mem[i], 0);
1994 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
1996 if (reg_equiv_address[i])
1997 addr = reg_equiv_address[i];
2000 if (reg_renumber[i] < 0)
2002 rtx reg = regno_reg_rtx[i];
2003 XEXP (reg, 0) = addr;
2004 REG_USERVAR_P (reg) = 0;
2005 MEM_IN_STRUCT_P (reg) = in_struct;
2006 PUT_CODE (reg, MEM);
2008 else if (reg_equiv_mem[i])
2009 XEXP (reg_equiv_mem[i], 0) = addr;
2013 #ifdef PRESERVE_DEATH_INFO_REGNO_P
2014 /* Make a pass over all the insns and remove death notes for things that
2015 are no longer registers or no longer die in the insn (e.g., an input
2016 and output pseudo being tied). */
2018 for (insn = first; insn; insn = NEXT_INSN (insn))
2019 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2023 for (note = REG_NOTES (insn); note; note = next)
2025 next = XEXP (note, 1);
2026 if (REG_NOTE_KIND (note) == REG_DEAD
2027 && (GET_CODE (XEXP (note, 0)) != REG
2028 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
2029 remove_note (insn, note);
2034 /* Indicate that we no longer have known memory locations or constants. */
2035 reg_equiv_constant = 0;
2036 reg_equiv_memory_loc = 0;
2039 free (scratch_list);
2042 free (scratch_block);
2045 CLEAR_HARD_REG_SET (used_spill_regs);
2046 for (i = 0; i < n_spills; i++)
2047 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
2052 /* Nonzero if, after spilling reg REGNO for non-groups,
2053 it will still be possible to find a group if we still need one. */
2056 possible_group_p (regno, max_groups)
2061 int class = (int) NO_REGS;
2063 for (i = 0; i < (int) N_REG_CLASSES; i++)
2064 if (max_groups[i] > 0)
2070 if (class == (int) NO_REGS)
2073 /* Consider each pair of consecutive registers. */
2074 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2076 /* Ignore pairs that include reg REGNO. */
2077 if (i == regno || i + 1 == regno)
2080 /* Ignore pairs that are outside the class that needs the group.
2081 ??? Here we fail to handle the case where two different classes
2082 independently need groups. But this never happens with our
2083 current machine descriptions. */
2084 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2085 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2088 /* A pair of consecutive regs we can still spill does the trick. */
2089 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2090 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2091 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2094 /* A pair of one already spilled and one we can spill does it
2095 provided the one already spilled is not otherwise reserved. */
2096 if (spill_reg_order[i] < 0
2097 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2098 && spill_reg_order[i + 1] >= 0
2099 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2100 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2102 if (spill_reg_order[i + 1] < 0
2103 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2104 && spill_reg_order[i] >= 0
2105 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2106 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2113 /* Count any groups of CLASS that can be formed from the registers recently
2117 count_possible_groups (group_size, group_mode, max_groups, class)
2119 enum machine_mode *group_mode;
2126 /* Now find all consecutive groups of spilled registers
2127 and mark each group off against the need for such groups.
2128 But don't count them against ordinary need, yet. */
2130 if (group_size[class] == 0)
2133 CLEAR_HARD_REG_SET (new);
2135 /* Make a mask of all the regs that are spill regs in class I. */
2136 for (i = 0; i < n_spills; i++)
2137 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
2138 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i])
2139 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
2140 SET_HARD_REG_BIT (new, spill_regs[i]);
2142 /* Find each consecutive group of them. */
2143 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++)
2144 if (TEST_HARD_REG_BIT (new, i)
2145 && i + group_size[class] <= FIRST_PSEUDO_REGISTER
2146 && HARD_REGNO_MODE_OK (i, group_mode[class]))
2148 for (j = 1; j < group_size[class]; j++)
2149 if (! TEST_HARD_REG_BIT (new, i + j))
2152 if (j == group_size[class])
2154 /* We found a group. Mark it off against this class's need for
2155 groups, and against each superclass too. */
2156 register enum reg_class *p;
2158 max_groups[class]--;
2159 p = reg_class_superclasses[class];
2160 while (*p != LIM_REG_CLASSES)
2162 if (group_size [(int) *p] <= group_size [class])
2163 max_groups[(int) *p]--;
2167 /* Don't count these registers again. */
2168 for (j = 0; j < group_size[class]; j++)
2169 SET_HARD_REG_BIT (counted_for_groups, i + j);
2172 /* Skip to the last reg in this group. When i is incremented above,
2173 it will then point to the first reg of the next possible group. */
2178 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2179 another mode that needs to be reloaded for the same register class CLASS.
2180 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2181 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2183 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2184 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2185 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2186 causes unnecessary failures on machines requiring alignment of register
2187 groups when the two modes are different sizes, because the larger mode has
2188 more strict alignment rules than the smaller mode. */
2191 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2192 enum machine_mode allocate_mode, other_mode;
2193 enum reg_class class;
2196 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2198 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2199 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2200 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2206 /* Handle the failure to find a register to spill.
2207 INSN should be one of the insns which needed this particular spill reg. */
2210 spill_failure (insn)
2213 if (asm_noperands (PATTERN (insn)) >= 0)
2214 error_for_asm (insn, "`asm' needs too many reloads");
2216 fatal_insn ("Unable to find a register to spill.", insn);
2219 /* Add a new register to the tables of available spill-registers
2220 (as well as spilling all pseudos allocated to the register).
2221 I is the index of this register in potential_reload_regs.
2222 CLASS is the regclass whose need is being satisfied.
2223 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2224 so that this register can count off against them.
2225 MAX_NONGROUPS is 0 if this register is part of a group.
2226 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2229 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2237 register enum reg_class *p;
2239 int regno = potential_reload_regs[i];
2241 if (i >= FIRST_PSEUDO_REGISTER)
2242 abort (); /* Caller failed to find any register. */
2244 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2245 fatal ("fixed or forbidden register was spilled.\n\
2246 This may be due to a compiler bug or to impossible asm\n\
2247 statements or clauses.");
2249 /* Make reg REGNO an additional reload reg. */
2251 potential_reload_regs[i] = -1;
2252 spill_regs[n_spills] = regno;
2253 spill_reg_order[regno] = n_spills;
2255 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2257 /* Clear off the needs we just satisfied. */
2260 p = reg_class_superclasses[class];
2261 while (*p != LIM_REG_CLASSES)
2262 max_needs[(int) *p++]--;
2264 if (max_nongroups && max_nongroups[class] > 0)
2266 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2267 max_nongroups[class]--;
2268 p = reg_class_superclasses[class];
2269 while (*p != LIM_REG_CLASSES)
2270 max_nongroups[(int) *p++]--;
2273 /* Spill every pseudo reg that was allocated to this reg
2274 or to something that overlaps this reg. */
2276 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2278 /* If there are some registers still to eliminate and this register
2279 wasn't ever used before, additional stack space may have to be
2280 allocated to store this register. Thus, we may have changed the offset
2281 between the stack and frame pointers, so mark that something has changed.
2282 (If new pseudos were spilled, thus requiring more space, VAL would have
2283 been set non-zero by the call to spill_hard_reg above since additional
2284 reloads may be needed in that case.
2286 One might think that we need only set VAL to 1 if this is a call-used
2287 register. However, the set of registers that must be saved by the
2288 prologue is not identical to the call-used set. For example, the
2289 register used by the call insn for the return PC is a call-used register,
2290 but must be saved by the prologue. */
2291 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2294 regs_ever_live[spill_regs[n_spills]] = 1;
2300 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2301 data that is dead in INSN. */
2304 delete_dead_insn (insn)
2307 rtx prev = prev_real_insn (insn);
2310 /* If the previous insn sets a register that dies in our insn, delete it
2312 if (prev && GET_CODE (PATTERN (prev)) == SET
2313 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2314 && reg_mentioned_p (prev_dest, PATTERN (insn))
2315 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2316 delete_dead_insn (prev);
2318 PUT_CODE (insn, NOTE);
2319 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2320 NOTE_SOURCE_FILE (insn) = 0;
2323 /* Modify the home of pseudo-reg I.
2324 The new home is present in reg_renumber[I].
2326 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2327 or it may be -1, meaning there is none or it is not relevant.
2328 This is used so that all pseudos spilled from a given hard reg
2329 can share one stack slot. */
2332 alter_reg (i, from_reg)
2336 /* When outputting an inline function, this can happen
2337 for a reg that isn't actually used. */
2338 if (regno_reg_rtx[i] == 0)
2341 /* If the reg got changed to a MEM at rtl-generation time,
2343 if (GET_CODE (regno_reg_rtx[i]) != REG)
2346 /* Modify the reg-rtx to contain the new hard reg
2347 number or else to contain its pseudo reg number. */
2348 REGNO (regno_reg_rtx[i])
2349 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2351 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2352 allocate a stack slot for it. */
2354 if (reg_renumber[i] < 0
2355 && reg_n_refs[i] > 0
2356 && reg_equiv_constant[i] == 0
2357 && reg_equiv_memory_loc[i] == 0)
2360 int inherent_size = PSEUDO_REGNO_BYTES (i);
2361 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2364 /* Each pseudo reg has an inherent size which comes from its own mode,
2365 and a total size which provides room for paradoxical subregs
2366 which refer to the pseudo reg in wider modes.
2368 We can use a slot already allocated if it provides both
2369 enough inherent space and enough total space.
2370 Otherwise, we allocate a new slot, making sure that it has no less
2371 inherent space, and no less total space, then the previous slot. */
2374 /* No known place to spill from => no slot to reuse. */
2375 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2376 if (BYTES_BIG_ENDIAN)
2377 /* Cancel the big-endian correction done in assign_stack_local.
2378 Get the address of the beginning of the slot.
2379 This is so we can do a big-endian correction unconditionally
2381 adjust = inherent_size - total_size;
2383 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2385 /* Reuse a stack slot if possible. */
2386 else if (spill_stack_slot[from_reg] != 0
2387 && spill_stack_slot_width[from_reg] >= total_size
2388 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2390 x = spill_stack_slot[from_reg];
2391 /* Allocate a bigger slot. */
2394 /* Compute maximum size needed, both for inherent size
2395 and for total size. */
2396 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2398 if (spill_stack_slot[from_reg])
2400 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2402 mode = GET_MODE (spill_stack_slot[from_reg]);
2403 if (spill_stack_slot_width[from_reg] > total_size)
2404 total_size = spill_stack_slot_width[from_reg];
2406 /* Make a slot with that size. */
2407 x = assign_stack_local (mode, total_size, -1);
2409 if (BYTES_BIG_ENDIAN)
2411 /* Cancel the big-endian correction done in assign_stack_local.
2412 Get the address of the beginning of the slot.
2413 This is so we can do a big-endian correction unconditionally
2415 adjust = GET_MODE_SIZE (mode) - total_size;
2417 stack_slot = gen_rtx (MEM, mode_for_size (total_size
2420 plus_constant (XEXP (x, 0), adjust));
2422 spill_stack_slot[from_reg] = stack_slot;
2423 spill_stack_slot_width[from_reg] = total_size;
2426 /* On a big endian machine, the "address" of the slot
2427 is the address of the low part that fits its inherent mode. */
2428 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2429 adjust += (total_size - inherent_size);
2431 /* If we have any adjustment to make, or if the stack slot is the
2432 wrong mode, make a new stack slot. */
2433 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2435 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2436 plus_constant (XEXP (x, 0), adjust));
2437 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2440 /* Save the stack slot for later. */
2441 reg_equiv_memory_loc[i] = x;
2445 /* Mark the slots in regs_ever_live for the hard regs
2446 used by pseudo-reg number REGNO. */
2449 mark_home_live (regno)
2452 register int i, lim;
2453 i = reg_renumber[regno];
2456 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2458 regs_ever_live[i++] = 1;
2461 /* Mark the registers used in SCRATCH as being live. */
2464 mark_scratch_live (scratch)
2468 int regno = REGNO (scratch);
2469 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2471 for (i = regno; i < lim; i++)
2472 regs_ever_live[i] = 1;
2475 /* This function handles the tracking of elimination offsets around branches.
2477 X is a piece of RTL being scanned.
2479 INSN is the insn that it came from, if any.
2481 INITIAL_P is non-zero if we are to set the offset to be the initial
2482 offset and zero if we are setting the offset of the label to be the
2486 set_label_offsets (x, insn, initial_p)
2491 enum rtx_code code = GET_CODE (x);
2494 struct elim_table *p;
2499 if (LABEL_REF_NONLOCAL_P (x))
2504 /* ... fall through ... */
2507 /* If we know nothing about this label, set the desired offsets. Note
2508 that this sets the offset at a label to be the offset before a label
2509 if we don't know anything about the label. This is not correct for
2510 the label after a BARRIER, but is the best guess we can make. If
2511 we guessed wrong, we will suppress an elimination that might have
2512 been possible had we been able to guess correctly. */
2514 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2516 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2517 offsets_at[CODE_LABEL_NUMBER (x)][i]
2518 = (initial_p ? reg_eliminate[i].initial_offset
2519 : reg_eliminate[i].offset);
2520 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2523 /* Otherwise, if this is the definition of a label and it is
2524 preceded by a BARRIER, set our offsets to the known offset of
2528 && (tem = prev_nonnote_insn (insn)) != 0
2529 && GET_CODE (tem) == BARRIER)
2531 num_not_at_initial_offset = 0;
2532 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2534 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2535 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2536 if (reg_eliminate[i].can_eliminate
2537 && (reg_eliminate[i].offset
2538 != reg_eliminate[i].initial_offset))
2539 num_not_at_initial_offset++;
2544 /* If neither of the above cases is true, compare each offset
2545 with those previously recorded and suppress any eliminations
2546 where the offsets disagree. */
2548 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2549 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2550 != (initial_p ? reg_eliminate[i].initial_offset
2551 : reg_eliminate[i].offset))
2552 reg_eliminate[i].can_eliminate = 0;
2557 set_label_offsets (PATTERN (insn), insn, initial_p);
2559 /* ... fall through ... */
2563 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2564 and hence must have all eliminations at their initial offsets. */
2565 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2566 if (REG_NOTE_KIND (tem) == REG_LABEL)
2567 set_label_offsets (XEXP (tem, 0), insn, 1);
2572 /* Each of the labels in the address vector must be at their initial
2573 offsets. We want the first first for ADDR_VEC and the second
2574 field for ADDR_DIFF_VEC. */
2576 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2577 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2582 /* We only care about setting PC. If the source is not RETURN,
2583 IF_THEN_ELSE, or a label, disable any eliminations not at
2584 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2585 isn't one of those possibilities. For branches to a label,
2586 call ourselves recursively.
2588 Note that this can disable elimination unnecessarily when we have
2589 a non-local goto since it will look like a non-constant jump to
2590 someplace in the current function. This isn't a significant
2591 problem since such jumps will normally be when all elimination
2592 pairs are back to their initial offsets. */
2594 if (SET_DEST (x) != pc_rtx)
2597 switch (GET_CODE (SET_SRC (x)))
2604 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2608 tem = XEXP (SET_SRC (x), 1);
2609 if (GET_CODE (tem) == LABEL_REF)
2610 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2611 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2614 tem = XEXP (SET_SRC (x), 2);
2615 if (GET_CODE (tem) == LABEL_REF)
2616 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2617 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2622 /* If we reach here, all eliminations must be at their initial
2623 offset because we are doing a jump to a variable address. */
2624 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2625 if (p->offset != p->initial_offset)
2626 p->can_eliminate = 0;
2630 /* Used for communication between the next two function to properly share
2631 the vector for an ASM_OPERANDS. */
2633 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2635 /* Scan X and replace any eliminable registers (such as fp) with a
2636 replacement (such as sp), plus an offset.
2638 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2639 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2640 MEM, we are allowed to replace a sum of a register and the constant zero
2641 with the register, which we cannot do outside a MEM. In addition, we need
2642 to record the fact that a register is referenced outside a MEM.
2644 If INSN is an insn, it is the insn containing X. If we replace a REG
2645 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2646 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2647 that the REG is being modified.
2649 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2650 That's used when we eliminate in expressions stored in notes.
2651 This means, do not set ref_outside_mem even if the reference
2654 If we see a modification to a register we know about, take the
2655 appropriate action (see case SET, below).
2657 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2658 replacements done assuming all offsets are at their initial values. If
2659 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2660 encounter, return the actual location so that find_reloads will do
2661 the proper thing. */
2664 eliminate_regs (x, mem_mode, insn)
2666 enum machine_mode mem_mode;
2669 enum rtx_code code = GET_CODE (x);
2670 struct elim_table *ep;
2695 /* First handle the case where we encounter a bare register that
2696 is eliminable. Replace it with a PLUS. */
2697 if (regno < FIRST_PSEUDO_REGISTER)
2699 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2701 if (ep->from_rtx == x && ep->can_eliminate)
2704 /* Refs inside notes don't count for this purpose. */
2705 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2706 || GET_CODE (insn) == INSN_LIST)))
2707 ep->ref_outside_mem = 1;
2708 return plus_constant (ep->to_rtx, ep->previous_offset);
2712 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2713 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2715 /* In this case, find_reloads would attempt to either use an
2716 incorrect address (if something is not at its initial offset)
2717 or substitute an replaced address into an insn (which loses
2718 if the offset is changed by some later action). So we simply
2719 return the replaced stack slot (assuming it is changed by
2720 elimination) and ignore the fact that this is actually a
2721 reference to the pseudo. Ensure we make a copy of the
2722 address in case it is shared. */
2723 new = eliminate_regs (reg_equiv_memory_loc[regno],
2725 if (new != reg_equiv_memory_loc[regno])
2727 cannot_omit_stores[regno] = 1;
2728 return copy_rtx (new);
2734 /* If this is the sum of an eliminable register and a constant, rework
2736 if (GET_CODE (XEXP (x, 0)) == REG
2737 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2738 && CONSTANT_P (XEXP (x, 1)))
2740 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2742 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2745 /* Refs inside notes don't count for this purpose. */
2746 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2747 || GET_CODE (insn) == INSN_LIST)))
2748 ep->ref_outside_mem = 1;
2750 /* The only time we want to replace a PLUS with a REG (this
2751 occurs when the constant operand of the PLUS is the negative
2752 of the offset) is when we are inside a MEM. We won't want
2753 to do so at other times because that would change the
2754 structure of the insn in a way that reload can't handle.
2755 We special-case the commonest situation in
2756 eliminate_regs_in_insn, so just replace a PLUS with a
2757 PLUS here, unless inside a MEM. */
2758 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2759 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2762 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2763 plus_constant (XEXP (x, 1),
2764 ep->previous_offset));
2767 /* If the register is not eliminable, we are done since the other
2768 operand is a constant. */
2772 /* If this is part of an address, we want to bring any constant to the
2773 outermost PLUS. We will do this by doing register replacement in
2774 our operands and seeing if a constant shows up in one of them.
2776 We assume here this is part of an address (or a "load address" insn)
2777 since an eliminable register is not likely to appear in any other
2780 If we have (plus (eliminable) (reg)), we want to produce
2781 (plus (plus (replacement) (reg) (const))). If this was part of a
2782 normal add insn, (plus (replacement) (reg)) will be pushed as a
2783 reload. This is the desired action. */
2786 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2787 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2789 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2791 /* If one side is a PLUS and the other side is a pseudo that
2792 didn't get a hard register but has a reg_equiv_constant,
2793 we must replace the constant here since it may no longer
2794 be in the position of any operand. */
2795 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2796 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2797 && reg_renumber[REGNO (new1)] < 0
2798 && reg_equiv_constant != 0
2799 && reg_equiv_constant[REGNO (new1)] != 0)
2800 new1 = reg_equiv_constant[REGNO (new1)];
2801 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2802 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2803 && reg_renumber[REGNO (new0)] < 0
2804 && reg_equiv_constant[REGNO (new0)] != 0)
2805 new0 = reg_equiv_constant[REGNO (new0)];
2807 new = form_sum (new0, new1);
2809 /* As above, if we are not inside a MEM we do not want to
2810 turn a PLUS into something else. We might try to do so here
2811 for an addition of 0 if we aren't optimizing. */
2812 if (! mem_mode && GET_CODE (new) != PLUS)
2813 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2821 /* If this is the product of an eliminable register and a
2822 constant, apply the distribute law and move the constant out
2823 so that we have (plus (mult ..) ..). This is needed in order
2824 to keep load-address insns valid. This case is pathological.
2825 We ignore the possibility of overflow here. */
2826 if (GET_CODE (XEXP (x, 0)) == REG
2827 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2828 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2829 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2831 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2834 /* Refs inside notes don't count for this purpose. */
2835 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2836 || GET_CODE (insn) == INSN_LIST)))
2837 ep->ref_outside_mem = 1;
2840 plus_constant (gen_rtx (MULT, Pmode, ep->to_rtx, XEXP (x, 1)),
2841 ep->previous_offset * INTVAL (XEXP (x, 1)));
2844 /* ... fall through ... */
2849 case DIV: case UDIV:
2850 case MOD: case UMOD:
2851 case AND: case IOR: case XOR:
2852 case ROTATERT: case ROTATE:
2853 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2855 case GE: case GT: case GEU: case GTU:
2856 case LE: case LT: case LEU: case LTU:
2858 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2860 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2862 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2863 return gen_rtx (code, GET_MODE (x), new0, new1);
2868 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2871 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2872 if (new != XEXP (x, 0))
2873 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2876 /* ... fall through ... */
2879 /* Now do eliminations in the rest of the chain. If this was
2880 an EXPR_LIST, this might result in allocating more memory than is
2881 strictly needed, but it simplifies the code. */
2884 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2885 if (new != XEXP (x, 1))
2886 return gen_rtx (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2894 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2895 if (ep->to_rtx == XEXP (x, 0))
2897 int size = GET_MODE_SIZE (mem_mode);
2899 /* If more bytes than MEM_MODE are pushed, account for them. */
2900 #ifdef PUSH_ROUNDING
2901 if (ep->to_rtx == stack_pointer_rtx)
2902 size = PUSH_ROUNDING (size);
2904 if (code == PRE_DEC || code == POST_DEC)
2910 /* Fall through to generic unary operation case. */
2911 case STRICT_LOW_PART:
2913 case SIGN_EXTEND: case ZERO_EXTEND:
2914 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2915 case FLOAT: case FIX:
2916 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2920 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2921 if (new != XEXP (x, 0))
2922 return gen_rtx (code, GET_MODE (x), new);
2926 /* Similar to above processing, but preserve SUBREG_WORD.
2927 Convert (subreg (mem)) to (mem) if not paradoxical.
2928 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2929 pseudo didn't get a hard reg, we must replace this with the
2930 eliminated version of the memory location because push_reloads
2931 may do the replacement in certain circumstances. */
2932 if (GET_CODE (SUBREG_REG (x)) == REG
2933 && (GET_MODE_SIZE (GET_MODE (x))
2934 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2935 && reg_equiv_memory_loc != 0
2936 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2938 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2941 /* If we didn't change anything, we must retain the pseudo. */
2942 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2943 new = SUBREG_REG (x);
2946 /* Otherwise, ensure NEW isn't shared in case we have to reload
2948 new = copy_rtx (new);
2950 /* In this case, we must show that the pseudo is used in this
2951 insn so that delete_output_reload will do the right thing. */
2952 if (insn != 0 && GET_CODE (insn) != EXPR_LIST
2953 && GET_CODE (insn) != INSN_LIST)
2954 emit_insn_before (gen_rtx (USE, VOIDmode, SUBREG_REG (x)),
2959 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2961 if (new != XEXP (x, 0))
2963 if (GET_CODE (new) == MEM
2964 && (GET_MODE_SIZE (GET_MODE (x))
2965 <= GET_MODE_SIZE (GET_MODE (new)))
2966 #ifdef LOAD_EXTEND_OP
2967 /* On these machines we will be reloading what is
2968 inside the SUBREG if it originally was a pseudo and
2969 the inner and outer modes are both a word or
2970 smaller. So leave the SUBREG then. */
2971 && ! (GET_CODE (SUBREG_REG (x)) == REG
2972 && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD
2973 && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD
2974 && (GET_MODE_SIZE (GET_MODE (x))
2975 > GET_MODE_SIZE (GET_MODE (new)))
2976 && INTEGRAL_MODE_P (GET_MODE (new))
2977 && LOAD_EXTEND_OP (GET_MODE (new)) != NIL)
2981 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2982 enum machine_mode mode = GET_MODE (x);
2984 if (BYTES_BIG_ENDIAN)
2985 offset += (MIN (UNITS_PER_WORD,
2986 GET_MODE_SIZE (GET_MODE (new)))
2987 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2989 PUT_MODE (new, mode);
2990 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2994 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
3000 /* If using a register that is the source of an eliminate we still
3001 think can be performed, note it cannot be performed since we don't
3002 know how this register is used. */
3003 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3004 if (ep->from_rtx == XEXP (x, 0))
3005 ep->can_eliminate = 0;
3007 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3008 if (new != XEXP (x, 0))
3009 return gen_rtx (code, GET_MODE (x), new);
3013 /* If clobbering a register that is the replacement register for an
3014 elimination we still think can be performed, note that it cannot
3015 be performed. Otherwise, we need not be concerned about it. */
3016 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3017 if (ep->to_rtx == XEXP (x, 0))
3018 ep->can_eliminate = 0;
3020 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
3021 if (new != XEXP (x, 0))
3022 return gen_rtx (code, GET_MODE (x), new);
3028 /* Properly handle sharing input and constraint vectors. */
3029 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
3031 /* When we come to a new vector not seen before,
3032 scan all its elements; keep the old vector if none
3033 of them changes; otherwise, make a copy. */
3034 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
3035 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
3036 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3037 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
3040 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
3041 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
3044 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
3045 new_asm_operands_vec = old_asm_operands_vec;
3047 new_asm_operands_vec
3048 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
3051 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3052 if (new_asm_operands_vec == old_asm_operands_vec)
3055 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
3056 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
3057 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
3058 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
3059 ASM_OPERANDS_SOURCE_FILE (x),
3060 ASM_OPERANDS_SOURCE_LINE (x));
3061 new->volatil = x->volatil;
3066 /* Check for setting a register that we know about. */
3067 if (GET_CODE (SET_DEST (x)) == REG)
3069 /* See if this is setting the replacement register for an
3072 If DEST is the hard frame pointer, we do nothing because we
3073 assume that all assignments to the frame pointer are for
3074 non-local gotos and are being done at a time when they are valid
3075 and do not disturb anything else. Some machines want to
3076 eliminate a fake argument pointer (or even a fake frame pointer)
3077 with either the real frame or the stack pointer. Assignments to
3078 the hard frame pointer must not prevent this elimination. */
3080 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3082 if (ep->to_rtx == SET_DEST (x)
3083 && SET_DEST (x) != hard_frame_pointer_rtx)
3085 /* If it is being incremented, adjust the offset. Otherwise,
3086 this elimination can't be done. */
3087 rtx src = SET_SRC (x);
3089 if (GET_CODE (src) == PLUS
3090 && XEXP (src, 0) == SET_DEST (x)
3091 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3092 ep->offset -= INTVAL (XEXP (src, 1));
3094 ep->can_eliminate = 0;
3097 /* Now check to see we are assigning to a register that can be
3098 eliminated. If so, it must be as part of a PARALLEL, since we
3099 will not have been called if this is a single SET. So indicate
3100 that we can no longer eliminate this reg. */
3101 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3103 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
3104 ep->can_eliminate = 0;
3107 /* Now avoid the loop below in this common case. */
3109 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
3110 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
3112 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3113 write a CLOBBER insn. */
3114 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3115 && insn != 0 && GET_CODE (insn) != EXPR_LIST
3116 && GET_CODE (insn) != INSN_LIST)
3117 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
3119 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3120 return gen_rtx (SET, VOIDmode, new0, new1);
3126 /* Our only special processing is to pass the mode of the MEM to our
3127 recursive call and copy the flags. While we are here, handle this
3128 case more efficiently. */
3129 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
3130 if (new != XEXP (x, 0))
3132 new = gen_rtx (MEM, GET_MODE (x), new);
3133 new->volatil = x->volatil;
3134 new->unchanging = x->unchanging;
3135 new->in_struct = x->in_struct;
3142 /* Process each of our operands recursively. If any have changed, make a
3144 fmt = GET_RTX_FORMAT (code);
3145 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3149 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
3150 if (new != XEXP (x, i) && ! copied)
3152 rtx new_x = rtx_alloc (code);
3153 bcopy ((char *) x, (char *) new_x,
3154 (sizeof (*new_x) - sizeof (new_x->fld)
3155 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
3161 else if (*fmt == 'E')
3164 for (j = 0; j < XVECLEN (x, i); j++)
3166 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3167 if (new != XVECEXP (x, i, j) && ! copied_vec)
3169 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
3170 &XVECEXP (x, i, 0));
3173 rtx new_x = rtx_alloc (code);
3174 bcopy ((char *) x, (char *) new_x,
3175 (sizeof (*new_x) - sizeof (new_x->fld)
3176 + (sizeof (new_x->fld[0])
3177 * GET_RTX_LENGTH (code))));
3181 XVEC (x, i) = new_v;
3184 XVECEXP (x, i, j) = new;
3192 /* Scan INSN and eliminate all eliminable registers in it.
3194 If REPLACE is nonzero, do the replacement destructively. Also
3195 delete the insn as dead it if it is setting an eliminable register.
3197 If REPLACE is zero, do all our allocations in reload_obstack.
3199 If no eliminations were done and this insn doesn't require any elimination
3200 processing (these are not identical conditions: it might be updating sp,
3201 but not referencing fp; this needs to be seen during reload_as_needed so
3202 that the offset between fp and sp can be taken into consideration), zero
3203 is returned. Otherwise, 1 is returned. */
3206 eliminate_regs_in_insn (insn, replace)
3210 rtx old_body = PATTERN (insn);
3211 rtx old_set = single_set (insn);
3214 struct elim_table *ep;
3217 push_obstacks (&reload_obstack, &reload_obstack);
3219 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
3220 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3222 /* Check for setting an eliminable register. */
3223 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3224 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3226 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3227 /* If this is setting the frame pointer register to the
3228 hardware frame pointer register and this is an elimination
3229 that will be done (tested above), this insn is really
3230 adjusting the frame pointer downward to compensate for
3231 the adjustment done before a nonlocal goto. */
3232 if (ep->from == FRAME_POINTER_REGNUM
3233 && ep->to == HARD_FRAME_POINTER_REGNUM)
3235 rtx src = SET_SRC (old_set);
3238 if (src == ep->to_rtx)
3240 else if (GET_CODE (src) == PLUS
3241 && GET_CODE (XEXP (src, 0)) == CONST_INT)
3242 offset = INTVAL (XEXP (src, 0)), ok = 1;
3249 = plus_constant (ep->to_rtx, offset - ep->offset);
3251 /* First see if this insn remains valid when we
3252 make the change. If not, keep the INSN_CODE
3253 the same and let reload fit it up. */
3254 validate_change (insn, &SET_SRC (old_set), src, 1);
3255 validate_change (insn, &SET_DEST (old_set),
3257 if (! apply_change_group ())
3259 SET_SRC (old_set) = src;
3260 SET_DEST (old_set) = ep->to_rtx;
3270 /* In this case this insn isn't serving a useful purpose. We
3271 will delete it in reload_as_needed once we know that this
3272 elimination is, in fact, being done.
3274 If REPLACE isn't set, we can't delete this insn, but needn't
3275 process it since it won't be used unless something changes. */
3277 delete_dead_insn (insn);
3282 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3283 in the insn is the negative of the offset in FROM. Substitute
3284 (set (reg) (reg to)) for the insn and change its code.
3286 We have to do this here, rather than in eliminate_regs, do that we can
3287 change the insn code. */
3289 if (GET_CODE (SET_SRC (old_set)) == PLUS
3290 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3291 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT)
3292 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3294 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0)
3295 && ep->can_eliminate)
3297 /* We must stop at the first elimination that will be used.
3298 If this one would replace the PLUS with a REG, do it
3299 now. Otherwise, quit the loop and let eliminate_regs
3300 do its normal replacement. */
3301 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1)))
3303 /* We assume here that we don't need a PARALLEL of
3304 any CLOBBERs for this assignment. There's not
3305 much we can do if we do need it. */
3306 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3307 SET_DEST (old_set), ep->to_rtx);
3308 INSN_CODE (insn) = -1;
3317 old_asm_operands_vec = 0;
3319 /* Replace the body of this insn with a substituted form. If we changed
3320 something, return non-zero.
3322 If we are replacing a body that was a (set X (plus Y Z)), try to
3323 re-recognize the insn. We do this in case we had a simple addition
3324 but now can do this as a load-address. This saves an insn in this
3327 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3328 if (new_body != old_body)
3330 /* If we aren't replacing things permanently and we changed something,
3331 make another copy to ensure that all the RTL is new. Otherwise
3332 things can go wrong if find_reload swaps commutative operands
3333 and one is inside RTL that has been copied while the other is not. */
3335 /* Don't copy an asm_operands because (1) there's no need and (2)
3336 copy_rtx can't do it properly when there are multiple outputs. */
3337 if (! replace && asm_noperands (old_body) < 0)
3338 new_body = copy_rtx (new_body);
3340 /* If we had a move insn but now we don't, rerecognize it. This will
3341 cause spurious re-recognition if the old move had a PARALLEL since
3342 the new one still will, but we can't call single_set without
3343 having put NEW_BODY into the insn and the re-recognition won't
3344 hurt in this rare case. */
3346 && ((GET_CODE (SET_SRC (old_set)) == REG
3347 && (GET_CODE (new_body) != SET
3348 || GET_CODE (SET_SRC (new_body)) != REG))
3349 /* If this was a load from or store to memory, compare
3350 the MEM in recog_operand to the one in the insn. If they
3351 are not equal, then rerecognize the insn. */
3353 && ((GET_CODE (SET_SRC (old_set)) == MEM
3354 && SET_SRC (old_set) != recog_operand[1])
3355 || (GET_CODE (SET_DEST (old_set)) == MEM
3356 && SET_DEST (old_set) != recog_operand[0])))
3357 /* If this was an add insn before, rerecognize. */
3358 || GET_CODE (SET_SRC (old_set)) == PLUS))
3360 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3361 /* If recognition fails, store the new body anyway.
3362 It's normal to have recognition failures here
3363 due to bizarre memory addresses; reloading will fix them. */
3364 PATTERN (insn) = new_body;
3367 PATTERN (insn) = new_body;
3372 /* Loop through all elimination pairs. See if any have changed and
3373 recalculate the number not at initial offset.
3375 Compute the maximum offset (minimum offset if the stack does not
3376 grow downward) for each elimination pair.
3378 We also detect a cases where register elimination cannot be done,
3379 namely, if a register would be both changed and referenced outside a MEM
3380 in the resulting insn since such an insn is often undefined and, even if
3381 not, we cannot know what meaning will be given to it. Note that it is
3382 valid to have a register used in an address in an insn that changes it
3383 (presumably with a pre- or post-increment or decrement).
3385 If anything changes, return nonzero. */
3387 num_not_at_initial_offset = 0;
3388 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3390 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3391 ep->can_eliminate = 0;
3393 ep->ref_outside_mem = 0;
3395 if (ep->previous_offset != ep->offset)
3398 ep->previous_offset = ep->offset;
3399 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3400 num_not_at_initial_offset++;
3402 #ifdef STACK_GROWS_DOWNWARD
3403 ep->max_offset = MAX (ep->max_offset, ep->offset);
3405 ep->max_offset = MIN (ep->max_offset, ep->offset);
3410 /* If we changed something, perform elimination in REG_NOTES. This is
3411 needed even when REPLACE is zero because a REG_DEAD note might refer
3412 to a register that we eliminate and could cause a different number
3413 of spill registers to be needed in the final reload pass than in
3415 if (val && REG_NOTES (insn) != 0)
3416 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3424 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3425 replacement we currently believe is valid, mark it as not eliminable if X
3426 modifies DEST in any way other than by adding a constant integer to it.
3428 If DEST is the frame pointer, we do nothing because we assume that
3429 all assignments to the hard frame pointer are nonlocal gotos and are being
3430 done at a time when they are valid and do not disturb anything else.
3431 Some machines want to eliminate a fake argument pointer with either the
3432 frame or stack pointer. Assignments to the hard frame pointer must not
3433 prevent this elimination.
3435 Called via note_stores from reload before starting its passes to scan
3436 the insns of the function. */
3439 mark_not_eliminable (dest, x)
3445 /* A SUBREG of a hard register here is just changing its mode. We should
3446 not see a SUBREG of an eliminable hard register, but check just in
3448 if (GET_CODE (dest) == SUBREG)
3449 dest = SUBREG_REG (dest);
3451 if (dest == hard_frame_pointer_rtx)
3454 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3455 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3456 && (GET_CODE (x) != SET
3457 || GET_CODE (SET_SRC (x)) != PLUS
3458 || XEXP (SET_SRC (x), 0) != dest
3459 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3461 reg_eliminate[i].can_eliminate_previous
3462 = reg_eliminate[i].can_eliminate = 0;
3467 /* Kick all pseudos out of hard register REGNO.
3468 If GLOBAL is nonzero, try to find someplace else to put them.
3469 If DUMPFILE is nonzero, log actions taken on that file.
3471 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3472 because we found we can't eliminate some register. In the case, no pseudos
3473 are allowed to be in the register, even if they are only in a block that
3474 doesn't require spill registers, unlike the case when we are spilling this
3475 hard reg to produce another spill register.
3477 Return nonzero if any pseudos needed to be kicked out. */
3480 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3486 enum reg_class class = REGNO_REG_CLASS (regno);
3487 int something_changed = 0;
3490 SET_HARD_REG_BIT (forbidden_regs, regno);
3493 regs_ever_live[regno] = 1;
3495 /* Spill every pseudo reg that was allocated to this reg
3496 or to something that overlaps this reg. */
3498 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3499 if (reg_renumber[i] >= 0
3500 && reg_renumber[i] <= regno
3502 + HARD_REGNO_NREGS (reg_renumber[i],
3503 PSEUDO_REGNO_MODE (i))
3506 /* If this register belongs solely to a basic block which needed no
3507 spilling of any class that this register is contained in,
3508 leave it be, unless we are spilling this register because
3509 it was a hard register that can't be eliminated. */
3511 if (! cant_eliminate
3512 && basic_block_needs[0]
3513 && reg_basic_block[i] >= 0
3514 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3518 for (p = reg_class_superclasses[(int) class];
3519 *p != LIM_REG_CLASSES; p++)
3520 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3523 if (*p == LIM_REG_CLASSES)
3527 /* Mark it as no longer having a hard register home. */
3528 reg_renumber[i] = -1;
3529 /* We will need to scan everything again. */
3530 something_changed = 1;
3532 retry_global_alloc (i, forbidden_regs);
3534 alter_reg (i, regno);
3537 if (reg_renumber[i] == -1)
3538 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3540 fprintf (dumpfile, " Register %d now in %d.\n\n",
3541 i, reg_renumber[i]);
3544 for (i = 0; i < scratch_list_length; i++)
3546 if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3548 if (! cant_eliminate && basic_block_needs[0]
3549 && ! basic_block_needs[(int) class][scratch_block[i]])
3553 for (p = reg_class_superclasses[(int) class];
3554 *p != LIM_REG_CLASSES; p++)
3555 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3558 if (*p == LIM_REG_CLASSES)
3561 PUT_CODE (scratch_list[i], SCRATCH);
3562 scratch_list[i] = 0;
3563 something_changed = 1;
3568 return something_changed;
3571 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3572 Also mark any hard registers used to store user variables as
3573 forbidden from being used for spill registers. */
3576 scan_paradoxical_subregs (x)
3581 register enum rtx_code code = GET_CODE (x);
3586 #ifdef SMALL_REGISTER_CLASSES
3587 if (REGNO (x) < FIRST_PSEUDO_REGISTER && REG_USERVAR_P (x))
3588 SET_HARD_REG_BIT (forbidden_regs, REGNO (x));
3604 if (GET_CODE (SUBREG_REG (x)) == REG
3605 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3606 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3607 = GET_MODE_SIZE (GET_MODE (x));
3611 fmt = GET_RTX_FORMAT (code);
3612 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3615 scan_paradoxical_subregs (XEXP (x, i));
3616 else if (fmt[i] == 'E')
3619 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3620 scan_paradoxical_subregs (XVECEXP (x, i, j));
3626 hard_reg_use_compare (p1p, p2p)
3627 const GENERIC_PTR p1p;
3628 const GENERIC_PTR p2p;
3630 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p,
3631 *p2 = (struct hard_reg_n_uses *)p2p;
3632 int tem = p1->uses - p2->uses;
3633 if (tem != 0) return tem;
3634 /* If regs are equally good, sort by regno,
3635 so that the results of qsort leave nothing to chance. */
3636 return p1->regno - p2->regno;
3639 /* Choose the order to consider regs for use as reload registers
3640 based on how much trouble would be caused by spilling one.
3641 Store them in order of decreasing preference in potential_reload_regs. */
3644 order_regs_for_reload (global)
3651 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3653 CLEAR_HARD_REG_SET (bad_spill_regs);
3655 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3656 potential_reload_regs[i] = -1;
3658 /* Count number of uses of each hard reg by pseudo regs allocated to it
3659 and then order them by decreasing use. */
3661 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3663 hard_reg_n_uses[i].uses = 0;
3664 hard_reg_n_uses[i].regno = i;
3667 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3669 int regno = reg_renumber[i];
3672 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3675 /* If allocated by local-alloc, show more uses since
3676 we're not going to be able to reallocate it, but
3677 we might if allocated by global alloc. */
3678 if (global && reg_allocno[i] < 0)
3679 hard_reg_n_uses[regno].uses += (reg_n_refs[i] + 1) / 2;
3681 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3684 large += reg_n_refs[i];
3687 /* Now fixed registers (which cannot safely be used for reloading)
3688 get a very high use count so they will be considered least desirable.
3689 Registers used explicitly in the rtl code are almost as bad. */
3691 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3695 hard_reg_n_uses[i].uses += 2 * large + 2;
3696 SET_HARD_REG_BIT (bad_spill_regs, i);
3698 else if (regs_explicitly_used[i])
3700 hard_reg_n_uses[i].uses += large + 1;
3701 #ifndef SMALL_REGISTER_CLASSES
3702 /* ??? We are doing this here because of the potential that
3703 bad code may be generated if a register explicitly used in
3704 an insn was used as a spill register for that insn. But
3705 not using these are spill registers may lose on some machine.
3706 We'll have to see how this works out. */
3707 SET_HARD_REG_BIT (bad_spill_regs, i);
3711 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3712 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM);
3714 #ifdef ELIMINABLE_REGS
3715 /* If registers other than the frame pointer are eliminable, mark them as
3717 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3719 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3720 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3724 /* Prefer registers not so far used, for use in temporary loading.
3725 Among them, if REG_ALLOC_ORDER is defined, use that order.
3726 Otherwise, prefer registers not preserved by calls. */
3728 #ifdef REG_ALLOC_ORDER
3729 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3731 int regno = reg_alloc_order[i];
3733 if (hard_reg_n_uses[regno].uses == 0)
3734 potential_reload_regs[o++] = regno;
3737 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3739 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3740 potential_reload_regs[o++] = i;
3742 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3744 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3745 potential_reload_regs[o++] = i;
3749 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3750 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3752 /* Now add the regs that are already used,
3753 preferring those used less often. The fixed and otherwise forbidden
3754 registers will be at the end of this list. */
3756 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3757 if (hard_reg_n_uses[i].uses != 0)
3758 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3761 /* Used in reload_as_needed to sort the spilled regs. */
3764 compare_spill_regs (r1p, r2p)
3765 const GENERIC_PTR r1p;
3766 const GENERIC_PTR r2p;
3768 short r1 = *(short *)r1p, r2 = *(short *)r2p;
3772 /* Reload pseudo-registers into hard regs around each insn as needed.
3773 Additional register load insns are output before the insn that needs it
3774 and perhaps store insns after insns that modify the reloaded pseudo reg.
3776 reg_last_reload_reg and reg_reloaded_contents keep track of
3777 which registers are already available in reload registers.
3778 We update these for the reloads that we perform,
3779 as the insns are scanned. */
3782 reload_as_needed (first, live_known)
3792 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3793 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3794 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3795 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
3796 reg_has_output_reload = (char *) alloca (max_regno);
3797 for (i = 0; i < n_spills; i++)
3799 reg_reloaded_contents[i] = -1;
3800 reg_reloaded_insn[i] = 0;
3803 /* Reset all offsets on eliminable registers to their initial values. */
3804 #ifdef ELIMINABLE_REGS
3805 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3807 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3808 reg_eliminate[i].initial_offset);
3809 reg_eliminate[i].previous_offset
3810 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3813 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3814 reg_eliminate[0].previous_offset
3815 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3818 num_not_at_initial_offset = 0;
3820 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
3821 pack registers with group needs. */
3824 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs);
3825 for (i = 0; i < n_spills; i++)
3826 spill_reg_order[spill_regs[i]] = i;
3829 for (insn = first; insn;)
3831 register rtx next = NEXT_INSN (insn);
3833 /* Notice when we move to a new basic block. */
3834 if (live_known && this_block + 1 < n_basic_blocks
3835 && insn == basic_block_head[this_block+1])
3838 /* If we pass a label, copy the offsets from the label information
3839 into the current offsets of each elimination. */
3840 if (GET_CODE (insn) == CODE_LABEL)
3842 num_not_at_initial_offset = 0;
3843 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3845 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3846 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3847 if (reg_eliminate[i].can_eliminate
3848 && (reg_eliminate[i].offset
3849 != reg_eliminate[i].initial_offset))
3850 num_not_at_initial_offset++;
3854 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3856 rtx avoid_return_reg = 0;
3857 rtx oldpat = PATTERN (insn);
3859 #ifdef SMALL_REGISTER_CLASSES
3860 /* Set avoid_return_reg if this is an insn
3861 that might use the value of a function call. */
3862 if (GET_CODE (insn) == CALL_INSN)
3864 if (GET_CODE (PATTERN (insn)) == SET)
3865 after_call = SET_DEST (PATTERN (insn));
3866 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3867 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3868 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3872 else if (after_call != 0
3873 && !(GET_CODE (PATTERN (insn)) == SET
3874 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3876 if (reg_referenced_p (after_call, PATTERN (insn)))
3877 avoid_return_reg = after_call;
3880 #endif /* SMALL_REGISTER_CLASSES */
3882 /* If this is a USE and CLOBBER of a MEM, ensure that any
3883 references to eliminable registers have been removed. */
3885 if ((GET_CODE (PATTERN (insn)) == USE
3886 || GET_CODE (PATTERN (insn)) == CLOBBER)
3887 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3888 XEXP (XEXP (PATTERN (insn), 0), 0)
3889 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3890 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3892 /* If we need to do register elimination processing, do so.
3893 This might delete the insn, in which case we are done. */
3894 if (num_eliminable && GET_MODE (insn) == QImode)
3896 eliminate_regs_in_insn (insn, 1);
3897 if (GET_CODE (insn) == NOTE)
3904 if (GET_MODE (insn) == VOIDmode)
3906 /* First find the pseudo regs that must be reloaded for this insn.
3907 This info is returned in the tables reload_... (see reload.h).
3908 Also modify the body of INSN by substituting RELOAD
3909 rtx's for those pseudo regs. */
3912 bzero (reg_has_output_reload, max_regno);
3913 CLEAR_HARD_REG_SET (reg_is_output_reload);
3915 find_reloads (insn, 1, spill_indirect_levels, live_known,
3921 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3925 /* If this block has not had spilling done for a
3926 particular clas and we have any non-optionals that need a
3927 spill reg in that class, abort. */
3929 for (class = 0; class < N_REG_CLASSES; class++)
3930 if (basic_block_needs[class] != 0
3931 && basic_block_needs[class][this_block] == 0)
3932 for (i = 0; i < n_reloads; i++)
3933 if (class == (int) reload_reg_class[i]
3934 && reload_reg_rtx[i] == 0
3935 && ! reload_optional[i]
3936 && (reload_in[i] != 0 || reload_out[i] != 0
3937 || reload_secondary_p[i] != 0))
3938 fatal_insn ("Non-optional registers need a spill register", insn);
3940 /* Now compute which reload regs to reload them into. Perhaps
3941 reusing reload regs from previous insns, or else output
3942 load insns to reload them. Maybe output store insns too.
3943 Record the choices of reload reg in reload_reg_rtx. */
3944 choose_reload_regs (insn, avoid_return_reg);
3946 #ifdef SMALL_REGISTER_CLASSES
3947 /* Merge any reloads that we didn't combine for fear of
3948 increasing the number of spill registers needed but now
3949 discover can be safely merged. */
3950 merge_assigned_reloads (insn);
3953 /* Generate the insns to reload operands into or out of
3954 their reload regs. */
3955 emit_reload_insns (insn);
3957 /* Substitute the chosen reload regs from reload_reg_rtx
3958 into the insn's body (or perhaps into the bodies of other
3959 load and store insn that we just made for reloading
3960 and that we moved the structure into). */
3963 /* If this was an ASM, make sure that all the reload insns
3964 we have generated are valid. If not, give an error
3967 if (asm_noperands (PATTERN (insn)) >= 0)
3968 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3969 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3970 && (recog_memoized (p) < 0
3971 || (insn_extract (p),
3972 ! constrain_operands (INSN_CODE (p), 1))))
3974 error_for_asm (insn,
3975 "`asm' operand requires impossible reload");
3977 NOTE_SOURCE_FILE (p) = 0;
3978 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3981 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3982 is no longer validly lying around to save a future reload.
3983 Note that this does not detect pseudos that were reloaded
3984 for this insn in order to be stored in
3985 (obeying register constraints). That is correct; such reload
3986 registers ARE still valid. */
3987 note_stores (oldpat, forget_old_reloads_1);
3989 /* There may have been CLOBBER insns placed after INSN. So scan
3990 between INSN and NEXT and use them to forget old reloads. */
3991 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3992 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3993 note_stores (PATTERN (x), forget_old_reloads_1);
3996 /* Likewise for regs altered by auto-increment in this insn.
3997 But note that the reg-notes are not changed by reloading:
3998 they still contain the pseudo-regs, not the spill regs. */
3999 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4000 if (REG_NOTE_KIND (x) == REG_INC)
4002 /* See if this pseudo reg was reloaded in this insn.
4003 If so, its last-reload info is still valid
4004 because it is based on this insn's reload. */
4005 for (i = 0; i < n_reloads; i++)
4006 if (reload_out[i] == XEXP (x, 0))
4010 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
4014 /* A reload reg's contents are unknown after a label. */
4015 if (GET_CODE (insn) == CODE_LABEL)
4016 for (i = 0; i < n_spills; i++)
4018 reg_reloaded_contents[i] = -1;
4019 reg_reloaded_insn[i] = 0;
4022 /* Don't assume a reload reg is still good after a call insn
4023 if it is a call-used reg. */
4024 else if (GET_CODE (insn) == CALL_INSN)
4025 for (i = 0; i < n_spills; i++)
4026 if (call_used_regs[spill_regs[i]])
4028 reg_reloaded_contents[i] = -1;
4029 reg_reloaded_insn[i] = 0;
4032 /* In case registers overlap, allow certain insns to invalidate
4033 particular hard registers. */
4035 #ifdef INSN_CLOBBERS_REGNO_P
4036 for (i = 0 ; i < n_spills ; i++)
4037 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
4039 reg_reloaded_contents[i] = -1;
4040 reg_reloaded_insn[i] = 0;
4052 /* Discard all record of any value reloaded from X,
4053 or reloaded in X from someplace else;
4054 unless X is an output reload reg of the current insn.
4056 X may be a hard reg (the reload reg)
4057 or it may be a pseudo reg that was reloaded from. */
4060 forget_old_reloads_1 (x, ignored)
4068 /* note_stores does give us subregs of hard regs. */
4069 while (GET_CODE (x) == SUBREG)
4071 offset += SUBREG_WORD (x);
4075 if (GET_CODE (x) != REG)
4078 regno = REGNO (x) + offset;
4080 if (regno >= FIRST_PSEUDO_REGISTER)
4085 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4086 /* Storing into a spilled-reg invalidates its contents.
4087 This can happen if a block-local pseudo is allocated to that reg
4088 and it wasn't spilled because this block's total need is 0.
4089 Then some insn might have an optional reload and use this reg. */
4090 for (i = 0; i < nr; i++)
4091 if (spill_reg_order[regno + i] >= 0
4092 /* But don't do this if the reg actually serves as an output
4093 reload reg in the current instruction. */
4095 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
4097 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
4098 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
4102 /* Since value of X has changed,
4103 forget any value previously copied from it. */
4106 /* But don't forget a copy if this is the output reload
4107 that establishes the copy's validity. */
4108 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4109 reg_last_reload_reg[regno + nr] = 0;
4112 /* For each reload, the mode of the reload register. */
4113 static enum machine_mode reload_mode[MAX_RELOADS];
4115 /* For each reload, the largest number of registers it will require. */
4116 static int reload_nregs[MAX_RELOADS];
4118 /* Comparison function for qsort to decide which of two reloads
4119 should be handled first. *P1 and *P2 are the reload numbers. */
4122 reload_reg_class_lower (r1p, r2p)
4123 const GENERIC_PTR r1p;
4124 const GENERIC_PTR r2p;
4126 register int r1 = *(short *)r1p, r2 = *(short *)r2p;
4129 /* Consider required reloads before optional ones. */
4130 t = reload_optional[r1] - reload_optional[r2];
4134 /* Count all solitary classes before non-solitary ones. */
4135 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
4136 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
4140 /* Aside from solitaires, consider all multi-reg groups first. */
4141 t = reload_nregs[r2] - reload_nregs[r1];
4145 /* Consider reloads in order of increasing reg-class number. */
4146 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
4150 /* If reloads are equally urgent, sort by reload number,
4151 so that the results of qsort leave nothing to chance. */
4155 /* The following HARD_REG_SETs indicate when each hard register is
4156 used for a reload of various parts of the current insn. */
4158 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4159 static HARD_REG_SET reload_reg_used;
4160 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4161 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4162 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4163 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4164 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4165 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4166 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4167 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4168 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4169 static HARD_REG_SET reload_reg_used_in_op_addr;
4170 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4171 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4172 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4173 static HARD_REG_SET reload_reg_used_in_insn;
4174 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4175 static HARD_REG_SET reload_reg_used_in_other_addr;
4177 /* If reg is in use as a reload reg for any sort of reload. */
4178 static HARD_REG_SET reload_reg_used_at_all;
4180 /* If reg is use as an inherited reload. We just mark the first register
4182 static HARD_REG_SET reload_reg_used_for_inherit;
4184 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4185 TYPE. MODE is used to indicate how many consecutive regs are
4189 mark_reload_reg_in_use (regno, opnum, type, mode)
4192 enum reload_type type;
4193 enum machine_mode mode;
4195 int nregs = HARD_REGNO_NREGS (regno, mode);
4198 for (i = regno; i < nregs + regno; i++)
4203 SET_HARD_REG_BIT (reload_reg_used, i);
4206 case RELOAD_FOR_INPUT_ADDRESS:
4207 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4210 case RELOAD_FOR_OUTPUT_ADDRESS:
4211 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4214 case RELOAD_FOR_OPERAND_ADDRESS:
4215 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4218 case RELOAD_FOR_OPADDR_ADDR:
4219 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4222 case RELOAD_FOR_OTHER_ADDRESS:
4223 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4226 case RELOAD_FOR_INPUT:
4227 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4230 case RELOAD_FOR_OUTPUT:
4231 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4234 case RELOAD_FOR_INSN:
4235 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4239 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4243 /* Similarly, but show REGNO is no longer in use for a reload. */
4246 clear_reload_reg_in_use (regno, opnum, type, mode)
4249 enum reload_type type;
4250 enum machine_mode mode;
4252 int nregs = HARD_REGNO_NREGS (regno, mode);
4255 for (i = regno; i < nregs + regno; i++)
4260 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4263 case RELOAD_FOR_INPUT_ADDRESS:
4264 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4267 case RELOAD_FOR_OUTPUT_ADDRESS:
4268 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4271 case RELOAD_FOR_OPERAND_ADDRESS:
4272 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4275 case RELOAD_FOR_OPADDR_ADDR:
4276 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4279 case RELOAD_FOR_OTHER_ADDRESS:
4280 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4283 case RELOAD_FOR_INPUT:
4284 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4287 case RELOAD_FOR_OUTPUT:
4288 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4291 case RELOAD_FOR_INSN:
4292 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4298 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4299 specified by OPNUM and TYPE. */
4302 reload_reg_free_p (regno, opnum, type)
4305 enum reload_type type;
4309 /* In use for a RELOAD_OTHER means it's not available for anything. */
4310 if (TEST_HARD_REG_BIT (reload_reg_used, regno))
4316 /* In use for anything means we can't use it for RELOAD_OTHER. */
4317 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4318 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4319 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4322 for (i = 0; i < reload_n_operands; i++)
4323 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4324 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4325 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4326 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4331 case RELOAD_FOR_INPUT:
4332 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4333 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4336 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4339 /* If it is used for some other input, can't use it. */
4340 for (i = 0; i < reload_n_operands; i++)
4341 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4344 /* If it is used in a later operand's address, can't use it. */
4345 for (i = opnum + 1; i < reload_n_operands; i++)
4346 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4351 case RELOAD_FOR_INPUT_ADDRESS:
4352 /* Can't use a register if it is used for an input address for this
4353 operand or used as an input in an earlier one. */
4354 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
4357 for (i = 0; i < opnum; i++)
4358 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4363 case RELOAD_FOR_OUTPUT_ADDRESS:
4364 /* Can't use a register if it is used for an output address for this
4365 operand or used as an output in this or a later operand. */
4366 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4369 for (i = opnum; i < reload_n_operands; i++)
4370 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4375 case RELOAD_FOR_OPERAND_ADDRESS:
4376 for (i = 0; i < reload_n_operands; i++)
4377 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4380 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4381 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4383 case RELOAD_FOR_OPADDR_ADDR:
4384 for (i = 0; i < reload_n_operands; i++)
4385 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4388 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4390 case RELOAD_FOR_OUTPUT:
4391 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4392 outputs, or an operand address for this or an earlier output. */
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4396 for (i = 0; i < reload_n_operands; i++)
4397 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4400 for (i = 0; i <= opnum; i++)
4401 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4406 case RELOAD_FOR_INSN:
4407 for (i = 0; i < reload_n_operands; i++)
4408 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4409 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4412 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4413 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4415 case RELOAD_FOR_OTHER_ADDRESS:
4416 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4421 /* Return 1 if the value in reload reg REGNO, as used by a reload
4422 needed for the part of the insn specified by OPNUM and TYPE,
4423 is not in use for a reload in any prior part of the insn.
4425 We can assume that the reload reg was already tested for availability
4426 at the time it is needed, and we should not check this again,
4427 in case the reg has already been marked in use. */
4430 reload_reg_free_before_p (regno, opnum, type)
4433 enum reload_type type;
4439 case RELOAD_FOR_OTHER_ADDRESS:
4440 /* These always come first. */
4444 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4446 /* If this use is for part of the insn,
4447 check the reg is not in use for any prior part. It is tempting
4448 to try to do this by falling through from objecs that occur
4449 later in the insn to ones that occur earlier, but that will not
4450 correctly take into account the fact that here we MUST ignore
4451 things that would prevent the register from being allocated in
4452 the first place, since we know that it was allocated. */
4454 case RELOAD_FOR_OUTPUT_ADDRESS:
4455 /* Earlier reloads are for earlier outputs or their addresses,
4456 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4457 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4459 for (i = 0; i < opnum; i++)
4460 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4461 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4464 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4467 for (i = 0; i < reload_n_operands; i++)
4468 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4469 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4472 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4473 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4474 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4476 case RELOAD_FOR_OUTPUT:
4477 /* This can't be used in the output address for this operand and
4478 anything that can't be used for it, except that we've already
4479 tested for RELOAD_FOR_INSN objects. */
4481 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4484 for (i = 0; i < opnum; i++)
4485 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4486 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4489 for (i = 0; i < reload_n_operands; i++)
4490 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4491 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4492 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4495 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4497 case RELOAD_FOR_OPERAND_ADDRESS:
4498 case RELOAD_FOR_OPADDR_ADDR:
4499 case RELOAD_FOR_INSN:
4500 /* These can't conflict with inputs, or each other, so all we have to
4501 test is input addresses and the addresses of OTHER items. */
4503 for (i = 0; i < reload_n_operands; i++)
4504 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4507 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4509 case RELOAD_FOR_INPUT:
4510 /* The only things earlier are the address for this and
4511 earlier inputs, other inputs (which we know we don't conflict
4512 with), and addresses of RELOAD_OTHER objects. */
4514 for (i = 0; i <= opnum; i++)
4515 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4518 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4520 case RELOAD_FOR_INPUT_ADDRESS:
4521 /* Similarly, all we have to check is for use in earlier inputs'
4523 for (i = 0; i < opnum; i++)
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4527 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4532 /* Return 1 if the value in reload reg REGNO, as used by a reload
4533 needed for the part of the insn specified by OPNUM and TYPE,
4534 is still available in REGNO at the end of the insn.
4536 We can assume that the reload reg was already tested for availability
4537 at the time it is needed, and we should not check this again,
4538 in case the reg has already been marked in use. */
4541 reload_reg_reaches_end_p (regno, opnum, type)
4544 enum reload_type type;
4551 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4552 its value must reach the end. */
4555 /* If this use is for part of the insn,
4556 its value reaches if no subsequent part uses the same register.
4557 Just like the above function, don't try to do this with lots
4560 case RELOAD_FOR_OTHER_ADDRESS:
4561 /* Here we check for everything else, since these don't conflict
4562 with anything else and everything comes later. */
4564 for (i = 0; i < reload_n_operands; i++)
4565 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4566 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4567 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4568 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4571 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4572 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4573 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4575 case RELOAD_FOR_INPUT_ADDRESS:
4576 /* Similar, except that we check only for this and subsequent inputs
4577 and the address of only subsequent inputs and we do not need
4578 to check for RELOAD_OTHER objects since they are known not to
4581 for (i = opnum; i < reload_n_operands; i++)
4582 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4585 for (i = opnum + 1; i < reload_n_operands; i++)
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4589 for (i = 0; i < reload_n_operands; i++)
4590 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4591 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4594 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4597 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4598 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4600 case RELOAD_FOR_INPUT:
4601 /* Similar to input address, except we start at the next operand for
4602 both input and input address and we do not check for
4603 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4606 for (i = opnum + 1; i < reload_n_operands; i++)
4607 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4608 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4611 /* ... fall through ... */
4613 case RELOAD_FOR_OPERAND_ADDRESS:
4614 /* Check outputs and their addresses. */
4616 for (i = 0; i < reload_n_operands; i++)
4617 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4618 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4623 case RELOAD_FOR_OPADDR_ADDR:
4624 for (i = 0; i < reload_n_operands; i++)
4625 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4626 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4629 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4630 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4632 case RELOAD_FOR_INSN:
4633 /* These conflict with other outputs with RELOAD_OTHER. So
4634 we need only check for output addresses. */
4638 /* ... fall through ... */
4640 case RELOAD_FOR_OUTPUT:
4641 case RELOAD_FOR_OUTPUT_ADDRESS:
4642 /* We already know these can't conflict with a later output. So the
4643 only thing to check are later output addresses. */
4644 for (i = opnum + 1; i < reload_n_operands; i++)
4645 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4654 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4657 This function uses the same algorithm as reload_reg_free_p above. */
4660 reloads_conflict (r1, r2)
4663 enum reload_type r1_type = reload_when_needed[r1];
4664 enum reload_type r2_type = reload_when_needed[r2];
4665 int r1_opnum = reload_opnum[r1];
4666 int r2_opnum = reload_opnum[r2];
4668 /* RELOAD_OTHER conflicts with everything. */
4669 if (r2_type == RELOAD_OTHER)
4672 /* Otherwise, check conflicts differently for each type. */
4676 case RELOAD_FOR_INPUT:
4677 return (r2_type == RELOAD_FOR_INSN
4678 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4679 || r2_type == RELOAD_FOR_OPADDR_ADDR
4680 || r2_type == RELOAD_FOR_INPUT
4681 || (r2_type == RELOAD_FOR_INPUT_ADDRESS && r2_opnum > r1_opnum));
4683 case RELOAD_FOR_INPUT_ADDRESS:
4684 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4685 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4687 case RELOAD_FOR_OUTPUT_ADDRESS:
4688 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4689 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4691 case RELOAD_FOR_OPERAND_ADDRESS:
4692 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4693 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4695 case RELOAD_FOR_OPADDR_ADDR:
4696 return (r2_type == RELOAD_FOR_INPUT
4697 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4699 case RELOAD_FOR_OUTPUT:
4700 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4701 || (r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4702 && r2_opnum >= r1_opnum));
4704 case RELOAD_FOR_INSN:
4705 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4706 || r2_type == RELOAD_FOR_INSN
4707 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4709 case RELOAD_FOR_OTHER_ADDRESS:
4710 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4720 /* Vector of reload-numbers showing the order in which the reloads should
4722 short reload_order[MAX_RELOADS];
4724 /* Indexed by reload number, 1 if incoming value
4725 inherited from previous insns. */
4726 char reload_inherited[MAX_RELOADS];
4728 /* For an inherited reload, this is the insn the reload was inherited from,
4729 if we know it. Otherwise, this is 0. */
4730 rtx reload_inheritance_insn[MAX_RELOADS];
4732 /* If non-zero, this is a place to get the value of the reload,
4733 rather than using reload_in. */
4734 rtx reload_override_in[MAX_RELOADS];
4736 /* For each reload, the index in spill_regs of the spill register used,
4737 or -1 if we did not need one of the spill registers for this reload. */
4738 int reload_spill_index[MAX_RELOADS];
4740 /* Find a spill register to use as a reload register for reload R.
4741 LAST_RELOAD is non-zero if this is the last reload for the insn being
4744 Set reload_reg_rtx[R] to the register allocated.
4746 If NOERROR is nonzero, we return 1 if successful,
4747 or 0 if we couldn't find a spill reg and we didn't change anything. */
4750 allocate_reload_reg (r, insn, last_reload, noerror)
4762 /* If we put this reload ahead, thinking it is a group,
4763 then insist on finding a group. Otherwise we can grab a
4764 reg that some other reload needs.
4765 (That can happen when we have a 68000 DATA_OR_FP_REG
4766 which is a group of data regs or one fp reg.)
4767 We need not be so restrictive if there are no more reloads
4770 ??? Really it would be nicer to have smarter handling
4771 for that kind of reg class, where a problem like this is normal.
4772 Perhaps those classes should be avoided for reloading
4773 by use of more alternatives. */
4775 int force_group = reload_nregs[r] > 1 && ! last_reload;
4777 /* If we want a single register and haven't yet found one,
4778 take any reg in the right class and not in use.
4779 If we want a consecutive group, here is where we look for it.
4781 We use two passes so we can first look for reload regs to
4782 reuse, which are already in use for other reloads in this insn,
4783 and only then use additional registers.
4784 I think that maximizing reuse is needed to make sure we don't
4785 run out of reload regs. Suppose we have three reloads, and
4786 reloads A and B can share regs. These need two regs.
4787 Suppose A and B are given different regs.
4788 That leaves none for C. */
4789 for (pass = 0; pass < 2; pass++)
4791 /* I is the index in spill_regs.
4792 We advance it round-robin between insns to use all spill regs
4793 equally, so that inherited reloads have a chance
4794 of leapfrogging each other. Don't do this, however, when we have
4795 group needs and failure would be fatal; if we only have a relatively
4796 small number of spill registers, and more than one of them has
4797 group needs, then by starting in the middle, we may end up
4798 allocating the first one in such a way that we are not left with
4799 sufficient groups to handle the rest. */
4801 if (noerror || ! force_group)
4806 for (count = 0; count < n_spills; count++)
4808 int class = (int) reload_reg_class[r];
4810 i = (i + 1) % n_spills;
4812 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
4813 reload_when_needed[r])
4814 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
4815 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4816 /* Look first for regs to share, then for unshared. But
4817 don't share regs used for inherited reloads; they are
4818 the ones we want to preserve. */
4820 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4822 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4825 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4826 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4827 (on 68000) got us two FP regs. If NR is 1,
4828 we would reject both of them. */
4830 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
4831 /* If we need only one reg, we have already won. */
4834 /* But reject a single reg if we demand a group. */
4839 /* Otherwise check that as many consecutive regs as we need
4841 Also, don't use for a group registers that are
4842 needed for nongroups. */
4843 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
4846 regno = spill_regs[i] + nr - 1;
4847 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4848 && spill_reg_order[regno] >= 0
4849 && reload_reg_free_p (regno, reload_opnum[r],
4850 reload_when_needed[r])
4851 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
4861 /* If we found something on pass 1, omit pass 2. */
4862 if (count < n_spills)
4866 /* We should have found a spill register by now. */
4867 if (count == n_spills)
4874 /* I is the index in SPILL_REG_RTX of the reload register we are to
4875 allocate. Get an rtx for it and find its register number. */
4877 new = spill_reg_rtx[i];
4879 if (new == 0 || GET_MODE (new) != reload_mode[r])
4880 spill_reg_rtx[i] = new
4881 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
4883 regno = true_regnum (new);
4885 /* Detect when the reload reg can't hold the reload mode.
4886 This used to be one `if', but Sequent compiler can't handle that. */
4887 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4889 enum machine_mode test_mode = VOIDmode;
4891 test_mode = GET_MODE (reload_in[r]);
4892 /* If reload_in[r] has VOIDmode, it means we will load it
4893 in whatever mode the reload reg has: to wit, reload_mode[r].
4894 We have already tested that for validity. */
4895 /* Aside from that, we need to test that the expressions
4896 to reload from or into have modes which are valid for this
4897 reload register. Otherwise the reload insns would be invalid. */
4898 if (! (reload_in[r] != 0 && test_mode != VOIDmode
4899 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4900 if (! (reload_out[r] != 0
4901 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
4903 /* The reg is OK. */
4906 /* Mark as in use for this insn the reload regs we use
4908 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
4909 reload_when_needed[r], reload_mode[r]);
4911 reload_reg_rtx[r] = new;
4912 reload_spill_index[r] = i;
4917 /* The reg is not OK. */
4922 if (asm_noperands (PATTERN (insn)) < 0)
4923 /* It's the compiler's fault. */
4924 fatal_insn ("Could not find a spill register", insn);
4926 /* It's the user's fault; the operand's mode and constraint
4927 don't match. Disable this reload so we don't crash in final. */
4928 error_for_asm (insn,
4929 "`asm' operand constraint incompatible with operand size");
4932 reload_reg_rtx[r] = 0;
4933 reload_optional[r] = 1;
4934 reload_secondary_p[r] = 1;
4939 /* Assign hard reg targets for the pseudo-registers we must reload
4940 into hard regs for this insn.
4941 Also output the instructions to copy them in and out of the hard regs.
4943 For machines with register classes, we are responsible for
4944 finding a reload reg in the proper class. */
4947 choose_reload_regs (insn, avoid_return_reg)
4949 rtx avoid_return_reg;
4952 int max_group_size = 1;
4953 enum reg_class group_class = NO_REGS;
4956 rtx save_reload_reg_rtx[MAX_RELOADS];
4957 char save_reload_inherited[MAX_RELOADS];
4958 rtx save_reload_inheritance_insn[MAX_RELOADS];
4959 rtx save_reload_override_in[MAX_RELOADS];
4960 int save_reload_spill_index[MAX_RELOADS];
4961 HARD_REG_SET save_reload_reg_used;
4962 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4963 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4964 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4965 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4966 HARD_REG_SET save_reload_reg_used_in_op_addr;
4967 HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
4968 HARD_REG_SET save_reload_reg_used_in_insn;
4969 HARD_REG_SET save_reload_reg_used_in_other_addr;
4970 HARD_REG_SET save_reload_reg_used_at_all;
4972 bzero (reload_inherited, MAX_RELOADS);
4973 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4974 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
4976 CLEAR_HARD_REG_SET (reload_reg_used);
4977 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4978 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4979 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
4980 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
4981 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
4983 for (i = 0; i < reload_n_operands; i++)
4985 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
4986 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
4987 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
4988 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
4991 #ifdef SMALL_REGISTER_CLASSES
4992 /* Don't bother with avoiding the return reg
4993 if we have no mandatory reload that could use it. */
4994 if (avoid_return_reg)
4997 int regno = REGNO (avoid_return_reg);
4999 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5002 for (r = regno; r < regno + nregs; r++)
5003 if (spill_reg_order[r] >= 0)
5004 for (j = 0; j < n_reloads; j++)
5005 if (!reload_optional[j] && reload_reg_rtx[j] == 0
5006 && (reload_in[j] != 0 || reload_out[j] != 0
5007 || reload_secondary_p[j])
5009 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
5012 avoid_return_reg = 0;
5014 #endif /* SMALL_REGISTER_CLASSES */
5016 #if 0 /* Not needed, now that we can always retry without inheritance. */
5017 /* See if we have more mandatory reloads than spill regs.
5018 If so, then we cannot risk optimizations that could prevent
5019 reloads from sharing one spill register.
5021 Since we will try finding a better register than reload_reg_rtx
5022 unless it is equal to reload_in or reload_out, count such reloads. */
5026 #ifdef SMALL_REGISTER_CLASSES
5027 int tem = (avoid_return_reg != 0);
5029 for (j = 0; j < n_reloads; j++)
5030 if (! reload_optional[j]
5031 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
5032 && (reload_reg_rtx[j] == 0
5033 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
5034 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
5041 #ifdef SMALL_REGISTER_CLASSES
5042 /* Don't use the subroutine call return reg for a reload
5043 if we are supposed to avoid it. */
5044 if (avoid_return_reg)
5046 int regno = REGNO (avoid_return_reg);
5048 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
5051 for (r = regno; r < regno + nregs; r++)
5052 if (spill_reg_order[r] >= 0)
5053 SET_HARD_REG_BIT (reload_reg_used, r);
5055 #endif /* SMALL_REGISTER_CLASSES */
5057 /* In order to be certain of getting the registers we need,
5058 we must sort the reloads into order of increasing register class.
5059 Then our grabbing of reload registers will parallel the process
5060 that provided the reload registers.
5062 Also note whether any of the reloads wants a consecutive group of regs.
5063 If so, record the maximum size of the group desired and what
5064 register class contains all the groups needed by this insn. */
5066 for (j = 0; j < n_reloads; j++)
5068 reload_order[j] = j;
5069 reload_spill_index[j] = -1;
5072 = (reload_inmode[j] == VOIDmode
5073 || (GET_MODE_SIZE (reload_outmode[j])
5074 > GET_MODE_SIZE (reload_inmode[j])))
5075 ? reload_outmode[j] : reload_inmode[j];
5077 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
5079 if (reload_nregs[j] > 1)
5081 max_group_size = MAX (reload_nregs[j], max_group_size);
5082 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
5085 /* If we have already decided to use a certain register,
5086 don't use it in another way. */
5087 if (reload_reg_rtx[j])
5088 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
5089 reload_when_needed[j], reload_mode[j]);
5093 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5095 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
5096 sizeof reload_reg_rtx);
5097 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
5098 bcopy ((char *) reload_inheritance_insn,
5099 (char *) save_reload_inheritance_insn,
5100 sizeof reload_inheritance_insn);
5101 bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
5102 sizeof reload_override_in);
5103 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
5104 sizeof reload_spill_index);
5105 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
5106 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
5107 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
5108 reload_reg_used_in_op_addr);
5110 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
5111 reload_reg_used_in_op_addr_reload);
5113 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
5114 reload_reg_used_in_insn);
5115 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
5116 reload_reg_used_in_other_addr);
5118 for (i = 0; i < reload_n_operands; i++)
5120 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
5121 reload_reg_used_in_output[i]);
5122 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
5123 reload_reg_used_in_input[i]);
5124 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
5125 reload_reg_used_in_input_addr[i]);
5126 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
5127 reload_reg_used_in_output_addr[i]);
5130 /* If -O, try first with inheritance, then turning it off.
5131 If not -O, don't do inheritance.
5132 Using inheritance when not optimizing leads to paradoxes
5133 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5134 because one side of the comparison might be inherited. */
5136 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5138 /* Process the reloads in order of preference just found.
5139 Beyond this point, subregs can be found in reload_reg_rtx.
5141 This used to look for an existing reloaded home for all
5142 of the reloads, and only then perform any new reloads.
5143 But that could lose if the reloads were done out of reg-class order
5144 because a later reload with a looser constraint might have an old
5145 home in a register needed by an earlier reload with a tighter constraint.
5147 To solve this, we make two passes over the reloads, in the order
5148 described above. In the first pass we try to inherit a reload
5149 from a previous insn. If there is a later reload that needs a
5150 class that is a proper subset of the class being processed, we must
5151 also allocate a spill register during the first pass.
5153 Then make a second pass over the reloads to allocate any reloads
5154 that haven't been given registers yet. */
5156 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5158 for (j = 0; j < n_reloads; j++)
5160 register int r = reload_order[j];
5162 /* Ignore reloads that got marked inoperative. */
5163 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5166 /* If find_reloads chose a to use reload_in or reload_out as a reload
5167 register, we don't need to chose one. Otherwise, try even if it found
5168 one since we might save an insn if we find the value lying around. */
5169 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
5170 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
5171 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
5174 #if 0 /* No longer needed for correct operation.
5175 It might give better code, or might not; worth an experiment? */
5176 /* If this is an optional reload, we can't inherit from earlier insns
5177 until we are sure that any non-optional reloads have been allocated.
5178 The following code takes advantage of the fact that optional reloads
5179 are at the end of reload_order. */
5180 if (reload_optional[r] != 0)
5181 for (i = 0; i < j; i++)
5182 if ((reload_out[reload_order[i]] != 0
5183 || reload_in[reload_order[i]] != 0
5184 || reload_secondary_p[reload_order[i]])
5185 && ! reload_optional[reload_order[i]]
5186 && reload_reg_rtx[reload_order[i]] == 0)
5187 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
5190 /* First see if this pseudo is already available as reloaded
5191 for a previous insn. We cannot try to inherit for reloads
5192 that are smaller than the maximum number of registers needed
5193 for groups unless the register we would allocate cannot be used
5196 We could check here to see if this is a secondary reload for
5197 an object that is already in a register of the desired class.
5198 This would avoid the need for the secondary reload register.
5199 But this is complex because we can't easily determine what
5200 objects might want to be loaded via this reload. So let a register
5201 be allocated here. In `emit_reload_insns' we suppress one of the
5202 loads in the case described above. */
5206 register int regno = -1;
5207 enum machine_mode mode;
5209 if (reload_in[r] == 0)
5211 else if (GET_CODE (reload_in[r]) == REG)
5213 regno = REGNO (reload_in[r]);
5214 mode = GET_MODE (reload_in[r]);
5216 else if (GET_CODE (reload_in_reg[r]) == REG)
5218 regno = REGNO (reload_in_reg[r]);
5219 mode = GET_MODE (reload_in_reg[r]);
5222 /* This won't work, since REGNO can be a pseudo reg number.
5223 Also, it takes much more hair to keep track of all the things
5224 that can invalidate an inherited reload of part of a pseudoreg. */
5225 else if (GET_CODE (reload_in[r]) == SUBREG
5226 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
5227 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
5230 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5232 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
5234 if (reg_reloaded_contents[i] == regno
5235 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
5236 >= GET_MODE_SIZE (mode))
5237 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
5238 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5240 && (reload_nregs[r] == max_group_size
5241 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5243 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
5244 reload_when_needed[r])
5245 && reload_reg_free_before_p (spill_regs[i],
5247 reload_when_needed[r]))
5249 /* If a group is needed, verify that all the subsequent
5250 registers still have their values intact. */
5252 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5255 for (k = 1; k < nr; k++)
5256 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
5264 /* We found a register that contains the
5265 value we need. If this register is the
5266 same as an `earlyclobber' operand of the
5267 current insn, just mark it as a place to
5268 reload from since we can't use it as the
5269 reload register itself. */
5271 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5272 if (reg_overlap_mentioned_for_reload_p
5273 (reg_last_reload_reg[regno],
5274 reload_earlyclobbers[i1]))
5277 if (i1 != n_earlyclobbers
5278 /* Don't really use the inherited spill reg
5279 if we need it wider than we've got it. */
5280 || (GET_MODE_SIZE (reload_mode[r])
5281 > GET_MODE_SIZE (mode)))
5282 reload_override_in[r] = reg_last_reload_reg[regno];
5286 /* We can use this as a reload reg. */
5287 /* Mark the register as in use for this part of
5289 mark_reload_reg_in_use (spill_regs[i],
5291 reload_when_needed[r],
5293 reload_reg_rtx[r] = reg_last_reload_reg[regno];
5294 reload_inherited[r] = 1;
5295 reload_inheritance_insn[r]
5296 = reg_reloaded_insn[i];
5297 reload_spill_index[r] = i;
5298 for (k = 0; k < nr; k++)
5299 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5307 /* Here's another way to see if the value is already lying around. */
5309 && reload_in[r] != 0
5310 && ! reload_inherited[r]
5311 && reload_out[r] == 0
5312 && (CONSTANT_P (reload_in[r])
5313 || GET_CODE (reload_in[r]) == PLUS
5314 || GET_CODE (reload_in[r]) == REG
5315 || GET_CODE (reload_in[r]) == MEM)
5316 && (reload_nregs[r] == max_group_size
5317 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
5320 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
5321 -1, NULL_PTR, 0, reload_mode[r]);
5326 if (GET_CODE (equiv) == REG)
5327 regno = REGNO (equiv);
5328 else if (GET_CODE (equiv) == SUBREG)
5330 /* This must be a SUBREG of a hard register.
5331 Make a new REG since this might be used in an
5332 address and not all machines support SUBREGs
5334 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5335 equiv = gen_rtx (REG, reload_mode[r], regno);
5341 /* If we found a spill reg, reject it unless it is free
5342 and of the desired class. */
5344 && ((spill_reg_order[regno] >= 0
5345 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5346 reload_when_needed[r]))
5347 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5351 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5354 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5357 /* We found a register that contains the value we need.
5358 If this register is the same as an `earlyclobber' operand
5359 of the current insn, just mark it as a place to reload from
5360 since we can't use it as the reload register itself. */
5363 for (i = 0; i < n_earlyclobbers; i++)
5364 if (reg_overlap_mentioned_for_reload_p (equiv,
5365 reload_earlyclobbers[i]))
5367 reload_override_in[r] = equiv;
5372 /* JRV: If the equiv register we have found is
5373 explicitly clobbered in the current insn, mark but
5374 don't use, as above. */
5376 if (equiv != 0 && regno_clobbered_p (regno, insn))
5378 reload_override_in[r] = equiv;
5382 /* If we found an equivalent reg, say no code need be generated
5383 to load it, and use it as our reload reg. */
5384 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5386 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
5388 reload_reg_rtx[r] = equiv;
5389 reload_inherited[r] = 1;
5391 /* If any of the hard registers in EQUIV are spill
5392 registers, mark them as in use for this insn. */
5393 for (k = 0; k < nr; k++)
5395 i = spill_reg_order[regno + k];
5398 mark_reload_reg_in_use (regno, reload_opnum[r],
5399 reload_when_needed[r],
5401 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5408 /* If we found a register to use already, or if this is an optional
5409 reload, we are done. */
5410 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5413 #if 0 /* No longer needed for correct operation. Might or might not
5414 give better code on the average. Want to experiment? */
5416 /* See if there is a later reload that has a class different from our
5417 class that intersects our class or that requires less register
5418 than our reload. If so, we must allocate a register to this
5419 reload now, since that reload might inherit a previous reload
5420 and take the only available register in our class. Don't do this
5421 for optional reloads since they will force all previous reloads
5422 to be allocated. Also don't do this for reloads that have been
5425 for (i = j + 1; i < n_reloads; i++)
5427 int s = reload_order[i];
5429 if ((reload_in[s] == 0 && reload_out[s] == 0
5430 && ! reload_secondary_p[s])
5431 || reload_optional[s])
5434 if ((reload_reg_class[s] != reload_reg_class[r]
5435 && reg_classes_intersect_p (reload_reg_class[r],
5436 reload_reg_class[s]))
5437 || reload_nregs[s] < reload_nregs[r])
5444 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5448 /* Now allocate reload registers for anything non-optional that
5449 didn't get one yet. */
5450 for (j = 0; j < n_reloads; j++)
5452 register int r = reload_order[j];
5454 /* Ignore reloads that got marked inoperative. */
5455 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5458 /* Skip reloads that already have a register allocated or are
5460 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5463 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5467 /* If that loop got all the way, we have won. */
5472 /* Loop around and try without any inheritance. */
5473 /* First undo everything done by the failed attempt
5474 to allocate with inheritance. */
5475 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
5476 sizeof reload_reg_rtx);
5477 bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
5478 sizeof reload_inherited);
5479 bcopy ((char *) save_reload_inheritance_insn,
5480 (char *) reload_inheritance_insn,
5481 sizeof reload_inheritance_insn);
5482 bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
5483 sizeof reload_override_in);
5484 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
5485 sizeof reload_spill_index);
5486 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5487 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5488 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5489 save_reload_reg_used_in_op_addr);
5490 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
5491 save_reload_reg_used_in_op_addr_reload);
5492 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5493 save_reload_reg_used_in_insn);
5494 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5495 save_reload_reg_used_in_other_addr);
5497 for (i = 0; i < reload_n_operands; i++)
5499 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5500 save_reload_reg_used_in_input[i]);
5501 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5502 save_reload_reg_used_in_output[i]);
5503 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5504 save_reload_reg_used_in_input_addr[i]);
5505 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5506 save_reload_reg_used_in_output_addr[i]);
5510 /* If we thought we could inherit a reload, because it seemed that
5511 nothing else wanted the same reload register earlier in the insn,
5512 verify that assumption, now that all reloads have been assigned. */
5514 for (j = 0; j < n_reloads; j++)
5516 register int r = reload_order[j];
5518 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5519 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5521 reload_when_needed[r]))
5522 reload_inherited[r] = 0;
5524 /* If we found a better place to reload from,
5525 validate it in the same fashion, if it is a reload reg. */
5526 if (reload_override_in[r]
5527 && (GET_CODE (reload_override_in[r]) == REG
5528 || GET_CODE (reload_override_in[r]) == SUBREG))
5530 int regno = true_regnum (reload_override_in[r]);
5531 if (spill_reg_order[regno] >= 0
5532 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5533 reload_when_needed[r]))
5534 reload_override_in[r] = 0;
5538 /* Now that reload_override_in is known valid,
5539 actually override reload_in. */
5540 for (j = 0; j < n_reloads; j++)
5541 if (reload_override_in[j])
5542 reload_in[j] = reload_override_in[j];
5544 /* If this reload won't be done because it has been cancelled or is
5545 optional and not inherited, clear reload_reg_rtx so other
5546 routines (such as subst_reloads) don't get confused. */
5547 for (j = 0; j < n_reloads; j++)
5548 if (reload_reg_rtx[j] != 0
5549 && ((reload_optional[j] && ! reload_inherited[j])
5550 || (reload_in[j] == 0 && reload_out[j] == 0
5551 && ! reload_secondary_p[j])))
5553 int regno = true_regnum (reload_reg_rtx[j]);
5555 if (spill_reg_order[regno] >= 0)
5556 clear_reload_reg_in_use (regno, reload_opnum[j],
5557 reload_when_needed[j], reload_mode[j]);
5558 reload_reg_rtx[j] = 0;
5561 /* Record which pseudos and which spill regs have output reloads. */
5562 for (j = 0; j < n_reloads; j++)
5564 register int r = reload_order[j];
5566 i = reload_spill_index[r];
5568 /* I is nonneg if this reload used one of the spill regs.
5569 If reload_reg_rtx[r] is 0, this is an optional reload
5570 that we opted to ignore. */
5571 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5572 && reload_reg_rtx[r] != 0)
5574 register int nregno = REGNO (reload_out[r]);
5577 if (nregno < FIRST_PSEUDO_REGISTER)
5578 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5581 reg_has_output_reload[nregno + nr] = 1;
5585 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5587 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5590 if (reload_when_needed[r] != RELOAD_OTHER
5591 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5592 && reload_when_needed[r] != RELOAD_FOR_INSN)
5598 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5599 reloads of the same item for fear that we might not have enough reload
5600 registers. However, normally they will get the same reload register
5601 and hence actually need not be loaded twice.
5603 Here we check for the most common case of this phenomenon: when we have
5604 a number of reloads for the same object, each of which were allocated
5605 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5606 reload, and is not modified in the insn itself. If we find such,
5607 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5608 This will not increase the number of spill registers needed and will
5609 prevent redundant code. */
5611 #ifdef SMALL_REGISTER_CLASSES
5614 merge_assigned_reloads (insn)
5619 /* Scan all the reloads looking for ones that only load values and
5620 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5621 assigned and not modified by INSN. */
5623 for (i = 0; i < n_reloads; i++)
5625 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5626 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5627 || reg_set_p (reload_reg_rtx[i], insn))
5630 /* Look at all other reloads. Ensure that the only use of this
5631 reload_reg_rtx is in a reload that just loads the same value
5632 as we do. Note that any secondary reloads must be of the identical
5633 class since the values, modes, and result registers are the
5634 same, so we need not do anything with any secondary reloads. */
5636 for (j = 0; j < n_reloads; j++)
5638 if (i == j || reload_reg_rtx[j] == 0
5639 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5643 /* If the reload regs aren't exactly the same (e.g, different modes)
5644 or if the values are different, we can't merge anything with this
5647 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5648 || reload_out[j] != 0 || reload_in[j] == 0
5649 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5653 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5654 we, in fact, found any matching reloads. */
5658 for (j = 0; j < n_reloads; j++)
5659 if (i != j && reload_reg_rtx[j] != 0
5660 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5662 reload_when_needed[i] = RELOAD_OTHER;
5664 transfer_replacements (i, j);
5667 /* If this is now RELOAD_OTHER, look for any reloads that load
5668 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5669 if they were for inputs, RELOAD_OTHER for outputs. Note that
5670 this test is equivalent to looking for reloads for this operand
5673 if (reload_when_needed[i] == RELOAD_OTHER)
5674 for (j = 0; j < n_reloads; j++)
5675 if (reload_in[j] != 0
5676 && reload_when_needed[i] != RELOAD_OTHER
5677 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5679 reload_when_needed[j]
5680 = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5681 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER;
5685 #endif /* SMALL_RELOAD_CLASSES */
5687 /* Output insns to reload values in and out of the chosen reload regs. */
5690 emit_reload_insns (insn)
5694 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5695 rtx other_input_address_reload_insns = 0;
5696 rtx other_input_reload_insns = 0;
5697 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5698 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5699 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5700 rtx operand_reload_insns = 0;
5701 rtx other_operand_reload_insns = 0;
5702 rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5703 rtx following_insn = NEXT_INSN (insn);
5704 rtx before_insn = insn;
5706 /* Values to be put in spill_reg_store are put here first. */
5707 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5709 for (j = 0; j < reload_n_operands; j++)
5710 input_reload_insns[j] = input_address_reload_insns[j]
5711 = output_reload_insns[j] = output_address_reload_insns[j]
5712 = other_output_reload_insns[j] = 0;
5714 /* Now output the instructions to copy the data into and out of the
5715 reload registers. Do these in the order that the reloads were reported,
5716 since reloads of base and index registers precede reloads of operands
5717 and the operands may need the base and index registers reloaded. */
5719 for (j = 0; j < n_reloads; j++)
5722 rtx oldequiv_reg = 0;
5723 rtx this_reload_insn = 0;
5725 if (reload_spill_index[j] >= 0)
5726 new_spill_reg_store[reload_spill_index[j]] = 0;
5729 if (old != 0 && ! reload_inherited[j]
5730 && ! rtx_equal_p (reload_reg_rtx[j], old)
5731 && reload_reg_rtx[j] != 0)
5733 register rtx reloadreg = reload_reg_rtx[j];
5735 enum machine_mode mode;
5738 /* Determine the mode to reload in.
5739 This is very tricky because we have three to choose from.
5740 There is the mode the insn operand wants (reload_inmode[J]).
5741 There is the mode of the reload register RELOADREG.
5742 There is the intrinsic mode of the operand, which we could find
5743 by stripping some SUBREGs.
5744 It turns out that RELOADREG's mode is irrelevant:
5745 we can change that arbitrarily.
5747 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5748 then the reload reg may not support QImode moves, so use SImode.
5749 If foo is in memory due to spilling a pseudo reg, this is safe,
5750 because the QImode value is in the least significant part of a
5751 slot big enough for a SImode. If foo is some other sort of
5752 memory reference, then it is impossible to reload this case,
5753 so previous passes had better make sure this never happens.
5755 Then consider a one-word union which has SImode and one of its
5756 members is a float, being fetched as (SUBREG:SF union:SI).
5757 We must fetch that as SFmode because we could be loading into
5758 a float-only register. In this case OLD's mode is correct.
5760 Consider an immediate integer: it has VOIDmode. Here we need
5761 to get a mode from something else.
5763 In some cases, there is a fourth mode, the operand's
5764 containing mode. If the insn specifies a containing mode for
5765 this operand, it overrides all others.
5767 I am not sure whether the algorithm here is always right,
5768 but it does the right things in those cases. */
5770 mode = GET_MODE (old);
5771 if (mode == VOIDmode)
5772 mode = reload_inmode[j];
5774 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5775 /* If we need a secondary register for this operation, see if
5776 the value is already in a register in that class. Don't
5777 do this if the secondary register will be used as a scratch
5780 if (reload_secondary_in_reload[j] >= 0
5781 && reload_secondary_in_icode[j] == CODE_FOR_nothing
5784 = find_equiv_reg (old, insn,
5785 reload_reg_class[reload_secondary_in_reload[j]],
5786 -1, NULL_PTR, 0, mode);
5789 /* If reloading from memory, see if there is a register
5790 that already holds the same value. If so, reload from there.
5791 We can pass 0 as the reload_reg_p argument because
5792 any other reload has either already been emitted,
5793 in which case find_equiv_reg will see the reload-insn,
5794 or has yet to be emitted, in which case it doesn't matter
5795 because we will use this equiv reg right away. */
5797 if (oldequiv == 0 && optimize
5798 && (GET_CODE (old) == MEM
5799 || (GET_CODE (old) == REG
5800 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5801 && reg_renumber[REGNO (old)] < 0)))
5802 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5803 -1, NULL_PTR, 0, mode);
5807 int regno = true_regnum (oldequiv);
5809 /* If OLDEQUIV is a spill register, don't use it for this
5810 if any other reload needs it at an earlier stage of this insn
5811 or at this stage. */
5812 if (spill_reg_order[regno] >= 0
5813 && (! reload_reg_free_p (regno, reload_opnum[j],
5814 reload_when_needed[j])
5815 || ! reload_reg_free_before_p (regno, reload_opnum[j],
5816 reload_when_needed[j])))
5819 /* If OLDEQUIV is not a spill register,
5820 don't use it if any other reload wants it. */
5821 if (spill_reg_order[regno] < 0)
5824 for (k = 0; k < n_reloads; k++)
5825 if (reload_reg_rtx[k] != 0 && k != j
5826 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
5834 /* If it is no cheaper to copy from OLDEQUIV into the
5835 reload register than it would be to move from memory,
5836 don't use it. Likewise, if we need a secondary register
5840 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
5841 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5842 reload_reg_class[j])
5843 >= MEMORY_MOVE_COST (mode)))
5844 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5845 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5849 #ifdef SECONDARY_MEMORY_NEEDED
5850 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
5851 REGNO_REG_CLASS (regno),
5860 else if (GET_CODE (oldequiv) == REG)
5861 oldequiv_reg = oldequiv;
5862 else if (GET_CODE (oldequiv) == SUBREG)
5863 oldequiv_reg = SUBREG_REG (oldequiv);
5865 /* If we are reloading from a register that was recently stored in
5866 with an output-reload, see if we can prove there was
5867 actually no need to store the old value in it. */
5869 if (optimize && GET_CODE (oldequiv) == REG
5870 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
5871 && spill_reg_order[REGNO (oldequiv)] >= 0
5872 && spill_reg_store[spill_reg_order[REGNO (oldequiv)]] != 0
5873 && find_reg_note (insn, REG_DEAD, reload_in[j])
5874 /* This is unsafe if operand occurs more than once in current
5875 insn. Perhaps some occurrences weren't reloaded. */
5876 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5877 delete_output_reload
5878 (insn, j, spill_reg_store[spill_reg_order[REGNO (oldequiv)]]);
5880 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
5881 then load RELOADREG from OLDEQUIV. Note that we cannot use
5882 gen_lowpart_common since it can do the wrong thing when
5883 RELOADREG has a multi-word mode. Note that RELOADREG
5884 must always be a REG here. */
5886 if (GET_MODE (reloadreg) != mode)
5887 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5888 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
5889 oldequiv = SUBREG_REG (oldequiv);
5890 if (GET_MODE (oldequiv) != VOIDmode
5891 && mode != GET_MODE (oldequiv))
5892 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
5894 /* Switch to the right place to emit the reload insns. */
5895 switch (reload_when_needed[j])
5898 where = &other_input_reload_insns;
5900 case RELOAD_FOR_INPUT:
5901 where = &input_reload_insns[reload_opnum[j]];
5903 case RELOAD_FOR_INPUT_ADDRESS:
5904 where = &input_address_reload_insns[reload_opnum[j]];
5906 case RELOAD_FOR_OUTPUT_ADDRESS:
5907 where = &output_address_reload_insns[reload_opnum[j]];
5909 case RELOAD_FOR_OPERAND_ADDRESS:
5910 where = &operand_reload_insns;
5912 case RELOAD_FOR_OPADDR_ADDR:
5913 where = &other_operand_reload_insns;
5915 case RELOAD_FOR_OTHER_ADDRESS:
5916 where = &other_input_address_reload_insns;
5922 push_to_sequence (*where);
5925 /* Auto-increment addresses must be reloaded in a special way. */
5926 if (GET_CODE (oldequiv) == POST_INC
5927 || GET_CODE (oldequiv) == POST_DEC
5928 || GET_CODE (oldequiv) == PRE_INC
5929 || GET_CODE (oldequiv) == PRE_DEC)
5931 /* We are not going to bother supporting the case where a
5932 incremented register can't be copied directly from
5933 OLDEQUIV since this seems highly unlikely. */
5934 if (reload_secondary_in_reload[j] >= 0)
5936 /* Prevent normal processing of this reload. */
5938 /* Output a special code sequence for this case. */
5939 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
5942 /* If we are reloading a pseudo-register that was set by the previous
5943 insn, see if we can get rid of that pseudo-register entirely
5944 by redirecting the previous insn into our reload register. */
5946 else if (optimize && GET_CODE (old) == REG
5947 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5948 && dead_or_set_p (insn, old)
5949 /* This is unsafe if some other reload
5950 uses the same reg first. */
5951 && reload_reg_free_before_p (REGNO (reloadreg),
5953 reload_when_needed[j]))
5955 rtx temp = PREV_INSN (insn);
5956 while (temp && GET_CODE (temp) == NOTE)
5957 temp = PREV_INSN (temp);
5959 && GET_CODE (temp) == INSN
5960 && GET_CODE (PATTERN (temp)) == SET
5961 && SET_DEST (PATTERN (temp)) == old
5962 /* Make sure we can access insn_operand_constraint. */
5963 && asm_noperands (PATTERN (temp)) < 0
5964 /* This is unsafe if prev insn rejects our reload reg. */
5965 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
5967 /* This is unsafe if operand occurs more than once in current
5968 insn. Perhaps some occurrences aren't reloaded. */
5969 && count_occurrences (PATTERN (insn), old) == 1
5970 /* Don't risk splitting a matching pair of operands. */
5971 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
5973 /* Store into the reload register instead of the pseudo. */
5974 SET_DEST (PATTERN (temp)) = reloadreg;
5975 /* If these are the only uses of the pseudo reg,
5976 pretend for GDB it lives in the reload reg we used. */
5977 if (reg_n_deaths[REGNO (old)] == 1
5978 && reg_n_sets[REGNO (old)] == 1)
5980 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
5981 alter_reg (REGNO (old), -1);
5987 /* We can't do that, so output an insn to load RELOADREG. */
5991 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5992 rtx second_reload_reg = 0;
5993 enum insn_code icode;
5995 /* If we have a secondary reload, pick up the secondary register
5996 and icode, if any. If OLDEQUIV and OLD are different or
5997 if this is an in-out reload, recompute whether or not we
5998 still need a secondary register and what the icode should
5999 be. If we still need a secondary register and the class or
6000 icode is different, go back to reloading from OLD if using
6001 OLDEQUIV means that we got the wrong type of register. We
6002 cannot have different class or icode due to an in-out reload
6003 because we don't make such reloads when both the input and
6004 output need secondary reload registers. */
6006 if (reload_secondary_in_reload[j] >= 0)
6008 int secondary_reload = reload_secondary_in_reload[j];
6009 rtx real_oldequiv = oldequiv;
6012 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6013 and similarly for OLD.
6014 See comments in get_secondary_reload in reload.c. */
6015 if (GET_CODE (oldequiv) == REG
6016 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6017 && reg_equiv_mem[REGNO (oldequiv)] != 0)
6018 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
6020 if (GET_CODE (old) == REG
6021 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6022 && reg_equiv_mem[REGNO (old)] != 0)
6023 real_old = reg_equiv_mem[REGNO (old)];
6025 second_reload_reg = reload_reg_rtx[secondary_reload];
6026 icode = reload_secondary_in_icode[j];
6028 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6029 || (reload_in[j] != 0 && reload_out[j] != 0))
6031 enum reg_class new_class
6032 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
6033 mode, real_oldequiv);
6035 if (new_class == NO_REGS)
6036 second_reload_reg = 0;
6039 enum insn_code new_icode;
6040 enum machine_mode new_mode;
6042 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6043 REGNO (second_reload_reg)))
6044 oldequiv = old, real_oldequiv = real_old;
6047 new_icode = reload_in_optab[(int) mode];
6048 if (new_icode != CODE_FOR_nothing
6049 && ((insn_operand_predicate[(int) new_icode][0]
6050 && ! ((*insn_operand_predicate[(int) new_icode][0])
6052 || (insn_operand_predicate[(int) new_icode][1]
6053 && ! ((*insn_operand_predicate[(int) new_icode][1])
6054 (real_oldequiv, mode)))))
6055 new_icode = CODE_FOR_nothing;
6057 if (new_icode == CODE_FOR_nothing)
6060 new_mode = insn_operand_mode[(int) new_icode][2];
6062 if (GET_MODE (second_reload_reg) != new_mode)
6064 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6066 oldequiv = old, real_oldequiv = real_old;
6069 = gen_rtx (REG, new_mode,
6070 REGNO (second_reload_reg));
6076 /* If we still need a secondary reload register, check
6077 to see if it is being used as a scratch or intermediate
6078 register and generate code appropriately. If we need
6079 a scratch register, use REAL_OLDEQUIV since the form of
6080 the insn may depend on the actual address if it is
6083 if (second_reload_reg)
6085 if (icode != CODE_FOR_nothing)
6087 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6088 second_reload_reg));
6093 /* See if we need a scratch register to load the
6094 intermediate register (a tertiary reload). */
6095 enum insn_code tertiary_icode
6096 = reload_secondary_in_icode[secondary_reload];
6098 if (tertiary_icode != CODE_FOR_nothing)
6100 rtx third_reload_reg
6101 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
6103 emit_insn ((GEN_FCN (tertiary_icode)
6104 (second_reload_reg, real_oldequiv,
6105 third_reload_reg)));
6108 gen_reload (second_reload_reg, oldequiv,
6110 reload_when_needed[j]);
6112 oldequiv = second_reload_reg;
6118 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6119 gen_reload (reloadreg, oldequiv, reload_opnum[j],
6120 reload_when_needed[j]);
6122 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
6123 /* We may have to make a REG_DEAD note for the secondary reload
6124 register in the insns we just made. Find the last insn that
6125 mentioned the register. */
6126 if (! special && second_reload_reg
6127 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
6131 for (prev = get_last_insn (); prev;
6132 prev = PREV_INSN (prev))
6133 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
6134 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
6137 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
6146 this_reload_insn = get_last_insn ();
6147 /* End this sequence. */
6148 *where = get_insns ();
6152 /* Add a note saying the input reload reg
6153 dies in this insn, if anyone cares. */
6154 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6156 && reload_reg_rtx[j] != old
6157 && reload_reg_rtx[j] != 0
6158 && reload_out[j] == 0
6159 && ! reload_inherited[j]
6160 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
6162 register rtx reloadreg = reload_reg_rtx[j];
6165 /* We can't abort here because we need to support this for sched.c.
6166 It's not terrible to miss a REG_DEAD note, but we should try
6167 to figure out how to do this correctly. */
6168 /* The code below is incorrect for address-only reloads. */
6169 if (reload_when_needed[j] != RELOAD_OTHER
6170 && reload_when_needed[j] != RELOAD_FOR_INPUT)
6174 /* Add a death note to this insn, for an input reload. */
6176 if ((reload_when_needed[j] == RELOAD_OTHER
6177 || reload_when_needed[j] == RELOAD_FOR_INPUT)
6178 && ! dead_or_set_p (insn, reloadreg))
6180 = gen_rtx (EXPR_LIST, REG_DEAD,
6181 reloadreg, REG_NOTES (insn));
6184 /* When we inherit a reload, the last marked death of the reload reg
6185 may no longer really be a death. */
6186 if (reload_reg_rtx[j] != 0
6187 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
6188 && reload_inherited[j])
6190 /* Handle inheriting an output reload.
6191 Remove the death note from the output reload insn. */
6192 if (reload_spill_index[j] >= 0
6193 && GET_CODE (reload_in[j]) == REG
6194 && spill_reg_store[reload_spill_index[j]] != 0
6195 && find_regno_note (spill_reg_store[reload_spill_index[j]],
6196 REG_DEAD, REGNO (reload_reg_rtx[j])))
6197 remove_death (REGNO (reload_reg_rtx[j]),
6198 spill_reg_store[reload_spill_index[j]]);
6199 /* Likewise for input reloads that were inherited. */
6200 else if (reload_spill_index[j] >= 0
6201 && GET_CODE (reload_in[j]) == REG
6202 && spill_reg_store[reload_spill_index[j]] == 0
6203 && reload_inheritance_insn[j] != 0
6204 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
6205 REGNO (reload_reg_rtx[j])))
6206 remove_death (REGNO (reload_reg_rtx[j]),
6207 reload_inheritance_insn[j]);
6212 /* We got this register from find_equiv_reg.
6213 Search back for its last death note and get rid of it.
6214 But don't search back too far.
6215 Don't go past a place where this reg is set,
6216 since a death note before that remains valid. */
6217 for (prev = PREV_INSN (insn);
6218 prev && GET_CODE (prev) != CODE_LABEL;
6219 prev = PREV_INSN (prev))
6220 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6221 && dead_or_set_p (prev, reload_reg_rtx[j]))
6223 if (find_regno_note (prev, REG_DEAD,
6224 REGNO (reload_reg_rtx[j])))
6225 remove_death (REGNO (reload_reg_rtx[j]), prev);
6231 /* We might have used find_equiv_reg above to choose an alternate
6232 place from which to reload. If so, and it died, we need to remove
6233 that death and move it to one of the insns we just made. */
6235 if (oldequiv_reg != 0
6236 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
6240 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
6241 prev = PREV_INSN (prev))
6242 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
6243 && dead_or_set_p (prev, oldequiv_reg))
6245 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
6247 for (prev1 = this_reload_insn;
6248 prev1; prev1 = PREV_INSN (prev1))
6249 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
6250 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
6253 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
6258 remove_death (REGNO (oldequiv_reg), prev);
6265 /* If we are reloading a register that was recently stored in with an
6266 output-reload, see if we can prove there was
6267 actually no need to store the old value in it. */
6269 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
6270 && reload_in[j] != 0
6271 && GET_CODE (reload_in[j]) == REG
6273 /* There doesn't seem to be any reason to restrict this to pseudos
6274 and doing so loses in the case where we are copying from a
6275 register of the wrong class. */
6276 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
6278 && spill_reg_store[reload_spill_index[j]] != 0
6279 /* This is unsafe if some other reload uses the same reg first. */
6280 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
6281 reload_opnum[j], reload_when_needed[j])
6282 && dead_or_set_p (insn, reload_in[j])
6283 /* This is unsafe if operand occurs more than once in current
6284 insn. Perhaps some occurrences weren't reloaded. */
6285 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
6286 delete_output_reload (insn, j,
6287 spill_reg_store[reload_spill_index[j]]);
6289 /* Input-reloading is done. Now do output-reloading,
6290 storing the value from the reload-register after the main insn
6291 if reload_out[j] is nonzero.
6293 ??? At some point we need to support handling output reloads of
6294 JUMP_INSNs or insns that set cc0. */
6295 old = reload_out[j];
6297 && reload_reg_rtx[j] != old
6298 && reload_reg_rtx[j] != 0)
6300 register rtx reloadreg = reload_reg_rtx[j];
6301 register rtx second_reloadreg = 0;
6303 enum machine_mode mode;
6306 /* An output operand that dies right away does need a reload,
6307 but need not be copied from it. Show the new location in the
6309 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6310 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6312 XEXP (note, 0) = reload_reg_rtx[j];
6315 /* Likewise for a SUBREG of an operand that dies. */
6316 else if (GET_CODE (old) == SUBREG
6317 && GET_CODE (SUBREG_REG (old)) == REG
6318 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6321 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6325 else if (GET_CODE (old) == SCRATCH)
6326 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6327 but we don't want to make an output reload. */
6331 /* Strip off of OLD any size-increasing SUBREGs such as
6332 (SUBREG:SI foo:QI 0). */
6334 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
6335 && (GET_MODE_SIZE (GET_MODE (old))
6336 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
6337 old = SUBREG_REG (old);
6340 /* If is a JUMP_INSN, we can't support output reloads yet. */
6341 if (GET_CODE (insn) == JUMP_INSN)
6344 if (reload_when_needed[j] == RELOAD_OTHER)
6347 push_to_sequence (output_reload_insns[reload_opnum[j]]);
6349 /* Determine the mode to reload in.
6350 See comments above (for input reloading). */
6352 mode = GET_MODE (old);
6353 if (mode == VOIDmode)
6355 /* VOIDmode should never happen for an output. */
6356 if (asm_noperands (PATTERN (insn)) < 0)
6357 /* It's the compiler's fault. */
6358 fatal_insn ("VOIDmode on an output", insn);
6359 error_for_asm (insn, "output operand is constant in `asm'");
6360 /* Prevent crash--use something we know is valid. */
6362 old = gen_rtx (REG, mode, REGNO (reloadreg));
6365 if (GET_MODE (reloadreg) != mode)
6366 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6368 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6370 /* If we need two reload regs, set RELOADREG to the intermediate
6371 one, since it will be stored into OLD. We might need a secondary
6372 register only for an input reload, so check again here. */
6374 if (reload_secondary_out_reload[j] >= 0)
6378 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6379 && reg_equiv_mem[REGNO (old)] != 0)
6380 real_old = reg_equiv_mem[REGNO (old)];
6382 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6386 second_reloadreg = reloadreg;
6387 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
6389 /* See if RELOADREG is to be used as a scratch register
6390 or as an intermediate register. */
6391 if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
6393 emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
6394 (real_old, second_reloadreg, reloadreg)));
6399 /* See if we need both a scratch and intermediate reload
6402 int secondary_reload = reload_secondary_out_reload[j];
6403 enum insn_code tertiary_icode
6404 = reload_secondary_out_icode[secondary_reload];
6406 if (GET_MODE (reloadreg) != mode)
6407 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6409 if (tertiary_icode != CODE_FOR_nothing)
6412 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
6415 /* Copy primary reload reg to secondary reload reg.
6416 (Note that these have been swapped above, then
6417 secondary reload reg to OLD using our insn. */
6419 /* If REAL_OLD is a paradoxical SUBREG, remove it
6420 and try to put the opposite SUBREG on
6422 if (GET_CODE (real_old) == SUBREG
6423 && (GET_MODE_SIZE (GET_MODE (real_old))
6424 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6425 && 0 != (tem = gen_lowpart_common
6426 (GET_MODE (SUBREG_REG (real_old)),
6428 real_old = SUBREG_REG (real_old), reloadreg = tem;
6430 gen_reload (reloadreg, second_reloadreg,
6431 reload_opnum[j], reload_when_needed[j]);
6432 emit_insn ((GEN_FCN (tertiary_icode)
6433 (real_old, reloadreg, third_reloadreg)));
6438 /* Copy between the reload regs here and then to
6441 gen_reload (reloadreg, second_reloadreg,
6442 reload_opnum[j], reload_when_needed[j]);
6448 /* Output the last reload insn. */
6450 gen_reload (old, reloadreg, reload_opnum[j],
6451 reload_when_needed[j]);
6453 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6454 /* If final will look at death notes for this reg,
6455 put one on the last output-reload insn to use it. Similarly
6456 for any secondary register. */
6457 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6458 for (p = get_last_insn (); p; p = PREV_INSN (p))
6459 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6460 && reg_overlap_mentioned_for_reload_p (reloadreg,
6462 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6463 reloadreg, REG_NOTES (p));
6465 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6466 if (! special && second_reloadreg
6467 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6468 for (p = get_last_insn (); p; p = PREV_INSN (p))
6469 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6470 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6472 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6473 second_reloadreg, REG_NOTES (p));
6476 /* Look at all insns we emitted, just to be safe. */
6477 for (p = get_insns (); p; p = NEXT_INSN (p))
6478 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6480 /* If this output reload doesn't come from a spill reg,
6481 clear any memory of reloaded copies of the pseudo reg.
6482 If this output reload comes from a spill reg,
6483 reg_has_output_reload will make this do nothing. */
6484 note_stores (PATTERN (p), forget_old_reloads_1);
6486 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p))
6487 && reload_spill_index[j] >= 0)
6488 new_spill_reg_store[reload_spill_index[j]] = p;
6491 if (reload_when_needed[j] == RELOAD_OTHER)
6493 emit_insns (other_output_reload_insns[reload_opnum[j]]);
6494 other_output_reload_insns[reload_opnum[j]] = get_insns ();
6497 output_reload_insns[reload_opnum[j]] = get_insns ();
6503 /* Now write all the insns we made for reloads in the order expected by
6504 the allocation functions. Prior to the insn being reloaded, we write
6505 the following reloads:
6507 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6509 RELOAD_OTHER reloads.
6511 For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by
6512 the RELOAD_FOR_INPUT reload for the operand.
6514 RELOAD_FOR_OPADDR_ADDRS reloads.
6516 RELOAD_FOR_OPERAND_ADDRESS reloads.
6518 After the insn being reloaded, we write the following:
6520 For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by
6521 the RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6522 reloads for the operand. The RELOAD_OTHER output reloads are output
6523 in descending order by reload number. */
6525 emit_insns_before (other_input_address_reload_insns, before_insn);
6526 emit_insns_before (other_input_reload_insns, before_insn);
6528 for (j = 0; j < reload_n_operands; j++)
6530 emit_insns_before (input_address_reload_insns[j], before_insn);
6531 emit_insns_before (input_reload_insns[j], before_insn);
6534 emit_insns_before (other_operand_reload_insns, before_insn);
6535 emit_insns_before (operand_reload_insns, before_insn);
6537 for (j = 0; j < reload_n_operands; j++)
6539 emit_insns_before (output_address_reload_insns[j], following_insn);
6540 emit_insns_before (output_reload_insns[j], following_insn);
6541 emit_insns_before (other_output_reload_insns[j], following_insn);
6544 /* Move death notes from INSN
6545 to output-operand-address and output reload insns. */
6546 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6549 /* Loop over those insns, last ones first. */
6550 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6551 insn1 = PREV_INSN (insn1))
6552 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6554 rtx source = SET_SRC (PATTERN (insn1));
6555 rtx dest = SET_DEST (PATTERN (insn1));
6557 /* The note we will examine next. */
6558 rtx reg_notes = REG_NOTES (insn);
6559 /* The place that pointed to this note. */
6560 rtx *prev_reg_note = ®_NOTES (insn);
6562 /* If the note is for something used in the source of this
6563 reload insn, or in the output address, move the note. */
6566 rtx next_reg_notes = XEXP (reg_notes, 1);
6567 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6568 && GET_CODE (XEXP (reg_notes, 0)) == REG
6569 && ((GET_CODE (dest) != REG
6570 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6572 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6575 *prev_reg_note = next_reg_notes;
6576 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6577 REG_NOTES (insn1) = reg_notes;
6580 prev_reg_note = &XEXP (reg_notes, 1);
6582 reg_notes = next_reg_notes;
6588 /* For all the spill regs newly reloaded in this instruction,
6589 record what they were reloaded from, so subsequent instructions
6590 can inherit the reloads.
6592 Update spill_reg_store for the reloads of this insn.
6593 Copy the elements that were updated in the loop above. */
6595 for (j = 0; j < n_reloads; j++)
6597 register int r = reload_order[j];
6598 register int i = reload_spill_index[r];
6600 /* I is nonneg if this reload used one of the spill regs.
6601 If reload_reg_rtx[r] is 0, this is an optional reload
6602 that we opted to ignore. */
6604 if (i >= 0 && reload_reg_rtx[r] != 0)
6607 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6609 int part_reaches_end = 0;
6610 int all_reaches_end = 1;
6612 /* For a multi register reload, we need to check if all or part
6613 of the value lives to the end. */
6614 for (k = 0; k < nr; k++)
6616 if (reload_reg_reaches_end_p (spill_regs[i] + k, reload_opnum[r],
6617 reload_when_needed[r]))
6618 part_reaches_end = 1;
6620 all_reaches_end = 0;
6623 /* Ignore reloads that don't reach the end of the insn in
6625 if (all_reaches_end)
6627 /* First, clear out memory of what used to be in this spill reg.
6628 If consecutive registers are used, clear them all. */
6630 for (k = 0; k < nr; k++)
6632 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6633 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6636 /* Maybe the spill reg contains a copy of reload_out. */
6637 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6639 register int nregno = REGNO (reload_out[r]);
6640 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6641 : HARD_REGNO_NREGS (nregno,
6642 GET_MODE (reload_reg_rtx[r])));
6644 spill_reg_store[i] = new_spill_reg_store[i];
6645 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6647 /* If NREGNO is a hard register, it may occupy more than
6648 one register. If it does, say what is in the
6649 rest of the registers assuming that both registers
6650 agree on how many words the object takes. If not,
6651 invalidate the subsequent registers. */
6653 if (nregno < FIRST_PSEUDO_REGISTER)
6654 for (k = 1; k < nnr; k++)
6655 reg_last_reload_reg[nregno + k]
6658 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6659 REGNO (reload_reg_rtx[r]) + k)
6662 /* Now do the inverse operation. */
6663 for (k = 0; k < nr; k++)
6665 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6666 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6669 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6673 /* Maybe the spill reg contains a copy of reload_in. Only do
6674 something if there will not be an output reload for
6675 the register being reloaded. */
6676 else if (reload_out[r] == 0
6677 && reload_in[r] != 0
6678 && ((GET_CODE (reload_in[r]) == REG
6679 && ! reg_has_output_reload[REGNO (reload_in[r])])
6680 || (GET_CODE (reload_in_reg[r]) == REG
6681 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])))
6683 register int nregno;
6686 if (GET_CODE (reload_in[r]) == REG)
6687 nregno = REGNO (reload_in[r]);
6689 nregno = REGNO (reload_in_reg[r]);
6691 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6692 : HARD_REGNO_NREGS (nregno,
6693 GET_MODE (reload_reg_rtx[r])));
6695 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6697 if (nregno < FIRST_PSEUDO_REGISTER)
6698 for (k = 1; k < nnr; k++)
6699 reg_last_reload_reg[nregno + k]
6702 reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
6703 REGNO (reload_reg_rtx[r]) + k)
6706 /* Unless we inherited this reload, show we haven't
6707 recently done a store. */
6708 if (! reload_inherited[r])
6709 spill_reg_store[i] = 0;
6711 for (k = 0; k < nr; k++)
6713 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6714 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6717 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6723 /* However, if part of the reload reaches the end, then we must
6724 invalidate the old info for the part that survives to the end. */
6725 else if (part_reaches_end)
6727 for (k = 0; k < nr; k++)
6728 if (reload_reg_reaches_end_p (spill_regs[i] + k,
6730 reload_when_needed[r]))
6732 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6733 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6738 /* The following if-statement was #if 0'd in 1.34 (or before...).
6739 It's reenabled in 1.35 because supposedly nothing else
6740 deals with this problem. */
6742 /* If a register gets output-reloaded from a non-spill register,
6743 that invalidates any previous reloaded copy of it.
6744 But forget_old_reloads_1 won't get to see it, because
6745 it thinks only about the original insn. So invalidate it here. */
6746 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6748 register int nregno = REGNO (reload_out[r]);
6749 if (nregno >= FIRST_PSEUDO_REGISTER)
6750 reg_last_reload_reg[nregno] = 0;
6753 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
6755 while (num_regs-- > 0)
6756 reg_last_reload_reg[nregno + num_regs] = 0;
6762 /* Emit code to perform a reload from IN (which may be a reload register) to
6763 OUT (which may also be a reload register). IN or OUT is from operand
6764 OPNUM with reload type TYPE.
6766 Returns first insn emitted. */
6769 gen_reload (out, in, opnum, type)
6773 enum reload_type type;
6775 rtx last = get_last_insn ();
6778 /* If IN is a paradoxical SUBREG, remove it and try to put the
6779 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
6780 if (GET_CODE (in) == SUBREG
6781 && (GET_MODE_SIZE (GET_MODE (in))
6782 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
6783 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
6784 in = SUBREG_REG (in), out = tem;
6785 else if (GET_CODE (out) == SUBREG
6786 && (GET_MODE_SIZE (GET_MODE (out))
6787 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
6788 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
6789 out = SUBREG_REG (out), in = tem;
6791 /* How to do this reload can get quite tricky. Normally, we are being
6792 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
6793 register that didn't get a hard register. In that case we can just
6794 call emit_move_insn.
6796 We can also be asked to reload a PLUS that adds a register or a MEM to
6797 another register, constant or MEM. This can occur during frame pointer
6798 elimination and while reloading addresses. This case is handled by
6799 trying to emit a single insn to perform the add. If it is not valid,
6800 we use a two insn sequence.
6802 Finally, we could be called to handle an 'o' constraint by putting
6803 an address into a register. In that case, we first try to do this
6804 with a named pattern of "reload_load_address". If no such pattern
6805 exists, we just emit a SET insn and hope for the best (it will normally
6806 be valid on machines that use 'o').
6808 This entire process is made complex because reload will never
6809 process the insns we generate here and so we must ensure that
6810 they will fit their constraints and also by the fact that parts of
6811 IN might be being reloaded separately and replaced with spill registers.
6812 Because of this, we are, in some sense, just guessing the right approach
6813 here. The one listed above seems to work.
6815 ??? At some point, this whole thing needs to be rethought. */
6817 if (GET_CODE (in) == PLUS
6818 && (GET_CODE (XEXP (in, 0)) == REG
6819 || GET_CODE (XEXP (in, 0)) == SUBREG
6820 || GET_CODE (XEXP (in, 0)) == MEM)
6821 && (GET_CODE (XEXP (in, 1)) == REG
6822 || GET_CODE (XEXP (in, 1)) == SUBREG
6823 || CONSTANT_P (XEXP (in, 1))
6824 || GET_CODE (XEXP (in, 1)) == MEM))
6826 /* We need to compute the sum of a register or a MEM and another
6827 register, constant, or MEM, and put it into the reload
6828 register. The best possible way of doing this is if the machine
6829 has a three-operand ADD insn that accepts the required operands.
6831 The simplest approach is to try to generate such an insn and see if it
6832 is recognized and matches its constraints. If so, it can be used.
6834 It might be better not to actually emit the insn unless it is valid,
6835 but we need to pass the insn as an operand to `recog' and
6836 `insn_extract' and it is simpler to emit and then delete the insn if
6837 not valid than to dummy things up. */
6839 rtx op0, op1, tem, insn;
6842 op0 = find_replacement (&XEXP (in, 0));
6843 op1 = find_replacement (&XEXP (in, 1));
6845 /* Since constraint checking is strict, commutativity won't be
6846 checked, so we need to do that here to avoid spurious failure
6847 if the add instruction is two-address and the second operand
6848 of the add is the same as the reload reg, which is frequently
6849 the case. If the insn would be A = B + A, rearrange it so
6850 it will be A = A + B as constrain_operands expects. */
6852 if (GET_CODE (XEXP (in, 1)) == REG
6853 && REGNO (out) == REGNO (XEXP (in, 1)))
6854 tem = op0, op0 = op1, op1 = tem;
6856 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
6857 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
6859 insn = emit_insn (gen_rtx (SET, VOIDmode, out, in));
6860 code = recog_memoized (insn);
6864 insn_extract (insn);
6865 /* We want constrain operands to treat this insn strictly in
6866 its validity determination, i.e., the way it would after reload
6868 if (constrain_operands (code, 1))
6872 delete_insns_since (last);
6874 /* If that failed, we must use a conservative two-insn sequence.
6875 use move to copy constant, MEM, or pseudo register to the reload
6876 register since "move" will be able to handle an arbitrary operand,
6877 unlike add which can't, in general. Then add the registers.
6879 If there is another way to do this for a specific machine, a
6880 DEFINE_PEEPHOLE should be specified that recognizes the sequence
6883 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
6884 || (GET_CODE (op1) == REG
6885 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
6886 tem = op0, op0 = op1, op1 = tem;
6888 gen_reload (out, op0, opnum, type);
6890 /* If OP0 and OP1 are the same, we can use OUT for OP1.
6891 This fixes a problem on the 32K where the stack pointer cannot
6892 be used as an operand of an add insn. */
6894 if (rtx_equal_p (op0, op1))
6897 insn = emit_insn (gen_add2_insn (out, op1));
6899 /* If that failed, copy the address register to the reload register.
6900 Then add the constant to the reload register. */
6902 code = recog_memoized (insn);
6906 insn_extract (insn);
6907 /* We want constrain operands to treat this insn strictly in
6908 its validity determination, i.e., the way it would after reload
6910 if (constrain_operands (code, 1))
6914 delete_insns_since (last);
6916 gen_reload (out, op1, opnum, type);
6917 emit_insn (gen_add2_insn (out, op0));
6920 #ifdef SECONDARY_MEMORY_NEEDED
6921 /* If we need a memory location to do the move, do it that way. */
6922 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
6923 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
6924 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
6925 REGNO_REG_CLASS (REGNO (out)),
6928 /* Get the memory to use and rewrite both registers to its mode. */
6929 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
6931 if (GET_MODE (loc) != GET_MODE (out))
6932 out = gen_rtx (REG, GET_MODE (loc), REGNO (out));
6934 if (GET_MODE (loc) != GET_MODE (in))
6935 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
6937 gen_reload (loc, in, opnum, type);
6938 gen_reload (out, loc, opnum, type);
6942 /* If IN is a simple operand, use gen_move_insn. */
6943 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
6944 emit_insn (gen_move_insn (out, in));
6946 #ifdef HAVE_reload_load_address
6947 else if (HAVE_reload_load_address)
6948 emit_insn (gen_reload_load_address (out, in));
6951 /* Otherwise, just write (set OUT IN) and hope for the best. */
6953 emit_insn (gen_rtx (SET, VOIDmode, out, in));
6955 /* Return the first insn emitted.
6956 We can not just return get_last_insn, because there may have
6957 been multiple instructions emitted. Also note that gen_move_insn may
6958 emit more than one insn itself, so we can not assume that there is one
6959 insn emitted per emit_insn_before call. */
6961 return last ? NEXT_INSN (last) : get_insns ();
6964 /* Delete a previously made output-reload
6965 whose result we now believe is not needed.
6966 First we double-check.
6968 INSN is the insn now being processed.
6969 OUTPUT_RELOAD_INSN is the insn of the output reload.
6970 J is the reload-number for this insn. */
6973 delete_output_reload (insn, j, output_reload_insn)
6976 rtx output_reload_insn;
6980 /* Get the raw pseudo-register referred to. */
6982 rtx reg = reload_in[j];
6983 while (GET_CODE (reg) == SUBREG)
6984 reg = SUBREG_REG (reg);
6986 /* If the pseudo-reg we are reloading is no longer referenced
6987 anywhere between the store into it and here,
6988 and no jumps or labels intervene, then the value can get
6989 here through the reload reg alone.
6990 Otherwise, give up--return. */
6991 for (i1 = NEXT_INSN (output_reload_insn);
6992 i1 != insn; i1 = NEXT_INSN (i1))
6994 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
6996 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
6997 && reg_mentioned_p (reg, PATTERN (i1)))
7001 if (cannot_omit_stores[REGNO (reg)])
7004 /* If this insn will store in the pseudo again,
7005 the previous store can be removed. */
7006 if (reload_out[j] == reload_in[j])
7007 delete_insn (output_reload_insn);
7009 /* See if the pseudo reg has been completely replaced
7010 with reload regs. If so, delete the store insn
7011 and forget we had a stack slot for the pseudo. */
7012 else if (reg_n_deaths[REGNO (reg)] == 1
7013 && reg_basic_block[REGNO (reg)] >= 0
7014 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7018 /* We know that it was used only between here
7019 and the beginning of the current basic block.
7020 (We also know that the last use before INSN was
7021 the output reload we are thinking of deleting, but never mind that.)
7022 Search that range; see if any ref remains. */
7023 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7025 rtx set = single_set (i2);
7027 /* Uses which just store in the pseudo don't count,
7028 since if they are the only uses, they are dead. */
7029 if (set != 0 && SET_DEST (set) == reg)
7031 if (GET_CODE (i2) == CODE_LABEL
7032 || GET_CODE (i2) == JUMP_INSN)
7034 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7035 && reg_mentioned_p (reg, PATTERN (i2)))
7036 /* Some other ref remains;
7037 we can't do anything. */
7041 /* Delete the now-dead stores into this pseudo. */
7042 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7044 rtx set = single_set (i2);
7046 if (set != 0 && SET_DEST (set) == reg)
7048 /* This might be a basic block head,
7049 thus don't use delete_insn. */
7050 PUT_CODE (i2, NOTE);
7051 NOTE_SOURCE_FILE (i2) = 0;
7052 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7054 if (GET_CODE (i2) == CODE_LABEL
7055 || GET_CODE (i2) == JUMP_INSN)
7059 /* For the debugging info,
7060 say the pseudo lives in this reload reg. */
7061 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
7062 alter_reg (REGNO (reg), -1);
7066 /* Output reload-insns to reload VALUE into RELOADREG.
7067 VALUE is an autoincrement or autodecrement RTX whose operand
7068 is a register or memory location;
7069 so reloading involves incrementing that location.
7071 INC_AMOUNT is the number to increment or decrement by (always positive).
7072 This cannot be deduced from VALUE. */
7075 inc_for_reload (reloadreg, value, inc_amount)
7080 /* REG or MEM to be copied and incremented. */
7081 rtx incloc = XEXP (value, 0);
7082 /* Nonzero if increment after copying. */
7083 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7089 /* No hard register is equivalent to this register after
7090 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7091 we could inc/dec that register as well (maybe even using it for
7092 the source), but I'm not sure it's worth worrying about. */
7093 if (GET_CODE (incloc) == REG)
7094 reg_last_reload_reg[REGNO (incloc)] = 0;
7096 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7097 inc_amount = - inc_amount;
7099 inc = GEN_INT (inc_amount);
7101 /* If this is post-increment, first copy the location to the reload reg. */
7103 emit_insn (gen_move_insn (reloadreg, incloc));
7105 /* See if we can directly increment INCLOC. Use a method similar to that
7108 last = get_last_insn ();
7109 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
7110 gen_rtx (PLUS, GET_MODE (incloc),
7113 code = recog_memoized (add_insn);
7116 insn_extract (add_insn);
7117 if (constrain_operands (code, 1))
7119 /* If this is a pre-increment and we have incremented the value
7120 where it lives, copy the incremented value to RELOADREG to
7121 be used as an address. */
7124 emit_insn (gen_move_insn (reloadreg, incloc));
7130 delete_insns_since (last);
7132 /* If couldn't do the increment directly, must increment in RELOADREG.
7133 The way we do this depends on whether this is pre- or post-increment.
7134 For pre-increment, copy INCLOC to the reload register, increment it
7135 there, then save back. */
7139 emit_insn (gen_move_insn (reloadreg, incloc));
7140 emit_insn (gen_add2_insn (reloadreg, inc));
7141 emit_insn (gen_move_insn (incloc, reloadreg));
7146 Because this might be a jump insn or a compare, and because RELOADREG
7147 may not be available after the insn in an input reload, we must do
7148 the incrementation before the insn being reloaded for.
7150 We have already copied INCLOC to RELOADREG. Increment the copy in
7151 RELOADREG, save that back, then decrement RELOADREG so it has
7152 the original value. */
7154 emit_insn (gen_add2_insn (reloadreg, inc));
7155 emit_insn (gen_move_insn (incloc, reloadreg));
7156 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7162 /* Return 1 if we are certain that the constraint-string STRING allows
7163 the hard register REG. Return 0 if we can't be sure of this. */
7166 constraint_accepts_reg_p (string, reg)
7171 int regno = true_regnum (reg);
7174 /* Initialize for first alternative. */
7176 /* Check that each alternative contains `g' or `r'. */
7178 switch (c = *string++)
7181 /* If an alternative lacks `g' or `r', we lose. */
7184 /* If an alternative lacks `g' or `r', we lose. */
7187 /* Initialize for next alternative. */
7192 /* Any general reg wins for this alternative. */
7193 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7197 /* Any reg in specified class wins for this alternative. */
7199 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7201 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7207 /* Return the number of places FIND appears within X, but don't count
7208 an occurrence if some SET_DEST is FIND. */
7211 count_occurrences (x, find)
7212 register rtx x, find;
7215 register enum rtx_code code;
7216 register char *format_ptr;
7224 code = GET_CODE (x);
7239 if (SET_DEST (x) == find)
7240 return count_occurrences (SET_SRC (x), find);
7244 format_ptr = GET_RTX_FORMAT (code);
7247 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7249 switch (*format_ptr++)
7252 count += count_occurrences (XEXP (x, i), find);
7256 if (XVEC (x, i) != NULL)
7258 for (j = 0; j < XVECLEN (x, i); j++)
7259 count += count_occurrences (XVECEXP (x, i, j), find);
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