1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static regset_head reg_has_output_reload;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx *reg_equiv_invariant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
127 alternate representations of the location of pseudo reg N. */
128 rtx *reg_equiv_alt_mem_list;
130 /* Widest width in which each pseudo reg is referred to (via subreg). */
131 static unsigned int *reg_max_ref_width;
133 /* Element N is the list of insns that initialized reg N from its equivalent
134 constant or memory slot. */
136 int reg_equiv_init_size;
138 /* Vector to remember old contents of reg_renumber before spilling. */
139 static short *reg_old_renumber;
141 /* During reload_as_needed, element N contains the last pseudo regno reloaded
142 into hard register N. If that pseudo reg occupied more than one register,
143 reg_reloaded_contents points to that pseudo for each spill register in
144 use; all of these must remain set for an inheritance to occur. */
145 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
147 /* During reload_as_needed, element N contains the insn for which
148 hard register N was last used. Its contents are significant only
149 when reg_reloaded_valid is set for this register. */
150 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
152 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
153 static HARD_REG_SET reg_reloaded_valid;
154 /* Indicate if the register was dead at the end of the reload.
155 This is only valid if reg_reloaded_contents is set and valid. */
156 static HARD_REG_SET reg_reloaded_dead;
158 /* Indicate whether the register's current value is one that is not
159 safe to retain across a call, even for registers that are normally
161 static HARD_REG_SET reg_reloaded_call_part_clobbered;
163 /* Number of spill-regs so far; number of valid elements of spill_regs. */
166 /* In parallel with spill_regs, contains REG rtx's for those regs.
167 Holds the last rtx used for any given reg, or 0 if it has never
168 been used for spilling yet. This rtx is reused, provided it has
170 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
172 /* In parallel with spill_regs, contains nonzero for a spill reg
173 that was stored after the last time it was used.
174 The precise value is the insn generated to do the store. */
175 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
177 /* This is the register that was stored with spill_reg_store. This is a
178 copy of reload_out / reload_out_reg when the value was stored; if
179 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
180 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
182 /* This table is the inverse mapping of spill_regs:
183 indexed by hard reg number,
184 it contains the position of that reg in spill_regs,
185 or -1 for something that is not in spill_regs.
187 ?!? This is no longer accurate. */
188 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
190 /* This reg set indicates registers that can't be used as spill registers for
191 the currently processed insn. These are the hard registers which are live
192 during the insn, but not allocated to pseudos, as well as fixed
194 static HARD_REG_SET bad_spill_regs;
196 /* These are the hard registers that can't be used as spill register for any
197 insn. This includes registers used for user variables and registers that
198 we can't eliminate. A register that appears in this set also can't be used
199 to retry register allocation. */
200 static HARD_REG_SET bad_spill_regs_global;
202 /* Describes order of use of registers for reloading
203 of spilled pseudo-registers. `n_spills' is the number of
204 elements that are actually valid; new ones are added at the end.
206 Both spill_regs and spill_reg_order are used on two occasions:
207 once during find_reload_regs, where they keep track of the spill registers
208 for a single insn, but also during reload_as_needed where they show all
209 the registers ever used by reload. For the latter case, the information
210 is calculated during finish_spills. */
211 static short spill_regs[FIRST_PSEUDO_REGISTER];
213 /* This vector of reg sets indicates, for each pseudo, which hard registers
214 may not be used for retrying global allocation because the register was
215 formerly spilled from one of them. If we allowed reallocating a pseudo to
216 a register that it was already allocated to, reload might not
218 static HARD_REG_SET *pseudo_previous_regs;
220 /* This vector of reg sets indicates, for each pseudo, which hard
221 registers may not be used for retrying global allocation because they
222 are used as spill registers during one of the insns in which the
224 static HARD_REG_SET *pseudo_forbidden_regs;
226 /* All hard regs that have been used as spill registers for any insn are
227 marked in this set. */
228 static HARD_REG_SET used_spill_regs;
230 /* Index of last register assigned as a spill register. We allocate in
231 a round-robin fashion. */
232 static int last_spill_reg;
234 /* Nonzero if indirect addressing is supported on the machine; this means
235 that spilling (REG n) does not require reloading it into a register in
236 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
237 value indicates the level of indirect addressing supported, e.g., two
238 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
240 static char spill_indirect_levels;
242 /* Nonzero if indirect addressing is supported when the innermost MEM is
243 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
244 which these are valid is the same as spill_indirect_levels, above. */
245 char indirect_symref_ok;
247 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
248 char double_reg_address_ok;
250 /* Record the stack slot for each spilled hard register. */
251 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
253 /* Width allocated so far for that stack slot. */
254 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
256 /* Record which pseudos needed to be spilled. */
257 static regset_head spilled_pseudos;
259 /* Used for communication between order_regs_for_reload and count_pseudo.
260 Used to avoid counting one pseudo twice. */
261 static regset_head pseudos_counted;
263 /* First uid used by insns created by reload in this function.
264 Used in find_equiv_reg. */
265 int reload_first_uid;
267 /* Flag set by local-alloc or global-alloc if anything is live in
268 a call-clobbered reg across calls. */
269 int caller_save_needed;
271 /* Set to 1 while reload_as_needed is operating.
272 Required by some machines to handle any generated moves differently. */
273 int reload_in_progress = 0;
275 /* These arrays record the insn_code of insns that may be needed to
276 perform input and output reloads of special objects. They provide a
277 place to pass a scratch register. */
278 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
279 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
281 /* This obstack is used for allocation of rtl during register elimination.
282 The allocated storage can be freed once find_reloads has processed the
284 static struct obstack reload_obstack;
286 /* Points to the beginning of the reload_obstack. All insn_chain structures
287 are allocated first. */
288 static char *reload_startobj;
290 /* The point after all insn_chain structures. Used to quickly deallocate
291 memory allocated in copy_reloads during calculate_needs_all_insns. */
292 static char *reload_firstobj;
294 /* This points before all local rtl generated by register elimination.
295 Used to quickly free all memory after processing one insn. */
296 static char *reload_insn_firstobj;
298 /* List of insn_chain instructions, one for every insn that reload needs to
300 struct insn_chain *reload_insn_chain;
302 /* List of all insns needing reloads. */
303 static struct insn_chain *insns_need_reload;
305 /* This structure is used to record information about register eliminations.
306 Each array entry describes one possible way of eliminating a register
307 in favor of another. If there is more than one way of eliminating a
308 particular register, the most preferred should be specified first. */
312 int from; /* Register number to be eliminated. */
313 int to; /* Register number used as replacement. */
314 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
315 int can_eliminate; /* Nonzero if this elimination can be done. */
316 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
317 insns made by reload. */
318 HOST_WIDE_INT offset; /* Current offset between the two regs. */
319 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
320 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
321 rtx from_rtx; /* REG rtx for the register to be eliminated.
322 We cannot simply compare the number since
323 we might then spuriously replace a hard
324 register corresponding to a pseudo
325 assigned to the reg to be eliminated. */
326 rtx to_rtx; /* REG rtx for the replacement. */
329 static struct elim_table *reg_eliminate = 0;
331 /* This is an intermediate structure to initialize the table. It has
332 exactly the members provided by ELIMINABLE_REGS. */
333 static const struct elim_table_1
337 } reg_eliminate_1[] =
339 /* If a set of eliminable registers was specified, define the table from it.
340 Otherwise, default to the normal case of the frame pointer being
341 replaced by the stack pointer. */
343 #ifdef ELIMINABLE_REGS
346 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
349 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
351 /* Record the number of pending eliminations that have an offset not equal
352 to their initial offset. If nonzero, we use a new copy of each
353 replacement result in any insns encountered. */
354 int num_not_at_initial_offset;
356 /* Count the number of registers that we may be able to eliminate. */
357 static int num_eliminable;
358 /* And the number of registers that are equivalent to a constant that
359 can be eliminated to frame_pointer / arg_pointer + constant. */
360 static int num_eliminable_invariants;
362 /* For each label, we record the offset of each elimination. If we reach
363 a label by more than one path and an offset differs, we cannot do the
364 elimination. This information is indexed by the difference of the
365 number of the label and the first label number. We can't offset the
366 pointer itself as this can cause problems on machines with segmented
367 memory. The first table is an array of flags that records whether we
368 have yet encountered a label and the second table is an array of arrays,
369 one entry in the latter array for each elimination. */
371 static int first_label_num;
372 static char *offsets_known_at;
373 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
375 /* Number of labels in the current function. */
377 static int num_labels;
379 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
380 static void maybe_fix_stack_asms (void);
381 static void copy_reloads (struct insn_chain *);
382 static void calculate_needs_all_insns (int);
383 static int find_reg (struct insn_chain *, int);
384 static void find_reload_regs (struct insn_chain *);
385 static void select_reload_regs (void);
386 static void delete_caller_save_insns (void);
388 static void spill_failure (rtx, enum reg_class);
389 static void count_spilled_pseudo (int, int, int);
390 static void delete_dead_insn (rtx);
391 static void alter_reg (int, int);
392 static void set_label_offsets (rtx, rtx, int);
393 static void check_eliminable_occurrences (rtx);
394 static void elimination_effects (rtx, enum machine_mode);
395 static int eliminate_regs_in_insn (rtx, int);
396 static void update_eliminable_offsets (void);
397 static void mark_not_eliminable (rtx, rtx, void *);
398 static void set_initial_elim_offsets (void);
399 static bool verify_initial_elim_offsets (void);
400 static void set_initial_label_offsets (void);
401 static void set_offsets_for_label (rtx);
402 static void init_elim_table (void);
403 static void update_eliminables (HARD_REG_SET *);
404 static void spill_hard_reg (unsigned int, int);
405 static int finish_spills (int);
406 static void scan_paradoxical_subregs (rtx);
407 static void count_pseudo (int);
408 static void order_regs_for_reload (struct insn_chain *);
409 static void reload_as_needed (int);
410 static void forget_old_reloads_1 (rtx, rtx, void *);
411 static void forget_marked_reloads (regset);
412 static int reload_reg_class_lower (const void *, const void *);
413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
420 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
422 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
423 static int allocate_reload_reg (struct insn_chain *, int, int);
424 static int conflicts_with_override (rtx);
425 static void failed_reload (rtx, int);
426 static int set_reload_reg (int, int);
427 static void choose_reload_regs_init (struct insn_chain *, rtx *);
428 static void choose_reload_regs (struct insn_chain *);
429 static void merge_assigned_reloads (rtx);
430 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
432 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
434 static void do_input_reload (struct insn_chain *, struct reload *, int);
435 static void do_output_reload (struct insn_chain *, struct reload *, int);
436 static bool inherit_piecemeal_p (int, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass once per compilation. */
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
462 = gen_rtx_MEM (Pmode,
465 LAST_VIRTUAL_REGISTER + 1),
467 spill_indirect_levels = 0;
469 while (memory_address_p (QImode, tem))
471 spill_indirect_levels++;
472 tem = gen_rtx_MEM (Pmode, tem);
475 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
477 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
478 indirect_symref_ok = memory_address_p (QImode, tem);
480 /* See if reg+reg is a valid (and offsettable) address. */
482 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 tem = gen_rtx_PLUS (Pmode,
485 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
486 gen_rtx_REG (Pmode, i));
488 /* This way, we make sure that reg+reg is an offsettable address. */
489 tem = plus_constant (tem, 4);
491 if (memory_address_p (QImode, tem))
493 double_reg_address_ok = 1;
498 /* Initialize obstack for our rtl allocation. */
499 gcc_obstack_init (&reload_obstack);
500 reload_startobj = obstack_alloc (&reload_obstack, 0);
502 INIT_REG_SET (&spilled_pseudos);
503 INIT_REG_SET (&pseudos_counted);
506 /* List of insn chains that are currently unused. */
507 static struct insn_chain *unused_insn_chains = 0;
509 /* Allocate an empty insn_chain structure. */
511 new_insn_chain (void)
513 struct insn_chain *c;
515 if (unused_insn_chains == 0)
517 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
518 INIT_REG_SET (&c->live_throughout);
519 INIT_REG_SET (&c->dead_or_set);
523 c = unused_insn_chains;
524 unused_insn_chains = c->next;
526 c->is_caller_save_insn = 0;
527 c->need_operand_change = 0;
533 /* Small utility function to set all regs in hard reg set TO which are
534 allocated to pseudos in regset FROM. */
537 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
540 reg_set_iterator rsi;
542 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
544 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 BASIC_BLOCK->global_live_at_start, which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
557 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
559 SET_HARD_REG_BIT (*to, r + nregs);
564 /* Replace all pseudos found in LOC with their corresponding
568 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
581 unsigned int regno = REGNO (x);
583 if (regno < FIRST_PSEUDO_REGISTER)
586 x = eliminate_regs (x, mem_mode, usage);
590 replace_pseudos_in (loc, mem_mode, usage);
594 if (reg_equiv_constant[regno])
595 *loc = reg_equiv_constant[regno];
596 else if (reg_equiv_mem[regno])
597 *loc = reg_equiv_mem[regno];
598 else if (reg_equiv_address[regno])
599 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
602 gcc_assert (!REG_P (regno_reg_rtx[regno])
603 || REGNO (regno_reg_rtx[regno]) != regno);
604 *loc = regno_reg_rtx[regno];
609 else if (code == MEM)
611 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
615 /* Process each of our operands recursively. */
616 fmt = GET_RTX_FORMAT (code);
617 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
619 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
620 else if (*fmt == 'E')
621 for (j = 0; j < XVECLEN (x, i); j++)
622 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
626 /* Global variables used by reload and its subroutines. */
628 /* Set during calculate_needs if an insn needs register elimination. */
629 static int something_needs_elimination;
630 /* Set during calculate_needs if an insn needs an operand changed. */
631 static int something_needs_operands_changed;
633 /* Nonzero means we couldn't get enough spill regs. */
636 /* Main entry point for the reload pass.
638 FIRST is the first insn of the function being compiled.
640 GLOBAL nonzero means we were called from global_alloc
641 and should attempt to reallocate any pseudoregs that we
642 displace from hard regs we will use for reloads.
643 If GLOBAL is zero, we do not have enough information to do that,
644 so any pseudo reg that is spilled must go to the stack.
646 Return value is nonzero if reload failed
647 and we must not do any more for this function. */
650 reload (rtx first, int global)
654 struct elim_table *ep;
657 /* Make sure even insns with volatile mem refs are recognizable. */
662 reload_firstobj = obstack_alloc (&reload_obstack, 0);
664 /* Make sure that the last insn in the chain
665 is not something that needs reloading. */
666 emit_note (NOTE_INSN_DELETED);
668 /* Enable find_equiv_reg to distinguish insns made by reload. */
669 reload_first_uid = get_max_uid ();
671 #ifdef SECONDARY_MEMORY_NEEDED
672 /* Initialize the secondary memory table. */
673 clear_secondary_mem ();
676 /* We don't have a stack slot for any spill reg yet. */
677 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
678 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
680 /* Initialize the save area information for caller-save, in case some
684 /* Compute which hard registers are now in use
685 as homes for pseudo registers.
686 This is done here rather than (eg) in global_alloc
687 because this point is reached even if not optimizing. */
688 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
691 /* A function that receives a nonlocal goto must save all call-saved
693 if (current_function_has_nonlocal_label)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
696 regs_ever_live[i] = 1;
698 /* Find all the pseudo registers that didn't get hard regs
699 but do have known equivalent constants or memory slots.
700 These include parameters (known equivalent to parameter slots)
701 and cse'd or loop-moved constant memory addresses.
703 Record constant equivalents in reg_equiv_constant
704 so they will be substituted by find_reloads.
705 Record memory equivalents in reg_mem_equiv so they can
706 be substituted eventually by altering the REG-rtx's. */
708 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
709 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
710 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
711 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
712 reg_equiv_address = XCNEWVEC (rtx, max_regno);
713 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
714 reg_old_renumber = XCNEWVEC (short, max_regno);
715 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
716 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
717 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
719 CLEAR_HARD_REG_SET (bad_spill_regs_global);
721 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
722 to. Also find all paradoxical subregs and find largest such for
725 num_eliminable_invariants = 0;
726 for (insn = first; insn; insn = NEXT_INSN (insn))
728 rtx set = single_set (insn);
730 /* We may introduce USEs that we want to remove at the end, so
731 we'll mark them with QImode. Make sure there are no
732 previously-marked insns left by say regmove. */
733 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
734 && GET_MODE (insn) != VOIDmode)
735 PUT_MODE (insn, VOIDmode);
738 scan_paradoxical_subregs (PATTERN (insn));
740 if (set != 0 && REG_P (SET_DEST (set)))
742 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
748 i = REGNO (SET_DEST (set));
751 if (i <= LAST_VIRTUAL_REGISTER)
754 if (! function_invariant_p (x)
756 /* A function invariant is often CONSTANT_P but may
757 include a register. We promise to only pass
758 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
760 && LEGITIMATE_PIC_OPERAND_P (x)))
762 /* It can happen that a REG_EQUIV note contains a MEM
763 that is not a legitimate memory operand. As later
764 stages of reload assume that all addresses found
765 in the reg_equiv_* arrays were originally legitimate,
766 we ignore such REG_EQUIV notes. */
767 if (memory_operand (x, VOIDmode))
769 /* Always unshare the equivalence, so we can
770 substitute into this insn without touching the
772 reg_equiv_memory_loc[i] = copy_rtx (x);
774 else if (function_invariant_p (x))
776 if (GET_CODE (x) == PLUS)
778 /* This is PLUS of frame pointer and a constant,
779 and might be shared. Unshare it. */
780 reg_equiv_invariant[i] = copy_rtx (x);
781 num_eliminable_invariants++;
783 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
785 reg_equiv_invariant[i] = x;
786 num_eliminable_invariants++;
788 else if (LEGITIMATE_CONSTANT_P (x))
789 reg_equiv_constant[i] = x;
792 reg_equiv_memory_loc[i]
793 = force_const_mem (GET_MODE (SET_DEST (set)), x);
794 if (! reg_equiv_memory_loc[i])
795 reg_equiv_init[i] = NULL_RTX;
800 reg_equiv_init[i] = NULL_RTX;
805 reg_equiv_init[i] = NULL_RTX;
810 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
811 if (reg_equiv_init[i])
813 fprintf (dump_file, "init_insns for %u: ", i);
814 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
815 fprintf (dump_file, "\n");
820 first_label_num = get_first_label_num ();
821 num_labels = max_label_num () - first_label_num;
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at = XNEWVEC (char, num_labels);
828 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
834 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
843 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
847 maybe_fix_stack_asms ();
849 insns_need_reload = 0;
850 something_needs_elimination = 0;
852 /* Initialize to -1, which means take the first spill register. */
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
863 int can_eliminate = 0;
866 can_eliminate |= ep->can_eliminate;
869 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
871 spill_hard_reg (from, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed;
891 HOST_WIDE_INT starting_frame_size;
893 starting_frame_size = get_frame_size ();
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
923 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
925 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
927 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
929 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
930 else if (CONSTANT_P (XEXP (x, 0))
931 || (REG_P (XEXP (x, 0))
932 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
933 || (GET_CODE (XEXP (x, 0)) == PLUS
934 && REG_P (XEXP (XEXP (x, 0), 0))
935 && (REGNO (XEXP (XEXP (x, 0), 0))
936 < FIRST_PSEUDO_REGISTER)
937 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
938 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
941 /* Make a new stack slot. Then indicate that something
942 changed so we go back and recompute offsets for
943 eliminable registers because the allocation of memory
944 below might change some offset. reg_equiv_{mem,address}
945 will be set up for this pseudo on the next pass around
947 reg_equiv_memory_loc[i] = 0;
948 reg_equiv_init[i] = 0;
953 if (caller_save_needed)
956 /* If we allocated another stack slot, redo elimination bookkeeping. */
957 if (starting_frame_size != get_frame_size ())
959 if (starting_frame_size && cfun->stack_alignment_needed)
961 /* If we have a stack frame, we must align it now. The
962 stack size may be a part of the offset computation for
963 register elimination. So if this changes the stack size,
964 then repeat the elimination bookkeeping. We don't
965 realign when there is no stack, as that will cause a
966 stack frame when none is needed should
967 STARTING_FRAME_OFFSET not be already aligned to
969 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
970 if (starting_frame_size != get_frame_size ())
974 if (caller_save_needed)
976 save_call_clobbered_regs ();
977 /* That might have allocated new insn_chain structures. */
978 reload_firstobj = obstack_alloc (&reload_obstack, 0);
981 calculate_needs_all_insns (global);
983 CLEAR_REG_SET (&spilled_pseudos);
986 something_changed = 0;
988 /* If we allocated any new memory locations, make another pass
989 since it might have changed elimination offsets. */
990 if (starting_frame_size != get_frame_size ())
991 something_changed = 1;
993 /* Even if the frame size remained the same, we might still have
994 changed elimination offsets, e.g. if find_reloads called
995 force_const_mem requiring the back end to allocate a constant
996 pool base register that needs to be saved on the stack. */
997 else if (!verify_initial_elim_offsets ())
998 something_changed = 1;
1001 HARD_REG_SET to_spill;
1002 CLEAR_HARD_REG_SET (to_spill);
1003 update_eliminables (&to_spill);
1004 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1006 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1007 if (TEST_HARD_REG_BIT (to_spill, i))
1009 spill_hard_reg (i, 1);
1012 /* Regardless of the state of spills, if we previously had
1013 a register that we thought we could eliminate, but now can
1014 not eliminate, we must run another pass.
1016 Consider pseudos which have an entry in reg_equiv_* which
1017 reference an eliminable register. We must make another pass
1018 to update reg_equiv_* so that we do not substitute in the
1019 old value from when we thought the elimination could be
1021 something_changed = 1;
1025 select_reload_regs ();
1029 if (insns_need_reload != 0 || did_spill)
1030 something_changed |= finish_spills (global);
1032 if (! something_changed)
1035 if (caller_save_needed)
1036 delete_caller_save_insns ();
1038 obstack_free (&reload_obstack, reload_firstobj);
1041 /* If global-alloc was run, notify it of any register eliminations we have
1044 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1045 if (ep->can_eliminate)
1046 mark_elimination (ep->from, ep->to);
1048 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1049 If that insn didn't set the register (i.e., it copied the register to
1050 memory), just delete that insn instead of the equivalencing insn plus
1051 anything now dead. If we call delete_dead_insn on that insn, we may
1052 delete the insn that actually sets the register if the register dies
1053 there and that is incorrect. */
1055 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1057 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1060 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1062 rtx equiv_insn = XEXP (list, 0);
1064 /* If we already deleted the insn or if it may trap, we can't
1065 delete it. The latter case shouldn't happen, but can
1066 if an insn has a variable address, gets a REG_EH_REGION
1067 note added to it, and then gets converted into a load
1068 from a constant address. */
1069 if (NOTE_P (equiv_insn)
1070 || can_throw_internal (equiv_insn))
1072 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1073 delete_dead_insn (equiv_insn);
1075 SET_INSN_DELETED (equiv_insn);
1080 /* Use the reload registers where necessary
1081 by generating move instructions to move the must-be-register
1082 values into or out of the reload registers. */
1084 if (insns_need_reload != 0 || something_needs_elimination
1085 || something_needs_operands_changed)
1087 HOST_WIDE_INT old_frame_size = get_frame_size ();
1089 reload_as_needed (global);
1091 gcc_assert (old_frame_size == get_frame_size ());
1093 gcc_assert (verify_initial_elim_offsets ());
1096 /* If we were able to eliminate the frame pointer, show that it is no
1097 longer live at the start of any basic block. If it ls live by
1098 virtue of being in a pseudo, that pseudo will be marked live
1099 and hence the frame pointer will be known to be live via that
1102 if (! frame_pointer_needed)
1104 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1105 HARD_FRAME_POINTER_REGNUM);
1107 /* Come here (with failure set nonzero) if we can't get enough spill
1111 CLEAR_REG_SET (&spilled_pseudos);
1112 reload_in_progress = 0;
1114 /* Now eliminate all pseudo regs by modifying them into
1115 their equivalent memory references.
1116 The REG-rtx's for the pseudos are modified in place,
1117 so all insns that used to refer to them now refer to memory.
1119 For a reg that has a reg_equiv_address, all those insns
1120 were changed by reloading so that no insns refer to it any longer;
1121 but the DECL_RTL of a variable decl may refer to it,
1122 and if so this causes the debugging info to mention the variable. */
1124 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1128 if (reg_equiv_mem[i])
1129 addr = XEXP (reg_equiv_mem[i], 0);
1131 if (reg_equiv_address[i])
1132 addr = reg_equiv_address[i];
1136 if (reg_renumber[i] < 0)
1138 rtx reg = regno_reg_rtx[i];
1140 REG_USERVAR_P (reg) = 0;
1141 PUT_CODE (reg, MEM);
1142 XEXP (reg, 0) = addr;
1143 if (reg_equiv_memory_loc[i])
1144 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1147 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1148 MEM_ATTRS (reg) = 0;
1150 MEM_NOTRAP_P (reg) = 1;
1152 else if (reg_equiv_mem[i])
1153 XEXP (reg_equiv_mem[i], 0) = addr;
1157 /* We must set reload_completed now since the cleanup_subreg_operands call
1158 below will re-recognize each insn and reload may have generated insns
1159 which are only valid during and after reload. */
1160 reload_completed = 1;
1162 /* Make a pass over all the insns and delete all USEs which we inserted
1163 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1164 notes. Delete all CLOBBER insns, except those that refer to the return
1165 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1166 from misarranging variable-array code, and simplify (subreg (reg))
1167 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1168 are no longer useful or accurate. Strip and regenerate REG_INC notes
1169 that may have been moved around. */
1171 for (insn = first; insn; insn = NEXT_INSN (insn))
1177 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1178 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1180 if ((GET_CODE (PATTERN (insn)) == USE
1181 /* We mark with QImode USEs introduced by reload itself. */
1182 && (GET_MODE (insn) == QImode
1183 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1184 || (GET_CODE (PATTERN (insn)) == CLOBBER
1185 && (!MEM_P (XEXP (PATTERN (insn), 0))
1186 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1187 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1188 && XEXP (XEXP (PATTERN (insn), 0), 0)
1189 != stack_pointer_rtx))
1190 && (!REG_P (XEXP (PATTERN (insn), 0))
1191 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1197 /* Some CLOBBERs may survive until here and still reference unassigned
1198 pseudos with const equivalent, which may in turn cause ICE in later
1199 passes if the reference remains in place. */
1200 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1201 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1202 VOIDmode, PATTERN (insn));
1204 /* Discard obvious no-ops, even without -O. This optimization
1205 is fast and doesn't interfere with debugging. */
1206 if (NONJUMP_INSN_P (insn)
1207 && GET_CODE (PATTERN (insn)) == SET
1208 && REG_P (SET_SRC (PATTERN (insn)))
1209 && REG_P (SET_DEST (PATTERN (insn)))
1210 && (REGNO (SET_SRC (PATTERN (insn)))
1211 == REGNO (SET_DEST (PATTERN (insn)))))
1217 pnote = ®_NOTES (insn);
1220 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1221 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1222 || REG_NOTE_KIND (*pnote) == REG_INC
1223 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1224 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1225 *pnote = XEXP (*pnote, 1);
1227 pnote = &XEXP (*pnote, 1);
1231 add_auto_inc_notes (insn, PATTERN (insn));
1234 /* Simplify (subreg (reg)) if it appears as an operand. */
1235 cleanup_subreg_operands (insn);
1237 /* Clean up invalid ASMs so that they don't confuse later passes.
1239 if (asm_noperands (PATTERN (insn)) >= 0)
1241 extract_insn (insn);
1242 if (!constrain_operands (1))
1244 error_for_asm (insn,
1245 "%<asm%> operand has impossible constraints");
1252 /* If we are doing stack checking, give a warning if this function's
1253 frame size is larger than we expect. */
1254 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1256 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1257 static int verbose_warned = 0;
1259 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1260 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1261 size += UNITS_PER_WORD;
1263 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1265 warning (0, "frame size too large for reliable stack checking");
1266 if (! verbose_warned)
1268 warning (0, "try reducing the number of local variables");
1274 /* Indicate that we no longer have known memory locations or constants. */
1275 if (reg_equiv_constant)
1276 free (reg_equiv_constant);
1277 if (reg_equiv_invariant)
1278 free (reg_equiv_invariant);
1279 reg_equiv_constant = 0;
1280 reg_equiv_invariant = 0;
1281 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1282 reg_equiv_memory_loc = 0;
1284 if (offsets_known_at)
1285 free (offsets_known_at);
1289 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1290 if (reg_equiv_alt_mem_list[i])
1291 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1292 free (reg_equiv_alt_mem_list);
1294 free (reg_equiv_mem);
1296 free (reg_equiv_address);
1297 free (reg_max_ref_width);
1298 free (reg_old_renumber);
1299 free (pseudo_previous_regs);
1300 free (pseudo_forbidden_regs);
1302 CLEAR_HARD_REG_SET (used_spill_regs);
1303 for (i = 0; i < n_spills; i++)
1304 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1306 /* Free all the insn_chain structures at once. */
1307 obstack_free (&reload_obstack, reload_startobj);
1308 unused_insn_chains = 0;
1309 fixup_abnormal_edges ();
1311 /* Replacing pseudos with their memory equivalents might have
1312 created shared rtx. Subsequent passes would get confused
1313 by this, so unshare everything here. */
1314 unshare_all_rtl_again (first);
1316 #ifdef STACK_BOUNDARY
1317 /* init_emit has set the alignment of the hard frame pointer
1318 to STACK_BOUNDARY. It is very likely no longer valid if
1319 the hard frame pointer was used for register allocation. */
1320 if (!frame_pointer_needed)
1321 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1327 /* Yet another special case. Unfortunately, reg-stack forces people to
1328 write incorrect clobbers in asm statements. These clobbers must not
1329 cause the register to appear in bad_spill_regs, otherwise we'll call
1330 fatal_insn later. We clear the corresponding regnos in the live
1331 register sets to avoid this.
1332 The whole thing is rather sick, I'm afraid. */
1335 maybe_fix_stack_asms (void)
1338 const char *constraints[MAX_RECOG_OPERANDS];
1339 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1340 struct insn_chain *chain;
1342 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1345 HARD_REG_SET clobbered, allowed;
1348 if (! INSN_P (chain->insn)
1349 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1351 pat = PATTERN (chain->insn);
1352 if (GET_CODE (pat) != PARALLEL)
1355 CLEAR_HARD_REG_SET (clobbered);
1356 CLEAR_HARD_REG_SET (allowed);
1358 /* First, make a mask of all stack regs that are clobbered. */
1359 for (i = 0; i < XVECLEN (pat, 0); i++)
1361 rtx t = XVECEXP (pat, 0, i);
1362 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1363 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1366 /* Get the operand values and constraints out of the insn. */
1367 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1368 constraints, operand_mode, NULL);
1370 /* For every operand, see what registers are allowed. */
1371 for (i = 0; i < noperands; i++)
1373 const char *p = constraints[i];
1374 /* For every alternative, we compute the class of registers allowed
1375 for reloading in CLS, and merge its contents into the reg set
1377 int cls = (int) NO_REGS;
1383 if (c == '\0' || c == ',' || c == '#')
1385 /* End of one alternative - mark the regs in the current
1386 class, and reset the class. */
1387 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1393 } while (c != '\0' && c != ',');
1401 case '=': case '+': case '*': case '%': case '?': case '!':
1402 case '0': case '1': case '2': case '3': case '4': case 'm':
1403 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1404 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1405 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1410 cls = (int) reg_class_subunion[cls]
1411 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1416 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1420 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1421 cls = (int) reg_class_subunion[cls]
1422 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1424 cls = (int) reg_class_subunion[cls]
1425 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1427 p += CONSTRAINT_LEN (c, p);
1430 /* Those of the registers which are clobbered, but allowed by the
1431 constraints, must be usable as reload registers. So clear them
1432 out of the life information. */
1433 AND_HARD_REG_SET (allowed, clobbered);
1434 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1435 if (TEST_HARD_REG_BIT (allowed, i))
1437 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1438 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1445 /* Copy the global variables n_reloads and rld into the corresponding elts
1448 copy_reloads (struct insn_chain *chain)
1450 chain->n_reloads = n_reloads;
1451 chain->rld = obstack_alloc (&reload_obstack,
1452 n_reloads * sizeof (struct reload));
1453 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1454 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1457 /* Walk the chain of insns, and determine for each whether it needs reloads
1458 and/or eliminations. Build the corresponding insns_need_reload list, and
1459 set something_needs_elimination as appropriate. */
1461 calculate_needs_all_insns (int global)
1463 struct insn_chain **pprev_reload = &insns_need_reload;
1464 struct insn_chain *chain, *next = 0;
1466 something_needs_elimination = 0;
1468 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1469 for (chain = reload_insn_chain; chain != 0; chain = next)
1471 rtx insn = chain->insn;
1475 /* Clear out the shortcuts. */
1476 chain->n_reloads = 0;
1477 chain->need_elim = 0;
1478 chain->need_reload = 0;
1479 chain->need_operand_change = 0;
1481 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1482 include REG_LABEL), we need to see what effects this has on the
1483 known offsets at labels. */
1485 if (LABEL_P (insn) || JUMP_P (insn)
1486 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1487 set_label_offsets (insn, insn, 0);
1491 rtx old_body = PATTERN (insn);
1492 int old_code = INSN_CODE (insn);
1493 rtx old_notes = REG_NOTES (insn);
1494 int did_elimination = 0;
1495 int operands_changed = 0;
1496 rtx set = single_set (insn);
1498 /* Skip insns that only set an equivalence. */
1499 if (set && REG_P (SET_DEST (set))
1500 && reg_renumber[REGNO (SET_DEST (set))] < 0
1501 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1502 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1503 && reg_equiv_init[REGNO (SET_DEST (set))])
1506 /* If needed, eliminate any eliminable registers. */
1507 if (num_eliminable || num_eliminable_invariants)
1508 did_elimination = eliminate_regs_in_insn (insn, 0);
1510 /* Analyze the instruction. */
1511 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1512 global, spill_reg_order);
1514 /* If a no-op set needs more than one reload, this is likely
1515 to be something that needs input address reloads. We
1516 can't get rid of this cleanly later, and it is of no use
1517 anyway, so discard it now.
1518 We only do this when expensive_optimizations is enabled,
1519 since this complements reload inheritance / output
1520 reload deletion, and it can make debugging harder. */
1521 if (flag_expensive_optimizations && n_reloads > 1)
1523 rtx set = single_set (insn);
1525 && SET_SRC (set) == SET_DEST (set)
1526 && REG_P (SET_SRC (set))
1527 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1530 /* Delete it from the reload chain. */
1532 chain->prev->next = next;
1534 reload_insn_chain = next;
1536 next->prev = chain->prev;
1537 chain->next = unused_insn_chains;
1538 unused_insn_chains = chain;
1543 update_eliminable_offsets ();
1545 /* Remember for later shortcuts which insns had any reloads or
1546 register eliminations. */
1547 chain->need_elim = did_elimination;
1548 chain->need_reload = n_reloads > 0;
1549 chain->need_operand_change = operands_changed;
1551 /* Discard any register replacements done. */
1552 if (did_elimination)
1554 obstack_free (&reload_obstack, reload_insn_firstobj);
1555 PATTERN (insn) = old_body;
1556 INSN_CODE (insn) = old_code;
1557 REG_NOTES (insn) = old_notes;
1558 something_needs_elimination = 1;
1561 something_needs_operands_changed |= operands_changed;
1565 copy_reloads (chain);
1566 *pprev_reload = chain;
1567 pprev_reload = &chain->next_need_reload;
1574 /* Comparison function for qsort to decide which of two reloads
1575 should be handled first. *P1 and *P2 are the reload numbers. */
1578 reload_reg_class_lower (const void *r1p, const void *r2p)
1580 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1583 /* Consider required reloads before optional ones. */
1584 t = rld[r1].optional - rld[r2].optional;
1588 /* Count all solitary classes before non-solitary ones. */
1589 t = ((reg_class_size[(int) rld[r2].class] == 1)
1590 - (reg_class_size[(int) rld[r1].class] == 1));
1594 /* Aside from solitaires, consider all multi-reg groups first. */
1595 t = rld[r2].nregs - rld[r1].nregs;
1599 /* Consider reloads in order of increasing reg-class number. */
1600 t = (int) rld[r1].class - (int) rld[r2].class;
1604 /* If reloads are equally urgent, sort by reload number,
1605 so that the results of qsort leave nothing to chance. */
1609 /* The cost of spilling each hard reg. */
1610 static int spill_cost[FIRST_PSEUDO_REGISTER];
1612 /* When spilling multiple hard registers, we use SPILL_COST for the first
1613 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1614 only the first hard reg for a multi-reg pseudo. */
1615 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1617 /* Update the spill cost arrays, considering that pseudo REG is live. */
1620 count_pseudo (int reg)
1622 int freq = REG_FREQ (reg);
1623 int r = reg_renumber[reg];
1626 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1627 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1630 SET_REGNO_REG_SET (&pseudos_counted, reg);
1632 gcc_assert (r >= 0);
1634 spill_add_cost[r] += freq;
1636 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1638 spill_cost[r + nregs] += freq;
1641 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1642 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1645 order_regs_for_reload (struct insn_chain *chain)
1648 HARD_REG_SET used_by_pseudos;
1649 HARD_REG_SET used_by_pseudos2;
1650 reg_set_iterator rsi;
1652 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1654 memset (spill_cost, 0, sizeof spill_cost);
1655 memset (spill_add_cost, 0, sizeof spill_add_cost);
1657 /* Count number of uses of each hard reg by pseudo regs allocated to it
1658 and then order them by decreasing use. First exclude hard registers
1659 that are live in or across this insn. */
1661 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1662 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1663 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1664 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1666 /* Now find out which pseudos are allocated to it, and update
1668 CLEAR_REG_SET (&pseudos_counted);
1670 EXECUTE_IF_SET_IN_REG_SET
1671 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1675 EXECUTE_IF_SET_IN_REG_SET
1676 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1680 CLEAR_REG_SET (&pseudos_counted);
1683 /* Vector of reload-numbers showing the order in which the reloads should
1685 static short reload_order[MAX_RELOADS];
1687 /* This is used to keep track of the spill regs used in one insn. */
1688 static HARD_REG_SET used_spill_regs_local;
1690 /* We decided to spill hard register SPILLED, which has a size of
1691 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1692 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1693 update SPILL_COST/SPILL_ADD_COST. */
1696 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1698 int r = reg_renumber[reg];
1699 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1701 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1702 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1705 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1707 spill_add_cost[r] -= REG_FREQ (reg);
1709 spill_cost[r + nregs] -= REG_FREQ (reg);
1712 /* Find reload register to use for reload number ORDER. */
1715 find_reg (struct insn_chain *chain, int order)
1717 int rnum = reload_order[order];
1718 struct reload *rl = rld + rnum;
1719 int best_cost = INT_MAX;
1723 HARD_REG_SET not_usable;
1724 HARD_REG_SET used_by_other_reload;
1725 reg_set_iterator rsi;
1727 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1728 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1729 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1731 CLEAR_HARD_REG_SET (used_by_other_reload);
1732 for (k = 0; k < order; k++)
1734 int other = reload_order[k];
1736 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1737 for (j = 0; j < rld[other].nregs; j++)
1738 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1741 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1743 unsigned int regno = i;
1745 if (! TEST_HARD_REG_BIT (not_usable, regno)
1746 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1747 && HARD_REGNO_MODE_OK (regno, rl->mode))
1749 int this_cost = spill_cost[regno];
1751 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1753 for (j = 1; j < this_nregs; j++)
1755 this_cost += spill_add_cost[regno + j];
1756 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1757 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1762 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1764 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1766 if (this_cost < best_cost
1767 /* Among registers with equal cost, prefer caller-saved ones, or
1768 use REG_ALLOC_ORDER if it is defined. */
1769 || (this_cost == best_cost
1770 #ifdef REG_ALLOC_ORDER
1771 && (inv_reg_alloc_order[regno]
1772 < inv_reg_alloc_order[best_reg])
1774 && call_used_regs[regno]
1775 && ! call_used_regs[best_reg]
1780 best_cost = this_cost;
1788 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1790 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1791 rl->regno = best_reg;
1793 EXECUTE_IF_SET_IN_REG_SET
1794 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1796 count_spilled_pseudo (best_reg, rl->nregs, j);
1799 EXECUTE_IF_SET_IN_REG_SET
1800 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1802 count_spilled_pseudo (best_reg, rl->nregs, j);
1805 for (i = 0; i < rl->nregs; i++)
1807 gcc_assert (spill_cost[best_reg + i] == 0);
1808 gcc_assert (spill_add_cost[best_reg + i] == 0);
1809 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1814 /* Find more reload regs to satisfy the remaining need of an insn, which
1816 Do it by ascending class number, since otherwise a reg
1817 might be spilled for a big class and might fail to count
1818 for a smaller class even though it belongs to that class. */
1821 find_reload_regs (struct insn_chain *chain)
1825 /* In order to be certain of getting the registers we need,
1826 we must sort the reloads into order of increasing register class.
1827 Then our grabbing of reload registers will parallel the process
1828 that provided the reload registers. */
1829 for (i = 0; i < chain->n_reloads; i++)
1831 /* Show whether this reload already has a hard reg. */
1832 if (chain->rld[i].reg_rtx)
1834 int regno = REGNO (chain->rld[i].reg_rtx);
1835 chain->rld[i].regno = regno;
1837 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1840 chain->rld[i].regno = -1;
1841 reload_order[i] = i;
1844 n_reloads = chain->n_reloads;
1845 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1847 CLEAR_HARD_REG_SET (used_spill_regs_local);
1850 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1852 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1854 /* Compute the order of preference for hard registers to spill. */
1856 order_regs_for_reload (chain);
1858 for (i = 0; i < n_reloads; i++)
1860 int r = reload_order[i];
1862 /* Ignore reloads that got marked inoperative. */
1863 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1864 && ! rld[r].optional
1865 && rld[r].regno == -1)
1866 if (! find_reg (chain, i))
1869 fprintf (dump_file, "reload failure for reload %d\n", r);
1870 spill_failure (chain->insn, rld[r].class);
1876 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1877 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1879 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1883 select_reload_regs (void)
1885 struct insn_chain *chain;
1887 /* Try to satisfy the needs for each insn. */
1888 for (chain = insns_need_reload; chain != 0;
1889 chain = chain->next_need_reload)
1890 find_reload_regs (chain);
1893 /* Delete all insns that were inserted by emit_caller_save_insns during
1896 delete_caller_save_insns (void)
1898 struct insn_chain *c = reload_insn_chain;
1902 while (c != 0 && c->is_caller_save_insn)
1904 struct insn_chain *next = c->next;
1907 if (c == reload_insn_chain)
1908 reload_insn_chain = next;
1912 next->prev = c->prev;
1914 c->prev->next = next;
1915 c->next = unused_insn_chains;
1916 unused_insn_chains = c;
1924 /* Handle the failure to find a register to spill.
1925 INSN should be one of the insns which needed this particular spill reg. */
1928 spill_failure (rtx insn, enum reg_class class)
1930 if (asm_noperands (PATTERN (insn)) >= 0)
1931 error_for_asm (insn, "can't find a register in class %qs while "
1932 "reloading %<asm%>",
1933 reg_class_names[class]);
1936 error ("unable to find a register to spill in class %qs",
1937 reg_class_names[class]);
1941 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1942 debug_reload_to_stream (dump_file);
1944 fatal_insn ("this is the insn:", insn);
1948 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1949 data that is dead in INSN. */
1952 delete_dead_insn (rtx insn)
1954 rtx prev = prev_real_insn (insn);
1957 /* If the previous insn sets a register that dies in our insn, delete it
1959 if (prev && GET_CODE (PATTERN (prev)) == SET
1960 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1961 && reg_mentioned_p (prev_dest, PATTERN (insn))
1962 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1963 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1964 delete_dead_insn (prev);
1966 SET_INSN_DELETED (insn);
1969 /* Modify the home of pseudo-reg I.
1970 The new home is present in reg_renumber[I].
1972 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1973 or it may be -1, meaning there is none or it is not relevant.
1974 This is used so that all pseudos spilled from a given hard reg
1975 can share one stack slot. */
1978 alter_reg (int i, int from_reg)
1980 /* When outputting an inline function, this can happen
1981 for a reg that isn't actually used. */
1982 if (regno_reg_rtx[i] == 0)
1985 /* If the reg got changed to a MEM at rtl-generation time,
1987 if (!REG_P (regno_reg_rtx[i]))
1990 /* Modify the reg-rtx to contain the new hard reg
1991 number or else to contain its pseudo reg number. */
1992 REGNO (regno_reg_rtx[i])
1993 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1995 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1996 allocate a stack slot for it. */
1998 if (reg_renumber[i] < 0
1999 && REG_N_REFS (i) > 0
2000 && reg_equiv_constant[i] == 0
2001 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2002 && reg_equiv_memory_loc[i] == 0)
2005 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2006 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2007 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2008 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2009 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2012 /* Each pseudo reg has an inherent size which comes from its own mode,
2013 and a total size which provides room for paradoxical subregs
2014 which refer to the pseudo reg in wider modes.
2016 We can use a slot already allocated if it provides both
2017 enough inherent space and enough total space.
2018 Otherwise, we allocate a new slot, making sure that it has no less
2019 inherent space, and no less total space, then the previous slot. */
2022 /* No known place to spill from => no slot to reuse. */
2023 x = assign_stack_local (mode, total_size,
2024 min_align > inherent_align
2025 || total_size > inherent_size ? -1 : 0);
2026 if (BYTES_BIG_ENDIAN)
2027 /* Cancel the big-endian correction done in assign_stack_local.
2028 Get the address of the beginning of the slot.
2029 This is so we can do a big-endian correction unconditionally
2031 adjust = inherent_size - total_size;
2033 /* Nothing can alias this slot except this pseudo. */
2034 set_mem_alias_set (x, new_alias_set ());
2037 /* Reuse a stack slot if possible. */
2038 else if (spill_stack_slot[from_reg] != 0
2039 && spill_stack_slot_width[from_reg] >= total_size
2040 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2042 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2043 x = spill_stack_slot[from_reg];
2045 /* Allocate a bigger slot. */
2048 /* Compute maximum size needed, both for inherent size
2049 and for total size. */
2052 if (spill_stack_slot[from_reg])
2054 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2056 mode = GET_MODE (spill_stack_slot[from_reg]);
2057 if (spill_stack_slot_width[from_reg] > total_size)
2058 total_size = spill_stack_slot_width[from_reg];
2059 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2060 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2063 /* Make a slot with that size. */
2064 x = assign_stack_local (mode, total_size,
2065 min_align > inherent_align
2066 || total_size > inherent_size ? -1 : 0);
2069 /* All pseudos mapped to this slot can alias each other. */
2070 if (spill_stack_slot[from_reg])
2071 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2073 set_mem_alias_set (x, new_alias_set ());
2075 if (BYTES_BIG_ENDIAN)
2077 /* Cancel the big-endian correction done in assign_stack_local.
2078 Get the address of the beginning of the slot.
2079 This is so we can do a big-endian correction unconditionally
2081 adjust = GET_MODE_SIZE (mode) - total_size;
2084 = adjust_address_nv (x, mode_for_size (total_size
2090 spill_stack_slot[from_reg] = stack_slot;
2091 spill_stack_slot_width[from_reg] = total_size;
2094 /* On a big endian machine, the "address" of the slot
2095 is the address of the low part that fits its inherent mode. */
2096 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2097 adjust += (total_size - inherent_size);
2099 /* If we have any adjustment to make, or if the stack slot is the
2100 wrong mode, make a new stack slot. */
2101 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2103 /* If we have a decl for the original register, set it for the
2104 memory. If this is a shared MEM, make a copy. */
2105 if (REG_EXPR (regno_reg_rtx[i])
2106 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2108 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2110 /* We can do this only for the DECLs home pseudo, not for
2111 any copies of it, since otherwise when the stack slot
2112 is reused, nonoverlapping_memrefs_p might think they
2114 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2116 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2119 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2123 /* Save the stack slot for later. */
2124 reg_equiv_memory_loc[i] = x;
2128 /* Mark the slots in regs_ever_live for the hard regs
2129 used by pseudo-reg number REGNO. */
2132 mark_home_live (int regno)
2136 i = reg_renumber[regno];
2139 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2141 regs_ever_live[i++] = 1;
2144 /* This function handles the tracking of elimination offsets around branches.
2146 X is a piece of RTL being scanned.
2148 INSN is the insn that it came from, if any.
2150 INITIAL_P is nonzero if we are to set the offset to be the initial
2151 offset and zero if we are setting the offset of the label to be the
2155 set_label_offsets (rtx x, rtx insn, int initial_p)
2157 enum rtx_code code = GET_CODE (x);
2160 struct elim_table *p;
2165 if (LABEL_REF_NONLOCAL_P (x))
2170 /* ... fall through ... */
2173 /* If we know nothing about this label, set the desired offsets. Note
2174 that this sets the offset at a label to be the offset before a label
2175 if we don't know anything about the label. This is not correct for
2176 the label after a BARRIER, but is the best guess we can make. If
2177 we guessed wrong, we will suppress an elimination that might have
2178 been possible had we been able to guess correctly. */
2180 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2182 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2183 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2184 = (initial_p ? reg_eliminate[i].initial_offset
2185 : reg_eliminate[i].offset);
2186 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2189 /* Otherwise, if this is the definition of a label and it is
2190 preceded by a BARRIER, set our offsets to the known offset of
2194 && (tem = prev_nonnote_insn (insn)) != 0
2196 set_offsets_for_label (insn);
2198 /* If neither of the above cases is true, compare each offset
2199 with those previously recorded and suppress any eliminations
2200 where the offsets disagree. */
2202 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2203 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2204 != (initial_p ? reg_eliminate[i].initial_offset
2205 : reg_eliminate[i].offset))
2206 reg_eliminate[i].can_eliminate = 0;
2211 set_label_offsets (PATTERN (insn), insn, initial_p);
2213 /* ... fall through ... */
2217 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2218 and hence must have all eliminations at their initial offsets. */
2219 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2220 if (REG_NOTE_KIND (tem) == REG_LABEL)
2221 set_label_offsets (XEXP (tem, 0), insn, 1);
2227 /* Each of the labels in the parallel or address vector must be
2228 at their initial offsets. We want the first field for PARALLEL
2229 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2231 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2232 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2237 /* We only care about setting PC. If the source is not RETURN,
2238 IF_THEN_ELSE, or a label, disable any eliminations not at
2239 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2240 isn't one of those possibilities. For branches to a label,
2241 call ourselves recursively.
2243 Note that this can disable elimination unnecessarily when we have
2244 a non-local goto since it will look like a non-constant jump to
2245 someplace in the current function. This isn't a significant
2246 problem since such jumps will normally be when all elimination
2247 pairs are back to their initial offsets. */
2249 if (SET_DEST (x) != pc_rtx)
2252 switch (GET_CODE (SET_SRC (x)))
2259 set_label_offsets (SET_SRC (x), insn, initial_p);
2263 tem = XEXP (SET_SRC (x), 1);
2264 if (GET_CODE (tem) == LABEL_REF)
2265 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2266 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2269 tem = XEXP (SET_SRC (x), 2);
2270 if (GET_CODE (tem) == LABEL_REF)
2271 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2272 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2280 /* If we reach here, all eliminations must be at their initial
2281 offset because we are doing a jump to a variable address. */
2282 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2283 if (p->offset != p->initial_offset)
2284 p->can_eliminate = 0;
2292 /* Scan X and replace any eliminable registers (such as fp) with a
2293 replacement (such as sp), plus an offset.
2295 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2296 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2297 MEM, we are allowed to replace a sum of a register and the constant zero
2298 with the register, which we cannot do outside a MEM. In addition, we need
2299 to record the fact that a register is referenced outside a MEM.
2301 If INSN is an insn, it is the insn containing X. If we replace a REG
2302 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2303 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2304 the REG is being modified.
2306 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2307 That's used when we eliminate in expressions stored in notes.
2308 This means, do not set ref_outside_mem even if the reference
2311 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2312 replacements done assuming all offsets are at their initial values. If
2313 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2314 encounter, return the actual location so that find_reloads will do
2315 the proper thing. */
2318 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2319 bool may_use_invariant)
2321 enum rtx_code code = GET_CODE (x);
2322 struct elim_table *ep;
2329 if (! current_function_decl)
2351 /* First handle the case where we encounter a bare register that
2352 is eliminable. Replace it with a PLUS. */
2353 if (regno < FIRST_PSEUDO_REGISTER)
2355 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2357 if (ep->from_rtx == x && ep->can_eliminate)
2358 return plus_constant (ep->to_rtx, ep->previous_offset);
2361 else if (reg_renumber && reg_renumber[regno] < 0
2362 && reg_equiv_invariant && reg_equiv_invariant[regno])
2364 if (may_use_invariant)
2365 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2366 mem_mode, insn, true);
2367 /* There exists at least one use of REGNO that cannot be
2368 eliminated. Prevent the defining insn from being deleted. */
2369 reg_equiv_init[regno] = NULL_RTX;
2370 alter_reg (regno, -1);
2374 /* You might think handling MINUS in a manner similar to PLUS is a
2375 good idea. It is not. It has been tried multiple times and every
2376 time the change has had to have been reverted.
2378 Other parts of reload know a PLUS is special (gen_reload for example)
2379 and require special code to handle code a reloaded PLUS operand.
2381 Also consider backends where the flags register is clobbered by a
2382 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2383 lea instruction comes to mind). If we try to reload a MINUS, we
2384 may kill the flags register that was holding a useful value.
2386 So, please before trying to handle MINUS, consider reload as a
2387 whole instead of this little section as well as the backend issues. */
2389 /* If this is the sum of an eliminable register and a constant, rework
2391 if (REG_P (XEXP (x, 0))
2392 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2393 && CONSTANT_P (XEXP (x, 1)))
2395 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2397 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2399 /* The only time we want to replace a PLUS with a REG (this
2400 occurs when the constant operand of the PLUS is the negative
2401 of the offset) is when we are inside a MEM. We won't want
2402 to do so at other times because that would change the
2403 structure of the insn in a way that reload can't handle.
2404 We special-case the commonest situation in
2405 eliminate_regs_in_insn, so just replace a PLUS with a
2406 PLUS here, unless inside a MEM. */
2407 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2408 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2411 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2412 plus_constant (XEXP (x, 1),
2413 ep->previous_offset));
2416 /* If the register is not eliminable, we are done since the other
2417 operand is a constant. */
2421 /* If this is part of an address, we want to bring any constant to the
2422 outermost PLUS. We will do this by doing register replacement in
2423 our operands and seeing if a constant shows up in one of them.
2425 Note that there is no risk of modifying the structure of the insn,
2426 since we only get called for its operands, thus we are either
2427 modifying the address inside a MEM, or something like an address
2428 operand of a load-address insn. */
2431 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2432 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2434 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2436 /* If one side is a PLUS and the other side is a pseudo that
2437 didn't get a hard register but has a reg_equiv_constant,
2438 we must replace the constant here since it may no longer
2439 be in the position of any operand. */
2440 if (GET_CODE (new0) == PLUS && REG_P (new1)
2441 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2442 && reg_renumber[REGNO (new1)] < 0
2443 && reg_equiv_constant != 0
2444 && reg_equiv_constant[REGNO (new1)] != 0)
2445 new1 = reg_equiv_constant[REGNO (new1)];
2446 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2447 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2448 && reg_renumber[REGNO (new0)] < 0
2449 && reg_equiv_constant[REGNO (new0)] != 0)
2450 new0 = reg_equiv_constant[REGNO (new0)];
2452 new = form_sum (new0, new1);
2454 /* As above, if we are not inside a MEM we do not want to
2455 turn a PLUS into something else. We might try to do so here
2456 for an addition of 0 if we aren't optimizing. */
2457 if (! mem_mode && GET_CODE (new) != PLUS)
2458 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2466 /* If this is the product of an eliminable register and a
2467 constant, apply the distribute law and move the constant out
2468 so that we have (plus (mult ..) ..). This is needed in order
2469 to keep load-address insns valid. This case is pathological.
2470 We ignore the possibility of overflow here. */
2471 if (REG_P (XEXP (x, 0))
2472 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2473 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2474 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2476 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2479 /* Refs inside notes don't count for this purpose. */
2480 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2481 || GET_CODE (insn) == INSN_LIST)))
2482 ep->ref_outside_mem = 1;
2485 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2486 ep->previous_offset * INTVAL (XEXP (x, 1)));
2489 /* ... fall through ... */
2493 /* See comments before PLUS about handling MINUS. */
2495 case DIV: case UDIV:
2496 case MOD: case UMOD:
2497 case AND: case IOR: case XOR:
2498 case ROTATERT: case ROTATE:
2499 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2501 case GE: case GT: case GEU: case GTU:
2502 case LE: case LT: case LEU: case LTU:
2504 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2505 rtx new1 = XEXP (x, 1)
2506 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2508 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2509 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2514 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2517 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2518 if (new != XEXP (x, 0))
2520 /* If this is a REG_DEAD note, it is not valid anymore.
2521 Using the eliminated version could result in creating a
2522 REG_DEAD note for the stack or frame pointer. */
2523 if (GET_MODE (x) == REG_DEAD)
2525 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2528 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2532 /* ... fall through ... */
2535 /* Now do eliminations in the rest of the chain. If this was
2536 an EXPR_LIST, this might result in allocating more memory than is
2537 strictly needed, but it simplifies the code. */
2540 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2541 if (new != XEXP (x, 1))
2543 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2551 /* We do not support elimination of a register that is modified.
2552 elimination_effects has already make sure that this does not
2558 /* We do not support elimination of a register that is modified.
2559 elimination_effects has already make sure that this does not
2560 happen. The only remaining case we need to consider here is
2561 that the increment value may be an eliminable register. */
2562 if (GET_CODE (XEXP (x, 1)) == PLUS
2563 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2565 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2568 if (new != XEXP (XEXP (x, 1), 1))
2569 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2570 gen_rtx_PLUS (GET_MODE (x),
2575 case STRICT_LOW_PART:
2577 case SIGN_EXTEND: case ZERO_EXTEND:
2578 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2579 case FLOAT: case FIX:
2580 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2589 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2590 if (new != XEXP (x, 0))
2591 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2595 /* Similar to above processing, but preserve SUBREG_BYTE.
2596 Convert (subreg (mem)) to (mem) if not paradoxical.
2597 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2598 pseudo didn't get a hard reg, we must replace this with the
2599 eliminated version of the memory location because push_reload
2600 may do the replacement in certain circumstances. */
2601 if (REG_P (SUBREG_REG (x))
2602 && (GET_MODE_SIZE (GET_MODE (x))
2603 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2604 && reg_equiv_memory_loc != 0
2605 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2607 new = SUBREG_REG (x);
2610 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2612 if (new != SUBREG_REG (x))
2614 int x_size = GET_MODE_SIZE (GET_MODE (x));
2615 int new_size = GET_MODE_SIZE (GET_MODE (new));
2618 && ((x_size < new_size
2619 #ifdef WORD_REGISTER_OPERATIONS
2620 /* On these machines, combine can create rtl of the form
2621 (set (subreg:m1 (reg:m2 R) 0) ...)
2622 where m1 < m2, and expects something interesting to
2623 happen to the entire word. Moreover, it will use the
2624 (reg:m2 R) later, expecting all bits to be preserved.
2625 So if the number of words is the same, preserve the
2626 subreg so that push_reload can see it. */
2627 && ! ((x_size - 1) / UNITS_PER_WORD
2628 == (new_size -1 ) / UNITS_PER_WORD)
2631 || x_size == new_size)
2633 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2635 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2641 /* Our only special processing is to pass the mode of the MEM to our
2642 recursive call and copy the flags. While we are here, handle this
2643 case more efficiently. */
2645 replace_equiv_address_nv (x,
2646 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2650 /* Handle insn_list USE that a call to a pure function may generate. */
2651 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2652 if (new != XEXP (x, 0))
2653 return gen_rtx_USE (GET_MODE (x), new);
2665 /* Process each of our operands recursively. If any have changed, make a
2667 fmt = GET_RTX_FORMAT (code);
2668 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2672 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2673 if (new != XEXP (x, i) && ! copied)
2675 x = shallow_copy_rtx (x);
2680 else if (*fmt == 'E')
2683 for (j = 0; j < XVECLEN (x, i); j++)
2685 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2686 if (new != XVECEXP (x, i, j) && ! copied_vec)
2688 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2692 x = shallow_copy_rtx (x);
2695 XVEC (x, i) = new_v;
2698 XVECEXP (x, i, j) = new;
2707 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2709 return eliminate_regs_1 (x, mem_mode, insn, false);
2712 /* Scan rtx X for modifications of elimination target registers. Update
2713 the table of eliminables to reflect the changed state. MEM_MODE is
2714 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2717 elimination_effects (rtx x, enum machine_mode mem_mode)
2719 enum rtx_code code = GET_CODE (x);
2720 struct elim_table *ep;
2744 /* First handle the case where we encounter a bare register that
2745 is eliminable. Replace it with a PLUS. */
2746 if (regno < FIRST_PSEUDO_REGISTER)
2748 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2750 if (ep->from_rtx == x && ep->can_eliminate)
2753 ep->ref_outside_mem = 1;
2758 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2759 && reg_equiv_constant[regno]
2760 && ! function_invariant_p (reg_equiv_constant[regno]))
2761 elimination_effects (reg_equiv_constant[regno], mem_mode);
2770 /* If we modify the source of an elimination rule, disable it. */
2771 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2772 if (ep->from_rtx == XEXP (x, 0))
2773 ep->can_eliminate = 0;
2775 /* If we modify the target of an elimination rule by adding a constant,
2776 update its offset. If we modify the target in any other way, we'll
2777 have to disable the rule as well. */
2778 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2779 if (ep->to_rtx == XEXP (x, 0))
2781 int size = GET_MODE_SIZE (mem_mode);
2783 /* If more bytes than MEM_MODE are pushed, account for them. */
2784 #ifdef PUSH_ROUNDING
2785 if (ep->to_rtx == stack_pointer_rtx)
2786 size = PUSH_ROUNDING (size);
2788 if (code == PRE_DEC || code == POST_DEC)
2790 else if (code == PRE_INC || code == POST_INC)
2792 else if (code == PRE_MODIFY || code == POST_MODIFY)
2794 if (GET_CODE (XEXP (x, 1)) == PLUS
2795 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2796 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2797 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2799 ep->can_eliminate = 0;
2803 /* These two aren't unary operators. */
2804 if (code == POST_MODIFY || code == PRE_MODIFY)
2807 /* Fall through to generic unary operation case. */
2808 case STRICT_LOW_PART:
2810 case SIGN_EXTEND: case ZERO_EXTEND:
2811 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2812 case FLOAT: case FIX:
2813 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2822 elimination_effects (XEXP (x, 0), mem_mode);
2826 if (REG_P (SUBREG_REG (x))
2827 && (GET_MODE_SIZE (GET_MODE (x))
2828 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2829 && reg_equiv_memory_loc != 0
2830 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2833 elimination_effects (SUBREG_REG (x), mem_mode);
2837 /* If using a register that is the source of an eliminate we still
2838 think can be performed, note it cannot be performed since we don't
2839 know how this register is used. */
2840 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2841 if (ep->from_rtx == XEXP (x, 0))
2842 ep->can_eliminate = 0;
2844 elimination_effects (XEXP (x, 0), mem_mode);
2848 /* If clobbering a register that is the replacement register for an
2849 elimination we still think can be performed, note that it cannot
2850 be performed. Otherwise, we need not be concerned about it. */
2851 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2852 if (ep->to_rtx == XEXP (x, 0))
2853 ep->can_eliminate = 0;
2855 elimination_effects (XEXP (x, 0), mem_mode);
2859 /* Check for setting a register that we know about. */
2860 if (REG_P (SET_DEST (x)))
2862 /* See if this is setting the replacement register for an
2865 If DEST is the hard frame pointer, we do nothing because we
2866 assume that all assignments to the frame pointer are for
2867 non-local gotos and are being done at a time when they are valid
2868 and do not disturb anything else. Some machines want to
2869 eliminate a fake argument pointer (or even a fake frame pointer)
2870 with either the real frame or the stack pointer. Assignments to
2871 the hard frame pointer must not prevent this elimination. */
2873 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2875 if (ep->to_rtx == SET_DEST (x)
2876 && SET_DEST (x) != hard_frame_pointer_rtx)
2878 /* If it is being incremented, adjust the offset. Otherwise,
2879 this elimination can't be done. */
2880 rtx src = SET_SRC (x);
2882 if (GET_CODE (src) == PLUS
2883 && XEXP (src, 0) == SET_DEST (x)
2884 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2885 ep->offset -= INTVAL (XEXP (src, 1));
2887 ep->can_eliminate = 0;
2891 elimination_effects (SET_DEST (x), 0);
2892 elimination_effects (SET_SRC (x), 0);
2896 /* Our only special processing is to pass the mode of the MEM to our
2898 elimination_effects (XEXP (x, 0), GET_MODE (x));
2905 fmt = GET_RTX_FORMAT (code);
2906 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2909 elimination_effects (XEXP (x, i), mem_mode);
2910 else if (*fmt == 'E')
2911 for (j = 0; j < XVECLEN (x, i); j++)
2912 elimination_effects (XVECEXP (x, i, j), mem_mode);
2916 /* Descend through rtx X and verify that no references to eliminable registers
2917 remain. If any do remain, mark the involved register as not
2921 check_eliminable_occurrences (rtx x)
2930 code = GET_CODE (x);
2932 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2934 struct elim_table *ep;
2936 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2937 if (ep->from_rtx == x)
2938 ep->can_eliminate = 0;
2942 fmt = GET_RTX_FORMAT (code);
2943 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2946 check_eliminable_occurrences (XEXP (x, i));
2947 else if (*fmt == 'E')
2950 for (j = 0; j < XVECLEN (x, i); j++)
2951 check_eliminable_occurrences (XVECEXP (x, i, j));
2956 /* Scan INSN and eliminate all eliminable registers in it.
2958 If REPLACE is nonzero, do the replacement destructively. Also
2959 delete the insn as dead it if it is setting an eliminable register.
2961 If REPLACE is zero, do all our allocations in reload_obstack.
2963 If no eliminations were done and this insn doesn't require any elimination
2964 processing (these are not identical conditions: it might be updating sp,
2965 but not referencing fp; this needs to be seen during reload_as_needed so
2966 that the offset between fp and sp can be taken into consideration), zero
2967 is returned. Otherwise, 1 is returned. */
2970 eliminate_regs_in_insn (rtx insn, int replace)
2972 int icode = recog_memoized (insn);
2973 rtx old_body = PATTERN (insn);
2974 int insn_is_asm = asm_noperands (old_body) >= 0;
2975 rtx old_set = single_set (insn);
2979 rtx substed_operand[MAX_RECOG_OPERANDS];
2980 rtx orig_operand[MAX_RECOG_OPERANDS];
2981 struct elim_table *ep;
2982 rtx plus_src, plus_cst_src;
2984 if (! insn_is_asm && icode < 0)
2986 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2987 || GET_CODE (PATTERN (insn)) == CLOBBER
2988 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2989 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2990 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2994 if (old_set != 0 && REG_P (SET_DEST (old_set))
2995 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2997 /* Check for setting an eliminable register. */
2998 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2999 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3001 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3002 /* If this is setting the frame pointer register to the
3003 hardware frame pointer register and this is an elimination
3004 that will be done (tested above), this insn is really
3005 adjusting the frame pointer downward to compensate for
3006 the adjustment done before a nonlocal goto. */
3007 if (ep->from == FRAME_POINTER_REGNUM
3008 && ep->to == HARD_FRAME_POINTER_REGNUM)
3010 rtx base = SET_SRC (old_set);
3011 rtx base_insn = insn;
3012 HOST_WIDE_INT offset = 0;
3014 while (base != ep->to_rtx)
3016 rtx prev_insn, prev_set;
3018 if (GET_CODE (base) == PLUS
3019 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3021 offset += INTVAL (XEXP (base, 1));
3022 base = XEXP (base, 0);
3024 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3025 && (prev_set = single_set (prev_insn)) != 0
3026 && rtx_equal_p (SET_DEST (prev_set), base))
3028 base = SET_SRC (prev_set);
3029 base_insn = prev_insn;
3035 if (base == ep->to_rtx)
3038 = plus_constant (ep->to_rtx, offset - ep->offset);
3040 new_body = old_body;
3043 new_body = copy_insn (old_body);
3044 if (REG_NOTES (insn))
3045 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3047 PATTERN (insn) = new_body;
3048 old_set = single_set (insn);
3050 /* First see if this insn remains valid when we
3051 make the change. If not, keep the INSN_CODE
3052 the same and let reload fit it up. */
3053 validate_change (insn, &SET_SRC (old_set), src, 1);
3054 validate_change (insn, &SET_DEST (old_set),
3056 if (! apply_change_group ())
3058 SET_SRC (old_set) = src;
3059 SET_DEST (old_set) = ep->to_rtx;
3068 /* In this case this insn isn't serving a useful purpose. We
3069 will delete it in reload_as_needed once we know that this
3070 elimination is, in fact, being done.
3072 If REPLACE isn't set, we can't delete this insn, but needn't
3073 process it since it won't be used unless something changes. */
3076 delete_dead_insn (insn);
3084 /* We allow one special case which happens to work on all machines we
3085 currently support: a single set with the source or a REG_EQUAL
3086 note being a PLUS of an eliminable register and a constant. */
3087 plus_src = plus_cst_src = 0;
3088 if (old_set && REG_P (SET_DEST (old_set)))
3090 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3091 plus_src = SET_SRC (old_set);
3092 /* First see if the source is of the form (plus (...) CST). */
3094 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3095 plus_cst_src = plus_src;
3096 else if (REG_P (SET_SRC (old_set))
3099 /* Otherwise, see if we have a REG_EQUAL note of the form
3100 (plus (...) CST). */
3102 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3104 if (REG_NOTE_KIND (links) == REG_EQUAL
3105 && GET_CODE (XEXP (links, 0)) == PLUS
3106 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3108 plus_cst_src = XEXP (links, 0);
3114 /* Check that the first operand of the PLUS is a hard reg or
3115 the lowpart subreg of one. */
3118 rtx reg = XEXP (plus_cst_src, 0);
3119 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3120 reg = SUBREG_REG (reg);
3122 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3128 rtx reg = XEXP (plus_cst_src, 0);
3129 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3131 if (GET_CODE (reg) == SUBREG)
3132 reg = SUBREG_REG (reg);
3134 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3135 if (ep->from_rtx == reg && ep->can_eliminate)
3137 rtx to_rtx = ep->to_rtx;
3138 offset += ep->offset;
3139 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3141 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3142 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3144 /* If we have a nonzero offset, and the source is already
3145 a simple REG, the following transformation would
3146 increase the cost of the insn by replacing a simple REG
3147 with (plus (reg sp) CST). So try only when we already
3148 had a PLUS before. */
3149 if (offset == 0 || plus_src)
3151 rtx new_src = plus_constant (to_rtx, offset);
3153 new_body = old_body;
3156 new_body = copy_insn (old_body);
3157 if (REG_NOTES (insn))
3158 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3160 PATTERN (insn) = new_body;
3161 old_set = single_set (insn);
3163 /* First see if this insn remains valid when we make the
3164 change. If not, try to replace the whole pattern with
3165 a simple set (this may help if the original insn was a
3166 PARALLEL that was only recognized as single_set due to
3167 REG_UNUSED notes). If this isn't valid either, keep
3168 the INSN_CODE the same and let reload fix it up. */
3169 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3171 rtx new_pat = gen_rtx_SET (VOIDmode,
3172 SET_DEST (old_set), new_src);
3174 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3175 SET_SRC (old_set) = new_src;
3182 /* This can't have an effect on elimination offsets, so skip right
3188 /* Determine the effects of this insn on elimination offsets. */
3189 elimination_effects (old_body, 0);
3191 /* Eliminate all eliminable registers occurring in operands that
3192 can be handled by reload. */
3193 extract_insn (insn);
3194 for (i = 0; i < recog_data.n_operands; i++)
3196 orig_operand[i] = recog_data.operand[i];
3197 substed_operand[i] = recog_data.operand[i];
3199 /* For an asm statement, every operand is eliminable. */
3200 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3202 bool is_set_src, in_plus;
3204 /* Check for setting a register that we know about. */
3205 if (recog_data.operand_type[i] != OP_IN
3206 && REG_P (orig_operand[i]))
3208 /* If we are assigning to a register that can be eliminated, it
3209 must be as part of a PARALLEL, since the code above handles
3210 single SETs. We must indicate that we can no longer
3211 eliminate this reg. */
3212 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3214 if (ep->from_rtx == orig_operand[i])
3215 ep->can_eliminate = 0;
3218 /* Companion to the above plus substitution, we can allow
3219 invariants as the source of a plain move. */
3221 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3225 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3226 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3230 = eliminate_regs_1 (recog_data.operand[i], 0,
3231 replace ? insn : NULL_RTX,
3232 is_set_src || in_plus);
3233 if (substed_operand[i] != orig_operand[i])
3235 /* Terminate the search in check_eliminable_occurrences at
3237 *recog_data.operand_loc[i] = 0;
3239 /* If an output operand changed from a REG to a MEM and INSN is an
3240 insn, write a CLOBBER insn. */
3241 if (recog_data.operand_type[i] != OP_IN
3242 && REG_P (orig_operand[i])
3243 && MEM_P (substed_operand[i])
3245 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3250 for (i = 0; i < recog_data.n_dups; i++)
3251 *recog_data.dup_loc[i]
3252 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3254 /* If any eliminable remain, they aren't eliminable anymore. */
3255 check_eliminable_occurrences (old_body);
3257 /* Substitute the operands; the new values are in the substed_operand
3259 for (i = 0; i < recog_data.n_operands; i++)
3260 *recog_data.operand_loc[i] = substed_operand[i];
3261 for (i = 0; i < recog_data.n_dups; i++)
3262 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3264 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3265 re-recognize the insn. We do this in case we had a simple addition
3266 but now can do this as a load-address. This saves an insn in this
3268 If re-recognition fails, the old insn code number will still be used,
3269 and some register operands may have changed into PLUS expressions.
3270 These will be handled by find_reloads by loading them into a register
3275 /* If we aren't replacing things permanently and we changed something,
3276 make another copy to ensure that all the RTL is new. Otherwise
3277 things can go wrong if find_reload swaps commutative operands
3278 and one is inside RTL that has been copied while the other is not. */
3279 new_body = old_body;
3282 new_body = copy_insn (old_body);
3283 if (REG_NOTES (insn))
3284 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3286 PATTERN (insn) = new_body;
3288 /* If we had a move insn but now we don't, rerecognize it. This will
3289 cause spurious re-recognition if the old move had a PARALLEL since
3290 the new one still will, but we can't call single_set without
3291 having put NEW_BODY into the insn and the re-recognition won't
3292 hurt in this rare case. */
3293 /* ??? Why this huge if statement - why don't we just rerecognize the
3297 && ((REG_P (SET_SRC (old_set))
3298 && (GET_CODE (new_body) != SET
3299 || !REG_P (SET_SRC (new_body))))
3300 /* If this was a load from or store to memory, compare
3301 the MEM in recog_data.operand to the one in the insn.
3302 If they are not equal, then rerecognize the insn. */
3304 && ((MEM_P (SET_SRC (old_set))
3305 && SET_SRC (old_set) != recog_data.operand[1])
3306 || (MEM_P (SET_DEST (old_set))
3307 && SET_DEST (old_set) != recog_data.operand[0])))
3308 /* If this was an add insn before, rerecognize. */
3309 || GET_CODE (SET_SRC (old_set)) == PLUS))
3311 int new_icode = recog (PATTERN (insn), insn, 0);
3313 INSN_CODE (insn) = new_icode;
3317 /* Restore the old body. If there were any changes to it, we made a copy
3318 of it while the changes were still in place, so we'll correctly return
3319 a modified insn below. */
3322 /* Restore the old body. */
3323 for (i = 0; i < recog_data.n_operands; i++)
3324 *recog_data.operand_loc[i] = orig_operand[i];
3325 for (i = 0; i < recog_data.n_dups; i++)
3326 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3329 /* Update all elimination pairs to reflect the status after the current
3330 insn. The changes we make were determined by the earlier call to
3331 elimination_effects.
3333 We also detect cases where register elimination cannot be done,
3334 namely, if a register would be both changed and referenced outside a MEM
3335 in the resulting insn since such an insn is often undefined and, even if
3336 not, we cannot know what meaning will be given to it. Note that it is
3337 valid to have a register used in an address in an insn that changes it
3338 (presumably with a pre- or post-increment or decrement).
3340 If anything changes, return nonzero. */
3342 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3344 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3345 ep->can_eliminate = 0;
3347 ep->ref_outside_mem = 0;
3349 if (ep->previous_offset != ep->offset)
3354 /* If we changed something, perform elimination in REG_NOTES. This is
3355 needed even when REPLACE is zero because a REG_DEAD note might refer
3356 to a register that we eliminate and could cause a different number
3357 of spill registers to be needed in the final reload pass than in
3359 if (val && REG_NOTES (insn) != 0)
3361 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3366 /* Loop through all elimination pairs.
3367 Recalculate the number not at initial offset.
3369 Compute the maximum offset (minimum offset if the stack does not
3370 grow downward) for each elimination pair. */
3373 update_eliminable_offsets (void)
3375 struct elim_table *ep;
3377 num_not_at_initial_offset = 0;
3378 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3380 ep->previous_offset = ep->offset;
3381 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3382 num_not_at_initial_offset++;
3386 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3387 replacement we currently believe is valid, mark it as not eliminable if X
3388 modifies DEST in any way other than by adding a constant integer to it.
3390 If DEST is the frame pointer, we do nothing because we assume that
3391 all assignments to the hard frame pointer are nonlocal gotos and are being
3392 done at a time when they are valid and do not disturb anything else.
3393 Some machines want to eliminate a fake argument pointer with either the
3394 frame or stack pointer. Assignments to the hard frame pointer must not
3395 prevent this elimination.
3397 Called via note_stores from reload before starting its passes to scan
3398 the insns of the function. */
3401 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3405 /* A SUBREG of a hard register here is just changing its mode. We should
3406 not see a SUBREG of an eliminable hard register, but check just in
3408 if (GET_CODE (dest) == SUBREG)
3409 dest = SUBREG_REG (dest);
3411 if (dest == hard_frame_pointer_rtx)
3414 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3415 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3416 && (GET_CODE (x) != SET
3417 || GET_CODE (SET_SRC (x)) != PLUS
3418 || XEXP (SET_SRC (x), 0) != dest
3419 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3421 reg_eliminate[i].can_eliminate_previous
3422 = reg_eliminate[i].can_eliminate = 0;
3427 /* Verify that the initial elimination offsets did not change since the
3428 last call to set_initial_elim_offsets. This is used to catch cases
3429 where something illegal happened during reload_as_needed that could
3430 cause incorrect code to be generated if we did not check for it. */
3433 verify_initial_elim_offsets (void)
3437 if (!num_eliminable)
3440 #ifdef ELIMINABLE_REGS
3442 struct elim_table *ep;
3444 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3446 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3447 if (t != ep->initial_offset)
3452 INITIAL_FRAME_POINTER_OFFSET (t);
3453 if (t != reg_eliminate[0].initial_offset)
3460 /* Reset all offsets on eliminable registers to their initial values. */
3463 set_initial_elim_offsets (void)
3465 struct elim_table *ep = reg_eliminate;
3467 #ifdef ELIMINABLE_REGS
3468 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3470 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3471 ep->previous_offset = ep->offset = ep->initial_offset;
3474 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3475 ep->previous_offset = ep->offset = ep->initial_offset;
3478 num_not_at_initial_offset = 0;
3481 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3484 set_initial_eh_label_offset (rtx label)
3486 set_label_offsets (label, NULL_RTX, 1);
3489 /* Initialize the known label offsets.
3490 Set a known offset for each forced label to be at the initial offset
3491 of each elimination. We do this because we assume that all
3492 computed jumps occur from a location where each elimination is
3493 at its initial offset.
3494 For all other labels, show that we don't know the offsets. */
3497 set_initial_label_offsets (void)
3500 memset (offsets_known_at, 0, num_labels);
3502 for (x = forced_labels; x; x = XEXP (x, 1))
3504 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3506 for_each_eh_label (set_initial_eh_label_offset);
3509 /* Set all elimination offsets to the known values for the code label given
3513 set_offsets_for_label (rtx insn)
3516 int label_nr = CODE_LABEL_NUMBER (insn);
3517 struct elim_table *ep;
3519 num_not_at_initial_offset = 0;
3520 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3522 ep->offset = ep->previous_offset
3523 = offsets_at[label_nr - first_label_num][i];
3524 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3525 num_not_at_initial_offset++;
3529 /* See if anything that happened changes which eliminations are valid.
3530 For example, on the SPARC, whether or not the frame pointer can
3531 be eliminated can depend on what registers have been used. We need
3532 not check some conditions again (such as flag_omit_frame_pointer)
3533 since they can't have changed. */
3536 update_eliminables (HARD_REG_SET *pset)
3538 int previous_frame_pointer_needed = frame_pointer_needed;
3539 struct elim_table *ep;
3541 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3542 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3543 #ifdef ELIMINABLE_REGS
3544 || ! CAN_ELIMINATE (ep->from, ep->to)
3547 ep->can_eliminate = 0;
3549 /* Look for the case where we have discovered that we can't replace
3550 register A with register B and that means that we will now be
3551 trying to replace register A with register C. This means we can
3552 no longer replace register C with register B and we need to disable
3553 such an elimination, if it exists. This occurs often with A == ap,
3554 B == sp, and C == fp. */
3556 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3558 struct elim_table *op;
3561 if (! ep->can_eliminate && ep->can_eliminate_previous)
3563 /* Find the current elimination for ep->from, if there is a
3565 for (op = reg_eliminate;
3566 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3567 if (op->from == ep->from && op->can_eliminate)
3573 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3575 for (op = reg_eliminate;
3576 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3577 if (op->from == new_to && op->to == ep->to)
3578 op->can_eliminate = 0;
3582 /* See if any registers that we thought we could eliminate the previous
3583 time are no longer eliminable. If so, something has changed and we
3584 must spill the register. Also, recompute the number of eliminable
3585 registers and see if the frame pointer is needed; it is if there is
3586 no elimination of the frame pointer that we can perform. */
3588 frame_pointer_needed = 1;
3589 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3591 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3592 && ep->to != HARD_FRAME_POINTER_REGNUM)
3593 frame_pointer_needed = 0;
3595 if (! ep->can_eliminate && ep->can_eliminate_previous)
3597 ep->can_eliminate_previous = 0;
3598 SET_HARD_REG_BIT (*pset, ep->from);
3603 /* If we didn't need a frame pointer last time, but we do now, spill
3604 the hard frame pointer. */
3605 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3606 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3609 /* Initialize the table of registers to eliminate. */
3612 init_elim_table (void)
3614 struct elim_table *ep;
3615 #ifdef ELIMINABLE_REGS
3616 const struct elim_table_1 *ep1;
3620 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3622 /* Does this function require a frame pointer? */
3624 frame_pointer_needed = (! flag_omit_frame_pointer
3625 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3626 and restore sp for alloca. So we can't eliminate
3627 the frame pointer in that case. At some point,
3628 we should improve this by emitting the
3629 sp-adjusting insns for this case. */
3630 || (current_function_calls_alloca
3631 && EXIT_IGNORE_STACK)
3632 || current_function_accesses_prior_frames
3633 || FRAME_POINTER_REQUIRED);
3637 #ifdef ELIMINABLE_REGS
3638 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3639 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3641 ep->from = ep1->from;
3643 ep->can_eliminate = ep->can_eliminate_previous
3644 = (CAN_ELIMINATE (ep->from, ep->to)
3645 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3648 reg_eliminate[0].from = reg_eliminate_1[0].from;
3649 reg_eliminate[0].to = reg_eliminate_1[0].to;
3650 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3651 = ! frame_pointer_needed;
3654 /* Count the number of eliminable registers and build the FROM and TO
3655 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3656 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3657 We depend on this. */
3658 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3660 num_eliminable += ep->can_eliminate;
3661 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3662 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3666 /* Kick all pseudos out of hard register REGNO.
3668 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3669 because we found we can't eliminate some register. In the case, no pseudos
3670 are allowed to be in the register, even if they are only in a block that
3671 doesn't require spill registers, unlike the case when we are spilling this
3672 hard reg to produce another spill register.
3674 Return nonzero if any pseudos needed to be kicked out. */
3677 spill_hard_reg (unsigned int regno, int cant_eliminate)
3683 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3684 regs_ever_live[regno] = 1;
3687 /* Spill every pseudo reg that was allocated to this reg
3688 or to something that overlaps this reg. */
3690 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3691 if (reg_renumber[i] >= 0
3692 && (unsigned int) reg_renumber[i] <= regno
3693 && ((unsigned int) reg_renumber[i]
3694 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3695 [PSEUDO_REGNO_MODE (i)]
3697 SET_REGNO_REG_SET (&spilled_pseudos, i);
3700 /* After find_reload_regs has been run for all insn that need reloads,
3701 and/or spill_hard_regs was called, this function is used to actually
3702 spill pseudo registers and try to reallocate them. It also sets up the
3703 spill_regs array for use by choose_reload_regs. */
3706 finish_spills (int global)
3708 struct insn_chain *chain;
3709 int something_changed = 0;
3711 reg_set_iterator rsi;
3713 /* Build the spill_regs array for the function. */
3714 /* If there are some registers still to eliminate and one of the spill regs
3715 wasn't ever used before, additional stack space may have to be
3716 allocated to store this register. Thus, we may have changed the offset
3717 between the stack and frame pointers, so mark that something has changed.
3719 One might think that we need only set VAL to 1 if this is a call-used
3720 register. However, the set of registers that must be saved by the
3721 prologue is not identical to the call-used set. For example, the
3722 register used by the call insn for the return PC is a call-used register,
3723 but must be saved by the prologue. */
3726 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3727 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3729 spill_reg_order[i] = n_spills;
3730 spill_regs[n_spills++] = i;
3731 if (num_eliminable && ! regs_ever_live[i])
3732 something_changed = 1;
3733 regs_ever_live[i] = 1;
3736 spill_reg_order[i] = -1;
3738 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3740 /* Record the current hard register the pseudo is allocated to in
3741 pseudo_previous_regs so we avoid reallocating it to the same
3742 hard reg in a later pass. */
3743 gcc_assert (reg_renumber[i] >= 0);
3745 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3746 /* Mark it as no longer having a hard register home. */
3747 reg_renumber[i] = -1;
3748 /* We will need to scan everything again. */
3749 something_changed = 1;
3752 /* Retry global register allocation if possible. */
3755 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3756 /* For every insn that needs reloads, set the registers used as spill
3757 regs in pseudo_forbidden_regs for every pseudo live across the
3759 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3761 EXECUTE_IF_SET_IN_REG_SET
3762 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3764 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3765 chain->used_spill_regs);
3767 EXECUTE_IF_SET_IN_REG_SET
3768 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3770 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3771 chain->used_spill_regs);
3775 /* Retry allocating the spilled pseudos. For each reg, merge the
3776 various reg sets that indicate which hard regs can't be used,
3777 and call retry_global_alloc.
3778 We change spill_pseudos here to only contain pseudos that did not
3779 get a new hard register. */
3780 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3781 if (reg_old_renumber[i] != reg_renumber[i])
3783 HARD_REG_SET forbidden;
3784 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3785 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3786 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3787 retry_global_alloc (i, forbidden);
3788 if (reg_renumber[i] >= 0)
3789 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3793 /* Fix up the register information in the insn chain.
3794 This involves deleting those of the spilled pseudos which did not get
3795 a new hard register home from the live_{before,after} sets. */
3796 for (chain = reload_insn_chain; chain; chain = chain->next)
3798 HARD_REG_SET used_by_pseudos;
3799 HARD_REG_SET used_by_pseudos2;
3801 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3802 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3804 /* Mark any unallocated hard regs as available for spills. That
3805 makes inheritance work somewhat better. */
3806 if (chain->need_reload)
3808 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3809 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3810 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3812 /* Save the old value for the sanity test below. */
3813 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3815 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3816 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3817 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3818 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3820 /* Make sure we only enlarge the set. */
3821 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3827 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3828 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3830 int regno = reg_renumber[i];
3831 if (reg_old_renumber[i] == regno)
3834 alter_reg (i, reg_old_renumber[i]);
3835 reg_old_renumber[i] = regno;
3839 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3841 fprintf (dump_file, " Register %d now in %d.\n\n",
3842 i, reg_renumber[i]);
3846 return something_changed;
3849 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3852 scan_paradoxical_subregs (rtx x)
3856 enum rtx_code code = GET_CODE (x);
3866 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3874 if (REG_P (SUBREG_REG (x))
3875 && (GET_MODE_SIZE (GET_MODE (x))
3876 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3877 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3878 = GET_MODE_SIZE (GET_MODE (x));
3885 fmt = GET_RTX_FORMAT (code);
3886 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3889 scan_paradoxical_subregs (XEXP (x, i));
3890 else if (fmt[i] == 'E')
3893 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3894 scan_paradoxical_subregs (XVECEXP (x, i, j));
3899 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3900 examine all of the reload insns between PREV and NEXT exclusive, and
3901 annotate all that may trap. */
3904 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3906 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3907 unsigned int trap_count;
3913 if (may_trap_p (PATTERN (insn)))
3917 remove_note (insn, note);
3921 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3922 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3926 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3930 /* Reload pseudo-registers into hard regs around each insn as needed.
3931 Additional register load insns are output before the insn that needs it
3932 and perhaps store insns after insns that modify the reloaded pseudo reg.
3934 reg_last_reload_reg and reg_reloaded_contents keep track of
3935 which registers are already available in reload registers.
3936 We update these for the reloads that we perform,
3937 as the insns are scanned. */
3940 reload_as_needed (int live_known)
3942 struct insn_chain *chain;
3943 #if defined (AUTO_INC_DEC)
3948 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3949 memset (spill_reg_store, 0, sizeof spill_reg_store);
3950 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3951 INIT_REG_SET (®_has_output_reload);
3952 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3953 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3955 set_initial_elim_offsets ();
3957 for (chain = reload_insn_chain; chain; chain = chain->next)
3960 rtx insn = chain->insn;
3961 rtx old_next = NEXT_INSN (insn);
3963 /* If we pass a label, copy the offsets from the label information
3964 into the current offsets of each elimination. */
3966 set_offsets_for_label (insn);
3968 else if (INSN_P (insn))
3970 regset_head regs_to_forget;
3971 INIT_REG_SET (®s_to_forget);
3972 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
3974 /* If this is a USE and CLOBBER of a MEM, ensure that any
3975 references to eliminable registers have been removed. */
3977 if ((GET_CODE (PATTERN (insn)) == USE
3978 || GET_CODE (PATTERN (insn)) == CLOBBER)
3979 && MEM_P (XEXP (PATTERN (insn), 0)))
3980 XEXP (XEXP (PATTERN (insn), 0), 0)
3981 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3982 GET_MODE (XEXP (PATTERN (insn), 0)),
3985 /* If we need to do register elimination processing, do so.
3986 This might delete the insn, in which case we are done. */
3987 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3989 eliminate_regs_in_insn (insn, 1);
3992 update_eliminable_offsets ();
3993 CLEAR_REG_SET (®s_to_forget);
3998 /* If need_elim is nonzero but need_reload is zero, one might think
3999 that we could simply set n_reloads to 0. However, find_reloads
4000 could have done some manipulation of the insn (such as swapping
4001 commutative operands), and these manipulations are lost during
4002 the first pass for every insn that needs register elimination.
4003 So the actions of find_reloads must be redone here. */
4005 if (! chain->need_elim && ! chain->need_reload
4006 && ! chain->need_operand_change)
4008 /* First find the pseudo regs that must be reloaded for this insn.
4009 This info is returned in the tables reload_... (see reload.h).
4010 Also modify the body of INSN by substituting RELOAD
4011 rtx's for those pseudo regs. */
4014 CLEAR_REG_SET (®_has_output_reload);
4015 CLEAR_HARD_REG_SET (reg_is_output_reload);
4017 find_reloads (insn, 1, spill_indirect_levels, live_known,
4023 rtx next = NEXT_INSN (insn);
4026 prev = PREV_INSN (insn);
4028 /* Now compute which reload regs to reload them into. Perhaps
4029 reusing reload regs from previous insns, or else output
4030 load insns to reload them. Maybe output store insns too.
4031 Record the choices of reload reg in reload_reg_rtx. */
4032 choose_reload_regs (chain);
4034 /* Merge any reloads that we didn't combine for fear of
4035 increasing the number of spill registers needed but now
4036 discover can be safely merged. */
4037 if (SMALL_REGISTER_CLASSES)
4038 merge_assigned_reloads (insn);
4040 /* Generate the insns to reload operands into or out of
4041 their reload regs. */
4042 emit_reload_insns (chain);
4044 /* Substitute the chosen reload regs from reload_reg_rtx
4045 into the insn's body (or perhaps into the bodies of other
4046 load and store insn that we just made for reloading
4047 and that we moved the structure into). */
4048 subst_reloads (insn);
4050 /* Adjust the exception region notes for loads and stores. */
4051 if (flag_non_call_exceptions && !CALL_P (insn))
4052 fixup_eh_region_note (insn, prev, next);
4054 /* If this was an ASM, make sure that all the reload insns
4055 we have generated are valid. If not, give an error
4057 if (asm_noperands (PATTERN (insn)) >= 0)
4058 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4059 if (p != insn && INSN_P (p)
4060 && GET_CODE (PATTERN (p)) != USE
4061 && (recog_memoized (p) < 0
4062 || (extract_insn (p), ! constrain_operands (1))))
4064 error_for_asm (insn,
4065 "%<asm%> operand requires "
4066 "impossible reload");
4071 if (num_eliminable && chain->need_elim)
4072 update_eliminable_offsets ();
4074 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4075 is no longer validly lying around to save a future reload.
4076 Note that this does not detect pseudos that were reloaded
4077 for this insn in order to be stored in
4078 (obeying register constraints). That is correct; such reload
4079 registers ARE still valid. */
4080 forget_marked_reloads (®s_to_forget);
4081 CLEAR_REG_SET (®s_to_forget);
4083 /* There may have been CLOBBER insns placed after INSN. So scan
4084 between INSN and NEXT and use them to forget old reloads. */
4085 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4086 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4087 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4090 /* Likewise for regs altered by auto-increment in this insn.
4091 REG_INC notes have been changed by reloading:
4092 find_reloads_address_1 records substitutions for them,
4093 which have been performed by subst_reloads above. */
4094 for (i = n_reloads - 1; i >= 0; i--)
4096 rtx in_reg = rld[i].in_reg;
4099 enum rtx_code code = GET_CODE (in_reg);
4100 /* PRE_INC / PRE_DEC will have the reload register ending up
4101 with the same value as the stack slot, but that doesn't
4102 hold true for POST_INC / POST_DEC. Either we have to
4103 convert the memory access to a true POST_INC / POST_DEC,
4104 or we can't use the reload register for inheritance. */
4105 if ((code == POST_INC || code == POST_DEC)
4106 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4107 REGNO (rld[i].reg_rtx))
4108 /* Make sure it is the inc/dec pseudo, and not
4109 some other (e.g. output operand) pseudo. */
4110 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4111 == REGNO (XEXP (in_reg, 0))))
4114 rtx reload_reg = rld[i].reg_rtx;
4115 enum machine_mode mode = GET_MODE (reload_reg);
4119 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4121 /* We really want to ignore REG_INC notes here, so
4122 use PATTERN (p) as argument to reg_set_p . */
4123 if (reg_set_p (reload_reg, PATTERN (p)))
4125 n = count_occurrences (PATTERN (p), reload_reg, 0);
4130 n = validate_replace_rtx (reload_reg,
4131 gen_rtx_fmt_e (code,
4136 /* We must also verify that the constraints
4137 are met after the replacement. */
4140 n = constrain_operands (1);
4144 /* If the constraints were not met, then
4145 undo the replacement. */
4148 validate_replace_rtx (gen_rtx_fmt_e (code,
4161 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4163 /* Mark this as having an output reload so that the
4164 REG_INC processing code below won't invalidate
4165 the reload for inheritance. */
4166 SET_HARD_REG_BIT (reg_is_output_reload,
4167 REGNO (reload_reg));
4168 SET_REGNO_REG_SET (®_has_output_reload,
4169 REGNO (XEXP (in_reg, 0)));
4172 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4175 else if ((code == PRE_INC || code == PRE_DEC)
4176 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4177 REGNO (rld[i].reg_rtx))
4178 /* Make sure it is the inc/dec pseudo, and not
4179 some other (e.g. output operand) pseudo. */
4180 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4181 == REGNO (XEXP (in_reg, 0))))
4183 SET_HARD_REG_BIT (reg_is_output_reload,
4184 REGNO (rld[i].reg_rtx));
4185 SET_REGNO_REG_SET (®_has_output_reload,
4186 REGNO (XEXP (in_reg, 0)));
4190 /* If a pseudo that got a hard register is auto-incremented,
4191 we must purge records of copying it into pseudos without
4193 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4194 if (REG_NOTE_KIND (x) == REG_INC)
4196 /* See if this pseudo reg was reloaded in this insn.
4197 If so, its last-reload info is still valid
4198 because it is based on this insn's reload. */
4199 for (i = 0; i < n_reloads; i++)
4200 if (rld[i].out == XEXP (x, 0))
4204 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4208 /* A reload reg's contents are unknown after a label. */
4210 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4212 /* Don't assume a reload reg is still good after a call insn
4213 if it is a call-used reg, or if it contains a value that will
4214 be partially clobbered by the call. */
4215 else if (CALL_P (insn))
4217 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4218 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4223 free (reg_last_reload_reg);
4224 CLEAR_REG_SET (®_has_output_reload);
4227 /* Discard all record of any value reloaded from X,
4228 or reloaded in X from someplace else;
4229 unless X is an output reload reg of the current insn.
4231 X may be a hard reg (the reload reg)
4232 or it may be a pseudo reg that was reloaded from.
4234 When DATA is non-NULL just mark the registers in regset
4235 to be forgotten later. */
4238 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4243 regset regs = (regset) data;
4245 /* note_stores does give us subregs of hard regs,
4246 subreg_regno_offset requires a hard reg. */
4247 while (GET_CODE (x) == SUBREG)
4249 /* We ignore the subreg offset when calculating the regno,
4250 because we are using the entire underlying hard register
4260 if (regno >= FIRST_PSEUDO_REGISTER)
4266 nr = hard_regno_nregs[regno][GET_MODE (x)];
4267 /* Storing into a spilled-reg invalidates its contents.
4268 This can happen if a block-local pseudo is allocated to that reg
4269 and it wasn't spilled because this block's total need is 0.
4270 Then some insn might have an optional reload and use this reg. */
4272 for (i = 0; i < nr; i++)
4273 /* But don't do this if the reg actually serves as an output
4274 reload reg in the current instruction. */
4276 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4278 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4279 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4280 spill_reg_store[regno + i] = 0;
4286 SET_REGNO_REG_SET (regs, regno + nr);
4289 /* Since value of X has changed,
4290 forget any value previously copied from it. */
4293 /* But don't forget a copy if this is the output reload
4294 that establishes the copy's validity. */
4296 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4297 reg_last_reload_reg[regno + nr] = 0;
4301 /* Forget the reloads marked in regset by previous function. */
4303 forget_marked_reloads (regset regs)
4306 reg_set_iterator rsi;
4307 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4309 if (reg < FIRST_PSEUDO_REGISTER
4310 /* But don't do this if the reg actually serves as an output
4311 reload reg in the current instruction. */
4313 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4315 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4316 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4317 spill_reg_store[reg] = 0;
4320 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4321 reg_last_reload_reg[reg] = 0;
4325 /* The following HARD_REG_SETs indicate when each hard register is
4326 used for a reload of various parts of the current insn. */
4328 /* If reg is unavailable for all reloads. */
4329 static HARD_REG_SET reload_reg_unavailable;
4330 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4331 static HARD_REG_SET reload_reg_used;
4332 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4333 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4334 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4335 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4336 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4337 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4338 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4339 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4340 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4341 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4342 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4343 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4344 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4345 static HARD_REG_SET reload_reg_used_in_op_addr;
4346 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4347 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4348 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4349 static HARD_REG_SET reload_reg_used_in_insn;
4350 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4351 static HARD_REG_SET reload_reg_used_in_other_addr;
4353 /* If reg is in use as a reload reg for any sort of reload. */
4354 static HARD_REG_SET reload_reg_used_at_all;
4356 /* If reg is use as an inherited reload. We just mark the first register
4358 static HARD_REG_SET reload_reg_used_for_inherit;
4360 /* Records which hard regs are used in any way, either as explicit use or
4361 by being allocated to a pseudo during any point of the current insn. */
4362 static HARD_REG_SET reg_used_in_insn;
4364 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4365 TYPE. MODE is used to indicate how many consecutive regs are
4369 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4370 enum machine_mode mode)
4372 unsigned int nregs = hard_regno_nregs[regno][mode];
4375 for (i = regno; i < nregs + regno; i++)
4380 SET_HARD_REG_BIT (reload_reg_used, i);
4383 case RELOAD_FOR_INPUT_ADDRESS:
4384 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4387 case RELOAD_FOR_INPADDR_ADDRESS:
4388 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4391 case RELOAD_FOR_OUTPUT_ADDRESS:
4392 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4395 case RELOAD_FOR_OUTADDR_ADDRESS:
4396 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4399 case RELOAD_FOR_OPERAND_ADDRESS:
4400 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4403 case RELOAD_FOR_OPADDR_ADDR:
4404 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4407 case RELOAD_FOR_OTHER_ADDRESS:
4408 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4411 case RELOAD_FOR_INPUT:
4412 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4415 case RELOAD_FOR_OUTPUT:
4416 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4419 case RELOAD_FOR_INSN:
4420 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4424 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4428 /* Similarly, but show REGNO is no longer in use for a reload. */
4431 clear_reload_reg_in_use (unsigned int regno, int opnum,
4432 enum reload_type type, enum machine_mode mode)
4434 unsigned int nregs = hard_regno_nregs[regno][mode];
4435 unsigned int start_regno, end_regno, r;
4437 /* A complication is that for some reload types, inheritance might
4438 allow multiple reloads of the same types to share a reload register.
4439 We set check_opnum if we have to check only reloads with the same
4440 operand number, and check_any if we have to check all reloads. */
4441 int check_opnum = 0;
4443 HARD_REG_SET *used_in_set;
4448 used_in_set = &reload_reg_used;
4451 case RELOAD_FOR_INPUT_ADDRESS:
4452 used_in_set = &reload_reg_used_in_input_addr[opnum];
4455 case RELOAD_FOR_INPADDR_ADDRESS:
4457 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4460 case RELOAD_FOR_OUTPUT_ADDRESS:
4461 used_in_set = &reload_reg_used_in_output_addr[opnum];
4464 case RELOAD_FOR_OUTADDR_ADDRESS:
4466 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4469 case RELOAD_FOR_OPERAND_ADDRESS:
4470 used_in_set = &reload_reg_used_in_op_addr;
4473 case RELOAD_FOR_OPADDR_ADDR:
4475 used_in_set = &reload_reg_used_in_op_addr_reload;
4478 case RELOAD_FOR_OTHER_ADDRESS:
4479 used_in_set = &reload_reg_used_in_other_addr;
4483 case RELOAD_FOR_INPUT:
4484 used_in_set = &reload_reg_used_in_input[opnum];
4487 case RELOAD_FOR_OUTPUT:
4488 used_in_set = &reload_reg_used_in_output[opnum];
4491 case RELOAD_FOR_INSN:
4492 used_in_set = &reload_reg_used_in_insn;
4497 /* We resolve conflicts with remaining reloads of the same type by
4498 excluding the intervals of reload registers by them from the
4499 interval of freed reload registers. Since we only keep track of
4500 one set of interval bounds, we might have to exclude somewhat
4501 more than what would be necessary if we used a HARD_REG_SET here.
4502 But this should only happen very infrequently, so there should
4503 be no reason to worry about it. */
4505 start_regno = regno;
4506 end_regno = regno + nregs;
4507 if (check_opnum || check_any)
4509 for (i = n_reloads - 1; i >= 0; i--)
4511 if (rld[i].when_needed == type
4512 && (check_any || rld[i].opnum == opnum)
4515 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4516 unsigned int conflict_end
4518 + hard_regno_nregs[conflict_start][rld[i].mode]);
4520 /* If there is an overlap with the first to-be-freed register,
4521 adjust the interval start. */
4522 if (conflict_start <= start_regno && conflict_end > start_regno)
4523 start_regno = conflict_end;
4524 /* Otherwise, if there is a conflict with one of the other
4525 to-be-freed registers, adjust the interval end. */
4526 if (conflict_start > start_regno && conflict_start < end_regno)
4527 end_regno = conflict_start;
4532 for (r = start_regno; r < end_regno; r++)
4533 CLEAR_HARD_REG_BIT (*used_in_set, r);
4536 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4537 specified by OPNUM and TYPE. */
4540 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4544 /* In use for a RELOAD_OTHER means it's not available for anything. */
4545 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4546 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4552 /* In use for anything means we can't use it for RELOAD_OTHER. */
4553 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4554 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4555 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4556 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4559 for (i = 0; i < reload_n_operands; i++)
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4561 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4562 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4564 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4570 case RELOAD_FOR_INPUT:
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4578 /* If it is used for some other input, can't use it. */
4579 for (i = 0; i < reload_n_operands; i++)
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4583 /* If it is used in a later operand's address, can't use it. */
4584 for (i = opnum + 1; i < reload_n_operands; i++)
4585 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4586 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4591 case RELOAD_FOR_INPUT_ADDRESS:
4592 /* Can't use a register if it is used for an input address for this
4593 operand or used as an input in an earlier one. */
4594 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4595 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4598 for (i = 0; i < opnum; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4604 case RELOAD_FOR_INPADDR_ADDRESS:
4605 /* Can't use a register if it is used for an input address
4606 for this operand or used as an input in an earlier
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4611 for (i = 0; i < opnum; i++)
4612 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4617 case RELOAD_FOR_OUTPUT_ADDRESS:
4618 /* Can't use a register if it is used for an output address for this
4619 operand or used as an output in this or a later operand. Note
4620 that multiple output operands are emitted in reverse order, so
4621 the conflicting ones are those with lower indices. */
4622 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4625 for (i = 0; i <= opnum; i++)
4626 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4631 case RELOAD_FOR_OUTADDR_ADDRESS:
4632 /* Can't use a register if it is used for an output address
4633 for this operand or used as an output in this or a
4634 later operand. Note that multiple output operands are
4635 emitted in reverse order, so the conflicting ones are
4636 those with lower indices. */
4637 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4640 for (i = 0; i <= opnum; i++)
4641 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4646 case RELOAD_FOR_OPERAND_ADDRESS:
4647 for (i = 0; i < reload_n_operands; i++)
4648 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4651 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4652 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4654 case RELOAD_FOR_OPADDR_ADDR:
4655 for (i = 0; i < reload_n_operands; i++)
4656 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4659 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4661 case RELOAD_FOR_OUTPUT:
4662 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4663 outputs, or an operand address for this or an earlier output.
4664 Note that multiple output operands are emitted in reverse order,
4665 so the conflicting ones are those with higher indices. */
4666 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4669 for (i = 0; i < reload_n_operands; i++)
4670 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4673 for (i = opnum; i < reload_n_operands; i++)
4674 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4675 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4680 case RELOAD_FOR_INSN:
4681 for (i = 0; i < reload_n_operands; i++)
4682 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4683 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4686 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4687 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4689 case RELOAD_FOR_OTHER_ADDRESS:
4690 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4697 /* Return 1 if the value in reload reg REGNO, as used by a reload
4698 needed for the part of the insn specified by OPNUM and TYPE,
4699 is still available in REGNO at the end of the insn.
4701 We can assume that the reload reg was already tested for availability
4702 at the time it is needed, and we should not check this again,
4703 in case the reg has already been marked in use. */
4706 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4713 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4714 its value must reach the end. */
4717 /* If this use is for part of the insn,
4718 its value reaches if no subsequent part uses the same register.
4719 Just like the above function, don't try to do this with lots
4722 case RELOAD_FOR_OTHER_ADDRESS:
4723 /* Here we check for everything else, since these don't conflict
4724 with anything else and everything comes later. */
4726 for (i = 0; i < reload_n_operands; i++)
4727 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4728 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4729 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4730 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4731 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4732 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4735 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4736 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4737 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4738 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4740 case RELOAD_FOR_INPUT_ADDRESS:
4741 case RELOAD_FOR_INPADDR_ADDRESS:
4742 /* Similar, except that we check only for this and subsequent inputs
4743 and the address of only subsequent inputs and we do not need
4744 to check for RELOAD_OTHER objects since they are known not to
4747 for (i = opnum; i < reload_n_operands; i++)
4748 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4751 for (i = opnum + 1; i < reload_n_operands; i++)
4752 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4753 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4756 for (i = 0; i < reload_n_operands; i++)
4757 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4758 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4759 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4762 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4765 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4766 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4767 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4769 case RELOAD_FOR_INPUT:
4770 /* Similar to input address, except we start at the next operand for
4771 both input and input address and we do not check for
4772 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4775 for (i = opnum + 1; i < reload_n_operands; i++)
4776 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4777 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4778 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4781 /* ... fall through ... */
4783 case RELOAD_FOR_OPERAND_ADDRESS:
4784 /* Check outputs and their addresses. */
4786 for (i = 0; i < reload_n_operands; i++)
4787 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4788 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4789 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4792 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4794 case RELOAD_FOR_OPADDR_ADDR:
4795 for (i = 0; i < reload_n_operands; i++)
4796 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4797 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4798 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4801 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4802 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4803 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4805 case RELOAD_FOR_INSN:
4806 /* These conflict with other outputs with RELOAD_OTHER. So
4807 we need only check for output addresses. */
4809 opnum = reload_n_operands;
4811 /* ... fall through ... */
4813 case RELOAD_FOR_OUTPUT:
4814 case RELOAD_FOR_OUTPUT_ADDRESS:
4815 case RELOAD_FOR_OUTADDR_ADDRESS:
4816 /* We already know these can't conflict with a later output. So the
4817 only thing to check are later output addresses.
4818 Note that multiple output operands are emitted in reverse order,
4819 so the conflicting ones are those with lower indices. */
4820 for (i = 0; i < opnum; i++)
4821 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4833 /* Returns whether R1 and R2 are uniquely chained: the value of one
4834 is used by the other, and that value is not used by any other
4835 reload for this insn. This is used to partially undo the decision
4836 made in find_reloads when in the case of multiple
4837 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4838 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4839 reloads. This code tries to avoid the conflict created by that
4840 change. It might be cleaner to explicitly keep track of which
4841 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4842 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4843 this after the fact. */
4845 reloads_unique_chain_p (int r1, int r2)
4849 /* We only check input reloads. */
4850 if (! rld[r1].in || ! rld[r2].in)
4853 /* Avoid anything with output reloads. */
4854 if (rld[r1].out || rld[r2].out)
4857 /* "chained" means one reload is a component of the other reload,
4858 not the same as the other reload. */
4859 if (rld[r1].opnum != rld[r2].opnum
4860 || rtx_equal_p (rld[r1].in, rld[r2].in)
4861 || rld[r1].optional || rld[r2].optional
4862 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4863 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4866 for (i = 0; i < n_reloads; i ++)
4867 /* Look for input reloads that aren't our two */
4868 if (i != r1 && i != r2 && rld[i].in)
4870 /* If our reload is mentioned at all, it isn't a simple chain. */
4871 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4877 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4880 This function uses the same algorithm as reload_reg_free_p above. */
4883 reloads_conflict (int r1, int r2)
4885 enum reload_type r1_type = rld[r1].when_needed;
4886 enum reload_type r2_type = rld[r2].when_needed;
4887 int r1_opnum = rld[r1].opnum;
4888 int r2_opnum = rld[r2].opnum;
4890 /* RELOAD_OTHER conflicts with everything. */
4891 if (r2_type == RELOAD_OTHER)
4894 /* Otherwise, check conflicts differently for each type. */
4898 case RELOAD_FOR_INPUT:
4899 return (r2_type == RELOAD_FOR_INSN
4900 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4901 || r2_type == RELOAD_FOR_OPADDR_ADDR
4902 || r2_type == RELOAD_FOR_INPUT
4903 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4904 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4905 && r2_opnum > r1_opnum));
4907 case RELOAD_FOR_INPUT_ADDRESS:
4908 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4909 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4911 case RELOAD_FOR_INPADDR_ADDRESS:
4912 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4913 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4915 case RELOAD_FOR_OUTPUT_ADDRESS:
4916 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4917 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4919 case RELOAD_FOR_OUTADDR_ADDRESS:
4920 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4921 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4923 case RELOAD_FOR_OPERAND_ADDRESS:
4924 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4925 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
4926 && !reloads_unique_chain_p (r1, r2)));
4928 case RELOAD_FOR_OPADDR_ADDR:
4929 return (r2_type == RELOAD_FOR_INPUT
4930 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4932 case RELOAD_FOR_OUTPUT:
4933 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4934 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4935 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4936 && r2_opnum >= r1_opnum));
4938 case RELOAD_FOR_INSN:
4939 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4940 || r2_type == RELOAD_FOR_INSN
4941 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4943 case RELOAD_FOR_OTHER_ADDRESS:
4944 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4954 /* Indexed by reload number, 1 if incoming value
4955 inherited from previous insns. */
4956 static char reload_inherited[MAX_RELOADS];
4958 /* For an inherited reload, this is the insn the reload was inherited from,
4959 if we know it. Otherwise, this is 0. */
4960 static rtx reload_inheritance_insn[MAX_RELOADS];
4962 /* If nonzero, this is a place to get the value of the reload,
4963 rather than using reload_in. */
4964 static rtx reload_override_in[MAX_RELOADS];
4966 /* For each reload, the hard register number of the register used,
4967 or -1 if we did not need a register for this reload. */
4968 static int reload_spill_index[MAX_RELOADS];
4970 /* Subroutine of free_for_value_p, used to check a single register.
4971 START_REGNO is the starting regno of the full reload register
4972 (possibly comprising multiple hard registers) that we are considering. */
4975 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4976 enum reload_type type, rtx value, rtx out,
4977 int reloadnum, int ignore_address_reloads)
4980 /* Set if we see an input reload that must not share its reload register
4981 with any new earlyclobber, but might otherwise share the reload
4982 register with an output or input-output reload. */
4983 int check_earlyclobber = 0;
4987 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4990 if (out == const0_rtx)
4996 /* We use some pseudo 'time' value to check if the lifetimes of the
4997 new register use would overlap with the one of a previous reload
4998 that is not read-only or uses a different value.
4999 The 'time' used doesn't have to be linear in any shape or form, just
5001 Some reload types use different 'buckets' for each operand.
5002 So there are MAX_RECOG_OPERANDS different time values for each
5004 We compute TIME1 as the time when the register for the prospective
5005 new reload ceases to be live, and TIME2 for each existing
5006 reload as the time when that the reload register of that reload
5008 Where there is little to be gained by exact lifetime calculations,
5009 we just make conservative assumptions, i.e. a longer lifetime;
5010 this is done in the 'default:' cases. */
5013 case RELOAD_FOR_OTHER_ADDRESS:
5014 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5015 time1 = copy ? 0 : 1;
5018 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5020 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5021 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5022 respectively, to the time values for these, we get distinct time
5023 values. To get distinct time values for each operand, we have to
5024 multiply opnum by at least three. We round that up to four because
5025 multiply by four is often cheaper. */
5026 case RELOAD_FOR_INPADDR_ADDRESS:
5027 time1 = opnum * 4 + 2;
5029 case RELOAD_FOR_INPUT_ADDRESS:
5030 time1 = opnum * 4 + 3;
5032 case RELOAD_FOR_INPUT:
5033 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5034 executes (inclusive). */
5035 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5037 case RELOAD_FOR_OPADDR_ADDR:
5039 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5040 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5042 case RELOAD_FOR_OPERAND_ADDRESS:
5043 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5045 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5047 case RELOAD_FOR_OUTADDR_ADDRESS:
5048 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5050 case RELOAD_FOR_OUTPUT_ADDRESS:
5051 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5054 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5057 for (i = 0; i < n_reloads; i++)
5059 rtx reg = rld[i].reg_rtx;
5060 if (reg && REG_P (reg)
5061 && ((unsigned) regno - true_regnum (reg)
5062 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5065 rtx other_input = rld[i].in;
5067 /* If the other reload loads the same input value, that
5068 will not cause a conflict only if it's loading it into
5069 the same register. */
5070 if (true_regnum (reg) != start_regno)
5071 other_input = NULL_RTX;
5072 if (! other_input || ! rtx_equal_p (other_input, value)
5073 || rld[i].out || out)
5076 switch (rld[i].when_needed)
5078 case RELOAD_FOR_OTHER_ADDRESS:
5081 case RELOAD_FOR_INPADDR_ADDRESS:
5082 /* find_reloads makes sure that a
5083 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5084 by at most one - the first -
5085 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5086 address reload is inherited, the address address reload
5087 goes away, so we can ignore this conflict. */
5088 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5089 && ignore_address_reloads
5090 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5091 Then the address address is still needed to store
5092 back the new address. */
5093 && ! rld[reloadnum].out)
5095 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5096 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5098 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5099 && ignore_address_reloads
5100 /* Unless we are reloading an auto_inc expression. */
5101 && ! rld[reloadnum].out)
5103 time2 = rld[i].opnum * 4 + 2;
5105 case RELOAD_FOR_INPUT_ADDRESS:
5106 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5107 && ignore_address_reloads
5108 && ! rld[reloadnum].out)
5110 time2 = rld[i].opnum * 4 + 3;
5112 case RELOAD_FOR_INPUT:
5113 time2 = rld[i].opnum * 4 + 4;
5114 check_earlyclobber = 1;
5116 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5117 == MAX_RECOG_OPERAND * 4 */
5118 case RELOAD_FOR_OPADDR_ADDR:
5119 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5120 && ignore_address_reloads
5121 && ! rld[reloadnum].out)
5123 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5125 case RELOAD_FOR_OPERAND_ADDRESS:
5126 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5127 check_earlyclobber = 1;
5129 case RELOAD_FOR_INSN:
5130 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5132 case RELOAD_FOR_OUTPUT:
5133 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5134 instruction is executed. */
5135 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5137 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5138 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5140 case RELOAD_FOR_OUTADDR_ADDRESS:
5141 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5142 && ignore_address_reloads
5143 && ! rld[reloadnum].out)
5145 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5147 case RELOAD_FOR_OUTPUT_ADDRESS:
5148 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5151 /* If there is no conflict in the input part, handle this
5152 like an output reload. */
5153 if (! rld[i].in || rtx_equal_p (other_input, value))
5155 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5156 /* Earlyclobbered outputs must conflict with inputs. */
5157 if (earlyclobber_operand_p (rld[i].out))
5158 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5163 /* RELOAD_OTHER might be live beyond instruction execution,
5164 but this is not obvious when we set time2 = 1. So check
5165 here if there might be a problem with the new reload
5166 clobbering the register used by the RELOAD_OTHER. */
5174 && (! rld[i].in || rld[i].out
5175 || ! rtx_equal_p (other_input, value)))
5176 || (out && rld[reloadnum].out_reg
5177 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5183 /* Earlyclobbered outputs must conflict with inputs. */
5184 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5190 /* Return 1 if the value in reload reg REGNO, as used by a reload
5191 needed for the part of the insn specified by OPNUM and TYPE,
5192 may be used to load VALUE into it.
5194 MODE is the mode in which the register is used, this is needed to
5195 determine how many hard regs to test.
5197 Other read-only reloads with the same value do not conflict
5198 unless OUT is nonzero and these other reloads have to live while
5199 output reloads live.
5200 If OUT is CONST0_RTX, this is a special case: it means that the
5201 test should not be for using register REGNO as reload register, but
5202 for copying from register REGNO into the reload register.
5204 RELOADNUM is the number of the reload we want to load this value for;
5205 a reload does not conflict with itself.
5207 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5208 reloads that load an address for the very reload we are considering.
5210 The caller has to make sure that there is no conflict with the return
5214 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5215 enum reload_type type, rtx value, rtx out, int reloadnum,
5216 int ignore_address_reloads)
5218 int nregs = hard_regno_nregs[regno][mode];
5220 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5221 value, out, reloadnum,
5222 ignore_address_reloads))
5227 /* Return nonzero if the rtx X is invariant over the current function. */
5228 /* ??? Actually, the places where we use this expect exactly what is
5229 tested here, and not everything that is function invariant. In
5230 particular, the frame pointer and arg pointer are special cased;
5231 pic_offset_table_rtx is not, and we must not spill these things to
5235 function_invariant_p (rtx x)
5239 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5241 if (GET_CODE (x) == PLUS
5242 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5243 && CONSTANT_P (XEXP (x, 1)))
5248 /* Determine whether the reload reg X overlaps any rtx'es used for
5249 overriding inheritance. Return nonzero if so. */
5252 conflicts_with_override (rtx x)
5255 for (i = 0; i < n_reloads; i++)
5256 if (reload_override_in[i]
5257 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5262 /* Give an error message saying we failed to find a reload for INSN,
5263 and clear out reload R. */
5265 failed_reload (rtx insn, int r)
5267 if (asm_noperands (PATTERN (insn)) < 0)
5268 /* It's the compiler's fault. */
5269 fatal_insn ("could not find a spill register", insn);
5271 /* It's the user's fault; the operand's mode and constraint
5272 don't match. Disable this reload so we don't crash in final. */
5273 error_for_asm (insn,
5274 "%<asm%> operand constraint incompatible with operand size");
5278 rld[r].optional = 1;
5279 rld[r].secondary_p = 1;
5282 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5283 for reload R. If it's valid, get an rtx for it. Return nonzero if
5286 set_reload_reg (int i, int r)
5289 rtx reg = spill_reg_rtx[i];
5291 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5292 spill_reg_rtx[i] = reg
5293 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5295 regno = true_regnum (reg);
5297 /* Detect when the reload reg can't hold the reload mode.
5298 This used to be one `if', but Sequent compiler can't handle that. */
5299 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5301 enum machine_mode test_mode = VOIDmode;
5303 test_mode = GET_MODE (rld[r].in);
5304 /* If rld[r].in has VOIDmode, it means we will load it
5305 in whatever mode the reload reg has: to wit, rld[r].mode.
5306 We have already tested that for validity. */
5307 /* Aside from that, we need to test that the expressions
5308 to reload from or into have modes which are valid for this
5309 reload register. Otherwise the reload insns would be invalid. */
5310 if (! (rld[r].in != 0 && test_mode != VOIDmode
5311 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5312 if (! (rld[r].out != 0
5313 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5315 /* The reg is OK. */
5318 /* Mark as in use for this insn the reload regs we use
5320 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5321 rld[r].when_needed, rld[r].mode);
5323 rld[r].reg_rtx = reg;
5324 reload_spill_index[r] = spill_regs[i];
5331 /* Find a spill register to use as a reload register for reload R.
5332 LAST_RELOAD is nonzero if this is the last reload for the insn being
5335 Set rld[R].reg_rtx to the register allocated.
5337 We return 1 if successful, or 0 if we couldn't find a spill reg and
5338 we didn't change anything. */
5341 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5346 /* If we put this reload ahead, thinking it is a group,
5347 then insist on finding a group. Otherwise we can grab a
5348 reg that some other reload needs.
5349 (That can happen when we have a 68000 DATA_OR_FP_REG
5350 which is a group of data regs or one fp reg.)
5351 We need not be so restrictive if there are no more reloads
5354 ??? Really it would be nicer to have smarter handling
5355 for that kind of reg class, where a problem like this is normal.
5356 Perhaps those classes should be avoided for reloading
5357 by use of more alternatives. */
5359 int force_group = rld[r].nregs > 1 && ! last_reload;
5361 /* If we want a single register and haven't yet found one,
5362 take any reg in the right class and not in use.
5363 If we want a consecutive group, here is where we look for it.
5365 We use two passes so we can first look for reload regs to
5366 reuse, which are already in use for other reloads in this insn,
5367 and only then use additional registers.
5368 I think that maximizing reuse is needed to make sure we don't
5369 run out of reload regs. Suppose we have three reloads, and
5370 reloads A and B can share regs. These need two regs.
5371 Suppose A and B are given different regs.
5372 That leaves none for C. */
5373 for (pass = 0; pass < 2; pass++)
5375 /* I is the index in spill_regs.
5376 We advance it round-robin between insns to use all spill regs
5377 equally, so that inherited reloads have a chance
5378 of leapfrogging each other. */
5382 for (count = 0; count < n_spills; count++)
5384 int class = (int) rld[r].class;
5390 regnum = spill_regs[i];
5392 if ((reload_reg_free_p (regnum, rld[r].opnum,
5395 /* We check reload_reg_used to make sure we
5396 don't clobber the return register. */
5397 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5398 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5399 rld[r].when_needed, rld[r].in,
5401 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5402 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5403 /* Look first for regs to share, then for unshared. But
5404 don't share regs used for inherited reloads; they are
5405 the ones we want to preserve. */
5407 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5409 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5412 int nr = hard_regno_nregs[regnum][rld[r].mode];
5413 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5414 (on 68000) got us two FP regs. If NR is 1,
5415 we would reject both of them. */
5418 /* If we need only one reg, we have already won. */
5421 /* But reject a single reg if we demand a group. */
5426 /* Otherwise check that as many consecutive regs as we need
5427 are available here. */
5430 int regno = regnum + nr - 1;
5431 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5432 && spill_reg_order[regno] >= 0
5433 && reload_reg_free_p (regno, rld[r].opnum,
5434 rld[r].when_needed)))
5443 /* If we found something on pass 1, omit pass 2. */
5444 if (count < n_spills)
5448 /* We should have found a spill register by now. */
5449 if (count >= n_spills)
5452 /* I is the index in SPILL_REG_RTX of the reload register we are to
5453 allocate. Get an rtx for it and find its register number. */
5455 return set_reload_reg (i, r);
5458 /* Initialize all the tables needed to allocate reload registers.
5459 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5460 is the array we use to restore the reg_rtx field for every reload. */
5463 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5467 for (i = 0; i < n_reloads; i++)
5468 rld[i].reg_rtx = save_reload_reg_rtx[i];
5470 memset (reload_inherited, 0, MAX_RELOADS);
5471 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5472 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5474 CLEAR_HARD_REG_SET (reload_reg_used);
5475 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5476 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5477 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5478 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5479 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5481 CLEAR_HARD_REG_SET (reg_used_in_insn);
5484 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5485 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5486 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5487 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5488 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5489 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5492 for (i = 0; i < reload_n_operands; i++)
5494 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5495 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5496 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5497 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5498 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5499 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5502 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5504 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5506 for (i = 0; i < n_reloads; i++)
5507 /* If we have already decided to use a certain register,
5508 don't use it in another way. */
5510 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5511 rld[i].when_needed, rld[i].mode);
5514 /* Assign hard reg targets for the pseudo-registers we must reload
5515 into hard regs for this insn.
5516 Also output the instructions to copy them in and out of the hard regs.
5518 For machines with register classes, we are responsible for
5519 finding a reload reg in the proper class. */
5522 choose_reload_regs (struct insn_chain *chain)
5524 rtx insn = chain->insn;
5526 unsigned int max_group_size = 1;
5527 enum reg_class group_class = NO_REGS;
5528 int pass, win, inheritance;
5530 rtx save_reload_reg_rtx[MAX_RELOADS];
5532 /* In order to be certain of getting the registers we need,
5533 we must sort the reloads into order of increasing register class.
5534 Then our grabbing of reload registers will parallel the process
5535 that provided the reload registers.
5537 Also note whether any of the reloads wants a consecutive group of regs.
5538 If so, record the maximum size of the group desired and what
5539 register class contains all the groups needed by this insn. */
5541 for (j = 0; j < n_reloads; j++)
5543 reload_order[j] = j;
5544 reload_spill_index[j] = -1;
5546 if (rld[j].nregs > 1)
5548 max_group_size = MAX (rld[j].nregs, max_group_size);
5550 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5553 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5557 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5559 /* If -O, try first with inheritance, then turning it off.
5560 If not -O, don't do inheritance.
5561 Using inheritance when not optimizing leads to paradoxes
5562 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5563 because one side of the comparison might be inherited. */
5565 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5567 choose_reload_regs_init (chain, save_reload_reg_rtx);
5569 /* Process the reloads in order of preference just found.
5570 Beyond this point, subregs can be found in reload_reg_rtx.
5572 This used to look for an existing reloaded home for all of the
5573 reloads, and only then perform any new reloads. But that could lose
5574 if the reloads were done out of reg-class order because a later
5575 reload with a looser constraint might have an old home in a register
5576 needed by an earlier reload with a tighter constraint.
5578 To solve this, we make two passes over the reloads, in the order
5579 described above. In the first pass we try to inherit a reload
5580 from a previous insn. If there is a later reload that needs a
5581 class that is a proper subset of the class being processed, we must
5582 also allocate a spill register during the first pass.
5584 Then make a second pass over the reloads to allocate any reloads
5585 that haven't been given registers yet. */
5587 for (j = 0; j < n_reloads; j++)
5589 int r = reload_order[j];
5590 rtx search_equiv = NULL_RTX;
5592 /* Ignore reloads that got marked inoperative. */
5593 if (rld[r].out == 0 && rld[r].in == 0
5594 && ! rld[r].secondary_p)
5597 /* If find_reloads chose to use reload_in or reload_out as a reload
5598 register, we don't need to chose one. Otherwise, try even if it
5599 found one since we might save an insn if we find the value lying
5601 Try also when reload_in is a pseudo without a hard reg. */
5602 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5603 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5604 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5605 && !MEM_P (rld[r].in)
5606 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5609 #if 0 /* No longer needed for correct operation.
5610 It might give better code, or might not; worth an experiment? */
5611 /* If this is an optional reload, we can't inherit from earlier insns
5612 until we are sure that any non-optional reloads have been allocated.
5613 The following code takes advantage of the fact that optional reloads
5614 are at the end of reload_order. */
5615 if (rld[r].optional != 0)
5616 for (i = 0; i < j; i++)
5617 if ((rld[reload_order[i]].out != 0
5618 || rld[reload_order[i]].in != 0
5619 || rld[reload_order[i]].secondary_p)
5620 && ! rld[reload_order[i]].optional
5621 && rld[reload_order[i]].reg_rtx == 0)
5622 allocate_reload_reg (chain, reload_order[i], 0);
5625 /* First see if this pseudo is already available as reloaded
5626 for a previous insn. We cannot try to inherit for reloads
5627 that are smaller than the maximum number of registers needed
5628 for groups unless the register we would allocate cannot be used
5631 We could check here to see if this is a secondary reload for
5632 an object that is already in a register of the desired class.
5633 This would avoid the need for the secondary reload register.
5634 But this is complex because we can't easily determine what
5635 objects might want to be loaded via this reload. So let a
5636 register be allocated here. In `emit_reload_insns' we suppress
5637 one of the loads in the case described above. */
5643 enum machine_mode mode = VOIDmode;
5647 else if (REG_P (rld[r].in))
5649 regno = REGNO (rld[r].in);
5650 mode = GET_MODE (rld[r].in);
5652 else if (REG_P (rld[r].in_reg))
5654 regno = REGNO (rld[r].in_reg);
5655 mode = GET_MODE (rld[r].in_reg);
5657 else if (GET_CODE (rld[r].in_reg) == SUBREG
5658 && REG_P (SUBREG_REG (rld[r].in_reg)))
5660 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5661 if (regno < FIRST_PSEUDO_REGISTER)
5662 regno = subreg_regno (rld[r].in_reg);
5664 byte = SUBREG_BYTE (rld[r].in_reg);
5665 mode = GET_MODE (rld[r].in_reg);
5668 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5669 && REG_P (XEXP (rld[r].in_reg, 0)))
5671 regno = REGNO (XEXP (rld[r].in_reg, 0));
5672 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5673 rld[r].out = rld[r].in;
5677 /* This won't work, since REGNO can be a pseudo reg number.
5678 Also, it takes much more hair to keep track of all the things
5679 that can invalidate an inherited reload of part of a pseudoreg. */
5680 else if (GET_CODE (rld[r].in) == SUBREG
5681 && REG_P (SUBREG_REG (rld[r].in)))
5682 regno = subreg_regno (rld[r].in);
5686 && reg_last_reload_reg[regno] != 0
5687 #ifdef CANNOT_CHANGE_MODE_CLASS
5688 /* Verify that the register it's in can be used in
5690 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5691 GET_MODE (reg_last_reload_reg[regno]),
5696 enum reg_class class = rld[r].class, last_class;
5697 rtx last_reg = reg_last_reload_reg[regno];
5698 enum machine_mode need_mode;
5700 i = REGNO (last_reg);
5701 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5702 last_class = REGNO_REG_CLASS (i);
5708 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5709 + byte * BITS_PER_UNIT,
5710 GET_MODE_CLASS (mode));
5712 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5713 >= GET_MODE_SIZE (need_mode))
5714 && reg_reloaded_contents[i] == regno
5715 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5716 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5717 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5718 /* Even if we can't use this register as a reload
5719 register, we might use it for reload_override_in,
5720 if copying it to the desired class is cheap
5722 || ((REGISTER_MOVE_COST (mode, last_class, class)
5723 < MEMORY_MOVE_COST (mode, class, 1))
5724 && (secondary_reload_class (1, class, mode,
5727 #ifdef SECONDARY_MEMORY_NEEDED
5728 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5733 && (rld[r].nregs == max_group_size
5734 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5736 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5737 rld[r].when_needed, rld[r].in,
5740 /* If a group is needed, verify that all the subsequent
5741 registers still have their values intact. */
5742 int nr = hard_regno_nregs[i][rld[r].mode];
5745 for (k = 1; k < nr; k++)
5746 if (reg_reloaded_contents[i + k] != regno
5747 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5755 last_reg = (GET_MODE (last_reg) == mode
5756 ? last_reg : gen_rtx_REG (mode, i));
5759 for (k = 0; k < nr; k++)
5760 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5763 /* We found a register that contains the
5764 value we need. If this register is the
5765 same as an `earlyclobber' operand of the
5766 current insn, just mark it as a place to
5767 reload from since we can't use it as the
5768 reload register itself. */
5770 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5771 if (reg_overlap_mentioned_for_reload_p
5772 (reg_last_reload_reg[regno],
5773 reload_earlyclobbers[i1]))
5776 if (i1 != n_earlyclobbers
5777 || ! (free_for_value_p (i, rld[r].mode,
5779 rld[r].when_needed, rld[r].in,
5781 /* Don't use it if we'd clobber a pseudo reg. */
5782 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5784 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5785 /* Don't clobber the frame pointer. */
5786 || (i == HARD_FRAME_POINTER_REGNUM
5787 && frame_pointer_needed
5789 /* Don't really use the inherited spill reg
5790 if we need it wider than we've got it. */
5791 || (GET_MODE_SIZE (rld[r].mode)
5792 > GET_MODE_SIZE (mode))
5795 /* If find_reloads chose reload_out as reload
5796 register, stay with it - that leaves the
5797 inherited register for subsequent reloads. */
5798 || (rld[r].out && rld[r].reg_rtx
5799 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5801 if (! rld[r].optional)
5803 reload_override_in[r] = last_reg;
5804 reload_inheritance_insn[r]
5805 = reg_reloaded_insn[i];
5811 /* We can use this as a reload reg. */
5812 /* Mark the register as in use for this part of
5814 mark_reload_reg_in_use (i,
5818 rld[r].reg_rtx = last_reg;
5819 reload_inherited[r] = 1;
5820 reload_inheritance_insn[r]
5821 = reg_reloaded_insn[i];
5822 reload_spill_index[r] = i;
5823 for (k = 0; k < nr; k++)
5824 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5832 /* Here's another way to see if the value is already lying around. */
5835 && ! reload_inherited[r]
5837 && (CONSTANT_P (rld[r].in)
5838 || GET_CODE (rld[r].in) == PLUS
5839 || REG_P (rld[r].in)
5840 || MEM_P (rld[r].in))
5841 && (rld[r].nregs == max_group_size
5842 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5843 search_equiv = rld[r].in;
5844 /* If this is an output reload from a simple move insn, look
5845 if an equivalence for the input is available. */
5846 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5848 rtx set = single_set (insn);
5851 && rtx_equal_p (rld[r].out, SET_DEST (set))
5852 && CONSTANT_P (SET_SRC (set)))
5853 search_equiv = SET_SRC (set);
5859 = find_equiv_reg (search_equiv, insn, rld[r].class,
5860 -1, NULL, 0, rld[r].mode);
5866 regno = REGNO (equiv);
5869 /* This must be a SUBREG of a hard register.
5870 Make a new REG since this might be used in an
5871 address and not all machines support SUBREGs
5873 gcc_assert (GET_CODE (equiv) == SUBREG);
5874 regno = subreg_regno (equiv);
5875 equiv = gen_rtx_REG (rld[r].mode, regno);
5876 /* If we choose EQUIV as the reload register, but the
5877 loop below decides to cancel the inheritance, we'll
5878 end up reloading EQUIV in rld[r].mode, not the mode
5879 it had originally. That isn't safe when EQUIV isn't
5880 available as a spill register since its value might
5881 still be live at this point. */
5882 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5883 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5888 /* If we found a spill reg, reject it unless it is free
5889 and of the desired class. */
5893 int bad_for_class = 0;
5894 int max_regno = regno + rld[r].nregs;
5896 for (i = regno; i < max_regno; i++)
5898 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5900 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5905 && ! free_for_value_p (regno, rld[r].mode,
5906 rld[r].opnum, rld[r].when_needed,
5907 rld[r].in, rld[r].out, r, 1))
5912 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5915 /* We found a register that contains the value we need.
5916 If this register is the same as an `earlyclobber' operand
5917 of the current insn, just mark it as a place to reload from
5918 since we can't use it as the reload register itself. */
5921 for (i = 0; i < n_earlyclobbers; i++)
5922 if (reg_overlap_mentioned_for_reload_p (equiv,
5923 reload_earlyclobbers[i]))
5925 if (! rld[r].optional)
5926 reload_override_in[r] = equiv;
5931 /* If the equiv register we have found is explicitly clobbered
5932 in the current insn, it depends on the reload type if we
5933 can use it, use it for reload_override_in, or not at all.
5934 In particular, we then can't use EQUIV for a
5935 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5939 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5940 switch (rld[r].when_needed)
5942 case RELOAD_FOR_OTHER_ADDRESS:
5943 case RELOAD_FOR_INPADDR_ADDRESS:
5944 case RELOAD_FOR_INPUT_ADDRESS:
5945 case RELOAD_FOR_OPADDR_ADDR:
5948 case RELOAD_FOR_INPUT:
5949 case RELOAD_FOR_OPERAND_ADDRESS:
5950 if (! rld[r].optional)
5951 reload_override_in[r] = equiv;
5957 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5958 switch (rld[r].when_needed)
5960 case RELOAD_FOR_OTHER_ADDRESS:
5961 case RELOAD_FOR_INPADDR_ADDRESS:
5962 case RELOAD_FOR_INPUT_ADDRESS:
5963 case RELOAD_FOR_OPADDR_ADDR:
5964 case RELOAD_FOR_OPERAND_ADDRESS:
5965 case RELOAD_FOR_INPUT:
5968 if (! rld[r].optional)
5969 reload_override_in[r] = equiv;
5977 /* If we found an equivalent reg, say no code need be generated
5978 to load it, and use it as our reload reg. */
5980 && (regno != HARD_FRAME_POINTER_REGNUM
5981 || !frame_pointer_needed))
5983 int nr = hard_regno_nregs[regno][rld[r].mode];
5985 rld[r].reg_rtx = equiv;
5986 reload_inherited[r] = 1;
5988 /* If reg_reloaded_valid is not set for this register,
5989 there might be a stale spill_reg_store lying around.
5990 We must clear it, since otherwise emit_reload_insns
5991 might delete the store. */
5992 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5993 spill_reg_store[regno] = NULL_RTX;
5994 /* If any of the hard registers in EQUIV are spill
5995 registers, mark them as in use for this insn. */
5996 for (k = 0; k < nr; k++)
5998 i = spill_reg_order[regno + k];
6001 mark_reload_reg_in_use (regno, rld[r].opnum,
6004 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6011 /* If we found a register to use already, or if this is an optional
6012 reload, we are done. */
6013 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6017 /* No longer needed for correct operation. Might or might
6018 not give better code on the average. Want to experiment? */
6020 /* See if there is a later reload that has a class different from our
6021 class that intersects our class or that requires less register
6022 than our reload. If so, we must allocate a register to this
6023 reload now, since that reload might inherit a previous reload
6024 and take the only available register in our class. Don't do this
6025 for optional reloads since they will force all previous reloads
6026 to be allocated. Also don't do this for reloads that have been
6029 for (i = j + 1; i < n_reloads; i++)
6031 int s = reload_order[i];
6033 if ((rld[s].in == 0 && rld[s].out == 0
6034 && ! rld[s].secondary_p)
6038 if ((rld[s].class != rld[r].class
6039 && reg_classes_intersect_p (rld[r].class,
6041 || rld[s].nregs < rld[r].nregs)
6048 allocate_reload_reg (chain, r, j == n_reloads - 1);
6052 /* Now allocate reload registers for anything non-optional that
6053 didn't get one yet. */
6054 for (j = 0; j < n_reloads; j++)
6056 int r = reload_order[j];
6058 /* Ignore reloads that got marked inoperative. */
6059 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6062 /* Skip reloads that already have a register allocated or are
6064 if (rld[r].reg_rtx != 0 || rld[r].optional)
6067 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6071 /* If that loop got all the way, we have won. */
6078 /* Loop around and try without any inheritance. */
6083 /* First undo everything done by the failed attempt
6084 to allocate with inheritance. */
6085 choose_reload_regs_init (chain, save_reload_reg_rtx);
6087 /* Some sanity tests to verify that the reloads found in the first
6088 pass are identical to the ones we have now. */
6089 gcc_assert (chain->n_reloads == n_reloads);
6091 for (i = 0; i < n_reloads; i++)
6093 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6095 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6096 for (j = 0; j < n_spills; j++)
6097 if (spill_regs[j] == chain->rld[i].regno)
6098 if (! set_reload_reg (j, i))
6099 failed_reload (chain->insn, i);
6103 /* If we thought we could inherit a reload, because it seemed that
6104 nothing else wanted the same reload register earlier in the insn,
6105 verify that assumption, now that all reloads have been assigned.
6106 Likewise for reloads where reload_override_in has been set. */
6108 /* If doing expensive optimizations, do one preliminary pass that doesn't
6109 cancel any inheritance, but removes reloads that have been needed only
6110 for reloads that we know can be inherited. */
6111 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6113 for (j = 0; j < n_reloads; j++)
6115 int r = reload_order[j];
6117 if (reload_inherited[r] && rld[r].reg_rtx)
6118 check_reg = rld[r].reg_rtx;
6119 else if (reload_override_in[r]
6120 && (REG_P (reload_override_in[r])
6121 || GET_CODE (reload_override_in[r]) == SUBREG))
6122 check_reg = reload_override_in[r];
6125 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6126 rld[r].opnum, rld[r].when_needed, rld[r].in,
6127 (reload_inherited[r]
6128 ? rld[r].out : const0_rtx),
6133 reload_inherited[r] = 0;
6134 reload_override_in[r] = 0;
6136 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6137 reload_override_in, then we do not need its related
6138 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6139 likewise for other reload types.
6140 We handle this by removing a reload when its only replacement
6141 is mentioned in reload_in of the reload we are going to inherit.
6142 A special case are auto_inc expressions; even if the input is
6143 inherited, we still need the address for the output. We can
6144 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6145 If we succeeded removing some reload and we are doing a preliminary
6146 pass just to remove such reloads, make another pass, since the
6147 removal of one reload might allow us to inherit another one. */
6149 && rld[r].out != rld[r].in
6150 && remove_address_replacements (rld[r].in) && pass)
6155 /* Now that reload_override_in is known valid,
6156 actually override reload_in. */
6157 for (j = 0; j < n_reloads; j++)
6158 if (reload_override_in[j])
6159 rld[j].in = reload_override_in[j];
6161 /* If this reload won't be done because it has been canceled or is
6162 optional and not inherited, clear reload_reg_rtx so other
6163 routines (such as subst_reloads) don't get confused. */
6164 for (j = 0; j < n_reloads; j++)
6165 if (rld[j].reg_rtx != 0
6166 && ((rld[j].optional && ! reload_inherited[j])
6167 || (rld[j].in == 0 && rld[j].out == 0
6168 && ! rld[j].secondary_p)))
6170 int regno = true_regnum (rld[j].reg_rtx);
6172 if (spill_reg_order[regno] >= 0)
6173 clear_reload_reg_in_use (regno, rld[j].opnum,
6174 rld[j].when_needed, rld[j].mode);
6176 reload_spill_index[j] = -1;
6179 /* Record which pseudos and which spill regs have output reloads. */
6180 for (j = 0; j < n_reloads; j++)
6182 int r = reload_order[j];
6184 i = reload_spill_index[r];
6186 /* I is nonneg if this reload uses a register.
6187 If rld[r].reg_rtx is 0, this is an optional reload
6188 that we opted to ignore. */
6189 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6190 && rld[r].reg_rtx != 0)
6192 int nregno = REGNO (rld[r].out_reg);
6195 if (nregno < FIRST_PSEUDO_REGISTER)
6196 nr = hard_regno_nregs[nregno][rld[r].mode];
6199 SET_REGNO_REG_SET (®_has_output_reload,
6204 nr = hard_regno_nregs[i][rld[r].mode];
6206 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6209 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6210 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6211 || rld[r].when_needed == RELOAD_FOR_INSN);
6216 /* Deallocate the reload register for reload R. This is called from
6217 remove_address_replacements. */
6220 deallocate_reload_reg (int r)
6224 if (! rld[r].reg_rtx)
6226 regno = true_regnum (rld[r].reg_rtx);
6228 if (spill_reg_order[regno] >= 0)
6229 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6231 reload_spill_index[r] = -1;
6234 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6235 reloads of the same item for fear that we might not have enough reload
6236 registers. However, normally they will get the same reload register
6237 and hence actually need not be loaded twice.
6239 Here we check for the most common case of this phenomenon: when we have
6240 a number of reloads for the same object, each of which were allocated
6241 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6242 reload, and is not modified in the insn itself. If we find such,
6243 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6244 This will not increase the number of spill registers needed and will
6245 prevent redundant code. */
6248 merge_assigned_reloads (rtx insn)
6252 /* Scan all the reloads looking for ones that only load values and
6253 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6254 assigned and not modified by INSN. */
6256 for (i = 0; i < n_reloads; i++)
6258 int conflicting_input = 0;
6259 int max_input_address_opnum = -1;
6260 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6262 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6263 || rld[i].out != 0 || rld[i].reg_rtx == 0
6264 || reg_set_p (rld[i].reg_rtx, insn))
6267 /* Look at all other reloads. Ensure that the only use of this
6268 reload_reg_rtx is in a reload that just loads the same value
6269 as we do. Note that any secondary reloads must be of the identical
6270 class since the values, modes, and result registers are the
6271 same, so we need not do anything with any secondary reloads. */
6273 for (j = 0; j < n_reloads; j++)
6275 if (i == j || rld[j].reg_rtx == 0
6276 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6280 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6281 && rld[j].opnum > max_input_address_opnum)
6282 max_input_address_opnum = rld[j].opnum;
6284 /* If the reload regs aren't exactly the same (e.g, different modes)
6285 or if the values are different, we can't merge this reload.
6286 But if it is an input reload, we might still merge
6287 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6289 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6290 || rld[j].out != 0 || rld[j].in == 0
6291 || ! rtx_equal_p (rld[i].in, rld[j].in))
6293 if (rld[j].when_needed != RELOAD_FOR_INPUT
6294 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6295 || rld[i].opnum > rld[j].opnum)
6296 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6298 conflicting_input = 1;
6299 if (min_conflicting_input_opnum > rld[j].opnum)
6300 min_conflicting_input_opnum = rld[j].opnum;
6304 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6305 we, in fact, found any matching reloads. */
6308 && max_input_address_opnum <= min_conflicting_input_opnum)
6310 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6312 for (j = 0; j < n_reloads; j++)
6313 if (i != j && rld[j].reg_rtx != 0
6314 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6315 && (! conflicting_input
6316 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6317 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6319 rld[i].when_needed = RELOAD_OTHER;
6321 reload_spill_index[j] = -1;
6322 transfer_replacements (i, j);
6325 /* If this is now RELOAD_OTHER, look for any reloads that load
6326 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6327 if they were for inputs, RELOAD_OTHER for outputs. Note that
6328 this test is equivalent to looking for reloads for this operand
6330 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6331 share registers with a RELOAD_FOR_INPUT, so we can not change it
6332 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6333 do not modify RELOAD_FOR_OUTPUT. */
6335 if (rld[i].when_needed == RELOAD_OTHER)
6336 for (j = 0; j < n_reloads; j++)
6338 && rld[j].when_needed != RELOAD_OTHER
6339 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6340 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6341 && (! conflicting_input
6342 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6343 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6344 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6350 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6351 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6352 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6354 /* Check to see if we accidentally converted two
6355 reloads that use the same reload register with
6356 different inputs to the same type. If so, the
6357 resulting code won't work. */
6359 for (k = 0; k < j; k++)
6360 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6361 || rld[k].when_needed != rld[j].when_needed
6362 || !rtx_equal_p (rld[k].reg_rtx,
6364 || rtx_equal_p (rld[k].in,
6371 /* These arrays are filled by emit_reload_insns and its subroutines. */
6372 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6373 static rtx other_input_address_reload_insns = 0;
6374 static rtx other_input_reload_insns = 0;
6375 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6376 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6377 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6378 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6379 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6380 static rtx operand_reload_insns = 0;
6381 static rtx other_operand_reload_insns = 0;
6382 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6384 /* Values to be put in spill_reg_store are put here first. */
6385 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6386 static HARD_REG_SET reg_reloaded_died;
6388 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6389 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6390 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6391 adjusted register, and return true. Otherwise, return false. */
6393 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6394 enum reg_class new_class,
6395 enum machine_mode new_mode)
6400 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6402 unsigned regno = REGNO (reg);
6404 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6406 if (GET_MODE (reg) != new_mode)
6408 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6410 if (hard_regno_nregs[regno][new_mode]
6411 > hard_regno_nregs[regno][GET_MODE (reg)])
6413 reg = reload_adjust_reg_for_mode (reg, new_mode);
6421 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6422 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6423 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6424 adjusted register, and return true. Otherwise, return false. */
6426 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6427 enum insn_code icode)
6430 enum reg_class new_class = scratch_reload_class (icode);
6431 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6433 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6434 new_class, new_mode);
6437 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6438 has the number J. OLD contains the value to be used as input. */
6441 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6444 rtx insn = chain->insn;
6445 rtx reloadreg = rl->reg_rtx;
6446 rtx oldequiv_reg = 0;
6449 enum machine_mode mode;
6452 /* Determine the mode to reload in.
6453 This is very tricky because we have three to choose from.
6454 There is the mode the insn operand wants (rl->inmode).
6455 There is the mode of the reload register RELOADREG.
6456 There is the intrinsic mode of the operand, which we could find
6457 by stripping some SUBREGs.
6458 It turns out that RELOADREG's mode is irrelevant:
6459 we can change that arbitrarily.
6461 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6462 then the reload reg may not support QImode moves, so use SImode.
6463 If foo is in memory due to spilling a pseudo reg, this is safe,
6464 because the QImode value is in the least significant part of a
6465 slot big enough for a SImode. If foo is some other sort of
6466 memory reference, then it is impossible to reload this case,
6467 so previous passes had better make sure this never happens.
6469 Then consider a one-word union which has SImode and one of its
6470 members is a float, being fetched as (SUBREG:SF union:SI).
6471 We must fetch that as SFmode because we could be loading into
6472 a float-only register. In this case OLD's mode is correct.
6474 Consider an immediate integer: it has VOIDmode. Here we need
6475 to get a mode from something else.
6477 In some cases, there is a fourth mode, the operand's
6478 containing mode. If the insn specifies a containing mode for
6479 this operand, it overrides all others.
6481 I am not sure whether the algorithm here is always right,
6482 but it does the right things in those cases. */
6484 mode = GET_MODE (old);
6485 if (mode == VOIDmode)
6488 /* delete_output_reload is only invoked properly if old contains
6489 the original pseudo register. Since this is replaced with a
6490 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6491 find the pseudo in RELOAD_IN_REG. */
6492 if (reload_override_in[j]
6493 && REG_P (rl->in_reg))
6500 else if (REG_P (oldequiv))
6501 oldequiv_reg = oldequiv;
6502 else if (GET_CODE (oldequiv) == SUBREG)
6503 oldequiv_reg = SUBREG_REG (oldequiv);
6505 /* If we are reloading from a register that was recently stored in
6506 with an output-reload, see if we can prove there was
6507 actually no need to store the old value in it. */
6509 if (optimize && REG_P (oldequiv)
6510 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6511 && spill_reg_store[REGNO (oldequiv)]
6513 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6514 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6516 delete_output_reload (insn, j, REGNO (oldequiv));
6518 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6519 then load RELOADREG from OLDEQUIV. Note that we cannot use
6520 gen_lowpart_common since it can do the wrong thing when
6521 RELOADREG has a multi-word mode. Note that RELOADREG
6522 must always be a REG here. */
6524 if (GET_MODE (reloadreg) != mode)
6525 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6526 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6527 oldequiv = SUBREG_REG (oldequiv);
6528 if (GET_MODE (oldequiv) != VOIDmode
6529 && mode != GET_MODE (oldequiv))
6530 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6532 /* Switch to the right place to emit the reload insns. */
6533 switch (rl->when_needed)
6536 where = &other_input_reload_insns;
6538 case RELOAD_FOR_INPUT:
6539 where = &input_reload_insns[rl->opnum];
6541 case RELOAD_FOR_INPUT_ADDRESS:
6542 where = &input_address_reload_insns[rl->opnum];
6544 case RELOAD_FOR_INPADDR_ADDRESS:
6545 where = &inpaddr_address_reload_insns[rl->opnum];
6547 case RELOAD_FOR_OUTPUT_ADDRESS:
6548 where = &output_address_reload_insns[rl->opnum];
6550 case RELOAD_FOR_OUTADDR_ADDRESS:
6551 where = &outaddr_address_reload_insns[rl->opnum];
6553 case RELOAD_FOR_OPERAND_ADDRESS:
6554 where = &operand_reload_insns;
6556 case RELOAD_FOR_OPADDR_ADDR:
6557 where = &other_operand_reload_insns;
6559 case RELOAD_FOR_OTHER_ADDRESS:
6560 where = &other_input_address_reload_insns;
6566 push_to_sequence (*where);
6568 /* Auto-increment addresses must be reloaded in a special way. */
6569 if (rl->out && ! rl->out_reg)
6571 /* We are not going to bother supporting the case where a
6572 incremented register can't be copied directly from
6573 OLDEQUIV since this seems highly unlikely. */
6574 gcc_assert (rl->secondary_in_reload < 0);
6576 if (reload_inherited[j])
6577 oldequiv = reloadreg;
6579 old = XEXP (rl->in_reg, 0);
6581 if (optimize && REG_P (oldequiv)
6582 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6583 && spill_reg_store[REGNO (oldequiv)]
6585 && (dead_or_set_p (insn,
6586 spill_reg_stored_to[REGNO (oldequiv)])
6587 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6589 delete_output_reload (insn, j, REGNO (oldequiv));
6591 /* Prevent normal processing of this reload. */
6593 /* Output a special code sequence for this case. */
6594 new_spill_reg_store[REGNO (reloadreg)]
6595 = inc_for_reload (reloadreg, oldequiv, rl->out,
6599 /* If we are reloading a pseudo-register that was set by the previous
6600 insn, see if we can get rid of that pseudo-register entirely
6601 by redirecting the previous insn into our reload register. */
6603 else if (optimize && REG_P (old)
6604 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6605 && dead_or_set_p (insn, old)
6606 /* This is unsafe if some other reload
6607 uses the same reg first. */
6608 && ! conflicts_with_override (reloadreg)
6609 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6610 rl->when_needed, old, rl->out, j, 0))
6612 rtx temp = PREV_INSN (insn);
6613 while (temp && NOTE_P (temp))
6614 temp = PREV_INSN (temp);
6616 && NONJUMP_INSN_P (temp)
6617 && GET_CODE (PATTERN (temp)) == SET
6618 && SET_DEST (PATTERN (temp)) == old
6619 /* Make sure we can access insn_operand_constraint. */
6620 && asm_noperands (PATTERN (temp)) < 0
6621 /* This is unsafe if operand occurs more than once in current
6622 insn. Perhaps some occurrences aren't reloaded. */
6623 && count_occurrences (PATTERN (insn), old, 0) == 1)
6625 rtx old = SET_DEST (PATTERN (temp));
6626 /* Store into the reload register instead of the pseudo. */
6627 SET_DEST (PATTERN (temp)) = reloadreg;
6629 /* Verify that resulting insn is valid. */
6630 extract_insn (temp);
6631 if (constrain_operands (1))
6633 /* If the previous insn is an output reload, the source is
6634 a reload register, and its spill_reg_store entry will
6635 contain the previous destination. This is now
6637 if (REG_P (SET_SRC (PATTERN (temp)))
6638 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6640 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6641 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6644 /* If these are the only uses of the pseudo reg,
6645 pretend for GDB it lives in the reload reg we used. */
6646 if (REG_N_DEATHS (REGNO (old)) == 1
6647 && REG_N_SETS (REGNO (old)) == 1)
6649 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6650 alter_reg (REGNO (old), -1);
6656 SET_DEST (PATTERN (temp)) = old;
6661 /* We can't do that, so output an insn to load RELOADREG. */
6663 /* If we have a secondary reload, pick up the secondary register
6664 and icode, if any. If OLDEQUIV and OLD are different or
6665 if this is an in-out reload, recompute whether or not we
6666 still need a secondary register and what the icode should
6667 be. If we still need a secondary register and the class or
6668 icode is different, go back to reloading from OLD if using
6669 OLDEQUIV means that we got the wrong type of register. We
6670 cannot have different class or icode due to an in-out reload
6671 because we don't make such reloads when both the input and
6672 output need secondary reload registers. */
6674 if (! special && rl->secondary_in_reload >= 0)
6676 rtx second_reload_reg = 0;
6677 rtx third_reload_reg = 0;
6678 int secondary_reload = rl->secondary_in_reload;
6679 rtx real_oldequiv = oldequiv;
6682 enum insn_code icode;
6683 enum insn_code tertiary_icode = CODE_FOR_nothing;
6685 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6686 and similarly for OLD.
6687 See comments in get_secondary_reload in reload.c. */
6688 /* If it is a pseudo that cannot be replaced with its
6689 equivalent MEM, we must fall back to reload_in, which
6690 will have all the necessary substitutions registered.
6691 Likewise for a pseudo that can't be replaced with its
6692 equivalent constant.
6694 Take extra care for subregs of such pseudos. Note that
6695 we cannot use reg_equiv_mem in this case because it is
6696 not in the right mode. */
6699 if (GET_CODE (tmp) == SUBREG)
6700 tmp = SUBREG_REG (tmp);
6702 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6703 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6704 || reg_equiv_constant[REGNO (tmp)] != 0))
6706 if (! reg_equiv_mem[REGNO (tmp)]
6707 || num_not_at_initial_offset
6708 || GET_CODE (oldequiv) == SUBREG)
6709 real_oldequiv = rl->in;
6711 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6715 if (GET_CODE (tmp) == SUBREG)
6716 tmp = SUBREG_REG (tmp);
6718 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6719 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6720 || reg_equiv_constant[REGNO (tmp)] != 0))
6722 if (! reg_equiv_mem[REGNO (tmp)]
6723 || num_not_at_initial_offset
6724 || GET_CODE (old) == SUBREG)
6727 real_old = reg_equiv_mem[REGNO (tmp)];
6730 second_reload_reg = rld[secondary_reload].reg_rtx;
6731 if (rld[secondary_reload].secondary_in_reload >= 0)
6733 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6735 third_reload_reg = rld[tertiary_reload].reg_rtx;
6736 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6737 /* We'd have to add more code for quartary reloads. */
6738 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6740 icode = rl->secondary_in_icode;
6742 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6743 || (rl->in != 0 && rl->out != 0))
6745 secondary_reload_info sri, sri2;
6746 enum reg_class new_class, new_t_class;
6748 sri.icode = CODE_FOR_nothing;
6749 sri.prev_sri = NULL;
6750 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6753 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6754 second_reload_reg = 0;
6755 else if (new_class == NO_REGS)
6757 if (reload_adjust_reg_for_icode (&second_reload_reg,
6758 third_reload_reg, sri.icode))
6759 icode = sri.icode, third_reload_reg = 0;
6761 oldequiv = old, real_oldequiv = real_old;
6763 else if (sri.icode != CODE_FOR_nothing)
6764 /* We currently lack a way to express this in reloads. */
6768 sri2.icode = CODE_FOR_nothing;
6769 sri2.prev_sri = &sri;
6770 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6771 new_class, mode, &sri);
6772 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6774 if (reload_adjust_reg_for_temp (&second_reload_reg,
6777 third_reload_reg = 0, tertiary_icode = sri2.icode;
6779 oldequiv = old, real_oldequiv = real_old;
6781 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6783 rtx intermediate = second_reload_reg;
6785 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6787 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6790 second_reload_reg = intermediate;
6791 tertiary_icode = sri2.icode;
6794 oldequiv = old, real_oldequiv = real_old;
6796 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6798 rtx intermediate = second_reload_reg;
6800 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6802 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6805 second_reload_reg = intermediate;
6806 tertiary_icode = sri2.icode;
6809 oldequiv = old, real_oldequiv = real_old;
6812 /* This could be handled more intelligently too. */
6813 oldequiv = old, real_oldequiv = real_old;
6817 /* If we still need a secondary reload register, check
6818 to see if it is being used as a scratch or intermediate
6819 register and generate code appropriately. If we need
6820 a scratch register, use REAL_OLDEQUIV since the form of
6821 the insn may depend on the actual address if it is
6824 if (second_reload_reg)
6826 if (icode != CODE_FOR_nothing)
6828 /* We'd have to add extra code to handle this case. */
6829 gcc_assert (!third_reload_reg);
6831 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6832 second_reload_reg));
6837 /* See if we need a scratch register to load the
6838 intermediate register (a tertiary reload). */
6839 if (tertiary_icode != CODE_FOR_nothing)
6841 emit_insn ((GEN_FCN (tertiary_icode)
6842 (second_reload_reg, real_oldequiv,
6843 third_reload_reg)));
6845 else if (third_reload_reg)
6847 gen_reload (third_reload_reg, real_oldequiv,
6850 gen_reload (second_reload_reg, third_reload_reg,
6855 gen_reload (second_reload_reg, real_oldequiv,
6859 oldequiv = second_reload_reg;
6864 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6866 rtx real_oldequiv = oldequiv;
6868 if ((REG_P (oldequiv)
6869 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6870 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6871 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6872 || (GET_CODE (oldequiv) == SUBREG
6873 && REG_P (SUBREG_REG (oldequiv))
6874 && (REGNO (SUBREG_REG (oldequiv))
6875 >= FIRST_PSEUDO_REGISTER)
6876 && ((reg_equiv_memory_loc
6877 [REGNO (SUBREG_REG (oldequiv))] != 0)
6878 || (reg_equiv_constant
6879 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6880 || (CONSTANT_P (oldequiv)
6881 && (PREFERRED_RELOAD_CLASS (oldequiv,
6882 REGNO_REG_CLASS (REGNO (reloadreg)))
6884 real_oldequiv = rl->in;
6885 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6889 if (flag_non_call_exceptions)
6890 copy_eh_notes (insn, get_insns ());
6892 /* End this sequence. */
6893 *where = get_insns ();
6896 /* Update reload_override_in so that delete_address_reloads_1
6897 can see the actual register usage. */
6899 reload_override_in[j] = oldequiv;
6902 /* Generate insns to for the output reload RL, which is for the insn described
6903 by CHAIN and has the number J. */
6905 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6908 rtx reloadreg = rl->reg_rtx;
6909 rtx insn = chain->insn;
6912 enum machine_mode mode = GET_MODE (old);
6915 if (rl->when_needed == RELOAD_OTHER)
6918 push_to_sequence (output_reload_insns[rl->opnum]);
6920 /* Determine the mode to reload in.
6921 See comments above (for input reloading). */
6923 if (mode == VOIDmode)
6925 /* VOIDmode should never happen for an output. */
6926 if (asm_noperands (PATTERN (insn)) < 0)
6927 /* It's the compiler's fault. */
6928 fatal_insn ("VOIDmode on an output", insn);
6929 error_for_asm (insn, "output operand is constant in %<asm%>");
6930 /* Prevent crash--use something we know is valid. */
6932 old = gen_rtx_REG (mode, REGNO (reloadreg));
6935 if (GET_MODE (reloadreg) != mode)
6936 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6938 /* If we need two reload regs, set RELOADREG to the intermediate
6939 one, since it will be stored into OLD. We might need a secondary
6940 register only for an input reload, so check again here. */
6942 if (rl->secondary_out_reload >= 0)
6945 int secondary_reload = rl->secondary_out_reload;
6946 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6948 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6949 && reg_equiv_mem[REGNO (old)] != 0)
6950 real_old = reg_equiv_mem[REGNO (old)];
6952 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6954 rtx second_reloadreg = reloadreg;
6955 reloadreg = rld[secondary_reload].reg_rtx;
6957 /* See if RELOADREG is to be used as a scratch register
6958 or as an intermediate register. */
6959 if (rl->secondary_out_icode != CODE_FOR_nothing)
6961 /* We'd have to add extra code to handle this case. */
6962 gcc_assert (tertiary_reload < 0);
6964 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6965 (real_old, second_reloadreg, reloadreg)));
6970 /* See if we need both a scratch and intermediate reload
6973 enum insn_code tertiary_icode
6974 = rld[secondary_reload].secondary_out_icode;
6976 /* We'd have to add more code for quartary reloads. */
6977 gcc_assert (tertiary_reload < 0
6978 || rld[tertiary_reload].secondary_out_reload < 0);
6980 if (GET_MODE (reloadreg) != mode)
6981 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6983 if (tertiary_icode != CODE_FOR_nothing)
6985 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6988 /* Copy primary reload reg to secondary reload reg.
6989 (Note that these have been swapped above, then
6990 secondary reload reg to OLD using our insn.) */
6992 /* If REAL_OLD is a paradoxical SUBREG, remove it
6993 and try to put the opposite SUBREG on
6995 if (GET_CODE (real_old) == SUBREG
6996 && (GET_MODE_SIZE (GET_MODE (real_old))
6997 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6998 && 0 != (tem = gen_lowpart_common
6999 (GET_MODE (SUBREG_REG (real_old)),
7001 real_old = SUBREG_REG (real_old), reloadreg = tem;
7003 gen_reload (reloadreg, second_reloadreg,
7004 rl->opnum, rl->when_needed);
7005 emit_insn ((GEN_FCN (tertiary_icode)
7006 (real_old, reloadreg, third_reloadreg)));
7012 /* Copy between the reload regs here and then to
7015 gen_reload (reloadreg, second_reloadreg,
7016 rl->opnum, rl->when_needed);
7017 if (tertiary_reload >= 0)
7019 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7021 gen_reload (third_reloadreg, reloadreg,
7022 rl->opnum, rl->when_needed);
7023 reloadreg = third_reloadreg;
7030 /* Output the last reload insn. */
7035 /* Don't output the last reload if OLD is not the dest of
7036 INSN and is in the src and is clobbered by INSN. */
7037 if (! flag_expensive_optimizations
7039 || !(set = single_set (insn))
7040 || rtx_equal_p (old, SET_DEST (set))
7041 || !reg_mentioned_p (old, SET_SRC (set))
7042 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7043 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7044 gen_reload (old, reloadreg, rl->opnum,
7048 /* Look at all insns we emitted, just to be safe. */
7049 for (p = get_insns (); p; p = NEXT_INSN (p))
7052 rtx pat = PATTERN (p);
7054 /* If this output reload doesn't come from a spill reg,
7055 clear any memory of reloaded copies of the pseudo reg.
7056 If this output reload comes from a spill reg,
7057 reg_has_output_reload will make this do nothing. */
7058 note_stores (pat, forget_old_reloads_1, NULL);
7060 if (reg_mentioned_p (rl->reg_rtx, pat))
7062 rtx set = single_set (insn);
7063 if (reload_spill_index[j] < 0
7065 && SET_SRC (set) == rl->reg_rtx)
7067 int src = REGNO (SET_SRC (set));
7069 reload_spill_index[j] = src;
7070 SET_HARD_REG_BIT (reg_is_output_reload, src);
7071 if (find_regno_note (insn, REG_DEAD, src))
7072 SET_HARD_REG_BIT (reg_reloaded_died, src);
7074 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7076 int s = rl->secondary_out_reload;
7077 set = single_set (p);
7078 /* If this reload copies only to the secondary reload
7079 register, the secondary reload does the actual
7081 if (s >= 0 && set == NULL_RTX)
7082 /* We can't tell what function the secondary reload
7083 has and where the actual store to the pseudo is
7084 made; leave new_spill_reg_store alone. */
7087 && SET_SRC (set) == rl->reg_rtx
7088 && SET_DEST (set) == rld[s].reg_rtx)
7090 /* Usually the next instruction will be the
7091 secondary reload insn; if we can confirm
7092 that it is, setting new_spill_reg_store to
7093 that insn will allow an extra optimization. */
7094 rtx s_reg = rld[s].reg_rtx;
7095 rtx next = NEXT_INSN (p);
7096 rld[s].out = rl->out;
7097 rld[s].out_reg = rl->out_reg;
7098 set = single_set (next);
7099 if (set && SET_SRC (set) == s_reg
7100 && ! new_spill_reg_store[REGNO (s_reg)])
7102 SET_HARD_REG_BIT (reg_is_output_reload,
7104 new_spill_reg_store[REGNO (s_reg)] = next;
7108 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7113 if (rl->when_needed == RELOAD_OTHER)
7115 emit_insn (other_output_reload_insns[rl->opnum]);
7116 other_output_reload_insns[rl->opnum] = get_insns ();
7119 output_reload_insns[rl->opnum] = get_insns ();
7121 if (flag_non_call_exceptions)
7122 copy_eh_notes (insn, get_insns ());
7127 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7128 and has the number J. */
7130 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7132 rtx insn = chain->insn;
7133 rtx old = (rl->in && MEM_P (rl->in)
7134 ? rl->in_reg : rl->in);
7137 /* AUTO_INC reloads need to be handled even if inherited. We got an
7138 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7139 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7140 && ! rtx_equal_p (rl->reg_rtx, old)
7141 && rl->reg_rtx != 0)
7142 emit_input_reload_insns (chain, rld + j, old, j);
7144 /* When inheriting a wider reload, we have a MEM in rl->in,
7145 e.g. inheriting a SImode output reload for
7146 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7147 if (optimize && reload_inherited[j] && rl->in
7149 && MEM_P (rl->in_reg)
7150 && reload_spill_index[j] >= 0
7151 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7152 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7154 /* If we are reloading a register that was recently stored in with an
7155 output-reload, see if we can prove there was
7156 actually no need to store the old value in it. */
7159 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7160 that there may be multiple uses of the previous output reload.
7161 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7162 && rl->when_needed == RELOAD_FOR_INPUT
7163 && (reload_inherited[j] || reload_override_in[j])
7165 && REG_P (rl->reg_rtx)
7166 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7168 /* There doesn't seem to be any reason to restrict this to pseudos
7169 and doing so loses in the case where we are copying from a
7170 register of the wrong class. */
7171 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7172 >= FIRST_PSEUDO_REGISTER)
7174 /* The insn might have already some references to stackslots
7175 replaced by MEMs, while reload_out_reg still names the
7177 && (dead_or_set_p (insn,
7178 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7179 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7181 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7184 /* Do output reloading for reload RL, which is for the insn described by
7185 CHAIN and has the number J.
7186 ??? At some point we need to support handling output reloads of
7187 JUMP_INSNs or insns that set cc0. */
7189 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7192 rtx insn = chain->insn;
7193 /* If this is an output reload that stores something that is
7194 not loaded in this same reload, see if we can eliminate a previous
7196 rtx pseudo = rl->out_reg;
7201 && ! rtx_equal_p (rl->in_reg, pseudo)
7202 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7203 && reg_last_reload_reg[REGNO (pseudo)])
7205 int pseudo_no = REGNO (pseudo);
7206 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7208 /* We don't need to test full validity of last_regno for
7209 inherit here; we only want to know if the store actually
7210 matches the pseudo. */
7211 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7212 && reg_reloaded_contents[last_regno] == pseudo_no
7213 && spill_reg_store[last_regno]
7214 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7215 delete_output_reload (insn, j, last_regno);
7220 || rl->reg_rtx == old
7221 || rl->reg_rtx == 0)
7224 /* An output operand that dies right away does need a reload,
7225 but need not be copied from it. Show the new location in the
7227 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7228 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7230 XEXP (note, 0) = rl->reg_rtx;
7233 /* Likewise for a SUBREG of an operand that dies. */
7234 else if (GET_CODE (old) == SUBREG
7235 && REG_P (SUBREG_REG (old))
7236 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7239 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7243 else if (GET_CODE (old) == SCRATCH)
7244 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7245 but we don't want to make an output reload. */
7248 /* If is a JUMP_INSN, we can't support output reloads yet. */
7249 gcc_assert (NONJUMP_INSN_P (insn));
7251 emit_output_reload_insns (chain, rld + j, j);
7254 /* Reload number R reloads from or to a group of hard registers starting at
7255 register REGNO. Return true if it can be treated for inheritance purposes
7256 like a group of reloads, each one reloading a single hard register.
7257 The caller has already checked that the spill register and REGNO use
7258 the same number of registers to store the reload value. */
7261 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7263 #ifdef CANNOT_CHANGE_MODE_CLASS
7264 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7265 GET_MODE (rld[r].reg_rtx),
7266 reg_raw_mode[reload_spill_index[r]])
7267 && !REG_CANNOT_CHANGE_MODE_P (regno,
7268 GET_MODE (rld[r].reg_rtx),
7269 reg_raw_mode[regno]));
7275 /* Output insns to reload values in and out of the chosen reload regs. */
7278 emit_reload_insns (struct insn_chain *chain)
7280 rtx insn = chain->insn;
7284 CLEAR_HARD_REG_SET (reg_reloaded_died);
7286 for (j = 0; j < reload_n_operands; j++)
7287 input_reload_insns[j] = input_address_reload_insns[j]
7288 = inpaddr_address_reload_insns[j]
7289 = output_reload_insns[j] = output_address_reload_insns[j]
7290 = outaddr_address_reload_insns[j]
7291 = other_output_reload_insns[j] = 0;
7292 other_input_address_reload_insns = 0;
7293 other_input_reload_insns = 0;
7294 operand_reload_insns = 0;
7295 other_operand_reload_insns = 0;
7297 /* Dump reloads into the dump file. */
7300 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7301 debug_reload_to_stream (dump_file);
7304 /* Now output the instructions to copy the data into and out of the
7305 reload registers. Do these in the order that the reloads were reported,
7306 since reloads of base and index registers precede reloads of operands
7307 and the operands may need the base and index registers reloaded. */
7309 for (j = 0; j < n_reloads; j++)
7312 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7313 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7315 do_input_reload (chain, rld + j, j);
7316 do_output_reload (chain, rld + j, j);
7319 /* Now write all the insns we made for reloads in the order expected by
7320 the allocation functions. Prior to the insn being reloaded, we write
7321 the following reloads:
7323 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7325 RELOAD_OTHER reloads.
7327 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7328 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7329 RELOAD_FOR_INPUT reload for the operand.
7331 RELOAD_FOR_OPADDR_ADDRS reloads.
7333 RELOAD_FOR_OPERAND_ADDRESS reloads.
7335 After the insn being reloaded, we write the following:
7337 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7338 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7339 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7340 reloads for the operand. The RELOAD_OTHER output reloads are
7341 output in descending order by reload number. */
7343 emit_insn_before (other_input_address_reload_insns, insn);
7344 emit_insn_before (other_input_reload_insns, insn);
7346 for (j = 0; j < reload_n_operands; j++)
7348 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7349 emit_insn_before (input_address_reload_insns[j], insn);
7350 emit_insn_before (input_reload_insns[j], insn);
7353 emit_insn_before (other_operand_reload_insns, insn);
7354 emit_insn_before (operand_reload_insns, insn);
7356 for (j = 0; j < reload_n_operands; j++)
7358 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7359 x = emit_insn_after (output_address_reload_insns[j], x);
7360 x = emit_insn_after (output_reload_insns[j], x);
7361 emit_insn_after (other_output_reload_insns[j], x);
7364 /* For all the spill regs newly reloaded in this instruction,
7365 record what they were reloaded from, so subsequent instructions
7366 can inherit the reloads.
7368 Update spill_reg_store for the reloads of this insn.
7369 Copy the elements that were updated in the loop above. */
7371 for (j = 0; j < n_reloads; j++)
7373 int r = reload_order[j];
7374 int i = reload_spill_index[r];
7376 /* If this is a non-inherited input reload from a pseudo, we must
7377 clear any memory of a previous store to the same pseudo. Only do
7378 something if there will not be an output reload for the pseudo
7380 if (rld[r].in_reg != 0
7381 && ! (reload_inherited[r] || reload_override_in[r]))
7383 rtx reg = rld[r].in_reg;
7385 if (GET_CODE (reg) == SUBREG)
7386 reg = SUBREG_REG (reg);
7389 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7390 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7392 int nregno = REGNO (reg);
7394 if (reg_last_reload_reg[nregno])
7396 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7398 if (reg_reloaded_contents[last_regno] == nregno)
7399 spill_reg_store[last_regno] = 0;
7404 /* I is nonneg if this reload used a register.
7405 If rld[r].reg_rtx is 0, this is an optional reload
7406 that we opted to ignore. */
7408 if (i >= 0 && rld[r].reg_rtx != 0)
7410 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7412 int part_reaches_end = 0;
7413 int all_reaches_end = 1;
7415 /* For a multi register reload, we need to check if all or part
7416 of the value lives to the end. */
7417 for (k = 0; k < nr; k++)
7419 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7420 rld[r].when_needed))
7421 part_reaches_end = 1;
7423 all_reaches_end = 0;
7426 /* Ignore reloads that don't reach the end of the insn in
7428 if (all_reaches_end)
7430 /* First, clear out memory of what used to be in this spill reg.
7431 If consecutive registers are used, clear them all. */
7433 for (k = 0; k < nr; k++)
7435 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7436 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7439 /* Maybe the spill reg contains a copy of reload_out. */
7441 && (REG_P (rld[r].out)
7445 || REG_P (rld[r].out_reg)))
7447 rtx out = (REG_P (rld[r].out)
7451 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7452 int nregno = REGNO (out);
7453 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7454 : hard_regno_nregs[nregno]
7455 [GET_MODE (rld[r].reg_rtx)]);
7458 spill_reg_store[i] = new_spill_reg_store[i];
7459 spill_reg_stored_to[i] = out;
7460 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7462 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7464 && inherit_piecemeal_p (r, nregno));
7466 /* If NREGNO is a hard register, it may occupy more than
7467 one register. If it does, say what is in the
7468 rest of the registers assuming that both registers
7469 agree on how many words the object takes. If not,
7470 invalidate the subsequent registers. */
7472 if (nregno < FIRST_PSEUDO_REGISTER)
7473 for (k = 1; k < nnr; k++)
7474 reg_last_reload_reg[nregno + k]
7476 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7479 /* Now do the inverse operation. */
7480 for (k = 0; k < nr; k++)
7482 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7483 reg_reloaded_contents[i + k]
7484 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7487 reg_reloaded_insn[i + k] = insn;
7488 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7489 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7490 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7494 /* Maybe the spill reg contains a copy of reload_in. Only do
7495 something if there will not be an output reload for
7496 the register being reloaded. */
7497 else if (rld[r].out_reg == 0
7499 && ((REG_P (rld[r].in)
7500 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7501 && !REGNO_REG_SET_P (®_has_output_reload,
7503 || (REG_P (rld[r].in_reg)
7504 && !REGNO_REG_SET_P (®_has_output_reload,
7505 REGNO (rld[r].in_reg))))
7506 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7513 if (REG_P (rld[r].in)
7514 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7516 else if (REG_P (rld[r].in_reg))
7519 in = XEXP (rld[r].in_reg, 0);
7520 nregno = REGNO (in);
7522 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7523 : hard_regno_nregs[nregno]
7524 [GET_MODE (rld[r].reg_rtx)]);
7526 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7528 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7530 && inherit_piecemeal_p (r, nregno));
7532 if (nregno < FIRST_PSEUDO_REGISTER)
7533 for (k = 1; k < nnr; k++)
7534 reg_last_reload_reg[nregno + k]
7536 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7539 /* Unless we inherited this reload, show we haven't
7540 recently done a store.
7541 Previous stores of inherited auto_inc expressions
7542 also have to be discarded. */
7543 if (! reload_inherited[r]
7544 || (rld[r].out && ! rld[r].out_reg))
7545 spill_reg_store[i] = 0;
7547 for (k = 0; k < nr; k++)
7549 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7550 reg_reloaded_contents[i + k]
7551 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7554 reg_reloaded_insn[i + k] = insn;
7555 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7556 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7557 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7562 /* However, if part of the reload reaches the end, then we must
7563 invalidate the old info for the part that survives to the end. */
7564 else if (part_reaches_end)
7566 for (k = 0; k < nr; k++)
7567 if (reload_reg_reaches_end_p (i + k,
7569 rld[r].when_needed))
7570 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7574 /* The following if-statement was #if 0'd in 1.34 (or before...).
7575 It's reenabled in 1.35 because supposedly nothing else
7576 deals with this problem. */
7578 /* If a register gets output-reloaded from a non-spill register,
7579 that invalidates any previous reloaded copy of it.
7580 But forget_old_reloads_1 won't get to see it, because
7581 it thinks only about the original insn. So invalidate it here.
7582 Also do the same thing for RELOAD_OTHER constraints where the
7583 output is discarded. */
7585 && ((rld[r].out != 0
7586 && (REG_P (rld[r].out)
7587 || (MEM_P (rld[r].out)
7588 && REG_P (rld[r].out_reg))))
7589 || (rld[r].out == 0 && rld[r].out_reg
7590 && REG_P (rld[r].out_reg))))
7592 rtx out = ((rld[r].out && REG_P (rld[r].out))
7593 ? rld[r].out : rld[r].out_reg);
7594 int nregno = REGNO (out);
7596 /* REG_RTX is now set or clobbered by the main instruction.
7597 As the comment above explains, forget_old_reloads_1 only
7598 sees the original instruction, and there is no guarantee
7599 that the original instruction also clobbered REG_RTX.
7600 For example, if find_reloads sees that the input side of
7601 a matched operand pair dies in this instruction, it may
7602 use the input register as the reload register.
7604 Calling forget_old_reloads_1 is a waste of effort if
7605 REG_RTX is also the output register.
7607 If we know that REG_RTX holds the value of a pseudo
7608 register, the code after the call will record that fact. */
7609 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7610 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7612 if (nregno >= FIRST_PSEUDO_REGISTER)
7614 rtx src_reg, store_insn = NULL_RTX;
7616 reg_last_reload_reg[nregno] = 0;
7618 /* If we can find a hard register that is stored, record
7619 the storing insn so that we may delete this insn with
7620 delete_output_reload. */
7621 src_reg = rld[r].reg_rtx;
7623 /* If this is an optional reload, try to find the source reg
7624 from an input reload. */
7627 rtx set = single_set (insn);
7628 if (set && SET_DEST (set) == rld[r].out)
7632 src_reg = SET_SRC (set);
7634 for (k = 0; k < n_reloads; k++)
7636 if (rld[k].in == src_reg)
7638 src_reg = rld[k].reg_rtx;
7645 store_insn = new_spill_reg_store[REGNO (src_reg)];
7646 if (src_reg && REG_P (src_reg)
7647 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7649 int src_regno = REGNO (src_reg);
7650 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7651 /* The place where to find a death note varies with
7652 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7653 necessarily checked exactly in the code that moves
7654 notes, so just check both locations. */
7655 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7656 if (! note && store_insn)
7657 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7660 spill_reg_store[src_regno + nr] = store_insn;
7661 spill_reg_stored_to[src_regno + nr] = out;
7662 reg_reloaded_contents[src_regno + nr] = nregno;
7663 reg_reloaded_insn[src_regno + nr] = store_insn;
7664 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7665 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7666 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7667 GET_MODE (src_reg)))
7668 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7670 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7672 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7674 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7676 reg_last_reload_reg[nregno] = src_reg;
7677 /* We have to set reg_has_output_reload here, or else
7678 forget_old_reloads_1 will clear reg_last_reload_reg
7680 SET_REGNO_REG_SET (®_has_output_reload,
7686 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7688 while (num_regs-- > 0)
7689 reg_last_reload_reg[nregno + num_regs] = 0;
7693 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7696 /* Go through the motions to emit INSN and test if it is strictly valid.
7697 Return the emitted insn if valid, else return NULL. */
7700 emit_insn_if_valid_for_reload (rtx insn)
7702 rtx last = get_last_insn ();
7705 insn = emit_insn (insn);
7706 code = recog_memoized (insn);
7710 extract_insn (insn);
7711 /* We want constrain operands to treat this insn strictly in its
7712 validity determination, i.e., the way it would after reload has
7714 if (constrain_operands (1))
7718 delete_insns_since (last);
7722 /* Emit code to perform a reload from IN (which may be a reload register) to
7723 OUT (which may also be a reload register). IN or OUT is from operand
7724 OPNUM with reload type TYPE.
7726 Returns first insn emitted. */
7729 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7731 rtx last = get_last_insn ();
7734 /* If IN is a paradoxical SUBREG, remove it and try to put the
7735 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7736 if (GET_CODE (in) == SUBREG
7737 && (GET_MODE_SIZE (GET_MODE (in))
7738 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7739 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7740 in = SUBREG_REG (in), out = tem;
7741 else if (GET_CODE (out) == SUBREG
7742 && (GET_MODE_SIZE (GET_MODE (out))
7743 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7744 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7745 out = SUBREG_REG (out), in = tem;
7747 /* How to do this reload can get quite tricky. Normally, we are being
7748 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7749 register that didn't get a hard register. In that case we can just
7750 call emit_move_insn.
7752 We can also be asked to reload a PLUS that adds a register or a MEM to
7753 another register, constant or MEM. This can occur during frame pointer
7754 elimination and while reloading addresses. This case is handled by
7755 trying to emit a single insn to perform the add. If it is not valid,
7756 we use a two insn sequence.
7758 Or we can be asked to reload an unary operand that was a fragment of
7759 an addressing mode, into a register. If it isn't recognized as-is,
7760 we try making the unop operand and the reload-register the same:
7761 (set reg:X (unop:X expr:Y))
7762 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7764 Finally, we could be called to handle an 'o' constraint by putting
7765 an address into a register. In that case, we first try to do this
7766 with a named pattern of "reload_load_address". If no such pattern
7767 exists, we just emit a SET insn and hope for the best (it will normally
7768 be valid on machines that use 'o').
7770 This entire process is made complex because reload will never
7771 process the insns we generate here and so we must ensure that
7772 they will fit their constraints and also by the fact that parts of
7773 IN might be being reloaded separately and replaced with spill registers.
7774 Because of this, we are, in some sense, just guessing the right approach
7775 here. The one listed above seems to work.
7777 ??? At some point, this whole thing needs to be rethought. */
7779 if (GET_CODE (in) == PLUS
7780 && (REG_P (XEXP (in, 0))
7781 || GET_CODE (XEXP (in, 0)) == SUBREG
7782 || MEM_P (XEXP (in, 0)))
7783 && (REG_P (XEXP (in, 1))
7784 || GET_CODE (XEXP (in, 1)) == SUBREG
7785 || CONSTANT_P (XEXP (in, 1))
7786 || MEM_P (XEXP (in, 1))))
7788 /* We need to compute the sum of a register or a MEM and another
7789 register, constant, or MEM, and put it into the reload
7790 register. The best possible way of doing this is if the machine
7791 has a three-operand ADD insn that accepts the required operands.
7793 The simplest approach is to try to generate such an insn and see if it
7794 is recognized and matches its constraints. If so, it can be used.
7796 It might be better not to actually emit the insn unless it is valid,
7797 but we need to pass the insn as an operand to `recog' and
7798 `extract_insn' and it is simpler to emit and then delete the insn if
7799 not valid than to dummy things up. */
7801 rtx op0, op1, tem, insn;
7804 op0 = find_replacement (&XEXP (in, 0));
7805 op1 = find_replacement (&XEXP (in, 1));
7807 /* Since constraint checking is strict, commutativity won't be
7808 checked, so we need to do that here to avoid spurious failure
7809 if the add instruction is two-address and the second operand
7810 of the add is the same as the reload reg, which is frequently
7811 the case. If the insn would be A = B + A, rearrange it so
7812 it will be A = A + B as constrain_operands expects. */
7814 if (REG_P (XEXP (in, 1))
7815 && REGNO (out) == REGNO (XEXP (in, 1)))
7816 tem = op0, op0 = op1, op1 = tem;
7818 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7819 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7821 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7825 /* If that failed, we must use a conservative two-insn sequence.
7827 Use a move to copy one operand into the reload register. Prefer
7828 to reload a constant, MEM or pseudo since the move patterns can
7829 handle an arbitrary operand. If OP1 is not a constant, MEM or
7830 pseudo and OP1 is not a valid operand for an add instruction, then
7833 After reloading one of the operands into the reload register, add
7834 the reload register to the output register.
7836 If there is another way to do this for a specific machine, a
7837 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7840 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7842 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7844 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7845 || (code != CODE_FOR_nothing
7846 && ! ((*insn_data[code].operand[2].predicate)
7847 (op1, insn_data[code].operand[2].mode))))
7848 tem = op0, op0 = op1, op1 = tem;
7850 gen_reload (out, op0, opnum, type);
7852 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7853 This fixes a problem on the 32K where the stack pointer cannot
7854 be used as an operand of an add insn. */
7856 if (rtx_equal_p (op0, op1))
7859 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7862 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7863 set_unique_reg_note (insn, REG_EQUIV, in);
7867 /* If that failed, copy the address register to the reload register.
7868 Then add the constant to the reload register. */
7870 gen_reload (out, op1, opnum, type);
7871 insn = emit_insn (gen_add2_insn (out, op0));
7872 set_unique_reg_note (insn, REG_EQUIV, in);
7875 #ifdef SECONDARY_MEMORY_NEEDED
7876 /* If we need a memory location to do the move, do it that way. */
7877 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7878 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7879 && (REG_P (out) || GET_CODE (out) == SUBREG)
7880 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7881 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7882 REGNO_REG_CLASS (reg_or_subregno (out)),
7885 /* Get the memory to use and rewrite both registers to its mode. */
7886 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7888 if (GET_MODE (loc) != GET_MODE (out))
7889 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7891 if (GET_MODE (loc) != GET_MODE (in))
7892 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7894 gen_reload (loc, in, opnum, type);
7895 gen_reload (out, loc, opnum, type);
7898 else if (REG_P (out) && UNARY_P (in))
7905 op1 = find_replacement (&XEXP (in, 0));
7906 if (op1 != XEXP (in, 0))
7907 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7909 /* First, try a plain SET. */
7910 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7914 /* If that failed, move the inner operand to the reload
7915 register, and try the same unop with the inner expression
7916 replaced with the reload register. */
7918 if (GET_MODE (op1) != GET_MODE (out))
7919 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7923 gen_reload (out_moded, op1, opnum, type);
7926 = gen_rtx_SET (VOIDmode, out,
7927 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7929 insn = emit_insn_if_valid_for_reload (insn);
7932 set_unique_reg_note (insn, REG_EQUIV, in);
7936 fatal_insn ("Failure trying to reload:", set);
7938 /* If IN is a simple operand, use gen_move_insn. */
7939 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7941 tem = emit_insn (gen_move_insn (out, in));
7942 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
7943 mark_jump_label (in, tem, 0);
7946 #ifdef HAVE_reload_load_address
7947 else if (HAVE_reload_load_address)
7948 emit_insn (gen_reload_load_address (out, in));
7951 /* Otherwise, just write (set OUT IN) and hope for the best. */
7953 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7955 /* Return the first insn emitted.
7956 We can not just return get_last_insn, because there may have
7957 been multiple instructions emitted. Also note that gen_move_insn may
7958 emit more than one insn itself, so we can not assume that there is one
7959 insn emitted per emit_insn_before call. */
7961 return last ? NEXT_INSN (last) : get_insns ();
7964 /* Delete a previously made output-reload whose result we now believe
7965 is not needed. First we double-check.
7967 INSN is the insn now being processed.
7968 LAST_RELOAD_REG is the hard register number for which we want to delete
7969 the last output reload.
7970 J is the reload-number that originally used REG. The caller has made
7971 certain that reload J doesn't use REG any longer for input. */
7974 delete_output_reload (rtx insn, int j, int last_reload_reg)
7976 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7977 rtx reg = spill_reg_stored_to[last_reload_reg];
7980 int n_inherited = 0;
7984 /* It is possible that this reload has been only used to set another reload
7985 we eliminated earlier and thus deleted this instruction too. */
7986 if (INSN_DELETED_P (output_reload_insn))
7989 /* Get the raw pseudo-register referred to. */
7991 while (GET_CODE (reg) == SUBREG)
7992 reg = SUBREG_REG (reg);
7993 substed = reg_equiv_memory_loc[REGNO (reg)];
7995 /* This is unsafe if the operand occurs more often in the current
7996 insn than it is inherited. */
7997 for (k = n_reloads - 1; k >= 0; k--)
7999 rtx reg2 = rld[k].in;
8002 if (MEM_P (reg2) || reload_override_in[k])
8003 reg2 = rld[k].in_reg;
8005 if (rld[k].out && ! rld[k].out_reg)
8006 reg2 = XEXP (rld[k].in_reg, 0);
8008 while (GET_CODE (reg2) == SUBREG)
8009 reg2 = SUBREG_REG (reg2);
8010 if (rtx_equal_p (reg2, reg))
8012 if (reload_inherited[k] || reload_override_in[k] || k == j)
8015 reg2 = rld[k].out_reg;
8018 while (GET_CODE (reg2) == SUBREG)
8019 reg2 = XEXP (reg2, 0);
8020 if (rtx_equal_p (reg2, reg))
8027 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8028 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8029 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8032 n_occurrences += count_occurrences (PATTERN (insn),
8033 eliminate_regs (substed, 0,
8035 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8037 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8038 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8040 if (n_occurrences > n_inherited)
8043 /* If the pseudo-reg we are reloading is no longer referenced
8044 anywhere between the store into it and here,
8045 and we're within the same basic block, then the value can only
8046 pass through the reload reg and end up here.
8047 Otherwise, give up--return. */
8048 for (i1 = NEXT_INSN (output_reload_insn);
8049 i1 != insn; i1 = NEXT_INSN (i1))
8051 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8053 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8054 && reg_mentioned_p (reg, PATTERN (i1)))
8056 /* If this is USE in front of INSN, we only have to check that
8057 there are no more references than accounted for by inheritance. */
8058 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8060 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8061 i1 = NEXT_INSN (i1);
8063 if (n_occurrences <= n_inherited && i1 == insn)
8069 /* We will be deleting the insn. Remove the spill reg information. */
8070 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8072 spill_reg_store[last_reload_reg + k] = 0;
8073 spill_reg_stored_to[last_reload_reg + k] = 0;
8076 /* The caller has already checked that REG dies or is set in INSN.
8077 It has also checked that we are optimizing, and thus some
8078 inaccuracies in the debugging information are acceptable.
8079 So we could just delete output_reload_insn. But in some cases
8080 we can improve the debugging information without sacrificing
8081 optimization - maybe even improving the code: See if the pseudo
8082 reg has been completely replaced with reload regs. If so, delete
8083 the store insn and forget we had a stack slot for the pseudo. */
8084 if (rld[j].out != rld[j].in
8085 && REG_N_DEATHS (REGNO (reg)) == 1
8086 && REG_N_SETS (REGNO (reg)) == 1
8087 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8088 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8092 /* We know that it was used only between here and the beginning of
8093 the current basic block. (We also know that the last use before
8094 INSN was the output reload we are thinking of deleting, but never
8095 mind that.) Search that range; see if any ref remains. */
8096 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8098 rtx set = single_set (i2);
8100 /* Uses which just store in the pseudo don't count,
8101 since if they are the only uses, they are dead. */
8102 if (set != 0 && SET_DEST (set) == reg)
8107 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8108 && reg_mentioned_p (reg, PATTERN (i2)))
8110 /* Some other ref remains; just delete the output reload we
8112 delete_address_reloads (output_reload_insn, insn);
8113 delete_insn (output_reload_insn);
8118 /* Delete the now-dead stores into this pseudo. Note that this
8119 loop also takes care of deleting output_reload_insn. */
8120 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8122 rtx set = single_set (i2);
8124 if (set != 0 && SET_DEST (set) == reg)
8126 delete_address_reloads (i2, insn);
8134 /* For the debugging info, say the pseudo lives in this reload reg. */
8135 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8136 alter_reg (REGNO (reg), -1);
8140 delete_address_reloads (output_reload_insn, insn);
8141 delete_insn (output_reload_insn);
8145 /* We are going to delete DEAD_INSN. Recursively delete loads of
8146 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8147 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8149 delete_address_reloads (rtx dead_insn, rtx current_insn)
8151 rtx set = single_set (dead_insn);
8152 rtx set2, dst, prev, next;
8155 rtx dst = SET_DEST (set);
8157 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8159 /* If we deleted the store from a reloaded post_{in,de}c expression,
8160 we can delete the matching adds. */
8161 prev = PREV_INSN (dead_insn);
8162 next = NEXT_INSN (dead_insn);
8163 if (! prev || ! next)
8165 set = single_set (next);
8166 set2 = single_set (prev);
8168 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8169 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8170 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8172 dst = SET_DEST (set);
8173 if (! rtx_equal_p (dst, SET_DEST (set2))
8174 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8175 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8176 || (INTVAL (XEXP (SET_SRC (set), 1))
8177 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8179 delete_related_insns (prev);
8180 delete_related_insns (next);
8183 /* Subfunction of delete_address_reloads: process registers found in X. */
8185 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8187 rtx prev, set, dst, i2;
8189 enum rtx_code code = GET_CODE (x);
8193 const char *fmt = GET_RTX_FORMAT (code);
8194 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8197 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8198 else if (fmt[i] == 'E')
8200 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8201 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8208 if (spill_reg_order[REGNO (x)] < 0)
8211 /* Scan backwards for the insn that sets x. This might be a way back due
8213 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8215 code = GET_CODE (prev);
8216 if (code == CODE_LABEL || code == JUMP_INSN)
8220 if (reg_set_p (x, PATTERN (prev)))
8222 if (reg_referenced_p (x, PATTERN (prev)))
8225 if (! prev || INSN_UID (prev) < reload_first_uid)
8227 /* Check that PREV only sets the reload register. */
8228 set = single_set (prev);
8231 dst = SET_DEST (set);
8233 || ! rtx_equal_p (dst, x))
8235 if (! reg_set_p (dst, PATTERN (dead_insn)))
8237 /* Check if DST was used in a later insn -
8238 it might have been inherited. */
8239 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8245 if (reg_referenced_p (dst, PATTERN (i2)))
8247 /* If there is a reference to the register in the current insn,
8248 it might be loaded in a non-inherited reload. If no other
8249 reload uses it, that means the register is set before
8251 if (i2 == current_insn)
8253 for (j = n_reloads - 1; j >= 0; j--)
8254 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8255 || reload_override_in[j] == dst)
8257 for (j = n_reloads - 1; j >= 0; j--)
8258 if (rld[j].in && rld[j].reg_rtx == dst)
8267 /* If DST is still live at CURRENT_INSN, check if it is used for
8268 any reload. Note that even if CURRENT_INSN sets DST, we still
8269 have to check the reloads. */
8270 if (i2 == current_insn)
8272 for (j = n_reloads - 1; j >= 0; j--)
8273 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8274 || reload_override_in[j] == dst)
8276 /* ??? We can't finish the loop here, because dst might be
8277 allocated to a pseudo in this block if no reload in this
8278 block needs any of the classes containing DST - see
8279 spill_hard_reg. There is no easy way to tell this, so we
8280 have to scan till the end of the basic block. */
8282 if (reg_set_p (dst, PATTERN (i2)))
8286 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8287 reg_reloaded_contents[REGNO (dst)] = -1;
8291 /* Output reload-insns to reload VALUE into RELOADREG.
8292 VALUE is an autoincrement or autodecrement RTX whose operand
8293 is a register or memory location;
8294 so reloading involves incrementing that location.
8295 IN is either identical to VALUE, or some cheaper place to reload from.
8297 INC_AMOUNT is the number to increment or decrement by (always positive).
8298 This cannot be deduced from VALUE.
8300 Return the instruction that stores into RELOADREG. */
8303 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8305 /* REG or MEM to be copied and incremented. */
8306 rtx incloc = find_replacement (&XEXP (value, 0));
8307 /* Nonzero if increment after copying. */
8308 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8309 || GET_CODE (value) == POST_MODIFY);
8315 rtx real_in = in == value ? incloc : in;
8317 /* No hard register is equivalent to this register after
8318 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8319 we could inc/dec that register as well (maybe even using it for
8320 the source), but I'm not sure it's worth worrying about. */
8322 reg_last_reload_reg[REGNO (incloc)] = 0;
8324 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8326 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8327 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8331 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8332 inc_amount = -inc_amount;
8334 inc = GEN_INT (inc_amount);
8337 /* If this is post-increment, first copy the location to the reload reg. */
8338 if (post && real_in != reloadreg)
8339 emit_insn (gen_move_insn (reloadreg, real_in));
8343 /* See if we can directly increment INCLOC. Use a method similar to
8344 that in gen_reload. */
8346 last = get_last_insn ();
8347 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8348 gen_rtx_PLUS (GET_MODE (incloc),
8351 code = recog_memoized (add_insn);
8354 extract_insn (add_insn);
8355 if (constrain_operands (1))
8357 /* If this is a pre-increment and we have incremented the value
8358 where it lives, copy the incremented value to RELOADREG to
8359 be used as an address. */
8362 emit_insn (gen_move_insn (reloadreg, incloc));
8367 delete_insns_since (last);
8370 /* If couldn't do the increment directly, must increment in RELOADREG.
8371 The way we do this depends on whether this is pre- or post-increment.
8372 For pre-increment, copy INCLOC to the reload register, increment it
8373 there, then save back. */
8377 if (in != reloadreg)
8378 emit_insn (gen_move_insn (reloadreg, real_in));
8379 emit_insn (gen_add2_insn (reloadreg, inc));
8380 store = emit_insn (gen_move_insn (incloc, reloadreg));
8385 Because this might be a jump insn or a compare, and because RELOADREG
8386 may not be available after the insn in an input reload, we must do
8387 the incrementation before the insn being reloaded for.
8389 We have already copied IN to RELOADREG. Increment the copy in
8390 RELOADREG, save that back, then decrement RELOADREG so it has
8391 the original value. */
8393 emit_insn (gen_add2_insn (reloadreg, inc));
8394 store = emit_insn (gen_move_insn (incloc, reloadreg));
8395 if (GET_CODE (inc) == CONST_INT)
8396 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8398 emit_insn (gen_sub2_insn (reloadreg, inc));
8406 add_auto_inc_notes (rtx insn, rtx x)
8408 enum rtx_code code = GET_CODE (x);
8412 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8415 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8419 /* Scan all the operand sub-expressions. */
8420 fmt = GET_RTX_FORMAT (code);
8421 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8424 add_auto_inc_notes (insn, XEXP (x, i));
8425 else if (fmt[i] == 'E')
8426 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8427 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8432 /* Copy EH notes from an insn to its reloads. */
8434 copy_eh_notes (rtx insn, rtx x)
8436 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8439 for (; x != 0; x = NEXT_INSN (x))
8441 if (may_trap_p (PATTERN (x)))
8443 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8449 /* This is used by reload pass, that does emit some instructions after
8450 abnormal calls moving basic block end, but in fact it wants to emit
8451 them on the edge. Looks for abnormal call edges, find backward the
8452 proper call and fix the damage.
8454 Similar handle instructions throwing exceptions internally. */
8456 fixup_abnormal_edges (void)
8458 bool inserted = false;
8466 /* Look for cases we are interested in - calls or instructions causing
8468 FOR_EACH_EDGE (e, ei, bb->succs)
8470 if (e->flags & EDGE_ABNORMAL_CALL)
8472 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8473 == (EDGE_ABNORMAL | EDGE_EH))
8476 if (e && !CALL_P (BB_END (bb))
8477 && !can_throw_internal (BB_END (bb)))
8481 /* Get past the new insns generated. Allow notes, as the insns
8482 may be already deleted. */
8484 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8485 && !can_throw_internal (insn)
8486 && insn != BB_HEAD (bb))
8487 insn = PREV_INSN (insn);
8489 if (CALL_P (insn) || can_throw_internal (insn))
8493 stop = NEXT_INSN (BB_END (bb));
8495 insn = NEXT_INSN (insn);
8497 FOR_EACH_EDGE (e, ei, bb->succs)
8498 if (e->flags & EDGE_FALLTHRU)
8501 while (insn && insn != stop)
8503 next = NEXT_INSN (insn);
8508 /* Sometimes there's still the return value USE.
8509 If it's placed after a trapping call (i.e. that
8510 call is the last insn anyway), we have no fallthru
8511 edge. Simply delete this use and don't try to insert
8512 on the non-existent edge. */
8513 if (GET_CODE (PATTERN (insn)) != USE)
8515 /* We're not deleting it, we're moving it. */
8516 INSN_DELETED_P (insn) = 0;
8517 PREV_INSN (insn) = NULL_RTX;
8518 NEXT_INSN (insn) = NULL_RTX;
8520 insert_insn_on_edge (insn, e);
8528 /* It may be that we don't find any such trapping insn. In this
8529 case we discovered quite late that the insn that had been
8530 marked as can_throw_internal in fact couldn't trap at all.
8531 So we should in fact delete the EH edges out of the block. */
8533 purge_dead_edges (bb);
8537 /* We've possibly turned single trapping insn into multiple ones. */
8538 if (flag_non_call_exceptions)
8541 blocks = sbitmap_alloc (last_basic_block);
8542 sbitmap_ones (blocks);
8543 find_many_sub_basic_blocks (blocks);
8547 commit_edge_insertions ();
8549 #ifdef ENABLE_CHECKING
8550 /* Verify that we didn't turn one trapping insn into many, and that
8551 we found and corrected all of the problems wrt fixups on the
8553 verify_flow_info ();
OSDN Git Service
