1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
322 insns made by reload. */
323 HOST_WIDE_INT offset; /* Current offset between the two regs. */
324 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
325 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
326 rtx from_rtx; /* REG rtx for the register to be eliminated.
327 We cannot simply compare the number since
328 we might then spuriously replace a hard
329 register corresponding to a pseudo
330 assigned to the reg to be eliminated. */
331 rtx to_rtx; /* REG rtx for the replacement. */
334 static struct elim_table *reg_eliminate = 0;
336 /* This is an intermediate structure to initialize the table. It has
337 exactly the members provided by ELIMINABLE_REGS. */
338 static const struct elim_table_1
342 } reg_eliminate_1[] =
344 /* If a set of eliminable registers was specified, define the table from it.
345 Otherwise, default to the normal case of the frame pointer being
346 replaced by the stack pointer. */
348 #ifdef ELIMINABLE_REGS
351 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
354 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
356 /* Record the number of pending eliminations that have an offset not equal
357 to their initial offset. If nonzero, we use a new copy of each
358 replacement result in any insns encountered. */
359 int num_not_at_initial_offset;
361 /* Count the number of registers that we may be able to eliminate. */
362 static int num_eliminable;
363 /* And the number of registers that are equivalent to a constant that
364 can be eliminated to frame_pointer / arg_pointer + constant. */
365 static int num_eliminable_invariants;
367 /* For each label, we record the offset of each elimination. If we reach
368 a label by more than one path and an offset differs, we cannot do the
369 elimination. This information is indexed by the difference of the
370 number of the label and the first label number. We can't offset the
371 pointer itself as this can cause problems on machines with segmented
372 memory. The first table is an array of flags that records whether we
373 have yet encountered a label and the second table is an array of arrays,
374 one entry in the latter array for each elimination. */
376 static int first_label_num;
377 static char *offsets_known_at;
378 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
380 /* Number of labels in the current function. */
382 static int num_labels;
384 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain *);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain *, int);
389 static void find_reload_regs (struct insn_chain *);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx, enum reg_class);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx, rtx, int);
398 static void check_eliminable_occurrences (rtx);
399 static void elimination_effects (rtx, enum machine_mode);
400 static int eliminate_regs_in_insn (rtx, int);
401 static void update_eliminable_offsets (void);
402 static void mark_not_eliminable (rtx, const_rtx, void *);
403 static void set_initial_elim_offsets (void);
404 static bool verify_initial_elim_offsets (void);
405 static void set_initial_label_offsets (void);
406 static void set_offsets_for_label (rtx);
407 static void init_elim_table (void);
408 static void update_eliminables (HARD_REG_SET *);
409 static void spill_hard_reg (unsigned int, int);
410 static int finish_spills (int);
411 static void scan_paradoxical_subregs (rtx);
412 static void count_pseudo (int);
413 static void order_regs_for_reload (struct insn_chain *);
414 static void reload_as_needed (int);
415 static void forget_old_reloads_1 (rtx, const_rtx, void *);
416 static void forget_marked_reloads (regset);
417 static int reload_reg_class_lower (const void *, const void *);
418 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
420 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
422 static int reload_reg_free_p (unsigned int, int, enum reload_type);
423 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
425 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
427 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
428 static int allocate_reload_reg (struct insn_chain *, int, int);
429 static int conflicts_with_override (rtx);
430 static void failed_reload (rtx, int);
431 static int set_reload_reg (int, int);
432 static void choose_reload_regs_init (struct insn_chain *, rtx *);
433 static void choose_reload_regs (struct insn_chain *);
434 static void merge_assigned_reloads (rtx);
435 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
437 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
439 static void do_input_reload (struct insn_chain *, struct reload *, int);
440 static void do_output_reload (struct insn_chain *, struct reload *, int);
441 static void emit_reload_insns (struct insn_chain *);
442 static void delete_output_reload (rtx, int, int, rtx);
443 static void delete_address_reloads (rtx, rtx);
444 static void delete_address_reloads_1 (rtx, rtx, rtx);
445 static rtx inc_for_reload (rtx, rtx, rtx, int);
447 static void add_auto_inc_notes (rtx, rtx);
449 static void copy_eh_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert ((flag_ira && optimize) || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
904 if (flag_ira && optimize)
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
1002 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1004 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1005 else if (CONSTANT_P (XEXP (x, 0))
1006 || (REG_P (XEXP (x, 0))
1007 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1008 || (GET_CODE (XEXP (x, 0)) == PLUS
1009 && REG_P (XEXP (XEXP (x, 0), 0))
1010 && (REGNO (XEXP (XEXP (x, 0), 0))
1011 < FIRST_PSEUDO_REGISTER)
1012 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1013 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1016 /* Make a new stack slot. Then indicate that something
1017 changed so we go back and recompute offsets for
1018 eliminable registers because the allocation of memory
1019 below might change some offset. reg_equiv_{mem,address}
1020 will be set up for this pseudo on the next pass around
1022 reg_equiv_memory_loc[i] = 0;
1023 reg_equiv_init[i] = 0;
1024 alter_reg (i, -1, true);
1028 if (caller_save_needed)
1029 setup_save_areas ();
1031 /* If we allocated another stack slot, redo elimination bookkeeping. */
1032 if (starting_frame_size != get_frame_size ())
1034 if (starting_frame_size && crtl->stack_alignment_needed)
1036 /* If we have a stack frame, we must align it now. The
1037 stack size may be a part of the offset computation for
1038 register elimination. So if this changes the stack size,
1039 then repeat the elimination bookkeeping. We don't
1040 realign when there is no stack, as that will cause a
1041 stack frame when none is needed should
1042 STARTING_FRAME_OFFSET not be already aligned to
1044 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1045 if (starting_frame_size != get_frame_size ())
1049 if (caller_save_needed)
1051 save_call_clobbered_regs ();
1052 /* That might have allocated new insn_chain structures. */
1053 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1056 calculate_needs_all_insns (global);
1058 if (! flag_ira || ! optimize)
1059 /* Don't do it for IRA. We need this info because we don't
1060 change live_throughout and dead_or_set for chains when IRA
1062 CLEAR_REG_SET (&spilled_pseudos);
1066 something_changed = 0;
1068 /* If we allocated any new memory locations, make another pass
1069 since it might have changed elimination offsets. */
1070 if (starting_frame_size != get_frame_size ())
1071 something_changed = 1;
1073 /* Even if the frame size remained the same, we might still have
1074 changed elimination offsets, e.g. if find_reloads called
1075 force_const_mem requiring the back end to allocate a constant
1076 pool base register that needs to be saved on the stack. */
1077 else if (!verify_initial_elim_offsets ())
1078 something_changed = 1;
1081 HARD_REG_SET to_spill;
1082 CLEAR_HARD_REG_SET (to_spill);
1083 update_eliminables (&to_spill);
1084 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1086 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1087 if (TEST_HARD_REG_BIT (to_spill, i))
1089 spill_hard_reg (i, 1);
1092 /* Regardless of the state of spills, if we previously had
1093 a register that we thought we could eliminate, but now can
1094 not eliminate, we must run another pass.
1096 Consider pseudos which have an entry in reg_equiv_* which
1097 reference an eliminable register. We must make another pass
1098 to update reg_equiv_* so that we do not substitute in the
1099 old value from when we thought the elimination could be
1101 something_changed = 1;
1105 select_reload_regs ();
1109 if (insns_need_reload != 0 || did_spill)
1110 something_changed |= finish_spills (global);
1112 if (! something_changed)
1115 if (caller_save_needed)
1116 delete_caller_save_insns ();
1118 obstack_free (&reload_obstack, reload_firstobj);
1121 /* If global-alloc was run, notify it of any register eliminations we have
1124 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1125 if (ep->can_eliminate)
1126 mark_elimination (ep->from, ep->to);
1128 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1129 If that insn didn't set the register (i.e., it copied the register to
1130 memory), just delete that insn instead of the equivalencing insn plus
1131 anything now dead. If we call delete_dead_insn on that insn, we may
1132 delete the insn that actually sets the register if the register dies
1133 there and that is incorrect. */
1135 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1137 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1140 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1142 rtx equiv_insn = XEXP (list, 0);
1144 /* If we already deleted the insn or if it may trap, we can't
1145 delete it. The latter case shouldn't happen, but can
1146 if an insn has a variable address, gets a REG_EH_REGION
1147 note added to it, and then gets converted into a load
1148 from a constant address. */
1149 if (NOTE_P (equiv_insn)
1150 || can_throw_internal (equiv_insn))
1152 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1153 delete_dead_insn (equiv_insn);
1155 SET_INSN_DELETED (equiv_insn);
1160 /* Use the reload registers where necessary
1161 by generating move instructions to move the must-be-register
1162 values into or out of the reload registers. */
1164 if (insns_need_reload != 0 || something_needs_elimination
1165 || something_needs_operands_changed)
1167 HOST_WIDE_INT old_frame_size = get_frame_size ();
1169 reload_as_needed (global);
1171 gcc_assert (old_frame_size == get_frame_size ());
1173 gcc_assert (verify_initial_elim_offsets ());
1176 /* If we were able to eliminate the frame pointer, show that it is no
1177 longer live at the start of any basic block. If it ls live by
1178 virtue of being in a pseudo, that pseudo will be marked live
1179 and hence the frame pointer will be known to be live via that
1182 if (! frame_pointer_needed)
1184 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1186 /* Come here (with failure set nonzero) if we can't get enough spill
1190 CLEAR_REG_SET (&changed_allocation_pseudos);
1191 CLEAR_REG_SET (&spilled_pseudos);
1192 reload_in_progress = 0;
1194 /* Now eliminate all pseudo regs by modifying them into
1195 their equivalent memory references.
1196 The REG-rtx's for the pseudos are modified in place,
1197 so all insns that used to refer to them now refer to memory.
1199 For a reg that has a reg_equiv_address, all those insns
1200 were changed by reloading so that no insns refer to it any longer;
1201 but the DECL_RTL of a variable decl may refer to it,
1202 and if so this causes the debugging info to mention the variable. */
1204 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1208 if (reg_equiv_mem[i])
1209 addr = XEXP (reg_equiv_mem[i], 0);
1211 if (reg_equiv_address[i])
1212 addr = reg_equiv_address[i];
1216 if (reg_renumber[i] < 0)
1218 rtx reg = regno_reg_rtx[i];
1220 REG_USERVAR_P (reg) = 0;
1221 PUT_CODE (reg, MEM);
1222 XEXP (reg, 0) = addr;
1223 if (reg_equiv_memory_loc[i])
1224 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1227 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1228 MEM_ATTRS (reg) = 0;
1230 MEM_NOTRAP_P (reg) = 1;
1232 else if (reg_equiv_mem[i])
1233 XEXP (reg_equiv_mem[i], 0) = addr;
1237 /* We must set reload_completed now since the cleanup_subreg_operands call
1238 below will re-recognize each insn and reload may have generated insns
1239 which are only valid during and after reload. */
1240 reload_completed = 1;
1242 /* Make a pass over all the insns and delete all USEs which we inserted
1243 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1244 notes. Delete all CLOBBER insns, except those that refer to the return
1245 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1246 from misarranging variable-array code, and simplify (subreg (reg))
1247 operands. Strip and regenerate REG_INC notes that may have been moved
1250 for (insn = first; insn; insn = NEXT_INSN (insn))
1256 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1257 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1259 if ((GET_CODE (PATTERN (insn)) == USE
1260 /* We mark with QImode USEs introduced by reload itself. */
1261 && (GET_MODE (insn) == QImode
1262 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1263 || (GET_CODE (PATTERN (insn)) == CLOBBER
1264 && (!MEM_P (XEXP (PATTERN (insn), 0))
1265 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1266 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1267 && XEXP (XEXP (PATTERN (insn), 0), 0)
1268 != stack_pointer_rtx))
1269 && (!REG_P (XEXP (PATTERN (insn), 0))
1270 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1276 /* Some CLOBBERs may survive until here and still reference unassigned
1277 pseudos with const equivalent, which may in turn cause ICE in later
1278 passes if the reference remains in place. */
1279 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1280 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1281 VOIDmode, PATTERN (insn));
1283 /* Discard obvious no-ops, even without -O. This optimization
1284 is fast and doesn't interfere with debugging. */
1285 if (NONJUMP_INSN_P (insn)
1286 && GET_CODE (PATTERN (insn)) == SET
1287 && REG_P (SET_SRC (PATTERN (insn)))
1288 && REG_P (SET_DEST (PATTERN (insn)))
1289 && (REGNO (SET_SRC (PATTERN (insn)))
1290 == REGNO (SET_DEST (PATTERN (insn)))))
1296 pnote = ®_NOTES (insn);
1299 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1300 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1301 || REG_NOTE_KIND (*pnote) == REG_INC)
1302 *pnote = XEXP (*pnote, 1);
1304 pnote = &XEXP (*pnote, 1);
1308 add_auto_inc_notes (insn, PATTERN (insn));
1311 /* Simplify (subreg (reg)) if it appears as an operand. */
1312 cleanup_subreg_operands (insn);
1314 /* Clean up invalid ASMs so that they don't confuse later passes.
1316 if (asm_noperands (PATTERN (insn)) >= 0)
1318 extract_insn (insn);
1319 if (!constrain_operands (1))
1321 error_for_asm (insn,
1322 "%<asm%> operand has impossible constraints");
1329 /* If we are doing generic stack checking, give a warning if this
1330 function's frame size is larger than we expect. */
1331 if (flag_stack_check == GENERIC_STACK_CHECK)
1333 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1334 static int verbose_warned = 0;
1336 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1337 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1338 size += UNITS_PER_WORD;
1340 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1342 warning (0, "frame size too large for reliable stack checking");
1343 if (! verbose_warned)
1345 warning (0, "try reducing the number of local variables");
1351 /* Indicate that we no longer have known memory locations or constants. */
1352 if (reg_equiv_constant)
1353 free (reg_equiv_constant);
1354 if (reg_equiv_invariant)
1355 free (reg_equiv_invariant);
1356 reg_equiv_constant = 0;
1357 reg_equiv_invariant = 0;
1358 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1359 reg_equiv_memory_loc = 0;
1361 free (temp_pseudo_reg_arr);
1363 if (offsets_known_at)
1364 free (offsets_known_at);
1368 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1369 if (reg_equiv_alt_mem_list[i])
1370 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1371 free (reg_equiv_alt_mem_list);
1373 free (reg_equiv_mem);
1375 free (reg_equiv_address);
1376 free (reg_max_ref_width);
1377 free (reg_old_renumber);
1378 free (pseudo_previous_regs);
1379 free (pseudo_forbidden_regs);
1381 CLEAR_HARD_REG_SET (used_spill_regs);
1382 for (i = 0; i < n_spills; i++)
1383 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1385 /* Free all the insn_chain structures at once. */
1386 obstack_free (&reload_obstack, reload_startobj);
1387 unused_insn_chains = 0;
1388 fixup_abnormal_edges ();
1390 /* Replacing pseudos with their memory equivalents might have
1391 created shared rtx. Subsequent passes would get confused
1392 by this, so unshare everything here. */
1393 unshare_all_rtl_again (first);
1395 #ifdef STACK_BOUNDARY
1396 /* init_emit has set the alignment of the hard frame pointer
1397 to STACK_BOUNDARY. It is very likely no longer valid if
1398 the hard frame pointer was used for register allocation. */
1399 if (!frame_pointer_needed)
1400 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1406 /* Yet another special case. Unfortunately, reg-stack forces people to
1407 write incorrect clobbers in asm statements. These clobbers must not
1408 cause the register to appear in bad_spill_regs, otherwise we'll call
1409 fatal_insn later. We clear the corresponding regnos in the live
1410 register sets to avoid this.
1411 The whole thing is rather sick, I'm afraid. */
1414 maybe_fix_stack_asms (void)
1417 const char *constraints[MAX_RECOG_OPERANDS];
1418 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1419 struct insn_chain *chain;
1421 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1424 HARD_REG_SET clobbered, allowed;
1427 if (! INSN_P (chain->insn)
1428 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1430 pat = PATTERN (chain->insn);
1431 if (GET_CODE (pat) != PARALLEL)
1434 CLEAR_HARD_REG_SET (clobbered);
1435 CLEAR_HARD_REG_SET (allowed);
1437 /* First, make a mask of all stack regs that are clobbered. */
1438 for (i = 0; i < XVECLEN (pat, 0); i++)
1440 rtx t = XVECEXP (pat, 0, i);
1441 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1442 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1445 /* Get the operand values and constraints out of the insn. */
1446 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1447 constraints, operand_mode, NULL);
1449 /* For every operand, see what registers are allowed. */
1450 for (i = 0; i < noperands; i++)
1452 const char *p = constraints[i];
1453 /* For every alternative, we compute the class of registers allowed
1454 for reloading in CLS, and merge its contents into the reg set
1456 int cls = (int) NO_REGS;
1462 if (c == '\0' || c == ',' || c == '#')
1464 /* End of one alternative - mark the regs in the current
1465 class, and reset the class. */
1466 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1472 } while (c != '\0' && c != ',');
1480 case '=': case '+': case '*': case '%': case '?': case '!':
1481 case '0': case '1': case '2': case '3': case '4': case '<':
1482 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1483 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1484 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1485 case TARGET_MEM_CONSTRAINT:
1489 cls = (int) reg_class_subunion[cls]
1490 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1495 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1499 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1500 cls = (int) reg_class_subunion[cls]
1501 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1503 cls = (int) reg_class_subunion[cls]
1504 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1506 p += CONSTRAINT_LEN (c, p);
1509 /* Those of the registers which are clobbered, but allowed by the
1510 constraints, must be usable as reload registers. So clear them
1511 out of the life information. */
1512 AND_HARD_REG_SET (allowed, clobbered);
1513 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1514 if (TEST_HARD_REG_BIT (allowed, i))
1516 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1517 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1524 /* Copy the global variables n_reloads and rld into the corresponding elts
1527 copy_reloads (struct insn_chain *chain)
1529 chain->n_reloads = n_reloads;
1530 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1531 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1532 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1535 /* Walk the chain of insns, and determine for each whether it needs reloads
1536 and/or eliminations. Build the corresponding insns_need_reload list, and
1537 set something_needs_elimination as appropriate. */
1539 calculate_needs_all_insns (int global)
1541 struct insn_chain **pprev_reload = &insns_need_reload;
1542 struct insn_chain *chain, *next = 0;
1544 something_needs_elimination = 0;
1546 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1547 for (chain = reload_insn_chain; chain != 0; chain = next)
1549 rtx insn = chain->insn;
1553 /* Clear out the shortcuts. */
1554 chain->n_reloads = 0;
1555 chain->need_elim = 0;
1556 chain->need_reload = 0;
1557 chain->need_operand_change = 0;
1559 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1560 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1561 what effects this has on the known offsets at labels. */
1563 if (LABEL_P (insn) || JUMP_P (insn)
1564 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1565 set_label_offsets (insn, insn, 0);
1569 rtx old_body = PATTERN (insn);
1570 int old_code = INSN_CODE (insn);
1571 rtx old_notes = REG_NOTES (insn);
1572 int did_elimination = 0;
1573 int operands_changed = 0;
1574 rtx set = single_set (insn);
1576 /* Skip insns that only set an equivalence. */
1577 if (set && REG_P (SET_DEST (set))
1578 && reg_renumber[REGNO (SET_DEST (set))] < 0
1579 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1580 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1581 && reg_equiv_init[REGNO (SET_DEST (set))])
1584 /* If needed, eliminate any eliminable registers. */
1585 if (num_eliminable || num_eliminable_invariants)
1586 did_elimination = eliminate_regs_in_insn (insn, 0);
1588 /* Analyze the instruction. */
1589 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1590 global, spill_reg_order);
1592 /* If a no-op set needs more than one reload, this is likely
1593 to be something that needs input address reloads. We
1594 can't get rid of this cleanly later, and it is of no use
1595 anyway, so discard it now.
1596 We only do this when expensive_optimizations is enabled,
1597 since this complements reload inheritance / output
1598 reload deletion, and it can make debugging harder. */
1599 if (flag_expensive_optimizations && n_reloads > 1)
1601 rtx set = single_set (insn);
1604 ((SET_SRC (set) == SET_DEST (set)
1605 && REG_P (SET_SRC (set))
1606 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1607 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1608 && reg_renumber[REGNO (SET_SRC (set))] < 0
1609 && reg_renumber[REGNO (SET_DEST (set))] < 0
1610 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1611 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1612 && rtx_equal_p (reg_equiv_memory_loc
1613 [REGNO (SET_SRC (set))],
1614 reg_equiv_memory_loc
1615 [REGNO (SET_DEST (set))]))))
1617 if (flag_ira && optimize)
1618 /* Inform IRA about the insn deletion. */
1619 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1620 REGNO (SET_SRC (set)));
1622 /* Delete it from the reload chain. */
1624 chain->prev->next = next;
1626 reload_insn_chain = next;
1628 next->prev = chain->prev;
1629 chain->next = unused_insn_chains;
1630 unused_insn_chains = chain;
1635 update_eliminable_offsets ();
1637 /* Remember for later shortcuts which insns had any reloads or
1638 register eliminations. */
1639 chain->need_elim = did_elimination;
1640 chain->need_reload = n_reloads > 0;
1641 chain->need_operand_change = operands_changed;
1643 /* Discard any register replacements done. */
1644 if (did_elimination)
1646 obstack_free (&reload_obstack, reload_insn_firstobj);
1647 PATTERN (insn) = old_body;
1648 INSN_CODE (insn) = old_code;
1649 REG_NOTES (insn) = old_notes;
1650 something_needs_elimination = 1;
1653 something_needs_operands_changed |= operands_changed;
1657 copy_reloads (chain);
1658 *pprev_reload = chain;
1659 pprev_reload = &chain->next_need_reload;
1666 /* Comparison function for qsort to decide which of two reloads
1667 should be handled first. *P1 and *P2 are the reload numbers. */
1670 reload_reg_class_lower (const void *r1p, const void *r2p)
1672 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1675 /* Consider required reloads before optional ones. */
1676 t = rld[r1].optional - rld[r2].optional;
1680 /* Count all solitary classes before non-solitary ones. */
1681 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1682 - (reg_class_size[(int) rld[r1].rclass] == 1));
1686 /* Aside from solitaires, consider all multi-reg groups first. */
1687 t = rld[r2].nregs - rld[r1].nregs;
1691 /* Consider reloads in order of increasing reg-class number. */
1692 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1696 /* If reloads are equally urgent, sort by reload number,
1697 so that the results of qsort leave nothing to chance. */
1701 /* The cost of spilling each hard reg. */
1702 static int spill_cost[FIRST_PSEUDO_REGISTER];
1704 /* When spilling multiple hard registers, we use SPILL_COST for the first
1705 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1706 only the first hard reg for a multi-reg pseudo. */
1707 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1709 /* Map of hard regno to pseudo regno currently occupying the hard
1711 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1713 /* Update the spill cost arrays, considering that pseudo REG is live. */
1716 count_pseudo (int reg)
1718 int freq = REG_FREQ (reg);
1719 int r = reg_renumber[reg];
1722 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1723 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1724 /* Ignore spilled pseudo-registers which can be here only if IRA
1726 || (flag_ira && optimize && r < 0))
1729 SET_REGNO_REG_SET (&pseudos_counted, reg);
1731 gcc_assert (r >= 0);
1733 spill_add_cost[r] += freq;
1734 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1737 hard_regno_to_pseudo_regno[r + nregs] = reg;
1738 spill_cost[r + nregs] += freq;
1742 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1743 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1746 order_regs_for_reload (struct insn_chain *chain)
1749 HARD_REG_SET used_by_pseudos;
1750 HARD_REG_SET used_by_pseudos2;
1751 reg_set_iterator rsi;
1753 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1755 memset (spill_cost, 0, sizeof spill_cost);
1756 memset (spill_add_cost, 0, sizeof spill_add_cost);
1757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1758 hard_regno_to_pseudo_regno[i] = -1;
1760 /* Count number of uses of each hard reg by pseudo regs allocated to it
1761 and then order them by decreasing use. First exclude hard registers
1762 that are live in or across this insn. */
1764 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1765 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1766 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1767 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1769 /* Now find out which pseudos are allocated to it, and update
1771 CLEAR_REG_SET (&pseudos_counted);
1773 EXECUTE_IF_SET_IN_REG_SET
1774 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1778 EXECUTE_IF_SET_IN_REG_SET
1779 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1783 CLEAR_REG_SET (&pseudos_counted);
1786 /* Vector of reload-numbers showing the order in which the reloads should
1788 static short reload_order[MAX_RELOADS];
1790 /* This is used to keep track of the spill regs used in one insn. */
1791 static HARD_REG_SET used_spill_regs_local;
1793 /* We decided to spill hard register SPILLED, which has a size of
1794 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1795 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1796 update SPILL_COST/SPILL_ADD_COST. */
1799 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1801 int freq = REG_FREQ (reg);
1802 int r = reg_renumber[reg];
1803 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1805 /* Ignore spilled pseudo-registers which can be here only if IRA is
1807 if ((flag_ira && optimize && r < 0)
1808 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1809 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1812 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1814 spill_add_cost[r] -= freq;
1817 hard_regno_to_pseudo_regno[r + nregs] = -1;
1818 spill_cost[r + nregs] -= freq;
1822 /* Find reload register to use for reload number ORDER. */
1825 find_reg (struct insn_chain *chain, int order)
1827 int rnum = reload_order[order];
1828 struct reload *rl = rld + rnum;
1829 int best_cost = INT_MAX;
1831 unsigned int i, j, n;
1833 HARD_REG_SET not_usable;
1834 HARD_REG_SET used_by_other_reload;
1835 reg_set_iterator rsi;
1836 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1837 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1839 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1840 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1841 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1843 CLEAR_HARD_REG_SET (used_by_other_reload);
1844 for (k = 0; k < order; k++)
1846 int other = reload_order[k];
1848 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1849 for (j = 0; j < rld[other].nregs; j++)
1850 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1853 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1855 #ifdef REG_ALLOC_ORDER
1856 unsigned int regno = reg_alloc_order[i];
1858 unsigned int regno = i;
1861 if (! TEST_HARD_REG_BIT (not_usable, regno)
1862 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1863 && HARD_REGNO_MODE_OK (regno, rl->mode))
1865 int this_cost = spill_cost[regno];
1867 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1869 for (j = 1; j < this_nregs; j++)
1871 this_cost += spill_add_cost[regno + j];
1872 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1873 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1879 if (flag_ira && optimize)
1881 /* Ask IRA to find a better pseudo-register for
1883 for (n = j = 0; j < this_nregs; j++)
1885 int r = hard_regno_to_pseudo_regno[regno + j];
1889 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1890 regno_pseudo_regs[n++] = r;
1892 regno_pseudo_regs[n++] = -1;
1894 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1895 best_regno_pseudo_regs,
1902 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1903 if (regno_pseudo_regs[j] < 0)
1910 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1912 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1914 if (this_cost < best_cost
1915 /* Among registers with equal cost, prefer caller-saved ones, or
1916 use REG_ALLOC_ORDER if it is defined. */
1917 || (this_cost == best_cost
1918 #ifdef REG_ALLOC_ORDER
1919 && (inv_reg_alloc_order[regno]
1920 < inv_reg_alloc_order[best_reg])
1922 && call_used_regs[regno]
1923 && ! call_used_regs[best_reg]
1928 best_cost = this_cost;
1936 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1938 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1939 rl->regno = best_reg;
1941 EXECUTE_IF_SET_IN_REG_SET
1942 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1944 count_spilled_pseudo (best_reg, rl->nregs, j);
1947 EXECUTE_IF_SET_IN_REG_SET
1948 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1950 count_spilled_pseudo (best_reg, rl->nregs, j);
1953 for (i = 0; i < rl->nregs; i++)
1955 gcc_assert (spill_cost[best_reg + i] == 0);
1956 gcc_assert (spill_add_cost[best_reg + i] == 0);
1957 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1958 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1963 /* Find more reload regs to satisfy the remaining need of an insn, which
1965 Do it by ascending class number, since otherwise a reg
1966 might be spilled for a big class and might fail to count
1967 for a smaller class even though it belongs to that class. */
1970 find_reload_regs (struct insn_chain *chain)
1974 /* In order to be certain of getting the registers we need,
1975 we must sort the reloads into order of increasing register class.
1976 Then our grabbing of reload registers will parallel the process
1977 that provided the reload registers. */
1978 for (i = 0; i < chain->n_reloads; i++)
1980 /* Show whether this reload already has a hard reg. */
1981 if (chain->rld[i].reg_rtx)
1983 int regno = REGNO (chain->rld[i].reg_rtx);
1984 chain->rld[i].regno = regno;
1986 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1989 chain->rld[i].regno = -1;
1990 reload_order[i] = i;
1993 n_reloads = chain->n_reloads;
1994 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1996 CLEAR_HARD_REG_SET (used_spill_regs_local);
1999 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2001 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2003 /* Compute the order of preference for hard registers to spill. */
2005 order_regs_for_reload (chain);
2007 for (i = 0; i < n_reloads; i++)
2009 int r = reload_order[i];
2011 /* Ignore reloads that got marked inoperative. */
2012 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2013 && ! rld[r].optional
2014 && rld[r].regno == -1)
2015 if (! find_reg (chain, i))
2018 fprintf (dump_file, "reload failure for reload %d\n", r);
2019 spill_failure (chain->insn, rld[r].rclass);
2025 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2026 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2028 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2032 select_reload_regs (void)
2034 struct insn_chain *chain;
2036 /* Try to satisfy the needs for each insn. */
2037 for (chain = insns_need_reload; chain != 0;
2038 chain = chain->next_need_reload)
2039 find_reload_regs (chain);
2042 /* Delete all insns that were inserted by emit_caller_save_insns during
2045 delete_caller_save_insns (void)
2047 struct insn_chain *c = reload_insn_chain;
2051 while (c != 0 && c->is_caller_save_insn)
2053 struct insn_chain *next = c->next;
2056 if (c == reload_insn_chain)
2057 reload_insn_chain = next;
2061 next->prev = c->prev;
2063 c->prev->next = next;
2064 c->next = unused_insn_chains;
2065 unused_insn_chains = c;
2073 /* Handle the failure to find a register to spill.
2074 INSN should be one of the insns which needed this particular spill reg. */
2077 spill_failure (rtx insn, enum reg_class rclass)
2079 if (asm_noperands (PATTERN (insn)) >= 0)
2080 error_for_asm (insn, "can't find a register in class %qs while "
2081 "reloading %<asm%>",
2082 reg_class_names[rclass]);
2085 error ("unable to find a register to spill in class %qs",
2086 reg_class_names[rclass]);
2090 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2091 debug_reload_to_stream (dump_file);
2093 fatal_insn ("this is the insn:", insn);
2097 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2098 data that is dead in INSN. */
2101 delete_dead_insn (rtx insn)
2103 rtx prev = prev_real_insn (insn);
2106 /* If the previous insn sets a register that dies in our insn, delete it
2108 if (prev && GET_CODE (PATTERN (prev)) == SET
2109 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2110 && reg_mentioned_p (prev_dest, PATTERN (insn))
2111 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2112 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2113 delete_dead_insn (prev);
2115 SET_INSN_DELETED (insn);
2118 /* Modify the home of pseudo-reg I.
2119 The new home is present in reg_renumber[I].
2121 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2122 or it may be -1, meaning there is none or it is not relevant.
2123 This is used so that all pseudos spilled from a given hard reg
2124 can share one stack slot. */
2127 alter_reg (int i, int from_reg, bool dont_share_p)
2129 /* When outputting an inline function, this can happen
2130 for a reg that isn't actually used. */
2131 if (regno_reg_rtx[i] == 0)
2134 /* If the reg got changed to a MEM at rtl-generation time,
2136 if (!REG_P (regno_reg_rtx[i]))
2139 /* Modify the reg-rtx to contain the new hard reg
2140 number or else to contain its pseudo reg number. */
2141 SET_REGNO (regno_reg_rtx[i],
2142 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2144 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2145 allocate a stack slot for it. */
2147 if (reg_renumber[i] < 0
2148 && REG_N_REFS (i) > 0
2149 && reg_equiv_constant[i] == 0
2150 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2151 && reg_equiv_memory_loc[i] == 0)
2154 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2155 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2156 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2157 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2158 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2160 bool shared_p = false;
2162 if (flag_ira && optimize)
2163 /* Mark the spill for IRA. */
2164 SET_REGNO_REG_SET (&spilled_pseudos, i);
2165 x = (dont_share_p || ! flag_ira || ! optimize
2166 ? NULL_RTX : ira_reuse_stack_slot (i, inherent_size, total_size));
2169 /* Each pseudo reg has an inherent size which comes from its own mode,
2170 and a total size which provides room for paradoxical subregs
2171 which refer to the pseudo reg in wider modes.
2173 We can use a slot already allocated if it provides both
2174 enough inherent space and enough total space.
2175 Otherwise, we allocate a new slot, making sure that it has no less
2176 inherent space, and no less total space, then the previous slot. */
2177 else if (from_reg == -1 || (! dont_share_p && flag_ira && optimize))
2180 alias_set_type alias_set = new_alias_set ();
2182 /* No known place to spill from => no slot to reuse. */
2183 x = assign_stack_local (mode, total_size,
2184 min_align > inherent_align
2185 || total_size > inherent_size ? -1 : 0);
2189 if (BYTES_BIG_ENDIAN)
2190 /* Cancel the big-endian correction done in assign_stack_local.
2191 Get the address of the beginning of the slot.
2192 This is so we can do a big-endian correction unconditionally
2194 adjust = inherent_size - total_size;
2197 = adjust_address_nv (x, mode_for_size (total_size
2202 /* Nothing can alias this slot except this pseudo. */
2203 set_mem_alias_set (x, alias_set);
2204 dse_record_singleton_alias_set (alias_set, mode);
2206 if (! dont_share_p && flag_ira && optimize)
2207 /* Inform IRA about allocation a new stack slot. */
2208 ira_mark_new_stack_slot (stack_slot, i, total_size);
2211 /* Reuse a stack slot if possible. */
2212 else if (spill_stack_slot[from_reg] != 0
2213 && spill_stack_slot_width[from_reg] >= total_size
2214 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2216 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2217 x = spill_stack_slot[from_reg];
2218 /* Allocate a bigger slot. */
2221 /* Compute maximum size needed, both for inherent size
2222 and for total size. */
2225 if (spill_stack_slot[from_reg])
2227 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2229 mode = GET_MODE (spill_stack_slot[from_reg]);
2230 if (spill_stack_slot_width[from_reg] > total_size)
2231 total_size = spill_stack_slot_width[from_reg];
2232 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2233 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2236 /* Make a slot with that size. */
2237 x = assign_stack_local (mode, total_size,
2238 min_align > inherent_align
2239 || total_size > inherent_size ? -1 : 0);
2242 /* All pseudos mapped to this slot can alias each other. */
2243 if (spill_stack_slot[from_reg])
2245 alias_set_type alias_set
2246 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2247 set_mem_alias_set (x, alias_set);
2248 dse_invalidate_singleton_alias_set (alias_set);
2252 alias_set_type alias_set = new_alias_set ();
2253 set_mem_alias_set (x, alias_set);
2254 dse_record_singleton_alias_set (alias_set, mode);
2257 if (BYTES_BIG_ENDIAN)
2259 /* Cancel the big-endian correction done in assign_stack_local.
2260 Get the address of the beginning of the slot.
2261 This is so we can do a big-endian correction unconditionally
2263 adjust = GET_MODE_SIZE (mode) - total_size;
2266 = adjust_address_nv (x, mode_for_size (total_size
2272 spill_stack_slot[from_reg] = stack_slot;
2273 spill_stack_slot_width[from_reg] = total_size;
2276 /* On a big endian machine, the "address" of the slot
2277 is the address of the low part that fits its inherent mode. */
2278 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2279 adjust += (total_size - inherent_size);
2281 /* If we have any adjustment to make, or if the stack slot is the
2282 wrong mode, make a new stack slot. */
2283 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2285 /* If we have a decl for the original register, set it for the
2286 memory. If this is a shared MEM, make a copy. */
2290 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2292 else if (REG_EXPR (regno_reg_rtx[i])
2293 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2295 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2297 /* We can do this only for the DECLs home pseudo, not for
2298 any copies of it, since otherwise when the stack slot
2299 is reused, nonoverlapping_memrefs_p might think they
2301 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2303 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2306 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2310 /* Save the stack slot for later. */
2311 reg_equiv_memory_loc[i] = x;
2315 /* Mark the slots in regs_ever_live for the hard regs used by
2316 pseudo-reg number REGNO, accessed in MODE. */
2319 mark_home_live_1 (int regno, enum machine_mode mode)
2323 i = reg_renumber[regno];
2326 lim = end_hard_regno (mode, i);
2328 df_set_regs_ever_live(i++, true);
2331 /* Mark the slots in regs_ever_live for the hard regs
2332 used by pseudo-reg number REGNO. */
2335 mark_home_live (int regno)
2337 if (reg_renumber[regno] >= 0)
2338 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2341 /* This function handles the tracking of elimination offsets around branches.
2343 X is a piece of RTL being scanned.
2345 INSN is the insn that it came from, if any.
2347 INITIAL_P is nonzero if we are to set the offset to be the initial
2348 offset and zero if we are setting the offset of the label to be the
2352 set_label_offsets (rtx x, rtx insn, int initial_p)
2354 enum rtx_code code = GET_CODE (x);
2357 struct elim_table *p;
2362 if (LABEL_REF_NONLOCAL_P (x))
2367 /* ... fall through ... */
2370 /* If we know nothing about this label, set the desired offsets. Note
2371 that this sets the offset at a label to be the offset before a label
2372 if we don't know anything about the label. This is not correct for
2373 the label after a BARRIER, but is the best guess we can make. If
2374 we guessed wrong, we will suppress an elimination that might have
2375 been possible had we been able to guess correctly. */
2377 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2379 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2380 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2381 = (initial_p ? reg_eliminate[i].initial_offset
2382 : reg_eliminate[i].offset);
2383 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2386 /* Otherwise, if this is the definition of a label and it is
2387 preceded by a BARRIER, set our offsets to the known offset of
2391 && (tem = prev_nonnote_insn (insn)) != 0
2393 set_offsets_for_label (insn);
2395 /* If neither of the above cases is true, compare each offset
2396 with those previously recorded and suppress any eliminations
2397 where the offsets disagree. */
2399 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2400 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2401 != (initial_p ? reg_eliminate[i].initial_offset
2402 : reg_eliminate[i].offset))
2403 reg_eliminate[i].can_eliminate = 0;
2408 set_label_offsets (PATTERN (insn), insn, initial_p);
2410 /* ... fall through ... */
2414 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2415 to indirectly and hence must have all eliminations at their
2417 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2418 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2419 set_label_offsets (XEXP (tem, 0), insn, 1);
2425 /* Each of the labels in the parallel or address vector must be
2426 at their initial offsets. We want the first field for PARALLEL
2427 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2429 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2430 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2435 /* We only care about setting PC. If the source is not RETURN,
2436 IF_THEN_ELSE, or a label, disable any eliminations not at
2437 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2438 isn't one of those possibilities. For branches to a label,
2439 call ourselves recursively.
2441 Note that this can disable elimination unnecessarily when we have
2442 a non-local goto since it will look like a non-constant jump to
2443 someplace in the current function. This isn't a significant
2444 problem since such jumps will normally be when all elimination
2445 pairs are back to their initial offsets. */
2447 if (SET_DEST (x) != pc_rtx)
2450 switch (GET_CODE (SET_SRC (x)))
2457 set_label_offsets (SET_SRC (x), insn, initial_p);
2461 tem = XEXP (SET_SRC (x), 1);
2462 if (GET_CODE (tem) == LABEL_REF)
2463 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2464 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2467 tem = XEXP (SET_SRC (x), 2);
2468 if (GET_CODE (tem) == LABEL_REF)
2469 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2470 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2478 /* If we reach here, all eliminations must be at their initial
2479 offset because we are doing a jump to a variable address. */
2480 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2481 if (p->offset != p->initial_offset)
2482 p->can_eliminate = 0;
2490 /* Scan X and replace any eliminable registers (such as fp) with a
2491 replacement (such as sp), plus an offset.
2493 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2494 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2495 MEM, we are allowed to replace a sum of a register and the constant zero
2496 with the register, which we cannot do outside a MEM. In addition, we need
2497 to record the fact that a register is referenced outside a MEM.
2499 If INSN is an insn, it is the insn containing X. If we replace a REG
2500 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2501 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2502 the REG is being modified.
2504 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2505 That's used when we eliminate in expressions stored in notes.
2506 This means, do not set ref_outside_mem even if the reference
2509 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2510 replacements done assuming all offsets are at their initial values. If
2511 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2512 encounter, return the actual location so that find_reloads will do
2513 the proper thing. */
2516 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2517 bool may_use_invariant)
2519 enum rtx_code code = GET_CODE (x);
2520 struct elim_table *ep;
2527 if (! current_function_decl)
2550 /* First handle the case where we encounter a bare register that
2551 is eliminable. Replace it with a PLUS. */
2552 if (regno < FIRST_PSEUDO_REGISTER)
2554 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2556 if (ep->from_rtx == x && ep->can_eliminate)
2557 return plus_constant (ep->to_rtx, ep->previous_offset);
2560 else if (reg_renumber && reg_renumber[regno] < 0
2561 && reg_equiv_invariant && reg_equiv_invariant[regno])
2563 if (may_use_invariant)
2564 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2565 mem_mode, insn, true);
2566 /* There exists at least one use of REGNO that cannot be
2567 eliminated. Prevent the defining insn from being deleted. */
2568 reg_equiv_init[regno] = NULL_RTX;
2569 alter_reg (regno, -1, true);
2573 /* You might think handling MINUS in a manner similar to PLUS is a
2574 good idea. It is not. It has been tried multiple times and every
2575 time the change has had to have been reverted.
2577 Other parts of reload know a PLUS is special (gen_reload for example)
2578 and require special code to handle code a reloaded PLUS operand.
2580 Also consider backends where the flags register is clobbered by a
2581 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2582 lea instruction comes to mind). If we try to reload a MINUS, we
2583 may kill the flags register that was holding a useful value.
2585 So, please before trying to handle MINUS, consider reload as a
2586 whole instead of this little section as well as the backend issues. */
2588 /* If this is the sum of an eliminable register and a constant, rework
2590 if (REG_P (XEXP (x, 0))
2591 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2592 && CONSTANT_P (XEXP (x, 1)))
2594 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2596 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2598 /* The only time we want to replace a PLUS with a REG (this
2599 occurs when the constant operand of the PLUS is the negative
2600 of the offset) is when we are inside a MEM. We won't want
2601 to do so at other times because that would change the
2602 structure of the insn in a way that reload can't handle.
2603 We special-case the commonest situation in
2604 eliminate_regs_in_insn, so just replace a PLUS with a
2605 PLUS here, unless inside a MEM. */
2606 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2607 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2610 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2611 plus_constant (XEXP (x, 1),
2612 ep->previous_offset));
2615 /* If the register is not eliminable, we are done since the other
2616 operand is a constant. */
2620 /* If this is part of an address, we want to bring any constant to the
2621 outermost PLUS. We will do this by doing register replacement in
2622 our operands and seeing if a constant shows up in one of them.
2624 Note that there is no risk of modifying the structure of the insn,
2625 since we only get called for its operands, thus we are either
2626 modifying the address inside a MEM, or something like an address
2627 operand of a load-address insn. */
2630 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2631 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2633 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2635 /* If one side is a PLUS and the other side is a pseudo that
2636 didn't get a hard register but has a reg_equiv_constant,
2637 we must replace the constant here since it may no longer
2638 be in the position of any operand. */
2639 if (GET_CODE (new0) == PLUS && REG_P (new1)
2640 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2641 && reg_renumber[REGNO (new1)] < 0
2642 && reg_equiv_constant != 0
2643 && reg_equiv_constant[REGNO (new1)] != 0)
2644 new1 = reg_equiv_constant[REGNO (new1)];
2645 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2646 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2647 && reg_renumber[REGNO (new0)] < 0
2648 && reg_equiv_constant[REGNO (new0)] != 0)
2649 new0 = reg_equiv_constant[REGNO (new0)];
2651 new_rtx = form_sum (new0, new1);
2653 /* As above, if we are not inside a MEM we do not want to
2654 turn a PLUS into something else. We might try to do so here
2655 for an addition of 0 if we aren't optimizing. */
2656 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2657 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2665 /* If this is the product of an eliminable register and a
2666 constant, apply the distribute law and move the constant out
2667 so that we have (plus (mult ..) ..). This is needed in order
2668 to keep load-address insns valid. This case is pathological.
2669 We ignore the possibility of overflow here. */
2670 if (REG_P (XEXP (x, 0))
2671 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2672 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2673 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2675 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2678 /* Refs inside notes don't count for this purpose. */
2679 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2680 || GET_CODE (insn) == INSN_LIST)))
2681 ep->ref_outside_mem = 1;
2684 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2685 ep->previous_offset * INTVAL (XEXP (x, 1)));
2688 /* ... fall through ... */
2692 /* See comments before PLUS about handling MINUS. */
2694 case DIV: case UDIV:
2695 case MOD: case UMOD:
2696 case AND: case IOR: case XOR:
2697 case ROTATERT: case ROTATE:
2698 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2700 case GE: case GT: case GEU: case GTU:
2701 case LE: case LT: case LEU: case LTU:
2703 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2704 rtx new1 = XEXP (x, 1)
2705 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2707 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2708 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2713 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2716 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2717 if (new_rtx != XEXP (x, 0))
2719 /* If this is a REG_DEAD note, it is not valid anymore.
2720 Using the eliminated version could result in creating a
2721 REG_DEAD note for the stack or frame pointer. */
2722 if (REG_NOTE_KIND (x) == REG_DEAD)
2724 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2727 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2731 /* ... fall through ... */
2734 /* Now do eliminations in the rest of the chain. If this was
2735 an EXPR_LIST, this might result in allocating more memory than is
2736 strictly needed, but it simplifies the code. */
2739 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2740 if (new_rtx != XEXP (x, 1))
2742 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2750 /* We do not support elimination of a register that is modified.
2751 elimination_effects has already make sure that this does not
2757 /* We do not support elimination of a register that is modified.
2758 elimination_effects has already make sure that this does not
2759 happen. The only remaining case we need to consider here is
2760 that the increment value may be an eliminable register. */
2761 if (GET_CODE (XEXP (x, 1)) == PLUS
2762 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2764 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2767 if (new_rtx != XEXP (XEXP (x, 1), 1))
2768 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2769 gen_rtx_PLUS (GET_MODE (x),
2770 XEXP (x, 0), new_rtx));
2774 case STRICT_LOW_PART:
2776 case SIGN_EXTEND: case ZERO_EXTEND:
2777 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2778 case FLOAT: case FIX:
2779 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2788 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2789 if (new_rtx != XEXP (x, 0))
2790 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2794 /* Similar to above processing, but preserve SUBREG_BYTE.
2795 Convert (subreg (mem)) to (mem) if not paradoxical.
2796 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2797 pseudo didn't get a hard reg, we must replace this with the
2798 eliminated version of the memory location because push_reload
2799 may do the replacement in certain circumstances. */
2800 if (REG_P (SUBREG_REG (x))
2801 && (GET_MODE_SIZE (GET_MODE (x))
2802 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2803 && reg_equiv_memory_loc != 0
2804 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2806 new_rtx = SUBREG_REG (x);
2809 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2811 if (new_rtx != SUBREG_REG (x))
2813 int x_size = GET_MODE_SIZE (GET_MODE (x));
2814 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2817 && ((x_size < new_size
2818 #ifdef WORD_REGISTER_OPERATIONS
2819 /* On these machines, combine can create rtl of the form
2820 (set (subreg:m1 (reg:m2 R) 0) ...)
2821 where m1 < m2, and expects something interesting to
2822 happen to the entire word. Moreover, it will use the
2823 (reg:m2 R) later, expecting all bits to be preserved.
2824 So if the number of words is the same, preserve the
2825 subreg so that push_reload can see it. */
2826 && ! ((x_size - 1) / UNITS_PER_WORD
2827 == (new_size -1 ) / UNITS_PER_WORD)
2830 || x_size == new_size)
2832 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2834 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2840 /* Our only special processing is to pass the mode of the MEM to our
2841 recursive call and copy the flags. While we are here, handle this
2842 case more efficiently. */
2844 replace_equiv_address_nv (x,
2845 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2849 /* Handle insn_list USE that a call to a pure function may generate. */
2850 new_rtx = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2851 if (new_rtx != XEXP (x, 0))
2852 return gen_rtx_USE (GET_MODE (x), new_rtx);
2864 /* Process each of our operands recursively. If any have changed, make a
2866 fmt = GET_RTX_FORMAT (code);
2867 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2871 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2872 if (new_rtx != XEXP (x, i) && ! copied)
2874 x = shallow_copy_rtx (x);
2877 XEXP (x, i) = new_rtx;
2879 else if (*fmt == 'E')
2882 for (j = 0; j < XVECLEN (x, i); j++)
2884 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2885 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2887 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2891 x = shallow_copy_rtx (x);
2894 XVEC (x, i) = new_v;
2897 XVECEXP (x, i, j) = new_rtx;
2906 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2908 return eliminate_regs_1 (x, mem_mode, insn, false);
2911 /* Scan rtx X for modifications of elimination target registers. Update
2912 the table of eliminables to reflect the changed state. MEM_MODE is
2913 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2916 elimination_effects (rtx x, enum machine_mode mem_mode)
2918 enum rtx_code code = GET_CODE (x);
2919 struct elim_table *ep;
2944 /* First handle the case where we encounter a bare register that
2945 is eliminable. Replace it with a PLUS. */
2946 if (regno < FIRST_PSEUDO_REGISTER)
2948 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2950 if (ep->from_rtx == x && ep->can_eliminate)
2953 ep->ref_outside_mem = 1;
2958 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2959 && reg_equiv_constant[regno]
2960 && ! function_invariant_p (reg_equiv_constant[regno]))
2961 elimination_effects (reg_equiv_constant[regno], mem_mode);
2970 /* If we modify the source of an elimination rule, disable it. */
2971 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2972 if (ep->from_rtx == XEXP (x, 0))
2973 ep->can_eliminate = 0;
2975 /* If we modify the target of an elimination rule by adding a constant,
2976 update its offset. If we modify the target in any other way, we'll
2977 have to disable the rule as well. */
2978 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2979 if (ep->to_rtx == XEXP (x, 0))
2981 int size = GET_MODE_SIZE (mem_mode);
2983 /* If more bytes than MEM_MODE are pushed, account for them. */
2984 #ifdef PUSH_ROUNDING
2985 if (ep->to_rtx == stack_pointer_rtx)
2986 size = PUSH_ROUNDING (size);
2988 if (code == PRE_DEC || code == POST_DEC)
2990 else if (code == PRE_INC || code == POST_INC)
2992 else if (code == PRE_MODIFY || code == POST_MODIFY)
2994 if (GET_CODE (XEXP (x, 1)) == PLUS
2995 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2996 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2997 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2999 ep->can_eliminate = 0;
3003 /* These two aren't unary operators. */
3004 if (code == POST_MODIFY || code == PRE_MODIFY)
3007 /* Fall through to generic unary operation case. */
3008 case STRICT_LOW_PART:
3010 case SIGN_EXTEND: case ZERO_EXTEND:
3011 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3012 case FLOAT: case FIX:
3013 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3022 elimination_effects (XEXP (x, 0), mem_mode);
3026 if (REG_P (SUBREG_REG (x))
3027 && (GET_MODE_SIZE (GET_MODE (x))
3028 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3029 && reg_equiv_memory_loc != 0
3030 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3033 elimination_effects (SUBREG_REG (x), mem_mode);
3037 /* If using a register that is the source of an eliminate we still
3038 think can be performed, note it cannot be performed since we don't
3039 know how this register is used. */
3040 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3041 if (ep->from_rtx == XEXP (x, 0))
3042 ep->can_eliminate = 0;
3044 elimination_effects (XEXP (x, 0), mem_mode);
3048 /* If clobbering a register that is the replacement register for an
3049 elimination we still think can be performed, note that it cannot
3050 be performed. Otherwise, we need not be concerned about it. */
3051 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3052 if (ep->to_rtx == XEXP (x, 0))
3053 ep->can_eliminate = 0;
3055 elimination_effects (XEXP (x, 0), mem_mode);
3059 /* Check for setting a register that we know about. */
3060 if (REG_P (SET_DEST (x)))
3062 /* See if this is setting the replacement register for an
3065 If DEST is the hard frame pointer, we do nothing because we
3066 assume that all assignments to the frame pointer are for
3067 non-local gotos and are being done at a time when they are valid
3068 and do not disturb anything else. Some machines want to
3069 eliminate a fake argument pointer (or even a fake frame pointer)
3070 with either the real frame or the stack pointer. Assignments to
3071 the hard frame pointer must not prevent this elimination. */
3073 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3075 if (ep->to_rtx == SET_DEST (x)
3076 && SET_DEST (x) != hard_frame_pointer_rtx)
3078 /* If it is being incremented, adjust the offset. Otherwise,
3079 this elimination can't be done. */
3080 rtx src = SET_SRC (x);
3082 if (GET_CODE (src) == PLUS
3083 && XEXP (src, 0) == SET_DEST (x)
3084 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3085 ep->offset -= INTVAL (XEXP (src, 1));
3087 ep->can_eliminate = 0;
3091 elimination_effects (SET_DEST (x), 0);
3092 elimination_effects (SET_SRC (x), 0);
3096 /* Our only special processing is to pass the mode of the MEM to our
3098 elimination_effects (XEXP (x, 0), GET_MODE (x));
3105 fmt = GET_RTX_FORMAT (code);
3106 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3109 elimination_effects (XEXP (x, i), mem_mode);
3110 else if (*fmt == 'E')
3111 for (j = 0; j < XVECLEN (x, i); j++)
3112 elimination_effects (XVECEXP (x, i, j), mem_mode);
3116 /* Descend through rtx X and verify that no references to eliminable registers
3117 remain. If any do remain, mark the involved register as not
3121 check_eliminable_occurrences (rtx x)
3130 code = GET_CODE (x);
3132 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3134 struct elim_table *ep;
3136 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3137 if (ep->from_rtx == x)
3138 ep->can_eliminate = 0;
3142 fmt = GET_RTX_FORMAT (code);
3143 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3146 check_eliminable_occurrences (XEXP (x, i));
3147 else if (*fmt == 'E')
3150 for (j = 0; j < XVECLEN (x, i); j++)
3151 check_eliminable_occurrences (XVECEXP (x, i, j));
3156 /* Scan INSN and eliminate all eliminable registers in it.
3158 If REPLACE is nonzero, do the replacement destructively. Also
3159 delete the insn as dead it if it is setting an eliminable register.
3161 If REPLACE is zero, do all our allocations in reload_obstack.
3163 If no eliminations were done and this insn doesn't require any elimination
3164 processing (these are not identical conditions: it might be updating sp,
3165 but not referencing fp; this needs to be seen during reload_as_needed so
3166 that the offset between fp and sp can be taken into consideration), zero
3167 is returned. Otherwise, 1 is returned. */
3170 eliminate_regs_in_insn (rtx insn, int replace)
3172 int icode = recog_memoized (insn);
3173 rtx old_body = PATTERN (insn);
3174 int insn_is_asm = asm_noperands (old_body) >= 0;
3175 rtx old_set = single_set (insn);
3179 rtx substed_operand[MAX_RECOG_OPERANDS];
3180 rtx orig_operand[MAX_RECOG_OPERANDS];
3181 struct elim_table *ep;
3182 rtx plus_src, plus_cst_src;
3184 if (! insn_is_asm && icode < 0)
3186 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3187 || GET_CODE (PATTERN (insn)) == CLOBBER
3188 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3189 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3190 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3194 if (old_set != 0 && REG_P (SET_DEST (old_set))
3195 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3197 /* Check for setting an eliminable register. */
3198 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3199 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3201 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3202 /* If this is setting the frame pointer register to the
3203 hardware frame pointer register and this is an elimination
3204 that will be done (tested above), this insn is really
3205 adjusting the frame pointer downward to compensate for
3206 the adjustment done before a nonlocal goto. */
3207 if (ep->from == FRAME_POINTER_REGNUM
3208 && ep->to == HARD_FRAME_POINTER_REGNUM)
3210 rtx base = SET_SRC (old_set);
3211 rtx base_insn = insn;
3212 HOST_WIDE_INT offset = 0;
3214 while (base != ep->to_rtx)
3216 rtx prev_insn, prev_set;
3218 if (GET_CODE (base) == PLUS
3219 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3221 offset += INTVAL (XEXP (base, 1));
3222 base = XEXP (base, 0);
3224 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3225 && (prev_set = single_set (prev_insn)) != 0
3226 && rtx_equal_p (SET_DEST (prev_set), base))
3228 base = SET_SRC (prev_set);
3229 base_insn = prev_insn;
3235 if (base == ep->to_rtx)
3238 = plus_constant (ep->to_rtx, offset - ep->offset);
3240 new_body = old_body;
3243 new_body = copy_insn (old_body);
3244 if (REG_NOTES (insn))
3245 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3247 PATTERN (insn) = new_body;
3248 old_set = single_set (insn);
3250 /* First see if this insn remains valid when we
3251 make the change. If not, keep the INSN_CODE
3252 the same and let reload fit it up. */
3253 validate_change (insn, &SET_SRC (old_set), src, 1);
3254 validate_change (insn, &SET_DEST (old_set),
3256 if (! apply_change_group ())
3258 SET_SRC (old_set) = src;
3259 SET_DEST (old_set) = ep->to_rtx;
3268 /* In this case this insn isn't serving a useful purpose. We
3269 will delete it in reload_as_needed once we know that this
3270 elimination is, in fact, being done.
3272 If REPLACE isn't set, we can't delete this insn, but needn't
3273 process it since it won't be used unless something changes. */
3276 delete_dead_insn (insn);
3284 /* We allow one special case which happens to work on all machines we
3285 currently support: a single set with the source or a REG_EQUAL
3286 note being a PLUS of an eliminable register and a constant. */
3287 plus_src = plus_cst_src = 0;
3288 if (old_set && REG_P (SET_DEST (old_set)))
3290 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3291 plus_src = SET_SRC (old_set);
3292 /* First see if the source is of the form (plus (...) CST). */
3294 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3295 plus_cst_src = plus_src;
3296 else if (REG_P (SET_SRC (old_set))
3299 /* Otherwise, see if we have a REG_EQUAL note of the form
3300 (plus (...) CST). */
3302 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3304 if ((REG_NOTE_KIND (links) == REG_EQUAL
3305 || REG_NOTE_KIND (links) == REG_EQUIV)
3306 && GET_CODE (XEXP (links, 0)) == PLUS
3307 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3309 plus_cst_src = XEXP (links, 0);
3315 /* Check that the first operand of the PLUS is a hard reg or
3316 the lowpart subreg of one. */
3319 rtx reg = XEXP (plus_cst_src, 0);
3320 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3321 reg = SUBREG_REG (reg);
3323 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3329 rtx reg = XEXP (plus_cst_src, 0);
3330 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3332 if (GET_CODE (reg) == SUBREG)
3333 reg = SUBREG_REG (reg);
3335 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3336 if (ep->from_rtx == reg && ep->can_eliminate)
3338 rtx to_rtx = ep->to_rtx;
3339 offset += ep->offset;
3340 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3342 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3343 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3345 /* If we have a nonzero offset, and the source is already
3346 a simple REG, the following transformation would
3347 increase the cost of the insn by replacing a simple REG
3348 with (plus (reg sp) CST). So try only when we already
3349 had a PLUS before. */
3350 if (offset == 0 || plus_src)
3352 rtx new_src = plus_constant (to_rtx, offset);
3354 new_body = old_body;
3357 new_body = copy_insn (old_body);
3358 if (REG_NOTES (insn))
3359 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3361 PATTERN (insn) = new_body;
3362 old_set = single_set (insn);
3364 /* First see if this insn remains valid when we make the
3365 change. If not, try to replace the whole pattern with
3366 a simple set (this may help if the original insn was a
3367 PARALLEL that was only recognized as single_set due to
3368 REG_UNUSED notes). If this isn't valid either, keep
3369 the INSN_CODE the same and let reload fix it up. */
3370 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3372 rtx new_pat = gen_rtx_SET (VOIDmode,
3373 SET_DEST (old_set), new_src);
3375 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3376 SET_SRC (old_set) = new_src;
3383 /* This can't have an effect on elimination offsets, so skip right
3389 /* Determine the effects of this insn on elimination offsets. */
3390 elimination_effects (old_body, 0);
3392 /* Eliminate all eliminable registers occurring in operands that
3393 can be handled by reload. */
3394 extract_insn (insn);
3395 for (i = 0; i < recog_data.n_operands; i++)
3397 orig_operand[i] = recog_data.operand[i];
3398 substed_operand[i] = recog_data.operand[i];
3400 /* For an asm statement, every operand is eliminable. */
3401 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3403 bool is_set_src, in_plus;
3405 /* Check for setting a register that we know about. */
3406 if (recog_data.operand_type[i] != OP_IN
3407 && REG_P (orig_operand[i]))
3409 /* If we are assigning to a register that can be eliminated, it
3410 must be as part of a PARALLEL, since the code above handles
3411 single SETs. We must indicate that we can no longer
3412 eliminate this reg. */
3413 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3415 if (ep->from_rtx == orig_operand[i])
3416 ep->can_eliminate = 0;
3419 /* Companion to the above plus substitution, we can allow
3420 invariants as the source of a plain move. */
3422 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3426 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3427 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3431 = eliminate_regs_1 (recog_data.operand[i], 0,
3432 replace ? insn : NULL_RTX,
3433 is_set_src || in_plus);
3434 if (substed_operand[i] != orig_operand[i])
3436 /* Terminate the search in check_eliminable_occurrences at
3438 *recog_data.operand_loc[i] = 0;
3440 /* If an output operand changed from a REG to a MEM and INSN is an
3441 insn, write a CLOBBER insn. */
3442 if (recog_data.operand_type[i] != OP_IN
3443 && REG_P (orig_operand[i])
3444 && MEM_P (substed_operand[i])
3446 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3450 for (i = 0; i < recog_data.n_dups; i++)
3451 *recog_data.dup_loc[i]
3452 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3454 /* If any eliminable remain, they aren't eliminable anymore. */
3455 check_eliminable_occurrences (old_body);
3457 /* Substitute the operands; the new values are in the substed_operand
3459 for (i = 0; i < recog_data.n_operands; i++)
3460 *recog_data.operand_loc[i] = substed_operand[i];
3461 for (i = 0; i < recog_data.n_dups; i++)
3462 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3464 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3465 re-recognize the insn. We do this in case we had a simple addition
3466 but now can do this as a load-address. This saves an insn in this
3468 If re-recognition fails, the old insn code number will still be used,
3469 and some register operands may have changed into PLUS expressions.
3470 These will be handled by find_reloads by loading them into a register
3475 /* If we aren't replacing things permanently and we changed something,
3476 make another copy to ensure that all the RTL is new. Otherwise
3477 things can go wrong if find_reload swaps commutative operands
3478 and one is inside RTL that has been copied while the other is not. */
3479 new_body = old_body;
3482 new_body = copy_insn (old_body);
3483 if (REG_NOTES (insn))
3484 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3486 PATTERN (insn) = new_body;
3488 /* If we had a move insn but now we don't, rerecognize it. This will
3489 cause spurious re-recognition if the old move had a PARALLEL since
3490 the new one still will, but we can't call single_set without
3491 having put NEW_BODY into the insn and the re-recognition won't
3492 hurt in this rare case. */
3493 /* ??? Why this huge if statement - why don't we just rerecognize the
3497 && ((REG_P (SET_SRC (old_set))
3498 && (GET_CODE (new_body) != SET
3499 || !REG_P (SET_SRC (new_body))))
3500 /* If this was a load from or store to memory, compare
3501 the MEM in recog_data.operand to the one in the insn.
3502 If they are not equal, then rerecognize the insn. */
3504 && ((MEM_P (SET_SRC (old_set))
3505 && SET_SRC (old_set) != recog_data.operand[1])
3506 || (MEM_P (SET_DEST (old_set))
3507 && SET_DEST (old_set) != recog_data.operand[0])))
3508 /* If this was an add insn before, rerecognize. */
3509 || GET_CODE (SET_SRC (old_set)) == PLUS))
3511 int new_icode = recog (PATTERN (insn), insn, 0);
3513 INSN_CODE (insn) = new_icode;
3517 /* Restore the old body. If there were any changes to it, we made a copy
3518 of it while the changes were still in place, so we'll correctly return
3519 a modified insn below. */
3522 /* Restore the old body. */
3523 for (i = 0; i < recog_data.n_operands; i++)
3524 *recog_data.operand_loc[i] = orig_operand[i];
3525 for (i = 0; i < recog_data.n_dups; i++)
3526 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3529 /* Update all elimination pairs to reflect the status after the current
3530 insn. The changes we make were determined by the earlier call to
3531 elimination_effects.
3533 We also detect cases where register elimination cannot be done,
3534 namely, if a register would be both changed and referenced outside a MEM
3535 in the resulting insn since such an insn is often undefined and, even if
3536 not, we cannot know what meaning will be given to it. Note that it is
3537 valid to have a register used in an address in an insn that changes it
3538 (presumably with a pre- or post-increment or decrement).
3540 If anything changes, return nonzero. */
3542 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3544 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3545 ep->can_eliminate = 0;
3547 ep->ref_outside_mem = 0;
3549 if (ep->previous_offset != ep->offset)
3554 /* If we changed something, perform elimination in REG_NOTES. This is
3555 needed even when REPLACE is zero because a REG_DEAD note might refer
3556 to a register that we eliminate and could cause a different number
3557 of spill registers to be needed in the final reload pass than in
3559 if (val && REG_NOTES (insn) != 0)
3561 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3566 /* Loop through all elimination pairs.
3567 Recalculate the number not at initial offset.
3569 Compute the maximum offset (minimum offset if the stack does not
3570 grow downward) for each elimination pair. */
3573 update_eliminable_offsets (void)
3575 struct elim_table *ep;
3577 num_not_at_initial_offset = 0;
3578 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3580 ep->previous_offset = ep->offset;
3581 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3582 num_not_at_initial_offset++;
3586 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3587 replacement we currently believe is valid, mark it as not eliminable if X
3588 modifies DEST in any way other than by adding a constant integer to it.
3590 If DEST is the frame pointer, we do nothing because we assume that
3591 all assignments to the hard frame pointer are nonlocal gotos and are being
3592 done at a time when they are valid and do not disturb anything else.
3593 Some machines want to eliminate a fake argument pointer with either the
3594 frame or stack pointer. Assignments to the hard frame pointer must not
3595 prevent this elimination.
3597 Called via note_stores from reload before starting its passes to scan
3598 the insns of the function. */
3601 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3605 /* A SUBREG of a hard register here is just changing its mode. We should
3606 not see a SUBREG of an eliminable hard register, but check just in
3608 if (GET_CODE (dest) == SUBREG)
3609 dest = SUBREG_REG (dest);
3611 if (dest == hard_frame_pointer_rtx)
3614 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3615 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3616 && (GET_CODE (x) != SET
3617 || GET_CODE (SET_SRC (x)) != PLUS
3618 || XEXP (SET_SRC (x), 0) != dest
3619 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3621 reg_eliminate[i].can_eliminate_previous
3622 = reg_eliminate[i].can_eliminate = 0;
3627 /* Verify that the initial elimination offsets did not change since the
3628 last call to set_initial_elim_offsets. This is used to catch cases
3629 where something illegal happened during reload_as_needed that could
3630 cause incorrect code to be generated if we did not check for it. */
3633 verify_initial_elim_offsets (void)
3637 if (!num_eliminable)
3640 #ifdef ELIMINABLE_REGS
3642 struct elim_table *ep;
3644 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3646 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3647 if (t != ep->initial_offset)
3652 INITIAL_FRAME_POINTER_OFFSET (t);
3653 if (t != reg_eliminate[0].initial_offset)
3660 /* Reset all offsets on eliminable registers to their initial values. */
3663 set_initial_elim_offsets (void)
3665 struct elim_table *ep = reg_eliminate;
3667 #ifdef ELIMINABLE_REGS
3668 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3670 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3671 ep->previous_offset = ep->offset = ep->initial_offset;
3674 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3675 ep->previous_offset = ep->offset = ep->initial_offset;
3678 num_not_at_initial_offset = 0;
3681 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3684 set_initial_eh_label_offset (rtx label)
3686 set_label_offsets (label, NULL_RTX, 1);
3689 /* Initialize the known label offsets.
3690 Set a known offset for each forced label to be at the initial offset
3691 of each elimination. We do this because we assume that all
3692 computed jumps occur from a location where each elimination is
3693 at its initial offset.
3694 For all other labels, show that we don't know the offsets. */
3697 set_initial_label_offsets (void)
3700 memset (offsets_known_at, 0, num_labels);
3702 for (x = forced_labels; x; x = XEXP (x, 1))
3704 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3706 for_each_eh_label (set_initial_eh_label_offset);
3709 /* Set all elimination offsets to the known values for the code label given
3713 set_offsets_for_label (rtx insn)
3716 int label_nr = CODE_LABEL_NUMBER (insn);
3717 struct elim_table *ep;
3719 num_not_at_initial_offset = 0;
3720 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3722 ep->offset = ep->previous_offset
3723 = offsets_at[label_nr - first_label_num][i];
3724 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3725 num_not_at_initial_offset++;
3729 /* See if anything that happened changes which eliminations are valid.
3730 For example, on the SPARC, whether or not the frame pointer can
3731 be eliminated can depend on what registers have been used. We need
3732 not check some conditions again (such as flag_omit_frame_pointer)
3733 since they can't have changed. */
3736 update_eliminables (HARD_REG_SET *pset)
3738 int previous_frame_pointer_needed = frame_pointer_needed;
3739 struct elim_table *ep;
3741 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3742 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3743 #ifdef ELIMINABLE_REGS
3744 || ! CAN_ELIMINATE (ep->from, ep->to)
3747 ep->can_eliminate = 0;
3749 /* Look for the case where we have discovered that we can't replace
3750 register A with register B and that means that we will now be
3751 trying to replace register A with register C. This means we can
3752 no longer replace register C with register B and we need to disable
3753 such an elimination, if it exists. This occurs often with A == ap,
3754 B == sp, and C == fp. */
3756 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3758 struct elim_table *op;
3761 if (! ep->can_eliminate && ep->can_eliminate_previous)
3763 /* Find the current elimination for ep->from, if there is a
3765 for (op = reg_eliminate;
3766 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3767 if (op->from == ep->from && op->can_eliminate)
3773 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3775 for (op = reg_eliminate;
3776 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3777 if (op->from == new_to && op->to == ep->to)
3778 op->can_eliminate = 0;
3782 /* See if any registers that we thought we could eliminate the previous
3783 time are no longer eliminable. If so, something has changed and we
3784 must spill the register. Also, recompute the number of eliminable
3785 registers and see if the frame pointer is needed; it is if there is
3786 no elimination of the frame pointer that we can perform. */
3788 frame_pointer_needed = 1;
3789 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3791 if (ep->can_eliminate
3792 && ep->from == FRAME_POINTER_REGNUM
3793 && ep->to != HARD_FRAME_POINTER_REGNUM
3794 && (! SUPPORTS_STACK_ALIGNMENT
3795 || ! crtl->stack_realign_needed))
3796 frame_pointer_needed = 0;
3798 if (! ep->can_eliminate && ep->can_eliminate_previous)
3800 ep->can_eliminate_previous = 0;
3801 SET_HARD_REG_BIT (*pset, ep->from);
3806 /* If we didn't need a frame pointer last time, but we do now, spill
3807 the hard frame pointer. */
3808 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3809 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3812 /* Return true if X is used as the target register of an elimination. */
3815 elimination_target_reg_p (rtx x)
3817 struct elim_table *ep;
3819 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3820 if (ep->to_rtx == x && ep->can_eliminate)
3826 /* Initialize the table of registers to eliminate.
3827 Pre-condition: global flag frame_pointer_needed has been set before
3828 calling this function. */
3831 init_elim_table (void)
3833 struct elim_table *ep;
3834 #ifdef ELIMINABLE_REGS
3835 const struct elim_table_1 *ep1;
3839 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3843 #ifdef ELIMINABLE_REGS
3844 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3845 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3847 ep->from = ep1->from;
3849 ep->can_eliminate = ep->can_eliminate_previous
3850 = (CAN_ELIMINATE (ep->from, ep->to)
3851 && ! (ep->to == STACK_POINTER_REGNUM
3852 && frame_pointer_needed
3853 && (! SUPPORTS_STACK_ALIGNMENT
3854 || ! stack_realign_fp)));
3857 reg_eliminate[0].from = reg_eliminate_1[0].from;
3858 reg_eliminate[0].to = reg_eliminate_1[0].to;
3859 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3860 = ! frame_pointer_needed;
3863 /* Count the number of eliminable registers and build the FROM and TO
3864 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3865 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3866 We depend on this. */
3867 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3869 num_eliminable += ep->can_eliminate;
3870 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3871 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3875 /* Kick all pseudos out of hard register REGNO.
3877 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3878 because we found we can't eliminate some register. In the case, no pseudos
3879 are allowed to be in the register, even if they are only in a block that
3880 doesn't require spill registers, unlike the case when we are spilling this
3881 hard reg to produce another spill register.
3883 Return nonzero if any pseudos needed to be kicked out. */
3886 spill_hard_reg (unsigned int regno, int cant_eliminate)
3892 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3893 df_set_regs_ever_live (regno, true);
3896 /* Spill every pseudo reg that was allocated to this reg
3897 or to something that overlaps this reg. */
3899 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3900 if (reg_renumber[i] >= 0
3901 && (unsigned int) reg_renumber[i] <= regno
3902 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3903 SET_REGNO_REG_SET (&spilled_pseudos, i);
3906 /* After find_reload_regs has been run for all insn that need reloads,
3907 and/or spill_hard_regs was called, this function is used to actually
3908 spill pseudo registers and try to reallocate them. It also sets up the
3909 spill_regs array for use by choose_reload_regs. */
3912 finish_spills (int global)
3914 struct insn_chain *chain;
3915 int something_changed = 0;
3917 reg_set_iterator rsi;
3919 /* Build the spill_regs array for the function. */
3920 /* If there are some registers still to eliminate and one of the spill regs
3921 wasn't ever used before, additional stack space may have to be
3922 allocated to store this register. Thus, we may have changed the offset
3923 between the stack and frame pointers, so mark that something has changed.
3925 One might think that we need only set VAL to 1 if this is a call-used
3926 register. However, the set of registers that must be saved by the
3927 prologue is not identical to the call-used set. For example, the
3928 register used by the call insn for the return PC is a call-used register,
3929 but must be saved by the prologue. */
3932 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3933 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3935 spill_reg_order[i] = n_spills;
3936 spill_regs[n_spills++] = i;
3937 if (num_eliminable && ! df_regs_ever_live_p (i))
3938 something_changed = 1;
3939 df_set_regs_ever_live (i, true);
3942 spill_reg_order[i] = -1;
3944 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3945 if (! flag_ira || ! optimize || reg_renumber[i] >= 0)
3947 /* Record the current hard register the pseudo is allocated to
3948 in pseudo_previous_regs so we avoid reallocating it to the
3949 same hard reg in a later pass. */
3950 gcc_assert (reg_renumber[i] >= 0);
3952 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3953 /* Mark it as no longer having a hard register home. */
3954 reg_renumber[i] = -1;
3955 if (flag_ira && optimize)
3956 /* Inform IRA about the change. */
3957 ira_mark_allocation_change (i);
3958 /* We will need to scan everything again. */
3959 something_changed = 1;
3962 /* Retry global register allocation if possible. */
3965 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3966 /* For every insn that needs reloads, set the registers used as spill
3967 regs in pseudo_forbidden_regs for every pseudo live across the
3969 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3971 EXECUTE_IF_SET_IN_REG_SET
3972 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3974 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3975 chain->used_spill_regs);
3977 EXECUTE_IF_SET_IN_REG_SET
3978 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3980 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3981 chain->used_spill_regs);
3985 if (! flag_ira || ! optimize)
3987 /* Retry allocating the spilled pseudos. For each reg,
3988 merge the various reg sets that indicate which hard regs
3989 can't be used, and call retry_global_alloc. We change
3990 spill_pseudos here to only contain pseudos that did not
3991 get a new hard register. */
3992 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3993 if (reg_old_renumber[i] != reg_renumber[i])
3995 HARD_REG_SET forbidden;
3997 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3998 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3999 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
4000 retry_global_alloc (i, forbidden);
4001 if (reg_renumber[i] >= 0)
4002 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4007 /* Retry allocating the pseudos spilled in IRA and the
4008 reload. For each reg, merge the various reg sets that
4009 indicate which hard regs can't be used, and call
4010 ira_reassign_pseudos. */
4013 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4014 if (reg_old_renumber[i] != reg_renumber[i])
4016 if (reg_renumber[i] < 0)
4017 temp_pseudo_reg_arr[n++] = i;
4019 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4021 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4022 bad_spill_regs_global,
4023 pseudo_forbidden_regs, pseudo_previous_regs,
4025 something_changed = 1;
4029 /* Fix up the register information in the insn chain.
4030 This involves deleting those of the spilled pseudos which did not get
4031 a new hard register home from the live_{before,after} sets. */
4032 for (chain = reload_insn_chain; chain; chain = chain->next)
4034 HARD_REG_SET used_by_pseudos;
4035 HARD_REG_SET used_by_pseudos2;
4037 if (! flag_ira || ! optimize)
4039 /* Don't do it for IRA because IRA and the reload still can
4040 assign hard registers to the spilled pseudos on next
4041 reload iterations. */
4042 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4043 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4045 /* Mark any unallocated hard regs as available for spills. That
4046 makes inheritance work somewhat better. */
4047 if (chain->need_reload)
4049 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4050 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4051 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4053 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4054 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4055 /* Value of chain->used_spill_regs from previous iteration
4056 may be not included in the value calculated here because
4057 of possible removing caller-saves insns (see function
4058 delete_caller_save_insns. */
4059 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4060 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4064 CLEAR_REG_SET (&changed_allocation_pseudos);
4065 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4066 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4068 int regno = reg_renumber[i];
4069 if (reg_old_renumber[i] == regno)
4072 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4074 alter_reg (i, reg_old_renumber[i], false);
4075 reg_old_renumber[i] = regno;
4079 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4081 fprintf (dump_file, " Register %d now in %d.\n\n",
4082 i, reg_renumber[i]);
4086 return something_changed;
4089 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4092 scan_paradoxical_subregs (rtx x)
4096 enum rtx_code code = GET_CODE (x);
4107 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4115 if (REG_P (SUBREG_REG (x))
4116 && (GET_MODE_SIZE (GET_MODE (x))
4117 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4119 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4120 = GET_MODE_SIZE (GET_MODE (x));
4121 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4129 fmt = GET_RTX_FORMAT (code);
4130 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4133 scan_paradoxical_subregs (XEXP (x, i));
4134 else if (fmt[i] == 'E')
4137 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4138 scan_paradoxical_subregs (XVECEXP (x, i, j));
4143 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4144 examine all of the reload insns between PREV and NEXT exclusive, and
4145 annotate all that may trap. */
4148 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4150 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4151 unsigned int trap_count;
4157 if (may_trap_p (PATTERN (insn)))
4161 remove_note (insn, note);
4165 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4166 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4169 add_reg_note (i, REG_EH_REGION, XEXP (note, 0));
4173 /* Reload pseudo-registers into hard regs around each insn as needed.
4174 Additional register load insns are output before the insn that needs it
4175 and perhaps store insns after insns that modify the reloaded pseudo reg.
4177 reg_last_reload_reg and reg_reloaded_contents keep track of
4178 which registers are already available in reload registers.
4179 We update these for the reloads that we perform,
4180 as the insns are scanned. */
4183 reload_as_needed (int live_known)
4185 struct insn_chain *chain;
4186 #if defined (AUTO_INC_DEC)
4191 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4192 memset (spill_reg_store, 0, sizeof spill_reg_store);
4193 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4194 INIT_REG_SET (®_has_output_reload);
4195 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4196 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4198 set_initial_elim_offsets ();
4200 for (chain = reload_insn_chain; chain; chain = chain->next)
4203 rtx insn = chain->insn;
4204 rtx old_next = NEXT_INSN (insn);
4206 /* If we pass a label, copy the offsets from the label information
4207 into the current offsets of each elimination. */
4209 set_offsets_for_label (insn);
4211 else if (INSN_P (insn))
4213 regset_head regs_to_forget;
4214 INIT_REG_SET (®s_to_forget);
4215 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4217 /* If this is a USE and CLOBBER of a MEM, ensure that any
4218 references to eliminable registers have been removed. */
4220 if ((GET_CODE (PATTERN (insn)) == USE
4221 || GET_CODE (PATTERN (insn)) == CLOBBER)
4222 && MEM_P (XEXP (PATTERN (insn), 0)))
4223 XEXP (XEXP (PATTERN (insn), 0), 0)
4224 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4225 GET_MODE (XEXP (PATTERN (insn), 0)),
4228 /* If we need to do register elimination processing, do so.
4229 This might delete the insn, in which case we are done. */
4230 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4232 eliminate_regs_in_insn (insn, 1);
4235 update_eliminable_offsets ();
4236 CLEAR_REG_SET (®s_to_forget);
4241 /* If need_elim is nonzero but need_reload is zero, one might think
4242 that we could simply set n_reloads to 0. However, find_reloads
4243 could have done some manipulation of the insn (such as swapping
4244 commutative operands), and these manipulations are lost during
4245 the first pass for every insn that needs register elimination.
4246 So the actions of find_reloads must be redone here. */
4248 if (! chain->need_elim && ! chain->need_reload
4249 && ! chain->need_operand_change)
4251 /* First find the pseudo regs that must be reloaded for this insn.
4252 This info is returned in the tables reload_... (see reload.h).
4253 Also modify the body of INSN by substituting RELOAD
4254 rtx's for those pseudo regs. */
4257 CLEAR_REG_SET (®_has_output_reload);
4258 CLEAR_HARD_REG_SET (reg_is_output_reload);
4260 find_reloads (insn, 1, spill_indirect_levels, live_known,
4266 rtx next = NEXT_INSN (insn);
4269 prev = PREV_INSN (insn);
4271 /* Now compute which reload regs to reload them into. Perhaps
4272 reusing reload regs from previous insns, or else output
4273 load insns to reload them. Maybe output store insns too.
4274 Record the choices of reload reg in reload_reg_rtx. */
4275 choose_reload_regs (chain);
4277 /* Merge any reloads that we didn't combine for fear of
4278 increasing the number of spill registers needed but now
4279 discover can be safely merged. */
4280 if (SMALL_REGISTER_CLASSES)
4281 merge_assigned_reloads (insn);
4283 /* Generate the insns to reload operands into or out of
4284 their reload regs. */
4285 emit_reload_insns (chain);
4287 /* Substitute the chosen reload regs from reload_reg_rtx
4288 into the insn's body (or perhaps into the bodies of other
4289 load and store insn that we just made for reloading
4290 and that we moved the structure into). */
4291 subst_reloads (insn);
4293 /* Adjust the exception region notes for loads and stores. */
4294 if (flag_non_call_exceptions && !CALL_P (insn))
4295 fixup_eh_region_note (insn, prev, next);
4297 /* If this was an ASM, make sure that all the reload insns
4298 we have generated are valid. If not, give an error
4300 if (asm_noperands (PATTERN (insn)) >= 0)
4301 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4302 if (p != insn && INSN_P (p)
4303 && GET_CODE (PATTERN (p)) != USE
4304 && (recog_memoized (p) < 0
4305 || (extract_insn (p), ! constrain_operands (1))))
4307 error_for_asm (insn,
4308 "%<asm%> operand requires "
4309 "impossible reload");
4314 if (num_eliminable && chain->need_elim)
4315 update_eliminable_offsets ();
4317 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4318 is no longer validly lying around to save a future reload.
4319 Note that this does not detect pseudos that were reloaded
4320 for this insn in order to be stored in
4321 (obeying register constraints). That is correct; such reload
4322 registers ARE still valid. */
4323 forget_marked_reloads (®s_to_forget);
4324 CLEAR_REG_SET (®s_to_forget);
4326 /* There may have been CLOBBER insns placed after INSN. So scan
4327 between INSN and NEXT and use them to forget old reloads. */
4328 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4329 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4330 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4333 /* Likewise for regs altered by auto-increment in this insn.
4334 REG_INC notes have been changed by reloading:
4335 find_reloads_address_1 records substitutions for them,
4336 which have been performed by subst_reloads above. */
4337 for (i = n_reloads - 1; i >= 0; i--)
4339 rtx in_reg = rld[i].in_reg;
4342 enum rtx_code code = GET_CODE (in_reg);
4343 /* PRE_INC / PRE_DEC will have the reload register ending up
4344 with the same value as the stack slot, but that doesn't
4345 hold true for POST_INC / POST_DEC. Either we have to
4346 convert the memory access to a true POST_INC / POST_DEC,
4347 or we can't use the reload register for inheritance. */
4348 if ((code == POST_INC || code == POST_DEC)
4349 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4350 REGNO (rld[i].reg_rtx))
4351 /* Make sure it is the inc/dec pseudo, and not
4352 some other (e.g. output operand) pseudo. */
4353 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4354 == REGNO (XEXP (in_reg, 0))))
4357 rtx reload_reg = rld[i].reg_rtx;
4358 enum machine_mode mode = GET_MODE (reload_reg);
4362 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4364 /* We really want to ignore REG_INC notes here, so
4365 use PATTERN (p) as argument to reg_set_p . */
4366 if (reg_set_p (reload_reg, PATTERN (p)))
4368 n = count_occurrences (PATTERN (p), reload_reg, 0);
4373 n = validate_replace_rtx (reload_reg,
4374 gen_rtx_fmt_e (code,
4379 /* We must also verify that the constraints
4380 are met after the replacement. */
4383 n = constrain_operands (1);
4387 /* If the constraints were not met, then
4388 undo the replacement. */
4391 validate_replace_rtx (gen_rtx_fmt_e (code,
4403 add_reg_note (p, REG_INC, reload_reg);
4404 /* Mark this as having an output reload so that the
4405 REG_INC processing code below won't invalidate
4406 the reload for inheritance. */
4407 SET_HARD_REG_BIT (reg_is_output_reload,
4408 REGNO (reload_reg));
4409 SET_REGNO_REG_SET (®_has_output_reload,
4410 REGNO (XEXP (in_reg, 0)));
4413 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4416 else if ((code == PRE_INC || code == PRE_DEC)
4417 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4418 REGNO (rld[i].reg_rtx))
4419 /* Make sure it is the inc/dec pseudo, and not
4420 some other (e.g. output operand) pseudo. */
4421 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4422 == REGNO (XEXP (in_reg, 0))))
4424 SET_HARD_REG_BIT (reg_is_output_reload,
4425 REGNO (rld[i].reg_rtx));
4426 SET_REGNO_REG_SET (®_has_output_reload,
4427 REGNO (XEXP (in_reg, 0)));
4431 /* If a pseudo that got a hard register is auto-incremented,
4432 we must purge records of copying it into pseudos without
4434 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4435 if (REG_NOTE_KIND (x) == REG_INC)
4437 /* See if this pseudo reg was reloaded in this insn.
4438 If so, its last-reload info is still valid
4439 because it is based on this insn's reload. */
4440 for (i = 0; i < n_reloads; i++)
4441 if (rld[i].out == XEXP (x, 0))
4445 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4449 /* A reload reg's contents are unknown after a label. */
4451 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4453 /* Don't assume a reload reg is still good after a call insn
4454 if it is a call-used reg, or if it contains a value that will
4455 be partially clobbered by the call. */
4456 else if (CALL_P (insn))
4458 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4459 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4464 free (reg_last_reload_reg);
4465 CLEAR_REG_SET (®_has_output_reload);
4468 /* Discard all record of any value reloaded from X,
4469 or reloaded in X from someplace else;
4470 unless X is an output reload reg of the current insn.
4472 X may be a hard reg (the reload reg)
4473 or it may be a pseudo reg that was reloaded from.
4475 When DATA is non-NULL just mark the registers in regset
4476 to be forgotten later. */
4479 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4484 regset regs = (regset) data;
4486 /* note_stores does give us subregs of hard regs,
4487 subreg_regno_offset requires a hard reg. */
4488 while (GET_CODE (x) == SUBREG)
4490 /* We ignore the subreg offset when calculating the regno,
4491 because we are using the entire underlying hard register
4501 if (regno >= FIRST_PSEUDO_REGISTER)
4507 nr = hard_regno_nregs[regno][GET_MODE (x)];
4508 /* Storing into a spilled-reg invalidates its contents.
4509 This can happen if a block-local pseudo is allocated to that reg
4510 and it wasn't spilled because this block's total need is 0.
4511 Then some insn might have an optional reload and use this reg. */
4513 for (i = 0; i < nr; i++)
4514 /* But don't do this if the reg actually serves as an output
4515 reload reg in the current instruction. */
4517 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4519 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4520 spill_reg_store[regno + i] = 0;
4526 SET_REGNO_REG_SET (regs, regno + nr);
4529 /* Since value of X has changed,
4530 forget any value previously copied from it. */
4533 /* But don't forget a copy if this is the output reload
4534 that establishes the copy's validity. */
4536 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4537 reg_last_reload_reg[regno + nr] = 0;
4541 /* Forget the reloads marked in regset by previous function. */
4543 forget_marked_reloads (regset regs)
4546 reg_set_iterator rsi;
4547 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4549 if (reg < FIRST_PSEUDO_REGISTER
4550 /* But don't do this if the reg actually serves as an output
4551 reload reg in the current instruction. */
4553 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4555 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4556 spill_reg_store[reg] = 0;
4559 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4560 reg_last_reload_reg[reg] = 0;
4564 /* The following HARD_REG_SETs indicate when each hard register is
4565 used for a reload of various parts of the current insn. */
4567 /* If reg is unavailable for all reloads. */
4568 static HARD_REG_SET reload_reg_unavailable;
4569 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4570 static HARD_REG_SET reload_reg_used;
4571 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4572 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4573 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4574 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4575 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4576 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4577 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4578 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4579 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4580 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4581 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4582 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4583 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4584 static HARD_REG_SET reload_reg_used_in_op_addr;
4585 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4586 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4587 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4588 static HARD_REG_SET reload_reg_used_in_insn;
4589 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4590 static HARD_REG_SET reload_reg_used_in_other_addr;
4592 /* If reg is in use as a reload reg for any sort of reload. */
4593 static HARD_REG_SET reload_reg_used_at_all;
4595 /* If reg is use as an inherited reload. We just mark the first register
4597 static HARD_REG_SET reload_reg_used_for_inherit;
4599 /* Records which hard regs are used in any way, either as explicit use or
4600 by being allocated to a pseudo during any point of the current insn. */
4601 static HARD_REG_SET reg_used_in_insn;
4603 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4604 TYPE. MODE is used to indicate how many consecutive regs are
4608 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4609 enum machine_mode mode)
4611 unsigned int nregs = hard_regno_nregs[regno][mode];
4614 for (i = regno; i < nregs + regno; i++)
4619 SET_HARD_REG_BIT (reload_reg_used, i);
4622 case RELOAD_FOR_INPUT_ADDRESS:
4623 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4626 case RELOAD_FOR_INPADDR_ADDRESS:
4627 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4630 case RELOAD_FOR_OUTPUT_ADDRESS:
4631 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4634 case RELOAD_FOR_OUTADDR_ADDRESS:
4635 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4638 case RELOAD_FOR_OPERAND_ADDRESS:
4639 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4642 case RELOAD_FOR_OPADDR_ADDR:
4643 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4646 case RELOAD_FOR_OTHER_ADDRESS:
4647 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4650 case RELOAD_FOR_INPUT:
4651 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4654 case RELOAD_FOR_OUTPUT:
4655 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4658 case RELOAD_FOR_INSN:
4659 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4663 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4667 /* Similarly, but show REGNO is no longer in use for a reload. */
4670 clear_reload_reg_in_use (unsigned int regno, int opnum,
4671 enum reload_type type, enum machine_mode mode)
4673 unsigned int nregs = hard_regno_nregs[regno][mode];
4674 unsigned int start_regno, end_regno, r;
4676 /* A complication is that for some reload types, inheritance might
4677 allow multiple reloads of the same types to share a reload register.
4678 We set check_opnum if we have to check only reloads with the same
4679 operand number, and check_any if we have to check all reloads. */
4680 int check_opnum = 0;
4682 HARD_REG_SET *used_in_set;
4687 used_in_set = &reload_reg_used;
4690 case RELOAD_FOR_INPUT_ADDRESS:
4691 used_in_set = &reload_reg_used_in_input_addr[opnum];
4694 case RELOAD_FOR_INPADDR_ADDRESS:
4696 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4699 case RELOAD_FOR_OUTPUT_ADDRESS:
4700 used_in_set = &reload_reg_used_in_output_addr[opnum];
4703 case RELOAD_FOR_OUTADDR_ADDRESS:
4705 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4708 case RELOAD_FOR_OPERAND_ADDRESS:
4709 used_in_set = &reload_reg_used_in_op_addr;
4712 case RELOAD_FOR_OPADDR_ADDR:
4714 used_in_set = &reload_reg_used_in_op_addr_reload;
4717 case RELOAD_FOR_OTHER_ADDRESS:
4718 used_in_set = &reload_reg_used_in_other_addr;
4722 case RELOAD_FOR_INPUT:
4723 used_in_set = &reload_reg_used_in_input[opnum];
4726 case RELOAD_FOR_OUTPUT:
4727 used_in_set = &reload_reg_used_in_output[opnum];
4730 case RELOAD_FOR_INSN:
4731 used_in_set = &reload_reg_used_in_insn;
4736 /* We resolve conflicts with remaining reloads of the same type by
4737 excluding the intervals of reload registers by them from the
4738 interval of freed reload registers. Since we only keep track of
4739 one set of interval bounds, we might have to exclude somewhat
4740 more than what would be necessary if we used a HARD_REG_SET here.
4741 But this should only happen very infrequently, so there should
4742 be no reason to worry about it. */
4744 start_regno = regno;
4745 end_regno = regno + nregs;
4746 if (check_opnum || check_any)
4748 for (i = n_reloads - 1; i >= 0; i--)
4750 if (rld[i].when_needed == type
4751 && (check_any || rld[i].opnum == opnum)
4754 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4755 unsigned int conflict_end
4756 = end_hard_regno (rld[i].mode, conflict_start);
4758 /* If there is an overlap with the first to-be-freed register,
4759 adjust the interval start. */
4760 if (conflict_start <= start_regno && conflict_end > start_regno)
4761 start_regno = conflict_end;
4762 /* Otherwise, if there is a conflict with one of the other
4763 to-be-freed registers, adjust the interval end. */
4764 if (conflict_start > start_regno && conflict_start < end_regno)
4765 end_regno = conflict_start;
4770 for (r = start_regno; r < end_regno; r++)
4771 CLEAR_HARD_REG_BIT (*used_in_set, r);
4774 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4775 specified by OPNUM and TYPE. */
4778 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4782 /* In use for a RELOAD_OTHER means it's not available for anything. */
4783 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4784 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4790 /* In use for anything means we can't use it for RELOAD_OTHER. */
4791 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4792 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4793 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4794 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4797 for (i = 0; i < reload_n_operands; i++)
4798 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4799 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4800 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4801 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4802 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4803 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4808 case RELOAD_FOR_INPUT:
4809 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4810 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4813 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4816 /* If it is used for some other input, can't use it. */
4817 for (i = 0; i < reload_n_operands; i++)
4818 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4821 /* If it is used in a later operand's address, can't use it. */
4822 for (i = opnum + 1; i < reload_n_operands; i++)
4823 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4824 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4829 case RELOAD_FOR_INPUT_ADDRESS:
4830 /* Can't use a register if it is used for an input address for this
4831 operand or used as an input in an earlier one. */
4832 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4833 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4836 for (i = 0; i < opnum; i++)
4837 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4842 case RELOAD_FOR_INPADDR_ADDRESS:
4843 /* Can't use a register if it is used for an input address
4844 for this operand or used as an input in an earlier
4846 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4849 for (i = 0; i < opnum; i++)
4850 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4855 case RELOAD_FOR_OUTPUT_ADDRESS:
4856 /* Can't use a register if it is used for an output address for this
4857 operand or used as an output in this or a later operand. Note
4858 that multiple output operands are emitted in reverse order, so
4859 the conflicting ones are those with lower indices. */
4860 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4863 for (i = 0; i <= opnum; i++)
4864 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4869 case RELOAD_FOR_OUTADDR_ADDRESS:
4870 /* Can't use a register if it is used for an output address
4871 for this operand or used as an output in this or a
4872 later operand. Note that multiple output operands are
4873 emitted in reverse order, so the conflicting ones are
4874 those with lower indices. */
4875 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4878 for (i = 0; i <= opnum; i++)
4879 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4884 case RELOAD_FOR_OPERAND_ADDRESS:
4885 for (i = 0; i < reload_n_operands; i++)
4886 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4889 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4890 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4892 case RELOAD_FOR_OPADDR_ADDR:
4893 for (i = 0; i < reload_n_operands; i++)
4894 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4897 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4899 case RELOAD_FOR_OUTPUT:
4900 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4901 outputs, or an operand address for this or an earlier output.
4902 Note that multiple output operands are emitted in reverse order,
4903 so the conflicting ones are those with higher indices. */
4904 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4907 for (i = 0; i < reload_n_operands; i++)
4908 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4911 for (i = opnum; i < reload_n_operands; i++)
4912 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4913 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4918 case RELOAD_FOR_INSN:
4919 for (i = 0; i < reload_n_operands; i++)
4920 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4921 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4924 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4925 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4927 case RELOAD_FOR_OTHER_ADDRESS:
4928 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4935 /* Return 1 if the value in reload reg REGNO, as used by a reload
4936 needed for the part of the insn specified by OPNUM and TYPE,
4937 is still available in REGNO at the end of the insn.
4939 We can assume that the reload reg was already tested for availability
4940 at the time it is needed, and we should not check this again,
4941 in case the reg has already been marked in use. */
4944 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4951 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4952 its value must reach the end. */
4955 /* If this use is for part of the insn,
4956 its value reaches if no subsequent part uses the same register.
4957 Just like the above function, don't try to do this with lots
4960 case RELOAD_FOR_OTHER_ADDRESS:
4961 /* Here we check for everything else, since these don't conflict
4962 with anything else and everything comes later. */
4964 for (i = 0; i < reload_n_operands; i++)
4965 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4966 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4967 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4968 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4969 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4970 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4973 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4974 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4975 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4976 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4978 case RELOAD_FOR_INPUT_ADDRESS:
4979 case RELOAD_FOR_INPADDR_ADDRESS:
4980 /* Similar, except that we check only for this and subsequent inputs
4981 and the address of only subsequent inputs and we do not need
4982 to check for RELOAD_OTHER objects since they are known not to
4985 for (i = opnum; i < reload_n_operands; i++)
4986 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4989 for (i = opnum + 1; i < reload_n_operands; i++)
4990 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4991 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4994 for (i = 0; i < reload_n_operands; i++)
4995 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4996 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4997 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5000 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5003 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5004 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5005 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5007 case RELOAD_FOR_INPUT:
5008 /* Similar to input address, except we start at the next operand for
5009 both input and input address and we do not check for
5010 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5013 for (i = opnum + 1; i < reload_n_operands; i++)
5014 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5015 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5016 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5019 /* ... fall through ... */
5021 case RELOAD_FOR_OPERAND_ADDRESS:
5022 /* Check outputs and their addresses. */
5024 for (i = 0; i < reload_n_operands; i++)
5025 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5026 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5027 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5030 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5032 case RELOAD_FOR_OPADDR_ADDR:
5033 for (i = 0; i < reload_n_operands; i++)
5034 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5035 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5036 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5039 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5040 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5041 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5043 case RELOAD_FOR_INSN:
5044 /* These conflict with other outputs with RELOAD_OTHER. So
5045 we need only check for output addresses. */
5047 opnum = reload_n_operands;
5049 /* ... fall through ... */
5051 case RELOAD_FOR_OUTPUT:
5052 case RELOAD_FOR_OUTPUT_ADDRESS:
5053 case RELOAD_FOR_OUTADDR_ADDRESS:
5054 /* We already know these can't conflict with a later output. So the
5055 only thing to check are later output addresses.
5056 Note that multiple output operands are emitted in reverse order,
5057 so the conflicting ones are those with lower indices. */
5058 for (i = 0; i < opnum; i++)
5059 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5060 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5070 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5071 every register in the range [REGNO, REGNO + NREGS). */
5074 reload_regs_reach_end_p (unsigned int regno, int nregs,
5075 int opnum, enum reload_type type)
5079 for (i = 0; i < nregs; i++)
5080 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5086 /* Returns whether R1 and R2 are uniquely chained: the value of one
5087 is used by the other, and that value is not used by any other
5088 reload for this insn. This is used to partially undo the decision
5089 made in find_reloads when in the case of multiple
5090 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5091 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5092 reloads. This code tries to avoid the conflict created by that
5093 change. It might be cleaner to explicitly keep track of which
5094 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5095 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5096 this after the fact. */
5098 reloads_unique_chain_p (int r1, int r2)
5102 /* We only check input reloads. */
5103 if (! rld[r1].in || ! rld[r2].in)
5106 /* Avoid anything with output reloads. */
5107 if (rld[r1].out || rld[r2].out)
5110 /* "chained" means one reload is a component of the other reload,
5111 not the same as the other reload. */
5112 if (rld[r1].opnum != rld[r2].opnum
5113 || rtx_equal_p (rld[r1].in, rld[r2].in)
5114 || rld[r1].optional || rld[r2].optional
5115 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5116 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5119 for (i = 0; i < n_reloads; i ++)
5120 /* Look for input reloads that aren't our two */
5121 if (i != r1 && i != r2 && rld[i].in)
5123 /* If our reload is mentioned at all, it isn't a simple chain. */
5124 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5131 /* The recursive function change all occurrences of WHAT in *WHERE
5134 substitute (rtx *where, const_rtx what, rtx repl)
5143 if (*where == what || rtx_equal_p (*where, what))
5149 code = GET_CODE (*where);
5150 fmt = GET_RTX_FORMAT (code);
5151 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5157 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5158 substitute (&XVECEXP (*where, i, j), what, repl);
5160 else if (fmt[i] == 'e')
5161 substitute (&XEXP (*where, i), what, repl);
5165 /* The function returns TRUE if chain of reload R1 and R2 (in any
5166 order) can be evaluated without usage of intermediate register for
5167 the reload containing another reload. It is important to see
5168 gen_reload to understand what the function is trying to do. As an
5169 example, let us have reload chain
5172 r1: <something> + const
5174 and reload R2 got reload reg HR. The function returns true if
5175 there is a correct insn HR = HR + <something>. Otherwise,
5176 gen_reload will use intermediate register (and this is the reload
5177 reg for R1) to reload <something>.
5179 We need this function to find a conflict for chain reloads. In our
5180 example, if HR = HR + <something> is incorrect insn, then we cannot
5181 use HR as a reload register for R2. If we do use it then we get a
5190 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5194 rtx out, in, tem, insn;
5195 rtx last = get_last_insn ();
5197 /* Make r2 a component of r1. */
5198 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5204 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5205 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5206 gcc_assert (regno >= 0);
5207 out = gen_rtx_REG (rld[r1].mode, regno);
5208 in = copy_rtx (rld[r1].in);
5209 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5211 /* If IN is a paradoxical SUBREG, remove it and try to put the
5212 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5213 if (GET_CODE (in) == SUBREG
5214 && (GET_MODE_SIZE (GET_MODE (in))
5215 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5216 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5217 in = SUBREG_REG (in), out = tem;
5219 if (GET_CODE (in) == PLUS
5220 && (REG_P (XEXP (in, 0))
5221 || GET_CODE (XEXP (in, 0)) == SUBREG
5222 || MEM_P (XEXP (in, 0)))
5223 && (REG_P (XEXP (in, 1))
5224 || GET_CODE (XEXP (in, 1)) == SUBREG
5225 || CONSTANT_P (XEXP (in, 1))
5226 || MEM_P (XEXP (in, 1))))
5228 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5229 code = recog_memoized (insn);
5234 extract_insn (insn);
5235 /* We want constrain operands to treat this insn strictly in
5236 its validity determination, i.e., the way it would after
5237 reload has completed. */
5238 result = constrain_operands (1);
5241 delete_insns_since (last);
5245 /* It looks like other cases in gen_reload are not possible for
5246 chain reloads or do need an intermediate hard registers. */
5250 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5253 This function uses the same algorithm as reload_reg_free_p above. */
5256 reloads_conflict (int r1, int r2)
5258 enum reload_type r1_type = rld[r1].when_needed;
5259 enum reload_type r2_type = rld[r2].when_needed;
5260 int r1_opnum = rld[r1].opnum;
5261 int r2_opnum = rld[r2].opnum;
5263 /* RELOAD_OTHER conflicts with everything. */
5264 if (r2_type == RELOAD_OTHER)
5267 /* Otherwise, check conflicts differently for each type. */
5271 case RELOAD_FOR_INPUT:
5272 return (r2_type == RELOAD_FOR_INSN
5273 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5274 || r2_type == RELOAD_FOR_OPADDR_ADDR
5275 || r2_type == RELOAD_FOR_INPUT
5276 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5277 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5278 && r2_opnum > r1_opnum));
5280 case RELOAD_FOR_INPUT_ADDRESS:
5281 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5282 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5284 case RELOAD_FOR_INPADDR_ADDRESS:
5285 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5286 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5288 case RELOAD_FOR_OUTPUT_ADDRESS:
5289 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5290 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5292 case RELOAD_FOR_OUTADDR_ADDRESS:
5293 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5294 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5296 case RELOAD_FOR_OPERAND_ADDRESS:
5297 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5298 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5299 && (!reloads_unique_chain_p (r1, r2)
5300 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5302 case RELOAD_FOR_OPADDR_ADDR:
5303 return (r2_type == RELOAD_FOR_INPUT
5304 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5306 case RELOAD_FOR_OUTPUT:
5307 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5308 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5309 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5310 && r2_opnum >= r1_opnum));
5312 case RELOAD_FOR_INSN:
5313 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5314 || r2_type == RELOAD_FOR_INSN
5315 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5317 case RELOAD_FOR_OTHER_ADDRESS:
5318 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5328 /* Indexed by reload number, 1 if incoming value
5329 inherited from previous insns. */
5330 static char reload_inherited[MAX_RELOADS];
5332 /* For an inherited reload, this is the insn the reload was inherited from,
5333 if we know it. Otherwise, this is 0. */
5334 static rtx reload_inheritance_insn[MAX_RELOADS];
5336 /* If nonzero, this is a place to get the value of the reload,
5337 rather than using reload_in. */
5338 static rtx reload_override_in[MAX_RELOADS];
5340 /* For each reload, the hard register number of the register used,
5341 or -1 if we did not need a register for this reload. */
5342 static int reload_spill_index[MAX_RELOADS];
5344 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5345 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5347 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5348 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5350 /* Subroutine of free_for_value_p, used to check a single register.
5351 START_REGNO is the starting regno of the full reload register
5352 (possibly comprising multiple hard registers) that we are considering. */
5355 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5356 enum reload_type type, rtx value, rtx out,
5357 int reloadnum, int ignore_address_reloads)
5360 /* Set if we see an input reload that must not share its reload register
5361 with any new earlyclobber, but might otherwise share the reload
5362 register with an output or input-output reload. */
5363 int check_earlyclobber = 0;
5367 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5370 if (out == const0_rtx)
5376 /* We use some pseudo 'time' value to check if the lifetimes of the
5377 new register use would overlap with the one of a previous reload
5378 that is not read-only or uses a different value.
5379 The 'time' used doesn't have to be linear in any shape or form, just
5381 Some reload types use different 'buckets' for each operand.
5382 So there are MAX_RECOG_OPERANDS different time values for each
5384 We compute TIME1 as the time when the register for the prospective
5385 new reload ceases to be live, and TIME2 for each existing
5386 reload as the time when that the reload register of that reload
5388 Where there is little to be gained by exact lifetime calculations,
5389 we just make conservative assumptions, i.e. a longer lifetime;
5390 this is done in the 'default:' cases. */
5393 case RELOAD_FOR_OTHER_ADDRESS:
5394 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5395 time1 = copy ? 0 : 1;
5398 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5400 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5401 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5402 respectively, to the time values for these, we get distinct time
5403 values. To get distinct time values for each operand, we have to
5404 multiply opnum by at least three. We round that up to four because
5405 multiply by four is often cheaper. */
5406 case RELOAD_FOR_INPADDR_ADDRESS:
5407 time1 = opnum * 4 + 2;
5409 case RELOAD_FOR_INPUT_ADDRESS:
5410 time1 = opnum * 4 + 3;
5412 case RELOAD_FOR_INPUT:
5413 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5414 executes (inclusive). */
5415 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5417 case RELOAD_FOR_OPADDR_ADDR:
5419 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5420 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5422 case RELOAD_FOR_OPERAND_ADDRESS:
5423 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5425 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5427 case RELOAD_FOR_OUTADDR_ADDRESS:
5428 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5430 case RELOAD_FOR_OUTPUT_ADDRESS:
5431 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5434 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5437 for (i = 0; i < n_reloads; i++)
5439 rtx reg = rld[i].reg_rtx;
5440 if (reg && REG_P (reg)
5441 && ((unsigned) regno - true_regnum (reg)
5442 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5445 rtx other_input = rld[i].in;
5447 /* If the other reload loads the same input value, that
5448 will not cause a conflict only if it's loading it into
5449 the same register. */
5450 if (true_regnum (reg) != start_regno)
5451 other_input = NULL_RTX;
5452 if (! other_input || ! rtx_equal_p (other_input, value)
5453 || rld[i].out || out)
5456 switch (rld[i].when_needed)
5458 case RELOAD_FOR_OTHER_ADDRESS:
5461 case RELOAD_FOR_INPADDR_ADDRESS:
5462 /* find_reloads makes sure that a
5463 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5464 by at most one - the first -
5465 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5466 address reload is inherited, the address address reload
5467 goes away, so we can ignore this conflict. */
5468 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5469 && ignore_address_reloads
5470 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5471 Then the address address is still needed to store
5472 back the new address. */
5473 && ! rld[reloadnum].out)
5475 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5476 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5478 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5479 && ignore_address_reloads
5480 /* Unless we are reloading an auto_inc expression. */
5481 && ! rld[reloadnum].out)
5483 time2 = rld[i].opnum * 4 + 2;
5485 case RELOAD_FOR_INPUT_ADDRESS:
5486 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5487 && ignore_address_reloads
5488 && ! rld[reloadnum].out)
5490 time2 = rld[i].opnum * 4 + 3;
5492 case RELOAD_FOR_INPUT:
5493 time2 = rld[i].opnum * 4 + 4;
5494 check_earlyclobber = 1;
5496 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5497 == MAX_RECOG_OPERAND * 4 */
5498 case RELOAD_FOR_OPADDR_ADDR:
5499 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5500 && ignore_address_reloads
5501 && ! rld[reloadnum].out)
5503 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5505 case RELOAD_FOR_OPERAND_ADDRESS:
5506 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5507 check_earlyclobber = 1;
5509 case RELOAD_FOR_INSN:
5510 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5512 case RELOAD_FOR_OUTPUT:
5513 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5514 instruction is executed. */
5515 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5517 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5518 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5520 case RELOAD_FOR_OUTADDR_ADDRESS:
5521 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5522 && ignore_address_reloads
5523 && ! rld[reloadnum].out)
5525 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5527 case RELOAD_FOR_OUTPUT_ADDRESS:
5528 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5531 /* If there is no conflict in the input part, handle this
5532 like an output reload. */
5533 if (! rld[i].in || rtx_equal_p (other_input, value))
5535 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5536 /* Earlyclobbered outputs must conflict with inputs. */
5537 if (earlyclobber_operand_p (rld[i].out))
5538 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5543 /* RELOAD_OTHER might be live beyond instruction execution,
5544 but this is not obvious when we set time2 = 1. So check
5545 here if there might be a problem with the new reload
5546 clobbering the register used by the RELOAD_OTHER. */
5554 && (! rld[i].in || rld[i].out
5555 || ! rtx_equal_p (other_input, value)))
5556 || (out && rld[reloadnum].out_reg
5557 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5563 /* Earlyclobbered outputs must conflict with inputs. */
5564 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5570 /* Return 1 if the value in reload reg REGNO, as used by a reload
5571 needed for the part of the insn specified by OPNUM and TYPE,
5572 may be used to load VALUE into it.
5574 MODE is the mode in which the register is used, this is needed to
5575 determine how many hard regs to test.
5577 Other read-only reloads with the same value do not conflict
5578 unless OUT is nonzero and these other reloads have to live while
5579 output reloads live.
5580 If OUT is CONST0_RTX, this is a special case: it means that the
5581 test should not be for using register REGNO as reload register, but
5582 for copying from register REGNO into the reload register.
5584 RELOADNUM is the number of the reload we want to load this value for;
5585 a reload does not conflict with itself.
5587 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5588 reloads that load an address for the very reload we are considering.
5590 The caller has to make sure that there is no conflict with the return
5594 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5595 enum reload_type type, rtx value, rtx out, int reloadnum,
5596 int ignore_address_reloads)
5598 int nregs = hard_regno_nregs[regno][mode];
5600 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5601 value, out, reloadnum,
5602 ignore_address_reloads))
5607 /* Return nonzero if the rtx X is invariant over the current function. */
5608 /* ??? Actually, the places where we use this expect exactly what is
5609 tested here, and not everything that is function invariant. In
5610 particular, the frame pointer and arg pointer are special cased;
5611 pic_offset_table_rtx is not, and we must not spill these things to
5615 function_invariant_p (const_rtx x)
5619 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5621 if (GET_CODE (x) == PLUS
5622 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5623 && CONSTANT_P (XEXP (x, 1)))
5628 /* Determine whether the reload reg X overlaps any rtx'es used for
5629 overriding inheritance. Return nonzero if so. */
5632 conflicts_with_override (rtx x)
5635 for (i = 0; i < n_reloads; i++)
5636 if (reload_override_in[i]
5637 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5642 /* Give an error message saying we failed to find a reload for INSN,
5643 and clear out reload R. */
5645 failed_reload (rtx insn, int r)
5647 if (asm_noperands (PATTERN (insn)) < 0)
5648 /* It's the compiler's fault. */
5649 fatal_insn ("could not find a spill register", insn);
5651 /* It's the user's fault; the operand's mode and constraint
5652 don't match. Disable this reload so we don't crash in final. */
5653 error_for_asm (insn,
5654 "%<asm%> operand constraint incompatible with operand size");
5658 rld[r].optional = 1;
5659 rld[r].secondary_p = 1;
5662 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5663 for reload R. If it's valid, get an rtx for it. Return nonzero if
5666 set_reload_reg (int i, int r)
5669 rtx reg = spill_reg_rtx[i];
5671 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5672 spill_reg_rtx[i] = reg
5673 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5675 regno = true_regnum (reg);
5677 /* Detect when the reload reg can't hold the reload mode.
5678 This used to be one `if', but Sequent compiler can't handle that. */
5679 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5681 enum machine_mode test_mode = VOIDmode;
5683 test_mode = GET_MODE (rld[r].in);
5684 /* If rld[r].in has VOIDmode, it means we will load it
5685 in whatever mode the reload reg has: to wit, rld[r].mode.
5686 We have already tested that for validity. */
5687 /* Aside from that, we need to test that the expressions
5688 to reload from or into have modes which are valid for this
5689 reload register. Otherwise the reload insns would be invalid. */
5690 if (! (rld[r].in != 0 && test_mode != VOIDmode
5691 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5692 if (! (rld[r].out != 0
5693 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5695 /* The reg is OK. */
5698 /* Mark as in use for this insn the reload regs we use
5700 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5701 rld[r].when_needed, rld[r].mode);
5703 rld[r].reg_rtx = reg;
5704 reload_spill_index[r] = spill_regs[i];
5711 /* Find a spill register to use as a reload register for reload R.
5712 LAST_RELOAD is nonzero if this is the last reload for the insn being
5715 Set rld[R].reg_rtx to the register allocated.
5717 We return 1 if successful, or 0 if we couldn't find a spill reg and
5718 we didn't change anything. */
5721 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5726 /* If we put this reload ahead, thinking it is a group,
5727 then insist on finding a group. Otherwise we can grab a
5728 reg that some other reload needs.
5729 (That can happen when we have a 68000 DATA_OR_FP_REG
5730 which is a group of data regs or one fp reg.)
5731 We need not be so restrictive if there are no more reloads
5734 ??? Really it would be nicer to have smarter handling
5735 for that kind of reg class, where a problem like this is normal.
5736 Perhaps those classes should be avoided for reloading
5737 by use of more alternatives. */
5739 int force_group = rld[r].nregs > 1 && ! last_reload;
5741 /* If we want a single register and haven't yet found one,
5742 take any reg in the right class and not in use.
5743 If we want a consecutive group, here is where we look for it.
5745 We use two passes so we can first look for reload regs to
5746 reuse, which are already in use for other reloads in this insn,
5747 and only then use additional registers.
5748 I think that maximizing reuse is needed to make sure we don't
5749 run out of reload regs. Suppose we have three reloads, and
5750 reloads A and B can share regs. These need two regs.
5751 Suppose A and B are given different regs.
5752 That leaves none for C. */
5753 for (pass = 0; pass < 2; pass++)
5755 /* I is the index in spill_regs.
5756 We advance it round-robin between insns to use all spill regs
5757 equally, so that inherited reloads have a chance
5758 of leapfrogging each other. */
5762 for (count = 0; count < n_spills; count++)
5764 int rclass = (int) rld[r].rclass;
5770 regnum = spill_regs[i];
5772 if ((reload_reg_free_p (regnum, rld[r].opnum,
5775 /* We check reload_reg_used to make sure we
5776 don't clobber the return register. */
5777 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5778 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5779 rld[r].when_needed, rld[r].in,
5781 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5782 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5783 /* Look first for regs to share, then for unshared. But
5784 don't share regs used for inherited reloads; they are
5785 the ones we want to preserve. */
5787 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5789 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5792 int nr = hard_regno_nregs[regnum][rld[r].mode];
5793 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5794 (on 68000) got us two FP regs. If NR is 1,
5795 we would reject both of them. */
5798 /* If we need only one reg, we have already won. */
5801 /* But reject a single reg if we demand a group. */
5806 /* Otherwise check that as many consecutive regs as we need
5807 are available here. */
5810 int regno = regnum + nr - 1;
5811 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5812 && spill_reg_order[regno] >= 0
5813 && reload_reg_free_p (regno, rld[r].opnum,
5814 rld[r].when_needed)))
5823 /* If we found something on pass 1, omit pass 2. */
5824 if (count < n_spills)
5828 /* We should have found a spill register by now. */
5829 if (count >= n_spills)
5832 /* I is the index in SPILL_REG_RTX of the reload register we are to
5833 allocate. Get an rtx for it and find its register number. */
5835 return set_reload_reg (i, r);
5838 /* Initialize all the tables needed to allocate reload registers.
5839 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5840 is the array we use to restore the reg_rtx field for every reload. */
5843 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5847 for (i = 0; i < n_reloads; i++)
5848 rld[i].reg_rtx = save_reload_reg_rtx[i];
5850 memset (reload_inherited, 0, MAX_RELOADS);
5851 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5852 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5854 CLEAR_HARD_REG_SET (reload_reg_used);
5855 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5856 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5857 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5858 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5859 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5861 CLEAR_HARD_REG_SET (reg_used_in_insn);
5864 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5865 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5866 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5867 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5868 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5869 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5872 for (i = 0; i < reload_n_operands; i++)
5874 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5875 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5876 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5877 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5878 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5879 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5882 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5884 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5886 for (i = 0; i < n_reloads; i++)
5887 /* If we have already decided to use a certain register,
5888 don't use it in another way. */
5890 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5891 rld[i].when_needed, rld[i].mode);
5894 /* Assign hard reg targets for the pseudo-registers we must reload
5895 into hard regs for this insn.
5896 Also output the instructions to copy them in and out of the hard regs.
5898 For machines with register classes, we are responsible for
5899 finding a reload reg in the proper class. */
5902 choose_reload_regs (struct insn_chain *chain)
5904 rtx insn = chain->insn;
5906 unsigned int max_group_size = 1;
5907 enum reg_class group_class = NO_REGS;
5908 int pass, win, inheritance;
5910 rtx save_reload_reg_rtx[MAX_RELOADS];
5912 /* In order to be certain of getting the registers we need,
5913 we must sort the reloads into order of increasing register class.
5914 Then our grabbing of reload registers will parallel the process
5915 that provided the reload registers.
5917 Also note whether any of the reloads wants a consecutive group of regs.
5918 If so, record the maximum size of the group desired and what
5919 register class contains all the groups needed by this insn. */
5921 for (j = 0; j < n_reloads; j++)
5923 reload_order[j] = j;
5924 if (rld[j].reg_rtx != NULL_RTX)
5926 gcc_assert (REG_P (rld[j].reg_rtx)
5927 && HARD_REGISTER_P (rld[j].reg_rtx));
5928 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5931 reload_spill_index[j] = -1;
5933 if (rld[j].nregs > 1)
5935 max_group_size = MAX (rld[j].nregs, max_group_size);
5937 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5940 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5944 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5946 /* If -O, try first with inheritance, then turning it off.
5947 If not -O, don't do inheritance.
5948 Using inheritance when not optimizing leads to paradoxes
5949 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5950 because one side of the comparison might be inherited. */
5952 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5954 choose_reload_regs_init (chain, save_reload_reg_rtx);
5956 /* Process the reloads in order of preference just found.
5957 Beyond this point, subregs can be found in reload_reg_rtx.
5959 This used to look for an existing reloaded home for all of the
5960 reloads, and only then perform any new reloads. But that could lose
5961 if the reloads were done out of reg-class order because a later
5962 reload with a looser constraint might have an old home in a register
5963 needed by an earlier reload with a tighter constraint.
5965 To solve this, we make two passes over the reloads, in the order
5966 described above. In the first pass we try to inherit a reload
5967 from a previous insn. If there is a later reload that needs a
5968 class that is a proper subset of the class being processed, we must
5969 also allocate a spill register during the first pass.
5971 Then make a second pass over the reloads to allocate any reloads
5972 that haven't been given registers yet. */
5974 for (j = 0; j < n_reloads; j++)
5976 int r = reload_order[j];
5977 rtx search_equiv = NULL_RTX;
5979 /* Ignore reloads that got marked inoperative. */
5980 if (rld[r].out == 0 && rld[r].in == 0
5981 && ! rld[r].secondary_p)
5984 /* If find_reloads chose to use reload_in or reload_out as a reload
5985 register, we don't need to chose one. Otherwise, try even if it
5986 found one since we might save an insn if we find the value lying
5988 Try also when reload_in is a pseudo without a hard reg. */
5989 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5990 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5991 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5992 && !MEM_P (rld[r].in)
5993 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5996 #if 0 /* No longer needed for correct operation.
5997 It might give better code, or might not; worth an experiment? */
5998 /* If this is an optional reload, we can't inherit from earlier insns
5999 until we are sure that any non-optional reloads have been allocated.
6000 The following code takes advantage of the fact that optional reloads
6001 are at the end of reload_order. */
6002 if (rld[r].optional != 0)
6003 for (i = 0; i < j; i++)
6004 if ((rld[reload_order[i]].out != 0
6005 || rld[reload_order[i]].in != 0
6006 || rld[reload_order[i]].secondary_p)
6007 && ! rld[reload_order[i]].optional
6008 && rld[reload_order[i]].reg_rtx == 0)
6009 allocate_reload_reg (chain, reload_order[i], 0);
6012 /* First see if this pseudo is already available as reloaded
6013 for a previous insn. We cannot try to inherit for reloads
6014 that are smaller than the maximum number of registers needed
6015 for groups unless the register we would allocate cannot be used
6018 We could check here to see if this is a secondary reload for
6019 an object that is already in a register of the desired class.
6020 This would avoid the need for the secondary reload register.
6021 But this is complex because we can't easily determine what
6022 objects might want to be loaded via this reload. So let a
6023 register be allocated here. In `emit_reload_insns' we suppress
6024 one of the loads in the case described above. */
6030 enum machine_mode mode = VOIDmode;
6034 else if (REG_P (rld[r].in))
6036 regno = REGNO (rld[r].in);
6037 mode = GET_MODE (rld[r].in);
6039 else if (REG_P (rld[r].in_reg))
6041 regno = REGNO (rld[r].in_reg);
6042 mode = GET_MODE (rld[r].in_reg);
6044 else if (GET_CODE (rld[r].in_reg) == SUBREG
6045 && REG_P (SUBREG_REG (rld[r].in_reg)))
6047 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6048 if (regno < FIRST_PSEUDO_REGISTER)
6049 regno = subreg_regno (rld[r].in_reg);
6051 byte = SUBREG_BYTE (rld[r].in_reg);
6052 mode = GET_MODE (rld[r].in_reg);
6055 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6056 && REG_P (XEXP (rld[r].in_reg, 0)))
6058 regno = REGNO (XEXP (rld[r].in_reg, 0));
6059 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6060 rld[r].out = rld[r].in;
6064 /* This won't work, since REGNO can be a pseudo reg number.
6065 Also, it takes much more hair to keep track of all the things
6066 that can invalidate an inherited reload of part of a pseudoreg. */
6067 else if (GET_CODE (rld[r].in) == SUBREG
6068 && REG_P (SUBREG_REG (rld[r].in)))
6069 regno = subreg_regno (rld[r].in);
6073 && reg_last_reload_reg[regno] != 0
6074 #ifdef CANNOT_CHANGE_MODE_CLASS
6075 /* Verify that the register it's in can be used in
6077 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6078 GET_MODE (reg_last_reload_reg[regno]),
6083 enum reg_class rclass = rld[r].rclass, last_class;
6084 rtx last_reg = reg_last_reload_reg[regno];
6085 enum machine_mode need_mode;
6087 i = REGNO (last_reg);
6088 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6089 last_class = REGNO_REG_CLASS (i);
6095 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
6096 + byte * BITS_PER_UNIT,
6097 GET_MODE_CLASS (mode));
6099 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6100 >= GET_MODE_SIZE (need_mode))
6101 && reg_reloaded_contents[i] == regno
6102 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6103 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6104 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6105 /* Even if we can't use this register as a reload
6106 register, we might use it for reload_override_in,
6107 if copying it to the desired class is cheap
6109 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6110 < MEMORY_MOVE_COST (mode, rclass, 1))
6111 && (secondary_reload_class (1, rclass, mode,
6114 #ifdef SECONDARY_MEMORY_NEEDED
6115 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6120 && (rld[r].nregs == max_group_size
6121 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6123 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6124 rld[r].when_needed, rld[r].in,
6127 /* If a group is needed, verify that all the subsequent
6128 registers still have their values intact. */
6129 int nr = hard_regno_nregs[i][rld[r].mode];
6132 for (k = 1; k < nr; k++)
6133 if (reg_reloaded_contents[i + k] != regno
6134 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6142 last_reg = (GET_MODE (last_reg) == mode
6143 ? last_reg : gen_rtx_REG (mode, i));
6146 for (k = 0; k < nr; k++)
6147 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6150 /* We found a register that contains the
6151 value we need. If this register is the
6152 same as an `earlyclobber' operand of the
6153 current insn, just mark it as a place to
6154 reload from since we can't use it as the
6155 reload register itself. */
6157 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6158 if (reg_overlap_mentioned_for_reload_p
6159 (reg_last_reload_reg[regno],
6160 reload_earlyclobbers[i1]))
6163 if (i1 != n_earlyclobbers
6164 || ! (free_for_value_p (i, rld[r].mode,
6166 rld[r].when_needed, rld[r].in,
6168 /* Don't use it if we'd clobber a pseudo reg. */
6169 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6171 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6172 /* Don't clobber the frame pointer. */
6173 || (i == HARD_FRAME_POINTER_REGNUM
6174 && frame_pointer_needed
6176 /* Don't really use the inherited spill reg
6177 if we need it wider than we've got it. */
6178 || (GET_MODE_SIZE (rld[r].mode)
6179 > GET_MODE_SIZE (mode))
6182 /* If find_reloads chose reload_out as reload
6183 register, stay with it - that leaves the
6184 inherited register for subsequent reloads. */
6185 || (rld[r].out && rld[r].reg_rtx
6186 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6188 if (! rld[r].optional)
6190 reload_override_in[r] = last_reg;
6191 reload_inheritance_insn[r]
6192 = reg_reloaded_insn[i];
6198 /* We can use this as a reload reg. */
6199 /* Mark the register as in use for this part of
6201 mark_reload_reg_in_use (i,
6205 rld[r].reg_rtx = last_reg;
6206 reload_inherited[r] = 1;
6207 reload_inheritance_insn[r]
6208 = reg_reloaded_insn[i];
6209 reload_spill_index[r] = i;
6210 for (k = 0; k < nr; k++)
6211 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6219 /* Here's another way to see if the value is already lying around. */
6222 && ! reload_inherited[r]
6224 && (CONSTANT_P (rld[r].in)
6225 || GET_CODE (rld[r].in) == PLUS
6226 || REG_P (rld[r].in)
6227 || MEM_P (rld[r].in))
6228 && (rld[r].nregs == max_group_size
6229 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6230 search_equiv = rld[r].in;
6231 /* If this is an output reload from a simple move insn, look
6232 if an equivalence for the input is available. */
6233 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6235 rtx set = single_set (insn);
6238 && rtx_equal_p (rld[r].out, SET_DEST (set))
6239 && CONSTANT_P (SET_SRC (set)))
6240 search_equiv = SET_SRC (set);
6246 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6247 -1, NULL, 0, rld[r].mode);
6253 regno = REGNO (equiv);
6256 /* This must be a SUBREG of a hard register.
6257 Make a new REG since this might be used in an
6258 address and not all machines support SUBREGs
6260 gcc_assert (GET_CODE (equiv) == SUBREG);
6261 regno = subreg_regno (equiv);
6262 equiv = gen_rtx_REG (rld[r].mode, regno);
6263 /* If we choose EQUIV as the reload register, but the
6264 loop below decides to cancel the inheritance, we'll
6265 end up reloading EQUIV in rld[r].mode, not the mode
6266 it had originally. That isn't safe when EQUIV isn't
6267 available as a spill register since its value might
6268 still be live at this point. */
6269 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6270 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6275 /* If we found a spill reg, reject it unless it is free
6276 and of the desired class. */
6280 int bad_for_class = 0;
6281 int max_regno = regno + rld[r].nregs;
6283 for (i = regno; i < max_regno; i++)
6285 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6287 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6292 && ! free_for_value_p (regno, rld[r].mode,
6293 rld[r].opnum, rld[r].when_needed,
6294 rld[r].in, rld[r].out, r, 1))
6299 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6302 /* We found a register that contains the value we need.
6303 If this register is the same as an `earlyclobber' operand
6304 of the current insn, just mark it as a place to reload from
6305 since we can't use it as the reload register itself. */
6308 for (i = 0; i < n_earlyclobbers; i++)
6309 if (reg_overlap_mentioned_for_reload_p (equiv,
6310 reload_earlyclobbers[i]))
6312 if (! rld[r].optional)
6313 reload_override_in[r] = equiv;
6318 /* If the equiv register we have found is explicitly clobbered
6319 in the current insn, it depends on the reload type if we
6320 can use it, use it for reload_override_in, or not at all.
6321 In particular, we then can't use EQUIV for a
6322 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6326 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6327 switch (rld[r].when_needed)
6329 case RELOAD_FOR_OTHER_ADDRESS:
6330 case RELOAD_FOR_INPADDR_ADDRESS:
6331 case RELOAD_FOR_INPUT_ADDRESS:
6332 case RELOAD_FOR_OPADDR_ADDR:
6335 case RELOAD_FOR_INPUT:
6336 case RELOAD_FOR_OPERAND_ADDRESS:
6337 if (! rld[r].optional)
6338 reload_override_in[r] = equiv;
6344 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6345 switch (rld[r].when_needed)
6347 case RELOAD_FOR_OTHER_ADDRESS:
6348 case RELOAD_FOR_INPADDR_ADDRESS:
6349 case RELOAD_FOR_INPUT_ADDRESS:
6350 case RELOAD_FOR_OPADDR_ADDR:
6351 case RELOAD_FOR_OPERAND_ADDRESS:
6352 case RELOAD_FOR_INPUT:
6355 if (! rld[r].optional)
6356 reload_override_in[r] = equiv;
6364 /* If we found an equivalent reg, say no code need be generated
6365 to load it, and use it as our reload reg. */
6367 && (regno != HARD_FRAME_POINTER_REGNUM
6368 || !frame_pointer_needed))
6370 int nr = hard_regno_nregs[regno][rld[r].mode];
6372 rld[r].reg_rtx = equiv;
6373 reload_inherited[r] = 1;
6375 /* If reg_reloaded_valid is not set for this register,
6376 there might be a stale spill_reg_store lying around.
6377 We must clear it, since otherwise emit_reload_insns
6378 might delete the store. */
6379 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6380 spill_reg_store[regno] = NULL_RTX;
6381 /* If any of the hard registers in EQUIV are spill
6382 registers, mark them as in use for this insn. */
6383 for (k = 0; k < nr; k++)
6385 i = spill_reg_order[regno + k];
6388 mark_reload_reg_in_use (regno, rld[r].opnum,
6391 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6398 /* If we found a register to use already, or if this is an optional
6399 reload, we are done. */
6400 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6404 /* No longer needed for correct operation. Might or might
6405 not give better code on the average. Want to experiment? */
6407 /* See if there is a later reload that has a class different from our
6408 class that intersects our class or that requires less register
6409 than our reload. If so, we must allocate a register to this
6410 reload now, since that reload might inherit a previous reload
6411 and take the only available register in our class. Don't do this
6412 for optional reloads since they will force all previous reloads
6413 to be allocated. Also don't do this for reloads that have been
6416 for (i = j + 1; i < n_reloads; i++)
6418 int s = reload_order[i];
6420 if ((rld[s].in == 0 && rld[s].out == 0
6421 && ! rld[s].secondary_p)
6425 if ((rld[s].rclass != rld[r].rclass
6426 && reg_classes_intersect_p (rld[r].rclass,
6428 || rld[s].nregs < rld[r].nregs)
6435 allocate_reload_reg (chain, r, j == n_reloads - 1);
6439 /* Now allocate reload registers for anything non-optional that
6440 didn't get one yet. */
6441 for (j = 0; j < n_reloads; j++)
6443 int r = reload_order[j];
6445 /* Ignore reloads that got marked inoperative. */
6446 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6449 /* Skip reloads that already have a register allocated or are
6451 if (rld[r].reg_rtx != 0 || rld[r].optional)
6454 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6458 /* If that loop got all the way, we have won. */
6465 /* Loop around and try without any inheritance. */
6470 /* First undo everything done by the failed attempt
6471 to allocate with inheritance. */
6472 choose_reload_regs_init (chain, save_reload_reg_rtx);
6474 /* Some sanity tests to verify that the reloads found in the first
6475 pass are identical to the ones we have now. */
6476 gcc_assert (chain->n_reloads == n_reloads);
6478 for (i = 0; i < n_reloads; i++)
6480 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6482 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6483 for (j = 0; j < n_spills; j++)
6484 if (spill_regs[j] == chain->rld[i].regno)
6485 if (! set_reload_reg (j, i))
6486 failed_reload (chain->insn, i);
6490 /* If we thought we could inherit a reload, because it seemed that
6491 nothing else wanted the same reload register earlier in the insn,
6492 verify that assumption, now that all reloads have been assigned.
6493 Likewise for reloads where reload_override_in has been set. */
6495 /* If doing expensive optimizations, do one preliminary pass that doesn't
6496 cancel any inheritance, but removes reloads that have been needed only
6497 for reloads that we know can be inherited. */
6498 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6500 for (j = 0; j < n_reloads; j++)
6502 int r = reload_order[j];
6504 if (reload_inherited[r] && rld[r].reg_rtx)
6505 check_reg = rld[r].reg_rtx;
6506 else if (reload_override_in[r]
6507 && (REG_P (reload_override_in[r])
6508 || GET_CODE (reload_override_in[r]) == SUBREG))
6509 check_reg = reload_override_in[r];
6512 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6513 rld[r].opnum, rld[r].when_needed, rld[r].in,
6514 (reload_inherited[r]
6515 ? rld[r].out : const0_rtx),
6520 reload_inherited[r] = 0;
6521 reload_override_in[r] = 0;
6523 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6524 reload_override_in, then we do not need its related
6525 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6526 likewise for other reload types.
6527 We handle this by removing a reload when its only replacement
6528 is mentioned in reload_in of the reload we are going to inherit.
6529 A special case are auto_inc expressions; even if the input is
6530 inherited, we still need the address for the output. We can
6531 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6532 If we succeeded removing some reload and we are doing a preliminary
6533 pass just to remove such reloads, make another pass, since the
6534 removal of one reload might allow us to inherit another one. */
6536 && rld[r].out != rld[r].in
6537 && remove_address_replacements (rld[r].in) && pass)
6542 /* Now that reload_override_in is known valid,
6543 actually override reload_in. */
6544 for (j = 0; j < n_reloads; j++)
6545 if (reload_override_in[j])
6546 rld[j].in = reload_override_in[j];
6548 /* If this reload won't be done because it has been canceled or is
6549 optional and not inherited, clear reload_reg_rtx so other
6550 routines (such as subst_reloads) don't get confused. */
6551 for (j = 0; j < n_reloads; j++)
6552 if (rld[j].reg_rtx != 0
6553 && ((rld[j].optional && ! reload_inherited[j])
6554 || (rld[j].in == 0 && rld[j].out == 0
6555 && ! rld[j].secondary_p)))
6557 int regno = true_regnum (rld[j].reg_rtx);
6559 if (spill_reg_order[regno] >= 0)
6560 clear_reload_reg_in_use (regno, rld[j].opnum,
6561 rld[j].when_needed, rld[j].mode);
6563 reload_spill_index[j] = -1;
6566 /* Record which pseudos and which spill regs have output reloads. */
6567 for (j = 0; j < n_reloads; j++)
6569 int r = reload_order[j];
6571 i = reload_spill_index[r];
6573 /* I is nonneg if this reload uses a register.
6574 If rld[r].reg_rtx is 0, this is an optional reload
6575 that we opted to ignore. */
6576 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6577 && rld[r].reg_rtx != 0)
6579 int nregno = REGNO (rld[r].out_reg);
6582 if (nregno < FIRST_PSEUDO_REGISTER)
6583 nr = hard_regno_nregs[nregno][rld[r].mode];
6586 SET_REGNO_REG_SET (®_has_output_reload,
6591 nr = hard_regno_nregs[i][rld[r].mode];
6593 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6596 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6597 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6598 || rld[r].when_needed == RELOAD_FOR_INSN);
6603 /* Deallocate the reload register for reload R. This is called from
6604 remove_address_replacements. */
6607 deallocate_reload_reg (int r)
6611 if (! rld[r].reg_rtx)
6613 regno = true_regnum (rld[r].reg_rtx);
6615 if (spill_reg_order[regno] >= 0)
6616 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6618 reload_spill_index[r] = -1;
6621 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6622 reloads of the same item for fear that we might not have enough reload
6623 registers. However, normally they will get the same reload register
6624 and hence actually need not be loaded twice.
6626 Here we check for the most common case of this phenomenon: when we have
6627 a number of reloads for the same object, each of which were allocated
6628 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6629 reload, and is not modified in the insn itself. If we find such,
6630 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6631 This will not increase the number of spill registers needed and will
6632 prevent redundant code. */
6635 merge_assigned_reloads (rtx insn)
6639 /* Scan all the reloads looking for ones that only load values and
6640 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6641 assigned and not modified by INSN. */
6643 for (i = 0; i < n_reloads; i++)
6645 int conflicting_input = 0;
6646 int max_input_address_opnum = -1;
6647 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6649 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6650 || rld[i].out != 0 || rld[i].reg_rtx == 0
6651 || reg_set_p (rld[i].reg_rtx, insn))
6654 /* Look at all other reloads. Ensure that the only use of this
6655 reload_reg_rtx is in a reload that just loads the same value
6656 as we do. Note that any secondary reloads must be of the identical
6657 class since the values, modes, and result registers are the
6658 same, so we need not do anything with any secondary reloads. */
6660 for (j = 0; j < n_reloads; j++)
6662 if (i == j || rld[j].reg_rtx == 0
6663 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6667 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6668 && rld[j].opnum > max_input_address_opnum)
6669 max_input_address_opnum = rld[j].opnum;
6671 /* If the reload regs aren't exactly the same (e.g, different modes)
6672 or if the values are different, we can't merge this reload.
6673 But if it is an input reload, we might still merge
6674 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6676 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6677 || rld[j].out != 0 || rld[j].in == 0
6678 || ! rtx_equal_p (rld[i].in, rld[j].in))
6680 if (rld[j].when_needed != RELOAD_FOR_INPUT
6681 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6682 || rld[i].opnum > rld[j].opnum)
6683 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6685 conflicting_input = 1;
6686 if (min_conflicting_input_opnum > rld[j].opnum)
6687 min_conflicting_input_opnum = rld[j].opnum;
6691 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6692 we, in fact, found any matching reloads. */
6695 && max_input_address_opnum <= min_conflicting_input_opnum)
6697 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6699 for (j = 0; j < n_reloads; j++)
6700 if (i != j && rld[j].reg_rtx != 0
6701 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6702 && (! conflicting_input
6703 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6704 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6706 rld[i].when_needed = RELOAD_OTHER;
6708 reload_spill_index[j] = -1;
6709 transfer_replacements (i, j);
6712 /* If this is now RELOAD_OTHER, look for any reloads that
6713 load parts of this operand and set them to
6714 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6715 RELOAD_OTHER for outputs. Note that this test is
6716 equivalent to looking for reloads for this operand
6719 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6720 it may share registers with a RELOAD_FOR_INPUT, so we can
6721 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6722 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6724 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6725 instruction is assigned the same register as the earlier
6726 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6727 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6728 instruction to be deleted later on. */
6730 if (rld[i].when_needed == RELOAD_OTHER)
6731 for (j = 0; j < n_reloads; j++)
6733 && rld[j].when_needed != RELOAD_OTHER
6734 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6735 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6736 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6737 && (! conflicting_input
6738 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6739 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6740 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6746 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6747 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6748 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6750 /* Check to see if we accidentally converted two
6751 reloads that use the same reload register with
6752 different inputs to the same type. If so, the
6753 resulting code won't work. */
6755 for (k = 0; k < j; k++)
6756 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6757 || rld[k].when_needed != rld[j].when_needed
6758 || !rtx_equal_p (rld[k].reg_rtx,
6760 || rtx_equal_p (rld[k].in,
6767 /* These arrays are filled by emit_reload_insns and its subroutines. */
6768 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6769 static rtx other_input_address_reload_insns = 0;
6770 static rtx other_input_reload_insns = 0;
6771 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6772 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6773 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6774 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6775 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6776 static rtx operand_reload_insns = 0;
6777 static rtx other_operand_reload_insns = 0;
6778 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6780 /* Values to be put in spill_reg_store are put here first. */
6781 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6782 static HARD_REG_SET reg_reloaded_died;
6784 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6785 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6786 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6787 adjusted register, and return true. Otherwise, return false. */
6789 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6790 enum reg_class new_class,
6791 enum machine_mode new_mode)
6796 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6798 unsigned regno = REGNO (reg);
6800 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6802 if (GET_MODE (reg) != new_mode)
6804 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6806 if (hard_regno_nregs[regno][new_mode]
6807 > hard_regno_nregs[regno][GET_MODE (reg)])
6809 reg = reload_adjust_reg_for_mode (reg, new_mode);
6817 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6818 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6819 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6820 adjusted register, and return true. Otherwise, return false. */
6822 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6823 enum insn_code icode)
6826 enum reg_class new_class = scratch_reload_class (icode);
6827 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6829 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6830 new_class, new_mode);
6833 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6834 has the number J. OLD contains the value to be used as input. */
6837 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6840 rtx insn = chain->insn;
6842 rtx oldequiv_reg = 0;
6845 enum machine_mode mode;
6848 /* delete_output_reload is only invoked properly if old contains
6849 the original pseudo register. Since this is replaced with a
6850 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6851 find the pseudo in RELOAD_IN_REG. */
6852 if (reload_override_in[j]
6853 && REG_P (rl->in_reg))
6860 else if (REG_P (oldequiv))
6861 oldequiv_reg = oldequiv;
6862 else if (GET_CODE (oldequiv) == SUBREG)
6863 oldequiv_reg = SUBREG_REG (oldequiv);
6865 reloadreg = reload_reg_rtx_for_input[j];
6866 mode = GET_MODE (reloadreg);
6868 /* If we are reloading from a register that was recently stored in
6869 with an output-reload, see if we can prove there was
6870 actually no need to store the old value in it. */
6872 if (optimize && REG_P (oldequiv)
6873 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6874 && spill_reg_store[REGNO (oldequiv)]
6876 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6877 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6879 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6881 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6884 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6885 oldequiv = SUBREG_REG (oldequiv);
6886 if (GET_MODE (oldequiv) != VOIDmode
6887 && mode != GET_MODE (oldequiv))
6888 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6890 /* Switch to the right place to emit the reload insns. */
6891 switch (rl->when_needed)
6894 where = &other_input_reload_insns;
6896 case RELOAD_FOR_INPUT:
6897 where = &input_reload_insns[rl->opnum];
6899 case RELOAD_FOR_INPUT_ADDRESS:
6900 where = &input_address_reload_insns[rl->opnum];
6902 case RELOAD_FOR_INPADDR_ADDRESS:
6903 where = &inpaddr_address_reload_insns[rl->opnum];
6905 case RELOAD_FOR_OUTPUT_ADDRESS:
6906 where = &output_address_reload_insns[rl->opnum];
6908 case RELOAD_FOR_OUTADDR_ADDRESS:
6909 where = &outaddr_address_reload_insns[rl->opnum];
6911 case RELOAD_FOR_OPERAND_ADDRESS:
6912 where = &operand_reload_insns;
6914 case RELOAD_FOR_OPADDR_ADDR:
6915 where = &other_operand_reload_insns;
6917 case RELOAD_FOR_OTHER_ADDRESS:
6918 where = &other_input_address_reload_insns;
6924 push_to_sequence (*where);
6926 /* Auto-increment addresses must be reloaded in a special way. */
6927 if (rl->out && ! rl->out_reg)
6929 /* We are not going to bother supporting the case where a
6930 incremented register can't be copied directly from
6931 OLDEQUIV since this seems highly unlikely. */
6932 gcc_assert (rl->secondary_in_reload < 0);
6934 if (reload_inherited[j])
6935 oldequiv = reloadreg;
6937 old = XEXP (rl->in_reg, 0);
6939 if (optimize && REG_P (oldequiv)
6940 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6941 && spill_reg_store[REGNO (oldequiv)]
6943 && (dead_or_set_p (insn,
6944 spill_reg_stored_to[REGNO (oldequiv)])
6945 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6947 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6949 /* Prevent normal processing of this reload. */
6951 /* Output a special code sequence for this case. */
6952 new_spill_reg_store[REGNO (reloadreg)]
6953 = inc_for_reload (reloadreg, oldequiv, rl->out,
6957 /* If we are reloading a pseudo-register that was set by the previous
6958 insn, see if we can get rid of that pseudo-register entirely
6959 by redirecting the previous insn into our reload register. */
6961 else if (optimize && REG_P (old)
6962 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6963 && dead_or_set_p (insn, old)
6964 /* This is unsafe if some other reload
6965 uses the same reg first. */
6966 && ! conflicts_with_override (reloadreg)
6967 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6968 rl->when_needed, old, rl->out, j, 0))
6970 rtx temp = PREV_INSN (insn);
6971 while (temp && NOTE_P (temp))
6972 temp = PREV_INSN (temp);
6974 && NONJUMP_INSN_P (temp)
6975 && GET_CODE (PATTERN (temp)) == SET
6976 && SET_DEST (PATTERN (temp)) == old
6977 /* Make sure we can access insn_operand_constraint. */
6978 && asm_noperands (PATTERN (temp)) < 0
6979 /* This is unsafe if operand occurs more than once in current
6980 insn. Perhaps some occurrences aren't reloaded. */
6981 && count_occurrences (PATTERN (insn), old, 0) == 1)
6983 rtx old = SET_DEST (PATTERN (temp));
6984 /* Store into the reload register instead of the pseudo. */
6985 SET_DEST (PATTERN (temp)) = reloadreg;
6987 /* Verify that resulting insn is valid. */
6988 extract_insn (temp);
6989 if (constrain_operands (1))
6991 /* If the previous insn is an output reload, the source is
6992 a reload register, and its spill_reg_store entry will
6993 contain the previous destination. This is now
6995 if (REG_P (SET_SRC (PATTERN (temp)))
6996 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6998 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6999 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7002 /* If these are the only uses of the pseudo reg,
7003 pretend for GDB it lives in the reload reg we used. */
7004 if (REG_N_DEATHS (REGNO (old)) == 1
7005 && REG_N_SETS (REGNO (old)) == 1)
7007 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7008 if (flag_ira && optimize)
7009 /* Inform IRA about the change. */
7010 ira_mark_allocation_change (REGNO (old));
7011 alter_reg (REGNO (old), -1, false);
7017 SET_DEST (PATTERN (temp)) = old;
7022 /* We can't do that, so output an insn to load RELOADREG. */
7024 /* If we have a secondary reload, pick up the secondary register
7025 and icode, if any. If OLDEQUIV and OLD are different or
7026 if this is an in-out reload, recompute whether or not we
7027 still need a secondary register and what the icode should
7028 be. If we still need a secondary register and the class or
7029 icode is different, go back to reloading from OLD if using
7030 OLDEQUIV means that we got the wrong type of register. We
7031 cannot have different class or icode due to an in-out reload
7032 because we don't make such reloads when both the input and
7033 output need secondary reload registers. */
7035 if (! special && rl->secondary_in_reload >= 0)
7037 rtx second_reload_reg = 0;
7038 rtx third_reload_reg = 0;
7039 int secondary_reload = rl->secondary_in_reload;
7040 rtx real_oldequiv = oldequiv;
7043 enum insn_code icode;
7044 enum insn_code tertiary_icode = CODE_FOR_nothing;
7046 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7047 and similarly for OLD.
7048 See comments in get_secondary_reload in reload.c. */
7049 /* If it is a pseudo that cannot be replaced with its
7050 equivalent MEM, we must fall back to reload_in, which
7051 will have all the necessary substitutions registered.
7052 Likewise for a pseudo that can't be replaced with its
7053 equivalent constant.
7055 Take extra care for subregs of such pseudos. Note that
7056 we cannot use reg_equiv_mem in this case because it is
7057 not in the right mode. */
7060 if (GET_CODE (tmp) == SUBREG)
7061 tmp = SUBREG_REG (tmp);
7063 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7064 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7065 || reg_equiv_constant[REGNO (tmp)] != 0))
7067 if (! reg_equiv_mem[REGNO (tmp)]
7068 || num_not_at_initial_offset
7069 || GET_CODE (oldequiv) == SUBREG)
7070 real_oldequiv = rl->in;
7072 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7076 if (GET_CODE (tmp) == SUBREG)
7077 tmp = SUBREG_REG (tmp);
7079 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7080 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7081 || reg_equiv_constant[REGNO (tmp)] != 0))
7083 if (! reg_equiv_mem[REGNO (tmp)]
7084 || num_not_at_initial_offset
7085 || GET_CODE (old) == SUBREG)
7088 real_old = reg_equiv_mem[REGNO (tmp)];
7091 second_reload_reg = rld[secondary_reload].reg_rtx;
7092 if (rld[secondary_reload].secondary_in_reload >= 0)
7094 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7096 third_reload_reg = rld[tertiary_reload].reg_rtx;
7097 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7098 /* We'd have to add more code for quartary reloads. */
7099 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7101 icode = rl->secondary_in_icode;
7103 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7104 || (rl->in != 0 && rl->out != 0))
7106 secondary_reload_info sri, sri2;
7107 enum reg_class new_class, new_t_class;
7109 sri.icode = CODE_FOR_nothing;
7110 sri.prev_sri = NULL;
7111 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7114 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7115 second_reload_reg = 0;
7116 else if (new_class == NO_REGS)
7118 if (reload_adjust_reg_for_icode (&second_reload_reg,
7119 third_reload_reg, sri.icode))
7120 icode = sri.icode, third_reload_reg = 0;
7122 oldequiv = old, real_oldequiv = real_old;
7124 else if (sri.icode != CODE_FOR_nothing)
7125 /* We currently lack a way to express this in reloads. */
7129 sri2.icode = CODE_FOR_nothing;
7130 sri2.prev_sri = &sri;
7131 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7132 new_class, mode, &sri);
7133 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7135 if (reload_adjust_reg_for_temp (&second_reload_reg,
7138 third_reload_reg = 0, tertiary_icode = sri2.icode;
7140 oldequiv = old, real_oldequiv = real_old;
7142 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7144 rtx intermediate = second_reload_reg;
7146 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7148 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7151 second_reload_reg = intermediate;
7152 tertiary_icode = sri2.icode;
7155 oldequiv = old, real_oldequiv = real_old;
7157 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7159 rtx intermediate = second_reload_reg;
7161 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7163 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7166 second_reload_reg = intermediate;
7167 tertiary_icode = sri2.icode;
7170 oldequiv = old, real_oldequiv = real_old;
7173 /* This could be handled more intelligently too. */
7174 oldequiv = old, real_oldequiv = real_old;
7178 /* If we still need a secondary reload register, check
7179 to see if it is being used as a scratch or intermediate
7180 register and generate code appropriately. If we need
7181 a scratch register, use REAL_OLDEQUIV since the form of
7182 the insn may depend on the actual address if it is
7185 if (second_reload_reg)
7187 if (icode != CODE_FOR_nothing)
7189 /* We'd have to add extra code to handle this case. */
7190 gcc_assert (!third_reload_reg);
7192 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7193 second_reload_reg));
7198 /* See if we need a scratch register to load the
7199 intermediate register (a tertiary reload). */
7200 if (tertiary_icode != CODE_FOR_nothing)
7202 emit_insn ((GEN_FCN (tertiary_icode)
7203 (second_reload_reg, real_oldequiv,
7204 third_reload_reg)));
7206 else if (third_reload_reg)
7208 gen_reload (third_reload_reg, real_oldequiv,
7211 gen_reload (second_reload_reg, third_reload_reg,
7216 gen_reload (second_reload_reg, real_oldequiv,
7220 oldequiv = second_reload_reg;
7225 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7227 rtx real_oldequiv = oldequiv;
7229 if ((REG_P (oldequiv)
7230 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7231 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7232 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7233 || (GET_CODE (oldequiv) == SUBREG
7234 && REG_P (SUBREG_REG (oldequiv))
7235 && (REGNO (SUBREG_REG (oldequiv))
7236 >= FIRST_PSEUDO_REGISTER)
7237 && ((reg_equiv_memory_loc
7238 [REGNO (SUBREG_REG (oldequiv))] != 0)
7239 || (reg_equiv_constant
7240 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7241 || (CONSTANT_P (oldequiv)
7242 && (PREFERRED_RELOAD_CLASS (oldequiv,
7243 REGNO_REG_CLASS (REGNO (reloadreg)))
7245 real_oldequiv = rl->in;
7246 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7250 if (flag_non_call_exceptions)
7251 copy_eh_notes (insn, get_insns ());
7253 /* End this sequence. */
7254 *where = get_insns ();
7257 /* Update reload_override_in so that delete_address_reloads_1
7258 can see the actual register usage. */
7260 reload_override_in[j] = oldequiv;
7263 /* Generate insns to for the output reload RL, which is for the insn described
7264 by CHAIN and has the number J. */
7266 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7270 rtx insn = chain->insn;
7273 enum machine_mode mode;
7277 if (rl->when_needed == RELOAD_OTHER)
7280 push_to_sequence (output_reload_insns[rl->opnum]);
7282 rl_reg_rtx = reload_reg_rtx_for_output[j];
7283 mode = GET_MODE (rl_reg_rtx);
7285 reloadreg = rl_reg_rtx;
7287 /* If we need two reload regs, set RELOADREG to the intermediate
7288 one, since it will be stored into OLD. We might need a secondary
7289 register only for an input reload, so check again here. */
7291 if (rl->secondary_out_reload >= 0)
7294 int secondary_reload = rl->secondary_out_reload;
7295 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7297 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7298 && reg_equiv_mem[REGNO (old)] != 0)
7299 real_old = reg_equiv_mem[REGNO (old)];
7301 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7303 rtx second_reloadreg = reloadreg;
7304 reloadreg = rld[secondary_reload].reg_rtx;
7306 /* See if RELOADREG is to be used as a scratch register
7307 or as an intermediate register. */
7308 if (rl->secondary_out_icode != CODE_FOR_nothing)
7310 /* We'd have to add extra code to handle this case. */
7311 gcc_assert (tertiary_reload < 0);
7313 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7314 (real_old, second_reloadreg, reloadreg)));
7319 /* See if we need both a scratch and intermediate reload
7322 enum insn_code tertiary_icode
7323 = rld[secondary_reload].secondary_out_icode;
7325 /* We'd have to add more code for quartary reloads. */
7326 gcc_assert (tertiary_reload < 0
7327 || rld[tertiary_reload].secondary_out_reload < 0);
7329 if (GET_MODE (reloadreg) != mode)
7330 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7332 if (tertiary_icode != CODE_FOR_nothing)
7334 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7337 /* Copy primary reload reg to secondary reload reg.
7338 (Note that these have been swapped above, then
7339 secondary reload reg to OLD using our insn.) */
7341 /* If REAL_OLD is a paradoxical SUBREG, remove it
7342 and try to put the opposite SUBREG on
7344 if (GET_CODE (real_old) == SUBREG
7345 && (GET_MODE_SIZE (GET_MODE (real_old))
7346 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7347 && 0 != (tem = gen_lowpart_common
7348 (GET_MODE (SUBREG_REG (real_old)),
7350 real_old = SUBREG_REG (real_old), reloadreg = tem;
7352 gen_reload (reloadreg, second_reloadreg,
7353 rl->opnum, rl->when_needed);
7354 emit_insn ((GEN_FCN (tertiary_icode)
7355 (real_old, reloadreg, third_reloadreg)));
7361 /* Copy between the reload regs here and then to
7364 gen_reload (reloadreg, second_reloadreg,
7365 rl->opnum, rl->when_needed);
7366 if (tertiary_reload >= 0)
7368 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7370 gen_reload (third_reloadreg, reloadreg,
7371 rl->opnum, rl->when_needed);
7372 reloadreg = third_reloadreg;
7379 /* Output the last reload insn. */
7384 /* Don't output the last reload if OLD is not the dest of
7385 INSN and is in the src and is clobbered by INSN. */
7386 if (! flag_expensive_optimizations
7388 || !(set = single_set (insn))
7389 || rtx_equal_p (old, SET_DEST (set))
7390 || !reg_mentioned_p (old, SET_SRC (set))
7391 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7392 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7393 gen_reload (old, reloadreg, rl->opnum,
7397 /* Look at all insns we emitted, just to be safe. */
7398 for (p = get_insns (); p; p = NEXT_INSN (p))
7401 rtx pat = PATTERN (p);
7403 /* If this output reload doesn't come from a spill reg,
7404 clear any memory of reloaded copies of the pseudo reg.
7405 If this output reload comes from a spill reg,
7406 reg_has_output_reload will make this do nothing. */
7407 note_stores (pat, forget_old_reloads_1, NULL);
7409 if (reg_mentioned_p (rl_reg_rtx, pat))
7411 rtx set = single_set (insn);
7412 if (reload_spill_index[j] < 0
7414 && SET_SRC (set) == rl_reg_rtx)
7416 int src = REGNO (SET_SRC (set));
7418 reload_spill_index[j] = src;
7419 SET_HARD_REG_BIT (reg_is_output_reload, src);
7420 if (find_regno_note (insn, REG_DEAD, src))
7421 SET_HARD_REG_BIT (reg_reloaded_died, src);
7423 if (HARD_REGISTER_P (rl_reg_rtx))
7425 int s = rl->secondary_out_reload;
7426 set = single_set (p);
7427 /* If this reload copies only to the secondary reload
7428 register, the secondary reload does the actual
7430 if (s >= 0 && set == NULL_RTX)
7431 /* We can't tell what function the secondary reload
7432 has and where the actual store to the pseudo is
7433 made; leave new_spill_reg_store alone. */
7436 && SET_SRC (set) == rl_reg_rtx
7437 && SET_DEST (set) == rld[s].reg_rtx)
7439 /* Usually the next instruction will be the
7440 secondary reload insn; if we can confirm
7441 that it is, setting new_spill_reg_store to
7442 that insn will allow an extra optimization. */
7443 rtx s_reg = rld[s].reg_rtx;
7444 rtx next = NEXT_INSN (p);
7445 rld[s].out = rl->out;
7446 rld[s].out_reg = rl->out_reg;
7447 set = single_set (next);
7448 if (set && SET_SRC (set) == s_reg
7449 && ! new_spill_reg_store[REGNO (s_reg)])
7451 SET_HARD_REG_BIT (reg_is_output_reload,
7453 new_spill_reg_store[REGNO (s_reg)] = next;
7457 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7462 if (rl->when_needed == RELOAD_OTHER)
7464 emit_insn (other_output_reload_insns[rl->opnum]);
7465 other_output_reload_insns[rl->opnum] = get_insns ();
7468 output_reload_insns[rl->opnum] = get_insns ();
7470 if (flag_non_call_exceptions)
7471 copy_eh_notes (insn, get_insns ());
7476 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7477 and has the number J. */
7479 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7481 rtx insn = chain->insn;
7482 rtx old = (rl->in && MEM_P (rl->in)
7483 ? rl->in_reg : rl->in);
7484 rtx reg_rtx = rl->reg_rtx;
7488 enum machine_mode mode;
7490 /* Determine the mode to reload in.
7491 This is very tricky because we have three to choose from.
7492 There is the mode the insn operand wants (rl->inmode).
7493 There is the mode of the reload register RELOADREG.
7494 There is the intrinsic mode of the operand, which we could find
7495 by stripping some SUBREGs.
7496 It turns out that RELOADREG's mode is irrelevant:
7497 we can change that arbitrarily.
7499 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7500 then the reload reg may not support QImode moves, so use SImode.
7501 If foo is in memory due to spilling a pseudo reg, this is safe,
7502 because the QImode value is in the least significant part of a
7503 slot big enough for a SImode. If foo is some other sort of
7504 memory reference, then it is impossible to reload this case,
7505 so previous passes had better make sure this never happens.
7507 Then consider a one-word union which has SImode and one of its
7508 members is a float, being fetched as (SUBREG:SF union:SI).
7509 We must fetch that as SFmode because we could be loading into
7510 a float-only register. In this case OLD's mode is correct.
7512 Consider an immediate integer: it has VOIDmode. Here we need
7513 to get a mode from something else.
7515 In some cases, there is a fourth mode, the operand's
7516 containing mode. If the insn specifies a containing mode for
7517 this operand, it overrides all others.
7519 I am not sure whether the algorithm here is always right,
7520 but it does the right things in those cases. */
7522 mode = GET_MODE (old);
7523 if (mode == VOIDmode)
7526 /* We cannot use gen_lowpart_common since it can do the wrong thing
7527 when REG_RTX has a multi-word mode. Note that REG_RTX must
7528 always be a REG here. */
7529 if (GET_MODE (reg_rtx) != mode)
7530 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7532 reload_reg_rtx_for_input[j] = reg_rtx;
7535 /* AUTO_INC reloads need to be handled even if inherited. We got an
7536 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7537 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7538 && ! rtx_equal_p (reg_rtx, old)
7540 emit_input_reload_insns (chain, rld + j, old, j);
7542 /* When inheriting a wider reload, we have a MEM in rl->in,
7543 e.g. inheriting a SImode output reload for
7544 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7545 if (optimize && reload_inherited[j] && rl->in
7547 && MEM_P (rl->in_reg)
7548 && reload_spill_index[j] >= 0
7549 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7550 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7552 /* If we are reloading a register that was recently stored in with an
7553 output-reload, see if we can prove there was
7554 actually no need to store the old value in it. */
7557 && (reload_inherited[j] || reload_override_in[j])
7560 && spill_reg_store[REGNO (reg_rtx)] != 0
7562 /* There doesn't seem to be any reason to restrict this to pseudos
7563 and doing so loses in the case where we are copying from a
7564 register of the wrong class. */
7565 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7567 /* The insn might have already some references to stackslots
7568 replaced by MEMs, while reload_out_reg still names the
7570 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7571 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7572 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7575 /* Do output reloading for reload RL, which is for the insn described by
7576 CHAIN and has the number J.
7577 ??? At some point we need to support handling output reloads of
7578 JUMP_INSNs or insns that set cc0. */
7580 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7583 rtx insn = chain->insn;
7584 /* If this is an output reload that stores something that is
7585 not loaded in this same reload, see if we can eliminate a previous
7587 rtx pseudo = rl->out_reg;
7588 rtx reg_rtx = rl->reg_rtx;
7590 if (rl->out && reg_rtx)
7592 enum machine_mode mode;
7594 /* Determine the mode to reload in.
7595 See comments above (for input reloading). */
7596 mode = GET_MODE (rl->out);
7597 if (mode == VOIDmode)
7599 /* VOIDmode should never happen for an output. */
7600 if (asm_noperands (PATTERN (insn)) < 0)
7601 /* It's the compiler's fault. */
7602 fatal_insn ("VOIDmode on an output", insn);
7603 error_for_asm (insn, "output operand is constant in %<asm%>");
7604 /* Prevent crash--use something we know is valid. */
7606 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7608 if (GET_MODE (reg_rtx) != mode)
7609 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7611 reload_reg_rtx_for_output[j] = reg_rtx;
7616 && ! rtx_equal_p (rl->in_reg, pseudo)
7617 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7618 && reg_last_reload_reg[REGNO (pseudo)])
7620 int pseudo_no = REGNO (pseudo);
7621 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7623 /* We don't need to test full validity of last_regno for
7624 inherit here; we only want to know if the store actually
7625 matches the pseudo. */
7626 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7627 && reg_reloaded_contents[last_regno] == pseudo_no
7628 && spill_reg_store[last_regno]
7629 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7630 delete_output_reload (insn, j, last_regno, reg_rtx);
7636 || rtx_equal_p (old, reg_rtx))
7639 /* An output operand that dies right away does need a reload,
7640 but need not be copied from it. Show the new location in the
7642 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7643 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7645 XEXP (note, 0) = reg_rtx;
7648 /* Likewise for a SUBREG of an operand that dies. */
7649 else if (GET_CODE (old) == SUBREG
7650 && REG_P (SUBREG_REG (old))
7651 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7654 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7657 else if (GET_CODE (old) == SCRATCH)
7658 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7659 but we don't want to make an output reload. */
7662 /* If is a JUMP_INSN, we can't support output reloads yet. */
7663 gcc_assert (NONJUMP_INSN_P (insn));
7665 emit_output_reload_insns (chain, rld + j, j);
7668 /* A reload copies values of MODE from register SRC to register DEST.
7669 Return true if it can be treated for inheritance purposes like a
7670 group of reloads, each one reloading a single hard register. The
7671 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7672 occupy the same number of hard registers. */
7675 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7676 int src ATTRIBUTE_UNUSED,
7677 enum machine_mode mode ATTRIBUTE_UNUSED)
7679 #ifdef CANNOT_CHANGE_MODE_CLASS
7680 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7681 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7687 /* Output insns to reload values in and out of the chosen reload regs. */
7690 emit_reload_insns (struct insn_chain *chain)
7692 rtx insn = chain->insn;
7696 CLEAR_HARD_REG_SET (reg_reloaded_died);
7698 for (j = 0; j < reload_n_operands; j++)
7699 input_reload_insns[j] = input_address_reload_insns[j]
7700 = inpaddr_address_reload_insns[j]
7701 = output_reload_insns[j] = output_address_reload_insns[j]
7702 = outaddr_address_reload_insns[j]
7703 = other_output_reload_insns[j] = 0;
7704 other_input_address_reload_insns = 0;
7705 other_input_reload_insns = 0;
7706 operand_reload_insns = 0;
7707 other_operand_reload_insns = 0;
7709 /* Dump reloads into the dump file. */
7712 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7713 debug_reload_to_stream (dump_file);
7716 /* Now output the instructions to copy the data into and out of the
7717 reload registers. Do these in the order that the reloads were reported,
7718 since reloads of base and index registers precede reloads of operands
7719 and the operands may need the base and index registers reloaded. */
7721 for (j = 0; j < n_reloads; j++)
7723 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7727 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7728 new_spill_reg_store[i] = 0;
7731 do_input_reload (chain, rld + j, j);
7732 do_output_reload (chain, rld + j, j);
7735 /* Now write all the insns we made for reloads in the order expected by
7736 the allocation functions. Prior to the insn being reloaded, we write
7737 the following reloads:
7739 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7741 RELOAD_OTHER reloads.
7743 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7744 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7745 RELOAD_FOR_INPUT reload for the operand.
7747 RELOAD_FOR_OPADDR_ADDRS reloads.
7749 RELOAD_FOR_OPERAND_ADDRESS reloads.
7751 After the insn being reloaded, we write the following:
7753 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7754 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7755 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7756 reloads for the operand. The RELOAD_OTHER output reloads are
7757 output in descending order by reload number. */
7759 emit_insn_before (other_input_address_reload_insns, insn);
7760 emit_insn_before (other_input_reload_insns, insn);
7762 for (j = 0; j < reload_n_operands; j++)
7764 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7765 emit_insn_before (input_address_reload_insns[j], insn);
7766 emit_insn_before (input_reload_insns[j], insn);
7769 emit_insn_before (other_operand_reload_insns, insn);
7770 emit_insn_before (operand_reload_insns, insn);
7772 for (j = 0; j < reload_n_operands; j++)
7774 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7775 x = emit_insn_after (output_address_reload_insns[j], x);
7776 x = emit_insn_after (output_reload_insns[j], x);
7777 emit_insn_after (other_output_reload_insns[j], x);
7780 /* For all the spill regs newly reloaded in this instruction,
7781 record what they were reloaded from, so subsequent instructions
7782 can inherit the reloads.
7784 Update spill_reg_store for the reloads of this insn.
7785 Copy the elements that were updated in the loop above. */
7787 for (j = 0; j < n_reloads; j++)
7789 int r = reload_order[j];
7790 int i = reload_spill_index[r];
7792 /* If this is a non-inherited input reload from a pseudo, we must
7793 clear any memory of a previous store to the same pseudo. Only do
7794 something if there will not be an output reload for the pseudo
7796 if (rld[r].in_reg != 0
7797 && ! (reload_inherited[r] || reload_override_in[r]))
7799 rtx reg = rld[r].in_reg;
7801 if (GET_CODE (reg) == SUBREG)
7802 reg = SUBREG_REG (reg);
7805 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7806 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7808 int nregno = REGNO (reg);
7810 if (reg_last_reload_reg[nregno])
7812 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7814 if (reg_reloaded_contents[last_regno] == nregno)
7815 spill_reg_store[last_regno] = 0;
7820 /* I is nonneg if this reload used a register.
7821 If rld[r].reg_rtx is 0, this is an optional reload
7822 that we opted to ignore. */
7824 if (i >= 0 && rld[r].reg_rtx != 0)
7826 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7829 /* For a multi register reload, we need to check if all or part
7830 of the value lives to the end. */
7831 for (k = 0; k < nr; k++)
7832 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7833 rld[r].when_needed))
7834 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7836 /* Maybe the spill reg contains a copy of reload_out. */
7838 && (REG_P (rld[r].out)
7842 || REG_P (rld[r].out_reg)))
7845 enum machine_mode mode;
7848 reg = reload_reg_rtx_for_output[r];
7849 mode = GET_MODE (reg);
7850 regno = REGNO (reg);
7851 nregs = hard_regno_nregs[regno][mode];
7852 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7853 rld[r].when_needed))
7855 rtx out = (REG_P (rld[r].out)
7859 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7860 int out_regno = REGNO (out);
7861 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7862 : hard_regno_nregs[out_regno][mode]);
7865 spill_reg_store[regno] = new_spill_reg_store[regno];
7866 spill_reg_stored_to[regno] = out;
7867 reg_last_reload_reg[out_regno] = reg;
7869 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7870 && nregs == out_nregs
7871 && inherit_piecemeal_p (out_regno, regno, mode));
7873 /* If OUT_REGNO is a hard register, it may occupy more than
7874 one register. If it does, say what is in the
7875 rest of the registers assuming that both registers
7876 agree on how many words the object takes. If not,
7877 invalidate the subsequent registers. */
7879 if (HARD_REGISTER_NUM_P (out_regno))
7880 for (k = 1; k < out_nregs; k++)
7881 reg_last_reload_reg[out_regno + k]
7882 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7884 /* Now do the inverse operation. */
7885 for (k = 0; k < nregs; k++)
7887 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7888 reg_reloaded_contents[regno + k]
7889 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7892 reg_reloaded_insn[regno + k] = insn;
7893 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7894 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7895 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7898 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7903 /* Maybe the spill reg contains a copy of reload_in. Only do
7904 something if there will not be an output reload for
7905 the register being reloaded. */
7906 else if (rld[r].out_reg == 0
7908 && ((REG_P (rld[r].in)
7909 && !HARD_REGISTER_P (rld[r].in)
7910 && !REGNO_REG_SET_P (®_has_output_reload,
7912 || (REG_P (rld[r].in_reg)
7913 && !REGNO_REG_SET_P (®_has_output_reload,
7914 REGNO (rld[r].in_reg))))
7915 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7918 enum machine_mode mode;
7921 reg = reload_reg_rtx_for_input[r];
7922 mode = GET_MODE (reg);
7923 regno = REGNO (reg);
7924 nregs = hard_regno_nregs[regno][mode];
7925 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7926 rld[r].when_needed))
7933 if (REG_P (rld[r].in)
7934 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7936 else if (REG_P (rld[r].in_reg))
7939 in = XEXP (rld[r].in_reg, 0);
7940 in_regno = REGNO (in);
7942 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7943 : hard_regno_nregs[in_regno][mode]);
7945 reg_last_reload_reg[in_regno] = reg;
7947 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7948 && nregs == in_nregs
7949 && inherit_piecemeal_p (regno, in_regno, mode));
7951 if (HARD_REGISTER_NUM_P (in_regno))
7952 for (k = 1; k < in_nregs; k++)
7953 reg_last_reload_reg[in_regno + k]
7954 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7956 /* Unless we inherited this reload, show we haven't
7957 recently done a store.
7958 Previous stores of inherited auto_inc expressions
7959 also have to be discarded. */
7960 if (! reload_inherited[r]
7961 || (rld[r].out && ! rld[r].out_reg))
7962 spill_reg_store[regno] = 0;
7964 for (k = 0; k < nregs; k++)
7966 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7967 reg_reloaded_contents[regno + k]
7968 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7971 reg_reloaded_insn[regno + k] = insn;
7972 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7973 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7974 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7977 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7984 /* The following if-statement was #if 0'd in 1.34 (or before...).
7985 It's reenabled in 1.35 because supposedly nothing else
7986 deals with this problem. */
7988 /* If a register gets output-reloaded from a non-spill register,
7989 that invalidates any previous reloaded copy of it.
7990 But forget_old_reloads_1 won't get to see it, because
7991 it thinks only about the original insn. So invalidate it here.
7992 Also do the same thing for RELOAD_OTHER constraints where the
7993 output is discarded. */
7995 && ((rld[r].out != 0
7996 && (REG_P (rld[r].out)
7997 || (MEM_P (rld[r].out)
7998 && REG_P (rld[r].out_reg))))
7999 || (rld[r].out == 0 && rld[r].out_reg
8000 && REG_P (rld[r].out_reg))))
8002 rtx out = ((rld[r].out && REG_P (rld[r].out))
8003 ? rld[r].out : rld[r].out_reg);
8004 int out_regno = REGNO (out);
8005 enum machine_mode mode = GET_MODE (out);
8007 /* REG_RTX is now set or clobbered by the main instruction.
8008 As the comment above explains, forget_old_reloads_1 only
8009 sees the original instruction, and there is no guarantee
8010 that the original instruction also clobbered REG_RTX.
8011 For example, if find_reloads sees that the input side of
8012 a matched operand pair dies in this instruction, it may
8013 use the input register as the reload register.
8015 Calling forget_old_reloads_1 is a waste of effort if
8016 REG_RTX is also the output register.
8018 If we know that REG_RTX holds the value of a pseudo
8019 register, the code after the call will record that fact. */
8020 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8021 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8023 if (!HARD_REGISTER_NUM_P (out_regno))
8025 rtx src_reg, store_insn = NULL_RTX;
8027 reg_last_reload_reg[out_regno] = 0;
8029 /* If we can find a hard register that is stored, record
8030 the storing insn so that we may delete this insn with
8031 delete_output_reload. */
8032 src_reg = reload_reg_rtx_for_output[r];
8034 /* If this is an optional reload, try to find the source reg
8035 from an input reload. */
8038 rtx set = single_set (insn);
8039 if (set && SET_DEST (set) == rld[r].out)
8043 src_reg = SET_SRC (set);
8045 for (k = 0; k < n_reloads; k++)
8047 if (rld[k].in == src_reg)
8049 src_reg = reload_reg_rtx_for_input[k];
8056 store_insn = new_spill_reg_store[REGNO (src_reg)];
8057 if (src_reg && REG_P (src_reg)
8058 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8060 int src_regno, src_nregs, k;
8063 gcc_assert (GET_MODE (src_reg) == mode);
8064 src_regno = REGNO (src_reg);
8065 src_nregs = hard_regno_nregs[src_regno][mode];
8066 /* The place where to find a death note varies with
8067 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8068 necessarily checked exactly in the code that moves
8069 notes, so just check both locations. */
8070 note = find_regno_note (insn, REG_DEAD, src_regno);
8071 if (! note && store_insn)
8072 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8073 for (k = 0; k < src_nregs; k++)
8075 spill_reg_store[src_regno + k] = store_insn;
8076 spill_reg_stored_to[src_regno + k] = out;
8077 reg_reloaded_contents[src_regno + k] = out_regno;
8078 reg_reloaded_insn[src_regno + k] = store_insn;
8079 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8080 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8081 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8083 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8086 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8088 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8090 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8092 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8094 reg_last_reload_reg[out_regno] = src_reg;
8095 /* We have to set reg_has_output_reload here, or else
8096 forget_old_reloads_1 will clear reg_last_reload_reg
8098 SET_REGNO_REG_SET (®_has_output_reload,
8104 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8106 for (k = 0; k < out_nregs; k++)
8107 reg_last_reload_reg[out_regno + k] = 0;
8111 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8114 /* Go through the motions to emit INSN and test if it is strictly valid.
8115 Return the emitted insn if valid, else return NULL. */
8118 emit_insn_if_valid_for_reload (rtx insn)
8120 rtx last = get_last_insn ();
8123 insn = emit_insn (insn);
8124 code = recog_memoized (insn);
8128 extract_insn (insn);
8129 /* We want constrain operands to treat this insn strictly in its
8130 validity determination, i.e., the way it would after reload has
8132 if (constrain_operands (1))
8136 delete_insns_since (last);
8140 /* Emit code to perform a reload from IN (which may be a reload register) to
8141 OUT (which may also be a reload register). IN or OUT is from operand
8142 OPNUM with reload type TYPE.
8144 Returns first insn emitted. */
8147 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8149 rtx last = get_last_insn ();
8152 /* If IN is a paradoxical SUBREG, remove it and try to put the
8153 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8154 if (GET_CODE (in) == SUBREG
8155 && (GET_MODE_SIZE (GET_MODE (in))
8156 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8157 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8158 in = SUBREG_REG (in), out = tem;
8159 else if (GET_CODE (out) == SUBREG
8160 && (GET_MODE_SIZE (GET_MODE (out))
8161 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8162 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8163 out = SUBREG_REG (out), in = tem;
8165 /* How to do this reload can get quite tricky. Normally, we are being
8166 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8167 register that didn't get a hard register. In that case we can just
8168 call emit_move_insn.
8170 We can also be asked to reload a PLUS that adds a register or a MEM to
8171 another register, constant or MEM. This can occur during frame pointer
8172 elimination and while reloading addresses. This case is handled by
8173 trying to emit a single insn to perform the add. If it is not valid,
8174 we use a two insn sequence.
8176 Or we can be asked to reload an unary operand that was a fragment of
8177 an addressing mode, into a register. If it isn't recognized as-is,
8178 we try making the unop operand and the reload-register the same:
8179 (set reg:X (unop:X expr:Y))
8180 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8182 Finally, we could be called to handle an 'o' constraint by putting
8183 an address into a register. In that case, we first try to do this
8184 with a named pattern of "reload_load_address". If no such pattern
8185 exists, we just emit a SET insn and hope for the best (it will normally
8186 be valid on machines that use 'o').
8188 This entire process is made complex because reload will never
8189 process the insns we generate here and so we must ensure that
8190 they will fit their constraints and also by the fact that parts of
8191 IN might be being reloaded separately and replaced with spill registers.
8192 Because of this, we are, in some sense, just guessing the right approach
8193 here. The one listed above seems to work.
8195 ??? At some point, this whole thing needs to be rethought. */
8197 if (GET_CODE (in) == PLUS
8198 && (REG_P (XEXP (in, 0))
8199 || GET_CODE (XEXP (in, 0)) == SUBREG
8200 || MEM_P (XEXP (in, 0)))
8201 && (REG_P (XEXP (in, 1))
8202 || GET_CODE (XEXP (in, 1)) == SUBREG
8203 || CONSTANT_P (XEXP (in, 1))
8204 || MEM_P (XEXP (in, 1))))
8206 /* We need to compute the sum of a register or a MEM and another
8207 register, constant, or MEM, and put it into the reload
8208 register. The best possible way of doing this is if the machine
8209 has a three-operand ADD insn that accepts the required operands.
8211 The simplest approach is to try to generate such an insn and see if it
8212 is recognized and matches its constraints. If so, it can be used.
8214 It might be better not to actually emit the insn unless it is valid,
8215 but we need to pass the insn as an operand to `recog' and
8216 `extract_insn' and it is simpler to emit and then delete the insn if
8217 not valid than to dummy things up. */
8219 rtx op0, op1, tem, insn;
8222 op0 = find_replacement (&XEXP (in, 0));
8223 op1 = find_replacement (&XEXP (in, 1));
8225 /* Since constraint checking is strict, commutativity won't be
8226 checked, so we need to do that here to avoid spurious failure
8227 if the add instruction is two-address and the second operand
8228 of the add is the same as the reload reg, which is frequently
8229 the case. If the insn would be A = B + A, rearrange it so
8230 it will be A = A + B as constrain_operands expects. */
8232 if (REG_P (XEXP (in, 1))
8233 && REGNO (out) == REGNO (XEXP (in, 1)))
8234 tem = op0, op0 = op1, op1 = tem;
8236 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8237 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8239 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8243 /* If that failed, we must use a conservative two-insn sequence.
8245 Use a move to copy one operand into the reload register. Prefer
8246 to reload a constant, MEM or pseudo since the move patterns can
8247 handle an arbitrary operand. If OP1 is not a constant, MEM or
8248 pseudo and OP1 is not a valid operand for an add instruction, then
8251 After reloading one of the operands into the reload register, add
8252 the reload register to the output register.
8254 If there is another way to do this for a specific machine, a
8255 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8258 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8260 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8262 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8263 || (code != CODE_FOR_nothing
8264 && ! ((*insn_data[code].operand[2].predicate)
8265 (op1, insn_data[code].operand[2].mode))))
8266 tem = op0, op0 = op1, op1 = tem;
8268 gen_reload (out, op0, opnum, type);
8270 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8271 This fixes a problem on the 32K where the stack pointer cannot
8272 be used as an operand of an add insn. */
8274 if (rtx_equal_p (op0, op1))
8277 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8280 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8281 set_unique_reg_note (insn, REG_EQUIV, in);
8285 /* If that failed, copy the address register to the reload register.
8286 Then add the constant to the reload register. */
8288 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8289 gen_reload (out, op1, opnum, type);
8290 insn = emit_insn (gen_add2_insn (out, op0));
8291 set_unique_reg_note (insn, REG_EQUIV, in);
8294 #ifdef SECONDARY_MEMORY_NEEDED
8295 /* If we need a memory location to do the move, do it that way. */
8296 else if ((REG_P (in)
8297 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8298 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8300 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8301 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8302 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8303 REGNO_REG_CLASS (reg_or_subregno (out)),
8306 /* Get the memory to use and rewrite both registers to its mode. */
8307 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8309 if (GET_MODE (loc) != GET_MODE (out))
8310 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8312 if (GET_MODE (loc) != GET_MODE (in))
8313 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8315 gen_reload (loc, in, opnum, type);
8316 gen_reload (out, loc, opnum, type);
8319 else if (REG_P (out) && UNARY_P (in))
8326 op1 = find_replacement (&XEXP (in, 0));
8327 if (op1 != XEXP (in, 0))
8328 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8330 /* First, try a plain SET. */
8331 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8335 /* If that failed, move the inner operand to the reload
8336 register, and try the same unop with the inner expression
8337 replaced with the reload register. */
8339 if (GET_MODE (op1) != GET_MODE (out))
8340 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8344 gen_reload (out_moded, op1, opnum, type);
8347 = gen_rtx_SET (VOIDmode, out,
8348 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8350 insn = emit_insn_if_valid_for_reload (insn);
8353 set_unique_reg_note (insn, REG_EQUIV, in);
8357 fatal_insn ("Failure trying to reload:", set);
8359 /* If IN is a simple operand, use gen_move_insn. */
8360 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8362 tem = emit_insn (gen_move_insn (out, in));
8363 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8364 mark_jump_label (in, tem, 0);
8367 #ifdef HAVE_reload_load_address
8368 else if (HAVE_reload_load_address)
8369 emit_insn (gen_reload_load_address (out, in));
8372 /* Otherwise, just write (set OUT IN) and hope for the best. */
8374 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8376 /* Return the first insn emitted.
8377 We can not just return get_last_insn, because there may have
8378 been multiple instructions emitted. Also note that gen_move_insn may
8379 emit more than one insn itself, so we can not assume that there is one
8380 insn emitted per emit_insn_before call. */
8382 return last ? NEXT_INSN (last) : get_insns ();
8385 /* Delete a previously made output-reload whose result we now believe
8386 is not needed. First we double-check.
8388 INSN is the insn now being processed.
8389 LAST_RELOAD_REG is the hard register number for which we want to delete
8390 the last output reload.
8391 J is the reload-number that originally used REG. The caller has made
8392 certain that reload J doesn't use REG any longer for input.
8393 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8396 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8398 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8399 rtx reg = spill_reg_stored_to[last_reload_reg];
8402 int n_inherited = 0;
8406 /* It is possible that this reload has been only used to set another reload
8407 we eliminated earlier and thus deleted this instruction too. */
8408 if (INSN_DELETED_P (output_reload_insn))
8411 /* Get the raw pseudo-register referred to. */
8413 while (GET_CODE (reg) == SUBREG)
8414 reg = SUBREG_REG (reg);
8415 substed = reg_equiv_memory_loc[REGNO (reg)];
8417 /* This is unsafe if the operand occurs more often in the current
8418 insn than it is inherited. */
8419 for (k = n_reloads - 1; k >= 0; k--)
8421 rtx reg2 = rld[k].in;
8424 if (MEM_P (reg2) || reload_override_in[k])
8425 reg2 = rld[k].in_reg;
8427 if (rld[k].out && ! rld[k].out_reg)
8428 reg2 = XEXP (rld[k].in_reg, 0);
8430 while (GET_CODE (reg2) == SUBREG)
8431 reg2 = SUBREG_REG (reg2);
8432 if (rtx_equal_p (reg2, reg))
8434 if (reload_inherited[k] || reload_override_in[k] || k == j)
8440 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8441 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8442 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8445 n_occurrences += count_occurrences (PATTERN (insn),
8446 eliminate_regs (substed, 0,
8448 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8450 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8451 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8453 if (n_occurrences > n_inherited)
8456 /* If the pseudo-reg we are reloading is no longer referenced
8457 anywhere between the store into it and here,
8458 and we're within the same basic block, then the value can only
8459 pass through the reload reg and end up here.
8460 Otherwise, give up--return. */
8461 for (i1 = NEXT_INSN (output_reload_insn);
8462 i1 != insn; i1 = NEXT_INSN (i1))
8464 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8466 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8467 && reg_mentioned_p (reg, PATTERN (i1)))
8469 /* If this is USE in front of INSN, we only have to check that
8470 there are no more references than accounted for by inheritance. */
8471 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8473 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8474 i1 = NEXT_INSN (i1);
8476 if (n_occurrences <= n_inherited && i1 == insn)
8482 /* We will be deleting the insn. Remove the spill reg information. */
8483 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8485 spill_reg_store[last_reload_reg + k] = 0;
8486 spill_reg_stored_to[last_reload_reg + k] = 0;
8489 /* The caller has already checked that REG dies or is set in INSN.
8490 It has also checked that we are optimizing, and thus some
8491 inaccuracies in the debugging information are acceptable.
8492 So we could just delete output_reload_insn. But in some cases
8493 we can improve the debugging information without sacrificing
8494 optimization - maybe even improving the code: See if the pseudo
8495 reg has been completely replaced with reload regs. If so, delete
8496 the store insn and forget we had a stack slot for the pseudo. */
8497 if (rld[j].out != rld[j].in
8498 && REG_N_DEATHS (REGNO (reg)) == 1
8499 && REG_N_SETS (REGNO (reg)) == 1
8500 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8501 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8505 /* We know that it was used only between here and the beginning of
8506 the current basic block. (We also know that the last use before
8507 INSN was the output reload we are thinking of deleting, but never
8508 mind that.) Search that range; see if any ref remains. */
8509 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8511 rtx set = single_set (i2);
8513 /* Uses which just store in the pseudo don't count,
8514 since if they are the only uses, they are dead. */
8515 if (set != 0 && SET_DEST (set) == reg)
8520 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8521 && reg_mentioned_p (reg, PATTERN (i2)))
8523 /* Some other ref remains; just delete the output reload we
8525 delete_address_reloads (output_reload_insn, insn);
8526 delete_insn (output_reload_insn);
8531 /* Delete the now-dead stores into this pseudo. Note that this
8532 loop also takes care of deleting output_reload_insn. */
8533 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8535 rtx set = single_set (i2);
8537 if (set != 0 && SET_DEST (set) == reg)
8539 delete_address_reloads (i2, insn);
8547 /* For the debugging info, say the pseudo lives in this reload reg. */
8548 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8549 if (flag_ira && optimize)
8550 /* Inform IRA about the change. */
8551 ira_mark_allocation_change (REGNO (reg));
8552 alter_reg (REGNO (reg), -1, false);
8556 delete_address_reloads (output_reload_insn, insn);
8557 delete_insn (output_reload_insn);
8561 /* We are going to delete DEAD_INSN. Recursively delete loads of
8562 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8563 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8565 delete_address_reloads (rtx dead_insn, rtx current_insn)
8567 rtx set = single_set (dead_insn);
8568 rtx set2, dst, prev, next;
8571 rtx dst = SET_DEST (set);
8573 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8575 /* If we deleted the store from a reloaded post_{in,de}c expression,
8576 we can delete the matching adds. */
8577 prev = PREV_INSN (dead_insn);
8578 next = NEXT_INSN (dead_insn);
8579 if (! prev || ! next)
8581 set = single_set (next);
8582 set2 = single_set (prev);
8584 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8585 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8586 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8588 dst = SET_DEST (set);
8589 if (! rtx_equal_p (dst, SET_DEST (set2))
8590 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8591 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8592 || (INTVAL (XEXP (SET_SRC (set), 1))
8593 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8595 delete_related_insns (prev);
8596 delete_related_insns (next);
8599 /* Subfunction of delete_address_reloads: process registers found in X. */
8601 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8603 rtx prev, set, dst, i2;
8605 enum rtx_code code = GET_CODE (x);
8609 const char *fmt = GET_RTX_FORMAT (code);
8610 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8613 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8614 else if (fmt[i] == 'E')
8616 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8617 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8624 if (spill_reg_order[REGNO (x)] < 0)
8627 /* Scan backwards for the insn that sets x. This might be a way back due
8629 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8631 code = GET_CODE (prev);
8632 if (code == CODE_LABEL || code == JUMP_INSN)
8636 if (reg_set_p (x, PATTERN (prev)))
8638 if (reg_referenced_p (x, PATTERN (prev)))
8641 if (! prev || INSN_UID (prev) < reload_first_uid)
8643 /* Check that PREV only sets the reload register. */
8644 set = single_set (prev);
8647 dst = SET_DEST (set);
8649 || ! rtx_equal_p (dst, x))
8651 if (! reg_set_p (dst, PATTERN (dead_insn)))
8653 /* Check if DST was used in a later insn -
8654 it might have been inherited. */
8655 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8661 if (reg_referenced_p (dst, PATTERN (i2)))
8663 /* If there is a reference to the register in the current insn,
8664 it might be loaded in a non-inherited reload. If no other
8665 reload uses it, that means the register is set before
8667 if (i2 == current_insn)
8669 for (j = n_reloads - 1; j >= 0; j--)
8670 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8671 || reload_override_in[j] == dst)
8673 for (j = n_reloads - 1; j >= 0; j--)
8674 if (rld[j].in && rld[j].reg_rtx == dst)
8683 /* If DST is still live at CURRENT_INSN, check if it is used for
8684 any reload. Note that even if CURRENT_INSN sets DST, we still
8685 have to check the reloads. */
8686 if (i2 == current_insn)
8688 for (j = n_reloads - 1; j >= 0; j--)
8689 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8690 || reload_override_in[j] == dst)
8692 /* ??? We can't finish the loop here, because dst might be
8693 allocated to a pseudo in this block if no reload in this
8694 block needs any of the classes containing DST - see
8695 spill_hard_reg. There is no easy way to tell this, so we
8696 have to scan till the end of the basic block. */
8698 if (reg_set_p (dst, PATTERN (i2)))
8702 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8703 reg_reloaded_contents[REGNO (dst)] = -1;
8707 /* Output reload-insns to reload VALUE into RELOADREG.
8708 VALUE is an autoincrement or autodecrement RTX whose operand
8709 is a register or memory location;
8710 so reloading involves incrementing that location.
8711 IN is either identical to VALUE, or some cheaper place to reload from.
8713 INC_AMOUNT is the number to increment or decrement by (always positive).
8714 This cannot be deduced from VALUE.
8716 Return the instruction that stores into RELOADREG. */
8719 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8721 /* REG or MEM to be copied and incremented. */
8722 rtx incloc = find_replacement (&XEXP (value, 0));
8723 /* Nonzero if increment after copying. */
8724 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8725 || GET_CODE (value) == POST_MODIFY);
8731 rtx real_in = in == value ? incloc : in;
8733 /* No hard register is equivalent to this register after
8734 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8735 we could inc/dec that register as well (maybe even using it for
8736 the source), but I'm not sure it's worth worrying about. */
8738 reg_last_reload_reg[REGNO (incloc)] = 0;
8740 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8742 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8743 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8747 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8748 inc_amount = -inc_amount;
8750 inc = GEN_INT (inc_amount);
8753 /* If this is post-increment, first copy the location to the reload reg. */
8754 if (post && real_in != reloadreg)
8755 emit_insn (gen_move_insn (reloadreg, real_in));
8759 /* See if we can directly increment INCLOC. Use a method similar to
8760 that in gen_reload. */
8762 last = get_last_insn ();
8763 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8764 gen_rtx_PLUS (GET_MODE (incloc),
8767 code = recog_memoized (add_insn);
8770 extract_insn (add_insn);
8771 if (constrain_operands (1))
8773 /* If this is a pre-increment and we have incremented the value
8774 where it lives, copy the incremented value to RELOADREG to
8775 be used as an address. */
8778 emit_insn (gen_move_insn (reloadreg, incloc));
8783 delete_insns_since (last);
8786 /* If couldn't do the increment directly, must increment in RELOADREG.
8787 The way we do this depends on whether this is pre- or post-increment.
8788 For pre-increment, copy INCLOC to the reload register, increment it
8789 there, then save back. */
8793 if (in != reloadreg)
8794 emit_insn (gen_move_insn (reloadreg, real_in));
8795 emit_insn (gen_add2_insn (reloadreg, inc));
8796 store = emit_insn (gen_move_insn (incloc, reloadreg));
8801 Because this might be a jump insn or a compare, and because RELOADREG
8802 may not be available after the insn in an input reload, we must do
8803 the incrementation before the insn being reloaded for.
8805 We have already copied IN to RELOADREG. Increment the copy in
8806 RELOADREG, save that back, then decrement RELOADREG so it has
8807 the original value. */
8809 emit_insn (gen_add2_insn (reloadreg, inc));
8810 store = emit_insn (gen_move_insn (incloc, reloadreg));
8811 if (GET_CODE (inc) == CONST_INT)
8812 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8814 emit_insn (gen_sub2_insn (reloadreg, inc));
8822 add_auto_inc_notes (rtx insn, rtx x)
8824 enum rtx_code code = GET_CODE (x);
8828 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8830 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8834 /* Scan all the operand sub-expressions. */
8835 fmt = GET_RTX_FORMAT (code);
8836 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8839 add_auto_inc_notes (insn, XEXP (x, i));
8840 else if (fmt[i] == 'E')
8841 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8842 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8847 /* Copy EH notes from an insn to its reloads. */
8849 copy_eh_notes (rtx insn, rtx x)
8851 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8854 for (; x != 0; x = NEXT_INSN (x))
8856 if (may_trap_p (PATTERN (x)))
8857 add_reg_note (x, REG_EH_REGION, XEXP (eh_note, 0));
8862 /* This is used by reload pass, that does emit some instructions after
8863 abnormal calls moving basic block end, but in fact it wants to emit
8864 them on the edge. Looks for abnormal call edges, find backward the
8865 proper call and fix the damage.
8867 Similar handle instructions throwing exceptions internally. */
8869 fixup_abnormal_edges (void)
8871 bool inserted = false;
8879 /* Look for cases we are interested in - calls or instructions causing
8881 FOR_EACH_EDGE (e, ei, bb->succs)
8883 if (e->flags & EDGE_ABNORMAL_CALL)
8885 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8886 == (EDGE_ABNORMAL | EDGE_EH))
8889 if (e && !CALL_P (BB_END (bb))
8890 && !can_throw_internal (BB_END (bb)))
8894 /* Get past the new insns generated. Allow notes, as the insns
8895 may be already deleted. */
8897 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8898 && !can_throw_internal (insn)
8899 && insn != BB_HEAD (bb))
8900 insn = PREV_INSN (insn);
8902 if (CALL_P (insn) || can_throw_internal (insn))
8906 stop = NEXT_INSN (BB_END (bb));
8908 insn = NEXT_INSN (insn);
8910 FOR_EACH_EDGE (e, ei, bb->succs)
8911 if (e->flags & EDGE_FALLTHRU)
8914 while (insn && insn != stop)
8916 next = NEXT_INSN (insn);
8921 /* Sometimes there's still the return value USE.
8922 If it's placed after a trapping call (i.e. that
8923 call is the last insn anyway), we have no fallthru
8924 edge. Simply delete this use and don't try to insert
8925 on the non-existent edge. */
8926 if (GET_CODE (PATTERN (insn)) != USE)
8928 /* We're not deleting it, we're moving it. */
8929 INSN_DELETED_P (insn) = 0;
8930 PREV_INSN (insn) = NULL_RTX;
8931 NEXT_INSN (insn) = NULL_RTX;
8933 insert_insn_on_edge (insn, e);
8937 else if (!BARRIER_P (insn))
8938 set_block_for_insn (insn, NULL);
8943 /* It may be that we don't find any such trapping insn. In this
8944 case we discovered quite late that the insn that had been
8945 marked as can_throw_internal in fact couldn't trap at all.
8946 So we should in fact delete the EH edges out of the block. */
8948 purge_dead_edges (bb);
8952 /* We've possibly turned single trapping insn into multiple ones. */
8953 if (flag_non_call_exceptions)
8956 blocks = sbitmap_alloc (last_basic_block);
8957 sbitmap_ones (blocks);
8958 find_many_sub_basic_blocks (blocks);
8959 sbitmap_free (blocks);
8963 commit_edge_insertions ();
8965 #ifdef ENABLE_CHECKING
8966 /* Verify that we didn't turn one trapping insn into many, and that
8967 we found and corrected all of the problems wrt fixups on the
8969 verify_flow_info ();
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