1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "insn-flags.h"
32 #include "insn-codes.h"
37 #include "basic-block.h"
45 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
46 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 #ifndef REGISTER_MOVE_COST
84 #define REGISTER_MOVE_COST(x, y) 2
88 #define LOCAL_REGNO(REGNO) 0
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static char *reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Element N is the constant value to which pseudo reg N is equivalent,
104 or zero if pseudo reg N is not equivalent to a constant.
105 find_reloads looks at this in order to replace pseudo reg N
106 with the constant it stands for. */
107 rtx *reg_equiv_constant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
116 This is used when the address is not valid as a memory address
117 (because its displacement is too big for the machine.) */
118 rtx *reg_equiv_address;
120 /* Element N is the memory slot to which pseudo reg N is equivalent,
121 or zero if pseudo reg N is not equivalent to a memory slot. */
124 /* Widest width in which each pseudo reg is referred to (via subreg). */
125 static unsigned int *reg_max_ref_width;
127 /* Element N is the list of insns that initialized reg N from its equivalent
128 constant or memory slot. */
129 static rtx *reg_equiv_init;
131 /* Vector to remember old contents of reg_renumber before spilling. */
132 static short *reg_old_renumber;
134 /* During reload_as_needed, element N contains the last pseudo regno reloaded
135 into hard register N. If that pseudo reg occupied more than one register,
136 reg_reloaded_contents points to that pseudo for each spill register in
137 use; all of these must remain set for an inheritance to occur. */
138 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
140 /* During reload_as_needed, element N contains the insn for which
141 hard register N was last used. Its contents are significant only
142 when reg_reloaded_valid is set for this register. */
143 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
145 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
146 static HARD_REG_SET reg_reloaded_valid;
147 /* Indicate if the register was dead at the end of the reload.
148 This is only valid if reg_reloaded_contents is set and valid. */
149 static HARD_REG_SET reg_reloaded_dead;
151 /* Number of spill-regs so far; number of valid elements of spill_regs. */
154 /* In parallel with spill_regs, contains REG rtx's for those regs.
155 Holds the last rtx used for any given reg, or 0 if it has never
156 been used for spilling yet. This rtx is reused, provided it has
158 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
160 /* In parallel with spill_regs, contains nonzero for a spill reg
161 that was stored after the last time it was used.
162 The precise value is the insn generated to do the store. */
163 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
165 /* This is the register that was stored with spill_reg_store. This is a
166 copy of reload_out / reload_out_reg when the value was stored; if
167 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
168 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
170 /* This table is the inverse mapping of spill_regs:
171 indexed by hard reg number,
172 it contains the position of that reg in spill_regs,
173 or -1 for something that is not in spill_regs.
175 ?!? This is no longer accurate. */
176 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
178 /* This reg set indicates registers that can't be used as spill registers for
179 the currently processed insn. These are the hard registers which are live
180 during the insn, but not allocated to pseudos, as well as fixed
182 static HARD_REG_SET bad_spill_regs;
184 /* These are the hard registers that can't be used as spill register for any
185 insn. This includes registers used for user variables and registers that
186 we can't eliminate. A register that appears in this set also can't be used
187 to retry register allocation. */
188 static HARD_REG_SET bad_spill_regs_global;
190 /* Describes order of use of registers for reloading
191 of spilled pseudo-registers. `n_spills' is the number of
192 elements that are actually valid; new ones are added at the end.
194 Both spill_regs and spill_reg_order are used on two occasions:
195 once during find_reload_regs, where they keep track of the spill registers
196 for a single insn, but also during reload_as_needed where they show all
197 the registers ever used by reload. For the latter case, the information
198 is calculated during finish_spills. */
199 static short spill_regs[FIRST_PSEUDO_REGISTER];
201 /* This vector of reg sets indicates, for each pseudo, which hard registers
202 may not be used for retrying global allocation because the register was
203 formerly spilled from one of them. If we allowed reallocating a pseudo to
204 a register that it was already allocated to, reload might not
206 static HARD_REG_SET *pseudo_previous_regs;
208 /* This vector of reg sets indicates, for each pseudo, which hard
209 registers may not be used for retrying global allocation because they
210 are used as spill registers during one of the insns in which the
212 static HARD_REG_SET *pseudo_forbidden_regs;
214 /* All hard regs that have been used as spill registers for any insn are
215 marked in this set. */
216 static HARD_REG_SET used_spill_regs;
218 /* Index of last register assigned as a spill register. We allocate in
219 a round-robin fashion. */
220 static int last_spill_reg;
222 /* Nonzero if indirect addressing is supported on the machine; this means
223 that spilling (REG n) does not require reloading it into a register in
224 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
225 value indicates the level of indirect addressing supported, e.g., two
226 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
228 static char spill_indirect_levels;
230 /* Nonzero if indirect addressing is supported when the innermost MEM is
231 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
232 which these are valid is the same as spill_indirect_levels, above. */
233 char indirect_symref_ok;
235 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
236 char double_reg_address_ok;
238 /* Record the stack slot for each spilled hard register. */
239 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
241 /* Width allocated so far for that stack slot. */
242 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
244 /* Record which pseudos needed to be spilled. */
245 static regset_head spilled_pseudos;
247 /* Used for communication between order_regs_for_reload and count_pseudo.
248 Used to avoid counting one pseudo twice. */
249 static regset_head pseudos_counted;
251 /* First uid used by insns created by reload in this function.
252 Used in find_equiv_reg. */
253 int reload_first_uid;
255 /* Flag set by local-alloc or global-alloc if anything is live in
256 a call-clobbered reg across calls. */
257 int caller_save_needed;
259 /* Set to 1 while reload_as_needed is operating.
260 Required by some machines to handle any generated moves differently. */
261 int reload_in_progress = 0;
263 /* These arrays record the insn_code of insns that may be needed to
264 perform input and output reloads of special objects. They provide a
265 place to pass a scratch register. */
266 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
267 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
269 /* This obstack is used for allocation of rtl during register elimination.
270 The allocated storage can be freed once find_reloads has processed the
272 struct obstack reload_obstack;
274 /* Points to the beginning of the reload_obstack. All insn_chain structures
275 are allocated first. */
276 char *reload_startobj;
278 /* The point after all insn_chain structures. Used to quickly deallocate
279 memory allocated in copy_reloads during calculate_needs_all_insns. */
280 char *reload_firstobj;
282 /* This points before all local rtl generated by register elimination.
283 Used to quickly free all memory after processing one insn. */
284 static char *reload_insn_firstobj;
286 #define obstack_chunk_alloc xmalloc
287 #define obstack_chunk_free free
289 /* List of insn_chain instructions, one for every insn that reload needs to
291 struct insn_chain *reload_insn_chain;
294 extern tree current_function_decl;
296 extern union tree_node *current_function_decl;
299 /* List of all insns needing reloads. */
300 static struct insn_chain *insns_need_reload;
302 /* This structure is used to record information about register eliminations.
303 Each array entry describes one possible way of eliminating a register
304 in favor of another. If there is more than one way of eliminating a
305 particular register, the most preferred should be specified first. */
309 int from; /* Register number to be eliminated. */
310 int to; /* Register number used as replacement. */
311 int initial_offset; /* Initial difference between values. */
312 int can_eliminate; /* Non-zero if this elimination can be done. */
313 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
314 insns made by reload. */
315 int offset; /* Current offset between the two regs. */
316 int previous_offset; /* Offset at end of previous insn. */
317 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
318 rtx from_rtx; /* REG rtx for the register to be eliminated.
319 We cannot simply compare the number since
320 we might then spuriously replace a hard
321 register corresponding to a pseudo
322 assigned to the reg to be eliminated. */
323 rtx to_rtx; /* REG rtx for the replacement. */
326 static struct elim_table *reg_eliminate = 0;
328 /* This is an intermediate structure to initialize the table. It has
329 exactly the members provided by ELIMINABLE_REGS. */
330 static struct elim_table_1
334 } reg_eliminate_1[] =
336 /* If a set of eliminable registers was specified, define the table from it.
337 Otherwise, default to the normal case of the frame pointer being
338 replaced by the stack pointer. */
340 #ifdef ELIMINABLE_REGS
343 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
346 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
348 /* Record the number of pending eliminations that have an offset not equal
349 to their initial offset. If non-zero, we use a new copy of each
350 replacement result in any insns encountered. */
351 int num_not_at_initial_offset;
353 /* Count the number of registers that we may be able to eliminate. */
354 static int num_eliminable;
355 /* And the number of registers that are equivalent to a constant that
356 can be eliminated to frame_pointer / arg_pointer + constant. */
357 static int num_eliminable_invariants;
359 /* For each label, we record the offset of each elimination. If we reach
360 a label by more than one path and an offset differs, we cannot do the
361 elimination. This information is indexed by the number of the label.
362 The first table is an array of flags that records whether we have yet
363 encountered a label and the second table is an array of arrays, one
364 entry in the latter array for each elimination. */
366 static char *offsets_known_at;
367 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
369 /* Number of labels in the current function. */
371 static int num_labels;
373 static void maybe_fix_stack_asms PARAMS ((void));
374 static void copy_reloads PARAMS ((struct insn_chain *));
375 static void calculate_needs_all_insns PARAMS ((int));
376 static int find_reg PARAMS ((struct insn_chain *, int));
377 static void find_reload_regs PARAMS ((struct insn_chain *));
378 static void select_reload_regs PARAMS ((void));
379 static void delete_caller_save_insns PARAMS ((void));
381 static void spill_failure PARAMS ((rtx, enum reg_class));
382 static void count_spilled_pseudo PARAMS ((int, int, int));
383 static void delete_dead_insn PARAMS ((rtx));
384 static void alter_reg PARAMS ((int, int));
385 static void set_label_offsets PARAMS ((rtx, rtx, int));
386 static void check_eliminable_occurrences PARAMS ((rtx));
387 static void elimination_effects PARAMS ((rtx, enum machine_mode));
388 static int eliminate_regs_in_insn PARAMS ((rtx, int));
389 static void update_eliminable_offsets PARAMS ((void));
390 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
391 static void set_initial_elim_offsets PARAMS ((void));
392 static void verify_initial_elim_offsets PARAMS ((void));
393 static void set_initial_label_offsets PARAMS ((void));
394 static void set_offsets_for_label PARAMS ((rtx));
395 static void init_elim_table PARAMS ((void));
396 static void update_eliminables PARAMS ((HARD_REG_SET *));
397 static void spill_hard_reg PARAMS ((unsigned int, int));
398 static int finish_spills PARAMS ((int));
399 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
400 static void scan_paradoxical_subregs PARAMS ((rtx));
401 static void count_pseudo PARAMS ((int));
402 static void order_regs_for_reload PARAMS ((struct insn_chain *));
403 static void reload_as_needed PARAMS ((int));
404 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
405 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
406 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
409 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
412 static int reload_reg_free_p PARAMS ((unsigned int, int,
414 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
415 rtx, rtx, int, int));
416 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
418 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
420 static void failed_reload PARAMS ((rtx, int));
421 static int set_reload_reg PARAMS ((int, int));
422 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
423 static void choose_reload_regs PARAMS ((struct insn_chain *));
424 static void merge_assigned_reloads PARAMS ((rtx));
425 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
426 struct reload *, rtx, int));
427 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
428 struct reload *, int));
429 static void do_input_reload PARAMS ((struct insn_chain *,
430 struct reload *, int));
431 static void do_output_reload PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void emit_reload_insns PARAMS ((struct insn_chain *));
434 static void delete_output_reload PARAMS ((rtx, int, int));
435 static void delete_address_reloads PARAMS ((rtx, rtx));
436 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
437 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
438 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
439 static void reload_cse_regs_1 PARAMS ((rtx));
440 static int reload_cse_noop_set_p PARAMS ((rtx));
441 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
442 static int reload_cse_simplify_operands PARAMS ((rtx));
443 static void reload_combine PARAMS ((void));
444 static void reload_combine_note_use PARAMS ((rtx *, rtx));
445 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
446 static void reload_cse_move2add PARAMS ((rtx));
447 static void move2add_note_store PARAMS ((rtx, rtx, void *));
449 static void add_auto_inc_notes PARAMS ((rtx, rtx));
451 static rtx gen_mode_int PARAMS ((enum machine_mode,
453 static void failed_reload PARAMS ((rtx, int));
454 static int set_reload_reg PARAMS ((int, int));
455 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
456 static void reload_cse_simplify PARAMS ((rtx));
457 extern void dump_needs PARAMS ((struct insn_chain *));
459 /* Initialize the reload pass once per compilation. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode,
474 LAST_VIRTUAL_REGISTER + 1),
476 spill_indirect_levels = 0;
478 while (memory_address_p (QImode, tem))
480 spill_indirect_levels++;
481 tem = gen_rtx_MEM (Pmode, tem);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
487 indirect_symref_ok = memory_address_p (QImode, tem);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
493 tem = gen_rtx_PLUS (Pmode,
494 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
495 gen_rtx_REG (Pmode, i));
497 /* This way, we make sure that reg+reg is an offsettable address. */
498 tem = plus_constant (tem, 4);
500 if (memory_address_p (QImode, tem))
502 double_reg_address_ok = 1;
507 /* Initialize obstack for our rtl allocation. */
508 gcc_obstack_init (&reload_obstack);
509 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
511 INIT_REG_SET (&spilled_pseudos);
512 INIT_REG_SET (&pseudos_counted);
515 /* List of insn chains that are currently unused. */
516 static struct insn_chain *unused_insn_chains = 0;
518 /* Allocate an empty insn_chain structure. */
522 struct insn_chain *c;
524 if (unused_insn_chains == 0)
526 c = (struct insn_chain *)
527 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
528 INIT_REG_SET (&c->live_throughout);
529 INIT_REG_SET (&c->dead_or_set);
533 c = unused_insn_chains;
534 unused_insn_chains = c->next;
536 c->is_caller_save_insn = 0;
537 c->need_operand_change = 0;
543 /* Small utility function to set all regs in hard reg set TO which are
544 allocated to pseudos in regset FROM. */
547 compute_use_by_pseudos (to, from)
553 EXECUTE_IF_SET_IN_REG_SET
554 (from, FIRST_PSEUDO_REGISTER, regno,
556 int r = reg_renumber[regno];
561 /* reload_combine uses the information from
562 BASIC_BLOCK->global_live_at_start, which might still
563 contain registers that have not actually been allocated
564 since they have an equivalence. */
565 if (! reload_completed)
570 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
572 SET_HARD_REG_BIT (*to, r + nregs);
577 /* Global variables used by reload and its subroutines. */
579 /* Set during calculate_needs if an insn needs register elimination. */
580 static int something_needs_elimination;
581 /* Set during calculate_needs if an insn needs an operand changed. */
582 int something_needs_operands_changed;
584 /* Nonzero means we couldn't get enough spill regs. */
587 /* Main entry point for the reload pass.
589 FIRST is the first insn of the function being compiled.
591 GLOBAL nonzero means we were called from global_alloc
592 and should attempt to reallocate any pseudoregs that we
593 displace from hard regs we will use for reloads.
594 If GLOBAL is zero, we do not have enough information to do that,
595 so any pseudo reg that is spilled must go to the stack.
597 Return value is nonzero if reload failed
598 and we must not do any more for this function. */
601 reload (first, global)
607 register struct elim_table *ep;
609 /* The two pointers used to track the true location of the memory used
610 for label offsets. */
611 char *real_known_ptr = NULL_PTR;
612 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
614 /* Make sure even insns with volatile mem refs are recognizable. */
619 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
621 /* Make sure that the last insn in the chain
622 is not something that needs reloading. */
623 emit_note (NULL_PTR, NOTE_INSN_DELETED);
625 /* Enable find_equiv_reg to distinguish insns made by reload. */
626 reload_first_uid = get_max_uid ();
628 #ifdef SECONDARY_MEMORY_NEEDED
629 /* Initialize the secondary memory table. */
630 clear_secondary_mem ();
633 /* We don't have a stack slot for any spill reg yet. */
634 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
635 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
637 /* Initialize the save area information for caller-save, in case some
641 /* Compute which hard registers are now in use
642 as homes for pseudo registers.
643 This is done here rather than (eg) in global_alloc
644 because this point is reached even if not optimizing. */
645 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
648 /* A function that receives a nonlocal goto must save all call-saved
650 if (current_function_has_nonlocal_label)
651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
652 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
653 regs_ever_live[i] = 1;
655 /* Find all the pseudo registers that didn't get hard regs
656 but do have known equivalent constants or memory slots.
657 These include parameters (known equivalent to parameter slots)
658 and cse'd or loop-moved constant memory addresses.
660 Record constant equivalents in reg_equiv_constant
661 so they will be substituted by find_reloads.
662 Record memory equivalents in reg_mem_equiv so they can
663 be substituted eventually by altering the REG-rtx's. */
665 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
666 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
667 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
668 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
669 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
670 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
671 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
672 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
673 pseudo_forbidden_regs
674 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
676 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
678 CLEAR_HARD_REG_SET (bad_spill_regs_global);
680 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
681 Also find all paradoxical subregs and find largest such for each pseudo.
682 On machines with small register classes, record hard registers that
683 are used for user variables. These can never be used for spills.
684 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
685 caller-saved registers must be marked live. */
687 num_eliminable_invariants = 0;
688 for (insn = first; insn; insn = NEXT_INSN (insn))
690 rtx set = single_set (insn);
692 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
693 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i])
696 regs_ever_live[i] = 1;
698 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
700 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
702 #ifdef LEGITIMATE_PIC_OPERAND_P
703 && (! function_invariant_p (XEXP (note, 0))
705 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
709 rtx x = XEXP (note, 0);
710 i = REGNO (SET_DEST (set));
711 if (i > LAST_VIRTUAL_REGISTER)
713 if (GET_CODE (x) == MEM)
715 /* If the operand is a PLUS, the MEM may be shared,
716 so make sure we have an unshared copy here. */
717 if (GET_CODE (XEXP (x, 0)) == PLUS)
720 reg_equiv_memory_loc[i] = x;
722 else if (function_invariant_p (x))
724 if (GET_CODE (x) == PLUS)
726 /* This is PLUS of frame pointer and a constant,
727 and might be shared. Unshare it. */
728 reg_equiv_constant[i] = copy_rtx (x);
729 num_eliminable_invariants++;
731 else if (x == frame_pointer_rtx
732 || x == arg_pointer_rtx)
734 reg_equiv_constant[i] = x;
735 num_eliminable_invariants++;
737 else if (LEGITIMATE_CONSTANT_P (x))
738 reg_equiv_constant[i] = x;
740 reg_equiv_memory_loc[i]
741 = force_const_mem (GET_MODE (SET_DEST (set)), x);
746 /* If this register is being made equivalent to a MEM
747 and the MEM is not SET_SRC, the equivalencing insn
748 is one with the MEM as a SET_DEST and it occurs later.
749 So don't mark this insn now. */
750 if (GET_CODE (x) != MEM
751 || rtx_equal_p (SET_SRC (set), x))
753 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
758 /* If this insn is setting a MEM from a register equivalent to it,
759 this is the equivalencing insn. */
760 else if (set && GET_CODE (SET_DEST (set)) == MEM
761 && GET_CODE (SET_SRC (set)) == REG
762 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
763 && rtx_equal_p (SET_DEST (set),
764 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
765 reg_equiv_init[REGNO (SET_SRC (set))]
766 = gen_rtx_INSN_LIST (VOIDmode, insn,
767 reg_equiv_init[REGNO (SET_SRC (set))]);
770 scan_paradoxical_subregs (PATTERN (insn));
775 num_labels = max_label_num () - get_first_label_num ();
777 /* Allocate the tables used to store offset information at labels. */
778 /* We used to use alloca here, but the size of what it would try to
779 allocate would occasionally cause it to exceed the stack limit and
780 cause a core dump. */
781 real_known_ptr = xmalloc (num_labels);
783 = (int (*)[NUM_ELIMINABLE_REGS])
784 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
786 offsets_known_at = real_known_ptr - get_first_label_num ();
788 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
790 /* Alter each pseudo-reg rtx to contain its hard reg number.
791 Assign stack slots to the pseudos that lack hard regs or equivalents.
792 Do not touch virtual registers. */
794 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
797 /* If we have some registers we think can be eliminated, scan all insns to
798 see if there is an insn that sets one of these registers to something
799 other than itself plus a constant. If so, the register cannot be
800 eliminated. Doing this scan here eliminates an extra pass through the
801 main reload loop in the most common case where register elimination
803 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
804 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
805 || GET_CODE (insn) == CALL_INSN)
806 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
808 maybe_fix_stack_asms ();
810 insns_need_reload = 0;
811 something_needs_elimination = 0;
813 /* Initialize to -1, which means take the first spill register. */
816 /* Spill any hard regs that we know we can't eliminate. */
817 CLEAR_HARD_REG_SET (used_spill_regs);
818 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
819 if (! ep->can_eliminate)
820 spill_hard_reg (ep->from, 1);
822 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
823 if (frame_pointer_needed)
824 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
826 finish_spills (global);
828 /* From now on, we may need to generate moves differently. We may also
829 allow modifications of insns which cause them to not be recognized.
830 Any such modifications will be cleaned up during reload itself. */
831 reload_in_progress = 1;
833 /* This loop scans the entire function each go-round
834 and repeats until one repetition spills no additional hard regs. */
837 int something_changed;
840 HOST_WIDE_INT starting_frame_size;
842 /* Round size of stack frame to stack_alignment_needed. This must be done
843 here because the stack size may be a part of the offset computation
844 for register elimination, and there might have been new stack slots
845 created in the last iteration of this loop. */
846 if (cfun->stack_alignment_needed)
847 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
849 starting_frame_size = get_frame_size ();
851 set_initial_elim_offsets ();
852 set_initial_label_offsets ();
854 /* For each pseudo register that has an equivalent location defined,
855 try to eliminate any eliminable registers (such as the frame pointer)
856 assuming initial offsets for the replacement register, which
859 If the resulting location is directly addressable, substitute
860 the MEM we just got directly for the old REG.
862 If it is not addressable but is a constant or the sum of a hard reg
863 and constant, it is probably not addressable because the constant is
864 out of range, in that case record the address; we will generate
865 hairy code to compute the address in a register each time it is
866 needed. Similarly if it is a hard register, but one that is not
867 valid as an address register.
869 If the location is not addressable, but does not have one of the
870 above forms, assign a stack slot. We have to do this to avoid the
871 potential of producing lots of reloads if, e.g., a location involves
872 a pseudo that didn't get a hard register and has an equivalent memory
873 location that also involves a pseudo that didn't get a hard register.
875 Perhaps at some point we will improve reload_when_needed handling
876 so this problem goes away. But that's very hairy. */
878 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
879 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
881 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
883 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
885 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
886 else if (CONSTANT_P (XEXP (x, 0))
887 || (GET_CODE (XEXP (x, 0)) == REG
888 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
889 || (GET_CODE (XEXP (x, 0)) == PLUS
890 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
891 && (REGNO (XEXP (XEXP (x, 0), 0))
892 < FIRST_PSEUDO_REGISTER)
893 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
894 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
897 /* Make a new stack slot. Then indicate that something
898 changed so we go back and recompute offsets for
899 eliminable registers because the allocation of memory
900 below might change some offset. reg_equiv_{mem,address}
901 will be set up for this pseudo on the next pass around
903 reg_equiv_memory_loc[i] = 0;
904 reg_equiv_init[i] = 0;
909 if (caller_save_needed)
912 /* If we allocated another stack slot, redo elimination bookkeeping. */
913 if (starting_frame_size != get_frame_size ())
916 if (caller_save_needed)
918 save_call_clobbered_regs ();
919 /* That might have allocated new insn_chain structures. */
920 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
923 calculate_needs_all_insns (global);
925 CLEAR_REG_SET (&spilled_pseudos);
928 something_changed = 0;
930 /* If we allocated any new memory locations, make another pass
931 since it might have changed elimination offsets. */
932 if (starting_frame_size != get_frame_size ())
933 something_changed = 1;
936 HARD_REG_SET to_spill;
937 CLEAR_HARD_REG_SET (to_spill);
938 update_eliminables (&to_spill);
939 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
940 if (TEST_HARD_REG_BIT (to_spill, i))
942 spill_hard_reg (i, 1);
945 /* Regardless of the state of spills, if we previously had
946 a register that we thought we could eliminate, but no can
947 not eliminate, we must run another pass.
949 Consider pseudos which have an entry in reg_equiv_* which
950 reference an eliminable register. We must make another pass
951 to update reg_equiv_* so that we do not substitute in the
952 old value from when we thought the elimination could be
954 something_changed = 1;
958 select_reload_regs ();
962 if (insns_need_reload != 0 || did_spill)
963 something_changed |= finish_spills (global);
965 if (! something_changed)
968 if (caller_save_needed)
969 delete_caller_save_insns ();
971 obstack_free (&reload_obstack, reload_firstobj);
974 /* If global-alloc was run, notify it of any register eliminations we have
977 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
978 if (ep->can_eliminate)
979 mark_elimination (ep->from, ep->to);
981 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
982 If that insn didn't set the register (i.e., it copied the register to
983 memory), just delete that insn instead of the equivalencing insn plus
984 anything now dead. If we call delete_dead_insn on that insn, we may
985 delete the insn that actually sets the register if the register dies
986 there and that is incorrect. */
988 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
990 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
993 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
995 rtx equiv_insn = XEXP (list, 0);
996 if (GET_CODE (equiv_insn) == NOTE)
998 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
999 delete_dead_insn (equiv_insn);
1002 PUT_CODE (equiv_insn, NOTE);
1003 NOTE_SOURCE_FILE (equiv_insn) = 0;
1004 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1010 /* Use the reload registers where necessary
1011 by generating move instructions to move the must-be-register
1012 values into or out of the reload registers. */
1014 if (insns_need_reload != 0 || something_needs_elimination
1015 || something_needs_operands_changed)
1017 int old_frame_size = get_frame_size ();
1019 reload_as_needed (global);
1021 if (old_frame_size != get_frame_size ())
1025 verify_initial_elim_offsets ();
1028 /* If we were able to eliminate the frame pointer, show that it is no
1029 longer live at the start of any basic block. If it ls live by
1030 virtue of being in a pseudo, that pseudo will be marked live
1031 and hence the frame pointer will be known to be live via that
1034 if (! frame_pointer_needed)
1035 for (i = 0; i < n_basic_blocks; i++)
1036 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1037 HARD_FRAME_POINTER_REGNUM);
1039 /* Come here (with failure set nonzero) if we can't get enough spill regs
1040 and we decide not to abort about it. */
1043 CLEAR_REG_SET (&spilled_pseudos);
1044 reload_in_progress = 0;
1046 /* Now eliminate all pseudo regs by modifying them into
1047 their equivalent memory references.
1048 The REG-rtx's for the pseudos are modified in place,
1049 so all insns that used to refer to them now refer to memory.
1051 For a reg that has a reg_equiv_address, all those insns
1052 were changed by reloading so that no insns refer to it any longer;
1053 but the DECL_RTL of a variable decl may refer to it,
1054 and if so this causes the debugging info to mention the variable. */
1056 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1061 int is_readonly = 0;
1063 if (reg_equiv_memory_loc[i])
1065 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1066 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1067 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1070 if (reg_equiv_mem[i])
1071 addr = XEXP (reg_equiv_mem[i], 0);
1073 if (reg_equiv_address[i])
1074 addr = reg_equiv_address[i];
1078 if (reg_renumber[i] < 0)
1080 rtx reg = regno_reg_rtx[i];
1081 PUT_CODE (reg, MEM);
1082 XEXP (reg, 0) = addr;
1083 REG_USERVAR_P (reg) = 0;
1084 RTX_UNCHANGING_P (reg) = is_readonly;
1085 MEM_IN_STRUCT_P (reg) = in_struct;
1086 MEM_SCALAR_P (reg) = is_scalar;
1087 /* We have no alias information about this newly created
1089 MEM_ALIAS_SET (reg) = 0;
1091 else if (reg_equiv_mem[i])
1092 XEXP (reg_equiv_mem[i], 0) = addr;
1096 /* We must set reload_completed now since the cleanup_subreg_operands call
1097 below will re-recognize each insn and reload may have generated insns
1098 which are only valid during and after reload. */
1099 reload_completed = 1;
1101 /* Make a pass over all the insns and delete all USEs which we inserted
1102 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1103 notes. Delete all CLOBBER insns that don't refer to the return value
1104 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1105 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1106 and regenerate REG_INC notes that may have been moved around. */
1108 for (insn = first; insn; insn = NEXT_INSN (insn))
1113 if ((GET_CODE (PATTERN (insn)) == USE
1114 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1115 || (GET_CODE (PATTERN (insn)) == CLOBBER
1116 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1117 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1119 PUT_CODE (insn, NOTE);
1120 NOTE_SOURCE_FILE (insn) = 0;
1121 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1125 pnote = ®_NOTES (insn);
1128 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1129 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1130 || REG_NOTE_KIND (*pnote) == REG_INC
1131 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1132 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1133 *pnote = XEXP (*pnote, 1);
1135 pnote = &XEXP (*pnote, 1);
1139 add_auto_inc_notes (insn, PATTERN (insn));
1142 /* And simplify (subreg (reg)) if it appears as an operand. */
1143 cleanup_subreg_operands (insn);
1146 /* If we are doing stack checking, give a warning if this function's
1147 frame size is larger than we expect. */
1148 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1150 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1151 static int verbose_warned = 0;
1153 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1154 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1155 size += UNITS_PER_WORD;
1157 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1159 warning ("frame size too large for reliable stack checking");
1160 if (! verbose_warned)
1162 warning ("try reducing the number of local variables");
1168 /* Indicate that we no longer have known memory locations or constants. */
1169 if (reg_equiv_constant)
1170 free (reg_equiv_constant);
1171 reg_equiv_constant = 0;
1172 if (reg_equiv_memory_loc)
1173 free (reg_equiv_memory_loc);
1174 reg_equiv_memory_loc = 0;
1177 free (real_known_ptr);
1181 free (reg_equiv_mem);
1182 free (reg_equiv_init);
1183 free (reg_equiv_address);
1184 free (reg_max_ref_width);
1185 free (reg_old_renumber);
1186 free (pseudo_previous_regs);
1187 free (pseudo_forbidden_regs);
1189 CLEAR_HARD_REG_SET (used_spill_regs);
1190 for (i = 0; i < n_spills; i++)
1191 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1193 /* Free all the insn_chain structures at once. */
1194 obstack_free (&reload_obstack, reload_startobj);
1195 unused_insn_chains = 0;
1200 /* Yet another special case. Unfortunately, reg-stack forces people to
1201 write incorrect clobbers in asm statements. These clobbers must not
1202 cause the register to appear in bad_spill_regs, otherwise we'll call
1203 fatal_insn later. We clear the corresponding regnos in the live
1204 register sets to avoid this.
1205 The whole thing is rather sick, I'm afraid. */
1208 maybe_fix_stack_asms ()
1211 const char *constraints[MAX_RECOG_OPERANDS];
1212 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1213 struct insn_chain *chain;
1215 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1218 HARD_REG_SET clobbered, allowed;
1221 if (! INSN_P (chain->insn)
1222 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1224 pat = PATTERN (chain->insn);
1225 if (GET_CODE (pat) != PARALLEL)
1228 CLEAR_HARD_REG_SET (clobbered);
1229 CLEAR_HARD_REG_SET (allowed);
1231 /* First, make a mask of all stack regs that are clobbered. */
1232 for (i = 0; i < XVECLEN (pat, 0); i++)
1234 rtx t = XVECEXP (pat, 0, i);
1235 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1236 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1239 /* Get the operand values and constraints out of the insn. */
1240 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1241 constraints, operand_mode);
1243 /* For every operand, see what registers are allowed. */
1244 for (i = 0; i < noperands; i++)
1246 const char *p = constraints[i];
1247 /* For every alternative, we compute the class of registers allowed
1248 for reloading in CLS, and merge its contents into the reg set
1250 int cls = (int) NO_REGS;
1256 if (c == '\0' || c == ',' || c == '#')
1258 /* End of one alternative - mark the regs in the current
1259 class, and reset the class. */
1260 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1265 } while (c != '\0' && c != ',');
1273 case '=': case '+': case '*': case '%': case '?': case '!':
1274 case '0': case '1': case '2': case '3': case '4': case 'm':
1275 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1276 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1277 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1282 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1287 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1291 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1296 /* Those of the registers which are clobbered, but allowed by the
1297 constraints, must be usable as reload registers. So clear them
1298 out of the life information. */
1299 AND_HARD_REG_SET (allowed, clobbered);
1300 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1301 if (TEST_HARD_REG_BIT (allowed, i))
1303 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1304 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1311 /* Copy the global variables n_reloads and rld into the corresponding elts
1314 copy_reloads (chain)
1315 struct insn_chain *chain;
1317 chain->n_reloads = n_reloads;
1319 = (struct reload *) obstack_alloc (&reload_obstack,
1320 n_reloads * sizeof (struct reload));
1321 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1322 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1325 /* Walk the chain of insns, and determine for each whether it needs reloads
1326 and/or eliminations. Build the corresponding insns_need_reload list, and
1327 set something_needs_elimination as appropriate. */
1329 calculate_needs_all_insns (global)
1332 struct insn_chain **pprev_reload = &insns_need_reload;
1333 struct insn_chain *chain, *next = 0;
1335 something_needs_elimination = 0;
1337 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1338 for (chain = reload_insn_chain; chain != 0; chain = next)
1340 rtx insn = chain->insn;
1344 /* Clear out the shortcuts. */
1345 chain->n_reloads = 0;
1346 chain->need_elim = 0;
1347 chain->need_reload = 0;
1348 chain->need_operand_change = 0;
1350 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1351 include REG_LABEL), we need to see what effects this has on the
1352 known offsets at labels. */
1354 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1355 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1356 set_label_offsets (insn, insn, 0);
1360 rtx old_body = PATTERN (insn);
1361 int old_code = INSN_CODE (insn);
1362 rtx old_notes = REG_NOTES (insn);
1363 int did_elimination = 0;
1364 int operands_changed = 0;
1365 rtx set = single_set (insn);
1367 /* Skip insns that only set an equivalence. */
1368 if (set && GET_CODE (SET_DEST (set)) == REG
1369 && reg_renumber[REGNO (SET_DEST (set))] < 0
1370 && reg_equiv_constant[REGNO (SET_DEST (set))])
1373 /* If needed, eliminate any eliminable registers. */
1374 if (num_eliminable || num_eliminable_invariants)
1375 did_elimination = eliminate_regs_in_insn (insn, 0);
1377 /* Analyze the instruction. */
1378 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1379 global, spill_reg_order);
1381 /* If a no-op set needs more than one reload, this is likely
1382 to be something that needs input address reloads. We
1383 can't get rid of this cleanly later, and it is of no use
1384 anyway, so discard it now.
1385 We only do this when expensive_optimizations is enabled,
1386 since this complements reload inheritance / output
1387 reload deletion, and it can make debugging harder. */
1388 if (flag_expensive_optimizations && n_reloads > 1)
1390 rtx set = single_set (insn);
1392 && SET_SRC (set) == SET_DEST (set)
1393 && GET_CODE (SET_SRC (set)) == REG
1394 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1396 PUT_CODE (insn, NOTE);
1397 NOTE_SOURCE_FILE (insn) = 0;
1398 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1399 /* Delete it from the reload chain */
1401 chain->prev->next = next;
1403 reload_insn_chain = next;
1405 next->prev = chain->prev;
1406 chain->next = unused_insn_chains;
1407 unused_insn_chains = chain;
1412 update_eliminable_offsets ();
1414 /* Remember for later shortcuts which insns had any reloads or
1415 register eliminations. */
1416 chain->need_elim = did_elimination;
1417 chain->need_reload = n_reloads > 0;
1418 chain->need_operand_change = operands_changed;
1420 /* Discard any register replacements done. */
1421 if (did_elimination)
1423 obstack_free (&reload_obstack, reload_insn_firstobj);
1424 PATTERN (insn) = old_body;
1425 INSN_CODE (insn) = old_code;
1426 REG_NOTES (insn) = old_notes;
1427 something_needs_elimination = 1;
1430 something_needs_operands_changed |= operands_changed;
1434 copy_reloads (chain);
1435 *pprev_reload = chain;
1436 pprev_reload = &chain->next_need_reload;
1443 /* Comparison function for qsort to decide which of two reloads
1444 should be handled first. *P1 and *P2 are the reload numbers. */
1447 reload_reg_class_lower (r1p, r2p)
1451 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1454 /* Consider required reloads before optional ones. */
1455 t = rld[r1].optional - rld[r2].optional;
1459 /* Count all solitary classes before non-solitary ones. */
1460 t = ((reg_class_size[(int) rld[r2].class] == 1)
1461 - (reg_class_size[(int) rld[r1].class] == 1));
1465 /* Aside from solitaires, consider all multi-reg groups first. */
1466 t = rld[r2].nregs - rld[r1].nregs;
1470 /* Consider reloads in order of increasing reg-class number. */
1471 t = (int) rld[r1].class - (int) rld[r2].class;
1475 /* If reloads are equally urgent, sort by reload number,
1476 so that the results of qsort leave nothing to chance. */
1480 /* The cost of spilling each hard reg. */
1481 static int spill_cost[FIRST_PSEUDO_REGISTER];
1483 /* When spilling multiple hard registers, we use SPILL_COST for the first
1484 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1485 only the first hard reg for a multi-reg pseudo. */
1486 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1488 /* Update the spill cost arrays, considering that pseudo REG is live. */
1494 int n_refs = REG_N_REFS (reg);
1495 int r = reg_renumber[reg];
1498 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1499 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1502 SET_REGNO_REG_SET (&pseudos_counted, reg);
1507 spill_add_cost[r] += n_refs;
1509 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1511 spill_cost[r + nregs] += n_refs;
1514 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1515 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1518 order_regs_for_reload (chain)
1519 struct insn_chain *chain;
1522 HARD_REG_SET used_by_pseudos;
1523 HARD_REG_SET used_by_pseudos2;
1525 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1527 memset (spill_cost, 0, sizeof spill_cost);
1528 memset (spill_add_cost, 0, sizeof spill_add_cost);
1530 /* Count number of uses of each hard reg by pseudo regs allocated to it
1531 and then order them by decreasing use. First exclude hard registers
1532 that are live in or across this insn. */
1534 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1535 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1536 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1537 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1539 /* Now find out which pseudos are allocated to it, and update
1541 CLEAR_REG_SET (&pseudos_counted);
1543 EXECUTE_IF_SET_IN_REG_SET
1544 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1548 EXECUTE_IF_SET_IN_REG_SET
1549 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1553 CLEAR_REG_SET (&pseudos_counted);
1556 /* Vector of reload-numbers showing the order in which the reloads should
1558 static short reload_order[MAX_RELOADS];
1560 /* This is used to keep track of the spill regs used in one insn. */
1561 static HARD_REG_SET used_spill_regs_local;
1563 /* We decided to spill hard register SPILLED, which has a size of
1564 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1565 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1566 update SPILL_COST/SPILL_ADD_COST. */
1569 count_spilled_pseudo (spilled, spilled_nregs, reg)
1570 int spilled, spilled_nregs, reg;
1572 int r = reg_renumber[reg];
1573 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1575 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1576 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1579 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1581 spill_add_cost[r] -= REG_N_REFS (reg);
1583 spill_cost[r + nregs] -= REG_N_REFS (reg);
1586 /* Find reload register to use for reload number ORDER. */
1589 find_reg (chain, order)
1590 struct insn_chain *chain;
1593 int rnum = reload_order[order];
1594 struct reload *rl = rld + rnum;
1595 int best_cost = INT_MAX;
1599 HARD_REG_SET not_usable;
1600 HARD_REG_SET used_by_other_reload;
1602 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1603 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1604 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1606 CLEAR_HARD_REG_SET (used_by_other_reload);
1607 for (k = 0; k < order; k++)
1609 int other = reload_order[k];
1611 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1612 for (j = 0; j < rld[other].nregs; j++)
1613 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1616 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1618 unsigned int regno = i;
1620 if (! TEST_HARD_REG_BIT (not_usable, regno)
1621 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1622 && HARD_REGNO_MODE_OK (regno, rl->mode))
1624 int this_cost = spill_cost[regno];
1626 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1628 for (j = 1; j < this_nregs; j++)
1630 this_cost += spill_add_cost[regno + j];
1631 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1632 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1637 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1639 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1641 if (this_cost < best_cost
1642 /* Among registers with equal cost, prefer caller-saved ones, or
1643 use REG_ALLOC_ORDER if it is defined. */
1644 || (this_cost == best_cost
1645 #ifdef REG_ALLOC_ORDER
1646 && (inv_reg_alloc_order[regno]
1647 < inv_reg_alloc_order[best_reg])
1649 && call_used_regs[regno]
1650 && ! call_used_regs[best_reg]
1655 best_cost = this_cost;
1663 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1665 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1666 rl->regno = best_reg;
1668 EXECUTE_IF_SET_IN_REG_SET
1669 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1671 count_spilled_pseudo (best_reg, rl->nregs, j);
1674 EXECUTE_IF_SET_IN_REG_SET
1675 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1677 count_spilled_pseudo (best_reg, rl->nregs, j);
1680 for (i = 0; i < rl->nregs; i++)
1682 if (spill_cost[best_reg + i] != 0
1683 || spill_add_cost[best_reg + i] != 0)
1685 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1690 /* Find more reload regs to satisfy the remaining need of an insn, which
1692 Do it by ascending class number, since otherwise a reg
1693 might be spilled for a big class and might fail to count
1694 for a smaller class even though it belongs to that class. */
1697 find_reload_regs (chain)
1698 struct insn_chain *chain;
1702 /* In order to be certain of getting the registers we need,
1703 we must sort the reloads into order of increasing register class.
1704 Then our grabbing of reload registers will parallel the process
1705 that provided the reload registers. */
1706 for (i = 0; i < chain->n_reloads; i++)
1708 /* Show whether this reload already has a hard reg. */
1709 if (chain->rld[i].reg_rtx)
1711 int regno = REGNO (chain->rld[i].reg_rtx);
1712 chain->rld[i].regno = regno;
1714 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1717 chain->rld[i].regno = -1;
1718 reload_order[i] = i;
1721 n_reloads = chain->n_reloads;
1722 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1724 CLEAR_HARD_REG_SET (used_spill_regs_local);
1727 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1729 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1731 /* Compute the order of preference for hard registers to spill. */
1733 order_regs_for_reload (chain);
1735 for (i = 0; i < n_reloads; i++)
1737 int r = reload_order[i];
1739 /* Ignore reloads that got marked inoperative. */
1740 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1741 && ! rld[r].optional
1742 && rld[r].regno == -1)
1743 if (! find_reg (chain, i))
1745 spill_failure (chain->insn, rld[r].class);
1751 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1752 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1754 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1758 select_reload_regs ()
1760 struct insn_chain *chain;
1762 /* Try to satisfy the needs for each insn. */
1763 for (chain = insns_need_reload; chain != 0;
1764 chain = chain->next_need_reload)
1765 find_reload_regs (chain);
1768 /* Delete all insns that were inserted by emit_caller_save_insns during
1771 delete_caller_save_insns ()
1773 struct insn_chain *c = reload_insn_chain;
1777 while (c != 0 && c->is_caller_save_insn)
1779 struct insn_chain *next = c->next;
1782 if (insn == BLOCK_HEAD (c->block))
1783 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1784 if (insn == BLOCK_END (c->block))
1785 BLOCK_END (c->block) = PREV_INSN (insn);
1786 if (c == reload_insn_chain)
1787 reload_insn_chain = next;
1789 if (NEXT_INSN (insn) != 0)
1790 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1791 if (PREV_INSN (insn) != 0)
1792 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1795 next->prev = c->prev;
1797 c->prev->next = next;
1798 c->next = unused_insn_chains;
1799 unused_insn_chains = c;
1807 /* Handle the failure to find a register to spill.
1808 INSN should be one of the insns which needed this particular spill reg. */
1811 spill_failure (insn, class)
1813 enum reg_class class;
1815 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1816 if (asm_noperands (PATTERN (insn)) >= 0)
1817 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1818 reg_class_names[class]);
1821 error ("Unable to find a register to spill in class `%s'.",
1822 reg_class_names[class]);
1823 fatal_insn ("This is the insn:", insn);
1827 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1828 data that is dead in INSN. */
1831 delete_dead_insn (insn)
1834 rtx prev = prev_real_insn (insn);
1837 /* If the previous insn sets a register that dies in our insn, delete it
1839 if (prev && GET_CODE (PATTERN (prev)) == SET
1840 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1841 && reg_mentioned_p (prev_dest, PATTERN (insn))
1842 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1843 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1844 delete_dead_insn (prev);
1846 PUT_CODE (insn, NOTE);
1847 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1848 NOTE_SOURCE_FILE (insn) = 0;
1851 /* Modify the home of pseudo-reg I.
1852 The new home is present in reg_renumber[I].
1854 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1855 or it may be -1, meaning there is none or it is not relevant.
1856 This is used so that all pseudos spilled from a given hard reg
1857 can share one stack slot. */
1860 alter_reg (i, from_reg)
1864 /* When outputting an inline function, this can happen
1865 for a reg that isn't actually used. */
1866 if (regno_reg_rtx[i] == 0)
1869 /* If the reg got changed to a MEM at rtl-generation time,
1871 if (GET_CODE (regno_reg_rtx[i]) != REG)
1874 /* Modify the reg-rtx to contain the new hard reg
1875 number or else to contain its pseudo reg number. */
1876 REGNO (regno_reg_rtx[i])
1877 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1879 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1880 allocate a stack slot for it. */
1882 if (reg_renumber[i] < 0
1883 && REG_N_REFS (i) > 0
1884 && reg_equiv_constant[i] == 0
1885 && reg_equiv_memory_loc[i] == 0)
1888 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1889 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1892 /* Each pseudo reg has an inherent size which comes from its own mode,
1893 and a total size which provides room for paradoxical subregs
1894 which refer to the pseudo reg in wider modes.
1896 We can use a slot already allocated if it provides both
1897 enough inherent space and enough total space.
1898 Otherwise, we allocate a new slot, making sure that it has no less
1899 inherent space, and no less total space, then the previous slot. */
1902 /* No known place to spill from => no slot to reuse. */
1903 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1904 inherent_size == total_size ? 0 : -1);
1905 if (BYTES_BIG_ENDIAN)
1906 /* Cancel the big-endian correction done in assign_stack_local.
1907 Get the address of the beginning of the slot.
1908 This is so we can do a big-endian correction unconditionally
1910 adjust = inherent_size - total_size;
1912 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1914 /* Nothing can alias this slot except this pseudo. */
1915 MEM_ALIAS_SET (x) = new_alias_set ();
1918 /* Reuse a stack slot if possible. */
1919 else if (spill_stack_slot[from_reg] != 0
1920 && spill_stack_slot_width[from_reg] >= total_size
1921 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1923 x = spill_stack_slot[from_reg];
1925 /* Allocate a bigger slot. */
1928 /* Compute maximum size needed, both for inherent size
1929 and for total size. */
1930 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1933 if (spill_stack_slot[from_reg])
1935 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1937 mode = GET_MODE (spill_stack_slot[from_reg]);
1938 if (spill_stack_slot_width[from_reg] > total_size)
1939 total_size = spill_stack_slot_width[from_reg];
1942 /* Make a slot with that size. */
1943 x = assign_stack_local (mode, total_size,
1944 inherent_size == total_size ? 0 : -1);
1947 /* All pseudos mapped to this slot can alias each other. */
1948 if (spill_stack_slot[from_reg])
1949 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
1951 MEM_ALIAS_SET (x) = new_alias_set ();
1953 if (BYTES_BIG_ENDIAN)
1955 /* Cancel the big-endian correction done in assign_stack_local.
1956 Get the address of the beginning of the slot.
1957 This is so we can do a big-endian correction unconditionally
1959 adjust = GET_MODE_SIZE (mode) - total_size;
1961 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1964 plus_constant (XEXP (x, 0), adjust));
1967 spill_stack_slot[from_reg] = stack_slot;
1968 spill_stack_slot_width[from_reg] = total_size;
1971 /* On a big endian machine, the "address" of the slot
1972 is the address of the low part that fits its inherent mode. */
1973 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1974 adjust += (total_size - inherent_size);
1976 /* If we have any adjustment to make, or if the stack slot is the
1977 wrong mode, make a new stack slot. */
1978 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1980 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1981 plus_constant (XEXP (x, 0), adjust));
1983 MEM_COPY_ATTRIBUTES (new, x);
1987 /* Save the stack slot for later. */
1988 reg_equiv_memory_loc[i] = x;
1992 /* Mark the slots in regs_ever_live for the hard regs
1993 used by pseudo-reg number REGNO. */
1996 mark_home_live (regno)
1999 register int i, lim;
2001 i = reg_renumber[regno];
2004 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2006 regs_ever_live[i++] = 1;
2009 /* This function handles the tracking of elimination offsets around branches.
2011 X is a piece of RTL being scanned.
2013 INSN is the insn that it came from, if any.
2015 INITIAL_P is non-zero if we are to set the offset to be the initial
2016 offset and zero if we are setting the offset of the label to be the
2020 set_label_offsets (x, insn, initial_p)
2025 enum rtx_code code = GET_CODE (x);
2028 struct elim_table *p;
2033 if (LABEL_REF_NONLOCAL_P (x))
2038 /* ... fall through ... */
2041 /* If we know nothing about this label, set the desired offsets. Note
2042 that this sets the offset at a label to be the offset before a label
2043 if we don't know anything about the label. This is not correct for
2044 the label after a BARRIER, but is the best guess we can make. If
2045 we guessed wrong, we will suppress an elimination that might have
2046 been possible had we been able to guess correctly. */
2048 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2050 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2051 offsets_at[CODE_LABEL_NUMBER (x)][i]
2052 = (initial_p ? reg_eliminate[i].initial_offset
2053 : reg_eliminate[i].offset);
2054 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2057 /* Otherwise, if this is the definition of a label and it is
2058 preceded by a BARRIER, set our offsets to the known offset of
2062 && (tem = prev_nonnote_insn (insn)) != 0
2063 && GET_CODE (tem) == BARRIER)
2064 set_offsets_for_label (insn);
2066 /* If neither of the above cases is true, compare each offset
2067 with those previously recorded and suppress any eliminations
2068 where the offsets disagree. */
2070 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2071 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2072 != (initial_p ? reg_eliminate[i].initial_offset
2073 : reg_eliminate[i].offset))
2074 reg_eliminate[i].can_eliminate = 0;
2079 set_label_offsets (PATTERN (insn), insn, initial_p);
2081 /* ... fall through ... */
2085 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2086 and hence must have all eliminations at their initial offsets. */
2087 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2088 if (REG_NOTE_KIND (tem) == REG_LABEL)
2089 set_label_offsets (XEXP (tem, 0), insn, 1);
2095 /* Each of the labels in the parallel or address vector must be
2096 at their initial offsets. We want the first field for PARALLEL
2097 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2099 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2100 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2105 /* We only care about setting PC. If the source is not RETURN,
2106 IF_THEN_ELSE, or a label, disable any eliminations not at
2107 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2108 isn't one of those possibilities. For branches to a label,
2109 call ourselves recursively.
2111 Note that this can disable elimination unnecessarily when we have
2112 a non-local goto since it will look like a non-constant jump to
2113 someplace in the current function. This isn't a significant
2114 problem since such jumps will normally be when all elimination
2115 pairs are back to their initial offsets. */
2117 if (SET_DEST (x) != pc_rtx)
2120 switch (GET_CODE (SET_SRC (x)))
2127 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2131 tem = XEXP (SET_SRC (x), 1);
2132 if (GET_CODE (tem) == LABEL_REF)
2133 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2134 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2137 tem = XEXP (SET_SRC (x), 2);
2138 if (GET_CODE (tem) == LABEL_REF)
2139 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2140 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2148 /* If we reach here, all eliminations must be at their initial
2149 offset because we are doing a jump to a variable address. */
2150 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2151 if (p->offset != p->initial_offset)
2152 p->can_eliminate = 0;
2160 /* Scan X and replace any eliminable registers (such as fp) with a
2161 replacement (such as sp), plus an offset.
2163 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2164 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2165 MEM, we are allowed to replace a sum of a register and the constant zero
2166 with the register, which we cannot do outside a MEM. In addition, we need
2167 to record the fact that a register is referenced outside a MEM.
2169 If INSN is an insn, it is the insn containing X. If we replace a REG
2170 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2171 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2172 the REG is being modified.
2174 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2175 That's used when we eliminate in expressions stored in notes.
2176 This means, do not set ref_outside_mem even if the reference
2179 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2180 replacements done assuming all offsets are at their initial values. If
2181 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2182 encounter, return the actual location so that find_reloads will do
2183 the proper thing. */
2186 eliminate_regs (x, mem_mode, insn)
2188 enum machine_mode mem_mode;
2191 enum rtx_code code = GET_CODE (x);
2192 struct elim_table *ep;
2199 if (! current_function_decl)
2218 /* This is only for the benefit of the debugging backends, which call
2219 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2220 removed after CSE. */
2221 new = eliminate_regs (XEXP (x, 0), 0, insn);
2222 if (GET_CODE (new) == MEM)
2223 return XEXP (new, 0);
2229 /* First handle the case where we encounter a bare register that
2230 is eliminable. Replace it with a PLUS. */
2231 if (regno < FIRST_PSEUDO_REGISTER)
2233 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2235 if (ep->from_rtx == x && ep->can_eliminate)
2236 return plus_constant (ep->to_rtx, ep->previous_offset);
2239 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2240 && reg_equiv_constant[regno]
2241 && ! CONSTANT_P (reg_equiv_constant[regno]))
2242 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2246 /* You might think handling MINUS in a manner similar to PLUS is a
2247 good idea. It is not. It has been tried multiple times and every
2248 time the change has had to have been reverted.
2250 Other parts of reload know a PLUS is special (gen_reload for example)
2251 and require special code to handle code a reloaded PLUS operand.
2253 Also consider backends where the flags register is clobbered by a
2254 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2255 lea instruction comes to mind). If we try to reload a MINUS, we
2256 may kill the flags register that was holding a useful value.
2258 So, please before trying to handle MINUS, consider reload as a
2259 whole instead of this little section as well as the backend issues. */
2261 /* If this is the sum of an eliminable register and a constant, rework
2263 if (GET_CODE (XEXP (x, 0)) == REG
2264 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2265 && CONSTANT_P (XEXP (x, 1)))
2267 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2269 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2271 /* The only time we want to replace a PLUS with a REG (this
2272 occurs when the constant operand of the PLUS is the negative
2273 of the offset) is when we are inside a MEM. We won't want
2274 to do so at other times because that would change the
2275 structure of the insn in a way that reload can't handle.
2276 We special-case the commonest situation in
2277 eliminate_regs_in_insn, so just replace a PLUS with a
2278 PLUS here, unless inside a MEM. */
2279 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2280 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2283 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2284 plus_constant (XEXP (x, 1),
2285 ep->previous_offset));
2288 /* If the register is not eliminable, we are done since the other
2289 operand is a constant. */
2293 /* If this is part of an address, we want to bring any constant to the
2294 outermost PLUS. We will do this by doing register replacement in
2295 our operands and seeing if a constant shows up in one of them.
2297 Note that there is no risk of modifying the structure of the insn,
2298 since we only get called for its operands, thus we are either
2299 modifying the address inside a MEM, or something like an address
2300 operand of a load-address insn. */
2303 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2304 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2306 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2308 /* If one side is a PLUS and the other side is a pseudo that
2309 didn't get a hard register but has a reg_equiv_constant,
2310 we must replace the constant here since it may no longer
2311 be in the position of any operand. */
2312 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2313 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2314 && reg_renumber[REGNO (new1)] < 0
2315 && reg_equiv_constant != 0
2316 && reg_equiv_constant[REGNO (new1)] != 0)
2317 new1 = reg_equiv_constant[REGNO (new1)];
2318 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2319 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2320 && reg_renumber[REGNO (new0)] < 0
2321 && reg_equiv_constant[REGNO (new0)] != 0)
2322 new0 = reg_equiv_constant[REGNO (new0)];
2324 new = form_sum (new0, new1);
2326 /* As above, if we are not inside a MEM we do not want to
2327 turn a PLUS into something else. We might try to do so here
2328 for an addition of 0 if we aren't optimizing. */
2329 if (! mem_mode && GET_CODE (new) != PLUS)
2330 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2338 /* If this is the product of an eliminable register and a
2339 constant, apply the distribute law and move the constant out
2340 so that we have (plus (mult ..) ..). This is needed in order
2341 to keep load-address insns valid. This case is pathological.
2342 We ignore the possibility of overflow here. */
2343 if (GET_CODE (XEXP (x, 0)) == REG
2344 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2345 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2346 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2348 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2351 /* Refs inside notes don't count for this purpose. */
2352 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2353 || GET_CODE (insn) == INSN_LIST)))
2354 ep->ref_outside_mem = 1;
2357 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2358 ep->previous_offset * INTVAL (XEXP (x, 1)));
2361 /* ... fall through ... */
2365 /* See comments before PLUS about handling MINUS. */
2367 case DIV: case UDIV:
2368 case MOD: case UMOD:
2369 case AND: case IOR: case XOR:
2370 case ROTATERT: case ROTATE:
2371 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2373 case GE: case GT: case GEU: case GTU:
2374 case LE: case LT: case LEU: case LTU:
2376 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2378 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2380 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2381 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2386 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2389 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2390 if (new != XEXP (x, 0))
2392 /* If this is a REG_DEAD note, it is not valid anymore.
2393 Using the eliminated version could result in creating a
2394 REG_DEAD note for the stack or frame pointer. */
2395 if (GET_MODE (x) == REG_DEAD)
2397 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2400 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2404 /* ... fall through ... */
2407 /* Now do eliminations in the rest of the chain. If this was
2408 an EXPR_LIST, this might result in allocating more memory than is
2409 strictly needed, but it simplifies the code. */
2412 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2413 if (new != XEXP (x, 1))
2414 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2422 case STRICT_LOW_PART:
2424 case SIGN_EXTEND: case ZERO_EXTEND:
2425 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2426 case FLOAT: case FIX:
2427 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2431 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2432 if (new != XEXP (x, 0))
2433 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2437 /* Similar to above processing, but preserve SUBREG_WORD.
2438 Convert (subreg (mem)) to (mem) if not paradoxical.
2439 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2440 pseudo didn't get a hard reg, we must replace this with the
2441 eliminated version of the memory location because push_reloads
2442 may do the replacement in certain circumstances. */
2443 if (GET_CODE (SUBREG_REG (x)) == REG
2444 && (GET_MODE_SIZE (GET_MODE (x))
2445 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2446 && reg_equiv_memory_loc != 0
2447 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2449 new = SUBREG_REG (x);
2452 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2454 if (new != XEXP (x, 0))
2456 int x_size = GET_MODE_SIZE (GET_MODE (x));
2457 int new_size = GET_MODE_SIZE (GET_MODE (new));
2459 if (GET_CODE (new) == MEM
2460 && ((x_size < new_size
2461 #ifdef WORD_REGISTER_OPERATIONS
2462 /* On these machines, combine can create rtl of the form
2463 (set (subreg:m1 (reg:m2 R) 0) ...)
2464 where m1 < m2, and expects something interesting to
2465 happen to the entire word. Moreover, it will use the
2466 (reg:m2 R) later, expecting all bits to be preserved.
2467 So if the number of words is the same, preserve the
2468 subreg so that push_reloads can see it. */
2469 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2472 || (x_size == new_size))
2475 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2476 enum machine_mode mode = GET_MODE (x);
2478 if (BYTES_BIG_ENDIAN)
2479 offset += (MIN (UNITS_PER_WORD,
2480 GET_MODE_SIZE (GET_MODE (new)))
2481 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2483 PUT_MODE (new, mode);
2484 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2488 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2494 /* This is only for the benefit of the debugging backends, which call
2495 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2496 removed after CSE. */
2497 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2498 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2500 /* Our only special processing is to pass the mode of the MEM to our
2501 recursive call and copy the flags. While we are here, handle this
2502 case more efficiently. */
2503 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2504 if (new != XEXP (x, 0))
2506 new = gen_rtx_MEM (GET_MODE (x), new);
2507 MEM_COPY_ATTRIBUTES (new, x);
2523 /* Process each of our operands recursively. If any have changed, make a
2525 fmt = GET_RTX_FORMAT (code);
2526 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2530 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2531 if (new != XEXP (x, i) && ! copied)
2533 rtx new_x = rtx_alloc (code);
2535 (sizeof (*new_x) - sizeof (new_x->fld)
2536 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2542 else if (*fmt == 'E')
2545 for (j = 0; j < XVECLEN (x, i); j++)
2547 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2548 if (new != XVECEXP (x, i, j) && ! copied_vec)
2550 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2554 rtx new_x = rtx_alloc (code);
2556 (sizeof (*new_x) - sizeof (new_x->fld)
2557 + (sizeof (new_x->fld[0])
2558 * GET_RTX_LENGTH (code))));
2562 XVEC (x, i) = new_v;
2565 XVECEXP (x, i, j) = new;
2573 /* Scan rtx X for modifications of elimination target registers. Update
2574 the table of eliminables to reflect the changed state. MEM_MODE is
2575 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2578 elimination_effects (x, mem_mode)
2580 enum machine_mode mem_mode;
2583 enum rtx_code code = GET_CODE (x);
2584 struct elim_table *ep;
2610 /* First handle the case where we encounter a bare register that
2611 is eliminable. Replace it with a PLUS. */
2612 if (regno < FIRST_PSEUDO_REGISTER)
2614 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2616 if (ep->from_rtx == x && ep->can_eliminate)
2619 ep->ref_outside_mem = 1;
2624 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2625 && reg_equiv_constant[regno]
2626 && ! CONSTANT_P (reg_equiv_constant[regno]))
2627 elimination_effects (reg_equiv_constant[regno], mem_mode);
2636 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2637 if (ep->to_rtx == XEXP (x, 0))
2639 int size = GET_MODE_SIZE (mem_mode);
2641 /* If more bytes than MEM_MODE are pushed, account for them. */
2642 #ifdef PUSH_ROUNDING
2643 if (ep->to_rtx == stack_pointer_rtx)
2644 size = PUSH_ROUNDING (size);
2646 if (code == PRE_DEC || code == POST_DEC)
2648 else if (code == PRE_INC || code == POST_INC)
2650 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2651 && GET_CODE (XEXP (x, 1)) == PLUS
2652 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2653 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2654 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2657 /* These two aren't unary operators. */
2658 if (code == POST_MODIFY || code == PRE_MODIFY)
2661 /* Fall through to generic unary operation case. */
2662 case STRICT_LOW_PART:
2664 case SIGN_EXTEND: case ZERO_EXTEND:
2665 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2666 case FLOAT: case FIX:
2667 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2671 elimination_effects (XEXP (x, 0), mem_mode);
2675 if (GET_CODE (SUBREG_REG (x)) == REG
2676 && (GET_MODE_SIZE (GET_MODE (x))
2677 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2678 && reg_equiv_memory_loc != 0
2679 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2682 elimination_effects (SUBREG_REG (x), mem_mode);
2686 /* If using a register that is the source of an eliminate we still
2687 think can be performed, note it cannot be performed since we don't
2688 know how this register is used. */
2689 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2690 if (ep->from_rtx == XEXP (x, 0))
2691 ep->can_eliminate = 0;
2693 elimination_effects (XEXP (x, 0), mem_mode);
2697 /* If clobbering a register that is the replacement register for an
2698 elimination we still think can be performed, note that it cannot
2699 be performed. Otherwise, we need not be concerned about it. */
2700 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2701 if (ep->to_rtx == XEXP (x, 0))
2702 ep->can_eliminate = 0;
2704 elimination_effects (XEXP (x, 0), mem_mode);
2708 /* Check for setting a register that we know about. */
2709 if (GET_CODE (SET_DEST (x)) == REG)
2711 /* See if this is setting the replacement register for an
2714 If DEST is the hard frame pointer, we do nothing because we
2715 assume that all assignments to the frame pointer are for
2716 non-local gotos and are being done at a time when they are valid
2717 and do not disturb anything else. Some machines want to
2718 eliminate a fake argument pointer (or even a fake frame pointer)
2719 with either the real frame or the stack pointer. Assignments to
2720 the hard frame pointer must not prevent this elimination. */
2722 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2724 if (ep->to_rtx == SET_DEST (x)
2725 && SET_DEST (x) != hard_frame_pointer_rtx)
2727 /* If it is being incremented, adjust the offset. Otherwise,
2728 this elimination can't be done. */
2729 rtx src = SET_SRC (x);
2731 if (GET_CODE (src) == PLUS
2732 && XEXP (src, 0) == SET_DEST (x)
2733 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2734 ep->offset -= INTVAL (XEXP (src, 1));
2736 ep->can_eliminate = 0;
2740 elimination_effects (SET_DEST (x), 0);
2741 elimination_effects (SET_SRC (x), 0);
2745 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2748 /* Our only special processing is to pass the mode of the MEM to our
2750 elimination_effects (XEXP (x, 0), GET_MODE (x));
2757 fmt = GET_RTX_FORMAT (code);
2758 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2761 elimination_effects (XEXP (x, i), mem_mode);
2762 else if (*fmt == 'E')
2763 for (j = 0; j < XVECLEN (x, i); j++)
2764 elimination_effects (XVECEXP (x, i, j), mem_mode);
2768 /* Descend through rtx X and verify that no references to eliminable registers
2769 remain. If any do remain, mark the involved register as not
2773 check_eliminable_occurrences (x)
2783 code = GET_CODE (x);
2785 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2787 struct elim_table *ep;
2789 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2790 if (ep->from_rtx == x && ep->can_eliminate)
2791 ep->can_eliminate = 0;
2795 fmt = GET_RTX_FORMAT (code);
2796 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2799 check_eliminable_occurrences (XEXP (x, i));
2800 else if (*fmt == 'E')
2803 for (j = 0; j < XVECLEN (x, i); j++)
2804 check_eliminable_occurrences (XVECEXP (x, i, j));
2809 /* Scan INSN and eliminate all eliminable registers in it.
2811 If REPLACE is nonzero, do the replacement destructively. Also
2812 delete the insn as dead it if it is setting an eliminable register.
2814 If REPLACE is zero, do all our allocations in reload_obstack.
2816 If no eliminations were done and this insn doesn't require any elimination
2817 processing (these are not identical conditions: it might be updating sp,
2818 but not referencing fp; this needs to be seen during reload_as_needed so
2819 that the offset between fp and sp can be taken into consideration), zero
2820 is returned. Otherwise, 1 is returned. */
2823 eliminate_regs_in_insn (insn, replace)
2827 int icode = recog_memoized (insn);
2828 rtx old_body = PATTERN (insn);
2829 int insn_is_asm = asm_noperands (old_body) >= 0;
2830 rtx old_set = single_set (insn);
2834 rtx substed_operand[MAX_RECOG_OPERANDS];
2835 rtx orig_operand[MAX_RECOG_OPERANDS];
2836 struct elim_table *ep;
2838 if (! insn_is_asm && icode < 0)
2840 if (GET_CODE (PATTERN (insn)) == USE
2841 || GET_CODE (PATTERN (insn)) == CLOBBER
2842 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2843 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2844 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2849 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2850 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2852 /* Check for setting an eliminable register. */
2853 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2854 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2856 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2857 /* If this is setting the frame pointer register to the
2858 hardware frame pointer register and this is an elimination
2859 that will be done (tested above), this insn is really
2860 adjusting the frame pointer downward to compensate for
2861 the adjustment done before a nonlocal goto. */
2862 if (ep->from == FRAME_POINTER_REGNUM
2863 && ep->to == HARD_FRAME_POINTER_REGNUM)
2865 rtx src = SET_SRC (old_set);
2866 int offset = 0, ok = 0;
2867 rtx prev_insn, prev_set;
2869 if (src == ep->to_rtx)
2871 else if (GET_CODE (src) == PLUS
2872 && GET_CODE (XEXP (src, 0)) == CONST_INT
2873 && XEXP (src, 1) == ep->to_rtx)
2874 offset = INTVAL (XEXP (src, 0)), ok = 1;
2875 else if (GET_CODE (src) == PLUS
2876 && GET_CODE (XEXP (src, 1)) == CONST_INT
2877 && XEXP (src, 0) == ep->to_rtx)
2878 offset = INTVAL (XEXP (src, 1)), ok = 1;
2879 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2880 && (prev_set = single_set (prev_insn)) != 0
2881 && rtx_equal_p (SET_DEST (prev_set), src))
2883 src = SET_SRC (prev_set);
2884 if (src == ep->to_rtx)
2886 else if (GET_CODE (src) == PLUS
2887 && GET_CODE (XEXP (src, 0)) == CONST_INT
2888 && XEXP (src, 1) == ep->to_rtx)
2889 offset = INTVAL (XEXP (src, 0)), ok = 1;
2890 else if (GET_CODE (src) == PLUS
2891 && GET_CODE (XEXP (src, 1)) == CONST_INT
2892 && XEXP (src, 0) == ep->to_rtx)
2893 offset = INTVAL (XEXP (src, 1)), ok = 1;
2901 = plus_constant (ep->to_rtx, offset - ep->offset);
2903 /* First see if this insn remains valid when we
2904 make the change. If not, keep the INSN_CODE
2905 the same and let reload fit it up. */
2906 validate_change (insn, &SET_SRC (old_set), src, 1);
2907 validate_change (insn, &SET_DEST (old_set),
2909 if (! apply_change_group ())
2911 SET_SRC (old_set) = src;
2912 SET_DEST (old_set) = ep->to_rtx;
2922 /* In this case this insn isn't serving a useful purpose. We
2923 will delete it in reload_as_needed once we know that this
2924 elimination is, in fact, being done.
2926 If REPLACE isn't set, we can't delete this insn, but needn't
2927 process it since it won't be used unless something changes. */
2930 delete_dead_insn (insn);
2938 /* We allow one special case which happens to work on all machines we
2939 currently support: a single set with the source being a PLUS of an
2940 eliminable register and a constant. */
2942 && GET_CODE (SET_SRC (old_set)) == PLUS
2943 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2944 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2945 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2947 rtx reg = XEXP (SET_SRC (old_set), 0);
2948 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2950 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2951 if (ep->from_rtx == reg && ep->can_eliminate)
2953 offset += ep->offset;
2958 /* We assume here that if we need a PARALLEL with
2959 CLOBBERs for this assignment, we can do with the
2960 MATCH_SCRATCHes that add_clobbers allocates.
2961 There's not much we can do if that doesn't work. */
2962 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2966 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
2969 rtvec vec = rtvec_alloc (num_clobbers + 1);
2971 vec->elem[0] = PATTERN (insn);
2972 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
2973 add_clobbers (PATTERN (insn), INSN_CODE (insn));
2975 if (INSN_CODE (insn) < 0)
2980 new_body = old_body;
2983 new_body = copy_insn (old_body);
2984 if (REG_NOTES (insn))
2985 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2987 PATTERN (insn) = new_body;
2988 old_set = single_set (insn);
2990 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
2991 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
2994 /* This can't have an effect on elimination offsets, so skip right
3000 /* Determine the effects of this insn on elimination offsets. */
3001 elimination_effects (old_body, 0);
3003 /* Eliminate all eliminable registers occurring in operands that
3004 can be handled by reload. */
3005 extract_insn (insn);
3007 for (i = 0; i < recog_data.n_operands; i++)
3009 orig_operand[i] = recog_data.operand[i];
3010 substed_operand[i] = recog_data.operand[i];
3012 /* For an asm statement, every operand is eliminable. */
3013 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3015 /* Check for setting a register that we know about. */
3016 if (recog_data.operand_type[i] != OP_IN
3017 && GET_CODE (orig_operand[i]) == REG)
3019 /* If we are assigning to a register that can be eliminated, it
3020 must be as part of a PARALLEL, since the code above handles
3021 single SETs. We must indicate that we can no longer
3022 eliminate this reg. */
3023 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3025 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3026 ep->can_eliminate = 0;
3029 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3030 replace ? insn : NULL_RTX);
3031 if (substed_operand[i] != orig_operand[i])
3032 val = any_changes = 1;
3033 /* Terminate the search in check_eliminable_occurrences at
3035 *recog_data.operand_loc[i] = 0;
3037 /* If an output operand changed from a REG to a MEM and INSN is an
3038 insn, write a CLOBBER insn. */
3039 if (recog_data.operand_type[i] != OP_IN
3040 && GET_CODE (orig_operand[i]) == REG
3041 && GET_CODE (substed_operand[i]) == MEM
3043 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3048 for (i = 0; i < recog_data.n_dups; i++)
3049 *recog_data.dup_loc[i]
3050 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3052 /* If any eliminable remain, they aren't eliminable anymore. */
3053 check_eliminable_occurrences (old_body);
3055 /* Substitute the operands; the new values are in the substed_operand
3057 for (i = 0; i < recog_data.n_operands; i++)
3058 *recog_data.operand_loc[i] = substed_operand[i];
3059 for (i = 0; i < recog_data.n_dups; i++)
3060 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3062 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3063 re-recognize the insn. We do this in case we had a simple addition
3064 but now can do this as a load-address. This saves an insn in this
3066 If re-recognition fails, the old insn code number will still be used,
3067 and some register operands may have changed into PLUS expressions.
3068 These will be handled by find_reloads by loading them into a register
3073 /* If we aren't replacing things permanently and we changed something,
3074 make another copy to ensure that all the RTL is new. Otherwise
3075 things can go wrong if find_reload swaps commutative operands
3076 and one is inside RTL that has been copied while the other is not. */
3077 new_body = old_body;
3080 new_body = copy_insn (old_body);
3081 if (REG_NOTES (insn))
3082 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3084 PATTERN (insn) = new_body;
3086 /* If we had a move insn but now we don't, rerecognize it. This will
3087 cause spurious re-recognition if the old move had a PARALLEL since
3088 the new one still will, but we can't call single_set without
3089 having put NEW_BODY into the insn and the re-recognition won't
3090 hurt in this rare case. */
3091 /* ??? Why this huge if statement - why don't we just rerecognize the
3095 && ((GET_CODE (SET_SRC (old_set)) == REG
3096 && (GET_CODE (new_body) != SET
3097 || GET_CODE (SET_SRC (new_body)) != REG))
3098 /* If this was a load from or store to memory, compare
3099 the MEM in recog_data.operand to the one in the insn.
3100 If they are not equal, then rerecognize the insn. */
3102 && ((GET_CODE (SET_SRC (old_set)) == MEM
3103 && SET_SRC (old_set) != recog_data.operand[1])
3104 || (GET_CODE (SET_DEST (old_set)) == MEM
3105 && SET_DEST (old_set) != recog_data.operand[0])))
3106 /* If this was an add insn before, rerecognize. */
3107 || GET_CODE (SET_SRC (old_set)) == PLUS))
3109 int new_icode = recog (PATTERN (insn), insn, 0);
3111 INSN_CODE (insn) = icode;
3115 /* Restore the old body. If there were any changes to it, we made a copy
3116 of it while the changes were still in place, so we'll correctly return
3117 a modified insn below. */
3120 /* Restore the old body. */
3121 for (i = 0; i < recog_data.n_operands; i++)
3122 *recog_data.operand_loc[i] = orig_operand[i];
3123 for (i = 0; i < recog_data.n_dups; i++)
3124 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3127 /* Update all elimination pairs to reflect the status after the current
3128 insn. The changes we make were determined by the earlier call to
3129 elimination_effects.
3131 We also detect a cases where register elimination cannot be done,
3132 namely, if a register would be both changed and referenced outside a MEM
3133 in the resulting insn since such an insn is often undefined and, even if
3134 not, we cannot know what meaning will be given to it. Note that it is
3135 valid to have a register used in an address in an insn that changes it
3136 (presumably with a pre- or post-increment or decrement).
3138 If anything changes, return nonzero. */
3140 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3142 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3143 ep->can_eliminate = 0;
3145 ep->ref_outside_mem = 0;
3147 if (ep->previous_offset != ep->offset)
3152 /* If we changed something, perform elimination in REG_NOTES. This is
3153 needed even when REPLACE is zero because a REG_DEAD note might refer
3154 to a register that we eliminate and could cause a different number
3155 of spill registers to be needed in the final reload pass than in
3157 if (val && REG_NOTES (insn) != 0)
3158 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3163 /* Loop through all elimination pairs.
3164 Recalculate the number not at initial offset.
3166 Compute the maximum offset (minimum offset if the stack does not
3167 grow downward) for each elimination pair. */
3170 update_eliminable_offsets ()
3172 struct elim_table *ep;
3174 num_not_at_initial_offset = 0;
3175 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3177 ep->previous_offset = ep->offset;
3178 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3179 num_not_at_initial_offset++;
3183 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3184 replacement we currently believe is valid, mark it as not eliminable if X
3185 modifies DEST in any way other than by adding a constant integer to it.
3187 If DEST is the frame pointer, we do nothing because we assume that
3188 all assignments to the hard frame pointer are nonlocal gotos and are being
3189 done at a time when they are valid and do not disturb anything else.
3190 Some machines want to eliminate a fake argument pointer with either the
3191 frame or stack pointer. Assignments to the hard frame pointer must not
3192 prevent this elimination.
3194 Called via note_stores from reload before starting its passes to scan
3195 the insns of the function. */
3198 mark_not_eliminable (dest, x, data)
3201 void *data ATTRIBUTE_UNUSED;
3203 register unsigned int i;
3205 /* A SUBREG of a hard register here is just changing its mode. We should
3206 not see a SUBREG of an eliminable hard register, but check just in
3208 if (GET_CODE (dest) == SUBREG)
3209 dest = SUBREG_REG (dest);
3211 if (dest == hard_frame_pointer_rtx)
3214 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3215 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3216 && (GET_CODE (x) != SET
3217 || GET_CODE (SET_SRC (x)) != PLUS
3218 || XEXP (SET_SRC (x), 0) != dest
3219 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3221 reg_eliminate[i].can_eliminate_previous
3222 = reg_eliminate[i].can_eliminate = 0;
3227 /* Verify that the initial elimination offsets did not change since the
3228 last call to set_initial_elim_offsets. This is used to catch cases
3229 where something illegal happened during reload_as_needed that could
3230 cause incorrect code to be generated if we did not check for it. */
3233 verify_initial_elim_offsets ()
3237 #ifdef ELIMINABLE_REGS
3238 struct elim_table *ep;
3240 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3242 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3243 if (t != ep->initial_offset)
3247 INITIAL_FRAME_POINTER_OFFSET (t);
3248 if (t != reg_eliminate[0].initial_offset)
3253 /* Reset all offsets on eliminable registers to their initial values. */
3256 set_initial_elim_offsets ()
3258 struct elim_table *ep = reg_eliminate;
3260 #ifdef ELIMINABLE_REGS
3261 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3263 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3264 ep->previous_offset = ep->offset = ep->initial_offset;
3267 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3268 ep->previous_offset = ep->offset = ep->initial_offset;
3271 num_not_at_initial_offset = 0;
3274 /* Initialize the known label offsets.
3275 Set a known offset for each forced label to be at the initial offset
3276 of each elimination. We do this because we assume that all
3277 computed jumps occur from a location where each elimination is
3278 at its initial offset.
3279 For all other labels, show that we don't know the offsets. */
3282 set_initial_label_offsets ()
3285 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3287 for (x = forced_labels; x; x = XEXP (x, 1))
3289 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3292 /* Set all elimination offsets to the known values for the code label given
3296 set_offsets_for_label (insn)
3300 int label_nr = CODE_LABEL_NUMBER (insn);
3301 struct elim_table *ep;
3303 num_not_at_initial_offset = 0;
3304 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3306 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3307 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3308 num_not_at_initial_offset++;
3312 /* See if anything that happened changes which eliminations are valid.
3313 For example, on the Sparc, whether or not the frame pointer can
3314 be eliminated can depend on what registers have been used. We need
3315 not check some conditions again (such as flag_omit_frame_pointer)
3316 since they can't have changed. */
3319 update_eliminables (pset)
3322 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3323 int previous_frame_pointer_needed = frame_pointer_needed;
3325 struct elim_table *ep;
3327 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3328 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3329 #ifdef ELIMINABLE_REGS
3330 || ! CAN_ELIMINATE (ep->from, ep->to)
3333 ep->can_eliminate = 0;
3335 /* Look for the case where we have discovered that we can't replace
3336 register A with register B and that means that we will now be
3337 trying to replace register A with register C. This means we can
3338 no longer replace register C with register B and we need to disable
3339 such an elimination, if it exists. This occurs often with A == ap,
3340 B == sp, and C == fp. */
3342 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3344 struct elim_table *op;
3345 register int new_to = -1;
3347 if (! ep->can_eliminate && ep->can_eliminate_previous)
3349 /* Find the current elimination for ep->from, if there is a
3351 for (op = reg_eliminate;
3352 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3353 if (op->from == ep->from && op->can_eliminate)
3359 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3361 for (op = reg_eliminate;
3362 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3363 if (op->from == new_to && op->to == ep->to)
3364 op->can_eliminate = 0;
3368 /* See if any registers that we thought we could eliminate the previous
3369 time are no longer eliminable. If so, something has changed and we
3370 must spill the register. Also, recompute the number of eliminable
3371 registers and see if the frame pointer is needed; it is if there is
3372 no elimination of the frame pointer that we can perform. */
3374 frame_pointer_needed = 1;
3375 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3377 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3378 && ep->to != HARD_FRAME_POINTER_REGNUM)
3379 frame_pointer_needed = 0;
3381 if (! ep->can_eliminate && ep->can_eliminate_previous)
3383 ep->can_eliminate_previous = 0;
3384 SET_HARD_REG_BIT (*pset, ep->from);
3389 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3390 /* If we didn't need a frame pointer last time, but we do now, spill
3391 the hard frame pointer. */
3392 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3393 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3397 /* Initialize the table of registers to eliminate. */
3402 struct elim_table *ep;
3403 #ifdef ELIMINABLE_REGS
3404 struct elim_table_1 *ep1;
3408 reg_eliminate = (struct elim_table *)
3409 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3411 /* Does this function require a frame pointer? */
3413 frame_pointer_needed = (! flag_omit_frame_pointer
3414 #ifdef EXIT_IGNORE_STACK
3415 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3416 and restore sp for alloca. So we can't eliminate
3417 the frame pointer in that case. At some point,
3418 we should improve this by emitting the
3419 sp-adjusting insns for this case. */
3420 || (current_function_calls_alloca
3421 && EXIT_IGNORE_STACK)
3423 || FRAME_POINTER_REQUIRED);
3427 #ifdef ELIMINABLE_REGS
3428 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3429 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3431 ep->from = ep1->from;
3433 ep->can_eliminate = ep->can_eliminate_previous
3434 = (CAN_ELIMINATE (ep->from, ep->to)
3435 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3438 reg_eliminate[0].from = reg_eliminate_1[0].from;
3439 reg_eliminate[0].to = reg_eliminate_1[0].to;
3440 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3441 = ! frame_pointer_needed;
3444 /* Count the number of eliminable registers and build the FROM and TO
3445 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3446 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3447 We depend on this. */
3448 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3450 num_eliminable += ep->can_eliminate;
3451 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3452 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3456 /* Kick all pseudos out of hard register REGNO.
3458 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3459 because we found we can't eliminate some register. In the case, no pseudos
3460 are allowed to be in the register, even if they are only in a block that
3461 doesn't require spill registers, unlike the case when we are spilling this
3462 hard reg to produce another spill register.
3464 Return nonzero if any pseudos needed to be kicked out. */
3467 spill_hard_reg (regno, cant_eliminate)
3475 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3476 regs_ever_live[regno] = 1;
3479 /* Spill every pseudo reg that was allocated to this reg
3480 or to something that overlaps this reg. */
3482 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3483 if (reg_renumber[i] >= 0
3484 && (unsigned int) reg_renumber[i] <= regno
3485 && ((unsigned int) reg_renumber[i]
3486 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3487 PSEUDO_REGNO_MODE (i))
3489 SET_REGNO_REG_SET (&spilled_pseudos, i);
3492 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3493 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3496 ior_hard_reg_set (set1, set2)
3497 HARD_REG_SET *set1, *set2;
3499 IOR_HARD_REG_SET (*set1, *set2);
3502 /* After find_reload_regs has been run for all insn that need reloads,
3503 and/or spill_hard_regs was called, this function is used to actually
3504 spill pseudo registers and try to reallocate them. It also sets up the
3505 spill_regs array for use by choose_reload_regs. */
3508 finish_spills (global)
3511 struct insn_chain *chain;
3512 int something_changed = 0;
3515 /* Build the spill_regs array for the function. */
3516 /* If there are some registers still to eliminate and one of the spill regs
3517 wasn't ever used before, additional stack space may have to be
3518 allocated to store this register. Thus, we may have changed the offset
3519 between the stack and frame pointers, so mark that something has changed.
3521 One might think that we need only set VAL to 1 if this is a call-used
3522 register. However, the set of registers that must be saved by the
3523 prologue is not identical to the call-used set. For example, the
3524 register used by the call insn for the return PC is a call-used register,
3525 but must be saved by the prologue. */
3528 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3529 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3531 spill_reg_order[i] = n_spills;
3532 spill_regs[n_spills++] = i;
3533 if (num_eliminable && ! regs_ever_live[i])
3534 something_changed = 1;
3535 regs_ever_live[i] = 1;
3538 spill_reg_order[i] = -1;
3540 EXECUTE_IF_SET_IN_REG_SET
3541 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3543 /* Record the current hard register the pseudo is allocated to in
3544 pseudo_previous_regs so we avoid reallocating it to the same
3545 hard reg in a later pass. */
3546 if (reg_renumber[i] < 0)
3549 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3550 /* Mark it as no longer having a hard register home. */
3551 reg_renumber[i] = -1;
3552 /* We will need to scan everything again. */
3553 something_changed = 1;
3556 /* Retry global register allocation if possible. */
3559 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3560 /* For every insn that needs reloads, set the registers used as spill
3561 regs in pseudo_forbidden_regs for every pseudo live across the
3563 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3565 EXECUTE_IF_SET_IN_REG_SET
3566 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3568 ior_hard_reg_set (pseudo_forbidden_regs + i,
3569 &chain->used_spill_regs);
3571 EXECUTE_IF_SET_IN_REG_SET
3572 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3574 ior_hard_reg_set (pseudo_forbidden_regs + i,
3575 &chain->used_spill_regs);
3579 /* Retry allocating the spilled pseudos. For each reg, merge the
3580 various reg sets that indicate which hard regs can't be used,
3581 and call retry_global_alloc.
3582 We change spill_pseudos here to only contain pseudos that did not
3583 get a new hard register. */
3584 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3585 if (reg_old_renumber[i] != reg_renumber[i])
3587 HARD_REG_SET forbidden;
3588 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3589 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3590 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3591 retry_global_alloc (i, forbidden);
3592 if (reg_renumber[i] >= 0)
3593 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3597 /* Fix up the register information in the insn chain.
3598 This involves deleting those of the spilled pseudos which did not get
3599 a new hard register home from the live_{before,after} sets. */
3600 for (chain = reload_insn_chain; chain; chain = chain->next)
3602 HARD_REG_SET used_by_pseudos;
3603 HARD_REG_SET used_by_pseudos2;
3605 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3606 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3608 /* Mark any unallocated hard regs as available for spills. That
3609 makes inheritance work somewhat better. */
3610 if (chain->need_reload)
3612 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3613 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3614 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3616 /* Save the old value for the sanity test below. */
3617 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3619 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3620 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3621 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3622 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3624 /* Make sure we only enlarge the set. */
3625 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3631 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3632 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3634 int regno = reg_renumber[i];
3635 if (reg_old_renumber[i] == regno)
3638 alter_reg (i, reg_old_renumber[i]);
3639 reg_old_renumber[i] = regno;
3643 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3645 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3646 i, reg_renumber[i]);
3650 return something_changed;
3653 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3654 Also mark any hard registers used to store user variables as
3655 forbidden from being used for spill registers. */
3658 scan_paradoxical_subregs (x)
3662 register const char *fmt;
3663 register enum rtx_code code = GET_CODE (x);
3669 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3670 && REG_USERVAR_P (x))
3671 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3687 if (GET_CODE (SUBREG_REG (x)) == REG
3688 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3689 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3690 = GET_MODE_SIZE (GET_MODE (x));
3697 fmt = GET_RTX_FORMAT (code);
3698 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3701 scan_paradoxical_subregs (XEXP (x, i));
3702 else if (fmt[i] == 'E')
3705 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3706 scan_paradoxical_subregs (XVECEXP (x, i, j));
3711 /* Reload pseudo-registers into hard regs around each insn as needed.
3712 Additional register load insns are output before the insn that needs it
3713 and perhaps store insns after insns that modify the reloaded pseudo reg.
3715 reg_last_reload_reg and reg_reloaded_contents keep track of
3716 which registers are already available in reload registers.
3717 We update these for the reloads that we perform,
3718 as the insns are scanned. */
3721 reload_as_needed (live_known)
3724 struct insn_chain *chain;
3725 #if defined (AUTO_INC_DEC)
3730 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3731 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3732 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3733 reg_has_output_reload = (char *) xmalloc (max_regno);
3734 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3736 set_initial_elim_offsets ();
3738 for (chain = reload_insn_chain; chain; chain = chain->next)
3741 rtx insn = chain->insn;
3742 rtx old_next = NEXT_INSN (insn);
3744 /* If we pass a label, copy the offsets from the label information
3745 into the current offsets of each elimination. */
3746 if (GET_CODE (insn) == CODE_LABEL)
3747 set_offsets_for_label (insn);
3749 else if (INSN_P (insn))
3751 rtx oldpat = PATTERN (insn);
3753 /* If this is a USE and CLOBBER of a MEM, ensure that any
3754 references to eliminable registers have been removed. */
3756 if ((GET_CODE (PATTERN (insn)) == USE
3757 || GET_CODE (PATTERN (insn)) == CLOBBER)
3758 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3759 XEXP (XEXP (PATTERN (insn), 0), 0)
3760 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3761 GET_MODE (XEXP (PATTERN (insn), 0)),
3764 /* If we need to do register elimination processing, do so.
3765 This might delete the insn, in which case we are done. */
3766 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3768 eliminate_regs_in_insn (insn, 1);
3769 if (GET_CODE (insn) == NOTE)
3771 update_eliminable_offsets ();
3776 /* If need_elim is nonzero but need_reload is zero, one might think
3777 that we could simply set n_reloads to 0. However, find_reloads
3778 could have done some manipulation of the insn (such as swapping
3779 commutative operands), and these manipulations are lost during
3780 the first pass for every insn that needs register elimination.
3781 So the actions of find_reloads must be redone here. */
3783 if (! chain->need_elim && ! chain->need_reload
3784 && ! chain->need_operand_change)
3786 /* First find the pseudo regs that must be reloaded for this insn.
3787 This info is returned in the tables reload_... (see reload.h).
3788 Also modify the body of INSN by substituting RELOAD
3789 rtx's for those pseudo regs. */
3792 memset (reg_has_output_reload, 0, max_regno);
3793 CLEAR_HARD_REG_SET (reg_is_output_reload);
3795 find_reloads (insn, 1, spill_indirect_levels, live_known,
3799 if (num_eliminable && chain->need_elim)
3800 update_eliminable_offsets ();
3804 rtx next = NEXT_INSN (insn);
3807 prev = PREV_INSN (insn);
3809 /* Now compute which reload regs to reload them into. Perhaps
3810 reusing reload regs from previous insns, or else output
3811 load insns to reload them. Maybe output store insns too.
3812 Record the choices of reload reg in reload_reg_rtx. */
3813 choose_reload_regs (chain);
3815 /* Merge any reloads that we didn't combine for fear of
3816 increasing the number of spill registers needed but now
3817 discover can be safely merged. */
3818 if (SMALL_REGISTER_CLASSES)
3819 merge_assigned_reloads (insn);
3821 /* Generate the insns to reload operands into or out of
3822 their reload regs. */
3823 emit_reload_insns (chain);
3825 /* Substitute the chosen reload regs from reload_reg_rtx
3826 into the insn's body (or perhaps into the bodies of other
3827 load and store insn that we just made for reloading
3828 and that we moved the structure into). */
3831 /* If this was an ASM, make sure that all the reload insns
3832 we have generated are valid. If not, give an error
3835 if (asm_noperands (PATTERN (insn)) >= 0)
3836 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3837 if (p != insn && INSN_P (p)
3838 && (recog_memoized (p) < 0
3839 || (extract_insn (p), ! constrain_operands (1))))
3841 error_for_asm (insn,
3842 "`asm' operand requires impossible reload");
3844 NOTE_SOURCE_FILE (p) = 0;
3845 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3848 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3849 is no longer validly lying around to save a future reload.
3850 Note that this does not detect pseudos that were reloaded
3851 for this insn in order to be stored in
3852 (obeying register constraints). That is correct; such reload
3853 registers ARE still valid. */
3854 note_stores (oldpat, forget_old_reloads_1, NULL);
3856 /* There may have been CLOBBER insns placed after INSN. So scan
3857 between INSN and NEXT and use them to forget old reloads. */
3858 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3859 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3860 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3863 /* Likewise for regs altered by auto-increment in this insn.
3864 REG_INC notes have been changed by reloading:
3865 find_reloads_address_1 records substitutions for them,
3866 which have been performed by subst_reloads above. */
3867 for (i = n_reloads - 1; i >= 0; i--)
3869 rtx in_reg = rld[i].in_reg;
3872 enum rtx_code code = GET_CODE (in_reg);
3873 /* PRE_INC / PRE_DEC will have the reload register ending up
3874 with the same value as the stack slot, but that doesn't
3875 hold true for POST_INC / POST_DEC. Either we have to
3876 convert the memory access to a true POST_INC / POST_DEC,
3877 or we can't use the reload register for inheritance. */
3878 if ((code == POST_INC || code == POST_DEC)
3879 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3880 REGNO (rld[i].reg_rtx))
3881 /* Make sure it is the inc/dec pseudo, and not
3882 some other (e.g. output operand) pseudo. */
3883 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3884 == REGNO (XEXP (in_reg, 0))))
3887 rtx reload_reg = rld[i].reg_rtx;
3888 enum machine_mode mode = GET_MODE (reload_reg);
3892 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3894 /* We really want to ignore REG_INC notes here, so
3895 use PATTERN (p) as argument to reg_set_p . */
3896 if (reg_set_p (reload_reg, PATTERN (p)))
3898 n = count_occurrences (PATTERN (p), reload_reg, 0);
3903 n = validate_replace_rtx (reload_reg,
3904 gen_rtx (code, mode,
3908 /* We must also verify that the constraints
3909 are met after the replacement. */
3912 n = constrain_operands (1);
3916 /* If the constraints were not met, then
3917 undo the replacement. */
3920 validate_replace_rtx (gen_rtx (code, mode,
3932 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3934 /* Mark this as having an output reload so that the
3935 REG_INC processing code below won't invalidate
3936 the reload for inheritance. */
3937 SET_HARD_REG_BIT (reg_is_output_reload,
3938 REGNO (reload_reg));
3939 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3942 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3945 else if ((code == PRE_INC || code == PRE_DEC)
3946 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3947 REGNO (rld[i].reg_rtx))
3948 /* Make sure it is the inc/dec pseudo, and not
3949 some other (e.g. output operand) pseudo. */
3950 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3951 == REGNO (XEXP (in_reg, 0))))
3953 SET_HARD_REG_BIT (reg_is_output_reload,
3954 REGNO (rld[i].reg_rtx));
3955 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3959 /* If a pseudo that got a hard register is auto-incremented,
3960 we must purge records of copying it into pseudos without
3962 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3963 if (REG_NOTE_KIND (x) == REG_INC)
3965 /* See if this pseudo reg was reloaded in this insn.
3966 If so, its last-reload info is still valid
3967 because it is based on this insn's reload. */
3968 for (i = 0; i < n_reloads; i++)
3969 if (rld[i].out == XEXP (x, 0))
3973 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3977 /* A reload reg's contents are unknown after a label. */
3978 if (GET_CODE (insn) == CODE_LABEL)
3979 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3981 /* Don't assume a reload reg is still good after a call insn
3982 if it is a call-used reg. */
3983 else if (GET_CODE (insn) == CALL_INSN)
3984 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3988 free (reg_last_reload_reg);
3989 free (reg_has_output_reload);
3992 /* Discard all record of any value reloaded from X,
3993 or reloaded in X from someplace else;
3994 unless X is an output reload reg of the current insn.
3996 X may be a hard reg (the reload reg)
3997 or it may be a pseudo reg that was reloaded from. */
4000 forget_old_reloads_1 (x, ignored, data)
4002 rtx ignored ATTRIBUTE_UNUSED;
4003 void *data ATTRIBUTE_UNUSED;
4009 /* note_stores does give us subregs of hard regs. */
4010 while (GET_CODE (x) == SUBREG)
4012 offset += SUBREG_WORD (x);
4016 if (GET_CODE (x) != REG)
4019 regno = REGNO (x) + offset;
4021 if (regno >= FIRST_PSEUDO_REGISTER)
4027 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4028 /* Storing into a spilled-reg invalidates its contents.
4029 This can happen if a block-local pseudo is allocated to that reg
4030 and it wasn't spilled because this block's total need is 0.
4031 Then some insn might have an optional reload and use this reg. */
4032 for (i = 0; i < nr; i++)
4033 /* But don't do this if the reg actually serves as an output
4034 reload reg in the current instruction. */
4036 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4038 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4039 spill_reg_store[regno + i] = 0;
4043 /* Since value of X has changed,
4044 forget any value previously copied from it. */
4047 /* But don't forget a copy if this is the output reload
4048 that establishes the copy's validity. */
4049 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4050 reg_last_reload_reg[regno + nr] = 0;
4053 /* The following HARD_REG_SETs indicate when each hard register is
4054 used for a reload of various parts of the current insn. */
4056 /* If reg is unavailable for all reloads. */
4057 static HARD_REG_SET reload_reg_unavailable;
4058 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4059 static HARD_REG_SET reload_reg_used;
4060 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4061 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4062 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4063 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4064 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4065 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4066 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4067 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4068 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4069 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4070 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4071 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4072 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4073 static HARD_REG_SET reload_reg_used_in_op_addr;
4074 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4075 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4076 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4077 static HARD_REG_SET reload_reg_used_in_insn;
4078 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4079 static HARD_REG_SET reload_reg_used_in_other_addr;
4081 /* If reg is in use as a reload reg for any sort of reload. */
4082 static HARD_REG_SET reload_reg_used_at_all;
4084 /* If reg is use as an inherited reload. We just mark the first register
4086 static HARD_REG_SET reload_reg_used_for_inherit;
4088 /* Records which hard regs are used in any way, either as explicit use or
4089 by being allocated to a pseudo during any point of the current insn. */
4090 static HARD_REG_SET reg_used_in_insn;
4092 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4093 TYPE. MODE is used to indicate how many consecutive regs are
4097 mark_reload_reg_in_use (regno, opnum, type, mode)
4100 enum reload_type type;
4101 enum machine_mode mode;
4103 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4106 for (i = regno; i < nregs + regno; i++)
4111 SET_HARD_REG_BIT (reload_reg_used, i);
4114 case RELOAD_FOR_INPUT_ADDRESS:
4115 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4118 case RELOAD_FOR_INPADDR_ADDRESS:
4119 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4122 case RELOAD_FOR_OUTPUT_ADDRESS:
4123 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4126 case RELOAD_FOR_OUTADDR_ADDRESS:
4127 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4130 case RELOAD_FOR_OPERAND_ADDRESS:
4131 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4134 case RELOAD_FOR_OPADDR_ADDR:
4135 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4138 case RELOAD_FOR_OTHER_ADDRESS:
4139 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4142 case RELOAD_FOR_INPUT:
4143 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4146 case RELOAD_FOR_OUTPUT:
4147 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4150 case RELOAD_FOR_INSN:
4151 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4155 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4159 /* Similarly, but show REGNO is no longer in use for a reload. */
4162 clear_reload_reg_in_use (regno, opnum, type, mode)
4165 enum reload_type type;
4166 enum machine_mode mode;
4168 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4169 unsigned int start_regno, end_regno, r;
4171 /* A complication is that for some reload types, inheritance might
4172 allow multiple reloads of the same types to share a reload register.
4173 We set check_opnum if we have to check only reloads with the same
4174 operand number, and check_any if we have to check all reloads. */
4175 int check_opnum = 0;
4177 HARD_REG_SET *used_in_set;
4182 used_in_set = &reload_reg_used;
4185 case RELOAD_FOR_INPUT_ADDRESS:
4186 used_in_set = &reload_reg_used_in_input_addr[opnum];
4189 case RELOAD_FOR_INPADDR_ADDRESS:
4191 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4194 case RELOAD_FOR_OUTPUT_ADDRESS:
4195 used_in_set = &reload_reg_used_in_output_addr[opnum];
4198 case RELOAD_FOR_OUTADDR_ADDRESS:
4200 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4203 case RELOAD_FOR_OPERAND_ADDRESS:
4204 used_in_set = &reload_reg_used_in_op_addr;
4207 case RELOAD_FOR_OPADDR_ADDR:
4209 used_in_set = &reload_reg_used_in_op_addr_reload;
4212 case RELOAD_FOR_OTHER_ADDRESS:
4213 used_in_set = &reload_reg_used_in_other_addr;
4217 case RELOAD_FOR_INPUT:
4218 used_in_set = &reload_reg_used_in_input[opnum];
4221 case RELOAD_FOR_OUTPUT:
4222 used_in_set = &reload_reg_used_in_output[opnum];
4225 case RELOAD_FOR_INSN:
4226 used_in_set = &reload_reg_used_in_insn;
4231 /* We resolve conflicts with remaining reloads of the same type by
4232 excluding the intervals of of reload registers by them from the
4233 interval of freed reload registers. Since we only keep track of
4234 one set of interval bounds, we might have to exclude somewhat
4235 more then what would be necessary if we used a HARD_REG_SET here.
4236 But this should only happen very infrequently, so there should
4237 be no reason to worry about it. */
4239 start_regno = regno;
4240 end_regno = regno + nregs;
4241 if (check_opnum || check_any)
4243 for (i = n_reloads - 1; i >= 0; i--)
4245 if (rld[i].when_needed == type
4246 && (check_any || rld[i].opnum == opnum)
4249 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4250 unsigned int conflict_end
4252 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4254 /* If there is an overlap with the first to-be-freed register,
4255 adjust the interval start. */
4256 if (conflict_start <= start_regno && conflict_end > start_regno)
4257 start_regno = conflict_end;
4258 /* Otherwise, if there is a conflict with one of the other
4259 to-be-freed registers, adjust the interval end. */
4260 if (conflict_start > start_regno && conflict_start < end_regno)
4261 end_regno = conflict_start;
4266 for (r = start_regno; r < end_regno; r++)
4267 CLEAR_HARD_REG_BIT (*used_in_set, r);
4270 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4271 specified by OPNUM and TYPE. */
4274 reload_reg_free_p (regno, opnum, type)
4277 enum reload_type type;
4281 /* In use for a RELOAD_OTHER means it's not available for anything. */
4282 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4283 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4289 /* In use for anything means we can't use it for RELOAD_OTHER. */
4290 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4291 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4292 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4295 for (i = 0; i < reload_n_operands; i++)
4296 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4297 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4298 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4299 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4300 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4301 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4306 case RELOAD_FOR_INPUT:
4307 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4308 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4311 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4314 /* If it is used for some other input, can't use it. */
4315 for (i = 0; i < reload_n_operands; i++)
4316 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4319 /* If it is used in a later operand's address, can't use it. */
4320 for (i = opnum + 1; i < reload_n_operands; i++)
4321 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4322 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4327 case RELOAD_FOR_INPUT_ADDRESS:
4328 /* Can't use a register if it is used for an input address for this
4329 operand or used as an input in an earlier one. */
4330 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4331 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4334 for (i = 0; i < opnum; i++)
4335 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4340 case RELOAD_FOR_INPADDR_ADDRESS:
4341 /* Can't use a register if it is used for an input address
4342 for this operand or used as an input in an earlier
4344 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4347 for (i = 0; i < opnum; i++)
4348 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4353 case RELOAD_FOR_OUTPUT_ADDRESS:
4354 /* Can't use a register if it is used for an output address for this
4355 operand or used as an output in this or a later operand. */
4356 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4359 for (i = opnum; i < reload_n_operands; i++)
4360 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4365 case RELOAD_FOR_OUTADDR_ADDRESS:
4366 /* Can't use a register if it is used for an output address
4367 for this operand or used as an output in this or a
4369 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4372 for (i = opnum; i < reload_n_operands; i++)
4373 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4378 case RELOAD_FOR_OPERAND_ADDRESS:
4379 for (i = 0; i < reload_n_operands; i++)
4380 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4383 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4384 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4386 case RELOAD_FOR_OPADDR_ADDR:
4387 for (i = 0; i < reload_n_operands; i++)
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4391 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4393 case RELOAD_FOR_OUTPUT:
4394 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4395 outputs, or an operand address for this or an earlier output. */
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4399 for (i = 0; i < reload_n_operands; i++)
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4403 for (i = 0; i <= opnum; i++)
4404 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4405 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4410 case RELOAD_FOR_INSN:
4411 for (i = 0; i < reload_n_operands; i++)
4412 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4413 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4416 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4417 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4419 case RELOAD_FOR_OTHER_ADDRESS:
4420 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4425 /* Return 1 if the value in reload reg REGNO, as used by a reload
4426 needed for the part of the insn specified by OPNUM and TYPE,
4427 is still available in REGNO at the end of the insn.
4429 We can assume that the reload reg was already tested for availability
4430 at the time it is needed, and we should not check this again,
4431 in case the reg has already been marked in use. */
4434 reload_reg_reaches_end_p (regno, opnum, type)
4437 enum reload_type type;
4444 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4445 its value must reach the end. */
4448 /* If this use is for part of the insn,
4449 its value reaches if no subsequent part uses the same register.
4450 Just like the above function, don't try to do this with lots
4453 case RELOAD_FOR_OTHER_ADDRESS:
4454 /* Here we check for everything else, since these don't conflict
4455 with anything else and everything comes later. */
4457 for (i = 0; i < reload_n_operands; i++)
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4459 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4460 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4461 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4462 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4463 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4466 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4467 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4468 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4470 case RELOAD_FOR_INPUT_ADDRESS:
4471 case RELOAD_FOR_INPADDR_ADDRESS:
4472 /* Similar, except that we check only for this and subsequent inputs
4473 and the address of only subsequent inputs and we do not need
4474 to check for RELOAD_OTHER objects since they are known not to
4477 for (i = opnum; i < reload_n_operands; i++)
4478 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4481 for (i = opnum + 1; i < reload_n_operands; i++)
4482 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4483 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4486 for (i = 0; i < reload_n_operands; i++)
4487 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4488 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4489 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4492 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4495 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4496 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4497 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4499 case RELOAD_FOR_INPUT:
4500 /* Similar to input address, except we start at the next operand for
4501 both input and input address and we do not check for
4502 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4505 for (i = opnum + 1; i < reload_n_operands; i++)
4506 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4507 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4508 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4511 /* ... fall through ... */
4513 case RELOAD_FOR_OPERAND_ADDRESS:
4514 /* Check outputs and their addresses. */
4516 for (i = 0; i < reload_n_operands; i++)
4517 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4518 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4519 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4522 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4524 case RELOAD_FOR_OPADDR_ADDR:
4525 for (i = 0; i < reload_n_operands; i++)
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4531 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4532 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4533 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4535 case RELOAD_FOR_INSN:
4536 /* These conflict with other outputs with RELOAD_OTHER. So
4537 we need only check for output addresses. */
4541 /* ... fall through ... */
4543 case RELOAD_FOR_OUTPUT:
4544 case RELOAD_FOR_OUTPUT_ADDRESS:
4545 case RELOAD_FOR_OUTADDR_ADDRESS:
4546 /* We already know these can't conflict with a later output. So the
4547 only thing to check are later output addresses. */
4548 for (i = opnum + 1; i < reload_n_operands; i++)
4549 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4550 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4559 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4562 This function uses the same algorithm as reload_reg_free_p above. */
4565 reloads_conflict (r1, r2)
4568 enum reload_type r1_type = rld[r1].when_needed;
4569 enum reload_type r2_type = rld[r2].when_needed;
4570 int r1_opnum = rld[r1].opnum;
4571 int r2_opnum = rld[r2].opnum;
4573 /* RELOAD_OTHER conflicts with everything. */
4574 if (r2_type == RELOAD_OTHER)
4577 /* Otherwise, check conflicts differently for each type. */
4581 case RELOAD_FOR_INPUT:
4582 return (r2_type == RELOAD_FOR_INSN
4583 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4584 || r2_type == RELOAD_FOR_OPADDR_ADDR
4585 || r2_type == RELOAD_FOR_INPUT
4586 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4587 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4588 && r2_opnum > r1_opnum));
4590 case RELOAD_FOR_INPUT_ADDRESS:
4591 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4592 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4594 case RELOAD_FOR_INPADDR_ADDRESS:
4595 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4596 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4598 case RELOAD_FOR_OUTPUT_ADDRESS:
4599 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4600 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4602 case RELOAD_FOR_OUTADDR_ADDRESS:
4603 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4604 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4606 case RELOAD_FOR_OPERAND_ADDRESS:
4607 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4608 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4610 case RELOAD_FOR_OPADDR_ADDR:
4611 return (r2_type == RELOAD_FOR_INPUT
4612 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4614 case RELOAD_FOR_OUTPUT:
4615 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4616 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4617 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4618 && r2_opnum <= r1_opnum));
4620 case RELOAD_FOR_INSN:
4621 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4622 || r2_type == RELOAD_FOR_INSN
4623 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4625 case RELOAD_FOR_OTHER_ADDRESS:
4626 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4636 /* Indexed by reload number, 1 if incoming value
4637 inherited from previous insns. */
4638 char reload_inherited[MAX_RELOADS];
4640 /* For an inherited reload, this is the insn the reload was inherited from,
4641 if we know it. Otherwise, this is 0. */
4642 rtx reload_inheritance_insn[MAX_RELOADS];
4644 /* If non-zero, this is a place to get the value of the reload,
4645 rather than using reload_in. */
4646 rtx reload_override_in[MAX_RELOADS];
4648 /* For each reload, the hard register number of the register used,
4649 or -1 if we did not need a register for this reload. */
4650 int reload_spill_index[MAX_RELOADS];
4652 /* Return 1 if the value in reload reg REGNO, as used by a reload
4653 needed for the part of the insn specified by OPNUM and TYPE,
4654 may be used to load VALUE into it.
4656 Other read-only reloads with the same value do not conflict
4657 unless OUT is non-zero and these other reloads have to live while
4658 output reloads live.
4659 If OUT is CONST0_RTX, this is a special case: it means that the
4660 test should not be for using register REGNO as reload register, but
4661 for copying from register REGNO into the reload register.
4663 RELOADNUM is the number of the reload we want to load this value for;
4664 a reload does not conflict with itself.
4666 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4667 reloads that load an address for the very reload we are considering.
4669 The caller has to make sure that there is no conflict with the return
4672 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4673 ignore_address_reloads)
4676 enum reload_type type;
4679 int ignore_address_reloads;
4682 /* Set if we see an input reload that must not share its reload register
4683 with any new earlyclobber, but might otherwise share the reload
4684 register with an output or input-output reload. */
4685 int check_earlyclobber = 0;
4689 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4692 if (out == const0_rtx)
4698 /* We use some pseudo 'time' value to check if the lifetimes of the
4699 new register use would overlap with the one of a previous reload
4700 that is not read-only or uses a different value.
4701 The 'time' used doesn't have to be linear in any shape or form, just
4703 Some reload types use different 'buckets' for each operand.
4704 So there are MAX_RECOG_OPERANDS different time values for each
4706 We compute TIME1 as the time when the register for the prospective
4707 new reload ceases to be live, and TIME2 for each existing
4708 reload as the time when that the reload register of that reload
4710 Where there is little to be gained by exact lifetime calculations,
4711 we just make conservative assumptions, i.e. a longer lifetime;
4712 this is done in the 'default:' cases. */
4715 case RELOAD_FOR_OTHER_ADDRESS:
4716 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4717 time1 = copy ? 0 : 1;
4720 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4722 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4723 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4724 respectively, to the time values for these, we get distinct time
4725 values. To get distinct time values for each operand, we have to
4726 multiply opnum by at least three. We round that up to four because
4727 multiply by four is often cheaper. */
4728 case RELOAD_FOR_INPADDR_ADDRESS:
4729 time1 = opnum * 4 + 2;
4731 case RELOAD_FOR_INPUT_ADDRESS:
4732 time1 = opnum * 4 + 3;
4734 case RELOAD_FOR_INPUT:
4735 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4736 executes (inclusive). */
4737 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4739 case RELOAD_FOR_OPADDR_ADDR:
4741 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4742 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4744 case RELOAD_FOR_OPERAND_ADDRESS:
4745 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4747 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4749 case RELOAD_FOR_OUTADDR_ADDRESS:
4750 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4752 case RELOAD_FOR_OUTPUT_ADDRESS:
4753 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4756 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4759 for (i = 0; i < n_reloads; i++)
4761 rtx reg = rld[i].reg_rtx;
4762 if (reg && GET_CODE (reg) == REG
4763 && ((unsigned) regno - true_regnum (reg)
4764 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4767 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4768 || rld[i].out || out)
4771 switch (rld[i].when_needed)
4773 case RELOAD_FOR_OTHER_ADDRESS:
4776 case RELOAD_FOR_INPADDR_ADDRESS:
4777 /* find_reloads makes sure that a
4778 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4779 by at most one - the first -
4780 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4781 address reload is inherited, the address address reload
4782 goes away, so we can ignore this conflict. */
4783 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4784 && ignore_address_reloads
4785 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4786 Then the address address is still needed to store
4787 back the new address. */
4788 && ! rld[reloadnum].out)
4790 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4791 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4793 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4794 && ignore_address_reloads
4795 /* Unless we are reloading an auto_inc expression. */
4796 && ! rld[reloadnum].out)
4798 time2 = rld[i].opnum * 4 + 2;
4800 case RELOAD_FOR_INPUT_ADDRESS:
4801 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4802 && ignore_address_reloads
4803 && ! rld[reloadnum].out)
4805 time2 = rld[i].opnum * 4 + 3;
4807 case RELOAD_FOR_INPUT:
4808 time2 = rld[i].opnum * 4 + 4;
4809 check_earlyclobber = 1;
4811 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4812 == MAX_RECOG_OPERAND * 4 */
4813 case RELOAD_FOR_OPADDR_ADDR:
4814 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4815 && ignore_address_reloads
4816 && ! rld[reloadnum].out)
4818 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4820 case RELOAD_FOR_OPERAND_ADDRESS:
4821 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4822 check_earlyclobber = 1;
4824 case RELOAD_FOR_INSN:
4825 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4827 case RELOAD_FOR_OUTPUT:
4828 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4829 instruction is executed. */
4830 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4832 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4833 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4835 case RELOAD_FOR_OUTADDR_ADDRESS:
4836 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4837 && ignore_address_reloads
4838 && ! rld[reloadnum].out)
4840 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4842 case RELOAD_FOR_OUTPUT_ADDRESS:
4843 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4846 /* If there is no conflict in the input part, handle this
4847 like an output reload. */
4848 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4850 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4851 /* Earlyclobbered outputs must conflict with inputs. */
4852 if (earlyclobber_operand_p (rld[i].out))
4853 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4858 /* RELOAD_OTHER might be live beyond instruction execution,
4859 but this is not obvious when we set time2 = 1. So check
4860 here if there might be a problem with the new reload
4861 clobbering the register used by the RELOAD_OTHER. */
4869 && (! rld[i].in || rld[i].out
4870 || ! rtx_equal_p (rld[i].in, value)))
4871 || (out && rld[reloadnum].out_reg
4872 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4878 /* Earlyclobbered outputs must conflict with inputs. */
4879 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4885 /* Give an error message saying we failed to find a reload for INSN,
4886 and clear out reload R. */
4888 failed_reload (insn, r)
4892 if (asm_noperands (PATTERN (insn)) < 0)
4893 /* It's the compiler's fault. */
4894 fatal_insn ("Could not find a spill register", insn);
4896 /* It's the user's fault; the operand's mode and constraint
4897 don't match. Disable this reload so we don't crash in final. */
4898 error_for_asm (insn,
4899 "`asm' operand constraint incompatible with operand size");
4903 rld[r].optional = 1;
4904 rld[r].secondary_p = 1;
4907 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4908 for reload R. If it's valid, get an rtx for it. Return nonzero if
4911 set_reload_reg (i, r)
4915 rtx reg = spill_reg_rtx[i];
4917 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4918 spill_reg_rtx[i] = reg
4919 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4921 regno = true_regnum (reg);
4923 /* Detect when the reload reg can't hold the reload mode.
4924 This used to be one `if', but Sequent compiler can't handle that. */
4925 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4927 enum machine_mode test_mode = VOIDmode;
4929 test_mode = GET_MODE (rld[r].in);
4930 /* If rld[r].in has VOIDmode, it means we will load it
4931 in whatever mode the reload reg has: to wit, rld[r].mode.
4932 We have already tested that for validity. */
4933 /* Aside from that, we need to test that the expressions
4934 to reload from or into have modes which are valid for this
4935 reload register. Otherwise the reload insns would be invalid. */
4936 if (! (rld[r].in != 0 && test_mode != VOIDmode
4937 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4938 if (! (rld[r].out != 0
4939 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4941 /* The reg is OK. */
4944 /* Mark as in use for this insn the reload regs we use
4946 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4947 rld[r].when_needed, rld[r].mode);
4949 rld[r].reg_rtx = reg;
4950 reload_spill_index[r] = spill_regs[i];
4957 /* Find a spill register to use as a reload register for reload R.
4958 LAST_RELOAD is non-zero if this is the last reload for the insn being
4961 Set rld[R].reg_rtx to the register allocated.
4963 We return 1 if successful, or 0 if we couldn't find a spill reg and
4964 we didn't change anything. */
4967 allocate_reload_reg (chain, r, last_reload)
4968 struct insn_chain *chain ATTRIBUTE_UNUSED;
4974 /* If we put this reload ahead, thinking it is a group,
4975 then insist on finding a group. Otherwise we can grab a
4976 reg that some other reload needs.
4977 (That can happen when we have a 68000 DATA_OR_FP_REG
4978 which is a group of data regs or one fp reg.)
4979 We need not be so restrictive if there are no more reloads
4982 ??? Really it would be nicer to have smarter handling
4983 for that kind of reg class, where a problem like this is normal.
4984 Perhaps those classes should be avoided for reloading
4985 by use of more alternatives. */
4987 int force_group = rld[r].nregs > 1 && ! last_reload;
4989 /* If we want a single register and haven't yet found one,
4990 take any reg in the right class and not in use.
4991 If we want a consecutive group, here is where we look for it.
4993 We use two passes so we can first look for reload regs to
4994 reuse, which are already in use for other reloads in this insn,
4995 and only then use additional registers.
4996 I think that maximizing reuse is needed to make sure we don't
4997 run out of reload regs. Suppose we have three reloads, and
4998 reloads A and B can share regs. These need two regs.
4999 Suppose A and B are given different regs.
5000 That leaves none for C. */
5001 for (pass = 0; pass < 2; pass++)
5003 /* I is the index in spill_regs.
5004 We advance it round-robin between insns to use all spill regs
5005 equally, so that inherited reloads have a chance
5006 of leapfrogging each other. */
5010 for (count = 0; count < n_spills; count++)
5012 int class = (int) rld[r].class;
5018 regnum = spill_regs[i];
5020 if ((reload_reg_free_p (regnum, rld[r].opnum,
5023 /* We check reload_reg_used to make sure we
5024 don't clobber the return register. */
5025 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5026 && reload_reg_free_for_value_p (regnum,
5031 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5032 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5033 /* Look first for regs to share, then for unshared. But
5034 don't share regs used for inherited reloads; they are
5035 the ones we want to preserve. */
5037 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5039 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5042 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5043 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5044 (on 68000) got us two FP regs. If NR is 1,
5045 we would reject both of them. */
5048 /* If we need only one reg, we have already won. */
5051 /* But reject a single reg if we demand a group. */
5056 /* Otherwise check that as many consecutive regs as we need
5057 are available here. */
5060 int regno = regnum + nr - 1;
5061 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5062 && spill_reg_order[regno] >= 0
5063 && reload_reg_free_p (regno, rld[r].opnum,
5064 rld[r].when_needed)))
5073 /* If we found something on pass 1, omit pass 2. */
5074 if (count < n_spills)
5078 /* We should have found a spill register by now. */
5079 if (count >= n_spills)
5082 /* I is the index in SPILL_REG_RTX of the reload register we are to
5083 allocate. Get an rtx for it and find its register number. */
5085 return set_reload_reg (i, r);
5088 /* Initialize all the tables needed to allocate reload registers.
5089 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5090 is the array we use to restore the reg_rtx field for every reload. */
5093 choose_reload_regs_init (chain, save_reload_reg_rtx)
5094 struct insn_chain *chain;
5095 rtx *save_reload_reg_rtx;
5099 for (i = 0; i < n_reloads; i++)
5100 rld[i].reg_rtx = save_reload_reg_rtx[i];
5102 memset (reload_inherited, 0, MAX_RELOADS);
5103 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5104 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5106 CLEAR_HARD_REG_SET (reload_reg_used);
5107 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5108 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5109 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5110 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5111 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5113 CLEAR_HARD_REG_SET (reg_used_in_insn);
5116 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5117 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5118 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5119 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5120 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5121 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5124 for (i = 0; i < reload_n_operands; i++)
5126 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5127 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5128 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5129 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5130 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5131 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5134 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5136 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5138 for (i = 0; i < n_reloads; i++)
5139 /* If we have already decided to use a certain register,
5140 don't use it in another way. */
5142 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5143 rld[i].when_needed, rld[i].mode);
5146 /* Assign hard reg targets for the pseudo-registers we must reload
5147 into hard regs for this insn.
5148 Also output the instructions to copy them in and out of the hard regs.
5150 For machines with register classes, we are responsible for
5151 finding a reload reg in the proper class. */
5154 choose_reload_regs (chain)
5155 struct insn_chain *chain;
5157 rtx insn = chain->insn;
5159 unsigned int max_group_size = 1;
5160 enum reg_class group_class = NO_REGS;
5161 int pass, win, inheritance;
5163 rtx save_reload_reg_rtx[MAX_RELOADS];
5165 /* In order to be certain of getting the registers we need,
5166 we must sort the reloads into order of increasing register class.
5167 Then our grabbing of reload registers will parallel the process
5168 that provided the reload registers.
5170 Also note whether any of the reloads wants a consecutive group of regs.
5171 If so, record the maximum size of the group desired and what
5172 register class contains all the groups needed by this insn. */
5174 for (j = 0; j < n_reloads; j++)
5176 reload_order[j] = j;
5177 reload_spill_index[j] = -1;
5179 if (rld[j].nregs > 1)
5181 max_group_size = MAX (rld[j].nregs, max_group_size);
5183 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5186 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5190 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5192 /* If -O, try first with inheritance, then turning it off.
5193 If not -O, don't do inheritance.
5194 Using inheritance when not optimizing leads to paradoxes
5195 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5196 because one side of the comparison might be inherited. */
5198 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5200 choose_reload_regs_init (chain, save_reload_reg_rtx);
5202 /* Process the reloads in order of preference just found.
5203 Beyond this point, subregs can be found in reload_reg_rtx.
5205 This used to look for an existing reloaded home for all of the
5206 reloads, and only then perform any new reloads. But that could lose
5207 if the reloads were done out of reg-class order because a later
5208 reload with a looser constraint might have an old home in a register
5209 needed by an earlier reload with a tighter constraint.
5211 To solve this, we make two passes over the reloads, in the order
5212 described above. In the first pass we try to inherit a reload
5213 from a previous insn. If there is a later reload that needs a
5214 class that is a proper subset of the class being processed, we must
5215 also allocate a spill register during the first pass.
5217 Then make a second pass over the reloads to allocate any reloads
5218 that haven't been given registers yet. */
5220 for (j = 0; j < n_reloads; j++)
5222 register int r = reload_order[j];
5223 rtx search_equiv = NULL_RTX;
5225 /* Ignore reloads that got marked inoperative. */
5226 if (rld[r].out == 0 && rld[r].in == 0
5227 && ! rld[r].secondary_p)
5230 /* If find_reloads chose to use reload_in or reload_out as a reload
5231 register, we don't need to chose one. Otherwise, try even if it
5232 found one since we might save an insn if we find the value lying
5234 Try also when reload_in is a pseudo without a hard reg. */
5235 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5236 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5237 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5238 && GET_CODE (rld[r].in) != MEM
5239 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5242 #if 0 /* No longer needed for correct operation.
5243 It might give better code, or might not; worth an experiment? */
5244 /* If this is an optional reload, we can't inherit from earlier insns
5245 until we are sure that any non-optional reloads have been allocated.
5246 The following code takes advantage of the fact that optional reloads
5247 are at the end of reload_order. */
5248 if (rld[r].optional != 0)
5249 for (i = 0; i < j; i++)
5250 if ((rld[reload_order[i]].out != 0
5251 || rld[reload_order[i]].in != 0
5252 || rld[reload_order[i]].secondary_p)
5253 && ! rld[reload_order[i]].optional
5254 && rld[reload_order[i]].reg_rtx == 0)
5255 allocate_reload_reg (chain, reload_order[i], 0);
5258 /* First see if this pseudo is already available as reloaded
5259 for a previous insn. We cannot try to inherit for reloads
5260 that are smaller than the maximum number of registers needed
5261 for groups unless the register we would allocate cannot be used
5264 We could check here to see if this is a secondary reload for
5265 an object that is already in a register of the desired class.
5266 This would avoid the need for the secondary reload register.
5267 But this is complex because we can't easily determine what
5268 objects might want to be loaded via this reload. So let a
5269 register be allocated here. In `emit_reload_insns' we suppress
5270 one of the loads in the case described above. */
5275 register int regno = -1;
5276 enum machine_mode mode = VOIDmode;
5280 else if (GET_CODE (rld[r].in) == REG)
5282 regno = REGNO (rld[r].in);
5283 mode = GET_MODE (rld[r].in);
5285 else if (GET_CODE (rld[r].in_reg) == REG)
5287 regno = REGNO (rld[r].in_reg);
5288 mode = GET_MODE (rld[r].in_reg);
5290 else if (GET_CODE (rld[r].in_reg) == SUBREG
5291 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5293 word = SUBREG_WORD (rld[r].in_reg);
5294 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5295 if (regno < FIRST_PSEUDO_REGISTER)
5297 mode = GET_MODE (rld[r].in_reg);
5300 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5301 || GET_CODE (rld[r].in_reg) == PRE_DEC
5302 || GET_CODE (rld[r].in_reg) == POST_INC
5303 || GET_CODE (rld[r].in_reg) == POST_DEC)
5304 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5306 regno = REGNO (XEXP (rld[r].in_reg, 0));
5307 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5308 rld[r].out = rld[r].in;
5312 /* This won't work, since REGNO can be a pseudo reg number.
5313 Also, it takes much more hair to keep track of all the things
5314 that can invalidate an inherited reload of part of a pseudoreg. */
5315 else if (GET_CODE (rld[r].in) == SUBREG
5316 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5317 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5320 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5322 enum reg_class class = rld[r].class, last_class;
5323 rtx last_reg = reg_last_reload_reg[regno];
5324 enum machine_mode need_mode;
5326 i = REGNO (last_reg) + word;
5327 last_class = REGNO_REG_CLASS (i);
5333 = smallest_mode_for_size (GET_MODE_SIZE (mode)
5334 + word * UNITS_PER_WORD,
5335 GET_MODE_CLASS (mode));
5338 #ifdef CLASS_CANNOT_CHANGE_MODE
5340 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5341 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5343 : (GET_MODE_SIZE (GET_MODE (last_reg))
5344 >= GET_MODE_SIZE (need_mode)))
5346 (GET_MODE_SIZE (GET_MODE (last_reg))
5347 >= GET_MODE_SIZE (need_mode))
5349 && reg_reloaded_contents[i] == regno
5350 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5351 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5352 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5353 /* Even if we can't use this register as a reload
5354 register, we might use it for reload_override_in,
5355 if copying it to the desired class is cheap
5357 || ((REGISTER_MOVE_COST (last_class, class)
5358 < MEMORY_MOVE_COST (mode, class, 1))
5359 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5360 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5364 #ifdef SECONDARY_MEMORY_NEEDED
5365 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5370 && (rld[r].nregs == max_group_size
5371 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5373 && reload_reg_free_for_value_p (i, rld[r].opnum,
5378 /* If a group is needed, verify that all the subsequent
5379 registers still have their values intact. */
5380 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5383 for (k = 1; k < nr; k++)
5384 if (reg_reloaded_contents[i + k] != regno
5385 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5392 last_reg = (GET_MODE (last_reg) == mode
5393 ? last_reg : gen_rtx_REG (mode, i));
5395 /* We found a register that contains the
5396 value we need. If this register is the
5397 same as an `earlyclobber' operand of the
5398 current insn, just mark it as a place to
5399 reload from since we can't use it as the
5400 reload register itself. */
5402 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5403 if (reg_overlap_mentioned_for_reload_p
5404 (reg_last_reload_reg[regno],
5405 reload_earlyclobbers[i1]))
5408 if (i1 != n_earlyclobbers
5409 || ! (reload_reg_free_for_value_p
5410 (i, rld[r].opnum, rld[r].when_needed,
5411 rld[r].in, rld[r].out, r, 1))
5412 /* Don't use it if we'd clobber a pseudo reg. */
5413 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5415 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5416 /* Don't clobber the frame pointer. */
5417 || (i == HARD_FRAME_POINTER_REGNUM
5419 /* Don't really use the inherited spill reg
5420 if we need it wider than we've got it. */
5421 || (GET_MODE_SIZE (rld[r].mode)
5422 > GET_MODE_SIZE (mode))
5423 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5426 /* If find_reloads chose reload_out as reload
5427 register, stay with it - that leaves the
5428 inherited register for subsequent reloads. */
5429 || (rld[r].out && rld[r].reg_rtx
5430 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5432 if (! rld[r].optional)
5434 reload_override_in[r] = last_reg;
5435 reload_inheritance_insn[r]
5436 = reg_reloaded_insn[i];
5442 /* We can use this as a reload reg. */
5443 /* Mark the register as in use for this part of
5445 mark_reload_reg_in_use (i,
5449 rld[r].reg_rtx = last_reg;
5450 reload_inherited[r] = 1;
5451 reload_inheritance_insn[r]
5452 = reg_reloaded_insn[i];
5453 reload_spill_index[r] = i;
5454 for (k = 0; k < nr; k++)
5455 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5463 /* Here's another way to see if the value is already lying around. */
5466 && ! reload_inherited[r]
5468 && (CONSTANT_P (rld[r].in)
5469 || GET_CODE (rld[r].in) == PLUS
5470 || GET_CODE (rld[r].in) == REG
5471 || GET_CODE (rld[r].in) == MEM)
5472 && (rld[r].nregs == max_group_size
5473 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5474 search_equiv = rld[r].in;
5475 /* If this is an output reload from a simple move insn, look
5476 if an equivalence for the input is available. */
5477 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5479 rtx set = single_set (insn);
5482 && rtx_equal_p (rld[r].out, SET_DEST (set))
5483 && CONSTANT_P (SET_SRC (set)))
5484 search_equiv = SET_SRC (set);
5490 = find_equiv_reg (search_equiv, insn, rld[r].class,
5491 -1, NULL_PTR, 0, rld[r].mode);
5496 if (GET_CODE (equiv) == REG)
5497 regno = REGNO (equiv);
5498 else if (GET_CODE (equiv) == SUBREG)
5500 /* This must be a SUBREG of a hard register.
5501 Make a new REG since this might be used in an
5502 address and not all machines support SUBREGs
5504 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5505 equiv = gen_rtx_REG (rld[r].mode, regno);
5511 /* If we found a spill reg, reject it unless it is free
5512 and of the desired class. */
5514 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5515 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5519 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5523 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5526 /* We found a register that contains the value we need.
5527 If this register is the same as an `earlyclobber' operand
5528 of the current insn, just mark it as a place to reload from
5529 since we can't use it as the reload register itself. */
5532 for (i = 0; i < n_earlyclobbers; i++)
5533 if (reg_overlap_mentioned_for_reload_p (equiv,
5534 reload_earlyclobbers[i]))
5536 if (! rld[r].optional)
5537 reload_override_in[r] = equiv;
5542 /* If the equiv register we have found is explicitly clobbered
5543 in the current insn, it depends on the reload type if we
5544 can use it, use it for reload_override_in, or not at all.
5545 In particular, we then can't use EQUIV for a
5546 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5550 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5551 switch (rld[r].when_needed)
5553 case RELOAD_FOR_OTHER_ADDRESS:
5554 case RELOAD_FOR_INPADDR_ADDRESS:
5555 case RELOAD_FOR_INPUT_ADDRESS:
5556 case RELOAD_FOR_OPADDR_ADDR:
5559 case RELOAD_FOR_INPUT:
5560 case RELOAD_FOR_OPERAND_ADDRESS:
5561 if (! rld[r].optional)
5562 reload_override_in[r] = equiv;
5568 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5569 switch (rld[r].when_needed)
5571 case RELOAD_FOR_OTHER_ADDRESS:
5572 case RELOAD_FOR_INPADDR_ADDRESS:
5573 case RELOAD_FOR_INPUT_ADDRESS:
5574 case RELOAD_FOR_OPADDR_ADDR:
5575 case RELOAD_FOR_OPERAND_ADDRESS:
5576 case RELOAD_FOR_INPUT:
5579 if (! rld[r].optional)
5580 reload_override_in[r] = equiv;
5588 /* If we found an equivalent reg, say no code need be generated
5589 to load it, and use it as our reload reg. */
5590 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5592 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5594 rld[r].reg_rtx = equiv;
5595 reload_inherited[r] = 1;
5597 /* If reg_reloaded_valid is not set for this register,
5598 there might be a stale spill_reg_store lying around.
5599 We must clear it, since otherwise emit_reload_insns
5600 might delete the store. */
5601 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5602 spill_reg_store[regno] = NULL_RTX;
5603 /* If any of the hard registers in EQUIV are spill
5604 registers, mark them as in use for this insn. */
5605 for (k = 0; k < nr; k++)
5607 i = spill_reg_order[regno + k];
5610 mark_reload_reg_in_use (regno, rld[r].opnum,
5613 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5620 /* If we found a register to use already, or if this is an optional
5621 reload, we are done. */
5622 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5626 /* No longer needed for correct operation. Might or might
5627 not give better code on the average. Want to experiment? */
5629 /* See if there is a later reload that has a class different from our
5630 class that intersects our class or that requires less register
5631 than our reload. If so, we must allocate a register to this
5632 reload now, since that reload might inherit a previous reload
5633 and take the only available register in our class. Don't do this
5634 for optional reloads since they will force all previous reloads
5635 to be allocated. Also don't do this for reloads that have been
5638 for (i = j + 1; i < n_reloads; i++)
5640 int s = reload_order[i];
5642 if ((rld[s].in == 0 && rld[s].out == 0
5643 && ! rld[s].secondary_p)
5647 if ((rld[s].class != rld[r].class
5648 && reg_classes_intersect_p (rld[r].class,
5650 || rld[s].nregs < rld[r].nregs)
5657 allocate_reload_reg (chain, r, j == n_reloads - 1);
5661 /* Now allocate reload registers for anything non-optional that
5662 didn't get one yet. */
5663 for (j = 0; j < n_reloads; j++)
5665 register int r = reload_order[j];
5667 /* Ignore reloads that got marked inoperative. */
5668 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5671 /* Skip reloads that already have a register allocated or are
5673 if (rld[r].reg_rtx != 0 || rld[r].optional)
5676 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5680 /* If that loop got all the way, we have won. */
5687 /* Loop around and try without any inheritance. */
5692 /* First undo everything done by the failed attempt
5693 to allocate with inheritance. */
5694 choose_reload_regs_init (chain, save_reload_reg_rtx);
5696 /* Some sanity tests to verify that the reloads found in the first
5697 pass are identical to the ones we have now. */
5698 if (chain->n_reloads != n_reloads)
5701 for (i = 0; i < n_reloads; i++)
5703 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5705 if (chain->rld[i].when_needed != rld[i].when_needed)
5707 for (j = 0; j < n_spills; j++)
5708 if (spill_regs[j] == chain->rld[i].regno)
5709 if (! set_reload_reg (j, i))
5710 failed_reload (chain->insn, i);
5714 /* If we thought we could inherit a reload, because it seemed that
5715 nothing else wanted the same reload register earlier in the insn,
5716 verify that assumption, now that all reloads have been assigned.
5717 Likewise for reloads where reload_override_in has been set. */
5719 /* If doing expensive optimizations, do one preliminary pass that doesn't
5720 cancel any inheritance, but removes reloads that have been needed only
5721 for reloads that we know can be inherited. */
5722 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5724 for (j = 0; j < n_reloads; j++)
5726 register int r = reload_order[j];
5728 if (reload_inherited[r] && rld[r].reg_rtx)
5729 check_reg = rld[r].reg_rtx;
5730 else if (reload_override_in[r]
5731 && (GET_CODE (reload_override_in[r]) == REG
5732 || GET_CODE (reload_override_in[r]) == SUBREG))
5733 check_reg = reload_override_in[r];
5736 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5740 (reload_inherited[r]
5741 ? rld[r].out : const0_rtx),
5746 reload_inherited[r] = 0;
5747 reload_override_in[r] = 0;
5749 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5750 reload_override_in, then we do not need its related
5751 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5752 likewise for other reload types.
5753 We handle this by removing a reload when its only replacement
5754 is mentioned in reload_in of the reload we are going to inherit.
5755 A special case are auto_inc expressions; even if the input is
5756 inherited, we still need the address for the output. We can
5757 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5758 If we suceeded removing some reload and we are doing a preliminary
5759 pass just to remove such reloads, make another pass, since the
5760 removal of one reload might allow us to inherit another one. */
5762 && rld[r].out != rld[r].in
5763 && remove_address_replacements (rld[r].in) && pass)
5768 /* Now that reload_override_in is known valid,
5769 actually override reload_in. */
5770 for (j = 0; j < n_reloads; j++)
5771 if (reload_override_in[j])
5772 rld[j].in = reload_override_in[j];
5774 /* If this reload won't be done because it has been cancelled or is
5775 optional and not inherited, clear reload_reg_rtx so other
5776 routines (such as subst_reloads) don't get confused. */
5777 for (j = 0; j < n_reloads; j++)
5778 if (rld[j].reg_rtx != 0
5779 && ((rld[j].optional && ! reload_inherited[j])
5780 || (rld[j].in == 0 && rld[j].out == 0
5781 && ! rld[j].secondary_p)))
5783 int regno = true_regnum (rld[j].reg_rtx);
5785 if (spill_reg_order[regno] >= 0)
5786 clear_reload_reg_in_use (regno, rld[j].opnum,
5787 rld[j].when_needed, rld[j].mode);
5789 reload_spill_index[j] = -1;
5792 /* Record which pseudos and which spill regs have output reloads. */
5793 for (j = 0; j < n_reloads; j++)
5795 register int r = reload_order[j];
5797 i = reload_spill_index[r];
5799 /* I is nonneg if this reload uses a register.
5800 If rld[r].reg_rtx is 0, this is an optional reload
5801 that we opted to ignore. */
5802 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5803 && rld[r].reg_rtx != 0)
5805 register int nregno = REGNO (rld[r].out_reg);
5808 if (nregno < FIRST_PSEUDO_REGISTER)
5809 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5812 reg_has_output_reload[nregno + nr] = 1;
5816 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5818 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5821 if (rld[r].when_needed != RELOAD_OTHER
5822 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5823 && rld[r].when_needed != RELOAD_FOR_INSN)
5829 /* Deallocate the reload register for reload R. This is called from
5830 remove_address_replacements. */
5833 deallocate_reload_reg (r)
5838 if (! rld[r].reg_rtx)
5840 regno = true_regnum (rld[r].reg_rtx);
5842 if (spill_reg_order[regno] >= 0)
5843 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5845 reload_spill_index[r] = -1;
5848 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5849 reloads of the same item for fear that we might not have enough reload
5850 registers. However, normally they will get the same reload register
5851 and hence actually need not be loaded twice.
5853 Here we check for the most common case of this phenomenon: when we have
5854 a number of reloads for the same object, each of which were allocated
5855 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5856 reload, and is not modified in the insn itself. If we find such,
5857 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5858 This will not increase the number of spill registers needed and will
5859 prevent redundant code. */
5862 merge_assigned_reloads (insn)
5867 /* Scan all the reloads looking for ones that only load values and
5868 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5869 assigned and not modified by INSN. */
5871 for (i = 0; i < n_reloads; i++)
5873 int conflicting_input = 0;
5874 int max_input_address_opnum = -1;
5875 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5877 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5878 || rld[i].out != 0 || rld[i].reg_rtx == 0
5879 || reg_set_p (rld[i].reg_rtx, insn))
5882 /* Look at all other reloads. Ensure that the only use of this
5883 reload_reg_rtx is in a reload that just loads the same value
5884 as we do. Note that any secondary reloads must be of the identical
5885 class since the values, modes, and result registers are the
5886 same, so we need not do anything with any secondary reloads. */
5888 for (j = 0; j < n_reloads; j++)
5890 if (i == j || rld[j].reg_rtx == 0
5891 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5895 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5896 && rld[j].opnum > max_input_address_opnum)
5897 max_input_address_opnum = rld[j].opnum;
5899 /* If the reload regs aren't exactly the same (e.g, different modes)
5900 or if the values are different, we can't merge this reload.
5901 But if it is an input reload, we might still merge
5902 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5904 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5905 || rld[j].out != 0 || rld[j].in == 0
5906 || ! rtx_equal_p (rld[i].in, rld[j].in))
5908 if (rld[j].when_needed != RELOAD_FOR_INPUT
5909 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5910 || rld[i].opnum > rld[j].opnum)
5911 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5913 conflicting_input = 1;
5914 if (min_conflicting_input_opnum > rld[j].opnum)
5915 min_conflicting_input_opnum = rld[j].opnum;
5919 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5920 we, in fact, found any matching reloads. */
5923 && max_input_address_opnum <= min_conflicting_input_opnum)
5925 for (j = 0; j < n_reloads; j++)
5926 if (i != j && rld[j].reg_rtx != 0
5927 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5928 && (! conflicting_input
5929 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5930 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5932 rld[i].when_needed = RELOAD_OTHER;
5934 reload_spill_index[j] = -1;
5935 transfer_replacements (i, j);
5938 /* If this is now RELOAD_OTHER, look for any reloads that load
5939 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5940 if they were for inputs, RELOAD_OTHER for outputs. Note that
5941 this test is equivalent to looking for reloads for this operand
5944 if (rld[i].when_needed == RELOAD_OTHER)
5945 for (j = 0; j < n_reloads; j++)
5947 && rld[i].when_needed != RELOAD_OTHER
5948 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5951 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5952 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5953 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5958 /* These arrays are filled by emit_reload_insns and its subroutines. */
5959 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5960 static rtx other_input_address_reload_insns = 0;
5961 static rtx other_input_reload_insns = 0;
5962 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5963 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5964 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5965 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5966 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5967 static rtx operand_reload_insns = 0;
5968 static rtx other_operand_reload_insns = 0;
5969 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5971 /* Values to be put in spill_reg_store are put here first. */
5972 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5973 static HARD_REG_SET reg_reloaded_died;
5975 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5976 has the number J. OLD contains the value to be used as input. */
5979 emit_input_reload_insns (chain, rl, old, j)
5980 struct insn_chain *chain;
5985 rtx insn = chain->insn;
5986 register rtx reloadreg = rl->reg_rtx;
5987 rtx oldequiv_reg = 0;
5990 enum machine_mode mode;
5993 /* Determine the mode to reload in.
5994 This is very tricky because we have three to choose from.
5995 There is the mode the insn operand wants (rl->inmode).
5996 There is the mode of the reload register RELOADREG.
5997 There is the intrinsic mode of the operand, which we could find
5998 by stripping some SUBREGs.
5999 It turns out that RELOADREG's mode is irrelevant:
6000 we can change that arbitrarily.
6002 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6003 then the reload reg may not support QImode moves, so use SImode.
6004 If foo is in memory due to spilling a pseudo reg, this is safe,
6005 because the QImode value is in the least significant part of a
6006 slot big enough for a SImode. If foo is some other sort of
6007 memory reference, then it is impossible to reload this case,
6008 so previous passes had better make sure this never happens.
6010 Then consider a one-word union which has SImode and one of its
6011 members is a float, being fetched as (SUBREG:SF union:SI).
6012 We must fetch that as SFmode because we could be loading into
6013 a float-only register. In this case OLD's mode is correct.
6015 Consider an immediate integer: it has VOIDmode. Here we need
6016 to get a mode from something else.
6018 In some cases, there is a fourth mode, the operand's
6019 containing mode. If the insn specifies a containing mode for
6020 this operand, it overrides all others.
6022 I am not sure whether the algorithm here is always right,
6023 but it does the right things in those cases. */
6025 mode = GET_MODE (old);
6026 if (mode == VOIDmode)
6029 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6030 /* If we need a secondary register for this operation, see if
6031 the value is already in a register in that class. Don't
6032 do this if the secondary register will be used as a scratch
6035 if (rl->secondary_in_reload >= 0
6036 && rl->secondary_in_icode == CODE_FOR_nothing
6039 = find_equiv_reg (old, insn,
6040 rld[rl->secondary_in_reload].class,
6041 -1, NULL_PTR, 0, mode);
6044 /* If reloading from memory, see if there is a register
6045 that already holds the same value. If so, reload from there.
6046 We can pass 0 as the reload_reg_p argument because
6047 any other reload has either already been emitted,
6048 in which case find_equiv_reg will see the reload-insn,
6049 or has yet to be emitted, in which case it doesn't matter
6050 because we will use this equiv reg right away. */
6052 if (oldequiv == 0 && optimize
6053 && (GET_CODE (old) == MEM
6054 || (GET_CODE (old) == REG
6055 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6056 && reg_renumber[REGNO (old)] < 0)))
6057 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6058 -1, NULL_PTR, 0, mode);
6062 unsigned int regno = true_regnum (oldequiv);
6064 /* Don't use OLDEQUIV if any other reload changes it at an
6065 earlier stage of this insn or at this stage. */
6066 if (! reload_reg_free_for_value_p (regno, rl->opnum,
6068 rl->in, const0_rtx, j,
6072 /* If it is no cheaper to copy from OLDEQUIV into the
6073 reload register than it would be to move from memory,
6074 don't use it. Likewise, if we need a secondary register
6078 && ((REGNO_REG_CLASS (regno) != rl->class
6079 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6081 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6082 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6083 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6087 #ifdef SECONDARY_MEMORY_NEEDED
6088 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6096 /* delete_output_reload is only invoked properly if old contains
6097 the original pseudo register. Since this is replaced with a
6098 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6099 find the pseudo in RELOAD_IN_REG. */
6101 && reload_override_in[j]
6102 && GET_CODE (rl->in_reg) == REG)
6109 else if (GET_CODE (oldequiv) == REG)
6110 oldequiv_reg = oldequiv;
6111 else if (GET_CODE (oldequiv) == SUBREG)
6112 oldequiv_reg = SUBREG_REG (oldequiv);
6114 /* If we are reloading from a register that was recently stored in
6115 with an output-reload, see if we can prove there was
6116 actually no need to store the old value in it. */
6118 if (optimize && GET_CODE (oldequiv) == REG
6119 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6120 && spill_reg_store[REGNO (oldequiv)]
6121 && GET_CODE (old) == REG
6122 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6123 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6125 delete_output_reload (insn, j, REGNO (oldequiv));
6127 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6128 then load RELOADREG from OLDEQUIV. Note that we cannot use
6129 gen_lowpart_common since it can do the wrong thing when
6130 RELOADREG has a multi-word mode. Note that RELOADREG
6131 must always be a REG here. */
6133 if (GET_MODE (reloadreg) != mode)
6134 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6135 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6136 oldequiv = SUBREG_REG (oldequiv);
6137 if (GET_MODE (oldequiv) != VOIDmode
6138 && mode != GET_MODE (oldequiv))
6139 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6141 /* Switch to the right place to emit the reload insns. */
6142 switch (rl->when_needed)
6145 where = &other_input_reload_insns;
6147 case RELOAD_FOR_INPUT:
6148 where = &input_reload_insns[rl->opnum];
6150 case RELOAD_FOR_INPUT_ADDRESS:
6151 where = &input_address_reload_insns[rl->opnum];
6153 case RELOAD_FOR_INPADDR_ADDRESS:
6154 where = &inpaddr_address_reload_insns[rl->opnum];
6156 case RELOAD_FOR_OUTPUT_ADDRESS:
6157 where = &output_address_reload_insns[rl->opnum];
6159 case RELOAD_FOR_OUTADDR_ADDRESS:
6160 where = &outaddr_address_reload_insns[rl->opnum];
6162 case RELOAD_FOR_OPERAND_ADDRESS:
6163 where = &operand_reload_insns;
6165 case RELOAD_FOR_OPADDR_ADDR:
6166 where = &other_operand_reload_insns;
6168 case RELOAD_FOR_OTHER_ADDRESS:
6169 where = &other_input_address_reload_insns;
6175 push_to_sequence (*where);
6177 /* Auto-increment addresses must be reloaded in a special way. */
6178 if (rl->out && ! rl->out_reg)
6180 /* We are not going to bother supporting the case where a
6181 incremented register can't be copied directly from
6182 OLDEQUIV since this seems highly unlikely. */
6183 if (rl->secondary_in_reload >= 0)
6186 if (reload_inherited[j])
6187 oldequiv = reloadreg;
6189 old = XEXP (rl->in_reg, 0);
6191 if (optimize && GET_CODE (oldequiv) == REG
6192 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6193 && spill_reg_store[REGNO (oldequiv)]
6194 && GET_CODE (old) == REG
6195 && (dead_or_set_p (insn,
6196 spill_reg_stored_to[REGNO (oldequiv)])
6197 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6199 delete_output_reload (insn, j, REGNO (oldequiv));
6201 /* Prevent normal processing of this reload. */
6203 /* Output a special code sequence for this case. */
6204 new_spill_reg_store[REGNO (reloadreg)]
6205 = inc_for_reload (reloadreg, oldequiv, rl->out,
6209 /* If we are reloading a pseudo-register that was set by the previous
6210 insn, see if we can get rid of that pseudo-register entirely
6211 by redirecting the previous insn into our reload register. */
6213 else if (optimize && GET_CODE (old) == REG
6214 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6215 && dead_or_set_p (insn, old)
6216 /* This is unsafe if some other reload
6217 uses the same reg first. */
6218 && reload_reg_free_for_value_p (REGNO (reloadreg),
6224 rtx temp = PREV_INSN (insn);
6225 while (temp && GET_CODE (temp) == NOTE)
6226 temp = PREV_INSN (temp);
6228 && GET_CODE (temp) == INSN
6229 && GET_CODE (PATTERN (temp)) == SET
6230 && SET_DEST (PATTERN (temp)) == old
6231 /* Make sure we can access insn_operand_constraint. */
6232 && asm_noperands (PATTERN (temp)) < 0
6233 /* This is unsafe if prev insn rejects our reload reg. */
6234 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6236 /* This is unsafe if operand occurs more than once in current
6237 insn. Perhaps some occurrences aren't reloaded. */
6238 && count_occurrences (PATTERN (insn), old, 0) == 1
6239 /* Don't risk splitting a matching pair of operands. */
6240 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6242 /* Store into the reload register instead of the pseudo. */
6243 SET_DEST (PATTERN (temp)) = reloadreg;
6245 /* If the previous insn is an output reload, the source is
6246 a reload register, and its spill_reg_store entry will
6247 contain the previous destination. This is now
6249 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6250 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6252 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6253 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6256 /* If these are the only uses of the pseudo reg,
6257 pretend for GDB it lives in the reload reg we used. */
6258 if (REG_N_DEATHS (REGNO (old)) == 1
6259 && REG_N_SETS (REGNO (old)) == 1)
6261 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6262 alter_reg (REGNO (old), -1);
6268 /* We can't do that, so output an insn to load RELOADREG. */
6270 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6271 /* If we have a secondary reload, pick up the secondary register
6272 and icode, if any. If OLDEQUIV and OLD are different or
6273 if this is an in-out reload, recompute whether or not we
6274 still need a secondary register and what the icode should
6275 be. If we still need a secondary register and the class or
6276 icode is different, go back to reloading from OLD if using
6277 OLDEQUIV means that we got the wrong type of register. We
6278 cannot have different class or icode due to an in-out reload
6279 because we don't make such reloads when both the input and
6280 output need secondary reload registers. */
6282 if (! special && rl->secondary_in_reload >= 0)
6284 rtx second_reload_reg = 0;
6285 int secondary_reload = rl->secondary_in_reload;
6286 rtx real_oldequiv = oldequiv;
6289 enum insn_code icode;
6291 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6292 and similarly for OLD.
6293 See comments in get_secondary_reload in reload.c. */
6294 /* If it is a pseudo that cannot be replaced with its
6295 equivalent MEM, we must fall back to reload_in, which
6296 will have all the necessary substitutions registered.
6297 Likewise for a pseudo that can't be replaced with its
6298 equivalent constant.
6300 Take extra care for subregs of such pseudos. Note that
6301 we cannot use reg_equiv_mem in this case because it is
6302 not in the right mode. */
6305 if (GET_CODE (tmp) == SUBREG)
6306 tmp = SUBREG_REG (tmp);
6307 if (GET_CODE (tmp) == REG
6308 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6309 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6310 || reg_equiv_constant[REGNO (tmp)] != 0))
6312 if (! reg_equiv_mem[REGNO (tmp)]
6313 || num_not_at_initial_offset
6314 || GET_CODE (oldequiv) == SUBREG)
6315 real_oldequiv = rl->in;
6317 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6321 if (GET_CODE (tmp) == SUBREG)
6322 tmp = SUBREG_REG (tmp);
6323 if (GET_CODE (tmp) == REG
6324 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6325 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6326 || reg_equiv_constant[REGNO (tmp)] != 0))
6328 if (! reg_equiv_mem[REGNO (tmp)]
6329 || num_not_at_initial_offset
6330 || GET_CODE (old) == SUBREG)
6333 real_old = reg_equiv_mem[REGNO (tmp)];
6336 second_reload_reg = rld[secondary_reload].reg_rtx;
6337 icode = rl->secondary_in_icode;
6339 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6340 || (rl->in != 0 && rl->out != 0))
6342 enum reg_class new_class
6343 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6344 mode, real_oldequiv);
6346 if (new_class == NO_REGS)
6347 second_reload_reg = 0;
6350 enum insn_code new_icode;
6351 enum machine_mode new_mode;
6353 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6354 REGNO (second_reload_reg)))
6355 oldequiv = old, real_oldequiv = real_old;
6358 new_icode = reload_in_optab[(int) mode];
6359 if (new_icode != CODE_FOR_nothing
6360 && ((insn_data[(int) new_icode].operand[0].predicate
6361 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6363 || (insn_data[(int) new_icode].operand[1].predicate
6364 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6365 (real_oldequiv, mode)))))
6366 new_icode = CODE_FOR_nothing;
6368 if (new_icode == CODE_FOR_nothing)
6371 new_mode = insn_data[(int) new_icode].operand[2].mode;
6373 if (GET_MODE (second_reload_reg) != new_mode)
6375 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6377 oldequiv = old, real_oldequiv = real_old;
6380 = gen_rtx_REG (new_mode,
6381 REGNO (second_reload_reg));
6387 /* If we still need a secondary reload register, check
6388 to see if it is being used as a scratch or intermediate
6389 register and generate code appropriately. If we need
6390 a scratch register, use REAL_OLDEQUIV since the form of
6391 the insn may depend on the actual address if it is
6394 if (second_reload_reg)
6396 if (icode != CODE_FOR_nothing)
6398 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6399 second_reload_reg));
6404 /* See if we need a scratch register to load the
6405 intermediate register (a tertiary reload). */
6406 enum insn_code tertiary_icode
6407 = rld[secondary_reload].secondary_in_icode;
6409 if (tertiary_icode != CODE_FOR_nothing)
6411 rtx third_reload_reg
6412 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6414 emit_insn ((GEN_FCN (tertiary_icode)
6415 (second_reload_reg, real_oldequiv,
6416 third_reload_reg)));
6419 gen_reload (second_reload_reg, real_oldequiv,
6423 oldequiv = second_reload_reg;
6429 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6431 rtx real_oldequiv = oldequiv;
6433 if ((GET_CODE (oldequiv) == REG
6434 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6435 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6436 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6437 || (GET_CODE (oldequiv) == SUBREG
6438 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6439 && (REGNO (SUBREG_REG (oldequiv))
6440 >= FIRST_PSEUDO_REGISTER)
6441 && ((reg_equiv_memory_loc
6442 [REGNO (SUBREG_REG (oldequiv))] != 0)
6443 || (reg_equiv_constant
6444 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6445 || (CONSTANT_P (oldequiv)
6446 && PREFERRED_RELOAD_CLASS (oldequiv,
6447 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6448 real_oldequiv = rl->in;
6449 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6453 /* End this sequence. */
6454 *where = get_insns ();
6457 /* Update reload_override_in so that delete_address_reloads_1
6458 can see the actual register usage. */
6460 reload_override_in[j] = oldequiv;
6463 /* Generate insns to for the output reload RL, which is for the insn described
6464 by CHAIN and has the number J. */
6466 emit_output_reload_insns (chain, rl, j)
6467 struct insn_chain *chain;
6471 rtx reloadreg = rl->reg_rtx;
6472 rtx insn = chain->insn;
6475 enum machine_mode mode = GET_MODE (old);
6478 if (rl->when_needed == RELOAD_OTHER)
6481 push_to_sequence (output_reload_insns[rl->opnum]);
6483 /* Determine the mode to reload in.
6484 See comments above (for input reloading). */
6486 if (mode == VOIDmode)
6488 /* VOIDmode should never happen for an output. */
6489 if (asm_noperands (PATTERN (insn)) < 0)
6490 /* It's the compiler's fault. */
6491 fatal_insn ("VOIDmode on an output", insn);
6492 error_for_asm (insn, "output operand is constant in `asm'");
6493 /* Prevent crash--use something we know is valid. */
6495 old = gen_rtx_REG (mode, REGNO (reloadreg));
6498 if (GET_MODE (reloadreg) != mode)
6499 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6501 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6503 /* If we need two reload regs, set RELOADREG to the intermediate
6504 one, since it will be stored into OLD. We might need a secondary
6505 register only for an input reload, so check again here. */
6507 if (rl->secondary_out_reload >= 0)
6511 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6512 && reg_equiv_mem[REGNO (old)] != 0)
6513 real_old = reg_equiv_mem[REGNO (old)];
6515 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6519 rtx second_reloadreg = reloadreg;
6520 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6522 /* See if RELOADREG is to be used as a scratch register
6523 or as an intermediate register. */
6524 if (rl->secondary_out_icode != CODE_FOR_nothing)
6526 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6527 (real_old, second_reloadreg, reloadreg)));
6532 /* See if we need both a scratch and intermediate reload
6535 int secondary_reload = rl->secondary_out_reload;
6536 enum insn_code tertiary_icode
6537 = rld[secondary_reload].secondary_out_icode;
6539 if (GET_MODE (reloadreg) != mode)
6540 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6542 if (tertiary_icode != CODE_FOR_nothing)
6545 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6548 /* Copy primary reload reg to secondary reload reg.
6549 (Note that these have been swapped above, then
6550 secondary reload reg to OLD using our insn. */
6552 /* If REAL_OLD is a paradoxical SUBREG, remove it
6553 and try to put the opposite SUBREG on
6555 if (GET_CODE (real_old) == SUBREG
6556 && (GET_MODE_SIZE (GET_MODE (real_old))
6557 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6558 && 0 != (tem = gen_lowpart_common
6559 (GET_MODE (SUBREG_REG (real_old)),
6561 real_old = SUBREG_REG (real_old), reloadreg = tem;
6563 gen_reload (reloadreg, second_reloadreg,
6564 rl->opnum, rl->when_needed);
6565 emit_insn ((GEN_FCN (tertiary_icode)
6566 (real_old, reloadreg, third_reloadreg)));
6571 /* Copy between the reload regs here and then to
6574 gen_reload (reloadreg, second_reloadreg,
6575 rl->opnum, rl->when_needed);
6581 /* Output the last reload insn. */
6586 /* Don't output the last reload if OLD is not the dest of
6587 INSN and is in the src and is clobbered by INSN. */
6588 if (! flag_expensive_optimizations
6589 || GET_CODE (old) != REG
6590 || !(set = single_set (insn))
6591 || rtx_equal_p (old, SET_DEST (set))
6592 || !reg_mentioned_p (old, SET_SRC (set))
6593 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6594 gen_reload (old, reloadreg, rl->opnum,
6598 /* Look at all insns we emitted, just to be safe. */
6599 for (p = get_insns (); p; p = NEXT_INSN (p))
6602 rtx pat = PATTERN (p);
6604 /* If this output reload doesn't come from a spill reg,
6605 clear any memory of reloaded copies of the pseudo reg.
6606 If this output reload comes from a spill reg,
6607 reg_has_output_reload will make this do nothing. */
6608 note_stores (pat, forget_old_reloads_1, NULL);
6610 if (reg_mentioned_p (rl->reg_rtx, pat))
6612 rtx set = single_set (insn);
6613 if (reload_spill_index[j] < 0
6615 && SET_SRC (set) == rl->reg_rtx)
6617 int src = REGNO (SET_SRC (set));
6619 reload_spill_index[j] = src;
6620 SET_HARD_REG_BIT (reg_is_output_reload, src);
6621 if (find_regno_note (insn, REG_DEAD, src))
6622 SET_HARD_REG_BIT (reg_reloaded_died, src);
6624 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6626 int s = rl->secondary_out_reload;
6627 set = single_set (p);
6628 /* If this reload copies only to the secondary reload
6629 register, the secondary reload does the actual
6631 if (s >= 0 && set == NULL_RTX)
6632 /* We can't tell what function the secondary reload
6633 has and where the actual store to the pseudo is
6634 made; leave new_spill_reg_store alone. */
6637 && SET_SRC (set) == rl->reg_rtx
6638 && SET_DEST (set) == rld[s].reg_rtx)
6640 /* Usually the next instruction will be the
6641 secondary reload insn; if we can confirm
6642 that it is, setting new_spill_reg_store to
6643 that insn will allow an extra optimization. */
6644 rtx s_reg = rld[s].reg_rtx;
6645 rtx next = NEXT_INSN (p);
6646 rld[s].out = rl->out;
6647 rld[s].out_reg = rl->out_reg;
6648 set = single_set (next);
6649 if (set && SET_SRC (set) == s_reg
6650 && ! new_spill_reg_store[REGNO (s_reg)])
6652 SET_HARD_REG_BIT (reg_is_output_reload,
6654 new_spill_reg_store[REGNO (s_reg)] = next;
6658 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6663 if (rl->when_needed == RELOAD_OTHER)
6665 emit_insns (other_output_reload_insns[rl->opnum]);
6666 other_output_reload_insns[rl->opnum] = get_insns ();
6669 output_reload_insns[rl->opnum] = get_insns ();
6674 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6675 and has the number J. */
6677 do_input_reload (chain, rl, j)
6678 struct insn_chain *chain;
6682 int expect_occurrences = 1;
6683 rtx insn = chain->insn;
6684 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6685 ? rl->in_reg : rl->in);
6688 /* AUTO_INC reloads need to be handled even if inherited. We got an
6689 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6690 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6691 && ! rtx_equal_p (rl->reg_rtx, old)
6692 && rl->reg_rtx != 0)
6693 emit_input_reload_insns (chain, rld + j, old, j);
6695 /* When inheriting a wider reload, we have a MEM in rl->in,
6696 e.g. inheriting a SImode output reload for
6697 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6698 if (optimize && reload_inherited[j] && rl->in
6699 && GET_CODE (rl->in) == MEM
6700 && GET_CODE (rl->in_reg) == MEM
6701 && reload_spill_index[j] >= 0
6702 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6705 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6706 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6709 /* If we are reloading a register that was recently stored in with an
6710 output-reload, see if we can prove there was
6711 actually no need to store the old value in it. */
6714 && (reload_inherited[j] || reload_override_in[j])
6716 && GET_CODE (rl->reg_rtx) == REG
6717 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6719 /* There doesn't seem to be any reason to restrict this to pseudos
6720 and doing so loses in the case where we are copying from a
6721 register of the wrong class. */
6722 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6723 >= FIRST_PSEUDO_REGISTER)
6725 /* The insn might have already some references to stackslots
6726 replaced by MEMs, while reload_out_reg still names the
6728 && (dead_or_set_p (insn,
6729 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6730 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6732 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6735 /* Do output reloading for reload RL, which is for the insn described by
6736 CHAIN and has the number J.
6737 ??? At some point we need to support handling output reloads of
6738 JUMP_INSNs or insns that set cc0. */
6740 do_output_reload (chain, rl, j)
6741 struct insn_chain *chain;
6746 rtx insn = chain->insn;
6747 /* If this is an output reload that stores something that is
6748 not loaded in this same reload, see if we can eliminate a previous
6750 rtx pseudo = rl->out_reg;
6753 && GET_CODE (pseudo) == REG
6754 && ! rtx_equal_p (rl->in_reg, pseudo)
6755 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6756 && reg_last_reload_reg[REGNO (pseudo)])
6758 int pseudo_no = REGNO (pseudo);
6759 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6761 /* We don't need to test full validity of last_regno for
6762 inherit here; we only want to know if the store actually
6763 matches the pseudo. */
6764 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6765 && reg_reloaded_contents[last_regno] == pseudo_no
6766 && spill_reg_store[last_regno]
6767 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6768 delete_output_reload (insn, j, last_regno);
6773 || rl->reg_rtx == old
6774 || rl->reg_rtx == 0)
6777 /* An output operand that dies right away does need a reload,
6778 but need not be copied from it. Show the new location in the
6780 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6781 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6783 XEXP (note, 0) = rl->reg_rtx;
6786 /* Likewise for a SUBREG of an operand that dies. */
6787 else if (GET_CODE (old) == SUBREG
6788 && GET_CODE (SUBREG_REG (old)) == REG
6789 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6792 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6796 else if (GET_CODE (old) == SCRATCH)
6797 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6798 but we don't want to make an output reload. */
6801 /* If is a JUMP_INSN, we can't support output reloads yet. */
6802 if (GET_CODE (insn) == JUMP_INSN)
6805 emit_output_reload_insns (chain, rld + j, j);
6808 /* Output insns to reload values in and out of the chosen reload regs. */
6811 emit_reload_insns (chain)
6812 struct insn_chain *chain;
6814 rtx insn = chain->insn;
6817 rtx following_insn = NEXT_INSN (insn);
6818 rtx before_insn = PREV_INSN (insn);
6820 CLEAR_HARD_REG_SET (reg_reloaded_died);
6822 for (j = 0; j < reload_n_operands; j++)
6823 input_reload_insns[j] = input_address_reload_insns[j]
6824 = inpaddr_address_reload_insns[j]
6825 = output_reload_insns[j] = output_address_reload_insns[j]
6826 = outaddr_address_reload_insns[j]
6827 = other_output_reload_insns[j] = 0;
6828 other_input_address_reload_insns = 0;
6829 other_input_reload_insns = 0;
6830 operand_reload_insns = 0;
6831 other_operand_reload_insns = 0;
6833 /* Dump reloads into the dump file. */
6836 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6837 debug_reload_to_stream (rtl_dump_file);
6840 /* Now output the instructions to copy the data into and out of the
6841 reload registers. Do these in the order that the reloads were reported,
6842 since reloads of base and index registers precede reloads of operands
6843 and the operands may need the base and index registers reloaded. */
6845 for (j = 0; j < n_reloads; j++)
6848 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6849 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6851 do_input_reload (chain, rld + j, j);
6852 do_output_reload (chain, rld + j, j);
6855 /* Now write all the insns we made for reloads in the order expected by
6856 the allocation functions. Prior to the insn being reloaded, we write
6857 the following reloads:
6859 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6861 RELOAD_OTHER reloads.
6863 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6864 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6865 RELOAD_FOR_INPUT reload for the operand.
6867 RELOAD_FOR_OPADDR_ADDRS reloads.
6869 RELOAD_FOR_OPERAND_ADDRESS reloads.
6871 After the insn being reloaded, we write the following:
6873 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6874 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6875 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6876 reloads for the operand. The RELOAD_OTHER output reloads are
6877 output in descending order by reload number. */
6879 emit_insns_before (other_input_address_reload_insns, insn);
6880 emit_insns_before (other_input_reload_insns, insn);
6882 for (j = 0; j < reload_n_operands; j++)
6884 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6885 emit_insns_before (input_address_reload_insns[j], insn);
6886 emit_insns_before (input_reload_insns[j], insn);
6889 emit_insns_before (other_operand_reload_insns, insn);
6890 emit_insns_before (operand_reload_insns, insn);
6892 for (j = 0; j < reload_n_operands; j++)
6894 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6895 emit_insns_before (output_address_reload_insns[j], following_insn);
6896 emit_insns_before (output_reload_insns[j], following_insn);
6897 emit_insns_before (other_output_reload_insns[j], following_insn);
6900 /* Keep basic block info up to date. */
6903 if (BLOCK_HEAD (chain->block) == insn)
6904 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6905 if (BLOCK_END (chain->block) == insn)
6906 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6909 /* For all the spill regs newly reloaded in this instruction,
6910 record what they were reloaded from, so subsequent instructions
6911 can inherit the reloads.
6913 Update spill_reg_store for the reloads of this insn.
6914 Copy the elements that were updated in the loop above. */
6916 for (j = 0; j < n_reloads; j++)
6918 register int r = reload_order[j];
6919 register int i = reload_spill_index[r];
6921 /* If this is a non-inherited input reload from a pseudo, we must
6922 clear any memory of a previous store to the same pseudo. Only do
6923 something if there will not be an output reload for the pseudo
6925 if (rld[r].in_reg != 0
6926 && ! (reload_inherited[r] || reload_override_in[r]))
6928 rtx reg = rld[r].in_reg;
6930 if (GET_CODE (reg) == SUBREG)
6931 reg = SUBREG_REG (reg);
6933 if (GET_CODE (reg) == REG
6934 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6935 && ! reg_has_output_reload[REGNO (reg)])
6937 int nregno = REGNO (reg);
6939 if (reg_last_reload_reg[nregno])
6941 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6943 if (reg_reloaded_contents[last_regno] == nregno)
6944 spill_reg_store[last_regno] = 0;
6949 /* I is nonneg if this reload used a register.
6950 If rld[r].reg_rtx is 0, this is an optional reload
6951 that we opted to ignore. */
6953 if (i >= 0 && rld[r].reg_rtx != 0)
6955 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6957 int part_reaches_end = 0;
6958 int all_reaches_end = 1;
6960 /* For a multi register reload, we need to check if all or part
6961 of the value lives to the end. */
6962 for (k = 0; k < nr; k++)
6964 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6965 rld[r].when_needed))
6966 part_reaches_end = 1;
6968 all_reaches_end = 0;
6971 /* Ignore reloads that don't reach the end of the insn in
6973 if (all_reaches_end)
6975 /* First, clear out memory of what used to be in this spill reg.
6976 If consecutive registers are used, clear them all. */
6978 for (k = 0; k < nr; k++)
6979 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6981 /* Maybe the spill reg contains a copy of reload_out. */
6983 && (GET_CODE (rld[r].out) == REG
6987 || GET_CODE (rld[r].out_reg) == REG))
6989 rtx out = (GET_CODE (rld[r].out) == REG
6993 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6994 register int nregno = REGNO (out);
6995 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6996 : HARD_REGNO_NREGS (nregno,
6997 GET_MODE (rld[r].reg_rtx)));
6999 spill_reg_store[i] = new_spill_reg_store[i];
7000 spill_reg_stored_to[i] = out;
7001 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7003 /* If NREGNO is a hard register, it may occupy more than
7004 one register. If it does, say what is in the
7005 rest of the registers assuming that both registers
7006 agree on how many words the object takes. If not,
7007 invalidate the subsequent registers. */
7009 if (nregno < FIRST_PSEUDO_REGISTER)
7010 for (k = 1; k < nnr; k++)
7011 reg_last_reload_reg[nregno + k]
7013 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7014 REGNO (rld[r].reg_rtx) + k)
7017 /* Now do the inverse operation. */
7018 for (k = 0; k < nr; k++)
7020 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7021 reg_reloaded_contents[i + k]
7022 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7025 reg_reloaded_insn[i + k] = insn;
7026 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7030 /* Maybe the spill reg contains a copy of reload_in. Only do
7031 something if there will not be an output reload for
7032 the register being reloaded. */
7033 else if (rld[r].out_reg == 0
7035 && ((GET_CODE (rld[r].in) == REG
7036 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7037 && ! reg_has_output_reload[REGNO (rld[r].in)])
7038 || (GET_CODE (rld[r].in_reg) == REG
7039 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7040 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7042 register int nregno;
7045 if (GET_CODE (rld[r].in) == REG
7046 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7047 nregno = REGNO (rld[r].in);
7048 else if (GET_CODE (rld[r].in_reg) == REG)
7049 nregno = REGNO (rld[r].in_reg);
7051 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7053 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7054 : HARD_REGNO_NREGS (nregno,
7055 GET_MODE (rld[r].reg_rtx)));
7057 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7059 if (nregno < FIRST_PSEUDO_REGISTER)
7060 for (k = 1; k < nnr; k++)
7061 reg_last_reload_reg[nregno + k]
7063 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7064 REGNO (rld[r].reg_rtx) + k)
7067 /* Unless we inherited this reload, show we haven't
7068 recently done a store.
7069 Previous stores of inherited auto_inc expressions
7070 also have to be discarded. */
7071 if (! reload_inherited[r]
7072 || (rld[r].out && ! rld[r].out_reg))
7073 spill_reg_store[i] = 0;
7075 for (k = 0; k < nr; k++)
7077 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7078 reg_reloaded_contents[i + k]
7079 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7082 reg_reloaded_insn[i + k] = insn;
7083 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7088 /* However, if part of the reload reaches the end, then we must
7089 invalidate the old info for the part that survives to the end. */
7090 else if (part_reaches_end)
7092 for (k = 0; k < nr; k++)
7093 if (reload_reg_reaches_end_p (i + k,
7095 rld[r].when_needed))
7096 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7100 /* The following if-statement was #if 0'd in 1.34 (or before...).
7101 It's reenabled in 1.35 because supposedly nothing else
7102 deals with this problem. */
7104 /* If a register gets output-reloaded from a non-spill register,
7105 that invalidates any previous reloaded copy of it.
7106 But forget_old_reloads_1 won't get to see it, because
7107 it thinks only about the original insn. So invalidate it here. */
7108 if (i < 0 && rld[r].out != 0
7109 && (GET_CODE (rld[r].out) == REG
7110 || (GET_CODE (rld[r].out) == MEM
7111 && GET_CODE (rld[r].out_reg) == REG)))
7113 rtx out = (GET_CODE (rld[r].out) == REG
7114 ? rld[r].out : rld[r].out_reg);
7115 register int nregno = REGNO (out);
7116 if (nregno >= FIRST_PSEUDO_REGISTER)
7118 rtx src_reg, store_insn = NULL_RTX;
7120 reg_last_reload_reg[nregno] = 0;
7122 /* If we can find a hard register that is stored, record
7123 the storing insn so that we may delete this insn with
7124 delete_output_reload. */
7125 src_reg = rld[r].reg_rtx;
7127 /* If this is an optional reload, try to find the source reg
7128 from an input reload. */
7131 rtx set = single_set (insn);
7132 if (set && SET_DEST (set) == rld[r].out)
7136 src_reg = SET_SRC (set);
7138 for (k = 0; k < n_reloads; k++)
7140 if (rld[k].in == src_reg)
7142 src_reg = rld[k].reg_rtx;
7149 store_insn = new_spill_reg_store[REGNO (src_reg)];
7150 if (src_reg && GET_CODE (src_reg) == REG
7151 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7153 int src_regno = REGNO (src_reg);
7154 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7155 /* The place where to find a death note varies with
7156 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7157 necessarily checked exactly in the code that moves
7158 notes, so just check both locations. */
7159 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7161 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7164 spill_reg_store[src_regno + nr] = store_insn;
7165 spill_reg_stored_to[src_regno + nr] = out;
7166 reg_reloaded_contents[src_regno + nr] = nregno;
7167 reg_reloaded_insn[src_regno + nr] = store_insn;
7168 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7169 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7170 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7172 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7174 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7176 reg_last_reload_reg[nregno] = src_reg;
7181 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7183 while (num_regs-- > 0)
7184 reg_last_reload_reg[nregno + num_regs] = 0;
7188 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7191 /* Emit code to perform a reload from IN (which may be a reload register) to
7192 OUT (which may also be a reload register). IN or OUT is from operand
7193 OPNUM with reload type TYPE.
7195 Returns first insn emitted. */
7198 gen_reload (out, in, opnum, type)
7202 enum reload_type type;
7204 rtx last = get_last_insn ();
7207 /* If IN is a paradoxical SUBREG, remove it and try to put the
7208 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7209 if (GET_CODE (in) == SUBREG
7210 && (GET_MODE_SIZE (GET_MODE (in))
7211 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7212 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7213 in = SUBREG_REG (in), out = tem;
7214 else if (GET_CODE (out) == SUBREG
7215 && (GET_MODE_SIZE (GET_MODE (out))
7216 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7217 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7218 out = SUBREG_REG (out), in = tem;
7220 /* How to do this reload can get quite tricky. Normally, we are being
7221 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7222 register that didn't get a hard register. In that case we can just
7223 call emit_move_insn.
7225 We can also be asked to reload a PLUS that adds a register or a MEM to
7226 another register, constant or MEM. This can occur during frame pointer
7227 elimination and while reloading addresses. This case is handled by
7228 trying to emit a single insn to perform the add. If it is not valid,
7229 we use a two insn sequence.
7231 Finally, we could be called to handle an 'o' constraint by putting
7232 an address into a register. In that case, we first try to do this
7233 with a named pattern of "reload_load_address". If no such pattern
7234 exists, we just emit a SET insn and hope for the best (it will normally
7235 be valid on machines that use 'o').
7237 This entire process is made complex because reload will never
7238 process the insns we generate here and so we must ensure that
7239 they will fit their constraints and also by the fact that parts of
7240 IN might be being reloaded separately and replaced with spill registers.
7241 Because of this, we are, in some sense, just guessing the right approach
7242 here. The one listed above seems to work.
7244 ??? At some point, this whole thing needs to be rethought. */
7246 if (GET_CODE (in) == PLUS
7247 && (GET_CODE (XEXP (in, 0)) == REG
7248 || GET_CODE (XEXP (in, 0)) == SUBREG
7249 || GET_CODE (XEXP (in, 0)) == MEM)
7250 && (GET_CODE (XEXP (in, 1)) == REG
7251 || GET_CODE (XEXP (in, 1)) == SUBREG
7252 || CONSTANT_P (XEXP (in, 1))
7253 || GET_CODE (XEXP (in, 1)) == MEM))
7255 /* We need to compute the sum of a register or a MEM and another
7256 register, constant, or MEM, and put it into the reload
7257 register. The best possible way of doing this is if the machine
7258 has a three-operand ADD insn that accepts the required operands.
7260 The simplest approach is to try to generate such an insn and see if it
7261 is recognized and matches its constraints. If so, it can be used.
7263 It might be better not to actually emit the insn unless it is valid,
7264 but we need to pass the insn as an operand to `recog' and
7265 `extract_insn' and it is simpler to emit and then delete the insn if
7266 not valid than to dummy things up. */
7268 rtx op0, op1, tem, insn;
7271 op0 = find_replacement (&XEXP (in, 0));
7272 op1 = find_replacement (&XEXP (in, 1));
7274 /* Since constraint checking is strict, commutativity won't be
7275 checked, so we need to do that here to avoid spurious failure
7276 if the add instruction is two-address and the second operand
7277 of the add is the same as the reload reg, which is frequently
7278 the case. If the insn would be A = B + A, rearrange it so
7279 it will be A = A + B as constrain_operands expects. */
7281 if (GET_CODE (XEXP (in, 1)) == REG
7282 && REGNO (out) == REGNO (XEXP (in, 1)))
7283 tem = op0, op0 = op1, op1 = tem;
7285 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7286 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7288 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7289 code = recog_memoized (insn);
7293 extract_insn (insn);
7294 /* We want constrain operands to treat this insn strictly in
7295 its validity determination, i.e., the way it would after reload
7297 if (constrain_operands (1))
7301 delete_insns_since (last);
7303 /* If that failed, we must use a conservative two-insn sequence.
7305 Use a move to copy one operand into the reload register. Prefer
7306 to reload a constant, MEM or pseudo since the move patterns can
7307 handle an arbitrary operand. If OP1 is not a constant, MEM or
7308 pseudo and OP1 is not a valid operand for an add instruction, then
7311 After reloading one of the operands into the reload register, add
7312 the reload register to the output register.
7314 If there is another way to do this for a specific machine, a
7315 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7318 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7320 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7321 || (GET_CODE (op1) == REG
7322 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7323 || (code != CODE_FOR_nothing
7324 && ! ((*insn_data[code].operand[2].predicate)
7325 (op1, insn_data[code].operand[2].mode))))
7326 tem = op0, op0 = op1, op1 = tem;
7328 gen_reload (out, op0, opnum, type);
7330 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7331 This fixes a problem on the 32K where the stack pointer cannot
7332 be used as an operand of an add insn. */
7334 if (rtx_equal_p (op0, op1))
7337 insn = emit_insn (gen_add2_insn (out, op1));
7339 /* If that failed, copy the address register to the reload register.
7340 Then add the constant to the reload register. */
7342 code = recog_memoized (insn);
7346 extract_insn (insn);
7347 /* We want constrain operands to treat this insn strictly in
7348 its validity determination, i.e., the way it would after reload
7350 if (constrain_operands (1))
7352 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7354 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7359 delete_insns_since (last);
7361 gen_reload (out, op1, opnum, type);
7362 insn = emit_insn (gen_add2_insn (out, op0));
7363 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7366 #ifdef SECONDARY_MEMORY_NEEDED
7367 /* If we need a memory location to do the move, do it that way. */
7368 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7369 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7370 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7371 REGNO_REG_CLASS (REGNO (out)),
7374 /* Get the memory to use and rewrite both registers to its mode. */
7375 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7377 if (GET_MODE (loc) != GET_MODE (out))
7378 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7380 if (GET_MODE (loc) != GET_MODE (in))
7381 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7383 gen_reload (loc, in, opnum, type);
7384 gen_reload (out, loc, opnum, type);
7388 /* If IN is a simple operand, use gen_move_insn. */
7389 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7390 emit_insn (gen_move_insn (out, in));
7392 #ifdef HAVE_reload_load_address
7393 else if (HAVE_reload_load_address)
7394 emit_insn (gen_reload_load_address (out, in));
7397 /* Otherwise, just write (set OUT IN) and hope for the best. */
7399 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7401 /* Return the first insn emitted.
7402 We can not just return get_last_insn, because there may have
7403 been multiple instructions emitted. Also note that gen_move_insn may
7404 emit more than one insn itself, so we can not assume that there is one
7405 insn emitted per emit_insn_before call. */
7407 return last ? NEXT_INSN (last) : get_insns ();
7410 /* Delete a previously made output-reload
7411 whose result we now believe is not needed.
7412 First we double-check.
7414 INSN is the insn now being processed.
7415 LAST_RELOAD_REG is the hard register number for which we want to delete
7416 the last output reload.
7417 J is the reload-number that originally used REG. The caller has made
7418 certain that reload J doesn't use REG any longer for input. */
7421 delete_output_reload (insn, j, last_reload_reg)
7424 int last_reload_reg;
7426 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7427 rtx reg = spill_reg_stored_to[last_reload_reg];
7430 int n_inherited = 0;
7434 /* Get the raw pseudo-register referred to. */
7436 while (GET_CODE (reg) == SUBREG)
7437 reg = SUBREG_REG (reg);
7438 substed = reg_equiv_memory_loc[REGNO (reg)];
7440 /* This is unsafe if the operand occurs more often in the current
7441 insn than it is inherited. */
7442 for (k = n_reloads - 1; k >= 0; k--)
7444 rtx reg2 = rld[k].in;
7447 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7448 reg2 = rld[k].in_reg;
7450 if (rld[k].out && ! rld[k].out_reg)
7451 reg2 = XEXP (rld[k].in_reg, 0);
7453 while (GET_CODE (reg2) == SUBREG)
7454 reg2 = SUBREG_REG (reg2);
7455 if (rtx_equal_p (reg2, reg))
7457 if (reload_inherited[k] || reload_override_in[k] || k == j)
7460 reg2 = rld[k].out_reg;
7463 while (GET_CODE (reg2) == SUBREG)
7464 reg2 = XEXP (reg2, 0);
7465 if (rtx_equal_p (reg2, reg))
7472 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7474 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7475 if (n_occurrences > n_inherited)
7478 /* If the pseudo-reg we are reloading is no longer referenced
7479 anywhere between the store into it and here,
7480 and no jumps or labels intervene, then the value can get
7481 here through the reload reg alone.
7482 Otherwise, give up--return. */
7483 for (i1 = NEXT_INSN (output_reload_insn);
7484 i1 != insn; i1 = NEXT_INSN (i1))
7486 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7488 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7489 && reg_mentioned_p (reg, PATTERN (i1)))
7491 /* If this is USE in front of INSN, we only have to check that
7492 there are no more references than accounted for by inheritance. */
7493 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7495 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7496 i1 = NEXT_INSN (i1);
7498 if (n_occurrences <= n_inherited && i1 == insn)
7504 /* The caller has already checked that REG dies or is set in INSN.
7505 It has also checked that we are optimizing, and thus some inaccurancies
7506 in the debugging information are acceptable.
7507 So we could just delete output_reload_insn.
7508 But in some cases we can improve the debugging information without
7509 sacrificing optimization - maybe even improving the code:
7510 See if the pseudo reg has been completely replaced
7511 with reload regs. If so, delete the store insn
7512 and forget we had a stack slot for the pseudo. */
7513 if (rld[j].out != rld[j].in
7514 && REG_N_DEATHS (REGNO (reg)) == 1
7515 && REG_N_SETS (REGNO (reg)) == 1
7516 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7517 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7521 /* We know that it was used only between here
7522 and the beginning of the current basic block.
7523 (We also know that the last use before INSN was
7524 the output reload we are thinking of deleting, but never mind that.)
7525 Search that range; see if any ref remains. */
7526 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7528 rtx set = single_set (i2);
7530 /* Uses which just store in the pseudo don't count,
7531 since if they are the only uses, they are dead. */
7532 if (set != 0 && SET_DEST (set) == reg)
7534 if (GET_CODE (i2) == CODE_LABEL
7535 || GET_CODE (i2) == JUMP_INSN)
7537 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7538 && reg_mentioned_p (reg, PATTERN (i2)))
7540 /* Some other ref remains; just delete the output reload we
7542 delete_address_reloads (output_reload_insn, insn);
7543 PUT_CODE (output_reload_insn, NOTE);
7544 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7545 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7550 /* Delete the now-dead stores into this pseudo. */
7551 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7553 rtx set = single_set (i2);
7555 if (set != 0 && SET_DEST (set) == reg)
7557 delete_address_reloads (i2, insn);
7558 /* This might be a basic block head,
7559 thus don't use delete_insn. */
7560 PUT_CODE (i2, NOTE);
7561 NOTE_SOURCE_FILE (i2) = 0;
7562 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7564 if (GET_CODE (i2) == CODE_LABEL
7565 || GET_CODE (i2) == JUMP_INSN)
7569 /* For the debugging info,
7570 say the pseudo lives in this reload reg. */
7571 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7572 alter_reg (REGNO (reg), -1);
7574 delete_address_reloads (output_reload_insn, insn);
7575 PUT_CODE (output_reload_insn, NOTE);
7576 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7577 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7581 /* We are going to delete DEAD_INSN. Recursively delete loads of
7582 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7583 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7585 delete_address_reloads (dead_insn, current_insn)
7586 rtx dead_insn, current_insn;
7588 rtx set = single_set (dead_insn);
7589 rtx set2, dst, prev, next;
7592 rtx dst = SET_DEST (set);
7593 if (GET_CODE (dst) == MEM)
7594 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7596 /* If we deleted the store from a reloaded post_{in,de}c expression,
7597 we can delete the matching adds. */
7598 prev = PREV_INSN (dead_insn);
7599 next = NEXT_INSN (dead_insn);
7600 if (! prev || ! next)
7602 set = single_set (next);
7603 set2 = single_set (prev);
7605 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7606 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7607 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7609 dst = SET_DEST (set);
7610 if (! rtx_equal_p (dst, SET_DEST (set2))
7611 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7612 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7613 || (INTVAL (XEXP (SET_SRC (set), 1))
7614 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7620 /* Subfunction of delete_address_reloads: process registers found in X. */
7622 delete_address_reloads_1 (dead_insn, x, current_insn)
7623 rtx dead_insn, x, current_insn;
7625 rtx prev, set, dst, i2;
7627 enum rtx_code code = GET_CODE (x);
7631 const char *fmt = GET_RTX_FORMAT (code);
7632 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7635 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7636 else if (fmt[i] == 'E')
7638 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7639 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7646 if (spill_reg_order[REGNO (x)] < 0)
7649 /* Scan backwards for the insn that sets x. This might be a way back due
7651 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7653 code = GET_CODE (prev);
7654 if (code == CODE_LABEL || code == JUMP_INSN)
7656 if (GET_RTX_CLASS (code) != 'i')
7658 if (reg_set_p (x, PATTERN (prev)))
7660 if (reg_referenced_p (x, PATTERN (prev)))
7663 if (! prev || INSN_UID (prev) < reload_first_uid)
7665 /* Check that PREV only sets the reload register. */
7666 set = single_set (prev);
7669 dst = SET_DEST (set);
7670 if (GET_CODE (dst) != REG
7671 || ! rtx_equal_p (dst, x))
7673 if (! reg_set_p (dst, PATTERN (dead_insn)))
7675 /* Check if DST was used in a later insn -
7676 it might have been inherited. */
7677 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7679 if (GET_CODE (i2) == CODE_LABEL)
7683 if (reg_referenced_p (dst, PATTERN (i2)))
7685 /* If there is a reference to the register in the current insn,
7686 it might be loaded in a non-inherited reload. If no other
7687 reload uses it, that means the register is set before
7689 if (i2 == current_insn)
7691 for (j = n_reloads - 1; j >= 0; j--)
7692 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7693 || reload_override_in[j] == dst)
7695 for (j = n_reloads - 1; j >= 0; j--)
7696 if (rld[j].in && rld[j].reg_rtx == dst)
7703 if (GET_CODE (i2) == JUMP_INSN)
7705 /* If DST is still live at CURRENT_INSN, check if it is used for
7706 any reload. Note that even if CURRENT_INSN sets DST, we still
7707 have to check the reloads. */
7708 if (i2 == current_insn)
7710 for (j = n_reloads - 1; j >= 0; j--)
7711 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7712 || reload_override_in[j] == dst)
7714 /* ??? We can't finish the loop here, because dst might be
7715 allocated to a pseudo in this block if no reload in this
7716 block needs any of the clsses containing DST - see
7717 spill_hard_reg. There is no easy way to tell this, so we
7718 have to scan till the end of the basic block. */
7720 if (reg_set_p (dst, PATTERN (i2)))
7724 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7725 reg_reloaded_contents[REGNO (dst)] = -1;
7726 /* Can't use delete_insn here because PREV might be a basic block head. */
7727 PUT_CODE (prev, NOTE);
7728 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7729 NOTE_SOURCE_FILE (prev) = 0;
7732 /* Output reload-insns to reload VALUE into RELOADREG.
7733 VALUE is an autoincrement or autodecrement RTX whose operand
7734 is a register or memory location;
7735 so reloading involves incrementing that location.
7736 IN is either identical to VALUE, or some cheaper place to reload from.
7738 INC_AMOUNT is the number to increment or decrement by (always positive).
7739 This cannot be deduced from VALUE.
7741 Return the instruction that stores into RELOADREG. */
7744 inc_for_reload (reloadreg, in, value, inc_amount)
7749 /* REG or MEM to be copied and incremented. */
7750 rtx incloc = XEXP (value, 0);
7751 /* Nonzero if increment after copying. */
7752 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7758 rtx real_in = in == value ? XEXP (in, 0) : in;
7760 /* No hard register is equivalent to this register after
7761 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7762 we could inc/dec that register as well (maybe even using it for
7763 the source), but I'm not sure it's worth worrying about. */
7764 if (GET_CODE (incloc) == REG)
7765 reg_last_reload_reg[REGNO (incloc)] = 0;
7767 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7768 inc_amount = -inc_amount;
7770 inc = GEN_INT (inc_amount);
7772 /* If this is post-increment, first copy the location to the reload reg. */
7773 if (post && real_in != reloadreg)
7774 emit_insn (gen_move_insn (reloadreg, real_in));
7778 /* See if we can directly increment INCLOC. Use a method similar to
7779 that in gen_reload. */
7781 last = get_last_insn ();
7782 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7783 gen_rtx_PLUS (GET_MODE (incloc),
7786 code = recog_memoized (add_insn);
7789 extract_insn (add_insn);
7790 if (constrain_operands (1))
7792 /* If this is a pre-increment and we have incremented the value
7793 where it lives, copy the incremented value to RELOADREG to
7794 be used as an address. */
7797 emit_insn (gen_move_insn (reloadreg, incloc));
7802 delete_insns_since (last);
7805 /* If couldn't do the increment directly, must increment in RELOADREG.
7806 The way we do this depends on whether this is pre- or post-increment.
7807 For pre-increment, copy INCLOC to the reload register, increment it
7808 there, then save back. */
7812 if (in != reloadreg)
7813 emit_insn (gen_move_insn (reloadreg, real_in));
7814 emit_insn (gen_add2_insn (reloadreg, inc));
7815 store = emit_insn (gen_move_insn (incloc, reloadreg));
7820 Because this might be a jump insn or a compare, and because RELOADREG
7821 may not be available after the insn in an input reload, we must do
7822 the incrementation before the insn being reloaded for.
7824 We have already copied IN to RELOADREG. Increment the copy in
7825 RELOADREG, save that back, then decrement RELOADREG so it has
7826 the original value. */
7828 emit_insn (gen_add2_insn (reloadreg, inc));
7829 store = emit_insn (gen_move_insn (incloc, reloadreg));
7830 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7836 /* Return 1 if we are certain that the constraint-string STRING allows
7837 the hard register REG. Return 0 if we can't be sure of this. */
7840 constraint_accepts_reg_p (string, reg)
7845 int regno = true_regnum (reg);
7848 /* Initialize for first alternative. */
7850 /* Check that each alternative contains `g' or `r'. */
7852 switch (c = *string++)
7855 /* If an alternative lacks `g' or `r', we lose. */
7858 /* If an alternative lacks `g' or `r', we lose. */
7861 /* Initialize for next alternative. */
7866 /* Any general reg wins for this alternative. */
7867 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7871 /* Any reg in specified class wins for this alternative. */
7873 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7875 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7881 /* INSN is a no-op; delete it.
7882 If this sets the return value of the function, we must keep a USE around,
7883 in case this is in a different basic block than the final USE. Otherwise,
7884 we could loose important register lifeness information on
7885 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7886 spills: subsequent passes assume that spill registers are dead at the end
7888 VALUE must be the return value in such a case, NULL otherwise. */
7890 reload_cse_delete_noop_set (insn, value)
7895 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7896 INSN_CODE (insn) = -1;
7897 REG_NOTES (insn) = NULL_RTX;
7901 PUT_CODE (insn, NOTE);
7902 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7903 NOTE_SOURCE_FILE (insn) = 0;
7907 /* See whether a single set SET is a noop. */
7909 reload_cse_noop_set_p (set)
7912 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7915 /* Try to simplify INSN. */
7917 reload_cse_simplify (insn)
7920 rtx body = PATTERN (insn);
7922 if (GET_CODE (body) == SET)
7925 if (reload_cse_noop_set_p (body))
7927 rtx value = SET_DEST (body);
7928 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
7930 reload_cse_delete_noop_set (insn, value);
7934 /* It's not a no-op, but we can try to simplify it. */
7935 count += reload_cse_simplify_set (body, insn);
7938 apply_change_group ();
7940 reload_cse_simplify_operands (insn);
7942 else if (GET_CODE (body) == PARALLEL)
7946 rtx value = NULL_RTX;
7948 /* If every action in a PARALLEL is a noop, we can delete
7949 the entire PARALLEL. */
7950 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7952 rtx part = XVECEXP (body, 0, i);
7953 if (GET_CODE (part) == SET)
7955 if (! reload_cse_noop_set_p (part))
7957 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
7961 value = SET_DEST (part);
7964 else if (GET_CODE (part) != CLOBBER)
7970 reload_cse_delete_noop_set (insn, value);
7971 /* We're done with this insn. */
7975 /* It's not a no-op, but we can try to simplify it. */
7976 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7977 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
7978 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
7981 apply_change_group ();
7983 reload_cse_simplify_operands (insn);
7987 /* Do a very simple CSE pass over the hard registers.
7989 This function detects no-op moves where we happened to assign two
7990 different pseudo-registers to the same hard register, and then
7991 copied one to the other. Reload will generate a useless
7992 instruction copying a register to itself.
7994 This function also detects cases where we load a value from memory
7995 into two different registers, and (if memory is more expensive than
7996 registers) changes it to simply copy the first register into the
7999 Another optimization is performed that scans the operands of each
8000 instruction to see whether the value is already available in a
8001 hard register. It then replaces the operand with the hard register
8002 if possible, much like an optional reload would. */
8005 reload_cse_regs_1 (first)
8011 init_alias_analysis ();
8013 for (insn = first; insn; insn = NEXT_INSN (insn))
8016 reload_cse_simplify (insn);
8018 cselib_process_insn (insn);
8022 end_alias_analysis ();
8026 /* Call cse / combine like post-reload optimization phases.
8027 FIRST is the first instruction. */
8029 reload_cse_regs (first)
8032 reload_cse_regs_1 (first);
8034 reload_cse_move2add (first);
8035 if (flag_expensive_optimizations)
8036 reload_cse_regs_1 (first);
8039 /* Try to simplify a single SET instruction. SET is the set pattern.
8040 INSN is the instruction it came from.
8041 This function only handles one case: if we set a register to a value
8042 which is not a register, we try to find that value in some other register
8043 and change the set into a register copy. */
8046 reload_cse_simplify_set (set, insn)
8053 enum reg_class dclass;
8056 struct elt_loc_list *l;
8058 dreg = true_regnum (SET_DEST (set));
8062 src = SET_SRC (set);
8063 if (side_effects_p (src) || true_regnum (src) >= 0)
8066 dclass = REGNO_REG_CLASS (dreg);
8068 /* If memory loads are cheaper than register copies, don't change them. */
8069 if (GET_CODE (src) == MEM)
8070 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8071 else if (CONSTANT_P (src))
8072 old_cost = rtx_cost (src, SET);
8073 else if (GET_CODE (src) == REG)
8074 old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass);
8077 old_cost = rtx_cost (src, SET);
8079 val = cselib_lookup (src, VOIDmode, 0);
8082 for (l = val->locs; l; l = l->next)
8085 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8086 this_cost = rtx_cost (l->loc, SET);
8087 else if (GET_CODE (l->loc) == REG)
8088 this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)),
8092 /* If equal costs, prefer registers over anything else. That tends to
8093 lead to smaller instructions on some machines. */
8094 if ((this_cost < old_cost
8095 || (this_cost == old_cost
8096 && GET_CODE (l->loc) == REG
8097 && GET_CODE (SET_SRC (set)) != REG))
8098 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8099 old_cost = this_cost, did_change = 1;
8105 /* Try to replace operands in INSN with equivalent values that are already
8106 in registers. This can be viewed as optional reloading.
8108 For each non-register operand in the insn, see if any hard regs are
8109 known to be equivalent to that operand. Record the alternatives which
8110 can accept these hard registers. Among all alternatives, select the
8111 ones which are better or equal to the one currently matching, where
8112 "better" is in terms of '?' and '!' constraints. Among the remaining
8113 alternatives, select the one which replaces most operands with
8117 reload_cse_simplify_operands (insn)
8122 /* For each operand, all registers that are equivalent to it. */
8123 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8125 const char *constraints[MAX_RECOG_OPERANDS];
8127 /* Vector recording how bad an alternative is. */
8128 int *alternative_reject;
8129 /* Vector recording how many registers can be introduced by choosing
8130 this alternative. */
8131 int *alternative_nregs;
8132 /* Array of vectors recording, for each operand and each alternative,
8133 which hard register to substitute, or -1 if the operand should be
8135 int *op_alt_regno[MAX_RECOG_OPERANDS];
8136 /* Array of alternatives, sorted in order of decreasing desirability. */
8137 int *alternative_order;
8138 rtx reg = gen_rtx_REG (VOIDmode, -1);
8140 extract_insn (insn);
8142 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8145 /* Figure out which alternative currently matches. */
8146 if (! constrain_operands (1))
8147 fatal_insn_not_found (insn);
8149 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8150 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8151 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8152 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8153 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8155 /* For each operand, find out which regs are equivalent. */
8156 for (i = 0; i < recog_data.n_operands; i++)
8159 struct elt_loc_list *l;
8161 CLEAR_HARD_REG_SET (equiv_regs[i]);
8163 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8164 right, so avoid the problem here. */
8165 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL)
8168 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8172 for (l = v->locs; l; l = l->next)
8173 if (GET_CODE (l->loc) == REG)
8174 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8177 for (i = 0; i < recog_data.n_operands; i++)
8179 enum machine_mode mode;
8183 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8184 for (j = 0; j < recog_data.n_alternatives; j++)
8185 op_alt_regno[i][j] = -1;
8187 p = constraints[i] = recog_data.constraints[i];
8188 mode = recog_data.operand_mode[i];
8190 /* Add the reject values for each alternative given by the constraints
8191 for this operand. */
8199 alternative_reject[j] += 3;
8201 alternative_reject[j] += 300;
8204 /* We won't change operands which are already registers. We
8205 also don't want to modify output operands. */
8206 regno = true_regnum (recog_data.operand[i]);
8208 || constraints[i][0] == '='
8209 || constraints[i][0] == '+')
8212 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8214 int class = (int) NO_REGS;
8216 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8219 REGNO (reg) = regno;
8220 PUT_MODE (reg, mode);
8222 /* We found a register equal to this operand. Now look for all
8223 alternatives that can accept this register and have not been
8224 assigned a register they can use yet. */
8233 case '=': case '+': case '?':
8234 case '#': case '&': case '!':
8236 case '0': case '1': case '2': case '3': case '4':
8237 case '5': case '6': case '7': case '8': case '9':
8238 case 'm': case '<': case '>': case 'V': case 'o':
8239 case 'E': case 'F': case 'G': case 'H':
8240 case 's': case 'i': case 'n':
8241 case 'I': case 'J': case 'K': case 'L':
8242 case 'M': case 'N': case 'O': case 'P':
8244 /* These don't say anything we care about. */
8248 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8253 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8256 case ',': case '\0':
8257 /* See if REGNO fits this alternative, and set it up as the
8258 replacement register if we don't have one for this
8259 alternative yet and the operand being replaced is not
8260 a cheap CONST_INT. */
8261 if (op_alt_regno[i][j] == -1
8262 && reg_fits_class_p (reg, class, 0, mode)
8263 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8264 || (rtx_cost (recog_data.operand[i], SET)
8265 > rtx_cost (reg, SET))))
8267 alternative_nregs[j]++;
8268 op_alt_regno[i][j] = regno;
8280 /* Record all alternatives which are better or equal to the currently
8281 matching one in the alternative_order array. */
8282 for (i = j = 0; i < recog_data.n_alternatives; i++)
8283 if (alternative_reject[i] <= alternative_reject[which_alternative])
8284 alternative_order[j++] = i;
8285 recog_data.n_alternatives = j;
8287 /* Sort it. Given a small number of alternatives, a dumb algorithm
8288 won't hurt too much. */
8289 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8292 int best_reject = alternative_reject[alternative_order[i]];
8293 int best_nregs = alternative_nregs[alternative_order[i]];
8296 for (j = i + 1; j < recog_data.n_alternatives; j++)
8298 int this_reject = alternative_reject[alternative_order[j]];
8299 int this_nregs = alternative_nregs[alternative_order[j]];
8301 if (this_reject < best_reject
8302 || (this_reject == best_reject && this_nregs < best_nregs))
8305 best_reject = this_reject;
8306 best_nregs = this_nregs;
8310 tmp = alternative_order[best];
8311 alternative_order[best] = alternative_order[i];
8312 alternative_order[i] = tmp;
8315 /* Substitute the operands as determined by op_alt_regno for the best
8317 j = alternative_order[0];
8319 for (i = 0; i < recog_data.n_operands; i++)
8321 enum machine_mode mode = recog_data.operand_mode[i];
8322 if (op_alt_regno[i][j] == -1)
8325 validate_change (insn, recog_data.operand_loc[i],
8326 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8329 for (i = recog_data.n_dups - 1; i >= 0; i--)
8331 int op = recog_data.dup_num[i];
8332 enum machine_mode mode = recog_data.operand_mode[op];
8334 if (op_alt_regno[op][j] == -1)
8337 validate_change (insn, recog_data.dup_loc[i],
8338 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8341 return apply_change_group ();
8344 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8346 This code might also be useful when reload gave up on reg+reg addresssing
8347 because of clashes between the return register and INDEX_REG_CLASS. */
8349 /* The maximum number of uses of a register we can keep track of to
8350 replace them with reg+reg addressing. */
8351 #define RELOAD_COMBINE_MAX_USES 6
8353 /* INSN is the insn where a register has ben used, and USEP points to the
8354 location of the register within the rtl. */
8355 struct reg_use { rtx insn, *usep; };
8357 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8358 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8359 indicates where it becomes live again.
8360 Otherwise, USE_INDEX is the index of the last encountered use of the
8361 register (which is first among these we have seen since we scan backwards),
8362 OFFSET contains the constant offset that is added to the register in
8363 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8364 last, of these uses.
8365 STORE_RUID is always meaningful if we only want to use a value in a
8366 register in a different place: it denotes the next insn in the insn
8367 stream (i.e. the last ecountered) that sets or clobbers the register. */
8370 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8375 } reg_state[FIRST_PSEUDO_REGISTER];
8377 /* Reverse linear uid. This is increased in reload_combine while scanning
8378 the instructions from last to first. It is used to set last_label_ruid
8379 and the store_ruid / use_ruid fields in reg_state. */
8380 static int reload_combine_ruid;
8382 #define LABEL_LIVE(LABEL) \
8383 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8389 int first_index_reg = -1, last_index_reg;
8392 int last_label_ruid;
8393 int min_labelno, n_labels;
8394 HARD_REG_SET ever_live_at_start, *label_live;
8396 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8397 reload has already used it where appropriate, so there is no use in
8398 trying to generate it now. */
8399 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8402 /* To avoid wasting too much time later searching for an index register,
8403 determine the minimum and maximum index register numbers. */
8404 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8405 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8407 if (first_index_reg == -1)
8408 first_index_reg = r;
8413 /* If no index register is available, we can quit now. */
8414 if (first_index_reg == -1)
8417 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8418 information is a bit fuzzy immediately after reload, but it's
8419 still good enough to determine which registers are live at a jump
8421 min_labelno = get_first_label_num ();
8422 n_labels = max_label_num () - min_labelno;
8423 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8424 CLEAR_HARD_REG_SET (ever_live_at_start);
8426 for (i = n_basic_blocks - 1; i >= 0; i--)
8428 insn = BLOCK_HEAD (i);
8429 if (GET_CODE (insn) == CODE_LABEL)
8433 REG_SET_TO_HARD_REG_SET (live,
8434 BASIC_BLOCK (i)->global_live_at_start);
8435 compute_use_by_pseudos (&live,
8436 BASIC_BLOCK (i)->global_live_at_start);
8437 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8438 IOR_HARD_REG_SET (ever_live_at_start, live);
8442 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8443 last_label_ruid = reload_combine_ruid = 0;
8444 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8446 reg_state[r].store_ruid = reload_combine_ruid;
8448 reg_state[r].use_index = -1;
8450 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8453 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8457 /* We cannot do our optimization across labels. Invalidating all the use
8458 information we have would be costly, so we just note where the label
8459 is and then later disable any optimization that would cross it. */
8460 if (GET_CODE (insn) == CODE_LABEL)
8461 last_label_ruid = reload_combine_ruid;
8462 else if (GET_CODE (insn) == BARRIER)
8463 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8464 if (! fixed_regs[r])
8465 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8467 if (! INSN_P (insn))
8470 reload_combine_ruid++;
8472 /* Look for (set (REGX) (CONST_INT))
8473 (set (REGX) (PLUS (REGX) (REGY)))
8475 ... (MEM (REGX)) ...
8477 (set (REGZ) (CONST_INT))
8479 ... (MEM (PLUS (REGZ) (REGY)))... .
8481 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8482 and that we know all uses of REGX before it dies. */
8483 set = single_set (insn);
8485 && GET_CODE (SET_DEST (set)) == REG
8486 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8487 GET_MODE (SET_DEST (set)))
8489 && GET_CODE (SET_SRC (set)) == PLUS
8490 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8491 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8492 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8494 rtx reg = SET_DEST (set);
8495 rtx plus = SET_SRC (set);
8496 rtx base = XEXP (plus, 1);
8497 rtx prev = prev_nonnote_insn (insn);
8498 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8499 unsigned int regno = REGNO (reg);
8500 rtx const_reg = NULL_RTX;
8501 rtx reg_sum = NULL_RTX;
8503 /* Now, we need an index register.
8504 We'll set index_reg to this index register, const_reg to the
8505 register that is to be loaded with the constant
8506 (denoted as REGZ in the substitution illustration above),
8507 and reg_sum to the register-register that we want to use to
8508 substitute uses of REG (typically in MEMs) with.
8509 First check REG and BASE for being index registers;
8510 we can use them even if they are not dead. */
8511 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8512 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8520 /* Otherwise, look for a free index register. Since we have
8521 checked above that neiter REG nor BASE are index registers,
8522 if we find anything at all, it will be different from these
8524 for (i = first_index_reg; i <= last_index_reg; i++)
8526 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8528 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8529 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8530 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8532 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8534 const_reg = index_reg;
8535 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8541 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8542 (REGY), i.e. BASE, is not clobbered before the last use we'll
8545 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8546 && rtx_equal_p (SET_DEST (prev_set), reg)
8547 && reg_state[regno].use_index >= 0
8548 && (reg_state[REGNO (base)].store_ruid
8549 <= reg_state[regno].use_ruid)
8554 /* Change destination register and, if necessary, the
8555 constant value in PREV, the constant loading instruction. */
8556 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8557 if (reg_state[regno].offset != const0_rtx)
8558 validate_change (prev,
8559 &SET_SRC (prev_set),
8560 GEN_INT (INTVAL (SET_SRC (prev_set))
8561 + INTVAL (reg_state[regno].offset)),
8564 /* Now for every use of REG that we have recorded, replace REG
8566 for (i = reg_state[regno].use_index;
8567 i < RELOAD_COMBINE_MAX_USES; i++)
8568 validate_change (reg_state[regno].reg_use[i].insn,
8569 reg_state[regno].reg_use[i].usep,
8572 if (apply_change_group ())
8576 /* Delete the reg-reg addition. */
8577 PUT_CODE (insn, NOTE);
8578 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8579 NOTE_SOURCE_FILE (insn) = 0;
8581 if (reg_state[regno].offset != const0_rtx)
8582 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8584 for (np = ®_NOTES (prev); *np;)
8586 if (REG_NOTE_KIND (*np) == REG_EQUAL
8587 || REG_NOTE_KIND (*np) == REG_EQUIV)
8588 *np = XEXP (*np, 1);
8590 np = &XEXP (*np, 1);
8593 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8594 reg_state[REGNO (const_reg)].store_ruid
8595 = reload_combine_ruid;
8601 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8603 if (GET_CODE (insn) == CALL_INSN)
8607 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8608 if (call_used_regs[r])
8610 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8611 reg_state[r].store_ruid = reload_combine_ruid;
8614 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8615 link = XEXP (link, 1))
8616 if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG)
8618 unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0));
8620 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8622 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8623 reg_state[regno].store_ruid = reload_combine_ruid;
8626 reg_state[regno].use_index = -1;
8630 else if (GET_CODE (insn) == JUMP_INSN
8631 && GET_CODE (PATTERN (insn)) != RETURN)
8633 /* Non-spill registers might be used at the call destination in
8634 some unknown fashion, so we have to mark the unknown use. */
8637 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8638 && JUMP_LABEL (insn))
8639 live = &LABEL_LIVE (JUMP_LABEL (insn));
8641 live = &ever_live_at_start;
8643 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8644 if (TEST_HARD_REG_BIT (*live, i))
8645 reg_state[i].use_index = -1;
8648 reload_combine_note_use (&PATTERN (insn), insn);
8649 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8651 if (REG_NOTE_KIND (note) == REG_INC
8652 && GET_CODE (XEXP (note, 0)) == REG)
8654 int regno = REGNO (XEXP (note, 0));
8656 reg_state[regno].store_ruid = reload_combine_ruid;
8657 reg_state[regno].use_index = -1;
8665 /* Check if DST is a register or a subreg of a register; if it is,
8666 update reg_state[regno].store_ruid and reg_state[regno].use_index
8667 accordingly. Called via note_stores from reload_combine. */
8670 reload_combine_note_store (dst, set, data)
8672 void *data ATTRIBUTE_UNUSED;
8676 enum machine_mode mode = GET_MODE (dst);
8678 if (GET_CODE (dst) == SUBREG)
8680 regno = SUBREG_WORD (dst);
8681 dst = SUBREG_REG (dst);
8683 if (GET_CODE (dst) != REG)
8685 regno += REGNO (dst);
8687 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8688 careful with registers / register parts that are not full words.
8690 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8691 if (GET_CODE (set) != SET
8692 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8693 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8694 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8696 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8698 reg_state[i].use_index = -1;
8699 reg_state[i].store_ruid = reload_combine_ruid;
8704 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8706 reg_state[i].store_ruid = reload_combine_ruid;
8707 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8712 /* XP points to a piece of rtl that has to be checked for any uses of
8714 *XP is the pattern of INSN, or a part of it.
8715 Called from reload_combine, and recursively by itself. */
8717 reload_combine_note_use (xp, insn)
8721 enum rtx_code code = x->code;
8724 rtx offset = const0_rtx; /* For the REG case below. */
8729 if (GET_CODE (SET_DEST (x)) == REG)
8731 reload_combine_note_use (&SET_SRC (x), insn);
8737 /* If this is the USE of a return value, we can't change it. */
8738 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8740 /* Mark the return register as used in an unknown fashion. */
8741 rtx reg = XEXP (x, 0);
8742 int regno = REGNO (reg);
8743 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8745 while (--nregs >= 0)
8746 reg_state[regno + nregs].use_index = -1;
8752 if (GET_CODE (SET_DEST (x)) == REG)
8757 /* We are interested in (plus (reg) (const_int)) . */
8758 if (GET_CODE (XEXP (x, 0)) != REG
8759 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8761 offset = XEXP (x, 1);
8766 int regno = REGNO (x);
8770 /* Some spurious USEs of pseudo registers might remain.
8771 Just ignore them. */
8772 if (regno >= FIRST_PSEUDO_REGISTER)
8775 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8777 /* We can't substitute into multi-hard-reg uses. */
8780 while (--nregs >= 0)
8781 reg_state[regno + nregs].use_index = -1;
8785 /* If this register is already used in some unknown fashion, we
8787 If we decrement the index from zero to -1, we can't store more
8788 uses, so this register becomes used in an unknown fashion. */
8789 use_index = --reg_state[regno].use_index;
8793 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8795 /* We have found another use for a register that is already
8796 used later. Check if the offsets match; if not, mark the
8797 register as used in an unknown fashion. */
8798 if (! rtx_equal_p (offset, reg_state[regno].offset))
8800 reg_state[regno].use_index = -1;
8806 /* This is the first use of this register we have seen since we
8807 marked it as dead. */
8808 reg_state[regno].offset = offset;
8809 reg_state[regno].use_ruid = reload_combine_ruid;
8811 reg_state[regno].reg_use[use_index].insn = insn;
8812 reg_state[regno].reg_use[use_index].usep = xp;
8820 /* Recursively process the components of X. */
8821 fmt = GET_RTX_FORMAT (code);
8822 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8825 reload_combine_note_use (&XEXP (x, i), insn);
8826 else if (fmt[i] == 'E')
8828 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8829 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8834 /* See if we can reduce the cost of a constant by replacing a move with
8836 /* We cannot do our optimization across labels. Invalidating all the
8837 information about register contents we have would be costly, so we
8838 use last_label_luid (local variable of reload_cse_move2add) to note
8839 where the label is and then later disable any optimization that would
8841 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8842 reg_set_luid[n] is larger than last_label_luid[n] . */
8843 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8845 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8846 reg_mode[n] to be valid.
8847 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8848 has been set to reg_offset[n] in mode reg_mode[n] .
8849 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8850 register n has been set to the sum of reg_offset[n] and register
8851 reg_base_reg[n], calculated in mode reg_mode[n] . */
8852 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8853 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8854 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8856 /* move2add_luid is linearily increased while scanning the instructions
8857 from first to last. It is used to set reg_set_luid in
8858 reload_cse_move2add and move2add_note_store. */
8859 static int move2add_luid;
8861 /* Generate a CONST_INT and force it in the range of MODE. */
8864 gen_mode_int (mode, value)
8865 enum machine_mode mode;
8866 HOST_WIDE_INT value;
8868 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8869 int width = GET_MODE_BITSIZE (mode);
8871 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8873 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8874 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8875 cval |= (HOST_WIDE_INT) -1 << width;
8877 return GEN_INT (cval);
8881 reload_cse_move2add (first)
8886 int last_label_luid;
8888 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
8889 reg_set_luid[i] = 0;
8891 last_label_luid = 0;
8893 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
8897 if (GET_CODE (insn) == CODE_LABEL)
8898 last_label_luid = move2add_luid;
8899 if (! INSN_P (insn))
8901 pat = PATTERN (insn);
8902 /* For simplicity, we only perform this optimization on
8903 straightforward SETs. */
8904 if (GET_CODE (pat) == SET
8905 && GET_CODE (SET_DEST (pat)) == REG)
8907 rtx reg = SET_DEST (pat);
8908 int regno = REGNO (reg);
8909 rtx src = SET_SRC (pat);
8911 /* Check if we have valid information on the contents of this
8912 register in the mode of REG. */
8913 /* ??? We don't know how zero / sign extension is handled, hence
8914 we can't go from a narrower to a wider mode. */
8915 if (reg_set_luid[regno] > last_label_luid
8916 && ((GET_MODE_SIZE (GET_MODE (reg))
8917 == GET_MODE_SIZE (reg_mode[regno]))
8918 || ((GET_MODE_SIZE (GET_MODE (reg))
8919 <= GET_MODE_SIZE (reg_mode[regno]))
8920 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)),
8921 GET_MODE_BITSIZE (reg_mode[regno]))))
8922 && GET_CODE (reg_offset[regno]) == CONST_INT)
8924 /* Try to transform (set (REGX) (CONST_INT A))
8926 (set (REGX) (CONST_INT B))
8928 (set (REGX) (CONST_INT A))
8930 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8932 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
8936 = gen_mode_int (GET_MODE (reg),
8937 INTVAL (src) - INTVAL (reg_offset[regno]));
8938 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8939 use (set (reg) (reg)) instead.
8940 We don't delete this insn, nor do we convert it into a
8941 note, to avoid losing register notes or the return
8942 value flag. jump2 already knowns how to get rid of
8944 if (new_src == const0_rtx)
8945 success = validate_change (insn, &SET_SRC (pat), reg, 0);
8946 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
8947 && have_add2_insn (GET_MODE (reg)))
8948 success = validate_change (insn, &PATTERN (insn),
8949 gen_add2_insn (reg, new_src), 0);
8950 reg_set_luid[regno] = move2add_luid;
8951 reg_mode[regno] = GET_MODE (reg);
8952 reg_offset[regno] = src;
8956 /* Try to transform (set (REGX) (REGY))
8957 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8960 (set (REGX) (PLUS (REGX) (CONST_INT B)))
8963 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8965 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8966 else if (GET_CODE (src) == REG
8967 && reg_base_reg[regno] == (int) REGNO (src)
8968 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
8970 rtx next = next_nonnote_insn (insn);
8973 set = single_set (next);
8976 && SET_DEST (set) == reg
8977 && GET_CODE (SET_SRC (set)) == PLUS
8978 && XEXP (SET_SRC (set), 0) == reg
8979 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
8981 rtx src3 = XEXP (SET_SRC (set), 1);
8983 = gen_mode_int (GET_MODE (reg),
8985 - INTVAL (reg_offset[regno]));
8988 if (new_src == const0_rtx)
8989 /* See above why we create (set (reg) (reg)) here. */
8991 = validate_change (next, &SET_SRC (set), reg, 0);
8992 else if ((rtx_cost (new_src, PLUS)
8993 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
8994 && have_add2_insn (GET_MODE (reg)))
8996 = validate_change (next, &PATTERN (next),
8997 gen_add2_insn (reg, new_src), 0);
9000 /* INSN might be the first insn in a basic block
9001 if the preceding insn is a conditional jump
9002 or a possible-throwing call. */
9003 PUT_CODE (insn, NOTE);
9004 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9005 NOTE_SOURCE_FILE (insn) = 0;
9008 reg_set_luid[regno] = move2add_luid;
9009 reg_mode[regno] = GET_MODE (reg);
9010 reg_offset[regno] = src3;
9017 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9019 if (REG_NOTE_KIND (note) == REG_INC
9020 && GET_CODE (XEXP (note, 0)) == REG)
9022 /* Indicate that this register has been recently written to,
9023 but the exact contents are not available. */
9024 int regno = REGNO (XEXP (note, 0));
9025 if (regno < FIRST_PSEUDO_REGISTER)
9027 reg_set_luid[regno] = move2add_luid;
9028 reg_offset[regno] = note;
9032 note_stores (PATTERN (insn), move2add_note_store, NULL);
9033 /* If this is a CALL_INSN, all call used registers are stored with
9035 if (GET_CODE (insn) == CALL_INSN)
9037 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9039 if (call_used_regs[i])
9041 reg_set_luid[i] = move2add_luid;
9042 reg_offset[i] = insn; /* Invalidate contents. */
9049 /* SET is a SET or CLOBBER that sets DST.
9050 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9051 Called from reload_cse_move2add via note_stores. */
9054 move2add_note_store (dst, set, data)
9056 void *data ATTRIBUTE_UNUSED;
9058 unsigned int regno = 0;
9060 enum machine_mode mode = GET_MODE (dst);
9062 if (GET_CODE (dst) == SUBREG)
9064 regno = SUBREG_WORD (dst);
9065 dst = SUBREG_REG (dst);
9068 /* Some targets do argument pushes without adding REG_INC notes. */
9070 if (GET_CODE (dst) == MEM)
9072 dst = XEXP (dst, 0);
9073 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9074 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9076 regno = REGNO (XEXP (dst, 0));
9077 reg_set_luid[regno] = move2add_luid;
9078 reg_offset[regno] = dst;
9082 if (GET_CODE (dst) != REG)
9085 regno += REGNO (dst);
9087 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9088 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9089 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9090 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9092 rtx src = SET_SRC (set);
9094 reg_mode[regno] = mode;
9095 switch (GET_CODE (src))
9099 rtx src0 = XEXP (src, 0);
9101 if (GET_CODE (src0) == REG)
9103 if (REGNO (src0) != regno
9104 || reg_offset[regno] != const0_rtx)
9106 reg_base_reg[regno] = REGNO (src0);
9107 reg_set_luid[regno] = move2add_luid;
9110 reg_offset[regno] = XEXP (src, 1);
9114 reg_set_luid[regno] = move2add_luid;
9115 reg_offset[regno] = set; /* Invalidate contents. */
9120 reg_base_reg[regno] = REGNO (SET_SRC (set));
9121 reg_offset[regno] = const0_rtx;
9122 reg_set_luid[regno] = move2add_luid;
9126 reg_base_reg[regno] = -1;
9127 reg_offset[regno] = SET_SRC (set);
9128 reg_set_luid[regno] = move2add_luid;
9134 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9136 for (i = regno; i < endregno; i++)
9138 /* Indicate that this register has been recently written to,
9139 but the exact contents are not available. */
9140 reg_set_luid[i] = move2add_luid;
9141 reg_offset[i] = dst;
9148 add_auto_inc_notes (insn, x)
9152 enum rtx_code code = GET_CODE (x);
9156 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9159 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9163 /* Scan all the operand sub-expressions. */
9164 fmt = GET_RTX_FORMAT (code);
9165 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9168 add_auto_inc_notes (insn, XEXP (x, i));
9169 else if (fmt[i] == 'E')
9170 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9171 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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