1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static regset_head reg_has_output_reload;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx *reg_equiv_invariant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
127 alternate representations of the location of pseudo reg N. */
128 rtx *reg_equiv_alt_mem_list;
130 /* Widest width in which each pseudo reg is referred to (via subreg). */
131 static unsigned int *reg_max_ref_width;
133 /* Element N is the list of insns that initialized reg N from its equivalent
134 constant or memory slot. */
136 int reg_equiv_init_size;
138 /* Vector to remember old contents of reg_renumber before spilling. */
139 static short *reg_old_renumber;
141 /* During reload_as_needed, element N contains the last pseudo regno reloaded
142 into hard register N. If that pseudo reg occupied more than one register,
143 reg_reloaded_contents points to that pseudo for each spill register in
144 use; all of these must remain set for an inheritance to occur. */
145 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
147 /* During reload_as_needed, element N contains the insn for which
148 hard register N was last used. Its contents are significant only
149 when reg_reloaded_valid is set for this register. */
150 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
152 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
153 static HARD_REG_SET reg_reloaded_valid;
154 /* Indicate if the register was dead at the end of the reload.
155 This is only valid if reg_reloaded_contents is set and valid. */
156 static HARD_REG_SET reg_reloaded_dead;
158 /* Indicate whether the register's current value is one that is not
159 safe to retain across a call, even for registers that are normally
161 static HARD_REG_SET reg_reloaded_call_part_clobbered;
163 /* Number of spill-regs so far; number of valid elements of spill_regs. */
166 /* In parallel with spill_regs, contains REG rtx's for those regs.
167 Holds the last rtx used for any given reg, or 0 if it has never
168 been used for spilling yet. This rtx is reused, provided it has
170 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
172 /* In parallel with spill_regs, contains nonzero for a spill reg
173 that was stored after the last time it was used.
174 The precise value is the insn generated to do the store. */
175 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
177 /* This is the register that was stored with spill_reg_store. This is a
178 copy of reload_out / reload_out_reg when the value was stored; if
179 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
180 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
182 /* This table is the inverse mapping of spill_regs:
183 indexed by hard reg number,
184 it contains the position of that reg in spill_regs,
185 or -1 for something that is not in spill_regs.
187 ?!? This is no longer accurate. */
188 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
190 /* This reg set indicates registers that can't be used as spill registers for
191 the currently processed insn. These are the hard registers which are live
192 during the insn, but not allocated to pseudos, as well as fixed
194 static HARD_REG_SET bad_spill_regs;
196 /* These are the hard registers that can't be used as spill register for any
197 insn. This includes registers used for user variables and registers that
198 we can't eliminate. A register that appears in this set also can't be used
199 to retry register allocation. */
200 static HARD_REG_SET bad_spill_regs_global;
202 /* Describes order of use of registers for reloading
203 of spilled pseudo-registers. `n_spills' is the number of
204 elements that are actually valid; new ones are added at the end.
206 Both spill_regs and spill_reg_order are used on two occasions:
207 once during find_reload_regs, where they keep track of the spill registers
208 for a single insn, but also during reload_as_needed where they show all
209 the registers ever used by reload. For the latter case, the information
210 is calculated during finish_spills. */
211 static short spill_regs[FIRST_PSEUDO_REGISTER];
213 /* This vector of reg sets indicates, for each pseudo, which hard registers
214 may not be used for retrying global allocation because the register was
215 formerly spilled from one of them. If we allowed reallocating a pseudo to
216 a register that it was already allocated to, reload might not
218 static HARD_REG_SET *pseudo_previous_regs;
220 /* This vector of reg sets indicates, for each pseudo, which hard
221 registers may not be used for retrying global allocation because they
222 are used as spill registers during one of the insns in which the
224 static HARD_REG_SET *pseudo_forbidden_regs;
226 /* All hard regs that have been used as spill registers for any insn are
227 marked in this set. */
228 static HARD_REG_SET used_spill_regs;
230 /* Index of last register assigned as a spill register. We allocate in
231 a round-robin fashion. */
232 static int last_spill_reg;
234 /* Nonzero if indirect addressing is supported on the machine; this means
235 that spilling (REG n) does not require reloading it into a register in
236 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
237 value indicates the level of indirect addressing supported, e.g., two
238 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
240 static char spill_indirect_levels;
242 /* Nonzero if indirect addressing is supported when the innermost MEM is
243 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
244 which these are valid is the same as spill_indirect_levels, above. */
245 char indirect_symref_ok;
247 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
248 char double_reg_address_ok;
250 /* Record the stack slot for each spilled hard register. */
251 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
253 /* Width allocated so far for that stack slot. */
254 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
256 /* Record which pseudos needed to be spilled. */
257 static regset_head spilled_pseudos;
259 /* Used for communication between order_regs_for_reload and count_pseudo.
260 Used to avoid counting one pseudo twice. */
261 static regset_head pseudos_counted;
263 /* First uid used by insns created by reload in this function.
264 Used in find_equiv_reg. */
265 int reload_first_uid;
267 /* Flag set by local-alloc or global-alloc if anything is live in
268 a call-clobbered reg across calls. */
269 int caller_save_needed;
271 /* Set to 1 while reload_as_needed is operating.
272 Required by some machines to handle any generated moves differently. */
273 int reload_in_progress = 0;
275 /* These arrays record the insn_code of insns that may be needed to
276 perform input and output reloads of special objects. They provide a
277 place to pass a scratch register. */
278 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
279 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
281 /* This obstack is used for allocation of rtl during register elimination.
282 The allocated storage can be freed once find_reloads has processed the
284 static struct obstack reload_obstack;
286 /* Points to the beginning of the reload_obstack. All insn_chain structures
287 are allocated first. */
288 static char *reload_startobj;
290 /* The point after all insn_chain structures. Used to quickly deallocate
291 memory allocated in copy_reloads during calculate_needs_all_insns. */
292 static char *reload_firstobj;
294 /* This points before all local rtl generated by register elimination.
295 Used to quickly free all memory after processing one insn. */
296 static char *reload_insn_firstobj;
298 /* List of insn_chain instructions, one for every insn that reload needs to
300 struct insn_chain *reload_insn_chain;
302 /* List of all insns needing reloads. */
303 static struct insn_chain *insns_need_reload;
305 /* This structure is used to record information about register eliminations.
306 Each array entry describes one possible way of eliminating a register
307 in favor of another. If there is more than one way of eliminating a
308 particular register, the most preferred should be specified first. */
312 int from; /* Register number to be eliminated. */
313 int to; /* Register number used as replacement. */
314 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
315 int can_eliminate; /* Nonzero if this elimination can be done. */
316 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
317 insns made by reload. */
318 HOST_WIDE_INT offset; /* Current offset between the two regs. */
319 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
320 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
321 rtx from_rtx; /* REG rtx for the register to be eliminated.
322 We cannot simply compare the number since
323 we might then spuriously replace a hard
324 register corresponding to a pseudo
325 assigned to the reg to be eliminated. */
326 rtx to_rtx; /* REG rtx for the replacement. */
329 static struct elim_table *reg_eliminate = 0;
331 /* This is an intermediate structure to initialize the table. It has
332 exactly the members provided by ELIMINABLE_REGS. */
333 static const struct elim_table_1
337 } reg_eliminate_1[] =
339 /* If a set of eliminable registers was specified, define the table from it.
340 Otherwise, default to the normal case of the frame pointer being
341 replaced by the stack pointer. */
343 #ifdef ELIMINABLE_REGS
346 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
349 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
351 /* Record the number of pending eliminations that have an offset not equal
352 to their initial offset. If nonzero, we use a new copy of each
353 replacement result in any insns encountered. */
354 int num_not_at_initial_offset;
356 /* Count the number of registers that we may be able to eliminate. */
357 static int num_eliminable;
358 /* And the number of registers that are equivalent to a constant that
359 can be eliminated to frame_pointer / arg_pointer + constant. */
360 static int num_eliminable_invariants;
362 /* For each label, we record the offset of each elimination. If we reach
363 a label by more than one path and an offset differs, we cannot do the
364 elimination. This information is indexed by the difference of the
365 number of the label and the first label number. We can't offset the
366 pointer itself as this can cause problems on machines with segmented
367 memory. The first table is an array of flags that records whether we
368 have yet encountered a label and the second table is an array of arrays,
369 one entry in the latter array for each elimination. */
371 static int first_label_num;
372 static char *offsets_known_at;
373 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
375 /* Number of labels in the current function. */
377 static int num_labels;
379 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
380 static void maybe_fix_stack_asms (void);
381 static void copy_reloads (struct insn_chain *);
382 static void calculate_needs_all_insns (int);
383 static int find_reg (struct insn_chain *, int);
384 static void find_reload_regs (struct insn_chain *);
385 static void select_reload_regs (void);
386 static void delete_caller_save_insns (void);
388 static void spill_failure (rtx, enum reg_class);
389 static void count_spilled_pseudo (int, int, int);
390 static void delete_dead_insn (rtx);
391 static void alter_reg (int, int);
392 static void set_label_offsets (rtx, rtx, int);
393 static void check_eliminable_occurrences (rtx);
394 static void elimination_effects (rtx, enum machine_mode);
395 static int eliminate_regs_in_insn (rtx, int);
396 static void update_eliminable_offsets (void);
397 static void mark_not_eliminable (rtx, rtx, void *);
398 static void set_initial_elim_offsets (void);
399 static bool verify_initial_elim_offsets (void);
400 static void set_initial_label_offsets (void);
401 static void set_offsets_for_label (rtx);
402 static void init_elim_table (void);
403 static void update_eliminables (HARD_REG_SET *);
404 static void spill_hard_reg (unsigned int, int);
405 static int finish_spills (int);
406 static void scan_paradoxical_subregs (rtx);
407 static void count_pseudo (int);
408 static void order_regs_for_reload (struct insn_chain *);
409 static void reload_as_needed (int);
410 static void forget_old_reloads_1 (rtx, rtx, void *);
411 static void forget_marked_reloads (regset);
412 static int reload_reg_class_lower (const void *, const void *);
413 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
415 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
417 static int reload_reg_free_p (unsigned int, int, enum reload_type);
418 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
420 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
422 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
423 static int allocate_reload_reg (struct insn_chain *, int, int);
424 static int conflicts_with_override (rtx);
425 static void failed_reload (rtx, int);
426 static int set_reload_reg (int, int);
427 static void choose_reload_regs_init (struct insn_chain *, rtx *);
428 static void choose_reload_regs (struct insn_chain *);
429 static void merge_assigned_reloads (rtx);
430 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
432 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
434 static void do_input_reload (struct insn_chain *, struct reload *, int);
435 static void do_output_reload (struct insn_chain *, struct reload *, int);
436 static bool inherit_piecemeal_p (int, int);
437 static void emit_reload_insns (struct insn_chain *);
438 static void delete_output_reload (rtx, int, int);
439 static void delete_address_reloads (rtx, rtx);
440 static void delete_address_reloads_1 (rtx, rtx, rtx);
441 static rtx inc_for_reload (rtx, rtx, rtx, int);
443 static void add_auto_inc_notes (rtx, rtx);
445 static void copy_eh_notes (rtx, rtx);
446 static int reloads_conflict (int, int);
447 static rtx gen_reload (rtx, rtx, int, enum reload_type);
448 static rtx emit_insn_if_valid_for_reload (rtx);
450 /* Initialize the reload pass once per compilation. */
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
462 = gen_rtx_MEM (Pmode,
465 LAST_VIRTUAL_REGISTER + 1),
467 spill_indirect_levels = 0;
469 while (memory_address_p (QImode, tem))
471 spill_indirect_levels++;
472 tem = gen_rtx_MEM (Pmode, tem);
475 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
477 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
478 indirect_symref_ok = memory_address_p (QImode, tem);
480 /* See if reg+reg is a valid (and offsettable) address. */
482 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 tem = gen_rtx_PLUS (Pmode,
485 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
486 gen_rtx_REG (Pmode, i));
488 /* This way, we make sure that reg+reg is an offsettable address. */
489 tem = plus_constant (tem, 4);
491 if (memory_address_p (QImode, tem))
493 double_reg_address_ok = 1;
498 /* Initialize obstack for our rtl allocation. */
499 gcc_obstack_init (&reload_obstack);
500 reload_startobj = obstack_alloc (&reload_obstack, 0);
502 INIT_REG_SET (&spilled_pseudos);
503 INIT_REG_SET (&pseudos_counted);
506 /* List of insn chains that are currently unused. */
507 static struct insn_chain *unused_insn_chains = 0;
509 /* Allocate an empty insn_chain structure. */
511 new_insn_chain (void)
513 struct insn_chain *c;
515 if (unused_insn_chains == 0)
517 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
518 INIT_REG_SET (&c->live_throughout);
519 INIT_REG_SET (&c->dead_or_set);
523 c = unused_insn_chains;
524 unused_insn_chains = c->next;
526 c->is_caller_save_insn = 0;
527 c->need_operand_change = 0;
533 /* Small utility function to set all regs in hard reg set TO which are
534 allocated to pseudos in regset FROM. */
537 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
540 reg_set_iterator rsi;
542 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
544 int r = reg_renumber[regno];
549 /* reload_combine uses the information from
550 BASIC_BLOCK->global_live_at_start, which might still
551 contain registers that have not actually been allocated
552 since they have an equivalence. */
553 gcc_assert (reload_completed);
557 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
559 SET_HARD_REG_BIT (*to, r + nregs);
564 /* Replace all pseudos found in LOC with their corresponding
568 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
581 unsigned int regno = REGNO (x);
583 if (regno < FIRST_PSEUDO_REGISTER)
586 x = eliminate_regs (x, mem_mode, usage);
590 replace_pseudos_in (loc, mem_mode, usage);
594 if (reg_equiv_constant[regno])
595 *loc = reg_equiv_constant[regno];
596 else if (reg_equiv_mem[regno])
597 *loc = reg_equiv_mem[regno];
598 else if (reg_equiv_address[regno])
599 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
602 gcc_assert (!REG_P (regno_reg_rtx[regno])
603 || REGNO (regno_reg_rtx[regno]) != regno);
604 *loc = regno_reg_rtx[regno];
609 else if (code == MEM)
611 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
615 /* Process each of our operands recursively. */
616 fmt = GET_RTX_FORMAT (code);
617 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
619 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
620 else if (*fmt == 'E')
621 for (j = 0; j < XVECLEN (x, i); j++)
622 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
626 /* Global variables used by reload and its subroutines. */
628 /* Set during calculate_needs if an insn needs register elimination. */
629 static int something_needs_elimination;
630 /* Set during calculate_needs if an insn needs an operand changed. */
631 static int something_needs_operands_changed;
633 /* Nonzero means we couldn't get enough spill regs. */
636 /* Main entry point for the reload pass.
638 FIRST is the first insn of the function being compiled.
640 GLOBAL nonzero means we were called from global_alloc
641 and should attempt to reallocate any pseudoregs that we
642 displace from hard regs we will use for reloads.
643 If GLOBAL is zero, we do not have enough information to do that,
644 so any pseudo reg that is spilled must go to the stack.
646 Return value is nonzero if reload failed
647 and we must not do any more for this function. */
650 reload (rtx first, int global)
654 struct elim_table *ep;
657 /* Make sure even insns with volatile mem refs are recognizable. */
662 reload_firstobj = obstack_alloc (&reload_obstack, 0);
664 /* Make sure that the last insn in the chain
665 is not something that needs reloading. */
666 emit_note (NOTE_INSN_DELETED);
668 /* Enable find_equiv_reg to distinguish insns made by reload. */
669 reload_first_uid = get_max_uid ();
671 #ifdef SECONDARY_MEMORY_NEEDED
672 /* Initialize the secondary memory table. */
673 clear_secondary_mem ();
676 /* We don't have a stack slot for any spill reg yet. */
677 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
678 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
680 /* Initialize the save area information for caller-save, in case some
684 /* Compute which hard registers are now in use
685 as homes for pseudo registers.
686 This is done here rather than (eg) in global_alloc
687 because this point is reached even if not optimizing. */
688 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
691 /* A function that receives a nonlocal goto must save all call-saved
693 if (current_function_has_nonlocal_label)
694 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
695 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
696 regs_ever_live[i] = 1;
698 /* Find all the pseudo registers that didn't get hard regs
699 but do have known equivalent constants or memory slots.
700 These include parameters (known equivalent to parameter slots)
701 and cse'd or loop-moved constant memory addresses.
703 Record constant equivalents in reg_equiv_constant
704 so they will be substituted by find_reloads.
705 Record memory equivalents in reg_mem_equiv so they can
706 be substituted eventually by altering the REG-rtx's. */
708 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
709 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
710 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
711 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
712 reg_equiv_address = XCNEWVEC (rtx, max_regno);
713 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
714 reg_old_renumber = XCNEWVEC (short, max_regno);
715 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
716 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
717 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
719 CLEAR_HARD_REG_SET (bad_spill_regs_global);
721 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
722 to. Also find all paradoxical subregs and find largest such for
725 num_eliminable_invariants = 0;
726 for (insn = first; insn; insn = NEXT_INSN (insn))
728 rtx set = single_set (insn);
730 /* We may introduce USEs that we want to remove at the end, so
731 we'll mark them with QImode. Make sure there are no
732 previously-marked insns left by say regmove. */
733 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
734 && GET_MODE (insn) != VOIDmode)
735 PUT_MODE (insn, VOIDmode);
738 scan_paradoxical_subregs (PATTERN (insn));
740 if (set != 0 && REG_P (SET_DEST (set)))
742 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
748 i = REGNO (SET_DEST (set));
751 if (i <= LAST_VIRTUAL_REGISTER)
754 if (! function_invariant_p (x)
756 /* A function invariant is often CONSTANT_P but may
757 include a register. We promise to only pass
758 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
760 && LEGITIMATE_PIC_OPERAND_P (x)))
762 /* It can happen that a REG_EQUIV note contains a MEM
763 that is not a legitimate memory operand. As later
764 stages of reload assume that all addresses found
765 in the reg_equiv_* arrays were originally legitimate,
766 we ignore such REG_EQUIV notes. */
767 if (memory_operand (x, VOIDmode))
769 /* Always unshare the equivalence, so we can
770 substitute into this insn without touching the
772 reg_equiv_memory_loc[i] = copy_rtx (x);
774 else if (function_invariant_p (x))
776 if (GET_CODE (x) == PLUS)
778 /* This is PLUS of frame pointer and a constant,
779 and might be shared. Unshare it. */
780 reg_equiv_invariant[i] = copy_rtx (x);
781 num_eliminable_invariants++;
783 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
785 reg_equiv_invariant[i] = x;
786 num_eliminable_invariants++;
788 else if (LEGITIMATE_CONSTANT_P (x))
789 reg_equiv_constant[i] = x;
792 reg_equiv_memory_loc[i]
793 = force_const_mem (GET_MODE (SET_DEST (set)), x);
794 if (! reg_equiv_memory_loc[i])
795 reg_equiv_init[i] = NULL_RTX;
800 reg_equiv_init[i] = NULL_RTX;
805 reg_equiv_init[i] = NULL_RTX;
810 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
811 if (reg_equiv_init[i])
813 fprintf (dump_file, "init_insns for %u: ", i);
814 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
815 fprintf (dump_file, "\n");
820 first_label_num = get_first_label_num ();
821 num_labels = max_label_num () - first_label_num;
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at = XNEWVEC (char, num_labels);
828 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
834 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
843 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
847 maybe_fix_stack_asms ();
849 insns_need_reload = 0;
850 something_needs_elimination = 0;
852 /* Initialize to -1, which means take the first spill register. */
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
863 int can_eliminate = 0;
866 can_eliminate |= ep->can_eliminate;
869 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
871 spill_hard_reg (from, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed;
892 HOST_WIDE_INT starting_frame_size;
894 /* Round size of stack frame to stack_alignment_needed. This must be done
895 here because the stack size may be a part of the offset computation
896 for register elimination, and there might have been new stack slots
897 created in the last iteration of this loop. */
898 if (cfun->stack_alignment_needed)
899 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
901 starting_frame_size = get_frame_size ();
903 set_initial_elim_offsets ();
904 set_initial_label_offsets ();
906 /* For each pseudo register that has an equivalent location defined,
907 try to eliminate any eliminable registers (such as the frame pointer)
908 assuming initial offsets for the replacement register, which
911 If the resulting location is directly addressable, substitute
912 the MEM we just got directly for the old REG.
914 If it is not addressable but is a constant or the sum of a hard reg
915 and constant, it is probably not addressable because the constant is
916 out of range, in that case record the address; we will generate
917 hairy code to compute the address in a register each time it is
918 needed. Similarly if it is a hard register, but one that is not
919 valid as an address register.
921 If the location is not addressable, but does not have one of the
922 above forms, assign a stack slot. We have to do this to avoid the
923 potential of producing lots of reloads if, e.g., a location involves
924 a pseudo that didn't get a hard register and has an equivalent memory
925 location that also involves a pseudo that didn't get a hard register.
927 Perhaps at some point we will improve reload_when_needed handling
928 so this problem goes away. But that's very hairy. */
930 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
931 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
933 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
935 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
937 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
938 else if (CONSTANT_P (XEXP (x, 0))
939 || (REG_P (XEXP (x, 0))
940 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
941 || (GET_CODE (XEXP (x, 0)) == PLUS
942 && REG_P (XEXP (XEXP (x, 0), 0))
943 && (REGNO (XEXP (XEXP (x, 0), 0))
944 < FIRST_PSEUDO_REGISTER)
945 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
946 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
949 /* Make a new stack slot. Then indicate that something
950 changed so we go back and recompute offsets for
951 eliminable registers because the allocation of memory
952 below might change some offset. reg_equiv_{mem,address}
953 will be set up for this pseudo on the next pass around
955 reg_equiv_memory_loc[i] = 0;
956 reg_equiv_init[i] = 0;
961 if (caller_save_needed)
964 /* If we allocated another stack slot, redo elimination bookkeeping. */
965 if (starting_frame_size != get_frame_size ())
968 if (caller_save_needed)
970 save_call_clobbered_regs ();
971 /* That might have allocated new insn_chain structures. */
972 reload_firstobj = obstack_alloc (&reload_obstack, 0);
975 calculate_needs_all_insns (global);
977 CLEAR_REG_SET (&spilled_pseudos);
980 something_changed = 0;
982 /* If we allocated any new memory locations, make another pass
983 since it might have changed elimination offsets. */
984 if (starting_frame_size != get_frame_size ())
985 something_changed = 1;
987 /* Even if the frame size remained the same, we might still have
988 changed elimination offsets, e.g. if find_reloads called
989 force_const_mem requiring the back end to allocate a constant
990 pool base register that needs to be saved on the stack. */
991 else if (!verify_initial_elim_offsets ())
992 something_changed = 1;
995 HARD_REG_SET to_spill;
996 CLEAR_HARD_REG_SET (to_spill);
997 update_eliminables (&to_spill);
998 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1000 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1001 if (TEST_HARD_REG_BIT (to_spill, i))
1003 spill_hard_reg (i, 1);
1006 /* Regardless of the state of spills, if we previously had
1007 a register that we thought we could eliminate, but now can
1008 not eliminate, we must run another pass.
1010 Consider pseudos which have an entry in reg_equiv_* which
1011 reference an eliminable register. We must make another pass
1012 to update reg_equiv_* so that we do not substitute in the
1013 old value from when we thought the elimination could be
1015 something_changed = 1;
1019 select_reload_regs ();
1023 if (insns_need_reload != 0 || did_spill)
1024 something_changed |= finish_spills (global);
1026 if (! something_changed)
1029 if (caller_save_needed)
1030 delete_caller_save_insns ();
1032 obstack_free (&reload_obstack, reload_firstobj);
1035 /* If global-alloc was run, notify it of any register eliminations we have
1038 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1039 if (ep->can_eliminate)
1040 mark_elimination (ep->from, ep->to);
1042 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1043 If that insn didn't set the register (i.e., it copied the register to
1044 memory), just delete that insn instead of the equivalencing insn plus
1045 anything now dead. If we call delete_dead_insn on that insn, we may
1046 delete the insn that actually sets the register if the register dies
1047 there and that is incorrect. */
1049 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1051 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1054 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1056 rtx equiv_insn = XEXP (list, 0);
1058 /* If we already deleted the insn or if it may trap, we can't
1059 delete it. The latter case shouldn't happen, but can
1060 if an insn has a variable address, gets a REG_EH_REGION
1061 note added to it, and then gets converted into a load
1062 from a constant address. */
1063 if (NOTE_P (equiv_insn)
1064 || can_throw_internal (equiv_insn))
1066 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1067 delete_dead_insn (equiv_insn);
1069 SET_INSN_DELETED (equiv_insn);
1074 /* Use the reload registers where necessary
1075 by generating move instructions to move the must-be-register
1076 values into or out of the reload registers. */
1078 if (insns_need_reload != 0 || something_needs_elimination
1079 || something_needs_operands_changed)
1081 HOST_WIDE_INT old_frame_size = get_frame_size ();
1083 reload_as_needed (global);
1085 gcc_assert (old_frame_size == get_frame_size ());
1087 gcc_assert (verify_initial_elim_offsets ());
1090 /* If we were able to eliminate the frame pointer, show that it is no
1091 longer live at the start of any basic block. If it ls live by
1092 virtue of being in a pseudo, that pseudo will be marked live
1093 and hence the frame pointer will be known to be live via that
1096 if (! frame_pointer_needed)
1098 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1099 HARD_FRAME_POINTER_REGNUM);
1101 /* Come here (with failure set nonzero) if we can't get enough spill
1105 CLEAR_REG_SET (&spilled_pseudos);
1106 reload_in_progress = 0;
1108 /* Now eliminate all pseudo regs by modifying them into
1109 their equivalent memory references.
1110 The REG-rtx's for the pseudos are modified in place,
1111 so all insns that used to refer to them now refer to memory.
1113 For a reg that has a reg_equiv_address, all those insns
1114 were changed by reloading so that no insns refer to it any longer;
1115 but the DECL_RTL of a variable decl may refer to it,
1116 and if so this causes the debugging info to mention the variable. */
1118 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1122 if (reg_equiv_mem[i])
1123 addr = XEXP (reg_equiv_mem[i], 0);
1125 if (reg_equiv_address[i])
1126 addr = reg_equiv_address[i];
1130 if (reg_renumber[i] < 0)
1132 rtx reg = regno_reg_rtx[i];
1134 REG_USERVAR_P (reg) = 0;
1135 PUT_CODE (reg, MEM);
1136 XEXP (reg, 0) = addr;
1137 if (reg_equiv_memory_loc[i])
1138 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1141 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1142 MEM_ATTRS (reg) = 0;
1144 MEM_NOTRAP_P (reg) = 1;
1146 else if (reg_equiv_mem[i])
1147 XEXP (reg_equiv_mem[i], 0) = addr;
1151 /* We must set reload_completed now since the cleanup_subreg_operands call
1152 below will re-recognize each insn and reload may have generated insns
1153 which are only valid during and after reload. */
1154 reload_completed = 1;
1156 /* Make a pass over all the insns and delete all USEs which we inserted
1157 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1158 notes. Delete all CLOBBER insns, except those that refer to the return
1159 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1160 from misarranging variable-array code, and simplify (subreg (reg))
1161 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1162 are no longer useful or accurate. Strip and regenerate REG_INC notes
1163 that may have been moved around. */
1165 for (insn = first; insn; insn = NEXT_INSN (insn))
1170 /* Clean up invalid ASMs so that they don't confuse later passes.
1172 if (asm_noperands (PATTERN (insn)) >= 0)
1174 extract_insn (insn);
1175 if (!constrain_operands (1))
1177 error_for_asm (insn,
1178 "%<asm%> operand has impossible constraints");
1185 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1186 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1188 if ((GET_CODE (PATTERN (insn)) == USE
1189 /* We mark with QImode USEs introduced by reload itself. */
1190 && (GET_MODE (insn) == QImode
1191 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1192 || (GET_CODE (PATTERN (insn)) == CLOBBER
1193 && (!MEM_P (XEXP (PATTERN (insn), 0))
1194 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1195 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1196 && XEXP (XEXP (PATTERN (insn), 0), 0)
1197 != stack_pointer_rtx))
1198 && (!REG_P (XEXP (PATTERN (insn), 0))
1199 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1205 /* Some CLOBBERs may survive until here and still reference unassigned
1206 pseudos with const equivalent, which may in turn cause ICE in later
1207 passes if the reference remains in place. */
1208 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1209 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1210 VOIDmode, PATTERN (insn));
1212 /* Discard obvious no-ops, even without -O. This optimization
1213 is fast and doesn't interfere with debugging. */
1214 if (NONJUMP_INSN_P (insn)
1215 && GET_CODE (PATTERN (insn)) == SET
1216 && REG_P (SET_SRC (PATTERN (insn)))
1217 && REG_P (SET_DEST (PATTERN (insn)))
1218 && (REGNO (SET_SRC (PATTERN (insn)))
1219 == REGNO (SET_DEST (PATTERN (insn)))))
1225 pnote = ®_NOTES (insn);
1228 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1229 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1230 || REG_NOTE_KIND (*pnote) == REG_INC
1231 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1232 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1233 *pnote = XEXP (*pnote, 1);
1235 pnote = &XEXP (*pnote, 1);
1239 add_auto_inc_notes (insn, PATTERN (insn));
1242 /* And simplify (subreg (reg)) if it appears as an operand. */
1243 cleanup_subreg_operands (insn);
1246 /* If we are doing stack checking, give a warning if this function's
1247 frame size is larger than we expect. */
1248 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1250 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1251 static int verbose_warned = 0;
1253 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1254 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1255 size += UNITS_PER_WORD;
1257 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1259 warning (0, "frame size too large for reliable stack checking");
1260 if (! verbose_warned)
1262 warning (0, "try reducing the number of local variables");
1268 /* Indicate that we no longer have known memory locations or constants. */
1269 if (reg_equiv_constant)
1270 free (reg_equiv_constant);
1271 if (reg_equiv_invariant)
1272 free (reg_equiv_invariant);
1273 reg_equiv_constant = 0;
1274 reg_equiv_invariant = 0;
1275 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1276 reg_equiv_memory_loc = 0;
1278 if (offsets_known_at)
1279 free (offsets_known_at);
1283 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1284 if (reg_equiv_alt_mem_list[i])
1285 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1286 free (reg_equiv_alt_mem_list);
1288 free (reg_equiv_mem);
1290 free (reg_equiv_address);
1291 free (reg_max_ref_width);
1292 free (reg_old_renumber);
1293 free (pseudo_previous_regs);
1294 free (pseudo_forbidden_regs);
1296 CLEAR_HARD_REG_SET (used_spill_regs);
1297 for (i = 0; i < n_spills; i++)
1298 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1300 /* Free all the insn_chain structures at once. */
1301 obstack_free (&reload_obstack, reload_startobj);
1302 unused_insn_chains = 0;
1303 fixup_abnormal_edges ();
1305 /* Replacing pseudos with their memory equivalents might have
1306 created shared rtx. Subsequent passes would get confused
1307 by this, so unshare everything here. */
1308 unshare_all_rtl_again (first);
1310 #ifdef STACK_BOUNDARY
1311 /* init_emit has set the alignment of the hard frame pointer
1312 to STACK_BOUNDARY. It is very likely no longer valid if
1313 the hard frame pointer was used for register allocation. */
1314 if (!frame_pointer_needed)
1315 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1321 /* Yet another special case. Unfortunately, reg-stack forces people to
1322 write incorrect clobbers in asm statements. These clobbers must not
1323 cause the register to appear in bad_spill_regs, otherwise we'll call
1324 fatal_insn later. We clear the corresponding regnos in the live
1325 register sets to avoid this.
1326 The whole thing is rather sick, I'm afraid. */
1329 maybe_fix_stack_asms (void)
1332 const char *constraints[MAX_RECOG_OPERANDS];
1333 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1334 struct insn_chain *chain;
1336 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1339 HARD_REG_SET clobbered, allowed;
1342 if (! INSN_P (chain->insn)
1343 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1345 pat = PATTERN (chain->insn);
1346 if (GET_CODE (pat) != PARALLEL)
1349 CLEAR_HARD_REG_SET (clobbered);
1350 CLEAR_HARD_REG_SET (allowed);
1352 /* First, make a mask of all stack regs that are clobbered. */
1353 for (i = 0; i < XVECLEN (pat, 0); i++)
1355 rtx t = XVECEXP (pat, 0, i);
1356 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1357 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1360 /* Get the operand values and constraints out of the insn. */
1361 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1362 constraints, operand_mode);
1364 /* For every operand, see what registers are allowed. */
1365 for (i = 0; i < noperands; i++)
1367 const char *p = constraints[i];
1368 /* For every alternative, we compute the class of registers allowed
1369 for reloading in CLS, and merge its contents into the reg set
1371 int cls = (int) NO_REGS;
1377 if (c == '\0' || c == ',' || c == '#')
1379 /* End of one alternative - mark the regs in the current
1380 class, and reset the class. */
1381 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1387 } while (c != '\0' && c != ',');
1395 case '=': case '+': case '*': case '%': case '?': case '!':
1396 case '0': case '1': case '2': case '3': case '4': case 'm':
1397 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1398 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1399 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1404 cls = (int) reg_class_subunion[cls]
1405 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1410 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1414 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1415 cls = (int) reg_class_subunion[cls]
1416 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1418 cls = (int) reg_class_subunion[cls]
1419 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1421 p += CONSTRAINT_LEN (c, p);
1424 /* Those of the registers which are clobbered, but allowed by the
1425 constraints, must be usable as reload registers. So clear them
1426 out of the life information. */
1427 AND_HARD_REG_SET (allowed, clobbered);
1428 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1429 if (TEST_HARD_REG_BIT (allowed, i))
1431 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1432 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1439 /* Copy the global variables n_reloads and rld into the corresponding elts
1442 copy_reloads (struct insn_chain *chain)
1444 chain->n_reloads = n_reloads;
1445 chain->rld = obstack_alloc (&reload_obstack,
1446 n_reloads * sizeof (struct reload));
1447 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1448 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1451 /* Walk the chain of insns, and determine for each whether it needs reloads
1452 and/or eliminations. Build the corresponding insns_need_reload list, and
1453 set something_needs_elimination as appropriate. */
1455 calculate_needs_all_insns (int global)
1457 struct insn_chain **pprev_reload = &insns_need_reload;
1458 struct insn_chain *chain, *next = 0;
1460 something_needs_elimination = 0;
1462 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1463 for (chain = reload_insn_chain; chain != 0; chain = next)
1465 rtx insn = chain->insn;
1469 /* Clear out the shortcuts. */
1470 chain->n_reloads = 0;
1471 chain->need_elim = 0;
1472 chain->need_reload = 0;
1473 chain->need_operand_change = 0;
1475 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1476 include REG_LABEL), we need to see what effects this has on the
1477 known offsets at labels. */
1479 if (LABEL_P (insn) || JUMP_P (insn)
1480 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1481 set_label_offsets (insn, insn, 0);
1485 rtx old_body = PATTERN (insn);
1486 int old_code = INSN_CODE (insn);
1487 rtx old_notes = REG_NOTES (insn);
1488 int did_elimination = 0;
1489 int operands_changed = 0;
1490 rtx set = single_set (insn);
1492 /* Skip insns that only set an equivalence. */
1493 if (set && REG_P (SET_DEST (set))
1494 && reg_renumber[REGNO (SET_DEST (set))] < 0
1495 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1496 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1497 && reg_equiv_init[REGNO (SET_DEST (set))])
1500 /* If needed, eliminate any eliminable registers. */
1501 if (num_eliminable || num_eliminable_invariants)
1502 did_elimination = eliminate_regs_in_insn (insn, 0);
1504 /* Analyze the instruction. */
1505 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1506 global, spill_reg_order);
1508 /* If a no-op set needs more than one reload, this is likely
1509 to be something that needs input address reloads. We
1510 can't get rid of this cleanly later, and it is of no use
1511 anyway, so discard it now.
1512 We only do this when expensive_optimizations is enabled,
1513 since this complements reload inheritance / output
1514 reload deletion, and it can make debugging harder. */
1515 if (flag_expensive_optimizations && n_reloads > 1)
1517 rtx set = single_set (insn);
1519 && SET_SRC (set) == SET_DEST (set)
1520 && REG_P (SET_SRC (set))
1521 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1524 /* Delete it from the reload chain. */
1526 chain->prev->next = next;
1528 reload_insn_chain = next;
1530 next->prev = chain->prev;
1531 chain->next = unused_insn_chains;
1532 unused_insn_chains = chain;
1537 update_eliminable_offsets ();
1539 /* Remember for later shortcuts which insns had any reloads or
1540 register eliminations. */
1541 chain->need_elim = did_elimination;
1542 chain->need_reload = n_reloads > 0;
1543 chain->need_operand_change = operands_changed;
1545 /* Discard any register replacements done. */
1546 if (did_elimination)
1548 obstack_free (&reload_obstack, reload_insn_firstobj);
1549 PATTERN (insn) = old_body;
1550 INSN_CODE (insn) = old_code;
1551 REG_NOTES (insn) = old_notes;
1552 something_needs_elimination = 1;
1555 something_needs_operands_changed |= operands_changed;
1559 copy_reloads (chain);
1560 *pprev_reload = chain;
1561 pprev_reload = &chain->next_need_reload;
1568 /* Comparison function for qsort to decide which of two reloads
1569 should be handled first. *P1 and *P2 are the reload numbers. */
1572 reload_reg_class_lower (const void *r1p, const void *r2p)
1574 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1577 /* Consider required reloads before optional ones. */
1578 t = rld[r1].optional - rld[r2].optional;
1582 /* Count all solitary classes before non-solitary ones. */
1583 t = ((reg_class_size[(int) rld[r2].class] == 1)
1584 - (reg_class_size[(int) rld[r1].class] == 1));
1588 /* Aside from solitaires, consider all multi-reg groups first. */
1589 t = rld[r2].nregs - rld[r1].nregs;
1593 /* Consider reloads in order of increasing reg-class number. */
1594 t = (int) rld[r1].class - (int) rld[r2].class;
1598 /* If reloads are equally urgent, sort by reload number,
1599 so that the results of qsort leave nothing to chance. */
1603 /* The cost of spilling each hard reg. */
1604 static int spill_cost[FIRST_PSEUDO_REGISTER];
1606 /* When spilling multiple hard registers, we use SPILL_COST for the first
1607 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1608 only the first hard reg for a multi-reg pseudo. */
1609 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1611 /* Update the spill cost arrays, considering that pseudo REG is live. */
1614 count_pseudo (int reg)
1616 int freq = REG_FREQ (reg);
1617 int r = reg_renumber[reg];
1620 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1621 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1624 SET_REGNO_REG_SET (&pseudos_counted, reg);
1626 gcc_assert (r >= 0);
1628 spill_add_cost[r] += freq;
1630 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1632 spill_cost[r + nregs] += freq;
1635 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1636 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1639 order_regs_for_reload (struct insn_chain *chain)
1642 HARD_REG_SET used_by_pseudos;
1643 HARD_REG_SET used_by_pseudos2;
1644 reg_set_iterator rsi;
1646 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1648 memset (spill_cost, 0, sizeof spill_cost);
1649 memset (spill_add_cost, 0, sizeof spill_add_cost);
1651 /* Count number of uses of each hard reg by pseudo regs allocated to it
1652 and then order them by decreasing use. First exclude hard registers
1653 that are live in or across this insn. */
1655 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1656 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1657 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1658 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1660 /* Now find out which pseudos are allocated to it, and update
1662 CLEAR_REG_SET (&pseudos_counted);
1664 EXECUTE_IF_SET_IN_REG_SET
1665 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1669 EXECUTE_IF_SET_IN_REG_SET
1670 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1674 CLEAR_REG_SET (&pseudos_counted);
1677 /* Vector of reload-numbers showing the order in which the reloads should
1679 static short reload_order[MAX_RELOADS];
1681 /* This is used to keep track of the spill regs used in one insn. */
1682 static HARD_REG_SET used_spill_regs_local;
1684 /* We decided to spill hard register SPILLED, which has a size of
1685 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1686 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1687 update SPILL_COST/SPILL_ADD_COST. */
1690 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1692 int r = reg_renumber[reg];
1693 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1695 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1696 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1699 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1701 spill_add_cost[r] -= REG_FREQ (reg);
1703 spill_cost[r + nregs] -= REG_FREQ (reg);
1706 /* Find reload register to use for reload number ORDER. */
1709 find_reg (struct insn_chain *chain, int order)
1711 int rnum = reload_order[order];
1712 struct reload *rl = rld + rnum;
1713 int best_cost = INT_MAX;
1717 HARD_REG_SET not_usable;
1718 HARD_REG_SET used_by_other_reload;
1719 reg_set_iterator rsi;
1721 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1722 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1723 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1725 CLEAR_HARD_REG_SET (used_by_other_reload);
1726 for (k = 0; k < order; k++)
1728 int other = reload_order[k];
1730 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1731 for (j = 0; j < rld[other].nregs; j++)
1732 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1735 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1737 unsigned int regno = i;
1739 if (! TEST_HARD_REG_BIT (not_usable, regno)
1740 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1741 && HARD_REGNO_MODE_OK (regno, rl->mode))
1743 int this_cost = spill_cost[regno];
1745 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1747 for (j = 1; j < this_nregs; j++)
1749 this_cost += spill_add_cost[regno + j];
1750 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1751 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1756 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1758 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1760 if (this_cost < best_cost
1761 /* Among registers with equal cost, prefer caller-saved ones, or
1762 use REG_ALLOC_ORDER if it is defined. */
1763 || (this_cost == best_cost
1764 #ifdef REG_ALLOC_ORDER
1765 && (inv_reg_alloc_order[regno]
1766 < inv_reg_alloc_order[best_reg])
1768 && call_used_regs[regno]
1769 && ! call_used_regs[best_reg]
1774 best_cost = this_cost;
1782 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1784 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1785 rl->regno = best_reg;
1787 EXECUTE_IF_SET_IN_REG_SET
1788 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1790 count_spilled_pseudo (best_reg, rl->nregs, j);
1793 EXECUTE_IF_SET_IN_REG_SET
1794 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1796 count_spilled_pseudo (best_reg, rl->nregs, j);
1799 for (i = 0; i < rl->nregs; i++)
1801 gcc_assert (spill_cost[best_reg + i] == 0);
1802 gcc_assert (spill_add_cost[best_reg + i] == 0);
1803 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1808 /* Find more reload regs to satisfy the remaining need of an insn, which
1810 Do it by ascending class number, since otherwise a reg
1811 might be spilled for a big class and might fail to count
1812 for a smaller class even though it belongs to that class. */
1815 find_reload_regs (struct insn_chain *chain)
1819 /* In order to be certain of getting the registers we need,
1820 we must sort the reloads into order of increasing register class.
1821 Then our grabbing of reload registers will parallel the process
1822 that provided the reload registers. */
1823 for (i = 0; i < chain->n_reloads; i++)
1825 /* Show whether this reload already has a hard reg. */
1826 if (chain->rld[i].reg_rtx)
1828 int regno = REGNO (chain->rld[i].reg_rtx);
1829 chain->rld[i].regno = regno;
1831 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1834 chain->rld[i].regno = -1;
1835 reload_order[i] = i;
1838 n_reloads = chain->n_reloads;
1839 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1841 CLEAR_HARD_REG_SET (used_spill_regs_local);
1844 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1846 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1848 /* Compute the order of preference for hard registers to spill. */
1850 order_regs_for_reload (chain);
1852 for (i = 0; i < n_reloads; i++)
1854 int r = reload_order[i];
1856 /* Ignore reloads that got marked inoperative. */
1857 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1858 && ! rld[r].optional
1859 && rld[r].regno == -1)
1860 if (! find_reg (chain, i))
1863 fprintf (dump_file, "reload failure for reload %d\n", r);
1864 spill_failure (chain->insn, rld[r].class);
1870 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1871 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1873 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1877 select_reload_regs (void)
1879 struct insn_chain *chain;
1881 /* Try to satisfy the needs for each insn. */
1882 for (chain = insns_need_reload; chain != 0;
1883 chain = chain->next_need_reload)
1884 find_reload_regs (chain);
1887 /* Delete all insns that were inserted by emit_caller_save_insns during
1890 delete_caller_save_insns (void)
1892 struct insn_chain *c = reload_insn_chain;
1896 while (c != 0 && c->is_caller_save_insn)
1898 struct insn_chain *next = c->next;
1901 if (c == reload_insn_chain)
1902 reload_insn_chain = next;
1906 next->prev = c->prev;
1908 c->prev->next = next;
1909 c->next = unused_insn_chains;
1910 unused_insn_chains = c;
1918 /* Handle the failure to find a register to spill.
1919 INSN should be one of the insns which needed this particular spill reg. */
1922 spill_failure (rtx insn, enum reg_class class)
1924 if (asm_noperands (PATTERN (insn)) >= 0)
1925 error_for_asm (insn, "can't find a register in class %qs while "
1926 "reloading %<asm%>",
1927 reg_class_names[class]);
1930 error ("unable to find a register to spill in class %qs",
1931 reg_class_names[class]);
1935 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1936 debug_reload_to_stream (dump_file);
1938 fatal_insn ("this is the insn:", insn);
1942 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1943 data that is dead in INSN. */
1946 delete_dead_insn (rtx insn)
1948 rtx prev = prev_real_insn (insn);
1951 /* If the previous insn sets a register that dies in our insn, delete it
1953 if (prev && GET_CODE (PATTERN (prev)) == SET
1954 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1955 && reg_mentioned_p (prev_dest, PATTERN (insn))
1956 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1957 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1958 delete_dead_insn (prev);
1960 SET_INSN_DELETED (insn);
1963 /* Modify the home of pseudo-reg I.
1964 The new home is present in reg_renumber[I].
1966 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1967 or it may be -1, meaning there is none or it is not relevant.
1968 This is used so that all pseudos spilled from a given hard reg
1969 can share one stack slot. */
1972 alter_reg (int i, int from_reg)
1974 /* When outputting an inline function, this can happen
1975 for a reg that isn't actually used. */
1976 if (regno_reg_rtx[i] == 0)
1979 /* If the reg got changed to a MEM at rtl-generation time,
1981 if (!REG_P (regno_reg_rtx[i]))
1984 /* Modify the reg-rtx to contain the new hard reg
1985 number or else to contain its pseudo reg number. */
1986 REGNO (regno_reg_rtx[i])
1987 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1989 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1990 allocate a stack slot for it. */
1992 if (reg_renumber[i] < 0
1993 && REG_N_REFS (i) > 0
1994 && reg_equiv_constant[i] == 0
1995 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1996 && reg_equiv_memory_loc[i] == 0)
1999 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2000 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2001 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2002 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2003 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2006 /* Each pseudo reg has an inherent size which comes from its own mode,
2007 and a total size which provides room for paradoxical subregs
2008 which refer to the pseudo reg in wider modes.
2010 We can use a slot already allocated if it provides both
2011 enough inherent space and enough total space.
2012 Otherwise, we allocate a new slot, making sure that it has no less
2013 inherent space, and no less total space, then the previous slot. */
2016 /* No known place to spill from => no slot to reuse. */
2017 x = assign_stack_local (mode, total_size,
2018 min_align > inherent_align
2019 || total_size > inherent_size ? -1 : 0);
2020 if (BYTES_BIG_ENDIAN)
2021 /* Cancel the big-endian correction done in assign_stack_local.
2022 Get the address of the beginning of the slot.
2023 This is so we can do a big-endian correction unconditionally
2025 adjust = inherent_size - total_size;
2027 /* Nothing can alias this slot except this pseudo. */
2028 set_mem_alias_set (x, new_alias_set ());
2031 /* Reuse a stack slot if possible. */
2032 else if (spill_stack_slot[from_reg] != 0
2033 && spill_stack_slot_width[from_reg] >= total_size
2034 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2036 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2037 x = spill_stack_slot[from_reg];
2039 /* Allocate a bigger slot. */
2042 /* Compute maximum size needed, both for inherent size
2043 and for total size. */
2046 if (spill_stack_slot[from_reg])
2048 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2050 mode = GET_MODE (spill_stack_slot[from_reg]);
2051 if (spill_stack_slot_width[from_reg] > total_size)
2052 total_size = spill_stack_slot_width[from_reg];
2053 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2054 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2057 /* Make a slot with that size. */
2058 x = assign_stack_local (mode, total_size,
2059 min_align > inherent_align
2060 || total_size > inherent_size ? -1 : 0);
2063 /* All pseudos mapped to this slot can alias each other. */
2064 if (spill_stack_slot[from_reg])
2065 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2067 set_mem_alias_set (x, new_alias_set ());
2069 if (BYTES_BIG_ENDIAN)
2071 /* Cancel the big-endian correction done in assign_stack_local.
2072 Get the address of the beginning of the slot.
2073 This is so we can do a big-endian correction unconditionally
2075 adjust = GET_MODE_SIZE (mode) - total_size;
2078 = adjust_address_nv (x, mode_for_size (total_size
2084 spill_stack_slot[from_reg] = stack_slot;
2085 spill_stack_slot_width[from_reg] = total_size;
2088 /* On a big endian machine, the "address" of the slot
2089 is the address of the low part that fits its inherent mode. */
2090 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2091 adjust += (total_size - inherent_size);
2093 /* If we have any adjustment to make, or if the stack slot is the
2094 wrong mode, make a new stack slot. */
2095 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2097 /* If we have a decl for the original register, set it for the
2098 memory. If this is a shared MEM, make a copy. */
2099 if (REG_EXPR (regno_reg_rtx[i])
2100 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2102 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2104 /* We can do this only for the DECLs home pseudo, not for
2105 any copies of it, since otherwise when the stack slot
2106 is reused, nonoverlapping_memrefs_p might think they
2108 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2110 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2113 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2117 /* Save the stack slot for later. */
2118 reg_equiv_memory_loc[i] = x;
2122 /* Mark the slots in regs_ever_live for the hard regs
2123 used by pseudo-reg number REGNO. */
2126 mark_home_live (int regno)
2130 i = reg_renumber[regno];
2133 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2135 regs_ever_live[i++] = 1;
2138 /* This function handles the tracking of elimination offsets around branches.
2140 X is a piece of RTL being scanned.
2142 INSN is the insn that it came from, if any.
2144 INITIAL_P is nonzero if we are to set the offset to be the initial
2145 offset and zero if we are setting the offset of the label to be the
2149 set_label_offsets (rtx x, rtx insn, int initial_p)
2151 enum rtx_code code = GET_CODE (x);
2154 struct elim_table *p;
2159 if (LABEL_REF_NONLOCAL_P (x))
2164 /* ... fall through ... */
2167 /* If we know nothing about this label, set the desired offsets. Note
2168 that this sets the offset at a label to be the offset before a label
2169 if we don't know anything about the label. This is not correct for
2170 the label after a BARRIER, but is the best guess we can make. If
2171 we guessed wrong, we will suppress an elimination that might have
2172 been possible had we been able to guess correctly. */
2174 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2176 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2177 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2178 = (initial_p ? reg_eliminate[i].initial_offset
2179 : reg_eliminate[i].offset);
2180 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2183 /* Otherwise, if this is the definition of a label and it is
2184 preceded by a BARRIER, set our offsets to the known offset of
2188 && (tem = prev_nonnote_insn (insn)) != 0
2190 set_offsets_for_label (insn);
2192 /* If neither of the above cases is true, compare each offset
2193 with those previously recorded and suppress any eliminations
2194 where the offsets disagree. */
2196 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2197 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2198 != (initial_p ? reg_eliminate[i].initial_offset
2199 : reg_eliminate[i].offset))
2200 reg_eliminate[i].can_eliminate = 0;
2205 set_label_offsets (PATTERN (insn), insn, initial_p);
2207 /* ... fall through ... */
2211 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2212 and hence must have all eliminations at their initial offsets. */
2213 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2214 if (REG_NOTE_KIND (tem) == REG_LABEL)
2215 set_label_offsets (XEXP (tem, 0), insn, 1);
2221 /* Each of the labels in the parallel or address vector must be
2222 at their initial offsets. We want the first field for PARALLEL
2223 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2225 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2226 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2231 /* We only care about setting PC. If the source is not RETURN,
2232 IF_THEN_ELSE, or a label, disable any eliminations not at
2233 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2234 isn't one of those possibilities. For branches to a label,
2235 call ourselves recursively.
2237 Note that this can disable elimination unnecessarily when we have
2238 a non-local goto since it will look like a non-constant jump to
2239 someplace in the current function. This isn't a significant
2240 problem since such jumps will normally be when all elimination
2241 pairs are back to their initial offsets. */
2243 if (SET_DEST (x) != pc_rtx)
2246 switch (GET_CODE (SET_SRC (x)))
2253 set_label_offsets (SET_SRC (x), insn, initial_p);
2257 tem = XEXP (SET_SRC (x), 1);
2258 if (GET_CODE (tem) == LABEL_REF)
2259 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2260 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2263 tem = XEXP (SET_SRC (x), 2);
2264 if (GET_CODE (tem) == LABEL_REF)
2265 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2266 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2274 /* If we reach here, all eliminations must be at their initial
2275 offset because we are doing a jump to a variable address. */
2276 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2277 if (p->offset != p->initial_offset)
2278 p->can_eliminate = 0;
2286 /* Scan X and replace any eliminable registers (such as fp) with a
2287 replacement (such as sp), plus an offset.
2289 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2290 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2291 MEM, we are allowed to replace a sum of a register and the constant zero
2292 with the register, which we cannot do outside a MEM. In addition, we need
2293 to record the fact that a register is referenced outside a MEM.
2295 If INSN is an insn, it is the insn containing X. If we replace a REG
2296 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2297 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2298 the REG is being modified.
2300 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2301 That's used when we eliminate in expressions stored in notes.
2302 This means, do not set ref_outside_mem even if the reference
2305 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2306 replacements done assuming all offsets are at their initial values. If
2307 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2308 encounter, return the actual location so that find_reloads will do
2309 the proper thing. */
2312 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2313 bool may_use_invariant)
2315 enum rtx_code code = GET_CODE (x);
2316 struct elim_table *ep;
2323 if (! current_function_decl)
2345 /* First handle the case where we encounter a bare register that
2346 is eliminable. Replace it with a PLUS. */
2347 if (regno < FIRST_PSEUDO_REGISTER)
2349 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2351 if (ep->from_rtx == x && ep->can_eliminate)
2352 return plus_constant (ep->to_rtx, ep->previous_offset);
2355 else if (reg_renumber && reg_renumber[regno] < 0
2356 && reg_equiv_invariant && reg_equiv_invariant[regno])
2358 if (may_use_invariant)
2359 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2360 mem_mode, insn, true);
2361 /* There exists at least one use of REGNO that cannot be
2362 eliminated. Prevent the defining insn from being deleted. */
2363 reg_equiv_init[regno] = NULL_RTX;
2364 alter_reg (regno, -1);
2368 /* You might think handling MINUS in a manner similar to PLUS is a
2369 good idea. It is not. It has been tried multiple times and every
2370 time the change has had to have been reverted.
2372 Other parts of reload know a PLUS is special (gen_reload for example)
2373 and require special code to handle code a reloaded PLUS operand.
2375 Also consider backends where the flags register is clobbered by a
2376 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2377 lea instruction comes to mind). If we try to reload a MINUS, we
2378 may kill the flags register that was holding a useful value.
2380 So, please before trying to handle MINUS, consider reload as a
2381 whole instead of this little section as well as the backend issues. */
2383 /* If this is the sum of an eliminable register and a constant, rework
2385 if (REG_P (XEXP (x, 0))
2386 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2387 && CONSTANT_P (XEXP (x, 1)))
2389 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2391 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2393 /* The only time we want to replace a PLUS with a REG (this
2394 occurs when the constant operand of the PLUS is the negative
2395 of the offset) is when we are inside a MEM. We won't want
2396 to do so at other times because that would change the
2397 structure of the insn in a way that reload can't handle.
2398 We special-case the commonest situation in
2399 eliminate_regs_in_insn, so just replace a PLUS with a
2400 PLUS here, unless inside a MEM. */
2401 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2402 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2405 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2406 plus_constant (XEXP (x, 1),
2407 ep->previous_offset));
2410 /* If the register is not eliminable, we are done since the other
2411 operand is a constant. */
2415 /* If this is part of an address, we want to bring any constant to the
2416 outermost PLUS. We will do this by doing register replacement in
2417 our operands and seeing if a constant shows up in one of them.
2419 Note that there is no risk of modifying the structure of the insn,
2420 since we only get called for its operands, thus we are either
2421 modifying the address inside a MEM, or something like an address
2422 operand of a load-address insn. */
2425 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2426 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2428 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2430 /* If one side is a PLUS and the other side is a pseudo that
2431 didn't get a hard register but has a reg_equiv_constant,
2432 we must replace the constant here since it may no longer
2433 be in the position of any operand. */
2434 if (GET_CODE (new0) == PLUS && REG_P (new1)
2435 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2436 && reg_renumber[REGNO (new1)] < 0
2437 && reg_equiv_constant != 0
2438 && reg_equiv_constant[REGNO (new1)] != 0)
2439 new1 = reg_equiv_constant[REGNO (new1)];
2440 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2441 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2442 && reg_renumber[REGNO (new0)] < 0
2443 && reg_equiv_constant[REGNO (new0)] != 0)
2444 new0 = reg_equiv_constant[REGNO (new0)];
2446 new = form_sum (new0, new1);
2448 /* As above, if we are not inside a MEM we do not want to
2449 turn a PLUS into something else. We might try to do so here
2450 for an addition of 0 if we aren't optimizing. */
2451 if (! mem_mode && GET_CODE (new) != PLUS)
2452 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2460 /* If this is the product of an eliminable register and a
2461 constant, apply the distribute law and move the constant out
2462 so that we have (plus (mult ..) ..). This is needed in order
2463 to keep load-address insns valid. This case is pathological.
2464 We ignore the possibility of overflow here. */
2465 if (REG_P (XEXP (x, 0))
2466 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2467 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2468 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2470 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2473 /* Refs inside notes don't count for this purpose. */
2474 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2475 || GET_CODE (insn) == INSN_LIST)))
2476 ep->ref_outside_mem = 1;
2479 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2480 ep->previous_offset * INTVAL (XEXP (x, 1)));
2483 /* ... fall through ... */
2487 /* See comments before PLUS about handling MINUS. */
2489 case DIV: case UDIV:
2490 case MOD: case UMOD:
2491 case AND: case IOR: case XOR:
2492 case ROTATERT: case ROTATE:
2493 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2495 case GE: case GT: case GEU: case GTU:
2496 case LE: case LT: case LEU: case LTU:
2498 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2499 rtx new1 = XEXP (x, 1)
2500 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2502 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2503 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2508 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2511 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2512 if (new != XEXP (x, 0))
2514 /* If this is a REG_DEAD note, it is not valid anymore.
2515 Using the eliminated version could result in creating a
2516 REG_DEAD note for the stack or frame pointer. */
2517 if (GET_MODE (x) == REG_DEAD)
2519 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2522 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2526 /* ... fall through ... */
2529 /* Now do eliminations in the rest of the chain. If this was
2530 an EXPR_LIST, this might result in allocating more memory than is
2531 strictly needed, but it simplifies the code. */
2534 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2535 if (new != XEXP (x, 1))
2537 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2545 case STRICT_LOW_PART:
2547 case SIGN_EXTEND: case ZERO_EXTEND:
2548 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2549 case FLOAT: case FIX:
2550 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2559 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2560 if (new != XEXP (x, 0))
2561 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2565 /* Similar to above processing, but preserve SUBREG_BYTE.
2566 Convert (subreg (mem)) to (mem) if not paradoxical.
2567 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2568 pseudo didn't get a hard reg, we must replace this with the
2569 eliminated version of the memory location because push_reload
2570 may do the replacement in certain circumstances. */
2571 if (REG_P (SUBREG_REG (x))
2572 && (GET_MODE_SIZE (GET_MODE (x))
2573 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2574 && reg_equiv_memory_loc != 0
2575 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2577 new = SUBREG_REG (x);
2580 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2582 if (new != SUBREG_REG (x))
2584 int x_size = GET_MODE_SIZE (GET_MODE (x));
2585 int new_size = GET_MODE_SIZE (GET_MODE (new));
2588 && ((x_size < new_size
2589 #ifdef WORD_REGISTER_OPERATIONS
2590 /* On these machines, combine can create rtl of the form
2591 (set (subreg:m1 (reg:m2 R) 0) ...)
2592 where m1 < m2, and expects something interesting to
2593 happen to the entire word. Moreover, it will use the
2594 (reg:m2 R) later, expecting all bits to be preserved.
2595 So if the number of words is the same, preserve the
2596 subreg so that push_reload can see it. */
2597 && ! ((x_size - 1) / UNITS_PER_WORD
2598 == (new_size -1 ) / UNITS_PER_WORD)
2601 || x_size == new_size)
2603 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2605 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2611 /* Our only special processing is to pass the mode of the MEM to our
2612 recursive call and copy the flags. While we are here, handle this
2613 case more efficiently. */
2615 replace_equiv_address_nv (x,
2616 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2620 /* Handle insn_list USE that a call to a pure function may generate. */
2621 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2622 if (new != XEXP (x, 0))
2623 return gen_rtx_USE (GET_MODE (x), new);
2635 /* Process each of our operands recursively. If any have changed, make a
2637 fmt = GET_RTX_FORMAT (code);
2638 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2642 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2643 if (new != XEXP (x, i) && ! copied)
2645 x = shallow_copy_rtx (x);
2650 else if (*fmt == 'E')
2653 for (j = 0; j < XVECLEN (x, i); j++)
2655 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2656 if (new != XVECEXP (x, i, j) && ! copied_vec)
2658 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2662 x = shallow_copy_rtx (x);
2665 XVEC (x, i) = new_v;
2668 XVECEXP (x, i, j) = new;
2677 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2679 return eliminate_regs_1 (x, mem_mode, insn, false);
2682 /* Scan rtx X for modifications of elimination target registers. Update
2683 the table of eliminables to reflect the changed state. MEM_MODE is
2684 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2687 elimination_effects (rtx x, enum machine_mode mem_mode)
2689 enum rtx_code code = GET_CODE (x);
2690 struct elim_table *ep;
2714 /* First handle the case where we encounter a bare register that
2715 is eliminable. Replace it with a PLUS. */
2716 if (regno < FIRST_PSEUDO_REGISTER)
2718 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2720 if (ep->from_rtx == x && ep->can_eliminate)
2723 ep->ref_outside_mem = 1;
2728 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2729 && reg_equiv_constant[regno]
2730 && ! function_invariant_p (reg_equiv_constant[regno]))
2731 elimination_effects (reg_equiv_constant[regno], mem_mode);
2740 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2741 if (ep->to_rtx == XEXP (x, 0))
2743 int size = GET_MODE_SIZE (mem_mode);
2745 /* If more bytes than MEM_MODE are pushed, account for them. */
2746 #ifdef PUSH_ROUNDING
2747 if (ep->to_rtx == stack_pointer_rtx)
2748 size = PUSH_ROUNDING (size);
2750 if (code == PRE_DEC || code == POST_DEC)
2752 else if (code == PRE_INC || code == POST_INC)
2754 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2755 && GET_CODE (XEXP (x, 1)) == PLUS
2756 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2757 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2758 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2761 /* These two aren't unary operators. */
2762 if (code == POST_MODIFY || code == PRE_MODIFY)
2765 /* Fall through to generic unary operation case. */
2766 case STRICT_LOW_PART:
2768 case SIGN_EXTEND: case ZERO_EXTEND:
2769 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2770 case FLOAT: case FIX:
2771 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2780 elimination_effects (XEXP (x, 0), mem_mode);
2784 if (REG_P (SUBREG_REG (x))
2785 && (GET_MODE_SIZE (GET_MODE (x))
2786 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2787 && reg_equiv_memory_loc != 0
2788 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2791 elimination_effects (SUBREG_REG (x), mem_mode);
2795 /* If using a register that is the source of an eliminate we still
2796 think can be performed, note it cannot be performed since we don't
2797 know how this register is used. */
2798 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2799 if (ep->from_rtx == XEXP (x, 0))
2800 ep->can_eliminate = 0;
2802 elimination_effects (XEXP (x, 0), mem_mode);
2806 /* If clobbering a register that is the replacement register for an
2807 elimination we still think can be performed, note that it cannot
2808 be performed. Otherwise, we need not be concerned about it. */
2809 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2810 if (ep->to_rtx == XEXP (x, 0))
2811 ep->can_eliminate = 0;
2813 elimination_effects (XEXP (x, 0), mem_mode);
2817 /* Check for setting a register that we know about. */
2818 if (REG_P (SET_DEST (x)))
2820 /* See if this is setting the replacement register for an
2823 If DEST is the hard frame pointer, we do nothing because we
2824 assume that all assignments to the frame pointer are for
2825 non-local gotos and are being done at a time when they are valid
2826 and do not disturb anything else. Some machines want to
2827 eliminate a fake argument pointer (or even a fake frame pointer)
2828 with either the real frame or the stack pointer. Assignments to
2829 the hard frame pointer must not prevent this elimination. */
2831 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2833 if (ep->to_rtx == SET_DEST (x)
2834 && SET_DEST (x) != hard_frame_pointer_rtx)
2836 /* If it is being incremented, adjust the offset. Otherwise,
2837 this elimination can't be done. */
2838 rtx src = SET_SRC (x);
2840 if (GET_CODE (src) == PLUS
2841 && XEXP (src, 0) == SET_DEST (x)
2842 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2843 ep->offset -= INTVAL (XEXP (src, 1));
2845 ep->can_eliminate = 0;
2849 elimination_effects (SET_DEST (x), 0);
2850 elimination_effects (SET_SRC (x), 0);
2854 /* Our only special processing is to pass the mode of the MEM to our
2856 elimination_effects (XEXP (x, 0), GET_MODE (x));
2863 fmt = GET_RTX_FORMAT (code);
2864 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2867 elimination_effects (XEXP (x, i), mem_mode);
2868 else if (*fmt == 'E')
2869 for (j = 0; j < XVECLEN (x, i); j++)
2870 elimination_effects (XVECEXP (x, i, j), mem_mode);
2874 /* Descend through rtx X and verify that no references to eliminable registers
2875 remain. If any do remain, mark the involved register as not
2879 check_eliminable_occurrences (rtx x)
2888 code = GET_CODE (x);
2890 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2892 struct elim_table *ep;
2894 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2895 if (ep->from_rtx == x)
2896 ep->can_eliminate = 0;
2900 fmt = GET_RTX_FORMAT (code);
2901 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2904 check_eliminable_occurrences (XEXP (x, i));
2905 else if (*fmt == 'E')
2908 for (j = 0; j < XVECLEN (x, i); j++)
2909 check_eliminable_occurrences (XVECEXP (x, i, j));
2914 /* Scan INSN and eliminate all eliminable registers in it.
2916 If REPLACE is nonzero, do the replacement destructively. Also
2917 delete the insn as dead it if it is setting an eliminable register.
2919 If REPLACE is zero, do all our allocations in reload_obstack.
2921 If no eliminations were done and this insn doesn't require any elimination
2922 processing (these are not identical conditions: it might be updating sp,
2923 but not referencing fp; this needs to be seen during reload_as_needed so
2924 that the offset between fp and sp can be taken into consideration), zero
2925 is returned. Otherwise, 1 is returned. */
2928 eliminate_regs_in_insn (rtx insn, int replace)
2930 int icode = recog_memoized (insn);
2931 rtx old_body = PATTERN (insn);
2932 int insn_is_asm = asm_noperands (old_body) >= 0;
2933 rtx old_set = single_set (insn);
2937 rtx substed_operand[MAX_RECOG_OPERANDS];
2938 rtx orig_operand[MAX_RECOG_OPERANDS];
2939 struct elim_table *ep;
2940 rtx plus_src, plus_cst_src;
2942 if (! insn_is_asm && icode < 0)
2944 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2945 || GET_CODE (PATTERN (insn)) == CLOBBER
2946 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2947 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2948 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2952 if (old_set != 0 && REG_P (SET_DEST (old_set))
2953 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2955 /* Check for setting an eliminable register. */
2956 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2957 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2959 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2960 /* If this is setting the frame pointer register to the
2961 hardware frame pointer register and this is an elimination
2962 that will be done (tested above), this insn is really
2963 adjusting the frame pointer downward to compensate for
2964 the adjustment done before a nonlocal goto. */
2965 if (ep->from == FRAME_POINTER_REGNUM
2966 && ep->to == HARD_FRAME_POINTER_REGNUM)
2968 rtx base = SET_SRC (old_set);
2969 rtx base_insn = insn;
2970 HOST_WIDE_INT offset = 0;
2972 while (base != ep->to_rtx)
2974 rtx prev_insn, prev_set;
2976 if (GET_CODE (base) == PLUS
2977 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2979 offset += INTVAL (XEXP (base, 1));
2980 base = XEXP (base, 0);
2982 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2983 && (prev_set = single_set (prev_insn)) != 0
2984 && rtx_equal_p (SET_DEST (prev_set), base))
2986 base = SET_SRC (prev_set);
2987 base_insn = prev_insn;
2993 if (base == ep->to_rtx)
2996 = plus_constant (ep->to_rtx, offset - ep->offset);
2998 new_body = old_body;
3001 new_body = copy_insn (old_body);
3002 if (REG_NOTES (insn))
3003 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3005 PATTERN (insn) = new_body;
3006 old_set = single_set (insn);
3008 /* First see if this insn remains valid when we
3009 make the change. If not, keep the INSN_CODE
3010 the same and let reload fit it up. */
3011 validate_change (insn, &SET_SRC (old_set), src, 1);
3012 validate_change (insn, &SET_DEST (old_set),
3014 if (! apply_change_group ())
3016 SET_SRC (old_set) = src;
3017 SET_DEST (old_set) = ep->to_rtx;
3026 /* In this case this insn isn't serving a useful purpose. We
3027 will delete it in reload_as_needed once we know that this
3028 elimination is, in fact, being done.
3030 If REPLACE isn't set, we can't delete this insn, but needn't
3031 process it since it won't be used unless something changes. */
3034 delete_dead_insn (insn);
3042 /* We allow one special case which happens to work on all machines we
3043 currently support: a single set with the source or a REG_EQUAL
3044 note being a PLUS of an eliminable register and a constant. */
3045 plus_src = plus_cst_src = 0;
3046 if (old_set && REG_P (SET_DEST (old_set)))
3048 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3049 plus_src = SET_SRC (old_set);
3050 /* First see if the source is of the form (plus (...) CST). */
3052 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3053 plus_cst_src = plus_src;
3054 else if (REG_P (SET_SRC (old_set))
3057 /* Otherwise, see if we have a REG_EQUAL note of the form
3058 (plus (...) CST). */
3060 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3062 if (REG_NOTE_KIND (links) == REG_EQUAL
3063 && GET_CODE (XEXP (links, 0)) == PLUS
3064 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3066 plus_cst_src = XEXP (links, 0);
3072 /* Check that the first operand of the PLUS is a hard reg or
3073 the lowpart subreg of one. */
3076 rtx reg = XEXP (plus_cst_src, 0);
3077 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3078 reg = SUBREG_REG (reg);
3080 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3086 rtx reg = XEXP (plus_cst_src, 0);
3087 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3089 if (GET_CODE (reg) == SUBREG)
3090 reg = SUBREG_REG (reg);
3092 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3093 if (ep->from_rtx == reg && ep->can_eliminate)
3095 rtx to_rtx = ep->to_rtx;
3096 offset += ep->offset;
3098 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3099 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3104 /* We assume here that if we need a PARALLEL with
3105 CLOBBERs for this assignment, we can do with the
3106 MATCH_SCRATCHes that add_clobbers allocates.
3107 There's not much we can do if that doesn't work. */
3108 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3112 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3115 rtvec vec = rtvec_alloc (num_clobbers + 1);
3117 vec->elem[0] = PATTERN (insn);
3118 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3119 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3121 gcc_assert (INSN_CODE (insn) >= 0);
3123 /* If we have a nonzero offset, and the source is already
3124 a simple REG, the following transformation would
3125 increase the cost of the insn by replacing a simple REG
3126 with (plus (reg sp) CST). So try only when we already
3127 had a PLUS before. */
3130 new_body = old_body;
3133 new_body = copy_insn (old_body);
3134 if (REG_NOTES (insn))
3135 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3137 PATTERN (insn) = new_body;
3138 old_set = single_set (insn);
3140 XEXP (SET_SRC (old_set), 0) = to_rtx;
3141 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3147 /* This can't have an effect on elimination offsets, so skip right
3153 /* Determine the effects of this insn on elimination offsets. */
3154 elimination_effects (old_body, 0);
3156 /* Eliminate all eliminable registers occurring in operands that
3157 can be handled by reload. */
3158 extract_insn (insn);
3159 for (i = 0; i < recog_data.n_operands; i++)
3161 orig_operand[i] = recog_data.operand[i];
3162 substed_operand[i] = recog_data.operand[i];
3164 /* For an asm statement, every operand is eliminable. */
3165 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3167 bool is_set_src, in_plus;
3169 /* Check for setting a register that we know about. */
3170 if (recog_data.operand_type[i] != OP_IN
3171 && REG_P (orig_operand[i]))
3173 /* If we are assigning to a register that can be eliminated, it
3174 must be as part of a PARALLEL, since the code above handles
3175 single SETs. We must indicate that we can no longer
3176 eliminate this reg. */
3177 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3179 if (ep->from_rtx == orig_operand[i])
3180 ep->can_eliminate = 0;
3183 /* Companion to the above plus substitution, we can allow
3184 invariants as the source of a plain move. */
3186 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3190 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3191 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3195 = eliminate_regs_1 (recog_data.operand[i], 0,
3196 replace ? insn : NULL_RTX,
3197 is_set_src || in_plus);
3198 if (substed_operand[i] != orig_operand[i])
3200 /* Terminate the search in check_eliminable_occurrences at
3202 *recog_data.operand_loc[i] = 0;
3204 /* If an output operand changed from a REG to a MEM and INSN is an
3205 insn, write a CLOBBER insn. */
3206 if (recog_data.operand_type[i] != OP_IN
3207 && REG_P (orig_operand[i])
3208 && MEM_P (substed_operand[i])
3210 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3215 for (i = 0; i < recog_data.n_dups; i++)
3216 *recog_data.dup_loc[i]
3217 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3219 /* If any eliminable remain, they aren't eliminable anymore. */
3220 check_eliminable_occurrences (old_body);
3222 /* Substitute the operands; the new values are in the substed_operand
3224 for (i = 0; i < recog_data.n_operands; i++)
3225 *recog_data.operand_loc[i] = substed_operand[i];
3226 for (i = 0; i < recog_data.n_dups; i++)
3227 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3229 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3230 re-recognize the insn. We do this in case we had a simple addition
3231 but now can do this as a load-address. This saves an insn in this
3233 If re-recognition fails, the old insn code number will still be used,
3234 and some register operands may have changed into PLUS expressions.
3235 These will be handled by find_reloads by loading them into a register
3240 /* If we aren't replacing things permanently and we changed something,
3241 make another copy to ensure that all the RTL is new. Otherwise
3242 things can go wrong if find_reload swaps commutative operands
3243 and one is inside RTL that has been copied while the other is not. */
3244 new_body = old_body;
3247 new_body = copy_insn (old_body);
3248 if (REG_NOTES (insn))
3249 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3251 PATTERN (insn) = new_body;
3253 /* If we had a move insn but now we don't, rerecognize it. This will
3254 cause spurious re-recognition if the old move had a PARALLEL since
3255 the new one still will, but we can't call single_set without
3256 having put NEW_BODY into the insn and the re-recognition won't
3257 hurt in this rare case. */
3258 /* ??? Why this huge if statement - why don't we just rerecognize the
3262 && ((REG_P (SET_SRC (old_set))
3263 && (GET_CODE (new_body) != SET
3264 || !REG_P (SET_SRC (new_body))))
3265 /* If this was a load from or store to memory, compare
3266 the MEM in recog_data.operand to the one in the insn.
3267 If they are not equal, then rerecognize the insn. */
3269 && ((MEM_P (SET_SRC (old_set))
3270 && SET_SRC (old_set) != recog_data.operand[1])
3271 || (MEM_P (SET_DEST (old_set))
3272 && SET_DEST (old_set) != recog_data.operand[0])))
3273 /* If this was an add insn before, rerecognize. */
3274 || GET_CODE (SET_SRC (old_set)) == PLUS))
3276 int new_icode = recog (PATTERN (insn), insn, 0);
3278 INSN_CODE (insn) = new_icode;
3282 /* Restore the old body. If there were any changes to it, we made a copy
3283 of it while the changes were still in place, so we'll correctly return
3284 a modified insn below. */
3287 /* Restore the old body. */
3288 for (i = 0; i < recog_data.n_operands; i++)
3289 *recog_data.operand_loc[i] = orig_operand[i];
3290 for (i = 0; i < recog_data.n_dups; i++)
3291 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3294 /* Update all elimination pairs to reflect the status after the current
3295 insn. The changes we make were determined by the earlier call to
3296 elimination_effects.
3298 We also detect cases where register elimination cannot be done,
3299 namely, if a register would be both changed and referenced outside a MEM
3300 in the resulting insn since such an insn is often undefined and, even if
3301 not, we cannot know what meaning will be given to it. Note that it is
3302 valid to have a register used in an address in an insn that changes it
3303 (presumably with a pre- or post-increment or decrement).
3305 If anything changes, return nonzero. */
3307 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3309 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3310 ep->can_eliminate = 0;
3312 ep->ref_outside_mem = 0;
3314 if (ep->previous_offset != ep->offset)
3319 /* If we changed something, perform elimination in REG_NOTES. This is
3320 needed even when REPLACE is zero because a REG_DEAD note might refer
3321 to a register that we eliminate and could cause a different number
3322 of spill registers to be needed in the final reload pass than in
3324 if (val && REG_NOTES (insn) != 0)
3326 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3331 /* Loop through all elimination pairs.
3332 Recalculate the number not at initial offset.
3334 Compute the maximum offset (minimum offset if the stack does not
3335 grow downward) for each elimination pair. */
3338 update_eliminable_offsets (void)
3340 struct elim_table *ep;
3342 num_not_at_initial_offset = 0;
3343 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3345 ep->previous_offset = ep->offset;
3346 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3347 num_not_at_initial_offset++;
3351 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3352 replacement we currently believe is valid, mark it as not eliminable if X
3353 modifies DEST in any way other than by adding a constant integer to it.
3355 If DEST is the frame pointer, we do nothing because we assume that
3356 all assignments to the hard frame pointer are nonlocal gotos and are being
3357 done at a time when they are valid and do not disturb anything else.
3358 Some machines want to eliminate a fake argument pointer with either the
3359 frame or stack pointer. Assignments to the hard frame pointer must not
3360 prevent this elimination.
3362 Called via note_stores from reload before starting its passes to scan
3363 the insns of the function. */
3366 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3370 /* A SUBREG of a hard register here is just changing its mode. We should
3371 not see a SUBREG of an eliminable hard register, but check just in
3373 if (GET_CODE (dest) == SUBREG)
3374 dest = SUBREG_REG (dest);
3376 if (dest == hard_frame_pointer_rtx)
3379 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3380 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3381 && (GET_CODE (x) != SET
3382 || GET_CODE (SET_SRC (x)) != PLUS
3383 || XEXP (SET_SRC (x), 0) != dest
3384 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3386 reg_eliminate[i].can_eliminate_previous
3387 = reg_eliminate[i].can_eliminate = 0;
3392 /* Verify that the initial elimination offsets did not change since the
3393 last call to set_initial_elim_offsets. This is used to catch cases
3394 where something illegal happened during reload_as_needed that could
3395 cause incorrect code to be generated if we did not check for it. */
3398 verify_initial_elim_offsets (void)
3402 if (!num_eliminable)
3405 #ifdef ELIMINABLE_REGS
3407 struct elim_table *ep;
3409 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3411 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3412 if (t != ep->initial_offset)
3417 INITIAL_FRAME_POINTER_OFFSET (t);
3418 if (t != reg_eliminate[0].initial_offset)
3425 /* Reset all offsets on eliminable registers to their initial values. */
3428 set_initial_elim_offsets (void)
3430 struct elim_table *ep = reg_eliminate;
3432 #ifdef ELIMINABLE_REGS
3433 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3435 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3436 ep->previous_offset = ep->offset = ep->initial_offset;
3439 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3440 ep->previous_offset = ep->offset = ep->initial_offset;
3443 num_not_at_initial_offset = 0;
3446 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3449 set_initial_eh_label_offset (rtx label)
3451 set_label_offsets (label, NULL_RTX, 1);
3454 /* Initialize the known label offsets.
3455 Set a known offset for each forced label to be at the initial offset
3456 of each elimination. We do this because we assume that all
3457 computed jumps occur from a location where each elimination is
3458 at its initial offset.
3459 For all other labels, show that we don't know the offsets. */
3462 set_initial_label_offsets (void)
3465 memset (offsets_known_at, 0, num_labels);
3467 for (x = forced_labels; x; x = XEXP (x, 1))
3469 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3471 for_each_eh_label (set_initial_eh_label_offset);
3474 /* Set all elimination offsets to the known values for the code label given
3478 set_offsets_for_label (rtx insn)
3481 int label_nr = CODE_LABEL_NUMBER (insn);
3482 struct elim_table *ep;
3484 num_not_at_initial_offset = 0;
3485 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3487 ep->offset = ep->previous_offset
3488 = offsets_at[label_nr - first_label_num][i];
3489 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3490 num_not_at_initial_offset++;
3494 /* See if anything that happened changes which eliminations are valid.
3495 For example, on the SPARC, whether or not the frame pointer can
3496 be eliminated can depend on what registers have been used. We need
3497 not check some conditions again (such as flag_omit_frame_pointer)
3498 since they can't have changed. */
3501 update_eliminables (HARD_REG_SET *pset)
3503 int previous_frame_pointer_needed = frame_pointer_needed;
3504 struct elim_table *ep;
3506 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3507 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3508 #ifdef ELIMINABLE_REGS
3509 || ! CAN_ELIMINATE (ep->from, ep->to)
3512 ep->can_eliminate = 0;
3514 /* Look for the case where we have discovered that we can't replace
3515 register A with register B and that means that we will now be
3516 trying to replace register A with register C. This means we can
3517 no longer replace register C with register B and we need to disable
3518 such an elimination, if it exists. This occurs often with A == ap,
3519 B == sp, and C == fp. */
3521 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3523 struct elim_table *op;
3526 if (! ep->can_eliminate && ep->can_eliminate_previous)
3528 /* Find the current elimination for ep->from, if there is a
3530 for (op = reg_eliminate;
3531 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3532 if (op->from == ep->from && op->can_eliminate)
3538 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3540 for (op = reg_eliminate;
3541 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3542 if (op->from == new_to && op->to == ep->to)
3543 op->can_eliminate = 0;
3547 /* See if any registers that we thought we could eliminate the previous
3548 time are no longer eliminable. If so, something has changed and we
3549 must spill the register. Also, recompute the number of eliminable
3550 registers and see if the frame pointer is needed; it is if there is
3551 no elimination of the frame pointer that we can perform. */
3553 frame_pointer_needed = 1;
3554 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3556 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3557 && ep->to != HARD_FRAME_POINTER_REGNUM)
3558 frame_pointer_needed = 0;
3560 if (! ep->can_eliminate && ep->can_eliminate_previous)
3562 ep->can_eliminate_previous = 0;
3563 SET_HARD_REG_BIT (*pset, ep->from);
3568 /* If we didn't need a frame pointer last time, but we do now, spill
3569 the hard frame pointer. */
3570 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3571 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3574 /* Initialize the table of registers to eliminate. */
3577 init_elim_table (void)
3579 struct elim_table *ep;
3580 #ifdef ELIMINABLE_REGS
3581 const struct elim_table_1 *ep1;
3585 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3587 /* Does this function require a frame pointer? */
3589 frame_pointer_needed = (! flag_omit_frame_pointer
3590 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3591 and restore sp for alloca. So we can't eliminate
3592 the frame pointer in that case. At some point,
3593 we should improve this by emitting the
3594 sp-adjusting insns for this case. */
3595 || (current_function_calls_alloca
3596 && EXIT_IGNORE_STACK)
3597 || current_function_accesses_prior_frames
3598 || FRAME_POINTER_REQUIRED);
3602 #ifdef ELIMINABLE_REGS
3603 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3604 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3606 ep->from = ep1->from;
3608 ep->can_eliminate = ep->can_eliminate_previous
3609 = (CAN_ELIMINATE (ep->from, ep->to)
3610 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3613 reg_eliminate[0].from = reg_eliminate_1[0].from;
3614 reg_eliminate[0].to = reg_eliminate_1[0].to;
3615 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3616 = ! frame_pointer_needed;
3619 /* Count the number of eliminable registers and build the FROM and TO
3620 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3621 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3622 We depend on this. */
3623 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3625 num_eliminable += ep->can_eliminate;
3626 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3627 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3631 /* Kick all pseudos out of hard register REGNO.
3633 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3634 because we found we can't eliminate some register. In the case, no pseudos
3635 are allowed to be in the register, even if they are only in a block that
3636 doesn't require spill registers, unlike the case when we are spilling this
3637 hard reg to produce another spill register.
3639 Return nonzero if any pseudos needed to be kicked out. */
3642 spill_hard_reg (unsigned int regno, int cant_eliminate)
3648 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3649 regs_ever_live[regno] = 1;
3652 /* Spill every pseudo reg that was allocated to this reg
3653 or to something that overlaps this reg. */
3655 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3656 if (reg_renumber[i] >= 0
3657 && (unsigned int) reg_renumber[i] <= regno
3658 && ((unsigned int) reg_renumber[i]
3659 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3660 [PSEUDO_REGNO_MODE (i)]
3662 SET_REGNO_REG_SET (&spilled_pseudos, i);
3665 /* After find_reload_regs has been run for all insn that need reloads,
3666 and/or spill_hard_regs was called, this function is used to actually
3667 spill pseudo registers and try to reallocate them. It also sets up the
3668 spill_regs array for use by choose_reload_regs. */
3671 finish_spills (int global)
3673 struct insn_chain *chain;
3674 int something_changed = 0;
3676 reg_set_iterator rsi;
3678 /* Build the spill_regs array for the function. */
3679 /* If there are some registers still to eliminate and one of the spill regs
3680 wasn't ever used before, additional stack space may have to be
3681 allocated to store this register. Thus, we may have changed the offset
3682 between the stack and frame pointers, so mark that something has changed.
3684 One might think that we need only set VAL to 1 if this is a call-used
3685 register. However, the set of registers that must be saved by the
3686 prologue is not identical to the call-used set. For example, the
3687 register used by the call insn for the return PC is a call-used register,
3688 but must be saved by the prologue. */
3691 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3692 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3694 spill_reg_order[i] = n_spills;
3695 spill_regs[n_spills++] = i;
3696 if (num_eliminable && ! regs_ever_live[i])
3697 something_changed = 1;
3698 regs_ever_live[i] = 1;
3701 spill_reg_order[i] = -1;
3703 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3705 /* Record the current hard register the pseudo is allocated to in
3706 pseudo_previous_regs so we avoid reallocating it to the same
3707 hard reg in a later pass. */
3708 gcc_assert (reg_renumber[i] >= 0);
3710 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3711 /* Mark it as no longer having a hard register home. */
3712 reg_renumber[i] = -1;
3713 /* We will need to scan everything again. */
3714 something_changed = 1;
3717 /* Retry global register allocation if possible. */
3720 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3721 /* For every insn that needs reloads, set the registers used as spill
3722 regs in pseudo_forbidden_regs for every pseudo live across the
3724 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3726 EXECUTE_IF_SET_IN_REG_SET
3727 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3729 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3730 chain->used_spill_regs);
3732 EXECUTE_IF_SET_IN_REG_SET
3733 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3735 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3736 chain->used_spill_regs);
3740 /* Retry allocating the spilled pseudos. For each reg, merge the
3741 various reg sets that indicate which hard regs can't be used,
3742 and call retry_global_alloc.
3743 We change spill_pseudos here to only contain pseudos that did not
3744 get a new hard register. */
3745 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3746 if (reg_old_renumber[i] != reg_renumber[i])
3748 HARD_REG_SET forbidden;
3749 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3750 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3751 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3752 retry_global_alloc (i, forbidden);
3753 if (reg_renumber[i] >= 0)
3754 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3758 /* Fix up the register information in the insn chain.
3759 This involves deleting those of the spilled pseudos which did not get
3760 a new hard register home from the live_{before,after} sets. */
3761 for (chain = reload_insn_chain; chain; chain = chain->next)
3763 HARD_REG_SET used_by_pseudos;
3764 HARD_REG_SET used_by_pseudos2;
3766 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3767 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3769 /* Mark any unallocated hard regs as available for spills. That
3770 makes inheritance work somewhat better. */
3771 if (chain->need_reload)
3773 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3774 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3775 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3777 /* Save the old value for the sanity test below. */
3778 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3780 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3781 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3782 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3783 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3785 /* Make sure we only enlarge the set. */
3786 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3792 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3793 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3795 int regno = reg_renumber[i];
3796 if (reg_old_renumber[i] == regno)
3799 alter_reg (i, reg_old_renumber[i]);
3800 reg_old_renumber[i] = regno;
3804 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3806 fprintf (dump_file, " Register %d now in %d.\n\n",
3807 i, reg_renumber[i]);
3811 return something_changed;
3814 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3817 scan_paradoxical_subregs (rtx x)
3821 enum rtx_code code = GET_CODE (x);
3831 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3839 if (REG_P (SUBREG_REG (x))
3840 && (GET_MODE_SIZE (GET_MODE (x))
3841 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3842 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3843 = GET_MODE_SIZE (GET_MODE (x));
3850 fmt = GET_RTX_FORMAT (code);
3851 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3854 scan_paradoxical_subregs (XEXP (x, i));
3855 else if (fmt[i] == 'E')
3858 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3859 scan_paradoxical_subregs (XVECEXP (x, i, j));
3864 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3865 examine all of the reload insns between PREV and NEXT exclusive, and
3866 annotate all that may trap. */
3869 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3871 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3872 unsigned int trap_count;
3878 if (may_trap_p (PATTERN (insn)))
3882 remove_note (insn, note);
3886 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3887 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3891 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3895 /* Reload pseudo-registers into hard regs around each insn as needed.
3896 Additional register load insns are output before the insn that needs it
3897 and perhaps store insns after insns that modify the reloaded pseudo reg.
3899 reg_last_reload_reg and reg_reloaded_contents keep track of
3900 which registers are already available in reload registers.
3901 We update these for the reloads that we perform,
3902 as the insns are scanned. */
3905 reload_as_needed (int live_known)
3907 struct insn_chain *chain;
3908 #if defined (AUTO_INC_DEC)
3913 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3914 memset (spill_reg_store, 0, sizeof spill_reg_store);
3915 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3916 INIT_REG_SET (®_has_output_reload);
3917 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3918 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3920 set_initial_elim_offsets ();
3922 for (chain = reload_insn_chain; chain; chain = chain->next)
3925 rtx insn = chain->insn;
3926 rtx old_next = NEXT_INSN (insn);
3928 /* If we pass a label, copy the offsets from the label information
3929 into the current offsets of each elimination. */
3931 set_offsets_for_label (insn);
3933 else if (INSN_P (insn))
3935 regset_head regs_to_forget;
3936 INIT_REG_SET (®s_to_forget);
3937 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
3939 /* If this is a USE and CLOBBER of a MEM, ensure that any
3940 references to eliminable registers have been removed. */
3942 if ((GET_CODE (PATTERN (insn)) == USE
3943 || GET_CODE (PATTERN (insn)) == CLOBBER)
3944 && MEM_P (XEXP (PATTERN (insn), 0)))
3945 XEXP (XEXP (PATTERN (insn), 0), 0)
3946 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3947 GET_MODE (XEXP (PATTERN (insn), 0)),
3950 /* If we need to do register elimination processing, do so.
3951 This might delete the insn, in which case we are done. */
3952 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3954 eliminate_regs_in_insn (insn, 1);
3957 update_eliminable_offsets ();
3958 CLEAR_REG_SET (®s_to_forget);
3963 /* If need_elim is nonzero but need_reload is zero, one might think
3964 that we could simply set n_reloads to 0. However, find_reloads
3965 could have done some manipulation of the insn (such as swapping
3966 commutative operands), and these manipulations are lost during
3967 the first pass for every insn that needs register elimination.
3968 So the actions of find_reloads must be redone here. */
3970 if (! chain->need_elim && ! chain->need_reload
3971 && ! chain->need_operand_change)
3973 /* First find the pseudo regs that must be reloaded for this insn.
3974 This info is returned in the tables reload_... (see reload.h).
3975 Also modify the body of INSN by substituting RELOAD
3976 rtx's for those pseudo regs. */
3979 CLEAR_REG_SET (®_has_output_reload);
3980 CLEAR_HARD_REG_SET (reg_is_output_reload);
3982 find_reloads (insn, 1, spill_indirect_levels, live_known,
3988 rtx next = NEXT_INSN (insn);
3991 prev = PREV_INSN (insn);
3993 /* Now compute which reload regs to reload them into. Perhaps
3994 reusing reload regs from previous insns, or else output
3995 load insns to reload them. Maybe output store insns too.
3996 Record the choices of reload reg in reload_reg_rtx. */
3997 choose_reload_regs (chain);
3999 /* Merge any reloads that we didn't combine for fear of
4000 increasing the number of spill registers needed but now
4001 discover can be safely merged. */
4002 if (SMALL_REGISTER_CLASSES)
4003 merge_assigned_reloads (insn);
4005 /* Generate the insns to reload operands into or out of
4006 their reload regs. */
4007 emit_reload_insns (chain);
4009 /* Substitute the chosen reload regs from reload_reg_rtx
4010 into the insn's body (or perhaps into the bodies of other
4011 load and store insn that we just made for reloading
4012 and that we moved the structure into). */
4013 subst_reloads (insn);
4015 /* Adjust the exception region notes for loads and stores. */
4016 if (flag_non_call_exceptions && !CALL_P (insn))
4017 fixup_eh_region_note (insn, prev, next);
4019 /* If this was an ASM, make sure that all the reload insns
4020 we have generated are valid. If not, give an error
4022 if (asm_noperands (PATTERN (insn)) >= 0)
4023 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4024 if (p != insn && INSN_P (p)
4025 && GET_CODE (PATTERN (p)) != USE
4026 && (recog_memoized (p) < 0
4027 || (extract_insn (p), ! constrain_operands (1))))
4029 error_for_asm (insn,
4030 "%<asm%> operand requires "
4031 "impossible reload");
4036 if (num_eliminable && chain->need_elim)
4037 update_eliminable_offsets ();
4039 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4040 is no longer validly lying around to save a future reload.
4041 Note that this does not detect pseudos that were reloaded
4042 for this insn in order to be stored in
4043 (obeying register constraints). That is correct; such reload
4044 registers ARE still valid. */
4045 forget_marked_reloads (®s_to_forget);
4046 CLEAR_REG_SET (®s_to_forget);
4048 /* There may have been CLOBBER insns placed after INSN. So scan
4049 between INSN and NEXT and use them to forget old reloads. */
4050 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4051 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4052 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4055 /* Likewise for regs altered by auto-increment in this insn.
4056 REG_INC notes have been changed by reloading:
4057 find_reloads_address_1 records substitutions for them,
4058 which have been performed by subst_reloads above. */
4059 for (i = n_reloads - 1; i >= 0; i--)
4061 rtx in_reg = rld[i].in_reg;
4064 enum rtx_code code = GET_CODE (in_reg);
4065 /* PRE_INC / PRE_DEC will have the reload register ending up
4066 with the same value as the stack slot, but that doesn't
4067 hold true for POST_INC / POST_DEC. Either we have to
4068 convert the memory access to a true POST_INC / POST_DEC,
4069 or we can't use the reload register for inheritance. */
4070 if ((code == POST_INC || code == POST_DEC)
4071 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4072 REGNO (rld[i].reg_rtx))
4073 /* Make sure it is the inc/dec pseudo, and not
4074 some other (e.g. output operand) pseudo. */
4075 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4076 == REGNO (XEXP (in_reg, 0))))
4079 rtx reload_reg = rld[i].reg_rtx;
4080 enum machine_mode mode = GET_MODE (reload_reg);
4084 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4086 /* We really want to ignore REG_INC notes here, so
4087 use PATTERN (p) as argument to reg_set_p . */
4088 if (reg_set_p (reload_reg, PATTERN (p)))
4090 n = count_occurrences (PATTERN (p), reload_reg, 0);
4095 n = validate_replace_rtx (reload_reg,
4096 gen_rtx_fmt_e (code,
4101 /* We must also verify that the constraints
4102 are met after the replacement. */
4105 n = constrain_operands (1);
4109 /* If the constraints were not met, then
4110 undo the replacement. */
4113 validate_replace_rtx (gen_rtx_fmt_e (code,
4126 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4128 /* Mark this as having an output reload so that the
4129 REG_INC processing code below won't invalidate
4130 the reload for inheritance. */
4131 SET_HARD_REG_BIT (reg_is_output_reload,
4132 REGNO (reload_reg));
4133 SET_REGNO_REG_SET (®_has_output_reload,
4134 REGNO (XEXP (in_reg, 0)));
4137 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4140 else if ((code == PRE_INC || code == PRE_DEC)
4141 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4142 REGNO (rld[i].reg_rtx))
4143 /* Make sure it is the inc/dec pseudo, and not
4144 some other (e.g. output operand) pseudo. */
4145 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4146 == REGNO (XEXP (in_reg, 0))))
4148 SET_HARD_REG_BIT (reg_is_output_reload,
4149 REGNO (rld[i].reg_rtx));
4150 SET_REGNO_REG_SET (®_has_output_reload,
4151 REGNO (XEXP (in_reg, 0)));
4155 /* If a pseudo that got a hard register is auto-incremented,
4156 we must purge records of copying it into pseudos without
4158 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4159 if (REG_NOTE_KIND (x) == REG_INC)
4161 /* See if this pseudo reg was reloaded in this insn.
4162 If so, its last-reload info is still valid
4163 because it is based on this insn's reload. */
4164 for (i = 0; i < n_reloads; i++)
4165 if (rld[i].out == XEXP (x, 0))
4169 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4173 /* A reload reg's contents are unknown after a label. */
4175 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4177 /* Don't assume a reload reg is still good after a call insn
4178 if it is a call-used reg, or if it contains a value that will
4179 be partially clobbered by the call. */
4180 else if (CALL_P (insn))
4182 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4183 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4188 free (reg_last_reload_reg);
4189 CLEAR_REG_SET (®_has_output_reload);
4192 /* Discard all record of any value reloaded from X,
4193 or reloaded in X from someplace else;
4194 unless X is an output reload reg of the current insn.
4196 X may be a hard reg (the reload reg)
4197 or it may be a pseudo reg that was reloaded from.
4199 When DATA is non-NULL just mark the registers in regset
4200 to be forgotten later. */
4203 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4208 regset regs = (regset) data;
4210 /* note_stores does give us subregs of hard regs,
4211 subreg_regno_offset requires a hard reg. */
4212 while (GET_CODE (x) == SUBREG)
4214 /* We ignore the subreg offset when calculating the regno,
4215 because we are using the entire underlying hard register
4225 if (regno >= FIRST_PSEUDO_REGISTER)
4231 nr = hard_regno_nregs[regno][GET_MODE (x)];
4232 /* Storing into a spilled-reg invalidates its contents.
4233 This can happen if a block-local pseudo is allocated to that reg
4234 and it wasn't spilled because this block's total need is 0.
4235 Then some insn might have an optional reload and use this reg. */
4237 for (i = 0; i < nr; i++)
4238 /* But don't do this if the reg actually serves as an output
4239 reload reg in the current instruction. */
4241 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4243 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4244 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4245 spill_reg_store[regno + i] = 0;
4251 SET_REGNO_REG_SET (regs, regno + nr);
4254 /* Since value of X has changed,
4255 forget any value previously copied from it. */
4258 /* But don't forget a copy if this is the output reload
4259 that establishes the copy's validity. */
4261 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4262 reg_last_reload_reg[regno + nr] = 0;
4266 /* Forget the reloads marked in regset by previous function. */
4268 forget_marked_reloads (regset regs)
4271 reg_set_iterator rsi;
4272 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4274 if (reg < FIRST_PSEUDO_REGISTER
4275 /* But don't do this if the reg actually serves as an output
4276 reload reg in the current instruction. */
4278 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4280 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4281 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4282 spill_reg_store[reg] = 0;
4285 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4286 reg_last_reload_reg[reg] = 0;
4290 /* The following HARD_REG_SETs indicate when each hard register is
4291 used for a reload of various parts of the current insn. */
4293 /* If reg is unavailable for all reloads. */
4294 static HARD_REG_SET reload_reg_unavailable;
4295 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4296 static HARD_REG_SET reload_reg_used;
4297 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4298 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4299 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4300 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4301 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4302 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4303 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4304 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4305 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4306 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4307 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4308 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4309 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4310 static HARD_REG_SET reload_reg_used_in_op_addr;
4311 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4312 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4313 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4314 static HARD_REG_SET reload_reg_used_in_insn;
4315 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4316 static HARD_REG_SET reload_reg_used_in_other_addr;
4318 /* If reg is in use as a reload reg for any sort of reload. */
4319 static HARD_REG_SET reload_reg_used_at_all;
4321 /* If reg is use as an inherited reload. We just mark the first register
4323 static HARD_REG_SET reload_reg_used_for_inherit;
4325 /* Records which hard regs are used in any way, either as explicit use or
4326 by being allocated to a pseudo during any point of the current insn. */
4327 static HARD_REG_SET reg_used_in_insn;
4329 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4330 TYPE. MODE is used to indicate how many consecutive regs are
4334 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4335 enum machine_mode mode)
4337 unsigned int nregs = hard_regno_nregs[regno][mode];
4340 for (i = regno; i < nregs + regno; i++)
4345 SET_HARD_REG_BIT (reload_reg_used, i);
4348 case RELOAD_FOR_INPUT_ADDRESS:
4349 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4352 case RELOAD_FOR_INPADDR_ADDRESS:
4353 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4356 case RELOAD_FOR_OUTPUT_ADDRESS:
4357 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4360 case RELOAD_FOR_OUTADDR_ADDRESS:
4361 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4364 case RELOAD_FOR_OPERAND_ADDRESS:
4365 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4368 case RELOAD_FOR_OPADDR_ADDR:
4369 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4372 case RELOAD_FOR_OTHER_ADDRESS:
4373 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4376 case RELOAD_FOR_INPUT:
4377 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4380 case RELOAD_FOR_OUTPUT:
4381 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4384 case RELOAD_FOR_INSN:
4385 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4389 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4393 /* Similarly, but show REGNO is no longer in use for a reload. */
4396 clear_reload_reg_in_use (unsigned int regno, int opnum,
4397 enum reload_type type, enum machine_mode mode)
4399 unsigned int nregs = hard_regno_nregs[regno][mode];
4400 unsigned int start_regno, end_regno, r;
4402 /* A complication is that for some reload types, inheritance might
4403 allow multiple reloads of the same types to share a reload register.
4404 We set check_opnum if we have to check only reloads with the same
4405 operand number, and check_any if we have to check all reloads. */
4406 int check_opnum = 0;
4408 HARD_REG_SET *used_in_set;
4413 used_in_set = &reload_reg_used;
4416 case RELOAD_FOR_INPUT_ADDRESS:
4417 used_in_set = &reload_reg_used_in_input_addr[opnum];
4420 case RELOAD_FOR_INPADDR_ADDRESS:
4422 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4425 case RELOAD_FOR_OUTPUT_ADDRESS:
4426 used_in_set = &reload_reg_used_in_output_addr[opnum];
4429 case RELOAD_FOR_OUTADDR_ADDRESS:
4431 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4434 case RELOAD_FOR_OPERAND_ADDRESS:
4435 used_in_set = &reload_reg_used_in_op_addr;
4438 case RELOAD_FOR_OPADDR_ADDR:
4440 used_in_set = &reload_reg_used_in_op_addr_reload;
4443 case RELOAD_FOR_OTHER_ADDRESS:
4444 used_in_set = &reload_reg_used_in_other_addr;
4448 case RELOAD_FOR_INPUT:
4449 used_in_set = &reload_reg_used_in_input[opnum];
4452 case RELOAD_FOR_OUTPUT:
4453 used_in_set = &reload_reg_used_in_output[opnum];
4456 case RELOAD_FOR_INSN:
4457 used_in_set = &reload_reg_used_in_insn;
4462 /* We resolve conflicts with remaining reloads of the same type by
4463 excluding the intervals of reload registers by them from the
4464 interval of freed reload registers. Since we only keep track of
4465 one set of interval bounds, we might have to exclude somewhat
4466 more than what would be necessary if we used a HARD_REG_SET here.
4467 But this should only happen very infrequently, so there should
4468 be no reason to worry about it. */
4470 start_regno = regno;
4471 end_regno = regno + nregs;
4472 if (check_opnum || check_any)
4474 for (i = n_reloads - 1; i >= 0; i--)
4476 if (rld[i].when_needed == type
4477 && (check_any || rld[i].opnum == opnum)
4480 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4481 unsigned int conflict_end
4483 + hard_regno_nregs[conflict_start][rld[i].mode]);
4485 /* If there is an overlap with the first to-be-freed register,
4486 adjust the interval start. */
4487 if (conflict_start <= start_regno && conflict_end > start_regno)
4488 start_regno = conflict_end;
4489 /* Otherwise, if there is a conflict with one of the other
4490 to-be-freed registers, adjust the interval end. */
4491 if (conflict_start > start_regno && conflict_start < end_regno)
4492 end_regno = conflict_start;
4497 for (r = start_regno; r < end_regno; r++)
4498 CLEAR_HARD_REG_BIT (*used_in_set, r);
4501 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4502 specified by OPNUM and TYPE. */
4505 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4509 /* In use for a RELOAD_OTHER means it's not available for anything. */
4510 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4511 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4517 /* In use for anything means we can't use it for RELOAD_OTHER. */
4518 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4519 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4520 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4521 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4524 for (i = 0; i < reload_n_operands; i++)
4525 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4529 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4535 case RELOAD_FOR_INPUT:
4536 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4537 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4540 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4543 /* If it is used for some other input, can't use it. */
4544 for (i = 0; i < reload_n_operands; i++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4548 /* If it is used in a later operand's address, can't use it. */
4549 for (i = opnum + 1; i < reload_n_operands; i++)
4550 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4551 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4556 case RELOAD_FOR_INPUT_ADDRESS:
4557 /* Can't use a register if it is used for an input address for this
4558 operand or used as an input in an earlier one. */
4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4560 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4563 for (i = 0; i < opnum; i++)
4564 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4569 case RELOAD_FOR_INPADDR_ADDRESS:
4570 /* Can't use a register if it is used for an input address
4571 for this operand or used as an input in an earlier
4573 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4576 for (i = 0; i < opnum; i++)
4577 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4582 case RELOAD_FOR_OUTPUT_ADDRESS:
4583 /* Can't use a register if it is used for an output address for this
4584 operand or used as an output in this or a later operand. Note
4585 that multiple output operands are emitted in reverse order, so
4586 the conflicting ones are those with lower indices. */
4587 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4590 for (i = 0; i <= opnum; i++)
4591 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4596 case RELOAD_FOR_OUTADDR_ADDRESS:
4597 /* Can't use a register if it is used for an output address
4598 for this operand or used as an output in this or a
4599 later operand. Note that multiple output operands are
4600 emitted in reverse order, so the conflicting ones are
4601 those with lower indices. */
4602 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4605 for (i = 0; i <= opnum; i++)
4606 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4611 case RELOAD_FOR_OPERAND_ADDRESS:
4612 for (i = 0; i < reload_n_operands; i++)
4613 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4616 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4617 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4619 case RELOAD_FOR_OPADDR_ADDR:
4620 for (i = 0; i < reload_n_operands; i++)
4621 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4624 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4626 case RELOAD_FOR_OUTPUT:
4627 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4628 outputs, or an operand address for this or an earlier output.
4629 Note that multiple output operands are emitted in reverse order,
4630 so the conflicting ones are those with higher indices. */
4631 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4634 for (i = 0; i < reload_n_operands; i++)
4635 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4638 for (i = opnum; i < reload_n_operands; i++)
4639 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4640 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4645 case RELOAD_FOR_INSN:
4646 for (i = 0; i < reload_n_operands; i++)
4647 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4648 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4651 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4652 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4654 case RELOAD_FOR_OTHER_ADDRESS:
4655 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4662 /* Return 1 if the value in reload reg REGNO, as used by a reload
4663 needed for the part of the insn specified by OPNUM and TYPE,
4664 is still available in REGNO at the end of the insn.
4666 We can assume that the reload reg was already tested for availability
4667 at the time it is needed, and we should not check this again,
4668 in case the reg has already been marked in use. */
4671 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4678 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4679 its value must reach the end. */
4682 /* If this use is for part of the insn,
4683 its value reaches if no subsequent part uses the same register.
4684 Just like the above function, don't try to do this with lots
4687 case RELOAD_FOR_OTHER_ADDRESS:
4688 /* Here we check for everything else, since these don't conflict
4689 with anything else and everything comes later. */
4691 for (i = 0; i < reload_n_operands; i++)
4692 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4693 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4694 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4695 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4696 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4697 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4700 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4701 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4702 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4703 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4705 case RELOAD_FOR_INPUT_ADDRESS:
4706 case RELOAD_FOR_INPADDR_ADDRESS:
4707 /* Similar, except that we check only for this and subsequent inputs
4708 and the address of only subsequent inputs and we do not need
4709 to check for RELOAD_OTHER objects since they are known not to
4712 for (i = opnum; i < reload_n_operands; i++)
4713 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4716 for (i = opnum + 1; i < reload_n_operands; i++)
4717 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4718 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4721 for (i = 0; i < reload_n_operands; i++)
4722 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4723 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4724 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4727 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4730 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4731 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4732 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4734 case RELOAD_FOR_INPUT:
4735 /* Similar to input address, except we start at the next operand for
4736 both input and input address and we do not check for
4737 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4740 for (i = opnum + 1; i < reload_n_operands; i++)
4741 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4742 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4743 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4746 /* ... fall through ... */
4748 case RELOAD_FOR_OPERAND_ADDRESS:
4749 /* Check outputs and their addresses. */
4751 for (i = 0; i < reload_n_operands; i++)
4752 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4753 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4754 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4757 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4759 case RELOAD_FOR_OPADDR_ADDR:
4760 for (i = 0; i < reload_n_operands; i++)
4761 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4762 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4763 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4766 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4767 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4768 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4770 case RELOAD_FOR_INSN:
4771 /* These conflict with other outputs with RELOAD_OTHER. So
4772 we need only check for output addresses. */
4774 opnum = reload_n_operands;
4776 /* ... fall through ... */
4778 case RELOAD_FOR_OUTPUT:
4779 case RELOAD_FOR_OUTPUT_ADDRESS:
4780 case RELOAD_FOR_OUTADDR_ADDRESS:
4781 /* We already know these can't conflict with a later output. So the
4782 only thing to check are later output addresses.
4783 Note that multiple output operands are emitted in reverse order,
4784 so the conflicting ones are those with lower indices. */
4785 for (i = 0; i < opnum; i++)
4786 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4787 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4798 /* Returns whether R1 and R2 are uniquely chained: the value of one
4799 is used by the other, and that value is not used by any other
4800 reload for this insn. This is used to partially undo the decision
4801 made in find_reloads when in the case of multiple
4802 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4803 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4804 reloads. This code tries to avoid the conflict created by that
4805 change. It might be cleaner to explicitly keep track of which
4806 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4807 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4808 this after the fact. */
4810 reloads_unique_chain_p (int r1, int r2)
4814 /* We only check input reloads. */
4815 if (! rld[r1].in || ! rld[r2].in)
4818 /* Avoid anything with output reloads. */
4819 if (rld[r1].out || rld[r2].out)
4822 /* "chained" means one reload is a component of the other reload,
4823 not the same as the other reload. */
4824 if (rld[r1].opnum != rld[r2].opnum
4825 || rtx_equal_p (rld[r1].in, rld[r2].in)
4826 || rld[r1].optional || rld[r2].optional
4827 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4828 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4831 for (i = 0; i < n_reloads; i ++)
4832 /* Look for input reloads that aren't our two */
4833 if (i != r1 && i != r2 && rld[i].in)
4835 /* If our reload is mentioned at all, it isn't a simple chain. */
4836 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4842 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4845 This function uses the same algorithm as reload_reg_free_p above. */
4848 reloads_conflict (int r1, int r2)
4850 enum reload_type r1_type = rld[r1].when_needed;
4851 enum reload_type r2_type = rld[r2].when_needed;
4852 int r1_opnum = rld[r1].opnum;
4853 int r2_opnum = rld[r2].opnum;
4855 /* RELOAD_OTHER conflicts with everything. */
4856 if (r2_type == RELOAD_OTHER)
4859 /* Otherwise, check conflicts differently for each type. */
4863 case RELOAD_FOR_INPUT:
4864 return (r2_type == RELOAD_FOR_INSN
4865 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4866 || r2_type == RELOAD_FOR_OPADDR_ADDR
4867 || r2_type == RELOAD_FOR_INPUT
4868 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4869 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4870 && r2_opnum > r1_opnum));
4872 case RELOAD_FOR_INPUT_ADDRESS:
4873 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4874 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4876 case RELOAD_FOR_INPADDR_ADDRESS:
4877 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4878 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4880 case RELOAD_FOR_OUTPUT_ADDRESS:
4881 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4882 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4884 case RELOAD_FOR_OUTADDR_ADDRESS:
4885 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4886 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4888 case RELOAD_FOR_OPERAND_ADDRESS:
4889 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4890 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
4891 && !reloads_unique_chain_p (r1, r2)));
4893 case RELOAD_FOR_OPADDR_ADDR:
4894 return (r2_type == RELOAD_FOR_INPUT
4895 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4897 case RELOAD_FOR_OUTPUT:
4898 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4899 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4900 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4901 && r2_opnum >= r1_opnum));
4903 case RELOAD_FOR_INSN:
4904 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4905 || r2_type == RELOAD_FOR_INSN
4906 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4908 case RELOAD_FOR_OTHER_ADDRESS:
4909 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4919 /* Indexed by reload number, 1 if incoming value
4920 inherited from previous insns. */
4921 static char reload_inherited[MAX_RELOADS];
4923 /* For an inherited reload, this is the insn the reload was inherited from,
4924 if we know it. Otherwise, this is 0. */
4925 static rtx reload_inheritance_insn[MAX_RELOADS];
4927 /* If nonzero, this is a place to get the value of the reload,
4928 rather than using reload_in. */
4929 static rtx reload_override_in[MAX_RELOADS];
4931 /* For each reload, the hard register number of the register used,
4932 or -1 if we did not need a register for this reload. */
4933 static int reload_spill_index[MAX_RELOADS];
4935 /* Subroutine of free_for_value_p, used to check a single register.
4936 START_REGNO is the starting regno of the full reload register
4937 (possibly comprising multiple hard registers) that we are considering. */
4940 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4941 enum reload_type type, rtx value, rtx out,
4942 int reloadnum, int ignore_address_reloads)
4945 /* Set if we see an input reload that must not share its reload register
4946 with any new earlyclobber, but might otherwise share the reload
4947 register with an output or input-output reload. */
4948 int check_earlyclobber = 0;
4952 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4955 if (out == const0_rtx)
4961 /* We use some pseudo 'time' value to check if the lifetimes of the
4962 new register use would overlap with the one of a previous reload
4963 that is not read-only or uses a different value.
4964 The 'time' used doesn't have to be linear in any shape or form, just
4966 Some reload types use different 'buckets' for each operand.
4967 So there are MAX_RECOG_OPERANDS different time values for each
4969 We compute TIME1 as the time when the register for the prospective
4970 new reload ceases to be live, and TIME2 for each existing
4971 reload as the time when that the reload register of that reload
4973 Where there is little to be gained by exact lifetime calculations,
4974 we just make conservative assumptions, i.e. a longer lifetime;
4975 this is done in the 'default:' cases. */
4978 case RELOAD_FOR_OTHER_ADDRESS:
4979 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4980 time1 = copy ? 0 : 1;
4983 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4985 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4986 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4987 respectively, to the time values for these, we get distinct time
4988 values. To get distinct time values for each operand, we have to
4989 multiply opnum by at least three. We round that up to four because
4990 multiply by four is often cheaper. */
4991 case RELOAD_FOR_INPADDR_ADDRESS:
4992 time1 = opnum * 4 + 2;
4994 case RELOAD_FOR_INPUT_ADDRESS:
4995 time1 = opnum * 4 + 3;
4997 case RELOAD_FOR_INPUT:
4998 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4999 executes (inclusive). */
5000 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5002 case RELOAD_FOR_OPADDR_ADDR:
5004 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5005 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5007 case RELOAD_FOR_OPERAND_ADDRESS:
5008 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5010 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5012 case RELOAD_FOR_OUTADDR_ADDRESS:
5013 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5015 case RELOAD_FOR_OUTPUT_ADDRESS:
5016 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5019 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5022 for (i = 0; i < n_reloads; i++)
5024 rtx reg = rld[i].reg_rtx;
5025 if (reg && REG_P (reg)
5026 && ((unsigned) regno - true_regnum (reg)
5027 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5030 rtx other_input = rld[i].in;
5032 /* If the other reload loads the same input value, that
5033 will not cause a conflict only if it's loading it into
5034 the same register. */
5035 if (true_regnum (reg) != start_regno)
5036 other_input = NULL_RTX;
5037 if (! other_input || ! rtx_equal_p (other_input, value)
5038 || rld[i].out || out)
5041 switch (rld[i].when_needed)
5043 case RELOAD_FOR_OTHER_ADDRESS:
5046 case RELOAD_FOR_INPADDR_ADDRESS:
5047 /* find_reloads makes sure that a
5048 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5049 by at most one - the first -
5050 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5051 address reload is inherited, the address address reload
5052 goes away, so we can ignore this conflict. */
5053 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5054 && ignore_address_reloads
5055 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5056 Then the address address is still needed to store
5057 back the new address. */
5058 && ! rld[reloadnum].out)
5060 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5061 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5063 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5064 && ignore_address_reloads
5065 /* Unless we are reloading an auto_inc expression. */
5066 && ! rld[reloadnum].out)
5068 time2 = rld[i].opnum * 4 + 2;
5070 case RELOAD_FOR_INPUT_ADDRESS:
5071 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5072 && ignore_address_reloads
5073 && ! rld[reloadnum].out)
5075 time2 = rld[i].opnum * 4 + 3;
5077 case RELOAD_FOR_INPUT:
5078 time2 = rld[i].opnum * 4 + 4;
5079 check_earlyclobber = 1;
5081 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5082 == MAX_RECOG_OPERAND * 4 */
5083 case RELOAD_FOR_OPADDR_ADDR:
5084 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5085 && ignore_address_reloads
5086 && ! rld[reloadnum].out)
5088 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5090 case RELOAD_FOR_OPERAND_ADDRESS:
5091 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5092 check_earlyclobber = 1;
5094 case RELOAD_FOR_INSN:
5095 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5097 case RELOAD_FOR_OUTPUT:
5098 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5099 instruction is executed. */
5100 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5102 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5103 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5105 case RELOAD_FOR_OUTADDR_ADDRESS:
5106 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5107 && ignore_address_reloads
5108 && ! rld[reloadnum].out)
5110 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5112 case RELOAD_FOR_OUTPUT_ADDRESS:
5113 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5116 /* If there is no conflict in the input part, handle this
5117 like an output reload. */
5118 if (! rld[i].in || rtx_equal_p (other_input, value))
5120 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5121 /* Earlyclobbered outputs must conflict with inputs. */
5122 if (earlyclobber_operand_p (rld[i].out))
5123 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5128 /* RELOAD_OTHER might be live beyond instruction execution,
5129 but this is not obvious when we set time2 = 1. So check
5130 here if there might be a problem with the new reload
5131 clobbering the register used by the RELOAD_OTHER. */
5139 && (! rld[i].in || rld[i].out
5140 || ! rtx_equal_p (other_input, value)))
5141 || (out && rld[reloadnum].out_reg
5142 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5148 /* Earlyclobbered outputs must conflict with inputs. */
5149 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5155 /* Return 1 if the value in reload reg REGNO, as used by a reload
5156 needed for the part of the insn specified by OPNUM and TYPE,
5157 may be used to load VALUE into it.
5159 MODE is the mode in which the register is used, this is needed to
5160 determine how many hard regs to test.
5162 Other read-only reloads with the same value do not conflict
5163 unless OUT is nonzero and these other reloads have to live while
5164 output reloads live.
5165 If OUT is CONST0_RTX, this is a special case: it means that the
5166 test should not be for using register REGNO as reload register, but
5167 for copying from register REGNO into the reload register.
5169 RELOADNUM is the number of the reload we want to load this value for;
5170 a reload does not conflict with itself.
5172 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5173 reloads that load an address for the very reload we are considering.
5175 The caller has to make sure that there is no conflict with the return
5179 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5180 enum reload_type type, rtx value, rtx out, int reloadnum,
5181 int ignore_address_reloads)
5183 int nregs = hard_regno_nregs[regno][mode];
5185 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5186 value, out, reloadnum,
5187 ignore_address_reloads))
5192 /* Return nonzero if the rtx X is invariant over the current function. */
5193 /* ??? Actually, the places where we use this expect exactly what is
5194 tested here, and not everything that is function invariant. In
5195 particular, the frame pointer and arg pointer are special cased;
5196 pic_offset_table_rtx is not, and we must not spill these things to
5200 function_invariant_p (rtx x)
5204 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5206 if (GET_CODE (x) == PLUS
5207 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5208 && CONSTANT_P (XEXP (x, 1)))
5213 /* Determine whether the reload reg X overlaps any rtx'es used for
5214 overriding inheritance. Return nonzero if so. */
5217 conflicts_with_override (rtx x)
5220 for (i = 0; i < n_reloads; i++)
5221 if (reload_override_in[i]
5222 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5227 /* Give an error message saying we failed to find a reload for INSN,
5228 and clear out reload R. */
5230 failed_reload (rtx insn, int r)
5232 if (asm_noperands (PATTERN (insn)) < 0)
5233 /* It's the compiler's fault. */
5234 fatal_insn ("could not find a spill register", insn);
5236 /* It's the user's fault; the operand's mode and constraint
5237 don't match. Disable this reload so we don't crash in final. */
5238 error_for_asm (insn,
5239 "%<asm%> operand constraint incompatible with operand size");
5243 rld[r].optional = 1;
5244 rld[r].secondary_p = 1;
5247 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5248 for reload R. If it's valid, get an rtx for it. Return nonzero if
5251 set_reload_reg (int i, int r)
5254 rtx reg = spill_reg_rtx[i];
5256 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5257 spill_reg_rtx[i] = reg
5258 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5260 regno = true_regnum (reg);
5262 /* Detect when the reload reg can't hold the reload mode.
5263 This used to be one `if', but Sequent compiler can't handle that. */
5264 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5266 enum machine_mode test_mode = VOIDmode;
5268 test_mode = GET_MODE (rld[r].in);
5269 /* If rld[r].in has VOIDmode, it means we will load it
5270 in whatever mode the reload reg has: to wit, rld[r].mode.
5271 We have already tested that for validity. */
5272 /* Aside from that, we need to test that the expressions
5273 to reload from or into have modes which are valid for this
5274 reload register. Otherwise the reload insns would be invalid. */
5275 if (! (rld[r].in != 0 && test_mode != VOIDmode
5276 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5277 if (! (rld[r].out != 0
5278 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5280 /* The reg is OK. */
5283 /* Mark as in use for this insn the reload regs we use
5285 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5286 rld[r].when_needed, rld[r].mode);
5288 rld[r].reg_rtx = reg;
5289 reload_spill_index[r] = spill_regs[i];
5296 /* Find a spill register to use as a reload register for reload R.
5297 LAST_RELOAD is nonzero if this is the last reload for the insn being
5300 Set rld[R].reg_rtx to the register allocated.
5302 We return 1 if successful, or 0 if we couldn't find a spill reg and
5303 we didn't change anything. */
5306 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5311 /* If we put this reload ahead, thinking it is a group,
5312 then insist on finding a group. Otherwise we can grab a
5313 reg that some other reload needs.
5314 (That can happen when we have a 68000 DATA_OR_FP_REG
5315 which is a group of data regs or one fp reg.)
5316 We need not be so restrictive if there are no more reloads
5319 ??? Really it would be nicer to have smarter handling
5320 for that kind of reg class, where a problem like this is normal.
5321 Perhaps those classes should be avoided for reloading
5322 by use of more alternatives. */
5324 int force_group = rld[r].nregs > 1 && ! last_reload;
5326 /* If we want a single register and haven't yet found one,
5327 take any reg in the right class and not in use.
5328 If we want a consecutive group, here is where we look for it.
5330 We use two passes so we can first look for reload regs to
5331 reuse, which are already in use for other reloads in this insn,
5332 and only then use additional registers.
5333 I think that maximizing reuse is needed to make sure we don't
5334 run out of reload regs. Suppose we have three reloads, and
5335 reloads A and B can share regs. These need two regs.
5336 Suppose A and B are given different regs.
5337 That leaves none for C. */
5338 for (pass = 0; pass < 2; pass++)
5340 /* I is the index in spill_regs.
5341 We advance it round-robin between insns to use all spill regs
5342 equally, so that inherited reloads have a chance
5343 of leapfrogging each other. */
5347 for (count = 0; count < n_spills; count++)
5349 int class = (int) rld[r].class;
5355 regnum = spill_regs[i];
5357 if ((reload_reg_free_p (regnum, rld[r].opnum,
5360 /* We check reload_reg_used to make sure we
5361 don't clobber the return register. */
5362 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5363 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5364 rld[r].when_needed, rld[r].in,
5366 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5367 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5368 /* Look first for regs to share, then for unshared. But
5369 don't share regs used for inherited reloads; they are
5370 the ones we want to preserve. */
5372 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5374 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5377 int nr = hard_regno_nregs[regnum][rld[r].mode];
5378 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5379 (on 68000) got us two FP regs. If NR is 1,
5380 we would reject both of them. */
5383 /* If we need only one reg, we have already won. */
5386 /* But reject a single reg if we demand a group. */
5391 /* Otherwise check that as many consecutive regs as we need
5392 are available here. */
5395 int regno = regnum + nr - 1;
5396 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5397 && spill_reg_order[regno] >= 0
5398 && reload_reg_free_p (regno, rld[r].opnum,
5399 rld[r].when_needed)))
5408 /* If we found something on pass 1, omit pass 2. */
5409 if (count < n_spills)
5413 /* We should have found a spill register by now. */
5414 if (count >= n_spills)
5417 /* I is the index in SPILL_REG_RTX of the reload register we are to
5418 allocate. Get an rtx for it and find its register number. */
5420 return set_reload_reg (i, r);
5423 /* Initialize all the tables needed to allocate reload registers.
5424 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5425 is the array we use to restore the reg_rtx field for every reload. */
5428 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5432 for (i = 0; i < n_reloads; i++)
5433 rld[i].reg_rtx = save_reload_reg_rtx[i];
5435 memset (reload_inherited, 0, MAX_RELOADS);
5436 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5437 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5439 CLEAR_HARD_REG_SET (reload_reg_used);
5440 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5441 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5442 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5443 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5444 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5446 CLEAR_HARD_REG_SET (reg_used_in_insn);
5449 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5450 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5451 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5452 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5453 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5454 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5457 for (i = 0; i < reload_n_operands; i++)
5459 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5460 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5461 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5462 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5463 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5464 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5467 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5469 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5471 for (i = 0; i < n_reloads; i++)
5472 /* If we have already decided to use a certain register,
5473 don't use it in another way. */
5475 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5476 rld[i].when_needed, rld[i].mode);
5479 /* Assign hard reg targets for the pseudo-registers we must reload
5480 into hard regs for this insn.
5481 Also output the instructions to copy them in and out of the hard regs.
5483 For machines with register classes, we are responsible for
5484 finding a reload reg in the proper class. */
5487 choose_reload_regs (struct insn_chain *chain)
5489 rtx insn = chain->insn;
5491 unsigned int max_group_size = 1;
5492 enum reg_class group_class = NO_REGS;
5493 int pass, win, inheritance;
5495 rtx save_reload_reg_rtx[MAX_RELOADS];
5497 /* In order to be certain of getting the registers we need,
5498 we must sort the reloads into order of increasing register class.
5499 Then our grabbing of reload registers will parallel the process
5500 that provided the reload registers.
5502 Also note whether any of the reloads wants a consecutive group of regs.
5503 If so, record the maximum size of the group desired and what
5504 register class contains all the groups needed by this insn. */
5506 for (j = 0; j < n_reloads; j++)
5508 reload_order[j] = j;
5509 reload_spill_index[j] = -1;
5511 if (rld[j].nregs > 1)
5513 max_group_size = MAX (rld[j].nregs, max_group_size);
5515 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5518 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5522 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5524 /* If -O, try first with inheritance, then turning it off.
5525 If not -O, don't do inheritance.
5526 Using inheritance when not optimizing leads to paradoxes
5527 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5528 because one side of the comparison might be inherited. */
5530 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5532 choose_reload_regs_init (chain, save_reload_reg_rtx);
5534 /* Process the reloads in order of preference just found.
5535 Beyond this point, subregs can be found in reload_reg_rtx.
5537 This used to look for an existing reloaded home for all of the
5538 reloads, and only then perform any new reloads. But that could lose
5539 if the reloads were done out of reg-class order because a later
5540 reload with a looser constraint might have an old home in a register
5541 needed by an earlier reload with a tighter constraint.
5543 To solve this, we make two passes over the reloads, in the order
5544 described above. In the first pass we try to inherit a reload
5545 from a previous insn. If there is a later reload that needs a
5546 class that is a proper subset of the class being processed, we must
5547 also allocate a spill register during the first pass.
5549 Then make a second pass over the reloads to allocate any reloads
5550 that haven't been given registers yet. */
5552 for (j = 0; j < n_reloads; j++)
5554 int r = reload_order[j];
5555 rtx search_equiv = NULL_RTX;
5557 /* Ignore reloads that got marked inoperative. */
5558 if (rld[r].out == 0 && rld[r].in == 0
5559 && ! rld[r].secondary_p)
5562 /* If find_reloads chose to use reload_in or reload_out as a reload
5563 register, we don't need to chose one. Otherwise, try even if it
5564 found one since we might save an insn if we find the value lying
5566 Try also when reload_in is a pseudo without a hard reg. */
5567 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5568 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5569 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5570 && !MEM_P (rld[r].in)
5571 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5574 #if 0 /* No longer needed for correct operation.
5575 It might give better code, or might not; worth an experiment? */
5576 /* If this is an optional reload, we can't inherit from earlier insns
5577 until we are sure that any non-optional reloads have been allocated.
5578 The following code takes advantage of the fact that optional reloads
5579 are at the end of reload_order. */
5580 if (rld[r].optional != 0)
5581 for (i = 0; i < j; i++)
5582 if ((rld[reload_order[i]].out != 0
5583 || rld[reload_order[i]].in != 0
5584 || rld[reload_order[i]].secondary_p)
5585 && ! rld[reload_order[i]].optional
5586 && rld[reload_order[i]].reg_rtx == 0)
5587 allocate_reload_reg (chain, reload_order[i], 0);
5590 /* First see if this pseudo is already available as reloaded
5591 for a previous insn. We cannot try to inherit for reloads
5592 that are smaller than the maximum number of registers needed
5593 for groups unless the register we would allocate cannot be used
5596 We could check here to see if this is a secondary reload for
5597 an object that is already in a register of the desired class.
5598 This would avoid the need for the secondary reload register.
5599 But this is complex because we can't easily determine what
5600 objects might want to be loaded via this reload. So let a
5601 register be allocated here. In `emit_reload_insns' we suppress
5602 one of the loads in the case described above. */
5608 enum machine_mode mode = VOIDmode;
5612 else if (REG_P (rld[r].in))
5614 regno = REGNO (rld[r].in);
5615 mode = GET_MODE (rld[r].in);
5617 else if (REG_P (rld[r].in_reg))
5619 regno = REGNO (rld[r].in_reg);
5620 mode = GET_MODE (rld[r].in_reg);
5622 else if (GET_CODE (rld[r].in_reg) == SUBREG
5623 && REG_P (SUBREG_REG (rld[r].in_reg)))
5625 byte = SUBREG_BYTE (rld[r].in_reg);
5626 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5627 if (regno < FIRST_PSEUDO_REGISTER)
5628 regno = subreg_regno (rld[r].in_reg);
5629 mode = GET_MODE (rld[r].in_reg);
5632 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5633 && REG_P (XEXP (rld[r].in_reg, 0)))
5635 regno = REGNO (XEXP (rld[r].in_reg, 0));
5636 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5637 rld[r].out = rld[r].in;
5641 /* This won't work, since REGNO can be a pseudo reg number.
5642 Also, it takes much more hair to keep track of all the things
5643 that can invalidate an inherited reload of part of a pseudoreg. */
5644 else if (GET_CODE (rld[r].in) == SUBREG
5645 && REG_P (SUBREG_REG (rld[r].in)))
5646 regno = subreg_regno (rld[r].in);
5649 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5651 enum reg_class class = rld[r].class, last_class;
5652 rtx last_reg = reg_last_reload_reg[regno];
5653 enum machine_mode need_mode;
5655 i = REGNO (last_reg);
5656 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5657 last_class = REGNO_REG_CLASS (i);
5663 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5664 + byte * BITS_PER_UNIT,
5665 GET_MODE_CLASS (mode));
5667 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5668 >= GET_MODE_SIZE (need_mode))
5669 #ifdef CANNOT_CHANGE_MODE_CLASS
5670 /* Verify that the register in "i" can be obtained
5672 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5673 GET_MODE (last_reg),
5676 && reg_reloaded_contents[i] == regno
5677 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5678 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5679 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5680 /* Even if we can't use this register as a reload
5681 register, we might use it for reload_override_in,
5682 if copying it to the desired class is cheap
5684 || ((REGISTER_MOVE_COST (mode, last_class, class)
5685 < MEMORY_MOVE_COST (mode, class, 1))
5686 && (secondary_reload_class (1, class, mode,
5689 #ifdef SECONDARY_MEMORY_NEEDED
5690 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5695 && (rld[r].nregs == max_group_size
5696 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5698 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5699 rld[r].when_needed, rld[r].in,
5702 /* If a group is needed, verify that all the subsequent
5703 registers still have their values intact. */
5704 int nr = hard_regno_nregs[i][rld[r].mode];
5707 for (k = 1; k < nr; k++)
5708 if (reg_reloaded_contents[i + k] != regno
5709 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5717 last_reg = (GET_MODE (last_reg) == mode
5718 ? last_reg : gen_rtx_REG (mode, i));
5721 for (k = 0; k < nr; k++)
5722 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5725 /* We found a register that contains the
5726 value we need. If this register is the
5727 same as an `earlyclobber' operand of the
5728 current insn, just mark it as a place to
5729 reload from since we can't use it as the
5730 reload register itself. */
5732 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5733 if (reg_overlap_mentioned_for_reload_p
5734 (reg_last_reload_reg[regno],
5735 reload_earlyclobbers[i1]))
5738 if (i1 != n_earlyclobbers
5739 || ! (free_for_value_p (i, rld[r].mode,
5741 rld[r].when_needed, rld[r].in,
5743 /* Don't use it if we'd clobber a pseudo reg. */
5744 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5746 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5747 /* Don't clobber the frame pointer. */
5748 || (i == HARD_FRAME_POINTER_REGNUM
5749 && frame_pointer_needed
5751 /* Don't really use the inherited spill reg
5752 if we need it wider than we've got it. */
5753 || (GET_MODE_SIZE (rld[r].mode)
5754 > GET_MODE_SIZE (mode))
5757 /* If find_reloads chose reload_out as reload
5758 register, stay with it - that leaves the
5759 inherited register for subsequent reloads. */
5760 || (rld[r].out && rld[r].reg_rtx
5761 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5763 if (! rld[r].optional)
5765 reload_override_in[r] = last_reg;
5766 reload_inheritance_insn[r]
5767 = reg_reloaded_insn[i];
5773 /* We can use this as a reload reg. */
5774 /* Mark the register as in use for this part of
5776 mark_reload_reg_in_use (i,
5780 rld[r].reg_rtx = last_reg;
5781 reload_inherited[r] = 1;
5782 reload_inheritance_insn[r]
5783 = reg_reloaded_insn[i];
5784 reload_spill_index[r] = i;
5785 for (k = 0; k < nr; k++)
5786 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5794 /* Here's another way to see if the value is already lying around. */
5797 && ! reload_inherited[r]
5799 && (CONSTANT_P (rld[r].in)
5800 || GET_CODE (rld[r].in) == PLUS
5801 || REG_P (rld[r].in)
5802 || MEM_P (rld[r].in))
5803 && (rld[r].nregs == max_group_size
5804 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5805 search_equiv = rld[r].in;
5806 /* If this is an output reload from a simple move insn, look
5807 if an equivalence for the input is available. */
5808 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5810 rtx set = single_set (insn);
5813 && rtx_equal_p (rld[r].out, SET_DEST (set))
5814 && CONSTANT_P (SET_SRC (set)))
5815 search_equiv = SET_SRC (set);
5821 = find_equiv_reg (search_equiv, insn, rld[r].class,
5822 -1, NULL, 0, rld[r].mode);
5828 regno = REGNO (equiv);
5831 /* This must be a SUBREG of a hard register.
5832 Make a new REG since this might be used in an
5833 address and not all machines support SUBREGs
5835 gcc_assert (GET_CODE (equiv) == SUBREG);
5836 regno = subreg_regno (equiv);
5837 equiv = gen_rtx_REG (rld[r].mode, regno);
5838 /* If we choose EQUIV as the reload register, but the
5839 loop below decides to cancel the inheritance, we'll
5840 end up reloading EQUIV in rld[r].mode, not the mode
5841 it had originally. That isn't safe when EQUIV isn't
5842 available as a spill register since its value might
5843 still be live at this point. */
5844 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5845 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5850 /* If we found a spill reg, reject it unless it is free
5851 and of the desired class. */
5855 int bad_for_class = 0;
5856 int max_regno = regno + rld[r].nregs;
5858 for (i = regno; i < max_regno; i++)
5860 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5862 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5867 && ! free_for_value_p (regno, rld[r].mode,
5868 rld[r].opnum, rld[r].when_needed,
5869 rld[r].in, rld[r].out, r, 1))
5874 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5877 /* We found a register that contains the value we need.
5878 If this register is the same as an `earlyclobber' operand
5879 of the current insn, just mark it as a place to reload from
5880 since we can't use it as the reload register itself. */
5883 for (i = 0; i < n_earlyclobbers; i++)
5884 if (reg_overlap_mentioned_for_reload_p (equiv,
5885 reload_earlyclobbers[i]))
5887 if (! rld[r].optional)
5888 reload_override_in[r] = equiv;
5893 /* If the equiv register we have found is explicitly clobbered
5894 in the current insn, it depends on the reload type if we
5895 can use it, use it for reload_override_in, or not at all.
5896 In particular, we then can't use EQUIV for a
5897 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5901 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5902 switch (rld[r].when_needed)
5904 case RELOAD_FOR_OTHER_ADDRESS:
5905 case RELOAD_FOR_INPADDR_ADDRESS:
5906 case RELOAD_FOR_INPUT_ADDRESS:
5907 case RELOAD_FOR_OPADDR_ADDR:
5910 case RELOAD_FOR_INPUT:
5911 case RELOAD_FOR_OPERAND_ADDRESS:
5912 if (! rld[r].optional)
5913 reload_override_in[r] = equiv;
5919 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5920 switch (rld[r].when_needed)
5922 case RELOAD_FOR_OTHER_ADDRESS:
5923 case RELOAD_FOR_INPADDR_ADDRESS:
5924 case RELOAD_FOR_INPUT_ADDRESS:
5925 case RELOAD_FOR_OPADDR_ADDR:
5926 case RELOAD_FOR_OPERAND_ADDRESS:
5927 case RELOAD_FOR_INPUT:
5930 if (! rld[r].optional)
5931 reload_override_in[r] = equiv;
5939 /* If we found an equivalent reg, say no code need be generated
5940 to load it, and use it as our reload reg. */
5942 && (regno != HARD_FRAME_POINTER_REGNUM
5943 || !frame_pointer_needed))
5945 int nr = hard_regno_nregs[regno][rld[r].mode];
5947 rld[r].reg_rtx = equiv;
5948 reload_inherited[r] = 1;
5950 /* If reg_reloaded_valid is not set for this register,
5951 there might be a stale spill_reg_store lying around.
5952 We must clear it, since otherwise emit_reload_insns
5953 might delete the store. */
5954 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5955 spill_reg_store[regno] = NULL_RTX;
5956 /* If any of the hard registers in EQUIV are spill
5957 registers, mark them as in use for this insn. */
5958 for (k = 0; k < nr; k++)
5960 i = spill_reg_order[regno + k];
5963 mark_reload_reg_in_use (regno, rld[r].opnum,
5966 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5973 /* If we found a register to use already, or if this is an optional
5974 reload, we are done. */
5975 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5979 /* No longer needed for correct operation. Might or might
5980 not give better code on the average. Want to experiment? */
5982 /* See if there is a later reload that has a class different from our
5983 class that intersects our class or that requires less register
5984 than our reload. If so, we must allocate a register to this
5985 reload now, since that reload might inherit a previous reload
5986 and take the only available register in our class. Don't do this
5987 for optional reloads since they will force all previous reloads
5988 to be allocated. Also don't do this for reloads that have been
5991 for (i = j + 1; i < n_reloads; i++)
5993 int s = reload_order[i];
5995 if ((rld[s].in == 0 && rld[s].out == 0
5996 && ! rld[s].secondary_p)
6000 if ((rld[s].class != rld[r].class
6001 && reg_classes_intersect_p (rld[r].class,
6003 || rld[s].nregs < rld[r].nregs)
6010 allocate_reload_reg (chain, r, j == n_reloads - 1);
6014 /* Now allocate reload registers for anything non-optional that
6015 didn't get one yet. */
6016 for (j = 0; j < n_reloads; j++)
6018 int r = reload_order[j];
6020 /* Ignore reloads that got marked inoperative. */
6021 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6024 /* Skip reloads that already have a register allocated or are
6026 if (rld[r].reg_rtx != 0 || rld[r].optional)
6029 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6033 /* If that loop got all the way, we have won. */
6040 /* Loop around and try without any inheritance. */
6045 /* First undo everything done by the failed attempt
6046 to allocate with inheritance. */
6047 choose_reload_regs_init (chain, save_reload_reg_rtx);
6049 /* Some sanity tests to verify that the reloads found in the first
6050 pass are identical to the ones we have now. */
6051 gcc_assert (chain->n_reloads == n_reloads);
6053 for (i = 0; i < n_reloads; i++)
6055 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6057 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6058 for (j = 0; j < n_spills; j++)
6059 if (spill_regs[j] == chain->rld[i].regno)
6060 if (! set_reload_reg (j, i))
6061 failed_reload (chain->insn, i);
6065 /* If we thought we could inherit a reload, because it seemed that
6066 nothing else wanted the same reload register earlier in the insn,
6067 verify that assumption, now that all reloads have been assigned.
6068 Likewise for reloads where reload_override_in has been set. */
6070 /* If doing expensive optimizations, do one preliminary pass that doesn't
6071 cancel any inheritance, but removes reloads that have been needed only
6072 for reloads that we know can be inherited. */
6073 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6075 for (j = 0; j < n_reloads; j++)
6077 int r = reload_order[j];
6079 if (reload_inherited[r] && rld[r].reg_rtx)
6080 check_reg = rld[r].reg_rtx;
6081 else if (reload_override_in[r]
6082 && (REG_P (reload_override_in[r])
6083 || GET_CODE (reload_override_in[r]) == SUBREG))
6084 check_reg = reload_override_in[r];
6087 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6088 rld[r].opnum, rld[r].when_needed, rld[r].in,
6089 (reload_inherited[r]
6090 ? rld[r].out : const0_rtx),
6095 reload_inherited[r] = 0;
6096 reload_override_in[r] = 0;
6098 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6099 reload_override_in, then we do not need its related
6100 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6101 likewise for other reload types.
6102 We handle this by removing a reload when its only replacement
6103 is mentioned in reload_in of the reload we are going to inherit.
6104 A special case are auto_inc expressions; even if the input is
6105 inherited, we still need the address for the output. We can
6106 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6107 If we succeeded removing some reload and we are doing a preliminary
6108 pass just to remove such reloads, make another pass, since the
6109 removal of one reload might allow us to inherit another one. */
6111 && rld[r].out != rld[r].in
6112 && remove_address_replacements (rld[r].in) && pass)
6117 /* Now that reload_override_in is known valid,
6118 actually override reload_in. */
6119 for (j = 0; j < n_reloads; j++)
6120 if (reload_override_in[j])
6121 rld[j].in = reload_override_in[j];
6123 /* If this reload won't be done because it has been canceled or is
6124 optional and not inherited, clear reload_reg_rtx so other
6125 routines (such as subst_reloads) don't get confused. */
6126 for (j = 0; j < n_reloads; j++)
6127 if (rld[j].reg_rtx != 0
6128 && ((rld[j].optional && ! reload_inherited[j])
6129 || (rld[j].in == 0 && rld[j].out == 0
6130 && ! rld[j].secondary_p)))
6132 int regno = true_regnum (rld[j].reg_rtx);
6134 if (spill_reg_order[regno] >= 0)
6135 clear_reload_reg_in_use (regno, rld[j].opnum,
6136 rld[j].when_needed, rld[j].mode);
6138 reload_spill_index[j] = -1;
6141 /* Record which pseudos and which spill regs have output reloads. */
6142 for (j = 0; j < n_reloads; j++)
6144 int r = reload_order[j];
6146 i = reload_spill_index[r];
6148 /* I is nonneg if this reload uses a register.
6149 If rld[r].reg_rtx is 0, this is an optional reload
6150 that we opted to ignore. */
6151 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6152 && rld[r].reg_rtx != 0)
6154 int nregno = REGNO (rld[r].out_reg);
6157 if (nregno < FIRST_PSEUDO_REGISTER)
6158 nr = hard_regno_nregs[nregno][rld[r].mode];
6161 SET_REGNO_REG_SET (®_has_output_reload,
6166 nr = hard_regno_nregs[i][rld[r].mode];
6168 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6171 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6172 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6173 || rld[r].when_needed == RELOAD_FOR_INSN);
6178 /* Deallocate the reload register for reload R. This is called from
6179 remove_address_replacements. */
6182 deallocate_reload_reg (int r)
6186 if (! rld[r].reg_rtx)
6188 regno = true_regnum (rld[r].reg_rtx);
6190 if (spill_reg_order[regno] >= 0)
6191 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6193 reload_spill_index[r] = -1;
6196 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6197 reloads of the same item for fear that we might not have enough reload
6198 registers. However, normally they will get the same reload register
6199 and hence actually need not be loaded twice.
6201 Here we check for the most common case of this phenomenon: when we have
6202 a number of reloads for the same object, each of which were allocated
6203 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6204 reload, and is not modified in the insn itself. If we find such,
6205 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6206 This will not increase the number of spill registers needed and will
6207 prevent redundant code. */
6210 merge_assigned_reloads (rtx insn)
6214 /* Scan all the reloads looking for ones that only load values and
6215 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6216 assigned and not modified by INSN. */
6218 for (i = 0; i < n_reloads; i++)
6220 int conflicting_input = 0;
6221 int max_input_address_opnum = -1;
6222 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6224 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6225 || rld[i].out != 0 || rld[i].reg_rtx == 0
6226 || reg_set_p (rld[i].reg_rtx, insn))
6229 /* Look at all other reloads. Ensure that the only use of this
6230 reload_reg_rtx is in a reload that just loads the same value
6231 as we do. Note that any secondary reloads must be of the identical
6232 class since the values, modes, and result registers are the
6233 same, so we need not do anything with any secondary reloads. */
6235 for (j = 0; j < n_reloads; j++)
6237 if (i == j || rld[j].reg_rtx == 0
6238 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6242 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6243 && rld[j].opnum > max_input_address_opnum)
6244 max_input_address_opnum = rld[j].opnum;
6246 /* If the reload regs aren't exactly the same (e.g, different modes)
6247 or if the values are different, we can't merge this reload.
6248 But if it is an input reload, we might still merge
6249 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6251 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6252 || rld[j].out != 0 || rld[j].in == 0
6253 || ! rtx_equal_p (rld[i].in, rld[j].in))
6255 if (rld[j].when_needed != RELOAD_FOR_INPUT
6256 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6257 || rld[i].opnum > rld[j].opnum)
6258 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6260 conflicting_input = 1;
6261 if (min_conflicting_input_opnum > rld[j].opnum)
6262 min_conflicting_input_opnum = rld[j].opnum;
6266 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6267 we, in fact, found any matching reloads. */
6270 && max_input_address_opnum <= min_conflicting_input_opnum)
6272 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6274 for (j = 0; j < n_reloads; j++)
6275 if (i != j && rld[j].reg_rtx != 0
6276 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6277 && (! conflicting_input
6278 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6279 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6281 rld[i].when_needed = RELOAD_OTHER;
6283 reload_spill_index[j] = -1;
6284 transfer_replacements (i, j);
6287 /* If this is now RELOAD_OTHER, look for any reloads that load
6288 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6289 if they were for inputs, RELOAD_OTHER for outputs. Note that
6290 this test is equivalent to looking for reloads for this operand
6292 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6293 share registers with a RELOAD_FOR_INPUT, so we can not change it
6294 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6295 do not modify RELOAD_FOR_OUTPUT. */
6297 if (rld[i].when_needed == RELOAD_OTHER)
6298 for (j = 0; j < n_reloads; j++)
6300 && rld[j].when_needed != RELOAD_OTHER
6301 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6302 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6303 && (! conflicting_input
6304 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6305 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6306 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6312 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6313 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6314 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6316 /* Check to see if we accidentally converted two
6317 reloads that use the same reload register with
6318 different inputs to the same type. If so, the
6319 resulting code won't work. */
6321 for (k = 0; k < j; k++)
6322 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6323 || rld[k].when_needed != rld[j].when_needed
6324 || !rtx_equal_p (rld[k].reg_rtx,
6326 || rtx_equal_p (rld[k].in,
6333 /* These arrays are filled by emit_reload_insns and its subroutines. */
6334 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6335 static rtx other_input_address_reload_insns = 0;
6336 static rtx other_input_reload_insns = 0;
6337 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6338 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6339 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6340 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6341 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6342 static rtx operand_reload_insns = 0;
6343 static rtx other_operand_reload_insns = 0;
6344 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6346 /* Values to be put in spill_reg_store are put here first. */
6347 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6348 static HARD_REG_SET reg_reloaded_died;
6350 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6351 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6352 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6353 adjusted register, and return true. Otherwise, return false. */
6355 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6356 enum reg_class new_class,
6357 enum machine_mode new_mode)
6362 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6364 unsigned regno = REGNO (reg);
6366 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6368 if (GET_MODE (reg) != new_mode)
6370 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6372 if (hard_regno_nregs[regno][new_mode]
6373 > hard_regno_nregs[regno][GET_MODE (reg)])
6375 reg = reload_adjust_reg_for_mode (reg, new_mode);
6383 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6384 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6385 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6386 adjusted register, and return true. Otherwise, return false. */
6388 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6389 enum insn_code icode)
6392 enum reg_class new_class = scratch_reload_class (icode);
6393 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6395 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6396 new_class, new_mode);
6399 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6400 has the number J. OLD contains the value to be used as input. */
6403 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6406 rtx insn = chain->insn;
6407 rtx reloadreg = rl->reg_rtx;
6408 rtx oldequiv_reg = 0;
6411 enum machine_mode mode;
6414 /* Determine the mode to reload in.
6415 This is very tricky because we have three to choose from.
6416 There is the mode the insn operand wants (rl->inmode).
6417 There is the mode of the reload register RELOADREG.
6418 There is the intrinsic mode of the operand, which we could find
6419 by stripping some SUBREGs.
6420 It turns out that RELOADREG's mode is irrelevant:
6421 we can change that arbitrarily.
6423 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6424 then the reload reg may not support QImode moves, so use SImode.
6425 If foo is in memory due to spilling a pseudo reg, this is safe,
6426 because the QImode value is in the least significant part of a
6427 slot big enough for a SImode. If foo is some other sort of
6428 memory reference, then it is impossible to reload this case,
6429 so previous passes had better make sure this never happens.
6431 Then consider a one-word union which has SImode and one of its
6432 members is a float, being fetched as (SUBREG:SF union:SI).
6433 We must fetch that as SFmode because we could be loading into
6434 a float-only register. In this case OLD's mode is correct.
6436 Consider an immediate integer: it has VOIDmode. Here we need
6437 to get a mode from something else.
6439 In some cases, there is a fourth mode, the operand's
6440 containing mode. If the insn specifies a containing mode for
6441 this operand, it overrides all others.
6443 I am not sure whether the algorithm here is always right,
6444 but it does the right things in those cases. */
6446 mode = GET_MODE (old);
6447 if (mode == VOIDmode)
6450 /* delete_output_reload is only invoked properly if old contains
6451 the original pseudo register. Since this is replaced with a
6452 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6453 find the pseudo in RELOAD_IN_REG. */
6454 if (reload_override_in[j]
6455 && REG_P (rl->in_reg))
6462 else if (REG_P (oldequiv))
6463 oldequiv_reg = oldequiv;
6464 else if (GET_CODE (oldequiv) == SUBREG)
6465 oldequiv_reg = SUBREG_REG (oldequiv);
6467 /* If we are reloading from a register that was recently stored in
6468 with an output-reload, see if we can prove there was
6469 actually no need to store the old value in it. */
6471 if (optimize && REG_P (oldequiv)
6472 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6473 && spill_reg_store[REGNO (oldequiv)]
6475 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6476 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6478 delete_output_reload (insn, j, REGNO (oldequiv));
6480 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6481 then load RELOADREG from OLDEQUIV. Note that we cannot use
6482 gen_lowpart_common since it can do the wrong thing when
6483 RELOADREG has a multi-word mode. Note that RELOADREG
6484 must always be a REG here. */
6486 if (GET_MODE (reloadreg) != mode)
6487 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6488 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6489 oldequiv = SUBREG_REG (oldequiv);
6490 if (GET_MODE (oldequiv) != VOIDmode
6491 && mode != GET_MODE (oldequiv))
6492 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6494 /* Switch to the right place to emit the reload insns. */
6495 switch (rl->when_needed)
6498 where = &other_input_reload_insns;
6500 case RELOAD_FOR_INPUT:
6501 where = &input_reload_insns[rl->opnum];
6503 case RELOAD_FOR_INPUT_ADDRESS:
6504 where = &input_address_reload_insns[rl->opnum];
6506 case RELOAD_FOR_INPADDR_ADDRESS:
6507 where = &inpaddr_address_reload_insns[rl->opnum];
6509 case RELOAD_FOR_OUTPUT_ADDRESS:
6510 where = &output_address_reload_insns[rl->opnum];
6512 case RELOAD_FOR_OUTADDR_ADDRESS:
6513 where = &outaddr_address_reload_insns[rl->opnum];
6515 case RELOAD_FOR_OPERAND_ADDRESS:
6516 where = &operand_reload_insns;
6518 case RELOAD_FOR_OPADDR_ADDR:
6519 where = &other_operand_reload_insns;
6521 case RELOAD_FOR_OTHER_ADDRESS:
6522 where = &other_input_address_reload_insns;
6528 push_to_sequence (*where);
6530 /* Auto-increment addresses must be reloaded in a special way. */
6531 if (rl->out && ! rl->out_reg)
6533 /* We are not going to bother supporting the case where a
6534 incremented register can't be copied directly from
6535 OLDEQUIV since this seems highly unlikely. */
6536 gcc_assert (rl->secondary_in_reload < 0);
6538 if (reload_inherited[j])
6539 oldequiv = reloadreg;
6541 old = XEXP (rl->in_reg, 0);
6543 if (optimize && REG_P (oldequiv)
6544 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6545 && spill_reg_store[REGNO (oldequiv)]
6547 && (dead_or_set_p (insn,
6548 spill_reg_stored_to[REGNO (oldequiv)])
6549 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6551 delete_output_reload (insn, j, REGNO (oldequiv));
6553 /* Prevent normal processing of this reload. */
6555 /* Output a special code sequence for this case. */
6556 new_spill_reg_store[REGNO (reloadreg)]
6557 = inc_for_reload (reloadreg, oldequiv, rl->out,
6561 /* If we are reloading a pseudo-register that was set by the previous
6562 insn, see if we can get rid of that pseudo-register entirely
6563 by redirecting the previous insn into our reload register. */
6565 else if (optimize && REG_P (old)
6566 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6567 && dead_or_set_p (insn, old)
6568 /* This is unsafe if some other reload
6569 uses the same reg first. */
6570 && ! conflicts_with_override (reloadreg)
6571 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6572 rl->when_needed, old, rl->out, j, 0))
6574 rtx temp = PREV_INSN (insn);
6575 while (temp && NOTE_P (temp))
6576 temp = PREV_INSN (temp);
6578 && NONJUMP_INSN_P (temp)
6579 && GET_CODE (PATTERN (temp)) == SET
6580 && SET_DEST (PATTERN (temp)) == old
6581 /* Make sure we can access insn_operand_constraint. */
6582 && asm_noperands (PATTERN (temp)) < 0
6583 /* This is unsafe if operand occurs more than once in current
6584 insn. Perhaps some occurrences aren't reloaded. */
6585 && count_occurrences (PATTERN (insn), old, 0) == 1)
6587 rtx old = SET_DEST (PATTERN (temp));
6588 /* Store into the reload register instead of the pseudo. */
6589 SET_DEST (PATTERN (temp)) = reloadreg;
6591 /* Verify that resulting insn is valid. */
6592 extract_insn (temp);
6593 if (constrain_operands (1))
6595 /* If the previous insn is an output reload, the source is
6596 a reload register, and its spill_reg_store entry will
6597 contain the previous destination. This is now
6599 if (REG_P (SET_SRC (PATTERN (temp)))
6600 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6602 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6603 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6606 /* If these are the only uses of the pseudo reg,
6607 pretend for GDB it lives in the reload reg we used. */
6608 if (REG_N_DEATHS (REGNO (old)) == 1
6609 && REG_N_SETS (REGNO (old)) == 1)
6611 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6612 alter_reg (REGNO (old), -1);
6618 SET_DEST (PATTERN (temp)) = old;
6623 /* We can't do that, so output an insn to load RELOADREG. */
6625 /* If we have a secondary reload, pick up the secondary register
6626 and icode, if any. If OLDEQUIV and OLD are different or
6627 if this is an in-out reload, recompute whether or not we
6628 still need a secondary register and what the icode should
6629 be. If we still need a secondary register and the class or
6630 icode is different, go back to reloading from OLD if using
6631 OLDEQUIV means that we got the wrong type of register. We
6632 cannot have different class or icode due to an in-out reload
6633 because we don't make such reloads when both the input and
6634 output need secondary reload registers. */
6636 if (! special && rl->secondary_in_reload >= 0)
6638 rtx second_reload_reg = 0;
6639 rtx third_reload_reg = 0;
6640 int secondary_reload = rl->secondary_in_reload;
6641 rtx real_oldequiv = oldequiv;
6644 enum insn_code icode;
6645 enum insn_code tertiary_icode = CODE_FOR_nothing;
6647 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6648 and similarly for OLD.
6649 See comments in get_secondary_reload in reload.c. */
6650 /* If it is a pseudo that cannot be replaced with its
6651 equivalent MEM, we must fall back to reload_in, which
6652 will have all the necessary substitutions registered.
6653 Likewise for a pseudo that can't be replaced with its
6654 equivalent constant.
6656 Take extra care for subregs of such pseudos. Note that
6657 we cannot use reg_equiv_mem in this case because it is
6658 not in the right mode. */
6661 if (GET_CODE (tmp) == SUBREG)
6662 tmp = SUBREG_REG (tmp);
6664 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6665 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6666 || reg_equiv_constant[REGNO (tmp)] != 0))
6668 if (! reg_equiv_mem[REGNO (tmp)]
6669 || num_not_at_initial_offset
6670 || GET_CODE (oldequiv) == SUBREG)
6671 real_oldequiv = rl->in;
6673 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6677 if (GET_CODE (tmp) == SUBREG)
6678 tmp = SUBREG_REG (tmp);
6680 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6681 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6682 || reg_equiv_constant[REGNO (tmp)] != 0))
6684 if (! reg_equiv_mem[REGNO (tmp)]
6685 || num_not_at_initial_offset
6686 || GET_CODE (old) == SUBREG)
6689 real_old = reg_equiv_mem[REGNO (tmp)];
6692 second_reload_reg = rld[secondary_reload].reg_rtx;
6693 if (rld[secondary_reload].secondary_in_reload >= 0)
6695 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6697 third_reload_reg = rld[tertiary_reload].reg_rtx;
6698 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6699 /* We'd have to add more code for quartary reloads. */
6700 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6702 icode = rl->secondary_in_icode;
6704 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6705 || (rl->in != 0 && rl->out != 0))
6707 secondary_reload_info sri, sri2;
6708 enum reg_class new_class, new_t_class;
6710 sri.icode = CODE_FOR_nothing;
6711 sri.prev_sri = NULL;
6712 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6715 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6716 second_reload_reg = 0;
6717 else if (new_class == NO_REGS)
6719 if (reload_adjust_reg_for_icode (&second_reload_reg,
6720 third_reload_reg, sri.icode))
6721 icode = sri.icode, third_reload_reg = 0;
6723 oldequiv = old, real_oldequiv = real_old;
6725 else if (sri.icode != CODE_FOR_nothing)
6726 /* We currently lack a way to express this in reloads. */
6730 sri2.icode = CODE_FOR_nothing;
6731 sri2.prev_sri = &sri;
6732 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6733 new_class, mode, &sri);
6734 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6736 if (reload_adjust_reg_for_temp (&second_reload_reg,
6739 third_reload_reg = 0, tertiary_icode = sri2.icode;
6741 oldequiv = old, real_oldequiv = real_old;
6743 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6745 rtx intermediate = second_reload_reg;
6747 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6749 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6752 second_reload_reg = intermediate;
6753 tertiary_icode = sri2.icode;
6756 oldequiv = old, real_oldequiv = real_old;
6758 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6760 rtx intermediate = second_reload_reg;
6762 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6764 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6767 second_reload_reg = intermediate;
6768 tertiary_icode = sri2.icode;
6771 oldequiv = old, real_oldequiv = real_old;
6774 /* This could be handled more intelligently too. */
6775 oldequiv = old, real_oldequiv = real_old;
6779 /* If we still need a secondary reload register, check
6780 to see if it is being used as a scratch or intermediate
6781 register and generate code appropriately. If we need
6782 a scratch register, use REAL_OLDEQUIV since the form of
6783 the insn may depend on the actual address if it is
6786 if (second_reload_reg)
6788 if (icode != CODE_FOR_nothing)
6790 /* We'd have to add extra code to handle this case. */
6791 gcc_assert (!third_reload_reg);
6793 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6794 second_reload_reg));
6799 /* See if we need a scratch register to load the
6800 intermediate register (a tertiary reload). */
6801 if (tertiary_icode != CODE_FOR_nothing)
6803 emit_insn ((GEN_FCN (tertiary_icode)
6804 (second_reload_reg, real_oldequiv,
6805 third_reload_reg)));
6807 else if (third_reload_reg)
6809 gen_reload (third_reload_reg, real_oldequiv,
6812 gen_reload (second_reload_reg, third_reload_reg,
6817 gen_reload (second_reload_reg, real_oldequiv,
6821 oldequiv = second_reload_reg;
6826 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6828 rtx real_oldequiv = oldequiv;
6830 if ((REG_P (oldequiv)
6831 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6832 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6833 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6834 || (GET_CODE (oldequiv) == SUBREG
6835 && REG_P (SUBREG_REG (oldequiv))
6836 && (REGNO (SUBREG_REG (oldequiv))
6837 >= FIRST_PSEUDO_REGISTER)
6838 && ((reg_equiv_memory_loc
6839 [REGNO (SUBREG_REG (oldequiv))] != 0)
6840 || (reg_equiv_constant
6841 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6842 || (CONSTANT_P (oldequiv)
6843 && (PREFERRED_RELOAD_CLASS (oldequiv,
6844 REGNO_REG_CLASS (REGNO (reloadreg)))
6846 real_oldequiv = rl->in;
6847 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6851 if (flag_non_call_exceptions)
6852 copy_eh_notes (insn, get_insns ());
6854 /* End this sequence. */
6855 *where = get_insns ();
6858 /* Update reload_override_in so that delete_address_reloads_1
6859 can see the actual register usage. */
6861 reload_override_in[j] = oldequiv;
6864 /* Generate insns to for the output reload RL, which is for the insn described
6865 by CHAIN and has the number J. */
6867 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6870 rtx reloadreg = rl->reg_rtx;
6871 rtx insn = chain->insn;
6874 enum machine_mode mode = GET_MODE (old);
6877 if (rl->when_needed == RELOAD_OTHER)
6880 push_to_sequence (output_reload_insns[rl->opnum]);
6882 /* Determine the mode to reload in.
6883 See comments above (for input reloading). */
6885 if (mode == VOIDmode)
6887 /* VOIDmode should never happen for an output. */
6888 if (asm_noperands (PATTERN (insn)) < 0)
6889 /* It's the compiler's fault. */
6890 fatal_insn ("VOIDmode on an output", insn);
6891 error_for_asm (insn, "output operand is constant in %<asm%>");
6892 /* Prevent crash--use something we know is valid. */
6894 old = gen_rtx_REG (mode, REGNO (reloadreg));
6897 if (GET_MODE (reloadreg) != mode)
6898 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6900 /* If we need two reload regs, set RELOADREG to the intermediate
6901 one, since it will be stored into OLD. We might need a secondary
6902 register only for an input reload, so check again here. */
6904 if (rl->secondary_out_reload >= 0)
6907 int secondary_reload = rl->secondary_out_reload;
6908 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6910 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6911 && reg_equiv_mem[REGNO (old)] != 0)
6912 real_old = reg_equiv_mem[REGNO (old)];
6914 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6916 rtx second_reloadreg = reloadreg;
6917 reloadreg = rld[secondary_reload].reg_rtx;
6919 /* See if RELOADREG is to be used as a scratch register
6920 or as an intermediate register. */
6921 if (rl->secondary_out_icode != CODE_FOR_nothing)
6923 /* We'd have to add extra code to handle this case. */
6924 gcc_assert (tertiary_reload < 0);
6926 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6927 (real_old, second_reloadreg, reloadreg)));
6932 /* See if we need both a scratch and intermediate reload
6935 enum insn_code tertiary_icode
6936 = rld[secondary_reload].secondary_out_icode;
6938 /* We'd have to add more code for quartary reloads. */
6939 gcc_assert (tertiary_reload < 0
6940 || rld[tertiary_reload].secondary_out_reload < 0);
6942 if (GET_MODE (reloadreg) != mode)
6943 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6945 if (tertiary_icode != CODE_FOR_nothing)
6947 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6950 /* Copy primary reload reg to secondary reload reg.
6951 (Note that these have been swapped above, then
6952 secondary reload reg to OLD using our insn.) */
6954 /* If REAL_OLD is a paradoxical SUBREG, remove it
6955 and try to put the opposite SUBREG on
6957 if (GET_CODE (real_old) == SUBREG
6958 && (GET_MODE_SIZE (GET_MODE (real_old))
6959 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6960 && 0 != (tem = gen_lowpart_common
6961 (GET_MODE (SUBREG_REG (real_old)),
6963 real_old = SUBREG_REG (real_old), reloadreg = tem;
6965 gen_reload (reloadreg, second_reloadreg,
6966 rl->opnum, rl->when_needed);
6967 emit_insn ((GEN_FCN (tertiary_icode)
6968 (real_old, reloadreg, third_reloadreg)));
6974 /* Copy between the reload regs here and then to
6977 gen_reload (reloadreg, second_reloadreg,
6978 rl->opnum, rl->when_needed);
6979 if (tertiary_reload >= 0)
6981 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6983 gen_reload (third_reloadreg, reloadreg,
6984 rl->opnum, rl->when_needed);
6985 reloadreg = third_reloadreg;
6992 /* Output the last reload insn. */
6997 /* Don't output the last reload if OLD is not the dest of
6998 INSN and is in the src and is clobbered by INSN. */
6999 if (! flag_expensive_optimizations
7001 || !(set = single_set (insn))
7002 || rtx_equal_p (old, SET_DEST (set))
7003 || !reg_mentioned_p (old, SET_SRC (set))
7004 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7005 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7006 gen_reload (old, reloadreg, rl->opnum,
7010 /* Look at all insns we emitted, just to be safe. */
7011 for (p = get_insns (); p; p = NEXT_INSN (p))
7014 rtx pat = PATTERN (p);
7016 /* If this output reload doesn't come from a spill reg,
7017 clear any memory of reloaded copies of the pseudo reg.
7018 If this output reload comes from a spill reg,
7019 reg_has_output_reload will make this do nothing. */
7020 note_stores (pat, forget_old_reloads_1, NULL);
7022 if (reg_mentioned_p (rl->reg_rtx, pat))
7024 rtx set = single_set (insn);
7025 if (reload_spill_index[j] < 0
7027 && SET_SRC (set) == rl->reg_rtx)
7029 int src = REGNO (SET_SRC (set));
7031 reload_spill_index[j] = src;
7032 SET_HARD_REG_BIT (reg_is_output_reload, src);
7033 if (find_regno_note (insn, REG_DEAD, src))
7034 SET_HARD_REG_BIT (reg_reloaded_died, src);
7036 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7038 int s = rl->secondary_out_reload;
7039 set = single_set (p);
7040 /* If this reload copies only to the secondary reload
7041 register, the secondary reload does the actual
7043 if (s >= 0 && set == NULL_RTX)
7044 /* We can't tell what function the secondary reload
7045 has and where the actual store to the pseudo is
7046 made; leave new_spill_reg_store alone. */
7049 && SET_SRC (set) == rl->reg_rtx
7050 && SET_DEST (set) == rld[s].reg_rtx)
7052 /* Usually the next instruction will be the
7053 secondary reload insn; if we can confirm
7054 that it is, setting new_spill_reg_store to
7055 that insn will allow an extra optimization. */
7056 rtx s_reg = rld[s].reg_rtx;
7057 rtx next = NEXT_INSN (p);
7058 rld[s].out = rl->out;
7059 rld[s].out_reg = rl->out_reg;
7060 set = single_set (next);
7061 if (set && SET_SRC (set) == s_reg
7062 && ! new_spill_reg_store[REGNO (s_reg)])
7064 SET_HARD_REG_BIT (reg_is_output_reload,
7066 new_spill_reg_store[REGNO (s_reg)] = next;
7070 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7075 if (rl->when_needed == RELOAD_OTHER)
7077 emit_insn (other_output_reload_insns[rl->opnum]);
7078 other_output_reload_insns[rl->opnum] = get_insns ();
7081 output_reload_insns[rl->opnum] = get_insns ();
7083 if (flag_non_call_exceptions)
7084 copy_eh_notes (insn, get_insns ());
7089 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7090 and has the number J. */
7092 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7094 rtx insn = chain->insn;
7095 rtx old = (rl->in && MEM_P (rl->in)
7096 ? rl->in_reg : rl->in);
7099 /* AUTO_INC reloads need to be handled even if inherited. We got an
7100 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7101 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7102 && ! rtx_equal_p (rl->reg_rtx, old)
7103 && rl->reg_rtx != 0)
7104 emit_input_reload_insns (chain, rld + j, old, j);
7106 /* When inheriting a wider reload, we have a MEM in rl->in,
7107 e.g. inheriting a SImode output reload for
7108 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7109 if (optimize && reload_inherited[j] && rl->in
7111 && MEM_P (rl->in_reg)
7112 && reload_spill_index[j] >= 0
7113 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7114 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7116 /* If we are reloading a register that was recently stored in with an
7117 output-reload, see if we can prove there was
7118 actually no need to store the old value in it. */
7121 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
7122 that there may be multiple uses of the previous output reload.
7123 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7124 && rl->when_needed == RELOAD_FOR_INPUT
7125 && (reload_inherited[j] || reload_override_in[j])
7127 && REG_P (rl->reg_rtx)
7128 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7130 /* There doesn't seem to be any reason to restrict this to pseudos
7131 and doing so loses in the case where we are copying from a
7132 register of the wrong class. */
7133 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7134 >= FIRST_PSEUDO_REGISTER)
7136 /* The insn might have already some references to stackslots
7137 replaced by MEMs, while reload_out_reg still names the
7139 && (dead_or_set_p (insn,
7140 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7141 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7143 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7146 /* Do output reloading for reload RL, which is for the insn described by
7147 CHAIN and has the number J.
7148 ??? At some point we need to support handling output reloads of
7149 JUMP_INSNs or insns that set cc0. */
7151 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7154 rtx insn = chain->insn;
7155 /* If this is an output reload that stores something that is
7156 not loaded in this same reload, see if we can eliminate a previous
7158 rtx pseudo = rl->out_reg;
7163 && ! rtx_equal_p (rl->in_reg, pseudo)
7164 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7165 && reg_last_reload_reg[REGNO (pseudo)])
7167 int pseudo_no = REGNO (pseudo);
7168 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7170 /* We don't need to test full validity of last_regno for
7171 inherit here; we only want to know if the store actually
7172 matches the pseudo. */
7173 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7174 && reg_reloaded_contents[last_regno] == pseudo_no
7175 && spill_reg_store[last_regno]
7176 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7177 delete_output_reload (insn, j, last_regno);
7182 || rl->reg_rtx == old
7183 || rl->reg_rtx == 0)
7186 /* An output operand that dies right away does need a reload,
7187 but need not be copied from it. Show the new location in the
7189 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7190 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7192 XEXP (note, 0) = rl->reg_rtx;
7195 /* Likewise for a SUBREG of an operand that dies. */
7196 else if (GET_CODE (old) == SUBREG
7197 && REG_P (SUBREG_REG (old))
7198 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7201 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7205 else if (GET_CODE (old) == SCRATCH)
7206 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7207 but we don't want to make an output reload. */
7210 /* If is a JUMP_INSN, we can't support output reloads yet. */
7211 gcc_assert (NONJUMP_INSN_P (insn));
7213 emit_output_reload_insns (chain, rld + j, j);
7216 /* Reload number R reloads from or to a group of hard registers starting at
7217 register REGNO. Return true if it can be treated for inheritance purposes
7218 like a group of reloads, each one reloading a single hard register.
7219 The caller has already checked that the spill register and REGNO use
7220 the same number of registers to store the reload value. */
7223 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7225 #ifdef CANNOT_CHANGE_MODE_CLASS
7226 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7227 GET_MODE (rld[r].reg_rtx),
7228 reg_raw_mode[reload_spill_index[r]])
7229 && !REG_CANNOT_CHANGE_MODE_P (regno,
7230 GET_MODE (rld[r].reg_rtx),
7231 reg_raw_mode[regno]));
7237 /* Output insns to reload values in and out of the chosen reload regs. */
7240 emit_reload_insns (struct insn_chain *chain)
7242 rtx insn = chain->insn;
7246 CLEAR_HARD_REG_SET (reg_reloaded_died);
7248 for (j = 0; j < reload_n_operands; j++)
7249 input_reload_insns[j] = input_address_reload_insns[j]
7250 = inpaddr_address_reload_insns[j]
7251 = output_reload_insns[j] = output_address_reload_insns[j]
7252 = outaddr_address_reload_insns[j]
7253 = other_output_reload_insns[j] = 0;
7254 other_input_address_reload_insns = 0;
7255 other_input_reload_insns = 0;
7256 operand_reload_insns = 0;
7257 other_operand_reload_insns = 0;
7259 /* Dump reloads into the dump file. */
7262 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7263 debug_reload_to_stream (dump_file);
7266 /* Now output the instructions to copy the data into and out of the
7267 reload registers. Do these in the order that the reloads were reported,
7268 since reloads of base and index registers precede reloads of operands
7269 and the operands may need the base and index registers reloaded. */
7271 for (j = 0; j < n_reloads; j++)
7274 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7275 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7277 do_input_reload (chain, rld + j, j);
7278 do_output_reload (chain, rld + j, j);
7281 /* Now write all the insns we made for reloads in the order expected by
7282 the allocation functions. Prior to the insn being reloaded, we write
7283 the following reloads:
7285 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7287 RELOAD_OTHER reloads.
7289 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7290 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7291 RELOAD_FOR_INPUT reload for the operand.
7293 RELOAD_FOR_OPADDR_ADDRS reloads.
7295 RELOAD_FOR_OPERAND_ADDRESS reloads.
7297 After the insn being reloaded, we write the following:
7299 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7300 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7301 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7302 reloads for the operand. The RELOAD_OTHER output reloads are
7303 output in descending order by reload number. */
7305 emit_insn_before (other_input_address_reload_insns, insn);
7306 emit_insn_before (other_input_reload_insns, insn);
7308 for (j = 0; j < reload_n_operands; j++)
7310 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7311 emit_insn_before (input_address_reload_insns[j], insn);
7312 emit_insn_before (input_reload_insns[j], insn);
7315 emit_insn_before (other_operand_reload_insns, insn);
7316 emit_insn_before (operand_reload_insns, insn);
7318 for (j = 0; j < reload_n_operands; j++)
7320 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7321 x = emit_insn_after (output_address_reload_insns[j], x);
7322 x = emit_insn_after (output_reload_insns[j], x);
7323 emit_insn_after (other_output_reload_insns[j], x);
7326 /* For all the spill regs newly reloaded in this instruction,
7327 record what they were reloaded from, so subsequent instructions
7328 can inherit the reloads.
7330 Update spill_reg_store for the reloads of this insn.
7331 Copy the elements that were updated in the loop above. */
7333 for (j = 0; j < n_reloads; j++)
7335 int r = reload_order[j];
7336 int i = reload_spill_index[r];
7338 /* If this is a non-inherited input reload from a pseudo, we must
7339 clear any memory of a previous store to the same pseudo. Only do
7340 something if there will not be an output reload for the pseudo
7342 if (rld[r].in_reg != 0
7343 && ! (reload_inherited[r] || reload_override_in[r]))
7345 rtx reg = rld[r].in_reg;
7347 if (GET_CODE (reg) == SUBREG)
7348 reg = SUBREG_REG (reg);
7351 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7352 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7354 int nregno = REGNO (reg);
7356 if (reg_last_reload_reg[nregno])
7358 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7360 if (reg_reloaded_contents[last_regno] == nregno)
7361 spill_reg_store[last_regno] = 0;
7366 /* I is nonneg if this reload used a register.
7367 If rld[r].reg_rtx is 0, this is an optional reload
7368 that we opted to ignore. */
7370 if (i >= 0 && rld[r].reg_rtx != 0)
7372 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7374 int part_reaches_end = 0;
7375 int all_reaches_end = 1;
7377 /* For a multi register reload, we need to check if all or part
7378 of the value lives to the end. */
7379 for (k = 0; k < nr; k++)
7381 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7382 rld[r].when_needed))
7383 part_reaches_end = 1;
7385 all_reaches_end = 0;
7388 /* Ignore reloads that don't reach the end of the insn in
7390 if (all_reaches_end)
7392 /* First, clear out memory of what used to be in this spill reg.
7393 If consecutive registers are used, clear them all. */
7395 for (k = 0; k < nr; k++)
7397 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7398 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7401 /* Maybe the spill reg contains a copy of reload_out. */
7403 && (REG_P (rld[r].out)
7407 || REG_P (rld[r].out_reg)))
7409 rtx out = (REG_P (rld[r].out)
7413 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7414 int nregno = REGNO (out);
7415 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7416 : hard_regno_nregs[nregno]
7417 [GET_MODE (rld[r].reg_rtx)]);
7420 spill_reg_store[i] = new_spill_reg_store[i];
7421 spill_reg_stored_to[i] = out;
7422 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7424 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7426 && inherit_piecemeal_p (r, nregno));
7428 /* If NREGNO is a hard register, it may occupy more than
7429 one register. If it does, say what is in the
7430 rest of the registers assuming that both registers
7431 agree on how many words the object takes. If not,
7432 invalidate the subsequent registers. */
7434 if (nregno < FIRST_PSEUDO_REGISTER)
7435 for (k = 1; k < nnr; k++)
7436 reg_last_reload_reg[nregno + k]
7438 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7441 /* Now do the inverse operation. */
7442 for (k = 0; k < nr; k++)
7444 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7445 reg_reloaded_contents[i + k]
7446 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7449 reg_reloaded_insn[i + k] = insn;
7450 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7451 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7452 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7456 /* Maybe the spill reg contains a copy of reload_in. Only do
7457 something if there will not be an output reload for
7458 the register being reloaded. */
7459 else if (rld[r].out_reg == 0
7461 && ((REG_P (rld[r].in)
7462 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7463 && !REGNO_REG_SET_P (®_has_output_reload,
7465 || (REG_P (rld[r].in_reg)
7466 && !REGNO_REG_SET_P (®_has_output_reload,
7467 REGNO (rld[r].in_reg))))
7468 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7475 if (REG_P (rld[r].in)
7476 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7478 else if (REG_P (rld[r].in_reg))
7481 in = XEXP (rld[r].in_reg, 0);
7482 nregno = REGNO (in);
7484 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7485 : hard_regno_nregs[nregno]
7486 [GET_MODE (rld[r].reg_rtx)]);
7488 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7490 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7492 && inherit_piecemeal_p (r, nregno));
7494 if (nregno < FIRST_PSEUDO_REGISTER)
7495 for (k = 1; k < nnr; k++)
7496 reg_last_reload_reg[nregno + k]
7498 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7501 /* Unless we inherited this reload, show we haven't
7502 recently done a store.
7503 Previous stores of inherited auto_inc expressions
7504 also have to be discarded. */
7505 if (! reload_inherited[r]
7506 || (rld[r].out && ! rld[r].out_reg))
7507 spill_reg_store[i] = 0;
7509 for (k = 0; k < nr; k++)
7511 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7512 reg_reloaded_contents[i + k]
7513 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7516 reg_reloaded_insn[i + k] = insn;
7517 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7518 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7519 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7524 /* However, if part of the reload reaches the end, then we must
7525 invalidate the old info for the part that survives to the end. */
7526 else if (part_reaches_end)
7528 for (k = 0; k < nr; k++)
7529 if (reload_reg_reaches_end_p (i + k,
7531 rld[r].when_needed))
7532 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7536 /* The following if-statement was #if 0'd in 1.34 (or before...).
7537 It's reenabled in 1.35 because supposedly nothing else
7538 deals with this problem. */
7540 /* If a register gets output-reloaded from a non-spill register,
7541 that invalidates any previous reloaded copy of it.
7542 But forget_old_reloads_1 won't get to see it, because
7543 it thinks only about the original insn. So invalidate it here.
7544 Also do the same thing for RELOAD_OTHER constraints where the
7545 output is discarded. */
7547 && ((rld[r].out != 0
7548 && (REG_P (rld[r].out)
7549 || (MEM_P (rld[r].out)
7550 && REG_P (rld[r].out_reg))))
7551 || (rld[r].out == 0 && rld[r].out_reg
7552 && REG_P (rld[r].out_reg))))
7554 rtx out = ((rld[r].out && REG_P (rld[r].out))
7555 ? rld[r].out : rld[r].out_reg);
7556 int nregno = REGNO (out);
7557 if (nregno >= FIRST_PSEUDO_REGISTER)
7559 rtx src_reg, store_insn = NULL_RTX;
7561 reg_last_reload_reg[nregno] = 0;
7563 /* If we can find a hard register that is stored, record
7564 the storing insn so that we may delete this insn with
7565 delete_output_reload. */
7566 src_reg = rld[r].reg_rtx;
7568 /* If this is an optional reload, try to find the source reg
7569 from an input reload. */
7572 rtx set = single_set (insn);
7573 if (set && SET_DEST (set) == rld[r].out)
7577 src_reg = SET_SRC (set);
7579 for (k = 0; k < n_reloads; k++)
7581 if (rld[k].in == src_reg)
7583 src_reg = rld[k].reg_rtx;
7590 store_insn = new_spill_reg_store[REGNO (src_reg)];
7591 if (src_reg && REG_P (src_reg)
7592 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7594 int src_regno = REGNO (src_reg);
7595 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7596 /* The place where to find a death note varies with
7597 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7598 necessarily checked exactly in the code that moves
7599 notes, so just check both locations. */
7600 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7601 if (! note && store_insn)
7602 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7605 spill_reg_store[src_regno + nr] = store_insn;
7606 spill_reg_stored_to[src_regno + nr] = out;
7607 reg_reloaded_contents[src_regno + nr] = nregno;
7608 reg_reloaded_insn[src_regno + nr] = store_insn;
7609 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7610 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7611 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7612 GET_MODE (src_reg)))
7613 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7615 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7617 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7619 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7621 reg_last_reload_reg[nregno] = src_reg;
7622 /* We have to set reg_has_output_reload here, or else
7623 forget_old_reloads_1 will clear reg_last_reload_reg
7625 SET_REGNO_REG_SET (®_has_output_reload,
7631 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7633 while (num_regs-- > 0)
7634 reg_last_reload_reg[nregno + num_regs] = 0;
7638 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7641 /* Go through the motions to emit INSN and test if it is strictly valid.
7642 Return the emitted insn if valid, else return NULL. */
7645 emit_insn_if_valid_for_reload (rtx insn)
7647 rtx last = get_last_insn ();
7650 insn = emit_insn (insn);
7651 code = recog_memoized (insn);
7655 extract_insn (insn);
7656 /* We want constrain operands to treat this insn strictly in its
7657 validity determination, i.e., the way it would after reload has
7659 if (constrain_operands (1))
7663 delete_insns_since (last);
7667 /* Emit code to perform a reload from IN (which may be a reload register) to
7668 OUT (which may also be a reload register). IN or OUT is from operand
7669 OPNUM with reload type TYPE.
7671 Returns first insn emitted. */
7674 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7676 rtx last = get_last_insn ();
7679 /* If IN is a paradoxical SUBREG, remove it and try to put the
7680 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7681 if (GET_CODE (in) == SUBREG
7682 && (GET_MODE_SIZE (GET_MODE (in))
7683 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7684 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7685 in = SUBREG_REG (in), out = tem;
7686 else if (GET_CODE (out) == SUBREG
7687 && (GET_MODE_SIZE (GET_MODE (out))
7688 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7689 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7690 out = SUBREG_REG (out), in = tem;
7692 /* How to do this reload can get quite tricky. Normally, we are being
7693 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7694 register that didn't get a hard register. In that case we can just
7695 call emit_move_insn.
7697 We can also be asked to reload a PLUS that adds a register or a MEM to
7698 another register, constant or MEM. This can occur during frame pointer
7699 elimination and while reloading addresses. This case is handled by
7700 trying to emit a single insn to perform the add. If it is not valid,
7701 we use a two insn sequence.
7703 Or we can be asked to reload an unary operand that was a fragment of
7704 an addressing mode, into a register. If it isn't recognized as-is,
7705 we try making the unop operand and the reload-register the same:
7706 (set reg:X (unop:X expr:Y))
7707 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7709 Finally, we could be called to handle an 'o' constraint by putting
7710 an address into a register. In that case, we first try to do this
7711 with a named pattern of "reload_load_address". If no such pattern
7712 exists, we just emit a SET insn and hope for the best (it will normally
7713 be valid on machines that use 'o').
7715 This entire process is made complex because reload will never
7716 process the insns we generate here and so we must ensure that
7717 they will fit their constraints and also by the fact that parts of
7718 IN might be being reloaded separately and replaced with spill registers.
7719 Because of this, we are, in some sense, just guessing the right approach
7720 here. The one listed above seems to work.
7722 ??? At some point, this whole thing needs to be rethought. */
7724 if (GET_CODE (in) == PLUS
7725 && (REG_P (XEXP (in, 0))
7726 || GET_CODE (XEXP (in, 0)) == SUBREG
7727 || MEM_P (XEXP (in, 0)))
7728 && (REG_P (XEXP (in, 1))
7729 || GET_CODE (XEXP (in, 1)) == SUBREG
7730 || CONSTANT_P (XEXP (in, 1))
7731 || MEM_P (XEXP (in, 1))))
7733 /* We need to compute the sum of a register or a MEM and another
7734 register, constant, or MEM, and put it into the reload
7735 register. The best possible way of doing this is if the machine
7736 has a three-operand ADD insn that accepts the required operands.
7738 The simplest approach is to try to generate such an insn and see if it
7739 is recognized and matches its constraints. If so, it can be used.
7741 It might be better not to actually emit the insn unless it is valid,
7742 but we need to pass the insn as an operand to `recog' and
7743 `extract_insn' and it is simpler to emit and then delete the insn if
7744 not valid than to dummy things up. */
7746 rtx op0, op1, tem, insn;
7749 op0 = find_replacement (&XEXP (in, 0));
7750 op1 = find_replacement (&XEXP (in, 1));
7752 /* Since constraint checking is strict, commutativity won't be
7753 checked, so we need to do that here to avoid spurious failure
7754 if the add instruction is two-address and the second operand
7755 of the add is the same as the reload reg, which is frequently
7756 the case. If the insn would be A = B + A, rearrange it so
7757 it will be A = A + B as constrain_operands expects. */
7759 if (REG_P (XEXP (in, 1))
7760 && REGNO (out) == REGNO (XEXP (in, 1)))
7761 tem = op0, op0 = op1, op1 = tem;
7763 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7764 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7766 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7770 /* If that failed, we must use a conservative two-insn sequence.
7772 Use a move to copy one operand into the reload register. Prefer
7773 to reload a constant, MEM or pseudo since the move patterns can
7774 handle an arbitrary operand. If OP1 is not a constant, MEM or
7775 pseudo and OP1 is not a valid operand for an add instruction, then
7778 After reloading one of the operands into the reload register, add
7779 the reload register to the output register.
7781 If there is another way to do this for a specific machine, a
7782 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7785 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7787 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7789 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7790 || (code != CODE_FOR_nothing
7791 && ! ((*insn_data[code].operand[2].predicate)
7792 (op1, insn_data[code].operand[2].mode))))
7793 tem = op0, op0 = op1, op1 = tem;
7795 gen_reload (out, op0, opnum, type);
7797 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7798 This fixes a problem on the 32K where the stack pointer cannot
7799 be used as an operand of an add insn. */
7801 if (rtx_equal_p (op0, op1))
7804 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7807 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7809 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7813 /* If that failed, copy the address register to the reload register.
7814 Then add the constant to the reload register. */
7816 gen_reload (out, op1, opnum, type);
7817 insn = emit_insn (gen_add2_insn (out, op0));
7818 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7821 #ifdef SECONDARY_MEMORY_NEEDED
7822 /* If we need a memory location to do the move, do it that way. */
7823 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7824 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7825 && (REG_P (out) || GET_CODE (out) == SUBREG)
7826 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7827 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7828 REGNO_REG_CLASS (reg_or_subregno (out)),
7831 /* Get the memory to use and rewrite both registers to its mode. */
7832 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7834 if (GET_MODE (loc) != GET_MODE (out))
7835 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7837 if (GET_MODE (loc) != GET_MODE (in))
7838 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7840 gen_reload (loc, in, opnum, type);
7841 gen_reload (out, loc, opnum, type);
7844 else if (REG_P (out) && UNARY_P (in))
7851 op1 = find_replacement (&XEXP (in, 0));
7852 if (op1 != XEXP (in, 0))
7853 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7855 /* First, try a plain SET. */
7856 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7860 /* If that failed, move the inner operand to the reload
7861 register, and try the same unop with the inner expression
7862 replaced with the reload register. */
7864 if (GET_MODE (op1) != GET_MODE (out))
7865 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7869 gen_reload (out_moded, op1, opnum, type);
7872 = gen_rtx_SET (VOIDmode, out,
7873 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7875 insn = emit_insn_if_valid_for_reload (insn);
7879 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7883 fatal_insn ("Failure trying to reload:", set);
7885 /* If IN is a simple operand, use gen_move_insn. */
7886 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7888 tem = emit_insn (gen_move_insn (out, in));
7889 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
7890 mark_jump_label (in, tem, 0);
7893 #ifdef HAVE_reload_load_address
7894 else if (HAVE_reload_load_address)
7895 emit_insn (gen_reload_load_address (out, in));
7898 /* Otherwise, just write (set OUT IN) and hope for the best. */
7900 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7902 /* Return the first insn emitted.
7903 We can not just return get_last_insn, because there may have
7904 been multiple instructions emitted. Also note that gen_move_insn may
7905 emit more than one insn itself, so we can not assume that there is one
7906 insn emitted per emit_insn_before call. */
7908 return last ? NEXT_INSN (last) : get_insns ();
7911 /* Delete a previously made output-reload whose result we now believe
7912 is not needed. First we double-check.
7914 INSN is the insn now being processed.
7915 LAST_RELOAD_REG is the hard register number for which we want to delete
7916 the last output reload.
7917 J is the reload-number that originally used REG. The caller has made
7918 certain that reload J doesn't use REG any longer for input. */
7921 delete_output_reload (rtx insn, int j, int last_reload_reg)
7923 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7924 rtx reg = spill_reg_stored_to[last_reload_reg];
7927 int n_inherited = 0;
7931 /* It is possible that this reload has been only used to set another reload
7932 we eliminated earlier and thus deleted this instruction too. */
7933 if (INSN_DELETED_P (output_reload_insn))
7936 /* Get the raw pseudo-register referred to. */
7938 while (GET_CODE (reg) == SUBREG)
7939 reg = SUBREG_REG (reg);
7940 substed = reg_equiv_memory_loc[REGNO (reg)];
7942 /* This is unsafe if the operand occurs more often in the current
7943 insn than it is inherited. */
7944 for (k = n_reloads - 1; k >= 0; k--)
7946 rtx reg2 = rld[k].in;
7949 if (MEM_P (reg2) || reload_override_in[k])
7950 reg2 = rld[k].in_reg;
7952 if (rld[k].out && ! rld[k].out_reg)
7953 reg2 = XEXP (rld[k].in_reg, 0);
7955 while (GET_CODE (reg2) == SUBREG)
7956 reg2 = SUBREG_REG (reg2);
7957 if (rtx_equal_p (reg2, reg))
7959 if (reload_inherited[k] || reload_override_in[k] || k == j)
7962 reg2 = rld[k].out_reg;
7965 while (GET_CODE (reg2) == SUBREG)
7966 reg2 = XEXP (reg2, 0);
7967 if (rtx_equal_p (reg2, reg))
7974 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7976 n_occurrences += count_occurrences (PATTERN (insn),
7977 eliminate_regs (substed, 0,
7979 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
7981 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
7982 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
7984 if (n_occurrences > n_inherited)
7987 /* If the pseudo-reg we are reloading is no longer referenced
7988 anywhere between the store into it and here,
7989 and we're within the same basic block, then the value can only
7990 pass through the reload reg and end up here.
7991 Otherwise, give up--return. */
7992 for (i1 = NEXT_INSN (output_reload_insn);
7993 i1 != insn; i1 = NEXT_INSN (i1))
7995 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7997 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7998 && reg_mentioned_p (reg, PATTERN (i1)))
8000 /* If this is USE in front of INSN, we only have to check that
8001 there are no more references than accounted for by inheritance. */
8002 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8004 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8005 i1 = NEXT_INSN (i1);
8007 if (n_occurrences <= n_inherited && i1 == insn)
8013 /* We will be deleting the insn. Remove the spill reg information. */
8014 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8016 spill_reg_store[last_reload_reg + k] = 0;
8017 spill_reg_stored_to[last_reload_reg + k] = 0;
8020 /* The caller has already checked that REG dies or is set in INSN.
8021 It has also checked that we are optimizing, and thus some
8022 inaccuracies in the debugging information are acceptable.
8023 So we could just delete output_reload_insn. But in some cases
8024 we can improve the debugging information without sacrificing
8025 optimization - maybe even improving the code: See if the pseudo
8026 reg has been completely replaced with reload regs. If so, delete
8027 the store insn and forget we had a stack slot for the pseudo. */
8028 if (rld[j].out != rld[j].in
8029 && REG_N_DEATHS (REGNO (reg)) == 1
8030 && REG_N_SETS (REGNO (reg)) == 1
8031 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
8032 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8036 /* We know that it was used only between here and the beginning of
8037 the current basic block. (We also know that the last use before
8038 INSN was the output reload we are thinking of deleting, but never
8039 mind that.) Search that range; see if any ref remains. */
8040 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8042 rtx set = single_set (i2);
8044 /* Uses which just store in the pseudo don't count,
8045 since if they are the only uses, they are dead. */
8046 if (set != 0 && SET_DEST (set) == reg)
8051 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8052 && reg_mentioned_p (reg, PATTERN (i2)))
8054 /* Some other ref remains; just delete the output reload we
8056 delete_address_reloads (output_reload_insn, insn);
8057 delete_insn (output_reload_insn);
8062 /* Delete the now-dead stores into this pseudo. Note that this
8063 loop also takes care of deleting output_reload_insn. */
8064 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8066 rtx set = single_set (i2);
8068 if (set != 0 && SET_DEST (set) == reg)
8070 delete_address_reloads (i2, insn);
8078 /* For the debugging info, say the pseudo lives in this reload reg. */
8079 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8080 alter_reg (REGNO (reg), -1);
8084 delete_address_reloads (output_reload_insn, insn);
8085 delete_insn (output_reload_insn);
8089 /* We are going to delete DEAD_INSN. Recursively delete loads of
8090 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8091 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8093 delete_address_reloads (rtx dead_insn, rtx current_insn)
8095 rtx set = single_set (dead_insn);
8096 rtx set2, dst, prev, next;
8099 rtx dst = SET_DEST (set);
8101 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8103 /* If we deleted the store from a reloaded post_{in,de}c expression,
8104 we can delete the matching adds. */
8105 prev = PREV_INSN (dead_insn);
8106 next = NEXT_INSN (dead_insn);
8107 if (! prev || ! next)
8109 set = single_set (next);
8110 set2 = single_set (prev);
8112 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8113 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8114 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8116 dst = SET_DEST (set);
8117 if (! rtx_equal_p (dst, SET_DEST (set2))
8118 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8119 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8120 || (INTVAL (XEXP (SET_SRC (set), 1))
8121 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8123 delete_related_insns (prev);
8124 delete_related_insns (next);
8127 /* Subfunction of delete_address_reloads: process registers found in X. */
8129 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8131 rtx prev, set, dst, i2;
8133 enum rtx_code code = GET_CODE (x);
8137 const char *fmt = GET_RTX_FORMAT (code);
8138 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8141 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8142 else if (fmt[i] == 'E')
8144 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8145 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8152 if (spill_reg_order[REGNO (x)] < 0)
8155 /* Scan backwards for the insn that sets x. This might be a way back due
8157 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8159 code = GET_CODE (prev);
8160 if (code == CODE_LABEL || code == JUMP_INSN)
8164 if (reg_set_p (x, PATTERN (prev)))
8166 if (reg_referenced_p (x, PATTERN (prev)))
8169 if (! prev || INSN_UID (prev) < reload_first_uid)
8171 /* Check that PREV only sets the reload register. */
8172 set = single_set (prev);
8175 dst = SET_DEST (set);
8177 || ! rtx_equal_p (dst, x))
8179 if (! reg_set_p (dst, PATTERN (dead_insn)))
8181 /* Check if DST was used in a later insn -
8182 it might have been inherited. */
8183 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8189 if (reg_referenced_p (dst, PATTERN (i2)))
8191 /* If there is a reference to the register in the current insn,
8192 it might be loaded in a non-inherited reload. If no other
8193 reload uses it, that means the register is set before
8195 if (i2 == current_insn)
8197 for (j = n_reloads - 1; j >= 0; j--)
8198 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8199 || reload_override_in[j] == dst)
8201 for (j = n_reloads - 1; j >= 0; j--)
8202 if (rld[j].in && rld[j].reg_rtx == dst)
8211 /* If DST is still live at CURRENT_INSN, check if it is used for
8212 any reload. Note that even if CURRENT_INSN sets DST, we still
8213 have to check the reloads. */
8214 if (i2 == current_insn)
8216 for (j = n_reloads - 1; j >= 0; j--)
8217 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8218 || reload_override_in[j] == dst)
8220 /* ??? We can't finish the loop here, because dst might be
8221 allocated to a pseudo in this block if no reload in this
8222 block needs any of the classes containing DST - see
8223 spill_hard_reg. There is no easy way to tell this, so we
8224 have to scan till the end of the basic block. */
8226 if (reg_set_p (dst, PATTERN (i2)))
8230 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8231 reg_reloaded_contents[REGNO (dst)] = -1;
8235 /* Output reload-insns to reload VALUE into RELOADREG.
8236 VALUE is an autoincrement or autodecrement RTX whose operand
8237 is a register or memory location;
8238 so reloading involves incrementing that location.
8239 IN is either identical to VALUE, or some cheaper place to reload from.
8241 INC_AMOUNT is the number to increment or decrement by (always positive).
8242 This cannot be deduced from VALUE.
8244 Return the instruction that stores into RELOADREG. */
8247 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8249 /* REG or MEM to be copied and incremented. */
8250 rtx incloc = find_replacement (&XEXP (value, 0));
8251 /* Nonzero if increment after copying. */
8252 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8253 || GET_CODE (value) == POST_MODIFY);
8259 rtx real_in = in == value ? incloc : in;
8261 /* No hard register is equivalent to this register after
8262 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8263 we could inc/dec that register as well (maybe even using it for
8264 the source), but I'm not sure it's worth worrying about. */
8266 reg_last_reload_reg[REGNO (incloc)] = 0;
8268 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8270 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8271 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8275 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8276 inc_amount = -inc_amount;
8278 inc = GEN_INT (inc_amount);
8281 /* If this is post-increment, first copy the location to the reload reg. */
8282 if (post && real_in != reloadreg)
8283 emit_insn (gen_move_insn (reloadreg, real_in));
8287 /* See if we can directly increment INCLOC. Use a method similar to
8288 that in gen_reload. */
8290 last = get_last_insn ();
8291 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8292 gen_rtx_PLUS (GET_MODE (incloc),
8295 code = recog_memoized (add_insn);
8298 extract_insn (add_insn);
8299 if (constrain_operands (1))
8301 /* If this is a pre-increment and we have incremented the value
8302 where it lives, copy the incremented value to RELOADREG to
8303 be used as an address. */
8306 emit_insn (gen_move_insn (reloadreg, incloc));
8311 delete_insns_since (last);
8314 /* If couldn't do the increment directly, must increment in RELOADREG.
8315 The way we do this depends on whether this is pre- or post-increment.
8316 For pre-increment, copy INCLOC to the reload register, increment it
8317 there, then save back. */
8321 if (in != reloadreg)
8322 emit_insn (gen_move_insn (reloadreg, real_in));
8323 emit_insn (gen_add2_insn (reloadreg, inc));
8324 store = emit_insn (gen_move_insn (incloc, reloadreg));
8329 Because this might be a jump insn or a compare, and because RELOADREG
8330 may not be available after the insn in an input reload, we must do
8331 the incrementation before the insn being reloaded for.
8333 We have already copied IN to RELOADREG. Increment the copy in
8334 RELOADREG, save that back, then decrement RELOADREG so it has
8335 the original value. */
8337 emit_insn (gen_add2_insn (reloadreg, inc));
8338 store = emit_insn (gen_move_insn (incloc, reloadreg));
8339 if (GET_CODE (inc) == CONST_INT)
8340 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8342 emit_insn (gen_sub2_insn (reloadreg, inc));
8350 add_auto_inc_notes (rtx insn, rtx x)
8352 enum rtx_code code = GET_CODE (x);
8356 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8359 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8363 /* Scan all the operand sub-expressions. */
8364 fmt = GET_RTX_FORMAT (code);
8365 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8368 add_auto_inc_notes (insn, XEXP (x, i));
8369 else if (fmt[i] == 'E')
8370 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8371 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8376 /* Copy EH notes from an insn to its reloads. */
8378 copy_eh_notes (rtx insn, rtx x)
8380 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8383 for (; x != 0; x = NEXT_INSN (x))
8385 if (may_trap_p (PATTERN (x)))
8387 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8393 /* This is used by reload pass, that does emit some instructions after
8394 abnormal calls moving basic block end, but in fact it wants to emit
8395 them on the edge. Looks for abnormal call edges, find backward the
8396 proper call and fix the damage.
8398 Similar handle instructions throwing exceptions internally. */
8400 fixup_abnormal_edges (void)
8402 bool inserted = false;
8410 /* Look for cases we are interested in - calls or instructions causing
8412 FOR_EACH_EDGE (e, ei, bb->succs)
8414 if (e->flags & EDGE_ABNORMAL_CALL)
8416 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8417 == (EDGE_ABNORMAL | EDGE_EH))
8420 if (e && !CALL_P (BB_END (bb))
8421 && !can_throw_internal (BB_END (bb)))
8425 /* Get past the new insns generated. Allow notes, as the insns
8426 may be already deleted. */
8428 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8429 && !can_throw_internal (insn)
8430 && insn != BB_HEAD (bb))
8431 insn = PREV_INSN (insn);
8433 if (CALL_P (insn) || can_throw_internal (insn))
8437 stop = NEXT_INSN (BB_END (bb));
8439 insn = NEXT_INSN (insn);
8441 FOR_EACH_EDGE (e, ei, bb->succs)
8442 if (e->flags & EDGE_FALLTHRU)
8445 while (insn && insn != stop)
8447 next = NEXT_INSN (insn);
8452 /* Sometimes there's still the return value USE.
8453 If it's placed after a trapping call (i.e. that
8454 call is the last insn anyway), we have no fallthru
8455 edge. Simply delete this use and don't try to insert
8456 on the non-existent edge. */
8457 if (GET_CODE (PATTERN (insn)) != USE)
8459 /* We're not deleting it, we're moving it. */
8460 INSN_DELETED_P (insn) = 0;
8461 PREV_INSN (insn) = NULL_RTX;
8462 NEXT_INSN (insn) = NULL_RTX;
8464 insert_insn_on_edge (insn, e);
8472 /* It may be that we don't find any such trapping insn. In this
8473 case we discovered quite late that the insn that had been
8474 marked as can_throw_internal in fact couldn't trap at all.
8475 So we should in fact delete the EH edges out of the block. */
8477 purge_dead_edges (bb);
8481 /* We've possibly turned single trapping insn into multiple ones. */
8482 if (flag_non_call_exceptions)
8485 blocks = sbitmap_alloc (last_basic_block);
8486 sbitmap_ones (blocks);
8487 find_many_sub_basic_blocks (blocks);
8491 commit_edge_insertions ();
8493 #ifdef ENABLE_CHECKING
8494 /* Verify that we didn't turn one trapping insn into many, and that
8495 we found and corrected all of the problems wrt fixups on the
8497 verify_flow_info ();
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