1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 struct target_reload default_target_reload;
87 struct target_reload *this_target_reload = &default_target_reload;
90 #define spill_indirect_levels \
91 (this_target_reload->x_spill_indirect_levels)
93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
94 into which reg N has been reloaded (perhaps for a previous insn). */
95 static rtx *reg_last_reload_reg;
97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
98 for an output reload that stores into reg N. */
99 static regset_head reg_has_output_reload;
101 /* Indicates which hard regs are reload-registers for an output reload
102 in the current insn. */
103 static HARD_REG_SET reg_is_output_reload;
105 /* Widest width in which each pseudo reg is referred to (via subreg). */
106 static unsigned int *reg_max_ref_width;
108 /* Vector to remember old contents of reg_renumber before spilling. */
109 static short *reg_old_renumber;
111 /* During reload_as_needed, element N contains the last pseudo regno reloaded
112 into hard register N. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
117 /* During reload_as_needed, element N contains the insn for which
118 hard register N was last used. Its contents are significant only
119 when reg_reloaded_valid is set for this register. */
120 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
122 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
123 static HARD_REG_SET reg_reloaded_valid;
124 /* Indicate if the register was dead at the end of the reload.
125 This is only valid if reg_reloaded_contents is set and valid. */
126 static HARD_REG_SET reg_reloaded_dead;
128 /* Indicate whether the register's current value is one that is not
129 safe to retain across a call, even for registers that are normally
130 call-saved. This is only meaningful for members of reg_reloaded_valid. */
131 static HARD_REG_SET reg_reloaded_call_part_clobbered;
133 /* Number of spill-regs so far; number of valid elements of spill_regs. */
136 /* In parallel with spill_regs, contains REG rtx's for those regs.
137 Holds the last rtx used for any given reg, or 0 if it has never
138 been used for spilling yet. This rtx is reused, provided it has
140 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
142 /* In parallel with spill_regs, contains nonzero for a spill reg
143 that was stored after the last time it was used.
144 The precise value is the insn generated to do the store. */
145 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
147 /* This is the register that was stored with spill_reg_store. This is a
148 copy of reload_out / reload_out_reg when the value was stored; if
149 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
150 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
152 /* This table is the inverse mapping of spill_regs:
153 indexed by hard reg number,
154 it contains the position of that reg in spill_regs,
155 or -1 for something that is not in spill_regs.
157 ?!? This is no longer accurate. */
158 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
160 /* This reg set indicates registers that can't be used as spill registers for
161 the currently processed insn. These are the hard registers which are live
162 during the insn, but not allocated to pseudos, as well as fixed
164 static HARD_REG_SET bad_spill_regs;
166 /* These are the hard registers that can't be used as spill register for any
167 insn. This includes registers used for user variables and registers that
168 we can't eliminate. A register that appears in this set also can't be used
169 to retry register allocation. */
170 static HARD_REG_SET bad_spill_regs_global;
172 /* Describes order of use of registers for reloading
173 of spilled pseudo-registers. `n_spills' is the number of
174 elements that are actually valid; new ones are added at the end.
176 Both spill_regs and spill_reg_order are used on two occasions:
177 once during find_reload_regs, where they keep track of the spill registers
178 for a single insn, but also during reload_as_needed where they show all
179 the registers ever used by reload. For the latter case, the information
180 is calculated during finish_spills. */
181 static short spill_regs[FIRST_PSEUDO_REGISTER];
183 /* This vector of reg sets indicates, for each pseudo, which hard registers
184 may not be used for retrying global allocation because the register was
185 formerly spilled from one of them. If we allowed reallocating a pseudo to
186 a register that it was already allocated to, reload might not
188 static HARD_REG_SET *pseudo_previous_regs;
190 /* This vector of reg sets indicates, for each pseudo, which hard
191 registers may not be used for retrying global allocation because they
192 are used as spill registers during one of the insns in which the
194 static HARD_REG_SET *pseudo_forbidden_regs;
196 /* All hard regs that have been used as spill registers for any insn are
197 marked in this set. */
198 static HARD_REG_SET used_spill_regs;
200 /* Index of last register assigned as a spill register. We allocate in
201 a round-robin fashion. */
202 static int last_spill_reg;
204 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
207 /* Width allocated so far for that stack slot. */
208 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
210 /* Record which pseudos needed to be spilled. */
211 static regset_head spilled_pseudos;
213 /* Record which pseudos changed their allocation in finish_spills. */
214 static regset_head changed_allocation_pseudos;
216 /* Used for communication between order_regs_for_reload and count_pseudo.
217 Used to avoid counting one pseudo twice. */
218 static regset_head pseudos_counted;
220 /* First uid used by insns created by reload in this function.
221 Used in find_equiv_reg. */
222 int reload_first_uid;
224 /* Flag set by local-alloc or global-alloc if anything is live in
225 a call-clobbered reg across calls. */
226 int caller_save_needed;
228 /* Set to 1 while reload_as_needed is operating.
229 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress = 0;
232 /* This obstack is used for allocation of rtl during register elimination.
233 The allocated storage can be freed once find_reloads has processed the
235 static struct obstack reload_obstack;
237 /* Points to the beginning of the reload_obstack. All insn_chain structures
238 are allocated first. */
239 static char *reload_startobj;
241 /* The point after all insn_chain structures. Used to quickly deallocate
242 memory allocated in copy_reloads during calculate_needs_all_insns. */
243 static char *reload_firstobj;
245 /* This points before all local rtl generated by register elimination.
246 Used to quickly free all memory after processing one insn. */
247 static char *reload_insn_firstobj;
249 /* List of insn_chain instructions, one for every insn that reload needs to
251 struct insn_chain *reload_insn_chain;
253 /* TRUE if we potentially left dead insns in the insn stream and want to
254 run DCE immediately after reload, FALSE otherwise. */
255 static bool need_dce;
257 /* List of all insns needing reloads. */
258 static struct insn_chain *insns_need_reload;
260 /* This structure is used to record information about register eliminations.
261 Each array entry describes one possible way of eliminating a register
262 in favor of another. If there is more than one way of eliminating a
263 particular register, the most preferred should be specified first. */
267 int from; /* Register number to be eliminated. */
268 int to; /* Register number used as replacement. */
269 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
270 int can_eliminate; /* Nonzero if this elimination can be done. */
271 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
272 target hook in previous scan over insns
274 HOST_WIDE_INT offset; /* Current offset between the two regs. */
275 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
276 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
277 rtx from_rtx; /* REG rtx for the register to be eliminated.
278 We cannot simply compare the number since
279 we might then spuriously replace a hard
280 register corresponding to a pseudo
281 assigned to the reg to be eliminated. */
282 rtx to_rtx; /* REG rtx for the replacement. */
285 static struct elim_table *reg_eliminate = 0;
287 /* This is an intermediate structure to initialize the table. It has
288 exactly the members provided by ELIMINABLE_REGS. */
289 static const struct elim_table_1
293 } reg_eliminate_1[] =
295 /* If a set of eliminable registers was specified, define the table from it.
296 Otherwise, default to the normal case of the frame pointer being
297 replaced by the stack pointer. */
299 #ifdef ELIMINABLE_REGS
302 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
305 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
307 /* Record the number of pending eliminations that have an offset not equal
308 to their initial offset. If nonzero, we use a new copy of each
309 replacement result in any insns encountered. */
310 int num_not_at_initial_offset;
312 /* Count the number of registers that we may be able to eliminate. */
313 static int num_eliminable;
314 /* And the number of registers that are equivalent to a constant that
315 can be eliminated to frame_pointer / arg_pointer + constant. */
316 static int num_eliminable_invariants;
318 /* For each label, we record the offset of each elimination. If we reach
319 a label by more than one path and an offset differs, we cannot do the
320 elimination. This information is indexed by the difference of the
321 number of the label and the first label number. We can't offset the
322 pointer itself as this can cause problems on machines with segmented
323 memory. The first table is an array of flags that records whether we
324 have yet encountered a label and the second table is an array of arrays,
325 one entry in the latter array for each elimination. */
327 static int first_label_num;
328 static char *offsets_known_at;
329 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
331 VEC(reg_equivs_t,gc) *reg_equivs;
333 /* Stack of addresses where an rtx has been changed. We can undo the
334 changes by popping items off the stack and restoring the original
335 value at each location.
337 We use this simplistic undo capability rather than copy_rtx as copy_rtx
338 will not make a deep copy of a normally sharable rtx, such as
339 (const (plus (symbol_ref) (const_int))). If such an expression appears
340 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
341 rtx expression would be changed. See PR 42431. */
345 DEF_VEC_ALLOC_P(rtx_p,heap);
346 static VEC(rtx_p,heap) *substitute_stack;
348 /* Number of labels in the current function. */
350 static int num_labels;
352 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
353 static void maybe_fix_stack_asms (void);
354 static void copy_reloads (struct insn_chain *);
355 static void calculate_needs_all_insns (int);
356 static int find_reg (struct insn_chain *, int);
357 static void find_reload_regs (struct insn_chain *);
358 static void select_reload_regs (void);
359 static void delete_caller_save_insns (void);
361 static void spill_failure (rtx, enum reg_class);
362 static void count_spilled_pseudo (int, int, int);
363 static void delete_dead_insn (rtx);
364 static void alter_reg (int, int, bool);
365 static void set_label_offsets (rtx, rtx, int);
366 static void check_eliminable_occurrences (rtx);
367 static void elimination_effects (rtx, enum machine_mode);
368 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
369 static int eliminate_regs_in_insn (rtx, int);
370 static void update_eliminable_offsets (void);
371 static void mark_not_eliminable (rtx, const_rtx, void *);
372 static void set_initial_elim_offsets (void);
373 static bool verify_initial_elim_offsets (void);
374 static void set_initial_label_offsets (void);
375 static void set_offsets_for_label (rtx);
376 static void init_eliminable_invariants (rtx, bool);
377 static void init_elim_table (void);
378 static void free_reg_equiv (void);
379 static void update_eliminables (HARD_REG_SET *);
380 static void elimination_costs_in_insn (rtx);
381 static void spill_hard_reg (unsigned int, int);
382 static int finish_spills (int);
383 static void scan_paradoxical_subregs (rtx);
384 static void count_pseudo (int);
385 static void order_regs_for_reload (struct insn_chain *);
386 static void reload_as_needed (int);
387 static void forget_old_reloads_1 (rtx, const_rtx, void *);
388 static void forget_marked_reloads (regset);
389 static int reload_reg_class_lower (const void *, const void *);
390 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
392 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
394 static int reload_reg_free_p (unsigned int, int, enum reload_type);
395 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
397 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
399 static int allocate_reload_reg (struct insn_chain *, int, int);
400 static int conflicts_with_override (rtx);
401 static void failed_reload (rtx, int);
402 static int set_reload_reg (int, int);
403 static void choose_reload_regs_init (struct insn_chain *, rtx *);
404 static void choose_reload_regs (struct insn_chain *);
405 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
407 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
409 static void do_input_reload (struct insn_chain *, struct reload *, int);
410 static void do_output_reload (struct insn_chain *, struct reload *, int);
411 static void emit_reload_insns (struct insn_chain *);
412 static void delete_output_reload (rtx, int, int, rtx);
413 static void delete_address_reloads (rtx, rtx);
414 static void delete_address_reloads_1 (rtx, rtx, rtx);
415 static void inc_for_reload (rtx, rtx, rtx, int);
417 static void add_auto_inc_notes (rtx, rtx);
419 static void substitute (rtx *, const_rtx, rtx);
420 static bool gen_reload_chain_without_interm_reg_p (int, int);
421 static int reloads_conflict (int, int);
422 static rtx gen_reload (rtx, rtx, int, enum reload_type);
423 static rtx emit_insn_if_valid_for_reload (rtx);
425 /* Initialize the reload pass. This is called at the beginning of compilation
426 and may be called again if the target is reinitialized. */
433 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
434 Set spill_indirect_levels to the number of levels such addressing is
435 permitted, zero if it is not permitted at all. */
438 = gen_rtx_MEM (Pmode,
441 LAST_VIRTUAL_REGISTER + 1),
443 spill_indirect_levels = 0;
445 while (memory_address_p (QImode, tem))
447 spill_indirect_levels++;
448 tem = gen_rtx_MEM (Pmode, tem);
451 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
453 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
454 indirect_symref_ok = memory_address_p (QImode, tem);
456 /* See if reg+reg is a valid (and offsettable) address. */
458 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
460 tem = gen_rtx_PLUS (Pmode,
461 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
462 gen_rtx_REG (Pmode, i));
464 /* This way, we make sure that reg+reg is an offsettable address. */
465 tem = plus_constant (tem, 4);
467 if (memory_address_p (QImode, tem))
469 double_reg_address_ok = 1;
474 /* Initialize obstack for our rtl allocation. */
475 gcc_obstack_init (&reload_obstack);
476 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
478 INIT_REG_SET (&spilled_pseudos);
479 INIT_REG_SET (&changed_allocation_pseudos);
480 INIT_REG_SET (&pseudos_counted);
483 /* List of insn chains that are currently unused. */
484 static struct insn_chain *unused_insn_chains = 0;
486 /* Allocate an empty insn_chain structure. */
488 new_insn_chain (void)
490 struct insn_chain *c;
492 if (unused_insn_chains == 0)
494 c = XOBNEW (&reload_obstack, struct insn_chain);
495 INIT_REG_SET (&c->live_throughout);
496 INIT_REG_SET (&c->dead_or_set);
500 c = unused_insn_chains;
501 unused_insn_chains = c->next;
503 c->is_caller_save_insn = 0;
504 c->need_operand_change = 0;
510 /* Small utility function to set all regs in hard reg set TO which are
511 allocated to pseudos in regset FROM. */
514 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
517 reg_set_iterator rsi;
519 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
521 int r = reg_renumber[regno];
525 /* reload_combine uses the information from DF_LIVE_IN,
526 which might still contain registers that have not
527 actually been allocated since they have an
529 gcc_assert (ira_conflicts_p || reload_completed);
532 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
536 /* Replace all pseudos found in LOC with their corresponding
540 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
553 unsigned int regno = REGNO (x);
555 if (regno < FIRST_PSEUDO_REGISTER)
558 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
562 replace_pseudos_in (loc, mem_mode, usage);
566 if (reg_equiv_constant (regno))
567 *loc = reg_equiv_constant (regno);
568 else if (reg_equiv_invariant (regno))
569 *loc = reg_equiv_invariant (regno);
570 else if (reg_equiv_mem (regno))
571 *loc = reg_equiv_mem (regno);
572 else if (reg_equiv_address (regno))
573 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
576 gcc_assert (!REG_P (regno_reg_rtx[regno])
577 || REGNO (regno_reg_rtx[regno]) != regno);
578 *loc = regno_reg_rtx[regno];
583 else if (code == MEM)
585 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
589 /* Process each of our operands recursively. */
590 fmt = GET_RTX_FORMAT (code);
591 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
593 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
594 else if (*fmt == 'E')
595 for (j = 0; j < XVECLEN (x, i); j++)
596 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
599 /* Determine if the current function has an exception receiver block
600 that reaches the exit block via non-exceptional edges */
603 has_nonexceptional_receiver (void)
607 basic_block *tos, *worklist, bb;
609 /* If we're not optimizing, then just err on the safe side. */
613 /* First determine which blocks can reach exit via normal paths. */
614 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
617 bb->flags &= ~BB_REACHABLE;
619 /* Place the exit block on our worklist. */
620 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
621 *tos++ = EXIT_BLOCK_PTR;
623 /* Iterate: find everything reachable from what we've already seen. */
624 while (tos != worklist)
628 FOR_EACH_EDGE (e, ei, bb->preds)
629 if (!(e->flags & EDGE_ABNORMAL))
631 basic_block src = e->src;
633 if (!(src->flags & BB_REACHABLE))
635 src->flags |= BB_REACHABLE;
642 /* Now see if there's a reachable block with an exceptional incoming
645 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
648 /* No exceptional block reached exit unexceptionally. */
652 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
653 zero elements) to MAX_REG_NUM elements.
655 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
657 grow_reg_equivs (void)
659 int old_size = VEC_length (reg_equivs_t, reg_equivs);
660 int max_regno = max_reg_num ();
663 VEC_reserve (reg_equivs_t, gc, reg_equivs, max_regno);
664 for (i = old_size; i < max_regno; i++)
666 VEC_quick_insert (reg_equivs_t, reg_equivs, i, 0);
667 memset (VEC_index (reg_equivs_t, reg_equivs, i), 0, sizeof (reg_equivs_t));
673 /* Global variables used by reload and its subroutines. */
675 /* The current basic block while in calculate_elim_costs_all_insns. */
676 static basic_block elim_bb;
678 /* Set during calculate_needs if an insn needs register elimination. */
679 static int something_needs_elimination;
680 /* Set during calculate_needs if an insn needs an operand changed. */
681 static int something_needs_operands_changed;
682 /* Set by alter_regs if we spilled a register to the stack. */
683 static bool something_was_spilled;
685 /* Nonzero means we couldn't get enough spill regs. */
688 /* Temporary array of pseudo-register number. */
689 static int *temp_pseudo_reg_arr;
691 /* Main entry point for the reload pass.
693 FIRST is the first insn of the function being compiled.
695 GLOBAL nonzero means we were called from global_alloc
696 and should attempt to reallocate any pseudoregs that we
697 displace from hard regs we will use for reloads.
698 If GLOBAL is zero, we do not have enough information to do that,
699 so any pseudo reg that is spilled must go to the stack.
701 Return value is TRUE if reload likely left dead insns in the
702 stream and a DCE pass should be run to elimiante them. Else the
703 return value is FALSE. */
706 reload (rtx first, int global)
710 struct elim_table *ep;
714 /* Make sure even insns with volatile mem refs are recognizable. */
719 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
721 /* Make sure that the last insn in the chain
722 is not something that needs reloading. */
723 emit_note (NOTE_INSN_DELETED);
725 /* Enable find_equiv_reg to distinguish insns made by reload. */
726 reload_first_uid = get_max_uid ();
728 #ifdef SECONDARY_MEMORY_NEEDED
729 /* Initialize the secondary memory table. */
730 clear_secondary_mem ();
733 /* We don't have a stack slot for any spill reg yet. */
734 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
735 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
737 /* Initialize the save area information for caller-save, in case some
741 /* Compute which hard registers are now in use
742 as homes for pseudo registers.
743 This is done here rather than (eg) in global_alloc
744 because this point is reached even if not optimizing. */
745 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
748 /* A function that has a nonlocal label that can reach the exit
749 block via non-exceptional paths must save all call-saved
751 if (cfun->has_nonlocal_label
752 && has_nonexceptional_receiver ())
753 crtl->saves_all_registers = 1;
755 if (crtl->saves_all_registers)
756 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
757 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
758 df_set_regs_ever_live (i, true);
760 /* Find all the pseudo registers that didn't get hard regs
761 but do have known equivalent constants or memory slots.
762 These include parameters (known equivalent to parameter slots)
763 and cse'd or loop-moved constant memory addresses.
765 Record constant equivalents in reg_equiv_constant
766 so they will be substituted by find_reloads.
767 Record memory equivalents in reg_mem_equiv so they can
768 be substituted eventually by altering the REG-rtx's. */
771 reg_old_renumber = XCNEWVEC (short, max_regno);
772 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
773 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
774 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
776 CLEAR_HARD_REG_SET (bad_spill_regs_global);
778 init_eliminable_invariants (first, true);
781 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
782 stack slots to the pseudos that lack hard regs or equivalents.
783 Do not touch virtual registers. */
785 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
786 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
787 temp_pseudo_reg_arr[n++] = i;
790 /* Ask IRA to order pseudo-registers for better stack slot
792 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
794 for (i = 0; i < n; i++)
795 alter_reg (temp_pseudo_reg_arr[i], -1, false);
797 /* If we have some registers we think can be eliminated, scan all insns to
798 see if there is an insn that sets one of these registers to something
799 other than itself plus a constant. If so, the register cannot be
800 eliminated. Doing this scan here eliminates an extra pass through the
801 main reload loop in the most common case where register elimination
803 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
805 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
807 maybe_fix_stack_asms ();
809 insns_need_reload = 0;
810 something_needs_elimination = 0;
812 /* Initialize to -1, which means take the first spill register. */
815 /* Spill any hard regs that we know we can't eliminate. */
816 CLEAR_HARD_REG_SET (used_spill_regs);
817 /* There can be multiple ways to eliminate a register;
818 they should be listed adjacently.
819 Elimination for any register fails only if all possible ways fail. */
820 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
823 int can_eliminate = 0;
826 can_eliminate |= ep->can_eliminate;
829 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
831 spill_hard_reg (from, 1);
834 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
835 if (frame_pointer_needed)
836 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
838 finish_spills (global);
840 /* From now on, we may need to generate moves differently. We may also
841 allow modifications of insns which cause them to not be recognized.
842 Any such modifications will be cleaned up during reload itself. */
843 reload_in_progress = 1;
845 /* This loop scans the entire function each go-round
846 and repeats until one repetition spills no additional hard regs. */
849 int something_changed;
851 HOST_WIDE_INT starting_frame_size;
853 starting_frame_size = get_frame_size ();
854 something_was_spilled = false;
856 set_initial_elim_offsets ();
857 set_initial_label_offsets ();
859 /* For each pseudo register that has an equivalent location defined,
860 try to eliminate any eliminable registers (such as the frame pointer)
861 assuming initial offsets for the replacement register, which
864 If the resulting location is directly addressable, substitute
865 the MEM we just got directly for the old REG.
867 If it is not addressable but is a constant or the sum of a hard reg
868 and constant, it is probably not addressable because the constant is
869 out of range, in that case record the address; we will generate
870 hairy code to compute the address in a register each time it is
871 needed. Similarly if it is a hard register, but one that is not
872 valid as an address register.
874 If the location is not addressable, but does not have one of the
875 above forms, assign a stack slot. We have to do this to avoid the
876 potential of producing lots of reloads if, e.g., a location involves
877 a pseudo that didn't get a hard register and has an equivalent memory
878 location that also involves a pseudo that didn't get a hard register.
880 Perhaps at some point we will improve reload_when_needed handling
881 so this problem goes away. But that's very hairy. */
883 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
884 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
886 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
889 if (strict_memory_address_addr_space_p
890 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
892 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
893 else if (CONSTANT_P (XEXP (x, 0))
894 || (REG_P (XEXP (x, 0))
895 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
896 || (GET_CODE (XEXP (x, 0)) == PLUS
897 && REG_P (XEXP (XEXP (x, 0), 0))
898 && (REGNO (XEXP (XEXP (x, 0), 0))
899 < FIRST_PSEUDO_REGISTER)
900 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
901 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
904 /* Make a new stack slot. Then indicate that something
905 changed so we go back and recompute offsets for
906 eliminable registers because the allocation of memory
907 below might change some offset. reg_equiv_{mem,address}
908 will be set up for this pseudo on the next pass around
910 reg_equiv_memory_loc (i) = 0;
911 reg_equiv_init (i) = 0;
912 alter_reg (i, -1, true);
916 if (caller_save_needed)
919 /* If we allocated another stack slot, redo elimination bookkeeping. */
920 if (something_was_spilled || starting_frame_size != get_frame_size ())
922 if (starting_frame_size && crtl->stack_alignment_needed)
924 /* If we have a stack frame, we must align it now. The
925 stack size may be a part of the offset computation for
926 register elimination. So if this changes the stack size,
927 then repeat the elimination bookkeeping. We don't
928 realign when there is no stack, as that will cause a
929 stack frame when none is needed should
930 STARTING_FRAME_OFFSET not be already aligned to
932 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
933 if (starting_frame_size != get_frame_size ())
937 if (caller_save_needed)
939 save_call_clobbered_regs ();
940 /* That might have allocated new insn_chain structures. */
941 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
944 calculate_needs_all_insns (global);
946 if (! ira_conflicts_p)
947 /* Don't do it for IRA. We need this info because we don't
948 change live_throughout and dead_or_set for chains when IRA
950 CLEAR_REG_SET (&spilled_pseudos);
954 something_changed = 0;
956 /* If we allocated any new memory locations, make another pass
957 since it might have changed elimination offsets. */
958 if (something_was_spilled || starting_frame_size != get_frame_size ())
959 something_changed = 1;
961 /* Even if the frame size remained the same, we might still have
962 changed elimination offsets, e.g. if find_reloads called
963 force_const_mem requiring the back end to allocate a constant
964 pool base register that needs to be saved on the stack. */
965 else if (!verify_initial_elim_offsets ())
966 something_changed = 1;
969 HARD_REG_SET to_spill;
970 CLEAR_HARD_REG_SET (to_spill);
971 update_eliminables (&to_spill);
972 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
974 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
975 if (TEST_HARD_REG_BIT (to_spill, i))
977 spill_hard_reg (i, 1);
980 /* Regardless of the state of spills, if we previously had
981 a register that we thought we could eliminate, but now can
982 not eliminate, we must run another pass.
984 Consider pseudos which have an entry in reg_equiv_* which
985 reference an eliminable register. We must make another pass
986 to update reg_equiv_* so that we do not substitute in the
987 old value from when we thought the elimination could be
989 something_changed = 1;
993 select_reload_regs ();
997 if (insns_need_reload != 0 || did_spill)
998 something_changed |= finish_spills (global);
1000 if (! something_changed)
1003 if (caller_save_needed)
1004 delete_caller_save_insns ();
1006 obstack_free (&reload_obstack, reload_firstobj);
1009 /* If global-alloc was run, notify it of any register eliminations we have
1012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1013 if (ep->can_eliminate)
1014 mark_elimination (ep->from, ep->to);
1016 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1017 If that insn didn't set the register (i.e., it copied the register to
1018 memory), just delete that insn instead of the equivalencing insn plus
1019 anything now dead. If we call delete_dead_insn on that insn, we may
1020 delete the insn that actually sets the register if the register dies
1021 there and that is incorrect. */
1023 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1025 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
1028 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
1030 rtx equiv_insn = XEXP (list, 0);
1032 /* If we already deleted the insn or if it may trap, we can't
1033 delete it. The latter case shouldn't happen, but can
1034 if an insn has a variable address, gets a REG_EH_REGION
1035 note added to it, and then gets converted into a load
1036 from a constant address. */
1037 if (NOTE_P (equiv_insn)
1038 || can_throw_internal (equiv_insn))
1040 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1041 delete_dead_insn (equiv_insn);
1043 SET_INSN_DELETED (equiv_insn);
1048 /* Use the reload registers where necessary
1049 by generating move instructions to move the must-be-register
1050 values into or out of the reload registers. */
1052 if (insns_need_reload != 0 || something_needs_elimination
1053 || something_needs_operands_changed)
1055 HOST_WIDE_INT old_frame_size = get_frame_size ();
1057 reload_as_needed (global);
1059 gcc_assert (old_frame_size == get_frame_size ());
1061 gcc_assert (verify_initial_elim_offsets ());
1064 /* If we were able to eliminate the frame pointer, show that it is no
1065 longer live at the start of any basic block. If it ls live by
1066 virtue of being in a pseudo, that pseudo will be marked live
1067 and hence the frame pointer will be known to be live via that
1070 if (! frame_pointer_needed)
1072 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1074 /* Come here (with failure set nonzero) if we can't get enough spill
1078 CLEAR_REG_SET (&changed_allocation_pseudos);
1079 CLEAR_REG_SET (&spilled_pseudos);
1080 reload_in_progress = 0;
1082 /* Now eliminate all pseudo regs by modifying them into
1083 their equivalent memory references.
1084 The REG-rtx's for the pseudos are modified in place,
1085 so all insns that used to refer to them now refer to memory.
1087 For a reg that has a reg_equiv_address, all those insns
1088 were changed by reloading so that no insns refer to it any longer;
1089 but the DECL_RTL of a variable decl may refer to it,
1090 and if so this causes the debugging info to mention the variable. */
1092 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1096 if (reg_equiv_mem (i))
1097 addr = XEXP (reg_equiv_mem (i), 0);
1099 if (reg_equiv_address (i))
1100 addr = reg_equiv_address (i);
1104 if (reg_renumber[i] < 0)
1106 rtx reg = regno_reg_rtx[i];
1108 REG_USERVAR_P (reg) = 0;
1109 PUT_CODE (reg, MEM);
1110 XEXP (reg, 0) = addr;
1111 if (reg_equiv_memory_loc (i))
1112 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1115 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1116 MEM_ATTRS (reg) = 0;
1118 MEM_NOTRAP_P (reg) = 1;
1120 else if (reg_equiv_mem (i))
1121 XEXP (reg_equiv_mem (i), 0) = addr;
1124 /* We don't want complex addressing modes in debug insns
1125 if simpler ones will do, so delegitimize equivalences
1127 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1129 rtx reg = regno_reg_rtx[i];
1133 if (reg_equiv_constant (i))
1134 equiv = reg_equiv_constant (i);
1135 else if (reg_equiv_invariant (i))
1136 equiv = reg_equiv_invariant (i);
1137 else if (reg && MEM_P (reg))
1138 equiv = targetm.delegitimize_address (reg);
1139 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1145 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1147 insn = DF_REF_INSN (use);
1149 /* Make sure the next ref is for a different instruction,
1150 so that we're not affected by the rescan. */
1151 next = DF_REF_NEXT_REG (use);
1152 while (next && DF_REF_INSN (next) == insn)
1153 next = DF_REF_NEXT_REG (next);
1155 if (DEBUG_INSN_P (insn))
1159 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1160 df_insn_rescan_debug_internal (insn);
1163 INSN_VAR_LOCATION_LOC (insn)
1164 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1171 /* We must set reload_completed now since the cleanup_subreg_operands call
1172 below will re-recognize each insn and reload may have generated insns
1173 which are only valid during and after reload. */
1174 reload_completed = 1;
1176 /* Make a pass over all the insns and delete all USEs which we inserted
1177 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1178 notes. Delete all CLOBBER insns, except those that refer to the return
1179 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1180 from misarranging variable-array code, and simplify (subreg (reg))
1181 operands. Strip and regenerate REG_INC notes that may have been moved
1184 for (insn = first; insn; insn = NEXT_INSN (insn))
1190 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1191 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1193 if ((GET_CODE (PATTERN (insn)) == USE
1194 /* We mark with QImode USEs introduced by reload itself. */
1195 && (GET_MODE (insn) == QImode
1196 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1197 || (GET_CODE (PATTERN (insn)) == CLOBBER
1198 && (!MEM_P (XEXP (PATTERN (insn), 0))
1199 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1200 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1201 && XEXP (XEXP (PATTERN (insn), 0), 0)
1202 != stack_pointer_rtx))
1203 && (!REG_P (XEXP (PATTERN (insn), 0))
1204 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1210 /* Some CLOBBERs may survive until here and still reference unassigned
1211 pseudos with const equivalent, which may in turn cause ICE in later
1212 passes if the reference remains in place. */
1213 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1214 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1215 VOIDmode, PATTERN (insn));
1217 /* Discard obvious no-ops, even without -O. This optimization
1218 is fast and doesn't interfere with debugging. */
1219 if (NONJUMP_INSN_P (insn)
1220 && GET_CODE (PATTERN (insn)) == SET
1221 && REG_P (SET_SRC (PATTERN (insn)))
1222 && REG_P (SET_DEST (PATTERN (insn)))
1223 && (REGNO (SET_SRC (PATTERN (insn)))
1224 == REGNO (SET_DEST (PATTERN (insn)))))
1230 pnote = ®_NOTES (insn);
1233 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1234 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1235 || REG_NOTE_KIND (*pnote) == REG_INC)
1236 *pnote = XEXP (*pnote, 1);
1238 pnote = &XEXP (*pnote, 1);
1242 add_auto_inc_notes (insn, PATTERN (insn));
1245 /* Simplify (subreg (reg)) if it appears as an operand. */
1246 cleanup_subreg_operands (insn);
1248 /* Clean up invalid ASMs so that they don't confuse later passes.
1250 if (asm_noperands (PATTERN (insn)) >= 0)
1252 extract_insn (insn);
1253 if (!constrain_operands (1))
1255 error_for_asm (insn,
1256 "%<asm%> operand has impossible constraints");
1263 /* If we are doing generic stack checking, give a warning if this
1264 function's frame size is larger than we expect. */
1265 if (flag_stack_check == GENERIC_STACK_CHECK)
1267 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1268 static int verbose_warned = 0;
1270 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1271 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1272 size += UNITS_PER_WORD;
1274 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1276 warning (0, "frame size too large for reliable stack checking");
1277 if (! verbose_warned)
1279 warning (0, "try reducing the number of local variables");
1285 free (temp_pseudo_reg_arr);
1287 /* Indicate that we no longer have known memory locations or constants. */
1290 free (reg_max_ref_width);
1291 free (reg_old_renumber);
1292 free (pseudo_previous_regs);
1293 free (pseudo_forbidden_regs);
1295 CLEAR_HARD_REG_SET (used_spill_regs);
1296 for (i = 0; i < n_spills; i++)
1297 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1299 /* Free all the insn_chain structures at once. */
1300 obstack_free (&reload_obstack, reload_startobj);
1301 unused_insn_chains = 0;
1303 inserted = fixup_abnormal_edges ();
1305 /* We've possibly turned single trapping insn into multiple ones. */
1306 if (cfun->can_throw_non_call_exceptions)
1309 blocks = sbitmap_alloc (last_basic_block);
1310 sbitmap_ones (blocks);
1311 find_many_sub_basic_blocks (blocks);
1312 sbitmap_free (blocks);
1316 commit_edge_insertions ();
1318 /* Replacing pseudos with their memory equivalents might have
1319 created shared rtx. Subsequent passes would get confused
1320 by this, so unshare everything here. */
1321 unshare_all_rtl_again (first);
1323 #ifdef STACK_BOUNDARY
1324 /* init_emit has set the alignment of the hard frame pointer
1325 to STACK_BOUNDARY. It is very likely no longer valid if
1326 the hard frame pointer was used for register allocation. */
1327 if (!frame_pointer_needed)
1328 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1331 VEC_free (rtx_p, heap, substitute_stack);
1333 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1335 reload_completed = !failure;
1340 /* Yet another special case. Unfortunately, reg-stack forces people to
1341 write incorrect clobbers in asm statements. These clobbers must not
1342 cause the register to appear in bad_spill_regs, otherwise we'll call
1343 fatal_insn later. We clear the corresponding regnos in the live
1344 register sets to avoid this.
1345 The whole thing is rather sick, I'm afraid. */
1348 maybe_fix_stack_asms (void)
1351 const char *constraints[MAX_RECOG_OPERANDS];
1352 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1353 struct insn_chain *chain;
1355 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1358 HARD_REG_SET clobbered, allowed;
1361 if (! INSN_P (chain->insn)
1362 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1364 pat = PATTERN (chain->insn);
1365 if (GET_CODE (pat) != PARALLEL)
1368 CLEAR_HARD_REG_SET (clobbered);
1369 CLEAR_HARD_REG_SET (allowed);
1371 /* First, make a mask of all stack regs that are clobbered. */
1372 for (i = 0; i < XVECLEN (pat, 0); i++)
1374 rtx t = XVECEXP (pat, 0, i);
1375 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1376 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1379 /* Get the operand values and constraints out of the insn. */
1380 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1381 constraints, operand_mode, NULL);
1383 /* For every operand, see what registers are allowed. */
1384 for (i = 0; i < noperands; i++)
1386 const char *p = constraints[i];
1387 /* For every alternative, we compute the class of registers allowed
1388 for reloading in CLS, and merge its contents into the reg set
1390 int cls = (int) NO_REGS;
1396 if (c == '\0' || c == ',' || c == '#')
1398 /* End of one alternative - mark the regs in the current
1399 class, and reset the class. */
1400 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1406 } while (c != '\0' && c != ',');
1414 case '=': case '+': case '*': case '%': case '?': case '!':
1415 case '0': case '1': case '2': case '3': case '4': case '<':
1416 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1417 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1418 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1419 case TARGET_MEM_CONSTRAINT:
1423 cls = (int) reg_class_subunion[cls]
1424 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1430 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1434 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1435 cls = (int) reg_class_subunion[cls]
1436 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1439 cls = (int) reg_class_subunion[cls]
1440 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1442 p += CONSTRAINT_LEN (c, p);
1445 /* Those of the registers which are clobbered, but allowed by the
1446 constraints, must be usable as reload registers. So clear them
1447 out of the life information. */
1448 AND_HARD_REG_SET (allowed, clobbered);
1449 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1450 if (TEST_HARD_REG_BIT (allowed, i))
1452 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1453 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1460 /* Copy the global variables n_reloads and rld into the corresponding elts
1463 copy_reloads (struct insn_chain *chain)
1465 chain->n_reloads = n_reloads;
1466 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1467 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1468 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1471 /* Walk the chain of insns, and determine for each whether it needs reloads
1472 and/or eliminations. Build the corresponding insns_need_reload list, and
1473 set something_needs_elimination as appropriate. */
1475 calculate_needs_all_insns (int global)
1477 struct insn_chain **pprev_reload = &insns_need_reload;
1478 struct insn_chain *chain, *next = 0;
1480 something_needs_elimination = 0;
1482 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1483 for (chain = reload_insn_chain; chain != 0; chain = next)
1485 rtx insn = chain->insn;
1489 /* Clear out the shortcuts. */
1490 chain->n_reloads = 0;
1491 chain->need_elim = 0;
1492 chain->need_reload = 0;
1493 chain->need_operand_change = 0;
1495 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1496 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1497 what effects this has on the known offsets at labels. */
1499 if (LABEL_P (insn) || JUMP_P (insn)
1500 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1501 set_label_offsets (insn, insn, 0);
1505 rtx old_body = PATTERN (insn);
1506 int old_code = INSN_CODE (insn);
1507 rtx old_notes = REG_NOTES (insn);
1508 int did_elimination = 0;
1509 int operands_changed = 0;
1510 rtx set = single_set (insn);
1512 /* Skip insns that only set an equivalence. */
1513 if (set && REG_P (SET_DEST (set))
1514 && reg_renumber[REGNO (SET_DEST (set))] < 0
1515 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1516 || (reg_equiv_invariant (REGNO (SET_DEST (set)))))
1517 && reg_equiv_init (REGNO (SET_DEST (set))))
1520 /* If needed, eliminate any eliminable registers. */
1521 if (num_eliminable || num_eliminable_invariants)
1522 did_elimination = eliminate_regs_in_insn (insn, 0);
1524 /* Analyze the instruction. */
1525 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1526 global, spill_reg_order);
1528 /* If a no-op set needs more than one reload, this is likely
1529 to be something that needs input address reloads. We
1530 can't get rid of this cleanly later, and it is of no use
1531 anyway, so discard it now.
1532 We only do this when expensive_optimizations is enabled,
1533 since this complements reload inheritance / output
1534 reload deletion, and it can make debugging harder. */
1535 if (flag_expensive_optimizations && n_reloads > 1)
1537 rtx set = single_set (insn);
1540 ((SET_SRC (set) == SET_DEST (set)
1541 && REG_P (SET_SRC (set))
1542 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1543 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1544 && reg_renumber[REGNO (SET_SRC (set))] < 0
1545 && reg_renumber[REGNO (SET_DEST (set))] < 0
1546 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1547 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1548 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1549 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1551 if (ira_conflicts_p)
1552 /* Inform IRA about the insn deletion. */
1553 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1554 REGNO (SET_SRC (set)));
1556 /* Delete it from the reload chain. */
1558 chain->prev->next = next;
1560 reload_insn_chain = next;
1562 next->prev = chain->prev;
1563 chain->next = unused_insn_chains;
1564 unused_insn_chains = chain;
1569 update_eliminable_offsets ();
1571 /* Remember for later shortcuts which insns had any reloads or
1572 register eliminations. */
1573 chain->need_elim = did_elimination;
1574 chain->need_reload = n_reloads > 0;
1575 chain->need_operand_change = operands_changed;
1577 /* Discard any register replacements done. */
1578 if (did_elimination)
1580 obstack_free (&reload_obstack, reload_insn_firstobj);
1581 PATTERN (insn) = old_body;
1582 INSN_CODE (insn) = old_code;
1583 REG_NOTES (insn) = old_notes;
1584 something_needs_elimination = 1;
1587 something_needs_operands_changed |= operands_changed;
1591 copy_reloads (chain);
1592 *pprev_reload = chain;
1593 pprev_reload = &chain->next_need_reload;
1600 /* This function is called from the register allocator to set up estimates
1601 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1602 an invariant. The structure is similar to calculate_needs_all_insns. */
1605 calculate_elim_costs_all_insns (void)
1607 int *reg_equiv_init_cost;
1611 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1613 init_eliminable_invariants (get_insns (), false);
1615 set_initial_elim_offsets ();
1616 set_initial_label_offsets ();
1623 FOR_BB_INSNS (bb, insn)
1625 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1626 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1627 what effects this has on the known offsets at labels. */
1629 if (LABEL_P (insn) || JUMP_P (insn)
1630 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1631 set_label_offsets (insn, insn, 0);
1635 rtx set = single_set (insn);
1637 /* Skip insns that only set an equivalence. */
1638 if (set && REG_P (SET_DEST (set))
1639 && reg_renumber[REGNO (SET_DEST (set))] < 0
1640 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1641 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1643 unsigned regno = REGNO (SET_DEST (set));
1644 rtx init = reg_equiv_init (regno);
1647 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1649 int cost = set_src_cost (t, optimize_bb_for_speed_p (bb));
1650 int freq = REG_FREQ_FROM_BB (bb);
1652 reg_equiv_init_cost[regno] = cost * freq;
1656 /* If needed, eliminate any eliminable registers. */
1657 if (num_eliminable || num_eliminable_invariants)
1658 elimination_costs_in_insn (insn);
1661 update_eliminable_offsets ();
1665 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1667 if (reg_equiv_invariant (i))
1669 if (reg_equiv_init (i))
1671 int cost = reg_equiv_init_cost[i];
1674 "Reg %d has equivalence, initial gains %d\n", i, cost);
1676 ira_adjust_equiv_reg_cost (i, cost);
1682 "Reg %d had equivalence, but can't be eliminated\n",
1684 ira_adjust_equiv_reg_cost (i, 0);
1689 free (reg_equiv_init_cost);
1690 free (offsets_known_at);
1693 offsets_known_at = NULL;
1696 /* Comparison function for qsort to decide which of two reloads
1697 should be handled first. *P1 and *P2 are the reload numbers. */
1700 reload_reg_class_lower (const void *r1p, const void *r2p)
1702 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1705 /* Consider required reloads before optional ones. */
1706 t = rld[r1].optional - rld[r2].optional;
1710 /* Count all solitary classes before non-solitary ones. */
1711 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1712 - (reg_class_size[(int) rld[r1].rclass] == 1));
1716 /* Aside from solitaires, consider all multi-reg groups first. */
1717 t = rld[r2].nregs - rld[r1].nregs;
1721 /* Consider reloads in order of increasing reg-class number. */
1722 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1726 /* If reloads are equally urgent, sort by reload number,
1727 so that the results of qsort leave nothing to chance. */
1731 /* The cost of spilling each hard reg. */
1732 static int spill_cost[FIRST_PSEUDO_REGISTER];
1734 /* When spilling multiple hard registers, we use SPILL_COST for the first
1735 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1736 only the first hard reg for a multi-reg pseudo. */
1737 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1739 /* Map of hard regno to pseudo regno currently occupying the hard
1741 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1743 /* Update the spill cost arrays, considering that pseudo REG is live. */
1746 count_pseudo (int reg)
1748 int freq = REG_FREQ (reg);
1749 int r = reg_renumber[reg];
1752 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1753 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1754 /* Ignore spilled pseudo-registers which can be here only if IRA
1756 || (ira_conflicts_p && r < 0))
1759 SET_REGNO_REG_SET (&pseudos_counted, reg);
1761 gcc_assert (r >= 0);
1763 spill_add_cost[r] += freq;
1764 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1767 hard_regno_to_pseudo_regno[r + nregs] = reg;
1768 spill_cost[r + nregs] += freq;
1772 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1773 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1776 order_regs_for_reload (struct insn_chain *chain)
1779 HARD_REG_SET used_by_pseudos;
1780 HARD_REG_SET used_by_pseudos2;
1781 reg_set_iterator rsi;
1783 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1785 memset (spill_cost, 0, sizeof spill_cost);
1786 memset (spill_add_cost, 0, sizeof spill_add_cost);
1787 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1788 hard_regno_to_pseudo_regno[i] = -1;
1790 /* Count number of uses of each hard reg by pseudo regs allocated to it
1791 and then order them by decreasing use. First exclude hard registers
1792 that are live in or across this insn. */
1794 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1795 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1796 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1797 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1799 /* Now find out which pseudos are allocated to it, and update
1801 CLEAR_REG_SET (&pseudos_counted);
1803 EXECUTE_IF_SET_IN_REG_SET
1804 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1808 EXECUTE_IF_SET_IN_REG_SET
1809 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1813 CLEAR_REG_SET (&pseudos_counted);
1816 /* Vector of reload-numbers showing the order in which the reloads should
1818 static short reload_order[MAX_RELOADS];
1820 /* This is used to keep track of the spill regs used in one insn. */
1821 static HARD_REG_SET used_spill_regs_local;
1823 /* We decided to spill hard register SPILLED, which has a size of
1824 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1825 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1826 update SPILL_COST/SPILL_ADD_COST. */
1829 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1831 int freq = REG_FREQ (reg);
1832 int r = reg_renumber[reg];
1833 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1835 /* Ignore spilled pseudo-registers which can be here only if IRA is
1837 if ((ira_conflicts_p && r < 0)
1838 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1839 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1842 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1844 spill_add_cost[r] -= freq;
1847 hard_regno_to_pseudo_regno[r + nregs] = -1;
1848 spill_cost[r + nregs] -= freq;
1852 /* Find reload register to use for reload number ORDER. */
1855 find_reg (struct insn_chain *chain, int order)
1857 int rnum = reload_order[order];
1858 struct reload *rl = rld + rnum;
1859 int best_cost = INT_MAX;
1861 unsigned int i, j, n;
1863 HARD_REG_SET not_usable;
1864 HARD_REG_SET used_by_other_reload;
1865 reg_set_iterator rsi;
1866 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1867 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1869 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1870 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1871 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1873 CLEAR_HARD_REG_SET (used_by_other_reload);
1874 for (k = 0; k < order; k++)
1876 int other = reload_order[k];
1878 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1879 for (j = 0; j < rld[other].nregs; j++)
1880 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1883 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1885 #ifdef REG_ALLOC_ORDER
1886 unsigned int regno = reg_alloc_order[i];
1888 unsigned int regno = i;
1891 if (! TEST_HARD_REG_BIT (not_usable, regno)
1892 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1893 && HARD_REGNO_MODE_OK (regno, rl->mode))
1895 int this_cost = spill_cost[regno];
1897 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1899 for (j = 1; j < this_nregs; j++)
1901 this_cost += spill_add_cost[regno + j];
1902 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1903 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1909 if (ira_conflicts_p)
1911 /* Ask IRA to find a better pseudo-register for
1913 for (n = j = 0; j < this_nregs; j++)
1915 int r = hard_regno_to_pseudo_regno[regno + j];
1919 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1920 regno_pseudo_regs[n++] = r;
1922 regno_pseudo_regs[n++] = -1;
1924 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1925 best_regno_pseudo_regs,
1932 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1933 if (regno_pseudo_regs[j] < 0)
1940 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1942 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1944 if (this_cost < best_cost
1945 /* Among registers with equal cost, prefer caller-saved ones, or
1946 use REG_ALLOC_ORDER if it is defined. */
1947 || (this_cost == best_cost
1948 #ifdef REG_ALLOC_ORDER
1949 && (inv_reg_alloc_order[regno]
1950 < inv_reg_alloc_order[best_reg])
1952 && call_used_regs[regno]
1953 && ! call_used_regs[best_reg]
1958 best_cost = this_cost;
1966 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1968 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1969 rl->regno = best_reg;
1971 EXECUTE_IF_SET_IN_REG_SET
1972 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1974 count_spilled_pseudo (best_reg, rl->nregs, j);
1977 EXECUTE_IF_SET_IN_REG_SET
1978 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1980 count_spilled_pseudo (best_reg, rl->nregs, j);
1983 for (i = 0; i < rl->nregs; i++)
1985 gcc_assert (spill_cost[best_reg + i] == 0);
1986 gcc_assert (spill_add_cost[best_reg + i] == 0);
1987 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1988 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1993 /* Find more reload regs to satisfy the remaining need of an insn, which
1995 Do it by ascending class number, since otherwise a reg
1996 might be spilled for a big class and might fail to count
1997 for a smaller class even though it belongs to that class. */
2000 find_reload_regs (struct insn_chain *chain)
2004 /* In order to be certain of getting the registers we need,
2005 we must sort the reloads into order of increasing register class.
2006 Then our grabbing of reload registers will parallel the process
2007 that provided the reload registers. */
2008 for (i = 0; i < chain->n_reloads; i++)
2010 /* Show whether this reload already has a hard reg. */
2011 if (chain->rld[i].reg_rtx)
2013 int regno = REGNO (chain->rld[i].reg_rtx);
2014 chain->rld[i].regno = regno;
2016 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2019 chain->rld[i].regno = -1;
2020 reload_order[i] = i;
2023 n_reloads = chain->n_reloads;
2024 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2026 CLEAR_HARD_REG_SET (used_spill_regs_local);
2029 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2031 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2033 /* Compute the order of preference for hard registers to spill. */
2035 order_regs_for_reload (chain);
2037 for (i = 0; i < n_reloads; i++)
2039 int r = reload_order[i];
2041 /* Ignore reloads that got marked inoperative. */
2042 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2043 && ! rld[r].optional
2044 && rld[r].regno == -1)
2045 if (! find_reg (chain, i))
2048 fprintf (dump_file, "reload failure for reload %d\n", r);
2049 spill_failure (chain->insn, rld[r].rclass);
2055 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2056 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2058 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2062 select_reload_regs (void)
2064 struct insn_chain *chain;
2066 /* Try to satisfy the needs for each insn. */
2067 for (chain = insns_need_reload; chain != 0;
2068 chain = chain->next_need_reload)
2069 find_reload_regs (chain);
2072 /* Delete all insns that were inserted by emit_caller_save_insns during
2075 delete_caller_save_insns (void)
2077 struct insn_chain *c = reload_insn_chain;
2081 while (c != 0 && c->is_caller_save_insn)
2083 struct insn_chain *next = c->next;
2086 if (c == reload_insn_chain)
2087 reload_insn_chain = next;
2091 next->prev = c->prev;
2093 c->prev->next = next;
2094 c->next = unused_insn_chains;
2095 unused_insn_chains = c;
2103 /* Handle the failure to find a register to spill.
2104 INSN should be one of the insns which needed this particular spill reg. */
2107 spill_failure (rtx insn, enum reg_class rclass)
2109 if (asm_noperands (PATTERN (insn)) >= 0)
2110 error_for_asm (insn, "can%'t find a register in class %qs while "
2111 "reloading %<asm%>",
2112 reg_class_names[rclass]);
2115 error ("unable to find a register to spill in class %qs",
2116 reg_class_names[rclass]);
2120 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2121 debug_reload_to_stream (dump_file);
2123 fatal_insn ("this is the insn:", insn);
2127 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2128 data that is dead in INSN. */
2131 delete_dead_insn (rtx insn)
2133 rtx prev = prev_active_insn (insn);
2136 /* If the previous insn sets a register that dies in our insn make
2137 a note that we want to run DCE immediately after reload.
2139 We used to delete the previous insn & recurse, but that's wrong for
2140 block local equivalences. Instead of trying to figure out the exact
2141 circumstances where we can delete the potentially dead insns, just
2142 let DCE do the job. */
2143 if (prev && GET_CODE (PATTERN (prev)) == SET
2144 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2145 && reg_mentioned_p (prev_dest, PATTERN (insn))
2146 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2147 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2150 SET_INSN_DELETED (insn);
2153 /* Modify the home of pseudo-reg I.
2154 The new home is present in reg_renumber[I].
2156 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2157 or it may be -1, meaning there is none or it is not relevant.
2158 This is used so that all pseudos spilled from a given hard reg
2159 can share one stack slot. */
2162 alter_reg (int i, int from_reg, bool dont_share_p)
2164 /* When outputting an inline function, this can happen
2165 for a reg that isn't actually used. */
2166 if (regno_reg_rtx[i] == 0)
2169 /* If the reg got changed to a MEM at rtl-generation time,
2171 if (!REG_P (regno_reg_rtx[i]))
2174 /* Modify the reg-rtx to contain the new hard reg
2175 number or else to contain its pseudo reg number. */
2176 SET_REGNO (regno_reg_rtx[i],
2177 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2179 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2180 allocate a stack slot for it. */
2182 if (reg_renumber[i] < 0
2183 && REG_N_REFS (i) > 0
2184 && reg_equiv_constant (i) == 0
2185 && (reg_equiv_invariant (i) == 0
2186 || reg_equiv_init (i) == 0)
2187 && reg_equiv_memory_loc (i) == 0)
2190 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2191 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2192 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2193 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2194 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2197 something_was_spilled = true;
2199 if (ira_conflicts_p)
2201 /* Mark the spill for IRA. */
2202 SET_REGNO_REG_SET (&spilled_pseudos, i);
2204 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2210 /* Each pseudo reg has an inherent size which comes from its own mode,
2211 and a total size which provides room for paradoxical subregs
2212 which refer to the pseudo reg in wider modes.
2214 We can use a slot already allocated if it provides both
2215 enough inherent space and enough total space.
2216 Otherwise, we allocate a new slot, making sure that it has no less
2217 inherent space, and no less total space, then the previous slot. */
2218 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2222 /* No known place to spill from => no slot to reuse. */
2223 x = assign_stack_local (mode, total_size,
2224 min_align > inherent_align
2225 || total_size > inherent_size ? -1 : 0);
2229 /* Cancel the big-endian correction done in assign_stack_local.
2230 Get the address of the beginning of the slot. This is so we
2231 can do a big-endian correction unconditionally below. */
2232 if (BYTES_BIG_ENDIAN)
2234 adjust = inherent_size - total_size;
2237 = adjust_address_nv (x, mode_for_size (total_size
2243 if (! dont_share_p && ira_conflicts_p)
2244 /* Inform IRA about allocation a new stack slot. */
2245 ira_mark_new_stack_slot (stack_slot, i, total_size);
2248 /* Reuse a stack slot if possible. */
2249 else if (spill_stack_slot[from_reg] != 0
2250 && spill_stack_slot_width[from_reg] >= total_size
2251 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2253 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2254 x = spill_stack_slot[from_reg];
2256 /* Allocate a bigger slot. */
2259 /* Compute maximum size needed, both for inherent size
2260 and for total size. */
2263 if (spill_stack_slot[from_reg])
2265 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2267 mode = GET_MODE (spill_stack_slot[from_reg]);
2268 if (spill_stack_slot_width[from_reg] > total_size)
2269 total_size = spill_stack_slot_width[from_reg];
2270 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2271 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2274 /* Make a slot with that size. */
2275 x = assign_stack_local (mode, total_size,
2276 min_align > inherent_align
2277 || total_size > inherent_size ? -1 : 0);
2280 /* Cancel the big-endian correction done in assign_stack_local.
2281 Get the address of the beginning of the slot. This is so we
2282 can do a big-endian correction unconditionally below. */
2283 if (BYTES_BIG_ENDIAN)
2285 adjust = GET_MODE_SIZE (mode) - total_size;
2288 = adjust_address_nv (x, mode_for_size (total_size
2294 spill_stack_slot[from_reg] = stack_slot;
2295 spill_stack_slot_width[from_reg] = total_size;
2298 /* On a big endian machine, the "address" of the slot
2299 is the address of the low part that fits its inherent mode. */
2300 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2301 adjust += (total_size - inherent_size);
2303 /* If we have any adjustment to make, or if the stack slot is the
2304 wrong mode, make a new stack slot. */
2305 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2307 /* Set all of the memory attributes as appropriate for a spill. */
2308 set_mem_attrs_for_spill (x);
2310 /* Save the stack slot for later. */
2311 reg_equiv_memory_loc (i) = x;
2315 /* Mark the slots in regs_ever_live for the hard regs used by
2316 pseudo-reg number REGNO, accessed in MODE. */
2319 mark_home_live_1 (int regno, enum machine_mode mode)
2323 i = reg_renumber[regno];
2326 lim = end_hard_regno (mode, i);
2328 df_set_regs_ever_live(i++, true);
2331 /* Mark the slots in regs_ever_live for the hard regs
2332 used by pseudo-reg number REGNO. */
2335 mark_home_live (int regno)
2337 if (reg_renumber[regno] >= 0)
2338 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2341 /* This function handles the tracking of elimination offsets around branches.
2343 X is a piece of RTL being scanned.
2345 INSN is the insn that it came from, if any.
2347 INITIAL_P is nonzero if we are to set the offset to be the initial
2348 offset and zero if we are setting the offset of the label to be the
2352 set_label_offsets (rtx x, rtx insn, int initial_p)
2354 enum rtx_code code = GET_CODE (x);
2357 struct elim_table *p;
2362 if (LABEL_REF_NONLOCAL_P (x))
2367 /* ... fall through ... */
2370 /* If we know nothing about this label, set the desired offsets. Note
2371 that this sets the offset at a label to be the offset before a label
2372 if we don't know anything about the label. This is not correct for
2373 the label after a BARRIER, but is the best guess we can make. If
2374 we guessed wrong, we will suppress an elimination that might have
2375 been possible had we been able to guess correctly. */
2377 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2379 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2380 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2381 = (initial_p ? reg_eliminate[i].initial_offset
2382 : reg_eliminate[i].offset);
2383 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2386 /* Otherwise, if this is the definition of a label and it is
2387 preceded by a BARRIER, set our offsets to the known offset of
2391 && (tem = prev_nonnote_insn (insn)) != 0
2393 set_offsets_for_label (insn);
2395 /* If neither of the above cases is true, compare each offset
2396 with those previously recorded and suppress any eliminations
2397 where the offsets disagree. */
2399 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2400 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2401 != (initial_p ? reg_eliminate[i].initial_offset
2402 : reg_eliminate[i].offset))
2403 reg_eliminate[i].can_eliminate = 0;
2408 set_label_offsets (PATTERN (insn), insn, initial_p);
2410 /* ... fall through ... */
2414 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2415 to indirectly and hence must have all eliminations at their
2417 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2418 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2419 set_label_offsets (XEXP (tem, 0), insn, 1);
2425 /* Each of the labels in the parallel or address vector must be
2426 at their initial offsets. We want the first field for PARALLEL
2427 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2429 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2430 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2435 /* We only care about setting PC. If the source is not RETURN,
2436 IF_THEN_ELSE, or a label, disable any eliminations not at
2437 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2438 isn't one of those possibilities. For branches to a label,
2439 call ourselves recursively.
2441 Note that this can disable elimination unnecessarily when we have
2442 a non-local goto since it will look like a non-constant jump to
2443 someplace in the current function. This isn't a significant
2444 problem since such jumps will normally be when all elimination
2445 pairs are back to their initial offsets. */
2447 if (SET_DEST (x) != pc_rtx)
2450 switch (GET_CODE (SET_SRC (x)))
2457 set_label_offsets (SET_SRC (x), insn, initial_p);
2461 tem = XEXP (SET_SRC (x), 1);
2462 if (GET_CODE (tem) == LABEL_REF)
2463 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2464 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2467 tem = XEXP (SET_SRC (x), 2);
2468 if (GET_CODE (tem) == LABEL_REF)
2469 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2470 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2478 /* If we reach here, all eliminations must be at their initial
2479 offset because we are doing a jump to a variable address. */
2480 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2481 if (p->offset != p->initial_offset)
2482 p->can_eliminate = 0;
2490 /* Called through for_each_rtx, this function examines every reg that occurs
2491 in PX and adjusts the costs for its elimination which are gathered by IRA.
2492 DATA is the insn in which PX occurs. We do not recurse into MEM
2496 note_reg_elim_costly (rtx *px, void *data)
2498 rtx insn = (rtx)data;
2505 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2506 && reg_equiv_init (REGNO (x))
2507 && reg_equiv_invariant (REGNO (x)))
2509 rtx t = reg_equiv_invariant (REGNO (x));
2510 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2511 int cost = set_src_cost (new_rtx, optimize_bb_for_speed_p (elim_bb));
2512 int freq = REG_FREQ_FROM_BB (elim_bb);
2515 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2520 /* Scan X and replace any eliminable registers (such as fp) with a
2521 replacement (such as sp), plus an offset.
2523 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2524 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2525 MEM, we are allowed to replace a sum of a register and the constant zero
2526 with the register, which we cannot do outside a MEM. In addition, we need
2527 to record the fact that a register is referenced outside a MEM.
2529 If INSN is an insn, it is the insn containing X. If we replace a REG
2530 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2531 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2532 the REG is being modified.
2534 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2535 That's used when we eliminate in expressions stored in notes.
2536 This means, do not set ref_outside_mem even if the reference
2539 If FOR_COSTS is true, we are being called before reload in order to
2540 estimate the costs of keeping registers with an equivalence unallocated.
2542 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2543 replacements done assuming all offsets are at their initial values. If
2544 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2545 encounter, return the actual location so that find_reloads will do
2546 the proper thing. */
2549 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2550 bool may_use_invariant, bool for_costs)
2552 enum rtx_code code = GET_CODE (x);
2553 struct elim_table *ep;
2560 if (! current_function_decl)
2583 /* First handle the case where we encounter a bare register that
2584 is eliminable. Replace it with a PLUS. */
2585 if (regno < FIRST_PSEUDO_REGISTER)
2587 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2589 if (ep->from_rtx == x && ep->can_eliminate)
2590 return plus_constant (ep->to_rtx, ep->previous_offset);
2593 else if (reg_renumber && reg_renumber[regno] < 0
2595 && reg_equiv_invariant (regno))
2597 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2598 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2599 mem_mode, insn, true, for_costs);
2600 /* There exists at least one use of REGNO that cannot be
2601 eliminated. Prevent the defining insn from being deleted. */
2602 reg_equiv_init (regno) = NULL_RTX;
2604 alter_reg (regno, -1, true);
2608 /* You might think handling MINUS in a manner similar to PLUS is a
2609 good idea. It is not. It has been tried multiple times and every
2610 time the change has had to have been reverted.
2612 Other parts of reload know a PLUS is special (gen_reload for example)
2613 and require special code to handle code a reloaded PLUS operand.
2615 Also consider backends where the flags register is clobbered by a
2616 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2617 lea instruction comes to mind). If we try to reload a MINUS, we
2618 may kill the flags register that was holding a useful value.
2620 So, please before trying to handle MINUS, consider reload as a
2621 whole instead of this little section as well as the backend issues. */
2623 /* If this is the sum of an eliminable register and a constant, rework
2625 if (REG_P (XEXP (x, 0))
2626 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2627 && CONSTANT_P (XEXP (x, 1)))
2629 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2631 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2633 /* The only time we want to replace a PLUS with a REG (this
2634 occurs when the constant operand of the PLUS is the negative
2635 of the offset) is when we are inside a MEM. We won't want
2636 to do so at other times because that would change the
2637 structure of the insn in a way that reload can't handle.
2638 We special-case the commonest situation in
2639 eliminate_regs_in_insn, so just replace a PLUS with a
2640 PLUS here, unless inside a MEM. */
2641 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2642 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2645 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2646 plus_constant (XEXP (x, 1),
2647 ep->previous_offset));
2650 /* If the register is not eliminable, we are done since the other
2651 operand is a constant. */
2655 /* If this is part of an address, we want to bring any constant to the
2656 outermost PLUS. We will do this by doing register replacement in
2657 our operands and seeing if a constant shows up in one of them.
2659 Note that there is no risk of modifying the structure of the insn,
2660 since we only get called for its operands, thus we are either
2661 modifying the address inside a MEM, or something like an address
2662 operand of a load-address insn. */
2665 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2667 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2670 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2672 /* If one side is a PLUS and the other side is a pseudo that
2673 didn't get a hard register but has a reg_equiv_constant,
2674 we must replace the constant here since it may no longer
2675 be in the position of any operand. */
2676 if (GET_CODE (new0) == PLUS && REG_P (new1)
2677 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2678 && reg_renumber[REGNO (new1)] < 0
2680 && reg_equiv_constant (REGNO (new1)) != 0)
2681 new1 = reg_equiv_constant (REGNO (new1));
2682 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2683 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2684 && reg_renumber[REGNO (new0)] < 0
2685 && reg_equiv_constant (REGNO (new0)) != 0)
2686 new0 = reg_equiv_constant (REGNO (new0));
2688 new_rtx = form_sum (GET_MODE (x), new0, new1);
2690 /* As above, if we are not inside a MEM we do not want to
2691 turn a PLUS into something else. We might try to do so here
2692 for an addition of 0 if we aren't optimizing. */
2693 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2694 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2702 /* If this is the product of an eliminable register and a
2703 constant, apply the distribute law and move the constant out
2704 so that we have (plus (mult ..) ..). This is needed in order
2705 to keep load-address insns valid. This case is pathological.
2706 We ignore the possibility of overflow here. */
2707 if (REG_P (XEXP (x, 0))
2708 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2709 && CONST_INT_P (XEXP (x, 1)))
2710 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2712 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2715 /* Refs inside notes or in DEBUG_INSNs don't count for
2717 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2718 || GET_CODE (insn) == INSN_LIST
2719 || DEBUG_INSN_P (insn))))
2720 ep->ref_outside_mem = 1;
2723 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2724 ep->previous_offset * INTVAL (XEXP (x, 1)));
2727 /* ... fall through ... */
2731 /* See comments before PLUS about handling MINUS. */
2733 case DIV: case UDIV:
2734 case MOD: case UMOD:
2735 case AND: case IOR: case XOR:
2736 case ROTATERT: case ROTATE:
2737 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2739 case GE: case GT: case GEU: case GTU:
2740 case LE: case LT: case LEU: case LTU:
2742 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2744 rtx new1 = XEXP (x, 1)
2745 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2748 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2749 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2754 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2757 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2759 if (new_rtx != XEXP (x, 0))
2761 /* If this is a REG_DEAD note, it is not valid anymore.
2762 Using the eliminated version could result in creating a
2763 REG_DEAD note for the stack or frame pointer. */
2764 if (REG_NOTE_KIND (x) == REG_DEAD)
2766 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2770 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2774 /* ... fall through ... */
2777 /* Now do eliminations in the rest of the chain. If this was
2778 an EXPR_LIST, this might result in allocating more memory than is
2779 strictly needed, but it simplifies the code. */
2782 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2784 if (new_rtx != XEXP (x, 1))
2786 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2794 /* We do not support elimination of a register that is modified.
2795 elimination_effects has already make sure that this does not
2801 /* We do not support elimination of a register that is modified.
2802 elimination_effects has already make sure that this does not
2803 happen. The only remaining case we need to consider here is
2804 that the increment value may be an eliminable register. */
2805 if (GET_CODE (XEXP (x, 1)) == PLUS
2806 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2808 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2809 insn, true, for_costs);
2811 if (new_rtx != XEXP (XEXP (x, 1), 1))
2812 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2813 gen_rtx_PLUS (GET_MODE (x),
2814 XEXP (x, 0), new_rtx));
2818 case STRICT_LOW_PART:
2820 case SIGN_EXTEND: case ZERO_EXTEND:
2821 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2822 case FLOAT: case FIX:
2823 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2832 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2834 if (new_rtx != XEXP (x, 0))
2835 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2839 /* Similar to above processing, but preserve SUBREG_BYTE.
2840 Convert (subreg (mem)) to (mem) if not paradoxical.
2841 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2842 pseudo didn't get a hard reg, we must replace this with the
2843 eliminated version of the memory location because push_reload
2844 may do the replacement in certain circumstances. */
2845 if (REG_P (SUBREG_REG (x))
2846 && !paradoxical_subreg_p (x)
2848 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2850 new_rtx = SUBREG_REG (x);
2853 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2855 if (new_rtx != SUBREG_REG (x))
2857 int x_size = GET_MODE_SIZE (GET_MODE (x));
2858 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2861 && ((x_size < new_size
2862 #ifdef WORD_REGISTER_OPERATIONS
2863 /* On these machines, combine can create rtl of the form
2864 (set (subreg:m1 (reg:m2 R) 0) ...)
2865 where m1 < m2, and expects something interesting to
2866 happen to the entire word. Moreover, it will use the
2867 (reg:m2 R) later, expecting all bits to be preserved.
2868 So if the number of words is the same, preserve the
2869 subreg so that push_reload can see it. */
2870 && ! ((x_size - 1) / UNITS_PER_WORD
2871 == (new_size -1 ) / UNITS_PER_WORD)
2874 || x_size == new_size)
2876 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2878 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2884 /* Our only special processing is to pass the mode of the MEM to our
2885 recursive call and copy the flags. While we are here, handle this
2886 case more efficiently. */
2888 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2891 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2892 && !memory_address_p (GET_MODE (x), new_rtx))
2893 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2895 return replace_equiv_address_nv (x, new_rtx);
2898 /* Handle insn_list USE that a call to a pure function may generate. */
2899 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2901 if (new_rtx != XEXP (x, 0))
2902 return gen_rtx_USE (GET_MODE (x), new_rtx);
2907 gcc_assert (insn && DEBUG_INSN_P (insn));
2917 /* Process each of our operands recursively. If any have changed, make a
2919 fmt = GET_RTX_FORMAT (code);
2920 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2924 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2926 if (new_rtx != XEXP (x, i) && ! copied)
2928 x = shallow_copy_rtx (x);
2931 XEXP (x, i) = new_rtx;
2933 else if (*fmt == 'E')
2936 for (j = 0; j < XVECLEN (x, i); j++)
2938 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2940 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2942 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2946 x = shallow_copy_rtx (x);
2949 XVEC (x, i) = new_v;
2952 XVECEXP (x, i, j) = new_rtx;
2961 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2963 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2966 /* Scan rtx X for modifications of elimination target registers. Update
2967 the table of eliminables to reflect the changed state. MEM_MODE is
2968 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2971 elimination_effects (rtx x, enum machine_mode mem_mode)
2973 enum rtx_code code = GET_CODE (x);
2974 struct elim_table *ep;
2999 /* First handle the case where we encounter a bare register that
3000 is eliminable. Replace it with a PLUS. */
3001 if (regno < FIRST_PSEUDO_REGISTER)
3003 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3005 if (ep->from_rtx == x && ep->can_eliminate)
3008 ep->ref_outside_mem = 1;
3013 else if (reg_renumber[regno] < 0
3015 && reg_equiv_constant (regno)
3016 && ! function_invariant_p (reg_equiv_constant (regno)))
3017 elimination_effects (reg_equiv_constant (regno), mem_mode);
3026 /* If we modify the source of an elimination rule, disable it. */
3027 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3028 if (ep->from_rtx == XEXP (x, 0))
3029 ep->can_eliminate = 0;
3031 /* If we modify the target of an elimination rule by adding a constant,
3032 update its offset. If we modify the target in any other way, we'll
3033 have to disable the rule as well. */
3034 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3035 if (ep->to_rtx == XEXP (x, 0))
3037 int size = GET_MODE_SIZE (mem_mode);
3039 /* If more bytes than MEM_MODE are pushed, account for them. */
3040 #ifdef PUSH_ROUNDING
3041 if (ep->to_rtx == stack_pointer_rtx)
3042 size = PUSH_ROUNDING (size);
3044 if (code == PRE_DEC || code == POST_DEC)
3046 else if (code == PRE_INC || code == POST_INC)
3048 else if (code == PRE_MODIFY || code == POST_MODIFY)
3050 if (GET_CODE (XEXP (x, 1)) == PLUS
3051 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3052 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3053 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3055 ep->can_eliminate = 0;
3059 /* These two aren't unary operators. */
3060 if (code == POST_MODIFY || code == PRE_MODIFY)
3063 /* Fall through to generic unary operation case. */
3064 case STRICT_LOW_PART:
3066 case SIGN_EXTEND: case ZERO_EXTEND:
3067 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3068 case FLOAT: case FIX:
3069 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3078 elimination_effects (XEXP (x, 0), mem_mode);
3082 if (REG_P (SUBREG_REG (x))
3083 && (GET_MODE_SIZE (GET_MODE (x))
3084 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3086 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3089 elimination_effects (SUBREG_REG (x), mem_mode);
3093 /* If using a register that is the source of an eliminate we still
3094 think can be performed, note it cannot be performed since we don't
3095 know how this register is used. */
3096 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3097 if (ep->from_rtx == XEXP (x, 0))
3098 ep->can_eliminate = 0;
3100 elimination_effects (XEXP (x, 0), mem_mode);
3104 /* If clobbering a register that is the replacement register for an
3105 elimination we still think can be performed, note that it cannot
3106 be performed. Otherwise, we need not be concerned about it. */
3107 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3108 if (ep->to_rtx == XEXP (x, 0))
3109 ep->can_eliminate = 0;
3111 elimination_effects (XEXP (x, 0), mem_mode);
3115 /* Check for setting a register that we know about. */
3116 if (REG_P (SET_DEST (x)))
3118 /* See if this is setting the replacement register for an
3121 If DEST is the hard frame pointer, we do nothing because we
3122 assume that all assignments to the frame pointer are for
3123 non-local gotos and are being done at a time when they are valid
3124 and do not disturb anything else. Some machines want to
3125 eliminate a fake argument pointer (or even a fake frame pointer)
3126 with either the real frame or the stack pointer. Assignments to
3127 the hard frame pointer must not prevent this elimination. */
3129 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3131 if (ep->to_rtx == SET_DEST (x)
3132 && SET_DEST (x) != hard_frame_pointer_rtx)
3134 /* If it is being incremented, adjust the offset. Otherwise,
3135 this elimination can't be done. */
3136 rtx src = SET_SRC (x);
3138 if (GET_CODE (src) == PLUS
3139 && XEXP (src, 0) == SET_DEST (x)
3140 && CONST_INT_P (XEXP (src, 1)))
3141 ep->offset -= INTVAL (XEXP (src, 1));
3143 ep->can_eliminate = 0;
3147 elimination_effects (SET_DEST (x), VOIDmode);
3148 elimination_effects (SET_SRC (x), VOIDmode);
3152 /* Our only special processing is to pass the mode of the MEM to our
3154 elimination_effects (XEXP (x, 0), GET_MODE (x));
3161 fmt = GET_RTX_FORMAT (code);
3162 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3165 elimination_effects (XEXP (x, i), mem_mode);
3166 else if (*fmt == 'E')
3167 for (j = 0; j < XVECLEN (x, i); j++)
3168 elimination_effects (XVECEXP (x, i, j), mem_mode);
3172 /* Descend through rtx X and verify that no references to eliminable registers
3173 remain. If any do remain, mark the involved register as not
3177 check_eliminable_occurrences (rtx x)
3186 code = GET_CODE (x);
3188 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3190 struct elim_table *ep;
3192 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3193 if (ep->from_rtx == x)
3194 ep->can_eliminate = 0;
3198 fmt = GET_RTX_FORMAT (code);
3199 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3202 check_eliminable_occurrences (XEXP (x, i));
3203 else if (*fmt == 'E')
3206 for (j = 0; j < XVECLEN (x, i); j++)
3207 check_eliminable_occurrences (XVECEXP (x, i, j));
3212 /* Scan INSN and eliminate all eliminable registers in it.
3214 If REPLACE is nonzero, do the replacement destructively. Also
3215 delete the insn as dead it if it is setting an eliminable register.
3217 If REPLACE is zero, do all our allocations in reload_obstack.
3219 If no eliminations were done and this insn doesn't require any elimination
3220 processing (these are not identical conditions: it might be updating sp,
3221 but not referencing fp; this needs to be seen during reload_as_needed so
3222 that the offset between fp and sp can be taken into consideration), zero
3223 is returned. Otherwise, 1 is returned. */
3226 eliminate_regs_in_insn (rtx insn, int replace)
3228 int icode = recog_memoized (insn);
3229 rtx old_body = PATTERN (insn);
3230 int insn_is_asm = asm_noperands (old_body) >= 0;
3231 rtx old_set = single_set (insn);
3235 rtx substed_operand[MAX_RECOG_OPERANDS];
3236 rtx orig_operand[MAX_RECOG_OPERANDS];
3237 struct elim_table *ep;
3238 rtx plus_src, plus_cst_src;
3240 if (! insn_is_asm && icode < 0)
3242 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3243 || GET_CODE (PATTERN (insn)) == CLOBBER
3244 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3245 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3246 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3247 || DEBUG_INSN_P (insn));
3248 if (DEBUG_INSN_P (insn))
3249 INSN_VAR_LOCATION_LOC (insn)
3250 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3254 if (old_set != 0 && REG_P (SET_DEST (old_set))
3255 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3257 /* Check for setting an eliminable register. */
3258 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3259 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3261 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3262 /* If this is setting the frame pointer register to the
3263 hardware frame pointer register and this is an elimination
3264 that will be done (tested above), this insn is really
3265 adjusting the frame pointer downward to compensate for
3266 the adjustment done before a nonlocal goto. */
3267 if (ep->from == FRAME_POINTER_REGNUM
3268 && ep->to == HARD_FRAME_POINTER_REGNUM)
3270 rtx base = SET_SRC (old_set);
3271 rtx base_insn = insn;
3272 HOST_WIDE_INT offset = 0;
3274 while (base != ep->to_rtx)
3276 rtx prev_insn, prev_set;
3278 if (GET_CODE (base) == PLUS
3279 && CONST_INT_P (XEXP (base, 1)))
3281 offset += INTVAL (XEXP (base, 1));
3282 base = XEXP (base, 0);
3284 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3285 && (prev_set = single_set (prev_insn)) != 0
3286 && rtx_equal_p (SET_DEST (prev_set), base))
3288 base = SET_SRC (prev_set);
3289 base_insn = prev_insn;
3295 if (base == ep->to_rtx)
3298 = plus_constant (ep->to_rtx, offset - ep->offset);
3300 new_body = old_body;
3303 new_body = copy_insn (old_body);
3304 if (REG_NOTES (insn))
3305 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3307 PATTERN (insn) = new_body;
3308 old_set = single_set (insn);
3310 /* First see if this insn remains valid when we
3311 make the change. If not, keep the INSN_CODE
3312 the same and let reload fit it up. */
3313 validate_change (insn, &SET_SRC (old_set), src, 1);
3314 validate_change (insn, &SET_DEST (old_set),
3316 if (! apply_change_group ())
3318 SET_SRC (old_set) = src;
3319 SET_DEST (old_set) = ep->to_rtx;
3328 /* In this case this insn isn't serving a useful purpose. We
3329 will delete it in reload_as_needed once we know that this
3330 elimination is, in fact, being done.
3332 If REPLACE isn't set, we can't delete this insn, but needn't
3333 process it since it won't be used unless something changes. */
3336 delete_dead_insn (insn);
3344 /* We allow one special case which happens to work on all machines we
3345 currently support: a single set with the source or a REG_EQUAL
3346 note being a PLUS of an eliminable register and a constant. */
3347 plus_src = plus_cst_src = 0;
3348 if (old_set && REG_P (SET_DEST (old_set)))
3350 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3351 plus_src = SET_SRC (old_set);
3352 /* First see if the source is of the form (plus (...) CST). */
3354 && CONST_INT_P (XEXP (plus_src, 1)))
3355 plus_cst_src = plus_src;
3356 else if (REG_P (SET_SRC (old_set))
3359 /* Otherwise, see if we have a REG_EQUAL note of the form
3360 (plus (...) CST). */
3362 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3364 if ((REG_NOTE_KIND (links) == REG_EQUAL
3365 || REG_NOTE_KIND (links) == REG_EQUIV)
3366 && GET_CODE (XEXP (links, 0)) == PLUS
3367 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3369 plus_cst_src = XEXP (links, 0);
3375 /* Check that the first operand of the PLUS is a hard reg or
3376 the lowpart subreg of one. */
3379 rtx reg = XEXP (plus_cst_src, 0);
3380 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3381 reg = SUBREG_REG (reg);
3383 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3389 rtx reg = XEXP (plus_cst_src, 0);
3390 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3392 if (GET_CODE (reg) == SUBREG)
3393 reg = SUBREG_REG (reg);
3395 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3396 if (ep->from_rtx == reg && ep->can_eliminate)
3398 rtx to_rtx = ep->to_rtx;
3399 offset += ep->offset;
3400 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3402 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3403 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3405 /* If we have a nonzero offset, and the source is already
3406 a simple REG, the following transformation would
3407 increase the cost of the insn by replacing a simple REG
3408 with (plus (reg sp) CST). So try only when we already
3409 had a PLUS before. */
3410 if (offset == 0 || plus_src)
3412 rtx new_src = plus_constant (to_rtx, offset);
3414 new_body = old_body;
3417 new_body = copy_insn (old_body);
3418 if (REG_NOTES (insn))
3419 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3421 PATTERN (insn) = new_body;
3422 old_set = single_set (insn);
3424 /* First see if this insn remains valid when we make the
3425 change. If not, try to replace the whole pattern with
3426 a simple set (this may help if the original insn was a
3427 PARALLEL that was only recognized as single_set due to
3428 REG_UNUSED notes). If this isn't valid either, keep
3429 the INSN_CODE the same and let reload fix it up. */
3430 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3432 rtx new_pat = gen_rtx_SET (VOIDmode,
3433 SET_DEST (old_set), new_src);
3435 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3436 SET_SRC (old_set) = new_src;
3443 /* This can't have an effect on elimination offsets, so skip right
3449 /* Determine the effects of this insn on elimination offsets. */
3450 elimination_effects (old_body, VOIDmode);
3452 /* Eliminate all eliminable registers occurring in operands that
3453 can be handled by reload. */
3454 extract_insn (insn);
3455 for (i = 0; i < recog_data.n_operands; i++)
3457 orig_operand[i] = recog_data.operand[i];
3458 substed_operand[i] = recog_data.operand[i];
3460 /* For an asm statement, every operand is eliminable. */
3461 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3463 bool is_set_src, in_plus;
3465 /* Check for setting a register that we know about. */
3466 if (recog_data.operand_type[i] != OP_IN
3467 && REG_P (orig_operand[i]))
3469 /* If we are assigning to a register that can be eliminated, it
3470 must be as part of a PARALLEL, since the code above handles
3471 single SETs. We must indicate that we can no longer
3472 eliminate this reg. */
3473 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3475 if (ep->from_rtx == orig_operand[i])
3476 ep->can_eliminate = 0;
3479 /* Companion to the above plus substitution, we can allow
3480 invariants as the source of a plain move. */
3483 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3487 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3488 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3492 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3493 replace ? insn : NULL_RTX,
3494 is_set_src || in_plus, false);
3495 if (substed_operand[i] != orig_operand[i])
3497 /* Terminate the search in check_eliminable_occurrences at
3499 *recog_data.operand_loc[i] = 0;
3501 /* If an output operand changed from a REG to a MEM and INSN is an
3502 insn, write a CLOBBER insn. */
3503 if (recog_data.operand_type[i] != OP_IN
3504 && REG_P (orig_operand[i])
3505 && MEM_P (substed_operand[i])
3507 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3511 for (i = 0; i < recog_data.n_dups; i++)
3512 *recog_data.dup_loc[i]
3513 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3515 /* If any eliminable remain, they aren't eliminable anymore. */
3516 check_eliminable_occurrences (old_body);
3518 /* Substitute the operands; the new values are in the substed_operand
3520 for (i = 0; i < recog_data.n_operands; i++)
3521 *recog_data.operand_loc[i] = substed_operand[i];
3522 for (i = 0; i < recog_data.n_dups; i++)
3523 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3525 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3526 re-recognize the insn. We do this in case we had a simple addition
3527 but now can do this as a load-address. This saves an insn in this
3529 If re-recognition fails, the old insn code number will still be used,
3530 and some register operands may have changed into PLUS expressions.
3531 These will be handled by find_reloads by loading them into a register
3536 /* If we aren't replacing things permanently and we changed something,
3537 make another copy to ensure that all the RTL is new. Otherwise
3538 things can go wrong if find_reload swaps commutative operands
3539 and one is inside RTL that has been copied while the other is not. */
3540 new_body = old_body;
3543 new_body = copy_insn (old_body);
3544 if (REG_NOTES (insn))
3545 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3547 PATTERN (insn) = new_body;
3549 /* If we had a move insn but now we don't, rerecognize it. This will
3550 cause spurious re-recognition if the old move had a PARALLEL since
3551 the new one still will, but we can't call single_set without
3552 having put NEW_BODY into the insn and the re-recognition won't
3553 hurt in this rare case. */
3554 /* ??? Why this huge if statement - why don't we just rerecognize the
3558 && ((REG_P (SET_SRC (old_set))
3559 && (GET_CODE (new_body) != SET
3560 || !REG_P (SET_SRC (new_body))))
3561 /* If this was a load from or store to memory, compare
3562 the MEM in recog_data.operand to the one in the insn.
3563 If they are not equal, then rerecognize the insn. */
3565 && ((MEM_P (SET_SRC (old_set))
3566 && SET_SRC (old_set) != recog_data.operand[1])
3567 || (MEM_P (SET_DEST (old_set))
3568 && SET_DEST (old_set) != recog_data.operand[0])))
3569 /* If this was an add insn before, rerecognize. */
3570 || GET_CODE (SET_SRC (old_set)) == PLUS))
3572 int new_icode = recog (PATTERN (insn), insn, 0);
3574 INSN_CODE (insn) = new_icode;
3578 /* Restore the old body. If there were any changes to it, we made a copy
3579 of it while the changes were still in place, so we'll correctly return
3580 a modified insn below. */
3583 /* Restore the old body. */
3584 for (i = 0; i < recog_data.n_operands; i++)
3585 /* Restoring a top-level match_parallel would clobber the new_body
3586 we installed in the insn. */
3587 if (recog_data.operand_loc[i] != &PATTERN (insn))
3588 *recog_data.operand_loc[i] = orig_operand[i];
3589 for (i = 0; i < recog_data.n_dups; i++)
3590 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3593 /* Update all elimination pairs to reflect the status after the current
3594 insn. The changes we make were determined by the earlier call to
3595 elimination_effects.
3597 We also detect cases where register elimination cannot be done,
3598 namely, if a register would be both changed and referenced outside a MEM
3599 in the resulting insn since such an insn is often undefined and, even if
3600 not, we cannot know what meaning will be given to it. Note that it is
3601 valid to have a register used in an address in an insn that changes it
3602 (presumably with a pre- or post-increment or decrement).
3604 If anything changes, return nonzero. */
3606 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3608 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3609 ep->can_eliminate = 0;
3611 ep->ref_outside_mem = 0;
3613 if (ep->previous_offset != ep->offset)
3618 /* If we changed something, perform elimination in REG_NOTES. This is
3619 needed even when REPLACE is zero because a REG_DEAD note might refer
3620 to a register that we eliminate and could cause a different number
3621 of spill registers to be needed in the final reload pass than in
3623 if (val && REG_NOTES (insn) != 0)
3625 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3631 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3632 register allocator. INSN is the instruction we need to examine, we perform
3633 eliminations in its operands and record cases where eliminating a reg with
3634 an invariant equivalence would add extra cost. */
3637 elimination_costs_in_insn (rtx insn)
3639 int icode = recog_memoized (insn);
3640 rtx old_body = PATTERN (insn);
3641 int insn_is_asm = asm_noperands (old_body) >= 0;
3642 rtx old_set = single_set (insn);
3644 rtx orig_operand[MAX_RECOG_OPERANDS];
3645 rtx orig_dup[MAX_RECOG_OPERANDS];
3646 struct elim_table *ep;
3647 rtx plus_src, plus_cst_src;
3650 if (! insn_is_asm && icode < 0)
3652 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3653 || GET_CODE (PATTERN (insn)) == CLOBBER
3654 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3655 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3656 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3657 || DEBUG_INSN_P (insn));
3661 if (old_set != 0 && REG_P (SET_DEST (old_set))
3662 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3664 /* Check for setting an eliminable register. */
3665 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3666 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3670 /* We allow one special case which happens to work on all machines we
3671 currently support: a single set with the source or a REG_EQUAL
3672 note being a PLUS of an eliminable register and a constant. */
3673 plus_src = plus_cst_src = 0;
3675 if (old_set && REG_P (SET_DEST (old_set)))
3678 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3679 plus_src = SET_SRC (old_set);
3680 /* First see if the source is of the form (plus (...) CST). */
3682 && CONST_INT_P (XEXP (plus_src, 1)))
3683 plus_cst_src = plus_src;
3684 else if (REG_P (SET_SRC (old_set))
3687 /* Otherwise, see if we have a REG_EQUAL note of the form
3688 (plus (...) CST). */
3690 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3692 if ((REG_NOTE_KIND (links) == REG_EQUAL
3693 || REG_NOTE_KIND (links) == REG_EQUIV)
3694 && GET_CODE (XEXP (links, 0)) == PLUS
3695 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3697 plus_cst_src = XEXP (links, 0);
3704 /* Determine the effects of this insn on elimination offsets. */
3705 elimination_effects (old_body, VOIDmode);
3707 /* Eliminate all eliminable registers occurring in operands that
3708 can be handled by reload. */
3709 extract_insn (insn);
3710 for (i = 0; i < recog_data.n_dups; i++)
3711 orig_dup[i] = *recog_data.dup_loc[i];
3713 for (i = 0; i < recog_data.n_operands; i++)
3715 orig_operand[i] = recog_data.operand[i];
3717 /* For an asm statement, every operand is eliminable. */
3718 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3720 bool is_set_src, in_plus;
3722 /* Check for setting a register that we know about. */
3723 if (recog_data.operand_type[i] != OP_IN
3724 && REG_P (orig_operand[i]))
3726 /* If we are assigning to a register that can be eliminated, it
3727 must be as part of a PARALLEL, since the code above handles
3728 single SETs. We must indicate that we can no longer
3729 eliminate this reg. */
3730 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3732 if (ep->from_rtx == orig_operand[i])
3733 ep->can_eliminate = 0;
3736 /* Companion to the above plus substitution, we can allow
3737 invariants as the source of a plain move. */
3739 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3741 if (is_set_src && !sets_reg_p)
3742 note_reg_elim_costly (&SET_SRC (old_set), insn);
3744 if (plus_src && sets_reg_p
3745 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3746 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3749 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3751 is_set_src || in_plus, true);
3752 /* Terminate the search in check_eliminable_occurrences at
3754 *recog_data.operand_loc[i] = 0;
3758 for (i = 0; i < recog_data.n_dups; i++)
3759 *recog_data.dup_loc[i]
3760 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3762 /* If any eliminable remain, they aren't eliminable anymore. */
3763 check_eliminable_occurrences (old_body);
3765 /* Restore the old body. */
3766 for (i = 0; i < recog_data.n_operands; i++)
3767 *recog_data.operand_loc[i] = orig_operand[i];
3768 for (i = 0; i < recog_data.n_dups; i++)
3769 *recog_data.dup_loc[i] = orig_dup[i];
3771 /* Update all elimination pairs to reflect the status after the current
3772 insn. The changes we make were determined by the earlier call to
3773 elimination_effects. */
3775 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3777 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3778 ep->can_eliminate = 0;
3780 ep->ref_outside_mem = 0;
3786 /* Loop through all elimination pairs.
3787 Recalculate the number not at initial offset.
3789 Compute the maximum offset (minimum offset if the stack does not
3790 grow downward) for each elimination pair. */
3793 update_eliminable_offsets (void)
3795 struct elim_table *ep;
3797 num_not_at_initial_offset = 0;
3798 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3800 ep->previous_offset = ep->offset;
3801 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3802 num_not_at_initial_offset++;
3806 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3807 replacement we currently believe is valid, mark it as not eliminable if X
3808 modifies DEST in any way other than by adding a constant integer to it.
3810 If DEST is the frame pointer, we do nothing because we assume that
3811 all assignments to the hard frame pointer are nonlocal gotos and are being
3812 done at a time when they are valid and do not disturb anything else.
3813 Some machines want to eliminate a fake argument pointer with either the
3814 frame or stack pointer. Assignments to the hard frame pointer must not
3815 prevent this elimination.
3817 Called via note_stores from reload before starting its passes to scan
3818 the insns of the function. */
3821 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3825 /* A SUBREG of a hard register here is just changing its mode. We should
3826 not see a SUBREG of an eliminable hard register, but check just in
3828 if (GET_CODE (dest) == SUBREG)
3829 dest = SUBREG_REG (dest);
3831 if (dest == hard_frame_pointer_rtx)
3834 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3835 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3836 && (GET_CODE (x) != SET
3837 || GET_CODE (SET_SRC (x)) != PLUS
3838 || XEXP (SET_SRC (x), 0) != dest
3839 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3841 reg_eliminate[i].can_eliminate_previous
3842 = reg_eliminate[i].can_eliminate = 0;
3847 /* Verify that the initial elimination offsets did not change since the
3848 last call to set_initial_elim_offsets. This is used to catch cases
3849 where something illegal happened during reload_as_needed that could
3850 cause incorrect code to be generated if we did not check for it. */
3853 verify_initial_elim_offsets (void)
3857 if (!num_eliminable)
3860 #ifdef ELIMINABLE_REGS
3862 struct elim_table *ep;
3864 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3866 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3867 if (t != ep->initial_offset)
3872 INITIAL_FRAME_POINTER_OFFSET (t);
3873 if (t != reg_eliminate[0].initial_offset)
3880 /* Reset all offsets on eliminable registers to their initial values. */
3883 set_initial_elim_offsets (void)
3885 struct elim_table *ep = reg_eliminate;
3887 #ifdef ELIMINABLE_REGS
3888 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3890 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3891 ep->previous_offset = ep->offset = ep->initial_offset;
3894 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3895 ep->previous_offset = ep->offset = ep->initial_offset;
3898 num_not_at_initial_offset = 0;
3901 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3904 set_initial_eh_label_offset (rtx label)
3906 set_label_offsets (label, NULL_RTX, 1);
3909 /* Initialize the known label offsets.
3910 Set a known offset for each forced label to be at the initial offset
3911 of each elimination. We do this because we assume that all
3912 computed jumps occur from a location where each elimination is
3913 at its initial offset.
3914 For all other labels, show that we don't know the offsets. */
3917 set_initial_label_offsets (void)
3920 memset (offsets_known_at, 0, num_labels);
3922 for (x = forced_labels; x; x = XEXP (x, 1))
3924 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3926 for (x = nonlocal_goto_handler_labels; x; x = XEXP (x, 1))
3928 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3930 for_each_eh_label (set_initial_eh_label_offset);
3933 /* Set all elimination offsets to the known values for the code label given
3937 set_offsets_for_label (rtx insn)
3940 int label_nr = CODE_LABEL_NUMBER (insn);
3941 struct elim_table *ep;
3943 num_not_at_initial_offset = 0;
3944 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3946 ep->offset = ep->previous_offset
3947 = offsets_at[label_nr - first_label_num][i];
3948 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3949 num_not_at_initial_offset++;
3953 /* See if anything that happened changes which eliminations are valid.
3954 For example, on the SPARC, whether or not the frame pointer can
3955 be eliminated can depend on what registers have been used. We need
3956 not check some conditions again (such as flag_omit_frame_pointer)
3957 since they can't have changed. */
3960 update_eliminables (HARD_REG_SET *pset)
3962 int previous_frame_pointer_needed = frame_pointer_needed;
3963 struct elim_table *ep;
3965 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3966 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3967 && targetm.frame_pointer_required ())
3968 #ifdef ELIMINABLE_REGS
3969 || ! targetm.can_eliminate (ep->from, ep->to)
3972 ep->can_eliminate = 0;
3974 /* Look for the case where we have discovered that we can't replace
3975 register A with register B and that means that we will now be
3976 trying to replace register A with register C. This means we can
3977 no longer replace register C with register B and we need to disable
3978 such an elimination, if it exists. This occurs often with A == ap,
3979 B == sp, and C == fp. */
3981 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3983 struct elim_table *op;
3986 if (! ep->can_eliminate && ep->can_eliminate_previous)
3988 /* Find the current elimination for ep->from, if there is a
3990 for (op = reg_eliminate;
3991 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3992 if (op->from == ep->from && op->can_eliminate)
3998 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
4000 for (op = reg_eliminate;
4001 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
4002 if (op->from == new_to && op->to == ep->to)
4003 op->can_eliminate = 0;
4007 /* See if any registers that we thought we could eliminate the previous
4008 time are no longer eliminable. If so, something has changed and we
4009 must spill the register. Also, recompute the number of eliminable
4010 registers and see if the frame pointer is needed; it is if there is
4011 no elimination of the frame pointer that we can perform. */
4013 frame_pointer_needed = 1;
4014 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4016 if (ep->can_eliminate
4017 && ep->from == FRAME_POINTER_REGNUM
4018 && ep->to != HARD_FRAME_POINTER_REGNUM
4019 && (! SUPPORTS_STACK_ALIGNMENT
4020 || ! crtl->stack_realign_needed))
4021 frame_pointer_needed = 0;
4023 if (! ep->can_eliminate && ep->can_eliminate_previous)
4025 ep->can_eliminate_previous = 0;
4026 SET_HARD_REG_BIT (*pset, ep->from);
4031 /* If we didn't need a frame pointer last time, but we do now, spill
4032 the hard frame pointer. */
4033 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4034 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4037 /* Return true if X is used as the target register of an elimination. */
4040 elimination_target_reg_p (rtx x)
4042 struct elim_table *ep;
4044 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4045 if (ep->to_rtx == x && ep->can_eliminate)
4051 /* Initialize the table of registers to eliminate.
4052 Pre-condition: global flag frame_pointer_needed has been set before
4053 calling this function. */
4056 init_elim_table (void)
4058 struct elim_table *ep;
4059 #ifdef ELIMINABLE_REGS
4060 const struct elim_table_1 *ep1;
4064 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4068 #ifdef ELIMINABLE_REGS
4069 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4070 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4072 ep->from = ep1->from;
4074 ep->can_eliminate = ep->can_eliminate_previous
4075 = (targetm.can_eliminate (ep->from, ep->to)
4076 && ! (ep->to == STACK_POINTER_REGNUM
4077 && frame_pointer_needed
4078 && (! SUPPORTS_STACK_ALIGNMENT
4079 || ! stack_realign_fp)));
4082 reg_eliminate[0].from = reg_eliminate_1[0].from;
4083 reg_eliminate[0].to = reg_eliminate_1[0].to;
4084 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4085 = ! frame_pointer_needed;
4088 /* Count the number of eliminable registers and build the FROM and TO
4089 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4090 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4091 We depend on this. */
4092 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4094 num_eliminable += ep->can_eliminate;
4095 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4096 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4100 /* Find all the pseudo registers that didn't get hard regs
4101 but do have known equivalent constants or memory slots.
4102 These include parameters (known equivalent to parameter slots)
4103 and cse'd or loop-moved constant memory addresses.
4105 Record constant equivalents in reg_equiv_constant
4106 so they will be substituted by find_reloads.
4107 Record memory equivalents in reg_mem_equiv so they can
4108 be substituted eventually by altering the REG-rtx's. */
4111 init_eliminable_invariants (rtx first, bool do_subregs)
4118 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4120 reg_max_ref_width = NULL;
4122 num_eliminable_invariants = 0;
4124 first_label_num = get_first_label_num ();
4125 num_labels = max_label_num () - first_label_num;
4127 /* Allocate the tables used to store offset information at labels. */
4128 offsets_known_at = XNEWVEC (char, num_labels);
4129 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4131 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4132 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4133 find largest such for each pseudo. FIRST is the head of the insn
4136 for (insn = first; insn; insn = NEXT_INSN (insn))
4138 rtx set = single_set (insn);
4140 /* We may introduce USEs that we want to remove at the end, so
4141 we'll mark them with QImode. Make sure there are no
4142 previously-marked insns left by say regmove. */
4143 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4144 && GET_MODE (insn) != VOIDmode)
4145 PUT_MODE (insn, VOIDmode);
4147 if (do_subregs && NONDEBUG_INSN_P (insn))
4148 scan_paradoxical_subregs (PATTERN (insn));
4150 if (set != 0 && REG_P (SET_DEST (set)))
4152 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4158 i = REGNO (SET_DEST (set));
4161 if (i <= LAST_VIRTUAL_REGISTER)
4164 /* If flag_pic and we have constant, verify it's legitimate. */
4166 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4168 /* It can happen that a REG_EQUIV note contains a MEM
4169 that is not a legitimate memory operand. As later
4170 stages of reload assume that all addresses found
4171 in the reg_equiv_* arrays were originally legitimate,
4172 we ignore such REG_EQUIV notes. */
4173 if (memory_operand (x, VOIDmode))
4175 /* Always unshare the equivalence, so we can
4176 substitute into this insn without touching the
4178 reg_equiv_memory_loc (i) = copy_rtx (x);
4180 else if (function_invariant_p (x))
4182 enum machine_mode mode;
4184 mode = GET_MODE (SET_DEST (set));
4185 if (GET_CODE (x) == PLUS)
4187 /* This is PLUS of frame pointer and a constant,
4188 and might be shared. Unshare it. */
4189 reg_equiv_invariant (i) = copy_rtx (x);
4190 num_eliminable_invariants++;
4192 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4194 reg_equiv_invariant (i) = x;
4195 num_eliminable_invariants++;
4197 else if (targetm.legitimate_constant_p (mode, x))
4198 reg_equiv_constant (i) = x;
4201 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4202 if (! reg_equiv_memory_loc (i))
4203 reg_equiv_init (i) = NULL_RTX;
4208 reg_equiv_init (i) = NULL_RTX;
4213 reg_equiv_init (i) = NULL_RTX;
4218 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4219 if (reg_equiv_init (i))
4221 fprintf (dump_file, "init_insns for %u: ", i);
4222 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4223 fprintf (dump_file, "\n");
4227 /* Indicate that we no longer have known memory locations or constants.
4228 Free all data involved in tracking these. */
4231 free_reg_equiv (void)
4236 free (offsets_known_at);
4239 offsets_known_at = 0;
4241 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4242 if (reg_equiv_alt_mem_list (i))
4243 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4244 VEC_free (reg_equivs_t, gc, reg_equivs);
4249 /* Kick all pseudos out of hard register REGNO.
4251 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4252 because we found we can't eliminate some register. In the case, no pseudos
4253 are allowed to be in the register, even if they are only in a block that
4254 doesn't require spill registers, unlike the case when we are spilling this
4255 hard reg to produce another spill register.
4257 Return nonzero if any pseudos needed to be kicked out. */
4260 spill_hard_reg (unsigned int regno, int cant_eliminate)
4266 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4267 df_set_regs_ever_live (regno, true);
4270 /* Spill every pseudo reg that was allocated to this reg
4271 or to something that overlaps this reg. */
4273 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4274 if (reg_renumber[i] >= 0
4275 && (unsigned int) reg_renumber[i] <= regno
4276 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4277 SET_REGNO_REG_SET (&spilled_pseudos, i);
4280 /* After find_reload_regs has been run for all insn that need reloads,
4281 and/or spill_hard_regs was called, this function is used to actually
4282 spill pseudo registers and try to reallocate them. It also sets up the
4283 spill_regs array for use by choose_reload_regs. */
4286 finish_spills (int global)
4288 struct insn_chain *chain;
4289 int something_changed = 0;
4291 reg_set_iterator rsi;
4293 /* Build the spill_regs array for the function. */
4294 /* If there are some registers still to eliminate and one of the spill regs
4295 wasn't ever used before, additional stack space may have to be
4296 allocated to store this register. Thus, we may have changed the offset
4297 between the stack and frame pointers, so mark that something has changed.
4299 One might think that we need only set VAL to 1 if this is a call-used
4300 register. However, the set of registers that must be saved by the
4301 prologue is not identical to the call-used set. For example, the
4302 register used by the call insn for the return PC is a call-used register,
4303 but must be saved by the prologue. */
4306 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4307 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4309 spill_reg_order[i] = n_spills;
4310 spill_regs[n_spills++] = i;
4311 if (num_eliminable && ! df_regs_ever_live_p (i))
4312 something_changed = 1;
4313 df_set_regs_ever_live (i, true);
4316 spill_reg_order[i] = -1;
4318 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4319 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4321 /* Record the current hard register the pseudo is allocated to
4322 in pseudo_previous_regs so we avoid reallocating it to the
4323 same hard reg in a later pass. */
4324 gcc_assert (reg_renumber[i] >= 0);
4326 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4327 /* Mark it as no longer having a hard register home. */
4328 reg_renumber[i] = -1;
4329 if (ira_conflicts_p)
4330 /* Inform IRA about the change. */
4331 ira_mark_allocation_change (i);
4332 /* We will need to scan everything again. */
4333 something_changed = 1;
4336 /* Retry global register allocation if possible. */
4337 if (global && ira_conflicts_p)
4341 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4342 /* For every insn that needs reloads, set the registers used as spill
4343 regs in pseudo_forbidden_regs for every pseudo live across the
4345 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4347 EXECUTE_IF_SET_IN_REG_SET
4348 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4350 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4351 chain->used_spill_regs);
4353 EXECUTE_IF_SET_IN_REG_SET
4354 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4356 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4357 chain->used_spill_regs);
4361 /* Retry allocating the pseudos spilled in IRA and the
4362 reload. For each reg, merge the various reg sets that
4363 indicate which hard regs can't be used, and call
4364 ira_reassign_pseudos. */
4365 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4366 if (reg_old_renumber[i] != reg_renumber[i])
4368 if (reg_renumber[i] < 0)
4369 temp_pseudo_reg_arr[n++] = i;
4371 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4373 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4374 bad_spill_regs_global,
4375 pseudo_forbidden_regs, pseudo_previous_regs,
4377 something_changed = 1;
4379 /* Fix up the register information in the insn chain.
4380 This involves deleting those of the spilled pseudos which did not get
4381 a new hard register home from the live_{before,after} sets. */
4382 for (chain = reload_insn_chain; chain; chain = chain->next)
4384 HARD_REG_SET used_by_pseudos;
4385 HARD_REG_SET used_by_pseudos2;
4387 if (! ira_conflicts_p)
4389 /* Don't do it for IRA because IRA and the reload still can
4390 assign hard registers to the spilled pseudos on next
4391 reload iterations. */
4392 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4393 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4395 /* Mark any unallocated hard regs as available for spills. That
4396 makes inheritance work somewhat better. */
4397 if (chain->need_reload)
4399 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4400 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4401 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4403 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4404 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4405 /* Value of chain->used_spill_regs from previous iteration
4406 may be not included in the value calculated here because
4407 of possible removing caller-saves insns (see function
4408 delete_caller_save_insns. */
4409 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4410 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4414 CLEAR_REG_SET (&changed_allocation_pseudos);
4415 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4416 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4418 int regno = reg_renumber[i];
4419 if (reg_old_renumber[i] == regno)
4422 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4424 alter_reg (i, reg_old_renumber[i], false);
4425 reg_old_renumber[i] = regno;
4429 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4431 fprintf (dump_file, " Register %d now in %d.\n\n",
4432 i, reg_renumber[i]);
4436 return something_changed;
4439 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4442 scan_paradoxical_subregs (rtx x)
4446 enum rtx_code code = GET_CODE (x);
4457 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4465 if (REG_P (SUBREG_REG (x))
4466 && (GET_MODE_SIZE (GET_MODE (x))
4467 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4469 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4470 = GET_MODE_SIZE (GET_MODE (x));
4471 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4479 fmt = GET_RTX_FORMAT (code);
4480 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4483 scan_paradoxical_subregs (XEXP (x, i));
4484 else if (fmt[i] == 'E')
4487 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4488 scan_paradoxical_subregs (XVECEXP (x, i, j));
4493 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4494 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4495 and apply the corresponding narrowing subreg to *OTHER_PTR.
4496 Return true if the operands were changed, false otherwise. */
4499 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4501 rtx op, inner, other, tem;
4504 if (!paradoxical_subreg_p (op))
4506 inner = SUBREG_REG (op);
4509 tem = gen_lowpart_common (GET_MODE (inner), other);
4513 /* If the lowpart operation turned a hard register into a subreg,
4514 rather than simplifying it to another hard register, then the
4515 mode change cannot be properly represented. For example, OTHER
4516 might be valid in its current mode, but not in the new one. */
4517 if (GET_CODE (tem) == SUBREG
4519 && HARD_REGISTER_P (other))
4527 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4528 examine all of the reload insns between PREV and NEXT exclusive, and
4529 annotate all that may trap. */
4532 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4534 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4537 if (!insn_could_throw_p (insn))
4538 remove_note (insn, note);
4539 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4542 /* Reload pseudo-registers into hard regs around each insn as needed.
4543 Additional register load insns are output before the insn that needs it
4544 and perhaps store insns after insns that modify the reloaded pseudo reg.
4546 reg_last_reload_reg and reg_reloaded_contents keep track of
4547 which registers are already available in reload registers.
4548 We update these for the reloads that we perform,
4549 as the insns are scanned. */
4552 reload_as_needed (int live_known)
4554 struct insn_chain *chain;
4555 #if defined (AUTO_INC_DEC)
4560 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4561 memset (spill_reg_store, 0, sizeof spill_reg_store);
4562 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4563 INIT_REG_SET (®_has_output_reload);
4564 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4565 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4567 set_initial_elim_offsets ();
4569 /* Generate a marker insn that we will move around. */
4570 marker = emit_note (NOTE_INSN_DELETED);
4571 unlink_insn_chain (marker, marker);
4573 for (chain = reload_insn_chain; chain; chain = chain->next)
4576 rtx insn = chain->insn;
4577 rtx old_next = NEXT_INSN (insn);
4579 rtx old_prev = PREV_INSN (insn);
4582 /* If we pass a label, copy the offsets from the label information
4583 into the current offsets of each elimination. */
4585 set_offsets_for_label (insn);
4587 else if (INSN_P (insn))
4589 regset_head regs_to_forget;
4590 INIT_REG_SET (®s_to_forget);
4591 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4593 /* If this is a USE and CLOBBER of a MEM, ensure that any
4594 references to eliminable registers have been removed. */
4596 if ((GET_CODE (PATTERN (insn)) == USE
4597 || GET_CODE (PATTERN (insn)) == CLOBBER)
4598 && MEM_P (XEXP (PATTERN (insn), 0)))
4599 XEXP (XEXP (PATTERN (insn), 0), 0)
4600 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4601 GET_MODE (XEXP (PATTERN (insn), 0)),
4604 /* If we need to do register elimination processing, do so.
4605 This might delete the insn, in which case we are done. */
4606 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4608 eliminate_regs_in_insn (insn, 1);
4611 update_eliminable_offsets ();
4612 CLEAR_REG_SET (®s_to_forget);
4617 /* If need_elim is nonzero but need_reload is zero, one might think
4618 that we could simply set n_reloads to 0. However, find_reloads
4619 could have done some manipulation of the insn (such as swapping
4620 commutative operands), and these manipulations are lost during
4621 the first pass for every insn that needs register elimination.
4622 So the actions of find_reloads must be redone here. */
4624 if (! chain->need_elim && ! chain->need_reload
4625 && ! chain->need_operand_change)
4627 /* First find the pseudo regs that must be reloaded for this insn.
4628 This info is returned in the tables reload_... (see reload.h).
4629 Also modify the body of INSN by substituting RELOAD
4630 rtx's for those pseudo regs. */
4633 CLEAR_REG_SET (®_has_output_reload);
4634 CLEAR_HARD_REG_SET (reg_is_output_reload);
4636 find_reloads (insn, 1, spill_indirect_levels, live_known,
4642 rtx next = NEXT_INSN (insn);
4645 /* ??? PREV can get deleted by reload inheritance.
4646 Work around this by emitting a marker note. */
4647 prev = PREV_INSN (insn);
4648 reorder_insns_nobb (marker, marker, prev);
4650 /* Now compute which reload regs to reload them into. Perhaps
4651 reusing reload regs from previous insns, or else output
4652 load insns to reload them. Maybe output store insns too.
4653 Record the choices of reload reg in reload_reg_rtx. */
4654 choose_reload_regs (chain);
4656 /* Generate the insns to reload operands into or out of
4657 their reload regs. */
4658 emit_reload_insns (chain);
4660 /* Substitute the chosen reload regs from reload_reg_rtx
4661 into the insn's body (or perhaps into the bodies of other
4662 load and store insn that we just made for reloading
4663 and that we moved the structure into). */
4664 subst_reloads (insn);
4666 prev = PREV_INSN (marker);
4667 unlink_insn_chain (marker, marker);
4669 /* Adjust the exception region notes for loads and stores. */
4670 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4671 fixup_eh_region_note (insn, prev, next);
4673 /* Adjust the location of REG_ARGS_SIZE. */
4674 p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4677 remove_note (insn, p);
4678 fixup_args_size_notes (prev, PREV_INSN (next),
4679 INTVAL (XEXP (p, 0)));
4682 /* If this was an ASM, make sure that all the reload insns
4683 we have generated are valid. If not, give an error
4685 if (asm_noperands (PATTERN (insn)) >= 0)
4686 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4687 if (p != insn && INSN_P (p)
4688 && GET_CODE (PATTERN (p)) != USE
4689 && (recog_memoized (p) < 0
4690 || (extract_insn (p), ! constrain_operands (1))))
4692 error_for_asm (insn,
4693 "%<asm%> operand requires "
4694 "impossible reload");
4699 if (num_eliminable && chain->need_elim)
4700 update_eliminable_offsets ();
4702 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4703 is no longer validly lying around to save a future reload.
4704 Note that this does not detect pseudos that were reloaded
4705 for this insn in order to be stored in
4706 (obeying register constraints). That is correct; such reload
4707 registers ARE still valid. */
4708 forget_marked_reloads (®s_to_forget);
4709 CLEAR_REG_SET (®s_to_forget);
4711 /* There may have been CLOBBER insns placed after INSN. So scan
4712 between INSN and NEXT and use them to forget old reloads. */
4713 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4714 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4715 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4718 /* Likewise for regs altered by auto-increment in this insn.
4719 REG_INC notes have been changed by reloading:
4720 find_reloads_address_1 records substitutions for them,
4721 which have been performed by subst_reloads above. */
4722 for (i = n_reloads - 1; i >= 0; i--)
4724 rtx in_reg = rld[i].in_reg;
4727 enum rtx_code code = GET_CODE (in_reg);
4728 /* PRE_INC / PRE_DEC will have the reload register ending up
4729 with the same value as the stack slot, but that doesn't
4730 hold true for POST_INC / POST_DEC. Either we have to
4731 convert the memory access to a true POST_INC / POST_DEC,
4732 or we can't use the reload register for inheritance. */
4733 if ((code == POST_INC || code == POST_DEC)
4734 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4735 REGNO (rld[i].reg_rtx))
4736 /* Make sure it is the inc/dec pseudo, and not
4737 some other (e.g. output operand) pseudo. */
4738 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4739 == REGNO (XEXP (in_reg, 0))))
4742 rtx reload_reg = rld[i].reg_rtx;
4743 enum machine_mode mode = GET_MODE (reload_reg);
4747 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4749 /* We really want to ignore REG_INC notes here, so
4750 use PATTERN (p) as argument to reg_set_p . */
4751 if (reg_set_p (reload_reg, PATTERN (p)))
4753 n = count_occurrences (PATTERN (p), reload_reg, 0);
4759 = gen_rtx_fmt_e (code, mode, reload_reg);
4761 validate_replace_rtx_group (reload_reg,
4763 n = verify_changes (0);
4765 /* We must also verify that the constraints
4766 are met after the replacement. Make sure
4767 extract_insn is only called for an insn
4768 where the replacements were found to be
4773 n = constrain_operands (1);
4776 /* If the constraints were not met, then
4777 undo the replacement, else confirm it. */
4781 confirm_change_group ();
4787 add_reg_note (p, REG_INC, reload_reg);
4788 /* Mark this as having an output reload so that the
4789 REG_INC processing code below won't invalidate
4790 the reload for inheritance. */
4791 SET_HARD_REG_BIT (reg_is_output_reload,
4792 REGNO (reload_reg));
4793 SET_REGNO_REG_SET (®_has_output_reload,
4794 REGNO (XEXP (in_reg, 0)));
4797 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4800 else if ((code == PRE_INC || code == PRE_DEC)
4801 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4802 REGNO (rld[i].reg_rtx))
4803 /* Make sure it is the inc/dec pseudo, and not
4804 some other (e.g. output operand) pseudo. */
4805 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4806 == REGNO (XEXP (in_reg, 0))))
4808 SET_HARD_REG_BIT (reg_is_output_reload,
4809 REGNO (rld[i].reg_rtx));
4810 SET_REGNO_REG_SET (®_has_output_reload,
4811 REGNO (XEXP (in_reg, 0)));
4813 else if (code == PRE_INC || code == PRE_DEC
4814 || code == POST_INC || code == POST_DEC)
4816 int in_regno = REGNO (XEXP (in_reg, 0));
4818 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4821 bool forget_p = true;
4823 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4824 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4827 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4830 if (x == reg_reloaded_insn[in_hard_regno])
4836 /* If for some reasons, we didn't set up
4837 reg_last_reload_reg in this insn,
4838 invalidate inheritance from previous
4839 insns for the incremented/decremented
4840 register. Such registers will be not in
4841 reg_has_output_reload. Invalidate it
4842 also if the corresponding element in
4843 reg_reloaded_insn is also
4846 forget_old_reloads_1 (XEXP (in_reg, 0),
4852 /* If a pseudo that got a hard register is auto-incremented,
4853 we must purge records of copying it into pseudos without
4855 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4856 if (REG_NOTE_KIND (x) == REG_INC)
4858 /* See if this pseudo reg was reloaded in this insn.
4859 If so, its last-reload info is still valid
4860 because it is based on this insn's reload. */
4861 for (i = 0; i < n_reloads; i++)
4862 if (rld[i].out == XEXP (x, 0))
4866 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4870 /* A reload reg's contents are unknown after a label. */
4872 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4874 /* Don't assume a reload reg is still good after a call insn
4875 if it is a call-used reg, or if it contains a value that will
4876 be partially clobbered by the call. */
4877 else if (CALL_P (insn))
4879 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4880 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4882 /* If this is a call to a setjmp-type function, we must not
4883 reuse any reload reg contents across the call; that will
4884 just be clobbered by other uses of the register in later
4885 code, before the longjmp. */
4886 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4887 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4892 free (reg_last_reload_reg);
4893 CLEAR_REG_SET (®_has_output_reload);
4896 /* Discard all record of any value reloaded from X,
4897 or reloaded in X from someplace else;
4898 unless X is an output reload reg of the current insn.
4900 X may be a hard reg (the reload reg)
4901 or it may be a pseudo reg that was reloaded from.
4903 When DATA is non-NULL just mark the registers in regset
4904 to be forgotten later. */
4907 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4912 regset regs = (regset) data;
4914 /* note_stores does give us subregs of hard regs,
4915 subreg_regno_offset requires a hard reg. */
4916 while (GET_CODE (x) == SUBREG)
4918 /* We ignore the subreg offset when calculating the regno,
4919 because we are using the entire underlying hard register
4929 if (regno >= FIRST_PSEUDO_REGISTER)
4935 nr = hard_regno_nregs[regno][GET_MODE (x)];
4936 /* Storing into a spilled-reg invalidates its contents.
4937 This can happen if a block-local pseudo is allocated to that reg
4938 and it wasn't spilled because this block's total need is 0.
4939 Then some insn might have an optional reload and use this reg. */
4941 for (i = 0; i < nr; i++)
4942 /* But don't do this if the reg actually serves as an output
4943 reload reg in the current instruction. */
4945 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4947 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4948 spill_reg_store[regno + i] = 0;
4954 SET_REGNO_REG_SET (regs, regno + nr);
4957 /* Since value of X has changed,
4958 forget any value previously copied from it. */
4961 /* But don't forget a copy if this is the output reload
4962 that establishes the copy's validity. */
4964 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4965 reg_last_reload_reg[regno + nr] = 0;
4969 /* Forget the reloads marked in regset by previous function. */
4971 forget_marked_reloads (regset regs)
4974 reg_set_iterator rsi;
4975 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4977 if (reg < FIRST_PSEUDO_REGISTER
4978 /* But don't do this if the reg actually serves as an output
4979 reload reg in the current instruction. */
4981 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4983 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4984 spill_reg_store[reg] = 0;
4987 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4988 reg_last_reload_reg[reg] = 0;
4992 /* The following HARD_REG_SETs indicate when each hard register is
4993 used for a reload of various parts of the current insn. */
4995 /* If reg is unavailable for all reloads. */
4996 static HARD_REG_SET reload_reg_unavailable;
4997 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4998 static HARD_REG_SET reload_reg_used;
4999 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5000 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5001 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5002 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5003 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5004 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5005 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5006 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5007 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5008 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5009 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5010 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5011 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5012 static HARD_REG_SET reload_reg_used_in_op_addr;
5013 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5014 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5015 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5016 static HARD_REG_SET reload_reg_used_in_insn;
5017 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5018 static HARD_REG_SET reload_reg_used_in_other_addr;
5020 /* If reg is in use as a reload reg for any sort of reload. */
5021 static HARD_REG_SET reload_reg_used_at_all;
5023 /* If reg is use as an inherited reload. We just mark the first register
5025 static HARD_REG_SET reload_reg_used_for_inherit;
5027 /* Records which hard regs are used in any way, either as explicit use or
5028 by being allocated to a pseudo during any point of the current insn. */
5029 static HARD_REG_SET reg_used_in_insn;
5031 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5032 TYPE. MODE is used to indicate how many consecutive regs are
5036 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5037 enum machine_mode mode)
5042 add_to_hard_reg_set (&reload_reg_used, mode, regno);
5045 case RELOAD_FOR_INPUT_ADDRESS:
5046 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5049 case RELOAD_FOR_INPADDR_ADDRESS:
5050 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5053 case RELOAD_FOR_OUTPUT_ADDRESS:
5054 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5057 case RELOAD_FOR_OUTADDR_ADDRESS:
5058 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5061 case RELOAD_FOR_OPERAND_ADDRESS:
5062 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5065 case RELOAD_FOR_OPADDR_ADDR:
5066 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5069 case RELOAD_FOR_OTHER_ADDRESS:
5070 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5073 case RELOAD_FOR_INPUT:
5074 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5077 case RELOAD_FOR_OUTPUT:
5078 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5081 case RELOAD_FOR_INSN:
5082 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5086 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5089 /* Similarly, but show REGNO is no longer in use for a reload. */
5092 clear_reload_reg_in_use (unsigned int regno, int opnum,
5093 enum reload_type type, enum machine_mode mode)
5095 unsigned int nregs = hard_regno_nregs[regno][mode];
5096 unsigned int start_regno, end_regno, r;
5098 /* A complication is that for some reload types, inheritance might
5099 allow multiple reloads of the same types to share a reload register.
5100 We set check_opnum if we have to check only reloads with the same
5101 operand number, and check_any if we have to check all reloads. */
5102 int check_opnum = 0;
5104 HARD_REG_SET *used_in_set;
5109 used_in_set = &reload_reg_used;
5112 case RELOAD_FOR_INPUT_ADDRESS:
5113 used_in_set = &reload_reg_used_in_input_addr[opnum];
5116 case RELOAD_FOR_INPADDR_ADDRESS:
5118 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5121 case RELOAD_FOR_OUTPUT_ADDRESS:
5122 used_in_set = &reload_reg_used_in_output_addr[opnum];
5125 case RELOAD_FOR_OUTADDR_ADDRESS:
5127 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5130 case RELOAD_FOR_OPERAND_ADDRESS:
5131 used_in_set = &reload_reg_used_in_op_addr;
5134 case RELOAD_FOR_OPADDR_ADDR:
5136 used_in_set = &reload_reg_used_in_op_addr_reload;
5139 case RELOAD_FOR_OTHER_ADDRESS:
5140 used_in_set = &reload_reg_used_in_other_addr;
5144 case RELOAD_FOR_INPUT:
5145 used_in_set = &reload_reg_used_in_input[opnum];
5148 case RELOAD_FOR_OUTPUT:
5149 used_in_set = &reload_reg_used_in_output[opnum];
5152 case RELOAD_FOR_INSN:
5153 used_in_set = &reload_reg_used_in_insn;
5158 /* We resolve conflicts with remaining reloads of the same type by
5159 excluding the intervals of reload registers by them from the
5160 interval of freed reload registers. Since we only keep track of
5161 one set of interval bounds, we might have to exclude somewhat
5162 more than what would be necessary if we used a HARD_REG_SET here.
5163 But this should only happen very infrequently, so there should
5164 be no reason to worry about it. */
5166 start_regno = regno;
5167 end_regno = regno + nregs;
5168 if (check_opnum || check_any)
5170 for (i = n_reloads - 1; i >= 0; i--)
5172 if (rld[i].when_needed == type
5173 && (check_any || rld[i].opnum == opnum)
5176 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5177 unsigned int conflict_end
5178 = end_hard_regno (rld[i].mode, conflict_start);
5180 /* If there is an overlap with the first to-be-freed register,
5181 adjust the interval start. */
5182 if (conflict_start <= start_regno && conflict_end > start_regno)
5183 start_regno = conflict_end;
5184 /* Otherwise, if there is a conflict with one of the other
5185 to-be-freed registers, adjust the interval end. */
5186 if (conflict_start > start_regno && conflict_start < end_regno)
5187 end_regno = conflict_start;
5192 for (r = start_regno; r < end_regno; r++)
5193 CLEAR_HARD_REG_BIT (*used_in_set, r);
5196 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5197 specified by OPNUM and TYPE. */
5200 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5204 /* In use for a RELOAD_OTHER means it's not available for anything. */
5205 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5206 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5212 /* In use for anything means we can't use it for RELOAD_OTHER. */
5213 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5214 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5215 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5216 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5219 for (i = 0; i < reload_n_operands; i++)
5220 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5221 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5222 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5223 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5224 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5225 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5230 case RELOAD_FOR_INPUT:
5231 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5232 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5235 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5238 /* If it is used for some other input, can't use it. */
5239 for (i = 0; i < reload_n_operands; i++)
5240 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5243 /* If it is used in a later operand's address, can't use it. */
5244 for (i = opnum + 1; i < reload_n_operands; i++)
5245 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5246 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5251 case RELOAD_FOR_INPUT_ADDRESS:
5252 /* Can't use a register if it is used for an input address for this
5253 operand or used as an input in an earlier one. */
5254 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5255 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5258 for (i = 0; i < opnum; i++)
5259 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5264 case RELOAD_FOR_INPADDR_ADDRESS:
5265 /* Can't use a register if it is used for an input address
5266 for this operand or used as an input in an earlier
5268 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5271 for (i = 0; i < opnum; i++)
5272 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5277 case RELOAD_FOR_OUTPUT_ADDRESS:
5278 /* Can't use a register if it is used for an output address for this
5279 operand or used as an output in this or a later operand. Note
5280 that multiple output operands are emitted in reverse order, so
5281 the conflicting ones are those with lower indices. */
5282 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5285 for (i = 0; i <= opnum; i++)
5286 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5291 case RELOAD_FOR_OUTADDR_ADDRESS:
5292 /* Can't use a register if it is used for an output address
5293 for this operand or used as an output in this or a
5294 later operand. Note that multiple output operands are
5295 emitted in reverse order, so the conflicting ones are
5296 those with lower indices. */
5297 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5300 for (i = 0; i <= opnum; i++)
5301 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5306 case RELOAD_FOR_OPERAND_ADDRESS:
5307 for (i = 0; i < reload_n_operands; i++)
5308 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5311 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5312 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5314 case RELOAD_FOR_OPADDR_ADDR:
5315 for (i = 0; i < reload_n_operands; i++)
5316 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5319 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5321 case RELOAD_FOR_OUTPUT:
5322 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5323 outputs, or an operand address for this or an earlier output.
5324 Note that multiple output operands are emitted in reverse order,
5325 so the conflicting ones are those with higher indices. */
5326 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5329 for (i = 0; i < reload_n_operands; i++)
5330 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5333 for (i = opnum; i < reload_n_operands; i++)
5334 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5335 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5340 case RELOAD_FOR_INSN:
5341 for (i = 0; i < reload_n_operands; i++)
5342 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5343 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5346 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5347 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5349 case RELOAD_FOR_OTHER_ADDRESS:
5350 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5357 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5358 the number RELOADNUM, is still available in REGNO at the end of the insn.
5360 We can assume that the reload reg was already tested for availability
5361 at the time it is needed, and we should not check this again,
5362 in case the reg has already been marked in use. */
5365 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5367 int opnum = rld[reloadnum].opnum;
5368 enum reload_type type = rld[reloadnum].when_needed;
5371 /* See if there is a reload with the same type for this operand, using
5372 the same register. This case is not handled by the code below. */
5373 for (i = reloadnum + 1; i < n_reloads; i++)
5378 if (rld[i].opnum != opnum || rld[i].when_needed != type)
5380 reg = rld[i].reg_rtx;
5381 if (reg == NULL_RTX)
5383 nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5384 if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5391 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5392 its value must reach the end. */
5395 /* If this use is for part of the insn,
5396 its value reaches if no subsequent part uses the same register.
5397 Just like the above function, don't try to do this with lots
5400 case RELOAD_FOR_OTHER_ADDRESS:
5401 /* Here we check for everything else, since these don't conflict
5402 with anything else and everything comes later. */
5404 for (i = 0; i < reload_n_operands; i++)
5405 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5406 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5407 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5408 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5409 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5410 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5413 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5414 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5415 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5416 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5418 case RELOAD_FOR_INPUT_ADDRESS:
5419 case RELOAD_FOR_INPADDR_ADDRESS:
5420 /* Similar, except that we check only for this and subsequent inputs
5421 and the address of only subsequent inputs and we do not need
5422 to check for RELOAD_OTHER objects since they are known not to
5425 for (i = opnum; i < reload_n_operands; i++)
5426 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5429 for (i = opnum + 1; i < reload_n_operands; i++)
5430 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5431 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5434 for (i = 0; i < reload_n_operands; i++)
5435 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5436 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5437 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5440 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5443 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5444 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5445 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5447 case RELOAD_FOR_INPUT:
5448 /* Similar to input address, except we start at the next operand for
5449 both input and input address and we do not check for
5450 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5453 for (i = opnum + 1; i < reload_n_operands; i++)
5454 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5455 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5456 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5459 /* ... fall through ... */
5461 case RELOAD_FOR_OPERAND_ADDRESS:
5462 /* Check outputs and their addresses. */
5464 for (i = 0; i < reload_n_operands; i++)
5465 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5466 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5467 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5470 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5472 case RELOAD_FOR_OPADDR_ADDR:
5473 for (i = 0; i < reload_n_operands; i++)
5474 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5475 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5476 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5479 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5480 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5481 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5483 case RELOAD_FOR_INSN:
5484 /* These conflict with other outputs with RELOAD_OTHER. So
5485 we need only check for output addresses. */
5487 opnum = reload_n_operands;
5489 /* ... fall through ... */
5491 case RELOAD_FOR_OUTPUT:
5492 case RELOAD_FOR_OUTPUT_ADDRESS:
5493 case RELOAD_FOR_OUTADDR_ADDRESS:
5494 /* We already know these can't conflict with a later output. So the
5495 only thing to check are later output addresses.
5496 Note that multiple output operands are emitted in reverse order,
5497 so the conflicting ones are those with lower indices. */
5498 for (i = 0; i < opnum; i++)
5499 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5500 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5510 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5511 every register in the range [REGNO, REGNO + NREGS). */
5514 reload_regs_reach_end_p (unsigned int regno, int nregs, int reloadnum)
5518 for (i = 0; i < nregs; i++)
5519 if (!reload_reg_reaches_end_p (regno + i, reloadnum))
5525 /* Returns whether R1 and R2 are uniquely chained: the value of one
5526 is used by the other, and that value is not used by any other
5527 reload for this insn. This is used to partially undo the decision
5528 made in find_reloads when in the case of multiple
5529 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5530 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5531 reloads. This code tries to avoid the conflict created by that
5532 change. It might be cleaner to explicitly keep track of which
5533 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5534 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5535 this after the fact. */
5537 reloads_unique_chain_p (int r1, int r2)
5541 /* We only check input reloads. */
5542 if (! rld[r1].in || ! rld[r2].in)
5545 /* Avoid anything with output reloads. */
5546 if (rld[r1].out || rld[r2].out)
5549 /* "chained" means one reload is a component of the other reload,
5550 not the same as the other reload. */
5551 if (rld[r1].opnum != rld[r2].opnum
5552 || rtx_equal_p (rld[r1].in, rld[r2].in)
5553 || rld[r1].optional || rld[r2].optional
5554 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5555 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5558 for (i = 0; i < n_reloads; i ++)
5559 /* Look for input reloads that aren't our two */
5560 if (i != r1 && i != r2 && rld[i].in)
5562 /* If our reload is mentioned at all, it isn't a simple chain. */
5563 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5569 /* The recursive function change all occurrences of WHAT in *WHERE
5572 substitute (rtx *where, const_rtx what, rtx repl)
5581 if (*where == what || rtx_equal_p (*where, what))
5583 /* Record the location of the changed rtx. */
5584 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5589 code = GET_CODE (*where);
5590 fmt = GET_RTX_FORMAT (code);
5591 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5597 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5598 substitute (&XVECEXP (*where, i, j), what, repl);
5600 else if (fmt[i] == 'e')
5601 substitute (&XEXP (*where, i), what, repl);
5605 /* The function returns TRUE if chain of reload R1 and R2 (in any
5606 order) can be evaluated without usage of intermediate register for
5607 the reload containing another reload. It is important to see
5608 gen_reload to understand what the function is trying to do. As an
5609 example, let us have reload chain
5612 r1: <something> + const
5614 and reload R2 got reload reg HR. The function returns true if
5615 there is a correct insn HR = HR + <something>. Otherwise,
5616 gen_reload will use intermediate register (and this is the reload
5617 reg for R1) to reload <something>.
5619 We need this function to find a conflict for chain reloads. In our
5620 example, if HR = HR + <something> is incorrect insn, then we cannot
5621 use HR as a reload register for R2. If we do use it then we get a
5630 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5632 /* Assume other cases in gen_reload are not possible for
5633 chain reloads or do need an intermediate hard registers. */
5637 rtx last = get_last_insn ();
5639 /* Make r2 a component of r1. */
5640 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5646 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5647 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5648 gcc_assert (regno >= 0);
5649 out = gen_rtx_REG (rld[r1].mode, regno);
5651 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5653 /* If IN is a paradoxical SUBREG, remove it and try to put the
5654 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5655 strip_paradoxical_subreg (&in, &out);
5657 if (GET_CODE (in) == PLUS
5658 && (REG_P (XEXP (in, 0))
5659 || GET_CODE (XEXP (in, 0)) == SUBREG
5660 || MEM_P (XEXP (in, 0)))
5661 && (REG_P (XEXP (in, 1))
5662 || GET_CODE (XEXP (in, 1)) == SUBREG
5663 || CONSTANT_P (XEXP (in, 1))
5664 || MEM_P (XEXP (in, 1))))
5666 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5667 code = recog_memoized (insn);
5672 extract_insn (insn);
5673 /* We want constrain operands to treat this insn strictly in
5674 its validity determination, i.e., the way it would after
5675 reload has completed. */
5676 result = constrain_operands (1);
5679 delete_insns_since (last);
5682 /* Restore the original value at each changed address within R1. */
5683 while (!VEC_empty (rtx_p, substitute_stack))
5685 rtx *where = VEC_pop (rtx_p, substitute_stack);
5686 *where = rld[r2].in;
5692 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5695 This function uses the same algorithm as reload_reg_free_p above. */
5698 reloads_conflict (int r1, int r2)
5700 enum reload_type r1_type = rld[r1].when_needed;
5701 enum reload_type r2_type = rld[r2].when_needed;
5702 int r1_opnum = rld[r1].opnum;
5703 int r2_opnum = rld[r2].opnum;
5705 /* RELOAD_OTHER conflicts with everything. */
5706 if (r2_type == RELOAD_OTHER)
5709 /* Otherwise, check conflicts differently for each type. */
5713 case RELOAD_FOR_INPUT:
5714 return (r2_type == RELOAD_FOR_INSN
5715 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5716 || r2_type == RELOAD_FOR_OPADDR_ADDR
5717 || r2_type == RELOAD_FOR_INPUT
5718 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5719 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5720 && r2_opnum > r1_opnum));
5722 case RELOAD_FOR_INPUT_ADDRESS:
5723 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5724 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5726 case RELOAD_FOR_INPADDR_ADDRESS:
5727 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5728 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5730 case RELOAD_FOR_OUTPUT_ADDRESS:
5731 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5732 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5734 case RELOAD_FOR_OUTADDR_ADDRESS:
5735 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5736 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5738 case RELOAD_FOR_OPERAND_ADDRESS:
5739 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5740 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5741 && (!reloads_unique_chain_p (r1, r2)
5742 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5744 case RELOAD_FOR_OPADDR_ADDR:
5745 return (r2_type == RELOAD_FOR_INPUT
5746 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5748 case RELOAD_FOR_OUTPUT:
5749 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5750 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5751 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5752 && r2_opnum >= r1_opnum));
5754 case RELOAD_FOR_INSN:
5755 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5756 || r2_type == RELOAD_FOR_INSN
5757 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5759 case RELOAD_FOR_OTHER_ADDRESS:
5760 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5770 /* Indexed by reload number, 1 if incoming value
5771 inherited from previous insns. */
5772 static char reload_inherited[MAX_RELOADS];
5774 /* For an inherited reload, this is the insn the reload was inherited from,
5775 if we know it. Otherwise, this is 0. */
5776 static rtx reload_inheritance_insn[MAX_RELOADS];
5778 /* If nonzero, this is a place to get the value of the reload,
5779 rather than using reload_in. */
5780 static rtx reload_override_in[MAX_RELOADS];
5782 /* For each reload, the hard register number of the register used,
5783 or -1 if we did not need a register for this reload. */
5784 static int reload_spill_index[MAX_RELOADS];
5786 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5787 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5789 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5790 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5792 /* Subroutine of free_for_value_p, used to check a single register.
5793 START_REGNO is the starting regno of the full reload register
5794 (possibly comprising multiple hard registers) that we are considering. */
5797 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5798 enum reload_type type, rtx value, rtx out,
5799 int reloadnum, int ignore_address_reloads)
5802 /* Set if we see an input reload that must not share its reload register
5803 with any new earlyclobber, but might otherwise share the reload
5804 register with an output or input-output reload. */
5805 int check_earlyclobber = 0;
5809 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5812 if (out == const0_rtx)
5818 /* We use some pseudo 'time' value to check if the lifetimes of the
5819 new register use would overlap with the one of a previous reload
5820 that is not read-only or uses a different value.
5821 The 'time' used doesn't have to be linear in any shape or form, just
5823 Some reload types use different 'buckets' for each operand.
5824 So there are MAX_RECOG_OPERANDS different time values for each
5826 We compute TIME1 as the time when the register for the prospective
5827 new reload ceases to be live, and TIME2 for each existing
5828 reload as the time when that the reload register of that reload
5830 Where there is little to be gained by exact lifetime calculations,
5831 we just make conservative assumptions, i.e. a longer lifetime;
5832 this is done in the 'default:' cases. */
5835 case RELOAD_FOR_OTHER_ADDRESS:
5836 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5837 time1 = copy ? 0 : 1;
5840 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5842 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5843 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5844 respectively, to the time values for these, we get distinct time
5845 values. To get distinct time values for each operand, we have to
5846 multiply opnum by at least three. We round that up to four because
5847 multiply by four is often cheaper. */
5848 case RELOAD_FOR_INPADDR_ADDRESS:
5849 time1 = opnum * 4 + 2;
5851 case RELOAD_FOR_INPUT_ADDRESS:
5852 time1 = opnum * 4 + 3;
5854 case RELOAD_FOR_INPUT:
5855 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5856 executes (inclusive). */
5857 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5859 case RELOAD_FOR_OPADDR_ADDR:
5861 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5862 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5864 case RELOAD_FOR_OPERAND_ADDRESS:
5865 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5867 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5869 case RELOAD_FOR_OUTADDR_ADDRESS:
5870 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5872 case RELOAD_FOR_OUTPUT_ADDRESS:
5873 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5876 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5879 for (i = 0; i < n_reloads; i++)
5881 rtx reg = rld[i].reg_rtx;
5882 if (reg && REG_P (reg)
5883 && ((unsigned) regno - true_regnum (reg)
5884 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5887 rtx other_input = rld[i].in;
5889 /* If the other reload loads the same input value, that
5890 will not cause a conflict only if it's loading it into
5891 the same register. */
5892 if (true_regnum (reg) != start_regno)
5893 other_input = NULL_RTX;
5894 if (! other_input || ! rtx_equal_p (other_input, value)
5895 || rld[i].out || out)
5898 switch (rld[i].when_needed)
5900 case RELOAD_FOR_OTHER_ADDRESS:
5903 case RELOAD_FOR_INPADDR_ADDRESS:
5904 /* find_reloads makes sure that a
5905 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5906 by at most one - the first -
5907 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5908 address reload is inherited, the address address reload
5909 goes away, so we can ignore this conflict. */
5910 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5911 && ignore_address_reloads
5912 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5913 Then the address address is still needed to store
5914 back the new address. */
5915 && ! rld[reloadnum].out)
5917 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5918 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5920 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5921 && ignore_address_reloads
5922 /* Unless we are reloading an auto_inc expression. */
5923 && ! rld[reloadnum].out)
5925 time2 = rld[i].opnum * 4 + 2;
5927 case RELOAD_FOR_INPUT_ADDRESS:
5928 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5929 && ignore_address_reloads
5930 && ! rld[reloadnum].out)
5932 time2 = rld[i].opnum * 4 + 3;
5934 case RELOAD_FOR_INPUT:
5935 time2 = rld[i].opnum * 4 + 4;
5936 check_earlyclobber = 1;
5938 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5939 == MAX_RECOG_OPERAND * 4 */
5940 case RELOAD_FOR_OPADDR_ADDR:
5941 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5942 && ignore_address_reloads
5943 && ! rld[reloadnum].out)
5945 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5947 case RELOAD_FOR_OPERAND_ADDRESS:
5948 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5949 check_earlyclobber = 1;
5951 case RELOAD_FOR_INSN:
5952 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5954 case RELOAD_FOR_OUTPUT:
5955 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5956 instruction is executed. */
5957 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5959 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5960 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5962 case RELOAD_FOR_OUTADDR_ADDRESS:
5963 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5964 && ignore_address_reloads
5965 && ! rld[reloadnum].out)
5967 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5969 case RELOAD_FOR_OUTPUT_ADDRESS:
5970 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5973 /* If there is no conflict in the input part, handle this
5974 like an output reload. */
5975 if (! rld[i].in || rtx_equal_p (other_input, value))
5977 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5978 /* Earlyclobbered outputs must conflict with inputs. */
5979 if (earlyclobber_operand_p (rld[i].out))
5980 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5985 /* RELOAD_OTHER might be live beyond instruction execution,
5986 but this is not obvious when we set time2 = 1. So check
5987 here if there might be a problem with the new reload
5988 clobbering the register used by the RELOAD_OTHER. */
5996 && (! rld[i].in || rld[i].out
5997 || ! rtx_equal_p (other_input, value)))
5998 || (out && rld[reloadnum].out_reg
5999 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
6005 /* Earlyclobbered outputs must conflict with inputs. */
6006 if (check_earlyclobber && out && earlyclobber_operand_p (out))
6012 /* Return 1 if the value in reload reg REGNO, as used by a reload
6013 needed for the part of the insn specified by OPNUM and TYPE,
6014 may be used to load VALUE into it.
6016 MODE is the mode in which the register is used, this is needed to
6017 determine how many hard regs to test.
6019 Other read-only reloads with the same value do not conflict
6020 unless OUT is nonzero and these other reloads have to live while
6021 output reloads live.
6022 If OUT is CONST0_RTX, this is a special case: it means that the
6023 test should not be for using register REGNO as reload register, but
6024 for copying from register REGNO into the reload register.
6026 RELOADNUM is the number of the reload we want to load this value for;
6027 a reload does not conflict with itself.
6029 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6030 reloads that load an address for the very reload we are considering.
6032 The caller has to make sure that there is no conflict with the return
6036 free_for_value_p (int regno, enum machine_mode mode, int opnum,
6037 enum reload_type type, rtx value, rtx out, int reloadnum,
6038 int ignore_address_reloads)
6040 int nregs = hard_regno_nregs[regno][mode];
6042 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6043 value, out, reloadnum,
6044 ignore_address_reloads))
6049 /* Return nonzero if the rtx X is invariant over the current function. */
6050 /* ??? Actually, the places where we use this expect exactly what is
6051 tested here, and not everything that is function invariant. In
6052 particular, the frame pointer and arg pointer are special cased;
6053 pic_offset_table_rtx is not, and we must not spill these things to
6057 function_invariant_p (const_rtx x)
6061 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6063 if (GET_CODE (x) == PLUS
6064 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6065 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6070 /* Determine whether the reload reg X overlaps any rtx'es used for
6071 overriding inheritance. Return nonzero if so. */
6074 conflicts_with_override (rtx x)
6077 for (i = 0; i < n_reloads; i++)
6078 if (reload_override_in[i]
6079 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6084 /* Give an error message saying we failed to find a reload for INSN,
6085 and clear out reload R. */
6087 failed_reload (rtx insn, int r)
6089 if (asm_noperands (PATTERN (insn)) < 0)
6090 /* It's the compiler's fault. */
6091 fatal_insn ("could not find a spill register", insn);
6093 /* It's the user's fault; the operand's mode and constraint
6094 don't match. Disable this reload so we don't crash in final. */
6095 error_for_asm (insn,
6096 "%<asm%> operand constraint incompatible with operand size");
6100 rld[r].optional = 1;
6101 rld[r].secondary_p = 1;
6104 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6105 for reload R. If it's valid, get an rtx for it. Return nonzero if
6108 set_reload_reg (int i, int r)
6110 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6112 int regno ATTRIBUTE_UNUSED;
6113 rtx reg = spill_reg_rtx[i];
6115 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6116 spill_reg_rtx[i] = reg
6117 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6119 regno = true_regnum (reg);
6121 /* Detect when the reload reg can't hold the reload mode.
6122 This used to be one `if', but Sequent compiler can't handle that. */
6123 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6125 enum machine_mode test_mode = VOIDmode;
6127 test_mode = GET_MODE (rld[r].in);
6128 /* If rld[r].in has VOIDmode, it means we will load it
6129 in whatever mode the reload reg has: to wit, rld[r].mode.
6130 We have already tested that for validity. */
6131 /* Aside from that, we need to test that the expressions
6132 to reload from or into have modes which are valid for this
6133 reload register. Otherwise the reload insns would be invalid. */
6134 if (! (rld[r].in != 0 && test_mode != VOIDmode
6135 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6136 if (! (rld[r].out != 0
6137 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6139 /* The reg is OK. */
6142 /* Mark as in use for this insn the reload regs we use
6144 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6145 rld[r].when_needed, rld[r].mode);
6147 rld[r].reg_rtx = reg;
6148 reload_spill_index[r] = spill_regs[i];
6155 /* Find a spill register to use as a reload register for reload R.
6156 LAST_RELOAD is nonzero if this is the last reload for the insn being
6159 Set rld[R].reg_rtx to the register allocated.
6161 We return 1 if successful, or 0 if we couldn't find a spill reg and
6162 we didn't change anything. */
6165 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6170 /* If we put this reload ahead, thinking it is a group,
6171 then insist on finding a group. Otherwise we can grab a
6172 reg that some other reload needs.
6173 (That can happen when we have a 68000 DATA_OR_FP_REG
6174 which is a group of data regs or one fp reg.)
6175 We need not be so restrictive if there are no more reloads
6178 ??? Really it would be nicer to have smarter handling
6179 for that kind of reg class, where a problem like this is normal.
6180 Perhaps those classes should be avoided for reloading
6181 by use of more alternatives. */
6183 int force_group = rld[r].nregs > 1 && ! last_reload;
6185 /* If we want a single register and haven't yet found one,
6186 take any reg in the right class and not in use.
6187 If we want a consecutive group, here is where we look for it.
6189 We use three passes so we can first look for reload regs to
6190 reuse, which are already in use for other reloads in this insn,
6191 and only then use additional registers which are not "bad", then
6192 finally any register.
6194 I think that maximizing reuse is needed to make sure we don't
6195 run out of reload regs. Suppose we have three reloads, and
6196 reloads A and B can share regs. These need two regs.
6197 Suppose A and B are given different regs.
6198 That leaves none for C. */
6199 for (pass = 0; pass < 3; pass++)
6201 /* I is the index in spill_regs.
6202 We advance it round-robin between insns to use all spill regs
6203 equally, so that inherited reloads have a chance
6204 of leapfrogging each other. */
6208 for (count = 0; count < n_spills; count++)
6210 int rclass = (int) rld[r].rclass;
6216 regnum = spill_regs[i];
6218 if ((reload_reg_free_p (regnum, rld[r].opnum,
6221 /* We check reload_reg_used to make sure we
6222 don't clobber the return register. */
6223 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6224 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6225 rld[r].when_needed, rld[r].in,
6227 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6228 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6229 /* Look first for regs to share, then for unshared. But
6230 don't share regs used for inherited reloads; they are
6231 the ones we want to preserve. */
6233 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6235 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6238 int nr = hard_regno_nregs[regnum][rld[r].mode];
6240 /* During the second pass we want to avoid reload registers
6241 which are "bad" for this reload. */
6243 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6246 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6247 (on 68000) got us two FP regs. If NR is 1,
6248 we would reject both of them. */
6251 /* If we need only one reg, we have already won. */
6254 /* But reject a single reg if we demand a group. */
6259 /* Otherwise check that as many consecutive regs as we need
6260 are available here. */
6263 int regno = regnum + nr - 1;
6264 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6265 && spill_reg_order[regno] >= 0
6266 && reload_reg_free_p (regno, rld[r].opnum,
6267 rld[r].when_needed)))
6276 /* If we found something on the current pass, omit later passes. */
6277 if (count < n_spills)
6281 /* We should have found a spill register by now. */
6282 if (count >= n_spills)
6285 /* I is the index in SPILL_REG_RTX of the reload register we are to
6286 allocate. Get an rtx for it and find its register number. */
6288 return set_reload_reg (i, r);
6291 /* Initialize all the tables needed to allocate reload registers.
6292 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6293 is the array we use to restore the reg_rtx field for every reload. */
6296 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6300 for (i = 0; i < n_reloads; i++)
6301 rld[i].reg_rtx = save_reload_reg_rtx[i];
6303 memset (reload_inherited, 0, MAX_RELOADS);
6304 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6305 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6307 CLEAR_HARD_REG_SET (reload_reg_used);
6308 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6309 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6310 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6311 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6312 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6314 CLEAR_HARD_REG_SET (reg_used_in_insn);
6317 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6318 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6319 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6320 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6321 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6322 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6325 for (i = 0; i < reload_n_operands; i++)
6327 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6328 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6329 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6330 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6331 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6332 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6335 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6337 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6339 for (i = 0; i < n_reloads; i++)
6340 /* If we have already decided to use a certain register,
6341 don't use it in another way. */
6343 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6344 rld[i].when_needed, rld[i].mode);
6347 /* Assign hard reg targets for the pseudo-registers we must reload
6348 into hard regs for this insn.
6349 Also output the instructions to copy them in and out of the hard regs.
6351 For machines with register classes, we are responsible for
6352 finding a reload reg in the proper class. */
6355 choose_reload_regs (struct insn_chain *chain)
6357 rtx insn = chain->insn;
6359 unsigned int max_group_size = 1;
6360 enum reg_class group_class = NO_REGS;
6361 int pass, win, inheritance;
6363 rtx save_reload_reg_rtx[MAX_RELOADS];
6365 /* In order to be certain of getting the registers we need,
6366 we must sort the reloads into order of increasing register class.
6367 Then our grabbing of reload registers will parallel the process
6368 that provided the reload registers.
6370 Also note whether any of the reloads wants a consecutive group of regs.
6371 If so, record the maximum size of the group desired and what
6372 register class contains all the groups needed by this insn. */
6374 for (j = 0; j < n_reloads; j++)
6376 reload_order[j] = j;
6377 if (rld[j].reg_rtx != NULL_RTX)
6379 gcc_assert (REG_P (rld[j].reg_rtx)
6380 && HARD_REGISTER_P (rld[j].reg_rtx));
6381 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6384 reload_spill_index[j] = -1;
6386 if (rld[j].nregs > 1)
6388 max_group_size = MAX (rld[j].nregs, max_group_size);
6390 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6393 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6397 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6399 /* If -O, try first with inheritance, then turning it off.
6400 If not -O, don't do inheritance.
6401 Using inheritance when not optimizing leads to paradoxes
6402 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6403 because one side of the comparison might be inherited. */
6405 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6407 choose_reload_regs_init (chain, save_reload_reg_rtx);
6409 /* Process the reloads in order of preference just found.
6410 Beyond this point, subregs can be found in reload_reg_rtx.
6412 This used to look for an existing reloaded home for all of the
6413 reloads, and only then perform any new reloads. But that could lose
6414 if the reloads were done out of reg-class order because a later
6415 reload with a looser constraint might have an old home in a register
6416 needed by an earlier reload with a tighter constraint.
6418 To solve this, we make two passes over the reloads, in the order
6419 described above. In the first pass we try to inherit a reload
6420 from a previous insn. If there is a later reload that needs a
6421 class that is a proper subset of the class being processed, we must
6422 also allocate a spill register during the first pass.
6424 Then make a second pass over the reloads to allocate any reloads
6425 that haven't been given registers yet. */
6427 for (j = 0; j < n_reloads; j++)
6429 int r = reload_order[j];
6430 rtx search_equiv = NULL_RTX;
6432 /* Ignore reloads that got marked inoperative. */
6433 if (rld[r].out == 0 && rld[r].in == 0
6434 && ! rld[r].secondary_p)
6437 /* If find_reloads chose to use reload_in or reload_out as a reload
6438 register, we don't need to chose one. Otherwise, try even if it
6439 found one since we might save an insn if we find the value lying
6441 Try also when reload_in is a pseudo without a hard reg. */
6442 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6443 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6444 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6445 && !MEM_P (rld[r].in)
6446 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6449 #if 0 /* No longer needed for correct operation.
6450 It might give better code, or might not; worth an experiment? */
6451 /* If this is an optional reload, we can't inherit from earlier insns
6452 until we are sure that any non-optional reloads have been allocated.
6453 The following code takes advantage of the fact that optional reloads
6454 are at the end of reload_order. */
6455 if (rld[r].optional != 0)
6456 for (i = 0; i < j; i++)
6457 if ((rld[reload_order[i]].out != 0
6458 || rld[reload_order[i]].in != 0
6459 || rld[reload_order[i]].secondary_p)
6460 && ! rld[reload_order[i]].optional
6461 && rld[reload_order[i]].reg_rtx == 0)
6462 allocate_reload_reg (chain, reload_order[i], 0);
6465 /* First see if this pseudo is already available as reloaded
6466 for a previous insn. We cannot try to inherit for reloads
6467 that are smaller than the maximum number of registers needed
6468 for groups unless the register we would allocate cannot be used
6471 We could check here to see if this is a secondary reload for
6472 an object that is already in a register of the desired class.
6473 This would avoid the need for the secondary reload register.
6474 But this is complex because we can't easily determine what
6475 objects might want to be loaded via this reload. So let a
6476 register be allocated here. In `emit_reload_insns' we suppress
6477 one of the loads in the case described above. */
6483 enum machine_mode mode = VOIDmode;
6487 else if (REG_P (rld[r].in))
6489 regno = REGNO (rld[r].in);
6490 mode = GET_MODE (rld[r].in);
6492 else if (REG_P (rld[r].in_reg))
6494 regno = REGNO (rld[r].in_reg);
6495 mode = GET_MODE (rld[r].in_reg);
6497 else if (GET_CODE (rld[r].in_reg) == SUBREG
6498 && REG_P (SUBREG_REG (rld[r].in_reg)))
6500 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6501 if (regno < FIRST_PSEUDO_REGISTER)
6502 regno = subreg_regno (rld[r].in_reg);
6504 byte = SUBREG_BYTE (rld[r].in_reg);
6505 mode = GET_MODE (rld[r].in_reg);
6508 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6509 && REG_P (XEXP (rld[r].in_reg, 0)))
6511 regno = REGNO (XEXP (rld[r].in_reg, 0));
6512 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6513 rld[r].out = rld[r].in;
6517 /* This won't work, since REGNO can be a pseudo reg number.
6518 Also, it takes much more hair to keep track of all the things
6519 that can invalidate an inherited reload of part of a pseudoreg. */
6520 else if (GET_CODE (rld[r].in) == SUBREG
6521 && REG_P (SUBREG_REG (rld[r].in)))
6522 regno = subreg_regno (rld[r].in);
6526 && reg_last_reload_reg[regno] != 0
6527 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6528 >= GET_MODE_SIZE (mode) + byte)
6529 #ifdef CANNOT_CHANGE_MODE_CLASS
6530 /* Verify that the register it's in can be used in
6532 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6533 GET_MODE (reg_last_reload_reg[regno]),
6538 enum reg_class rclass = rld[r].rclass, last_class;
6539 rtx last_reg = reg_last_reload_reg[regno];
6541 i = REGNO (last_reg);
6542 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6543 last_class = REGNO_REG_CLASS (i);
6545 if (reg_reloaded_contents[i] == regno
6546 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6547 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6548 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6549 /* Even if we can't use this register as a reload
6550 register, we might use it for reload_override_in,
6551 if copying it to the desired class is cheap
6553 || ((register_move_cost (mode, last_class, rclass)
6554 < memory_move_cost (mode, rclass, true))
6555 && (secondary_reload_class (1, rclass, mode,
6558 #ifdef SECONDARY_MEMORY_NEEDED
6559 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6564 && (rld[r].nregs == max_group_size
6565 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6567 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6568 rld[r].when_needed, rld[r].in,
6571 /* If a group is needed, verify that all the subsequent
6572 registers still have their values intact. */
6573 int nr = hard_regno_nregs[i][rld[r].mode];
6576 for (k = 1; k < nr; k++)
6577 if (reg_reloaded_contents[i + k] != regno
6578 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6586 last_reg = (GET_MODE (last_reg) == mode
6587 ? last_reg : gen_rtx_REG (mode, i));
6590 for (k = 0; k < nr; k++)
6591 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6594 /* We found a register that contains the
6595 value we need. If this register is the
6596 same as an `earlyclobber' operand of the
6597 current insn, just mark it as a place to
6598 reload from since we can't use it as the
6599 reload register itself. */
6601 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6602 if (reg_overlap_mentioned_for_reload_p
6603 (reg_last_reload_reg[regno],
6604 reload_earlyclobbers[i1]))
6607 if (i1 != n_earlyclobbers
6608 || ! (free_for_value_p (i, rld[r].mode,
6610 rld[r].when_needed, rld[r].in,
6612 /* Don't use it if we'd clobber a pseudo reg. */
6613 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6615 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6616 /* Don't clobber the frame pointer. */
6617 || (i == HARD_FRAME_POINTER_REGNUM
6618 && frame_pointer_needed
6620 /* Don't really use the inherited spill reg
6621 if we need it wider than we've got it. */
6622 || (GET_MODE_SIZE (rld[r].mode)
6623 > GET_MODE_SIZE (mode))
6626 /* If find_reloads chose reload_out as reload
6627 register, stay with it - that leaves the
6628 inherited register for subsequent reloads. */
6629 || (rld[r].out && rld[r].reg_rtx
6630 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6632 if (! rld[r].optional)
6634 reload_override_in[r] = last_reg;
6635 reload_inheritance_insn[r]
6636 = reg_reloaded_insn[i];
6642 /* We can use this as a reload reg. */
6643 /* Mark the register as in use for this part of
6645 mark_reload_reg_in_use (i,
6649 rld[r].reg_rtx = last_reg;
6650 reload_inherited[r] = 1;
6651 reload_inheritance_insn[r]
6652 = reg_reloaded_insn[i];
6653 reload_spill_index[r] = i;
6654 for (k = 0; k < nr; k++)
6655 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6663 /* Here's another way to see if the value is already lying around. */
6666 && ! reload_inherited[r]
6668 && (CONSTANT_P (rld[r].in)
6669 || GET_CODE (rld[r].in) == PLUS
6670 || REG_P (rld[r].in)
6671 || MEM_P (rld[r].in))
6672 && (rld[r].nregs == max_group_size
6673 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6674 search_equiv = rld[r].in;
6679 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6680 -1, NULL, 0, rld[r].mode);
6686 regno = REGNO (equiv);
6689 /* This must be a SUBREG of a hard register.
6690 Make a new REG since this might be used in an
6691 address and not all machines support SUBREGs
6693 gcc_assert (GET_CODE (equiv) == SUBREG);
6694 regno = subreg_regno (equiv);
6695 equiv = gen_rtx_REG (rld[r].mode, regno);
6696 /* If we choose EQUIV as the reload register, but the
6697 loop below decides to cancel the inheritance, we'll
6698 end up reloading EQUIV in rld[r].mode, not the mode
6699 it had originally. That isn't safe when EQUIV isn't
6700 available as a spill register since its value might
6701 still be live at this point. */
6702 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6703 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6708 /* If we found a spill reg, reject it unless it is free
6709 and of the desired class. */
6713 int bad_for_class = 0;
6714 int max_regno = regno + rld[r].nregs;
6716 for (i = regno; i < max_regno; i++)
6718 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6720 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6725 && ! free_for_value_p (regno, rld[r].mode,
6726 rld[r].opnum, rld[r].when_needed,
6727 rld[r].in, rld[r].out, r, 1))
6732 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6735 /* We found a register that contains the value we need.
6736 If this register is the same as an `earlyclobber' operand
6737 of the current insn, just mark it as a place to reload from
6738 since we can't use it as the reload register itself. */
6741 for (i = 0; i < n_earlyclobbers; i++)
6742 if (reg_overlap_mentioned_for_reload_p (equiv,
6743 reload_earlyclobbers[i]))
6745 if (! rld[r].optional)
6746 reload_override_in[r] = equiv;
6751 /* If the equiv register we have found is explicitly clobbered
6752 in the current insn, it depends on the reload type if we
6753 can use it, use it for reload_override_in, or not at all.
6754 In particular, we then can't use EQUIV for a
6755 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6759 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6760 switch (rld[r].when_needed)
6762 case RELOAD_FOR_OTHER_ADDRESS:
6763 case RELOAD_FOR_INPADDR_ADDRESS:
6764 case RELOAD_FOR_INPUT_ADDRESS:
6765 case RELOAD_FOR_OPADDR_ADDR:
6768 case RELOAD_FOR_INPUT:
6769 case RELOAD_FOR_OPERAND_ADDRESS:
6770 if (! rld[r].optional)
6771 reload_override_in[r] = equiv;
6777 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6778 switch (rld[r].when_needed)
6780 case RELOAD_FOR_OTHER_ADDRESS:
6781 case RELOAD_FOR_INPADDR_ADDRESS:
6782 case RELOAD_FOR_INPUT_ADDRESS:
6783 case RELOAD_FOR_OPADDR_ADDR:
6784 case RELOAD_FOR_OPERAND_ADDRESS:
6785 case RELOAD_FOR_INPUT:
6788 if (! rld[r].optional)
6789 reload_override_in[r] = equiv;
6797 /* If we found an equivalent reg, say no code need be generated
6798 to load it, and use it as our reload reg. */
6800 && (regno != HARD_FRAME_POINTER_REGNUM
6801 || !frame_pointer_needed))
6803 int nr = hard_regno_nregs[regno][rld[r].mode];
6805 rld[r].reg_rtx = equiv;
6806 reload_spill_index[r] = regno;
6807 reload_inherited[r] = 1;
6809 /* If reg_reloaded_valid is not set for this register,
6810 there might be a stale spill_reg_store lying around.
6811 We must clear it, since otherwise emit_reload_insns
6812 might delete the store. */
6813 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6814 spill_reg_store[regno] = NULL_RTX;
6815 /* If any of the hard registers in EQUIV are spill
6816 registers, mark them as in use for this insn. */
6817 for (k = 0; k < nr; k++)
6819 i = spill_reg_order[regno + k];
6822 mark_reload_reg_in_use (regno, rld[r].opnum,
6825 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6832 /* If we found a register to use already, or if this is an optional
6833 reload, we are done. */
6834 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6838 /* No longer needed for correct operation. Might or might
6839 not give better code on the average. Want to experiment? */
6841 /* See if there is a later reload that has a class different from our
6842 class that intersects our class or that requires less register
6843 than our reload. If so, we must allocate a register to this
6844 reload now, since that reload might inherit a previous reload
6845 and take the only available register in our class. Don't do this
6846 for optional reloads since they will force all previous reloads
6847 to be allocated. Also don't do this for reloads that have been
6850 for (i = j + 1; i < n_reloads; i++)
6852 int s = reload_order[i];
6854 if ((rld[s].in == 0 && rld[s].out == 0
6855 && ! rld[s].secondary_p)
6859 if ((rld[s].rclass != rld[r].rclass
6860 && reg_classes_intersect_p (rld[r].rclass,
6862 || rld[s].nregs < rld[r].nregs)
6869 allocate_reload_reg (chain, r, j == n_reloads - 1);
6873 /* Now allocate reload registers for anything non-optional that
6874 didn't get one yet. */
6875 for (j = 0; j < n_reloads; j++)
6877 int r = reload_order[j];
6879 /* Ignore reloads that got marked inoperative. */
6880 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6883 /* Skip reloads that already have a register allocated or are
6885 if (rld[r].reg_rtx != 0 || rld[r].optional)
6888 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6892 /* If that loop got all the way, we have won. */
6899 /* Loop around and try without any inheritance. */
6904 /* First undo everything done by the failed attempt
6905 to allocate with inheritance. */
6906 choose_reload_regs_init (chain, save_reload_reg_rtx);
6908 /* Some sanity tests to verify that the reloads found in the first
6909 pass are identical to the ones we have now. */
6910 gcc_assert (chain->n_reloads == n_reloads);
6912 for (i = 0; i < n_reloads; i++)
6914 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6916 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6917 for (j = 0; j < n_spills; j++)
6918 if (spill_regs[j] == chain->rld[i].regno)
6919 if (! set_reload_reg (j, i))
6920 failed_reload (chain->insn, i);
6924 /* If we thought we could inherit a reload, because it seemed that
6925 nothing else wanted the same reload register earlier in the insn,
6926 verify that assumption, now that all reloads have been assigned.
6927 Likewise for reloads where reload_override_in has been set. */
6929 /* If doing expensive optimizations, do one preliminary pass that doesn't
6930 cancel any inheritance, but removes reloads that have been needed only
6931 for reloads that we know can be inherited. */
6932 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6934 for (j = 0; j < n_reloads; j++)
6936 int r = reload_order[j];
6938 if (reload_inherited[r] && rld[r].reg_rtx)
6939 check_reg = rld[r].reg_rtx;
6940 else if (reload_override_in[r]
6941 && (REG_P (reload_override_in[r])
6942 || GET_CODE (reload_override_in[r]) == SUBREG))
6943 check_reg = reload_override_in[r];
6946 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6947 rld[r].opnum, rld[r].when_needed, rld[r].in,
6948 (reload_inherited[r]
6949 ? rld[r].out : const0_rtx),
6954 reload_inherited[r] = 0;
6955 reload_override_in[r] = 0;
6957 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6958 reload_override_in, then we do not need its related
6959 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6960 likewise for other reload types.
6961 We handle this by removing a reload when its only replacement
6962 is mentioned in reload_in of the reload we are going to inherit.
6963 A special case are auto_inc expressions; even if the input is
6964 inherited, we still need the address for the output. We can
6965 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6966 If we succeeded removing some reload and we are doing a preliminary
6967 pass just to remove such reloads, make another pass, since the
6968 removal of one reload might allow us to inherit another one. */
6970 && rld[r].out != rld[r].in
6971 && remove_address_replacements (rld[r].in) && pass)
6976 /* Now that reload_override_in is known valid,
6977 actually override reload_in. */
6978 for (j = 0; j < n_reloads; j++)
6979 if (reload_override_in[j])
6980 rld[j].in = reload_override_in[j];
6982 /* If this reload won't be done because it has been canceled or is
6983 optional and not inherited, clear reload_reg_rtx so other
6984 routines (such as subst_reloads) don't get confused. */
6985 for (j = 0; j < n_reloads; j++)
6986 if (rld[j].reg_rtx != 0
6987 && ((rld[j].optional && ! reload_inherited[j])
6988 || (rld[j].in == 0 && rld[j].out == 0
6989 && ! rld[j].secondary_p)))
6991 int regno = true_regnum (rld[j].reg_rtx);
6993 if (spill_reg_order[regno] >= 0)
6994 clear_reload_reg_in_use (regno, rld[j].opnum,
6995 rld[j].when_needed, rld[j].mode);
6997 reload_spill_index[j] = -1;
7000 /* Record which pseudos and which spill regs have output reloads. */
7001 for (j = 0; j < n_reloads; j++)
7003 int r = reload_order[j];
7005 i = reload_spill_index[r];
7007 /* I is nonneg if this reload uses a register.
7008 If rld[r].reg_rtx is 0, this is an optional reload
7009 that we opted to ignore. */
7010 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7011 && rld[r].reg_rtx != 0)
7013 int nregno = REGNO (rld[r].out_reg);
7016 if (nregno < FIRST_PSEUDO_REGISTER)
7017 nr = hard_regno_nregs[nregno][rld[r].mode];
7020 SET_REGNO_REG_SET (®_has_output_reload,
7024 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
7026 gcc_assert (rld[r].when_needed == RELOAD_OTHER
7027 || rld[r].when_needed == RELOAD_FOR_OUTPUT
7028 || rld[r].when_needed == RELOAD_FOR_INSN);
7033 /* Deallocate the reload register for reload R. This is called from
7034 remove_address_replacements. */
7037 deallocate_reload_reg (int r)
7041 if (! rld[r].reg_rtx)
7043 regno = true_regnum (rld[r].reg_rtx);
7045 if (spill_reg_order[regno] >= 0)
7046 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7048 reload_spill_index[r] = -1;
7051 /* These arrays are filled by emit_reload_insns and its subroutines. */
7052 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
7053 static rtx other_input_address_reload_insns = 0;
7054 static rtx other_input_reload_insns = 0;
7055 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
7056 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7057 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7058 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7059 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7060 static rtx operand_reload_insns = 0;
7061 static rtx other_operand_reload_insns = 0;
7062 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7064 /* Values to be put in spill_reg_store are put here first. */
7065 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7066 static HARD_REG_SET reg_reloaded_died;
7068 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7069 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7070 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7071 adjusted register, and return true. Otherwise, return false. */
7073 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7074 enum reg_class new_class,
7075 enum machine_mode new_mode)
7080 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7082 unsigned regno = REGNO (reg);
7084 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7086 if (GET_MODE (reg) != new_mode)
7088 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7090 if (hard_regno_nregs[regno][new_mode]
7091 > hard_regno_nregs[regno][GET_MODE (reg)])
7093 reg = reload_adjust_reg_for_mode (reg, new_mode);
7101 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7102 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7103 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7104 adjusted register, and return true. Otherwise, return false. */
7106 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7107 enum insn_code icode)
7110 enum reg_class new_class = scratch_reload_class (icode);
7111 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7113 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7114 new_class, new_mode);
7117 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7118 has the number J. OLD contains the value to be used as input. */
7121 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7124 rtx insn = chain->insn;
7126 rtx oldequiv_reg = 0;
7129 enum machine_mode mode;
7132 /* delete_output_reload is only invoked properly if old contains
7133 the original pseudo register. Since this is replaced with a
7134 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7135 find the pseudo in RELOAD_IN_REG. */
7136 if (reload_override_in[j]
7137 && REG_P (rl->in_reg))
7144 else if (REG_P (oldequiv))
7145 oldequiv_reg = oldequiv;
7146 else if (GET_CODE (oldequiv) == SUBREG)
7147 oldequiv_reg = SUBREG_REG (oldequiv);
7149 reloadreg = reload_reg_rtx_for_input[j];
7150 mode = GET_MODE (reloadreg);
7152 /* If we are reloading from a register that was recently stored in
7153 with an output-reload, see if we can prove there was
7154 actually no need to store the old value in it. */
7156 if (optimize && REG_P (oldequiv)
7157 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7158 && spill_reg_store[REGNO (oldequiv)]
7160 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7161 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7163 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7165 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7168 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7169 oldequiv = SUBREG_REG (oldequiv);
7170 if (GET_MODE (oldequiv) != VOIDmode
7171 && mode != GET_MODE (oldequiv))
7172 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7174 /* Switch to the right place to emit the reload insns. */
7175 switch (rl->when_needed)
7178 where = &other_input_reload_insns;
7180 case RELOAD_FOR_INPUT:
7181 where = &input_reload_insns[rl->opnum];
7183 case RELOAD_FOR_INPUT_ADDRESS:
7184 where = &input_address_reload_insns[rl->opnum];
7186 case RELOAD_FOR_INPADDR_ADDRESS:
7187 where = &inpaddr_address_reload_insns[rl->opnum];
7189 case RELOAD_FOR_OUTPUT_ADDRESS:
7190 where = &output_address_reload_insns[rl->opnum];
7192 case RELOAD_FOR_OUTADDR_ADDRESS:
7193 where = &outaddr_address_reload_insns[rl->opnum];
7195 case RELOAD_FOR_OPERAND_ADDRESS:
7196 where = &operand_reload_insns;
7198 case RELOAD_FOR_OPADDR_ADDR:
7199 where = &other_operand_reload_insns;
7201 case RELOAD_FOR_OTHER_ADDRESS:
7202 where = &other_input_address_reload_insns;
7208 push_to_sequence (*where);
7210 /* Auto-increment addresses must be reloaded in a special way. */
7211 if (rl->out && ! rl->out_reg)
7213 /* We are not going to bother supporting the case where a
7214 incremented register can't be copied directly from
7215 OLDEQUIV since this seems highly unlikely. */
7216 gcc_assert (rl->secondary_in_reload < 0);
7218 if (reload_inherited[j])
7219 oldequiv = reloadreg;
7221 old = XEXP (rl->in_reg, 0);
7223 /* Prevent normal processing of this reload. */
7225 /* Output a special code sequence for this case, and forget about
7226 spill reg information. */
7227 new_spill_reg_store[REGNO (reloadreg)] = NULL;
7228 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7231 /* If we are reloading a pseudo-register that was set by the previous
7232 insn, see if we can get rid of that pseudo-register entirely
7233 by redirecting the previous insn into our reload register. */
7235 else if (optimize && REG_P (old)
7236 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7237 && dead_or_set_p (insn, old)
7238 /* This is unsafe if some other reload
7239 uses the same reg first. */
7240 && ! conflicts_with_override (reloadreg)
7241 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7242 rl->when_needed, old, rl->out, j, 0))
7244 rtx temp = PREV_INSN (insn);
7245 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7246 temp = PREV_INSN (temp);
7248 && NONJUMP_INSN_P (temp)
7249 && GET_CODE (PATTERN (temp)) == SET
7250 && SET_DEST (PATTERN (temp)) == old
7251 /* Make sure we can access insn_operand_constraint. */
7252 && asm_noperands (PATTERN (temp)) < 0
7253 /* This is unsafe if operand occurs more than once in current
7254 insn. Perhaps some occurrences aren't reloaded. */
7255 && count_occurrences (PATTERN (insn), old, 0) == 1)
7257 rtx old = SET_DEST (PATTERN (temp));
7258 /* Store into the reload register instead of the pseudo. */
7259 SET_DEST (PATTERN (temp)) = reloadreg;
7261 /* Verify that resulting insn is valid. */
7262 extract_insn (temp);
7263 if (constrain_operands (1))
7265 /* If the previous insn is an output reload, the source is
7266 a reload register, and its spill_reg_store entry will
7267 contain the previous destination. This is now
7269 if (REG_P (SET_SRC (PATTERN (temp)))
7270 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7272 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7273 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7276 /* If these are the only uses of the pseudo reg,
7277 pretend for GDB it lives in the reload reg we used. */
7278 if (REG_N_DEATHS (REGNO (old)) == 1
7279 && REG_N_SETS (REGNO (old)) == 1)
7281 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7282 if (ira_conflicts_p)
7283 /* Inform IRA about the change. */
7284 ira_mark_allocation_change (REGNO (old));
7285 alter_reg (REGNO (old), -1, false);
7289 /* Adjust any debug insns between temp and insn. */
7290 while ((temp = NEXT_INSN (temp)) != insn)
7291 if (DEBUG_INSN_P (temp))
7292 replace_rtx (PATTERN (temp), old, reloadreg);
7294 gcc_assert (NOTE_P (temp));
7298 SET_DEST (PATTERN (temp)) = old;
7303 /* We can't do that, so output an insn to load RELOADREG. */
7305 /* If we have a secondary reload, pick up the secondary register
7306 and icode, if any. If OLDEQUIV and OLD are different or
7307 if this is an in-out reload, recompute whether or not we
7308 still need a secondary register and what the icode should
7309 be. If we still need a secondary register and the class or
7310 icode is different, go back to reloading from OLD if using
7311 OLDEQUIV means that we got the wrong type of register. We
7312 cannot have different class or icode due to an in-out reload
7313 because we don't make such reloads when both the input and
7314 output need secondary reload registers. */
7316 if (! special && rl->secondary_in_reload >= 0)
7318 rtx second_reload_reg = 0;
7319 rtx third_reload_reg = 0;
7320 int secondary_reload = rl->secondary_in_reload;
7321 rtx real_oldequiv = oldequiv;
7324 enum insn_code icode;
7325 enum insn_code tertiary_icode = CODE_FOR_nothing;
7327 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7328 and similarly for OLD.
7329 See comments in get_secondary_reload in reload.c. */
7330 /* If it is a pseudo that cannot be replaced with its
7331 equivalent MEM, we must fall back to reload_in, which
7332 will have all the necessary substitutions registered.
7333 Likewise for a pseudo that can't be replaced with its
7334 equivalent constant.
7336 Take extra care for subregs of such pseudos. Note that
7337 we cannot use reg_equiv_mem in this case because it is
7338 not in the right mode. */
7341 if (GET_CODE (tmp) == SUBREG)
7342 tmp = SUBREG_REG (tmp);
7344 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7345 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7346 || reg_equiv_constant (REGNO (tmp)) != 0))
7348 if (! reg_equiv_mem (REGNO (tmp))
7349 || num_not_at_initial_offset
7350 || GET_CODE (oldequiv) == SUBREG)
7351 real_oldequiv = rl->in;
7353 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7357 if (GET_CODE (tmp) == SUBREG)
7358 tmp = SUBREG_REG (tmp);
7360 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7361 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7362 || reg_equiv_constant (REGNO (tmp)) != 0))
7364 if (! reg_equiv_mem (REGNO (tmp))
7365 || num_not_at_initial_offset
7366 || GET_CODE (old) == SUBREG)
7369 real_old = reg_equiv_mem (REGNO (tmp));
7372 second_reload_reg = rld[secondary_reload].reg_rtx;
7373 if (rld[secondary_reload].secondary_in_reload >= 0)
7375 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7377 third_reload_reg = rld[tertiary_reload].reg_rtx;
7378 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7379 /* We'd have to add more code for quartary reloads. */
7380 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7382 icode = rl->secondary_in_icode;
7384 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7385 || (rl->in != 0 && rl->out != 0))
7387 secondary_reload_info sri, sri2;
7388 enum reg_class new_class, new_t_class;
7390 sri.icode = CODE_FOR_nothing;
7391 sri.prev_sri = NULL;
7393 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7397 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7398 second_reload_reg = 0;
7399 else if (new_class == NO_REGS)
7401 if (reload_adjust_reg_for_icode (&second_reload_reg,
7403 (enum insn_code) sri.icode))
7405 icode = (enum insn_code) sri.icode;
7406 third_reload_reg = 0;
7411 real_oldequiv = real_old;
7414 else if (sri.icode != CODE_FOR_nothing)
7415 /* We currently lack a way to express this in reloads. */
7419 sri2.icode = CODE_FOR_nothing;
7420 sri2.prev_sri = &sri;
7422 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7425 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7427 if (reload_adjust_reg_for_temp (&second_reload_reg,
7431 third_reload_reg = 0;
7432 tertiary_icode = (enum insn_code) sri2.icode;
7437 real_oldequiv = real_old;
7440 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7442 rtx intermediate = second_reload_reg;
7444 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7446 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7450 second_reload_reg = intermediate;
7451 tertiary_icode = (enum insn_code) sri2.icode;
7456 real_oldequiv = real_old;
7459 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7461 rtx intermediate = second_reload_reg;
7463 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7465 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7468 second_reload_reg = intermediate;
7469 tertiary_icode = (enum insn_code) sri2.icode;
7474 real_oldequiv = real_old;
7479 /* This could be handled more intelligently too. */
7481 real_oldequiv = real_old;
7486 /* If we still need a secondary reload register, check
7487 to see if it is being used as a scratch or intermediate
7488 register and generate code appropriately. If we need
7489 a scratch register, use REAL_OLDEQUIV since the form of
7490 the insn may depend on the actual address if it is
7493 if (second_reload_reg)
7495 if (icode != CODE_FOR_nothing)
7497 /* We'd have to add extra code to handle this case. */
7498 gcc_assert (!third_reload_reg);
7500 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7501 second_reload_reg));
7506 /* See if we need a scratch register to load the
7507 intermediate register (a tertiary reload). */
7508 if (tertiary_icode != CODE_FOR_nothing)
7510 emit_insn ((GEN_FCN (tertiary_icode)
7511 (second_reload_reg, real_oldequiv,
7512 third_reload_reg)));
7514 else if (third_reload_reg)
7516 gen_reload (third_reload_reg, real_oldequiv,
7519 gen_reload (second_reload_reg, third_reload_reg,
7524 gen_reload (second_reload_reg, real_oldequiv,
7528 oldequiv = second_reload_reg;
7533 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7535 rtx real_oldequiv = oldequiv;
7537 if ((REG_P (oldequiv)
7538 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7539 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7540 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7541 || (GET_CODE (oldequiv) == SUBREG
7542 && REG_P (SUBREG_REG (oldequiv))
7543 && (REGNO (SUBREG_REG (oldequiv))
7544 >= FIRST_PSEUDO_REGISTER)
7545 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7546 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7547 || (CONSTANT_P (oldequiv)
7548 && (targetm.preferred_reload_class (oldequiv,
7549 REGNO_REG_CLASS (REGNO (reloadreg)))
7551 real_oldequiv = rl->in;
7552 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7556 if (cfun->can_throw_non_call_exceptions)
7557 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7559 /* End this sequence. */
7560 *where = get_insns ();
7563 /* Update reload_override_in so that delete_address_reloads_1
7564 can see the actual register usage. */
7566 reload_override_in[j] = oldequiv;
7569 /* Generate insns to for the output reload RL, which is for the insn described
7570 by CHAIN and has the number J. */
7572 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7576 rtx insn = chain->insn;
7579 enum machine_mode mode;
7583 if (rl->when_needed == RELOAD_OTHER)
7586 push_to_sequence (output_reload_insns[rl->opnum]);
7588 rl_reg_rtx = reload_reg_rtx_for_output[j];
7589 mode = GET_MODE (rl_reg_rtx);
7591 reloadreg = rl_reg_rtx;
7593 /* If we need two reload regs, set RELOADREG to the intermediate
7594 one, since it will be stored into OLD. We might need a secondary
7595 register only for an input reload, so check again here. */
7597 if (rl->secondary_out_reload >= 0)
7600 int secondary_reload = rl->secondary_out_reload;
7601 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7603 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7604 && reg_equiv_mem (REGNO (old)) != 0)
7605 real_old = reg_equiv_mem (REGNO (old));
7607 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7609 rtx second_reloadreg = reloadreg;
7610 reloadreg = rld[secondary_reload].reg_rtx;
7612 /* See if RELOADREG is to be used as a scratch register
7613 or as an intermediate register. */
7614 if (rl->secondary_out_icode != CODE_FOR_nothing)
7616 /* We'd have to add extra code to handle this case. */
7617 gcc_assert (tertiary_reload < 0);
7619 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7620 (real_old, second_reloadreg, reloadreg)));
7625 /* See if we need both a scratch and intermediate reload
7628 enum insn_code tertiary_icode
7629 = rld[secondary_reload].secondary_out_icode;
7631 /* We'd have to add more code for quartary reloads. */
7632 gcc_assert (tertiary_reload < 0
7633 || rld[tertiary_reload].secondary_out_reload < 0);
7635 if (GET_MODE (reloadreg) != mode)
7636 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7638 if (tertiary_icode != CODE_FOR_nothing)
7640 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7642 /* Copy primary reload reg to secondary reload reg.
7643 (Note that these have been swapped above, then
7644 secondary reload reg to OLD using our insn.) */
7646 /* If REAL_OLD is a paradoxical SUBREG, remove it
7647 and try to put the opposite SUBREG on
7649 strip_paradoxical_subreg (&real_old, &reloadreg);
7651 gen_reload (reloadreg, second_reloadreg,
7652 rl->opnum, rl->when_needed);
7653 emit_insn ((GEN_FCN (tertiary_icode)
7654 (real_old, reloadreg, third_reloadreg)));
7660 /* Copy between the reload regs here and then to
7663 gen_reload (reloadreg, second_reloadreg,
7664 rl->opnum, rl->when_needed);
7665 if (tertiary_reload >= 0)
7667 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7669 gen_reload (third_reloadreg, reloadreg,
7670 rl->opnum, rl->when_needed);
7671 reloadreg = third_reloadreg;
7678 /* Output the last reload insn. */
7683 /* Don't output the last reload if OLD is not the dest of
7684 INSN and is in the src and is clobbered by INSN. */
7685 if (! flag_expensive_optimizations
7687 || !(set = single_set (insn))
7688 || rtx_equal_p (old, SET_DEST (set))
7689 || !reg_mentioned_p (old, SET_SRC (set))
7690 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7691 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7692 gen_reload (old, reloadreg, rl->opnum,
7696 /* Look at all insns we emitted, just to be safe. */
7697 for (p = get_insns (); p; p = NEXT_INSN (p))
7700 rtx pat = PATTERN (p);
7702 /* If this output reload doesn't come from a spill reg,
7703 clear any memory of reloaded copies of the pseudo reg.
7704 If this output reload comes from a spill reg,
7705 reg_has_output_reload will make this do nothing. */
7706 note_stores (pat, forget_old_reloads_1, NULL);
7708 if (reg_mentioned_p (rl_reg_rtx, pat))
7710 rtx set = single_set (insn);
7711 if (reload_spill_index[j] < 0
7713 && SET_SRC (set) == rl_reg_rtx)
7715 int src = REGNO (SET_SRC (set));
7717 reload_spill_index[j] = src;
7718 SET_HARD_REG_BIT (reg_is_output_reload, src);
7719 if (find_regno_note (insn, REG_DEAD, src))
7720 SET_HARD_REG_BIT (reg_reloaded_died, src);
7722 if (HARD_REGISTER_P (rl_reg_rtx))
7724 int s = rl->secondary_out_reload;
7725 set = single_set (p);
7726 /* If this reload copies only to the secondary reload
7727 register, the secondary reload does the actual
7729 if (s >= 0 && set == NULL_RTX)
7730 /* We can't tell what function the secondary reload
7731 has and where the actual store to the pseudo is
7732 made; leave new_spill_reg_store alone. */
7735 && SET_SRC (set) == rl_reg_rtx
7736 && SET_DEST (set) == rld[s].reg_rtx)
7738 /* Usually the next instruction will be the
7739 secondary reload insn; if we can confirm
7740 that it is, setting new_spill_reg_store to
7741 that insn will allow an extra optimization. */
7742 rtx s_reg = rld[s].reg_rtx;
7743 rtx next = NEXT_INSN (p);
7744 rld[s].out = rl->out;
7745 rld[s].out_reg = rl->out_reg;
7746 set = single_set (next);
7747 if (set && SET_SRC (set) == s_reg
7748 && ! new_spill_reg_store[REGNO (s_reg)])
7750 SET_HARD_REG_BIT (reg_is_output_reload,
7752 new_spill_reg_store[REGNO (s_reg)] = next;
7756 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7761 if (rl->when_needed == RELOAD_OTHER)
7763 emit_insn (other_output_reload_insns[rl->opnum]);
7764 other_output_reload_insns[rl->opnum] = get_insns ();
7767 output_reload_insns[rl->opnum] = get_insns ();
7769 if (cfun->can_throw_non_call_exceptions)
7770 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7775 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7776 and has the number J. */
7778 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7780 rtx insn = chain->insn;
7781 rtx old = (rl->in && MEM_P (rl->in)
7782 ? rl->in_reg : rl->in);
7783 rtx reg_rtx = rl->reg_rtx;
7787 enum machine_mode mode;
7789 /* Determine the mode to reload in.
7790 This is very tricky because we have three to choose from.
7791 There is the mode the insn operand wants (rl->inmode).
7792 There is the mode of the reload register RELOADREG.
7793 There is the intrinsic mode of the operand, which we could find
7794 by stripping some SUBREGs.
7795 It turns out that RELOADREG's mode is irrelevant:
7796 we can change that arbitrarily.
7798 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7799 then the reload reg may not support QImode moves, so use SImode.
7800 If foo is in memory due to spilling a pseudo reg, this is safe,
7801 because the QImode value is in the least significant part of a
7802 slot big enough for a SImode. If foo is some other sort of
7803 memory reference, then it is impossible to reload this case,
7804 so previous passes had better make sure this never happens.
7806 Then consider a one-word union which has SImode and one of its
7807 members is a float, being fetched as (SUBREG:SF union:SI).
7808 We must fetch that as SFmode because we could be loading into
7809 a float-only register. In this case OLD's mode is correct.
7811 Consider an immediate integer: it has VOIDmode. Here we need
7812 to get a mode from something else.
7814 In some cases, there is a fourth mode, the operand's
7815 containing mode. If the insn specifies a containing mode for
7816 this operand, it overrides all others.
7818 I am not sure whether the algorithm here is always right,
7819 but it does the right things in those cases. */
7821 mode = GET_MODE (old);
7822 if (mode == VOIDmode)
7825 /* We cannot use gen_lowpart_common since it can do the wrong thing
7826 when REG_RTX has a multi-word mode. Note that REG_RTX must
7827 always be a REG here. */
7828 if (GET_MODE (reg_rtx) != mode)
7829 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7831 reload_reg_rtx_for_input[j] = reg_rtx;
7834 /* AUTO_INC reloads need to be handled even if inherited. We got an
7835 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7836 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7837 && ! rtx_equal_p (reg_rtx, old)
7839 emit_input_reload_insns (chain, rld + j, old, j);
7841 /* When inheriting a wider reload, we have a MEM in rl->in,
7842 e.g. inheriting a SImode output reload for
7843 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7844 if (optimize && reload_inherited[j] && rl->in
7846 && MEM_P (rl->in_reg)
7847 && reload_spill_index[j] >= 0
7848 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7849 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7851 /* If we are reloading a register that was recently stored in with an
7852 output-reload, see if we can prove there was
7853 actually no need to store the old value in it. */
7856 && (reload_inherited[j] || reload_override_in[j])
7859 && spill_reg_store[REGNO (reg_rtx)] != 0
7861 /* There doesn't seem to be any reason to restrict this to pseudos
7862 and doing so loses in the case where we are copying from a
7863 register of the wrong class. */
7864 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7866 /* The insn might have already some references to stackslots
7867 replaced by MEMs, while reload_out_reg still names the
7869 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7870 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7871 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7874 /* Do output reloading for reload RL, which is for the insn described by
7875 CHAIN and has the number J.
7876 ??? At some point we need to support handling output reloads of
7877 JUMP_INSNs or insns that set cc0. */
7879 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7882 rtx insn = chain->insn;
7883 /* If this is an output reload that stores something that is
7884 not loaded in this same reload, see if we can eliminate a previous
7886 rtx pseudo = rl->out_reg;
7887 rtx reg_rtx = rl->reg_rtx;
7889 if (rl->out && reg_rtx)
7891 enum machine_mode mode;
7893 /* Determine the mode to reload in.
7894 See comments above (for input reloading). */
7895 mode = GET_MODE (rl->out);
7896 if (mode == VOIDmode)
7898 /* VOIDmode should never happen for an output. */
7899 if (asm_noperands (PATTERN (insn)) < 0)
7900 /* It's the compiler's fault. */
7901 fatal_insn ("VOIDmode on an output", insn);
7902 error_for_asm (insn, "output operand is constant in %<asm%>");
7903 /* Prevent crash--use something we know is valid. */
7905 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7907 if (GET_MODE (reg_rtx) != mode)
7908 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7910 reload_reg_rtx_for_output[j] = reg_rtx;
7915 && ! rtx_equal_p (rl->in_reg, pseudo)
7916 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7917 && reg_last_reload_reg[REGNO (pseudo)])
7919 int pseudo_no = REGNO (pseudo);
7920 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7922 /* We don't need to test full validity of last_regno for
7923 inherit here; we only want to know if the store actually
7924 matches the pseudo. */
7925 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7926 && reg_reloaded_contents[last_regno] == pseudo_no
7927 && spill_reg_store[last_regno]
7928 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7929 delete_output_reload (insn, j, last_regno, reg_rtx);
7935 || rtx_equal_p (old, reg_rtx))
7938 /* An output operand that dies right away does need a reload,
7939 but need not be copied from it. Show the new location in the
7941 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7942 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7944 XEXP (note, 0) = reg_rtx;
7947 /* Likewise for a SUBREG of an operand that dies. */
7948 else if (GET_CODE (old) == SUBREG
7949 && REG_P (SUBREG_REG (old))
7950 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7953 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7956 else if (GET_CODE (old) == SCRATCH)
7957 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7958 but we don't want to make an output reload. */
7961 /* If is a JUMP_INSN, we can't support output reloads yet. */
7962 gcc_assert (NONJUMP_INSN_P (insn));
7964 emit_output_reload_insns (chain, rld + j, j);
7967 /* A reload copies values of MODE from register SRC to register DEST.
7968 Return true if it can be treated for inheritance purposes like a
7969 group of reloads, each one reloading a single hard register. The
7970 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7971 occupy the same number of hard registers. */
7974 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7975 int src ATTRIBUTE_UNUSED,
7976 enum machine_mode mode ATTRIBUTE_UNUSED)
7978 #ifdef CANNOT_CHANGE_MODE_CLASS
7979 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7980 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7986 /* Output insns to reload values in and out of the chosen reload regs. */
7989 emit_reload_insns (struct insn_chain *chain)
7991 rtx insn = chain->insn;
7995 CLEAR_HARD_REG_SET (reg_reloaded_died);
7997 for (j = 0; j < reload_n_operands; j++)
7998 input_reload_insns[j] = input_address_reload_insns[j]
7999 = inpaddr_address_reload_insns[j]
8000 = output_reload_insns[j] = output_address_reload_insns[j]
8001 = outaddr_address_reload_insns[j]
8002 = other_output_reload_insns[j] = 0;
8003 other_input_address_reload_insns = 0;
8004 other_input_reload_insns = 0;
8005 operand_reload_insns = 0;
8006 other_operand_reload_insns = 0;
8008 /* Dump reloads into the dump file. */
8011 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8012 debug_reload_to_stream (dump_file);
8015 /* Now output the instructions to copy the data into and out of the
8016 reload registers. Do these in the order that the reloads were reported,
8017 since reloads of base and index registers precede reloads of operands
8018 and the operands may need the base and index registers reloaded. */
8020 for (j = 0; j < n_reloads; j++)
8022 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8026 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8027 new_spill_reg_store[i] = 0;
8030 do_input_reload (chain, rld + j, j);
8031 do_output_reload (chain, rld + j, j);
8034 /* Now write all the insns we made for reloads in the order expected by
8035 the allocation functions. Prior to the insn being reloaded, we write
8036 the following reloads:
8038 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8040 RELOAD_OTHER reloads.
8042 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8043 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8044 RELOAD_FOR_INPUT reload for the operand.
8046 RELOAD_FOR_OPADDR_ADDRS reloads.
8048 RELOAD_FOR_OPERAND_ADDRESS reloads.
8050 After the insn being reloaded, we write the following:
8052 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8053 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8054 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8055 reloads for the operand. The RELOAD_OTHER output reloads are
8056 output in descending order by reload number. */
8058 emit_insn_before (other_input_address_reload_insns, insn);
8059 emit_insn_before (other_input_reload_insns, insn);
8061 for (j = 0; j < reload_n_operands; j++)
8063 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8064 emit_insn_before (input_address_reload_insns[j], insn);
8065 emit_insn_before (input_reload_insns[j], insn);
8068 emit_insn_before (other_operand_reload_insns, insn);
8069 emit_insn_before (operand_reload_insns, insn);
8071 for (j = 0; j < reload_n_operands; j++)
8073 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8074 x = emit_insn_after (output_address_reload_insns[j], x);
8075 x = emit_insn_after (output_reload_insns[j], x);
8076 emit_insn_after (other_output_reload_insns[j], x);
8079 /* For all the spill regs newly reloaded in this instruction,
8080 record what they were reloaded from, so subsequent instructions
8081 can inherit the reloads.
8083 Update spill_reg_store for the reloads of this insn.
8084 Copy the elements that were updated in the loop above. */
8086 for (j = 0; j < n_reloads; j++)
8088 int r = reload_order[j];
8089 int i = reload_spill_index[r];
8091 /* If this is a non-inherited input reload from a pseudo, we must
8092 clear any memory of a previous store to the same pseudo. Only do
8093 something if there will not be an output reload for the pseudo
8095 if (rld[r].in_reg != 0
8096 && ! (reload_inherited[r] || reload_override_in[r]))
8098 rtx reg = rld[r].in_reg;
8100 if (GET_CODE (reg) == SUBREG)
8101 reg = SUBREG_REG (reg);
8104 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8105 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8107 int nregno = REGNO (reg);
8109 if (reg_last_reload_reg[nregno])
8111 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8113 if (reg_reloaded_contents[last_regno] == nregno)
8114 spill_reg_store[last_regno] = 0;
8119 /* I is nonneg if this reload used a register.
8120 If rld[r].reg_rtx is 0, this is an optional reload
8121 that we opted to ignore. */
8123 if (i >= 0 && rld[r].reg_rtx != 0)
8125 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8128 /* For a multi register reload, we need to check if all or part
8129 of the value lives to the end. */
8130 for (k = 0; k < nr; k++)
8131 if (reload_reg_reaches_end_p (i + k, r))
8132 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8134 /* Maybe the spill reg contains a copy of reload_out. */
8136 && (REG_P (rld[r].out)
8138 ? REG_P (rld[r].out_reg)
8139 /* The reload value is an auto-modification of
8140 some kind. For PRE_INC, POST_INC, PRE_DEC
8141 and POST_DEC, we record an equivalence
8142 between the reload register and the operand
8143 on the optimistic assumption that we can make
8144 the equivalence hold. reload_as_needed must
8145 then either make it hold or invalidate the
8148 PRE_MODIFY and POST_MODIFY addresses are reloaded
8149 somewhat differently, and allowing them here leads
8151 : (GET_CODE (rld[r].out) != POST_MODIFY
8152 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8155 enum machine_mode mode;
8158 reg = reload_reg_rtx_for_output[r];
8159 mode = GET_MODE (reg);
8160 regno = REGNO (reg);
8161 nregs = hard_regno_nregs[regno][mode];
8162 if (reload_regs_reach_end_p (regno, nregs, r))
8164 rtx out = (REG_P (rld[r].out)
8168 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8169 int out_regno = REGNO (out);
8170 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8171 : hard_regno_nregs[out_regno][mode]);
8174 spill_reg_store[regno] = new_spill_reg_store[regno];
8175 spill_reg_stored_to[regno] = out;
8176 reg_last_reload_reg[out_regno] = reg;
8178 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8179 && nregs == out_nregs
8180 && inherit_piecemeal_p (out_regno, regno, mode));
8182 /* If OUT_REGNO is a hard register, it may occupy more than
8183 one register. If it does, say what is in the
8184 rest of the registers assuming that both registers
8185 agree on how many words the object takes. If not,
8186 invalidate the subsequent registers. */
8188 if (HARD_REGISTER_NUM_P (out_regno))
8189 for (k = 1; k < out_nregs; k++)
8190 reg_last_reload_reg[out_regno + k]
8191 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8193 /* Now do the inverse operation. */
8194 for (k = 0; k < nregs; k++)
8196 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8197 reg_reloaded_contents[regno + k]
8198 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8201 reg_reloaded_insn[regno + k] = insn;
8202 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8203 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8204 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8207 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8212 /* Maybe the spill reg contains a copy of reload_in. Only do
8213 something if there will not be an output reload for
8214 the register being reloaded. */
8215 else if (rld[r].out_reg == 0
8217 && ((REG_P (rld[r].in)
8218 && !HARD_REGISTER_P (rld[r].in)
8219 && !REGNO_REG_SET_P (®_has_output_reload,
8221 || (REG_P (rld[r].in_reg)
8222 && !REGNO_REG_SET_P (®_has_output_reload,
8223 REGNO (rld[r].in_reg))))
8224 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8227 enum machine_mode mode;
8230 reg = reload_reg_rtx_for_input[r];
8231 mode = GET_MODE (reg);
8232 regno = REGNO (reg);
8233 nregs = hard_regno_nregs[regno][mode];
8234 if (reload_regs_reach_end_p (regno, nregs, r))
8241 if (REG_P (rld[r].in)
8242 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8244 else if (REG_P (rld[r].in_reg))
8247 in = XEXP (rld[r].in_reg, 0);
8248 in_regno = REGNO (in);
8250 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8251 : hard_regno_nregs[in_regno][mode]);
8253 reg_last_reload_reg[in_regno] = reg;
8255 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8256 && nregs == in_nregs
8257 && inherit_piecemeal_p (regno, in_regno, mode));
8259 if (HARD_REGISTER_NUM_P (in_regno))
8260 for (k = 1; k < in_nregs; k++)
8261 reg_last_reload_reg[in_regno + k]
8262 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8264 /* Unless we inherited this reload, show we haven't
8265 recently done a store.
8266 Previous stores of inherited auto_inc expressions
8267 also have to be discarded. */
8268 if (! reload_inherited[r]
8269 || (rld[r].out && ! rld[r].out_reg))
8270 spill_reg_store[regno] = 0;
8272 for (k = 0; k < nregs; k++)
8274 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8275 reg_reloaded_contents[regno + k]
8276 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8279 reg_reloaded_insn[regno + k] = insn;
8280 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8281 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8282 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8285 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8292 /* The following if-statement was #if 0'd in 1.34 (or before...).
8293 It's reenabled in 1.35 because supposedly nothing else
8294 deals with this problem. */
8296 /* If a register gets output-reloaded from a non-spill register,
8297 that invalidates any previous reloaded copy of it.
8298 But forget_old_reloads_1 won't get to see it, because
8299 it thinks only about the original insn. So invalidate it here.
8300 Also do the same thing for RELOAD_OTHER constraints where the
8301 output is discarded. */
8303 && ((rld[r].out != 0
8304 && (REG_P (rld[r].out)
8305 || (MEM_P (rld[r].out)
8306 && REG_P (rld[r].out_reg))))
8307 || (rld[r].out == 0 && rld[r].out_reg
8308 && REG_P (rld[r].out_reg))))
8310 rtx out = ((rld[r].out && REG_P (rld[r].out))
8311 ? rld[r].out : rld[r].out_reg);
8312 int out_regno = REGNO (out);
8313 enum machine_mode mode = GET_MODE (out);
8315 /* REG_RTX is now set or clobbered by the main instruction.
8316 As the comment above explains, forget_old_reloads_1 only
8317 sees the original instruction, and there is no guarantee
8318 that the original instruction also clobbered REG_RTX.
8319 For example, if find_reloads sees that the input side of
8320 a matched operand pair dies in this instruction, it may
8321 use the input register as the reload register.
8323 Calling forget_old_reloads_1 is a waste of effort if
8324 REG_RTX is also the output register.
8326 If we know that REG_RTX holds the value of a pseudo
8327 register, the code after the call will record that fact. */
8328 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8329 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8331 if (!HARD_REGISTER_NUM_P (out_regno))
8333 rtx src_reg, store_insn = NULL_RTX;
8335 reg_last_reload_reg[out_regno] = 0;
8337 /* If we can find a hard register that is stored, record
8338 the storing insn so that we may delete this insn with
8339 delete_output_reload. */
8340 src_reg = reload_reg_rtx_for_output[r];
8342 /* If this is an optional reload, try to find the source reg
8343 from an input reload. */
8346 rtx set = single_set (insn);
8347 if (set && SET_DEST (set) == rld[r].out)
8351 src_reg = SET_SRC (set);
8353 for (k = 0; k < n_reloads; k++)
8355 if (rld[k].in == src_reg)
8357 src_reg = reload_reg_rtx_for_input[k];
8364 store_insn = new_spill_reg_store[REGNO (src_reg)];
8365 if (src_reg && REG_P (src_reg)
8366 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8368 int src_regno, src_nregs, k;
8371 gcc_assert (GET_MODE (src_reg) == mode);
8372 src_regno = REGNO (src_reg);
8373 src_nregs = hard_regno_nregs[src_regno][mode];
8374 /* The place where to find a death note varies with
8375 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8376 necessarily checked exactly in the code that moves
8377 notes, so just check both locations. */
8378 note = find_regno_note (insn, REG_DEAD, src_regno);
8379 if (! note && store_insn)
8380 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8381 for (k = 0; k < src_nregs; k++)
8383 spill_reg_store[src_regno + k] = store_insn;
8384 spill_reg_stored_to[src_regno + k] = out;
8385 reg_reloaded_contents[src_regno + k] = out_regno;
8386 reg_reloaded_insn[src_regno + k] = store_insn;
8387 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8388 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8389 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8391 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8394 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8396 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8398 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8400 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8402 reg_last_reload_reg[out_regno] = src_reg;
8403 /* We have to set reg_has_output_reload here, or else
8404 forget_old_reloads_1 will clear reg_last_reload_reg
8406 SET_REGNO_REG_SET (®_has_output_reload,
8412 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8414 for (k = 0; k < out_nregs; k++)
8415 reg_last_reload_reg[out_regno + k] = 0;
8419 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8422 /* Go through the motions to emit INSN and test if it is strictly valid.
8423 Return the emitted insn if valid, else return NULL. */
8426 emit_insn_if_valid_for_reload (rtx insn)
8428 rtx last = get_last_insn ();
8431 insn = emit_insn (insn);
8432 code = recog_memoized (insn);
8436 extract_insn (insn);
8437 /* We want constrain operands to treat this insn strictly in its
8438 validity determination, i.e., the way it would after reload has
8440 if (constrain_operands (1))
8444 delete_insns_since (last);
8448 /* Emit code to perform a reload from IN (which may be a reload register) to
8449 OUT (which may also be a reload register). IN or OUT is from operand
8450 OPNUM with reload type TYPE.
8452 Returns first insn emitted. */
8455 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8457 rtx last = get_last_insn ();
8460 /* If IN is a paradoxical SUBREG, remove it and try to put the
8461 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8462 if (!strip_paradoxical_subreg (&in, &out))
8463 strip_paradoxical_subreg (&out, &in);
8465 /* How to do this reload can get quite tricky. Normally, we are being
8466 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8467 register that didn't get a hard register. In that case we can just
8468 call emit_move_insn.
8470 We can also be asked to reload a PLUS that adds a register or a MEM to
8471 another register, constant or MEM. This can occur during frame pointer
8472 elimination and while reloading addresses. This case is handled by
8473 trying to emit a single insn to perform the add. If it is not valid,
8474 we use a two insn sequence.
8476 Or we can be asked to reload an unary operand that was a fragment of
8477 an addressing mode, into a register. If it isn't recognized as-is,
8478 we try making the unop operand and the reload-register the same:
8479 (set reg:X (unop:X expr:Y))
8480 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8482 Finally, we could be called to handle an 'o' constraint by putting
8483 an address into a register. In that case, we first try to do this
8484 with a named pattern of "reload_load_address". If no such pattern
8485 exists, we just emit a SET insn and hope for the best (it will normally
8486 be valid on machines that use 'o').
8488 This entire process is made complex because reload will never
8489 process the insns we generate here and so we must ensure that
8490 they will fit their constraints and also by the fact that parts of
8491 IN might be being reloaded separately and replaced with spill registers.
8492 Because of this, we are, in some sense, just guessing the right approach
8493 here. The one listed above seems to work.
8495 ??? At some point, this whole thing needs to be rethought. */
8497 if (GET_CODE (in) == PLUS
8498 && (REG_P (XEXP (in, 0))
8499 || GET_CODE (XEXP (in, 0)) == SUBREG
8500 || MEM_P (XEXP (in, 0)))
8501 && (REG_P (XEXP (in, 1))
8502 || GET_CODE (XEXP (in, 1)) == SUBREG
8503 || CONSTANT_P (XEXP (in, 1))
8504 || MEM_P (XEXP (in, 1))))
8506 /* We need to compute the sum of a register or a MEM and another
8507 register, constant, or MEM, and put it into the reload
8508 register. The best possible way of doing this is if the machine
8509 has a three-operand ADD insn that accepts the required operands.
8511 The simplest approach is to try to generate such an insn and see if it
8512 is recognized and matches its constraints. If so, it can be used.
8514 It might be better not to actually emit the insn unless it is valid,
8515 but we need to pass the insn as an operand to `recog' and
8516 `extract_insn' and it is simpler to emit and then delete the insn if
8517 not valid than to dummy things up. */
8519 rtx op0, op1, tem, insn;
8520 enum insn_code code;
8522 op0 = find_replacement (&XEXP (in, 0));
8523 op1 = find_replacement (&XEXP (in, 1));
8525 /* Since constraint checking is strict, commutativity won't be
8526 checked, so we need to do that here to avoid spurious failure
8527 if the add instruction is two-address and the second operand
8528 of the add is the same as the reload reg, which is frequently
8529 the case. If the insn would be A = B + A, rearrange it so
8530 it will be A = A + B as constrain_operands expects. */
8532 if (REG_P (XEXP (in, 1))
8533 && REGNO (out) == REGNO (XEXP (in, 1)))
8534 tem = op0, op0 = op1, op1 = tem;
8536 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8537 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8539 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8543 /* If that failed, we must use a conservative two-insn sequence.
8545 Use a move to copy one operand into the reload register. Prefer
8546 to reload a constant, MEM or pseudo since the move patterns can
8547 handle an arbitrary operand. If OP1 is not a constant, MEM or
8548 pseudo and OP1 is not a valid operand for an add instruction, then
8551 After reloading one of the operands into the reload register, add
8552 the reload register to the output register.
8554 If there is another way to do this for a specific machine, a
8555 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8558 code = optab_handler (add_optab, GET_MODE (out));
8560 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8562 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8563 || (code != CODE_FOR_nothing
8564 && !insn_operand_matches (code, 2, op1)))
8565 tem = op0, op0 = op1, op1 = tem;
8567 gen_reload (out, op0, opnum, type);
8569 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8570 This fixes a problem on the 32K where the stack pointer cannot
8571 be used as an operand of an add insn. */
8573 if (rtx_equal_p (op0, op1))
8576 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8579 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8580 set_dst_reg_note (insn, REG_EQUIV, in, out);
8584 /* If that failed, copy the address register to the reload register.
8585 Then add the constant to the reload register. */
8587 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8588 gen_reload (out, op1, opnum, type);
8589 insn = emit_insn (gen_add2_insn (out, op0));
8590 set_dst_reg_note (insn, REG_EQUIV, in, out);
8593 #ifdef SECONDARY_MEMORY_NEEDED
8594 /* If we need a memory location to do the move, do it that way. */
8595 else if ((REG_P (in)
8596 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8597 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8599 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8600 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8601 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8602 REGNO_REG_CLASS (reg_or_subregno (out)),
8605 /* Get the memory to use and rewrite both registers to its mode. */
8606 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8608 if (GET_MODE (loc) != GET_MODE (out))
8609 out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8611 if (GET_MODE (loc) != GET_MODE (in))
8612 in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8614 gen_reload (loc, in, opnum, type);
8615 gen_reload (out, loc, opnum, type);
8618 else if (REG_P (out) && UNARY_P (in))
8625 op1 = find_replacement (&XEXP (in, 0));
8626 if (op1 != XEXP (in, 0))
8627 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8629 /* First, try a plain SET. */
8630 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8634 /* If that failed, move the inner operand to the reload
8635 register, and try the same unop with the inner expression
8636 replaced with the reload register. */
8638 if (GET_MODE (op1) != GET_MODE (out))
8639 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8643 gen_reload (out_moded, op1, opnum, type);
8646 = gen_rtx_SET (VOIDmode, out,
8647 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8649 insn = emit_insn_if_valid_for_reload (insn);
8652 set_unique_reg_note (insn, REG_EQUIV, in);
8656 fatal_insn ("failure trying to reload:", set);
8658 /* If IN is a simple operand, use gen_move_insn. */
8659 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8661 tem = emit_insn (gen_move_insn (out, in));
8662 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8663 mark_jump_label (in, tem, 0);
8666 #ifdef HAVE_reload_load_address
8667 else if (HAVE_reload_load_address)
8668 emit_insn (gen_reload_load_address (out, in));
8671 /* Otherwise, just write (set OUT IN) and hope for the best. */
8673 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8675 /* Return the first insn emitted.
8676 We can not just return get_last_insn, because there may have
8677 been multiple instructions emitted. Also note that gen_move_insn may
8678 emit more than one insn itself, so we can not assume that there is one
8679 insn emitted per emit_insn_before call. */
8681 return last ? NEXT_INSN (last) : get_insns ();
8684 /* Delete a previously made output-reload whose result we now believe
8685 is not needed. First we double-check.
8687 INSN is the insn now being processed.
8688 LAST_RELOAD_REG is the hard register number for which we want to delete
8689 the last output reload.
8690 J is the reload-number that originally used REG. The caller has made
8691 certain that reload J doesn't use REG any longer for input.
8692 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8695 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8697 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8698 rtx reg = spill_reg_stored_to[last_reload_reg];
8701 int n_inherited = 0;
8707 /* It is possible that this reload has been only used to set another reload
8708 we eliminated earlier and thus deleted this instruction too. */
8709 if (INSN_DELETED_P (output_reload_insn))
8712 /* Get the raw pseudo-register referred to. */
8714 while (GET_CODE (reg) == SUBREG)
8715 reg = SUBREG_REG (reg);
8716 substed = reg_equiv_memory_loc (REGNO (reg));
8718 /* This is unsafe if the operand occurs more often in the current
8719 insn than it is inherited. */
8720 for (k = n_reloads - 1; k >= 0; k--)
8722 rtx reg2 = rld[k].in;
8725 if (MEM_P (reg2) || reload_override_in[k])
8726 reg2 = rld[k].in_reg;
8728 if (rld[k].out && ! rld[k].out_reg)
8729 reg2 = XEXP (rld[k].in_reg, 0);
8731 while (GET_CODE (reg2) == SUBREG)
8732 reg2 = SUBREG_REG (reg2);
8733 if (rtx_equal_p (reg2, reg))
8735 if (reload_inherited[k] || reload_override_in[k] || k == j)
8741 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8742 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8743 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8746 n_occurrences += count_occurrences (PATTERN (insn),
8747 eliminate_regs (substed, VOIDmode,
8749 for (i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8751 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8752 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8754 if (n_occurrences > n_inherited)
8757 regno = REGNO (reg);
8758 if (regno >= FIRST_PSEUDO_REGISTER)
8761 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8763 /* If the pseudo-reg we are reloading is no longer referenced
8764 anywhere between the store into it and here,
8765 and we're within the same basic block, then the value can only
8766 pass through the reload reg and end up here.
8767 Otherwise, give up--return. */
8768 for (i1 = NEXT_INSN (output_reload_insn);
8769 i1 != insn; i1 = NEXT_INSN (i1))
8771 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8773 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8774 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8776 /* If this is USE in front of INSN, we only have to check that
8777 there are no more references than accounted for by inheritance. */
8778 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8780 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8781 i1 = NEXT_INSN (i1);
8783 if (n_occurrences <= n_inherited && i1 == insn)
8789 /* We will be deleting the insn. Remove the spill reg information. */
8790 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8792 spill_reg_store[last_reload_reg + k] = 0;
8793 spill_reg_stored_to[last_reload_reg + k] = 0;
8796 /* The caller has already checked that REG dies or is set in INSN.
8797 It has also checked that we are optimizing, and thus some
8798 inaccuracies in the debugging information are acceptable.
8799 So we could just delete output_reload_insn. But in some cases
8800 we can improve the debugging information without sacrificing
8801 optimization - maybe even improving the code: See if the pseudo
8802 reg has been completely replaced with reload regs. If so, delete
8803 the store insn and forget we had a stack slot for the pseudo. */
8804 if (rld[j].out != rld[j].in
8805 && REG_N_DEATHS (REGNO (reg)) == 1
8806 && REG_N_SETS (REGNO (reg)) == 1
8807 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8808 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8812 /* We know that it was used only between here and the beginning of
8813 the current basic block. (We also know that the last use before
8814 INSN was the output reload we are thinking of deleting, but never
8815 mind that.) Search that range; see if any ref remains. */
8816 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8818 rtx set = single_set (i2);
8820 /* Uses which just store in the pseudo don't count,
8821 since if they are the only uses, they are dead. */
8822 if (set != 0 && SET_DEST (set) == reg)
8827 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8828 && reg_mentioned_p (reg, PATTERN (i2)))
8830 /* Some other ref remains; just delete the output reload we
8832 delete_address_reloads (output_reload_insn, insn);
8833 delete_insn (output_reload_insn);
8838 /* Delete the now-dead stores into this pseudo. Note that this
8839 loop also takes care of deleting output_reload_insn. */
8840 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8842 rtx set = single_set (i2);
8844 if (set != 0 && SET_DEST (set) == reg)
8846 delete_address_reloads (i2, insn);
8854 /* For the debugging info, say the pseudo lives in this reload reg. */
8855 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8856 if (ira_conflicts_p)
8857 /* Inform IRA about the change. */
8858 ira_mark_allocation_change (REGNO (reg));
8859 alter_reg (REGNO (reg), -1, false);
8863 delete_address_reloads (output_reload_insn, insn);
8864 delete_insn (output_reload_insn);
8868 /* We are going to delete DEAD_INSN. Recursively delete loads of
8869 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8870 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8872 delete_address_reloads (rtx dead_insn, rtx current_insn)
8874 rtx set = single_set (dead_insn);
8875 rtx set2, dst, prev, next;
8878 rtx dst = SET_DEST (set);
8880 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8882 /* If we deleted the store from a reloaded post_{in,de}c expression,
8883 we can delete the matching adds. */
8884 prev = PREV_INSN (dead_insn);
8885 next = NEXT_INSN (dead_insn);
8886 if (! prev || ! next)
8888 set = single_set (next);
8889 set2 = single_set (prev);
8891 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8892 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8893 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8895 dst = SET_DEST (set);
8896 if (! rtx_equal_p (dst, SET_DEST (set2))
8897 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8898 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8899 || (INTVAL (XEXP (SET_SRC (set), 1))
8900 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8902 delete_related_insns (prev);
8903 delete_related_insns (next);
8906 /* Subfunction of delete_address_reloads: process registers found in X. */
8908 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8910 rtx prev, set, dst, i2;
8912 enum rtx_code code = GET_CODE (x);
8916 const char *fmt = GET_RTX_FORMAT (code);
8917 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8920 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8921 else if (fmt[i] == 'E')
8923 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8924 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8931 if (spill_reg_order[REGNO (x)] < 0)
8934 /* Scan backwards for the insn that sets x. This might be a way back due
8936 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8938 code = GET_CODE (prev);
8939 if (code == CODE_LABEL || code == JUMP_INSN)
8943 if (reg_set_p (x, PATTERN (prev)))
8945 if (reg_referenced_p (x, PATTERN (prev)))
8948 if (! prev || INSN_UID (prev) < reload_first_uid)
8950 /* Check that PREV only sets the reload register. */
8951 set = single_set (prev);
8954 dst = SET_DEST (set);
8956 || ! rtx_equal_p (dst, x))
8958 if (! reg_set_p (dst, PATTERN (dead_insn)))
8960 /* Check if DST was used in a later insn -
8961 it might have been inherited. */
8962 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8968 if (reg_referenced_p (dst, PATTERN (i2)))
8970 /* If there is a reference to the register in the current insn,
8971 it might be loaded in a non-inherited reload. If no other
8972 reload uses it, that means the register is set before
8974 if (i2 == current_insn)
8976 for (j = n_reloads - 1; j >= 0; j--)
8977 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8978 || reload_override_in[j] == dst)
8980 for (j = n_reloads - 1; j >= 0; j--)
8981 if (rld[j].in && rld[j].reg_rtx == dst)
8990 /* If DST is still live at CURRENT_INSN, check if it is used for
8991 any reload. Note that even if CURRENT_INSN sets DST, we still
8992 have to check the reloads. */
8993 if (i2 == current_insn)
8995 for (j = n_reloads - 1; j >= 0; j--)
8996 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8997 || reload_override_in[j] == dst)
8999 /* ??? We can't finish the loop here, because dst might be
9000 allocated to a pseudo in this block if no reload in this
9001 block needs any of the classes containing DST - see
9002 spill_hard_reg. There is no easy way to tell this, so we
9003 have to scan till the end of the basic block. */
9005 if (reg_set_p (dst, PATTERN (i2)))
9009 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9010 reg_reloaded_contents[REGNO (dst)] = -1;
9014 /* Output reload-insns to reload VALUE into RELOADREG.
9015 VALUE is an autoincrement or autodecrement RTX whose operand
9016 is a register or memory location;
9017 so reloading involves incrementing that location.
9018 IN is either identical to VALUE, or some cheaper place to reload from.
9020 INC_AMOUNT is the number to increment or decrement by (always positive).
9021 This cannot be deduced from VALUE. */
9024 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9026 /* REG or MEM to be copied and incremented. */
9027 rtx incloc = find_replacement (&XEXP (value, 0));
9028 /* Nonzero if increment after copying. */
9029 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9030 || GET_CODE (value) == POST_MODIFY);
9035 rtx real_in = in == value ? incloc : in;
9037 /* No hard register is equivalent to this register after
9038 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9039 we could inc/dec that register as well (maybe even using it for
9040 the source), but I'm not sure it's worth worrying about. */
9042 reg_last_reload_reg[REGNO (incloc)] = 0;
9044 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9046 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9047 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9051 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9052 inc_amount = -inc_amount;
9054 inc = GEN_INT (inc_amount);
9057 /* If this is post-increment, first copy the location to the reload reg. */
9058 if (post && real_in != reloadreg)
9059 emit_insn (gen_move_insn (reloadreg, real_in));
9063 /* See if we can directly increment INCLOC. Use a method similar to
9064 that in gen_reload. */
9066 last = get_last_insn ();
9067 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9068 gen_rtx_PLUS (GET_MODE (incloc),
9071 code = recog_memoized (add_insn);
9074 extract_insn (add_insn);
9075 if (constrain_operands (1))
9077 /* If this is a pre-increment and we have incremented the value
9078 where it lives, copy the incremented value to RELOADREG to
9079 be used as an address. */
9082 emit_insn (gen_move_insn (reloadreg, incloc));
9086 delete_insns_since (last);
9089 /* If couldn't do the increment directly, must increment in RELOADREG.
9090 The way we do this depends on whether this is pre- or post-increment.
9091 For pre-increment, copy INCLOC to the reload register, increment it
9092 there, then save back. */
9096 if (in != reloadreg)
9097 emit_insn (gen_move_insn (reloadreg, real_in));
9098 emit_insn (gen_add2_insn (reloadreg, inc));
9099 emit_insn (gen_move_insn (incloc, reloadreg));
9104 Because this might be a jump insn or a compare, and because RELOADREG
9105 may not be available after the insn in an input reload, we must do
9106 the incrementation before the insn being reloaded for.
9108 We have already copied IN to RELOADREG. Increment the copy in
9109 RELOADREG, save that back, then decrement RELOADREG so it has
9110 the original value. */
9112 emit_insn (gen_add2_insn (reloadreg, inc));
9113 emit_insn (gen_move_insn (incloc, reloadreg));
9114 if (CONST_INT_P (inc))
9115 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9117 emit_insn (gen_sub2_insn (reloadreg, inc));
9123 add_auto_inc_notes (rtx insn, rtx x)
9125 enum rtx_code code = GET_CODE (x);
9129 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9131 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9135 /* Scan all the operand sub-expressions. */
9136 fmt = GET_RTX_FORMAT (code);
9137 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9140 add_auto_inc_notes (insn, XEXP (x, i));
9141 else if (fmt[i] == 'E')
9142 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9143 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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