1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 struct target_reload default_target_reload;
87 struct target_reload *this_target_reload = &default_target_reload;
90 #define spill_indirect_levels \
91 (this_target_reload->x_spill_indirect_levels)
93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
94 into which reg N has been reloaded (perhaps for a previous insn). */
95 static rtx *reg_last_reload_reg;
97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
98 for an output reload that stores into reg N. */
99 static regset_head reg_has_output_reload;
101 /* Indicates which hard regs are reload-registers for an output reload
102 in the current insn. */
103 static HARD_REG_SET reg_is_output_reload;
105 /* Widest width in which each pseudo reg is referred to (via subreg). */
106 static unsigned int *reg_max_ref_width;
108 /* Vector to remember old contents of reg_renumber before spilling. */
109 static short *reg_old_renumber;
111 /* During reload_as_needed, element N contains the last pseudo regno reloaded
112 into hard register N. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
117 /* During reload_as_needed, element N contains the insn for which
118 hard register N was last used. Its contents are significant only
119 when reg_reloaded_valid is set for this register. */
120 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
122 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
123 static HARD_REG_SET reg_reloaded_valid;
124 /* Indicate if the register was dead at the end of the reload.
125 This is only valid if reg_reloaded_contents is set and valid. */
126 static HARD_REG_SET reg_reloaded_dead;
128 /* Indicate whether the register's current value is one that is not
129 safe to retain across a call, even for registers that are normally
130 call-saved. This is only meaningful for members of reg_reloaded_valid. */
131 static HARD_REG_SET reg_reloaded_call_part_clobbered;
133 /* Number of spill-regs so far; number of valid elements of spill_regs. */
136 /* In parallel with spill_regs, contains REG rtx's for those regs.
137 Holds the last rtx used for any given reg, or 0 if it has never
138 been used for spilling yet. This rtx is reused, provided it has
140 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
142 /* In parallel with spill_regs, contains nonzero for a spill reg
143 that was stored after the last time it was used.
144 The precise value is the insn generated to do the store. */
145 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
147 /* This is the register that was stored with spill_reg_store. This is a
148 copy of reload_out / reload_out_reg when the value was stored; if
149 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
150 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
152 /* This table is the inverse mapping of spill_regs:
153 indexed by hard reg number,
154 it contains the position of that reg in spill_regs,
155 or -1 for something that is not in spill_regs.
157 ?!? This is no longer accurate. */
158 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
160 /* This reg set indicates registers that can't be used as spill registers for
161 the currently processed insn. These are the hard registers which are live
162 during the insn, but not allocated to pseudos, as well as fixed
164 static HARD_REG_SET bad_spill_regs;
166 /* These are the hard registers that can't be used as spill register for any
167 insn. This includes registers used for user variables and registers that
168 we can't eliminate. A register that appears in this set also can't be used
169 to retry register allocation. */
170 static HARD_REG_SET bad_spill_regs_global;
172 /* Describes order of use of registers for reloading
173 of spilled pseudo-registers. `n_spills' is the number of
174 elements that are actually valid; new ones are added at the end.
176 Both spill_regs and spill_reg_order are used on two occasions:
177 once during find_reload_regs, where they keep track of the spill registers
178 for a single insn, but also during reload_as_needed where they show all
179 the registers ever used by reload. For the latter case, the information
180 is calculated during finish_spills. */
181 static short spill_regs[FIRST_PSEUDO_REGISTER];
183 /* This vector of reg sets indicates, for each pseudo, which hard registers
184 may not be used for retrying global allocation because the register was
185 formerly spilled from one of them. If we allowed reallocating a pseudo to
186 a register that it was already allocated to, reload might not
188 static HARD_REG_SET *pseudo_previous_regs;
190 /* This vector of reg sets indicates, for each pseudo, which hard
191 registers may not be used for retrying global allocation because they
192 are used as spill registers during one of the insns in which the
194 static HARD_REG_SET *pseudo_forbidden_regs;
196 /* All hard regs that have been used as spill registers for any insn are
197 marked in this set. */
198 static HARD_REG_SET used_spill_regs;
200 /* Index of last register assigned as a spill register. We allocate in
201 a round-robin fashion. */
202 static int last_spill_reg;
204 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
207 /* Width allocated so far for that stack slot. */
208 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
210 /* Record which pseudos needed to be spilled. */
211 static regset_head spilled_pseudos;
213 /* Record which pseudos changed their allocation in finish_spills. */
214 static regset_head changed_allocation_pseudos;
216 /* Used for communication between order_regs_for_reload and count_pseudo.
217 Used to avoid counting one pseudo twice. */
218 static regset_head pseudos_counted;
220 /* First uid used by insns created by reload in this function.
221 Used in find_equiv_reg. */
222 int reload_first_uid;
224 /* Flag set by local-alloc or global-alloc if anything is live in
225 a call-clobbered reg across calls. */
226 int caller_save_needed;
228 /* Set to 1 while reload_as_needed is operating.
229 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress = 0;
232 /* This obstack is used for allocation of rtl during register elimination.
233 The allocated storage can be freed once find_reloads has processed the
235 static struct obstack reload_obstack;
237 /* Points to the beginning of the reload_obstack. All insn_chain structures
238 are allocated first. */
239 static char *reload_startobj;
241 /* The point after all insn_chain structures. Used to quickly deallocate
242 memory allocated in copy_reloads during calculate_needs_all_insns. */
243 static char *reload_firstobj;
245 /* This points before all local rtl generated by register elimination.
246 Used to quickly free all memory after processing one insn. */
247 static char *reload_insn_firstobj;
249 /* List of insn_chain instructions, one for every insn that reload needs to
251 struct insn_chain *reload_insn_chain;
253 /* List of all insns needing reloads. */
254 static struct insn_chain *insns_need_reload;
256 /* This structure is used to record information about register eliminations.
257 Each array entry describes one possible way of eliminating a register
258 in favor of another. If there is more than one way of eliminating a
259 particular register, the most preferred should be specified first. */
263 int from; /* Register number to be eliminated. */
264 int to; /* Register number used as replacement. */
265 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
266 int can_eliminate; /* Nonzero if this elimination can be done. */
267 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
268 target hook in previous scan over insns
270 HOST_WIDE_INT offset; /* Current offset between the two regs. */
271 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
272 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
273 rtx from_rtx; /* REG rtx for the register to be eliminated.
274 We cannot simply compare the number since
275 we might then spuriously replace a hard
276 register corresponding to a pseudo
277 assigned to the reg to be eliminated. */
278 rtx to_rtx; /* REG rtx for the replacement. */
281 static struct elim_table *reg_eliminate = 0;
283 /* This is an intermediate structure to initialize the table. It has
284 exactly the members provided by ELIMINABLE_REGS. */
285 static const struct elim_table_1
289 } reg_eliminate_1[] =
291 /* If a set of eliminable registers was specified, define the table from it.
292 Otherwise, default to the normal case of the frame pointer being
293 replaced by the stack pointer. */
295 #ifdef ELIMINABLE_REGS
298 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
301 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
303 /* Record the number of pending eliminations that have an offset not equal
304 to their initial offset. If nonzero, we use a new copy of each
305 replacement result in any insns encountered. */
306 int num_not_at_initial_offset;
308 /* Count the number of registers that we may be able to eliminate. */
309 static int num_eliminable;
310 /* And the number of registers that are equivalent to a constant that
311 can be eliminated to frame_pointer / arg_pointer + constant. */
312 static int num_eliminable_invariants;
314 /* For each label, we record the offset of each elimination. If we reach
315 a label by more than one path and an offset differs, we cannot do the
316 elimination. This information is indexed by the difference of the
317 number of the label and the first label number. We can't offset the
318 pointer itself as this can cause problems on machines with segmented
319 memory. The first table is an array of flags that records whether we
320 have yet encountered a label and the second table is an array of arrays,
321 one entry in the latter array for each elimination. */
323 static int first_label_num;
324 static char *offsets_known_at;
325 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
327 VEC(reg_equivs_t,gc) *reg_equivs;
329 /* Stack of addresses where an rtx has been changed. We can undo the
330 changes by popping items off the stack and restoring the original
331 value at each location.
333 We use this simplistic undo capability rather than copy_rtx as copy_rtx
334 will not make a deep copy of a normally sharable rtx, such as
335 (const (plus (symbol_ref) (const_int))). If such an expression appears
336 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
337 rtx expression would be changed. See PR 42431. */
341 DEF_VEC_ALLOC_P(rtx_p,heap);
342 static VEC(rtx_p,heap) *substitute_stack;
344 /* Number of labels in the current function. */
346 static int num_labels;
348 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
349 static void maybe_fix_stack_asms (void);
350 static void copy_reloads (struct insn_chain *);
351 static void calculate_needs_all_insns (int);
352 static int find_reg (struct insn_chain *, int);
353 static void find_reload_regs (struct insn_chain *);
354 static void select_reload_regs (void);
355 static void delete_caller_save_insns (void);
357 static void spill_failure (rtx, enum reg_class);
358 static void count_spilled_pseudo (int, int, int);
359 static void delete_dead_insn (rtx);
360 static void alter_reg (int, int, bool);
361 static void set_label_offsets (rtx, rtx, int);
362 static void check_eliminable_occurrences (rtx);
363 static void elimination_effects (rtx, enum machine_mode);
364 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
365 static int eliminate_regs_in_insn (rtx, int);
366 static void update_eliminable_offsets (void);
367 static void mark_not_eliminable (rtx, const_rtx, void *);
368 static void set_initial_elim_offsets (void);
369 static bool verify_initial_elim_offsets (void);
370 static void set_initial_label_offsets (void);
371 static void set_offsets_for_label (rtx);
372 static void init_eliminable_invariants (rtx, bool);
373 static void init_elim_table (void);
374 static void free_reg_equiv (void);
375 static void update_eliminables (HARD_REG_SET *);
376 static void elimination_costs_in_insn (rtx);
377 static void spill_hard_reg (unsigned int, int);
378 static int finish_spills (int);
379 static void scan_paradoxical_subregs (rtx);
380 static void count_pseudo (int);
381 static void order_regs_for_reload (struct insn_chain *);
382 static void reload_as_needed (int);
383 static void forget_old_reloads_1 (rtx, const_rtx, void *);
384 static void forget_marked_reloads (regset);
385 static int reload_reg_class_lower (const void *, const void *);
386 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
388 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
390 static int reload_reg_free_p (unsigned int, int, enum reload_type);
391 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
393 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
395 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
396 static int allocate_reload_reg (struct insn_chain *, int, int);
397 static int conflicts_with_override (rtx);
398 static void failed_reload (rtx, int);
399 static int set_reload_reg (int, int);
400 static void choose_reload_regs_init (struct insn_chain *, rtx *);
401 static void choose_reload_regs (struct insn_chain *);
402 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
404 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
406 static void do_input_reload (struct insn_chain *, struct reload *, int);
407 static void do_output_reload (struct insn_chain *, struct reload *, int);
408 static void emit_reload_insns (struct insn_chain *);
409 static void delete_output_reload (rtx, int, int, rtx);
410 static void delete_address_reloads (rtx, rtx);
411 static void delete_address_reloads_1 (rtx, rtx, rtx);
412 static void inc_for_reload (rtx, rtx, rtx, int);
414 static void add_auto_inc_notes (rtx, rtx);
416 static void substitute (rtx *, const_rtx, rtx);
417 static bool gen_reload_chain_without_interm_reg_p (int, int);
418 static int reloads_conflict (int, int);
419 static rtx gen_reload (rtx, rtx, int, enum reload_type);
420 static rtx emit_insn_if_valid_for_reload (rtx);
422 /* Initialize the reload pass. This is called at the beginning of compilation
423 and may be called again if the target is reinitialized. */
430 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
431 Set spill_indirect_levels to the number of levels such addressing is
432 permitted, zero if it is not permitted at all. */
435 = gen_rtx_MEM (Pmode,
438 LAST_VIRTUAL_REGISTER + 1),
440 spill_indirect_levels = 0;
442 while (memory_address_p (QImode, tem))
444 spill_indirect_levels++;
445 tem = gen_rtx_MEM (Pmode, tem);
448 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
450 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
451 indirect_symref_ok = memory_address_p (QImode, tem);
453 /* See if reg+reg is a valid (and offsettable) address. */
455 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
457 tem = gen_rtx_PLUS (Pmode,
458 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
459 gen_rtx_REG (Pmode, i));
461 /* This way, we make sure that reg+reg is an offsettable address. */
462 tem = plus_constant (tem, 4);
464 if (memory_address_p (QImode, tem))
466 double_reg_address_ok = 1;
471 /* Initialize obstack for our rtl allocation. */
472 gcc_obstack_init (&reload_obstack);
473 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
475 INIT_REG_SET (&spilled_pseudos);
476 INIT_REG_SET (&changed_allocation_pseudos);
477 INIT_REG_SET (&pseudos_counted);
480 /* List of insn chains that are currently unused. */
481 static struct insn_chain *unused_insn_chains = 0;
483 /* Allocate an empty insn_chain structure. */
485 new_insn_chain (void)
487 struct insn_chain *c;
489 if (unused_insn_chains == 0)
491 c = XOBNEW (&reload_obstack, struct insn_chain);
492 INIT_REG_SET (&c->live_throughout);
493 INIT_REG_SET (&c->dead_or_set);
497 c = unused_insn_chains;
498 unused_insn_chains = c->next;
500 c->is_caller_save_insn = 0;
501 c->need_operand_change = 0;
507 /* Small utility function to set all regs in hard reg set TO which are
508 allocated to pseudos in regset FROM. */
511 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
514 reg_set_iterator rsi;
516 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
518 int r = reg_renumber[regno];
522 /* reload_combine uses the information from DF_LIVE_IN,
523 which might still contain registers that have not
524 actually been allocated since they have an
526 gcc_assert (ira_conflicts_p || reload_completed);
529 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
533 /* Replace all pseudos found in LOC with their corresponding
537 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
550 unsigned int regno = REGNO (x);
552 if (regno < FIRST_PSEUDO_REGISTER)
555 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
559 replace_pseudos_in (loc, mem_mode, usage);
563 if (reg_equiv_constant (regno))
564 *loc = reg_equiv_constant (regno);
565 else if (reg_equiv_invariant (regno))
566 *loc = reg_equiv_invariant (regno);
567 else if (reg_equiv_mem (regno))
568 *loc = reg_equiv_mem (regno);
569 else if (reg_equiv_address (regno))
570 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
573 gcc_assert (!REG_P (regno_reg_rtx[regno])
574 || REGNO (regno_reg_rtx[regno]) != regno);
575 *loc = regno_reg_rtx[regno];
580 else if (code == MEM)
582 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
586 /* Process each of our operands recursively. */
587 fmt = GET_RTX_FORMAT (code);
588 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
590 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
591 else if (*fmt == 'E')
592 for (j = 0; j < XVECLEN (x, i); j++)
593 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
596 /* Determine if the current function has an exception receiver block
597 that reaches the exit block via non-exceptional edges */
600 has_nonexceptional_receiver (void)
604 basic_block *tos, *worklist, bb;
606 /* If we're not optimizing, then just err on the safe side. */
610 /* First determine which blocks can reach exit via normal paths. */
611 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
614 bb->flags &= ~BB_REACHABLE;
616 /* Place the exit block on our worklist. */
617 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
618 *tos++ = EXIT_BLOCK_PTR;
620 /* Iterate: find everything reachable from what we've already seen. */
621 while (tos != worklist)
625 FOR_EACH_EDGE (e, ei, bb->preds)
626 if (!(e->flags & EDGE_ABNORMAL))
628 basic_block src = e->src;
630 if (!(src->flags & BB_REACHABLE))
632 src->flags |= BB_REACHABLE;
639 /* Now see if there's a reachable block with an exceptional incoming
642 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
645 /* No exceptional block reached exit unexceptionally. */
649 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
650 zero elements) to MAX_REG_NUM elements.
652 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
654 grow_reg_equivs (void)
656 int old_size = VEC_length (reg_equivs_t, reg_equivs);
657 int max_regno = max_reg_num ();
660 VEC_reserve (reg_equivs_t, gc, reg_equivs, max_regno);
661 for (i = old_size; i < max_regno; i++)
663 VEC_quick_insert (reg_equivs_t, reg_equivs, i, 0);
664 memset (VEC_index (reg_equivs_t, reg_equivs, i), 0, sizeof (reg_equivs_t));
670 /* Global variables used by reload and its subroutines. */
672 /* The current basic block while in calculate_elim_costs_all_insns. */
673 static basic_block elim_bb;
675 /* Set during calculate_needs if an insn needs register elimination. */
676 static int something_needs_elimination;
677 /* Set during calculate_needs if an insn needs an operand changed. */
678 static int something_needs_operands_changed;
679 /* Set by alter_regs if we spilled a register to the stack. */
680 static bool something_was_spilled;
682 /* Nonzero means we couldn't get enough spill regs. */
685 /* Temporary array of pseudo-register number. */
686 static int *temp_pseudo_reg_arr;
688 /* Main entry point for the reload pass.
690 FIRST is the first insn of the function being compiled.
692 GLOBAL nonzero means we were called from global_alloc
693 and should attempt to reallocate any pseudoregs that we
694 displace from hard regs we will use for reloads.
695 If GLOBAL is zero, we do not have enough information to do that,
696 so any pseudo reg that is spilled must go to the stack.
698 Return value is nonzero if reload failed
699 and we must not do any more for this function. */
702 reload (rtx first, int global)
706 struct elim_table *ep;
710 /* Make sure even insns with volatile mem refs are recognizable. */
715 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
717 /* Make sure that the last insn in the chain
718 is not something that needs reloading. */
719 emit_note (NOTE_INSN_DELETED);
721 /* Enable find_equiv_reg to distinguish insns made by reload. */
722 reload_first_uid = get_max_uid ();
724 #ifdef SECONDARY_MEMORY_NEEDED
725 /* Initialize the secondary memory table. */
726 clear_secondary_mem ();
729 /* We don't have a stack slot for any spill reg yet. */
730 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
731 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
733 /* Initialize the save area information for caller-save, in case some
737 /* Compute which hard registers are now in use
738 as homes for pseudo registers.
739 This is done here rather than (eg) in global_alloc
740 because this point is reached even if not optimizing. */
741 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
744 /* A function that has a nonlocal label that can reach the exit
745 block via non-exceptional paths must save all call-saved
747 if (cfun->has_nonlocal_label
748 && has_nonexceptional_receiver ())
749 crtl->saves_all_registers = 1;
751 if (crtl->saves_all_registers)
752 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
753 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
754 df_set_regs_ever_live (i, true);
756 /* Find all the pseudo registers that didn't get hard regs
757 but do have known equivalent constants or memory slots.
758 These include parameters (known equivalent to parameter slots)
759 and cse'd or loop-moved constant memory addresses.
761 Record constant equivalents in reg_equiv_constant
762 so they will be substituted by find_reloads.
763 Record memory equivalents in reg_mem_equiv so they can
764 be substituted eventually by altering the REG-rtx's. */
767 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
768 reg_old_renumber = XCNEWVEC (short, max_regno);
769 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
770 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
771 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
773 CLEAR_HARD_REG_SET (bad_spill_regs_global);
775 init_eliminable_invariants (first, true);
778 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
779 stack slots to the pseudos that lack hard regs or equivalents.
780 Do not touch virtual registers. */
782 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
783 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
784 temp_pseudo_reg_arr[n++] = i;
787 /* Ask IRA to order pseudo-registers for better stack slot
789 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
791 for (i = 0; i < n; i++)
792 alter_reg (temp_pseudo_reg_arr[i], -1, false);
794 /* If we have some registers we think can be eliminated, scan all insns to
795 see if there is an insn that sets one of these registers to something
796 other than itself plus a constant. If so, the register cannot be
797 eliminated. Doing this scan here eliminates an extra pass through the
798 main reload loop in the most common case where register elimination
800 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
802 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
804 maybe_fix_stack_asms ();
806 insns_need_reload = 0;
807 something_needs_elimination = 0;
809 /* Initialize to -1, which means take the first spill register. */
812 /* Spill any hard regs that we know we can't eliminate. */
813 CLEAR_HARD_REG_SET (used_spill_regs);
814 /* There can be multiple ways to eliminate a register;
815 they should be listed adjacently.
816 Elimination for any register fails only if all possible ways fail. */
817 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
820 int can_eliminate = 0;
823 can_eliminate |= ep->can_eliminate;
826 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
828 spill_hard_reg (from, 1);
831 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
832 if (frame_pointer_needed)
833 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
835 finish_spills (global);
837 /* From now on, we may need to generate moves differently. We may also
838 allow modifications of insns which cause them to not be recognized.
839 Any such modifications will be cleaned up during reload itself. */
840 reload_in_progress = 1;
842 /* This loop scans the entire function each go-round
843 and repeats until one repetition spills no additional hard regs. */
846 int something_changed;
848 HOST_WIDE_INT starting_frame_size;
850 starting_frame_size = get_frame_size ();
851 something_was_spilled = false;
853 set_initial_elim_offsets ();
854 set_initial_label_offsets ();
856 /* For each pseudo register that has an equivalent location defined,
857 try to eliminate any eliminable registers (such as the frame pointer)
858 assuming initial offsets for the replacement register, which
861 If the resulting location is directly addressable, substitute
862 the MEM we just got directly for the old REG.
864 If it is not addressable but is a constant or the sum of a hard reg
865 and constant, it is probably not addressable because the constant is
866 out of range, in that case record the address; we will generate
867 hairy code to compute the address in a register each time it is
868 needed. Similarly if it is a hard register, but one that is not
869 valid as an address register.
871 If the location is not addressable, but does not have one of the
872 above forms, assign a stack slot. We have to do this to avoid the
873 potential of producing lots of reloads if, e.g., a location involves
874 a pseudo that didn't get a hard register and has an equivalent memory
875 location that also involves a pseudo that didn't get a hard register.
877 Perhaps at some point we will improve reload_when_needed handling
878 so this problem goes away. But that's very hairy. */
880 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
881 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
883 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
886 if (strict_memory_address_addr_space_p
887 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
889 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
890 else if (CONSTANT_P (XEXP (x, 0))
891 || (REG_P (XEXP (x, 0))
892 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
893 || (GET_CODE (XEXP (x, 0)) == PLUS
894 && REG_P (XEXP (XEXP (x, 0), 0))
895 && (REGNO (XEXP (XEXP (x, 0), 0))
896 < FIRST_PSEUDO_REGISTER)
897 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
898 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
901 /* Make a new stack slot. Then indicate that something
902 changed so we go back and recompute offsets for
903 eliminable registers because the allocation of memory
904 below might change some offset. reg_equiv_{mem,address}
905 will be set up for this pseudo on the next pass around
907 reg_equiv_memory_loc (i) = 0;
908 reg_equiv_init (i) = 0;
909 alter_reg (i, -1, true);
913 if (caller_save_needed)
916 /* If we allocated another stack slot, redo elimination bookkeeping. */
917 if (something_was_spilled || starting_frame_size != get_frame_size ())
919 if (starting_frame_size && crtl->stack_alignment_needed)
921 /* If we have a stack frame, we must align it now. The
922 stack size may be a part of the offset computation for
923 register elimination. So if this changes the stack size,
924 then repeat the elimination bookkeeping. We don't
925 realign when there is no stack, as that will cause a
926 stack frame when none is needed should
927 STARTING_FRAME_OFFSET not be already aligned to
929 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
930 if (starting_frame_size != get_frame_size ())
934 if (caller_save_needed)
936 save_call_clobbered_regs ();
937 /* That might have allocated new insn_chain structures. */
938 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
941 calculate_needs_all_insns (global);
943 if (! ira_conflicts_p)
944 /* Don't do it for IRA. We need this info because we don't
945 change live_throughout and dead_or_set for chains when IRA
947 CLEAR_REG_SET (&spilled_pseudos);
951 something_changed = 0;
953 /* If we allocated any new memory locations, make another pass
954 since it might have changed elimination offsets. */
955 if (something_was_spilled || starting_frame_size != get_frame_size ())
956 something_changed = 1;
958 /* Even if the frame size remained the same, we might still have
959 changed elimination offsets, e.g. if find_reloads called
960 force_const_mem requiring the back end to allocate a constant
961 pool base register that needs to be saved on the stack. */
962 else if (!verify_initial_elim_offsets ())
963 something_changed = 1;
966 HARD_REG_SET to_spill;
967 CLEAR_HARD_REG_SET (to_spill);
968 update_eliminables (&to_spill);
969 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
971 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
972 if (TEST_HARD_REG_BIT (to_spill, i))
974 spill_hard_reg (i, 1);
977 /* Regardless of the state of spills, if we previously had
978 a register that we thought we could eliminate, but now can
979 not eliminate, we must run another pass.
981 Consider pseudos which have an entry in reg_equiv_* which
982 reference an eliminable register. We must make another pass
983 to update reg_equiv_* so that we do not substitute in the
984 old value from when we thought the elimination could be
986 something_changed = 1;
990 select_reload_regs ();
994 if (insns_need_reload != 0 || did_spill)
995 something_changed |= finish_spills (global);
997 if (! something_changed)
1000 if (caller_save_needed)
1001 delete_caller_save_insns ();
1003 obstack_free (&reload_obstack, reload_firstobj);
1006 /* If global-alloc was run, notify it of any register eliminations we have
1009 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1010 if (ep->can_eliminate)
1011 mark_elimination (ep->from, ep->to);
1013 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1014 If that insn didn't set the register (i.e., it copied the register to
1015 memory), just delete that insn instead of the equivalencing insn plus
1016 anything now dead. If we call delete_dead_insn on that insn, we may
1017 delete the insn that actually sets the register if the register dies
1018 there and that is incorrect. */
1020 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1022 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
1025 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
1027 rtx equiv_insn = XEXP (list, 0);
1029 /* If we already deleted the insn or if it may trap, we can't
1030 delete it. The latter case shouldn't happen, but can
1031 if an insn has a variable address, gets a REG_EH_REGION
1032 note added to it, and then gets converted into a load
1033 from a constant address. */
1034 if (NOTE_P (equiv_insn)
1035 || can_throw_internal (equiv_insn))
1037 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1038 delete_dead_insn (equiv_insn);
1040 SET_INSN_DELETED (equiv_insn);
1045 /* Use the reload registers where necessary
1046 by generating move instructions to move the must-be-register
1047 values into or out of the reload registers. */
1049 if (insns_need_reload != 0 || something_needs_elimination
1050 || something_needs_operands_changed)
1052 HOST_WIDE_INT old_frame_size = get_frame_size ();
1054 reload_as_needed (global);
1056 gcc_assert (old_frame_size == get_frame_size ());
1058 gcc_assert (verify_initial_elim_offsets ());
1061 /* If we were able to eliminate the frame pointer, show that it is no
1062 longer live at the start of any basic block. If it ls live by
1063 virtue of being in a pseudo, that pseudo will be marked live
1064 and hence the frame pointer will be known to be live via that
1067 if (! frame_pointer_needed)
1069 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1071 /* Come here (with failure set nonzero) if we can't get enough spill
1075 CLEAR_REG_SET (&changed_allocation_pseudos);
1076 CLEAR_REG_SET (&spilled_pseudos);
1077 reload_in_progress = 0;
1079 /* Now eliminate all pseudo regs by modifying them into
1080 their equivalent memory references.
1081 The REG-rtx's for the pseudos are modified in place,
1082 so all insns that used to refer to them now refer to memory.
1084 For a reg that has a reg_equiv_address, all those insns
1085 were changed by reloading so that no insns refer to it any longer;
1086 but the DECL_RTL of a variable decl may refer to it,
1087 and if so this causes the debugging info to mention the variable. */
1089 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1093 if (reg_equiv_mem (i))
1094 addr = XEXP (reg_equiv_mem (i), 0);
1096 if (reg_equiv_address (i))
1097 addr = reg_equiv_address (i);
1101 if (reg_renumber[i] < 0)
1103 rtx reg = regno_reg_rtx[i];
1105 REG_USERVAR_P (reg) = 0;
1106 PUT_CODE (reg, MEM);
1107 XEXP (reg, 0) = addr;
1108 if (reg_equiv_memory_loc (i))
1109 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1112 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1113 MEM_ATTRS (reg) = 0;
1115 MEM_NOTRAP_P (reg) = 1;
1117 else if (reg_equiv_mem (i))
1118 XEXP (reg_equiv_mem (i), 0) = addr;
1121 /* We don't want complex addressing modes in debug insns
1122 if simpler ones will do, so delegitimize equivalences
1124 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1126 rtx reg = regno_reg_rtx[i];
1130 if (reg_equiv_constant (i))
1131 equiv = reg_equiv_constant (i);
1132 else if (reg_equiv_invariant (i))
1133 equiv = reg_equiv_invariant (i);
1134 else if (reg && MEM_P (reg))
1135 equiv = targetm.delegitimize_address (reg);
1136 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1142 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1144 insn = DF_REF_INSN (use);
1146 /* Make sure the next ref is for a different instruction,
1147 so that we're not affected by the rescan. */
1148 next = DF_REF_NEXT_REG (use);
1149 while (next && DF_REF_INSN (next) == insn)
1150 next = DF_REF_NEXT_REG (next);
1152 if (DEBUG_INSN_P (insn))
1156 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1157 df_insn_rescan_debug_internal (insn);
1160 INSN_VAR_LOCATION_LOC (insn)
1161 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1168 /* We must set reload_completed now since the cleanup_subreg_operands call
1169 below will re-recognize each insn and reload may have generated insns
1170 which are only valid during and after reload. */
1171 reload_completed = 1;
1173 /* Make a pass over all the insns and delete all USEs which we inserted
1174 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1175 notes. Delete all CLOBBER insns, except those that refer to the return
1176 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1177 from misarranging variable-array code, and simplify (subreg (reg))
1178 operands. Strip and regenerate REG_INC notes that may have been moved
1181 for (insn = first; insn; insn = NEXT_INSN (insn))
1187 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1188 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1190 if ((GET_CODE (PATTERN (insn)) == USE
1191 /* We mark with QImode USEs introduced by reload itself. */
1192 && (GET_MODE (insn) == QImode
1193 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1194 || (GET_CODE (PATTERN (insn)) == CLOBBER
1195 && (!MEM_P (XEXP (PATTERN (insn), 0))
1196 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1197 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1198 && XEXP (XEXP (PATTERN (insn), 0), 0)
1199 != stack_pointer_rtx))
1200 && (!REG_P (XEXP (PATTERN (insn), 0))
1201 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1207 /* Some CLOBBERs may survive until here and still reference unassigned
1208 pseudos with const equivalent, which may in turn cause ICE in later
1209 passes if the reference remains in place. */
1210 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1211 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1212 VOIDmode, PATTERN (insn));
1214 /* Discard obvious no-ops, even without -O. This optimization
1215 is fast and doesn't interfere with debugging. */
1216 if (NONJUMP_INSN_P (insn)
1217 && GET_CODE (PATTERN (insn)) == SET
1218 && REG_P (SET_SRC (PATTERN (insn)))
1219 && REG_P (SET_DEST (PATTERN (insn)))
1220 && (REGNO (SET_SRC (PATTERN (insn)))
1221 == REGNO (SET_DEST (PATTERN (insn)))))
1227 pnote = ®_NOTES (insn);
1230 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1231 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1232 || REG_NOTE_KIND (*pnote) == REG_INC)
1233 *pnote = XEXP (*pnote, 1);
1235 pnote = &XEXP (*pnote, 1);
1239 add_auto_inc_notes (insn, PATTERN (insn));
1242 /* Simplify (subreg (reg)) if it appears as an operand. */
1243 cleanup_subreg_operands (insn);
1245 /* Clean up invalid ASMs so that they don't confuse later passes.
1247 if (asm_noperands (PATTERN (insn)) >= 0)
1249 extract_insn (insn);
1250 if (!constrain_operands (1))
1252 error_for_asm (insn,
1253 "%<asm%> operand has impossible constraints");
1260 /* If we are doing generic stack checking, give a warning if this
1261 function's frame size is larger than we expect. */
1262 if (flag_stack_check == GENERIC_STACK_CHECK)
1264 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1265 static int verbose_warned = 0;
1267 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1268 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1269 size += UNITS_PER_WORD;
1271 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1273 warning (0, "frame size too large for reliable stack checking");
1274 if (! verbose_warned)
1276 warning (0, "try reducing the number of local variables");
1282 free (temp_pseudo_reg_arr);
1284 /* Indicate that we no longer have known memory locations or constants. */
1287 free (reg_max_ref_width);
1288 free (reg_old_renumber);
1289 free (pseudo_previous_regs);
1290 free (pseudo_forbidden_regs);
1292 CLEAR_HARD_REG_SET (used_spill_regs);
1293 for (i = 0; i < n_spills; i++)
1294 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1296 /* Free all the insn_chain structures at once. */
1297 obstack_free (&reload_obstack, reload_startobj);
1298 unused_insn_chains = 0;
1300 inserted = fixup_abnormal_edges ();
1302 /* We've possibly turned single trapping insn into multiple ones. */
1303 if (cfun->can_throw_non_call_exceptions)
1306 blocks = sbitmap_alloc (last_basic_block);
1307 sbitmap_ones (blocks);
1308 find_many_sub_basic_blocks (blocks);
1309 sbitmap_free (blocks);
1313 commit_edge_insertions ();
1315 /* Replacing pseudos with their memory equivalents might have
1316 created shared rtx. Subsequent passes would get confused
1317 by this, so unshare everything here. */
1318 unshare_all_rtl_again (first);
1320 #ifdef STACK_BOUNDARY
1321 /* init_emit has set the alignment of the hard frame pointer
1322 to STACK_BOUNDARY. It is very likely no longer valid if
1323 the hard frame pointer was used for register allocation. */
1324 if (!frame_pointer_needed)
1325 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1328 VEC_free (rtx_p, heap, substitute_stack);
1330 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1335 /* Yet another special case. Unfortunately, reg-stack forces people to
1336 write incorrect clobbers in asm statements. These clobbers must not
1337 cause the register to appear in bad_spill_regs, otherwise we'll call
1338 fatal_insn later. We clear the corresponding regnos in the live
1339 register sets to avoid this.
1340 The whole thing is rather sick, I'm afraid. */
1343 maybe_fix_stack_asms (void)
1346 const char *constraints[MAX_RECOG_OPERANDS];
1347 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1348 struct insn_chain *chain;
1350 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1353 HARD_REG_SET clobbered, allowed;
1356 if (! INSN_P (chain->insn)
1357 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1359 pat = PATTERN (chain->insn);
1360 if (GET_CODE (pat) != PARALLEL)
1363 CLEAR_HARD_REG_SET (clobbered);
1364 CLEAR_HARD_REG_SET (allowed);
1366 /* First, make a mask of all stack regs that are clobbered. */
1367 for (i = 0; i < XVECLEN (pat, 0); i++)
1369 rtx t = XVECEXP (pat, 0, i);
1370 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1371 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1374 /* Get the operand values and constraints out of the insn. */
1375 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1376 constraints, operand_mode, NULL);
1378 /* For every operand, see what registers are allowed. */
1379 for (i = 0; i < noperands; i++)
1381 const char *p = constraints[i];
1382 /* For every alternative, we compute the class of registers allowed
1383 for reloading in CLS, and merge its contents into the reg set
1385 int cls = (int) NO_REGS;
1391 if (c == '\0' || c == ',' || c == '#')
1393 /* End of one alternative - mark the regs in the current
1394 class, and reset the class. */
1395 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1401 } while (c != '\0' && c != ',');
1409 case '=': case '+': case '*': case '%': case '?': case '!':
1410 case '0': case '1': case '2': case '3': case '4': case '<':
1411 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1412 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1413 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1414 case TARGET_MEM_CONSTRAINT:
1418 cls = (int) reg_class_subunion[cls]
1419 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1424 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1428 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1429 cls = (int) reg_class_subunion[cls]
1430 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1432 cls = (int) reg_class_subunion[cls]
1433 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1435 p += CONSTRAINT_LEN (c, p);
1438 /* Those of the registers which are clobbered, but allowed by the
1439 constraints, must be usable as reload registers. So clear them
1440 out of the life information. */
1441 AND_HARD_REG_SET (allowed, clobbered);
1442 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1443 if (TEST_HARD_REG_BIT (allowed, i))
1445 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1446 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1453 /* Copy the global variables n_reloads and rld into the corresponding elts
1456 copy_reloads (struct insn_chain *chain)
1458 chain->n_reloads = n_reloads;
1459 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1460 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1461 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1464 /* Walk the chain of insns, and determine for each whether it needs reloads
1465 and/or eliminations. Build the corresponding insns_need_reload list, and
1466 set something_needs_elimination as appropriate. */
1468 calculate_needs_all_insns (int global)
1470 struct insn_chain **pprev_reload = &insns_need_reload;
1471 struct insn_chain *chain, *next = 0;
1473 something_needs_elimination = 0;
1475 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1476 for (chain = reload_insn_chain; chain != 0; chain = next)
1478 rtx insn = chain->insn;
1482 /* Clear out the shortcuts. */
1483 chain->n_reloads = 0;
1484 chain->need_elim = 0;
1485 chain->need_reload = 0;
1486 chain->need_operand_change = 0;
1488 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1489 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1490 what effects this has on the known offsets at labels. */
1492 if (LABEL_P (insn) || JUMP_P (insn)
1493 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1494 set_label_offsets (insn, insn, 0);
1498 rtx old_body = PATTERN (insn);
1499 int old_code = INSN_CODE (insn);
1500 rtx old_notes = REG_NOTES (insn);
1501 int did_elimination = 0;
1502 int operands_changed = 0;
1503 rtx set = single_set (insn);
1505 /* Skip insns that only set an equivalence. */
1506 if (set && REG_P (SET_DEST (set))
1507 && reg_renumber[REGNO (SET_DEST (set))] < 0
1508 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1509 || (reg_equiv_invariant (REGNO (SET_DEST (set)))))
1510 && reg_equiv_init (REGNO (SET_DEST (set))))
1513 /* If needed, eliminate any eliminable registers. */
1514 if (num_eliminable || num_eliminable_invariants)
1515 did_elimination = eliminate_regs_in_insn (insn, 0);
1517 /* Analyze the instruction. */
1518 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1519 global, spill_reg_order);
1521 /* If a no-op set needs more than one reload, this is likely
1522 to be something that needs input address reloads. We
1523 can't get rid of this cleanly later, and it is of no use
1524 anyway, so discard it now.
1525 We only do this when expensive_optimizations is enabled,
1526 since this complements reload inheritance / output
1527 reload deletion, and it can make debugging harder. */
1528 if (flag_expensive_optimizations && n_reloads > 1)
1530 rtx set = single_set (insn);
1533 ((SET_SRC (set) == SET_DEST (set)
1534 && REG_P (SET_SRC (set))
1535 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1536 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1537 && reg_renumber[REGNO (SET_SRC (set))] < 0
1538 && reg_renumber[REGNO (SET_DEST (set))] < 0
1539 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1540 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1541 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1542 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1544 if (ira_conflicts_p)
1545 /* Inform IRA about the insn deletion. */
1546 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1547 REGNO (SET_SRC (set)));
1549 /* Delete it from the reload chain. */
1551 chain->prev->next = next;
1553 reload_insn_chain = next;
1555 next->prev = chain->prev;
1556 chain->next = unused_insn_chains;
1557 unused_insn_chains = chain;
1562 update_eliminable_offsets ();
1564 /* Remember for later shortcuts which insns had any reloads or
1565 register eliminations. */
1566 chain->need_elim = did_elimination;
1567 chain->need_reload = n_reloads > 0;
1568 chain->need_operand_change = operands_changed;
1570 /* Discard any register replacements done. */
1571 if (did_elimination)
1573 obstack_free (&reload_obstack, reload_insn_firstobj);
1574 PATTERN (insn) = old_body;
1575 INSN_CODE (insn) = old_code;
1576 REG_NOTES (insn) = old_notes;
1577 something_needs_elimination = 1;
1580 something_needs_operands_changed |= operands_changed;
1584 copy_reloads (chain);
1585 *pprev_reload = chain;
1586 pprev_reload = &chain->next_need_reload;
1593 /* This function is called from the register allocator to set up estimates
1594 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1595 an invariant. The structure is similar to calculate_needs_all_insns. */
1598 calculate_elim_costs_all_insns (void)
1600 int *reg_equiv_init_cost;
1604 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1606 init_eliminable_invariants (get_insns (), false);
1608 set_initial_elim_offsets ();
1609 set_initial_label_offsets ();
1616 FOR_BB_INSNS (bb, insn)
1618 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1619 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1620 what effects this has on the known offsets at labels. */
1622 if (LABEL_P (insn) || JUMP_P (insn)
1623 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1624 set_label_offsets (insn, insn, 0);
1628 rtx set = single_set (insn);
1630 /* Skip insns that only set an equivalence. */
1631 if (set && REG_P (SET_DEST (set))
1632 && reg_renumber[REGNO (SET_DEST (set))] < 0
1633 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1634 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1636 unsigned regno = REGNO (SET_DEST (set));
1637 rtx init = reg_equiv_init (regno);
1640 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1642 int cost = rtx_cost (t, SET,
1643 optimize_bb_for_speed_p (bb));
1644 int freq = REG_FREQ_FROM_BB (bb);
1646 reg_equiv_init_cost[regno] = cost * freq;
1650 /* If needed, eliminate any eliminable registers. */
1651 if (num_eliminable || num_eliminable_invariants)
1652 elimination_costs_in_insn (insn);
1655 update_eliminable_offsets ();
1659 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1661 if (reg_equiv_invariant (i))
1663 if (reg_equiv_init (i))
1665 int cost = reg_equiv_init_cost[i];
1668 "Reg %d has equivalence, initial gains %d\n", i, cost);
1670 ira_adjust_equiv_reg_cost (i, cost);
1676 "Reg %d had equivalence, but can't be eliminated\n",
1678 ira_adjust_equiv_reg_cost (i, 0);
1683 free (reg_equiv_init_cost);
1686 /* Comparison function for qsort to decide which of two reloads
1687 should be handled first. *P1 and *P2 are the reload numbers. */
1690 reload_reg_class_lower (const void *r1p, const void *r2p)
1692 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1695 /* Consider required reloads before optional ones. */
1696 t = rld[r1].optional - rld[r2].optional;
1700 /* Count all solitary classes before non-solitary ones. */
1701 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1702 - (reg_class_size[(int) rld[r1].rclass] == 1));
1706 /* Aside from solitaires, consider all multi-reg groups first. */
1707 t = rld[r2].nregs - rld[r1].nregs;
1711 /* Consider reloads in order of increasing reg-class number. */
1712 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1716 /* If reloads are equally urgent, sort by reload number,
1717 so that the results of qsort leave nothing to chance. */
1721 /* The cost of spilling each hard reg. */
1722 static int spill_cost[FIRST_PSEUDO_REGISTER];
1724 /* When spilling multiple hard registers, we use SPILL_COST for the first
1725 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1726 only the first hard reg for a multi-reg pseudo. */
1727 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1729 /* Map of hard regno to pseudo regno currently occupying the hard
1731 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1733 /* Update the spill cost arrays, considering that pseudo REG is live. */
1736 count_pseudo (int reg)
1738 int freq = REG_FREQ (reg);
1739 int r = reg_renumber[reg];
1742 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1743 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1744 /* Ignore spilled pseudo-registers which can be here only if IRA
1746 || (ira_conflicts_p && r < 0))
1749 SET_REGNO_REG_SET (&pseudos_counted, reg);
1751 gcc_assert (r >= 0);
1753 spill_add_cost[r] += freq;
1754 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1757 hard_regno_to_pseudo_regno[r + nregs] = reg;
1758 spill_cost[r + nregs] += freq;
1762 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1763 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1766 order_regs_for_reload (struct insn_chain *chain)
1769 HARD_REG_SET used_by_pseudos;
1770 HARD_REG_SET used_by_pseudos2;
1771 reg_set_iterator rsi;
1773 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1775 memset (spill_cost, 0, sizeof spill_cost);
1776 memset (spill_add_cost, 0, sizeof spill_add_cost);
1777 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1778 hard_regno_to_pseudo_regno[i] = -1;
1780 /* Count number of uses of each hard reg by pseudo regs allocated to it
1781 and then order them by decreasing use. First exclude hard registers
1782 that are live in or across this insn. */
1784 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1785 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1786 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1787 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1789 /* Now find out which pseudos are allocated to it, and update
1791 CLEAR_REG_SET (&pseudos_counted);
1793 EXECUTE_IF_SET_IN_REG_SET
1794 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1798 EXECUTE_IF_SET_IN_REG_SET
1799 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1803 CLEAR_REG_SET (&pseudos_counted);
1806 /* Vector of reload-numbers showing the order in which the reloads should
1808 static short reload_order[MAX_RELOADS];
1810 /* This is used to keep track of the spill regs used in one insn. */
1811 static HARD_REG_SET used_spill_regs_local;
1813 /* We decided to spill hard register SPILLED, which has a size of
1814 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1815 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1816 update SPILL_COST/SPILL_ADD_COST. */
1819 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1821 int freq = REG_FREQ (reg);
1822 int r = reg_renumber[reg];
1823 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1825 /* Ignore spilled pseudo-registers which can be here only if IRA is
1827 if ((ira_conflicts_p && r < 0)
1828 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1829 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1832 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1834 spill_add_cost[r] -= freq;
1837 hard_regno_to_pseudo_regno[r + nregs] = -1;
1838 spill_cost[r + nregs] -= freq;
1842 /* Find reload register to use for reload number ORDER. */
1845 find_reg (struct insn_chain *chain, int order)
1847 int rnum = reload_order[order];
1848 struct reload *rl = rld + rnum;
1849 int best_cost = INT_MAX;
1851 unsigned int i, j, n;
1853 HARD_REG_SET not_usable;
1854 HARD_REG_SET used_by_other_reload;
1855 reg_set_iterator rsi;
1856 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1857 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1859 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1860 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1861 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1863 CLEAR_HARD_REG_SET (used_by_other_reload);
1864 for (k = 0; k < order; k++)
1866 int other = reload_order[k];
1868 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1869 for (j = 0; j < rld[other].nregs; j++)
1870 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1873 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1875 #ifdef REG_ALLOC_ORDER
1876 unsigned int regno = reg_alloc_order[i];
1878 unsigned int regno = i;
1881 if (! TEST_HARD_REG_BIT (not_usable, regno)
1882 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1883 && HARD_REGNO_MODE_OK (regno, rl->mode))
1885 int this_cost = spill_cost[regno];
1887 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1889 for (j = 1; j < this_nregs; j++)
1891 this_cost += spill_add_cost[regno + j];
1892 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1893 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1899 if (ira_conflicts_p)
1901 /* Ask IRA to find a better pseudo-register for
1903 for (n = j = 0; j < this_nregs; j++)
1905 int r = hard_regno_to_pseudo_regno[regno + j];
1909 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1910 regno_pseudo_regs[n++] = r;
1912 regno_pseudo_regs[n++] = -1;
1914 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1915 best_regno_pseudo_regs,
1922 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1923 if (regno_pseudo_regs[j] < 0)
1930 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1932 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1934 if (this_cost < best_cost
1935 /* Among registers with equal cost, prefer caller-saved ones, or
1936 use REG_ALLOC_ORDER if it is defined. */
1937 || (this_cost == best_cost
1938 #ifdef REG_ALLOC_ORDER
1939 && (inv_reg_alloc_order[regno]
1940 < inv_reg_alloc_order[best_reg])
1942 && call_used_regs[regno]
1943 && ! call_used_regs[best_reg]
1948 best_cost = this_cost;
1956 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1958 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1959 rl->regno = best_reg;
1961 EXECUTE_IF_SET_IN_REG_SET
1962 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1964 count_spilled_pseudo (best_reg, rl->nregs, j);
1967 EXECUTE_IF_SET_IN_REG_SET
1968 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1970 count_spilled_pseudo (best_reg, rl->nregs, j);
1973 for (i = 0; i < rl->nregs; i++)
1975 gcc_assert (spill_cost[best_reg + i] == 0);
1976 gcc_assert (spill_add_cost[best_reg + i] == 0);
1977 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1978 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1983 /* Find more reload regs to satisfy the remaining need of an insn, which
1985 Do it by ascending class number, since otherwise a reg
1986 might be spilled for a big class and might fail to count
1987 for a smaller class even though it belongs to that class. */
1990 find_reload_regs (struct insn_chain *chain)
1994 /* In order to be certain of getting the registers we need,
1995 we must sort the reloads into order of increasing register class.
1996 Then our grabbing of reload registers will parallel the process
1997 that provided the reload registers. */
1998 for (i = 0; i < chain->n_reloads; i++)
2000 /* Show whether this reload already has a hard reg. */
2001 if (chain->rld[i].reg_rtx)
2003 int regno = REGNO (chain->rld[i].reg_rtx);
2004 chain->rld[i].regno = regno;
2006 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2009 chain->rld[i].regno = -1;
2010 reload_order[i] = i;
2013 n_reloads = chain->n_reloads;
2014 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2016 CLEAR_HARD_REG_SET (used_spill_regs_local);
2019 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2021 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2023 /* Compute the order of preference for hard registers to spill. */
2025 order_regs_for_reload (chain);
2027 for (i = 0; i < n_reloads; i++)
2029 int r = reload_order[i];
2031 /* Ignore reloads that got marked inoperative. */
2032 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2033 && ! rld[r].optional
2034 && rld[r].regno == -1)
2035 if (! find_reg (chain, i))
2038 fprintf (dump_file, "reload failure for reload %d\n", r);
2039 spill_failure (chain->insn, rld[r].rclass);
2045 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2046 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2048 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2052 select_reload_regs (void)
2054 struct insn_chain *chain;
2056 /* Try to satisfy the needs for each insn. */
2057 for (chain = insns_need_reload; chain != 0;
2058 chain = chain->next_need_reload)
2059 find_reload_regs (chain);
2062 /* Delete all insns that were inserted by emit_caller_save_insns during
2065 delete_caller_save_insns (void)
2067 struct insn_chain *c = reload_insn_chain;
2071 while (c != 0 && c->is_caller_save_insn)
2073 struct insn_chain *next = c->next;
2076 if (c == reload_insn_chain)
2077 reload_insn_chain = next;
2081 next->prev = c->prev;
2083 c->prev->next = next;
2084 c->next = unused_insn_chains;
2085 unused_insn_chains = c;
2093 /* Handle the failure to find a register to spill.
2094 INSN should be one of the insns which needed this particular spill reg. */
2097 spill_failure (rtx insn, enum reg_class rclass)
2099 if (asm_noperands (PATTERN (insn)) >= 0)
2100 error_for_asm (insn, "can%'t find a register in class %qs while "
2101 "reloading %<asm%>",
2102 reg_class_names[rclass]);
2105 error ("unable to find a register to spill in class %qs",
2106 reg_class_names[rclass]);
2110 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2111 debug_reload_to_stream (dump_file);
2113 fatal_insn ("this is the insn:", insn);
2117 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2118 data that is dead in INSN. */
2121 delete_dead_insn (rtx insn)
2123 rtx prev = prev_active_insn (insn);
2126 /* If the previous insn sets a register that dies in our insn, delete it
2128 if (prev && GET_CODE (PATTERN (prev)) == SET
2129 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2130 && reg_mentioned_p (prev_dest, PATTERN (insn))
2131 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2132 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2133 delete_dead_insn (prev);
2135 SET_INSN_DELETED (insn);
2138 /* Modify the home of pseudo-reg I.
2139 The new home is present in reg_renumber[I].
2141 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2142 or it may be -1, meaning there is none or it is not relevant.
2143 This is used so that all pseudos spilled from a given hard reg
2144 can share one stack slot. */
2147 alter_reg (int i, int from_reg, bool dont_share_p)
2149 /* When outputting an inline function, this can happen
2150 for a reg that isn't actually used. */
2151 if (regno_reg_rtx[i] == 0)
2154 /* If the reg got changed to a MEM at rtl-generation time,
2156 if (!REG_P (regno_reg_rtx[i]))
2159 /* Modify the reg-rtx to contain the new hard reg
2160 number or else to contain its pseudo reg number. */
2161 SET_REGNO (regno_reg_rtx[i],
2162 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2164 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2165 allocate a stack slot for it. */
2167 if (reg_renumber[i] < 0
2168 && REG_N_REFS (i) > 0
2169 && reg_equiv_constant (i) == 0
2170 && (reg_equiv_invariant (i) == 0
2171 || reg_equiv_init (i) == 0)
2172 && reg_equiv_memory_loc (i) == 0)
2175 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2176 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2177 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2178 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2179 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2182 something_was_spilled = true;
2184 if (ira_conflicts_p)
2186 /* Mark the spill for IRA. */
2187 SET_REGNO_REG_SET (&spilled_pseudos, i);
2189 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2195 /* Each pseudo reg has an inherent size which comes from its own mode,
2196 and a total size which provides room for paradoxical subregs
2197 which refer to the pseudo reg in wider modes.
2199 We can use a slot already allocated if it provides both
2200 enough inherent space and enough total space.
2201 Otherwise, we allocate a new slot, making sure that it has no less
2202 inherent space, and no less total space, then the previous slot. */
2203 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2207 /* No known place to spill from => no slot to reuse. */
2208 x = assign_stack_local (mode, total_size,
2209 min_align > inherent_align
2210 || total_size > inherent_size ? -1 : 0);
2214 /* Cancel the big-endian correction done in assign_stack_local.
2215 Get the address of the beginning of the slot. This is so we
2216 can do a big-endian correction unconditionally below. */
2217 if (BYTES_BIG_ENDIAN)
2219 adjust = inherent_size - total_size;
2222 = adjust_address_nv (x, mode_for_size (total_size
2228 if (! dont_share_p && ira_conflicts_p)
2229 /* Inform IRA about allocation a new stack slot. */
2230 ira_mark_new_stack_slot (stack_slot, i, total_size);
2233 /* Reuse a stack slot if possible. */
2234 else if (spill_stack_slot[from_reg] != 0
2235 && spill_stack_slot_width[from_reg] >= total_size
2236 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2238 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2239 x = spill_stack_slot[from_reg];
2241 /* Allocate a bigger slot. */
2244 /* Compute maximum size needed, both for inherent size
2245 and for total size. */
2248 if (spill_stack_slot[from_reg])
2250 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2252 mode = GET_MODE (spill_stack_slot[from_reg]);
2253 if (spill_stack_slot_width[from_reg] > total_size)
2254 total_size = spill_stack_slot_width[from_reg];
2255 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2256 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2259 /* Make a slot with that size. */
2260 x = assign_stack_local (mode, total_size,
2261 min_align > inherent_align
2262 || total_size > inherent_size ? -1 : 0);
2265 /* Cancel the big-endian correction done in assign_stack_local.
2266 Get the address of the beginning of the slot. This is so we
2267 can do a big-endian correction unconditionally below. */
2268 if (BYTES_BIG_ENDIAN)
2270 adjust = GET_MODE_SIZE (mode) - total_size;
2273 = adjust_address_nv (x, mode_for_size (total_size
2279 spill_stack_slot[from_reg] = stack_slot;
2280 spill_stack_slot_width[from_reg] = total_size;
2283 /* On a big endian machine, the "address" of the slot
2284 is the address of the low part that fits its inherent mode. */
2285 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2286 adjust += (total_size - inherent_size);
2288 /* If we have any adjustment to make, or if the stack slot is the
2289 wrong mode, make a new stack slot. */
2290 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2292 /* Set all of the memory attributes as appropriate for a spill. */
2293 set_mem_attrs_for_spill (x);
2295 /* Save the stack slot for later. */
2296 reg_equiv_memory_loc (i) = x;
2300 /* Mark the slots in regs_ever_live for the hard regs used by
2301 pseudo-reg number REGNO, accessed in MODE. */
2304 mark_home_live_1 (int regno, enum machine_mode mode)
2308 i = reg_renumber[regno];
2311 lim = end_hard_regno (mode, i);
2313 df_set_regs_ever_live(i++, true);
2316 /* Mark the slots in regs_ever_live for the hard regs
2317 used by pseudo-reg number REGNO. */
2320 mark_home_live (int regno)
2322 if (reg_renumber[regno] >= 0)
2323 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2326 /* This function handles the tracking of elimination offsets around branches.
2328 X is a piece of RTL being scanned.
2330 INSN is the insn that it came from, if any.
2332 INITIAL_P is nonzero if we are to set the offset to be the initial
2333 offset and zero if we are setting the offset of the label to be the
2337 set_label_offsets (rtx x, rtx insn, int initial_p)
2339 enum rtx_code code = GET_CODE (x);
2342 struct elim_table *p;
2347 if (LABEL_REF_NONLOCAL_P (x))
2352 /* ... fall through ... */
2355 /* If we know nothing about this label, set the desired offsets. Note
2356 that this sets the offset at a label to be the offset before a label
2357 if we don't know anything about the label. This is not correct for
2358 the label after a BARRIER, but is the best guess we can make. If
2359 we guessed wrong, we will suppress an elimination that might have
2360 been possible had we been able to guess correctly. */
2362 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2364 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2365 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2366 = (initial_p ? reg_eliminate[i].initial_offset
2367 : reg_eliminate[i].offset);
2368 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2371 /* Otherwise, if this is the definition of a label and it is
2372 preceded by a BARRIER, set our offsets to the known offset of
2376 && (tem = prev_nonnote_insn (insn)) != 0
2378 set_offsets_for_label (insn);
2380 /* If neither of the above cases is true, compare each offset
2381 with those previously recorded and suppress any eliminations
2382 where the offsets disagree. */
2384 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2385 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2386 != (initial_p ? reg_eliminate[i].initial_offset
2387 : reg_eliminate[i].offset))
2388 reg_eliminate[i].can_eliminate = 0;
2393 set_label_offsets (PATTERN (insn), insn, initial_p);
2395 /* ... fall through ... */
2399 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2400 to indirectly and hence must have all eliminations at their
2402 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2403 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2404 set_label_offsets (XEXP (tem, 0), insn, 1);
2410 /* Each of the labels in the parallel or address vector must be
2411 at their initial offsets. We want the first field for PARALLEL
2412 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2414 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2415 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2420 /* We only care about setting PC. If the source is not RETURN,
2421 IF_THEN_ELSE, or a label, disable any eliminations not at
2422 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2423 isn't one of those possibilities. For branches to a label,
2424 call ourselves recursively.
2426 Note that this can disable elimination unnecessarily when we have
2427 a non-local goto since it will look like a non-constant jump to
2428 someplace in the current function. This isn't a significant
2429 problem since such jumps will normally be when all elimination
2430 pairs are back to their initial offsets. */
2432 if (SET_DEST (x) != pc_rtx)
2435 switch (GET_CODE (SET_SRC (x)))
2442 set_label_offsets (SET_SRC (x), insn, initial_p);
2446 tem = XEXP (SET_SRC (x), 1);
2447 if (GET_CODE (tem) == LABEL_REF)
2448 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2449 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2452 tem = XEXP (SET_SRC (x), 2);
2453 if (GET_CODE (tem) == LABEL_REF)
2454 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2455 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2463 /* If we reach here, all eliminations must be at their initial
2464 offset because we are doing a jump to a variable address. */
2465 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2466 if (p->offset != p->initial_offset)
2467 p->can_eliminate = 0;
2475 /* Called through for_each_rtx, this function examines every reg that occurs
2476 in PX and adjusts the costs for its elimination which are gathered by IRA.
2477 DATA is the insn in which PX occurs. We do not recurse into MEM
2481 note_reg_elim_costly (rtx *px, void *data)
2483 rtx insn = (rtx)data;
2490 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2491 && reg_equiv_init (REGNO (x))
2492 && reg_equiv_invariant (REGNO (x)))
2494 rtx t = reg_equiv_invariant (REGNO (x));
2495 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2496 int cost = rtx_cost (new_rtx, SET, optimize_bb_for_speed_p (elim_bb));
2497 int freq = REG_FREQ_FROM_BB (elim_bb);
2500 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2505 /* Scan X and replace any eliminable registers (such as fp) with a
2506 replacement (such as sp), plus an offset.
2508 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2509 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2510 MEM, we are allowed to replace a sum of a register and the constant zero
2511 with the register, which we cannot do outside a MEM. In addition, we need
2512 to record the fact that a register is referenced outside a MEM.
2514 If INSN is an insn, it is the insn containing X. If we replace a REG
2515 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2516 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2517 the REG is being modified.
2519 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2520 That's used when we eliminate in expressions stored in notes.
2521 This means, do not set ref_outside_mem even if the reference
2524 If FOR_COSTS is true, we are being called before reload in order to
2525 estimate the costs of keeping registers with an equivalence unallocated.
2527 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2528 replacements done assuming all offsets are at their initial values. If
2529 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2530 encounter, return the actual location so that find_reloads will do
2531 the proper thing. */
2534 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2535 bool may_use_invariant, bool for_costs)
2537 enum rtx_code code = GET_CODE (x);
2538 struct elim_table *ep;
2545 if (! current_function_decl)
2568 /* First handle the case where we encounter a bare register that
2569 is eliminable. Replace it with a PLUS. */
2570 if (regno < FIRST_PSEUDO_REGISTER)
2572 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2574 if (ep->from_rtx == x && ep->can_eliminate)
2575 return plus_constant (ep->to_rtx, ep->previous_offset);
2578 else if (reg_renumber && reg_renumber[regno] < 0
2580 && reg_equiv_invariant (regno))
2582 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2583 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2584 mem_mode, insn, true, for_costs);
2585 /* There exists at least one use of REGNO that cannot be
2586 eliminated. Prevent the defining insn from being deleted. */
2587 reg_equiv_init (regno) = NULL_RTX;
2589 alter_reg (regno, -1, true);
2593 /* You might think handling MINUS in a manner similar to PLUS is a
2594 good idea. It is not. It has been tried multiple times and every
2595 time the change has had to have been reverted.
2597 Other parts of reload know a PLUS is special (gen_reload for example)
2598 and require special code to handle code a reloaded PLUS operand.
2600 Also consider backends where the flags register is clobbered by a
2601 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2602 lea instruction comes to mind). If we try to reload a MINUS, we
2603 may kill the flags register that was holding a useful value.
2605 So, please before trying to handle MINUS, consider reload as a
2606 whole instead of this little section as well as the backend issues. */
2608 /* If this is the sum of an eliminable register and a constant, rework
2610 if (REG_P (XEXP (x, 0))
2611 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2612 && CONSTANT_P (XEXP (x, 1)))
2614 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2616 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2618 /* The only time we want to replace a PLUS with a REG (this
2619 occurs when the constant operand of the PLUS is the negative
2620 of the offset) is when we are inside a MEM. We won't want
2621 to do so at other times because that would change the
2622 structure of the insn in a way that reload can't handle.
2623 We special-case the commonest situation in
2624 eliminate_regs_in_insn, so just replace a PLUS with a
2625 PLUS here, unless inside a MEM. */
2626 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2627 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2630 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2631 plus_constant (XEXP (x, 1),
2632 ep->previous_offset));
2635 /* If the register is not eliminable, we are done since the other
2636 operand is a constant. */
2640 /* If this is part of an address, we want to bring any constant to the
2641 outermost PLUS. We will do this by doing register replacement in
2642 our operands and seeing if a constant shows up in one of them.
2644 Note that there is no risk of modifying the structure of the insn,
2645 since we only get called for its operands, thus we are either
2646 modifying the address inside a MEM, or something like an address
2647 operand of a load-address insn. */
2650 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2652 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2655 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2657 /* If one side is a PLUS and the other side is a pseudo that
2658 didn't get a hard register but has a reg_equiv_constant,
2659 we must replace the constant here since it may no longer
2660 be in the position of any operand. */
2661 if (GET_CODE (new0) == PLUS && REG_P (new1)
2662 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2663 && reg_renumber[REGNO (new1)] < 0
2665 && reg_equiv_constant (REGNO (new1)) != 0)
2666 new1 = reg_equiv_constant (REGNO (new1));
2667 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2668 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2669 && reg_renumber[REGNO (new0)] < 0
2670 && reg_equiv_constant (REGNO (new0)) != 0)
2671 new0 = reg_equiv_constant (REGNO (new0));
2673 new_rtx = form_sum (GET_MODE (x), new0, new1);
2675 /* As above, if we are not inside a MEM we do not want to
2676 turn a PLUS into something else. We might try to do so here
2677 for an addition of 0 if we aren't optimizing. */
2678 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2679 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2687 /* If this is the product of an eliminable register and a
2688 constant, apply the distribute law and move the constant out
2689 so that we have (plus (mult ..) ..). This is needed in order
2690 to keep load-address insns valid. This case is pathological.
2691 We ignore the possibility of overflow here. */
2692 if (REG_P (XEXP (x, 0))
2693 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2694 && CONST_INT_P (XEXP (x, 1)))
2695 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2697 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2700 /* Refs inside notes or in DEBUG_INSNs don't count for
2702 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2703 || GET_CODE (insn) == INSN_LIST
2704 || DEBUG_INSN_P (insn))))
2705 ep->ref_outside_mem = 1;
2708 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2709 ep->previous_offset * INTVAL (XEXP (x, 1)));
2712 /* ... fall through ... */
2716 /* See comments before PLUS about handling MINUS. */
2718 case DIV: case UDIV:
2719 case MOD: case UMOD:
2720 case AND: case IOR: case XOR:
2721 case ROTATERT: case ROTATE:
2722 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2724 case GE: case GT: case GEU: case GTU:
2725 case LE: case LT: case LEU: case LTU:
2727 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2729 rtx new1 = XEXP (x, 1)
2730 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2733 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2734 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2739 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2742 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2744 if (new_rtx != XEXP (x, 0))
2746 /* If this is a REG_DEAD note, it is not valid anymore.
2747 Using the eliminated version could result in creating a
2748 REG_DEAD note for the stack or frame pointer. */
2749 if (REG_NOTE_KIND (x) == REG_DEAD)
2751 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2755 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2759 /* ... fall through ... */
2762 /* Now do eliminations in the rest of the chain. If this was
2763 an EXPR_LIST, this might result in allocating more memory than is
2764 strictly needed, but it simplifies the code. */
2767 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2769 if (new_rtx != XEXP (x, 1))
2771 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2779 /* We do not support elimination of a register that is modified.
2780 elimination_effects has already make sure that this does not
2786 /* We do not support elimination of a register that is modified.
2787 elimination_effects has already make sure that this does not
2788 happen. The only remaining case we need to consider here is
2789 that the increment value may be an eliminable register. */
2790 if (GET_CODE (XEXP (x, 1)) == PLUS
2791 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2793 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2794 insn, true, for_costs);
2796 if (new_rtx != XEXP (XEXP (x, 1), 1))
2797 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2798 gen_rtx_PLUS (GET_MODE (x),
2799 XEXP (x, 0), new_rtx));
2803 case STRICT_LOW_PART:
2805 case SIGN_EXTEND: case ZERO_EXTEND:
2806 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2807 case FLOAT: case FIX:
2808 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2817 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2819 if (new_rtx != XEXP (x, 0))
2820 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2824 /* Similar to above processing, but preserve SUBREG_BYTE.
2825 Convert (subreg (mem)) to (mem) if not paradoxical.
2826 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2827 pseudo didn't get a hard reg, we must replace this with the
2828 eliminated version of the memory location because push_reload
2829 may do the replacement in certain circumstances. */
2830 if (REG_P (SUBREG_REG (x))
2831 && (GET_MODE_SIZE (GET_MODE (x))
2832 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2834 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2836 new_rtx = SUBREG_REG (x);
2839 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2841 if (new_rtx != SUBREG_REG (x))
2843 int x_size = GET_MODE_SIZE (GET_MODE (x));
2844 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2847 && ((x_size < new_size
2848 #ifdef WORD_REGISTER_OPERATIONS
2849 /* On these machines, combine can create rtl of the form
2850 (set (subreg:m1 (reg:m2 R) 0) ...)
2851 where m1 < m2, and expects something interesting to
2852 happen to the entire word. Moreover, it will use the
2853 (reg:m2 R) later, expecting all bits to be preserved.
2854 So if the number of words is the same, preserve the
2855 subreg so that push_reload can see it. */
2856 && ! ((x_size - 1) / UNITS_PER_WORD
2857 == (new_size -1 ) / UNITS_PER_WORD)
2860 || x_size == new_size)
2862 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2864 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2870 /* Our only special processing is to pass the mode of the MEM to our
2871 recursive call and copy the flags. While we are here, handle this
2872 case more efficiently. */
2874 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2877 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2878 && !memory_address_p (GET_MODE (x), new_rtx))
2879 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2881 return replace_equiv_address_nv (x, new_rtx);
2884 /* Handle insn_list USE that a call to a pure function may generate. */
2885 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2887 if (new_rtx != XEXP (x, 0))
2888 return gen_rtx_USE (GET_MODE (x), new_rtx);
2893 gcc_assert (insn && DEBUG_INSN_P (insn));
2903 /* Process each of our operands recursively. If any have changed, make a
2905 fmt = GET_RTX_FORMAT (code);
2906 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2910 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2912 if (new_rtx != XEXP (x, i) && ! copied)
2914 x = shallow_copy_rtx (x);
2917 XEXP (x, i) = new_rtx;
2919 else if (*fmt == 'E')
2922 for (j = 0; j < XVECLEN (x, i); j++)
2924 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2926 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2928 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2932 x = shallow_copy_rtx (x);
2935 XVEC (x, i) = new_v;
2938 XVECEXP (x, i, j) = new_rtx;
2947 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2949 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2952 /* Scan rtx X for modifications of elimination target registers. Update
2953 the table of eliminables to reflect the changed state. MEM_MODE is
2954 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2957 elimination_effects (rtx x, enum machine_mode mem_mode)
2959 enum rtx_code code = GET_CODE (x);
2960 struct elim_table *ep;
2985 /* First handle the case where we encounter a bare register that
2986 is eliminable. Replace it with a PLUS. */
2987 if (regno < FIRST_PSEUDO_REGISTER)
2989 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2991 if (ep->from_rtx == x && ep->can_eliminate)
2994 ep->ref_outside_mem = 1;
2999 else if (reg_renumber[regno] < 0
3001 && reg_equiv_constant (regno)
3002 && ! function_invariant_p (reg_equiv_constant (regno)))
3003 elimination_effects (reg_equiv_constant (regno), mem_mode);
3012 /* If we modify the source of an elimination rule, disable it. */
3013 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3014 if (ep->from_rtx == XEXP (x, 0))
3015 ep->can_eliminate = 0;
3017 /* If we modify the target of an elimination rule by adding a constant,
3018 update its offset. If we modify the target in any other way, we'll
3019 have to disable the rule as well. */
3020 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3021 if (ep->to_rtx == XEXP (x, 0))
3023 int size = GET_MODE_SIZE (mem_mode);
3025 /* If more bytes than MEM_MODE are pushed, account for them. */
3026 #ifdef PUSH_ROUNDING
3027 if (ep->to_rtx == stack_pointer_rtx)
3028 size = PUSH_ROUNDING (size);
3030 if (code == PRE_DEC || code == POST_DEC)
3032 else if (code == PRE_INC || code == POST_INC)
3034 else if (code == PRE_MODIFY || code == POST_MODIFY)
3036 if (GET_CODE (XEXP (x, 1)) == PLUS
3037 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3038 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3039 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3041 ep->can_eliminate = 0;
3045 /* These two aren't unary operators. */
3046 if (code == POST_MODIFY || code == PRE_MODIFY)
3049 /* Fall through to generic unary operation case. */
3050 case STRICT_LOW_PART:
3052 case SIGN_EXTEND: case ZERO_EXTEND:
3053 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3054 case FLOAT: case FIX:
3055 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3064 elimination_effects (XEXP (x, 0), mem_mode);
3068 if (REG_P (SUBREG_REG (x))
3069 && (GET_MODE_SIZE (GET_MODE (x))
3070 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3072 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3075 elimination_effects (SUBREG_REG (x), mem_mode);
3079 /* If using a register that is the source of an eliminate we still
3080 think can be performed, note it cannot be performed since we don't
3081 know how this register is used. */
3082 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3083 if (ep->from_rtx == XEXP (x, 0))
3084 ep->can_eliminate = 0;
3086 elimination_effects (XEXP (x, 0), mem_mode);
3090 /* If clobbering a register that is the replacement register for an
3091 elimination we still think can be performed, note that it cannot
3092 be performed. Otherwise, we need not be concerned about it. */
3093 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3094 if (ep->to_rtx == XEXP (x, 0))
3095 ep->can_eliminate = 0;
3097 elimination_effects (XEXP (x, 0), mem_mode);
3101 /* Check for setting a register that we know about. */
3102 if (REG_P (SET_DEST (x)))
3104 /* See if this is setting the replacement register for an
3107 If DEST is the hard frame pointer, we do nothing because we
3108 assume that all assignments to the frame pointer are for
3109 non-local gotos and are being done at a time when they are valid
3110 and do not disturb anything else. Some machines want to
3111 eliminate a fake argument pointer (or even a fake frame pointer)
3112 with either the real frame or the stack pointer. Assignments to
3113 the hard frame pointer must not prevent this elimination. */
3115 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3117 if (ep->to_rtx == SET_DEST (x)
3118 && SET_DEST (x) != hard_frame_pointer_rtx)
3120 /* If it is being incremented, adjust the offset. Otherwise,
3121 this elimination can't be done. */
3122 rtx src = SET_SRC (x);
3124 if (GET_CODE (src) == PLUS
3125 && XEXP (src, 0) == SET_DEST (x)
3126 && CONST_INT_P (XEXP (src, 1)))
3127 ep->offset -= INTVAL (XEXP (src, 1));
3129 ep->can_eliminate = 0;
3133 elimination_effects (SET_DEST (x), VOIDmode);
3134 elimination_effects (SET_SRC (x), VOIDmode);
3138 /* Our only special processing is to pass the mode of the MEM to our
3140 elimination_effects (XEXP (x, 0), GET_MODE (x));
3147 fmt = GET_RTX_FORMAT (code);
3148 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3151 elimination_effects (XEXP (x, i), mem_mode);
3152 else if (*fmt == 'E')
3153 for (j = 0; j < XVECLEN (x, i); j++)
3154 elimination_effects (XVECEXP (x, i, j), mem_mode);
3158 /* Descend through rtx X and verify that no references to eliminable registers
3159 remain. If any do remain, mark the involved register as not
3163 check_eliminable_occurrences (rtx x)
3172 code = GET_CODE (x);
3174 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3176 struct elim_table *ep;
3178 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3179 if (ep->from_rtx == x)
3180 ep->can_eliminate = 0;
3184 fmt = GET_RTX_FORMAT (code);
3185 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3188 check_eliminable_occurrences (XEXP (x, i));
3189 else if (*fmt == 'E')
3192 for (j = 0; j < XVECLEN (x, i); j++)
3193 check_eliminable_occurrences (XVECEXP (x, i, j));
3198 /* Scan INSN and eliminate all eliminable registers in it.
3200 If REPLACE is nonzero, do the replacement destructively. Also
3201 delete the insn as dead it if it is setting an eliminable register.
3203 If REPLACE is zero, do all our allocations in reload_obstack.
3205 If no eliminations were done and this insn doesn't require any elimination
3206 processing (these are not identical conditions: it might be updating sp,
3207 but not referencing fp; this needs to be seen during reload_as_needed so
3208 that the offset between fp and sp can be taken into consideration), zero
3209 is returned. Otherwise, 1 is returned. */
3212 eliminate_regs_in_insn (rtx insn, int replace)
3214 int icode = recog_memoized (insn);
3215 rtx old_body = PATTERN (insn);
3216 int insn_is_asm = asm_noperands (old_body) >= 0;
3217 rtx old_set = single_set (insn);
3221 rtx substed_operand[MAX_RECOG_OPERANDS];
3222 rtx orig_operand[MAX_RECOG_OPERANDS];
3223 struct elim_table *ep;
3224 rtx plus_src, plus_cst_src;
3226 if (! insn_is_asm && icode < 0)
3228 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3229 || GET_CODE (PATTERN (insn)) == CLOBBER
3230 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3231 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3232 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3233 || DEBUG_INSN_P (insn));
3234 if (DEBUG_INSN_P (insn))
3235 INSN_VAR_LOCATION_LOC (insn)
3236 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3240 if (old_set != 0 && REG_P (SET_DEST (old_set))
3241 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3243 /* Check for setting an eliminable register. */
3244 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3245 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3247 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3248 /* If this is setting the frame pointer register to the
3249 hardware frame pointer register and this is an elimination
3250 that will be done (tested above), this insn is really
3251 adjusting the frame pointer downward to compensate for
3252 the adjustment done before a nonlocal goto. */
3253 if (ep->from == FRAME_POINTER_REGNUM
3254 && ep->to == HARD_FRAME_POINTER_REGNUM)
3256 rtx base = SET_SRC (old_set);
3257 rtx base_insn = insn;
3258 HOST_WIDE_INT offset = 0;
3260 while (base != ep->to_rtx)
3262 rtx prev_insn, prev_set;
3264 if (GET_CODE (base) == PLUS
3265 && CONST_INT_P (XEXP (base, 1)))
3267 offset += INTVAL (XEXP (base, 1));
3268 base = XEXP (base, 0);
3270 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3271 && (prev_set = single_set (prev_insn)) != 0
3272 && rtx_equal_p (SET_DEST (prev_set), base))
3274 base = SET_SRC (prev_set);
3275 base_insn = prev_insn;
3281 if (base == ep->to_rtx)
3284 = plus_constant (ep->to_rtx, offset - ep->offset);
3286 new_body = old_body;
3289 new_body = copy_insn (old_body);
3290 if (REG_NOTES (insn))
3291 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3293 PATTERN (insn) = new_body;
3294 old_set = single_set (insn);
3296 /* First see if this insn remains valid when we
3297 make the change. If not, keep the INSN_CODE
3298 the same and let reload fit it up. */
3299 validate_change (insn, &SET_SRC (old_set), src, 1);
3300 validate_change (insn, &SET_DEST (old_set),
3302 if (! apply_change_group ())
3304 SET_SRC (old_set) = src;
3305 SET_DEST (old_set) = ep->to_rtx;
3314 /* In this case this insn isn't serving a useful purpose. We
3315 will delete it in reload_as_needed once we know that this
3316 elimination is, in fact, being done.
3318 If REPLACE isn't set, we can't delete this insn, but needn't
3319 process it since it won't be used unless something changes. */
3322 delete_dead_insn (insn);
3330 /* We allow one special case which happens to work on all machines we
3331 currently support: a single set with the source or a REG_EQUAL
3332 note being a PLUS of an eliminable register and a constant. */
3333 plus_src = plus_cst_src = 0;
3334 if (old_set && REG_P (SET_DEST (old_set)))
3336 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3337 plus_src = SET_SRC (old_set);
3338 /* First see if the source is of the form (plus (...) CST). */
3340 && CONST_INT_P (XEXP (plus_src, 1)))
3341 plus_cst_src = plus_src;
3342 else if (REG_P (SET_SRC (old_set))
3345 /* Otherwise, see if we have a REG_EQUAL note of the form
3346 (plus (...) CST). */
3348 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3350 if ((REG_NOTE_KIND (links) == REG_EQUAL
3351 || REG_NOTE_KIND (links) == REG_EQUIV)
3352 && GET_CODE (XEXP (links, 0)) == PLUS
3353 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3355 plus_cst_src = XEXP (links, 0);
3361 /* Check that the first operand of the PLUS is a hard reg or
3362 the lowpart subreg of one. */
3365 rtx reg = XEXP (plus_cst_src, 0);
3366 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3367 reg = SUBREG_REG (reg);
3369 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3375 rtx reg = XEXP (plus_cst_src, 0);
3376 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3378 if (GET_CODE (reg) == SUBREG)
3379 reg = SUBREG_REG (reg);
3381 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3382 if (ep->from_rtx == reg && ep->can_eliminate)
3384 rtx to_rtx = ep->to_rtx;
3385 offset += ep->offset;
3386 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3388 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3389 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3391 /* If we have a nonzero offset, and the source is already
3392 a simple REG, the following transformation would
3393 increase the cost of the insn by replacing a simple REG
3394 with (plus (reg sp) CST). So try only when we already
3395 had a PLUS before. */
3396 if (offset == 0 || plus_src)
3398 rtx new_src = plus_constant (to_rtx, offset);
3400 new_body = old_body;
3403 new_body = copy_insn (old_body);
3404 if (REG_NOTES (insn))
3405 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3407 PATTERN (insn) = new_body;
3408 old_set = single_set (insn);
3410 /* First see if this insn remains valid when we make the
3411 change. If not, try to replace the whole pattern with
3412 a simple set (this may help if the original insn was a
3413 PARALLEL that was only recognized as single_set due to
3414 REG_UNUSED notes). If this isn't valid either, keep
3415 the INSN_CODE the same and let reload fix it up. */
3416 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3418 rtx new_pat = gen_rtx_SET (VOIDmode,
3419 SET_DEST (old_set), new_src);
3421 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3422 SET_SRC (old_set) = new_src;
3429 /* This can't have an effect on elimination offsets, so skip right
3435 /* Determine the effects of this insn on elimination offsets. */
3436 elimination_effects (old_body, VOIDmode);
3438 /* Eliminate all eliminable registers occurring in operands that
3439 can be handled by reload. */
3440 extract_insn (insn);
3441 for (i = 0; i < recog_data.n_operands; i++)
3443 orig_operand[i] = recog_data.operand[i];
3444 substed_operand[i] = recog_data.operand[i];
3446 /* For an asm statement, every operand is eliminable. */
3447 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3449 bool is_set_src, in_plus;
3451 /* Check for setting a register that we know about. */
3452 if (recog_data.operand_type[i] != OP_IN
3453 && REG_P (orig_operand[i]))
3455 /* If we are assigning to a register that can be eliminated, it
3456 must be as part of a PARALLEL, since the code above handles
3457 single SETs. We must indicate that we can no longer
3458 eliminate this reg. */
3459 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3461 if (ep->from_rtx == orig_operand[i])
3462 ep->can_eliminate = 0;
3465 /* Companion to the above plus substitution, we can allow
3466 invariants as the source of a plain move. */
3469 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3473 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3474 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3478 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3479 replace ? insn : NULL_RTX,
3480 is_set_src || in_plus, false);
3481 if (substed_operand[i] != orig_operand[i])
3483 /* Terminate the search in check_eliminable_occurrences at
3485 *recog_data.operand_loc[i] = 0;
3487 /* If an output operand changed from a REG to a MEM and INSN is an
3488 insn, write a CLOBBER insn. */
3489 if (recog_data.operand_type[i] != OP_IN
3490 && REG_P (orig_operand[i])
3491 && MEM_P (substed_operand[i])
3493 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3497 for (i = 0; i < recog_data.n_dups; i++)
3498 *recog_data.dup_loc[i]
3499 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3501 /* If any eliminable remain, they aren't eliminable anymore. */
3502 check_eliminable_occurrences (old_body);
3504 /* Substitute the operands; the new values are in the substed_operand
3506 for (i = 0; i < recog_data.n_operands; i++)
3507 *recog_data.operand_loc[i] = substed_operand[i];
3508 for (i = 0; i < recog_data.n_dups; i++)
3509 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3511 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3512 re-recognize the insn. We do this in case we had a simple addition
3513 but now can do this as a load-address. This saves an insn in this
3515 If re-recognition fails, the old insn code number will still be used,
3516 and some register operands may have changed into PLUS expressions.
3517 These will be handled by find_reloads by loading them into a register
3522 /* If we aren't replacing things permanently and we changed something,
3523 make another copy to ensure that all the RTL is new. Otherwise
3524 things can go wrong if find_reload swaps commutative operands
3525 and one is inside RTL that has been copied while the other is not. */
3526 new_body = old_body;
3529 new_body = copy_insn (old_body);
3530 if (REG_NOTES (insn))
3531 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3533 PATTERN (insn) = new_body;
3535 /* If we had a move insn but now we don't, rerecognize it. This will
3536 cause spurious re-recognition if the old move had a PARALLEL since
3537 the new one still will, but we can't call single_set without
3538 having put NEW_BODY into the insn and the re-recognition won't
3539 hurt in this rare case. */
3540 /* ??? Why this huge if statement - why don't we just rerecognize the
3544 && ((REG_P (SET_SRC (old_set))
3545 && (GET_CODE (new_body) != SET
3546 || !REG_P (SET_SRC (new_body))))
3547 /* If this was a load from or store to memory, compare
3548 the MEM in recog_data.operand to the one in the insn.
3549 If they are not equal, then rerecognize the insn. */
3551 && ((MEM_P (SET_SRC (old_set))
3552 && SET_SRC (old_set) != recog_data.operand[1])
3553 || (MEM_P (SET_DEST (old_set))
3554 && SET_DEST (old_set) != recog_data.operand[0])))
3555 /* If this was an add insn before, rerecognize. */
3556 || GET_CODE (SET_SRC (old_set)) == PLUS))
3558 int new_icode = recog (PATTERN (insn), insn, 0);
3560 INSN_CODE (insn) = new_icode;
3564 /* Restore the old body. If there were any changes to it, we made a copy
3565 of it while the changes were still in place, so we'll correctly return
3566 a modified insn below. */
3569 /* Restore the old body. */
3570 for (i = 0; i < recog_data.n_operands; i++)
3571 /* Restoring a top-level match_parallel would clobber the new_body
3572 we installed in the insn. */
3573 if (recog_data.operand_loc[i] != &PATTERN (insn))
3574 *recog_data.operand_loc[i] = orig_operand[i];
3575 for (i = 0; i < recog_data.n_dups; i++)
3576 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3579 /* Update all elimination pairs to reflect the status after the current
3580 insn. The changes we make were determined by the earlier call to
3581 elimination_effects.
3583 We also detect cases where register elimination cannot be done,
3584 namely, if a register would be both changed and referenced outside a MEM
3585 in the resulting insn since such an insn is often undefined and, even if
3586 not, we cannot know what meaning will be given to it. Note that it is
3587 valid to have a register used in an address in an insn that changes it
3588 (presumably with a pre- or post-increment or decrement).
3590 If anything changes, return nonzero. */
3592 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3594 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3595 ep->can_eliminate = 0;
3597 ep->ref_outside_mem = 0;
3599 if (ep->previous_offset != ep->offset)
3604 /* If we changed something, perform elimination in REG_NOTES. This is
3605 needed even when REPLACE is zero because a REG_DEAD note might refer
3606 to a register that we eliminate and could cause a different number
3607 of spill registers to be needed in the final reload pass than in
3609 if (val && REG_NOTES (insn) != 0)
3611 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3617 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3618 register allocator. INSN is the instruction we need to examine, we perform
3619 eliminations in its operands and record cases where eliminating a reg with
3620 an invariant equivalence would add extra cost. */
3623 elimination_costs_in_insn (rtx insn)
3625 int icode = recog_memoized (insn);
3626 rtx old_body = PATTERN (insn);
3627 int insn_is_asm = asm_noperands (old_body) >= 0;
3628 rtx old_set = single_set (insn);
3630 rtx orig_operand[MAX_RECOG_OPERANDS];
3631 rtx orig_dup[MAX_RECOG_OPERANDS];
3632 struct elim_table *ep;
3633 rtx plus_src, plus_cst_src;
3636 if (! insn_is_asm && icode < 0)
3638 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3639 || GET_CODE (PATTERN (insn)) == CLOBBER
3640 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3641 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3642 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3643 || DEBUG_INSN_P (insn));
3647 if (old_set != 0 && REG_P (SET_DEST (old_set))
3648 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3650 /* Check for setting an eliminable register. */
3651 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3652 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3656 /* We allow one special case which happens to work on all machines we
3657 currently support: a single set with the source or a REG_EQUAL
3658 note being a PLUS of an eliminable register and a constant. */
3659 plus_src = plus_cst_src = 0;
3661 if (old_set && REG_P (SET_DEST (old_set)))
3664 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3665 plus_src = SET_SRC (old_set);
3666 /* First see if the source is of the form (plus (...) CST). */
3668 && CONST_INT_P (XEXP (plus_src, 1)))
3669 plus_cst_src = plus_src;
3670 else if (REG_P (SET_SRC (old_set))
3673 /* Otherwise, see if we have a REG_EQUAL note of the form
3674 (plus (...) CST). */
3676 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3678 if ((REG_NOTE_KIND (links) == REG_EQUAL
3679 || REG_NOTE_KIND (links) == REG_EQUIV)
3680 && GET_CODE (XEXP (links, 0)) == PLUS
3681 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3683 plus_cst_src = XEXP (links, 0);
3690 /* Determine the effects of this insn on elimination offsets. */
3691 elimination_effects (old_body, VOIDmode);
3693 /* Eliminate all eliminable registers occurring in operands that
3694 can be handled by reload. */
3695 extract_insn (insn);
3696 for (i = 0; i < recog_data.n_dups; i++)
3697 orig_dup[i] = *recog_data.dup_loc[i];
3699 for (i = 0; i < recog_data.n_operands; i++)
3701 orig_operand[i] = recog_data.operand[i];
3703 /* For an asm statement, every operand is eliminable. */
3704 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3706 bool is_set_src, in_plus;
3708 /* Check for setting a register that we know about. */
3709 if (recog_data.operand_type[i] != OP_IN
3710 && REG_P (orig_operand[i]))
3712 /* If we are assigning to a register that can be eliminated, it
3713 must be as part of a PARALLEL, since the code above handles
3714 single SETs. We must indicate that we can no longer
3715 eliminate this reg. */
3716 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3718 if (ep->from_rtx == orig_operand[i])
3719 ep->can_eliminate = 0;
3722 /* Companion to the above plus substitution, we can allow
3723 invariants as the source of a plain move. */
3725 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3727 if (is_set_src && !sets_reg_p)
3728 note_reg_elim_costly (&SET_SRC (old_set), insn);
3730 if (plus_src && sets_reg_p
3731 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3732 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3735 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3737 is_set_src || in_plus, true);
3738 /* Terminate the search in check_eliminable_occurrences at
3740 *recog_data.operand_loc[i] = 0;
3744 for (i = 0; i < recog_data.n_dups; i++)
3745 *recog_data.dup_loc[i]
3746 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3748 /* If any eliminable remain, they aren't eliminable anymore. */
3749 check_eliminable_occurrences (old_body);
3751 /* Restore the old body. */
3752 for (i = 0; i < recog_data.n_operands; i++)
3753 *recog_data.operand_loc[i] = orig_operand[i];
3754 for (i = 0; i < recog_data.n_dups; i++)
3755 *recog_data.dup_loc[i] = orig_dup[i];
3757 /* Update all elimination pairs to reflect the status after the current
3758 insn. The changes we make were determined by the earlier call to
3759 elimination_effects. */
3761 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3763 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3764 ep->can_eliminate = 0;
3766 ep->ref_outside_mem = 0;
3772 /* Loop through all elimination pairs.
3773 Recalculate the number not at initial offset.
3775 Compute the maximum offset (minimum offset if the stack does not
3776 grow downward) for each elimination pair. */
3779 update_eliminable_offsets (void)
3781 struct elim_table *ep;
3783 num_not_at_initial_offset = 0;
3784 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3786 ep->previous_offset = ep->offset;
3787 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3788 num_not_at_initial_offset++;
3792 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3793 replacement we currently believe is valid, mark it as not eliminable if X
3794 modifies DEST in any way other than by adding a constant integer to it.
3796 If DEST is the frame pointer, we do nothing because we assume that
3797 all assignments to the hard frame pointer are nonlocal gotos and are being
3798 done at a time when they are valid and do not disturb anything else.
3799 Some machines want to eliminate a fake argument pointer with either the
3800 frame or stack pointer. Assignments to the hard frame pointer must not
3801 prevent this elimination.
3803 Called via note_stores from reload before starting its passes to scan
3804 the insns of the function. */
3807 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3811 /* A SUBREG of a hard register here is just changing its mode. We should
3812 not see a SUBREG of an eliminable hard register, but check just in
3814 if (GET_CODE (dest) == SUBREG)
3815 dest = SUBREG_REG (dest);
3817 if (dest == hard_frame_pointer_rtx)
3820 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3821 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3822 && (GET_CODE (x) != SET
3823 || GET_CODE (SET_SRC (x)) != PLUS
3824 || XEXP (SET_SRC (x), 0) != dest
3825 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3827 reg_eliminate[i].can_eliminate_previous
3828 = reg_eliminate[i].can_eliminate = 0;
3833 /* Verify that the initial elimination offsets did not change since the
3834 last call to set_initial_elim_offsets. This is used to catch cases
3835 where something illegal happened during reload_as_needed that could
3836 cause incorrect code to be generated if we did not check for it. */
3839 verify_initial_elim_offsets (void)
3843 if (!num_eliminable)
3846 #ifdef ELIMINABLE_REGS
3848 struct elim_table *ep;
3850 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3852 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3853 if (t != ep->initial_offset)
3858 INITIAL_FRAME_POINTER_OFFSET (t);
3859 if (t != reg_eliminate[0].initial_offset)
3866 /* Reset all offsets on eliminable registers to their initial values. */
3869 set_initial_elim_offsets (void)
3871 struct elim_table *ep = reg_eliminate;
3873 #ifdef ELIMINABLE_REGS
3874 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3876 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3877 ep->previous_offset = ep->offset = ep->initial_offset;
3880 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3881 ep->previous_offset = ep->offset = ep->initial_offset;
3884 num_not_at_initial_offset = 0;
3887 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3890 set_initial_eh_label_offset (rtx label)
3892 set_label_offsets (label, NULL_RTX, 1);
3895 /* Initialize the known label offsets.
3896 Set a known offset for each forced label to be at the initial offset
3897 of each elimination. We do this because we assume that all
3898 computed jumps occur from a location where each elimination is
3899 at its initial offset.
3900 For all other labels, show that we don't know the offsets. */
3903 set_initial_label_offsets (void)
3906 memset (offsets_known_at, 0, num_labels);
3908 for (x = forced_labels; x; x = XEXP (x, 1))
3910 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3912 for_each_eh_label (set_initial_eh_label_offset);
3915 /* Set all elimination offsets to the known values for the code label given
3919 set_offsets_for_label (rtx insn)
3922 int label_nr = CODE_LABEL_NUMBER (insn);
3923 struct elim_table *ep;
3925 num_not_at_initial_offset = 0;
3926 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3928 ep->offset = ep->previous_offset
3929 = offsets_at[label_nr - first_label_num][i];
3930 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3931 num_not_at_initial_offset++;
3935 /* See if anything that happened changes which eliminations are valid.
3936 For example, on the SPARC, whether or not the frame pointer can
3937 be eliminated can depend on what registers have been used. We need
3938 not check some conditions again (such as flag_omit_frame_pointer)
3939 since they can't have changed. */
3942 update_eliminables (HARD_REG_SET *pset)
3944 int previous_frame_pointer_needed = frame_pointer_needed;
3945 struct elim_table *ep;
3947 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3948 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3949 && targetm.frame_pointer_required ())
3950 #ifdef ELIMINABLE_REGS
3951 || ! targetm.can_eliminate (ep->from, ep->to)
3954 ep->can_eliminate = 0;
3956 /* Look for the case where we have discovered that we can't replace
3957 register A with register B and that means that we will now be
3958 trying to replace register A with register C. This means we can
3959 no longer replace register C with register B and we need to disable
3960 such an elimination, if it exists. This occurs often with A == ap,
3961 B == sp, and C == fp. */
3963 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3965 struct elim_table *op;
3968 if (! ep->can_eliminate && ep->can_eliminate_previous)
3970 /* Find the current elimination for ep->from, if there is a
3972 for (op = reg_eliminate;
3973 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3974 if (op->from == ep->from && op->can_eliminate)
3980 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3982 for (op = reg_eliminate;
3983 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3984 if (op->from == new_to && op->to == ep->to)
3985 op->can_eliminate = 0;
3989 /* See if any registers that we thought we could eliminate the previous
3990 time are no longer eliminable. If so, something has changed and we
3991 must spill the register. Also, recompute the number of eliminable
3992 registers and see if the frame pointer is needed; it is if there is
3993 no elimination of the frame pointer that we can perform. */
3995 frame_pointer_needed = 1;
3996 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3998 if (ep->can_eliminate
3999 && ep->from == FRAME_POINTER_REGNUM
4000 && ep->to != HARD_FRAME_POINTER_REGNUM
4001 && (! SUPPORTS_STACK_ALIGNMENT
4002 || ! crtl->stack_realign_needed))
4003 frame_pointer_needed = 0;
4005 if (! ep->can_eliminate && ep->can_eliminate_previous)
4007 ep->can_eliminate_previous = 0;
4008 SET_HARD_REG_BIT (*pset, ep->from);
4013 /* If we didn't need a frame pointer last time, but we do now, spill
4014 the hard frame pointer. */
4015 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4016 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4019 /* Return true if X is used as the target register of an elimination. */
4022 elimination_target_reg_p (rtx x)
4024 struct elim_table *ep;
4026 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4027 if (ep->to_rtx == x && ep->can_eliminate)
4033 /* Initialize the table of registers to eliminate.
4034 Pre-condition: global flag frame_pointer_needed has been set before
4035 calling this function. */
4038 init_elim_table (void)
4040 struct elim_table *ep;
4041 #ifdef ELIMINABLE_REGS
4042 const struct elim_table_1 *ep1;
4046 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4050 #ifdef ELIMINABLE_REGS
4051 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4052 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4054 ep->from = ep1->from;
4056 ep->can_eliminate = ep->can_eliminate_previous
4057 = (targetm.can_eliminate (ep->from, ep->to)
4058 && ! (ep->to == STACK_POINTER_REGNUM
4059 && frame_pointer_needed
4060 && (! SUPPORTS_STACK_ALIGNMENT
4061 || ! stack_realign_fp)));
4064 reg_eliminate[0].from = reg_eliminate_1[0].from;
4065 reg_eliminate[0].to = reg_eliminate_1[0].to;
4066 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4067 = ! frame_pointer_needed;
4070 /* Count the number of eliminable registers and build the FROM and TO
4071 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4072 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4073 We depend on this. */
4074 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4076 num_eliminable += ep->can_eliminate;
4077 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4078 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4082 /* Find all the pseudo registers that didn't get hard regs
4083 but do have known equivalent constants or memory slots.
4084 These include parameters (known equivalent to parameter slots)
4085 and cse'd or loop-moved constant memory addresses.
4087 Record constant equivalents in reg_equiv_constant
4088 so they will be substituted by find_reloads.
4089 Record memory equivalents in reg_mem_equiv so they can
4090 be substituted eventually by altering the REG-rtx's. */
4093 init_eliminable_invariants (rtx first, bool do_subregs)
4100 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4102 reg_max_ref_width = NULL;
4104 num_eliminable_invariants = 0;
4106 first_label_num = get_first_label_num ();
4107 num_labels = max_label_num () - first_label_num;
4109 /* Allocate the tables used to store offset information at labels. */
4110 offsets_known_at = XNEWVEC (char, num_labels);
4111 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4113 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4114 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4115 find largest such for each pseudo. FIRST is the head of the insn
4118 for (insn = first; insn; insn = NEXT_INSN (insn))
4120 rtx set = single_set (insn);
4122 /* We may introduce USEs that we want to remove at the end, so
4123 we'll mark them with QImode. Make sure there are no
4124 previously-marked insns left by say regmove. */
4125 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4126 && GET_MODE (insn) != VOIDmode)
4127 PUT_MODE (insn, VOIDmode);
4129 if (do_subregs && NONDEBUG_INSN_P (insn))
4130 scan_paradoxical_subregs (PATTERN (insn));
4132 if (set != 0 && REG_P (SET_DEST (set)))
4134 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4140 i = REGNO (SET_DEST (set));
4143 if (i <= LAST_VIRTUAL_REGISTER)
4146 /* If flag_pic and we have constant, verify it's legitimate. */
4148 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4150 /* It can happen that a REG_EQUIV note contains a MEM
4151 that is not a legitimate memory operand. As later
4152 stages of reload assume that all addresses found
4153 in the reg_equiv_* arrays were originally legitimate,
4154 we ignore such REG_EQUIV notes. */
4155 if (memory_operand (x, VOIDmode))
4157 /* Always unshare the equivalence, so we can
4158 substitute into this insn without touching the
4160 reg_equiv_memory_loc (i) = copy_rtx (x);
4162 else if (function_invariant_p (x))
4164 if (GET_CODE (x) == PLUS)
4166 /* This is PLUS of frame pointer and a constant,
4167 and might be shared. Unshare it. */
4168 reg_equiv_invariant (i) = copy_rtx (x);
4169 num_eliminable_invariants++;
4171 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4173 reg_equiv_invariant (i) = x;
4174 num_eliminable_invariants++;
4176 else if (LEGITIMATE_CONSTANT_P (x))
4177 reg_equiv_constant (i) = x;
4180 reg_equiv_memory_loc (i)
4181 = force_const_mem (GET_MODE (SET_DEST (set)), x);
4182 if (! reg_equiv_memory_loc (i))
4183 reg_equiv_init (i) = NULL_RTX;
4188 reg_equiv_init (i) = NULL_RTX;
4193 reg_equiv_init (i) = NULL_RTX;
4198 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4199 if (reg_equiv_init (i))
4201 fprintf (dump_file, "init_insns for %u: ", i);
4202 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4203 fprintf (dump_file, "\n");
4207 /* Indicate that we no longer have known memory locations or constants.
4208 Free all data involved in tracking these. */
4211 free_reg_equiv (void)
4216 free (offsets_known_at);
4219 offsets_known_at = 0;
4221 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4222 if (reg_equiv_alt_mem_list (i))
4223 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4224 VEC_free (reg_equivs_t, gc, reg_equivs);
4229 /* Kick all pseudos out of hard register REGNO.
4231 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4232 because we found we can't eliminate some register. In the case, no pseudos
4233 are allowed to be in the register, even if they are only in a block that
4234 doesn't require spill registers, unlike the case when we are spilling this
4235 hard reg to produce another spill register.
4237 Return nonzero if any pseudos needed to be kicked out. */
4240 spill_hard_reg (unsigned int regno, int cant_eliminate)
4246 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4247 df_set_regs_ever_live (regno, true);
4250 /* Spill every pseudo reg that was allocated to this reg
4251 or to something that overlaps this reg. */
4253 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4254 if (reg_renumber[i] >= 0
4255 && (unsigned int) reg_renumber[i] <= regno
4256 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4257 SET_REGNO_REG_SET (&spilled_pseudos, i);
4260 /* After find_reload_regs has been run for all insn that need reloads,
4261 and/or spill_hard_regs was called, this function is used to actually
4262 spill pseudo registers and try to reallocate them. It also sets up the
4263 spill_regs array for use by choose_reload_regs. */
4266 finish_spills (int global)
4268 struct insn_chain *chain;
4269 int something_changed = 0;
4271 reg_set_iterator rsi;
4273 /* Build the spill_regs array for the function. */
4274 /* If there are some registers still to eliminate and one of the spill regs
4275 wasn't ever used before, additional stack space may have to be
4276 allocated to store this register. Thus, we may have changed the offset
4277 between the stack and frame pointers, so mark that something has changed.
4279 One might think that we need only set VAL to 1 if this is a call-used
4280 register. However, the set of registers that must be saved by the
4281 prologue is not identical to the call-used set. For example, the
4282 register used by the call insn for the return PC is a call-used register,
4283 but must be saved by the prologue. */
4286 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4287 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4289 spill_reg_order[i] = n_spills;
4290 spill_regs[n_spills++] = i;
4291 if (num_eliminable && ! df_regs_ever_live_p (i))
4292 something_changed = 1;
4293 df_set_regs_ever_live (i, true);
4296 spill_reg_order[i] = -1;
4298 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4299 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4301 /* Record the current hard register the pseudo is allocated to
4302 in pseudo_previous_regs so we avoid reallocating it to the
4303 same hard reg in a later pass. */
4304 gcc_assert (reg_renumber[i] >= 0);
4306 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4307 /* Mark it as no longer having a hard register home. */
4308 reg_renumber[i] = -1;
4309 if (ira_conflicts_p)
4310 /* Inform IRA about the change. */
4311 ira_mark_allocation_change (i);
4312 /* We will need to scan everything again. */
4313 something_changed = 1;
4316 /* Retry global register allocation if possible. */
4317 if (global && ira_conflicts_p)
4321 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4322 /* For every insn that needs reloads, set the registers used as spill
4323 regs in pseudo_forbidden_regs for every pseudo live across the
4325 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4327 EXECUTE_IF_SET_IN_REG_SET
4328 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4330 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4331 chain->used_spill_regs);
4333 EXECUTE_IF_SET_IN_REG_SET
4334 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4336 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4337 chain->used_spill_regs);
4341 /* Retry allocating the pseudos spilled in IRA and the
4342 reload. For each reg, merge the various reg sets that
4343 indicate which hard regs can't be used, and call
4344 ira_reassign_pseudos. */
4345 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4346 if (reg_old_renumber[i] != reg_renumber[i])
4348 if (reg_renumber[i] < 0)
4349 temp_pseudo_reg_arr[n++] = i;
4351 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4353 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4354 bad_spill_regs_global,
4355 pseudo_forbidden_regs, pseudo_previous_regs,
4357 something_changed = 1;
4359 /* Fix up the register information in the insn chain.
4360 This involves deleting those of the spilled pseudos which did not get
4361 a new hard register home from the live_{before,after} sets. */
4362 for (chain = reload_insn_chain; chain; chain = chain->next)
4364 HARD_REG_SET used_by_pseudos;
4365 HARD_REG_SET used_by_pseudos2;
4367 if (! ira_conflicts_p)
4369 /* Don't do it for IRA because IRA and the reload still can
4370 assign hard registers to the spilled pseudos on next
4371 reload iterations. */
4372 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4373 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4375 /* Mark any unallocated hard regs as available for spills. That
4376 makes inheritance work somewhat better. */
4377 if (chain->need_reload)
4379 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4380 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4381 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4383 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4384 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4385 /* Value of chain->used_spill_regs from previous iteration
4386 may be not included in the value calculated here because
4387 of possible removing caller-saves insns (see function
4388 delete_caller_save_insns. */
4389 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4390 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4394 CLEAR_REG_SET (&changed_allocation_pseudos);
4395 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4396 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4398 int regno = reg_renumber[i];
4399 if (reg_old_renumber[i] == regno)
4402 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4404 alter_reg (i, reg_old_renumber[i], false);
4405 reg_old_renumber[i] = regno;
4409 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4411 fprintf (dump_file, " Register %d now in %d.\n\n",
4412 i, reg_renumber[i]);
4416 return something_changed;
4419 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4422 scan_paradoxical_subregs (rtx x)
4426 enum rtx_code code = GET_CODE (x);
4437 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4445 if (REG_P (SUBREG_REG (x))
4446 && (GET_MODE_SIZE (GET_MODE (x))
4447 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4449 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4450 = GET_MODE_SIZE (GET_MODE (x));
4451 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4459 fmt = GET_RTX_FORMAT (code);
4460 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4463 scan_paradoxical_subregs (XEXP (x, i));
4464 else if (fmt[i] == 'E')
4467 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4468 scan_paradoxical_subregs (XVECEXP (x, i, j));
4473 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4474 examine all of the reload insns between PREV and NEXT exclusive, and
4475 annotate all that may trap. */
4478 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4480 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4483 if (!insn_could_throw_p (insn))
4484 remove_note (insn, note);
4485 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4488 /* Reload pseudo-registers into hard regs around each insn as needed.
4489 Additional register load insns are output before the insn that needs it
4490 and perhaps store insns after insns that modify the reloaded pseudo reg.
4492 reg_last_reload_reg and reg_reloaded_contents keep track of
4493 which registers are already available in reload registers.
4494 We update these for the reloads that we perform,
4495 as the insns are scanned. */
4498 reload_as_needed (int live_known)
4500 struct insn_chain *chain;
4501 #if defined (AUTO_INC_DEC)
4506 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4507 memset (spill_reg_store, 0, sizeof spill_reg_store);
4508 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4509 INIT_REG_SET (®_has_output_reload);
4510 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4511 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4513 set_initial_elim_offsets ();
4515 for (chain = reload_insn_chain; chain; chain = chain->next)
4518 rtx insn = chain->insn;
4519 rtx old_next = NEXT_INSN (insn);
4521 rtx old_prev = PREV_INSN (insn);
4524 /* If we pass a label, copy the offsets from the label information
4525 into the current offsets of each elimination. */
4527 set_offsets_for_label (insn);
4529 else if (INSN_P (insn))
4531 regset_head regs_to_forget;
4532 INIT_REG_SET (®s_to_forget);
4533 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4535 /* If this is a USE and CLOBBER of a MEM, ensure that any
4536 references to eliminable registers have been removed. */
4538 if ((GET_CODE (PATTERN (insn)) == USE
4539 || GET_CODE (PATTERN (insn)) == CLOBBER)
4540 && MEM_P (XEXP (PATTERN (insn), 0)))
4541 XEXP (XEXP (PATTERN (insn), 0), 0)
4542 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4543 GET_MODE (XEXP (PATTERN (insn), 0)),
4546 /* If we need to do register elimination processing, do so.
4547 This might delete the insn, in which case we are done. */
4548 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4550 eliminate_regs_in_insn (insn, 1);
4553 update_eliminable_offsets ();
4554 CLEAR_REG_SET (®s_to_forget);
4559 /* If need_elim is nonzero but need_reload is zero, one might think
4560 that we could simply set n_reloads to 0. However, find_reloads
4561 could have done some manipulation of the insn (such as swapping
4562 commutative operands), and these manipulations are lost during
4563 the first pass for every insn that needs register elimination.
4564 So the actions of find_reloads must be redone here. */
4566 if (! chain->need_elim && ! chain->need_reload
4567 && ! chain->need_operand_change)
4569 /* First find the pseudo regs that must be reloaded for this insn.
4570 This info is returned in the tables reload_... (see reload.h).
4571 Also modify the body of INSN by substituting RELOAD
4572 rtx's for those pseudo regs. */
4575 CLEAR_REG_SET (®_has_output_reload);
4576 CLEAR_HARD_REG_SET (reg_is_output_reload);
4578 find_reloads (insn, 1, spill_indirect_levels, live_known,
4584 rtx next = NEXT_INSN (insn);
4587 prev = PREV_INSN (insn);
4589 /* Now compute which reload regs to reload them into. Perhaps
4590 reusing reload regs from previous insns, or else output
4591 load insns to reload them. Maybe output store insns too.
4592 Record the choices of reload reg in reload_reg_rtx. */
4593 choose_reload_regs (chain);
4595 /* Generate the insns to reload operands into or out of
4596 their reload regs. */
4597 emit_reload_insns (chain);
4599 /* Substitute the chosen reload regs from reload_reg_rtx
4600 into the insn's body (or perhaps into the bodies of other
4601 load and store insn that we just made for reloading
4602 and that we moved the structure into). */
4603 subst_reloads (insn);
4605 /* Adjust the exception region notes for loads and stores. */
4606 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4607 fixup_eh_region_note (insn, prev, next);
4609 /* If this was an ASM, make sure that all the reload insns
4610 we have generated are valid. If not, give an error
4612 if (asm_noperands (PATTERN (insn)) >= 0)
4613 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4614 if (p != insn && INSN_P (p)
4615 && GET_CODE (PATTERN (p)) != USE
4616 && (recog_memoized (p) < 0
4617 || (extract_insn (p), ! constrain_operands (1))))
4619 error_for_asm (insn,
4620 "%<asm%> operand requires "
4621 "impossible reload");
4626 if (num_eliminable && chain->need_elim)
4627 update_eliminable_offsets ();
4629 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4630 is no longer validly lying around to save a future reload.
4631 Note that this does not detect pseudos that were reloaded
4632 for this insn in order to be stored in
4633 (obeying register constraints). That is correct; such reload
4634 registers ARE still valid. */
4635 forget_marked_reloads (®s_to_forget);
4636 CLEAR_REG_SET (®s_to_forget);
4638 /* There may have been CLOBBER insns placed after INSN. So scan
4639 between INSN and NEXT and use them to forget old reloads. */
4640 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4641 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4642 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4645 /* Likewise for regs altered by auto-increment in this insn.
4646 REG_INC notes have been changed by reloading:
4647 find_reloads_address_1 records substitutions for them,
4648 which have been performed by subst_reloads above. */
4649 for (i = n_reloads - 1; i >= 0; i--)
4651 rtx in_reg = rld[i].in_reg;
4654 enum rtx_code code = GET_CODE (in_reg);
4655 /* PRE_INC / PRE_DEC will have the reload register ending up
4656 with the same value as the stack slot, but that doesn't
4657 hold true for POST_INC / POST_DEC. Either we have to
4658 convert the memory access to a true POST_INC / POST_DEC,
4659 or we can't use the reload register for inheritance. */
4660 if ((code == POST_INC || code == POST_DEC)
4661 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4662 REGNO (rld[i].reg_rtx))
4663 /* Make sure it is the inc/dec pseudo, and not
4664 some other (e.g. output operand) pseudo. */
4665 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4666 == REGNO (XEXP (in_reg, 0))))
4669 rtx reload_reg = rld[i].reg_rtx;
4670 enum machine_mode mode = GET_MODE (reload_reg);
4674 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4676 /* We really want to ignore REG_INC notes here, so
4677 use PATTERN (p) as argument to reg_set_p . */
4678 if (reg_set_p (reload_reg, PATTERN (p)))
4680 n = count_occurrences (PATTERN (p), reload_reg, 0);
4686 = gen_rtx_fmt_e (code, mode, reload_reg);
4688 validate_replace_rtx_group (reload_reg,
4690 n = verify_changes (0);
4692 /* We must also verify that the constraints
4693 are met after the replacement. Make sure
4694 extract_insn is only called for an insn
4695 where the replacements were found to be
4700 n = constrain_operands (1);
4703 /* If the constraints were not met, then
4704 undo the replacement, else confirm it. */
4708 confirm_change_group ();
4714 add_reg_note (p, REG_INC, reload_reg);
4715 /* Mark this as having an output reload so that the
4716 REG_INC processing code below won't invalidate
4717 the reload for inheritance. */
4718 SET_HARD_REG_BIT (reg_is_output_reload,
4719 REGNO (reload_reg));
4720 SET_REGNO_REG_SET (®_has_output_reload,
4721 REGNO (XEXP (in_reg, 0)));
4724 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4727 else if ((code == PRE_INC || code == PRE_DEC)
4728 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4729 REGNO (rld[i].reg_rtx))
4730 /* Make sure it is the inc/dec pseudo, and not
4731 some other (e.g. output operand) pseudo. */
4732 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4733 == REGNO (XEXP (in_reg, 0))))
4735 SET_HARD_REG_BIT (reg_is_output_reload,
4736 REGNO (rld[i].reg_rtx));
4737 SET_REGNO_REG_SET (®_has_output_reload,
4738 REGNO (XEXP (in_reg, 0)));
4740 else if (code == PRE_INC || code == PRE_DEC
4741 || code == POST_INC || code == POST_DEC)
4743 int in_regno = REGNO (XEXP (in_reg, 0));
4745 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4748 bool forget_p = true;
4750 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4751 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4754 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4757 if (x == reg_reloaded_insn[in_hard_regno])
4763 /* If for some reasons, we didn't set up
4764 reg_last_reload_reg in this insn,
4765 invalidate inheritance from previous
4766 insns for the incremented/decremented
4767 register. Such registers will be not in
4768 reg_has_output_reload. Invalidate it
4769 also if the corresponding element in
4770 reg_reloaded_insn is also
4773 forget_old_reloads_1 (XEXP (in_reg, 0),
4779 /* If a pseudo that got a hard register is auto-incremented,
4780 we must purge records of copying it into pseudos without
4782 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4783 if (REG_NOTE_KIND (x) == REG_INC)
4785 /* See if this pseudo reg was reloaded in this insn.
4786 If so, its last-reload info is still valid
4787 because it is based on this insn's reload. */
4788 for (i = 0; i < n_reloads; i++)
4789 if (rld[i].out == XEXP (x, 0))
4793 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4797 /* A reload reg's contents are unknown after a label. */
4799 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4801 /* Don't assume a reload reg is still good after a call insn
4802 if it is a call-used reg, or if it contains a value that will
4803 be partially clobbered by the call. */
4804 else if (CALL_P (insn))
4806 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4807 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4812 free (reg_last_reload_reg);
4813 CLEAR_REG_SET (®_has_output_reload);
4816 /* Discard all record of any value reloaded from X,
4817 or reloaded in X from someplace else;
4818 unless X is an output reload reg of the current insn.
4820 X may be a hard reg (the reload reg)
4821 or it may be a pseudo reg that was reloaded from.
4823 When DATA is non-NULL just mark the registers in regset
4824 to be forgotten later. */
4827 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4832 regset regs = (regset) data;
4834 /* note_stores does give us subregs of hard regs,
4835 subreg_regno_offset requires a hard reg. */
4836 while (GET_CODE (x) == SUBREG)
4838 /* We ignore the subreg offset when calculating the regno,
4839 because we are using the entire underlying hard register
4849 if (regno >= FIRST_PSEUDO_REGISTER)
4855 nr = hard_regno_nregs[regno][GET_MODE (x)];
4856 /* Storing into a spilled-reg invalidates its contents.
4857 This can happen if a block-local pseudo is allocated to that reg
4858 and it wasn't spilled because this block's total need is 0.
4859 Then some insn might have an optional reload and use this reg. */
4861 for (i = 0; i < nr; i++)
4862 /* But don't do this if the reg actually serves as an output
4863 reload reg in the current instruction. */
4865 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4867 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4868 spill_reg_store[regno + i] = 0;
4874 SET_REGNO_REG_SET (regs, regno + nr);
4877 /* Since value of X has changed,
4878 forget any value previously copied from it. */
4881 /* But don't forget a copy if this is the output reload
4882 that establishes the copy's validity. */
4884 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4885 reg_last_reload_reg[regno + nr] = 0;
4889 /* Forget the reloads marked in regset by previous function. */
4891 forget_marked_reloads (regset regs)
4894 reg_set_iterator rsi;
4895 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4897 if (reg < FIRST_PSEUDO_REGISTER
4898 /* But don't do this if the reg actually serves as an output
4899 reload reg in the current instruction. */
4901 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4903 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4904 spill_reg_store[reg] = 0;
4907 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4908 reg_last_reload_reg[reg] = 0;
4912 /* The following HARD_REG_SETs indicate when each hard register is
4913 used for a reload of various parts of the current insn. */
4915 /* If reg is unavailable for all reloads. */
4916 static HARD_REG_SET reload_reg_unavailable;
4917 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4918 static HARD_REG_SET reload_reg_used;
4919 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4920 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4921 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4922 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4923 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4924 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4925 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4926 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4927 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4928 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4929 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4930 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4931 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4932 static HARD_REG_SET reload_reg_used_in_op_addr;
4933 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4934 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4935 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4936 static HARD_REG_SET reload_reg_used_in_insn;
4937 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4938 static HARD_REG_SET reload_reg_used_in_other_addr;
4940 /* If reg is in use as a reload reg for any sort of reload. */
4941 static HARD_REG_SET reload_reg_used_at_all;
4943 /* If reg is use as an inherited reload. We just mark the first register
4945 static HARD_REG_SET reload_reg_used_for_inherit;
4947 /* Records which hard regs are used in any way, either as explicit use or
4948 by being allocated to a pseudo during any point of the current insn. */
4949 static HARD_REG_SET reg_used_in_insn;
4951 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4952 TYPE. MODE is used to indicate how many consecutive regs are
4956 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4957 enum machine_mode mode)
4962 add_to_hard_reg_set (&reload_reg_used, mode, regno);
4965 case RELOAD_FOR_INPUT_ADDRESS:
4966 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
4969 case RELOAD_FOR_INPADDR_ADDRESS:
4970 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
4973 case RELOAD_FOR_OUTPUT_ADDRESS:
4974 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
4977 case RELOAD_FOR_OUTADDR_ADDRESS:
4978 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
4981 case RELOAD_FOR_OPERAND_ADDRESS:
4982 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
4985 case RELOAD_FOR_OPADDR_ADDR:
4986 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
4989 case RELOAD_FOR_OTHER_ADDRESS:
4990 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
4993 case RELOAD_FOR_INPUT:
4994 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
4997 case RELOAD_FOR_OUTPUT:
4998 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5001 case RELOAD_FOR_INSN:
5002 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5006 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5009 /* Similarly, but show REGNO is no longer in use for a reload. */
5012 clear_reload_reg_in_use (unsigned int regno, int opnum,
5013 enum reload_type type, enum machine_mode mode)
5015 unsigned int nregs = hard_regno_nregs[regno][mode];
5016 unsigned int start_regno, end_regno, r;
5018 /* A complication is that for some reload types, inheritance might
5019 allow multiple reloads of the same types to share a reload register.
5020 We set check_opnum if we have to check only reloads with the same
5021 operand number, and check_any if we have to check all reloads. */
5022 int check_opnum = 0;
5024 HARD_REG_SET *used_in_set;
5029 used_in_set = &reload_reg_used;
5032 case RELOAD_FOR_INPUT_ADDRESS:
5033 used_in_set = &reload_reg_used_in_input_addr[opnum];
5036 case RELOAD_FOR_INPADDR_ADDRESS:
5038 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5041 case RELOAD_FOR_OUTPUT_ADDRESS:
5042 used_in_set = &reload_reg_used_in_output_addr[opnum];
5045 case RELOAD_FOR_OUTADDR_ADDRESS:
5047 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5050 case RELOAD_FOR_OPERAND_ADDRESS:
5051 used_in_set = &reload_reg_used_in_op_addr;
5054 case RELOAD_FOR_OPADDR_ADDR:
5056 used_in_set = &reload_reg_used_in_op_addr_reload;
5059 case RELOAD_FOR_OTHER_ADDRESS:
5060 used_in_set = &reload_reg_used_in_other_addr;
5064 case RELOAD_FOR_INPUT:
5065 used_in_set = &reload_reg_used_in_input[opnum];
5068 case RELOAD_FOR_OUTPUT:
5069 used_in_set = &reload_reg_used_in_output[opnum];
5072 case RELOAD_FOR_INSN:
5073 used_in_set = &reload_reg_used_in_insn;
5078 /* We resolve conflicts with remaining reloads of the same type by
5079 excluding the intervals of reload registers by them from the
5080 interval of freed reload registers. Since we only keep track of
5081 one set of interval bounds, we might have to exclude somewhat
5082 more than what would be necessary if we used a HARD_REG_SET here.
5083 But this should only happen very infrequently, so there should
5084 be no reason to worry about it. */
5086 start_regno = regno;
5087 end_regno = regno + nregs;
5088 if (check_opnum || check_any)
5090 for (i = n_reloads - 1; i >= 0; i--)
5092 if (rld[i].when_needed == type
5093 && (check_any || rld[i].opnum == opnum)
5096 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5097 unsigned int conflict_end
5098 = end_hard_regno (rld[i].mode, conflict_start);
5100 /* If there is an overlap with the first to-be-freed register,
5101 adjust the interval start. */
5102 if (conflict_start <= start_regno && conflict_end > start_regno)
5103 start_regno = conflict_end;
5104 /* Otherwise, if there is a conflict with one of the other
5105 to-be-freed registers, adjust the interval end. */
5106 if (conflict_start > start_regno && conflict_start < end_regno)
5107 end_regno = conflict_start;
5112 for (r = start_regno; r < end_regno; r++)
5113 CLEAR_HARD_REG_BIT (*used_in_set, r);
5116 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5117 specified by OPNUM and TYPE. */
5120 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5124 /* In use for a RELOAD_OTHER means it's not available for anything. */
5125 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5126 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5132 /* In use for anything means we can't use it for RELOAD_OTHER. */
5133 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5134 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5135 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5136 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5139 for (i = 0; i < reload_n_operands; i++)
5140 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5141 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5142 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5143 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5144 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5145 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5150 case RELOAD_FOR_INPUT:
5151 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5152 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5155 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5158 /* If it is used for some other input, can't use it. */
5159 for (i = 0; i < reload_n_operands; i++)
5160 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5163 /* If it is used in a later operand's address, can't use it. */
5164 for (i = opnum + 1; i < reload_n_operands; i++)
5165 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5166 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5171 case RELOAD_FOR_INPUT_ADDRESS:
5172 /* Can't use a register if it is used for an input address for this
5173 operand or used as an input in an earlier one. */
5174 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5175 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5178 for (i = 0; i < opnum; i++)
5179 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5184 case RELOAD_FOR_INPADDR_ADDRESS:
5185 /* Can't use a register if it is used for an input address
5186 for this operand or used as an input in an earlier
5188 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5191 for (i = 0; i < opnum; i++)
5192 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5197 case RELOAD_FOR_OUTPUT_ADDRESS:
5198 /* Can't use a register if it is used for an output address for this
5199 operand or used as an output in this or a later operand. Note
5200 that multiple output operands are emitted in reverse order, so
5201 the conflicting ones are those with lower indices. */
5202 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5205 for (i = 0; i <= opnum; i++)
5206 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5211 case RELOAD_FOR_OUTADDR_ADDRESS:
5212 /* Can't use a register if it is used for an output address
5213 for this operand or used as an output in this or a
5214 later operand. Note that multiple output operands are
5215 emitted in reverse order, so the conflicting ones are
5216 those with lower indices. */
5217 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5220 for (i = 0; i <= opnum; i++)
5221 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5226 case RELOAD_FOR_OPERAND_ADDRESS:
5227 for (i = 0; i < reload_n_operands; i++)
5228 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5231 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5232 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5234 case RELOAD_FOR_OPADDR_ADDR:
5235 for (i = 0; i < reload_n_operands; i++)
5236 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5239 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5241 case RELOAD_FOR_OUTPUT:
5242 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5243 outputs, or an operand address for this or an earlier output.
5244 Note that multiple output operands are emitted in reverse order,
5245 so the conflicting ones are those with higher indices. */
5246 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5249 for (i = 0; i < reload_n_operands; i++)
5250 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5253 for (i = opnum; i < reload_n_operands; i++)
5254 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5255 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5260 case RELOAD_FOR_INSN:
5261 for (i = 0; i < reload_n_operands; i++)
5262 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5263 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5266 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5267 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5269 case RELOAD_FOR_OTHER_ADDRESS:
5270 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5277 /* Return 1 if the value in reload reg REGNO, as used by a reload
5278 needed for the part of the insn specified by OPNUM and TYPE,
5279 is still available in REGNO at the end of the insn.
5281 We can assume that the reload reg was already tested for availability
5282 at the time it is needed, and we should not check this again,
5283 in case the reg has already been marked in use. */
5286 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
5293 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5294 its value must reach the end. */
5297 /* If this use is for part of the insn,
5298 its value reaches if no subsequent part uses the same register.
5299 Just like the above function, don't try to do this with lots
5302 case RELOAD_FOR_OTHER_ADDRESS:
5303 /* Here we check for everything else, since these don't conflict
5304 with anything else and everything comes later. */
5306 for (i = 0; i < reload_n_operands; i++)
5307 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5308 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5309 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5310 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5311 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5312 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5315 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5316 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5317 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5318 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5320 case RELOAD_FOR_INPUT_ADDRESS:
5321 case RELOAD_FOR_INPADDR_ADDRESS:
5322 /* Similar, except that we check only for this and subsequent inputs
5323 and the address of only subsequent inputs and we do not need
5324 to check for RELOAD_OTHER objects since they are known not to
5327 for (i = opnum; i < reload_n_operands; i++)
5328 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5331 for (i = opnum + 1; i < reload_n_operands; i++)
5332 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5333 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5336 for (i = 0; i < reload_n_operands; i++)
5337 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5338 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5339 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5342 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5345 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5346 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5347 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5349 case RELOAD_FOR_INPUT:
5350 /* Similar to input address, except we start at the next operand for
5351 both input and input address and we do not check for
5352 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5355 for (i = opnum + 1; i < reload_n_operands; i++)
5356 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5357 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5358 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5361 /* ... fall through ... */
5363 case RELOAD_FOR_OPERAND_ADDRESS:
5364 /* Check outputs and their addresses. */
5366 for (i = 0; i < reload_n_operands; i++)
5367 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5368 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5369 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5372 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5374 case RELOAD_FOR_OPADDR_ADDR:
5375 for (i = 0; i < reload_n_operands; i++)
5376 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5377 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5378 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5381 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5382 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5383 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5385 case RELOAD_FOR_INSN:
5386 /* These conflict with other outputs with RELOAD_OTHER. So
5387 we need only check for output addresses. */
5389 opnum = reload_n_operands;
5391 /* ... fall through ... */
5393 case RELOAD_FOR_OUTPUT:
5394 case RELOAD_FOR_OUTPUT_ADDRESS:
5395 case RELOAD_FOR_OUTADDR_ADDRESS:
5396 /* We already know these can't conflict with a later output. So the
5397 only thing to check are later output addresses.
5398 Note that multiple output operands are emitted in reverse order,
5399 so the conflicting ones are those with lower indices. */
5400 for (i = 0; i < opnum; i++)
5401 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5402 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5412 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5413 every register in the range [REGNO, REGNO + NREGS). */
5416 reload_regs_reach_end_p (unsigned int regno, int nregs,
5417 int opnum, enum reload_type type)
5421 for (i = 0; i < nregs; i++)
5422 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5428 /* Returns whether R1 and R2 are uniquely chained: the value of one
5429 is used by the other, and that value is not used by any other
5430 reload for this insn. This is used to partially undo the decision
5431 made in find_reloads when in the case of multiple
5432 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5433 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5434 reloads. This code tries to avoid the conflict created by that
5435 change. It might be cleaner to explicitly keep track of which
5436 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5437 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5438 this after the fact. */
5440 reloads_unique_chain_p (int r1, int r2)
5444 /* We only check input reloads. */
5445 if (! rld[r1].in || ! rld[r2].in)
5448 /* Avoid anything with output reloads. */
5449 if (rld[r1].out || rld[r2].out)
5452 /* "chained" means one reload is a component of the other reload,
5453 not the same as the other reload. */
5454 if (rld[r1].opnum != rld[r2].opnum
5455 || rtx_equal_p (rld[r1].in, rld[r2].in)
5456 || rld[r1].optional || rld[r2].optional
5457 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5458 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5461 for (i = 0; i < n_reloads; i ++)
5462 /* Look for input reloads that aren't our two */
5463 if (i != r1 && i != r2 && rld[i].in)
5465 /* If our reload is mentioned at all, it isn't a simple chain. */
5466 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5472 /* The recursive function change all occurrences of WHAT in *WHERE
5475 substitute (rtx *where, const_rtx what, rtx repl)
5484 if (*where == what || rtx_equal_p (*where, what))
5486 /* Record the location of the changed rtx. */
5487 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5492 code = GET_CODE (*where);
5493 fmt = GET_RTX_FORMAT (code);
5494 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5500 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5501 substitute (&XVECEXP (*where, i, j), what, repl);
5503 else if (fmt[i] == 'e')
5504 substitute (&XEXP (*where, i), what, repl);
5508 /* The function returns TRUE if chain of reload R1 and R2 (in any
5509 order) can be evaluated without usage of intermediate register for
5510 the reload containing another reload. It is important to see
5511 gen_reload to understand what the function is trying to do. As an
5512 example, let us have reload chain
5515 r1: <something> + const
5517 and reload R2 got reload reg HR. The function returns true if
5518 there is a correct insn HR = HR + <something>. Otherwise,
5519 gen_reload will use intermediate register (and this is the reload
5520 reg for R1) to reload <something>.
5522 We need this function to find a conflict for chain reloads. In our
5523 example, if HR = HR + <something> is incorrect insn, then we cannot
5524 use HR as a reload register for R2. If we do use it then we get a
5533 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5535 /* Assume other cases in gen_reload are not possible for
5536 chain reloads or do need an intermediate hard registers. */
5539 rtx out, in, tem, insn;
5540 rtx last = get_last_insn ();
5542 /* Make r2 a component of r1. */
5543 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5549 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5550 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5551 gcc_assert (regno >= 0);
5552 out = gen_rtx_REG (rld[r1].mode, regno);
5554 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5556 /* If IN is a paradoxical SUBREG, remove it and try to put the
5557 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5558 if (GET_CODE (in) == SUBREG
5559 && (GET_MODE_SIZE (GET_MODE (in))
5560 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5561 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5562 in = SUBREG_REG (in), out = tem;
5564 if (GET_CODE (in) == PLUS
5565 && (REG_P (XEXP (in, 0))
5566 || GET_CODE (XEXP (in, 0)) == SUBREG
5567 || MEM_P (XEXP (in, 0)))
5568 && (REG_P (XEXP (in, 1))
5569 || GET_CODE (XEXP (in, 1)) == SUBREG
5570 || CONSTANT_P (XEXP (in, 1))
5571 || MEM_P (XEXP (in, 1))))
5573 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5574 code = recog_memoized (insn);
5579 extract_insn (insn);
5580 /* We want constrain operands to treat this insn strictly in
5581 its validity determination, i.e., the way it would after
5582 reload has completed. */
5583 result = constrain_operands (1);
5586 delete_insns_since (last);
5589 /* Restore the original value at each changed address within R1. */
5590 while (!VEC_empty (rtx_p, substitute_stack))
5592 rtx *where = VEC_pop (rtx_p, substitute_stack);
5593 *where = rld[r2].in;
5599 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5602 This function uses the same algorithm as reload_reg_free_p above. */
5605 reloads_conflict (int r1, int r2)
5607 enum reload_type r1_type = rld[r1].when_needed;
5608 enum reload_type r2_type = rld[r2].when_needed;
5609 int r1_opnum = rld[r1].opnum;
5610 int r2_opnum = rld[r2].opnum;
5612 /* RELOAD_OTHER conflicts with everything. */
5613 if (r2_type == RELOAD_OTHER)
5616 /* Otherwise, check conflicts differently for each type. */
5620 case RELOAD_FOR_INPUT:
5621 return (r2_type == RELOAD_FOR_INSN
5622 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5623 || r2_type == RELOAD_FOR_OPADDR_ADDR
5624 || r2_type == RELOAD_FOR_INPUT
5625 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5626 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5627 && r2_opnum > r1_opnum));
5629 case RELOAD_FOR_INPUT_ADDRESS:
5630 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5631 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5633 case RELOAD_FOR_INPADDR_ADDRESS:
5634 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5635 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5637 case RELOAD_FOR_OUTPUT_ADDRESS:
5638 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5639 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5641 case RELOAD_FOR_OUTADDR_ADDRESS:
5642 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5643 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5645 case RELOAD_FOR_OPERAND_ADDRESS:
5646 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5647 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5648 && (!reloads_unique_chain_p (r1, r2)
5649 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5651 case RELOAD_FOR_OPADDR_ADDR:
5652 return (r2_type == RELOAD_FOR_INPUT
5653 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5655 case RELOAD_FOR_OUTPUT:
5656 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5657 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5658 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5659 && r2_opnum >= r1_opnum));
5661 case RELOAD_FOR_INSN:
5662 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5663 || r2_type == RELOAD_FOR_INSN
5664 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5666 case RELOAD_FOR_OTHER_ADDRESS:
5667 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5677 /* Indexed by reload number, 1 if incoming value
5678 inherited from previous insns. */
5679 static char reload_inherited[MAX_RELOADS];
5681 /* For an inherited reload, this is the insn the reload was inherited from,
5682 if we know it. Otherwise, this is 0. */
5683 static rtx reload_inheritance_insn[MAX_RELOADS];
5685 /* If nonzero, this is a place to get the value of the reload,
5686 rather than using reload_in. */
5687 static rtx reload_override_in[MAX_RELOADS];
5689 /* For each reload, the hard register number of the register used,
5690 or -1 if we did not need a register for this reload. */
5691 static int reload_spill_index[MAX_RELOADS];
5693 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5694 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5696 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5697 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5699 /* Subroutine of free_for_value_p, used to check a single register.
5700 START_REGNO is the starting regno of the full reload register
5701 (possibly comprising multiple hard registers) that we are considering. */
5704 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5705 enum reload_type type, rtx value, rtx out,
5706 int reloadnum, int ignore_address_reloads)
5709 /* Set if we see an input reload that must not share its reload register
5710 with any new earlyclobber, but might otherwise share the reload
5711 register with an output or input-output reload. */
5712 int check_earlyclobber = 0;
5716 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5719 if (out == const0_rtx)
5725 /* We use some pseudo 'time' value to check if the lifetimes of the
5726 new register use would overlap with the one of a previous reload
5727 that is not read-only or uses a different value.
5728 The 'time' used doesn't have to be linear in any shape or form, just
5730 Some reload types use different 'buckets' for each operand.
5731 So there are MAX_RECOG_OPERANDS different time values for each
5733 We compute TIME1 as the time when the register for the prospective
5734 new reload ceases to be live, and TIME2 for each existing
5735 reload as the time when that the reload register of that reload
5737 Where there is little to be gained by exact lifetime calculations,
5738 we just make conservative assumptions, i.e. a longer lifetime;
5739 this is done in the 'default:' cases. */
5742 case RELOAD_FOR_OTHER_ADDRESS:
5743 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5744 time1 = copy ? 0 : 1;
5747 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5749 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5750 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5751 respectively, to the time values for these, we get distinct time
5752 values. To get distinct time values for each operand, we have to
5753 multiply opnum by at least three. We round that up to four because
5754 multiply by four is often cheaper. */
5755 case RELOAD_FOR_INPADDR_ADDRESS:
5756 time1 = opnum * 4 + 2;
5758 case RELOAD_FOR_INPUT_ADDRESS:
5759 time1 = opnum * 4 + 3;
5761 case RELOAD_FOR_INPUT:
5762 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5763 executes (inclusive). */
5764 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5766 case RELOAD_FOR_OPADDR_ADDR:
5768 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5769 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5771 case RELOAD_FOR_OPERAND_ADDRESS:
5772 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5774 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5776 case RELOAD_FOR_OUTADDR_ADDRESS:
5777 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5779 case RELOAD_FOR_OUTPUT_ADDRESS:
5780 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5783 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5786 for (i = 0; i < n_reloads; i++)
5788 rtx reg = rld[i].reg_rtx;
5789 if (reg && REG_P (reg)
5790 && ((unsigned) regno - true_regnum (reg)
5791 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5794 rtx other_input = rld[i].in;
5796 /* If the other reload loads the same input value, that
5797 will not cause a conflict only if it's loading it into
5798 the same register. */
5799 if (true_regnum (reg) != start_regno)
5800 other_input = NULL_RTX;
5801 if (! other_input || ! rtx_equal_p (other_input, value)
5802 || rld[i].out || out)
5805 switch (rld[i].when_needed)
5807 case RELOAD_FOR_OTHER_ADDRESS:
5810 case RELOAD_FOR_INPADDR_ADDRESS:
5811 /* find_reloads makes sure that a
5812 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5813 by at most one - the first -
5814 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5815 address reload is inherited, the address address reload
5816 goes away, so we can ignore this conflict. */
5817 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5818 && ignore_address_reloads
5819 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5820 Then the address address is still needed to store
5821 back the new address. */
5822 && ! rld[reloadnum].out)
5824 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5825 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5827 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5828 && ignore_address_reloads
5829 /* Unless we are reloading an auto_inc expression. */
5830 && ! rld[reloadnum].out)
5832 time2 = rld[i].opnum * 4 + 2;
5834 case RELOAD_FOR_INPUT_ADDRESS:
5835 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5836 && ignore_address_reloads
5837 && ! rld[reloadnum].out)
5839 time2 = rld[i].opnum * 4 + 3;
5841 case RELOAD_FOR_INPUT:
5842 time2 = rld[i].opnum * 4 + 4;
5843 check_earlyclobber = 1;
5845 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5846 == MAX_RECOG_OPERAND * 4 */
5847 case RELOAD_FOR_OPADDR_ADDR:
5848 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5849 && ignore_address_reloads
5850 && ! rld[reloadnum].out)
5852 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5854 case RELOAD_FOR_OPERAND_ADDRESS:
5855 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5856 check_earlyclobber = 1;
5858 case RELOAD_FOR_INSN:
5859 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5861 case RELOAD_FOR_OUTPUT:
5862 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5863 instruction is executed. */
5864 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5866 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5867 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5869 case RELOAD_FOR_OUTADDR_ADDRESS:
5870 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5871 && ignore_address_reloads
5872 && ! rld[reloadnum].out)
5874 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5876 case RELOAD_FOR_OUTPUT_ADDRESS:
5877 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5880 /* If there is no conflict in the input part, handle this
5881 like an output reload. */
5882 if (! rld[i].in || rtx_equal_p (other_input, value))
5884 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5885 /* Earlyclobbered outputs must conflict with inputs. */
5886 if (earlyclobber_operand_p (rld[i].out))
5887 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5892 /* RELOAD_OTHER might be live beyond instruction execution,
5893 but this is not obvious when we set time2 = 1. So check
5894 here if there might be a problem with the new reload
5895 clobbering the register used by the RELOAD_OTHER. */
5903 && (! rld[i].in || rld[i].out
5904 || ! rtx_equal_p (other_input, value)))
5905 || (out && rld[reloadnum].out_reg
5906 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5912 /* Earlyclobbered outputs must conflict with inputs. */
5913 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5919 /* Return 1 if the value in reload reg REGNO, as used by a reload
5920 needed for the part of the insn specified by OPNUM and TYPE,
5921 may be used to load VALUE into it.
5923 MODE is the mode in which the register is used, this is needed to
5924 determine how many hard regs to test.
5926 Other read-only reloads with the same value do not conflict
5927 unless OUT is nonzero and these other reloads have to live while
5928 output reloads live.
5929 If OUT is CONST0_RTX, this is a special case: it means that the
5930 test should not be for using register REGNO as reload register, but
5931 for copying from register REGNO into the reload register.
5933 RELOADNUM is the number of the reload we want to load this value for;
5934 a reload does not conflict with itself.
5936 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5937 reloads that load an address for the very reload we are considering.
5939 The caller has to make sure that there is no conflict with the return
5943 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5944 enum reload_type type, rtx value, rtx out, int reloadnum,
5945 int ignore_address_reloads)
5947 int nregs = hard_regno_nregs[regno][mode];
5949 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5950 value, out, reloadnum,
5951 ignore_address_reloads))
5956 /* Return nonzero if the rtx X is invariant over the current function. */
5957 /* ??? Actually, the places where we use this expect exactly what is
5958 tested here, and not everything that is function invariant. In
5959 particular, the frame pointer and arg pointer are special cased;
5960 pic_offset_table_rtx is not, and we must not spill these things to
5964 function_invariant_p (const_rtx x)
5968 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5970 if (GET_CODE (x) == PLUS
5971 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5972 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5977 /* Determine whether the reload reg X overlaps any rtx'es used for
5978 overriding inheritance. Return nonzero if so. */
5981 conflicts_with_override (rtx x)
5984 for (i = 0; i < n_reloads; i++)
5985 if (reload_override_in[i]
5986 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5991 /* Give an error message saying we failed to find a reload for INSN,
5992 and clear out reload R. */
5994 failed_reload (rtx insn, int r)
5996 if (asm_noperands (PATTERN (insn)) < 0)
5997 /* It's the compiler's fault. */
5998 fatal_insn ("could not find a spill register", insn);
6000 /* It's the user's fault; the operand's mode and constraint
6001 don't match. Disable this reload so we don't crash in final. */
6002 error_for_asm (insn,
6003 "%<asm%> operand constraint incompatible with operand size");
6007 rld[r].optional = 1;
6008 rld[r].secondary_p = 1;
6011 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6012 for reload R. If it's valid, get an rtx for it. Return nonzero if
6015 set_reload_reg (int i, int r)
6017 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6019 int regno ATTRIBUTE_UNUSED;
6020 rtx reg = spill_reg_rtx[i];
6022 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6023 spill_reg_rtx[i] = reg
6024 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6026 regno = true_regnum (reg);
6028 /* Detect when the reload reg can't hold the reload mode.
6029 This used to be one `if', but Sequent compiler can't handle that. */
6030 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6032 enum machine_mode test_mode = VOIDmode;
6034 test_mode = GET_MODE (rld[r].in);
6035 /* If rld[r].in has VOIDmode, it means we will load it
6036 in whatever mode the reload reg has: to wit, rld[r].mode.
6037 We have already tested that for validity. */
6038 /* Aside from that, we need to test that the expressions
6039 to reload from or into have modes which are valid for this
6040 reload register. Otherwise the reload insns would be invalid. */
6041 if (! (rld[r].in != 0 && test_mode != VOIDmode
6042 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6043 if (! (rld[r].out != 0
6044 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6046 /* The reg is OK. */
6049 /* Mark as in use for this insn the reload regs we use
6051 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6052 rld[r].when_needed, rld[r].mode);
6054 rld[r].reg_rtx = reg;
6055 reload_spill_index[r] = spill_regs[i];
6062 /* Find a spill register to use as a reload register for reload R.
6063 LAST_RELOAD is nonzero if this is the last reload for the insn being
6066 Set rld[R].reg_rtx to the register allocated.
6068 We return 1 if successful, or 0 if we couldn't find a spill reg and
6069 we didn't change anything. */
6072 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6077 /* If we put this reload ahead, thinking it is a group,
6078 then insist on finding a group. Otherwise we can grab a
6079 reg that some other reload needs.
6080 (That can happen when we have a 68000 DATA_OR_FP_REG
6081 which is a group of data regs or one fp reg.)
6082 We need not be so restrictive if there are no more reloads
6085 ??? Really it would be nicer to have smarter handling
6086 for that kind of reg class, where a problem like this is normal.
6087 Perhaps those classes should be avoided for reloading
6088 by use of more alternatives. */
6090 int force_group = rld[r].nregs > 1 && ! last_reload;
6092 /* If we want a single register and haven't yet found one,
6093 take any reg in the right class and not in use.
6094 If we want a consecutive group, here is where we look for it.
6096 We use three passes so we can first look for reload regs to
6097 reuse, which are already in use for other reloads in this insn,
6098 and only then use additional registers which are not "bad", then
6099 finally any register.
6101 I think that maximizing reuse is needed to make sure we don't
6102 run out of reload regs. Suppose we have three reloads, and
6103 reloads A and B can share regs. These need two regs.
6104 Suppose A and B are given different regs.
6105 That leaves none for C. */
6106 for (pass = 0; pass < 3; pass++)
6108 /* I is the index in spill_regs.
6109 We advance it round-robin between insns to use all spill regs
6110 equally, so that inherited reloads have a chance
6111 of leapfrogging each other. */
6115 for (count = 0; count < n_spills; count++)
6117 int rclass = (int) rld[r].rclass;
6123 regnum = spill_regs[i];
6125 if ((reload_reg_free_p (regnum, rld[r].opnum,
6128 /* We check reload_reg_used to make sure we
6129 don't clobber the return register. */
6130 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6131 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6132 rld[r].when_needed, rld[r].in,
6134 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6135 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6136 /* Look first for regs to share, then for unshared. But
6137 don't share regs used for inherited reloads; they are
6138 the ones we want to preserve. */
6140 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6142 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6145 int nr = hard_regno_nregs[regnum][rld[r].mode];
6147 /* During the second pass we want to avoid reload registers
6148 which are "bad" for this reload. */
6150 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6153 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6154 (on 68000) got us two FP regs. If NR is 1,
6155 we would reject both of them. */
6158 /* If we need only one reg, we have already won. */
6161 /* But reject a single reg if we demand a group. */
6166 /* Otherwise check that as many consecutive regs as we need
6167 are available here. */
6170 int regno = regnum + nr - 1;
6171 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6172 && spill_reg_order[regno] >= 0
6173 && reload_reg_free_p (regno, rld[r].opnum,
6174 rld[r].when_needed)))
6183 /* If we found something on the current pass, omit later passes. */
6184 if (count < n_spills)
6188 /* We should have found a spill register by now. */
6189 if (count >= n_spills)
6192 /* I is the index in SPILL_REG_RTX of the reload register we are to
6193 allocate. Get an rtx for it and find its register number. */
6195 return set_reload_reg (i, r);
6198 /* Initialize all the tables needed to allocate reload registers.
6199 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6200 is the array we use to restore the reg_rtx field for every reload. */
6203 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6207 for (i = 0; i < n_reloads; i++)
6208 rld[i].reg_rtx = save_reload_reg_rtx[i];
6210 memset (reload_inherited, 0, MAX_RELOADS);
6211 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6212 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6214 CLEAR_HARD_REG_SET (reload_reg_used);
6215 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6216 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6217 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6218 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6219 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6221 CLEAR_HARD_REG_SET (reg_used_in_insn);
6224 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6225 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6226 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6227 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6228 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6229 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6232 for (i = 0; i < reload_n_operands; i++)
6234 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6235 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6236 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6237 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6238 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6239 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6242 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6244 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6246 for (i = 0; i < n_reloads; i++)
6247 /* If we have already decided to use a certain register,
6248 don't use it in another way. */
6250 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6251 rld[i].when_needed, rld[i].mode);
6254 /* Assign hard reg targets for the pseudo-registers we must reload
6255 into hard regs for this insn.
6256 Also output the instructions to copy them in and out of the hard regs.
6258 For machines with register classes, we are responsible for
6259 finding a reload reg in the proper class. */
6262 choose_reload_regs (struct insn_chain *chain)
6264 rtx insn = chain->insn;
6266 unsigned int max_group_size = 1;
6267 enum reg_class group_class = NO_REGS;
6268 int pass, win, inheritance;
6270 rtx save_reload_reg_rtx[MAX_RELOADS];
6272 /* In order to be certain of getting the registers we need,
6273 we must sort the reloads into order of increasing register class.
6274 Then our grabbing of reload registers will parallel the process
6275 that provided the reload registers.
6277 Also note whether any of the reloads wants a consecutive group of regs.
6278 If so, record the maximum size of the group desired and what
6279 register class contains all the groups needed by this insn. */
6281 for (j = 0; j < n_reloads; j++)
6283 reload_order[j] = j;
6284 if (rld[j].reg_rtx != NULL_RTX)
6286 gcc_assert (REG_P (rld[j].reg_rtx)
6287 && HARD_REGISTER_P (rld[j].reg_rtx));
6288 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6291 reload_spill_index[j] = -1;
6293 if (rld[j].nregs > 1)
6295 max_group_size = MAX (rld[j].nregs, max_group_size);
6297 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6300 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6304 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6306 /* If -O, try first with inheritance, then turning it off.
6307 If not -O, don't do inheritance.
6308 Using inheritance when not optimizing leads to paradoxes
6309 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6310 because one side of the comparison might be inherited. */
6312 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6314 choose_reload_regs_init (chain, save_reload_reg_rtx);
6316 /* Process the reloads in order of preference just found.
6317 Beyond this point, subregs can be found in reload_reg_rtx.
6319 This used to look for an existing reloaded home for all of the
6320 reloads, and only then perform any new reloads. But that could lose
6321 if the reloads were done out of reg-class order because a later
6322 reload with a looser constraint might have an old home in a register
6323 needed by an earlier reload with a tighter constraint.
6325 To solve this, we make two passes over the reloads, in the order
6326 described above. In the first pass we try to inherit a reload
6327 from a previous insn. If there is a later reload that needs a
6328 class that is a proper subset of the class being processed, we must
6329 also allocate a spill register during the first pass.
6331 Then make a second pass over the reloads to allocate any reloads
6332 that haven't been given registers yet. */
6334 for (j = 0; j < n_reloads; j++)
6336 int r = reload_order[j];
6337 rtx search_equiv = NULL_RTX;
6339 /* Ignore reloads that got marked inoperative. */
6340 if (rld[r].out == 0 && rld[r].in == 0
6341 && ! rld[r].secondary_p)
6344 /* If find_reloads chose to use reload_in or reload_out as a reload
6345 register, we don't need to chose one. Otherwise, try even if it
6346 found one since we might save an insn if we find the value lying
6348 Try also when reload_in is a pseudo without a hard reg. */
6349 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6350 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6351 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6352 && !MEM_P (rld[r].in)
6353 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6356 #if 0 /* No longer needed for correct operation.
6357 It might give better code, or might not; worth an experiment? */
6358 /* If this is an optional reload, we can't inherit from earlier insns
6359 until we are sure that any non-optional reloads have been allocated.
6360 The following code takes advantage of the fact that optional reloads
6361 are at the end of reload_order. */
6362 if (rld[r].optional != 0)
6363 for (i = 0; i < j; i++)
6364 if ((rld[reload_order[i]].out != 0
6365 || rld[reload_order[i]].in != 0
6366 || rld[reload_order[i]].secondary_p)
6367 && ! rld[reload_order[i]].optional
6368 && rld[reload_order[i]].reg_rtx == 0)
6369 allocate_reload_reg (chain, reload_order[i], 0);
6372 /* First see if this pseudo is already available as reloaded
6373 for a previous insn. We cannot try to inherit for reloads
6374 that are smaller than the maximum number of registers needed
6375 for groups unless the register we would allocate cannot be used
6378 We could check here to see if this is a secondary reload for
6379 an object that is already in a register of the desired class.
6380 This would avoid the need for the secondary reload register.
6381 But this is complex because we can't easily determine what
6382 objects might want to be loaded via this reload. So let a
6383 register be allocated here. In `emit_reload_insns' we suppress
6384 one of the loads in the case described above. */
6390 enum machine_mode mode = VOIDmode;
6394 else if (REG_P (rld[r].in))
6396 regno = REGNO (rld[r].in);
6397 mode = GET_MODE (rld[r].in);
6399 else if (REG_P (rld[r].in_reg))
6401 regno = REGNO (rld[r].in_reg);
6402 mode = GET_MODE (rld[r].in_reg);
6404 else if (GET_CODE (rld[r].in_reg) == SUBREG
6405 && REG_P (SUBREG_REG (rld[r].in_reg)))
6407 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6408 if (regno < FIRST_PSEUDO_REGISTER)
6409 regno = subreg_regno (rld[r].in_reg);
6411 byte = SUBREG_BYTE (rld[r].in_reg);
6412 mode = GET_MODE (rld[r].in_reg);
6415 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6416 && REG_P (XEXP (rld[r].in_reg, 0)))
6418 regno = REGNO (XEXP (rld[r].in_reg, 0));
6419 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6420 rld[r].out = rld[r].in;
6424 /* This won't work, since REGNO can be a pseudo reg number.
6425 Also, it takes much more hair to keep track of all the things
6426 that can invalidate an inherited reload of part of a pseudoreg. */
6427 else if (GET_CODE (rld[r].in) == SUBREG
6428 && REG_P (SUBREG_REG (rld[r].in)))
6429 regno = subreg_regno (rld[r].in);
6433 && reg_last_reload_reg[regno] != 0
6434 #ifdef CANNOT_CHANGE_MODE_CLASS
6435 /* Verify that the register it's in can be used in
6437 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6438 GET_MODE (reg_last_reload_reg[regno]),
6443 enum reg_class rclass = rld[r].rclass, last_class;
6444 rtx last_reg = reg_last_reload_reg[regno];
6445 enum machine_mode need_mode;
6447 i = REGNO (last_reg);
6448 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6449 last_class = REGNO_REG_CLASS (i);
6455 = smallest_mode_for_size
6456 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6457 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6458 ? MODE_INT : GET_MODE_CLASS (mode));
6460 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6461 >= GET_MODE_SIZE (need_mode))
6462 && reg_reloaded_contents[i] == regno
6463 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6464 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6465 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6466 /* Even if we can't use this register as a reload
6467 register, we might use it for reload_override_in,
6468 if copying it to the desired class is cheap
6470 || ((register_move_cost (mode, last_class, rclass)
6471 < memory_move_cost (mode, rclass, true))
6472 && (secondary_reload_class (1, rclass, mode,
6475 #ifdef SECONDARY_MEMORY_NEEDED
6476 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6481 && (rld[r].nregs == max_group_size
6482 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6484 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6485 rld[r].when_needed, rld[r].in,
6488 /* If a group is needed, verify that all the subsequent
6489 registers still have their values intact. */
6490 int nr = hard_regno_nregs[i][rld[r].mode];
6493 for (k = 1; k < nr; k++)
6494 if (reg_reloaded_contents[i + k] != regno
6495 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6503 last_reg = (GET_MODE (last_reg) == mode
6504 ? last_reg : gen_rtx_REG (mode, i));
6507 for (k = 0; k < nr; k++)
6508 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6511 /* We found a register that contains the
6512 value we need. If this register is the
6513 same as an `earlyclobber' operand of the
6514 current insn, just mark it as a place to
6515 reload from since we can't use it as the
6516 reload register itself. */
6518 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6519 if (reg_overlap_mentioned_for_reload_p
6520 (reg_last_reload_reg[regno],
6521 reload_earlyclobbers[i1]))
6524 if (i1 != n_earlyclobbers
6525 || ! (free_for_value_p (i, rld[r].mode,
6527 rld[r].when_needed, rld[r].in,
6529 /* Don't use it if we'd clobber a pseudo reg. */
6530 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6532 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6533 /* Don't clobber the frame pointer. */
6534 || (i == HARD_FRAME_POINTER_REGNUM
6535 && frame_pointer_needed
6537 /* Don't really use the inherited spill reg
6538 if we need it wider than we've got it. */
6539 || (GET_MODE_SIZE (rld[r].mode)
6540 > GET_MODE_SIZE (mode))
6543 /* If find_reloads chose reload_out as reload
6544 register, stay with it - that leaves the
6545 inherited register for subsequent reloads. */
6546 || (rld[r].out && rld[r].reg_rtx
6547 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6549 if (! rld[r].optional)
6551 reload_override_in[r] = last_reg;
6552 reload_inheritance_insn[r]
6553 = reg_reloaded_insn[i];
6559 /* We can use this as a reload reg. */
6560 /* Mark the register as in use for this part of
6562 mark_reload_reg_in_use (i,
6566 rld[r].reg_rtx = last_reg;
6567 reload_inherited[r] = 1;
6568 reload_inheritance_insn[r]
6569 = reg_reloaded_insn[i];
6570 reload_spill_index[r] = i;
6571 for (k = 0; k < nr; k++)
6572 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6580 /* Here's another way to see if the value is already lying around. */
6583 && ! reload_inherited[r]
6585 && (CONSTANT_P (rld[r].in)
6586 || GET_CODE (rld[r].in) == PLUS
6587 || REG_P (rld[r].in)
6588 || MEM_P (rld[r].in))
6589 && (rld[r].nregs == max_group_size
6590 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6591 search_equiv = rld[r].in;
6596 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6597 -1, NULL, 0, rld[r].mode);
6603 regno = REGNO (equiv);
6606 /* This must be a SUBREG of a hard register.
6607 Make a new REG since this might be used in an
6608 address and not all machines support SUBREGs
6610 gcc_assert (GET_CODE (equiv) == SUBREG);
6611 regno = subreg_regno (equiv);
6612 equiv = gen_rtx_REG (rld[r].mode, regno);
6613 /* If we choose EQUIV as the reload register, but the
6614 loop below decides to cancel the inheritance, we'll
6615 end up reloading EQUIV in rld[r].mode, not the mode
6616 it had originally. That isn't safe when EQUIV isn't
6617 available as a spill register since its value might
6618 still be live at this point. */
6619 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6620 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6625 /* If we found a spill reg, reject it unless it is free
6626 and of the desired class. */
6630 int bad_for_class = 0;
6631 int max_regno = regno + rld[r].nregs;
6633 for (i = regno; i < max_regno; i++)
6635 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6637 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6642 && ! free_for_value_p (regno, rld[r].mode,
6643 rld[r].opnum, rld[r].when_needed,
6644 rld[r].in, rld[r].out, r, 1))
6649 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6652 /* We found a register that contains the value we need.
6653 If this register is the same as an `earlyclobber' operand
6654 of the current insn, just mark it as a place to reload from
6655 since we can't use it as the reload register itself. */
6658 for (i = 0; i < n_earlyclobbers; i++)
6659 if (reg_overlap_mentioned_for_reload_p (equiv,
6660 reload_earlyclobbers[i]))
6662 if (! rld[r].optional)
6663 reload_override_in[r] = equiv;
6668 /* If the equiv register we have found is explicitly clobbered
6669 in the current insn, it depends on the reload type if we
6670 can use it, use it for reload_override_in, or not at all.
6671 In particular, we then can't use EQUIV for a
6672 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6676 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6677 switch (rld[r].when_needed)
6679 case RELOAD_FOR_OTHER_ADDRESS:
6680 case RELOAD_FOR_INPADDR_ADDRESS:
6681 case RELOAD_FOR_INPUT_ADDRESS:
6682 case RELOAD_FOR_OPADDR_ADDR:
6685 case RELOAD_FOR_INPUT:
6686 case RELOAD_FOR_OPERAND_ADDRESS:
6687 if (! rld[r].optional)
6688 reload_override_in[r] = equiv;
6694 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6695 switch (rld[r].when_needed)
6697 case RELOAD_FOR_OTHER_ADDRESS:
6698 case RELOAD_FOR_INPADDR_ADDRESS:
6699 case RELOAD_FOR_INPUT_ADDRESS:
6700 case RELOAD_FOR_OPADDR_ADDR:
6701 case RELOAD_FOR_OPERAND_ADDRESS:
6702 case RELOAD_FOR_INPUT:
6705 if (! rld[r].optional)
6706 reload_override_in[r] = equiv;
6714 /* If we found an equivalent reg, say no code need be generated
6715 to load it, and use it as our reload reg. */
6717 && (regno != HARD_FRAME_POINTER_REGNUM
6718 || !frame_pointer_needed))
6720 int nr = hard_regno_nregs[regno][rld[r].mode];
6722 rld[r].reg_rtx = equiv;
6723 reload_spill_index[r] = regno;
6724 reload_inherited[r] = 1;
6726 /* If reg_reloaded_valid is not set for this register,
6727 there might be a stale spill_reg_store lying around.
6728 We must clear it, since otherwise emit_reload_insns
6729 might delete the store. */
6730 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6731 spill_reg_store[regno] = NULL_RTX;
6732 /* If any of the hard registers in EQUIV are spill
6733 registers, mark them as in use for this insn. */
6734 for (k = 0; k < nr; k++)
6736 i = spill_reg_order[regno + k];
6739 mark_reload_reg_in_use (regno, rld[r].opnum,
6742 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6749 /* If we found a register to use already, or if this is an optional
6750 reload, we are done. */
6751 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6755 /* No longer needed for correct operation. Might or might
6756 not give better code on the average. Want to experiment? */
6758 /* See if there is a later reload that has a class different from our
6759 class that intersects our class or that requires less register
6760 than our reload. If so, we must allocate a register to this
6761 reload now, since that reload might inherit a previous reload
6762 and take the only available register in our class. Don't do this
6763 for optional reloads since they will force all previous reloads
6764 to be allocated. Also don't do this for reloads that have been
6767 for (i = j + 1; i < n_reloads; i++)
6769 int s = reload_order[i];
6771 if ((rld[s].in == 0 && rld[s].out == 0
6772 && ! rld[s].secondary_p)
6776 if ((rld[s].rclass != rld[r].rclass
6777 && reg_classes_intersect_p (rld[r].rclass,
6779 || rld[s].nregs < rld[r].nregs)
6786 allocate_reload_reg (chain, r, j == n_reloads - 1);
6790 /* Now allocate reload registers for anything non-optional that
6791 didn't get one yet. */
6792 for (j = 0; j < n_reloads; j++)
6794 int r = reload_order[j];
6796 /* Ignore reloads that got marked inoperative. */
6797 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6800 /* Skip reloads that already have a register allocated or are
6802 if (rld[r].reg_rtx != 0 || rld[r].optional)
6805 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6809 /* If that loop got all the way, we have won. */
6816 /* Loop around and try without any inheritance. */
6821 /* First undo everything done by the failed attempt
6822 to allocate with inheritance. */
6823 choose_reload_regs_init (chain, save_reload_reg_rtx);
6825 /* Some sanity tests to verify that the reloads found in the first
6826 pass are identical to the ones we have now. */
6827 gcc_assert (chain->n_reloads == n_reloads);
6829 for (i = 0; i < n_reloads; i++)
6831 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6833 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6834 for (j = 0; j < n_spills; j++)
6835 if (spill_regs[j] == chain->rld[i].regno)
6836 if (! set_reload_reg (j, i))
6837 failed_reload (chain->insn, i);
6841 /* If we thought we could inherit a reload, because it seemed that
6842 nothing else wanted the same reload register earlier in the insn,
6843 verify that assumption, now that all reloads have been assigned.
6844 Likewise for reloads where reload_override_in has been set. */
6846 /* If doing expensive optimizations, do one preliminary pass that doesn't
6847 cancel any inheritance, but removes reloads that have been needed only
6848 for reloads that we know can be inherited. */
6849 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6851 for (j = 0; j < n_reloads; j++)
6853 int r = reload_order[j];
6855 if (reload_inherited[r] && rld[r].reg_rtx)
6856 check_reg = rld[r].reg_rtx;
6857 else if (reload_override_in[r]
6858 && (REG_P (reload_override_in[r])
6859 || GET_CODE (reload_override_in[r]) == SUBREG))
6860 check_reg = reload_override_in[r];
6863 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6864 rld[r].opnum, rld[r].when_needed, rld[r].in,
6865 (reload_inherited[r]
6866 ? rld[r].out : const0_rtx),
6871 reload_inherited[r] = 0;
6872 reload_override_in[r] = 0;
6874 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6875 reload_override_in, then we do not need its related
6876 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6877 likewise for other reload types.
6878 We handle this by removing a reload when its only replacement
6879 is mentioned in reload_in of the reload we are going to inherit.
6880 A special case are auto_inc expressions; even if the input is
6881 inherited, we still need the address for the output. We can
6882 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6883 If we succeeded removing some reload and we are doing a preliminary
6884 pass just to remove such reloads, make another pass, since the
6885 removal of one reload might allow us to inherit another one. */
6887 && rld[r].out != rld[r].in
6888 && remove_address_replacements (rld[r].in) && pass)
6893 /* Now that reload_override_in is known valid,
6894 actually override reload_in. */
6895 for (j = 0; j < n_reloads; j++)
6896 if (reload_override_in[j])
6897 rld[j].in = reload_override_in[j];
6899 /* If this reload won't be done because it has been canceled or is
6900 optional and not inherited, clear reload_reg_rtx so other
6901 routines (such as subst_reloads) don't get confused. */
6902 for (j = 0; j < n_reloads; j++)
6903 if (rld[j].reg_rtx != 0
6904 && ((rld[j].optional && ! reload_inherited[j])
6905 || (rld[j].in == 0 && rld[j].out == 0
6906 && ! rld[j].secondary_p)))
6908 int regno = true_regnum (rld[j].reg_rtx);
6910 if (spill_reg_order[regno] >= 0)
6911 clear_reload_reg_in_use (regno, rld[j].opnum,
6912 rld[j].when_needed, rld[j].mode);
6914 reload_spill_index[j] = -1;
6917 /* Record which pseudos and which spill regs have output reloads. */
6918 for (j = 0; j < n_reloads; j++)
6920 int r = reload_order[j];
6922 i = reload_spill_index[r];
6924 /* I is nonneg if this reload uses a register.
6925 If rld[r].reg_rtx is 0, this is an optional reload
6926 that we opted to ignore. */
6927 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6928 && rld[r].reg_rtx != 0)
6930 int nregno = REGNO (rld[r].out_reg);
6933 if (nregno < FIRST_PSEUDO_REGISTER)
6934 nr = hard_regno_nregs[nregno][rld[r].mode];
6937 SET_REGNO_REG_SET (®_has_output_reload,
6941 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
6943 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6944 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6945 || rld[r].when_needed == RELOAD_FOR_INSN);
6950 /* Deallocate the reload register for reload R. This is called from
6951 remove_address_replacements. */
6954 deallocate_reload_reg (int r)
6958 if (! rld[r].reg_rtx)
6960 regno = true_regnum (rld[r].reg_rtx);
6962 if (spill_reg_order[regno] >= 0)
6963 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6965 reload_spill_index[r] = -1;
6968 /* These arrays are filled by emit_reload_insns and its subroutines. */
6969 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6970 static rtx other_input_address_reload_insns = 0;
6971 static rtx other_input_reload_insns = 0;
6972 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6973 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6974 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6975 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6976 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6977 static rtx operand_reload_insns = 0;
6978 static rtx other_operand_reload_insns = 0;
6979 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6981 /* Values to be put in spill_reg_store are put here first. */
6982 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6983 static HARD_REG_SET reg_reloaded_died;
6985 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6986 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6987 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6988 adjusted register, and return true. Otherwise, return false. */
6990 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6991 enum reg_class new_class,
6992 enum machine_mode new_mode)
6997 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6999 unsigned regno = REGNO (reg);
7001 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7003 if (GET_MODE (reg) != new_mode)
7005 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7007 if (hard_regno_nregs[regno][new_mode]
7008 > hard_regno_nregs[regno][GET_MODE (reg)])
7010 reg = reload_adjust_reg_for_mode (reg, new_mode);
7018 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7019 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7020 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7021 adjusted register, and return true. Otherwise, return false. */
7023 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7024 enum insn_code icode)
7027 enum reg_class new_class = scratch_reload_class (icode);
7028 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7030 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7031 new_class, new_mode);
7034 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7035 has the number J. OLD contains the value to be used as input. */
7038 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7041 rtx insn = chain->insn;
7043 rtx oldequiv_reg = 0;
7046 enum machine_mode mode;
7049 /* delete_output_reload is only invoked properly if old contains
7050 the original pseudo register. Since this is replaced with a
7051 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7052 find the pseudo in RELOAD_IN_REG. */
7053 if (reload_override_in[j]
7054 && REG_P (rl->in_reg))
7061 else if (REG_P (oldequiv))
7062 oldequiv_reg = oldequiv;
7063 else if (GET_CODE (oldequiv) == SUBREG)
7064 oldequiv_reg = SUBREG_REG (oldequiv);
7066 reloadreg = reload_reg_rtx_for_input[j];
7067 mode = GET_MODE (reloadreg);
7069 /* If we are reloading from a register that was recently stored in
7070 with an output-reload, see if we can prove there was
7071 actually no need to store the old value in it. */
7073 if (optimize && REG_P (oldequiv)
7074 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7075 && spill_reg_store[REGNO (oldequiv)]
7077 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7078 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7080 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7082 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7085 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7086 oldequiv = SUBREG_REG (oldequiv);
7087 if (GET_MODE (oldequiv) != VOIDmode
7088 && mode != GET_MODE (oldequiv))
7089 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7091 /* Switch to the right place to emit the reload insns. */
7092 switch (rl->when_needed)
7095 where = &other_input_reload_insns;
7097 case RELOAD_FOR_INPUT:
7098 where = &input_reload_insns[rl->opnum];
7100 case RELOAD_FOR_INPUT_ADDRESS:
7101 where = &input_address_reload_insns[rl->opnum];
7103 case RELOAD_FOR_INPADDR_ADDRESS:
7104 where = &inpaddr_address_reload_insns[rl->opnum];
7106 case RELOAD_FOR_OUTPUT_ADDRESS:
7107 where = &output_address_reload_insns[rl->opnum];
7109 case RELOAD_FOR_OUTADDR_ADDRESS:
7110 where = &outaddr_address_reload_insns[rl->opnum];
7112 case RELOAD_FOR_OPERAND_ADDRESS:
7113 where = &operand_reload_insns;
7115 case RELOAD_FOR_OPADDR_ADDR:
7116 where = &other_operand_reload_insns;
7118 case RELOAD_FOR_OTHER_ADDRESS:
7119 where = &other_input_address_reload_insns;
7125 push_to_sequence (*where);
7127 /* Auto-increment addresses must be reloaded in a special way. */
7128 if (rl->out && ! rl->out_reg)
7130 /* We are not going to bother supporting the case where a
7131 incremented register can't be copied directly from
7132 OLDEQUIV since this seems highly unlikely. */
7133 gcc_assert (rl->secondary_in_reload < 0);
7135 if (reload_inherited[j])
7136 oldequiv = reloadreg;
7138 old = XEXP (rl->in_reg, 0);
7140 /* Prevent normal processing of this reload. */
7142 /* Output a special code sequence for this case, and forget about
7143 spill reg information. */
7144 new_spill_reg_store[REGNO (reloadreg)] = NULL;
7145 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7148 /* If we are reloading a pseudo-register that was set by the previous
7149 insn, see if we can get rid of that pseudo-register entirely
7150 by redirecting the previous insn into our reload register. */
7152 else if (optimize && REG_P (old)
7153 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7154 && dead_or_set_p (insn, old)
7155 /* This is unsafe if some other reload
7156 uses the same reg first. */
7157 && ! conflicts_with_override (reloadreg)
7158 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7159 rl->when_needed, old, rl->out, j, 0))
7161 rtx temp = PREV_INSN (insn);
7162 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7163 temp = PREV_INSN (temp);
7165 && NONJUMP_INSN_P (temp)
7166 && GET_CODE (PATTERN (temp)) == SET
7167 && SET_DEST (PATTERN (temp)) == old
7168 /* Make sure we can access insn_operand_constraint. */
7169 && asm_noperands (PATTERN (temp)) < 0
7170 /* This is unsafe if operand occurs more than once in current
7171 insn. Perhaps some occurrences aren't reloaded. */
7172 && count_occurrences (PATTERN (insn), old, 0) == 1)
7174 rtx old = SET_DEST (PATTERN (temp));
7175 /* Store into the reload register instead of the pseudo. */
7176 SET_DEST (PATTERN (temp)) = reloadreg;
7178 /* Verify that resulting insn is valid. */
7179 extract_insn (temp);
7180 if (constrain_operands (1))
7182 /* If the previous insn is an output reload, the source is
7183 a reload register, and its spill_reg_store entry will
7184 contain the previous destination. This is now
7186 if (REG_P (SET_SRC (PATTERN (temp)))
7187 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7189 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7190 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7193 /* If these are the only uses of the pseudo reg,
7194 pretend for GDB it lives in the reload reg we used. */
7195 if (REG_N_DEATHS (REGNO (old)) == 1
7196 && REG_N_SETS (REGNO (old)) == 1)
7198 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7199 if (ira_conflicts_p)
7200 /* Inform IRA about the change. */
7201 ira_mark_allocation_change (REGNO (old));
7202 alter_reg (REGNO (old), -1, false);
7206 /* Adjust any debug insns between temp and insn. */
7207 while ((temp = NEXT_INSN (temp)) != insn)
7208 if (DEBUG_INSN_P (temp))
7209 replace_rtx (PATTERN (temp), old, reloadreg);
7211 gcc_assert (NOTE_P (temp));
7215 SET_DEST (PATTERN (temp)) = old;
7220 /* We can't do that, so output an insn to load RELOADREG. */
7222 /* If we have a secondary reload, pick up the secondary register
7223 and icode, if any. If OLDEQUIV and OLD are different or
7224 if this is an in-out reload, recompute whether or not we
7225 still need a secondary register and what the icode should
7226 be. If we still need a secondary register and the class or
7227 icode is different, go back to reloading from OLD if using
7228 OLDEQUIV means that we got the wrong type of register. We
7229 cannot have different class or icode due to an in-out reload
7230 because we don't make such reloads when both the input and
7231 output need secondary reload registers. */
7233 if (! special && rl->secondary_in_reload >= 0)
7235 rtx second_reload_reg = 0;
7236 rtx third_reload_reg = 0;
7237 int secondary_reload = rl->secondary_in_reload;
7238 rtx real_oldequiv = oldequiv;
7241 enum insn_code icode;
7242 enum insn_code tertiary_icode = CODE_FOR_nothing;
7244 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7245 and similarly for OLD.
7246 See comments in get_secondary_reload in reload.c. */
7247 /* If it is a pseudo that cannot be replaced with its
7248 equivalent MEM, we must fall back to reload_in, which
7249 will have all the necessary substitutions registered.
7250 Likewise for a pseudo that can't be replaced with its
7251 equivalent constant.
7253 Take extra care for subregs of such pseudos. Note that
7254 we cannot use reg_equiv_mem in this case because it is
7255 not in the right mode. */
7258 if (GET_CODE (tmp) == SUBREG)
7259 tmp = SUBREG_REG (tmp);
7261 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7262 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7263 || reg_equiv_constant (REGNO (tmp)) != 0))
7265 if (! reg_equiv_mem (REGNO (tmp))
7266 || num_not_at_initial_offset
7267 || GET_CODE (oldequiv) == SUBREG)
7268 real_oldequiv = rl->in;
7270 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7274 if (GET_CODE (tmp) == SUBREG)
7275 tmp = SUBREG_REG (tmp);
7277 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7278 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7279 || reg_equiv_constant (REGNO (tmp)) != 0))
7281 if (! reg_equiv_mem (REGNO (tmp))
7282 || num_not_at_initial_offset
7283 || GET_CODE (old) == SUBREG)
7286 real_old = reg_equiv_mem (REGNO (tmp));
7289 second_reload_reg = rld[secondary_reload].reg_rtx;
7290 if (rld[secondary_reload].secondary_in_reload >= 0)
7292 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7294 third_reload_reg = rld[tertiary_reload].reg_rtx;
7295 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7296 /* We'd have to add more code for quartary reloads. */
7297 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7299 icode = rl->secondary_in_icode;
7301 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7302 || (rl->in != 0 && rl->out != 0))
7304 secondary_reload_info sri, sri2;
7305 enum reg_class new_class, new_t_class;
7307 sri.icode = CODE_FOR_nothing;
7308 sri.prev_sri = NULL;
7310 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7314 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7315 second_reload_reg = 0;
7316 else if (new_class == NO_REGS)
7318 if (reload_adjust_reg_for_icode (&second_reload_reg,
7320 (enum insn_code) sri.icode))
7322 icode = (enum insn_code) sri.icode;
7323 third_reload_reg = 0;
7328 real_oldequiv = real_old;
7331 else if (sri.icode != CODE_FOR_nothing)
7332 /* We currently lack a way to express this in reloads. */
7336 sri2.icode = CODE_FOR_nothing;
7337 sri2.prev_sri = &sri;
7339 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7342 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7344 if (reload_adjust_reg_for_temp (&second_reload_reg,
7348 third_reload_reg = 0;
7349 tertiary_icode = (enum insn_code) sri2.icode;
7354 real_oldequiv = real_old;
7357 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7359 rtx intermediate = second_reload_reg;
7361 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7363 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7367 second_reload_reg = intermediate;
7368 tertiary_icode = (enum insn_code) sri2.icode;
7373 real_oldequiv = real_old;
7376 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7378 rtx intermediate = second_reload_reg;
7380 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7382 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7385 second_reload_reg = intermediate;
7386 tertiary_icode = (enum insn_code) sri2.icode;
7391 real_oldequiv = real_old;
7396 /* This could be handled more intelligently too. */
7398 real_oldequiv = real_old;
7403 /* If we still need a secondary reload register, check
7404 to see if it is being used as a scratch or intermediate
7405 register and generate code appropriately. If we need
7406 a scratch register, use REAL_OLDEQUIV since the form of
7407 the insn may depend on the actual address if it is
7410 if (second_reload_reg)
7412 if (icode != CODE_FOR_nothing)
7414 /* We'd have to add extra code to handle this case. */
7415 gcc_assert (!third_reload_reg);
7417 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7418 second_reload_reg));
7423 /* See if we need a scratch register to load the
7424 intermediate register (a tertiary reload). */
7425 if (tertiary_icode != CODE_FOR_nothing)
7427 emit_insn ((GEN_FCN (tertiary_icode)
7428 (second_reload_reg, real_oldequiv,
7429 third_reload_reg)));
7431 else if (third_reload_reg)
7433 gen_reload (third_reload_reg, real_oldequiv,
7436 gen_reload (second_reload_reg, third_reload_reg,
7441 gen_reload (second_reload_reg, real_oldequiv,
7445 oldequiv = second_reload_reg;
7450 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7452 rtx real_oldequiv = oldequiv;
7454 if ((REG_P (oldequiv)
7455 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7456 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7457 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7458 || (GET_CODE (oldequiv) == SUBREG
7459 && REG_P (SUBREG_REG (oldequiv))
7460 && (REGNO (SUBREG_REG (oldequiv))
7461 >= FIRST_PSEUDO_REGISTER)
7462 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7463 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7464 || (CONSTANT_P (oldequiv)
7465 && (targetm.preferred_reload_class (oldequiv,
7466 REGNO_REG_CLASS (REGNO (reloadreg)))
7468 real_oldequiv = rl->in;
7469 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7473 if (cfun->can_throw_non_call_exceptions)
7474 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7476 /* End this sequence. */
7477 *where = get_insns ();
7480 /* Update reload_override_in so that delete_address_reloads_1
7481 can see the actual register usage. */
7483 reload_override_in[j] = oldequiv;
7486 /* Generate insns to for the output reload RL, which is for the insn described
7487 by CHAIN and has the number J. */
7489 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7493 rtx insn = chain->insn;
7496 enum machine_mode mode;
7500 if (rl->when_needed == RELOAD_OTHER)
7503 push_to_sequence (output_reload_insns[rl->opnum]);
7505 rl_reg_rtx = reload_reg_rtx_for_output[j];
7506 mode = GET_MODE (rl_reg_rtx);
7508 reloadreg = rl_reg_rtx;
7510 /* If we need two reload regs, set RELOADREG to the intermediate
7511 one, since it will be stored into OLD. We might need a secondary
7512 register only for an input reload, so check again here. */
7514 if (rl->secondary_out_reload >= 0)
7517 int secondary_reload = rl->secondary_out_reload;
7518 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7520 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7521 && reg_equiv_mem (REGNO (old)) != 0)
7522 real_old = reg_equiv_mem (REGNO (old));
7524 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7526 rtx second_reloadreg = reloadreg;
7527 reloadreg = rld[secondary_reload].reg_rtx;
7529 /* See if RELOADREG is to be used as a scratch register
7530 or as an intermediate register. */
7531 if (rl->secondary_out_icode != CODE_FOR_nothing)
7533 /* We'd have to add extra code to handle this case. */
7534 gcc_assert (tertiary_reload < 0);
7536 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7537 (real_old, second_reloadreg, reloadreg)));
7542 /* See if we need both a scratch and intermediate reload
7545 enum insn_code tertiary_icode
7546 = rld[secondary_reload].secondary_out_icode;
7548 /* We'd have to add more code for quartary reloads. */
7549 gcc_assert (tertiary_reload < 0
7550 || rld[tertiary_reload].secondary_out_reload < 0);
7552 if (GET_MODE (reloadreg) != mode)
7553 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7555 if (tertiary_icode != CODE_FOR_nothing)
7557 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7560 /* Copy primary reload reg to secondary reload reg.
7561 (Note that these have been swapped above, then
7562 secondary reload reg to OLD using our insn.) */
7564 /* If REAL_OLD is a paradoxical SUBREG, remove it
7565 and try to put the opposite SUBREG on
7567 if (GET_CODE (real_old) == SUBREG
7568 && (GET_MODE_SIZE (GET_MODE (real_old))
7569 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7570 && 0 != (tem = gen_lowpart_common
7571 (GET_MODE (SUBREG_REG (real_old)),
7573 real_old = SUBREG_REG (real_old), reloadreg = tem;
7575 gen_reload (reloadreg, second_reloadreg,
7576 rl->opnum, rl->when_needed);
7577 emit_insn ((GEN_FCN (tertiary_icode)
7578 (real_old, reloadreg, third_reloadreg)));
7584 /* Copy between the reload regs here and then to
7587 gen_reload (reloadreg, second_reloadreg,
7588 rl->opnum, rl->when_needed);
7589 if (tertiary_reload >= 0)
7591 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7593 gen_reload (third_reloadreg, reloadreg,
7594 rl->opnum, rl->when_needed);
7595 reloadreg = third_reloadreg;
7602 /* Output the last reload insn. */
7607 /* Don't output the last reload if OLD is not the dest of
7608 INSN and is in the src and is clobbered by INSN. */
7609 if (! flag_expensive_optimizations
7611 || !(set = single_set (insn))
7612 || rtx_equal_p (old, SET_DEST (set))
7613 || !reg_mentioned_p (old, SET_SRC (set))
7614 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7615 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7616 gen_reload (old, reloadreg, rl->opnum,
7620 /* Look at all insns we emitted, just to be safe. */
7621 for (p = get_insns (); p; p = NEXT_INSN (p))
7624 rtx pat = PATTERN (p);
7626 /* If this output reload doesn't come from a spill reg,
7627 clear any memory of reloaded copies of the pseudo reg.
7628 If this output reload comes from a spill reg,
7629 reg_has_output_reload will make this do nothing. */
7630 note_stores (pat, forget_old_reloads_1, NULL);
7632 if (reg_mentioned_p (rl_reg_rtx, pat))
7634 rtx set = single_set (insn);
7635 if (reload_spill_index[j] < 0
7637 && SET_SRC (set) == rl_reg_rtx)
7639 int src = REGNO (SET_SRC (set));
7641 reload_spill_index[j] = src;
7642 SET_HARD_REG_BIT (reg_is_output_reload, src);
7643 if (find_regno_note (insn, REG_DEAD, src))
7644 SET_HARD_REG_BIT (reg_reloaded_died, src);
7646 if (HARD_REGISTER_P (rl_reg_rtx))
7648 int s = rl->secondary_out_reload;
7649 set = single_set (p);
7650 /* If this reload copies only to the secondary reload
7651 register, the secondary reload does the actual
7653 if (s >= 0 && set == NULL_RTX)
7654 /* We can't tell what function the secondary reload
7655 has and where the actual store to the pseudo is
7656 made; leave new_spill_reg_store alone. */
7659 && SET_SRC (set) == rl_reg_rtx
7660 && SET_DEST (set) == rld[s].reg_rtx)
7662 /* Usually the next instruction will be the
7663 secondary reload insn; if we can confirm
7664 that it is, setting new_spill_reg_store to
7665 that insn will allow an extra optimization. */
7666 rtx s_reg = rld[s].reg_rtx;
7667 rtx next = NEXT_INSN (p);
7668 rld[s].out = rl->out;
7669 rld[s].out_reg = rl->out_reg;
7670 set = single_set (next);
7671 if (set && SET_SRC (set) == s_reg
7672 && ! new_spill_reg_store[REGNO (s_reg)])
7674 SET_HARD_REG_BIT (reg_is_output_reload,
7676 new_spill_reg_store[REGNO (s_reg)] = next;
7680 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7685 if (rl->when_needed == RELOAD_OTHER)
7687 emit_insn (other_output_reload_insns[rl->opnum]);
7688 other_output_reload_insns[rl->opnum] = get_insns ();
7691 output_reload_insns[rl->opnum] = get_insns ();
7693 if (cfun->can_throw_non_call_exceptions)
7694 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7699 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7700 and has the number J. */
7702 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7704 rtx insn = chain->insn;
7705 rtx old = (rl->in && MEM_P (rl->in)
7706 ? rl->in_reg : rl->in);
7707 rtx reg_rtx = rl->reg_rtx;
7711 enum machine_mode mode;
7713 /* Determine the mode to reload in.
7714 This is very tricky because we have three to choose from.
7715 There is the mode the insn operand wants (rl->inmode).
7716 There is the mode of the reload register RELOADREG.
7717 There is the intrinsic mode of the operand, which we could find
7718 by stripping some SUBREGs.
7719 It turns out that RELOADREG's mode is irrelevant:
7720 we can change that arbitrarily.
7722 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7723 then the reload reg may not support QImode moves, so use SImode.
7724 If foo is in memory due to spilling a pseudo reg, this is safe,
7725 because the QImode value is in the least significant part of a
7726 slot big enough for a SImode. If foo is some other sort of
7727 memory reference, then it is impossible to reload this case,
7728 so previous passes had better make sure this never happens.
7730 Then consider a one-word union which has SImode and one of its
7731 members is a float, being fetched as (SUBREG:SF union:SI).
7732 We must fetch that as SFmode because we could be loading into
7733 a float-only register. In this case OLD's mode is correct.
7735 Consider an immediate integer: it has VOIDmode. Here we need
7736 to get a mode from something else.
7738 In some cases, there is a fourth mode, the operand's
7739 containing mode. If the insn specifies a containing mode for
7740 this operand, it overrides all others.
7742 I am not sure whether the algorithm here is always right,
7743 but it does the right things in those cases. */
7745 mode = GET_MODE (old);
7746 if (mode == VOIDmode)
7749 /* We cannot use gen_lowpart_common since it can do the wrong thing
7750 when REG_RTX has a multi-word mode. Note that REG_RTX must
7751 always be a REG here. */
7752 if (GET_MODE (reg_rtx) != mode)
7753 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7755 reload_reg_rtx_for_input[j] = reg_rtx;
7758 /* AUTO_INC reloads need to be handled even if inherited. We got an
7759 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7760 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7761 && ! rtx_equal_p (reg_rtx, old)
7763 emit_input_reload_insns (chain, rld + j, old, j);
7765 /* When inheriting a wider reload, we have a MEM in rl->in,
7766 e.g. inheriting a SImode output reload for
7767 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7768 if (optimize && reload_inherited[j] && rl->in
7770 && MEM_P (rl->in_reg)
7771 && reload_spill_index[j] >= 0
7772 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7773 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7775 /* If we are reloading a register that was recently stored in with an
7776 output-reload, see if we can prove there was
7777 actually no need to store the old value in it. */
7780 && (reload_inherited[j] || reload_override_in[j])
7783 && spill_reg_store[REGNO (reg_rtx)] != 0
7785 /* There doesn't seem to be any reason to restrict this to pseudos
7786 and doing so loses in the case where we are copying from a
7787 register of the wrong class. */
7788 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7790 /* The insn might have already some references to stackslots
7791 replaced by MEMs, while reload_out_reg still names the
7793 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7794 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7795 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7798 /* Do output reloading for reload RL, which is for the insn described by
7799 CHAIN and has the number J.
7800 ??? At some point we need to support handling output reloads of
7801 JUMP_INSNs or insns that set cc0. */
7803 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7806 rtx insn = chain->insn;
7807 /* If this is an output reload that stores something that is
7808 not loaded in this same reload, see if we can eliminate a previous
7810 rtx pseudo = rl->out_reg;
7811 rtx reg_rtx = rl->reg_rtx;
7813 if (rl->out && reg_rtx)
7815 enum machine_mode mode;
7817 /* Determine the mode to reload in.
7818 See comments above (for input reloading). */
7819 mode = GET_MODE (rl->out);
7820 if (mode == VOIDmode)
7822 /* VOIDmode should never happen for an output. */
7823 if (asm_noperands (PATTERN (insn)) < 0)
7824 /* It's the compiler's fault. */
7825 fatal_insn ("VOIDmode on an output", insn);
7826 error_for_asm (insn, "output operand is constant in %<asm%>");
7827 /* Prevent crash--use something we know is valid. */
7829 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7831 if (GET_MODE (reg_rtx) != mode)
7832 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7834 reload_reg_rtx_for_output[j] = reg_rtx;
7839 && ! rtx_equal_p (rl->in_reg, pseudo)
7840 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7841 && reg_last_reload_reg[REGNO (pseudo)])
7843 int pseudo_no = REGNO (pseudo);
7844 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7846 /* We don't need to test full validity of last_regno for
7847 inherit here; we only want to know if the store actually
7848 matches the pseudo. */
7849 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7850 && reg_reloaded_contents[last_regno] == pseudo_no
7851 && spill_reg_store[last_regno]
7852 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7853 delete_output_reload (insn, j, last_regno, reg_rtx);
7859 || rtx_equal_p (old, reg_rtx))
7862 /* An output operand that dies right away does need a reload,
7863 but need not be copied from it. Show the new location in the
7865 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7866 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7868 XEXP (note, 0) = reg_rtx;
7871 /* Likewise for a SUBREG of an operand that dies. */
7872 else if (GET_CODE (old) == SUBREG
7873 && REG_P (SUBREG_REG (old))
7874 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7877 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7880 else if (GET_CODE (old) == SCRATCH)
7881 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7882 but we don't want to make an output reload. */
7885 /* If is a JUMP_INSN, we can't support output reloads yet. */
7886 gcc_assert (NONJUMP_INSN_P (insn));
7888 emit_output_reload_insns (chain, rld + j, j);
7891 /* A reload copies values of MODE from register SRC to register DEST.
7892 Return true if it can be treated for inheritance purposes like a
7893 group of reloads, each one reloading a single hard register. The
7894 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7895 occupy the same number of hard registers. */
7898 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7899 int src ATTRIBUTE_UNUSED,
7900 enum machine_mode mode ATTRIBUTE_UNUSED)
7902 #ifdef CANNOT_CHANGE_MODE_CLASS
7903 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7904 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7910 /* Output insns to reload values in and out of the chosen reload regs. */
7913 emit_reload_insns (struct insn_chain *chain)
7915 rtx insn = chain->insn;
7919 CLEAR_HARD_REG_SET (reg_reloaded_died);
7921 for (j = 0; j < reload_n_operands; j++)
7922 input_reload_insns[j] = input_address_reload_insns[j]
7923 = inpaddr_address_reload_insns[j]
7924 = output_reload_insns[j] = output_address_reload_insns[j]
7925 = outaddr_address_reload_insns[j]
7926 = other_output_reload_insns[j] = 0;
7927 other_input_address_reload_insns = 0;
7928 other_input_reload_insns = 0;
7929 operand_reload_insns = 0;
7930 other_operand_reload_insns = 0;
7932 /* Dump reloads into the dump file. */
7935 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7936 debug_reload_to_stream (dump_file);
7939 /* Now output the instructions to copy the data into and out of the
7940 reload registers. Do these in the order that the reloads were reported,
7941 since reloads of base and index registers precede reloads of operands
7942 and the operands may need the base and index registers reloaded. */
7944 for (j = 0; j < n_reloads; j++)
7946 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7950 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7951 new_spill_reg_store[i] = 0;
7954 do_input_reload (chain, rld + j, j);
7955 do_output_reload (chain, rld + j, j);
7958 /* Now write all the insns we made for reloads in the order expected by
7959 the allocation functions. Prior to the insn being reloaded, we write
7960 the following reloads:
7962 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7964 RELOAD_OTHER reloads.
7966 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7967 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7968 RELOAD_FOR_INPUT reload for the operand.
7970 RELOAD_FOR_OPADDR_ADDRS reloads.
7972 RELOAD_FOR_OPERAND_ADDRESS reloads.
7974 After the insn being reloaded, we write the following:
7976 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7977 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7978 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7979 reloads for the operand. The RELOAD_OTHER output reloads are
7980 output in descending order by reload number. */
7982 emit_insn_before (other_input_address_reload_insns, insn);
7983 emit_insn_before (other_input_reload_insns, insn);
7985 for (j = 0; j < reload_n_operands; j++)
7987 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7988 emit_insn_before (input_address_reload_insns[j], insn);
7989 emit_insn_before (input_reload_insns[j], insn);
7992 emit_insn_before (other_operand_reload_insns, insn);
7993 emit_insn_before (operand_reload_insns, insn);
7995 for (j = 0; j < reload_n_operands; j++)
7997 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7998 x = emit_insn_after (output_address_reload_insns[j], x);
7999 x = emit_insn_after (output_reload_insns[j], x);
8000 emit_insn_after (other_output_reload_insns[j], x);
8003 /* For all the spill regs newly reloaded in this instruction,
8004 record what they were reloaded from, so subsequent instructions
8005 can inherit the reloads.
8007 Update spill_reg_store for the reloads of this insn.
8008 Copy the elements that were updated in the loop above. */
8010 for (j = 0; j < n_reloads; j++)
8012 int r = reload_order[j];
8013 int i = reload_spill_index[r];
8015 /* If this is a non-inherited input reload from a pseudo, we must
8016 clear any memory of a previous store to the same pseudo. Only do
8017 something if there will not be an output reload for the pseudo
8019 if (rld[r].in_reg != 0
8020 && ! (reload_inherited[r] || reload_override_in[r]))
8022 rtx reg = rld[r].in_reg;
8024 if (GET_CODE (reg) == SUBREG)
8025 reg = SUBREG_REG (reg);
8028 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8029 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8031 int nregno = REGNO (reg);
8033 if (reg_last_reload_reg[nregno])
8035 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8037 if (reg_reloaded_contents[last_regno] == nregno)
8038 spill_reg_store[last_regno] = 0;
8043 /* I is nonneg if this reload used a register.
8044 If rld[r].reg_rtx is 0, this is an optional reload
8045 that we opted to ignore. */
8047 if (i >= 0 && rld[r].reg_rtx != 0)
8049 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8052 /* For a multi register reload, we need to check if all or part
8053 of the value lives to the end. */
8054 for (k = 0; k < nr; k++)
8055 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
8056 rld[r].when_needed))
8057 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8059 /* Maybe the spill reg contains a copy of reload_out. */
8061 && (REG_P (rld[r].out)
8063 ? REG_P (rld[r].out_reg)
8064 /* The reload value is an auto-modification of
8065 some kind. For PRE_INC, POST_INC, PRE_DEC
8066 and POST_DEC, we record an equivalence
8067 between the reload register and the operand
8068 on the optimistic assumption that we can make
8069 the equivalence hold. reload_as_needed must
8070 then either make it hold or invalidate the
8073 PRE_MODIFY and POST_MODIFY addresses are reloaded
8074 somewhat differently, and allowing them here leads
8076 : (GET_CODE (rld[r].out) != POST_MODIFY
8077 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8080 enum machine_mode mode;
8083 reg = reload_reg_rtx_for_output[r];
8084 mode = GET_MODE (reg);
8085 regno = REGNO (reg);
8086 nregs = hard_regno_nregs[regno][mode];
8087 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8088 rld[r].when_needed))
8090 rtx out = (REG_P (rld[r].out)
8094 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8095 int out_regno = REGNO (out);
8096 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8097 : hard_regno_nregs[out_regno][mode]);
8100 spill_reg_store[regno] = new_spill_reg_store[regno];
8101 spill_reg_stored_to[regno] = out;
8102 reg_last_reload_reg[out_regno] = reg;
8104 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8105 && nregs == out_nregs
8106 && inherit_piecemeal_p (out_regno, regno, mode));
8108 /* If OUT_REGNO is a hard register, it may occupy more than
8109 one register. If it does, say what is in the
8110 rest of the registers assuming that both registers
8111 agree on how many words the object takes. If not,
8112 invalidate the subsequent registers. */
8114 if (HARD_REGISTER_NUM_P (out_regno))
8115 for (k = 1; k < out_nregs; k++)
8116 reg_last_reload_reg[out_regno + k]
8117 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8119 /* Now do the inverse operation. */
8120 for (k = 0; k < nregs; k++)
8122 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8123 reg_reloaded_contents[regno + k]
8124 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8127 reg_reloaded_insn[regno + k] = insn;
8128 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8129 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8130 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8133 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8138 /* Maybe the spill reg contains a copy of reload_in. Only do
8139 something if there will not be an output reload for
8140 the register being reloaded. */
8141 else if (rld[r].out_reg == 0
8143 && ((REG_P (rld[r].in)
8144 && !HARD_REGISTER_P (rld[r].in)
8145 && !REGNO_REG_SET_P (®_has_output_reload,
8147 || (REG_P (rld[r].in_reg)
8148 && !REGNO_REG_SET_P (®_has_output_reload,
8149 REGNO (rld[r].in_reg))))
8150 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8153 enum machine_mode mode;
8156 reg = reload_reg_rtx_for_input[r];
8157 mode = GET_MODE (reg);
8158 regno = REGNO (reg);
8159 nregs = hard_regno_nregs[regno][mode];
8160 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
8161 rld[r].when_needed))
8168 if (REG_P (rld[r].in)
8169 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8171 else if (REG_P (rld[r].in_reg))
8174 in = XEXP (rld[r].in_reg, 0);
8175 in_regno = REGNO (in);
8177 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8178 : hard_regno_nregs[in_regno][mode]);
8180 reg_last_reload_reg[in_regno] = reg;
8182 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8183 && nregs == in_nregs
8184 && inherit_piecemeal_p (regno, in_regno, mode));
8186 if (HARD_REGISTER_NUM_P (in_regno))
8187 for (k = 1; k < in_nregs; k++)
8188 reg_last_reload_reg[in_regno + k]
8189 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8191 /* Unless we inherited this reload, show we haven't
8192 recently done a store.
8193 Previous stores of inherited auto_inc expressions
8194 also have to be discarded. */
8195 if (! reload_inherited[r]
8196 || (rld[r].out && ! rld[r].out_reg))
8197 spill_reg_store[regno] = 0;
8199 for (k = 0; k < nregs; k++)
8201 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8202 reg_reloaded_contents[regno + k]
8203 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8206 reg_reloaded_insn[regno + k] = insn;
8207 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8208 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8209 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8212 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8219 /* The following if-statement was #if 0'd in 1.34 (or before...).
8220 It's reenabled in 1.35 because supposedly nothing else
8221 deals with this problem. */
8223 /* If a register gets output-reloaded from a non-spill register,
8224 that invalidates any previous reloaded copy of it.
8225 But forget_old_reloads_1 won't get to see it, because
8226 it thinks only about the original insn. So invalidate it here.
8227 Also do the same thing for RELOAD_OTHER constraints where the
8228 output is discarded. */
8230 && ((rld[r].out != 0
8231 && (REG_P (rld[r].out)
8232 || (MEM_P (rld[r].out)
8233 && REG_P (rld[r].out_reg))))
8234 || (rld[r].out == 0 && rld[r].out_reg
8235 && REG_P (rld[r].out_reg))))
8237 rtx out = ((rld[r].out && REG_P (rld[r].out))
8238 ? rld[r].out : rld[r].out_reg);
8239 int out_regno = REGNO (out);
8240 enum machine_mode mode = GET_MODE (out);
8242 /* REG_RTX is now set or clobbered by the main instruction.
8243 As the comment above explains, forget_old_reloads_1 only
8244 sees the original instruction, and there is no guarantee
8245 that the original instruction also clobbered REG_RTX.
8246 For example, if find_reloads sees that the input side of
8247 a matched operand pair dies in this instruction, it may
8248 use the input register as the reload register.
8250 Calling forget_old_reloads_1 is a waste of effort if
8251 REG_RTX is also the output register.
8253 If we know that REG_RTX holds the value of a pseudo
8254 register, the code after the call will record that fact. */
8255 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8256 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8258 if (!HARD_REGISTER_NUM_P (out_regno))
8260 rtx src_reg, store_insn = NULL_RTX;
8262 reg_last_reload_reg[out_regno] = 0;
8264 /* If we can find a hard register that is stored, record
8265 the storing insn so that we may delete this insn with
8266 delete_output_reload. */
8267 src_reg = reload_reg_rtx_for_output[r];
8269 /* If this is an optional reload, try to find the source reg
8270 from an input reload. */
8273 rtx set = single_set (insn);
8274 if (set && SET_DEST (set) == rld[r].out)
8278 src_reg = SET_SRC (set);
8280 for (k = 0; k < n_reloads; k++)
8282 if (rld[k].in == src_reg)
8284 src_reg = reload_reg_rtx_for_input[k];
8291 store_insn = new_spill_reg_store[REGNO (src_reg)];
8292 if (src_reg && REG_P (src_reg)
8293 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8295 int src_regno, src_nregs, k;
8298 gcc_assert (GET_MODE (src_reg) == mode);
8299 src_regno = REGNO (src_reg);
8300 src_nregs = hard_regno_nregs[src_regno][mode];
8301 /* The place where to find a death note varies with
8302 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8303 necessarily checked exactly in the code that moves
8304 notes, so just check both locations. */
8305 note = find_regno_note (insn, REG_DEAD, src_regno);
8306 if (! note && store_insn)
8307 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8308 for (k = 0; k < src_nregs; k++)
8310 spill_reg_store[src_regno + k] = store_insn;
8311 spill_reg_stored_to[src_regno + k] = out;
8312 reg_reloaded_contents[src_regno + k] = out_regno;
8313 reg_reloaded_insn[src_regno + k] = store_insn;
8314 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8315 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8316 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8318 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8321 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8323 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8325 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8327 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8329 reg_last_reload_reg[out_regno] = src_reg;
8330 /* We have to set reg_has_output_reload here, or else
8331 forget_old_reloads_1 will clear reg_last_reload_reg
8333 SET_REGNO_REG_SET (®_has_output_reload,
8339 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8341 for (k = 0; k < out_nregs; k++)
8342 reg_last_reload_reg[out_regno + k] = 0;
8346 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8349 /* Go through the motions to emit INSN and test if it is strictly valid.
8350 Return the emitted insn if valid, else return NULL. */
8353 emit_insn_if_valid_for_reload (rtx insn)
8355 rtx last = get_last_insn ();
8358 insn = emit_insn (insn);
8359 code = recog_memoized (insn);
8363 extract_insn (insn);
8364 /* We want constrain operands to treat this insn strictly in its
8365 validity determination, i.e., the way it would after reload has
8367 if (constrain_operands (1))
8371 delete_insns_since (last);
8375 /* Emit code to perform a reload from IN (which may be a reload register) to
8376 OUT (which may also be a reload register). IN or OUT is from operand
8377 OPNUM with reload type TYPE.
8379 Returns first insn emitted. */
8382 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8384 rtx last = get_last_insn ();
8387 /* If IN is a paradoxical SUBREG, remove it and try to put the
8388 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8389 if (GET_CODE (in) == SUBREG
8390 && (GET_MODE_SIZE (GET_MODE (in))
8391 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8392 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8393 in = SUBREG_REG (in), out = tem;
8394 else if (GET_CODE (out) == SUBREG
8395 && (GET_MODE_SIZE (GET_MODE (out))
8396 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8397 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8398 out = SUBREG_REG (out), in = tem;
8400 /* How to do this reload can get quite tricky. Normally, we are being
8401 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8402 register that didn't get a hard register. In that case we can just
8403 call emit_move_insn.
8405 We can also be asked to reload a PLUS that adds a register or a MEM to
8406 another register, constant or MEM. This can occur during frame pointer
8407 elimination and while reloading addresses. This case is handled by
8408 trying to emit a single insn to perform the add. If it is not valid,
8409 we use a two insn sequence.
8411 Or we can be asked to reload an unary operand that was a fragment of
8412 an addressing mode, into a register. If it isn't recognized as-is,
8413 we try making the unop operand and the reload-register the same:
8414 (set reg:X (unop:X expr:Y))
8415 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8417 Finally, we could be called to handle an 'o' constraint by putting
8418 an address into a register. In that case, we first try to do this
8419 with a named pattern of "reload_load_address". If no such pattern
8420 exists, we just emit a SET insn and hope for the best (it will normally
8421 be valid on machines that use 'o').
8423 This entire process is made complex because reload will never
8424 process the insns we generate here and so we must ensure that
8425 they will fit their constraints and also by the fact that parts of
8426 IN might be being reloaded separately and replaced with spill registers.
8427 Because of this, we are, in some sense, just guessing the right approach
8428 here. The one listed above seems to work.
8430 ??? At some point, this whole thing needs to be rethought. */
8432 if (GET_CODE (in) == PLUS
8433 && (REG_P (XEXP (in, 0))
8434 || GET_CODE (XEXP (in, 0)) == SUBREG
8435 || MEM_P (XEXP (in, 0)))
8436 && (REG_P (XEXP (in, 1))
8437 || GET_CODE (XEXP (in, 1)) == SUBREG
8438 || CONSTANT_P (XEXP (in, 1))
8439 || MEM_P (XEXP (in, 1))))
8441 /* We need to compute the sum of a register or a MEM and another
8442 register, constant, or MEM, and put it into the reload
8443 register. The best possible way of doing this is if the machine
8444 has a three-operand ADD insn that accepts the required operands.
8446 The simplest approach is to try to generate such an insn and see if it
8447 is recognized and matches its constraints. If so, it can be used.
8449 It might be better not to actually emit the insn unless it is valid,
8450 but we need to pass the insn as an operand to `recog' and
8451 `extract_insn' and it is simpler to emit and then delete the insn if
8452 not valid than to dummy things up. */
8454 rtx op0, op1, tem, insn;
8455 enum insn_code code;
8457 op0 = find_replacement (&XEXP (in, 0));
8458 op1 = find_replacement (&XEXP (in, 1));
8460 /* Since constraint checking is strict, commutativity won't be
8461 checked, so we need to do that here to avoid spurious failure
8462 if the add instruction is two-address and the second operand
8463 of the add is the same as the reload reg, which is frequently
8464 the case. If the insn would be A = B + A, rearrange it so
8465 it will be A = A + B as constrain_operands expects. */
8467 if (REG_P (XEXP (in, 1))
8468 && REGNO (out) == REGNO (XEXP (in, 1)))
8469 tem = op0, op0 = op1, op1 = tem;
8471 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8472 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8474 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8478 /* If that failed, we must use a conservative two-insn sequence.
8480 Use a move to copy one operand into the reload register. Prefer
8481 to reload a constant, MEM or pseudo since the move patterns can
8482 handle an arbitrary operand. If OP1 is not a constant, MEM or
8483 pseudo and OP1 is not a valid operand for an add instruction, then
8486 After reloading one of the operands into the reload register, add
8487 the reload register to the output register.
8489 If there is another way to do this for a specific machine, a
8490 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8493 code = optab_handler (add_optab, GET_MODE (out));
8495 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8497 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8498 || (code != CODE_FOR_nothing
8499 && !insn_operand_matches (code, 2, op1)))
8500 tem = op0, op0 = op1, op1 = tem;
8502 gen_reload (out, op0, opnum, type);
8504 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8505 This fixes a problem on the 32K where the stack pointer cannot
8506 be used as an operand of an add insn. */
8508 if (rtx_equal_p (op0, op1))
8511 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8514 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8515 set_unique_reg_note (insn, REG_EQUIV, in);
8519 /* If that failed, copy the address register to the reload register.
8520 Then add the constant to the reload register. */
8522 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8523 gen_reload (out, op1, opnum, type);
8524 insn = emit_insn (gen_add2_insn (out, op0));
8525 set_unique_reg_note (insn, REG_EQUIV, in);
8528 #ifdef SECONDARY_MEMORY_NEEDED
8529 /* If we need a memory location to do the move, do it that way. */
8530 else if ((REG_P (in)
8531 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8532 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8534 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8535 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8536 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8537 REGNO_REG_CLASS (reg_or_subregno (out)),
8540 /* Get the memory to use and rewrite both registers to its mode. */
8541 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8543 if (GET_MODE (loc) != GET_MODE (out))
8544 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8546 if (GET_MODE (loc) != GET_MODE (in))
8547 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8549 gen_reload (loc, in, opnum, type);
8550 gen_reload (out, loc, opnum, type);
8553 else if (REG_P (out) && UNARY_P (in))
8560 op1 = find_replacement (&XEXP (in, 0));
8561 if (op1 != XEXP (in, 0))
8562 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8564 /* First, try a plain SET. */
8565 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8569 /* If that failed, move the inner operand to the reload
8570 register, and try the same unop with the inner expression
8571 replaced with the reload register. */
8573 if (GET_MODE (op1) != GET_MODE (out))
8574 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8578 gen_reload (out_moded, op1, opnum, type);
8581 = gen_rtx_SET (VOIDmode, out,
8582 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8584 insn = emit_insn_if_valid_for_reload (insn);
8587 set_unique_reg_note (insn, REG_EQUIV, in);
8591 fatal_insn ("failure trying to reload:", set);
8593 /* If IN is a simple operand, use gen_move_insn. */
8594 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8596 tem = emit_insn (gen_move_insn (out, in));
8597 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8598 mark_jump_label (in, tem, 0);
8601 #ifdef HAVE_reload_load_address
8602 else if (HAVE_reload_load_address)
8603 emit_insn (gen_reload_load_address (out, in));
8606 /* Otherwise, just write (set OUT IN) and hope for the best. */
8608 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8610 /* Return the first insn emitted.
8611 We can not just return get_last_insn, because there may have
8612 been multiple instructions emitted. Also note that gen_move_insn may
8613 emit more than one insn itself, so we can not assume that there is one
8614 insn emitted per emit_insn_before call. */
8616 return last ? NEXT_INSN (last) : get_insns ();
8619 /* Delete a previously made output-reload whose result we now believe
8620 is not needed. First we double-check.
8622 INSN is the insn now being processed.
8623 LAST_RELOAD_REG is the hard register number for which we want to delete
8624 the last output reload.
8625 J is the reload-number that originally used REG. The caller has made
8626 certain that reload J doesn't use REG any longer for input.
8627 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8630 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8632 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8633 rtx reg = spill_reg_stored_to[last_reload_reg];
8636 int n_inherited = 0;
8642 /* It is possible that this reload has been only used to set another reload
8643 we eliminated earlier and thus deleted this instruction too. */
8644 if (INSN_DELETED_P (output_reload_insn))
8647 /* Get the raw pseudo-register referred to. */
8649 while (GET_CODE (reg) == SUBREG)
8650 reg = SUBREG_REG (reg);
8651 substed = reg_equiv_memory_loc (REGNO (reg));
8653 /* This is unsafe if the operand occurs more often in the current
8654 insn than it is inherited. */
8655 for (k = n_reloads - 1; k >= 0; k--)
8657 rtx reg2 = rld[k].in;
8660 if (MEM_P (reg2) || reload_override_in[k])
8661 reg2 = rld[k].in_reg;
8663 if (rld[k].out && ! rld[k].out_reg)
8664 reg2 = XEXP (rld[k].in_reg, 0);
8666 while (GET_CODE (reg2) == SUBREG)
8667 reg2 = SUBREG_REG (reg2);
8668 if (rtx_equal_p (reg2, reg))
8670 if (reload_inherited[k] || reload_override_in[k] || k == j)
8676 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8677 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8678 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8681 n_occurrences += count_occurrences (PATTERN (insn),
8682 eliminate_regs (substed, VOIDmode,
8684 for (i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8686 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8687 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8689 if (n_occurrences > n_inherited)
8692 regno = REGNO (reg);
8693 if (regno >= FIRST_PSEUDO_REGISTER)
8696 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8698 /* If the pseudo-reg we are reloading is no longer referenced
8699 anywhere between the store into it and here,
8700 and we're within the same basic block, then the value can only
8701 pass through the reload reg and end up here.
8702 Otherwise, give up--return. */
8703 for (i1 = NEXT_INSN (output_reload_insn);
8704 i1 != insn; i1 = NEXT_INSN (i1))
8706 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8708 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8709 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8711 /* If this is USE in front of INSN, we only have to check that
8712 there are no more references than accounted for by inheritance. */
8713 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8715 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8716 i1 = NEXT_INSN (i1);
8718 if (n_occurrences <= n_inherited && i1 == insn)
8724 /* We will be deleting the insn. Remove the spill reg information. */
8725 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8727 spill_reg_store[last_reload_reg + k] = 0;
8728 spill_reg_stored_to[last_reload_reg + k] = 0;
8731 /* The caller has already checked that REG dies or is set in INSN.
8732 It has also checked that we are optimizing, and thus some
8733 inaccuracies in the debugging information are acceptable.
8734 So we could just delete output_reload_insn. But in some cases
8735 we can improve the debugging information without sacrificing
8736 optimization - maybe even improving the code: See if the pseudo
8737 reg has been completely replaced with reload regs. If so, delete
8738 the store insn and forget we had a stack slot for the pseudo. */
8739 if (rld[j].out != rld[j].in
8740 && REG_N_DEATHS (REGNO (reg)) == 1
8741 && REG_N_SETS (REGNO (reg)) == 1
8742 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8743 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8747 /* We know that it was used only between here and the beginning of
8748 the current basic block. (We also know that the last use before
8749 INSN was the output reload we are thinking of deleting, but never
8750 mind that.) Search that range; see if any ref remains. */
8751 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8753 rtx set = single_set (i2);
8755 /* Uses which just store in the pseudo don't count,
8756 since if they are the only uses, they are dead. */
8757 if (set != 0 && SET_DEST (set) == reg)
8762 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8763 && reg_mentioned_p (reg, PATTERN (i2)))
8765 /* Some other ref remains; just delete the output reload we
8767 delete_address_reloads (output_reload_insn, insn);
8768 delete_insn (output_reload_insn);
8773 /* Delete the now-dead stores into this pseudo. Note that this
8774 loop also takes care of deleting output_reload_insn. */
8775 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8777 rtx set = single_set (i2);
8779 if (set != 0 && SET_DEST (set) == reg)
8781 delete_address_reloads (i2, insn);
8789 /* For the debugging info, say the pseudo lives in this reload reg. */
8790 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8791 if (ira_conflicts_p)
8792 /* Inform IRA about the change. */
8793 ira_mark_allocation_change (REGNO (reg));
8794 alter_reg (REGNO (reg), -1, false);
8798 delete_address_reloads (output_reload_insn, insn);
8799 delete_insn (output_reload_insn);
8803 /* We are going to delete DEAD_INSN. Recursively delete loads of
8804 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8805 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8807 delete_address_reloads (rtx dead_insn, rtx current_insn)
8809 rtx set = single_set (dead_insn);
8810 rtx set2, dst, prev, next;
8813 rtx dst = SET_DEST (set);
8815 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8817 /* If we deleted the store from a reloaded post_{in,de}c expression,
8818 we can delete the matching adds. */
8819 prev = PREV_INSN (dead_insn);
8820 next = NEXT_INSN (dead_insn);
8821 if (! prev || ! next)
8823 set = single_set (next);
8824 set2 = single_set (prev);
8826 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8827 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8828 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8830 dst = SET_DEST (set);
8831 if (! rtx_equal_p (dst, SET_DEST (set2))
8832 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8833 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8834 || (INTVAL (XEXP (SET_SRC (set), 1))
8835 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8837 delete_related_insns (prev);
8838 delete_related_insns (next);
8841 /* Subfunction of delete_address_reloads: process registers found in X. */
8843 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8845 rtx prev, set, dst, i2;
8847 enum rtx_code code = GET_CODE (x);
8851 const char *fmt = GET_RTX_FORMAT (code);
8852 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8855 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8856 else if (fmt[i] == 'E')
8858 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8859 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8866 if (spill_reg_order[REGNO (x)] < 0)
8869 /* Scan backwards for the insn that sets x. This might be a way back due
8871 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8873 code = GET_CODE (prev);
8874 if (code == CODE_LABEL || code == JUMP_INSN)
8878 if (reg_set_p (x, PATTERN (prev)))
8880 if (reg_referenced_p (x, PATTERN (prev)))
8883 if (! prev || INSN_UID (prev) < reload_first_uid)
8885 /* Check that PREV only sets the reload register. */
8886 set = single_set (prev);
8889 dst = SET_DEST (set);
8891 || ! rtx_equal_p (dst, x))
8893 if (! reg_set_p (dst, PATTERN (dead_insn)))
8895 /* Check if DST was used in a later insn -
8896 it might have been inherited. */
8897 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8903 if (reg_referenced_p (dst, PATTERN (i2)))
8905 /* If there is a reference to the register in the current insn,
8906 it might be loaded in a non-inherited reload. If no other
8907 reload uses it, that means the register is set before
8909 if (i2 == current_insn)
8911 for (j = n_reloads - 1; j >= 0; j--)
8912 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8913 || reload_override_in[j] == dst)
8915 for (j = n_reloads - 1; j >= 0; j--)
8916 if (rld[j].in && rld[j].reg_rtx == dst)
8925 /* If DST is still live at CURRENT_INSN, check if it is used for
8926 any reload. Note that even if CURRENT_INSN sets DST, we still
8927 have to check the reloads. */
8928 if (i2 == current_insn)
8930 for (j = n_reloads - 1; j >= 0; j--)
8931 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8932 || reload_override_in[j] == dst)
8934 /* ??? We can't finish the loop here, because dst might be
8935 allocated to a pseudo in this block if no reload in this
8936 block needs any of the classes containing DST - see
8937 spill_hard_reg. There is no easy way to tell this, so we
8938 have to scan till the end of the basic block. */
8940 if (reg_set_p (dst, PATTERN (i2)))
8944 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8945 reg_reloaded_contents[REGNO (dst)] = -1;
8949 /* Output reload-insns to reload VALUE into RELOADREG.
8950 VALUE is an autoincrement or autodecrement RTX whose operand
8951 is a register or memory location;
8952 so reloading involves incrementing that location.
8953 IN is either identical to VALUE, or some cheaper place to reload from.
8955 INC_AMOUNT is the number to increment or decrement by (always positive).
8956 This cannot be deduced from VALUE. */
8959 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8961 /* REG or MEM to be copied and incremented. */
8962 rtx incloc = find_replacement (&XEXP (value, 0));
8963 /* Nonzero if increment after copying. */
8964 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8965 || GET_CODE (value) == POST_MODIFY);
8970 rtx real_in = in == value ? incloc : in;
8972 /* No hard register is equivalent to this register after
8973 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8974 we could inc/dec that register as well (maybe even using it for
8975 the source), but I'm not sure it's worth worrying about. */
8977 reg_last_reload_reg[REGNO (incloc)] = 0;
8979 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8981 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8982 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8986 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8987 inc_amount = -inc_amount;
8989 inc = GEN_INT (inc_amount);
8992 /* If this is post-increment, first copy the location to the reload reg. */
8993 if (post && real_in != reloadreg)
8994 emit_insn (gen_move_insn (reloadreg, real_in));
8998 /* See if we can directly increment INCLOC. Use a method similar to
8999 that in gen_reload. */
9001 last = get_last_insn ();
9002 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9003 gen_rtx_PLUS (GET_MODE (incloc),
9006 code = recog_memoized (add_insn);
9009 extract_insn (add_insn);
9010 if (constrain_operands (1))
9012 /* If this is a pre-increment and we have incremented the value
9013 where it lives, copy the incremented value to RELOADREG to
9014 be used as an address. */
9017 emit_insn (gen_move_insn (reloadreg, incloc));
9021 delete_insns_since (last);
9024 /* If couldn't do the increment directly, must increment in RELOADREG.
9025 The way we do this depends on whether this is pre- or post-increment.
9026 For pre-increment, copy INCLOC to the reload register, increment it
9027 there, then save back. */
9031 if (in != reloadreg)
9032 emit_insn (gen_move_insn (reloadreg, real_in));
9033 emit_insn (gen_add2_insn (reloadreg, inc));
9034 emit_insn (gen_move_insn (incloc, reloadreg));
9039 Because this might be a jump insn or a compare, and because RELOADREG
9040 may not be available after the insn in an input reload, we must do
9041 the incrementation before the insn being reloaded for.
9043 We have already copied IN to RELOADREG. Increment the copy in
9044 RELOADREG, save that back, then decrement RELOADREG so it has
9045 the original value. */
9047 emit_insn (gen_add2_insn (reloadreg, inc));
9048 emit_insn (gen_move_insn (incloc, reloadreg));
9049 if (CONST_INT_P (inc))
9050 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9052 emit_insn (gen_sub2_insn (reloadreg, inc));
9058 add_auto_inc_notes (rtx insn, rtx x)
9060 enum rtx_code code = GET_CODE (x);
9064 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9066 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9070 /* Scan all the operand sub-expressions. */
9071 fmt = GET_RTX_FORMAT (code);
9072 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9075 add_auto_inc_notes (insn, XEXP (x, i));
9076 else if (fmt[i] == 'E')
9077 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9078 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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