1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Used for communication between order_regs_for_reload and count_pseudo.
262 Used to avoid counting one pseudo twice. */
263 static regset_head pseudos_counted;
265 /* First uid used by insns created by reload in this function.
266 Used in find_equiv_reg. */
267 int reload_first_uid;
269 /* Flag set by local-alloc or global-alloc if anything is live in
270 a call-clobbered reg across calls. */
271 int caller_save_needed;
273 /* Set to 1 while reload_as_needed is operating.
274 Required by some machines to handle any generated moves differently. */
275 int reload_in_progress = 0;
277 /* These arrays record the insn_code of insns that may be needed to
278 perform input and output reloads of special objects. They provide a
279 place to pass a scratch register. */
280 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
281 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
283 /* This obstack is used for allocation of rtl during register elimination.
284 The allocated storage can be freed once find_reloads has processed the
286 static struct obstack reload_obstack;
288 /* Points to the beginning of the reload_obstack. All insn_chain structures
289 are allocated first. */
290 static char *reload_startobj;
292 /* The point after all insn_chain structures. Used to quickly deallocate
293 memory allocated in copy_reloads during calculate_needs_all_insns. */
294 static char *reload_firstobj;
296 /* This points before all local rtl generated by register elimination.
297 Used to quickly free all memory after processing one insn. */
298 static char *reload_insn_firstobj;
300 /* List of insn_chain instructions, one for every insn that reload needs to
302 struct insn_chain *reload_insn_chain;
304 /* List of all insns needing reloads. */
305 static struct insn_chain *insns_need_reload;
307 /* This structure is used to record information about register eliminations.
308 Each array entry describes one possible way of eliminating a register
309 in favor of another. If there is more than one way of eliminating a
310 particular register, the most preferred should be specified first. */
314 int from; /* Register number to be eliminated. */
315 int to; /* Register number used as replacement. */
316 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
317 int can_eliminate; /* Nonzero if this elimination can be done. */
318 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
319 insns made by reload. */
320 HOST_WIDE_INT offset; /* Current offset between the two regs. */
321 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
322 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
323 rtx from_rtx; /* REG rtx for the register to be eliminated.
324 We cannot simply compare the number since
325 we might then spuriously replace a hard
326 register corresponding to a pseudo
327 assigned to the reg to be eliminated. */
328 rtx to_rtx; /* REG rtx for the replacement. */
331 static struct elim_table *reg_eliminate = 0;
333 /* This is an intermediate structure to initialize the table. It has
334 exactly the members provided by ELIMINABLE_REGS. */
335 static const struct elim_table_1
339 } reg_eliminate_1[] =
341 /* If a set of eliminable registers was specified, define the table from it.
342 Otherwise, default to the normal case of the frame pointer being
343 replaced by the stack pointer. */
345 #ifdef ELIMINABLE_REGS
348 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
351 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
353 /* Record the number of pending eliminations that have an offset not equal
354 to their initial offset. If nonzero, we use a new copy of each
355 replacement result in any insns encountered. */
356 int num_not_at_initial_offset;
358 /* Count the number of registers that we may be able to eliminate. */
359 static int num_eliminable;
360 /* And the number of registers that are equivalent to a constant that
361 can be eliminated to frame_pointer / arg_pointer + constant. */
362 static int num_eliminable_invariants;
364 /* For each label, we record the offset of each elimination. If we reach
365 a label by more than one path and an offset differs, we cannot do the
366 elimination. This information is indexed by the difference of the
367 number of the label and the first label number. We can't offset the
368 pointer itself as this can cause problems on machines with segmented
369 memory. The first table is an array of flags that records whether we
370 have yet encountered a label and the second table is an array of arrays,
371 one entry in the latter array for each elimination. */
373 static int first_label_num;
374 static char *offsets_known_at;
375 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
377 /* Number of labels in the current function. */
379 static int num_labels;
381 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
382 static void maybe_fix_stack_asms (void);
383 static void copy_reloads (struct insn_chain *);
384 static void calculate_needs_all_insns (int);
385 static int find_reg (struct insn_chain *, int);
386 static void find_reload_regs (struct insn_chain *);
387 static void select_reload_regs (void);
388 static void delete_caller_save_insns (void);
390 static void spill_failure (rtx, enum reg_class);
391 static void count_spilled_pseudo (int, int, int);
392 static void delete_dead_insn (rtx);
393 static void alter_reg (int, int);
394 static void set_label_offsets (rtx, rtx, int);
395 static void check_eliminable_occurrences (rtx);
396 static void elimination_effects (rtx, enum machine_mode);
397 static int eliminate_regs_in_insn (rtx, int);
398 static void update_eliminable_offsets (void);
399 static void mark_not_eliminable (rtx, rtx, void *);
400 static void set_initial_elim_offsets (void);
401 static bool verify_initial_elim_offsets (void);
402 static void set_initial_label_offsets (void);
403 static void set_offsets_for_label (rtx);
404 static void init_elim_table (void);
405 static void update_eliminables (HARD_REG_SET *);
406 static void spill_hard_reg (unsigned int, int);
407 static int finish_spills (int);
408 static void scan_paradoxical_subregs (rtx);
409 static void count_pseudo (int);
410 static void order_regs_for_reload (struct insn_chain *);
411 static void reload_as_needed (int);
412 static void forget_old_reloads_1 (rtx, rtx, void *);
413 static void forget_marked_reloads (regset);
414 static int reload_reg_class_lower (const void *, const void *);
415 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
417 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
419 static int reload_reg_free_p (unsigned int, int, enum reload_type);
420 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
422 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
424 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
425 static int allocate_reload_reg (struct insn_chain *, int, int);
426 static int conflicts_with_override (rtx);
427 static void failed_reload (rtx, int);
428 static int set_reload_reg (int, int);
429 static void choose_reload_regs_init (struct insn_chain *, rtx *);
430 static void choose_reload_regs (struct insn_chain *);
431 static void merge_assigned_reloads (rtx);
432 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
434 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
436 static void do_input_reload (struct insn_chain *, struct reload *, int);
437 static void do_output_reload (struct insn_chain *, struct reload *, int);
438 static bool inherit_piecemeal_p (int, int);
439 static void emit_reload_insns (struct insn_chain *);
440 static void delete_output_reload (rtx, int, int);
441 static void delete_address_reloads (rtx, rtx);
442 static void delete_address_reloads_1 (rtx, rtx, rtx);
443 static rtx inc_for_reload (rtx, rtx, rtx, int);
445 static void add_auto_inc_notes (rtx, rtx);
447 static void copy_eh_notes (rtx, rtx);
448 static int reloads_conflict (int, int);
449 static rtx gen_reload (rtx, rtx, int, enum reload_type);
450 static rtx emit_insn_if_valid_for_reload (rtx);
452 /* Initialize the reload pass once per compilation. */
459 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
460 Set spill_indirect_levels to the number of levels such addressing is
461 permitted, zero if it is not permitted at all. */
464 = gen_rtx_MEM (Pmode,
467 LAST_VIRTUAL_REGISTER + 1),
469 spill_indirect_levels = 0;
471 while (memory_address_p (QImode, tem))
473 spill_indirect_levels++;
474 tem = gen_rtx_MEM (Pmode, tem);
477 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
479 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
480 indirect_symref_ok = memory_address_p (QImode, tem);
482 /* See if reg+reg is a valid (and offsettable) address. */
484 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
486 tem = gen_rtx_PLUS (Pmode,
487 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
488 gen_rtx_REG (Pmode, i));
490 /* This way, we make sure that reg+reg is an offsettable address. */
491 tem = plus_constant (tem, 4);
493 if (memory_address_p (QImode, tem))
495 double_reg_address_ok = 1;
500 /* Initialize obstack for our rtl allocation. */
501 gcc_obstack_init (&reload_obstack);
502 reload_startobj = obstack_alloc (&reload_obstack, 0);
504 INIT_REG_SET (&spilled_pseudos);
505 INIT_REG_SET (&pseudos_counted);
508 /* List of insn chains that are currently unused. */
509 static struct insn_chain *unused_insn_chains = 0;
511 /* Allocate an empty insn_chain structure. */
513 new_insn_chain (void)
515 struct insn_chain *c;
517 if (unused_insn_chains == 0)
519 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
520 INIT_REG_SET (&c->live_throughout);
521 INIT_REG_SET (&c->dead_or_set);
525 c = unused_insn_chains;
526 unused_insn_chains = c->next;
528 c->is_caller_save_insn = 0;
529 c->need_operand_change = 0;
535 /* Small utility function to set all regs in hard reg set TO which are
536 allocated to pseudos in regset FROM. */
539 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
542 reg_set_iterator rsi;
544 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
546 int r = reg_renumber[regno];
550 /* reload_combine uses the information from
551 DF_RA_LIVE_IN (BASIC_BLOCK), which might still
552 contain registers that have not actually been allocated
553 since they have an equivalence. */
554 gcc_assert (reload_completed);
557 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
561 /* Replace all pseudos found in LOC with their corresponding
565 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
578 unsigned int regno = REGNO (x);
580 if (regno < FIRST_PSEUDO_REGISTER)
583 x = eliminate_regs (x, mem_mode, usage);
587 replace_pseudos_in (loc, mem_mode, usage);
591 if (reg_equiv_constant[regno])
592 *loc = reg_equiv_constant[regno];
593 else if (reg_equiv_mem[regno])
594 *loc = reg_equiv_mem[regno];
595 else if (reg_equiv_address[regno])
596 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
599 gcc_assert (!REG_P (regno_reg_rtx[regno])
600 || REGNO (regno_reg_rtx[regno]) != regno);
601 *loc = regno_reg_rtx[regno];
606 else if (code == MEM)
608 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
612 /* Process each of our operands recursively. */
613 fmt = GET_RTX_FORMAT (code);
614 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
616 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
617 else if (*fmt == 'E')
618 for (j = 0; j < XVECLEN (x, i); j++)
619 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
622 /* Determine if the current function has an exception receiver block
623 that reaches the exit block via non-exceptional edges */
626 has_nonexceptional_receiver (void)
630 basic_block *tos, *worklist, bb;
632 /* If we're not optimizing, then just err on the safe side. */
636 /* First determine which blocks can reach exit via normal paths. */
637 tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1));
640 bb->flags &= ~BB_REACHABLE;
642 /* Place the exit block on our worklist. */
643 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
644 *tos++ = EXIT_BLOCK_PTR;
646 /* Iterate: find everything reachable from what we've already seen. */
647 while (tos != worklist)
651 FOR_EACH_EDGE (e, ei, bb->preds)
652 if (!(e->flags & EDGE_ABNORMAL))
654 basic_block src = e->src;
656 if (!(src->flags & BB_REACHABLE))
658 src->flags |= BB_REACHABLE;
665 /* Now see if there's a reachable block with an exceptional incoming
668 if (bb->flags & BB_REACHABLE)
669 FOR_EACH_EDGE (e, ei, bb->preds)
670 if (e->flags & EDGE_ABNORMAL)
673 /* No exceptional block reached exit unexceptionally. */
678 /* Global variables used by reload and its subroutines. */
680 /* Set during calculate_needs if an insn needs register elimination. */
681 static int something_needs_elimination;
682 /* Set during calculate_needs if an insn needs an operand changed. */
683 static int something_needs_operands_changed;
685 /* Nonzero means we couldn't get enough spill regs. */
688 /* Main entry point for the reload pass.
690 FIRST is the first insn of the function being compiled.
692 GLOBAL nonzero means we were called from global_alloc
693 and should attempt to reallocate any pseudoregs that we
694 displace from hard regs we will use for reloads.
695 If GLOBAL is zero, we do not have enough information to do that,
696 so any pseudo reg that is spilled must go to the stack.
698 Return value is nonzero if reload failed
699 and we must not do any more for this function. */
702 reload (rtx first, int global)
706 struct elim_table *ep;
709 /* Make sure even insns with volatile mem refs are recognizable. */
714 reload_firstobj = obstack_alloc (&reload_obstack, 0);
716 /* Make sure that the last insn in the chain
717 is not something that needs reloading. */
718 emit_note (NOTE_INSN_DELETED);
720 /* Enable find_equiv_reg to distinguish insns made by reload. */
721 reload_first_uid = get_max_uid ();
723 #ifdef SECONDARY_MEMORY_NEEDED
724 /* Initialize the secondary memory table. */
725 clear_secondary_mem ();
728 /* We don't have a stack slot for any spill reg yet. */
729 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
730 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
732 /* Initialize the save area information for caller-save, in case some
736 /* Compute which hard registers are now in use
737 as homes for pseudo registers.
738 This is done here rather than (eg) in global_alloc
739 because this point is reached even if not optimizing. */
740 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
743 /* A function that has a nonlocal label that can reach the exit
744 block via non-exceptional paths must save all call-saved
746 if (current_function_calls_unwind_init
747 || (current_function_has_nonlocal_label
748 && has_nonexceptional_receiver ()))
749 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
750 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
751 df_set_regs_ever_live (i, true);
753 /* Find all the pseudo registers that didn't get hard regs
754 but do have known equivalent constants or memory slots.
755 These include parameters (known equivalent to parameter slots)
756 and cse'd or loop-moved constant memory addresses.
758 Record constant equivalents in reg_equiv_constant
759 so they will be substituted by find_reloads.
760 Record memory equivalents in reg_mem_equiv so they can
761 be substituted eventually by altering the REG-rtx's. */
763 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
764 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
765 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
766 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
767 reg_equiv_address = XCNEWVEC (rtx, max_regno);
768 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
769 reg_old_renumber = XCNEWVEC (short, max_regno);
770 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
771 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
772 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
774 CLEAR_HARD_REG_SET (bad_spill_regs_global);
776 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
777 to. Also find all paradoxical subregs and find largest such for
780 num_eliminable_invariants = 0;
781 for (insn = first; insn; insn = NEXT_INSN (insn))
783 rtx set = single_set (insn);
785 /* We may introduce USEs that we want to remove at the end, so
786 we'll mark them with QImode. Make sure there are no
787 previously-marked insns left by say regmove. */
788 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
789 && GET_MODE (insn) != VOIDmode)
790 PUT_MODE (insn, VOIDmode);
793 scan_paradoxical_subregs (PATTERN (insn));
795 if (set != 0 && REG_P (SET_DEST (set)))
797 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
803 i = REGNO (SET_DEST (set));
806 if (i <= LAST_VIRTUAL_REGISTER)
809 if (! function_invariant_p (x)
811 /* A function invariant is often CONSTANT_P but may
812 include a register. We promise to only pass
813 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
815 && LEGITIMATE_PIC_OPERAND_P (x)))
817 /* It can happen that a REG_EQUIV note contains a MEM
818 that is not a legitimate memory operand. As later
819 stages of reload assume that all addresses found
820 in the reg_equiv_* arrays were originally legitimate,
821 we ignore such REG_EQUIV notes. */
822 if (memory_operand (x, VOIDmode))
824 /* Always unshare the equivalence, so we can
825 substitute into this insn without touching the
827 reg_equiv_memory_loc[i] = copy_rtx (x);
829 else if (function_invariant_p (x))
831 if (GET_CODE (x) == PLUS)
833 /* This is PLUS of frame pointer and a constant,
834 and might be shared. Unshare it. */
835 reg_equiv_invariant[i] = copy_rtx (x);
836 num_eliminable_invariants++;
838 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
840 reg_equiv_invariant[i] = x;
841 num_eliminable_invariants++;
843 else if (LEGITIMATE_CONSTANT_P (x))
844 reg_equiv_constant[i] = x;
847 reg_equiv_memory_loc[i]
848 = force_const_mem (GET_MODE (SET_DEST (set)), x);
849 if (! reg_equiv_memory_loc[i])
850 reg_equiv_init[i] = NULL_RTX;
855 reg_equiv_init[i] = NULL_RTX;
860 reg_equiv_init[i] = NULL_RTX;
865 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
866 if (reg_equiv_init[i])
868 fprintf (dump_file, "init_insns for %u: ", i);
869 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
870 fprintf (dump_file, "\n");
875 first_label_num = get_first_label_num ();
876 num_labels = max_label_num () - first_label_num;
878 /* Allocate the tables used to store offset information at labels. */
879 /* We used to use alloca here, but the size of what it would try to
880 allocate would occasionally cause it to exceed the stack limit and
881 cause a core dump. */
882 offsets_known_at = XNEWVEC (char, num_labels);
883 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
885 /* Alter each pseudo-reg rtx to contain its hard reg number.
886 Assign stack slots to the pseudos that lack hard regs or equivalents.
887 Do not touch virtual registers. */
889 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
892 /* If we have some registers we think can be eliminated, scan all insns to
893 see if there is an insn that sets one of these registers to something
894 other than itself plus a constant. If so, the register cannot be
895 eliminated. Doing this scan here eliminates an extra pass through the
896 main reload loop in the most common case where register elimination
898 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
900 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
902 maybe_fix_stack_asms ();
904 insns_need_reload = 0;
905 something_needs_elimination = 0;
907 /* Initialize to -1, which means take the first spill register. */
910 /* Spill any hard regs that we know we can't eliminate. */
911 CLEAR_HARD_REG_SET (used_spill_regs);
912 /* There can be multiple ways to eliminate a register;
913 they should be listed adjacently.
914 Elimination for any register fails only if all possible ways fail. */
915 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
918 int can_eliminate = 0;
921 can_eliminate |= ep->can_eliminate;
924 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
926 spill_hard_reg (from, 1);
929 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
930 if (frame_pointer_needed)
931 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
933 finish_spills (global);
935 /* From now on, we may need to generate moves differently. We may also
936 allow modifications of insns which cause them to not be recognized.
937 Any such modifications will be cleaned up during reload itself. */
938 reload_in_progress = 1;
940 /* This loop scans the entire function each go-round
941 and repeats until one repetition spills no additional hard regs. */
944 int something_changed;
946 HOST_WIDE_INT starting_frame_size;
948 starting_frame_size = get_frame_size ();
950 set_initial_elim_offsets ();
951 set_initial_label_offsets ();
953 /* For each pseudo register that has an equivalent location defined,
954 try to eliminate any eliminable registers (such as the frame pointer)
955 assuming initial offsets for the replacement register, which
958 If the resulting location is directly addressable, substitute
959 the MEM we just got directly for the old REG.
961 If it is not addressable but is a constant or the sum of a hard reg
962 and constant, it is probably not addressable because the constant is
963 out of range, in that case record the address; we will generate
964 hairy code to compute the address in a register each time it is
965 needed. Similarly if it is a hard register, but one that is not
966 valid as an address register.
968 If the location is not addressable, but does not have one of the
969 above forms, assign a stack slot. We have to do this to avoid the
970 potential of producing lots of reloads if, e.g., a location involves
971 a pseudo that didn't get a hard register and has an equivalent memory
972 location that also involves a pseudo that didn't get a hard register.
974 Perhaps at some point we will improve reload_when_needed handling
975 so this problem goes away. But that's very hairy. */
977 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
978 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
980 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
982 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
984 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
985 else if (CONSTANT_P (XEXP (x, 0))
986 || (REG_P (XEXP (x, 0))
987 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
988 || (GET_CODE (XEXP (x, 0)) == PLUS
989 && REG_P (XEXP (XEXP (x, 0), 0))
990 && (REGNO (XEXP (XEXP (x, 0), 0))
991 < FIRST_PSEUDO_REGISTER)
992 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
993 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
996 /* Make a new stack slot. Then indicate that something
997 changed so we go back and recompute offsets for
998 eliminable registers because the allocation of memory
999 below might change some offset. reg_equiv_{mem,address}
1000 will be set up for this pseudo on the next pass around
1002 reg_equiv_memory_loc[i] = 0;
1003 reg_equiv_init[i] = 0;
1008 if (caller_save_needed)
1009 setup_save_areas ();
1011 /* If we allocated another stack slot, redo elimination bookkeeping. */
1012 if (starting_frame_size != get_frame_size ())
1014 if (starting_frame_size && cfun->stack_alignment_needed)
1016 /* If we have a stack frame, we must align it now. The
1017 stack size may be a part of the offset computation for
1018 register elimination. So if this changes the stack size,
1019 then repeat the elimination bookkeeping. We don't
1020 realign when there is no stack, as that will cause a
1021 stack frame when none is needed should
1022 STARTING_FRAME_OFFSET not be already aligned to
1024 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
1025 if (starting_frame_size != get_frame_size ())
1029 if (caller_save_needed)
1031 save_call_clobbered_regs ();
1032 /* That might have allocated new insn_chain structures. */
1033 reload_firstobj = obstack_alloc (&reload_obstack, 0);
1036 calculate_needs_all_insns (global);
1038 CLEAR_REG_SET (&spilled_pseudos);
1041 something_changed = 0;
1043 /* If we allocated any new memory locations, make another pass
1044 since it might have changed elimination offsets. */
1045 if (starting_frame_size != get_frame_size ())
1046 something_changed = 1;
1048 /* Even if the frame size remained the same, we might still have
1049 changed elimination offsets, e.g. if find_reloads called
1050 force_const_mem requiring the back end to allocate a constant
1051 pool base register that needs to be saved on the stack. */
1052 else if (!verify_initial_elim_offsets ())
1053 something_changed = 1;
1056 HARD_REG_SET to_spill;
1057 CLEAR_HARD_REG_SET (to_spill);
1058 update_eliminables (&to_spill);
1059 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1061 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1062 if (TEST_HARD_REG_BIT (to_spill, i))
1064 spill_hard_reg (i, 1);
1067 /* Regardless of the state of spills, if we previously had
1068 a register that we thought we could eliminate, but now can
1069 not eliminate, we must run another pass.
1071 Consider pseudos which have an entry in reg_equiv_* which
1072 reference an eliminable register. We must make another pass
1073 to update reg_equiv_* so that we do not substitute in the
1074 old value from when we thought the elimination could be
1076 something_changed = 1;
1080 select_reload_regs ();
1084 if (insns_need_reload != 0 || did_spill)
1085 something_changed |= finish_spills (global);
1087 if (! something_changed)
1090 if (caller_save_needed)
1091 delete_caller_save_insns ();
1093 obstack_free (&reload_obstack, reload_firstobj);
1096 /* If global-alloc was run, notify it of any register eliminations we have
1099 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1100 if (ep->can_eliminate)
1101 mark_elimination (ep->from, ep->to);
1103 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1104 If that insn didn't set the register (i.e., it copied the register to
1105 memory), just delete that insn instead of the equivalencing insn plus
1106 anything now dead. If we call delete_dead_insn on that insn, we may
1107 delete the insn that actually sets the register if the register dies
1108 there and that is incorrect. */
1110 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1112 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1115 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1117 rtx equiv_insn = XEXP (list, 0);
1119 /* If we already deleted the insn or if it may trap, we can't
1120 delete it. The latter case shouldn't happen, but can
1121 if an insn has a variable address, gets a REG_EH_REGION
1122 note added to it, and then gets converted into a load
1123 from a constant address. */
1124 if (NOTE_P (equiv_insn)
1125 || can_throw_internal (equiv_insn))
1127 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1128 delete_dead_insn (equiv_insn);
1130 SET_INSN_DELETED (equiv_insn);
1135 /* Use the reload registers where necessary
1136 by generating move instructions to move the must-be-register
1137 values into or out of the reload registers. */
1139 if (insns_need_reload != 0 || something_needs_elimination
1140 || something_needs_operands_changed)
1142 HOST_WIDE_INT old_frame_size = get_frame_size ();
1144 reload_as_needed (global);
1146 gcc_assert (old_frame_size == get_frame_size ());
1148 gcc_assert (verify_initial_elim_offsets ());
1151 /* If we were able to eliminate the frame pointer, show that it is no
1152 longer live at the start of any basic block. If it ls live by
1153 virtue of being in a pseudo, that pseudo will be marked live
1154 and hence the frame pointer will be known to be live via that
1157 if (! frame_pointer_needed)
1160 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1161 bitmap_clear_bit (df_get_live_top (bb), HARD_FRAME_POINTER_REGNUM);
1164 /* Come here (with failure set nonzero) if we can't get enough spill
1168 CLEAR_REG_SET (&spilled_pseudos);
1169 reload_in_progress = 0;
1171 /* Now eliminate all pseudo regs by modifying them into
1172 their equivalent memory references.
1173 The REG-rtx's for the pseudos are modified in place,
1174 so all insns that used to refer to them now refer to memory.
1176 For a reg that has a reg_equiv_address, all those insns
1177 were changed by reloading so that no insns refer to it any longer;
1178 but the DECL_RTL of a variable decl may refer to it,
1179 and if so this causes the debugging info to mention the variable. */
1181 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1185 if (reg_equiv_mem[i])
1186 addr = XEXP (reg_equiv_mem[i], 0);
1188 if (reg_equiv_address[i])
1189 addr = reg_equiv_address[i];
1193 if (reg_renumber[i] < 0)
1195 rtx reg = regno_reg_rtx[i];
1197 REG_USERVAR_P (reg) = 0;
1198 PUT_CODE (reg, MEM);
1199 XEXP (reg, 0) = addr;
1200 if (reg_equiv_memory_loc[i])
1201 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1204 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1205 MEM_ATTRS (reg) = 0;
1207 MEM_NOTRAP_P (reg) = 1;
1209 else if (reg_equiv_mem[i])
1210 XEXP (reg_equiv_mem[i], 0) = addr;
1214 /* We must set reload_completed now since the cleanup_subreg_operands call
1215 below will re-recognize each insn and reload may have generated insns
1216 which are only valid during and after reload. */
1217 reload_completed = 1;
1219 /* Make a pass over all the insns and delete all USEs which we inserted
1220 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1221 notes. Delete all CLOBBER insns, except those that refer to the return
1222 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1223 from misarranging variable-array code, and simplify (subreg (reg))
1224 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1225 are no longer useful or accurate. Strip and regenerate REG_INC notes
1226 that may have been moved around. */
1228 for (insn = first; insn; insn = NEXT_INSN (insn))
1234 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1235 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1237 if ((GET_CODE (PATTERN (insn)) == USE
1238 /* We mark with QImode USEs introduced by reload itself. */
1239 && (GET_MODE (insn) == QImode
1240 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1241 || (GET_CODE (PATTERN (insn)) == CLOBBER
1242 && (!MEM_P (XEXP (PATTERN (insn), 0))
1243 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1244 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1245 && XEXP (XEXP (PATTERN (insn), 0), 0)
1246 != stack_pointer_rtx))
1247 && (!REG_P (XEXP (PATTERN (insn), 0))
1248 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1254 /* Some CLOBBERs may survive until here and still reference unassigned
1255 pseudos with const equivalent, which may in turn cause ICE in later
1256 passes if the reference remains in place. */
1257 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1258 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1259 VOIDmode, PATTERN (insn));
1261 /* Discard obvious no-ops, even without -O. This optimization
1262 is fast and doesn't interfere with debugging. */
1263 if (NONJUMP_INSN_P (insn)
1264 && GET_CODE (PATTERN (insn)) == SET
1265 && REG_P (SET_SRC (PATTERN (insn)))
1266 && REG_P (SET_DEST (PATTERN (insn)))
1267 && (REGNO (SET_SRC (PATTERN (insn)))
1268 == REGNO (SET_DEST (PATTERN (insn)))))
1274 pnote = ®_NOTES (insn);
1277 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1278 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1279 || REG_NOTE_KIND (*pnote) == REG_INC
1280 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1281 || REG_NOTE_KIND (*pnote) == REG_LIBCALL_ID
1282 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1283 *pnote = XEXP (*pnote, 1);
1285 pnote = &XEXP (*pnote, 1);
1289 add_auto_inc_notes (insn, PATTERN (insn));
1292 /* Simplify (subreg (reg)) if it appears as an operand. */
1293 cleanup_subreg_operands (insn);
1295 /* Clean up invalid ASMs so that they don't confuse later passes.
1297 if (asm_noperands (PATTERN (insn)) >= 0)
1299 extract_insn (insn);
1300 if (!constrain_operands (1))
1302 error_for_asm (insn,
1303 "%<asm%> operand has impossible constraints");
1310 /* If we are doing stack checking, give a warning if this function's
1311 frame size is larger than we expect. */
1312 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1314 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1315 static int verbose_warned = 0;
1317 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1318 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1319 size += UNITS_PER_WORD;
1321 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1323 warning (0, "frame size too large for reliable stack checking");
1324 if (! verbose_warned)
1326 warning (0, "try reducing the number of local variables");
1332 /* Indicate that we no longer have known memory locations or constants. */
1333 if (reg_equiv_constant)
1334 free (reg_equiv_constant);
1335 if (reg_equiv_invariant)
1336 free (reg_equiv_invariant);
1337 reg_equiv_constant = 0;
1338 reg_equiv_invariant = 0;
1339 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1340 reg_equiv_memory_loc = 0;
1342 if (offsets_known_at)
1343 free (offsets_known_at);
1347 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1348 if (reg_equiv_alt_mem_list[i])
1349 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1350 free (reg_equiv_alt_mem_list);
1352 free (reg_equiv_mem);
1354 free (reg_equiv_address);
1355 free (reg_max_ref_width);
1356 free (reg_old_renumber);
1357 free (pseudo_previous_regs);
1358 free (pseudo_forbidden_regs);
1360 CLEAR_HARD_REG_SET (used_spill_regs);
1361 for (i = 0; i < n_spills; i++)
1362 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1364 /* Free all the insn_chain structures at once. */
1365 obstack_free (&reload_obstack, reload_startobj);
1366 unused_insn_chains = 0;
1367 fixup_abnormal_edges ();
1369 /* Replacing pseudos with their memory equivalents might have
1370 created shared rtx. Subsequent passes would get confused
1371 by this, so unshare everything here. */
1372 unshare_all_rtl_again (first);
1374 #ifdef STACK_BOUNDARY
1375 /* init_emit has set the alignment of the hard frame pointer
1376 to STACK_BOUNDARY. It is very likely no longer valid if
1377 the hard frame pointer was used for register allocation. */
1378 if (!frame_pointer_needed)
1379 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1385 /* Yet another special case. Unfortunately, reg-stack forces people to
1386 write incorrect clobbers in asm statements. These clobbers must not
1387 cause the register to appear in bad_spill_regs, otherwise we'll call
1388 fatal_insn later. We clear the corresponding regnos in the live
1389 register sets to avoid this.
1390 The whole thing is rather sick, I'm afraid. */
1393 maybe_fix_stack_asms (void)
1396 const char *constraints[MAX_RECOG_OPERANDS];
1397 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1398 struct insn_chain *chain;
1400 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1403 HARD_REG_SET clobbered, allowed;
1406 if (! INSN_P (chain->insn)
1407 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1409 pat = PATTERN (chain->insn);
1410 if (GET_CODE (pat) != PARALLEL)
1413 CLEAR_HARD_REG_SET (clobbered);
1414 CLEAR_HARD_REG_SET (allowed);
1416 /* First, make a mask of all stack regs that are clobbered. */
1417 for (i = 0; i < XVECLEN (pat, 0); i++)
1419 rtx t = XVECEXP (pat, 0, i);
1420 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1421 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1424 /* Get the operand values and constraints out of the insn. */
1425 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1426 constraints, operand_mode, NULL);
1428 /* For every operand, see what registers are allowed. */
1429 for (i = 0; i < noperands; i++)
1431 const char *p = constraints[i];
1432 /* For every alternative, we compute the class of registers allowed
1433 for reloading in CLS, and merge its contents into the reg set
1435 int cls = (int) NO_REGS;
1441 if (c == '\0' || c == ',' || c == '#')
1443 /* End of one alternative - mark the regs in the current
1444 class, and reset the class. */
1445 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1451 } while (c != '\0' && c != ',');
1459 case '=': case '+': case '*': case '%': case '?': case '!':
1460 case '0': case '1': case '2': case '3': case '4': case 'm':
1461 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1462 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1463 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1468 cls = (int) reg_class_subunion[cls]
1469 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1474 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1478 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1479 cls = (int) reg_class_subunion[cls]
1480 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1482 cls = (int) reg_class_subunion[cls]
1483 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1485 p += CONSTRAINT_LEN (c, p);
1488 /* Those of the registers which are clobbered, but allowed by the
1489 constraints, must be usable as reload registers. So clear them
1490 out of the life information. */
1491 AND_HARD_REG_SET (allowed, clobbered);
1492 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1493 if (TEST_HARD_REG_BIT (allowed, i))
1495 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1496 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1503 /* Copy the global variables n_reloads and rld into the corresponding elts
1506 copy_reloads (struct insn_chain *chain)
1508 chain->n_reloads = n_reloads;
1509 chain->rld = obstack_alloc (&reload_obstack,
1510 n_reloads * sizeof (struct reload));
1511 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1512 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1515 /* Walk the chain of insns, and determine for each whether it needs reloads
1516 and/or eliminations. Build the corresponding insns_need_reload list, and
1517 set something_needs_elimination as appropriate. */
1519 calculate_needs_all_insns (int global)
1521 struct insn_chain **pprev_reload = &insns_need_reload;
1522 struct insn_chain *chain, *next = 0;
1524 something_needs_elimination = 0;
1526 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1527 for (chain = reload_insn_chain; chain != 0; chain = next)
1529 rtx insn = chain->insn;
1533 /* Clear out the shortcuts. */
1534 chain->n_reloads = 0;
1535 chain->need_elim = 0;
1536 chain->need_reload = 0;
1537 chain->need_operand_change = 0;
1539 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1540 include REG_LABEL), we need to see what effects this has on the
1541 known offsets at labels. */
1543 if (LABEL_P (insn) || JUMP_P (insn)
1544 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1545 set_label_offsets (insn, insn, 0);
1549 rtx old_body = PATTERN (insn);
1550 int old_code = INSN_CODE (insn);
1551 rtx old_notes = REG_NOTES (insn);
1552 int did_elimination = 0;
1553 int operands_changed = 0;
1554 rtx set = single_set (insn);
1556 /* Skip insns that only set an equivalence. */
1557 if (set && REG_P (SET_DEST (set))
1558 && reg_renumber[REGNO (SET_DEST (set))] < 0
1559 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1560 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1561 && reg_equiv_init[REGNO (SET_DEST (set))])
1564 /* If needed, eliminate any eliminable registers. */
1565 if (num_eliminable || num_eliminable_invariants)
1566 did_elimination = eliminate_regs_in_insn (insn, 0);
1568 /* Analyze the instruction. */
1569 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1570 global, spill_reg_order);
1572 /* If a no-op set needs more than one reload, this is likely
1573 to be something that needs input address reloads. We
1574 can't get rid of this cleanly later, and it is of no use
1575 anyway, so discard it now.
1576 We only do this when expensive_optimizations is enabled,
1577 since this complements reload inheritance / output
1578 reload deletion, and it can make debugging harder. */
1579 if (flag_expensive_optimizations && n_reloads > 1)
1581 rtx set = single_set (insn);
1583 && SET_SRC (set) == SET_DEST (set)
1584 && REG_P (SET_SRC (set))
1585 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1588 /* Delete it from the reload chain. */
1590 chain->prev->next = next;
1592 reload_insn_chain = next;
1594 next->prev = chain->prev;
1595 chain->next = unused_insn_chains;
1596 unused_insn_chains = chain;
1601 update_eliminable_offsets ();
1603 /* Remember for later shortcuts which insns had any reloads or
1604 register eliminations. */
1605 chain->need_elim = did_elimination;
1606 chain->need_reload = n_reloads > 0;
1607 chain->need_operand_change = operands_changed;
1609 /* Discard any register replacements done. */
1610 if (did_elimination)
1612 obstack_free (&reload_obstack, reload_insn_firstobj);
1613 PATTERN (insn) = old_body;
1614 INSN_CODE (insn) = old_code;
1615 REG_NOTES (insn) = old_notes;
1616 something_needs_elimination = 1;
1619 something_needs_operands_changed |= operands_changed;
1623 copy_reloads (chain);
1624 *pprev_reload = chain;
1625 pprev_reload = &chain->next_need_reload;
1632 /* Comparison function for qsort to decide which of two reloads
1633 should be handled first. *P1 and *P2 are the reload numbers. */
1636 reload_reg_class_lower (const void *r1p, const void *r2p)
1638 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1641 /* Consider required reloads before optional ones. */
1642 t = rld[r1].optional - rld[r2].optional;
1646 /* Count all solitary classes before non-solitary ones. */
1647 t = ((reg_class_size[(int) rld[r2].class] == 1)
1648 - (reg_class_size[(int) rld[r1].class] == 1));
1652 /* Aside from solitaires, consider all multi-reg groups first. */
1653 t = rld[r2].nregs - rld[r1].nregs;
1657 /* Consider reloads in order of increasing reg-class number. */
1658 t = (int) rld[r1].class - (int) rld[r2].class;
1662 /* If reloads are equally urgent, sort by reload number,
1663 so that the results of qsort leave nothing to chance. */
1667 /* The cost of spilling each hard reg. */
1668 static int spill_cost[FIRST_PSEUDO_REGISTER];
1670 /* When spilling multiple hard registers, we use SPILL_COST for the first
1671 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1672 only the first hard reg for a multi-reg pseudo. */
1673 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1675 /* Update the spill cost arrays, considering that pseudo REG is live. */
1678 count_pseudo (int reg)
1680 int freq = REG_FREQ (reg);
1681 int r = reg_renumber[reg];
1684 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1685 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1688 SET_REGNO_REG_SET (&pseudos_counted, reg);
1690 gcc_assert (r >= 0);
1692 spill_add_cost[r] += freq;
1694 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1696 spill_cost[r + nregs] += freq;
1699 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1700 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1703 order_regs_for_reload (struct insn_chain *chain)
1706 HARD_REG_SET used_by_pseudos;
1707 HARD_REG_SET used_by_pseudos2;
1708 reg_set_iterator rsi;
1710 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1712 memset (spill_cost, 0, sizeof spill_cost);
1713 memset (spill_add_cost, 0, sizeof spill_add_cost);
1715 /* Count number of uses of each hard reg by pseudo regs allocated to it
1716 and then order them by decreasing use. First exclude hard registers
1717 that are live in or across this insn. */
1719 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1720 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1721 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1722 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1724 /* Now find out which pseudos are allocated to it, and update
1726 CLEAR_REG_SET (&pseudos_counted);
1728 EXECUTE_IF_SET_IN_REG_SET
1729 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1733 EXECUTE_IF_SET_IN_REG_SET
1734 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1738 CLEAR_REG_SET (&pseudos_counted);
1741 /* Vector of reload-numbers showing the order in which the reloads should
1743 static short reload_order[MAX_RELOADS];
1745 /* This is used to keep track of the spill regs used in one insn. */
1746 static HARD_REG_SET used_spill_regs_local;
1748 /* We decided to spill hard register SPILLED, which has a size of
1749 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1750 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1751 update SPILL_COST/SPILL_ADD_COST. */
1754 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1756 int r = reg_renumber[reg];
1757 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1759 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1760 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1763 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1765 spill_add_cost[r] -= REG_FREQ (reg);
1767 spill_cost[r + nregs] -= REG_FREQ (reg);
1770 /* Find reload register to use for reload number ORDER. */
1773 find_reg (struct insn_chain *chain, int order)
1775 int rnum = reload_order[order];
1776 struct reload *rl = rld + rnum;
1777 int best_cost = INT_MAX;
1781 HARD_REG_SET not_usable;
1782 HARD_REG_SET used_by_other_reload;
1783 reg_set_iterator rsi;
1785 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1786 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1787 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1789 CLEAR_HARD_REG_SET (used_by_other_reload);
1790 for (k = 0; k < order; k++)
1792 int other = reload_order[k];
1794 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1795 for (j = 0; j < rld[other].nregs; j++)
1796 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1799 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1801 unsigned int regno = i;
1803 if (! TEST_HARD_REG_BIT (not_usable, regno)
1804 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1805 && HARD_REGNO_MODE_OK (regno, rl->mode))
1807 int this_cost = spill_cost[regno];
1809 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1811 for (j = 1; j < this_nregs; j++)
1813 this_cost += spill_add_cost[regno + j];
1814 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1815 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1820 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1822 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1824 if (this_cost < best_cost
1825 /* Among registers with equal cost, prefer caller-saved ones, or
1826 use REG_ALLOC_ORDER if it is defined. */
1827 || (this_cost == best_cost
1828 #ifdef REG_ALLOC_ORDER
1829 && (inv_reg_alloc_order[regno]
1830 < inv_reg_alloc_order[best_reg])
1832 && call_used_regs[regno]
1833 && ! call_used_regs[best_reg]
1838 best_cost = this_cost;
1846 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1848 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1849 rl->regno = best_reg;
1851 EXECUTE_IF_SET_IN_REG_SET
1852 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1854 count_spilled_pseudo (best_reg, rl->nregs, j);
1857 EXECUTE_IF_SET_IN_REG_SET
1858 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1860 count_spilled_pseudo (best_reg, rl->nregs, j);
1863 for (i = 0; i < rl->nregs; i++)
1865 gcc_assert (spill_cost[best_reg + i] == 0);
1866 gcc_assert (spill_add_cost[best_reg + i] == 0);
1867 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1872 /* Find more reload regs to satisfy the remaining need of an insn, which
1874 Do it by ascending class number, since otherwise a reg
1875 might be spilled for a big class and might fail to count
1876 for a smaller class even though it belongs to that class. */
1879 find_reload_regs (struct insn_chain *chain)
1883 /* In order to be certain of getting the registers we need,
1884 we must sort the reloads into order of increasing register class.
1885 Then our grabbing of reload registers will parallel the process
1886 that provided the reload registers. */
1887 for (i = 0; i < chain->n_reloads; i++)
1889 /* Show whether this reload already has a hard reg. */
1890 if (chain->rld[i].reg_rtx)
1892 int regno = REGNO (chain->rld[i].reg_rtx);
1893 chain->rld[i].regno = regno;
1895 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1898 chain->rld[i].regno = -1;
1899 reload_order[i] = i;
1902 n_reloads = chain->n_reloads;
1903 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1905 CLEAR_HARD_REG_SET (used_spill_regs_local);
1908 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1910 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1912 /* Compute the order of preference for hard registers to spill. */
1914 order_regs_for_reload (chain);
1916 for (i = 0; i < n_reloads; i++)
1918 int r = reload_order[i];
1920 /* Ignore reloads that got marked inoperative. */
1921 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1922 && ! rld[r].optional
1923 && rld[r].regno == -1)
1924 if (! find_reg (chain, i))
1927 fprintf (dump_file, "reload failure for reload %d\n", r);
1928 spill_failure (chain->insn, rld[r].class);
1934 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1935 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1937 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1941 select_reload_regs (void)
1943 struct insn_chain *chain;
1945 /* Try to satisfy the needs for each insn. */
1946 for (chain = insns_need_reload; chain != 0;
1947 chain = chain->next_need_reload)
1948 find_reload_regs (chain);
1951 /* Delete all insns that were inserted by emit_caller_save_insns during
1954 delete_caller_save_insns (void)
1956 struct insn_chain *c = reload_insn_chain;
1960 while (c != 0 && c->is_caller_save_insn)
1962 struct insn_chain *next = c->next;
1965 if (c == reload_insn_chain)
1966 reload_insn_chain = next;
1970 next->prev = c->prev;
1972 c->prev->next = next;
1973 c->next = unused_insn_chains;
1974 unused_insn_chains = c;
1982 /* Handle the failure to find a register to spill.
1983 INSN should be one of the insns which needed this particular spill reg. */
1986 spill_failure (rtx insn, enum reg_class class)
1988 if (asm_noperands (PATTERN (insn)) >= 0)
1989 error_for_asm (insn, "can't find a register in class %qs while "
1990 "reloading %<asm%>",
1991 reg_class_names[class]);
1994 error ("unable to find a register to spill in class %qs",
1995 reg_class_names[class]);
1999 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2000 debug_reload_to_stream (dump_file);
2002 fatal_insn ("this is the insn:", insn);
2006 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2007 data that is dead in INSN. */
2010 delete_dead_insn (rtx insn)
2012 rtx prev = prev_real_insn (insn);
2015 /* If the previous insn sets a register that dies in our insn, delete it
2017 if (prev && GET_CODE (PATTERN (prev)) == SET
2018 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2019 && reg_mentioned_p (prev_dest, PATTERN (insn))
2020 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2021 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2022 delete_dead_insn (prev);
2024 SET_INSN_DELETED (insn);
2027 /* Modify the home of pseudo-reg I.
2028 The new home is present in reg_renumber[I].
2030 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2031 or it may be -1, meaning there is none or it is not relevant.
2032 This is used so that all pseudos spilled from a given hard reg
2033 can share one stack slot. */
2036 alter_reg (int i, int from_reg)
2038 /* When outputting an inline function, this can happen
2039 for a reg that isn't actually used. */
2040 if (regno_reg_rtx[i] == 0)
2043 /* If the reg got changed to a MEM at rtl-generation time,
2045 if (!REG_P (regno_reg_rtx[i]))
2048 /* Modify the reg-rtx to contain the new hard reg
2049 number or else to contain its pseudo reg number. */
2050 SET_REGNO (regno_reg_rtx[i],
2051 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2053 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2054 allocate a stack slot for it. */
2056 if (reg_renumber[i] < 0
2057 && REG_N_REFS (i) > 0
2058 && reg_equiv_constant[i] == 0
2059 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2060 && reg_equiv_memory_loc[i] == 0)
2063 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2064 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2065 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2066 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2067 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2070 /* Each pseudo reg has an inherent size which comes from its own mode,
2071 and a total size which provides room for paradoxical subregs
2072 which refer to the pseudo reg in wider modes.
2074 We can use a slot already allocated if it provides both
2075 enough inherent space and enough total space.
2076 Otherwise, we allocate a new slot, making sure that it has no less
2077 inherent space, and no less total space, then the previous slot. */
2080 HOST_WIDE_INT alias_set = new_alias_set ();
2082 /* No known place to spill from => no slot to reuse. */
2083 x = assign_stack_local (mode, total_size,
2084 min_align > inherent_align
2085 || total_size > inherent_size ? -1 : 0);
2086 if (BYTES_BIG_ENDIAN)
2087 /* Cancel the big-endian correction done in assign_stack_local.
2088 Get the address of the beginning of the slot.
2089 This is so we can do a big-endian correction unconditionally
2091 adjust = inherent_size - total_size;
2093 /* Nothing can alias this slot except this pseudo. */
2094 set_mem_alias_set (x, alias_set);
2095 dse_record_singleton_alias_set (alias_set, mode);
2098 /* Reuse a stack slot if possible. */
2099 else if (spill_stack_slot[from_reg] != 0
2100 && spill_stack_slot_width[from_reg] >= total_size
2101 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2103 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2104 x = spill_stack_slot[from_reg];
2105 /* Allocate a bigger slot. */
2108 /* Compute maximum size needed, both for inherent size
2109 and for total size. */
2112 if (spill_stack_slot[from_reg])
2114 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2116 mode = GET_MODE (spill_stack_slot[from_reg]);
2117 if (spill_stack_slot_width[from_reg] > total_size)
2118 total_size = spill_stack_slot_width[from_reg];
2119 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2120 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2123 /* Make a slot with that size. */
2124 x = assign_stack_local (mode, total_size,
2125 min_align > inherent_align
2126 || total_size > inherent_size ? -1 : 0);
2129 /* All pseudos mapped to this slot can alias each other. */
2130 if (spill_stack_slot[from_reg])
2132 HOST_WIDE_INT alias_set
2133 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2134 set_mem_alias_set (x, alias_set);
2135 dse_invalidate_singleton_alias_set (alias_set);
2139 HOST_WIDE_INT alias_set = new_alias_set ();
2140 set_mem_alias_set (x, alias_set);
2141 dse_record_singleton_alias_set (alias_set, mode);
2144 if (BYTES_BIG_ENDIAN)
2146 /* Cancel the big-endian correction done in assign_stack_local.
2147 Get the address of the beginning of the slot.
2148 This is so we can do a big-endian correction unconditionally
2150 adjust = GET_MODE_SIZE (mode) - total_size;
2153 = adjust_address_nv (x, mode_for_size (total_size
2159 spill_stack_slot[from_reg] = stack_slot;
2160 spill_stack_slot_width[from_reg] = total_size;
2163 /* On a big endian machine, the "address" of the slot
2164 is the address of the low part that fits its inherent mode. */
2165 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2166 adjust += (total_size - inherent_size);
2168 /* If we have any adjustment to make, or if the stack slot is the
2169 wrong mode, make a new stack slot. */
2170 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2172 /* If we have a decl for the original register, set it for the
2173 memory. If this is a shared MEM, make a copy. */
2174 if (REG_EXPR (regno_reg_rtx[i])
2175 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2177 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2179 /* We can do this only for the DECLs home pseudo, not for
2180 any copies of it, since otherwise when the stack slot
2181 is reused, nonoverlapping_memrefs_p might think they
2183 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2185 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2188 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2192 /* Save the stack slot for later. */
2193 reg_equiv_memory_loc[i] = x;
2197 /* Mark the slots in regs_ever_live for the hard regs used by
2198 pseudo-reg number REGNO, accessed in MODE. */
2201 mark_home_live_1 (int regno, enum machine_mode mode)
2205 i = reg_renumber[regno];
2208 lim = end_hard_regno (mode, i);
2210 df_set_regs_ever_live(i++, true);
2213 /* Mark the slots in regs_ever_live for the hard regs
2214 used by pseudo-reg number REGNO. */
2217 mark_home_live (int regno)
2219 if (reg_renumber[regno] >= 0)
2220 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2223 /* This function handles the tracking of elimination offsets around branches.
2225 X is a piece of RTL being scanned.
2227 INSN is the insn that it came from, if any.
2229 INITIAL_P is nonzero if we are to set the offset to be the initial
2230 offset and zero if we are setting the offset of the label to be the
2234 set_label_offsets (rtx x, rtx insn, int initial_p)
2236 enum rtx_code code = GET_CODE (x);
2239 struct elim_table *p;
2244 if (LABEL_REF_NONLOCAL_P (x))
2249 /* ... fall through ... */
2252 /* If we know nothing about this label, set the desired offsets. Note
2253 that this sets the offset at a label to be the offset before a label
2254 if we don't know anything about the label. This is not correct for
2255 the label after a BARRIER, but is the best guess we can make. If
2256 we guessed wrong, we will suppress an elimination that might have
2257 been possible had we been able to guess correctly. */
2259 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2261 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2262 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2263 = (initial_p ? reg_eliminate[i].initial_offset
2264 : reg_eliminate[i].offset);
2265 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2268 /* Otherwise, if this is the definition of a label and it is
2269 preceded by a BARRIER, set our offsets to the known offset of
2273 && (tem = prev_nonnote_insn (insn)) != 0
2275 set_offsets_for_label (insn);
2277 /* If neither of the above cases is true, compare each offset
2278 with those previously recorded and suppress any eliminations
2279 where the offsets disagree. */
2281 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2282 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2283 != (initial_p ? reg_eliminate[i].initial_offset
2284 : reg_eliminate[i].offset))
2285 reg_eliminate[i].can_eliminate = 0;
2290 set_label_offsets (PATTERN (insn), insn, initial_p);
2292 /* ... fall through ... */
2296 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2297 and hence must have all eliminations at their initial offsets. */
2298 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2299 if (REG_NOTE_KIND (tem) == REG_LABEL)
2300 set_label_offsets (XEXP (tem, 0), insn, 1);
2306 /* Each of the labels in the parallel or address vector must be
2307 at their initial offsets. We want the first field for PARALLEL
2308 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2310 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2311 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2316 /* We only care about setting PC. If the source is not RETURN,
2317 IF_THEN_ELSE, or a label, disable any eliminations not at
2318 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2319 isn't one of those possibilities. For branches to a label,
2320 call ourselves recursively.
2322 Note that this can disable elimination unnecessarily when we have
2323 a non-local goto since it will look like a non-constant jump to
2324 someplace in the current function. This isn't a significant
2325 problem since such jumps will normally be when all elimination
2326 pairs are back to their initial offsets. */
2328 if (SET_DEST (x) != pc_rtx)
2331 switch (GET_CODE (SET_SRC (x)))
2338 set_label_offsets (SET_SRC (x), insn, initial_p);
2342 tem = XEXP (SET_SRC (x), 1);
2343 if (GET_CODE (tem) == LABEL_REF)
2344 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2345 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2348 tem = XEXP (SET_SRC (x), 2);
2349 if (GET_CODE (tem) == LABEL_REF)
2350 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2351 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2359 /* If we reach here, all eliminations must be at their initial
2360 offset because we are doing a jump to a variable address. */
2361 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2362 if (p->offset != p->initial_offset)
2363 p->can_eliminate = 0;
2371 /* Scan X and replace any eliminable registers (such as fp) with a
2372 replacement (such as sp), plus an offset.
2374 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2375 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2376 MEM, we are allowed to replace a sum of a register and the constant zero
2377 with the register, which we cannot do outside a MEM. In addition, we need
2378 to record the fact that a register is referenced outside a MEM.
2380 If INSN is an insn, it is the insn containing X. If we replace a REG
2381 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2382 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2383 the REG is being modified.
2385 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2386 That's used when we eliminate in expressions stored in notes.
2387 This means, do not set ref_outside_mem even if the reference
2390 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2391 replacements done assuming all offsets are at their initial values. If
2392 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2393 encounter, return the actual location so that find_reloads will do
2394 the proper thing. */
2397 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2398 bool may_use_invariant)
2400 enum rtx_code code = GET_CODE (x);
2401 struct elim_table *ep;
2408 if (! current_function_decl)
2430 /* First handle the case where we encounter a bare register that
2431 is eliminable. Replace it with a PLUS. */
2432 if (regno < FIRST_PSEUDO_REGISTER)
2434 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2436 if (ep->from_rtx == x && ep->can_eliminate)
2437 return plus_constant (ep->to_rtx, ep->previous_offset);
2440 else if (reg_renumber && reg_renumber[regno] < 0
2441 && reg_equiv_invariant && reg_equiv_invariant[regno])
2443 if (may_use_invariant)
2444 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2445 mem_mode, insn, true);
2446 /* There exists at least one use of REGNO that cannot be
2447 eliminated. Prevent the defining insn from being deleted. */
2448 reg_equiv_init[regno] = NULL_RTX;
2449 alter_reg (regno, -1);
2453 /* You might think handling MINUS in a manner similar to PLUS is a
2454 good idea. It is not. It has been tried multiple times and every
2455 time the change has had to have been reverted.
2457 Other parts of reload know a PLUS is special (gen_reload for example)
2458 and require special code to handle code a reloaded PLUS operand.
2460 Also consider backends where the flags register is clobbered by a
2461 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2462 lea instruction comes to mind). If we try to reload a MINUS, we
2463 may kill the flags register that was holding a useful value.
2465 So, please before trying to handle MINUS, consider reload as a
2466 whole instead of this little section as well as the backend issues. */
2468 /* If this is the sum of an eliminable register and a constant, rework
2470 if (REG_P (XEXP (x, 0))
2471 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2472 && CONSTANT_P (XEXP (x, 1)))
2474 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2476 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2478 /* The only time we want to replace a PLUS with a REG (this
2479 occurs when the constant operand of the PLUS is the negative
2480 of the offset) is when we are inside a MEM. We won't want
2481 to do so at other times because that would change the
2482 structure of the insn in a way that reload can't handle.
2483 We special-case the commonest situation in
2484 eliminate_regs_in_insn, so just replace a PLUS with a
2485 PLUS here, unless inside a MEM. */
2486 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2487 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2490 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2491 plus_constant (XEXP (x, 1),
2492 ep->previous_offset));
2495 /* If the register is not eliminable, we are done since the other
2496 operand is a constant. */
2500 /* If this is part of an address, we want to bring any constant to the
2501 outermost PLUS. We will do this by doing register replacement in
2502 our operands and seeing if a constant shows up in one of them.
2504 Note that there is no risk of modifying the structure of the insn,
2505 since we only get called for its operands, thus we are either
2506 modifying the address inside a MEM, or something like an address
2507 operand of a load-address insn. */
2510 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2511 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2513 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2515 /* If one side is a PLUS and the other side is a pseudo that
2516 didn't get a hard register but has a reg_equiv_constant,
2517 we must replace the constant here since it may no longer
2518 be in the position of any operand. */
2519 if (GET_CODE (new0) == PLUS && REG_P (new1)
2520 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2521 && reg_renumber[REGNO (new1)] < 0
2522 && reg_equiv_constant != 0
2523 && reg_equiv_constant[REGNO (new1)] != 0)
2524 new1 = reg_equiv_constant[REGNO (new1)];
2525 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2526 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2527 && reg_renumber[REGNO (new0)] < 0
2528 && reg_equiv_constant[REGNO (new0)] != 0)
2529 new0 = reg_equiv_constant[REGNO (new0)];
2531 new = form_sum (new0, new1);
2533 /* As above, if we are not inside a MEM we do not want to
2534 turn a PLUS into something else. We might try to do so here
2535 for an addition of 0 if we aren't optimizing. */
2536 if (! mem_mode && GET_CODE (new) != PLUS)
2537 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2545 /* If this is the product of an eliminable register and a
2546 constant, apply the distribute law and move the constant out
2547 so that we have (plus (mult ..) ..). This is needed in order
2548 to keep load-address insns valid. This case is pathological.
2549 We ignore the possibility of overflow here. */
2550 if (REG_P (XEXP (x, 0))
2551 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2552 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2553 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2555 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2558 /* Refs inside notes don't count for this purpose. */
2559 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2560 || GET_CODE (insn) == INSN_LIST)))
2561 ep->ref_outside_mem = 1;
2564 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2565 ep->previous_offset * INTVAL (XEXP (x, 1)));
2568 /* ... fall through ... */
2572 /* See comments before PLUS about handling MINUS. */
2574 case DIV: case UDIV:
2575 case MOD: case UMOD:
2576 case AND: case IOR: case XOR:
2577 case ROTATERT: case ROTATE:
2578 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2580 case GE: case GT: case GEU: case GTU:
2581 case LE: case LT: case LEU: case LTU:
2583 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2584 rtx new1 = XEXP (x, 1)
2585 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2587 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2588 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2593 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2596 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2597 if (new != XEXP (x, 0))
2599 /* If this is a REG_DEAD note, it is not valid anymore.
2600 Using the eliminated version could result in creating a
2601 REG_DEAD note for the stack or frame pointer. */
2602 if (GET_MODE (x) == REG_DEAD)
2604 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2607 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2611 /* ... fall through ... */
2614 /* Now do eliminations in the rest of the chain. If this was
2615 an EXPR_LIST, this might result in allocating more memory than is
2616 strictly needed, but it simplifies the code. */
2619 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2620 if (new != XEXP (x, 1))
2622 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2630 /* We do not support elimination of a register that is modified.
2631 elimination_effects has already make sure that this does not
2637 /* We do not support elimination of a register that is modified.
2638 elimination_effects has already make sure that this does not
2639 happen. The only remaining case we need to consider here is
2640 that the increment value may be an eliminable register. */
2641 if (GET_CODE (XEXP (x, 1)) == PLUS
2642 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2644 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2647 if (new != XEXP (XEXP (x, 1), 1))
2648 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2649 gen_rtx_PLUS (GET_MODE (x),
2654 case STRICT_LOW_PART:
2656 case SIGN_EXTEND: case ZERO_EXTEND:
2657 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2658 case FLOAT: case FIX:
2659 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2668 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2669 if (new != XEXP (x, 0))
2670 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2674 /* Similar to above processing, but preserve SUBREG_BYTE.
2675 Convert (subreg (mem)) to (mem) if not paradoxical.
2676 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2677 pseudo didn't get a hard reg, we must replace this with the
2678 eliminated version of the memory location because push_reload
2679 may do the replacement in certain circumstances. */
2680 if (REG_P (SUBREG_REG (x))
2681 && (GET_MODE_SIZE (GET_MODE (x))
2682 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2683 && reg_equiv_memory_loc != 0
2684 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2686 new = SUBREG_REG (x);
2689 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2691 if (new != SUBREG_REG (x))
2693 int x_size = GET_MODE_SIZE (GET_MODE (x));
2694 int new_size = GET_MODE_SIZE (GET_MODE (new));
2697 && ((x_size < new_size
2698 #ifdef WORD_REGISTER_OPERATIONS
2699 /* On these machines, combine can create rtl of the form
2700 (set (subreg:m1 (reg:m2 R) 0) ...)
2701 where m1 < m2, and expects something interesting to
2702 happen to the entire word. Moreover, it will use the
2703 (reg:m2 R) later, expecting all bits to be preserved.
2704 So if the number of words is the same, preserve the
2705 subreg so that push_reload can see it. */
2706 && ! ((x_size - 1) / UNITS_PER_WORD
2707 == (new_size -1 ) / UNITS_PER_WORD)
2710 || x_size == new_size)
2712 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2714 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2720 /* Our only special processing is to pass the mode of the MEM to our
2721 recursive call and copy the flags. While we are here, handle this
2722 case more efficiently. */
2724 replace_equiv_address_nv (x,
2725 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2729 /* Handle insn_list USE that a call to a pure function may generate. */
2730 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2731 if (new != XEXP (x, 0))
2732 return gen_rtx_USE (GET_MODE (x), new);
2744 /* Process each of our operands recursively. If any have changed, make a
2746 fmt = GET_RTX_FORMAT (code);
2747 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2751 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2752 if (new != XEXP (x, i) && ! copied)
2754 x = shallow_copy_rtx (x);
2759 else if (*fmt == 'E')
2762 for (j = 0; j < XVECLEN (x, i); j++)
2764 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2765 if (new != XVECEXP (x, i, j) && ! copied_vec)
2767 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2771 x = shallow_copy_rtx (x);
2774 XVEC (x, i) = new_v;
2777 XVECEXP (x, i, j) = new;
2786 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2788 return eliminate_regs_1 (x, mem_mode, insn, false);
2791 /* Scan rtx X for modifications of elimination target registers. Update
2792 the table of eliminables to reflect the changed state. MEM_MODE is
2793 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2796 elimination_effects (rtx x, enum machine_mode mem_mode)
2798 enum rtx_code code = GET_CODE (x);
2799 struct elim_table *ep;
2823 /* First handle the case where we encounter a bare register that
2824 is eliminable. Replace it with a PLUS. */
2825 if (regno < FIRST_PSEUDO_REGISTER)
2827 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2829 if (ep->from_rtx == x && ep->can_eliminate)
2832 ep->ref_outside_mem = 1;
2837 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2838 && reg_equiv_constant[regno]
2839 && ! function_invariant_p (reg_equiv_constant[regno]))
2840 elimination_effects (reg_equiv_constant[regno], mem_mode);
2849 /* If we modify the source of an elimination rule, disable it. */
2850 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2851 if (ep->from_rtx == XEXP (x, 0))
2852 ep->can_eliminate = 0;
2854 /* If we modify the target of an elimination rule by adding a constant,
2855 update its offset. If we modify the target in any other way, we'll
2856 have to disable the rule as well. */
2857 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2858 if (ep->to_rtx == XEXP (x, 0))
2860 int size = GET_MODE_SIZE (mem_mode);
2862 /* If more bytes than MEM_MODE are pushed, account for them. */
2863 #ifdef PUSH_ROUNDING
2864 if (ep->to_rtx == stack_pointer_rtx)
2865 size = PUSH_ROUNDING (size);
2867 if (code == PRE_DEC || code == POST_DEC)
2869 else if (code == PRE_INC || code == POST_INC)
2871 else if (code == PRE_MODIFY || code == POST_MODIFY)
2873 if (GET_CODE (XEXP (x, 1)) == PLUS
2874 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2875 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2876 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2878 ep->can_eliminate = 0;
2882 /* These two aren't unary operators. */
2883 if (code == POST_MODIFY || code == PRE_MODIFY)
2886 /* Fall through to generic unary operation case. */
2887 case STRICT_LOW_PART:
2889 case SIGN_EXTEND: case ZERO_EXTEND:
2890 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2891 case FLOAT: case FIX:
2892 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2901 elimination_effects (XEXP (x, 0), mem_mode);
2905 if (REG_P (SUBREG_REG (x))
2906 && (GET_MODE_SIZE (GET_MODE (x))
2907 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2908 && reg_equiv_memory_loc != 0
2909 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2912 elimination_effects (SUBREG_REG (x), mem_mode);
2916 /* If using a register that is the source of an eliminate we still
2917 think can be performed, note it cannot be performed since we don't
2918 know how this register is used. */
2919 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2920 if (ep->from_rtx == XEXP (x, 0))
2921 ep->can_eliminate = 0;
2923 elimination_effects (XEXP (x, 0), mem_mode);
2927 /* If clobbering a register that is the replacement register for an
2928 elimination we still think can be performed, note that it cannot
2929 be performed. Otherwise, we need not be concerned about it. */
2930 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2931 if (ep->to_rtx == XEXP (x, 0))
2932 ep->can_eliminate = 0;
2934 elimination_effects (XEXP (x, 0), mem_mode);
2938 /* Check for setting a register that we know about. */
2939 if (REG_P (SET_DEST (x)))
2941 /* See if this is setting the replacement register for an
2944 If DEST is the hard frame pointer, we do nothing because we
2945 assume that all assignments to the frame pointer are for
2946 non-local gotos and are being done at a time when they are valid
2947 and do not disturb anything else. Some machines want to
2948 eliminate a fake argument pointer (or even a fake frame pointer)
2949 with either the real frame or the stack pointer. Assignments to
2950 the hard frame pointer must not prevent this elimination. */
2952 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2954 if (ep->to_rtx == SET_DEST (x)
2955 && SET_DEST (x) != hard_frame_pointer_rtx)
2957 /* If it is being incremented, adjust the offset. Otherwise,
2958 this elimination can't be done. */
2959 rtx src = SET_SRC (x);
2961 if (GET_CODE (src) == PLUS
2962 && XEXP (src, 0) == SET_DEST (x)
2963 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2964 ep->offset -= INTVAL (XEXP (src, 1));
2966 ep->can_eliminate = 0;
2970 elimination_effects (SET_DEST (x), 0);
2971 elimination_effects (SET_SRC (x), 0);
2975 /* Our only special processing is to pass the mode of the MEM to our
2977 elimination_effects (XEXP (x, 0), GET_MODE (x));
2984 fmt = GET_RTX_FORMAT (code);
2985 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2988 elimination_effects (XEXP (x, i), mem_mode);
2989 else if (*fmt == 'E')
2990 for (j = 0; j < XVECLEN (x, i); j++)
2991 elimination_effects (XVECEXP (x, i, j), mem_mode);
2995 /* Descend through rtx X and verify that no references to eliminable registers
2996 remain. If any do remain, mark the involved register as not
3000 check_eliminable_occurrences (rtx x)
3009 code = GET_CODE (x);
3011 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3013 struct elim_table *ep;
3015 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3016 if (ep->from_rtx == x)
3017 ep->can_eliminate = 0;
3021 fmt = GET_RTX_FORMAT (code);
3022 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3025 check_eliminable_occurrences (XEXP (x, i));
3026 else if (*fmt == 'E')
3029 for (j = 0; j < XVECLEN (x, i); j++)
3030 check_eliminable_occurrences (XVECEXP (x, i, j));
3035 /* Scan INSN and eliminate all eliminable registers in it.
3037 If REPLACE is nonzero, do the replacement destructively. Also
3038 delete the insn as dead it if it is setting an eliminable register.
3040 If REPLACE is zero, do all our allocations in reload_obstack.
3042 If no eliminations were done and this insn doesn't require any elimination
3043 processing (these are not identical conditions: it might be updating sp,
3044 but not referencing fp; this needs to be seen during reload_as_needed so
3045 that the offset between fp and sp can be taken into consideration), zero
3046 is returned. Otherwise, 1 is returned. */
3049 eliminate_regs_in_insn (rtx insn, int replace)
3051 int icode = recog_memoized (insn);
3052 rtx old_body = PATTERN (insn);
3053 int insn_is_asm = asm_noperands (old_body) >= 0;
3054 rtx old_set = single_set (insn);
3058 rtx substed_operand[MAX_RECOG_OPERANDS];
3059 rtx orig_operand[MAX_RECOG_OPERANDS];
3060 struct elim_table *ep;
3061 rtx plus_src, plus_cst_src;
3063 if (! insn_is_asm && icode < 0)
3065 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3066 || GET_CODE (PATTERN (insn)) == CLOBBER
3067 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3068 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3069 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3073 if (old_set != 0 && REG_P (SET_DEST (old_set))
3074 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3076 /* Check for setting an eliminable register. */
3077 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3078 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3080 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3081 /* If this is setting the frame pointer register to the
3082 hardware frame pointer register and this is an elimination
3083 that will be done (tested above), this insn is really
3084 adjusting the frame pointer downward to compensate for
3085 the adjustment done before a nonlocal goto. */
3086 if (ep->from == FRAME_POINTER_REGNUM
3087 && ep->to == HARD_FRAME_POINTER_REGNUM)
3089 rtx base = SET_SRC (old_set);
3090 rtx base_insn = insn;
3091 HOST_WIDE_INT offset = 0;
3093 while (base != ep->to_rtx)
3095 rtx prev_insn, prev_set;
3097 if (GET_CODE (base) == PLUS
3098 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3100 offset += INTVAL (XEXP (base, 1));
3101 base = XEXP (base, 0);
3103 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3104 && (prev_set = single_set (prev_insn)) != 0
3105 && rtx_equal_p (SET_DEST (prev_set), base))
3107 base = SET_SRC (prev_set);
3108 base_insn = prev_insn;
3114 if (base == ep->to_rtx)
3117 = plus_constant (ep->to_rtx, offset - ep->offset);
3119 new_body = old_body;
3122 new_body = copy_insn (old_body);
3123 if (REG_NOTES (insn))
3124 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3126 PATTERN (insn) = new_body;
3127 old_set = single_set (insn);
3129 /* First see if this insn remains valid when we
3130 make the change. If not, keep the INSN_CODE
3131 the same and let reload fit it up. */
3132 validate_change (insn, &SET_SRC (old_set), src, 1);
3133 validate_change (insn, &SET_DEST (old_set),
3135 if (! apply_change_group ())
3137 SET_SRC (old_set) = src;
3138 SET_DEST (old_set) = ep->to_rtx;
3147 /* In this case this insn isn't serving a useful purpose. We
3148 will delete it in reload_as_needed once we know that this
3149 elimination is, in fact, being done.
3151 If REPLACE isn't set, we can't delete this insn, but needn't
3152 process it since it won't be used unless something changes. */
3155 delete_dead_insn (insn);
3163 /* We allow one special case which happens to work on all machines we
3164 currently support: a single set with the source or a REG_EQUAL
3165 note being a PLUS of an eliminable register and a constant. */
3166 plus_src = plus_cst_src = 0;
3167 if (old_set && REG_P (SET_DEST (old_set)))
3169 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3170 plus_src = SET_SRC (old_set);
3171 /* First see if the source is of the form (plus (...) CST). */
3173 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3174 plus_cst_src = plus_src;
3175 else if (REG_P (SET_SRC (old_set))
3178 /* Otherwise, see if we have a REG_EQUAL note of the form
3179 (plus (...) CST). */
3181 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3183 if ((REG_NOTE_KIND (links) == REG_EQUAL
3184 || REG_NOTE_KIND (links) == REG_EQUIV)
3185 && GET_CODE (XEXP (links, 0)) == PLUS
3186 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3188 plus_cst_src = XEXP (links, 0);
3194 /* Check that the first operand of the PLUS is a hard reg or
3195 the lowpart subreg of one. */
3198 rtx reg = XEXP (plus_cst_src, 0);
3199 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3200 reg = SUBREG_REG (reg);
3202 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3208 rtx reg = XEXP (plus_cst_src, 0);
3209 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3211 if (GET_CODE (reg) == SUBREG)
3212 reg = SUBREG_REG (reg);
3214 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3215 if (ep->from_rtx == reg && ep->can_eliminate)
3217 rtx to_rtx = ep->to_rtx;
3218 offset += ep->offset;
3219 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3221 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3222 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3224 /* If we have a nonzero offset, and the source is already
3225 a simple REG, the following transformation would
3226 increase the cost of the insn by replacing a simple REG
3227 with (plus (reg sp) CST). So try only when we already
3228 had a PLUS before. */
3229 if (offset == 0 || plus_src)
3231 rtx new_src = plus_constant (to_rtx, offset);
3233 new_body = old_body;
3236 new_body = copy_insn (old_body);
3237 if (REG_NOTES (insn))
3238 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3240 PATTERN (insn) = new_body;
3241 old_set = single_set (insn);
3243 /* First see if this insn remains valid when we make the
3244 change. If not, try to replace the whole pattern with
3245 a simple set (this may help if the original insn was a
3246 PARALLEL that was only recognized as single_set due to
3247 REG_UNUSED notes). If this isn't valid either, keep
3248 the INSN_CODE the same and let reload fix it up. */
3249 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3251 rtx new_pat = gen_rtx_SET (VOIDmode,
3252 SET_DEST (old_set), new_src);
3254 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3255 SET_SRC (old_set) = new_src;
3262 /* This can't have an effect on elimination offsets, so skip right
3268 /* Determine the effects of this insn on elimination offsets. */
3269 elimination_effects (old_body, 0);
3271 /* Eliminate all eliminable registers occurring in operands that
3272 can be handled by reload. */
3273 extract_insn (insn);
3274 for (i = 0; i < recog_data.n_operands; i++)
3276 orig_operand[i] = recog_data.operand[i];
3277 substed_operand[i] = recog_data.operand[i];
3279 /* For an asm statement, every operand is eliminable. */
3280 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3282 bool is_set_src, in_plus;
3284 /* Check for setting a register that we know about. */
3285 if (recog_data.operand_type[i] != OP_IN
3286 && REG_P (orig_operand[i]))
3288 /* If we are assigning to a register that can be eliminated, it
3289 must be as part of a PARALLEL, since the code above handles
3290 single SETs. We must indicate that we can no longer
3291 eliminate this reg. */
3292 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3294 if (ep->from_rtx == orig_operand[i])
3295 ep->can_eliminate = 0;
3298 /* Companion to the above plus substitution, we can allow
3299 invariants as the source of a plain move. */
3301 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3305 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3306 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3310 = eliminate_regs_1 (recog_data.operand[i], 0,
3311 replace ? insn : NULL_RTX,
3312 is_set_src || in_plus);
3313 if (substed_operand[i] != orig_operand[i])
3315 /* Terminate the search in check_eliminable_occurrences at
3317 *recog_data.operand_loc[i] = 0;
3319 /* If an output operand changed from a REG to a MEM and INSN is an
3320 insn, write a CLOBBER insn. */
3321 if (recog_data.operand_type[i] != OP_IN
3322 && REG_P (orig_operand[i])
3323 && MEM_P (substed_operand[i])
3325 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3330 for (i = 0; i < recog_data.n_dups; i++)
3331 *recog_data.dup_loc[i]
3332 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3334 /* If any eliminable remain, they aren't eliminable anymore. */
3335 check_eliminable_occurrences (old_body);
3337 /* Substitute the operands; the new values are in the substed_operand
3339 for (i = 0; i < recog_data.n_operands; i++)
3340 *recog_data.operand_loc[i] = substed_operand[i];
3341 for (i = 0; i < recog_data.n_dups; i++)
3342 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3344 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3345 re-recognize the insn. We do this in case we had a simple addition
3346 but now can do this as a load-address. This saves an insn in this
3348 If re-recognition fails, the old insn code number will still be used,
3349 and some register operands may have changed into PLUS expressions.
3350 These will be handled by find_reloads by loading them into a register
3355 /* If we aren't replacing things permanently and we changed something,
3356 make another copy to ensure that all the RTL is new. Otherwise
3357 things can go wrong if find_reload swaps commutative operands
3358 and one is inside RTL that has been copied while the other is not. */
3359 new_body = old_body;
3362 new_body = copy_insn (old_body);
3363 if (REG_NOTES (insn))
3364 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3366 PATTERN (insn) = new_body;
3368 /* If we had a move insn but now we don't, rerecognize it. This will
3369 cause spurious re-recognition if the old move had a PARALLEL since
3370 the new one still will, but we can't call single_set without
3371 having put NEW_BODY into the insn and the re-recognition won't
3372 hurt in this rare case. */
3373 /* ??? Why this huge if statement - why don't we just rerecognize the
3377 && ((REG_P (SET_SRC (old_set))
3378 && (GET_CODE (new_body) != SET
3379 || !REG_P (SET_SRC (new_body))))
3380 /* If this was a load from or store to memory, compare
3381 the MEM in recog_data.operand to the one in the insn.
3382 If they are not equal, then rerecognize the insn. */
3384 && ((MEM_P (SET_SRC (old_set))
3385 && SET_SRC (old_set) != recog_data.operand[1])
3386 || (MEM_P (SET_DEST (old_set))
3387 && SET_DEST (old_set) != recog_data.operand[0])))
3388 /* If this was an add insn before, rerecognize. */
3389 || GET_CODE (SET_SRC (old_set)) == PLUS))
3391 int new_icode = recog (PATTERN (insn), insn, 0);
3393 INSN_CODE (insn) = new_icode;
3397 /* Restore the old body. If there were any changes to it, we made a copy
3398 of it while the changes were still in place, so we'll correctly return
3399 a modified insn below. */
3402 /* Restore the old body. */
3403 for (i = 0; i < recog_data.n_operands; i++)
3404 *recog_data.operand_loc[i] = orig_operand[i];
3405 for (i = 0; i < recog_data.n_dups; i++)
3406 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3409 /* Update all elimination pairs to reflect the status after the current
3410 insn. The changes we make were determined by the earlier call to
3411 elimination_effects.
3413 We also detect cases where register elimination cannot be done,
3414 namely, if a register would be both changed and referenced outside a MEM
3415 in the resulting insn since such an insn is often undefined and, even if
3416 not, we cannot know what meaning will be given to it. Note that it is
3417 valid to have a register used in an address in an insn that changes it
3418 (presumably with a pre- or post-increment or decrement).
3420 If anything changes, return nonzero. */
3422 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3424 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3425 ep->can_eliminate = 0;
3427 ep->ref_outside_mem = 0;
3429 if (ep->previous_offset != ep->offset)
3434 /* If we changed something, perform elimination in REG_NOTES. This is
3435 needed even when REPLACE is zero because a REG_DEAD note might refer
3436 to a register that we eliminate and could cause a different number
3437 of spill registers to be needed in the final reload pass than in
3439 if (val && REG_NOTES (insn) != 0)
3441 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3446 /* Loop through all elimination pairs.
3447 Recalculate the number not at initial offset.
3449 Compute the maximum offset (minimum offset if the stack does not
3450 grow downward) for each elimination pair. */
3453 update_eliminable_offsets (void)
3455 struct elim_table *ep;
3457 num_not_at_initial_offset = 0;
3458 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3460 ep->previous_offset = ep->offset;
3461 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3462 num_not_at_initial_offset++;
3466 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3467 replacement we currently believe is valid, mark it as not eliminable if X
3468 modifies DEST in any way other than by adding a constant integer to it.
3470 If DEST is the frame pointer, we do nothing because we assume that
3471 all assignments to the hard frame pointer are nonlocal gotos and are being
3472 done at a time when they are valid and do not disturb anything else.
3473 Some machines want to eliminate a fake argument pointer with either the
3474 frame or stack pointer. Assignments to the hard frame pointer must not
3475 prevent this elimination.
3477 Called via note_stores from reload before starting its passes to scan
3478 the insns of the function. */
3481 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3485 /* A SUBREG of a hard register here is just changing its mode. We should
3486 not see a SUBREG of an eliminable hard register, but check just in
3488 if (GET_CODE (dest) == SUBREG)
3489 dest = SUBREG_REG (dest);
3491 if (dest == hard_frame_pointer_rtx)
3494 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3495 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3496 && (GET_CODE (x) != SET
3497 || GET_CODE (SET_SRC (x)) != PLUS
3498 || XEXP (SET_SRC (x), 0) != dest
3499 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3501 reg_eliminate[i].can_eliminate_previous
3502 = reg_eliminate[i].can_eliminate = 0;
3507 /* Verify that the initial elimination offsets did not change since the
3508 last call to set_initial_elim_offsets. This is used to catch cases
3509 where something illegal happened during reload_as_needed that could
3510 cause incorrect code to be generated if we did not check for it. */
3513 verify_initial_elim_offsets (void)
3517 if (!num_eliminable)
3520 #ifdef ELIMINABLE_REGS
3522 struct elim_table *ep;
3524 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3526 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3527 if (t != ep->initial_offset)
3532 INITIAL_FRAME_POINTER_OFFSET (t);
3533 if (t != reg_eliminate[0].initial_offset)
3540 /* Reset all offsets on eliminable registers to their initial values. */
3543 set_initial_elim_offsets (void)
3545 struct elim_table *ep = reg_eliminate;
3547 #ifdef ELIMINABLE_REGS
3548 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3550 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3551 ep->previous_offset = ep->offset = ep->initial_offset;
3554 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3555 ep->previous_offset = ep->offset = ep->initial_offset;
3558 num_not_at_initial_offset = 0;
3561 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3564 set_initial_eh_label_offset (rtx label)
3566 set_label_offsets (label, NULL_RTX, 1);
3569 /* Initialize the known label offsets.
3570 Set a known offset for each forced label to be at the initial offset
3571 of each elimination. We do this because we assume that all
3572 computed jumps occur from a location where each elimination is
3573 at its initial offset.
3574 For all other labels, show that we don't know the offsets. */
3577 set_initial_label_offsets (void)
3580 memset (offsets_known_at, 0, num_labels);
3582 for (x = forced_labels; x; x = XEXP (x, 1))
3584 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3586 for_each_eh_label (set_initial_eh_label_offset);
3589 /* Set all elimination offsets to the known values for the code label given
3593 set_offsets_for_label (rtx insn)
3596 int label_nr = CODE_LABEL_NUMBER (insn);
3597 struct elim_table *ep;
3599 num_not_at_initial_offset = 0;
3600 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3602 ep->offset = ep->previous_offset
3603 = offsets_at[label_nr - first_label_num][i];
3604 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3605 num_not_at_initial_offset++;
3609 /* See if anything that happened changes which eliminations are valid.
3610 For example, on the SPARC, whether or not the frame pointer can
3611 be eliminated can depend on what registers have been used. We need
3612 not check some conditions again (such as flag_omit_frame_pointer)
3613 since they can't have changed. */
3616 update_eliminables (HARD_REG_SET *pset)
3618 int previous_frame_pointer_needed = frame_pointer_needed;
3619 struct elim_table *ep;
3621 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3622 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3623 #ifdef ELIMINABLE_REGS
3624 || ! CAN_ELIMINATE (ep->from, ep->to)
3627 ep->can_eliminate = 0;
3629 /* Look for the case where we have discovered that we can't replace
3630 register A with register B and that means that we will now be
3631 trying to replace register A with register C. This means we can
3632 no longer replace register C with register B and we need to disable
3633 such an elimination, if it exists. This occurs often with A == ap,
3634 B == sp, and C == fp. */
3636 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3638 struct elim_table *op;
3641 if (! ep->can_eliminate && ep->can_eliminate_previous)
3643 /* Find the current elimination for ep->from, if there is a
3645 for (op = reg_eliminate;
3646 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3647 if (op->from == ep->from && op->can_eliminate)
3653 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3655 for (op = reg_eliminate;
3656 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3657 if (op->from == new_to && op->to == ep->to)
3658 op->can_eliminate = 0;
3662 /* See if any registers that we thought we could eliminate the previous
3663 time are no longer eliminable. If so, something has changed and we
3664 must spill the register. Also, recompute the number of eliminable
3665 registers and see if the frame pointer is needed; it is if there is
3666 no elimination of the frame pointer that we can perform. */
3668 frame_pointer_needed = 1;
3669 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3671 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3672 && ep->to != HARD_FRAME_POINTER_REGNUM)
3673 frame_pointer_needed = 0;
3675 if (! ep->can_eliminate && ep->can_eliminate_previous)
3677 ep->can_eliminate_previous = 0;
3678 SET_HARD_REG_BIT (*pset, ep->from);
3683 /* If we didn't need a frame pointer last time, but we do now, spill
3684 the hard frame pointer. */
3685 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3686 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3689 /* Return true if X is used as the target register of an elimination. */
3692 elimination_target_reg_p (rtx x)
3694 struct elim_table *ep;
3696 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3697 if (ep->to_rtx == x && ep->can_eliminate)
3703 /* Initialize the table of registers to eliminate. */
3706 init_elim_table (void)
3708 struct elim_table *ep;
3709 #ifdef ELIMINABLE_REGS
3710 const struct elim_table_1 *ep1;
3714 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3716 /* Does this function require a frame pointer? */
3718 frame_pointer_needed = (! flag_omit_frame_pointer
3719 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3720 and restore sp for alloca. So we can't eliminate
3721 the frame pointer in that case. At some point,
3722 we should improve this by emitting the
3723 sp-adjusting insns for this case. */
3724 || (current_function_calls_alloca
3725 && EXIT_IGNORE_STACK)
3726 || current_function_accesses_prior_frames
3727 || FRAME_POINTER_REQUIRED);
3731 #ifdef ELIMINABLE_REGS
3732 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3733 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3735 ep->from = ep1->from;
3737 ep->can_eliminate = ep->can_eliminate_previous
3738 = (CAN_ELIMINATE (ep->from, ep->to)
3739 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3742 reg_eliminate[0].from = reg_eliminate_1[0].from;
3743 reg_eliminate[0].to = reg_eliminate_1[0].to;
3744 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3745 = ! frame_pointer_needed;
3748 /* Count the number of eliminable registers and build the FROM and TO
3749 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3750 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3751 We depend on this. */
3752 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3754 num_eliminable += ep->can_eliminate;
3755 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3756 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3760 /* Kick all pseudos out of hard register REGNO.
3762 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3763 because we found we can't eliminate some register. In the case, no pseudos
3764 are allowed to be in the register, even if they are only in a block that
3765 doesn't require spill registers, unlike the case when we are spilling this
3766 hard reg to produce another spill register.
3768 Return nonzero if any pseudos needed to be kicked out. */
3771 spill_hard_reg (unsigned int regno, int cant_eliminate)
3777 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3778 df_set_regs_ever_live (regno, true);
3781 /* Spill every pseudo reg that was allocated to this reg
3782 or to something that overlaps this reg. */
3784 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3785 if (reg_renumber[i] >= 0
3786 && (unsigned int) reg_renumber[i] <= regno
3787 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3788 SET_REGNO_REG_SET (&spilled_pseudos, i);
3791 /* After find_reload_regs has been run for all insn that need reloads,
3792 and/or spill_hard_regs was called, this function is used to actually
3793 spill pseudo registers and try to reallocate them. It also sets up the
3794 spill_regs array for use by choose_reload_regs. */
3797 finish_spills (int global)
3799 struct insn_chain *chain;
3800 int something_changed = 0;
3802 reg_set_iterator rsi;
3804 /* Build the spill_regs array for the function. */
3805 /* If there are some registers still to eliminate and one of the spill regs
3806 wasn't ever used before, additional stack space may have to be
3807 allocated to store this register. Thus, we may have changed the offset
3808 between the stack and frame pointers, so mark that something has changed.
3810 One might think that we need only set VAL to 1 if this is a call-used
3811 register. However, the set of registers that must be saved by the
3812 prologue is not identical to the call-used set. For example, the
3813 register used by the call insn for the return PC is a call-used register,
3814 but must be saved by the prologue. */
3817 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3818 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3820 spill_reg_order[i] = n_spills;
3821 spill_regs[n_spills++] = i;
3822 if (num_eliminable && ! df_regs_ever_live_p (i))
3823 something_changed = 1;
3824 df_set_regs_ever_live (i, true);
3827 spill_reg_order[i] = -1;
3829 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3831 /* Record the current hard register the pseudo is allocated to in
3832 pseudo_previous_regs so we avoid reallocating it to the same
3833 hard reg in a later pass. */
3834 gcc_assert (reg_renumber[i] >= 0);
3836 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3837 /* Mark it as no longer having a hard register home. */
3838 reg_renumber[i] = -1;
3839 /* We will need to scan everything again. */
3840 something_changed = 1;
3843 /* Retry global register allocation if possible. */
3846 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3847 /* For every insn that needs reloads, set the registers used as spill
3848 regs in pseudo_forbidden_regs for every pseudo live across the
3850 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3852 EXECUTE_IF_SET_IN_REG_SET
3853 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3855 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3856 chain->used_spill_regs);
3858 EXECUTE_IF_SET_IN_REG_SET
3859 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3861 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3862 chain->used_spill_regs);
3866 /* Retry allocating the spilled pseudos. For each reg, merge the
3867 various reg sets that indicate which hard regs can't be used,
3868 and call retry_global_alloc.
3869 We change spill_pseudos here to only contain pseudos that did not
3870 get a new hard register. */
3871 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3872 if (reg_old_renumber[i] != reg_renumber[i])
3874 HARD_REG_SET forbidden;
3875 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3876 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3877 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3878 retry_global_alloc (i, forbidden);
3879 if (reg_renumber[i] >= 0)
3880 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3884 /* Fix up the register information in the insn chain.
3885 This involves deleting those of the spilled pseudos which did not get
3886 a new hard register home from the live_{before,after} sets. */
3887 for (chain = reload_insn_chain; chain; chain = chain->next)
3889 HARD_REG_SET used_by_pseudos;
3890 HARD_REG_SET used_by_pseudos2;
3892 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3893 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3895 /* Mark any unallocated hard regs as available for spills. That
3896 makes inheritance work somewhat better. */
3897 if (chain->need_reload)
3899 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3900 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3901 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3903 /* Save the old value for the sanity test below. */
3904 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3906 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3907 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3908 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3909 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3911 /* Make sure we only enlarge the set. */
3912 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2,
3913 chain->used_spill_regs));
3917 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3918 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3920 int regno = reg_renumber[i];
3921 if (reg_old_renumber[i] == regno)
3924 alter_reg (i, reg_old_renumber[i]);
3925 reg_old_renumber[i] = regno;
3929 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3931 fprintf (dump_file, " Register %d now in %d.\n\n",
3932 i, reg_renumber[i]);
3936 return something_changed;
3939 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3942 scan_paradoxical_subregs (rtx x)
3946 enum rtx_code code = GET_CODE (x);
3956 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3964 if (REG_P (SUBREG_REG (x))
3965 && (GET_MODE_SIZE (GET_MODE (x))
3966 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3968 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3969 = GET_MODE_SIZE (GET_MODE (x));
3970 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
3978 fmt = GET_RTX_FORMAT (code);
3979 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3982 scan_paradoxical_subregs (XEXP (x, i));
3983 else if (fmt[i] == 'E')
3986 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3987 scan_paradoxical_subregs (XVECEXP (x, i, j));
3992 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3993 examine all of the reload insns between PREV and NEXT exclusive, and
3994 annotate all that may trap. */
3997 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3999 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4000 unsigned int trap_count;
4006 if (may_trap_p (PATTERN (insn)))
4010 remove_note (insn, note);
4014 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4015 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4019 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
4023 /* Reload pseudo-registers into hard regs around each insn as needed.
4024 Additional register load insns are output before the insn that needs it
4025 and perhaps store insns after insns that modify the reloaded pseudo reg.
4027 reg_last_reload_reg and reg_reloaded_contents keep track of
4028 which registers are already available in reload registers.
4029 We update these for the reloads that we perform,
4030 as the insns are scanned. */
4033 reload_as_needed (int live_known)
4035 struct insn_chain *chain;
4036 #if defined (AUTO_INC_DEC)
4041 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4042 memset (spill_reg_store, 0, sizeof spill_reg_store);
4043 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4044 INIT_REG_SET (®_has_output_reload);
4045 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4046 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4048 set_initial_elim_offsets ();
4050 for (chain = reload_insn_chain; chain; chain = chain->next)
4053 rtx insn = chain->insn;
4054 rtx old_next = NEXT_INSN (insn);
4056 /* If we pass a label, copy the offsets from the label information
4057 into the current offsets of each elimination. */
4059 set_offsets_for_label (insn);
4061 else if (INSN_P (insn))
4063 regset_head regs_to_forget;
4064 INIT_REG_SET (®s_to_forget);
4065 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4067 /* If this is a USE and CLOBBER of a MEM, ensure that any
4068 references to eliminable registers have been removed. */
4070 if ((GET_CODE (PATTERN (insn)) == USE
4071 || GET_CODE (PATTERN (insn)) == CLOBBER)
4072 && MEM_P (XEXP (PATTERN (insn), 0)))
4073 XEXP (XEXP (PATTERN (insn), 0), 0)
4074 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4075 GET_MODE (XEXP (PATTERN (insn), 0)),
4078 /* If we need to do register elimination processing, do so.
4079 This might delete the insn, in which case we are done. */
4080 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4082 eliminate_regs_in_insn (insn, 1);
4085 update_eliminable_offsets ();
4086 CLEAR_REG_SET (®s_to_forget);
4091 /* If need_elim is nonzero but need_reload is zero, one might think
4092 that we could simply set n_reloads to 0. However, find_reloads
4093 could have done some manipulation of the insn (such as swapping
4094 commutative operands), and these manipulations are lost during
4095 the first pass for every insn that needs register elimination.
4096 So the actions of find_reloads must be redone here. */
4098 if (! chain->need_elim && ! chain->need_reload
4099 && ! chain->need_operand_change)
4101 /* First find the pseudo regs that must be reloaded for this insn.
4102 This info is returned in the tables reload_... (see reload.h).
4103 Also modify the body of INSN by substituting RELOAD
4104 rtx's for those pseudo regs. */
4107 CLEAR_REG_SET (®_has_output_reload);
4108 CLEAR_HARD_REG_SET (reg_is_output_reload);
4110 find_reloads (insn, 1, spill_indirect_levels, live_known,
4116 rtx next = NEXT_INSN (insn);
4119 prev = PREV_INSN (insn);
4121 /* Now compute which reload regs to reload them into. Perhaps
4122 reusing reload regs from previous insns, or else output
4123 load insns to reload them. Maybe output store insns too.
4124 Record the choices of reload reg in reload_reg_rtx. */
4125 choose_reload_regs (chain);
4127 /* Merge any reloads that we didn't combine for fear of
4128 increasing the number of spill registers needed but now
4129 discover can be safely merged. */
4130 if (SMALL_REGISTER_CLASSES)
4131 merge_assigned_reloads (insn);
4133 /* Generate the insns to reload operands into or out of
4134 their reload regs. */
4135 emit_reload_insns (chain);
4137 /* Substitute the chosen reload regs from reload_reg_rtx
4138 into the insn's body (or perhaps into the bodies of other
4139 load and store insn that we just made for reloading
4140 and that we moved the structure into). */
4141 subst_reloads (insn);
4143 /* Adjust the exception region notes for loads and stores. */
4144 if (flag_non_call_exceptions && !CALL_P (insn))
4145 fixup_eh_region_note (insn, prev, next);
4147 /* If this was an ASM, make sure that all the reload insns
4148 we have generated are valid. If not, give an error
4150 if (asm_noperands (PATTERN (insn)) >= 0)
4151 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4152 if (p != insn && INSN_P (p)
4153 && GET_CODE (PATTERN (p)) != USE
4154 && (recog_memoized (p) < 0
4155 || (extract_insn (p), ! constrain_operands (1))))
4157 error_for_asm (insn,
4158 "%<asm%> operand requires "
4159 "impossible reload");
4164 if (num_eliminable && chain->need_elim)
4165 update_eliminable_offsets ();
4167 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4168 is no longer validly lying around to save a future reload.
4169 Note that this does not detect pseudos that were reloaded
4170 for this insn in order to be stored in
4171 (obeying register constraints). That is correct; such reload
4172 registers ARE still valid. */
4173 forget_marked_reloads (®s_to_forget);
4174 CLEAR_REG_SET (®s_to_forget);
4176 /* There may have been CLOBBER insns placed after INSN. So scan
4177 between INSN and NEXT and use them to forget old reloads. */
4178 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4179 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4180 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4183 /* Likewise for regs altered by auto-increment in this insn.
4184 REG_INC notes have been changed by reloading:
4185 find_reloads_address_1 records substitutions for them,
4186 which have been performed by subst_reloads above. */
4187 for (i = n_reloads - 1; i >= 0; i--)
4189 rtx in_reg = rld[i].in_reg;
4192 enum rtx_code code = GET_CODE (in_reg);
4193 /* PRE_INC / PRE_DEC will have the reload register ending up
4194 with the same value as the stack slot, but that doesn't
4195 hold true for POST_INC / POST_DEC. Either we have to
4196 convert the memory access to a true POST_INC / POST_DEC,
4197 or we can't use the reload register for inheritance. */
4198 if ((code == POST_INC || code == POST_DEC)
4199 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4200 REGNO (rld[i].reg_rtx))
4201 /* Make sure it is the inc/dec pseudo, and not
4202 some other (e.g. output operand) pseudo. */
4203 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4204 == REGNO (XEXP (in_reg, 0))))
4207 rtx reload_reg = rld[i].reg_rtx;
4208 enum machine_mode mode = GET_MODE (reload_reg);
4212 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4214 /* We really want to ignore REG_INC notes here, so
4215 use PATTERN (p) as argument to reg_set_p . */
4216 if (reg_set_p (reload_reg, PATTERN (p)))
4218 n = count_occurrences (PATTERN (p), reload_reg, 0);
4223 n = validate_replace_rtx (reload_reg,
4224 gen_rtx_fmt_e (code,
4229 /* We must also verify that the constraints
4230 are met after the replacement. */
4233 n = constrain_operands (1);
4237 /* If the constraints were not met, then
4238 undo the replacement. */
4241 validate_replace_rtx (gen_rtx_fmt_e (code,
4254 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4256 /* Mark this as having an output reload so that the
4257 REG_INC processing code below won't invalidate
4258 the reload for inheritance. */
4259 SET_HARD_REG_BIT (reg_is_output_reload,
4260 REGNO (reload_reg));
4261 SET_REGNO_REG_SET (®_has_output_reload,
4262 REGNO (XEXP (in_reg, 0)));
4265 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4268 else if ((code == PRE_INC || code == PRE_DEC)
4269 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4270 REGNO (rld[i].reg_rtx))
4271 /* Make sure it is the inc/dec pseudo, and not
4272 some other (e.g. output operand) pseudo. */
4273 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4274 == REGNO (XEXP (in_reg, 0))))
4276 SET_HARD_REG_BIT (reg_is_output_reload,
4277 REGNO (rld[i].reg_rtx));
4278 SET_REGNO_REG_SET (®_has_output_reload,
4279 REGNO (XEXP (in_reg, 0)));
4283 /* If a pseudo that got a hard register is auto-incremented,
4284 we must purge records of copying it into pseudos without
4286 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4287 if (REG_NOTE_KIND (x) == REG_INC)
4289 /* See if this pseudo reg was reloaded in this insn.
4290 If so, its last-reload info is still valid
4291 because it is based on this insn's reload. */
4292 for (i = 0; i < n_reloads; i++)
4293 if (rld[i].out == XEXP (x, 0))
4297 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4301 /* A reload reg's contents are unknown after a label. */
4303 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4305 /* Don't assume a reload reg is still good after a call insn
4306 if it is a call-used reg, or if it contains a value that will
4307 be partially clobbered by the call. */
4308 else if (CALL_P (insn))
4310 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4311 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4316 free (reg_last_reload_reg);
4317 CLEAR_REG_SET (®_has_output_reload);
4320 /* Discard all record of any value reloaded from X,
4321 or reloaded in X from someplace else;
4322 unless X is an output reload reg of the current insn.
4324 X may be a hard reg (the reload reg)
4325 or it may be a pseudo reg that was reloaded from.
4327 When DATA is non-NULL just mark the registers in regset
4328 to be forgotten later. */
4331 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4336 regset regs = (regset) data;
4338 /* note_stores does give us subregs of hard regs,
4339 subreg_regno_offset requires a hard reg. */
4340 while (GET_CODE (x) == SUBREG)
4342 /* We ignore the subreg offset when calculating the regno,
4343 because we are using the entire underlying hard register
4353 if (regno >= FIRST_PSEUDO_REGISTER)
4359 nr = hard_regno_nregs[regno][GET_MODE (x)];
4360 /* Storing into a spilled-reg invalidates its contents.
4361 This can happen if a block-local pseudo is allocated to that reg
4362 and it wasn't spilled because this block's total need is 0.
4363 Then some insn might have an optional reload and use this reg. */
4365 for (i = 0; i < nr; i++)
4366 /* But don't do this if the reg actually serves as an output
4367 reload reg in the current instruction. */
4369 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4371 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4372 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4373 spill_reg_store[regno + i] = 0;
4379 SET_REGNO_REG_SET (regs, regno + nr);
4382 /* Since value of X has changed,
4383 forget any value previously copied from it. */
4386 /* But don't forget a copy if this is the output reload
4387 that establishes the copy's validity. */
4389 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4390 reg_last_reload_reg[regno + nr] = 0;
4394 /* Forget the reloads marked in regset by previous function. */
4396 forget_marked_reloads (regset regs)
4399 reg_set_iterator rsi;
4400 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4402 if (reg < FIRST_PSEUDO_REGISTER
4403 /* But don't do this if the reg actually serves as an output
4404 reload reg in the current instruction. */
4406 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4408 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4409 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4410 spill_reg_store[reg] = 0;
4413 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4414 reg_last_reload_reg[reg] = 0;
4418 /* The following HARD_REG_SETs indicate when each hard register is
4419 used for a reload of various parts of the current insn. */
4421 /* If reg is unavailable for all reloads. */
4422 static HARD_REG_SET reload_reg_unavailable;
4423 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4424 static HARD_REG_SET reload_reg_used;
4425 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4426 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4427 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4428 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4429 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4430 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4431 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4432 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4433 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4434 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4435 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4436 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4437 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4438 static HARD_REG_SET reload_reg_used_in_op_addr;
4439 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4440 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4441 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4442 static HARD_REG_SET reload_reg_used_in_insn;
4443 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4444 static HARD_REG_SET reload_reg_used_in_other_addr;
4446 /* If reg is in use as a reload reg for any sort of reload. */
4447 static HARD_REG_SET reload_reg_used_at_all;
4449 /* If reg is use as an inherited reload. We just mark the first register
4451 static HARD_REG_SET reload_reg_used_for_inherit;
4453 /* Records which hard regs are used in any way, either as explicit use or
4454 by being allocated to a pseudo during any point of the current insn. */
4455 static HARD_REG_SET reg_used_in_insn;
4457 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4458 TYPE. MODE is used to indicate how many consecutive regs are
4462 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4463 enum machine_mode mode)
4465 unsigned int nregs = hard_regno_nregs[regno][mode];
4468 for (i = regno; i < nregs + regno; i++)
4473 SET_HARD_REG_BIT (reload_reg_used, i);
4476 case RELOAD_FOR_INPUT_ADDRESS:
4477 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4480 case RELOAD_FOR_INPADDR_ADDRESS:
4481 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4484 case RELOAD_FOR_OUTPUT_ADDRESS:
4485 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4488 case RELOAD_FOR_OUTADDR_ADDRESS:
4489 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4492 case RELOAD_FOR_OPERAND_ADDRESS:
4493 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4496 case RELOAD_FOR_OPADDR_ADDR:
4497 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4500 case RELOAD_FOR_OTHER_ADDRESS:
4501 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4504 case RELOAD_FOR_INPUT:
4505 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4508 case RELOAD_FOR_OUTPUT:
4509 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4512 case RELOAD_FOR_INSN:
4513 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4517 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4521 /* Similarly, but show REGNO is no longer in use for a reload. */
4524 clear_reload_reg_in_use (unsigned int regno, int opnum,
4525 enum reload_type type, enum machine_mode mode)
4527 unsigned int nregs = hard_regno_nregs[regno][mode];
4528 unsigned int start_regno, end_regno, r;
4530 /* A complication is that for some reload types, inheritance might
4531 allow multiple reloads of the same types to share a reload register.
4532 We set check_opnum if we have to check only reloads with the same
4533 operand number, and check_any if we have to check all reloads. */
4534 int check_opnum = 0;
4536 HARD_REG_SET *used_in_set;
4541 used_in_set = &reload_reg_used;
4544 case RELOAD_FOR_INPUT_ADDRESS:
4545 used_in_set = &reload_reg_used_in_input_addr[opnum];
4548 case RELOAD_FOR_INPADDR_ADDRESS:
4550 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4553 case RELOAD_FOR_OUTPUT_ADDRESS:
4554 used_in_set = &reload_reg_used_in_output_addr[opnum];
4557 case RELOAD_FOR_OUTADDR_ADDRESS:
4559 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4562 case RELOAD_FOR_OPERAND_ADDRESS:
4563 used_in_set = &reload_reg_used_in_op_addr;
4566 case RELOAD_FOR_OPADDR_ADDR:
4568 used_in_set = &reload_reg_used_in_op_addr_reload;
4571 case RELOAD_FOR_OTHER_ADDRESS:
4572 used_in_set = &reload_reg_used_in_other_addr;
4576 case RELOAD_FOR_INPUT:
4577 used_in_set = &reload_reg_used_in_input[opnum];
4580 case RELOAD_FOR_OUTPUT:
4581 used_in_set = &reload_reg_used_in_output[opnum];
4584 case RELOAD_FOR_INSN:
4585 used_in_set = &reload_reg_used_in_insn;
4590 /* We resolve conflicts with remaining reloads of the same type by
4591 excluding the intervals of reload registers by them from the
4592 interval of freed reload registers. Since we only keep track of
4593 one set of interval bounds, we might have to exclude somewhat
4594 more than what would be necessary if we used a HARD_REG_SET here.
4595 But this should only happen very infrequently, so there should
4596 be no reason to worry about it. */
4598 start_regno = regno;
4599 end_regno = regno + nregs;
4600 if (check_opnum || check_any)
4602 for (i = n_reloads - 1; i >= 0; i--)
4604 if (rld[i].when_needed == type
4605 && (check_any || rld[i].opnum == opnum)
4608 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4609 unsigned int conflict_end
4610 = end_hard_regno (rld[i].mode, conflict_start);
4612 /* If there is an overlap with the first to-be-freed register,
4613 adjust the interval start. */
4614 if (conflict_start <= start_regno && conflict_end > start_regno)
4615 start_regno = conflict_end;
4616 /* Otherwise, if there is a conflict with one of the other
4617 to-be-freed registers, adjust the interval end. */
4618 if (conflict_start > start_regno && conflict_start < end_regno)
4619 end_regno = conflict_start;
4624 for (r = start_regno; r < end_regno; r++)
4625 CLEAR_HARD_REG_BIT (*used_in_set, r);
4628 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4629 specified by OPNUM and TYPE. */
4632 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4636 /* In use for a RELOAD_OTHER means it's not available for anything. */
4637 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4638 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4644 /* In use for anything means we can't use it for RELOAD_OTHER. */
4645 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4646 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4647 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4648 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4651 for (i = 0; i < reload_n_operands; i++)
4652 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4653 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4654 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4655 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4656 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4657 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4662 case RELOAD_FOR_INPUT:
4663 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4664 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4667 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4670 /* If it is used for some other input, can't use it. */
4671 for (i = 0; i < reload_n_operands; i++)
4672 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4675 /* If it is used in a later operand's address, can't use it. */
4676 for (i = opnum + 1; i < reload_n_operands; i++)
4677 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4678 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4683 case RELOAD_FOR_INPUT_ADDRESS:
4684 /* Can't use a register if it is used for an input address for this
4685 operand or used as an input in an earlier one. */
4686 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4687 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4690 for (i = 0; i < opnum; i++)
4691 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4696 case RELOAD_FOR_INPADDR_ADDRESS:
4697 /* Can't use a register if it is used for an input address
4698 for this operand or used as an input in an earlier
4700 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4703 for (i = 0; i < opnum; i++)
4704 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4709 case RELOAD_FOR_OUTPUT_ADDRESS:
4710 /* Can't use a register if it is used for an output address for this
4711 operand or used as an output in this or a later operand. Note
4712 that multiple output operands are emitted in reverse order, so
4713 the conflicting ones are those with lower indices. */
4714 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4717 for (i = 0; i <= opnum; i++)
4718 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4723 case RELOAD_FOR_OUTADDR_ADDRESS:
4724 /* Can't use a register if it is used for an output address
4725 for this operand or used as an output in this or a
4726 later operand. Note that multiple output operands are
4727 emitted in reverse order, so the conflicting ones are
4728 those with lower indices. */
4729 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4732 for (i = 0; i <= opnum; i++)
4733 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4738 case RELOAD_FOR_OPERAND_ADDRESS:
4739 for (i = 0; i < reload_n_operands; i++)
4740 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4743 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4744 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4746 case RELOAD_FOR_OPADDR_ADDR:
4747 for (i = 0; i < reload_n_operands; i++)
4748 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4751 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4753 case RELOAD_FOR_OUTPUT:
4754 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4755 outputs, or an operand address for this or an earlier output.
4756 Note that multiple output operands are emitted in reverse order,
4757 so the conflicting ones are those with higher indices. */
4758 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4761 for (i = 0; i < reload_n_operands; i++)
4762 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4765 for (i = opnum; i < reload_n_operands; i++)
4766 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4767 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4772 case RELOAD_FOR_INSN:
4773 for (i = 0; i < reload_n_operands; i++)
4774 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4775 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4778 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4779 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4781 case RELOAD_FOR_OTHER_ADDRESS:
4782 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4789 /* Return 1 if the value in reload reg REGNO, as used by a reload
4790 needed for the part of the insn specified by OPNUM and TYPE,
4791 is still available in REGNO at the end of the insn.
4793 We can assume that the reload reg was already tested for availability
4794 at the time it is needed, and we should not check this again,
4795 in case the reg has already been marked in use. */
4798 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4805 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4806 its value must reach the end. */
4809 /* If this use is for part of the insn,
4810 its value reaches if no subsequent part uses the same register.
4811 Just like the above function, don't try to do this with lots
4814 case RELOAD_FOR_OTHER_ADDRESS:
4815 /* Here we check for everything else, since these don't conflict
4816 with anything else and everything comes later. */
4818 for (i = 0; i < reload_n_operands; i++)
4819 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4820 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4821 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4823 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4824 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4827 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4828 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4829 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4830 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4832 case RELOAD_FOR_INPUT_ADDRESS:
4833 case RELOAD_FOR_INPADDR_ADDRESS:
4834 /* Similar, except that we check only for this and subsequent inputs
4835 and the address of only subsequent inputs and we do not need
4836 to check for RELOAD_OTHER objects since they are known not to
4839 for (i = opnum; i < reload_n_operands; i++)
4840 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4843 for (i = opnum + 1; i < reload_n_operands; i++)
4844 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4845 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4848 for (i = 0; i < reload_n_operands; i++)
4849 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4850 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4851 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4857 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4858 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4859 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4861 case RELOAD_FOR_INPUT:
4862 /* Similar to input address, except we start at the next operand for
4863 both input and input address and we do not check for
4864 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4867 for (i = opnum + 1; i < reload_n_operands; i++)
4868 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4869 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4870 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4873 /* ... fall through ... */
4875 case RELOAD_FOR_OPERAND_ADDRESS:
4876 /* Check outputs and their addresses. */
4878 for (i = 0; i < reload_n_operands; i++)
4879 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4880 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4881 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4884 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4886 case RELOAD_FOR_OPADDR_ADDR:
4887 for (i = 0; i < reload_n_operands; i++)
4888 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4889 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4890 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4893 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4894 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4895 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4897 case RELOAD_FOR_INSN:
4898 /* These conflict with other outputs with RELOAD_OTHER. So
4899 we need only check for output addresses. */
4901 opnum = reload_n_operands;
4903 /* ... fall through ... */
4905 case RELOAD_FOR_OUTPUT:
4906 case RELOAD_FOR_OUTPUT_ADDRESS:
4907 case RELOAD_FOR_OUTADDR_ADDRESS:
4908 /* We already know these can't conflict with a later output. So the
4909 only thing to check are later output addresses.
4910 Note that multiple output operands are emitted in reverse order,
4911 so the conflicting ones are those with lower indices. */
4912 for (i = 0; i < opnum; i++)
4913 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4914 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4925 /* Returns whether R1 and R2 are uniquely chained: the value of one
4926 is used by the other, and that value is not used by any other
4927 reload for this insn. This is used to partially undo the decision
4928 made in find_reloads when in the case of multiple
4929 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4930 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4931 reloads. This code tries to avoid the conflict created by that
4932 change. It might be cleaner to explicitly keep track of which
4933 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4934 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4935 this after the fact. */
4937 reloads_unique_chain_p (int r1, int r2)
4941 /* We only check input reloads. */
4942 if (! rld[r1].in || ! rld[r2].in)
4945 /* Avoid anything with output reloads. */
4946 if (rld[r1].out || rld[r2].out)
4949 /* "chained" means one reload is a component of the other reload,
4950 not the same as the other reload. */
4951 if (rld[r1].opnum != rld[r2].opnum
4952 || rtx_equal_p (rld[r1].in, rld[r2].in)
4953 || rld[r1].optional || rld[r2].optional
4954 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4955 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4958 for (i = 0; i < n_reloads; i ++)
4959 /* Look for input reloads that aren't our two */
4960 if (i != r1 && i != r2 && rld[i].in)
4962 /* If our reload is mentioned at all, it isn't a simple chain. */
4963 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4969 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4972 This function uses the same algorithm as reload_reg_free_p above. */
4975 reloads_conflict (int r1, int r2)
4977 enum reload_type r1_type = rld[r1].when_needed;
4978 enum reload_type r2_type = rld[r2].when_needed;
4979 int r1_opnum = rld[r1].opnum;
4980 int r2_opnum = rld[r2].opnum;
4982 /* RELOAD_OTHER conflicts with everything. */
4983 if (r2_type == RELOAD_OTHER)
4986 /* Otherwise, check conflicts differently for each type. */
4990 case RELOAD_FOR_INPUT:
4991 return (r2_type == RELOAD_FOR_INSN
4992 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4993 || r2_type == RELOAD_FOR_OPADDR_ADDR
4994 || r2_type == RELOAD_FOR_INPUT
4995 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4996 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4997 && r2_opnum > r1_opnum));
4999 case RELOAD_FOR_INPUT_ADDRESS:
5000 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5001 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5003 case RELOAD_FOR_INPADDR_ADDRESS:
5004 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5005 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5007 case RELOAD_FOR_OUTPUT_ADDRESS:
5008 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5009 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5011 case RELOAD_FOR_OUTADDR_ADDRESS:
5012 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5013 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5015 case RELOAD_FOR_OPERAND_ADDRESS:
5016 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5017 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5018 && !reloads_unique_chain_p (r1, r2)));
5020 case RELOAD_FOR_OPADDR_ADDR:
5021 return (r2_type == RELOAD_FOR_INPUT
5022 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5024 case RELOAD_FOR_OUTPUT:
5025 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5026 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5027 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5028 && r2_opnum >= r1_opnum));
5030 case RELOAD_FOR_INSN:
5031 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5032 || r2_type == RELOAD_FOR_INSN
5033 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5035 case RELOAD_FOR_OTHER_ADDRESS:
5036 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5046 /* Indexed by reload number, 1 if incoming value
5047 inherited from previous insns. */
5048 static char reload_inherited[MAX_RELOADS];
5050 /* For an inherited reload, this is the insn the reload was inherited from,
5051 if we know it. Otherwise, this is 0. */
5052 static rtx reload_inheritance_insn[MAX_RELOADS];
5054 /* If nonzero, this is a place to get the value of the reload,
5055 rather than using reload_in. */
5056 static rtx reload_override_in[MAX_RELOADS];
5058 /* For each reload, the hard register number of the register used,
5059 or -1 if we did not need a register for this reload. */
5060 static int reload_spill_index[MAX_RELOADS];
5062 /* Subroutine of free_for_value_p, used to check a single register.
5063 START_REGNO is the starting regno of the full reload register
5064 (possibly comprising multiple hard registers) that we are considering. */
5067 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5068 enum reload_type type, rtx value, rtx out,
5069 int reloadnum, int ignore_address_reloads)
5072 /* Set if we see an input reload that must not share its reload register
5073 with any new earlyclobber, but might otherwise share the reload
5074 register with an output or input-output reload. */
5075 int check_earlyclobber = 0;
5079 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5082 if (out == const0_rtx)
5088 /* We use some pseudo 'time' value to check if the lifetimes of the
5089 new register use would overlap with the one of a previous reload
5090 that is not read-only or uses a different value.
5091 The 'time' used doesn't have to be linear in any shape or form, just
5093 Some reload types use different 'buckets' for each operand.
5094 So there are MAX_RECOG_OPERANDS different time values for each
5096 We compute TIME1 as the time when the register for the prospective
5097 new reload ceases to be live, and TIME2 for each existing
5098 reload as the time when that the reload register of that reload
5100 Where there is little to be gained by exact lifetime calculations,
5101 we just make conservative assumptions, i.e. a longer lifetime;
5102 this is done in the 'default:' cases. */
5105 case RELOAD_FOR_OTHER_ADDRESS:
5106 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5107 time1 = copy ? 0 : 1;
5110 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5112 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5113 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5114 respectively, to the time values for these, we get distinct time
5115 values. To get distinct time values for each operand, we have to
5116 multiply opnum by at least three. We round that up to four because
5117 multiply by four is often cheaper. */
5118 case RELOAD_FOR_INPADDR_ADDRESS:
5119 time1 = opnum * 4 + 2;
5121 case RELOAD_FOR_INPUT_ADDRESS:
5122 time1 = opnum * 4 + 3;
5124 case RELOAD_FOR_INPUT:
5125 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5126 executes (inclusive). */
5127 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5129 case RELOAD_FOR_OPADDR_ADDR:
5131 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5132 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5134 case RELOAD_FOR_OPERAND_ADDRESS:
5135 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5137 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5139 case RELOAD_FOR_OUTADDR_ADDRESS:
5140 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5142 case RELOAD_FOR_OUTPUT_ADDRESS:
5143 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5146 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5149 for (i = 0; i < n_reloads; i++)
5151 rtx reg = rld[i].reg_rtx;
5152 if (reg && REG_P (reg)
5153 && ((unsigned) regno - true_regnum (reg)
5154 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5157 rtx other_input = rld[i].in;
5159 /* If the other reload loads the same input value, that
5160 will not cause a conflict only if it's loading it into
5161 the same register. */
5162 if (true_regnum (reg) != start_regno)
5163 other_input = NULL_RTX;
5164 if (! other_input || ! rtx_equal_p (other_input, value)
5165 || rld[i].out || out)
5168 switch (rld[i].when_needed)
5170 case RELOAD_FOR_OTHER_ADDRESS:
5173 case RELOAD_FOR_INPADDR_ADDRESS:
5174 /* find_reloads makes sure that a
5175 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5176 by at most one - the first -
5177 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5178 address reload is inherited, the address address reload
5179 goes away, so we can ignore this conflict. */
5180 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5181 && ignore_address_reloads
5182 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5183 Then the address address is still needed to store
5184 back the new address. */
5185 && ! rld[reloadnum].out)
5187 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5188 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5190 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5191 && ignore_address_reloads
5192 /* Unless we are reloading an auto_inc expression. */
5193 && ! rld[reloadnum].out)
5195 time2 = rld[i].opnum * 4 + 2;
5197 case RELOAD_FOR_INPUT_ADDRESS:
5198 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5199 && ignore_address_reloads
5200 && ! rld[reloadnum].out)
5202 time2 = rld[i].opnum * 4 + 3;
5204 case RELOAD_FOR_INPUT:
5205 time2 = rld[i].opnum * 4 + 4;
5206 check_earlyclobber = 1;
5208 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5209 == MAX_RECOG_OPERAND * 4 */
5210 case RELOAD_FOR_OPADDR_ADDR:
5211 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5212 && ignore_address_reloads
5213 && ! rld[reloadnum].out)
5215 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5217 case RELOAD_FOR_OPERAND_ADDRESS:
5218 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5219 check_earlyclobber = 1;
5221 case RELOAD_FOR_INSN:
5222 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5224 case RELOAD_FOR_OUTPUT:
5225 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5226 instruction is executed. */
5227 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5229 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5230 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5232 case RELOAD_FOR_OUTADDR_ADDRESS:
5233 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5234 && ignore_address_reloads
5235 && ! rld[reloadnum].out)
5237 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5239 case RELOAD_FOR_OUTPUT_ADDRESS:
5240 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5243 /* If there is no conflict in the input part, handle this
5244 like an output reload. */
5245 if (! rld[i].in || rtx_equal_p (other_input, value))
5247 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5248 /* Earlyclobbered outputs must conflict with inputs. */
5249 if (earlyclobber_operand_p (rld[i].out))
5250 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5255 /* RELOAD_OTHER might be live beyond instruction execution,
5256 but this is not obvious when we set time2 = 1. So check
5257 here if there might be a problem with the new reload
5258 clobbering the register used by the RELOAD_OTHER. */
5266 && (! rld[i].in || rld[i].out
5267 || ! rtx_equal_p (other_input, value)))
5268 || (out && rld[reloadnum].out_reg
5269 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5275 /* Earlyclobbered outputs must conflict with inputs. */
5276 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5282 /* Return 1 if the value in reload reg REGNO, as used by a reload
5283 needed for the part of the insn specified by OPNUM and TYPE,
5284 may be used to load VALUE into it.
5286 MODE is the mode in which the register is used, this is needed to
5287 determine how many hard regs to test.
5289 Other read-only reloads with the same value do not conflict
5290 unless OUT is nonzero and these other reloads have to live while
5291 output reloads live.
5292 If OUT is CONST0_RTX, this is a special case: it means that the
5293 test should not be for using register REGNO as reload register, but
5294 for copying from register REGNO into the reload register.
5296 RELOADNUM is the number of the reload we want to load this value for;
5297 a reload does not conflict with itself.
5299 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5300 reloads that load an address for the very reload we are considering.
5302 The caller has to make sure that there is no conflict with the return
5306 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5307 enum reload_type type, rtx value, rtx out, int reloadnum,
5308 int ignore_address_reloads)
5310 int nregs = hard_regno_nregs[regno][mode];
5312 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5313 value, out, reloadnum,
5314 ignore_address_reloads))
5319 /* Return nonzero if the rtx X is invariant over the current function. */
5320 /* ??? Actually, the places where we use this expect exactly what is
5321 tested here, and not everything that is function invariant. In
5322 particular, the frame pointer and arg pointer are special cased;
5323 pic_offset_table_rtx is not, and we must not spill these things to
5327 function_invariant_p (rtx x)
5331 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5333 if (GET_CODE (x) == PLUS
5334 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5335 && CONSTANT_P (XEXP (x, 1)))
5340 /* Determine whether the reload reg X overlaps any rtx'es used for
5341 overriding inheritance. Return nonzero if so. */
5344 conflicts_with_override (rtx x)
5347 for (i = 0; i < n_reloads; i++)
5348 if (reload_override_in[i]
5349 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5354 /* Give an error message saying we failed to find a reload for INSN,
5355 and clear out reload R. */
5357 failed_reload (rtx insn, int r)
5359 if (asm_noperands (PATTERN (insn)) < 0)
5360 /* It's the compiler's fault. */
5361 fatal_insn ("could not find a spill register", insn);
5363 /* It's the user's fault; the operand's mode and constraint
5364 don't match. Disable this reload so we don't crash in final. */
5365 error_for_asm (insn,
5366 "%<asm%> operand constraint incompatible with operand size");
5370 rld[r].optional = 1;
5371 rld[r].secondary_p = 1;
5374 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5375 for reload R. If it's valid, get an rtx for it. Return nonzero if
5378 set_reload_reg (int i, int r)
5381 rtx reg = spill_reg_rtx[i];
5383 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5384 spill_reg_rtx[i] = reg
5385 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5387 regno = true_regnum (reg);
5389 /* Detect when the reload reg can't hold the reload mode.
5390 This used to be one `if', but Sequent compiler can't handle that. */
5391 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5393 enum machine_mode test_mode = VOIDmode;
5395 test_mode = GET_MODE (rld[r].in);
5396 /* If rld[r].in has VOIDmode, it means we will load it
5397 in whatever mode the reload reg has: to wit, rld[r].mode.
5398 We have already tested that for validity. */
5399 /* Aside from that, we need to test that the expressions
5400 to reload from or into have modes which are valid for this
5401 reload register. Otherwise the reload insns would be invalid. */
5402 if (! (rld[r].in != 0 && test_mode != VOIDmode
5403 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5404 if (! (rld[r].out != 0
5405 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5407 /* The reg is OK. */
5410 /* Mark as in use for this insn the reload regs we use
5412 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5413 rld[r].when_needed, rld[r].mode);
5415 rld[r].reg_rtx = reg;
5416 reload_spill_index[r] = spill_regs[i];
5423 /* Find a spill register to use as a reload register for reload R.
5424 LAST_RELOAD is nonzero if this is the last reload for the insn being
5427 Set rld[R].reg_rtx to the register allocated.
5429 We return 1 if successful, or 0 if we couldn't find a spill reg and
5430 we didn't change anything. */
5433 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5438 /* If we put this reload ahead, thinking it is a group,
5439 then insist on finding a group. Otherwise we can grab a
5440 reg that some other reload needs.
5441 (That can happen when we have a 68000 DATA_OR_FP_REG
5442 which is a group of data regs or one fp reg.)
5443 We need not be so restrictive if there are no more reloads
5446 ??? Really it would be nicer to have smarter handling
5447 for that kind of reg class, where a problem like this is normal.
5448 Perhaps those classes should be avoided for reloading
5449 by use of more alternatives. */
5451 int force_group = rld[r].nregs > 1 && ! last_reload;
5453 /* If we want a single register and haven't yet found one,
5454 take any reg in the right class and not in use.
5455 If we want a consecutive group, here is where we look for it.
5457 We use two passes so we can first look for reload regs to
5458 reuse, which are already in use for other reloads in this insn,
5459 and only then use additional registers.
5460 I think that maximizing reuse is needed to make sure we don't
5461 run out of reload regs. Suppose we have three reloads, and
5462 reloads A and B can share regs. These need two regs.
5463 Suppose A and B are given different regs.
5464 That leaves none for C. */
5465 for (pass = 0; pass < 2; pass++)
5467 /* I is the index in spill_regs.
5468 We advance it round-robin between insns to use all spill regs
5469 equally, so that inherited reloads have a chance
5470 of leapfrogging each other. */
5474 for (count = 0; count < n_spills; count++)
5476 int class = (int) rld[r].class;
5482 regnum = spill_regs[i];
5484 if ((reload_reg_free_p (regnum, rld[r].opnum,
5487 /* We check reload_reg_used to make sure we
5488 don't clobber the return register. */
5489 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5490 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5491 rld[r].when_needed, rld[r].in,
5493 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5494 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5495 /* Look first for regs to share, then for unshared. But
5496 don't share regs used for inherited reloads; they are
5497 the ones we want to preserve. */
5499 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5501 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5504 int nr = hard_regno_nregs[regnum][rld[r].mode];
5505 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5506 (on 68000) got us two FP regs. If NR is 1,
5507 we would reject both of them. */
5510 /* If we need only one reg, we have already won. */
5513 /* But reject a single reg if we demand a group. */
5518 /* Otherwise check that as many consecutive regs as we need
5519 are available here. */
5522 int regno = regnum + nr - 1;
5523 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5524 && spill_reg_order[regno] >= 0
5525 && reload_reg_free_p (regno, rld[r].opnum,
5526 rld[r].when_needed)))
5535 /* If we found something on pass 1, omit pass 2. */
5536 if (count < n_spills)
5540 /* We should have found a spill register by now. */
5541 if (count >= n_spills)
5544 /* I is the index in SPILL_REG_RTX of the reload register we are to
5545 allocate. Get an rtx for it and find its register number. */
5547 return set_reload_reg (i, r);
5550 /* Initialize all the tables needed to allocate reload registers.
5551 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5552 is the array we use to restore the reg_rtx field for every reload. */
5555 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5559 for (i = 0; i < n_reloads; i++)
5560 rld[i].reg_rtx = save_reload_reg_rtx[i];
5562 memset (reload_inherited, 0, MAX_RELOADS);
5563 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5564 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5566 CLEAR_HARD_REG_SET (reload_reg_used);
5567 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5568 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5569 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5570 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5571 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5573 CLEAR_HARD_REG_SET (reg_used_in_insn);
5576 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5577 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5578 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5579 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5580 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5581 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5584 for (i = 0; i < reload_n_operands; i++)
5586 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5587 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5588 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5589 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5590 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5591 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5594 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5596 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5598 for (i = 0; i < n_reloads; i++)
5599 /* If we have already decided to use a certain register,
5600 don't use it in another way. */
5602 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5603 rld[i].when_needed, rld[i].mode);
5606 /* Assign hard reg targets for the pseudo-registers we must reload
5607 into hard regs for this insn.
5608 Also output the instructions to copy them in and out of the hard regs.
5610 For machines with register classes, we are responsible for
5611 finding a reload reg in the proper class. */
5614 choose_reload_regs (struct insn_chain *chain)
5616 rtx insn = chain->insn;
5618 unsigned int max_group_size = 1;
5619 enum reg_class group_class = NO_REGS;
5620 int pass, win, inheritance;
5622 rtx save_reload_reg_rtx[MAX_RELOADS];
5624 /* In order to be certain of getting the registers we need,
5625 we must sort the reloads into order of increasing register class.
5626 Then our grabbing of reload registers will parallel the process
5627 that provided the reload registers.
5629 Also note whether any of the reloads wants a consecutive group of regs.
5630 If so, record the maximum size of the group desired and what
5631 register class contains all the groups needed by this insn. */
5633 for (j = 0; j < n_reloads; j++)
5635 reload_order[j] = j;
5636 reload_spill_index[j] = -1;
5638 if (rld[j].nregs > 1)
5640 max_group_size = MAX (rld[j].nregs, max_group_size);
5642 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5645 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5649 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5651 /* If -O, try first with inheritance, then turning it off.
5652 If not -O, don't do inheritance.
5653 Using inheritance when not optimizing leads to paradoxes
5654 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5655 because one side of the comparison might be inherited. */
5657 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5659 choose_reload_regs_init (chain, save_reload_reg_rtx);
5661 /* Process the reloads in order of preference just found.
5662 Beyond this point, subregs can be found in reload_reg_rtx.
5664 This used to look for an existing reloaded home for all of the
5665 reloads, and only then perform any new reloads. But that could lose
5666 if the reloads were done out of reg-class order because a later
5667 reload with a looser constraint might have an old home in a register
5668 needed by an earlier reload with a tighter constraint.
5670 To solve this, we make two passes over the reloads, in the order
5671 described above. In the first pass we try to inherit a reload
5672 from a previous insn. If there is a later reload that needs a
5673 class that is a proper subset of the class being processed, we must
5674 also allocate a spill register during the first pass.
5676 Then make a second pass over the reloads to allocate any reloads
5677 that haven't been given registers yet. */
5679 for (j = 0; j < n_reloads; j++)
5681 int r = reload_order[j];
5682 rtx search_equiv = NULL_RTX;
5684 /* Ignore reloads that got marked inoperative. */
5685 if (rld[r].out == 0 && rld[r].in == 0
5686 && ! rld[r].secondary_p)
5689 /* If find_reloads chose to use reload_in or reload_out as a reload
5690 register, we don't need to chose one. Otherwise, try even if it
5691 found one since we might save an insn if we find the value lying
5693 Try also when reload_in is a pseudo without a hard reg. */
5694 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5695 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5696 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5697 && !MEM_P (rld[r].in)
5698 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5701 #if 0 /* No longer needed for correct operation.
5702 It might give better code, or might not; worth an experiment? */
5703 /* If this is an optional reload, we can't inherit from earlier insns
5704 until we are sure that any non-optional reloads have been allocated.
5705 The following code takes advantage of the fact that optional reloads
5706 are at the end of reload_order. */
5707 if (rld[r].optional != 0)
5708 for (i = 0; i < j; i++)
5709 if ((rld[reload_order[i]].out != 0
5710 || rld[reload_order[i]].in != 0
5711 || rld[reload_order[i]].secondary_p)
5712 && ! rld[reload_order[i]].optional
5713 && rld[reload_order[i]].reg_rtx == 0)
5714 allocate_reload_reg (chain, reload_order[i], 0);
5717 /* First see if this pseudo is already available as reloaded
5718 for a previous insn. We cannot try to inherit for reloads
5719 that are smaller than the maximum number of registers needed
5720 for groups unless the register we would allocate cannot be used
5723 We could check here to see if this is a secondary reload for
5724 an object that is already in a register of the desired class.
5725 This would avoid the need for the secondary reload register.
5726 But this is complex because we can't easily determine what
5727 objects might want to be loaded via this reload. So let a
5728 register be allocated here. In `emit_reload_insns' we suppress
5729 one of the loads in the case described above. */
5735 enum machine_mode mode = VOIDmode;
5739 else if (REG_P (rld[r].in))
5741 regno = REGNO (rld[r].in);
5742 mode = GET_MODE (rld[r].in);
5744 else if (REG_P (rld[r].in_reg))
5746 regno = REGNO (rld[r].in_reg);
5747 mode = GET_MODE (rld[r].in_reg);
5749 else if (GET_CODE (rld[r].in_reg) == SUBREG
5750 && REG_P (SUBREG_REG (rld[r].in_reg)))
5752 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5753 if (regno < FIRST_PSEUDO_REGISTER)
5754 regno = subreg_regno (rld[r].in_reg);
5756 byte = SUBREG_BYTE (rld[r].in_reg);
5757 mode = GET_MODE (rld[r].in_reg);
5760 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5761 && REG_P (XEXP (rld[r].in_reg, 0)))
5763 regno = REGNO (XEXP (rld[r].in_reg, 0));
5764 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5765 rld[r].out = rld[r].in;
5769 /* This won't work, since REGNO can be a pseudo reg number.
5770 Also, it takes much more hair to keep track of all the things
5771 that can invalidate an inherited reload of part of a pseudoreg. */
5772 else if (GET_CODE (rld[r].in) == SUBREG
5773 && REG_P (SUBREG_REG (rld[r].in)))
5774 regno = subreg_regno (rld[r].in);
5778 && reg_last_reload_reg[regno] != 0
5779 #ifdef CANNOT_CHANGE_MODE_CLASS
5780 /* Verify that the register it's in can be used in
5782 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5783 GET_MODE (reg_last_reload_reg[regno]),
5788 enum reg_class class = rld[r].class, last_class;
5789 rtx last_reg = reg_last_reload_reg[regno];
5790 enum machine_mode need_mode;
5792 i = REGNO (last_reg);
5793 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5794 last_class = REGNO_REG_CLASS (i);
5800 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5801 + byte * BITS_PER_UNIT,
5802 GET_MODE_CLASS (mode));
5804 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5805 >= GET_MODE_SIZE (need_mode))
5806 && reg_reloaded_contents[i] == regno
5807 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5808 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5809 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5810 /* Even if we can't use this register as a reload
5811 register, we might use it for reload_override_in,
5812 if copying it to the desired class is cheap
5814 || ((REGISTER_MOVE_COST (mode, last_class, class)
5815 < MEMORY_MOVE_COST (mode, class, 1))
5816 && (secondary_reload_class (1, class, mode,
5819 #ifdef SECONDARY_MEMORY_NEEDED
5820 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5825 && (rld[r].nregs == max_group_size
5826 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5828 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5829 rld[r].when_needed, rld[r].in,
5832 /* If a group is needed, verify that all the subsequent
5833 registers still have their values intact. */
5834 int nr = hard_regno_nregs[i][rld[r].mode];
5837 for (k = 1; k < nr; k++)
5838 if (reg_reloaded_contents[i + k] != regno
5839 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5847 last_reg = (GET_MODE (last_reg) == mode
5848 ? last_reg : gen_rtx_REG (mode, i));
5851 for (k = 0; k < nr; k++)
5852 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5855 /* We found a register that contains the
5856 value we need. If this register is the
5857 same as an `earlyclobber' operand of the
5858 current insn, just mark it as a place to
5859 reload from since we can't use it as the
5860 reload register itself. */
5862 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5863 if (reg_overlap_mentioned_for_reload_p
5864 (reg_last_reload_reg[regno],
5865 reload_earlyclobbers[i1]))
5868 if (i1 != n_earlyclobbers
5869 || ! (free_for_value_p (i, rld[r].mode,
5871 rld[r].when_needed, rld[r].in,
5873 /* Don't use it if we'd clobber a pseudo reg. */
5874 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5876 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5877 /* Don't clobber the frame pointer. */
5878 || (i == HARD_FRAME_POINTER_REGNUM
5879 && frame_pointer_needed
5881 /* Don't really use the inherited spill reg
5882 if we need it wider than we've got it. */
5883 || (GET_MODE_SIZE (rld[r].mode)
5884 > GET_MODE_SIZE (mode))
5887 /* If find_reloads chose reload_out as reload
5888 register, stay with it - that leaves the
5889 inherited register for subsequent reloads. */
5890 || (rld[r].out && rld[r].reg_rtx
5891 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5893 if (! rld[r].optional)
5895 reload_override_in[r] = last_reg;
5896 reload_inheritance_insn[r]
5897 = reg_reloaded_insn[i];
5903 /* We can use this as a reload reg. */
5904 /* Mark the register as in use for this part of
5906 mark_reload_reg_in_use (i,
5910 rld[r].reg_rtx = last_reg;
5911 reload_inherited[r] = 1;
5912 reload_inheritance_insn[r]
5913 = reg_reloaded_insn[i];
5914 reload_spill_index[r] = i;
5915 for (k = 0; k < nr; k++)
5916 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5924 /* Here's another way to see if the value is already lying around. */
5927 && ! reload_inherited[r]
5929 && (CONSTANT_P (rld[r].in)
5930 || GET_CODE (rld[r].in) == PLUS
5931 || REG_P (rld[r].in)
5932 || MEM_P (rld[r].in))
5933 && (rld[r].nregs == max_group_size
5934 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5935 search_equiv = rld[r].in;
5936 /* If this is an output reload from a simple move insn, look
5937 if an equivalence for the input is available. */
5938 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5940 rtx set = single_set (insn);
5943 && rtx_equal_p (rld[r].out, SET_DEST (set))
5944 && CONSTANT_P (SET_SRC (set)))
5945 search_equiv = SET_SRC (set);
5951 = find_equiv_reg (search_equiv, insn, rld[r].class,
5952 -1, NULL, 0, rld[r].mode);
5958 regno = REGNO (equiv);
5961 /* This must be a SUBREG of a hard register.
5962 Make a new REG since this might be used in an
5963 address and not all machines support SUBREGs
5965 gcc_assert (GET_CODE (equiv) == SUBREG);
5966 regno = subreg_regno (equiv);
5967 equiv = gen_rtx_REG (rld[r].mode, regno);
5968 /* If we choose EQUIV as the reload register, but the
5969 loop below decides to cancel the inheritance, we'll
5970 end up reloading EQUIV in rld[r].mode, not the mode
5971 it had originally. That isn't safe when EQUIV isn't
5972 available as a spill register since its value might
5973 still be live at this point. */
5974 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5975 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5980 /* If we found a spill reg, reject it unless it is free
5981 and of the desired class. */
5985 int bad_for_class = 0;
5986 int max_regno = regno + rld[r].nregs;
5988 for (i = regno; i < max_regno; i++)
5990 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5992 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5997 && ! free_for_value_p (regno, rld[r].mode,
5998 rld[r].opnum, rld[r].when_needed,
5999 rld[r].in, rld[r].out, r, 1))
6004 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6007 /* We found a register that contains the value we need.
6008 If this register is the same as an `earlyclobber' operand
6009 of the current insn, just mark it as a place to reload from
6010 since we can't use it as the reload register itself. */
6013 for (i = 0; i < n_earlyclobbers; i++)
6014 if (reg_overlap_mentioned_for_reload_p (equiv,
6015 reload_earlyclobbers[i]))
6017 if (! rld[r].optional)
6018 reload_override_in[r] = equiv;
6023 /* If the equiv register we have found is explicitly clobbered
6024 in the current insn, it depends on the reload type if we
6025 can use it, use it for reload_override_in, or not at all.
6026 In particular, we then can't use EQUIV for a
6027 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6031 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6032 switch (rld[r].when_needed)
6034 case RELOAD_FOR_OTHER_ADDRESS:
6035 case RELOAD_FOR_INPADDR_ADDRESS:
6036 case RELOAD_FOR_INPUT_ADDRESS:
6037 case RELOAD_FOR_OPADDR_ADDR:
6040 case RELOAD_FOR_INPUT:
6041 case RELOAD_FOR_OPERAND_ADDRESS:
6042 if (! rld[r].optional)
6043 reload_override_in[r] = equiv;
6049 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6050 switch (rld[r].when_needed)
6052 case RELOAD_FOR_OTHER_ADDRESS:
6053 case RELOAD_FOR_INPADDR_ADDRESS:
6054 case RELOAD_FOR_INPUT_ADDRESS:
6055 case RELOAD_FOR_OPADDR_ADDR:
6056 case RELOAD_FOR_OPERAND_ADDRESS:
6057 case RELOAD_FOR_INPUT:
6060 if (! rld[r].optional)
6061 reload_override_in[r] = equiv;
6069 /* If we found an equivalent reg, say no code need be generated
6070 to load it, and use it as our reload reg. */
6072 && (regno != HARD_FRAME_POINTER_REGNUM
6073 || !frame_pointer_needed))
6075 int nr = hard_regno_nregs[regno][rld[r].mode];
6077 rld[r].reg_rtx = equiv;
6078 reload_inherited[r] = 1;
6080 /* If reg_reloaded_valid is not set for this register,
6081 there might be a stale spill_reg_store lying around.
6082 We must clear it, since otherwise emit_reload_insns
6083 might delete the store. */
6084 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6085 spill_reg_store[regno] = NULL_RTX;
6086 /* If any of the hard registers in EQUIV are spill
6087 registers, mark them as in use for this insn. */
6088 for (k = 0; k < nr; k++)
6090 i = spill_reg_order[regno + k];
6093 mark_reload_reg_in_use (regno, rld[r].opnum,
6096 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6103 /* If we found a register to use already, or if this is an optional
6104 reload, we are done. */
6105 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6109 /* No longer needed for correct operation. Might or might
6110 not give better code on the average. Want to experiment? */
6112 /* See if there is a later reload that has a class different from our
6113 class that intersects our class or that requires less register
6114 than our reload. If so, we must allocate a register to this
6115 reload now, since that reload might inherit a previous reload
6116 and take the only available register in our class. Don't do this
6117 for optional reloads since they will force all previous reloads
6118 to be allocated. Also don't do this for reloads that have been
6121 for (i = j + 1; i < n_reloads; i++)
6123 int s = reload_order[i];
6125 if ((rld[s].in == 0 && rld[s].out == 0
6126 && ! rld[s].secondary_p)
6130 if ((rld[s].class != rld[r].class
6131 && reg_classes_intersect_p (rld[r].class,
6133 || rld[s].nregs < rld[r].nregs)
6140 allocate_reload_reg (chain, r, j == n_reloads - 1);
6144 /* Now allocate reload registers for anything non-optional that
6145 didn't get one yet. */
6146 for (j = 0; j < n_reloads; j++)
6148 int r = reload_order[j];
6150 /* Ignore reloads that got marked inoperative. */
6151 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6154 /* Skip reloads that already have a register allocated or are
6156 if (rld[r].reg_rtx != 0 || rld[r].optional)
6159 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6163 /* If that loop got all the way, we have won. */
6170 /* Loop around and try without any inheritance. */
6175 /* First undo everything done by the failed attempt
6176 to allocate with inheritance. */
6177 choose_reload_regs_init (chain, save_reload_reg_rtx);
6179 /* Some sanity tests to verify that the reloads found in the first
6180 pass are identical to the ones we have now. */
6181 gcc_assert (chain->n_reloads == n_reloads);
6183 for (i = 0; i < n_reloads; i++)
6185 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6187 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6188 for (j = 0; j < n_spills; j++)
6189 if (spill_regs[j] == chain->rld[i].regno)
6190 if (! set_reload_reg (j, i))
6191 failed_reload (chain->insn, i);
6195 /* If we thought we could inherit a reload, because it seemed that
6196 nothing else wanted the same reload register earlier in the insn,
6197 verify that assumption, now that all reloads have been assigned.
6198 Likewise for reloads where reload_override_in has been set. */
6200 /* If doing expensive optimizations, do one preliminary pass that doesn't
6201 cancel any inheritance, but removes reloads that have been needed only
6202 for reloads that we know can be inherited. */
6203 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6205 for (j = 0; j < n_reloads; j++)
6207 int r = reload_order[j];
6209 if (reload_inherited[r] && rld[r].reg_rtx)
6210 check_reg = rld[r].reg_rtx;
6211 else if (reload_override_in[r]
6212 && (REG_P (reload_override_in[r])
6213 || GET_CODE (reload_override_in[r]) == SUBREG))
6214 check_reg = reload_override_in[r];
6217 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6218 rld[r].opnum, rld[r].when_needed, rld[r].in,
6219 (reload_inherited[r]
6220 ? rld[r].out : const0_rtx),
6225 reload_inherited[r] = 0;
6226 reload_override_in[r] = 0;
6228 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6229 reload_override_in, then we do not need its related
6230 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6231 likewise for other reload types.
6232 We handle this by removing a reload when its only replacement
6233 is mentioned in reload_in of the reload we are going to inherit.
6234 A special case are auto_inc expressions; even if the input is
6235 inherited, we still need the address for the output. We can
6236 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6237 If we succeeded removing some reload and we are doing a preliminary
6238 pass just to remove such reloads, make another pass, since the
6239 removal of one reload might allow us to inherit another one. */
6241 && rld[r].out != rld[r].in
6242 && remove_address_replacements (rld[r].in) && pass)
6247 /* Now that reload_override_in is known valid,
6248 actually override reload_in. */
6249 for (j = 0; j < n_reloads; j++)
6250 if (reload_override_in[j])
6251 rld[j].in = reload_override_in[j];
6253 /* If this reload won't be done because it has been canceled or is
6254 optional and not inherited, clear reload_reg_rtx so other
6255 routines (such as subst_reloads) don't get confused. */
6256 for (j = 0; j < n_reloads; j++)
6257 if (rld[j].reg_rtx != 0
6258 && ((rld[j].optional && ! reload_inherited[j])
6259 || (rld[j].in == 0 && rld[j].out == 0
6260 && ! rld[j].secondary_p)))
6262 int regno = true_regnum (rld[j].reg_rtx);
6264 if (spill_reg_order[regno] >= 0)
6265 clear_reload_reg_in_use (regno, rld[j].opnum,
6266 rld[j].when_needed, rld[j].mode);
6268 reload_spill_index[j] = -1;
6271 /* Record which pseudos and which spill regs have output reloads. */
6272 for (j = 0; j < n_reloads; j++)
6274 int r = reload_order[j];
6276 i = reload_spill_index[r];
6278 /* I is nonneg if this reload uses a register.
6279 If rld[r].reg_rtx is 0, this is an optional reload
6280 that we opted to ignore. */
6281 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6282 && rld[r].reg_rtx != 0)
6284 int nregno = REGNO (rld[r].out_reg);
6287 if (nregno < FIRST_PSEUDO_REGISTER)
6288 nr = hard_regno_nregs[nregno][rld[r].mode];
6291 SET_REGNO_REG_SET (®_has_output_reload,
6296 nr = hard_regno_nregs[i][rld[r].mode];
6298 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6301 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6302 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6303 || rld[r].when_needed == RELOAD_FOR_INSN);
6308 /* Deallocate the reload register for reload R. This is called from
6309 remove_address_replacements. */
6312 deallocate_reload_reg (int r)
6316 if (! rld[r].reg_rtx)
6318 regno = true_regnum (rld[r].reg_rtx);
6320 if (spill_reg_order[regno] >= 0)
6321 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6323 reload_spill_index[r] = -1;
6326 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6327 reloads of the same item for fear that we might not have enough reload
6328 registers. However, normally they will get the same reload register
6329 and hence actually need not be loaded twice.
6331 Here we check for the most common case of this phenomenon: when we have
6332 a number of reloads for the same object, each of which were allocated
6333 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6334 reload, and is not modified in the insn itself. If we find such,
6335 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6336 This will not increase the number of spill registers needed and will
6337 prevent redundant code. */
6340 merge_assigned_reloads (rtx insn)
6344 /* Scan all the reloads looking for ones that only load values and
6345 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6346 assigned and not modified by INSN. */
6348 for (i = 0; i < n_reloads; i++)
6350 int conflicting_input = 0;
6351 int max_input_address_opnum = -1;
6352 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6354 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6355 || rld[i].out != 0 || rld[i].reg_rtx == 0
6356 || reg_set_p (rld[i].reg_rtx, insn))
6359 /* Look at all other reloads. Ensure that the only use of this
6360 reload_reg_rtx is in a reload that just loads the same value
6361 as we do. Note that any secondary reloads must be of the identical
6362 class since the values, modes, and result registers are the
6363 same, so we need not do anything with any secondary reloads. */
6365 for (j = 0; j < n_reloads; j++)
6367 if (i == j || rld[j].reg_rtx == 0
6368 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6372 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6373 && rld[j].opnum > max_input_address_opnum)
6374 max_input_address_opnum = rld[j].opnum;
6376 /* If the reload regs aren't exactly the same (e.g, different modes)
6377 or if the values are different, we can't merge this reload.
6378 But if it is an input reload, we might still merge
6379 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6381 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6382 || rld[j].out != 0 || rld[j].in == 0
6383 || ! rtx_equal_p (rld[i].in, rld[j].in))
6385 if (rld[j].when_needed != RELOAD_FOR_INPUT
6386 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6387 || rld[i].opnum > rld[j].opnum)
6388 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6390 conflicting_input = 1;
6391 if (min_conflicting_input_opnum > rld[j].opnum)
6392 min_conflicting_input_opnum = rld[j].opnum;
6396 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6397 we, in fact, found any matching reloads. */
6400 && max_input_address_opnum <= min_conflicting_input_opnum)
6402 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6404 for (j = 0; j < n_reloads; j++)
6405 if (i != j && rld[j].reg_rtx != 0
6406 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6407 && (! conflicting_input
6408 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6409 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6411 rld[i].when_needed = RELOAD_OTHER;
6413 reload_spill_index[j] = -1;
6414 transfer_replacements (i, j);
6417 /* If this is now RELOAD_OTHER, look for any reloads that
6418 load parts of this operand and set them to
6419 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6420 RELOAD_OTHER for outputs. Note that this test is
6421 equivalent to looking for reloads for this operand
6424 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6425 it may share registers with a RELOAD_FOR_INPUT, so we can
6426 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6427 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6429 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6430 instruction is assigned the same register as the earlier
6431 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6432 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6433 instruction to be deleted later on. */
6435 if (rld[i].when_needed == RELOAD_OTHER)
6436 for (j = 0; j < n_reloads; j++)
6438 && rld[j].when_needed != RELOAD_OTHER
6439 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6440 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6441 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6442 && (! conflicting_input
6443 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6444 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6445 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6451 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6452 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6453 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6455 /* Check to see if we accidentally converted two
6456 reloads that use the same reload register with
6457 different inputs to the same type. If so, the
6458 resulting code won't work. */
6460 for (k = 0; k < j; k++)
6461 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6462 || rld[k].when_needed != rld[j].when_needed
6463 || !rtx_equal_p (rld[k].reg_rtx,
6465 || rtx_equal_p (rld[k].in,
6472 /* These arrays are filled by emit_reload_insns and its subroutines. */
6473 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6474 static rtx other_input_address_reload_insns = 0;
6475 static rtx other_input_reload_insns = 0;
6476 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6477 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6478 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6479 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6480 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6481 static rtx operand_reload_insns = 0;
6482 static rtx other_operand_reload_insns = 0;
6483 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6485 /* Values to be put in spill_reg_store are put here first. */
6486 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6487 static HARD_REG_SET reg_reloaded_died;
6489 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6490 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6491 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6492 adjusted register, and return true. Otherwise, return false. */
6494 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6495 enum reg_class new_class,
6496 enum machine_mode new_mode)
6501 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6503 unsigned regno = REGNO (reg);
6505 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6507 if (GET_MODE (reg) != new_mode)
6509 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6511 if (hard_regno_nregs[regno][new_mode]
6512 > hard_regno_nregs[regno][GET_MODE (reg)])
6514 reg = reload_adjust_reg_for_mode (reg, new_mode);
6522 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6523 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6524 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6525 adjusted register, and return true. Otherwise, return false. */
6527 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6528 enum insn_code icode)
6531 enum reg_class new_class = scratch_reload_class (icode);
6532 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6534 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6535 new_class, new_mode);
6538 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6539 has the number J. OLD contains the value to be used as input. */
6542 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6545 rtx insn = chain->insn;
6546 rtx reloadreg = rl->reg_rtx;
6547 rtx oldequiv_reg = 0;
6550 enum machine_mode mode;
6553 /* Determine the mode to reload in.
6554 This is very tricky because we have three to choose from.
6555 There is the mode the insn operand wants (rl->inmode).
6556 There is the mode of the reload register RELOADREG.
6557 There is the intrinsic mode of the operand, which we could find
6558 by stripping some SUBREGs.
6559 It turns out that RELOADREG's mode is irrelevant:
6560 we can change that arbitrarily.
6562 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6563 then the reload reg may not support QImode moves, so use SImode.
6564 If foo is in memory due to spilling a pseudo reg, this is safe,
6565 because the QImode value is in the least significant part of a
6566 slot big enough for a SImode. If foo is some other sort of
6567 memory reference, then it is impossible to reload this case,
6568 so previous passes had better make sure this never happens.
6570 Then consider a one-word union which has SImode and one of its
6571 members is a float, being fetched as (SUBREG:SF union:SI).
6572 We must fetch that as SFmode because we could be loading into
6573 a float-only register. In this case OLD's mode is correct.
6575 Consider an immediate integer: it has VOIDmode. Here we need
6576 to get a mode from something else.
6578 In some cases, there is a fourth mode, the operand's
6579 containing mode. If the insn specifies a containing mode for
6580 this operand, it overrides all others.
6582 I am not sure whether the algorithm here is always right,
6583 but it does the right things in those cases. */
6585 mode = GET_MODE (old);
6586 if (mode == VOIDmode)
6589 /* delete_output_reload is only invoked properly if old contains
6590 the original pseudo register. Since this is replaced with a
6591 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6592 find the pseudo in RELOAD_IN_REG. */
6593 if (reload_override_in[j]
6594 && REG_P (rl->in_reg))
6601 else if (REG_P (oldequiv))
6602 oldequiv_reg = oldequiv;
6603 else if (GET_CODE (oldequiv) == SUBREG)
6604 oldequiv_reg = SUBREG_REG (oldequiv);
6606 /* If we are reloading from a register that was recently stored in
6607 with an output-reload, see if we can prove there was
6608 actually no need to store the old value in it. */
6610 if (optimize && REG_P (oldequiv)
6611 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6612 && spill_reg_store[REGNO (oldequiv)]
6614 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6615 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6617 delete_output_reload (insn, j, REGNO (oldequiv));
6619 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6620 then load RELOADREG from OLDEQUIV. Note that we cannot use
6621 gen_lowpart_common since it can do the wrong thing when
6622 RELOADREG has a multi-word mode. Note that RELOADREG
6623 must always be a REG here. */
6625 if (GET_MODE (reloadreg) != mode)
6626 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6627 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6628 oldequiv = SUBREG_REG (oldequiv);
6629 if (GET_MODE (oldequiv) != VOIDmode
6630 && mode != GET_MODE (oldequiv))
6631 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6633 /* Switch to the right place to emit the reload insns. */
6634 switch (rl->when_needed)
6637 where = &other_input_reload_insns;
6639 case RELOAD_FOR_INPUT:
6640 where = &input_reload_insns[rl->opnum];
6642 case RELOAD_FOR_INPUT_ADDRESS:
6643 where = &input_address_reload_insns[rl->opnum];
6645 case RELOAD_FOR_INPADDR_ADDRESS:
6646 where = &inpaddr_address_reload_insns[rl->opnum];
6648 case RELOAD_FOR_OUTPUT_ADDRESS:
6649 where = &output_address_reload_insns[rl->opnum];
6651 case RELOAD_FOR_OUTADDR_ADDRESS:
6652 where = &outaddr_address_reload_insns[rl->opnum];
6654 case RELOAD_FOR_OPERAND_ADDRESS:
6655 where = &operand_reload_insns;
6657 case RELOAD_FOR_OPADDR_ADDR:
6658 where = &other_operand_reload_insns;
6660 case RELOAD_FOR_OTHER_ADDRESS:
6661 where = &other_input_address_reload_insns;
6667 push_to_sequence (*where);
6669 /* Auto-increment addresses must be reloaded in a special way. */
6670 if (rl->out && ! rl->out_reg)
6672 /* We are not going to bother supporting the case where a
6673 incremented register can't be copied directly from
6674 OLDEQUIV since this seems highly unlikely. */
6675 gcc_assert (rl->secondary_in_reload < 0);
6677 if (reload_inherited[j])
6678 oldequiv = reloadreg;
6680 old = XEXP (rl->in_reg, 0);
6682 if (optimize && REG_P (oldequiv)
6683 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6684 && spill_reg_store[REGNO (oldequiv)]
6686 && (dead_or_set_p (insn,
6687 spill_reg_stored_to[REGNO (oldequiv)])
6688 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6690 delete_output_reload (insn, j, REGNO (oldequiv));
6692 /* Prevent normal processing of this reload. */
6694 /* Output a special code sequence for this case. */
6695 new_spill_reg_store[REGNO (reloadreg)]
6696 = inc_for_reload (reloadreg, oldequiv, rl->out,
6700 /* If we are reloading a pseudo-register that was set by the previous
6701 insn, see if we can get rid of that pseudo-register entirely
6702 by redirecting the previous insn into our reload register. */
6704 else if (optimize && REG_P (old)
6705 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6706 && dead_or_set_p (insn, old)
6707 /* This is unsafe if some other reload
6708 uses the same reg first. */
6709 && ! conflicts_with_override (reloadreg)
6710 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6711 rl->when_needed, old, rl->out, j, 0))
6713 rtx temp = PREV_INSN (insn);
6714 while (temp && NOTE_P (temp))
6715 temp = PREV_INSN (temp);
6717 && NONJUMP_INSN_P (temp)
6718 && GET_CODE (PATTERN (temp)) == SET
6719 && SET_DEST (PATTERN (temp)) == old
6720 /* Make sure we can access insn_operand_constraint. */
6721 && asm_noperands (PATTERN (temp)) < 0
6722 /* This is unsafe if operand occurs more than once in current
6723 insn. Perhaps some occurrences aren't reloaded. */
6724 && count_occurrences (PATTERN (insn), old, 0) == 1)
6726 rtx old = SET_DEST (PATTERN (temp));
6727 /* Store into the reload register instead of the pseudo. */
6728 SET_DEST (PATTERN (temp)) = reloadreg;
6730 /* Verify that resulting insn is valid. */
6731 extract_insn (temp);
6732 if (constrain_operands (1))
6734 /* If the previous insn is an output reload, the source is
6735 a reload register, and its spill_reg_store entry will
6736 contain the previous destination. This is now
6738 if (REG_P (SET_SRC (PATTERN (temp)))
6739 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6741 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6742 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6745 /* If these are the only uses of the pseudo reg,
6746 pretend for GDB it lives in the reload reg we used. */
6747 if (REG_N_DEATHS (REGNO (old)) == 1
6748 && REG_N_SETS (REGNO (old)) == 1)
6750 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6751 alter_reg (REGNO (old), -1);
6757 SET_DEST (PATTERN (temp)) = old;
6762 /* We can't do that, so output an insn to load RELOADREG. */
6764 /* If we have a secondary reload, pick up the secondary register
6765 and icode, if any. If OLDEQUIV and OLD are different or
6766 if this is an in-out reload, recompute whether or not we
6767 still need a secondary register and what the icode should
6768 be. If we still need a secondary register and the class or
6769 icode is different, go back to reloading from OLD if using
6770 OLDEQUIV means that we got the wrong type of register. We
6771 cannot have different class or icode due to an in-out reload
6772 because we don't make such reloads when both the input and
6773 output need secondary reload registers. */
6775 if (! special && rl->secondary_in_reload >= 0)
6777 rtx second_reload_reg = 0;
6778 rtx third_reload_reg = 0;
6779 int secondary_reload = rl->secondary_in_reload;
6780 rtx real_oldequiv = oldequiv;
6783 enum insn_code icode;
6784 enum insn_code tertiary_icode = CODE_FOR_nothing;
6786 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6787 and similarly for OLD.
6788 See comments in get_secondary_reload in reload.c. */
6789 /* If it is a pseudo that cannot be replaced with its
6790 equivalent MEM, we must fall back to reload_in, which
6791 will have all the necessary substitutions registered.
6792 Likewise for a pseudo that can't be replaced with its
6793 equivalent constant.
6795 Take extra care for subregs of such pseudos. Note that
6796 we cannot use reg_equiv_mem in this case because it is
6797 not in the right mode. */
6800 if (GET_CODE (tmp) == SUBREG)
6801 tmp = SUBREG_REG (tmp);
6803 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6804 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6805 || reg_equiv_constant[REGNO (tmp)] != 0))
6807 if (! reg_equiv_mem[REGNO (tmp)]
6808 || num_not_at_initial_offset
6809 || GET_CODE (oldequiv) == SUBREG)
6810 real_oldequiv = rl->in;
6812 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6816 if (GET_CODE (tmp) == SUBREG)
6817 tmp = SUBREG_REG (tmp);
6819 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6820 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6821 || reg_equiv_constant[REGNO (tmp)] != 0))
6823 if (! reg_equiv_mem[REGNO (tmp)]
6824 || num_not_at_initial_offset
6825 || GET_CODE (old) == SUBREG)
6828 real_old = reg_equiv_mem[REGNO (tmp)];
6831 second_reload_reg = rld[secondary_reload].reg_rtx;
6832 if (rld[secondary_reload].secondary_in_reload >= 0)
6834 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6836 third_reload_reg = rld[tertiary_reload].reg_rtx;
6837 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6838 /* We'd have to add more code for quartary reloads. */
6839 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6841 icode = rl->secondary_in_icode;
6843 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6844 || (rl->in != 0 && rl->out != 0))
6846 secondary_reload_info sri, sri2;
6847 enum reg_class new_class, new_t_class;
6849 sri.icode = CODE_FOR_nothing;
6850 sri.prev_sri = NULL;
6851 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6854 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6855 second_reload_reg = 0;
6856 else if (new_class == NO_REGS)
6858 if (reload_adjust_reg_for_icode (&second_reload_reg,
6859 third_reload_reg, sri.icode))
6860 icode = sri.icode, third_reload_reg = 0;
6862 oldequiv = old, real_oldequiv = real_old;
6864 else if (sri.icode != CODE_FOR_nothing)
6865 /* We currently lack a way to express this in reloads. */
6869 sri2.icode = CODE_FOR_nothing;
6870 sri2.prev_sri = &sri;
6871 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6872 new_class, mode, &sri);
6873 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6875 if (reload_adjust_reg_for_temp (&second_reload_reg,
6878 third_reload_reg = 0, tertiary_icode = sri2.icode;
6880 oldequiv = old, real_oldequiv = real_old;
6882 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6884 rtx intermediate = second_reload_reg;
6886 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6888 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6891 second_reload_reg = intermediate;
6892 tertiary_icode = sri2.icode;
6895 oldequiv = old, real_oldequiv = real_old;
6897 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6899 rtx intermediate = second_reload_reg;
6901 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6903 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6906 second_reload_reg = intermediate;
6907 tertiary_icode = sri2.icode;
6910 oldequiv = old, real_oldequiv = real_old;
6913 /* This could be handled more intelligently too. */
6914 oldequiv = old, real_oldequiv = real_old;
6918 /* If we still need a secondary reload register, check
6919 to see if it is being used as a scratch or intermediate
6920 register and generate code appropriately. If we need
6921 a scratch register, use REAL_OLDEQUIV since the form of
6922 the insn may depend on the actual address if it is
6925 if (second_reload_reg)
6927 if (icode != CODE_FOR_nothing)
6929 /* We'd have to add extra code to handle this case. */
6930 gcc_assert (!third_reload_reg);
6932 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6933 second_reload_reg));
6938 /* See if we need a scratch register to load the
6939 intermediate register (a tertiary reload). */
6940 if (tertiary_icode != CODE_FOR_nothing)
6942 emit_insn ((GEN_FCN (tertiary_icode)
6943 (second_reload_reg, real_oldequiv,
6944 third_reload_reg)));
6946 else if (third_reload_reg)
6948 gen_reload (third_reload_reg, real_oldequiv,
6951 gen_reload (second_reload_reg, third_reload_reg,
6956 gen_reload (second_reload_reg, real_oldequiv,
6960 oldequiv = second_reload_reg;
6965 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6967 rtx real_oldequiv = oldequiv;
6969 if ((REG_P (oldequiv)
6970 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6971 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6972 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6973 || (GET_CODE (oldequiv) == SUBREG
6974 && REG_P (SUBREG_REG (oldequiv))
6975 && (REGNO (SUBREG_REG (oldequiv))
6976 >= FIRST_PSEUDO_REGISTER)
6977 && ((reg_equiv_memory_loc
6978 [REGNO (SUBREG_REG (oldequiv))] != 0)
6979 || (reg_equiv_constant
6980 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6981 || (CONSTANT_P (oldequiv)
6982 && (PREFERRED_RELOAD_CLASS (oldequiv,
6983 REGNO_REG_CLASS (REGNO (reloadreg)))
6985 real_oldequiv = rl->in;
6986 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6990 if (flag_non_call_exceptions)
6991 copy_eh_notes (insn, get_insns ());
6993 /* End this sequence. */
6994 *where = get_insns ();
6997 /* Update reload_override_in so that delete_address_reloads_1
6998 can see the actual register usage. */
7000 reload_override_in[j] = oldequiv;
7003 /* Generate insns to for the output reload RL, which is for the insn described
7004 by CHAIN and has the number J. */
7006 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7009 rtx reloadreg = rl->reg_rtx;
7010 rtx insn = chain->insn;
7013 enum machine_mode mode = GET_MODE (old);
7016 if (rl->when_needed == RELOAD_OTHER)
7019 push_to_sequence (output_reload_insns[rl->opnum]);
7021 /* Determine the mode to reload in.
7022 See comments above (for input reloading). */
7024 if (mode == VOIDmode)
7026 /* VOIDmode should never happen for an output. */
7027 if (asm_noperands (PATTERN (insn)) < 0)
7028 /* It's the compiler's fault. */
7029 fatal_insn ("VOIDmode on an output", insn);
7030 error_for_asm (insn, "output operand is constant in %<asm%>");
7031 /* Prevent crash--use something we know is valid. */
7033 old = gen_rtx_REG (mode, REGNO (reloadreg));
7036 if (GET_MODE (reloadreg) != mode)
7037 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7039 /* If we need two reload regs, set RELOADREG to the intermediate
7040 one, since it will be stored into OLD. We might need a secondary
7041 register only for an input reload, so check again here. */
7043 if (rl->secondary_out_reload >= 0)
7046 int secondary_reload = rl->secondary_out_reload;
7047 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7049 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7050 && reg_equiv_mem[REGNO (old)] != 0)
7051 real_old = reg_equiv_mem[REGNO (old)];
7053 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
7055 rtx second_reloadreg = reloadreg;
7056 reloadreg = rld[secondary_reload].reg_rtx;
7058 /* See if RELOADREG is to be used as a scratch register
7059 or as an intermediate register. */
7060 if (rl->secondary_out_icode != CODE_FOR_nothing)
7062 /* We'd have to add extra code to handle this case. */
7063 gcc_assert (tertiary_reload < 0);
7065 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7066 (real_old, second_reloadreg, reloadreg)));
7071 /* See if we need both a scratch and intermediate reload
7074 enum insn_code tertiary_icode
7075 = rld[secondary_reload].secondary_out_icode;
7077 /* We'd have to add more code for quartary reloads. */
7078 gcc_assert (tertiary_reload < 0
7079 || rld[tertiary_reload].secondary_out_reload < 0);
7081 if (GET_MODE (reloadreg) != mode)
7082 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7084 if (tertiary_icode != CODE_FOR_nothing)
7086 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7089 /* Copy primary reload reg to secondary reload reg.
7090 (Note that these have been swapped above, then
7091 secondary reload reg to OLD using our insn.) */
7093 /* If REAL_OLD is a paradoxical SUBREG, remove it
7094 and try to put the opposite SUBREG on
7096 if (GET_CODE (real_old) == SUBREG
7097 && (GET_MODE_SIZE (GET_MODE (real_old))
7098 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7099 && 0 != (tem = gen_lowpart_common
7100 (GET_MODE (SUBREG_REG (real_old)),
7102 real_old = SUBREG_REG (real_old), reloadreg = tem;
7104 gen_reload (reloadreg, second_reloadreg,
7105 rl->opnum, rl->when_needed);
7106 emit_insn ((GEN_FCN (tertiary_icode)
7107 (real_old, reloadreg, third_reloadreg)));
7113 /* Copy between the reload regs here and then to
7116 gen_reload (reloadreg, second_reloadreg,
7117 rl->opnum, rl->when_needed);
7118 if (tertiary_reload >= 0)
7120 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7122 gen_reload (third_reloadreg, reloadreg,
7123 rl->opnum, rl->when_needed);
7124 reloadreg = third_reloadreg;
7131 /* Output the last reload insn. */
7136 /* Don't output the last reload if OLD is not the dest of
7137 INSN and is in the src and is clobbered by INSN. */
7138 if (! flag_expensive_optimizations
7140 || !(set = single_set (insn))
7141 || rtx_equal_p (old, SET_DEST (set))
7142 || !reg_mentioned_p (old, SET_SRC (set))
7143 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7144 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7145 gen_reload (old, reloadreg, rl->opnum,
7149 /* Look at all insns we emitted, just to be safe. */
7150 for (p = get_insns (); p; p = NEXT_INSN (p))
7153 rtx pat = PATTERN (p);
7155 /* If this output reload doesn't come from a spill reg,
7156 clear any memory of reloaded copies of the pseudo reg.
7157 If this output reload comes from a spill reg,
7158 reg_has_output_reload will make this do nothing. */
7159 note_stores (pat, forget_old_reloads_1, NULL);
7161 if (reg_mentioned_p (rl->reg_rtx, pat))
7163 rtx set = single_set (insn);
7164 if (reload_spill_index[j] < 0
7166 && SET_SRC (set) == rl->reg_rtx)
7168 int src = REGNO (SET_SRC (set));
7170 reload_spill_index[j] = src;
7171 SET_HARD_REG_BIT (reg_is_output_reload, src);
7172 if (find_regno_note (insn, REG_DEAD, src))
7173 SET_HARD_REG_BIT (reg_reloaded_died, src);
7175 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7177 int s = rl->secondary_out_reload;
7178 set = single_set (p);
7179 /* If this reload copies only to the secondary reload
7180 register, the secondary reload does the actual
7182 if (s >= 0 && set == NULL_RTX)
7183 /* We can't tell what function the secondary reload
7184 has and where the actual store to the pseudo is
7185 made; leave new_spill_reg_store alone. */
7188 && SET_SRC (set) == rl->reg_rtx
7189 && SET_DEST (set) == rld[s].reg_rtx)
7191 /* Usually the next instruction will be the
7192 secondary reload insn; if we can confirm
7193 that it is, setting new_spill_reg_store to
7194 that insn will allow an extra optimization. */
7195 rtx s_reg = rld[s].reg_rtx;
7196 rtx next = NEXT_INSN (p);
7197 rld[s].out = rl->out;
7198 rld[s].out_reg = rl->out_reg;
7199 set = single_set (next);
7200 if (set && SET_SRC (set) == s_reg
7201 && ! new_spill_reg_store[REGNO (s_reg)])
7203 SET_HARD_REG_BIT (reg_is_output_reload,
7205 new_spill_reg_store[REGNO (s_reg)] = next;
7209 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7214 if (rl->when_needed == RELOAD_OTHER)
7216 emit_insn (other_output_reload_insns[rl->opnum]);
7217 other_output_reload_insns[rl->opnum] = get_insns ();
7220 output_reload_insns[rl->opnum] = get_insns ();
7222 if (flag_non_call_exceptions)
7223 copy_eh_notes (insn, get_insns ());
7228 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7229 and has the number J. */
7231 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7233 rtx insn = chain->insn;
7234 rtx old = (rl->in && MEM_P (rl->in)
7235 ? rl->in_reg : rl->in);
7238 /* AUTO_INC reloads need to be handled even if inherited. We got an
7239 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7240 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7241 && ! rtx_equal_p (rl->reg_rtx, old)
7242 && rl->reg_rtx != 0)
7243 emit_input_reload_insns (chain, rld + j, old, j);
7245 /* When inheriting a wider reload, we have a MEM in rl->in,
7246 e.g. inheriting a SImode output reload for
7247 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7248 if (optimize && reload_inherited[j] && rl->in
7250 && MEM_P (rl->in_reg)
7251 && reload_spill_index[j] >= 0
7252 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7253 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7255 /* If we are reloading a register that was recently stored in with an
7256 output-reload, see if we can prove there was
7257 actually no need to store the old value in it. */
7260 && (reload_inherited[j] || reload_override_in[j])
7262 && REG_P (rl->reg_rtx)
7263 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7265 /* There doesn't seem to be any reason to restrict this to pseudos
7266 and doing so loses in the case where we are copying from a
7267 register of the wrong class. */
7268 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7269 >= FIRST_PSEUDO_REGISTER)
7271 /* The insn might have already some references to stackslots
7272 replaced by MEMs, while reload_out_reg still names the
7274 && (dead_or_set_p (insn,
7275 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7276 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7278 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7281 /* Do output reloading for reload RL, which is for the insn described by
7282 CHAIN and has the number J.
7283 ??? At some point we need to support handling output reloads of
7284 JUMP_INSNs or insns that set cc0. */
7286 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7289 rtx insn = chain->insn;
7290 /* If this is an output reload that stores something that is
7291 not loaded in this same reload, see if we can eliminate a previous
7293 rtx pseudo = rl->out_reg;
7298 && ! rtx_equal_p (rl->in_reg, pseudo)
7299 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7300 && reg_last_reload_reg[REGNO (pseudo)])
7302 int pseudo_no = REGNO (pseudo);
7303 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7305 /* We don't need to test full validity of last_regno for
7306 inherit here; we only want to know if the store actually
7307 matches the pseudo. */
7308 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7309 && reg_reloaded_contents[last_regno] == pseudo_no
7310 && spill_reg_store[last_regno]
7311 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7312 delete_output_reload (insn, j, last_regno);
7317 || rl->reg_rtx == old
7318 || rl->reg_rtx == 0)
7321 /* An output operand that dies right away does need a reload,
7322 but need not be copied from it. Show the new location in the
7324 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7325 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7327 XEXP (note, 0) = rl->reg_rtx;
7330 /* Likewise for a SUBREG of an operand that dies. */
7331 else if (GET_CODE (old) == SUBREG
7332 && REG_P (SUBREG_REG (old))
7333 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7336 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7340 else if (GET_CODE (old) == SCRATCH)
7341 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7342 but we don't want to make an output reload. */
7345 /* If is a JUMP_INSN, we can't support output reloads yet. */
7346 gcc_assert (NONJUMP_INSN_P (insn));
7348 emit_output_reload_insns (chain, rld + j, j);
7351 /* Reload number R reloads from or to a group of hard registers starting at
7352 register REGNO. Return true if it can be treated for inheritance purposes
7353 like a group of reloads, each one reloading a single hard register.
7354 The caller has already checked that the spill register and REGNO use
7355 the same number of registers to store the reload value. */
7358 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7360 #ifdef CANNOT_CHANGE_MODE_CLASS
7361 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7362 GET_MODE (rld[r].reg_rtx),
7363 reg_raw_mode[reload_spill_index[r]])
7364 && !REG_CANNOT_CHANGE_MODE_P (regno,
7365 GET_MODE (rld[r].reg_rtx),
7366 reg_raw_mode[regno]));
7372 /* Output insns to reload values in and out of the chosen reload regs. */
7375 emit_reload_insns (struct insn_chain *chain)
7377 rtx insn = chain->insn;
7381 CLEAR_HARD_REG_SET (reg_reloaded_died);
7383 for (j = 0; j < reload_n_operands; j++)
7384 input_reload_insns[j] = input_address_reload_insns[j]
7385 = inpaddr_address_reload_insns[j]
7386 = output_reload_insns[j] = output_address_reload_insns[j]
7387 = outaddr_address_reload_insns[j]
7388 = other_output_reload_insns[j] = 0;
7389 other_input_address_reload_insns = 0;
7390 other_input_reload_insns = 0;
7391 operand_reload_insns = 0;
7392 other_operand_reload_insns = 0;
7394 /* Dump reloads into the dump file. */
7397 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7398 debug_reload_to_stream (dump_file);
7401 /* Now output the instructions to copy the data into and out of the
7402 reload registers. Do these in the order that the reloads were reported,
7403 since reloads of base and index registers precede reloads of operands
7404 and the operands may need the base and index registers reloaded. */
7406 for (j = 0; j < n_reloads; j++)
7409 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7410 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7412 do_input_reload (chain, rld + j, j);
7413 do_output_reload (chain, rld + j, j);
7416 /* Now write all the insns we made for reloads in the order expected by
7417 the allocation functions. Prior to the insn being reloaded, we write
7418 the following reloads:
7420 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7422 RELOAD_OTHER reloads.
7424 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7425 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7426 RELOAD_FOR_INPUT reload for the operand.
7428 RELOAD_FOR_OPADDR_ADDRS reloads.
7430 RELOAD_FOR_OPERAND_ADDRESS reloads.
7432 After the insn being reloaded, we write the following:
7434 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7435 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7436 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7437 reloads for the operand. The RELOAD_OTHER output reloads are
7438 output in descending order by reload number. */
7440 emit_insn_before (other_input_address_reload_insns, insn);
7441 emit_insn_before (other_input_reload_insns, insn);
7443 for (j = 0; j < reload_n_operands; j++)
7445 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7446 emit_insn_before (input_address_reload_insns[j], insn);
7447 emit_insn_before (input_reload_insns[j], insn);
7450 emit_insn_before (other_operand_reload_insns, insn);
7451 emit_insn_before (operand_reload_insns, insn);
7453 for (j = 0; j < reload_n_operands; j++)
7455 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7456 x = emit_insn_after (output_address_reload_insns[j], x);
7457 x = emit_insn_after (output_reload_insns[j], x);
7458 emit_insn_after (other_output_reload_insns[j], x);
7461 /* For all the spill regs newly reloaded in this instruction,
7462 record what they were reloaded from, so subsequent instructions
7463 can inherit the reloads.
7465 Update spill_reg_store for the reloads of this insn.
7466 Copy the elements that were updated in the loop above. */
7468 for (j = 0; j < n_reloads; j++)
7470 int r = reload_order[j];
7471 int i = reload_spill_index[r];
7473 /* If this is a non-inherited input reload from a pseudo, we must
7474 clear any memory of a previous store to the same pseudo. Only do
7475 something if there will not be an output reload for the pseudo
7477 if (rld[r].in_reg != 0
7478 && ! (reload_inherited[r] || reload_override_in[r]))
7480 rtx reg = rld[r].in_reg;
7482 if (GET_CODE (reg) == SUBREG)
7483 reg = SUBREG_REG (reg);
7486 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7487 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7489 int nregno = REGNO (reg);
7491 if (reg_last_reload_reg[nregno])
7493 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7495 if (reg_reloaded_contents[last_regno] == nregno)
7496 spill_reg_store[last_regno] = 0;
7501 /* I is nonneg if this reload used a register.
7502 If rld[r].reg_rtx is 0, this is an optional reload
7503 that we opted to ignore. */
7505 if (i >= 0 && rld[r].reg_rtx != 0)
7507 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7509 int part_reaches_end = 0;
7510 int all_reaches_end = 1;
7512 /* For a multi register reload, we need to check if all or part
7513 of the value lives to the end. */
7514 for (k = 0; k < nr; k++)
7516 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7517 rld[r].when_needed))
7518 part_reaches_end = 1;
7520 all_reaches_end = 0;
7523 /* Ignore reloads that don't reach the end of the insn in
7525 if (all_reaches_end)
7527 /* First, clear out memory of what used to be in this spill reg.
7528 If consecutive registers are used, clear them all. */
7530 for (k = 0; k < nr; k++)
7532 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7533 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7536 /* Maybe the spill reg contains a copy of reload_out. */
7538 && (REG_P (rld[r].out)
7542 || REG_P (rld[r].out_reg)))
7544 rtx out = (REG_P (rld[r].out)
7548 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7549 int nregno = REGNO (out);
7550 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7551 : hard_regno_nregs[nregno]
7552 [GET_MODE (rld[r].reg_rtx)]);
7555 spill_reg_store[i] = new_spill_reg_store[i];
7556 spill_reg_stored_to[i] = out;
7557 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7559 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7561 && inherit_piecemeal_p (r, nregno));
7563 /* If NREGNO is a hard register, it may occupy more than
7564 one register. If it does, say what is in the
7565 rest of the registers assuming that both registers
7566 agree on how many words the object takes. If not,
7567 invalidate the subsequent registers. */
7569 if (nregno < FIRST_PSEUDO_REGISTER)
7570 for (k = 1; k < nnr; k++)
7571 reg_last_reload_reg[nregno + k]
7573 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7576 /* Now do the inverse operation. */
7577 for (k = 0; k < nr; k++)
7579 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7580 reg_reloaded_contents[i + k]
7581 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7584 reg_reloaded_insn[i + k] = insn;
7585 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7586 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7587 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7591 /* Maybe the spill reg contains a copy of reload_in. Only do
7592 something if there will not be an output reload for
7593 the register being reloaded. */
7594 else if (rld[r].out_reg == 0
7596 && ((REG_P (rld[r].in)
7597 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7598 && !REGNO_REG_SET_P (®_has_output_reload,
7600 || (REG_P (rld[r].in_reg)
7601 && !REGNO_REG_SET_P (®_has_output_reload,
7602 REGNO (rld[r].in_reg))))
7603 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7610 if (REG_P (rld[r].in)
7611 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7613 else if (REG_P (rld[r].in_reg))
7616 in = XEXP (rld[r].in_reg, 0);
7617 nregno = REGNO (in);
7619 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7620 : hard_regno_nregs[nregno]
7621 [GET_MODE (rld[r].reg_rtx)]);
7623 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7625 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7627 && inherit_piecemeal_p (r, nregno));
7629 if (nregno < FIRST_PSEUDO_REGISTER)
7630 for (k = 1; k < nnr; k++)
7631 reg_last_reload_reg[nregno + k]
7633 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7636 /* Unless we inherited this reload, show we haven't
7637 recently done a store.
7638 Previous stores of inherited auto_inc expressions
7639 also have to be discarded. */
7640 if (! reload_inherited[r]
7641 || (rld[r].out && ! rld[r].out_reg))
7642 spill_reg_store[i] = 0;
7644 for (k = 0; k < nr; k++)
7646 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7647 reg_reloaded_contents[i + k]
7648 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7651 reg_reloaded_insn[i + k] = insn;
7652 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7653 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7654 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7659 /* However, if part of the reload reaches the end, then we must
7660 invalidate the old info for the part that survives to the end. */
7661 else if (part_reaches_end)
7663 for (k = 0; k < nr; k++)
7664 if (reload_reg_reaches_end_p (i + k,
7666 rld[r].when_needed))
7667 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7671 /* The following if-statement was #if 0'd in 1.34 (or before...).
7672 It's reenabled in 1.35 because supposedly nothing else
7673 deals with this problem. */
7675 /* If a register gets output-reloaded from a non-spill register,
7676 that invalidates any previous reloaded copy of it.
7677 But forget_old_reloads_1 won't get to see it, because
7678 it thinks only about the original insn. So invalidate it here.
7679 Also do the same thing for RELOAD_OTHER constraints where the
7680 output is discarded. */
7682 && ((rld[r].out != 0
7683 && (REG_P (rld[r].out)
7684 || (MEM_P (rld[r].out)
7685 && REG_P (rld[r].out_reg))))
7686 || (rld[r].out == 0 && rld[r].out_reg
7687 && REG_P (rld[r].out_reg))))
7689 rtx out = ((rld[r].out && REG_P (rld[r].out))
7690 ? rld[r].out : rld[r].out_reg);
7691 int nregno = REGNO (out);
7693 /* REG_RTX is now set or clobbered by the main instruction.
7694 As the comment above explains, forget_old_reloads_1 only
7695 sees the original instruction, and there is no guarantee
7696 that the original instruction also clobbered REG_RTX.
7697 For example, if find_reloads sees that the input side of
7698 a matched operand pair dies in this instruction, it may
7699 use the input register as the reload register.
7701 Calling forget_old_reloads_1 is a waste of effort if
7702 REG_RTX is also the output register.
7704 If we know that REG_RTX holds the value of a pseudo
7705 register, the code after the call will record that fact. */
7706 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7707 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7709 if (nregno >= FIRST_PSEUDO_REGISTER)
7711 rtx src_reg, store_insn = NULL_RTX;
7713 reg_last_reload_reg[nregno] = 0;
7715 /* If we can find a hard register that is stored, record
7716 the storing insn so that we may delete this insn with
7717 delete_output_reload. */
7718 src_reg = rld[r].reg_rtx;
7720 /* If this is an optional reload, try to find the source reg
7721 from an input reload. */
7724 rtx set = single_set (insn);
7725 if (set && SET_DEST (set) == rld[r].out)
7729 src_reg = SET_SRC (set);
7731 for (k = 0; k < n_reloads; k++)
7733 if (rld[k].in == src_reg)
7735 src_reg = rld[k].reg_rtx;
7742 store_insn = new_spill_reg_store[REGNO (src_reg)];
7743 if (src_reg && REG_P (src_reg)
7744 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7746 int src_regno = REGNO (src_reg);
7747 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7748 /* The place where to find a death note varies with
7749 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7750 necessarily checked exactly in the code that moves
7751 notes, so just check both locations. */
7752 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7753 if (! note && store_insn)
7754 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7757 spill_reg_store[src_regno + nr] = store_insn;
7758 spill_reg_stored_to[src_regno + nr] = out;
7759 reg_reloaded_contents[src_regno + nr] = nregno;
7760 reg_reloaded_insn[src_regno + nr] = store_insn;
7761 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7762 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7763 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7764 GET_MODE (src_reg)))
7765 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7767 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7769 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7771 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7773 reg_last_reload_reg[nregno] = src_reg;
7774 /* We have to set reg_has_output_reload here, or else
7775 forget_old_reloads_1 will clear reg_last_reload_reg
7777 SET_REGNO_REG_SET (®_has_output_reload,
7783 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7785 while (num_regs-- > 0)
7786 reg_last_reload_reg[nregno + num_regs] = 0;
7790 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7793 /* Go through the motions to emit INSN and test if it is strictly valid.
7794 Return the emitted insn if valid, else return NULL. */
7797 emit_insn_if_valid_for_reload (rtx insn)
7799 rtx last = get_last_insn ();
7802 insn = emit_insn (insn);
7803 code = recog_memoized (insn);
7807 extract_insn (insn);
7808 /* We want constrain operands to treat this insn strictly in its
7809 validity determination, i.e., the way it would after reload has
7811 if (constrain_operands (1))
7815 delete_insns_since (last);
7819 /* Emit code to perform a reload from IN (which may be a reload register) to
7820 OUT (which may also be a reload register). IN or OUT is from operand
7821 OPNUM with reload type TYPE.
7823 Returns first insn emitted. */
7826 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7828 rtx last = get_last_insn ();
7831 /* If IN is a paradoxical SUBREG, remove it and try to put the
7832 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7833 if (GET_CODE (in) == SUBREG
7834 && (GET_MODE_SIZE (GET_MODE (in))
7835 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7836 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7837 in = SUBREG_REG (in), out = tem;
7838 else if (GET_CODE (out) == SUBREG
7839 && (GET_MODE_SIZE (GET_MODE (out))
7840 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7841 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7842 out = SUBREG_REG (out), in = tem;
7844 /* How to do this reload can get quite tricky. Normally, we are being
7845 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7846 register that didn't get a hard register. In that case we can just
7847 call emit_move_insn.
7849 We can also be asked to reload a PLUS that adds a register or a MEM to
7850 another register, constant or MEM. This can occur during frame pointer
7851 elimination and while reloading addresses. This case is handled by
7852 trying to emit a single insn to perform the add. If it is not valid,
7853 we use a two insn sequence.
7855 Or we can be asked to reload an unary operand that was a fragment of
7856 an addressing mode, into a register. If it isn't recognized as-is,
7857 we try making the unop operand and the reload-register the same:
7858 (set reg:X (unop:X expr:Y))
7859 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7861 Finally, we could be called to handle an 'o' constraint by putting
7862 an address into a register. In that case, we first try to do this
7863 with a named pattern of "reload_load_address". If no such pattern
7864 exists, we just emit a SET insn and hope for the best (it will normally
7865 be valid on machines that use 'o').
7867 This entire process is made complex because reload will never
7868 process the insns we generate here and so we must ensure that
7869 they will fit their constraints and also by the fact that parts of
7870 IN might be being reloaded separately and replaced with spill registers.
7871 Because of this, we are, in some sense, just guessing the right approach
7872 here. The one listed above seems to work.
7874 ??? At some point, this whole thing needs to be rethought. */
7876 if (GET_CODE (in) == PLUS
7877 && (REG_P (XEXP (in, 0))
7878 || GET_CODE (XEXP (in, 0)) == SUBREG
7879 || MEM_P (XEXP (in, 0)))
7880 && (REG_P (XEXP (in, 1))
7881 || GET_CODE (XEXP (in, 1)) == SUBREG
7882 || CONSTANT_P (XEXP (in, 1))
7883 || MEM_P (XEXP (in, 1))))
7885 /* We need to compute the sum of a register or a MEM and another
7886 register, constant, or MEM, and put it into the reload
7887 register. The best possible way of doing this is if the machine
7888 has a three-operand ADD insn that accepts the required operands.
7890 The simplest approach is to try to generate such an insn and see if it
7891 is recognized and matches its constraints. If so, it can be used.
7893 It might be better not to actually emit the insn unless it is valid,
7894 but we need to pass the insn as an operand to `recog' and
7895 `extract_insn' and it is simpler to emit and then delete the insn if
7896 not valid than to dummy things up. */
7898 rtx op0, op1, tem, insn;
7901 op0 = find_replacement (&XEXP (in, 0));
7902 op1 = find_replacement (&XEXP (in, 1));
7904 /* Since constraint checking is strict, commutativity won't be
7905 checked, so we need to do that here to avoid spurious failure
7906 if the add instruction is two-address and the second operand
7907 of the add is the same as the reload reg, which is frequently
7908 the case. If the insn would be A = B + A, rearrange it so
7909 it will be A = A + B as constrain_operands expects. */
7911 if (REG_P (XEXP (in, 1))
7912 && REGNO (out) == REGNO (XEXP (in, 1)))
7913 tem = op0, op0 = op1, op1 = tem;
7915 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7916 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7918 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7922 /* If that failed, we must use a conservative two-insn sequence.
7924 Use a move to copy one operand into the reload register. Prefer
7925 to reload a constant, MEM or pseudo since the move patterns can
7926 handle an arbitrary operand. If OP1 is not a constant, MEM or
7927 pseudo and OP1 is not a valid operand for an add instruction, then
7930 After reloading one of the operands into the reload register, add
7931 the reload register to the output register.
7933 If there is another way to do this for a specific machine, a
7934 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7937 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7939 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7941 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7942 || (code != CODE_FOR_nothing
7943 && ! ((*insn_data[code].operand[2].predicate)
7944 (op1, insn_data[code].operand[2].mode))))
7945 tem = op0, op0 = op1, op1 = tem;
7947 gen_reload (out, op0, opnum, type);
7949 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7950 This fixes a problem on the 32K where the stack pointer cannot
7951 be used as an operand of an add insn. */
7953 if (rtx_equal_p (op0, op1))
7956 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7959 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7960 set_unique_reg_note (insn, REG_EQUIV, in);
7964 /* If that failed, copy the address register to the reload register.
7965 Then add the constant to the reload register. */
7967 gcc_assert (!reg_overlap_mentioned_p (out, op0));
7968 gen_reload (out, op1, opnum, type);
7969 insn = emit_insn (gen_add2_insn (out, op0));
7970 set_unique_reg_note (insn, REG_EQUIV, in);
7973 #ifdef SECONDARY_MEMORY_NEEDED
7974 /* If we need a memory location to do the move, do it that way. */
7975 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7976 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7977 && (REG_P (out) || GET_CODE (out) == SUBREG)
7978 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7979 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7980 REGNO_REG_CLASS (reg_or_subregno (out)),
7983 /* Get the memory to use and rewrite both registers to its mode. */
7984 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7986 if (GET_MODE (loc) != GET_MODE (out))
7987 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7989 if (GET_MODE (loc) != GET_MODE (in))
7990 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7992 gen_reload (loc, in, opnum, type);
7993 gen_reload (out, loc, opnum, type);
7996 else if (REG_P (out) && UNARY_P (in))
8003 op1 = find_replacement (&XEXP (in, 0));
8004 if (op1 != XEXP (in, 0))
8005 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8007 /* First, try a plain SET. */
8008 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8012 /* If that failed, move the inner operand to the reload
8013 register, and try the same unop with the inner expression
8014 replaced with the reload register. */
8016 if (GET_MODE (op1) != GET_MODE (out))
8017 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8021 gen_reload (out_moded, op1, opnum, type);
8024 = gen_rtx_SET (VOIDmode, out,
8025 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8027 insn = emit_insn_if_valid_for_reload (insn);
8030 set_unique_reg_note (insn, REG_EQUIV, in);
8034 fatal_insn ("Failure trying to reload:", set);
8036 /* If IN is a simple operand, use gen_move_insn. */
8037 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8039 tem = emit_insn (gen_move_insn (out, in));
8040 /* IN may contain a LABEL_REF, if so add a REG_LABEL note. */
8041 mark_jump_label (in, tem, 0);
8044 #ifdef HAVE_reload_load_address
8045 else if (HAVE_reload_load_address)
8046 emit_insn (gen_reload_load_address (out, in));
8049 /* Otherwise, just write (set OUT IN) and hope for the best. */
8051 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8053 /* Return the first insn emitted.
8054 We can not just return get_last_insn, because there may have
8055 been multiple instructions emitted. Also note that gen_move_insn may
8056 emit more than one insn itself, so we can not assume that there is one
8057 insn emitted per emit_insn_before call. */
8059 return last ? NEXT_INSN (last) : get_insns ();
8062 /* Delete a previously made output-reload whose result we now believe
8063 is not needed. First we double-check.
8065 INSN is the insn now being processed.
8066 LAST_RELOAD_REG is the hard register number for which we want to delete
8067 the last output reload.
8068 J is the reload-number that originally used REG. The caller has made
8069 certain that reload J doesn't use REG any longer for input. */
8072 delete_output_reload (rtx insn, int j, int last_reload_reg)
8074 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8075 rtx reg = spill_reg_stored_to[last_reload_reg];
8078 int n_inherited = 0;
8082 /* It is possible that this reload has been only used to set another reload
8083 we eliminated earlier and thus deleted this instruction too. */
8084 if (INSN_DELETED_P (output_reload_insn))
8087 /* Get the raw pseudo-register referred to. */
8089 while (GET_CODE (reg) == SUBREG)
8090 reg = SUBREG_REG (reg);
8091 substed = reg_equiv_memory_loc[REGNO (reg)];
8093 /* This is unsafe if the operand occurs more often in the current
8094 insn than it is inherited. */
8095 for (k = n_reloads - 1; k >= 0; k--)
8097 rtx reg2 = rld[k].in;
8100 if (MEM_P (reg2) || reload_override_in[k])
8101 reg2 = rld[k].in_reg;
8103 if (rld[k].out && ! rld[k].out_reg)
8104 reg2 = XEXP (rld[k].in_reg, 0);
8106 while (GET_CODE (reg2) == SUBREG)
8107 reg2 = SUBREG_REG (reg2);
8108 if (rtx_equal_p (reg2, reg))
8110 if (reload_inherited[k] || reload_override_in[k] || k == j)
8116 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8117 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8118 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8121 n_occurrences += count_occurrences (PATTERN (insn),
8122 eliminate_regs (substed, 0,
8124 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8126 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8127 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8129 if (n_occurrences > n_inherited)
8132 /* If the pseudo-reg we are reloading is no longer referenced
8133 anywhere between the store into it and here,
8134 and we're within the same basic block, then the value can only
8135 pass through the reload reg and end up here.
8136 Otherwise, give up--return. */
8137 for (i1 = NEXT_INSN (output_reload_insn);
8138 i1 != insn; i1 = NEXT_INSN (i1))
8140 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8142 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8143 && reg_mentioned_p (reg, PATTERN (i1)))
8145 /* If this is USE in front of INSN, we only have to check that
8146 there are no more references than accounted for by inheritance. */
8147 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8149 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8150 i1 = NEXT_INSN (i1);
8152 if (n_occurrences <= n_inherited && i1 == insn)
8158 /* We will be deleting the insn. Remove the spill reg information. */
8159 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8161 spill_reg_store[last_reload_reg + k] = 0;
8162 spill_reg_stored_to[last_reload_reg + k] = 0;
8165 /* The caller has already checked that REG dies or is set in INSN.
8166 It has also checked that we are optimizing, and thus some
8167 inaccuracies in the debugging information are acceptable.
8168 So we could just delete output_reload_insn. But in some cases
8169 we can improve the debugging information without sacrificing
8170 optimization - maybe even improving the code: See if the pseudo
8171 reg has been completely replaced with reload regs. If so, delete
8172 the store insn and forget we had a stack slot for the pseudo. */
8173 if (rld[j].out != rld[j].in
8174 && REG_N_DEATHS (REGNO (reg)) == 1
8175 && REG_N_SETS (REGNO (reg)) == 1
8176 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8177 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8181 /* We know that it was used only between here and the beginning of
8182 the current basic block. (We also know that the last use before
8183 INSN was the output reload we are thinking of deleting, but never
8184 mind that.) Search that range; see if any ref remains. */
8185 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8187 rtx set = single_set (i2);
8189 /* Uses which just store in the pseudo don't count,
8190 since if they are the only uses, they are dead. */
8191 if (set != 0 && SET_DEST (set) == reg)
8196 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8197 && reg_mentioned_p (reg, PATTERN (i2)))
8199 /* Some other ref remains; just delete the output reload we
8201 delete_address_reloads (output_reload_insn, insn);
8202 delete_insn (output_reload_insn);
8207 /* Delete the now-dead stores into this pseudo. Note that this
8208 loop also takes care of deleting output_reload_insn. */
8209 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8211 rtx set = single_set (i2);
8213 if (set != 0 && SET_DEST (set) == reg)
8215 delete_address_reloads (i2, insn);
8223 /* For the debugging info, say the pseudo lives in this reload reg. */
8224 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8225 alter_reg (REGNO (reg), -1);
8229 delete_address_reloads (output_reload_insn, insn);
8230 delete_insn (output_reload_insn);
8234 /* We are going to delete DEAD_INSN. Recursively delete loads of
8235 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8236 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8238 delete_address_reloads (rtx dead_insn, rtx current_insn)
8240 rtx set = single_set (dead_insn);
8241 rtx set2, dst, prev, next;
8244 rtx dst = SET_DEST (set);
8246 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8248 /* If we deleted the store from a reloaded post_{in,de}c expression,
8249 we can delete the matching adds. */
8250 prev = PREV_INSN (dead_insn);
8251 next = NEXT_INSN (dead_insn);
8252 if (! prev || ! next)
8254 set = single_set (next);
8255 set2 = single_set (prev);
8257 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8258 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8259 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8261 dst = SET_DEST (set);
8262 if (! rtx_equal_p (dst, SET_DEST (set2))
8263 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8264 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8265 || (INTVAL (XEXP (SET_SRC (set), 1))
8266 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8268 delete_related_insns (prev);
8269 delete_related_insns (next);
8272 /* Subfunction of delete_address_reloads: process registers found in X. */
8274 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8276 rtx prev, set, dst, i2;
8278 enum rtx_code code = GET_CODE (x);
8282 const char *fmt = GET_RTX_FORMAT (code);
8283 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8286 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8287 else if (fmt[i] == 'E')
8289 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8290 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8297 if (spill_reg_order[REGNO (x)] < 0)
8300 /* Scan backwards for the insn that sets x. This might be a way back due
8302 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8304 code = GET_CODE (prev);
8305 if (code == CODE_LABEL || code == JUMP_INSN)
8309 if (reg_set_p (x, PATTERN (prev)))
8311 if (reg_referenced_p (x, PATTERN (prev)))
8314 if (! prev || INSN_UID (prev) < reload_first_uid)
8316 /* Check that PREV only sets the reload register. */
8317 set = single_set (prev);
8320 dst = SET_DEST (set);
8322 || ! rtx_equal_p (dst, x))
8324 if (! reg_set_p (dst, PATTERN (dead_insn)))
8326 /* Check if DST was used in a later insn -
8327 it might have been inherited. */
8328 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8334 if (reg_referenced_p (dst, PATTERN (i2)))
8336 /* If there is a reference to the register in the current insn,
8337 it might be loaded in a non-inherited reload. If no other
8338 reload uses it, that means the register is set before
8340 if (i2 == current_insn)
8342 for (j = n_reloads - 1; j >= 0; j--)
8343 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8344 || reload_override_in[j] == dst)
8346 for (j = n_reloads - 1; j >= 0; j--)
8347 if (rld[j].in && rld[j].reg_rtx == dst)
8356 /* If DST is still live at CURRENT_INSN, check if it is used for
8357 any reload. Note that even if CURRENT_INSN sets DST, we still
8358 have to check the reloads. */
8359 if (i2 == current_insn)
8361 for (j = n_reloads - 1; j >= 0; j--)
8362 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8363 || reload_override_in[j] == dst)
8365 /* ??? We can't finish the loop here, because dst might be
8366 allocated to a pseudo in this block if no reload in this
8367 block needs any of the classes containing DST - see
8368 spill_hard_reg. There is no easy way to tell this, so we
8369 have to scan till the end of the basic block. */
8371 if (reg_set_p (dst, PATTERN (i2)))
8375 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8376 reg_reloaded_contents[REGNO (dst)] = -1;
8380 /* Output reload-insns to reload VALUE into RELOADREG.
8381 VALUE is an autoincrement or autodecrement RTX whose operand
8382 is a register or memory location;
8383 so reloading involves incrementing that location.
8384 IN is either identical to VALUE, or some cheaper place to reload from.
8386 INC_AMOUNT is the number to increment or decrement by (always positive).
8387 This cannot be deduced from VALUE.
8389 Return the instruction that stores into RELOADREG. */
8392 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8394 /* REG or MEM to be copied and incremented. */
8395 rtx incloc = find_replacement (&XEXP (value, 0));
8396 /* Nonzero if increment after copying. */
8397 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8398 || GET_CODE (value) == POST_MODIFY);
8404 rtx real_in = in == value ? incloc : in;
8406 /* No hard register is equivalent to this register after
8407 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8408 we could inc/dec that register as well (maybe even using it for
8409 the source), but I'm not sure it's worth worrying about. */
8411 reg_last_reload_reg[REGNO (incloc)] = 0;
8413 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8415 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8416 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8420 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8421 inc_amount = -inc_amount;
8423 inc = GEN_INT (inc_amount);
8426 /* If this is post-increment, first copy the location to the reload reg. */
8427 if (post && real_in != reloadreg)
8428 emit_insn (gen_move_insn (reloadreg, real_in));
8432 /* See if we can directly increment INCLOC. Use a method similar to
8433 that in gen_reload. */
8435 last = get_last_insn ();
8436 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8437 gen_rtx_PLUS (GET_MODE (incloc),
8440 code = recog_memoized (add_insn);
8443 extract_insn (add_insn);
8444 if (constrain_operands (1))
8446 /* If this is a pre-increment and we have incremented the value
8447 where it lives, copy the incremented value to RELOADREG to
8448 be used as an address. */
8451 emit_insn (gen_move_insn (reloadreg, incloc));
8456 delete_insns_since (last);
8459 /* If couldn't do the increment directly, must increment in RELOADREG.
8460 The way we do this depends on whether this is pre- or post-increment.
8461 For pre-increment, copy INCLOC to the reload register, increment it
8462 there, then save back. */
8466 if (in != reloadreg)
8467 emit_insn (gen_move_insn (reloadreg, real_in));
8468 emit_insn (gen_add2_insn (reloadreg, inc));
8469 store = emit_insn (gen_move_insn (incloc, reloadreg));
8474 Because this might be a jump insn or a compare, and because RELOADREG
8475 may not be available after the insn in an input reload, we must do
8476 the incrementation before the insn being reloaded for.
8478 We have already copied IN to RELOADREG. Increment the copy in
8479 RELOADREG, save that back, then decrement RELOADREG so it has
8480 the original value. */
8482 emit_insn (gen_add2_insn (reloadreg, inc));
8483 store = emit_insn (gen_move_insn (incloc, reloadreg));
8484 if (GET_CODE (inc) == CONST_INT)
8485 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8487 emit_insn (gen_sub2_insn (reloadreg, inc));
8495 add_auto_inc_notes (rtx insn, rtx x)
8497 enum rtx_code code = GET_CODE (x);
8501 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8504 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8508 /* Scan all the operand sub-expressions. */
8509 fmt = GET_RTX_FORMAT (code);
8510 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8513 add_auto_inc_notes (insn, XEXP (x, i));
8514 else if (fmt[i] == 'E')
8515 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8516 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8521 /* Copy EH notes from an insn to its reloads. */
8523 copy_eh_notes (rtx insn, rtx x)
8525 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8528 for (; x != 0; x = NEXT_INSN (x))
8530 if (may_trap_p (PATTERN (x)))
8532 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8538 /* This is used by reload pass, that does emit some instructions after
8539 abnormal calls moving basic block end, but in fact it wants to emit
8540 them on the edge. Looks for abnormal call edges, find backward the
8541 proper call and fix the damage.
8543 Similar handle instructions throwing exceptions internally. */
8545 fixup_abnormal_edges (void)
8547 bool inserted = false;
8555 /* Look for cases we are interested in - calls or instructions causing
8557 FOR_EACH_EDGE (e, ei, bb->succs)
8559 if (e->flags & EDGE_ABNORMAL_CALL)
8561 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8562 == (EDGE_ABNORMAL | EDGE_EH))
8565 if (e && !CALL_P (BB_END (bb))
8566 && !can_throw_internal (BB_END (bb)))
8570 /* Get past the new insns generated. Allow notes, as the insns
8571 may be already deleted. */
8573 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8574 && !can_throw_internal (insn)
8575 && insn != BB_HEAD (bb))
8576 insn = PREV_INSN (insn);
8578 if (CALL_P (insn) || can_throw_internal (insn))
8582 stop = NEXT_INSN (BB_END (bb));
8584 insn = NEXT_INSN (insn);
8586 FOR_EACH_EDGE (e, ei, bb->succs)
8587 if (e->flags & EDGE_FALLTHRU)
8590 while (insn && insn != stop)
8592 next = NEXT_INSN (insn);
8597 /* Sometimes there's still the return value USE.
8598 If it's placed after a trapping call (i.e. that
8599 call is the last insn anyway), we have no fallthru
8600 edge. Simply delete this use and don't try to insert
8601 on the non-existent edge. */
8602 if (GET_CODE (PATTERN (insn)) != USE)
8604 /* We're not deleting it, we're moving it. */
8605 INSN_DELETED_P (insn) = 0;
8606 PREV_INSN (insn) = NULL_RTX;
8607 NEXT_INSN (insn) = NULL_RTX;
8609 insert_insn_on_edge (insn, e);
8613 else if (!BARRIER_P (insn))
8614 set_block_for_insn (insn, NULL);
8619 /* It may be that we don't find any such trapping insn. In this
8620 case we discovered quite late that the insn that had been
8621 marked as can_throw_internal in fact couldn't trap at all.
8622 So we should in fact delete the EH edges out of the block. */
8624 purge_dead_edges (bb);
8628 /* We've possibly turned single trapping insn into multiple ones. */
8629 if (flag_non_call_exceptions)
8632 blocks = sbitmap_alloc (last_basic_block);
8633 sbitmap_ones (blocks);
8634 find_many_sub_basic_blocks (blocks);
8638 commit_edge_insertions ();
8640 #ifdef ENABLE_CHECKING
8641 /* Verify that we didn't turn one trapping insn into many, and that
8642 we found and corrected all of the problems wrt fixups on the
8644 verify_flow_info ();
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