1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
322 insns made by reload. */
323 HOST_WIDE_INT offset; /* Current offset between the two regs. */
324 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
325 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
326 rtx from_rtx; /* REG rtx for the register to be eliminated.
327 We cannot simply compare the number since
328 we might then spuriously replace a hard
329 register corresponding to a pseudo
330 assigned to the reg to be eliminated. */
331 rtx to_rtx; /* REG rtx for the replacement. */
334 static struct elim_table *reg_eliminate = 0;
336 /* This is an intermediate structure to initialize the table. It has
337 exactly the members provided by ELIMINABLE_REGS. */
338 static const struct elim_table_1
342 } reg_eliminate_1[] =
344 /* If a set of eliminable registers was specified, define the table from it.
345 Otherwise, default to the normal case of the frame pointer being
346 replaced by the stack pointer. */
348 #ifdef ELIMINABLE_REGS
351 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
354 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
356 /* Record the number of pending eliminations that have an offset not equal
357 to their initial offset. If nonzero, we use a new copy of each
358 replacement result in any insns encountered. */
359 int num_not_at_initial_offset;
361 /* Count the number of registers that we may be able to eliminate. */
362 static int num_eliminable;
363 /* And the number of registers that are equivalent to a constant that
364 can be eliminated to frame_pointer / arg_pointer + constant. */
365 static int num_eliminable_invariants;
367 /* For each label, we record the offset of each elimination. If we reach
368 a label by more than one path and an offset differs, we cannot do the
369 elimination. This information is indexed by the difference of the
370 number of the label and the first label number. We can't offset the
371 pointer itself as this can cause problems on machines with segmented
372 memory. The first table is an array of flags that records whether we
373 have yet encountered a label and the second table is an array of arrays,
374 one entry in the latter array for each elimination. */
376 static int first_label_num;
377 static char *offsets_known_at;
378 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
380 /* Number of labels in the current function. */
382 static int num_labels;
384 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain *);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain *, int);
389 static void find_reload_regs (struct insn_chain *);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx, enum reg_class);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx, rtx, int);
398 static void check_eliminable_occurrences (rtx);
399 static void elimination_effects (rtx, enum machine_mode);
400 static int eliminate_regs_in_insn (rtx, int);
401 static void update_eliminable_offsets (void);
402 static void mark_not_eliminable (rtx, const_rtx, void *);
403 static void set_initial_elim_offsets (void);
404 static bool verify_initial_elim_offsets (void);
405 static void set_initial_label_offsets (void);
406 static void set_offsets_for_label (rtx);
407 static void init_elim_table (void);
408 static void update_eliminables (HARD_REG_SET *);
409 static void spill_hard_reg (unsigned int, int);
410 static int finish_spills (int);
411 static void scan_paradoxical_subregs (rtx);
412 static void count_pseudo (int);
413 static void order_regs_for_reload (struct insn_chain *);
414 static void reload_as_needed (int);
415 static void forget_old_reloads_1 (rtx, const_rtx, void *);
416 static void forget_marked_reloads (regset);
417 static int reload_reg_class_lower (const void *, const void *);
418 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
420 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
422 static int reload_reg_free_p (unsigned int, int, enum reload_type);
423 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
425 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
427 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
428 static int allocate_reload_reg (struct insn_chain *, int, int);
429 static int conflicts_with_override (rtx);
430 static void failed_reload (rtx, int);
431 static int set_reload_reg (int, int);
432 static void choose_reload_regs_init (struct insn_chain *, rtx *);
433 static void choose_reload_regs (struct insn_chain *);
434 static void merge_assigned_reloads (rtx);
435 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
437 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
439 static void do_input_reload (struct insn_chain *, struct reload *, int);
440 static void do_output_reload (struct insn_chain *, struct reload *, int);
441 static void emit_reload_insns (struct insn_chain *);
442 static void delete_output_reload (rtx, int, int, rtx);
443 static void delete_address_reloads (rtx, rtx);
444 static void delete_address_reloads_1 (rtx, rtx, rtx);
445 static rtx inc_for_reload (rtx, rtx, rtx, int);
447 static void add_auto_inc_notes (rtx, rtx);
449 static void copy_eh_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert ((flag_ira && optimize) || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
904 if (flag_ira && optimize)
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
1002 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1004 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1005 else if (CONSTANT_P (XEXP (x, 0))
1006 || (REG_P (XEXP (x, 0))
1007 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1008 || (GET_CODE (XEXP (x, 0)) == PLUS
1009 && REG_P (XEXP (XEXP (x, 0), 0))
1010 && (REGNO (XEXP (XEXP (x, 0), 0))
1011 < FIRST_PSEUDO_REGISTER)
1012 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1013 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1016 /* Make a new stack slot. Then indicate that something
1017 changed so we go back and recompute offsets for
1018 eliminable registers because the allocation of memory
1019 below might change some offset. reg_equiv_{mem,address}
1020 will be set up for this pseudo on the next pass around
1022 reg_equiv_memory_loc[i] = 0;
1023 reg_equiv_init[i] = 0;
1024 alter_reg (i, -1, true);
1028 if (caller_save_needed)
1029 setup_save_areas ();
1031 /* If we allocated another stack slot, redo elimination bookkeeping. */
1032 if (starting_frame_size != get_frame_size ())
1034 if (starting_frame_size && crtl->stack_alignment_needed)
1036 /* If we have a stack frame, we must align it now. The
1037 stack size may be a part of the offset computation for
1038 register elimination. So if this changes the stack size,
1039 then repeat the elimination bookkeeping. We don't
1040 realign when there is no stack, as that will cause a
1041 stack frame when none is needed should
1042 STARTING_FRAME_OFFSET not be already aligned to
1044 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1045 if (starting_frame_size != get_frame_size ())
1049 if (caller_save_needed)
1051 save_call_clobbered_regs ();
1052 /* That might have allocated new insn_chain structures. */
1053 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1056 calculate_needs_all_insns (global);
1058 if (! flag_ira || ! optimize)
1059 /* Don't do it for IRA. We need this info because we don't
1060 change live_throughout and dead_or_set for chains when IRA
1062 CLEAR_REG_SET (&spilled_pseudos);
1066 something_changed = 0;
1068 /* If we allocated any new memory locations, make another pass
1069 since it might have changed elimination offsets. */
1070 if (starting_frame_size != get_frame_size ())
1071 something_changed = 1;
1073 /* Even if the frame size remained the same, we might still have
1074 changed elimination offsets, e.g. if find_reloads called
1075 force_const_mem requiring the back end to allocate a constant
1076 pool base register that needs to be saved on the stack. */
1077 else if (!verify_initial_elim_offsets ())
1078 something_changed = 1;
1081 HARD_REG_SET to_spill;
1082 CLEAR_HARD_REG_SET (to_spill);
1083 update_eliminables (&to_spill);
1084 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1086 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1087 if (TEST_HARD_REG_BIT (to_spill, i))
1089 spill_hard_reg (i, 1);
1092 /* Regardless of the state of spills, if we previously had
1093 a register that we thought we could eliminate, but now can
1094 not eliminate, we must run another pass.
1096 Consider pseudos which have an entry in reg_equiv_* which
1097 reference an eliminable register. We must make another pass
1098 to update reg_equiv_* so that we do not substitute in the
1099 old value from when we thought the elimination could be
1101 something_changed = 1;
1105 select_reload_regs ();
1109 if (insns_need_reload != 0 || did_spill)
1110 something_changed |= finish_spills (global);
1112 if (! something_changed)
1115 if (caller_save_needed)
1116 delete_caller_save_insns ();
1118 obstack_free (&reload_obstack, reload_firstobj);
1121 /* If global-alloc was run, notify it of any register eliminations we have
1124 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1125 if (ep->can_eliminate)
1126 mark_elimination (ep->from, ep->to);
1128 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1129 If that insn didn't set the register (i.e., it copied the register to
1130 memory), just delete that insn instead of the equivalencing insn plus
1131 anything now dead. If we call delete_dead_insn on that insn, we may
1132 delete the insn that actually sets the register if the register dies
1133 there and that is incorrect. */
1135 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1137 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1140 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1142 rtx equiv_insn = XEXP (list, 0);
1144 /* If we already deleted the insn or if it may trap, we can't
1145 delete it. The latter case shouldn't happen, but can
1146 if an insn has a variable address, gets a REG_EH_REGION
1147 note added to it, and then gets converted into a load
1148 from a constant address. */
1149 if (NOTE_P (equiv_insn)
1150 || can_throw_internal (equiv_insn))
1152 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1153 delete_dead_insn (equiv_insn);
1155 SET_INSN_DELETED (equiv_insn);
1160 /* Use the reload registers where necessary
1161 by generating move instructions to move the must-be-register
1162 values into or out of the reload registers. */
1164 if (insns_need_reload != 0 || something_needs_elimination
1165 || something_needs_operands_changed)
1167 HOST_WIDE_INT old_frame_size = get_frame_size ();
1169 reload_as_needed (global);
1171 gcc_assert (old_frame_size == get_frame_size ());
1173 gcc_assert (verify_initial_elim_offsets ());
1176 /* If we were able to eliminate the frame pointer, show that it is no
1177 longer live at the start of any basic block. If it ls live by
1178 virtue of being in a pseudo, that pseudo will be marked live
1179 and hence the frame pointer will be known to be live via that
1182 if (! frame_pointer_needed)
1184 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1186 /* Come here (with failure set nonzero) if we can't get enough spill
1190 CLEAR_REG_SET (&changed_allocation_pseudos);
1191 CLEAR_REG_SET (&spilled_pseudos);
1192 reload_in_progress = 0;
1194 /* Now eliminate all pseudo regs by modifying them into
1195 their equivalent memory references.
1196 The REG-rtx's for the pseudos are modified in place,
1197 so all insns that used to refer to them now refer to memory.
1199 For a reg that has a reg_equiv_address, all those insns
1200 were changed by reloading so that no insns refer to it any longer;
1201 but the DECL_RTL of a variable decl may refer to it,
1202 and if so this causes the debugging info to mention the variable. */
1204 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1208 if (reg_equiv_mem[i])
1209 addr = XEXP (reg_equiv_mem[i], 0);
1211 if (reg_equiv_address[i])
1212 addr = reg_equiv_address[i];
1216 if (reg_renumber[i] < 0)
1218 rtx reg = regno_reg_rtx[i];
1220 REG_USERVAR_P (reg) = 0;
1221 PUT_CODE (reg, MEM);
1222 XEXP (reg, 0) = addr;
1223 if (reg_equiv_memory_loc[i])
1224 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1227 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1228 MEM_ATTRS (reg) = 0;
1230 MEM_NOTRAP_P (reg) = 1;
1232 else if (reg_equiv_mem[i])
1233 XEXP (reg_equiv_mem[i], 0) = addr;
1237 /* We must set reload_completed now since the cleanup_subreg_operands call
1238 below will re-recognize each insn and reload may have generated insns
1239 which are only valid during and after reload. */
1240 reload_completed = 1;
1242 /* Make a pass over all the insns and delete all USEs which we inserted
1243 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1244 notes. Delete all CLOBBER insns, except those that refer to the return
1245 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1246 from misarranging variable-array code, and simplify (subreg (reg))
1247 operands. Strip and regenerate REG_INC notes that may have been moved
1250 for (insn = first; insn; insn = NEXT_INSN (insn))
1256 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1257 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1259 if ((GET_CODE (PATTERN (insn)) == USE
1260 /* We mark with QImode USEs introduced by reload itself. */
1261 && (GET_MODE (insn) == QImode
1262 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1263 || (GET_CODE (PATTERN (insn)) == CLOBBER
1264 && (!MEM_P (XEXP (PATTERN (insn), 0))
1265 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1266 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1267 && XEXP (XEXP (PATTERN (insn), 0), 0)
1268 != stack_pointer_rtx))
1269 && (!REG_P (XEXP (PATTERN (insn), 0))
1270 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1276 /* Some CLOBBERs may survive until here and still reference unassigned
1277 pseudos with const equivalent, which may in turn cause ICE in later
1278 passes if the reference remains in place. */
1279 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1280 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1281 VOIDmode, PATTERN (insn));
1283 /* Discard obvious no-ops, even without -O. This optimization
1284 is fast and doesn't interfere with debugging. */
1285 if (NONJUMP_INSN_P (insn)
1286 && GET_CODE (PATTERN (insn)) == SET
1287 && REG_P (SET_SRC (PATTERN (insn)))
1288 && REG_P (SET_DEST (PATTERN (insn)))
1289 && (REGNO (SET_SRC (PATTERN (insn)))
1290 == REGNO (SET_DEST (PATTERN (insn)))))
1296 pnote = ®_NOTES (insn);
1299 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1300 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1301 || REG_NOTE_KIND (*pnote) == REG_INC)
1302 *pnote = XEXP (*pnote, 1);
1304 pnote = &XEXP (*pnote, 1);
1308 add_auto_inc_notes (insn, PATTERN (insn));
1311 /* Simplify (subreg (reg)) if it appears as an operand. */
1312 cleanup_subreg_operands (insn);
1314 /* Clean up invalid ASMs so that they don't confuse later passes.
1316 if (asm_noperands (PATTERN (insn)) >= 0)
1318 extract_insn (insn);
1319 if (!constrain_operands (1))
1321 error_for_asm (insn,
1322 "%<asm%> operand has impossible constraints");
1329 /* If we are doing generic stack checking, give a warning if this
1330 function's frame size is larger than we expect. */
1331 if (flag_stack_check == GENERIC_STACK_CHECK)
1333 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1334 static int verbose_warned = 0;
1336 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1337 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1338 size += UNITS_PER_WORD;
1340 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1342 warning (0, "frame size too large for reliable stack checking");
1343 if (! verbose_warned)
1345 warning (0, "try reducing the number of local variables");
1351 /* Indicate that we no longer have known memory locations or constants. */
1352 if (reg_equiv_constant)
1353 free (reg_equiv_constant);
1354 if (reg_equiv_invariant)
1355 free (reg_equiv_invariant);
1356 reg_equiv_constant = 0;
1357 reg_equiv_invariant = 0;
1358 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1359 reg_equiv_memory_loc = 0;
1361 free (temp_pseudo_reg_arr);
1363 if (offsets_known_at)
1364 free (offsets_known_at);
1368 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1369 if (reg_equiv_alt_mem_list[i])
1370 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1371 free (reg_equiv_alt_mem_list);
1373 free (reg_equiv_mem);
1375 free (reg_equiv_address);
1376 free (reg_max_ref_width);
1377 free (reg_old_renumber);
1378 free (pseudo_previous_regs);
1379 free (pseudo_forbidden_regs);
1381 CLEAR_HARD_REG_SET (used_spill_regs);
1382 for (i = 0; i < n_spills; i++)
1383 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1385 /* Free all the insn_chain structures at once. */
1386 obstack_free (&reload_obstack, reload_startobj);
1387 unused_insn_chains = 0;
1388 fixup_abnormal_edges ();
1390 /* Replacing pseudos with their memory equivalents might have
1391 created shared rtx. Subsequent passes would get confused
1392 by this, so unshare everything here. */
1393 unshare_all_rtl_again (first);
1395 #ifdef STACK_BOUNDARY
1396 /* init_emit has set the alignment of the hard frame pointer
1397 to STACK_BOUNDARY. It is very likely no longer valid if
1398 the hard frame pointer was used for register allocation. */
1399 if (!frame_pointer_needed)
1400 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1406 /* Yet another special case. Unfortunately, reg-stack forces people to
1407 write incorrect clobbers in asm statements. These clobbers must not
1408 cause the register to appear in bad_spill_regs, otherwise we'll call
1409 fatal_insn later. We clear the corresponding regnos in the live
1410 register sets to avoid this.
1411 The whole thing is rather sick, I'm afraid. */
1414 maybe_fix_stack_asms (void)
1417 const char *constraints[MAX_RECOG_OPERANDS];
1418 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1419 struct insn_chain *chain;
1421 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1424 HARD_REG_SET clobbered, allowed;
1427 if (! INSN_P (chain->insn)
1428 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1430 pat = PATTERN (chain->insn);
1431 if (GET_CODE (pat) != PARALLEL)
1434 CLEAR_HARD_REG_SET (clobbered);
1435 CLEAR_HARD_REG_SET (allowed);
1437 /* First, make a mask of all stack regs that are clobbered. */
1438 for (i = 0; i < XVECLEN (pat, 0); i++)
1440 rtx t = XVECEXP (pat, 0, i);
1441 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1442 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1445 /* Get the operand values and constraints out of the insn. */
1446 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1447 constraints, operand_mode, NULL);
1449 /* For every operand, see what registers are allowed. */
1450 for (i = 0; i < noperands; i++)
1452 const char *p = constraints[i];
1453 /* For every alternative, we compute the class of registers allowed
1454 for reloading in CLS, and merge its contents into the reg set
1456 int cls = (int) NO_REGS;
1462 if (c == '\0' || c == ',' || c == '#')
1464 /* End of one alternative - mark the regs in the current
1465 class, and reset the class. */
1466 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1472 } while (c != '\0' && c != ',');
1480 case '=': case '+': case '*': case '%': case '?': case '!':
1481 case '0': case '1': case '2': case '3': case '4': case '<':
1482 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1483 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1484 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1485 case TARGET_MEM_CONSTRAINT:
1489 cls = (int) reg_class_subunion[cls]
1490 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1495 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1499 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1500 cls = (int) reg_class_subunion[cls]
1501 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1503 cls = (int) reg_class_subunion[cls]
1504 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1506 p += CONSTRAINT_LEN (c, p);
1509 /* Those of the registers which are clobbered, but allowed by the
1510 constraints, must be usable as reload registers. So clear them
1511 out of the life information. */
1512 AND_HARD_REG_SET (allowed, clobbered);
1513 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1514 if (TEST_HARD_REG_BIT (allowed, i))
1516 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1517 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1524 /* Copy the global variables n_reloads and rld into the corresponding elts
1527 copy_reloads (struct insn_chain *chain)
1529 chain->n_reloads = n_reloads;
1530 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1531 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1532 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1535 /* Walk the chain of insns, and determine for each whether it needs reloads
1536 and/or eliminations. Build the corresponding insns_need_reload list, and
1537 set something_needs_elimination as appropriate. */
1539 calculate_needs_all_insns (int global)
1541 struct insn_chain **pprev_reload = &insns_need_reload;
1542 struct insn_chain *chain, *next = 0;
1544 something_needs_elimination = 0;
1546 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1547 for (chain = reload_insn_chain; chain != 0; chain = next)
1549 rtx insn = chain->insn;
1553 /* Clear out the shortcuts. */
1554 chain->n_reloads = 0;
1555 chain->need_elim = 0;
1556 chain->need_reload = 0;
1557 chain->need_operand_change = 0;
1559 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1560 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1561 what effects this has on the known offsets at labels. */
1563 if (LABEL_P (insn) || JUMP_P (insn)
1564 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1565 set_label_offsets (insn, insn, 0);
1569 rtx old_body = PATTERN (insn);
1570 int old_code = INSN_CODE (insn);
1571 rtx old_notes = REG_NOTES (insn);
1572 int did_elimination = 0;
1573 int operands_changed = 0;
1574 rtx set = single_set (insn);
1576 /* Skip insns that only set an equivalence. */
1577 if (set && REG_P (SET_DEST (set))
1578 && reg_renumber[REGNO (SET_DEST (set))] < 0
1579 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1580 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1581 && reg_equiv_init[REGNO (SET_DEST (set))])
1584 /* If needed, eliminate any eliminable registers. */
1585 if (num_eliminable || num_eliminable_invariants)
1586 did_elimination = eliminate_regs_in_insn (insn, 0);
1588 /* Analyze the instruction. */
1589 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1590 global, spill_reg_order);
1592 /* If a no-op set needs more than one reload, this is likely
1593 to be something that needs input address reloads. We
1594 can't get rid of this cleanly later, and it is of no use
1595 anyway, so discard it now.
1596 We only do this when expensive_optimizations is enabled,
1597 since this complements reload inheritance / output
1598 reload deletion, and it can make debugging harder. */
1599 if (flag_expensive_optimizations && n_reloads > 1)
1601 rtx set = single_set (insn);
1604 ((SET_SRC (set) == SET_DEST (set)
1605 && REG_P (SET_SRC (set))
1606 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1607 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1608 && reg_renumber[REGNO (SET_SRC (set))] < 0
1609 && reg_renumber[REGNO (SET_DEST (set))] < 0
1610 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1611 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1612 && rtx_equal_p (reg_equiv_memory_loc
1613 [REGNO (SET_SRC (set))],
1614 reg_equiv_memory_loc
1615 [REGNO (SET_DEST (set))]))))
1617 if (flag_ira && optimize)
1618 /* Inform IRA about the insn deletion. */
1619 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1620 REGNO (SET_SRC (set)));
1622 /* Delete it from the reload chain. */
1624 chain->prev->next = next;
1626 reload_insn_chain = next;
1628 next->prev = chain->prev;
1629 chain->next = unused_insn_chains;
1630 unused_insn_chains = chain;
1635 update_eliminable_offsets ();
1637 /* Remember for later shortcuts which insns had any reloads or
1638 register eliminations. */
1639 chain->need_elim = did_elimination;
1640 chain->need_reload = n_reloads > 0;
1641 chain->need_operand_change = operands_changed;
1643 /* Discard any register replacements done. */
1644 if (did_elimination)
1646 obstack_free (&reload_obstack, reload_insn_firstobj);
1647 PATTERN (insn) = old_body;
1648 INSN_CODE (insn) = old_code;
1649 REG_NOTES (insn) = old_notes;
1650 something_needs_elimination = 1;
1653 something_needs_operands_changed |= operands_changed;
1657 copy_reloads (chain);
1658 *pprev_reload = chain;
1659 pprev_reload = &chain->next_need_reload;
1666 /* Comparison function for qsort to decide which of two reloads
1667 should be handled first. *P1 and *P2 are the reload numbers. */
1670 reload_reg_class_lower (const void *r1p, const void *r2p)
1672 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1675 /* Consider required reloads before optional ones. */
1676 t = rld[r1].optional - rld[r2].optional;
1680 /* Count all solitary classes before non-solitary ones. */
1681 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1682 - (reg_class_size[(int) rld[r1].rclass] == 1));
1686 /* Aside from solitaires, consider all multi-reg groups first. */
1687 t = rld[r2].nregs - rld[r1].nregs;
1691 /* Consider reloads in order of increasing reg-class number. */
1692 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1696 /* If reloads are equally urgent, sort by reload number,
1697 so that the results of qsort leave nothing to chance. */
1701 /* The cost of spilling each hard reg. */
1702 static int spill_cost[FIRST_PSEUDO_REGISTER];
1704 /* When spilling multiple hard registers, we use SPILL_COST for the first
1705 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1706 only the first hard reg for a multi-reg pseudo. */
1707 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1709 /* Map of hard regno to pseudo regno currently occupying the hard
1711 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1713 /* Update the spill cost arrays, considering that pseudo REG is live. */
1716 count_pseudo (int reg)
1718 int freq = REG_FREQ (reg);
1719 int r = reg_renumber[reg];
1722 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1723 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1724 /* Ignore spilled pseudo-registers which can be here only if IRA
1726 || (flag_ira && optimize && r < 0))
1729 SET_REGNO_REG_SET (&pseudos_counted, reg);
1731 gcc_assert (r >= 0);
1733 spill_add_cost[r] += freq;
1734 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1737 hard_regno_to_pseudo_regno[r + nregs] = reg;
1738 spill_cost[r + nregs] += freq;
1742 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1743 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1746 order_regs_for_reload (struct insn_chain *chain)
1749 HARD_REG_SET used_by_pseudos;
1750 HARD_REG_SET used_by_pseudos2;
1751 reg_set_iterator rsi;
1753 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1755 memset (spill_cost, 0, sizeof spill_cost);
1756 memset (spill_add_cost, 0, sizeof spill_add_cost);
1757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1758 hard_regno_to_pseudo_regno[i] = -1;
1760 /* Count number of uses of each hard reg by pseudo regs allocated to it
1761 and then order them by decreasing use. First exclude hard registers
1762 that are live in or across this insn. */
1764 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1765 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1766 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1767 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1769 /* Now find out which pseudos are allocated to it, and update
1771 CLEAR_REG_SET (&pseudos_counted);
1773 EXECUTE_IF_SET_IN_REG_SET
1774 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1778 EXECUTE_IF_SET_IN_REG_SET
1779 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1783 CLEAR_REG_SET (&pseudos_counted);
1786 /* Vector of reload-numbers showing the order in which the reloads should
1788 static short reload_order[MAX_RELOADS];
1790 /* This is used to keep track of the spill regs used in one insn. */
1791 static HARD_REG_SET used_spill_regs_local;
1793 /* We decided to spill hard register SPILLED, which has a size of
1794 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1795 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1796 update SPILL_COST/SPILL_ADD_COST. */
1799 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1801 int freq = REG_FREQ (reg);
1802 int r = reg_renumber[reg];
1803 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1805 /* Ignore spilled pseudo-registers which can be here only if IRA is
1807 if ((flag_ira && optimize && r < 0)
1808 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1809 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1812 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1814 spill_add_cost[r] -= freq;
1817 hard_regno_to_pseudo_regno[r + nregs] = -1;
1818 spill_cost[r + nregs] -= freq;
1822 /* Find reload register to use for reload number ORDER. */
1825 find_reg (struct insn_chain *chain, int order)
1827 int rnum = reload_order[order];
1828 struct reload *rl = rld + rnum;
1829 int best_cost = INT_MAX;
1831 unsigned int i, j, n;
1833 HARD_REG_SET not_usable;
1834 HARD_REG_SET used_by_other_reload;
1835 reg_set_iterator rsi;
1836 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1837 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1839 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1840 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1841 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1843 CLEAR_HARD_REG_SET (used_by_other_reload);
1844 for (k = 0; k < order; k++)
1846 int other = reload_order[k];
1848 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1849 for (j = 0; j < rld[other].nregs; j++)
1850 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1853 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1855 #ifdef REG_ALLOC_ORDER
1856 unsigned int regno = reg_alloc_order[i];
1858 unsigned int regno = i;
1861 if (! TEST_HARD_REG_BIT (not_usable, regno)
1862 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1863 && HARD_REGNO_MODE_OK (regno, rl->mode))
1865 int this_cost = spill_cost[regno];
1867 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1869 for (j = 1; j < this_nregs; j++)
1871 this_cost += spill_add_cost[regno + j];
1872 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1873 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1879 if (flag_ira && optimize)
1881 /* Ask IRA to find a better pseudo-register for
1883 for (n = j = 0; j < this_nregs; j++)
1885 int r = hard_regno_to_pseudo_regno[regno + j];
1889 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1890 regno_pseudo_regs[n++] = r;
1892 regno_pseudo_regs[n++] = -1;
1894 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1895 best_regno_pseudo_regs,
1902 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1903 if (regno_pseudo_regs[j] < 0)
1910 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1912 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1914 if (this_cost < best_cost
1915 /* Among registers with equal cost, prefer caller-saved ones, or
1916 use REG_ALLOC_ORDER if it is defined. */
1917 || (this_cost == best_cost
1918 #ifdef REG_ALLOC_ORDER
1919 && (inv_reg_alloc_order[regno]
1920 < inv_reg_alloc_order[best_reg])
1922 && call_used_regs[regno]
1923 && ! call_used_regs[best_reg]
1928 best_cost = this_cost;
1936 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1938 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1939 rl->regno = best_reg;
1941 EXECUTE_IF_SET_IN_REG_SET
1942 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1944 count_spilled_pseudo (best_reg, rl->nregs, j);
1947 EXECUTE_IF_SET_IN_REG_SET
1948 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1950 count_spilled_pseudo (best_reg, rl->nregs, j);
1953 for (i = 0; i < rl->nregs; i++)
1955 gcc_assert (spill_cost[best_reg + i] == 0);
1956 gcc_assert (spill_add_cost[best_reg + i] == 0);
1957 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1958 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1963 /* Find more reload regs to satisfy the remaining need of an insn, which
1965 Do it by ascending class number, since otherwise a reg
1966 might be spilled for a big class and might fail to count
1967 for a smaller class even though it belongs to that class. */
1970 find_reload_regs (struct insn_chain *chain)
1974 /* In order to be certain of getting the registers we need,
1975 we must sort the reloads into order of increasing register class.
1976 Then our grabbing of reload registers will parallel the process
1977 that provided the reload registers. */
1978 for (i = 0; i < chain->n_reloads; i++)
1980 /* Show whether this reload already has a hard reg. */
1981 if (chain->rld[i].reg_rtx)
1983 int regno = REGNO (chain->rld[i].reg_rtx);
1984 chain->rld[i].regno = regno;
1986 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1989 chain->rld[i].regno = -1;
1990 reload_order[i] = i;
1993 n_reloads = chain->n_reloads;
1994 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1996 CLEAR_HARD_REG_SET (used_spill_regs_local);
1999 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2001 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2003 /* Compute the order of preference for hard registers to spill. */
2005 order_regs_for_reload (chain);
2007 for (i = 0; i < n_reloads; i++)
2009 int r = reload_order[i];
2011 /* Ignore reloads that got marked inoperative. */
2012 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2013 && ! rld[r].optional
2014 && rld[r].regno == -1)
2015 if (! find_reg (chain, i))
2018 fprintf (dump_file, "reload failure for reload %d\n", r);
2019 spill_failure (chain->insn, rld[r].rclass);
2025 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2026 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2028 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2032 select_reload_regs (void)
2034 struct insn_chain *chain;
2036 /* Try to satisfy the needs for each insn. */
2037 for (chain = insns_need_reload; chain != 0;
2038 chain = chain->next_need_reload)
2039 find_reload_regs (chain);
2042 /* Delete all insns that were inserted by emit_caller_save_insns during
2045 delete_caller_save_insns (void)
2047 struct insn_chain *c = reload_insn_chain;
2051 while (c != 0 && c->is_caller_save_insn)
2053 struct insn_chain *next = c->next;
2056 if (c == reload_insn_chain)
2057 reload_insn_chain = next;
2061 next->prev = c->prev;
2063 c->prev->next = next;
2064 c->next = unused_insn_chains;
2065 unused_insn_chains = c;
2073 /* Handle the failure to find a register to spill.
2074 INSN should be one of the insns which needed this particular spill reg. */
2077 spill_failure (rtx insn, enum reg_class rclass)
2079 if (asm_noperands (PATTERN (insn)) >= 0)
2080 error_for_asm (insn, "can't find a register in class %qs while "
2081 "reloading %<asm%>",
2082 reg_class_names[rclass]);
2085 error ("unable to find a register to spill in class %qs",
2086 reg_class_names[rclass]);
2090 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2091 debug_reload_to_stream (dump_file);
2093 fatal_insn ("this is the insn:", insn);
2097 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2098 data that is dead in INSN. */
2101 delete_dead_insn (rtx insn)
2103 rtx prev = prev_real_insn (insn);
2106 /* If the previous insn sets a register that dies in our insn, delete it
2108 if (prev && GET_CODE (PATTERN (prev)) == SET
2109 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2110 && reg_mentioned_p (prev_dest, PATTERN (insn))
2111 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2112 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2113 delete_dead_insn (prev);
2115 SET_INSN_DELETED (insn);
2118 /* Modify the home of pseudo-reg I.
2119 The new home is present in reg_renumber[I].
2121 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2122 or it may be -1, meaning there is none or it is not relevant.
2123 This is used so that all pseudos spilled from a given hard reg
2124 can share one stack slot. */
2127 alter_reg (int i, int from_reg, bool dont_share_p)
2129 /* When outputting an inline function, this can happen
2130 for a reg that isn't actually used. */
2131 if (regno_reg_rtx[i] == 0)
2134 /* If the reg got changed to a MEM at rtl-generation time,
2136 if (!REG_P (regno_reg_rtx[i]))
2139 /* Modify the reg-rtx to contain the new hard reg
2140 number or else to contain its pseudo reg number. */
2141 SET_REGNO (regno_reg_rtx[i],
2142 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2144 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2145 allocate a stack slot for it. */
2147 if (reg_renumber[i] < 0
2148 && REG_N_REFS (i) > 0
2149 && reg_equiv_constant[i] == 0
2150 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2151 && reg_equiv_memory_loc[i] == 0)
2154 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2155 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2156 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2157 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2158 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2160 bool shared_p = false;
2162 if (flag_ira && optimize)
2163 /* Mark the spill for IRA. */
2164 SET_REGNO_REG_SET (&spilled_pseudos, i);
2165 x = (dont_share_p || ! flag_ira || ! optimize
2166 ? NULL_RTX : ira_reuse_stack_slot (i, inherent_size, total_size));
2169 /* Each pseudo reg has an inherent size which comes from its own mode,
2170 and a total size which provides room for paradoxical subregs
2171 which refer to the pseudo reg in wider modes.
2173 We can use a slot already allocated if it provides both
2174 enough inherent space and enough total space.
2175 Otherwise, we allocate a new slot, making sure that it has no less
2176 inherent space, and no less total space, then the previous slot. */
2177 else if (from_reg == -1 || (! dont_share_p && flag_ira && optimize))
2180 alias_set_type alias_set = new_alias_set ();
2182 /* No known place to spill from => no slot to reuse. */
2183 x = assign_stack_local (mode, total_size,
2184 min_align > inherent_align
2185 || total_size > inherent_size ? -1 : 0);
2189 if (BYTES_BIG_ENDIAN)
2191 /* Cancel the big-endian correction done in assign_stack_local.
2192 Get the address of the beginning of the slot.
2193 This is so we can do a big-endian correction unconditionally
2195 adjust = inherent_size - total_size;
2198 = adjust_address_nv (x, mode_for_size (total_size
2204 /* Nothing can alias this slot except this pseudo. */
2205 set_mem_alias_set (x, alias_set);
2206 dse_record_singleton_alias_set (alias_set, mode);
2208 if (! dont_share_p && flag_ira && optimize)
2209 /* Inform IRA about allocation a new stack slot. */
2210 ira_mark_new_stack_slot (stack_slot, i, total_size);
2213 /* Reuse a stack slot if possible. */
2214 else if (spill_stack_slot[from_reg] != 0
2215 && spill_stack_slot_width[from_reg] >= total_size
2216 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2218 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2219 x = spill_stack_slot[from_reg];
2220 /* Allocate a bigger slot. */
2223 /* Compute maximum size needed, both for inherent size
2224 and for total size. */
2227 if (spill_stack_slot[from_reg])
2229 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2231 mode = GET_MODE (spill_stack_slot[from_reg]);
2232 if (spill_stack_slot_width[from_reg] > total_size)
2233 total_size = spill_stack_slot_width[from_reg];
2234 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2235 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2238 /* Make a slot with that size. */
2239 x = assign_stack_local (mode, total_size,
2240 min_align > inherent_align
2241 || total_size > inherent_size ? -1 : 0);
2244 /* All pseudos mapped to this slot can alias each other. */
2245 if (spill_stack_slot[from_reg])
2247 alias_set_type alias_set
2248 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2249 set_mem_alias_set (x, alias_set);
2250 dse_invalidate_singleton_alias_set (alias_set);
2254 alias_set_type alias_set = new_alias_set ();
2255 set_mem_alias_set (x, alias_set);
2256 dse_record_singleton_alias_set (alias_set, mode);
2259 if (BYTES_BIG_ENDIAN)
2261 /* Cancel the big-endian correction done in assign_stack_local.
2262 Get the address of the beginning of the slot.
2263 This is so we can do a big-endian correction unconditionally
2265 adjust = GET_MODE_SIZE (mode) - total_size;
2268 = adjust_address_nv (x, mode_for_size (total_size
2274 spill_stack_slot[from_reg] = stack_slot;
2275 spill_stack_slot_width[from_reg] = total_size;
2278 /* On a big endian machine, the "address" of the slot
2279 is the address of the low part that fits its inherent mode. */
2280 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2281 adjust += (total_size - inherent_size);
2283 /* If we have any adjustment to make, or if the stack slot is the
2284 wrong mode, make a new stack slot. */
2285 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2287 /* If we have a decl for the original register, set it for the
2288 memory. If this is a shared MEM, make a copy. */
2292 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2294 else if (REG_EXPR (regno_reg_rtx[i])
2295 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2297 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2299 /* We can do this only for the DECLs home pseudo, not for
2300 any copies of it, since otherwise when the stack slot
2301 is reused, nonoverlapping_memrefs_p might think they
2303 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2305 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2308 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2312 /* Save the stack slot for later. */
2313 reg_equiv_memory_loc[i] = x;
2317 /* Mark the slots in regs_ever_live for the hard regs used by
2318 pseudo-reg number REGNO, accessed in MODE. */
2321 mark_home_live_1 (int regno, enum machine_mode mode)
2325 i = reg_renumber[regno];
2328 lim = end_hard_regno (mode, i);
2330 df_set_regs_ever_live(i++, true);
2333 /* Mark the slots in regs_ever_live for the hard regs
2334 used by pseudo-reg number REGNO. */
2337 mark_home_live (int regno)
2339 if (reg_renumber[regno] >= 0)
2340 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2343 /* This function handles the tracking of elimination offsets around branches.
2345 X is a piece of RTL being scanned.
2347 INSN is the insn that it came from, if any.
2349 INITIAL_P is nonzero if we are to set the offset to be the initial
2350 offset and zero if we are setting the offset of the label to be the
2354 set_label_offsets (rtx x, rtx insn, int initial_p)
2356 enum rtx_code code = GET_CODE (x);
2359 struct elim_table *p;
2364 if (LABEL_REF_NONLOCAL_P (x))
2369 /* ... fall through ... */
2372 /* If we know nothing about this label, set the desired offsets. Note
2373 that this sets the offset at a label to be the offset before a label
2374 if we don't know anything about the label. This is not correct for
2375 the label after a BARRIER, but is the best guess we can make. If
2376 we guessed wrong, we will suppress an elimination that might have
2377 been possible had we been able to guess correctly. */
2379 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2381 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2382 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2383 = (initial_p ? reg_eliminate[i].initial_offset
2384 : reg_eliminate[i].offset);
2385 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2388 /* Otherwise, if this is the definition of a label and it is
2389 preceded by a BARRIER, set our offsets to the known offset of
2393 && (tem = prev_nonnote_insn (insn)) != 0
2395 set_offsets_for_label (insn);
2397 /* If neither of the above cases is true, compare each offset
2398 with those previously recorded and suppress any eliminations
2399 where the offsets disagree. */
2401 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2402 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2403 != (initial_p ? reg_eliminate[i].initial_offset
2404 : reg_eliminate[i].offset))
2405 reg_eliminate[i].can_eliminate = 0;
2410 set_label_offsets (PATTERN (insn), insn, initial_p);
2412 /* ... fall through ... */
2416 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2417 to indirectly and hence must have all eliminations at their
2419 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2420 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2421 set_label_offsets (XEXP (tem, 0), insn, 1);
2427 /* Each of the labels in the parallel or address vector must be
2428 at their initial offsets. We want the first field for PARALLEL
2429 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2431 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2432 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2437 /* We only care about setting PC. If the source is not RETURN,
2438 IF_THEN_ELSE, or a label, disable any eliminations not at
2439 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2440 isn't one of those possibilities. For branches to a label,
2441 call ourselves recursively.
2443 Note that this can disable elimination unnecessarily when we have
2444 a non-local goto since it will look like a non-constant jump to
2445 someplace in the current function. This isn't a significant
2446 problem since such jumps will normally be when all elimination
2447 pairs are back to their initial offsets. */
2449 if (SET_DEST (x) != pc_rtx)
2452 switch (GET_CODE (SET_SRC (x)))
2459 set_label_offsets (SET_SRC (x), insn, initial_p);
2463 tem = XEXP (SET_SRC (x), 1);
2464 if (GET_CODE (tem) == LABEL_REF)
2465 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2466 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2469 tem = XEXP (SET_SRC (x), 2);
2470 if (GET_CODE (tem) == LABEL_REF)
2471 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2472 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2480 /* If we reach here, all eliminations must be at their initial
2481 offset because we are doing a jump to a variable address. */
2482 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2483 if (p->offset != p->initial_offset)
2484 p->can_eliminate = 0;
2492 /* Scan X and replace any eliminable registers (such as fp) with a
2493 replacement (such as sp), plus an offset.
2495 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2496 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2497 MEM, we are allowed to replace a sum of a register and the constant zero
2498 with the register, which we cannot do outside a MEM. In addition, we need
2499 to record the fact that a register is referenced outside a MEM.
2501 If INSN is an insn, it is the insn containing X. If we replace a REG
2502 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2503 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2504 the REG is being modified.
2506 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2507 That's used when we eliminate in expressions stored in notes.
2508 This means, do not set ref_outside_mem even if the reference
2511 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2512 replacements done assuming all offsets are at their initial values. If
2513 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2514 encounter, return the actual location so that find_reloads will do
2515 the proper thing. */
2518 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2519 bool may_use_invariant)
2521 enum rtx_code code = GET_CODE (x);
2522 struct elim_table *ep;
2529 if (! current_function_decl)
2552 /* First handle the case where we encounter a bare register that
2553 is eliminable. Replace it with a PLUS. */
2554 if (regno < FIRST_PSEUDO_REGISTER)
2556 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2558 if (ep->from_rtx == x && ep->can_eliminate)
2559 return plus_constant (ep->to_rtx, ep->previous_offset);
2562 else if (reg_renumber && reg_renumber[regno] < 0
2563 && reg_equiv_invariant && reg_equiv_invariant[regno])
2565 if (may_use_invariant)
2566 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2567 mem_mode, insn, true);
2568 /* There exists at least one use of REGNO that cannot be
2569 eliminated. Prevent the defining insn from being deleted. */
2570 reg_equiv_init[regno] = NULL_RTX;
2571 alter_reg (regno, -1, true);
2575 /* You might think handling MINUS in a manner similar to PLUS is a
2576 good idea. It is not. It has been tried multiple times and every
2577 time the change has had to have been reverted.
2579 Other parts of reload know a PLUS is special (gen_reload for example)
2580 and require special code to handle code a reloaded PLUS operand.
2582 Also consider backends where the flags register is clobbered by a
2583 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2584 lea instruction comes to mind). If we try to reload a MINUS, we
2585 may kill the flags register that was holding a useful value.
2587 So, please before trying to handle MINUS, consider reload as a
2588 whole instead of this little section as well as the backend issues. */
2590 /* If this is the sum of an eliminable register and a constant, rework
2592 if (REG_P (XEXP (x, 0))
2593 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2594 && CONSTANT_P (XEXP (x, 1)))
2596 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2598 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2600 /* The only time we want to replace a PLUS with a REG (this
2601 occurs when the constant operand of the PLUS is the negative
2602 of the offset) is when we are inside a MEM. We won't want
2603 to do so at other times because that would change the
2604 structure of the insn in a way that reload can't handle.
2605 We special-case the commonest situation in
2606 eliminate_regs_in_insn, so just replace a PLUS with a
2607 PLUS here, unless inside a MEM. */
2608 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2609 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2612 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2613 plus_constant (XEXP (x, 1),
2614 ep->previous_offset));
2617 /* If the register is not eliminable, we are done since the other
2618 operand is a constant. */
2622 /* If this is part of an address, we want to bring any constant to the
2623 outermost PLUS. We will do this by doing register replacement in
2624 our operands and seeing if a constant shows up in one of them.
2626 Note that there is no risk of modifying the structure of the insn,
2627 since we only get called for its operands, thus we are either
2628 modifying the address inside a MEM, or something like an address
2629 operand of a load-address insn. */
2632 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2633 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2635 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2637 /* If one side is a PLUS and the other side is a pseudo that
2638 didn't get a hard register but has a reg_equiv_constant,
2639 we must replace the constant here since it may no longer
2640 be in the position of any operand. */
2641 if (GET_CODE (new0) == PLUS && REG_P (new1)
2642 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2643 && reg_renumber[REGNO (new1)] < 0
2644 && reg_equiv_constant != 0
2645 && reg_equiv_constant[REGNO (new1)] != 0)
2646 new1 = reg_equiv_constant[REGNO (new1)];
2647 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2648 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2649 && reg_renumber[REGNO (new0)] < 0
2650 && reg_equiv_constant[REGNO (new0)] != 0)
2651 new0 = reg_equiv_constant[REGNO (new0)];
2653 new_rtx = form_sum (new0, new1);
2655 /* As above, if we are not inside a MEM we do not want to
2656 turn a PLUS into something else. We might try to do so here
2657 for an addition of 0 if we aren't optimizing. */
2658 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2659 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2667 /* If this is the product of an eliminable register and a
2668 constant, apply the distribute law and move the constant out
2669 so that we have (plus (mult ..) ..). This is needed in order
2670 to keep load-address insns valid. This case is pathological.
2671 We ignore the possibility of overflow here. */
2672 if (REG_P (XEXP (x, 0))
2673 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2674 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2675 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2677 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2680 /* Refs inside notes don't count for this purpose. */
2681 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2682 || GET_CODE (insn) == INSN_LIST)))
2683 ep->ref_outside_mem = 1;
2686 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2687 ep->previous_offset * INTVAL (XEXP (x, 1)));
2690 /* ... fall through ... */
2694 /* See comments before PLUS about handling MINUS. */
2696 case DIV: case UDIV:
2697 case MOD: case UMOD:
2698 case AND: case IOR: case XOR:
2699 case ROTATERT: case ROTATE:
2700 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2702 case GE: case GT: case GEU: case GTU:
2703 case LE: case LT: case LEU: case LTU:
2705 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2706 rtx new1 = XEXP (x, 1)
2707 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2709 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2710 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2715 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2718 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2719 if (new_rtx != XEXP (x, 0))
2721 /* If this is a REG_DEAD note, it is not valid anymore.
2722 Using the eliminated version could result in creating a
2723 REG_DEAD note for the stack or frame pointer. */
2724 if (REG_NOTE_KIND (x) == REG_DEAD)
2726 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2729 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2733 /* ... fall through ... */
2736 /* Now do eliminations in the rest of the chain. If this was
2737 an EXPR_LIST, this might result in allocating more memory than is
2738 strictly needed, but it simplifies the code. */
2741 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2742 if (new_rtx != XEXP (x, 1))
2744 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2752 /* We do not support elimination of a register that is modified.
2753 elimination_effects has already make sure that this does not
2759 /* We do not support elimination of a register that is modified.
2760 elimination_effects has already make sure that this does not
2761 happen. The only remaining case we need to consider here is
2762 that the increment value may be an eliminable register. */
2763 if (GET_CODE (XEXP (x, 1)) == PLUS
2764 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2766 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2769 if (new_rtx != XEXP (XEXP (x, 1), 1))
2770 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2771 gen_rtx_PLUS (GET_MODE (x),
2772 XEXP (x, 0), new_rtx));
2776 case STRICT_LOW_PART:
2778 case SIGN_EXTEND: case ZERO_EXTEND:
2779 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2780 case FLOAT: case FIX:
2781 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2790 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2791 if (new_rtx != XEXP (x, 0))
2792 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2796 /* Similar to above processing, but preserve SUBREG_BYTE.
2797 Convert (subreg (mem)) to (mem) if not paradoxical.
2798 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2799 pseudo didn't get a hard reg, we must replace this with the
2800 eliminated version of the memory location because push_reload
2801 may do the replacement in certain circumstances. */
2802 if (REG_P (SUBREG_REG (x))
2803 && (GET_MODE_SIZE (GET_MODE (x))
2804 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2805 && reg_equiv_memory_loc != 0
2806 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2808 new_rtx = SUBREG_REG (x);
2811 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2813 if (new_rtx != SUBREG_REG (x))
2815 int x_size = GET_MODE_SIZE (GET_MODE (x));
2816 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2819 && ((x_size < new_size
2820 #ifdef WORD_REGISTER_OPERATIONS
2821 /* On these machines, combine can create rtl of the form
2822 (set (subreg:m1 (reg:m2 R) 0) ...)
2823 where m1 < m2, and expects something interesting to
2824 happen to the entire word. Moreover, it will use the
2825 (reg:m2 R) later, expecting all bits to be preserved.
2826 So if the number of words is the same, preserve the
2827 subreg so that push_reload can see it. */
2828 && ! ((x_size - 1) / UNITS_PER_WORD
2829 == (new_size -1 ) / UNITS_PER_WORD)
2832 || x_size == new_size)
2834 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2836 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2842 /* Our only special processing is to pass the mode of the MEM to our
2843 recursive call and copy the flags. While we are here, handle this
2844 case more efficiently. */
2846 replace_equiv_address_nv (x,
2847 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2851 /* Handle insn_list USE that a call to a pure function may generate. */
2852 new_rtx = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2853 if (new_rtx != XEXP (x, 0))
2854 return gen_rtx_USE (GET_MODE (x), new_rtx);
2866 /* Process each of our operands recursively. If any have changed, make a
2868 fmt = GET_RTX_FORMAT (code);
2869 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2873 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2874 if (new_rtx != XEXP (x, i) && ! copied)
2876 x = shallow_copy_rtx (x);
2879 XEXP (x, i) = new_rtx;
2881 else if (*fmt == 'E')
2884 for (j = 0; j < XVECLEN (x, i); j++)
2886 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2887 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2889 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2893 x = shallow_copy_rtx (x);
2896 XVEC (x, i) = new_v;
2899 XVECEXP (x, i, j) = new_rtx;
2908 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2910 return eliminate_regs_1 (x, mem_mode, insn, false);
2913 /* Scan rtx X for modifications of elimination target registers. Update
2914 the table of eliminables to reflect the changed state. MEM_MODE is
2915 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2918 elimination_effects (rtx x, enum machine_mode mem_mode)
2920 enum rtx_code code = GET_CODE (x);
2921 struct elim_table *ep;
2946 /* First handle the case where we encounter a bare register that
2947 is eliminable. Replace it with a PLUS. */
2948 if (regno < FIRST_PSEUDO_REGISTER)
2950 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2952 if (ep->from_rtx == x && ep->can_eliminate)
2955 ep->ref_outside_mem = 1;
2960 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2961 && reg_equiv_constant[regno]
2962 && ! function_invariant_p (reg_equiv_constant[regno]))
2963 elimination_effects (reg_equiv_constant[regno], mem_mode);
2972 /* If we modify the source of an elimination rule, disable it. */
2973 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2974 if (ep->from_rtx == XEXP (x, 0))
2975 ep->can_eliminate = 0;
2977 /* If we modify the target of an elimination rule by adding a constant,
2978 update its offset. If we modify the target in any other way, we'll
2979 have to disable the rule as well. */
2980 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2981 if (ep->to_rtx == XEXP (x, 0))
2983 int size = GET_MODE_SIZE (mem_mode);
2985 /* If more bytes than MEM_MODE are pushed, account for them. */
2986 #ifdef PUSH_ROUNDING
2987 if (ep->to_rtx == stack_pointer_rtx)
2988 size = PUSH_ROUNDING (size);
2990 if (code == PRE_DEC || code == POST_DEC)
2992 else if (code == PRE_INC || code == POST_INC)
2994 else if (code == PRE_MODIFY || code == POST_MODIFY)
2996 if (GET_CODE (XEXP (x, 1)) == PLUS
2997 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2998 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2999 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3001 ep->can_eliminate = 0;
3005 /* These two aren't unary operators. */
3006 if (code == POST_MODIFY || code == PRE_MODIFY)
3009 /* Fall through to generic unary operation case. */
3010 case STRICT_LOW_PART:
3012 case SIGN_EXTEND: case ZERO_EXTEND:
3013 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3014 case FLOAT: case FIX:
3015 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3024 elimination_effects (XEXP (x, 0), mem_mode);
3028 if (REG_P (SUBREG_REG (x))
3029 && (GET_MODE_SIZE (GET_MODE (x))
3030 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3031 && reg_equiv_memory_loc != 0
3032 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3035 elimination_effects (SUBREG_REG (x), mem_mode);
3039 /* If using a register that is the source of an eliminate we still
3040 think can be performed, note it cannot be performed since we don't
3041 know how this register is used. */
3042 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3043 if (ep->from_rtx == XEXP (x, 0))
3044 ep->can_eliminate = 0;
3046 elimination_effects (XEXP (x, 0), mem_mode);
3050 /* If clobbering a register that is the replacement register for an
3051 elimination we still think can be performed, note that it cannot
3052 be performed. Otherwise, we need not be concerned about it. */
3053 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3054 if (ep->to_rtx == XEXP (x, 0))
3055 ep->can_eliminate = 0;
3057 elimination_effects (XEXP (x, 0), mem_mode);
3061 /* Check for setting a register that we know about. */
3062 if (REG_P (SET_DEST (x)))
3064 /* See if this is setting the replacement register for an
3067 If DEST is the hard frame pointer, we do nothing because we
3068 assume that all assignments to the frame pointer are for
3069 non-local gotos and are being done at a time when they are valid
3070 and do not disturb anything else. Some machines want to
3071 eliminate a fake argument pointer (or even a fake frame pointer)
3072 with either the real frame or the stack pointer. Assignments to
3073 the hard frame pointer must not prevent this elimination. */
3075 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3077 if (ep->to_rtx == SET_DEST (x)
3078 && SET_DEST (x) != hard_frame_pointer_rtx)
3080 /* If it is being incremented, adjust the offset. Otherwise,
3081 this elimination can't be done. */
3082 rtx src = SET_SRC (x);
3084 if (GET_CODE (src) == PLUS
3085 && XEXP (src, 0) == SET_DEST (x)
3086 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3087 ep->offset -= INTVAL (XEXP (src, 1));
3089 ep->can_eliminate = 0;
3093 elimination_effects (SET_DEST (x), 0);
3094 elimination_effects (SET_SRC (x), 0);
3098 /* Our only special processing is to pass the mode of the MEM to our
3100 elimination_effects (XEXP (x, 0), GET_MODE (x));
3107 fmt = GET_RTX_FORMAT (code);
3108 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3111 elimination_effects (XEXP (x, i), mem_mode);
3112 else if (*fmt == 'E')
3113 for (j = 0; j < XVECLEN (x, i); j++)
3114 elimination_effects (XVECEXP (x, i, j), mem_mode);
3118 /* Descend through rtx X and verify that no references to eliminable registers
3119 remain. If any do remain, mark the involved register as not
3123 check_eliminable_occurrences (rtx x)
3132 code = GET_CODE (x);
3134 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3136 struct elim_table *ep;
3138 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3139 if (ep->from_rtx == x)
3140 ep->can_eliminate = 0;
3144 fmt = GET_RTX_FORMAT (code);
3145 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3148 check_eliminable_occurrences (XEXP (x, i));
3149 else if (*fmt == 'E')
3152 for (j = 0; j < XVECLEN (x, i); j++)
3153 check_eliminable_occurrences (XVECEXP (x, i, j));
3158 /* Scan INSN and eliminate all eliminable registers in it.
3160 If REPLACE is nonzero, do the replacement destructively. Also
3161 delete the insn as dead it if it is setting an eliminable register.
3163 If REPLACE is zero, do all our allocations in reload_obstack.
3165 If no eliminations were done and this insn doesn't require any elimination
3166 processing (these are not identical conditions: it might be updating sp,
3167 but not referencing fp; this needs to be seen during reload_as_needed so
3168 that the offset between fp and sp can be taken into consideration), zero
3169 is returned. Otherwise, 1 is returned. */
3172 eliminate_regs_in_insn (rtx insn, int replace)
3174 int icode = recog_memoized (insn);
3175 rtx old_body = PATTERN (insn);
3176 int insn_is_asm = asm_noperands (old_body) >= 0;
3177 rtx old_set = single_set (insn);
3181 rtx substed_operand[MAX_RECOG_OPERANDS];
3182 rtx orig_operand[MAX_RECOG_OPERANDS];
3183 struct elim_table *ep;
3184 rtx plus_src, plus_cst_src;
3186 if (! insn_is_asm && icode < 0)
3188 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3189 || GET_CODE (PATTERN (insn)) == CLOBBER
3190 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3191 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3192 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3196 if (old_set != 0 && REG_P (SET_DEST (old_set))
3197 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3199 /* Check for setting an eliminable register. */
3200 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3201 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3203 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3204 /* If this is setting the frame pointer register to the
3205 hardware frame pointer register and this is an elimination
3206 that will be done (tested above), this insn is really
3207 adjusting the frame pointer downward to compensate for
3208 the adjustment done before a nonlocal goto. */
3209 if (ep->from == FRAME_POINTER_REGNUM
3210 && ep->to == HARD_FRAME_POINTER_REGNUM)
3212 rtx base = SET_SRC (old_set);
3213 rtx base_insn = insn;
3214 HOST_WIDE_INT offset = 0;
3216 while (base != ep->to_rtx)
3218 rtx prev_insn, prev_set;
3220 if (GET_CODE (base) == PLUS
3221 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3223 offset += INTVAL (XEXP (base, 1));
3224 base = XEXP (base, 0);
3226 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3227 && (prev_set = single_set (prev_insn)) != 0
3228 && rtx_equal_p (SET_DEST (prev_set), base))
3230 base = SET_SRC (prev_set);
3231 base_insn = prev_insn;
3237 if (base == ep->to_rtx)
3240 = plus_constant (ep->to_rtx, offset - ep->offset);
3242 new_body = old_body;
3245 new_body = copy_insn (old_body);
3246 if (REG_NOTES (insn))
3247 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3249 PATTERN (insn) = new_body;
3250 old_set = single_set (insn);
3252 /* First see if this insn remains valid when we
3253 make the change. If not, keep the INSN_CODE
3254 the same and let reload fit it up. */
3255 validate_change (insn, &SET_SRC (old_set), src, 1);
3256 validate_change (insn, &SET_DEST (old_set),
3258 if (! apply_change_group ())
3260 SET_SRC (old_set) = src;
3261 SET_DEST (old_set) = ep->to_rtx;
3270 /* In this case this insn isn't serving a useful purpose. We
3271 will delete it in reload_as_needed once we know that this
3272 elimination is, in fact, being done.
3274 If REPLACE isn't set, we can't delete this insn, but needn't
3275 process it since it won't be used unless something changes. */
3278 delete_dead_insn (insn);
3286 /* We allow one special case which happens to work on all machines we
3287 currently support: a single set with the source or a REG_EQUAL
3288 note being a PLUS of an eliminable register and a constant. */
3289 plus_src = plus_cst_src = 0;
3290 if (old_set && REG_P (SET_DEST (old_set)))
3292 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3293 plus_src = SET_SRC (old_set);
3294 /* First see if the source is of the form (plus (...) CST). */
3296 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3297 plus_cst_src = plus_src;
3298 else if (REG_P (SET_SRC (old_set))
3301 /* Otherwise, see if we have a REG_EQUAL note of the form
3302 (plus (...) CST). */
3304 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3306 if ((REG_NOTE_KIND (links) == REG_EQUAL
3307 || REG_NOTE_KIND (links) == REG_EQUIV)
3308 && GET_CODE (XEXP (links, 0)) == PLUS
3309 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3311 plus_cst_src = XEXP (links, 0);
3317 /* Check that the first operand of the PLUS is a hard reg or
3318 the lowpart subreg of one. */
3321 rtx reg = XEXP (plus_cst_src, 0);
3322 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3323 reg = SUBREG_REG (reg);
3325 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3331 rtx reg = XEXP (plus_cst_src, 0);
3332 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3334 if (GET_CODE (reg) == SUBREG)
3335 reg = SUBREG_REG (reg);
3337 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3338 if (ep->from_rtx == reg && ep->can_eliminate)
3340 rtx to_rtx = ep->to_rtx;
3341 offset += ep->offset;
3342 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3344 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3345 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3347 /* If we have a nonzero offset, and the source is already
3348 a simple REG, the following transformation would
3349 increase the cost of the insn by replacing a simple REG
3350 with (plus (reg sp) CST). So try only when we already
3351 had a PLUS before. */
3352 if (offset == 0 || plus_src)
3354 rtx new_src = plus_constant (to_rtx, offset);
3356 new_body = old_body;
3359 new_body = copy_insn (old_body);
3360 if (REG_NOTES (insn))
3361 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3363 PATTERN (insn) = new_body;
3364 old_set = single_set (insn);
3366 /* First see if this insn remains valid when we make the
3367 change. If not, try to replace the whole pattern with
3368 a simple set (this may help if the original insn was a
3369 PARALLEL that was only recognized as single_set due to
3370 REG_UNUSED notes). If this isn't valid either, keep
3371 the INSN_CODE the same and let reload fix it up. */
3372 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3374 rtx new_pat = gen_rtx_SET (VOIDmode,
3375 SET_DEST (old_set), new_src);
3377 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3378 SET_SRC (old_set) = new_src;
3385 /* This can't have an effect on elimination offsets, so skip right
3391 /* Determine the effects of this insn on elimination offsets. */
3392 elimination_effects (old_body, 0);
3394 /* Eliminate all eliminable registers occurring in operands that
3395 can be handled by reload. */
3396 extract_insn (insn);
3397 for (i = 0; i < recog_data.n_operands; i++)
3399 orig_operand[i] = recog_data.operand[i];
3400 substed_operand[i] = recog_data.operand[i];
3402 /* For an asm statement, every operand is eliminable. */
3403 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3405 bool is_set_src, in_plus;
3407 /* Check for setting a register that we know about. */
3408 if (recog_data.operand_type[i] != OP_IN
3409 && REG_P (orig_operand[i]))
3411 /* If we are assigning to a register that can be eliminated, it
3412 must be as part of a PARALLEL, since the code above handles
3413 single SETs. We must indicate that we can no longer
3414 eliminate this reg. */
3415 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3417 if (ep->from_rtx == orig_operand[i])
3418 ep->can_eliminate = 0;
3421 /* Companion to the above plus substitution, we can allow
3422 invariants as the source of a plain move. */
3424 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3428 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3429 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3433 = eliminate_regs_1 (recog_data.operand[i], 0,
3434 replace ? insn : NULL_RTX,
3435 is_set_src || in_plus);
3436 if (substed_operand[i] != orig_operand[i])
3438 /* Terminate the search in check_eliminable_occurrences at
3440 *recog_data.operand_loc[i] = 0;
3442 /* If an output operand changed from a REG to a MEM and INSN is an
3443 insn, write a CLOBBER insn. */
3444 if (recog_data.operand_type[i] != OP_IN
3445 && REG_P (orig_operand[i])
3446 && MEM_P (substed_operand[i])
3448 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3452 for (i = 0; i < recog_data.n_dups; i++)
3453 *recog_data.dup_loc[i]
3454 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3456 /* If any eliminable remain, they aren't eliminable anymore. */
3457 check_eliminable_occurrences (old_body);
3459 /* Substitute the operands; the new values are in the substed_operand
3461 for (i = 0; i < recog_data.n_operands; i++)
3462 *recog_data.operand_loc[i] = substed_operand[i];
3463 for (i = 0; i < recog_data.n_dups; i++)
3464 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3466 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3467 re-recognize the insn. We do this in case we had a simple addition
3468 but now can do this as a load-address. This saves an insn in this
3470 If re-recognition fails, the old insn code number will still be used,
3471 and some register operands may have changed into PLUS expressions.
3472 These will be handled by find_reloads by loading them into a register
3477 /* If we aren't replacing things permanently and we changed something,
3478 make another copy to ensure that all the RTL is new. Otherwise
3479 things can go wrong if find_reload swaps commutative operands
3480 and one is inside RTL that has been copied while the other is not. */
3481 new_body = old_body;
3484 new_body = copy_insn (old_body);
3485 if (REG_NOTES (insn))
3486 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3488 PATTERN (insn) = new_body;
3490 /* If we had a move insn but now we don't, rerecognize it. This will
3491 cause spurious re-recognition if the old move had a PARALLEL since
3492 the new one still will, but we can't call single_set without
3493 having put NEW_BODY into the insn and the re-recognition won't
3494 hurt in this rare case. */
3495 /* ??? Why this huge if statement - why don't we just rerecognize the
3499 && ((REG_P (SET_SRC (old_set))
3500 && (GET_CODE (new_body) != SET
3501 || !REG_P (SET_SRC (new_body))))
3502 /* If this was a load from or store to memory, compare
3503 the MEM in recog_data.operand to the one in the insn.
3504 If they are not equal, then rerecognize the insn. */
3506 && ((MEM_P (SET_SRC (old_set))
3507 && SET_SRC (old_set) != recog_data.operand[1])
3508 || (MEM_P (SET_DEST (old_set))
3509 && SET_DEST (old_set) != recog_data.operand[0])))
3510 /* If this was an add insn before, rerecognize. */
3511 || GET_CODE (SET_SRC (old_set)) == PLUS))
3513 int new_icode = recog (PATTERN (insn), insn, 0);
3515 INSN_CODE (insn) = new_icode;
3519 /* Restore the old body. If there were any changes to it, we made a copy
3520 of it while the changes were still in place, so we'll correctly return
3521 a modified insn below. */
3524 /* Restore the old body. */
3525 for (i = 0; i < recog_data.n_operands; i++)
3526 *recog_data.operand_loc[i] = orig_operand[i];
3527 for (i = 0; i < recog_data.n_dups; i++)
3528 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3531 /* Update all elimination pairs to reflect the status after the current
3532 insn. The changes we make were determined by the earlier call to
3533 elimination_effects.
3535 We also detect cases where register elimination cannot be done,
3536 namely, if a register would be both changed and referenced outside a MEM
3537 in the resulting insn since such an insn is often undefined and, even if
3538 not, we cannot know what meaning will be given to it. Note that it is
3539 valid to have a register used in an address in an insn that changes it
3540 (presumably with a pre- or post-increment or decrement).
3542 If anything changes, return nonzero. */
3544 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3546 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3547 ep->can_eliminate = 0;
3549 ep->ref_outside_mem = 0;
3551 if (ep->previous_offset != ep->offset)
3556 /* If we changed something, perform elimination in REG_NOTES. This is
3557 needed even when REPLACE is zero because a REG_DEAD note might refer
3558 to a register that we eliminate and could cause a different number
3559 of spill registers to be needed in the final reload pass than in
3561 if (val && REG_NOTES (insn) != 0)
3563 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3568 /* Loop through all elimination pairs.
3569 Recalculate the number not at initial offset.
3571 Compute the maximum offset (minimum offset if the stack does not
3572 grow downward) for each elimination pair. */
3575 update_eliminable_offsets (void)
3577 struct elim_table *ep;
3579 num_not_at_initial_offset = 0;
3580 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3582 ep->previous_offset = ep->offset;
3583 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3584 num_not_at_initial_offset++;
3588 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3589 replacement we currently believe is valid, mark it as not eliminable if X
3590 modifies DEST in any way other than by adding a constant integer to it.
3592 If DEST is the frame pointer, we do nothing because we assume that
3593 all assignments to the hard frame pointer are nonlocal gotos and are being
3594 done at a time when they are valid and do not disturb anything else.
3595 Some machines want to eliminate a fake argument pointer with either the
3596 frame or stack pointer. Assignments to the hard frame pointer must not
3597 prevent this elimination.
3599 Called via note_stores from reload before starting its passes to scan
3600 the insns of the function. */
3603 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3607 /* A SUBREG of a hard register here is just changing its mode. We should
3608 not see a SUBREG of an eliminable hard register, but check just in
3610 if (GET_CODE (dest) == SUBREG)
3611 dest = SUBREG_REG (dest);
3613 if (dest == hard_frame_pointer_rtx)
3616 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3617 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3618 && (GET_CODE (x) != SET
3619 || GET_CODE (SET_SRC (x)) != PLUS
3620 || XEXP (SET_SRC (x), 0) != dest
3621 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3623 reg_eliminate[i].can_eliminate_previous
3624 = reg_eliminate[i].can_eliminate = 0;
3629 /* Verify that the initial elimination offsets did not change since the
3630 last call to set_initial_elim_offsets. This is used to catch cases
3631 where something illegal happened during reload_as_needed that could
3632 cause incorrect code to be generated if we did not check for it. */
3635 verify_initial_elim_offsets (void)
3639 if (!num_eliminable)
3642 #ifdef ELIMINABLE_REGS
3644 struct elim_table *ep;
3646 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3648 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3649 if (t != ep->initial_offset)
3654 INITIAL_FRAME_POINTER_OFFSET (t);
3655 if (t != reg_eliminate[0].initial_offset)
3662 /* Reset all offsets on eliminable registers to their initial values. */
3665 set_initial_elim_offsets (void)
3667 struct elim_table *ep = reg_eliminate;
3669 #ifdef ELIMINABLE_REGS
3670 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3672 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3673 ep->previous_offset = ep->offset = ep->initial_offset;
3676 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3677 ep->previous_offset = ep->offset = ep->initial_offset;
3680 num_not_at_initial_offset = 0;
3683 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3686 set_initial_eh_label_offset (rtx label)
3688 set_label_offsets (label, NULL_RTX, 1);
3691 /* Initialize the known label offsets.
3692 Set a known offset for each forced label to be at the initial offset
3693 of each elimination. We do this because we assume that all
3694 computed jumps occur from a location where each elimination is
3695 at its initial offset.
3696 For all other labels, show that we don't know the offsets. */
3699 set_initial_label_offsets (void)
3702 memset (offsets_known_at, 0, num_labels);
3704 for (x = forced_labels; x; x = XEXP (x, 1))
3706 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3708 for_each_eh_label (set_initial_eh_label_offset);
3711 /* Set all elimination offsets to the known values for the code label given
3715 set_offsets_for_label (rtx insn)
3718 int label_nr = CODE_LABEL_NUMBER (insn);
3719 struct elim_table *ep;
3721 num_not_at_initial_offset = 0;
3722 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3724 ep->offset = ep->previous_offset
3725 = offsets_at[label_nr - first_label_num][i];
3726 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3727 num_not_at_initial_offset++;
3731 /* See if anything that happened changes which eliminations are valid.
3732 For example, on the SPARC, whether or not the frame pointer can
3733 be eliminated can depend on what registers have been used. We need
3734 not check some conditions again (such as flag_omit_frame_pointer)
3735 since they can't have changed. */
3738 update_eliminables (HARD_REG_SET *pset)
3740 int previous_frame_pointer_needed = frame_pointer_needed;
3741 struct elim_table *ep;
3743 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3744 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3745 #ifdef ELIMINABLE_REGS
3746 || ! CAN_ELIMINATE (ep->from, ep->to)
3749 ep->can_eliminate = 0;
3751 /* Look for the case where we have discovered that we can't replace
3752 register A with register B and that means that we will now be
3753 trying to replace register A with register C. This means we can
3754 no longer replace register C with register B and we need to disable
3755 such an elimination, if it exists. This occurs often with A == ap,
3756 B == sp, and C == fp. */
3758 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3760 struct elim_table *op;
3763 if (! ep->can_eliminate && ep->can_eliminate_previous)
3765 /* Find the current elimination for ep->from, if there is a
3767 for (op = reg_eliminate;
3768 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3769 if (op->from == ep->from && op->can_eliminate)
3775 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3777 for (op = reg_eliminate;
3778 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3779 if (op->from == new_to && op->to == ep->to)
3780 op->can_eliminate = 0;
3784 /* See if any registers that we thought we could eliminate the previous
3785 time are no longer eliminable. If so, something has changed and we
3786 must spill the register. Also, recompute the number of eliminable
3787 registers and see if the frame pointer is needed; it is if there is
3788 no elimination of the frame pointer that we can perform. */
3790 frame_pointer_needed = 1;
3791 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3793 if (ep->can_eliminate
3794 && ep->from == FRAME_POINTER_REGNUM
3795 && ep->to != HARD_FRAME_POINTER_REGNUM
3796 && (! SUPPORTS_STACK_ALIGNMENT
3797 || ! crtl->stack_realign_needed))
3798 frame_pointer_needed = 0;
3800 if (! ep->can_eliminate && ep->can_eliminate_previous)
3802 ep->can_eliminate_previous = 0;
3803 SET_HARD_REG_BIT (*pset, ep->from);
3808 /* If we didn't need a frame pointer last time, but we do now, spill
3809 the hard frame pointer. */
3810 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3811 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3814 /* Return true if X is used as the target register of an elimination. */
3817 elimination_target_reg_p (rtx x)
3819 struct elim_table *ep;
3821 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3822 if (ep->to_rtx == x && ep->can_eliminate)
3828 /* Initialize the table of registers to eliminate.
3829 Pre-condition: global flag frame_pointer_needed has been set before
3830 calling this function. */
3833 init_elim_table (void)
3835 struct elim_table *ep;
3836 #ifdef ELIMINABLE_REGS
3837 const struct elim_table_1 *ep1;
3841 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3845 #ifdef ELIMINABLE_REGS
3846 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3847 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3849 ep->from = ep1->from;
3851 ep->can_eliminate = ep->can_eliminate_previous
3852 = (CAN_ELIMINATE (ep->from, ep->to)
3853 && ! (ep->to == STACK_POINTER_REGNUM
3854 && frame_pointer_needed
3855 && (! SUPPORTS_STACK_ALIGNMENT
3856 || ! stack_realign_fp)));
3859 reg_eliminate[0].from = reg_eliminate_1[0].from;
3860 reg_eliminate[0].to = reg_eliminate_1[0].to;
3861 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3862 = ! frame_pointer_needed;
3865 /* Count the number of eliminable registers and build the FROM and TO
3866 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3867 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3868 We depend on this. */
3869 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3871 num_eliminable += ep->can_eliminate;
3872 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3873 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3877 /* Kick all pseudos out of hard register REGNO.
3879 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3880 because we found we can't eliminate some register. In the case, no pseudos
3881 are allowed to be in the register, even if they are only in a block that
3882 doesn't require spill registers, unlike the case when we are spilling this
3883 hard reg to produce another spill register.
3885 Return nonzero if any pseudos needed to be kicked out. */
3888 spill_hard_reg (unsigned int regno, int cant_eliminate)
3894 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3895 df_set_regs_ever_live (regno, true);
3898 /* Spill every pseudo reg that was allocated to this reg
3899 or to something that overlaps this reg. */
3901 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3902 if (reg_renumber[i] >= 0
3903 && (unsigned int) reg_renumber[i] <= regno
3904 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3905 SET_REGNO_REG_SET (&spilled_pseudos, i);
3908 /* After find_reload_regs has been run for all insn that need reloads,
3909 and/or spill_hard_regs was called, this function is used to actually
3910 spill pseudo registers and try to reallocate them. It also sets up the
3911 spill_regs array for use by choose_reload_regs. */
3914 finish_spills (int global)
3916 struct insn_chain *chain;
3917 int something_changed = 0;
3919 reg_set_iterator rsi;
3921 /* Build the spill_regs array for the function. */
3922 /* If there are some registers still to eliminate and one of the spill regs
3923 wasn't ever used before, additional stack space may have to be
3924 allocated to store this register. Thus, we may have changed the offset
3925 between the stack and frame pointers, so mark that something has changed.
3927 One might think that we need only set VAL to 1 if this is a call-used
3928 register. However, the set of registers that must be saved by the
3929 prologue is not identical to the call-used set. For example, the
3930 register used by the call insn for the return PC is a call-used register,
3931 but must be saved by the prologue. */
3934 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3935 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3937 spill_reg_order[i] = n_spills;
3938 spill_regs[n_spills++] = i;
3939 if (num_eliminable && ! df_regs_ever_live_p (i))
3940 something_changed = 1;
3941 df_set_regs_ever_live (i, true);
3944 spill_reg_order[i] = -1;
3946 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3947 if (! flag_ira || ! optimize || reg_renumber[i] >= 0)
3949 /* Record the current hard register the pseudo is allocated to
3950 in pseudo_previous_regs so we avoid reallocating it to the
3951 same hard reg in a later pass. */
3952 gcc_assert (reg_renumber[i] >= 0);
3954 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3955 /* Mark it as no longer having a hard register home. */
3956 reg_renumber[i] = -1;
3957 if (flag_ira && optimize)
3958 /* Inform IRA about the change. */
3959 ira_mark_allocation_change (i);
3960 /* We will need to scan everything again. */
3961 something_changed = 1;
3964 /* Retry global register allocation if possible. */
3967 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3968 /* For every insn that needs reloads, set the registers used as spill
3969 regs in pseudo_forbidden_regs for every pseudo live across the
3971 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3973 EXECUTE_IF_SET_IN_REG_SET
3974 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3976 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3977 chain->used_spill_regs);
3979 EXECUTE_IF_SET_IN_REG_SET
3980 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3982 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3983 chain->used_spill_regs);
3987 if (! flag_ira || ! optimize)
3989 /* Retry allocating the spilled pseudos. For each reg,
3990 merge the various reg sets that indicate which hard regs
3991 can't be used, and call retry_global_alloc. We change
3992 spill_pseudos here to only contain pseudos that did not
3993 get a new hard register. */
3994 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3995 if (reg_old_renumber[i] != reg_renumber[i])
3997 HARD_REG_SET forbidden;
3999 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
4000 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
4001 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
4002 retry_global_alloc (i, forbidden);
4003 if (reg_renumber[i] >= 0)
4004 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4009 /* Retry allocating the pseudos spilled in IRA and the
4010 reload. For each reg, merge the various reg sets that
4011 indicate which hard regs can't be used, and call
4012 ira_reassign_pseudos. */
4015 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4016 if (reg_old_renumber[i] != reg_renumber[i])
4018 if (reg_renumber[i] < 0)
4019 temp_pseudo_reg_arr[n++] = i;
4021 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4023 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4024 bad_spill_regs_global,
4025 pseudo_forbidden_regs, pseudo_previous_regs,
4027 something_changed = 1;
4031 /* Fix up the register information in the insn chain.
4032 This involves deleting those of the spilled pseudos which did not get
4033 a new hard register home from the live_{before,after} sets. */
4034 for (chain = reload_insn_chain; chain; chain = chain->next)
4036 HARD_REG_SET used_by_pseudos;
4037 HARD_REG_SET used_by_pseudos2;
4039 if (! flag_ira || ! optimize)
4041 /* Don't do it for IRA because IRA and the reload still can
4042 assign hard registers to the spilled pseudos on next
4043 reload iterations. */
4044 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4045 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4047 /* Mark any unallocated hard regs as available for spills. That
4048 makes inheritance work somewhat better. */
4049 if (chain->need_reload)
4051 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4052 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4053 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4055 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4056 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4057 /* Value of chain->used_spill_regs from previous iteration
4058 may be not included in the value calculated here because
4059 of possible removing caller-saves insns (see function
4060 delete_caller_save_insns. */
4061 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4062 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4066 CLEAR_REG_SET (&changed_allocation_pseudos);
4067 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4068 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4070 int regno = reg_renumber[i];
4071 if (reg_old_renumber[i] == regno)
4074 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4076 alter_reg (i, reg_old_renumber[i], false);
4077 reg_old_renumber[i] = regno;
4081 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4083 fprintf (dump_file, " Register %d now in %d.\n\n",
4084 i, reg_renumber[i]);
4088 return something_changed;
4091 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4094 scan_paradoxical_subregs (rtx x)
4098 enum rtx_code code = GET_CODE (x);
4109 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4117 if (REG_P (SUBREG_REG (x))
4118 && (GET_MODE_SIZE (GET_MODE (x))
4119 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4121 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4122 = GET_MODE_SIZE (GET_MODE (x));
4123 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4131 fmt = GET_RTX_FORMAT (code);
4132 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4135 scan_paradoxical_subregs (XEXP (x, i));
4136 else if (fmt[i] == 'E')
4139 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4140 scan_paradoxical_subregs (XVECEXP (x, i, j));
4145 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4146 examine all of the reload insns between PREV and NEXT exclusive, and
4147 annotate all that may trap. */
4150 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4152 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4153 unsigned int trap_count;
4159 if (may_trap_p (PATTERN (insn)))
4163 remove_note (insn, note);
4167 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4168 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4171 add_reg_note (i, REG_EH_REGION, XEXP (note, 0));
4175 /* Reload pseudo-registers into hard regs around each insn as needed.
4176 Additional register load insns are output before the insn that needs it
4177 and perhaps store insns after insns that modify the reloaded pseudo reg.
4179 reg_last_reload_reg and reg_reloaded_contents keep track of
4180 which registers are already available in reload registers.
4181 We update these for the reloads that we perform,
4182 as the insns are scanned. */
4185 reload_as_needed (int live_known)
4187 struct insn_chain *chain;
4188 #if defined (AUTO_INC_DEC)
4193 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4194 memset (spill_reg_store, 0, sizeof spill_reg_store);
4195 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4196 INIT_REG_SET (®_has_output_reload);
4197 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4198 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4200 set_initial_elim_offsets ();
4202 for (chain = reload_insn_chain; chain; chain = chain->next)
4205 rtx insn = chain->insn;
4206 rtx old_next = NEXT_INSN (insn);
4208 /* If we pass a label, copy the offsets from the label information
4209 into the current offsets of each elimination. */
4211 set_offsets_for_label (insn);
4213 else if (INSN_P (insn))
4215 regset_head regs_to_forget;
4216 INIT_REG_SET (®s_to_forget);
4217 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4219 /* If this is a USE and CLOBBER of a MEM, ensure that any
4220 references to eliminable registers have been removed. */
4222 if ((GET_CODE (PATTERN (insn)) == USE
4223 || GET_CODE (PATTERN (insn)) == CLOBBER)
4224 && MEM_P (XEXP (PATTERN (insn), 0)))
4225 XEXP (XEXP (PATTERN (insn), 0), 0)
4226 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4227 GET_MODE (XEXP (PATTERN (insn), 0)),
4230 /* If we need to do register elimination processing, do so.
4231 This might delete the insn, in which case we are done. */
4232 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4234 eliminate_regs_in_insn (insn, 1);
4237 update_eliminable_offsets ();
4238 CLEAR_REG_SET (®s_to_forget);
4243 /* If need_elim is nonzero but need_reload is zero, one might think
4244 that we could simply set n_reloads to 0. However, find_reloads
4245 could have done some manipulation of the insn (such as swapping
4246 commutative operands), and these manipulations are lost during
4247 the first pass for every insn that needs register elimination.
4248 So the actions of find_reloads must be redone here. */
4250 if (! chain->need_elim && ! chain->need_reload
4251 && ! chain->need_operand_change)
4253 /* First find the pseudo regs that must be reloaded for this insn.
4254 This info is returned in the tables reload_... (see reload.h).
4255 Also modify the body of INSN by substituting RELOAD
4256 rtx's for those pseudo regs. */
4259 CLEAR_REG_SET (®_has_output_reload);
4260 CLEAR_HARD_REG_SET (reg_is_output_reload);
4262 find_reloads (insn, 1, spill_indirect_levels, live_known,
4268 rtx next = NEXT_INSN (insn);
4271 prev = PREV_INSN (insn);
4273 /* Now compute which reload regs to reload them into. Perhaps
4274 reusing reload regs from previous insns, or else output
4275 load insns to reload them. Maybe output store insns too.
4276 Record the choices of reload reg in reload_reg_rtx. */
4277 choose_reload_regs (chain);
4279 /* Merge any reloads that we didn't combine for fear of
4280 increasing the number of spill registers needed but now
4281 discover can be safely merged. */
4282 if (SMALL_REGISTER_CLASSES)
4283 merge_assigned_reloads (insn);
4285 /* Generate the insns to reload operands into or out of
4286 their reload regs. */
4287 emit_reload_insns (chain);
4289 /* Substitute the chosen reload regs from reload_reg_rtx
4290 into the insn's body (or perhaps into the bodies of other
4291 load and store insn that we just made for reloading
4292 and that we moved the structure into). */
4293 subst_reloads (insn);
4295 /* Adjust the exception region notes for loads and stores. */
4296 if (flag_non_call_exceptions && !CALL_P (insn))
4297 fixup_eh_region_note (insn, prev, next);
4299 /* If this was an ASM, make sure that all the reload insns
4300 we have generated are valid. If not, give an error
4302 if (asm_noperands (PATTERN (insn)) >= 0)
4303 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4304 if (p != insn && INSN_P (p)
4305 && GET_CODE (PATTERN (p)) != USE
4306 && (recog_memoized (p) < 0
4307 || (extract_insn (p), ! constrain_operands (1))))
4309 error_for_asm (insn,
4310 "%<asm%> operand requires "
4311 "impossible reload");
4316 if (num_eliminable && chain->need_elim)
4317 update_eliminable_offsets ();
4319 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4320 is no longer validly lying around to save a future reload.
4321 Note that this does not detect pseudos that were reloaded
4322 for this insn in order to be stored in
4323 (obeying register constraints). That is correct; such reload
4324 registers ARE still valid. */
4325 forget_marked_reloads (®s_to_forget);
4326 CLEAR_REG_SET (®s_to_forget);
4328 /* There may have been CLOBBER insns placed after INSN. So scan
4329 between INSN and NEXT and use them to forget old reloads. */
4330 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4331 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4332 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4335 /* Likewise for regs altered by auto-increment in this insn.
4336 REG_INC notes have been changed by reloading:
4337 find_reloads_address_1 records substitutions for them,
4338 which have been performed by subst_reloads above. */
4339 for (i = n_reloads - 1; i >= 0; i--)
4341 rtx in_reg = rld[i].in_reg;
4344 enum rtx_code code = GET_CODE (in_reg);
4345 /* PRE_INC / PRE_DEC will have the reload register ending up
4346 with the same value as the stack slot, but that doesn't
4347 hold true for POST_INC / POST_DEC. Either we have to
4348 convert the memory access to a true POST_INC / POST_DEC,
4349 or we can't use the reload register for inheritance. */
4350 if ((code == POST_INC || code == POST_DEC)
4351 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4352 REGNO (rld[i].reg_rtx))
4353 /* Make sure it is the inc/dec pseudo, and not
4354 some other (e.g. output operand) pseudo. */
4355 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4356 == REGNO (XEXP (in_reg, 0))))
4359 rtx reload_reg = rld[i].reg_rtx;
4360 enum machine_mode mode = GET_MODE (reload_reg);
4364 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4366 /* We really want to ignore REG_INC notes here, so
4367 use PATTERN (p) as argument to reg_set_p . */
4368 if (reg_set_p (reload_reg, PATTERN (p)))
4370 n = count_occurrences (PATTERN (p), reload_reg, 0);
4375 n = validate_replace_rtx (reload_reg,
4376 gen_rtx_fmt_e (code,
4381 /* We must also verify that the constraints
4382 are met after the replacement. */
4385 n = constrain_operands (1);
4389 /* If the constraints were not met, then
4390 undo the replacement. */
4393 validate_replace_rtx (gen_rtx_fmt_e (code,
4405 add_reg_note (p, REG_INC, reload_reg);
4406 /* Mark this as having an output reload so that the
4407 REG_INC processing code below won't invalidate
4408 the reload for inheritance. */
4409 SET_HARD_REG_BIT (reg_is_output_reload,
4410 REGNO (reload_reg));
4411 SET_REGNO_REG_SET (®_has_output_reload,
4412 REGNO (XEXP (in_reg, 0)));
4415 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4418 else if ((code == PRE_INC || code == PRE_DEC)
4419 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4420 REGNO (rld[i].reg_rtx))
4421 /* Make sure it is the inc/dec pseudo, and not
4422 some other (e.g. output operand) pseudo. */
4423 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4424 == REGNO (XEXP (in_reg, 0))))
4426 SET_HARD_REG_BIT (reg_is_output_reload,
4427 REGNO (rld[i].reg_rtx));
4428 SET_REGNO_REG_SET (®_has_output_reload,
4429 REGNO (XEXP (in_reg, 0)));
4433 /* If a pseudo that got a hard register is auto-incremented,
4434 we must purge records of copying it into pseudos without
4436 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4437 if (REG_NOTE_KIND (x) == REG_INC)
4439 /* See if this pseudo reg was reloaded in this insn.
4440 If so, its last-reload info is still valid
4441 because it is based on this insn's reload. */
4442 for (i = 0; i < n_reloads; i++)
4443 if (rld[i].out == XEXP (x, 0))
4447 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4451 /* A reload reg's contents are unknown after a label. */
4453 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4455 /* Don't assume a reload reg is still good after a call insn
4456 if it is a call-used reg, or if it contains a value that will
4457 be partially clobbered by the call. */
4458 else if (CALL_P (insn))
4460 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4461 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4466 free (reg_last_reload_reg);
4467 CLEAR_REG_SET (®_has_output_reload);
4470 /* Discard all record of any value reloaded from X,
4471 or reloaded in X from someplace else;
4472 unless X is an output reload reg of the current insn.
4474 X may be a hard reg (the reload reg)
4475 or it may be a pseudo reg that was reloaded from.
4477 When DATA is non-NULL just mark the registers in regset
4478 to be forgotten later. */
4481 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4486 regset regs = (regset) data;
4488 /* note_stores does give us subregs of hard regs,
4489 subreg_regno_offset requires a hard reg. */
4490 while (GET_CODE (x) == SUBREG)
4492 /* We ignore the subreg offset when calculating the regno,
4493 because we are using the entire underlying hard register
4503 if (regno >= FIRST_PSEUDO_REGISTER)
4509 nr = hard_regno_nregs[regno][GET_MODE (x)];
4510 /* Storing into a spilled-reg invalidates its contents.
4511 This can happen if a block-local pseudo is allocated to that reg
4512 and it wasn't spilled because this block's total need is 0.
4513 Then some insn might have an optional reload and use this reg. */
4515 for (i = 0; i < nr; i++)
4516 /* But don't do this if the reg actually serves as an output
4517 reload reg in the current instruction. */
4519 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4521 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4522 spill_reg_store[regno + i] = 0;
4528 SET_REGNO_REG_SET (regs, regno + nr);
4531 /* Since value of X has changed,
4532 forget any value previously copied from it. */
4535 /* But don't forget a copy if this is the output reload
4536 that establishes the copy's validity. */
4538 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4539 reg_last_reload_reg[regno + nr] = 0;
4543 /* Forget the reloads marked in regset by previous function. */
4545 forget_marked_reloads (regset regs)
4548 reg_set_iterator rsi;
4549 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4551 if (reg < FIRST_PSEUDO_REGISTER
4552 /* But don't do this if the reg actually serves as an output
4553 reload reg in the current instruction. */
4555 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4557 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4558 spill_reg_store[reg] = 0;
4561 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4562 reg_last_reload_reg[reg] = 0;
4566 /* The following HARD_REG_SETs indicate when each hard register is
4567 used for a reload of various parts of the current insn. */
4569 /* If reg is unavailable for all reloads. */
4570 static HARD_REG_SET reload_reg_unavailable;
4571 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4572 static HARD_REG_SET reload_reg_used;
4573 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4574 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4575 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4576 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4577 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4578 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4579 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4580 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4581 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4582 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4583 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4584 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4585 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4586 static HARD_REG_SET reload_reg_used_in_op_addr;
4587 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4588 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4589 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4590 static HARD_REG_SET reload_reg_used_in_insn;
4591 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4592 static HARD_REG_SET reload_reg_used_in_other_addr;
4594 /* If reg is in use as a reload reg for any sort of reload. */
4595 static HARD_REG_SET reload_reg_used_at_all;
4597 /* If reg is use as an inherited reload. We just mark the first register
4599 static HARD_REG_SET reload_reg_used_for_inherit;
4601 /* Records which hard regs are used in any way, either as explicit use or
4602 by being allocated to a pseudo during any point of the current insn. */
4603 static HARD_REG_SET reg_used_in_insn;
4605 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4606 TYPE. MODE is used to indicate how many consecutive regs are
4610 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4611 enum machine_mode mode)
4613 unsigned int nregs = hard_regno_nregs[regno][mode];
4616 for (i = regno; i < nregs + regno; i++)
4621 SET_HARD_REG_BIT (reload_reg_used, i);
4624 case RELOAD_FOR_INPUT_ADDRESS:
4625 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4628 case RELOAD_FOR_INPADDR_ADDRESS:
4629 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4632 case RELOAD_FOR_OUTPUT_ADDRESS:
4633 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4636 case RELOAD_FOR_OUTADDR_ADDRESS:
4637 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4640 case RELOAD_FOR_OPERAND_ADDRESS:
4641 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4644 case RELOAD_FOR_OPADDR_ADDR:
4645 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4648 case RELOAD_FOR_OTHER_ADDRESS:
4649 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4652 case RELOAD_FOR_INPUT:
4653 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4656 case RELOAD_FOR_OUTPUT:
4657 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4660 case RELOAD_FOR_INSN:
4661 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4665 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4669 /* Similarly, but show REGNO is no longer in use for a reload. */
4672 clear_reload_reg_in_use (unsigned int regno, int opnum,
4673 enum reload_type type, enum machine_mode mode)
4675 unsigned int nregs = hard_regno_nregs[regno][mode];
4676 unsigned int start_regno, end_regno, r;
4678 /* A complication is that for some reload types, inheritance might
4679 allow multiple reloads of the same types to share a reload register.
4680 We set check_opnum if we have to check only reloads with the same
4681 operand number, and check_any if we have to check all reloads. */
4682 int check_opnum = 0;
4684 HARD_REG_SET *used_in_set;
4689 used_in_set = &reload_reg_used;
4692 case RELOAD_FOR_INPUT_ADDRESS:
4693 used_in_set = &reload_reg_used_in_input_addr[opnum];
4696 case RELOAD_FOR_INPADDR_ADDRESS:
4698 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4701 case RELOAD_FOR_OUTPUT_ADDRESS:
4702 used_in_set = &reload_reg_used_in_output_addr[opnum];
4705 case RELOAD_FOR_OUTADDR_ADDRESS:
4707 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4710 case RELOAD_FOR_OPERAND_ADDRESS:
4711 used_in_set = &reload_reg_used_in_op_addr;
4714 case RELOAD_FOR_OPADDR_ADDR:
4716 used_in_set = &reload_reg_used_in_op_addr_reload;
4719 case RELOAD_FOR_OTHER_ADDRESS:
4720 used_in_set = &reload_reg_used_in_other_addr;
4724 case RELOAD_FOR_INPUT:
4725 used_in_set = &reload_reg_used_in_input[opnum];
4728 case RELOAD_FOR_OUTPUT:
4729 used_in_set = &reload_reg_used_in_output[opnum];
4732 case RELOAD_FOR_INSN:
4733 used_in_set = &reload_reg_used_in_insn;
4738 /* We resolve conflicts with remaining reloads of the same type by
4739 excluding the intervals of reload registers by them from the
4740 interval of freed reload registers. Since we only keep track of
4741 one set of interval bounds, we might have to exclude somewhat
4742 more than what would be necessary if we used a HARD_REG_SET here.
4743 But this should only happen very infrequently, so there should
4744 be no reason to worry about it. */
4746 start_regno = regno;
4747 end_regno = regno + nregs;
4748 if (check_opnum || check_any)
4750 for (i = n_reloads - 1; i >= 0; i--)
4752 if (rld[i].when_needed == type
4753 && (check_any || rld[i].opnum == opnum)
4756 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4757 unsigned int conflict_end
4758 = end_hard_regno (rld[i].mode, conflict_start);
4760 /* If there is an overlap with the first to-be-freed register,
4761 adjust the interval start. */
4762 if (conflict_start <= start_regno && conflict_end > start_regno)
4763 start_regno = conflict_end;
4764 /* Otherwise, if there is a conflict with one of the other
4765 to-be-freed registers, adjust the interval end. */
4766 if (conflict_start > start_regno && conflict_start < end_regno)
4767 end_regno = conflict_start;
4772 for (r = start_regno; r < end_regno; r++)
4773 CLEAR_HARD_REG_BIT (*used_in_set, r);
4776 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4777 specified by OPNUM and TYPE. */
4780 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4784 /* In use for a RELOAD_OTHER means it's not available for anything. */
4785 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4786 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4792 /* In use for anything means we can't use it for RELOAD_OTHER. */
4793 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4794 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4795 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4796 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4799 for (i = 0; i < reload_n_operands; i++)
4800 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4801 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4802 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4803 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4804 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4805 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4810 case RELOAD_FOR_INPUT:
4811 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4812 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4815 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4818 /* If it is used for some other input, can't use it. */
4819 for (i = 0; i < reload_n_operands; i++)
4820 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4823 /* If it is used in a later operand's address, can't use it. */
4824 for (i = opnum + 1; i < reload_n_operands; i++)
4825 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4826 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4831 case RELOAD_FOR_INPUT_ADDRESS:
4832 /* Can't use a register if it is used for an input address for this
4833 operand or used as an input in an earlier one. */
4834 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4835 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4838 for (i = 0; i < opnum; i++)
4839 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4844 case RELOAD_FOR_INPADDR_ADDRESS:
4845 /* Can't use a register if it is used for an input address
4846 for this operand or used as an input in an earlier
4848 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4851 for (i = 0; i < opnum; i++)
4852 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4857 case RELOAD_FOR_OUTPUT_ADDRESS:
4858 /* Can't use a register if it is used for an output address for this
4859 operand or used as an output in this or a later operand. Note
4860 that multiple output operands are emitted in reverse order, so
4861 the conflicting ones are those with lower indices. */
4862 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4865 for (i = 0; i <= opnum; i++)
4866 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4871 case RELOAD_FOR_OUTADDR_ADDRESS:
4872 /* Can't use a register if it is used for an output address
4873 for this operand or used as an output in this or a
4874 later operand. Note that multiple output operands are
4875 emitted in reverse order, so the conflicting ones are
4876 those with lower indices. */
4877 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4880 for (i = 0; i <= opnum; i++)
4881 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4886 case RELOAD_FOR_OPERAND_ADDRESS:
4887 for (i = 0; i < reload_n_operands; i++)
4888 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4891 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4892 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4894 case RELOAD_FOR_OPADDR_ADDR:
4895 for (i = 0; i < reload_n_operands; i++)
4896 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4899 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4901 case RELOAD_FOR_OUTPUT:
4902 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4903 outputs, or an operand address for this or an earlier output.
4904 Note that multiple output operands are emitted in reverse order,
4905 so the conflicting ones are those with higher indices. */
4906 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4909 for (i = 0; i < reload_n_operands; i++)
4910 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4913 for (i = opnum; i < reload_n_operands; i++)
4914 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4915 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4920 case RELOAD_FOR_INSN:
4921 for (i = 0; i < reload_n_operands; i++)
4922 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4923 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4926 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4927 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4929 case RELOAD_FOR_OTHER_ADDRESS:
4930 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4937 /* Return 1 if the value in reload reg REGNO, as used by a reload
4938 needed for the part of the insn specified by OPNUM and TYPE,
4939 is still available in REGNO at the end of the insn.
4941 We can assume that the reload reg was already tested for availability
4942 at the time it is needed, and we should not check this again,
4943 in case the reg has already been marked in use. */
4946 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4953 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4954 its value must reach the end. */
4957 /* If this use is for part of the insn,
4958 its value reaches if no subsequent part uses the same register.
4959 Just like the above function, don't try to do this with lots
4962 case RELOAD_FOR_OTHER_ADDRESS:
4963 /* Here we check for everything else, since these don't conflict
4964 with anything else and everything comes later. */
4966 for (i = 0; i < reload_n_operands; i++)
4967 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4968 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4969 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4970 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4971 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4972 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4975 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4976 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4977 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4978 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4980 case RELOAD_FOR_INPUT_ADDRESS:
4981 case RELOAD_FOR_INPADDR_ADDRESS:
4982 /* Similar, except that we check only for this and subsequent inputs
4983 and the address of only subsequent inputs and we do not need
4984 to check for RELOAD_OTHER objects since they are known not to
4987 for (i = opnum; i < reload_n_operands; i++)
4988 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4991 for (i = opnum + 1; i < reload_n_operands; i++)
4992 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4993 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4996 for (i = 0; i < reload_n_operands; i++)
4997 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4998 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4999 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5002 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5005 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5006 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5007 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5009 case RELOAD_FOR_INPUT:
5010 /* Similar to input address, except we start at the next operand for
5011 both input and input address and we do not check for
5012 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5015 for (i = opnum + 1; i < reload_n_operands; i++)
5016 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5017 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5018 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5021 /* ... fall through ... */
5023 case RELOAD_FOR_OPERAND_ADDRESS:
5024 /* Check outputs and their addresses. */
5026 for (i = 0; i < reload_n_operands; i++)
5027 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5028 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5029 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5032 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5034 case RELOAD_FOR_OPADDR_ADDR:
5035 for (i = 0; i < reload_n_operands; i++)
5036 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5037 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5038 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5041 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5042 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5043 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5045 case RELOAD_FOR_INSN:
5046 /* These conflict with other outputs with RELOAD_OTHER. So
5047 we need only check for output addresses. */
5049 opnum = reload_n_operands;
5051 /* ... fall through ... */
5053 case RELOAD_FOR_OUTPUT:
5054 case RELOAD_FOR_OUTPUT_ADDRESS:
5055 case RELOAD_FOR_OUTADDR_ADDRESS:
5056 /* We already know these can't conflict with a later output. So the
5057 only thing to check are later output addresses.
5058 Note that multiple output operands are emitted in reverse order,
5059 so the conflicting ones are those with lower indices. */
5060 for (i = 0; i < opnum; i++)
5061 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5062 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5072 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5073 every register in the range [REGNO, REGNO + NREGS). */
5076 reload_regs_reach_end_p (unsigned int regno, int nregs,
5077 int opnum, enum reload_type type)
5081 for (i = 0; i < nregs; i++)
5082 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5088 /* Returns whether R1 and R2 are uniquely chained: the value of one
5089 is used by the other, and that value is not used by any other
5090 reload for this insn. This is used to partially undo the decision
5091 made in find_reloads when in the case of multiple
5092 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5093 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5094 reloads. This code tries to avoid the conflict created by that
5095 change. It might be cleaner to explicitly keep track of which
5096 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5097 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5098 this after the fact. */
5100 reloads_unique_chain_p (int r1, int r2)
5104 /* We only check input reloads. */
5105 if (! rld[r1].in || ! rld[r2].in)
5108 /* Avoid anything with output reloads. */
5109 if (rld[r1].out || rld[r2].out)
5112 /* "chained" means one reload is a component of the other reload,
5113 not the same as the other reload. */
5114 if (rld[r1].opnum != rld[r2].opnum
5115 || rtx_equal_p (rld[r1].in, rld[r2].in)
5116 || rld[r1].optional || rld[r2].optional
5117 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5118 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5121 for (i = 0; i < n_reloads; i ++)
5122 /* Look for input reloads that aren't our two */
5123 if (i != r1 && i != r2 && rld[i].in)
5125 /* If our reload is mentioned at all, it isn't a simple chain. */
5126 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5133 /* The recursive function change all occurrences of WHAT in *WHERE
5136 substitute (rtx *where, const_rtx what, rtx repl)
5145 if (*where == what || rtx_equal_p (*where, what))
5151 code = GET_CODE (*where);
5152 fmt = GET_RTX_FORMAT (code);
5153 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5159 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5160 substitute (&XVECEXP (*where, i, j), what, repl);
5162 else if (fmt[i] == 'e')
5163 substitute (&XEXP (*where, i), what, repl);
5167 /* The function returns TRUE if chain of reload R1 and R2 (in any
5168 order) can be evaluated without usage of intermediate register for
5169 the reload containing another reload. It is important to see
5170 gen_reload to understand what the function is trying to do. As an
5171 example, let us have reload chain
5174 r1: <something> + const
5176 and reload R2 got reload reg HR. The function returns true if
5177 there is a correct insn HR = HR + <something>. Otherwise,
5178 gen_reload will use intermediate register (and this is the reload
5179 reg for R1) to reload <something>.
5181 We need this function to find a conflict for chain reloads. In our
5182 example, if HR = HR + <something> is incorrect insn, then we cannot
5183 use HR as a reload register for R2. If we do use it then we get a
5192 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5196 rtx out, in, tem, insn;
5197 rtx last = get_last_insn ();
5199 /* Make r2 a component of r1. */
5200 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5206 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5207 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5208 gcc_assert (regno >= 0);
5209 out = gen_rtx_REG (rld[r1].mode, regno);
5210 in = copy_rtx (rld[r1].in);
5211 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5213 /* If IN is a paradoxical SUBREG, remove it and try to put the
5214 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5215 if (GET_CODE (in) == SUBREG
5216 && (GET_MODE_SIZE (GET_MODE (in))
5217 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5218 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5219 in = SUBREG_REG (in), out = tem;
5221 if (GET_CODE (in) == PLUS
5222 && (REG_P (XEXP (in, 0))
5223 || GET_CODE (XEXP (in, 0)) == SUBREG
5224 || MEM_P (XEXP (in, 0)))
5225 && (REG_P (XEXP (in, 1))
5226 || GET_CODE (XEXP (in, 1)) == SUBREG
5227 || CONSTANT_P (XEXP (in, 1))
5228 || MEM_P (XEXP (in, 1))))
5230 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5231 code = recog_memoized (insn);
5236 extract_insn (insn);
5237 /* We want constrain operands to treat this insn strictly in
5238 its validity determination, i.e., the way it would after
5239 reload has completed. */
5240 result = constrain_operands (1);
5243 delete_insns_since (last);
5247 /* It looks like other cases in gen_reload are not possible for
5248 chain reloads or do need an intermediate hard registers. */
5252 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5255 This function uses the same algorithm as reload_reg_free_p above. */
5258 reloads_conflict (int r1, int r2)
5260 enum reload_type r1_type = rld[r1].when_needed;
5261 enum reload_type r2_type = rld[r2].when_needed;
5262 int r1_opnum = rld[r1].opnum;
5263 int r2_opnum = rld[r2].opnum;
5265 /* RELOAD_OTHER conflicts with everything. */
5266 if (r2_type == RELOAD_OTHER)
5269 /* Otherwise, check conflicts differently for each type. */
5273 case RELOAD_FOR_INPUT:
5274 return (r2_type == RELOAD_FOR_INSN
5275 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5276 || r2_type == RELOAD_FOR_OPADDR_ADDR
5277 || r2_type == RELOAD_FOR_INPUT
5278 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5279 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5280 && r2_opnum > r1_opnum));
5282 case RELOAD_FOR_INPUT_ADDRESS:
5283 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5284 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5286 case RELOAD_FOR_INPADDR_ADDRESS:
5287 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5288 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5290 case RELOAD_FOR_OUTPUT_ADDRESS:
5291 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5292 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5294 case RELOAD_FOR_OUTADDR_ADDRESS:
5295 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5296 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5298 case RELOAD_FOR_OPERAND_ADDRESS:
5299 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5300 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5301 && (!reloads_unique_chain_p (r1, r2)
5302 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5304 case RELOAD_FOR_OPADDR_ADDR:
5305 return (r2_type == RELOAD_FOR_INPUT
5306 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5308 case RELOAD_FOR_OUTPUT:
5309 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5310 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5311 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5312 && r2_opnum >= r1_opnum));
5314 case RELOAD_FOR_INSN:
5315 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5316 || r2_type == RELOAD_FOR_INSN
5317 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5319 case RELOAD_FOR_OTHER_ADDRESS:
5320 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5330 /* Indexed by reload number, 1 if incoming value
5331 inherited from previous insns. */
5332 static char reload_inherited[MAX_RELOADS];
5334 /* For an inherited reload, this is the insn the reload was inherited from,
5335 if we know it. Otherwise, this is 0. */
5336 static rtx reload_inheritance_insn[MAX_RELOADS];
5338 /* If nonzero, this is a place to get the value of the reload,
5339 rather than using reload_in. */
5340 static rtx reload_override_in[MAX_RELOADS];
5342 /* For each reload, the hard register number of the register used,
5343 or -1 if we did not need a register for this reload. */
5344 static int reload_spill_index[MAX_RELOADS];
5346 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5347 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5349 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5350 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5352 /* Subroutine of free_for_value_p, used to check a single register.
5353 START_REGNO is the starting regno of the full reload register
5354 (possibly comprising multiple hard registers) that we are considering. */
5357 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5358 enum reload_type type, rtx value, rtx out,
5359 int reloadnum, int ignore_address_reloads)
5362 /* Set if we see an input reload that must not share its reload register
5363 with any new earlyclobber, but might otherwise share the reload
5364 register with an output or input-output reload. */
5365 int check_earlyclobber = 0;
5369 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5372 if (out == const0_rtx)
5378 /* We use some pseudo 'time' value to check if the lifetimes of the
5379 new register use would overlap with the one of a previous reload
5380 that is not read-only or uses a different value.
5381 The 'time' used doesn't have to be linear in any shape or form, just
5383 Some reload types use different 'buckets' for each operand.
5384 So there are MAX_RECOG_OPERANDS different time values for each
5386 We compute TIME1 as the time when the register for the prospective
5387 new reload ceases to be live, and TIME2 for each existing
5388 reload as the time when that the reload register of that reload
5390 Where there is little to be gained by exact lifetime calculations,
5391 we just make conservative assumptions, i.e. a longer lifetime;
5392 this is done in the 'default:' cases. */
5395 case RELOAD_FOR_OTHER_ADDRESS:
5396 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5397 time1 = copy ? 0 : 1;
5400 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5402 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5403 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5404 respectively, to the time values for these, we get distinct time
5405 values. To get distinct time values for each operand, we have to
5406 multiply opnum by at least three. We round that up to four because
5407 multiply by four is often cheaper. */
5408 case RELOAD_FOR_INPADDR_ADDRESS:
5409 time1 = opnum * 4 + 2;
5411 case RELOAD_FOR_INPUT_ADDRESS:
5412 time1 = opnum * 4 + 3;
5414 case RELOAD_FOR_INPUT:
5415 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5416 executes (inclusive). */
5417 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5419 case RELOAD_FOR_OPADDR_ADDR:
5421 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5422 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5424 case RELOAD_FOR_OPERAND_ADDRESS:
5425 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5427 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5429 case RELOAD_FOR_OUTADDR_ADDRESS:
5430 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5432 case RELOAD_FOR_OUTPUT_ADDRESS:
5433 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5436 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5439 for (i = 0; i < n_reloads; i++)
5441 rtx reg = rld[i].reg_rtx;
5442 if (reg && REG_P (reg)
5443 && ((unsigned) regno - true_regnum (reg)
5444 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5447 rtx other_input = rld[i].in;
5449 /* If the other reload loads the same input value, that
5450 will not cause a conflict only if it's loading it into
5451 the same register. */
5452 if (true_regnum (reg) != start_regno)
5453 other_input = NULL_RTX;
5454 if (! other_input || ! rtx_equal_p (other_input, value)
5455 || rld[i].out || out)
5458 switch (rld[i].when_needed)
5460 case RELOAD_FOR_OTHER_ADDRESS:
5463 case RELOAD_FOR_INPADDR_ADDRESS:
5464 /* find_reloads makes sure that a
5465 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5466 by at most one - the first -
5467 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5468 address reload is inherited, the address address reload
5469 goes away, so we can ignore this conflict. */
5470 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5471 && ignore_address_reloads
5472 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5473 Then the address address is still needed to store
5474 back the new address. */
5475 && ! rld[reloadnum].out)
5477 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5478 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5480 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5481 && ignore_address_reloads
5482 /* Unless we are reloading an auto_inc expression. */
5483 && ! rld[reloadnum].out)
5485 time2 = rld[i].opnum * 4 + 2;
5487 case RELOAD_FOR_INPUT_ADDRESS:
5488 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5489 && ignore_address_reloads
5490 && ! rld[reloadnum].out)
5492 time2 = rld[i].opnum * 4 + 3;
5494 case RELOAD_FOR_INPUT:
5495 time2 = rld[i].opnum * 4 + 4;
5496 check_earlyclobber = 1;
5498 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5499 == MAX_RECOG_OPERAND * 4 */
5500 case RELOAD_FOR_OPADDR_ADDR:
5501 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5502 && ignore_address_reloads
5503 && ! rld[reloadnum].out)
5505 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5507 case RELOAD_FOR_OPERAND_ADDRESS:
5508 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5509 check_earlyclobber = 1;
5511 case RELOAD_FOR_INSN:
5512 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5514 case RELOAD_FOR_OUTPUT:
5515 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5516 instruction is executed. */
5517 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5519 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5520 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5522 case RELOAD_FOR_OUTADDR_ADDRESS:
5523 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5524 && ignore_address_reloads
5525 && ! rld[reloadnum].out)
5527 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5529 case RELOAD_FOR_OUTPUT_ADDRESS:
5530 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5533 /* If there is no conflict in the input part, handle this
5534 like an output reload. */
5535 if (! rld[i].in || rtx_equal_p (other_input, value))
5537 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5538 /* Earlyclobbered outputs must conflict with inputs. */
5539 if (earlyclobber_operand_p (rld[i].out))
5540 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5545 /* RELOAD_OTHER might be live beyond instruction execution,
5546 but this is not obvious when we set time2 = 1. So check
5547 here if there might be a problem with the new reload
5548 clobbering the register used by the RELOAD_OTHER. */
5556 && (! rld[i].in || rld[i].out
5557 || ! rtx_equal_p (other_input, value)))
5558 || (out && rld[reloadnum].out_reg
5559 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5565 /* Earlyclobbered outputs must conflict with inputs. */
5566 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5572 /* Return 1 if the value in reload reg REGNO, as used by a reload
5573 needed for the part of the insn specified by OPNUM and TYPE,
5574 may be used to load VALUE into it.
5576 MODE is the mode in which the register is used, this is needed to
5577 determine how many hard regs to test.
5579 Other read-only reloads with the same value do not conflict
5580 unless OUT is nonzero and these other reloads have to live while
5581 output reloads live.
5582 If OUT is CONST0_RTX, this is a special case: it means that the
5583 test should not be for using register REGNO as reload register, but
5584 for copying from register REGNO into the reload register.
5586 RELOADNUM is the number of the reload we want to load this value for;
5587 a reload does not conflict with itself.
5589 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5590 reloads that load an address for the very reload we are considering.
5592 The caller has to make sure that there is no conflict with the return
5596 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5597 enum reload_type type, rtx value, rtx out, int reloadnum,
5598 int ignore_address_reloads)
5600 int nregs = hard_regno_nregs[regno][mode];
5602 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5603 value, out, reloadnum,
5604 ignore_address_reloads))
5609 /* Return nonzero if the rtx X is invariant over the current function. */
5610 /* ??? Actually, the places where we use this expect exactly what is
5611 tested here, and not everything that is function invariant. In
5612 particular, the frame pointer and arg pointer are special cased;
5613 pic_offset_table_rtx is not, and we must not spill these things to
5617 function_invariant_p (const_rtx x)
5621 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5623 if (GET_CODE (x) == PLUS
5624 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5625 && CONSTANT_P (XEXP (x, 1)))
5630 /* Determine whether the reload reg X overlaps any rtx'es used for
5631 overriding inheritance. Return nonzero if so. */
5634 conflicts_with_override (rtx x)
5637 for (i = 0; i < n_reloads; i++)
5638 if (reload_override_in[i]
5639 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5644 /* Give an error message saying we failed to find a reload for INSN,
5645 and clear out reload R. */
5647 failed_reload (rtx insn, int r)
5649 if (asm_noperands (PATTERN (insn)) < 0)
5650 /* It's the compiler's fault. */
5651 fatal_insn ("could not find a spill register", insn);
5653 /* It's the user's fault; the operand's mode and constraint
5654 don't match. Disable this reload so we don't crash in final. */
5655 error_for_asm (insn,
5656 "%<asm%> operand constraint incompatible with operand size");
5660 rld[r].optional = 1;
5661 rld[r].secondary_p = 1;
5664 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5665 for reload R. If it's valid, get an rtx for it. Return nonzero if
5668 set_reload_reg (int i, int r)
5671 rtx reg = spill_reg_rtx[i];
5673 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5674 spill_reg_rtx[i] = reg
5675 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5677 regno = true_regnum (reg);
5679 /* Detect when the reload reg can't hold the reload mode.
5680 This used to be one `if', but Sequent compiler can't handle that. */
5681 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5683 enum machine_mode test_mode = VOIDmode;
5685 test_mode = GET_MODE (rld[r].in);
5686 /* If rld[r].in has VOIDmode, it means we will load it
5687 in whatever mode the reload reg has: to wit, rld[r].mode.
5688 We have already tested that for validity. */
5689 /* Aside from that, we need to test that the expressions
5690 to reload from or into have modes which are valid for this
5691 reload register. Otherwise the reload insns would be invalid. */
5692 if (! (rld[r].in != 0 && test_mode != VOIDmode
5693 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5694 if (! (rld[r].out != 0
5695 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5697 /* The reg is OK. */
5700 /* Mark as in use for this insn the reload regs we use
5702 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5703 rld[r].when_needed, rld[r].mode);
5705 rld[r].reg_rtx = reg;
5706 reload_spill_index[r] = spill_regs[i];
5713 /* Find a spill register to use as a reload register for reload R.
5714 LAST_RELOAD is nonzero if this is the last reload for the insn being
5717 Set rld[R].reg_rtx to the register allocated.
5719 We return 1 if successful, or 0 if we couldn't find a spill reg and
5720 we didn't change anything. */
5723 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5728 /* If we put this reload ahead, thinking it is a group,
5729 then insist on finding a group. Otherwise we can grab a
5730 reg that some other reload needs.
5731 (That can happen when we have a 68000 DATA_OR_FP_REG
5732 which is a group of data regs or one fp reg.)
5733 We need not be so restrictive if there are no more reloads
5736 ??? Really it would be nicer to have smarter handling
5737 for that kind of reg class, where a problem like this is normal.
5738 Perhaps those classes should be avoided for reloading
5739 by use of more alternatives. */
5741 int force_group = rld[r].nregs > 1 && ! last_reload;
5743 /* If we want a single register and haven't yet found one,
5744 take any reg in the right class and not in use.
5745 If we want a consecutive group, here is where we look for it.
5747 We use two passes so we can first look for reload regs to
5748 reuse, which are already in use for other reloads in this insn,
5749 and only then use additional registers.
5750 I think that maximizing reuse is needed to make sure we don't
5751 run out of reload regs. Suppose we have three reloads, and
5752 reloads A and B can share regs. These need two regs.
5753 Suppose A and B are given different regs.
5754 That leaves none for C. */
5755 for (pass = 0; pass < 2; pass++)
5757 /* I is the index in spill_regs.
5758 We advance it round-robin between insns to use all spill regs
5759 equally, so that inherited reloads have a chance
5760 of leapfrogging each other. */
5764 for (count = 0; count < n_spills; count++)
5766 int rclass = (int) rld[r].rclass;
5772 regnum = spill_regs[i];
5774 if ((reload_reg_free_p (regnum, rld[r].opnum,
5777 /* We check reload_reg_used to make sure we
5778 don't clobber the return register. */
5779 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5780 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5781 rld[r].when_needed, rld[r].in,
5783 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5784 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5785 /* Look first for regs to share, then for unshared. But
5786 don't share regs used for inherited reloads; they are
5787 the ones we want to preserve. */
5789 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5791 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5794 int nr = hard_regno_nregs[regnum][rld[r].mode];
5795 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5796 (on 68000) got us two FP regs. If NR is 1,
5797 we would reject both of them. */
5800 /* If we need only one reg, we have already won. */
5803 /* But reject a single reg if we demand a group. */
5808 /* Otherwise check that as many consecutive regs as we need
5809 are available here. */
5812 int regno = regnum + nr - 1;
5813 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5814 && spill_reg_order[regno] >= 0
5815 && reload_reg_free_p (regno, rld[r].opnum,
5816 rld[r].when_needed)))
5825 /* If we found something on pass 1, omit pass 2. */
5826 if (count < n_spills)
5830 /* We should have found a spill register by now. */
5831 if (count >= n_spills)
5834 /* I is the index in SPILL_REG_RTX of the reload register we are to
5835 allocate. Get an rtx for it and find its register number. */
5837 return set_reload_reg (i, r);
5840 /* Initialize all the tables needed to allocate reload registers.
5841 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5842 is the array we use to restore the reg_rtx field for every reload. */
5845 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5849 for (i = 0; i < n_reloads; i++)
5850 rld[i].reg_rtx = save_reload_reg_rtx[i];
5852 memset (reload_inherited, 0, MAX_RELOADS);
5853 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5854 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5856 CLEAR_HARD_REG_SET (reload_reg_used);
5857 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5858 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5859 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5860 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5861 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5863 CLEAR_HARD_REG_SET (reg_used_in_insn);
5866 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5867 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5868 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5869 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5870 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5871 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5874 for (i = 0; i < reload_n_operands; i++)
5876 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5877 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5878 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5879 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5880 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5881 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5884 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5886 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5888 for (i = 0; i < n_reloads; i++)
5889 /* If we have already decided to use a certain register,
5890 don't use it in another way. */
5892 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5893 rld[i].when_needed, rld[i].mode);
5896 /* Assign hard reg targets for the pseudo-registers we must reload
5897 into hard regs for this insn.
5898 Also output the instructions to copy them in and out of the hard regs.
5900 For machines with register classes, we are responsible for
5901 finding a reload reg in the proper class. */
5904 choose_reload_regs (struct insn_chain *chain)
5906 rtx insn = chain->insn;
5908 unsigned int max_group_size = 1;
5909 enum reg_class group_class = NO_REGS;
5910 int pass, win, inheritance;
5912 rtx save_reload_reg_rtx[MAX_RELOADS];
5914 /* In order to be certain of getting the registers we need,
5915 we must sort the reloads into order of increasing register class.
5916 Then our grabbing of reload registers will parallel the process
5917 that provided the reload registers.
5919 Also note whether any of the reloads wants a consecutive group of regs.
5920 If so, record the maximum size of the group desired and what
5921 register class contains all the groups needed by this insn. */
5923 for (j = 0; j < n_reloads; j++)
5925 reload_order[j] = j;
5926 if (rld[j].reg_rtx != NULL_RTX)
5928 gcc_assert (REG_P (rld[j].reg_rtx)
5929 && HARD_REGISTER_P (rld[j].reg_rtx));
5930 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5933 reload_spill_index[j] = -1;
5935 if (rld[j].nregs > 1)
5937 max_group_size = MAX (rld[j].nregs, max_group_size);
5939 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5942 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5946 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5948 /* If -O, try first with inheritance, then turning it off.
5949 If not -O, don't do inheritance.
5950 Using inheritance when not optimizing leads to paradoxes
5951 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5952 because one side of the comparison might be inherited. */
5954 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5956 choose_reload_regs_init (chain, save_reload_reg_rtx);
5958 /* Process the reloads in order of preference just found.
5959 Beyond this point, subregs can be found in reload_reg_rtx.
5961 This used to look for an existing reloaded home for all of the
5962 reloads, and only then perform any new reloads. But that could lose
5963 if the reloads were done out of reg-class order because a later
5964 reload with a looser constraint might have an old home in a register
5965 needed by an earlier reload with a tighter constraint.
5967 To solve this, we make two passes over the reloads, in the order
5968 described above. In the first pass we try to inherit a reload
5969 from a previous insn. If there is a later reload that needs a
5970 class that is a proper subset of the class being processed, we must
5971 also allocate a spill register during the first pass.
5973 Then make a second pass over the reloads to allocate any reloads
5974 that haven't been given registers yet. */
5976 for (j = 0; j < n_reloads; j++)
5978 int r = reload_order[j];
5979 rtx search_equiv = NULL_RTX;
5981 /* Ignore reloads that got marked inoperative. */
5982 if (rld[r].out == 0 && rld[r].in == 0
5983 && ! rld[r].secondary_p)
5986 /* If find_reloads chose to use reload_in or reload_out as a reload
5987 register, we don't need to chose one. Otherwise, try even if it
5988 found one since we might save an insn if we find the value lying
5990 Try also when reload_in is a pseudo without a hard reg. */
5991 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5992 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5993 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5994 && !MEM_P (rld[r].in)
5995 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5998 #if 0 /* No longer needed for correct operation.
5999 It might give better code, or might not; worth an experiment? */
6000 /* If this is an optional reload, we can't inherit from earlier insns
6001 until we are sure that any non-optional reloads have been allocated.
6002 The following code takes advantage of the fact that optional reloads
6003 are at the end of reload_order. */
6004 if (rld[r].optional != 0)
6005 for (i = 0; i < j; i++)
6006 if ((rld[reload_order[i]].out != 0
6007 || rld[reload_order[i]].in != 0
6008 || rld[reload_order[i]].secondary_p)
6009 && ! rld[reload_order[i]].optional
6010 && rld[reload_order[i]].reg_rtx == 0)
6011 allocate_reload_reg (chain, reload_order[i], 0);
6014 /* First see if this pseudo is already available as reloaded
6015 for a previous insn. We cannot try to inherit for reloads
6016 that are smaller than the maximum number of registers needed
6017 for groups unless the register we would allocate cannot be used
6020 We could check here to see if this is a secondary reload for
6021 an object that is already in a register of the desired class.
6022 This would avoid the need for the secondary reload register.
6023 But this is complex because we can't easily determine what
6024 objects might want to be loaded via this reload. So let a
6025 register be allocated here. In `emit_reload_insns' we suppress
6026 one of the loads in the case described above. */
6032 enum machine_mode mode = VOIDmode;
6036 else if (REG_P (rld[r].in))
6038 regno = REGNO (rld[r].in);
6039 mode = GET_MODE (rld[r].in);
6041 else if (REG_P (rld[r].in_reg))
6043 regno = REGNO (rld[r].in_reg);
6044 mode = GET_MODE (rld[r].in_reg);
6046 else if (GET_CODE (rld[r].in_reg) == SUBREG
6047 && REG_P (SUBREG_REG (rld[r].in_reg)))
6049 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6050 if (regno < FIRST_PSEUDO_REGISTER)
6051 regno = subreg_regno (rld[r].in_reg);
6053 byte = SUBREG_BYTE (rld[r].in_reg);
6054 mode = GET_MODE (rld[r].in_reg);
6057 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6058 && REG_P (XEXP (rld[r].in_reg, 0)))
6060 regno = REGNO (XEXP (rld[r].in_reg, 0));
6061 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6062 rld[r].out = rld[r].in;
6066 /* This won't work, since REGNO can be a pseudo reg number.
6067 Also, it takes much more hair to keep track of all the things
6068 that can invalidate an inherited reload of part of a pseudoreg. */
6069 else if (GET_CODE (rld[r].in) == SUBREG
6070 && REG_P (SUBREG_REG (rld[r].in)))
6071 regno = subreg_regno (rld[r].in);
6075 && reg_last_reload_reg[regno] != 0
6076 #ifdef CANNOT_CHANGE_MODE_CLASS
6077 /* Verify that the register it's in can be used in
6079 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6080 GET_MODE (reg_last_reload_reg[regno]),
6085 enum reg_class rclass = rld[r].rclass, last_class;
6086 rtx last_reg = reg_last_reload_reg[regno];
6087 enum machine_mode need_mode;
6089 i = REGNO (last_reg);
6090 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6091 last_class = REGNO_REG_CLASS (i);
6097 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
6098 + byte * BITS_PER_UNIT,
6099 GET_MODE_CLASS (mode));
6101 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6102 >= GET_MODE_SIZE (need_mode))
6103 && reg_reloaded_contents[i] == regno
6104 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6105 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6106 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6107 /* Even if we can't use this register as a reload
6108 register, we might use it for reload_override_in,
6109 if copying it to the desired class is cheap
6111 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6112 < MEMORY_MOVE_COST (mode, rclass, 1))
6113 && (secondary_reload_class (1, rclass, mode,
6116 #ifdef SECONDARY_MEMORY_NEEDED
6117 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6122 && (rld[r].nregs == max_group_size
6123 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6125 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6126 rld[r].when_needed, rld[r].in,
6129 /* If a group is needed, verify that all the subsequent
6130 registers still have their values intact. */
6131 int nr = hard_regno_nregs[i][rld[r].mode];
6134 for (k = 1; k < nr; k++)
6135 if (reg_reloaded_contents[i + k] != regno
6136 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6144 last_reg = (GET_MODE (last_reg) == mode
6145 ? last_reg : gen_rtx_REG (mode, i));
6148 for (k = 0; k < nr; k++)
6149 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6152 /* We found a register that contains the
6153 value we need. If this register is the
6154 same as an `earlyclobber' operand of the
6155 current insn, just mark it as a place to
6156 reload from since we can't use it as the
6157 reload register itself. */
6159 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6160 if (reg_overlap_mentioned_for_reload_p
6161 (reg_last_reload_reg[regno],
6162 reload_earlyclobbers[i1]))
6165 if (i1 != n_earlyclobbers
6166 || ! (free_for_value_p (i, rld[r].mode,
6168 rld[r].when_needed, rld[r].in,
6170 /* Don't use it if we'd clobber a pseudo reg. */
6171 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6173 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6174 /* Don't clobber the frame pointer. */
6175 || (i == HARD_FRAME_POINTER_REGNUM
6176 && frame_pointer_needed
6178 /* Don't really use the inherited spill reg
6179 if we need it wider than we've got it. */
6180 || (GET_MODE_SIZE (rld[r].mode)
6181 > GET_MODE_SIZE (mode))
6184 /* If find_reloads chose reload_out as reload
6185 register, stay with it - that leaves the
6186 inherited register for subsequent reloads. */
6187 || (rld[r].out && rld[r].reg_rtx
6188 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6190 if (! rld[r].optional)
6192 reload_override_in[r] = last_reg;
6193 reload_inheritance_insn[r]
6194 = reg_reloaded_insn[i];
6200 /* We can use this as a reload reg. */
6201 /* Mark the register as in use for this part of
6203 mark_reload_reg_in_use (i,
6207 rld[r].reg_rtx = last_reg;
6208 reload_inherited[r] = 1;
6209 reload_inheritance_insn[r]
6210 = reg_reloaded_insn[i];
6211 reload_spill_index[r] = i;
6212 for (k = 0; k < nr; k++)
6213 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6221 /* Here's another way to see if the value is already lying around. */
6224 && ! reload_inherited[r]
6226 && (CONSTANT_P (rld[r].in)
6227 || GET_CODE (rld[r].in) == PLUS
6228 || REG_P (rld[r].in)
6229 || MEM_P (rld[r].in))
6230 && (rld[r].nregs == max_group_size
6231 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6232 search_equiv = rld[r].in;
6233 /* If this is an output reload from a simple move insn, look
6234 if an equivalence for the input is available. */
6235 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6237 rtx set = single_set (insn);
6240 && rtx_equal_p (rld[r].out, SET_DEST (set))
6241 && CONSTANT_P (SET_SRC (set)))
6242 search_equiv = SET_SRC (set);
6248 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6249 -1, NULL, 0, rld[r].mode);
6255 regno = REGNO (equiv);
6258 /* This must be a SUBREG of a hard register.
6259 Make a new REG since this might be used in an
6260 address and not all machines support SUBREGs
6262 gcc_assert (GET_CODE (equiv) == SUBREG);
6263 regno = subreg_regno (equiv);
6264 equiv = gen_rtx_REG (rld[r].mode, regno);
6265 /* If we choose EQUIV as the reload register, but the
6266 loop below decides to cancel the inheritance, we'll
6267 end up reloading EQUIV in rld[r].mode, not the mode
6268 it had originally. That isn't safe when EQUIV isn't
6269 available as a spill register since its value might
6270 still be live at this point. */
6271 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6272 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6277 /* If we found a spill reg, reject it unless it is free
6278 and of the desired class. */
6282 int bad_for_class = 0;
6283 int max_regno = regno + rld[r].nregs;
6285 for (i = regno; i < max_regno; i++)
6287 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6289 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6294 && ! free_for_value_p (regno, rld[r].mode,
6295 rld[r].opnum, rld[r].when_needed,
6296 rld[r].in, rld[r].out, r, 1))
6301 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6304 /* We found a register that contains the value we need.
6305 If this register is the same as an `earlyclobber' operand
6306 of the current insn, just mark it as a place to reload from
6307 since we can't use it as the reload register itself. */
6310 for (i = 0; i < n_earlyclobbers; i++)
6311 if (reg_overlap_mentioned_for_reload_p (equiv,
6312 reload_earlyclobbers[i]))
6314 if (! rld[r].optional)
6315 reload_override_in[r] = equiv;
6320 /* If the equiv register we have found is explicitly clobbered
6321 in the current insn, it depends on the reload type if we
6322 can use it, use it for reload_override_in, or not at all.
6323 In particular, we then can't use EQUIV for a
6324 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6328 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6329 switch (rld[r].when_needed)
6331 case RELOAD_FOR_OTHER_ADDRESS:
6332 case RELOAD_FOR_INPADDR_ADDRESS:
6333 case RELOAD_FOR_INPUT_ADDRESS:
6334 case RELOAD_FOR_OPADDR_ADDR:
6337 case RELOAD_FOR_INPUT:
6338 case RELOAD_FOR_OPERAND_ADDRESS:
6339 if (! rld[r].optional)
6340 reload_override_in[r] = equiv;
6346 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6347 switch (rld[r].when_needed)
6349 case RELOAD_FOR_OTHER_ADDRESS:
6350 case RELOAD_FOR_INPADDR_ADDRESS:
6351 case RELOAD_FOR_INPUT_ADDRESS:
6352 case RELOAD_FOR_OPADDR_ADDR:
6353 case RELOAD_FOR_OPERAND_ADDRESS:
6354 case RELOAD_FOR_INPUT:
6357 if (! rld[r].optional)
6358 reload_override_in[r] = equiv;
6366 /* If we found an equivalent reg, say no code need be generated
6367 to load it, and use it as our reload reg. */
6369 && (regno != HARD_FRAME_POINTER_REGNUM
6370 || !frame_pointer_needed))
6372 int nr = hard_regno_nregs[regno][rld[r].mode];
6374 rld[r].reg_rtx = equiv;
6375 reload_inherited[r] = 1;
6377 /* If reg_reloaded_valid is not set for this register,
6378 there might be a stale spill_reg_store lying around.
6379 We must clear it, since otherwise emit_reload_insns
6380 might delete the store. */
6381 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6382 spill_reg_store[regno] = NULL_RTX;
6383 /* If any of the hard registers in EQUIV are spill
6384 registers, mark them as in use for this insn. */
6385 for (k = 0; k < nr; k++)
6387 i = spill_reg_order[regno + k];
6390 mark_reload_reg_in_use (regno, rld[r].opnum,
6393 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6400 /* If we found a register to use already, or if this is an optional
6401 reload, we are done. */
6402 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6406 /* No longer needed for correct operation. Might or might
6407 not give better code on the average. Want to experiment? */
6409 /* See if there is a later reload that has a class different from our
6410 class that intersects our class or that requires less register
6411 than our reload. If so, we must allocate a register to this
6412 reload now, since that reload might inherit a previous reload
6413 and take the only available register in our class. Don't do this
6414 for optional reloads since they will force all previous reloads
6415 to be allocated. Also don't do this for reloads that have been
6418 for (i = j + 1; i < n_reloads; i++)
6420 int s = reload_order[i];
6422 if ((rld[s].in == 0 && rld[s].out == 0
6423 && ! rld[s].secondary_p)
6427 if ((rld[s].rclass != rld[r].rclass
6428 && reg_classes_intersect_p (rld[r].rclass,
6430 || rld[s].nregs < rld[r].nregs)
6437 allocate_reload_reg (chain, r, j == n_reloads - 1);
6441 /* Now allocate reload registers for anything non-optional that
6442 didn't get one yet. */
6443 for (j = 0; j < n_reloads; j++)
6445 int r = reload_order[j];
6447 /* Ignore reloads that got marked inoperative. */
6448 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6451 /* Skip reloads that already have a register allocated or are
6453 if (rld[r].reg_rtx != 0 || rld[r].optional)
6456 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6460 /* If that loop got all the way, we have won. */
6467 /* Loop around and try without any inheritance. */
6472 /* First undo everything done by the failed attempt
6473 to allocate with inheritance. */
6474 choose_reload_regs_init (chain, save_reload_reg_rtx);
6476 /* Some sanity tests to verify that the reloads found in the first
6477 pass are identical to the ones we have now. */
6478 gcc_assert (chain->n_reloads == n_reloads);
6480 for (i = 0; i < n_reloads; i++)
6482 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6484 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6485 for (j = 0; j < n_spills; j++)
6486 if (spill_regs[j] == chain->rld[i].regno)
6487 if (! set_reload_reg (j, i))
6488 failed_reload (chain->insn, i);
6492 /* If we thought we could inherit a reload, because it seemed that
6493 nothing else wanted the same reload register earlier in the insn,
6494 verify that assumption, now that all reloads have been assigned.
6495 Likewise for reloads where reload_override_in has been set. */
6497 /* If doing expensive optimizations, do one preliminary pass that doesn't
6498 cancel any inheritance, but removes reloads that have been needed only
6499 for reloads that we know can be inherited. */
6500 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6502 for (j = 0; j < n_reloads; j++)
6504 int r = reload_order[j];
6506 if (reload_inherited[r] && rld[r].reg_rtx)
6507 check_reg = rld[r].reg_rtx;
6508 else if (reload_override_in[r]
6509 && (REG_P (reload_override_in[r])
6510 || GET_CODE (reload_override_in[r]) == SUBREG))
6511 check_reg = reload_override_in[r];
6514 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6515 rld[r].opnum, rld[r].when_needed, rld[r].in,
6516 (reload_inherited[r]
6517 ? rld[r].out : const0_rtx),
6522 reload_inherited[r] = 0;
6523 reload_override_in[r] = 0;
6525 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6526 reload_override_in, then we do not need its related
6527 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6528 likewise for other reload types.
6529 We handle this by removing a reload when its only replacement
6530 is mentioned in reload_in of the reload we are going to inherit.
6531 A special case are auto_inc expressions; even if the input is
6532 inherited, we still need the address for the output. We can
6533 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6534 If we succeeded removing some reload and we are doing a preliminary
6535 pass just to remove such reloads, make another pass, since the
6536 removal of one reload might allow us to inherit another one. */
6538 && rld[r].out != rld[r].in
6539 && remove_address_replacements (rld[r].in) && pass)
6544 /* Now that reload_override_in is known valid,
6545 actually override reload_in. */
6546 for (j = 0; j < n_reloads; j++)
6547 if (reload_override_in[j])
6548 rld[j].in = reload_override_in[j];
6550 /* If this reload won't be done because it has been canceled or is
6551 optional and not inherited, clear reload_reg_rtx so other
6552 routines (such as subst_reloads) don't get confused. */
6553 for (j = 0; j < n_reloads; j++)
6554 if (rld[j].reg_rtx != 0
6555 && ((rld[j].optional && ! reload_inherited[j])
6556 || (rld[j].in == 0 && rld[j].out == 0
6557 && ! rld[j].secondary_p)))
6559 int regno = true_regnum (rld[j].reg_rtx);
6561 if (spill_reg_order[regno] >= 0)
6562 clear_reload_reg_in_use (regno, rld[j].opnum,
6563 rld[j].when_needed, rld[j].mode);
6565 reload_spill_index[j] = -1;
6568 /* Record which pseudos and which spill regs have output reloads. */
6569 for (j = 0; j < n_reloads; j++)
6571 int r = reload_order[j];
6573 i = reload_spill_index[r];
6575 /* I is nonneg if this reload uses a register.
6576 If rld[r].reg_rtx is 0, this is an optional reload
6577 that we opted to ignore. */
6578 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6579 && rld[r].reg_rtx != 0)
6581 int nregno = REGNO (rld[r].out_reg);
6584 if (nregno < FIRST_PSEUDO_REGISTER)
6585 nr = hard_regno_nregs[nregno][rld[r].mode];
6588 SET_REGNO_REG_SET (®_has_output_reload,
6593 nr = hard_regno_nregs[i][rld[r].mode];
6595 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6598 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6599 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6600 || rld[r].when_needed == RELOAD_FOR_INSN);
6605 /* Deallocate the reload register for reload R. This is called from
6606 remove_address_replacements. */
6609 deallocate_reload_reg (int r)
6613 if (! rld[r].reg_rtx)
6615 regno = true_regnum (rld[r].reg_rtx);
6617 if (spill_reg_order[regno] >= 0)
6618 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6620 reload_spill_index[r] = -1;
6623 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6624 reloads of the same item for fear that we might not have enough reload
6625 registers. However, normally they will get the same reload register
6626 and hence actually need not be loaded twice.
6628 Here we check for the most common case of this phenomenon: when we have
6629 a number of reloads for the same object, each of which were allocated
6630 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6631 reload, and is not modified in the insn itself. If we find such,
6632 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6633 This will not increase the number of spill registers needed and will
6634 prevent redundant code. */
6637 merge_assigned_reloads (rtx insn)
6641 /* Scan all the reloads looking for ones that only load values and
6642 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6643 assigned and not modified by INSN. */
6645 for (i = 0; i < n_reloads; i++)
6647 int conflicting_input = 0;
6648 int max_input_address_opnum = -1;
6649 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6651 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6652 || rld[i].out != 0 || rld[i].reg_rtx == 0
6653 || reg_set_p (rld[i].reg_rtx, insn))
6656 /* Look at all other reloads. Ensure that the only use of this
6657 reload_reg_rtx is in a reload that just loads the same value
6658 as we do. Note that any secondary reloads must be of the identical
6659 class since the values, modes, and result registers are the
6660 same, so we need not do anything with any secondary reloads. */
6662 for (j = 0; j < n_reloads; j++)
6664 if (i == j || rld[j].reg_rtx == 0
6665 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6669 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6670 && rld[j].opnum > max_input_address_opnum)
6671 max_input_address_opnum = rld[j].opnum;
6673 /* If the reload regs aren't exactly the same (e.g, different modes)
6674 or if the values are different, we can't merge this reload.
6675 But if it is an input reload, we might still merge
6676 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6678 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6679 || rld[j].out != 0 || rld[j].in == 0
6680 || ! rtx_equal_p (rld[i].in, rld[j].in))
6682 if (rld[j].when_needed != RELOAD_FOR_INPUT
6683 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6684 || rld[i].opnum > rld[j].opnum)
6685 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6687 conflicting_input = 1;
6688 if (min_conflicting_input_opnum > rld[j].opnum)
6689 min_conflicting_input_opnum = rld[j].opnum;
6693 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6694 we, in fact, found any matching reloads. */
6697 && max_input_address_opnum <= min_conflicting_input_opnum)
6699 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6701 for (j = 0; j < n_reloads; j++)
6702 if (i != j && rld[j].reg_rtx != 0
6703 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6704 && (! conflicting_input
6705 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6706 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6708 rld[i].when_needed = RELOAD_OTHER;
6710 reload_spill_index[j] = -1;
6711 transfer_replacements (i, j);
6714 /* If this is now RELOAD_OTHER, look for any reloads that
6715 load parts of this operand and set them to
6716 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6717 RELOAD_OTHER for outputs. Note that this test is
6718 equivalent to looking for reloads for this operand
6721 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6722 it may share registers with a RELOAD_FOR_INPUT, so we can
6723 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6724 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6726 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6727 instruction is assigned the same register as the earlier
6728 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6729 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6730 instruction to be deleted later on. */
6732 if (rld[i].when_needed == RELOAD_OTHER)
6733 for (j = 0; j < n_reloads; j++)
6735 && rld[j].when_needed != RELOAD_OTHER
6736 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6737 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6738 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6739 && (! conflicting_input
6740 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6741 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6742 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6748 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6749 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6750 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6752 /* Check to see if we accidentally converted two
6753 reloads that use the same reload register with
6754 different inputs to the same type. If so, the
6755 resulting code won't work. */
6757 for (k = 0; k < j; k++)
6758 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6759 || rld[k].when_needed != rld[j].when_needed
6760 || !rtx_equal_p (rld[k].reg_rtx,
6762 || rtx_equal_p (rld[k].in,
6769 /* These arrays are filled by emit_reload_insns and its subroutines. */
6770 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6771 static rtx other_input_address_reload_insns = 0;
6772 static rtx other_input_reload_insns = 0;
6773 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6774 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6775 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6776 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6777 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6778 static rtx operand_reload_insns = 0;
6779 static rtx other_operand_reload_insns = 0;
6780 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6782 /* Values to be put in spill_reg_store are put here first. */
6783 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6784 static HARD_REG_SET reg_reloaded_died;
6786 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6787 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6788 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6789 adjusted register, and return true. Otherwise, return false. */
6791 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6792 enum reg_class new_class,
6793 enum machine_mode new_mode)
6798 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6800 unsigned regno = REGNO (reg);
6802 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6804 if (GET_MODE (reg) != new_mode)
6806 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6808 if (hard_regno_nregs[regno][new_mode]
6809 > hard_regno_nregs[regno][GET_MODE (reg)])
6811 reg = reload_adjust_reg_for_mode (reg, new_mode);
6819 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6820 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6821 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6822 adjusted register, and return true. Otherwise, return false. */
6824 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6825 enum insn_code icode)
6828 enum reg_class new_class = scratch_reload_class (icode);
6829 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6831 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6832 new_class, new_mode);
6835 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6836 has the number J. OLD contains the value to be used as input. */
6839 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6842 rtx insn = chain->insn;
6844 rtx oldequiv_reg = 0;
6847 enum machine_mode mode;
6850 /* delete_output_reload is only invoked properly if old contains
6851 the original pseudo register. Since this is replaced with a
6852 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6853 find the pseudo in RELOAD_IN_REG. */
6854 if (reload_override_in[j]
6855 && REG_P (rl->in_reg))
6862 else if (REG_P (oldequiv))
6863 oldequiv_reg = oldequiv;
6864 else if (GET_CODE (oldequiv) == SUBREG)
6865 oldequiv_reg = SUBREG_REG (oldequiv);
6867 reloadreg = reload_reg_rtx_for_input[j];
6868 mode = GET_MODE (reloadreg);
6870 /* If we are reloading from a register that was recently stored in
6871 with an output-reload, see if we can prove there was
6872 actually no need to store the old value in it. */
6874 if (optimize && REG_P (oldequiv)
6875 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6876 && spill_reg_store[REGNO (oldequiv)]
6878 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6879 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6881 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6883 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6886 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6887 oldequiv = SUBREG_REG (oldequiv);
6888 if (GET_MODE (oldequiv) != VOIDmode
6889 && mode != GET_MODE (oldequiv))
6890 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6892 /* Switch to the right place to emit the reload insns. */
6893 switch (rl->when_needed)
6896 where = &other_input_reload_insns;
6898 case RELOAD_FOR_INPUT:
6899 where = &input_reload_insns[rl->opnum];
6901 case RELOAD_FOR_INPUT_ADDRESS:
6902 where = &input_address_reload_insns[rl->opnum];
6904 case RELOAD_FOR_INPADDR_ADDRESS:
6905 where = &inpaddr_address_reload_insns[rl->opnum];
6907 case RELOAD_FOR_OUTPUT_ADDRESS:
6908 where = &output_address_reload_insns[rl->opnum];
6910 case RELOAD_FOR_OUTADDR_ADDRESS:
6911 where = &outaddr_address_reload_insns[rl->opnum];
6913 case RELOAD_FOR_OPERAND_ADDRESS:
6914 where = &operand_reload_insns;
6916 case RELOAD_FOR_OPADDR_ADDR:
6917 where = &other_operand_reload_insns;
6919 case RELOAD_FOR_OTHER_ADDRESS:
6920 where = &other_input_address_reload_insns;
6926 push_to_sequence (*where);
6928 /* Auto-increment addresses must be reloaded in a special way. */
6929 if (rl->out && ! rl->out_reg)
6931 /* We are not going to bother supporting the case where a
6932 incremented register can't be copied directly from
6933 OLDEQUIV since this seems highly unlikely. */
6934 gcc_assert (rl->secondary_in_reload < 0);
6936 if (reload_inherited[j])
6937 oldequiv = reloadreg;
6939 old = XEXP (rl->in_reg, 0);
6941 if (optimize && REG_P (oldequiv)
6942 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6943 && spill_reg_store[REGNO (oldequiv)]
6945 && (dead_or_set_p (insn,
6946 spill_reg_stored_to[REGNO (oldequiv)])
6947 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6949 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6951 /* Prevent normal processing of this reload. */
6953 /* Output a special code sequence for this case. */
6954 new_spill_reg_store[REGNO (reloadreg)]
6955 = inc_for_reload (reloadreg, oldequiv, rl->out,
6959 /* If we are reloading a pseudo-register that was set by the previous
6960 insn, see if we can get rid of that pseudo-register entirely
6961 by redirecting the previous insn into our reload register. */
6963 else if (optimize && REG_P (old)
6964 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6965 && dead_or_set_p (insn, old)
6966 /* This is unsafe if some other reload
6967 uses the same reg first. */
6968 && ! conflicts_with_override (reloadreg)
6969 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6970 rl->when_needed, old, rl->out, j, 0))
6972 rtx temp = PREV_INSN (insn);
6973 while (temp && NOTE_P (temp))
6974 temp = PREV_INSN (temp);
6976 && NONJUMP_INSN_P (temp)
6977 && GET_CODE (PATTERN (temp)) == SET
6978 && SET_DEST (PATTERN (temp)) == old
6979 /* Make sure we can access insn_operand_constraint. */
6980 && asm_noperands (PATTERN (temp)) < 0
6981 /* This is unsafe if operand occurs more than once in current
6982 insn. Perhaps some occurrences aren't reloaded. */
6983 && count_occurrences (PATTERN (insn), old, 0) == 1)
6985 rtx old = SET_DEST (PATTERN (temp));
6986 /* Store into the reload register instead of the pseudo. */
6987 SET_DEST (PATTERN (temp)) = reloadreg;
6989 /* Verify that resulting insn is valid. */
6990 extract_insn (temp);
6991 if (constrain_operands (1))
6993 /* If the previous insn is an output reload, the source is
6994 a reload register, and its spill_reg_store entry will
6995 contain the previous destination. This is now
6997 if (REG_P (SET_SRC (PATTERN (temp)))
6998 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7000 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7001 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7004 /* If these are the only uses of the pseudo reg,
7005 pretend for GDB it lives in the reload reg we used. */
7006 if (REG_N_DEATHS (REGNO (old)) == 1
7007 && REG_N_SETS (REGNO (old)) == 1)
7009 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7010 if (flag_ira && optimize)
7011 /* Inform IRA about the change. */
7012 ira_mark_allocation_change (REGNO (old));
7013 alter_reg (REGNO (old), -1, false);
7019 SET_DEST (PATTERN (temp)) = old;
7024 /* We can't do that, so output an insn to load RELOADREG. */
7026 /* If we have a secondary reload, pick up the secondary register
7027 and icode, if any. If OLDEQUIV and OLD are different or
7028 if this is an in-out reload, recompute whether or not we
7029 still need a secondary register and what the icode should
7030 be. If we still need a secondary register and the class or
7031 icode is different, go back to reloading from OLD if using
7032 OLDEQUIV means that we got the wrong type of register. We
7033 cannot have different class or icode due to an in-out reload
7034 because we don't make such reloads when both the input and
7035 output need secondary reload registers. */
7037 if (! special && rl->secondary_in_reload >= 0)
7039 rtx second_reload_reg = 0;
7040 rtx third_reload_reg = 0;
7041 int secondary_reload = rl->secondary_in_reload;
7042 rtx real_oldequiv = oldequiv;
7045 enum insn_code icode;
7046 enum insn_code tertiary_icode = CODE_FOR_nothing;
7048 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7049 and similarly for OLD.
7050 See comments in get_secondary_reload in reload.c. */
7051 /* If it is a pseudo that cannot be replaced with its
7052 equivalent MEM, we must fall back to reload_in, which
7053 will have all the necessary substitutions registered.
7054 Likewise for a pseudo that can't be replaced with its
7055 equivalent constant.
7057 Take extra care for subregs of such pseudos. Note that
7058 we cannot use reg_equiv_mem in this case because it is
7059 not in the right mode. */
7062 if (GET_CODE (tmp) == SUBREG)
7063 tmp = SUBREG_REG (tmp);
7065 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7066 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7067 || reg_equiv_constant[REGNO (tmp)] != 0))
7069 if (! reg_equiv_mem[REGNO (tmp)]
7070 || num_not_at_initial_offset
7071 || GET_CODE (oldequiv) == SUBREG)
7072 real_oldequiv = rl->in;
7074 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7078 if (GET_CODE (tmp) == SUBREG)
7079 tmp = SUBREG_REG (tmp);
7081 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7082 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7083 || reg_equiv_constant[REGNO (tmp)] != 0))
7085 if (! reg_equiv_mem[REGNO (tmp)]
7086 || num_not_at_initial_offset
7087 || GET_CODE (old) == SUBREG)
7090 real_old = reg_equiv_mem[REGNO (tmp)];
7093 second_reload_reg = rld[secondary_reload].reg_rtx;
7094 if (rld[secondary_reload].secondary_in_reload >= 0)
7096 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7098 third_reload_reg = rld[tertiary_reload].reg_rtx;
7099 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7100 /* We'd have to add more code for quartary reloads. */
7101 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7103 icode = rl->secondary_in_icode;
7105 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7106 || (rl->in != 0 && rl->out != 0))
7108 secondary_reload_info sri, sri2;
7109 enum reg_class new_class, new_t_class;
7111 sri.icode = CODE_FOR_nothing;
7112 sri.prev_sri = NULL;
7113 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7116 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7117 second_reload_reg = 0;
7118 else if (new_class == NO_REGS)
7120 if (reload_adjust_reg_for_icode (&second_reload_reg,
7121 third_reload_reg, sri.icode))
7122 icode = sri.icode, third_reload_reg = 0;
7124 oldequiv = old, real_oldequiv = real_old;
7126 else if (sri.icode != CODE_FOR_nothing)
7127 /* We currently lack a way to express this in reloads. */
7131 sri2.icode = CODE_FOR_nothing;
7132 sri2.prev_sri = &sri;
7133 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7134 new_class, mode, &sri);
7135 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7137 if (reload_adjust_reg_for_temp (&second_reload_reg,
7140 third_reload_reg = 0, tertiary_icode = sri2.icode;
7142 oldequiv = old, real_oldequiv = real_old;
7144 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7146 rtx intermediate = second_reload_reg;
7148 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7150 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7153 second_reload_reg = intermediate;
7154 tertiary_icode = sri2.icode;
7157 oldequiv = old, real_oldequiv = real_old;
7159 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7161 rtx intermediate = second_reload_reg;
7163 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7165 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7168 second_reload_reg = intermediate;
7169 tertiary_icode = sri2.icode;
7172 oldequiv = old, real_oldequiv = real_old;
7175 /* This could be handled more intelligently too. */
7176 oldequiv = old, real_oldequiv = real_old;
7180 /* If we still need a secondary reload register, check
7181 to see if it is being used as a scratch or intermediate
7182 register and generate code appropriately. If we need
7183 a scratch register, use REAL_OLDEQUIV since the form of
7184 the insn may depend on the actual address if it is
7187 if (second_reload_reg)
7189 if (icode != CODE_FOR_nothing)
7191 /* We'd have to add extra code to handle this case. */
7192 gcc_assert (!third_reload_reg);
7194 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7195 second_reload_reg));
7200 /* See if we need a scratch register to load the
7201 intermediate register (a tertiary reload). */
7202 if (tertiary_icode != CODE_FOR_nothing)
7204 emit_insn ((GEN_FCN (tertiary_icode)
7205 (second_reload_reg, real_oldequiv,
7206 third_reload_reg)));
7208 else if (third_reload_reg)
7210 gen_reload (third_reload_reg, real_oldequiv,
7213 gen_reload (second_reload_reg, third_reload_reg,
7218 gen_reload (second_reload_reg, real_oldequiv,
7222 oldequiv = second_reload_reg;
7227 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7229 rtx real_oldequiv = oldequiv;
7231 if ((REG_P (oldequiv)
7232 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7233 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7234 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7235 || (GET_CODE (oldequiv) == SUBREG
7236 && REG_P (SUBREG_REG (oldequiv))
7237 && (REGNO (SUBREG_REG (oldequiv))
7238 >= FIRST_PSEUDO_REGISTER)
7239 && ((reg_equiv_memory_loc
7240 [REGNO (SUBREG_REG (oldequiv))] != 0)
7241 || (reg_equiv_constant
7242 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7243 || (CONSTANT_P (oldequiv)
7244 && (PREFERRED_RELOAD_CLASS (oldequiv,
7245 REGNO_REG_CLASS (REGNO (reloadreg)))
7247 real_oldequiv = rl->in;
7248 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7252 if (flag_non_call_exceptions)
7253 copy_eh_notes (insn, get_insns ());
7255 /* End this sequence. */
7256 *where = get_insns ();
7259 /* Update reload_override_in so that delete_address_reloads_1
7260 can see the actual register usage. */
7262 reload_override_in[j] = oldequiv;
7265 /* Generate insns to for the output reload RL, which is for the insn described
7266 by CHAIN and has the number J. */
7268 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7272 rtx insn = chain->insn;
7275 enum machine_mode mode;
7279 if (rl->when_needed == RELOAD_OTHER)
7282 push_to_sequence (output_reload_insns[rl->opnum]);
7284 rl_reg_rtx = reload_reg_rtx_for_output[j];
7285 mode = GET_MODE (rl_reg_rtx);
7287 reloadreg = rl_reg_rtx;
7289 /* If we need two reload regs, set RELOADREG to the intermediate
7290 one, since it will be stored into OLD. We might need a secondary
7291 register only for an input reload, so check again here. */
7293 if (rl->secondary_out_reload >= 0)
7296 int secondary_reload = rl->secondary_out_reload;
7297 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7299 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7300 && reg_equiv_mem[REGNO (old)] != 0)
7301 real_old = reg_equiv_mem[REGNO (old)];
7303 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7305 rtx second_reloadreg = reloadreg;
7306 reloadreg = rld[secondary_reload].reg_rtx;
7308 /* See if RELOADREG is to be used as a scratch register
7309 or as an intermediate register. */
7310 if (rl->secondary_out_icode != CODE_FOR_nothing)
7312 /* We'd have to add extra code to handle this case. */
7313 gcc_assert (tertiary_reload < 0);
7315 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7316 (real_old, second_reloadreg, reloadreg)));
7321 /* See if we need both a scratch and intermediate reload
7324 enum insn_code tertiary_icode
7325 = rld[secondary_reload].secondary_out_icode;
7327 /* We'd have to add more code for quartary reloads. */
7328 gcc_assert (tertiary_reload < 0
7329 || rld[tertiary_reload].secondary_out_reload < 0);
7331 if (GET_MODE (reloadreg) != mode)
7332 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7334 if (tertiary_icode != CODE_FOR_nothing)
7336 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7339 /* Copy primary reload reg to secondary reload reg.
7340 (Note that these have been swapped above, then
7341 secondary reload reg to OLD using our insn.) */
7343 /* If REAL_OLD is a paradoxical SUBREG, remove it
7344 and try to put the opposite SUBREG on
7346 if (GET_CODE (real_old) == SUBREG
7347 && (GET_MODE_SIZE (GET_MODE (real_old))
7348 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7349 && 0 != (tem = gen_lowpart_common
7350 (GET_MODE (SUBREG_REG (real_old)),
7352 real_old = SUBREG_REG (real_old), reloadreg = tem;
7354 gen_reload (reloadreg, second_reloadreg,
7355 rl->opnum, rl->when_needed);
7356 emit_insn ((GEN_FCN (tertiary_icode)
7357 (real_old, reloadreg, third_reloadreg)));
7363 /* Copy between the reload regs here and then to
7366 gen_reload (reloadreg, second_reloadreg,
7367 rl->opnum, rl->when_needed);
7368 if (tertiary_reload >= 0)
7370 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7372 gen_reload (third_reloadreg, reloadreg,
7373 rl->opnum, rl->when_needed);
7374 reloadreg = third_reloadreg;
7381 /* Output the last reload insn. */
7386 /* Don't output the last reload if OLD is not the dest of
7387 INSN and is in the src and is clobbered by INSN. */
7388 if (! flag_expensive_optimizations
7390 || !(set = single_set (insn))
7391 || rtx_equal_p (old, SET_DEST (set))
7392 || !reg_mentioned_p (old, SET_SRC (set))
7393 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7394 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7395 gen_reload (old, reloadreg, rl->opnum,
7399 /* Look at all insns we emitted, just to be safe. */
7400 for (p = get_insns (); p; p = NEXT_INSN (p))
7403 rtx pat = PATTERN (p);
7405 /* If this output reload doesn't come from a spill reg,
7406 clear any memory of reloaded copies of the pseudo reg.
7407 If this output reload comes from a spill reg,
7408 reg_has_output_reload will make this do nothing. */
7409 note_stores (pat, forget_old_reloads_1, NULL);
7411 if (reg_mentioned_p (rl_reg_rtx, pat))
7413 rtx set = single_set (insn);
7414 if (reload_spill_index[j] < 0
7416 && SET_SRC (set) == rl_reg_rtx)
7418 int src = REGNO (SET_SRC (set));
7420 reload_spill_index[j] = src;
7421 SET_HARD_REG_BIT (reg_is_output_reload, src);
7422 if (find_regno_note (insn, REG_DEAD, src))
7423 SET_HARD_REG_BIT (reg_reloaded_died, src);
7425 if (HARD_REGISTER_P (rl_reg_rtx))
7427 int s = rl->secondary_out_reload;
7428 set = single_set (p);
7429 /* If this reload copies only to the secondary reload
7430 register, the secondary reload does the actual
7432 if (s >= 0 && set == NULL_RTX)
7433 /* We can't tell what function the secondary reload
7434 has and where the actual store to the pseudo is
7435 made; leave new_spill_reg_store alone. */
7438 && SET_SRC (set) == rl_reg_rtx
7439 && SET_DEST (set) == rld[s].reg_rtx)
7441 /* Usually the next instruction will be the
7442 secondary reload insn; if we can confirm
7443 that it is, setting new_spill_reg_store to
7444 that insn will allow an extra optimization. */
7445 rtx s_reg = rld[s].reg_rtx;
7446 rtx next = NEXT_INSN (p);
7447 rld[s].out = rl->out;
7448 rld[s].out_reg = rl->out_reg;
7449 set = single_set (next);
7450 if (set && SET_SRC (set) == s_reg
7451 && ! new_spill_reg_store[REGNO (s_reg)])
7453 SET_HARD_REG_BIT (reg_is_output_reload,
7455 new_spill_reg_store[REGNO (s_reg)] = next;
7459 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7464 if (rl->when_needed == RELOAD_OTHER)
7466 emit_insn (other_output_reload_insns[rl->opnum]);
7467 other_output_reload_insns[rl->opnum] = get_insns ();
7470 output_reload_insns[rl->opnum] = get_insns ();
7472 if (flag_non_call_exceptions)
7473 copy_eh_notes (insn, get_insns ());
7478 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7479 and has the number J. */
7481 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7483 rtx insn = chain->insn;
7484 rtx old = (rl->in && MEM_P (rl->in)
7485 ? rl->in_reg : rl->in);
7486 rtx reg_rtx = rl->reg_rtx;
7490 enum machine_mode mode;
7492 /* Determine the mode to reload in.
7493 This is very tricky because we have three to choose from.
7494 There is the mode the insn operand wants (rl->inmode).
7495 There is the mode of the reload register RELOADREG.
7496 There is the intrinsic mode of the operand, which we could find
7497 by stripping some SUBREGs.
7498 It turns out that RELOADREG's mode is irrelevant:
7499 we can change that arbitrarily.
7501 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7502 then the reload reg may not support QImode moves, so use SImode.
7503 If foo is in memory due to spilling a pseudo reg, this is safe,
7504 because the QImode value is in the least significant part of a
7505 slot big enough for a SImode. If foo is some other sort of
7506 memory reference, then it is impossible to reload this case,
7507 so previous passes had better make sure this never happens.
7509 Then consider a one-word union which has SImode and one of its
7510 members is a float, being fetched as (SUBREG:SF union:SI).
7511 We must fetch that as SFmode because we could be loading into
7512 a float-only register. In this case OLD's mode is correct.
7514 Consider an immediate integer: it has VOIDmode. Here we need
7515 to get a mode from something else.
7517 In some cases, there is a fourth mode, the operand's
7518 containing mode. If the insn specifies a containing mode for
7519 this operand, it overrides all others.
7521 I am not sure whether the algorithm here is always right,
7522 but it does the right things in those cases. */
7524 mode = GET_MODE (old);
7525 if (mode == VOIDmode)
7528 /* We cannot use gen_lowpart_common since it can do the wrong thing
7529 when REG_RTX has a multi-word mode. Note that REG_RTX must
7530 always be a REG here. */
7531 if (GET_MODE (reg_rtx) != mode)
7532 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7534 reload_reg_rtx_for_input[j] = reg_rtx;
7537 /* AUTO_INC reloads need to be handled even if inherited. We got an
7538 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7539 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7540 && ! rtx_equal_p (reg_rtx, old)
7542 emit_input_reload_insns (chain, rld + j, old, j);
7544 /* When inheriting a wider reload, we have a MEM in rl->in,
7545 e.g. inheriting a SImode output reload for
7546 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7547 if (optimize && reload_inherited[j] && rl->in
7549 && MEM_P (rl->in_reg)
7550 && reload_spill_index[j] >= 0
7551 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7552 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7554 /* If we are reloading a register that was recently stored in with an
7555 output-reload, see if we can prove there was
7556 actually no need to store the old value in it. */
7559 && (reload_inherited[j] || reload_override_in[j])
7562 && spill_reg_store[REGNO (reg_rtx)] != 0
7564 /* There doesn't seem to be any reason to restrict this to pseudos
7565 and doing so loses in the case where we are copying from a
7566 register of the wrong class. */
7567 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7569 /* The insn might have already some references to stackslots
7570 replaced by MEMs, while reload_out_reg still names the
7572 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7573 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7574 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7577 /* Do output reloading for reload RL, which is for the insn described by
7578 CHAIN and has the number J.
7579 ??? At some point we need to support handling output reloads of
7580 JUMP_INSNs or insns that set cc0. */
7582 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7585 rtx insn = chain->insn;
7586 /* If this is an output reload that stores something that is
7587 not loaded in this same reload, see if we can eliminate a previous
7589 rtx pseudo = rl->out_reg;
7590 rtx reg_rtx = rl->reg_rtx;
7592 if (rl->out && reg_rtx)
7594 enum machine_mode mode;
7596 /* Determine the mode to reload in.
7597 See comments above (for input reloading). */
7598 mode = GET_MODE (rl->out);
7599 if (mode == VOIDmode)
7601 /* VOIDmode should never happen for an output. */
7602 if (asm_noperands (PATTERN (insn)) < 0)
7603 /* It's the compiler's fault. */
7604 fatal_insn ("VOIDmode on an output", insn);
7605 error_for_asm (insn, "output operand is constant in %<asm%>");
7606 /* Prevent crash--use something we know is valid. */
7608 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7610 if (GET_MODE (reg_rtx) != mode)
7611 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7613 reload_reg_rtx_for_output[j] = reg_rtx;
7618 && ! rtx_equal_p (rl->in_reg, pseudo)
7619 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7620 && reg_last_reload_reg[REGNO (pseudo)])
7622 int pseudo_no = REGNO (pseudo);
7623 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7625 /* We don't need to test full validity of last_regno for
7626 inherit here; we only want to know if the store actually
7627 matches the pseudo. */
7628 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7629 && reg_reloaded_contents[last_regno] == pseudo_no
7630 && spill_reg_store[last_regno]
7631 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7632 delete_output_reload (insn, j, last_regno, reg_rtx);
7638 || rtx_equal_p (old, reg_rtx))
7641 /* An output operand that dies right away does need a reload,
7642 but need not be copied from it. Show the new location in the
7644 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7645 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7647 XEXP (note, 0) = reg_rtx;
7650 /* Likewise for a SUBREG of an operand that dies. */
7651 else if (GET_CODE (old) == SUBREG
7652 && REG_P (SUBREG_REG (old))
7653 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7656 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7659 else if (GET_CODE (old) == SCRATCH)
7660 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7661 but we don't want to make an output reload. */
7664 /* If is a JUMP_INSN, we can't support output reloads yet. */
7665 gcc_assert (NONJUMP_INSN_P (insn));
7667 emit_output_reload_insns (chain, rld + j, j);
7670 /* A reload copies values of MODE from register SRC to register DEST.
7671 Return true if it can be treated for inheritance purposes like a
7672 group of reloads, each one reloading a single hard register. The
7673 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7674 occupy the same number of hard registers. */
7677 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7678 int src ATTRIBUTE_UNUSED,
7679 enum machine_mode mode ATTRIBUTE_UNUSED)
7681 #ifdef CANNOT_CHANGE_MODE_CLASS
7682 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7683 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7689 /* Output insns to reload values in and out of the chosen reload regs. */
7692 emit_reload_insns (struct insn_chain *chain)
7694 rtx insn = chain->insn;
7698 CLEAR_HARD_REG_SET (reg_reloaded_died);
7700 for (j = 0; j < reload_n_operands; j++)
7701 input_reload_insns[j] = input_address_reload_insns[j]
7702 = inpaddr_address_reload_insns[j]
7703 = output_reload_insns[j] = output_address_reload_insns[j]
7704 = outaddr_address_reload_insns[j]
7705 = other_output_reload_insns[j] = 0;
7706 other_input_address_reload_insns = 0;
7707 other_input_reload_insns = 0;
7708 operand_reload_insns = 0;
7709 other_operand_reload_insns = 0;
7711 /* Dump reloads into the dump file. */
7714 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7715 debug_reload_to_stream (dump_file);
7718 /* Now output the instructions to copy the data into and out of the
7719 reload registers. Do these in the order that the reloads were reported,
7720 since reloads of base and index registers precede reloads of operands
7721 and the operands may need the base and index registers reloaded. */
7723 for (j = 0; j < n_reloads; j++)
7725 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7729 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7730 new_spill_reg_store[i] = 0;
7733 do_input_reload (chain, rld + j, j);
7734 do_output_reload (chain, rld + j, j);
7737 /* Now write all the insns we made for reloads in the order expected by
7738 the allocation functions. Prior to the insn being reloaded, we write
7739 the following reloads:
7741 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7743 RELOAD_OTHER reloads.
7745 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7746 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7747 RELOAD_FOR_INPUT reload for the operand.
7749 RELOAD_FOR_OPADDR_ADDRS reloads.
7751 RELOAD_FOR_OPERAND_ADDRESS reloads.
7753 After the insn being reloaded, we write the following:
7755 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7756 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7757 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7758 reloads for the operand. The RELOAD_OTHER output reloads are
7759 output in descending order by reload number. */
7761 emit_insn_before (other_input_address_reload_insns, insn);
7762 emit_insn_before (other_input_reload_insns, insn);
7764 for (j = 0; j < reload_n_operands; j++)
7766 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7767 emit_insn_before (input_address_reload_insns[j], insn);
7768 emit_insn_before (input_reload_insns[j], insn);
7771 emit_insn_before (other_operand_reload_insns, insn);
7772 emit_insn_before (operand_reload_insns, insn);
7774 for (j = 0; j < reload_n_operands; j++)
7776 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7777 x = emit_insn_after (output_address_reload_insns[j], x);
7778 x = emit_insn_after (output_reload_insns[j], x);
7779 emit_insn_after (other_output_reload_insns[j], x);
7782 /* For all the spill regs newly reloaded in this instruction,
7783 record what they were reloaded from, so subsequent instructions
7784 can inherit the reloads.
7786 Update spill_reg_store for the reloads of this insn.
7787 Copy the elements that were updated in the loop above. */
7789 for (j = 0; j < n_reloads; j++)
7791 int r = reload_order[j];
7792 int i = reload_spill_index[r];
7794 /* If this is a non-inherited input reload from a pseudo, we must
7795 clear any memory of a previous store to the same pseudo. Only do
7796 something if there will not be an output reload for the pseudo
7798 if (rld[r].in_reg != 0
7799 && ! (reload_inherited[r] || reload_override_in[r]))
7801 rtx reg = rld[r].in_reg;
7803 if (GET_CODE (reg) == SUBREG)
7804 reg = SUBREG_REG (reg);
7807 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7808 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7810 int nregno = REGNO (reg);
7812 if (reg_last_reload_reg[nregno])
7814 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7816 if (reg_reloaded_contents[last_regno] == nregno)
7817 spill_reg_store[last_regno] = 0;
7822 /* I is nonneg if this reload used a register.
7823 If rld[r].reg_rtx is 0, this is an optional reload
7824 that we opted to ignore. */
7826 if (i >= 0 && rld[r].reg_rtx != 0)
7828 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7831 /* For a multi register reload, we need to check if all or part
7832 of the value lives to the end. */
7833 for (k = 0; k < nr; k++)
7834 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7835 rld[r].when_needed))
7836 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7838 /* Maybe the spill reg contains a copy of reload_out. */
7840 && (REG_P (rld[r].out)
7844 || REG_P (rld[r].out_reg)))
7847 enum machine_mode mode;
7850 reg = reload_reg_rtx_for_output[r];
7851 mode = GET_MODE (reg);
7852 regno = REGNO (reg);
7853 nregs = hard_regno_nregs[regno][mode];
7854 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7855 rld[r].when_needed))
7857 rtx out = (REG_P (rld[r].out)
7861 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7862 int out_regno = REGNO (out);
7863 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7864 : hard_regno_nregs[out_regno][mode]);
7867 spill_reg_store[regno] = new_spill_reg_store[regno];
7868 spill_reg_stored_to[regno] = out;
7869 reg_last_reload_reg[out_regno] = reg;
7871 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7872 && nregs == out_nregs
7873 && inherit_piecemeal_p (out_regno, regno, mode));
7875 /* If OUT_REGNO is a hard register, it may occupy more than
7876 one register. If it does, say what is in the
7877 rest of the registers assuming that both registers
7878 agree on how many words the object takes. If not,
7879 invalidate the subsequent registers. */
7881 if (HARD_REGISTER_NUM_P (out_regno))
7882 for (k = 1; k < out_nregs; k++)
7883 reg_last_reload_reg[out_regno + k]
7884 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7886 /* Now do the inverse operation. */
7887 for (k = 0; k < nregs; k++)
7889 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7890 reg_reloaded_contents[regno + k]
7891 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7894 reg_reloaded_insn[regno + k] = insn;
7895 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7896 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7897 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7900 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7905 /* Maybe the spill reg contains a copy of reload_in. Only do
7906 something if there will not be an output reload for
7907 the register being reloaded. */
7908 else if (rld[r].out_reg == 0
7910 && ((REG_P (rld[r].in)
7911 && !HARD_REGISTER_P (rld[r].in)
7912 && !REGNO_REG_SET_P (®_has_output_reload,
7914 || (REG_P (rld[r].in_reg)
7915 && !REGNO_REG_SET_P (®_has_output_reload,
7916 REGNO (rld[r].in_reg))))
7917 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7920 enum machine_mode mode;
7923 reg = reload_reg_rtx_for_input[r];
7924 mode = GET_MODE (reg);
7925 regno = REGNO (reg);
7926 nregs = hard_regno_nregs[regno][mode];
7927 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7928 rld[r].when_needed))
7935 if (REG_P (rld[r].in)
7936 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7938 else if (REG_P (rld[r].in_reg))
7941 in = XEXP (rld[r].in_reg, 0);
7942 in_regno = REGNO (in);
7944 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7945 : hard_regno_nregs[in_regno][mode]);
7947 reg_last_reload_reg[in_regno] = reg;
7949 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7950 && nregs == in_nregs
7951 && inherit_piecemeal_p (regno, in_regno, mode));
7953 if (HARD_REGISTER_NUM_P (in_regno))
7954 for (k = 1; k < in_nregs; k++)
7955 reg_last_reload_reg[in_regno + k]
7956 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7958 /* Unless we inherited this reload, show we haven't
7959 recently done a store.
7960 Previous stores of inherited auto_inc expressions
7961 also have to be discarded. */
7962 if (! reload_inherited[r]
7963 || (rld[r].out && ! rld[r].out_reg))
7964 spill_reg_store[regno] = 0;
7966 for (k = 0; k < nregs; k++)
7968 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7969 reg_reloaded_contents[regno + k]
7970 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7973 reg_reloaded_insn[regno + k] = insn;
7974 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7975 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7976 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7979 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7986 /* The following if-statement was #if 0'd in 1.34 (or before...).
7987 It's reenabled in 1.35 because supposedly nothing else
7988 deals with this problem. */
7990 /* If a register gets output-reloaded from a non-spill register,
7991 that invalidates any previous reloaded copy of it.
7992 But forget_old_reloads_1 won't get to see it, because
7993 it thinks only about the original insn. So invalidate it here.
7994 Also do the same thing for RELOAD_OTHER constraints where the
7995 output is discarded. */
7997 && ((rld[r].out != 0
7998 && (REG_P (rld[r].out)
7999 || (MEM_P (rld[r].out)
8000 && REG_P (rld[r].out_reg))))
8001 || (rld[r].out == 0 && rld[r].out_reg
8002 && REG_P (rld[r].out_reg))))
8004 rtx out = ((rld[r].out && REG_P (rld[r].out))
8005 ? rld[r].out : rld[r].out_reg);
8006 int out_regno = REGNO (out);
8007 enum machine_mode mode = GET_MODE (out);
8009 /* REG_RTX is now set or clobbered by the main instruction.
8010 As the comment above explains, forget_old_reloads_1 only
8011 sees the original instruction, and there is no guarantee
8012 that the original instruction also clobbered REG_RTX.
8013 For example, if find_reloads sees that the input side of
8014 a matched operand pair dies in this instruction, it may
8015 use the input register as the reload register.
8017 Calling forget_old_reloads_1 is a waste of effort if
8018 REG_RTX is also the output register.
8020 If we know that REG_RTX holds the value of a pseudo
8021 register, the code after the call will record that fact. */
8022 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8023 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8025 if (!HARD_REGISTER_NUM_P (out_regno))
8027 rtx src_reg, store_insn = NULL_RTX;
8029 reg_last_reload_reg[out_regno] = 0;
8031 /* If we can find a hard register that is stored, record
8032 the storing insn so that we may delete this insn with
8033 delete_output_reload. */
8034 src_reg = reload_reg_rtx_for_output[r];
8036 /* If this is an optional reload, try to find the source reg
8037 from an input reload. */
8040 rtx set = single_set (insn);
8041 if (set && SET_DEST (set) == rld[r].out)
8045 src_reg = SET_SRC (set);
8047 for (k = 0; k < n_reloads; k++)
8049 if (rld[k].in == src_reg)
8051 src_reg = reload_reg_rtx_for_input[k];
8058 store_insn = new_spill_reg_store[REGNO (src_reg)];
8059 if (src_reg && REG_P (src_reg)
8060 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8062 int src_regno, src_nregs, k;
8065 gcc_assert (GET_MODE (src_reg) == mode);
8066 src_regno = REGNO (src_reg);
8067 src_nregs = hard_regno_nregs[src_regno][mode];
8068 /* The place where to find a death note varies with
8069 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8070 necessarily checked exactly in the code that moves
8071 notes, so just check both locations. */
8072 note = find_regno_note (insn, REG_DEAD, src_regno);
8073 if (! note && store_insn)
8074 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8075 for (k = 0; k < src_nregs; k++)
8077 spill_reg_store[src_regno + k] = store_insn;
8078 spill_reg_stored_to[src_regno + k] = out;
8079 reg_reloaded_contents[src_regno + k] = out_regno;
8080 reg_reloaded_insn[src_regno + k] = store_insn;
8081 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8082 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8083 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8085 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8088 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8090 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8092 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8094 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8096 reg_last_reload_reg[out_regno] = src_reg;
8097 /* We have to set reg_has_output_reload here, or else
8098 forget_old_reloads_1 will clear reg_last_reload_reg
8100 SET_REGNO_REG_SET (®_has_output_reload,
8106 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8108 for (k = 0; k < out_nregs; k++)
8109 reg_last_reload_reg[out_regno + k] = 0;
8113 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8116 /* Go through the motions to emit INSN and test if it is strictly valid.
8117 Return the emitted insn if valid, else return NULL. */
8120 emit_insn_if_valid_for_reload (rtx insn)
8122 rtx last = get_last_insn ();
8125 insn = emit_insn (insn);
8126 code = recog_memoized (insn);
8130 extract_insn (insn);
8131 /* We want constrain operands to treat this insn strictly in its
8132 validity determination, i.e., the way it would after reload has
8134 if (constrain_operands (1))
8138 delete_insns_since (last);
8142 /* Emit code to perform a reload from IN (which may be a reload register) to
8143 OUT (which may also be a reload register). IN or OUT is from operand
8144 OPNUM with reload type TYPE.
8146 Returns first insn emitted. */
8149 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8151 rtx last = get_last_insn ();
8154 /* If IN is a paradoxical SUBREG, remove it and try to put the
8155 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8156 if (GET_CODE (in) == SUBREG
8157 && (GET_MODE_SIZE (GET_MODE (in))
8158 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8159 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8160 in = SUBREG_REG (in), out = tem;
8161 else if (GET_CODE (out) == SUBREG
8162 && (GET_MODE_SIZE (GET_MODE (out))
8163 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8164 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8165 out = SUBREG_REG (out), in = tem;
8167 /* How to do this reload can get quite tricky. Normally, we are being
8168 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8169 register that didn't get a hard register. In that case we can just
8170 call emit_move_insn.
8172 We can also be asked to reload a PLUS that adds a register or a MEM to
8173 another register, constant or MEM. This can occur during frame pointer
8174 elimination and while reloading addresses. This case is handled by
8175 trying to emit a single insn to perform the add. If it is not valid,
8176 we use a two insn sequence.
8178 Or we can be asked to reload an unary operand that was a fragment of
8179 an addressing mode, into a register. If it isn't recognized as-is,
8180 we try making the unop operand and the reload-register the same:
8181 (set reg:X (unop:X expr:Y))
8182 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8184 Finally, we could be called to handle an 'o' constraint by putting
8185 an address into a register. In that case, we first try to do this
8186 with a named pattern of "reload_load_address". If no such pattern
8187 exists, we just emit a SET insn and hope for the best (it will normally
8188 be valid on machines that use 'o').
8190 This entire process is made complex because reload will never
8191 process the insns we generate here and so we must ensure that
8192 they will fit their constraints and also by the fact that parts of
8193 IN might be being reloaded separately and replaced with spill registers.
8194 Because of this, we are, in some sense, just guessing the right approach
8195 here. The one listed above seems to work.
8197 ??? At some point, this whole thing needs to be rethought. */
8199 if (GET_CODE (in) == PLUS
8200 && (REG_P (XEXP (in, 0))
8201 || GET_CODE (XEXP (in, 0)) == SUBREG
8202 || MEM_P (XEXP (in, 0)))
8203 && (REG_P (XEXP (in, 1))
8204 || GET_CODE (XEXP (in, 1)) == SUBREG
8205 || CONSTANT_P (XEXP (in, 1))
8206 || MEM_P (XEXP (in, 1))))
8208 /* We need to compute the sum of a register or a MEM and another
8209 register, constant, or MEM, and put it into the reload
8210 register. The best possible way of doing this is if the machine
8211 has a three-operand ADD insn that accepts the required operands.
8213 The simplest approach is to try to generate such an insn and see if it
8214 is recognized and matches its constraints. If so, it can be used.
8216 It might be better not to actually emit the insn unless it is valid,
8217 but we need to pass the insn as an operand to `recog' and
8218 `extract_insn' and it is simpler to emit and then delete the insn if
8219 not valid than to dummy things up. */
8221 rtx op0, op1, tem, insn;
8224 op0 = find_replacement (&XEXP (in, 0));
8225 op1 = find_replacement (&XEXP (in, 1));
8227 /* Since constraint checking is strict, commutativity won't be
8228 checked, so we need to do that here to avoid spurious failure
8229 if the add instruction is two-address and the second operand
8230 of the add is the same as the reload reg, which is frequently
8231 the case. If the insn would be A = B + A, rearrange it so
8232 it will be A = A + B as constrain_operands expects. */
8234 if (REG_P (XEXP (in, 1))
8235 && REGNO (out) == REGNO (XEXP (in, 1)))
8236 tem = op0, op0 = op1, op1 = tem;
8238 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8239 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8241 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8245 /* If that failed, we must use a conservative two-insn sequence.
8247 Use a move to copy one operand into the reload register. Prefer
8248 to reload a constant, MEM or pseudo since the move patterns can
8249 handle an arbitrary operand. If OP1 is not a constant, MEM or
8250 pseudo and OP1 is not a valid operand for an add instruction, then
8253 After reloading one of the operands into the reload register, add
8254 the reload register to the output register.
8256 If there is another way to do this for a specific machine, a
8257 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8260 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8262 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8264 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8265 || (code != CODE_FOR_nothing
8266 && ! ((*insn_data[code].operand[2].predicate)
8267 (op1, insn_data[code].operand[2].mode))))
8268 tem = op0, op0 = op1, op1 = tem;
8270 gen_reload (out, op0, opnum, type);
8272 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8273 This fixes a problem on the 32K where the stack pointer cannot
8274 be used as an operand of an add insn. */
8276 if (rtx_equal_p (op0, op1))
8279 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8282 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8283 set_unique_reg_note (insn, REG_EQUIV, in);
8287 /* If that failed, copy the address register to the reload register.
8288 Then add the constant to the reload register. */
8290 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8291 gen_reload (out, op1, opnum, type);
8292 insn = emit_insn (gen_add2_insn (out, op0));
8293 set_unique_reg_note (insn, REG_EQUIV, in);
8296 #ifdef SECONDARY_MEMORY_NEEDED
8297 /* If we need a memory location to do the move, do it that way. */
8298 else if ((REG_P (in)
8299 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8300 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8302 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8303 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8304 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8305 REGNO_REG_CLASS (reg_or_subregno (out)),
8308 /* Get the memory to use and rewrite both registers to its mode. */
8309 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8311 if (GET_MODE (loc) != GET_MODE (out))
8312 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8314 if (GET_MODE (loc) != GET_MODE (in))
8315 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8317 gen_reload (loc, in, opnum, type);
8318 gen_reload (out, loc, opnum, type);
8321 else if (REG_P (out) && UNARY_P (in))
8328 op1 = find_replacement (&XEXP (in, 0));
8329 if (op1 != XEXP (in, 0))
8330 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8332 /* First, try a plain SET. */
8333 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8337 /* If that failed, move the inner operand to the reload
8338 register, and try the same unop with the inner expression
8339 replaced with the reload register. */
8341 if (GET_MODE (op1) != GET_MODE (out))
8342 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8346 gen_reload (out_moded, op1, opnum, type);
8349 = gen_rtx_SET (VOIDmode, out,
8350 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8352 insn = emit_insn_if_valid_for_reload (insn);
8355 set_unique_reg_note (insn, REG_EQUIV, in);
8359 fatal_insn ("Failure trying to reload:", set);
8361 /* If IN is a simple operand, use gen_move_insn. */
8362 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8364 tem = emit_insn (gen_move_insn (out, in));
8365 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8366 mark_jump_label (in, tem, 0);
8369 #ifdef HAVE_reload_load_address
8370 else if (HAVE_reload_load_address)
8371 emit_insn (gen_reload_load_address (out, in));
8374 /* Otherwise, just write (set OUT IN) and hope for the best. */
8376 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8378 /* Return the first insn emitted.
8379 We can not just return get_last_insn, because there may have
8380 been multiple instructions emitted. Also note that gen_move_insn may
8381 emit more than one insn itself, so we can not assume that there is one
8382 insn emitted per emit_insn_before call. */
8384 return last ? NEXT_INSN (last) : get_insns ();
8387 /* Delete a previously made output-reload whose result we now believe
8388 is not needed. First we double-check.
8390 INSN is the insn now being processed.
8391 LAST_RELOAD_REG is the hard register number for which we want to delete
8392 the last output reload.
8393 J is the reload-number that originally used REG. The caller has made
8394 certain that reload J doesn't use REG any longer for input.
8395 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8398 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8400 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8401 rtx reg = spill_reg_stored_to[last_reload_reg];
8404 int n_inherited = 0;
8408 /* It is possible that this reload has been only used to set another reload
8409 we eliminated earlier and thus deleted this instruction too. */
8410 if (INSN_DELETED_P (output_reload_insn))
8413 /* Get the raw pseudo-register referred to. */
8415 while (GET_CODE (reg) == SUBREG)
8416 reg = SUBREG_REG (reg);
8417 substed = reg_equiv_memory_loc[REGNO (reg)];
8419 /* This is unsafe if the operand occurs more often in the current
8420 insn than it is inherited. */
8421 for (k = n_reloads - 1; k >= 0; k--)
8423 rtx reg2 = rld[k].in;
8426 if (MEM_P (reg2) || reload_override_in[k])
8427 reg2 = rld[k].in_reg;
8429 if (rld[k].out && ! rld[k].out_reg)
8430 reg2 = XEXP (rld[k].in_reg, 0);
8432 while (GET_CODE (reg2) == SUBREG)
8433 reg2 = SUBREG_REG (reg2);
8434 if (rtx_equal_p (reg2, reg))
8436 if (reload_inherited[k] || reload_override_in[k] || k == j)
8442 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8443 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8444 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8447 n_occurrences += count_occurrences (PATTERN (insn),
8448 eliminate_regs (substed, 0,
8450 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8452 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8453 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8455 if (n_occurrences > n_inherited)
8458 /* If the pseudo-reg we are reloading is no longer referenced
8459 anywhere between the store into it and here,
8460 and we're within the same basic block, then the value can only
8461 pass through the reload reg and end up here.
8462 Otherwise, give up--return. */
8463 for (i1 = NEXT_INSN (output_reload_insn);
8464 i1 != insn; i1 = NEXT_INSN (i1))
8466 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8468 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8469 && reg_mentioned_p (reg, PATTERN (i1)))
8471 /* If this is USE in front of INSN, we only have to check that
8472 there are no more references than accounted for by inheritance. */
8473 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8475 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8476 i1 = NEXT_INSN (i1);
8478 if (n_occurrences <= n_inherited && i1 == insn)
8484 /* We will be deleting the insn. Remove the spill reg information. */
8485 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8487 spill_reg_store[last_reload_reg + k] = 0;
8488 spill_reg_stored_to[last_reload_reg + k] = 0;
8491 /* The caller has already checked that REG dies or is set in INSN.
8492 It has also checked that we are optimizing, and thus some
8493 inaccuracies in the debugging information are acceptable.
8494 So we could just delete output_reload_insn. But in some cases
8495 we can improve the debugging information without sacrificing
8496 optimization - maybe even improving the code: See if the pseudo
8497 reg has been completely replaced with reload regs. If so, delete
8498 the store insn and forget we had a stack slot for the pseudo. */
8499 if (rld[j].out != rld[j].in
8500 && REG_N_DEATHS (REGNO (reg)) == 1
8501 && REG_N_SETS (REGNO (reg)) == 1
8502 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8503 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8507 /* We know that it was used only between here and the beginning of
8508 the current basic block. (We also know that the last use before
8509 INSN was the output reload we are thinking of deleting, but never
8510 mind that.) Search that range; see if any ref remains. */
8511 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8513 rtx set = single_set (i2);
8515 /* Uses which just store in the pseudo don't count,
8516 since if they are the only uses, they are dead. */
8517 if (set != 0 && SET_DEST (set) == reg)
8522 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8523 && reg_mentioned_p (reg, PATTERN (i2)))
8525 /* Some other ref remains; just delete the output reload we
8527 delete_address_reloads (output_reload_insn, insn);
8528 delete_insn (output_reload_insn);
8533 /* Delete the now-dead stores into this pseudo. Note that this
8534 loop also takes care of deleting output_reload_insn. */
8535 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8537 rtx set = single_set (i2);
8539 if (set != 0 && SET_DEST (set) == reg)
8541 delete_address_reloads (i2, insn);
8549 /* For the debugging info, say the pseudo lives in this reload reg. */
8550 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8551 if (flag_ira && optimize)
8552 /* Inform IRA about the change. */
8553 ira_mark_allocation_change (REGNO (reg));
8554 alter_reg (REGNO (reg), -1, false);
8558 delete_address_reloads (output_reload_insn, insn);
8559 delete_insn (output_reload_insn);
8563 /* We are going to delete DEAD_INSN. Recursively delete loads of
8564 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8565 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8567 delete_address_reloads (rtx dead_insn, rtx current_insn)
8569 rtx set = single_set (dead_insn);
8570 rtx set2, dst, prev, next;
8573 rtx dst = SET_DEST (set);
8575 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8577 /* If we deleted the store from a reloaded post_{in,de}c expression,
8578 we can delete the matching adds. */
8579 prev = PREV_INSN (dead_insn);
8580 next = NEXT_INSN (dead_insn);
8581 if (! prev || ! next)
8583 set = single_set (next);
8584 set2 = single_set (prev);
8586 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8587 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8588 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8590 dst = SET_DEST (set);
8591 if (! rtx_equal_p (dst, SET_DEST (set2))
8592 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8593 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8594 || (INTVAL (XEXP (SET_SRC (set), 1))
8595 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8597 delete_related_insns (prev);
8598 delete_related_insns (next);
8601 /* Subfunction of delete_address_reloads: process registers found in X. */
8603 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8605 rtx prev, set, dst, i2;
8607 enum rtx_code code = GET_CODE (x);
8611 const char *fmt = GET_RTX_FORMAT (code);
8612 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8615 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8616 else if (fmt[i] == 'E')
8618 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8619 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8626 if (spill_reg_order[REGNO (x)] < 0)
8629 /* Scan backwards for the insn that sets x. This might be a way back due
8631 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8633 code = GET_CODE (prev);
8634 if (code == CODE_LABEL || code == JUMP_INSN)
8638 if (reg_set_p (x, PATTERN (prev)))
8640 if (reg_referenced_p (x, PATTERN (prev)))
8643 if (! prev || INSN_UID (prev) < reload_first_uid)
8645 /* Check that PREV only sets the reload register. */
8646 set = single_set (prev);
8649 dst = SET_DEST (set);
8651 || ! rtx_equal_p (dst, x))
8653 if (! reg_set_p (dst, PATTERN (dead_insn)))
8655 /* Check if DST was used in a later insn -
8656 it might have been inherited. */
8657 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8663 if (reg_referenced_p (dst, PATTERN (i2)))
8665 /* If there is a reference to the register in the current insn,
8666 it might be loaded in a non-inherited reload. If no other
8667 reload uses it, that means the register is set before
8669 if (i2 == current_insn)
8671 for (j = n_reloads - 1; j >= 0; j--)
8672 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8673 || reload_override_in[j] == dst)
8675 for (j = n_reloads - 1; j >= 0; j--)
8676 if (rld[j].in && rld[j].reg_rtx == dst)
8685 /* If DST is still live at CURRENT_INSN, check if it is used for
8686 any reload. Note that even if CURRENT_INSN sets DST, we still
8687 have to check the reloads. */
8688 if (i2 == current_insn)
8690 for (j = n_reloads - 1; j >= 0; j--)
8691 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8692 || reload_override_in[j] == dst)
8694 /* ??? We can't finish the loop here, because dst might be
8695 allocated to a pseudo in this block if no reload in this
8696 block needs any of the classes containing DST - see
8697 spill_hard_reg. There is no easy way to tell this, so we
8698 have to scan till the end of the basic block. */
8700 if (reg_set_p (dst, PATTERN (i2)))
8704 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8705 reg_reloaded_contents[REGNO (dst)] = -1;
8709 /* Output reload-insns to reload VALUE into RELOADREG.
8710 VALUE is an autoincrement or autodecrement RTX whose operand
8711 is a register or memory location;
8712 so reloading involves incrementing that location.
8713 IN is either identical to VALUE, or some cheaper place to reload from.
8715 INC_AMOUNT is the number to increment or decrement by (always positive).
8716 This cannot be deduced from VALUE.
8718 Return the instruction that stores into RELOADREG. */
8721 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8723 /* REG or MEM to be copied and incremented. */
8724 rtx incloc = find_replacement (&XEXP (value, 0));
8725 /* Nonzero if increment after copying. */
8726 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8727 || GET_CODE (value) == POST_MODIFY);
8733 rtx real_in = in == value ? incloc : in;
8735 /* No hard register is equivalent to this register after
8736 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8737 we could inc/dec that register as well (maybe even using it for
8738 the source), but I'm not sure it's worth worrying about. */
8740 reg_last_reload_reg[REGNO (incloc)] = 0;
8742 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8744 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8745 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8749 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8750 inc_amount = -inc_amount;
8752 inc = GEN_INT (inc_amount);
8755 /* If this is post-increment, first copy the location to the reload reg. */
8756 if (post && real_in != reloadreg)
8757 emit_insn (gen_move_insn (reloadreg, real_in));
8761 /* See if we can directly increment INCLOC. Use a method similar to
8762 that in gen_reload. */
8764 last = get_last_insn ();
8765 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8766 gen_rtx_PLUS (GET_MODE (incloc),
8769 code = recog_memoized (add_insn);
8772 extract_insn (add_insn);
8773 if (constrain_operands (1))
8775 /* If this is a pre-increment and we have incremented the value
8776 where it lives, copy the incremented value to RELOADREG to
8777 be used as an address. */
8780 emit_insn (gen_move_insn (reloadreg, incloc));
8785 delete_insns_since (last);
8788 /* If couldn't do the increment directly, must increment in RELOADREG.
8789 The way we do this depends on whether this is pre- or post-increment.
8790 For pre-increment, copy INCLOC to the reload register, increment it
8791 there, then save back. */
8795 if (in != reloadreg)
8796 emit_insn (gen_move_insn (reloadreg, real_in));
8797 emit_insn (gen_add2_insn (reloadreg, inc));
8798 store = emit_insn (gen_move_insn (incloc, reloadreg));
8803 Because this might be a jump insn or a compare, and because RELOADREG
8804 may not be available after the insn in an input reload, we must do
8805 the incrementation before the insn being reloaded for.
8807 We have already copied IN to RELOADREG. Increment the copy in
8808 RELOADREG, save that back, then decrement RELOADREG so it has
8809 the original value. */
8811 emit_insn (gen_add2_insn (reloadreg, inc));
8812 store = emit_insn (gen_move_insn (incloc, reloadreg));
8813 if (GET_CODE (inc) == CONST_INT)
8814 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8816 emit_insn (gen_sub2_insn (reloadreg, inc));
8824 add_auto_inc_notes (rtx insn, rtx x)
8826 enum rtx_code code = GET_CODE (x);
8830 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8832 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8836 /* Scan all the operand sub-expressions. */
8837 fmt = GET_RTX_FORMAT (code);
8838 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8841 add_auto_inc_notes (insn, XEXP (x, i));
8842 else if (fmt[i] == 'E')
8843 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8844 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8849 /* Copy EH notes from an insn to its reloads. */
8851 copy_eh_notes (rtx insn, rtx x)
8853 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8856 for (; x != 0; x = NEXT_INSN (x))
8858 if (may_trap_p (PATTERN (x)))
8859 add_reg_note (x, REG_EH_REGION, XEXP (eh_note, 0));
8864 /* This is used by reload pass, that does emit some instructions after
8865 abnormal calls moving basic block end, but in fact it wants to emit
8866 them on the edge. Looks for abnormal call edges, find backward the
8867 proper call and fix the damage.
8869 Similar handle instructions throwing exceptions internally. */
8871 fixup_abnormal_edges (void)
8873 bool inserted = false;
8881 /* Look for cases we are interested in - calls or instructions causing
8883 FOR_EACH_EDGE (e, ei, bb->succs)
8885 if (e->flags & EDGE_ABNORMAL_CALL)
8887 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8888 == (EDGE_ABNORMAL | EDGE_EH))
8891 if (e && !CALL_P (BB_END (bb))
8892 && !can_throw_internal (BB_END (bb)))
8896 /* Get past the new insns generated. Allow notes, as the insns
8897 may be already deleted. */
8899 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8900 && !can_throw_internal (insn)
8901 && insn != BB_HEAD (bb))
8902 insn = PREV_INSN (insn);
8904 if (CALL_P (insn) || can_throw_internal (insn))
8908 stop = NEXT_INSN (BB_END (bb));
8910 insn = NEXT_INSN (insn);
8912 FOR_EACH_EDGE (e, ei, bb->succs)
8913 if (e->flags & EDGE_FALLTHRU)
8916 while (insn && insn != stop)
8918 next = NEXT_INSN (insn);
8923 /* Sometimes there's still the return value USE.
8924 If it's placed after a trapping call (i.e. that
8925 call is the last insn anyway), we have no fallthru
8926 edge. Simply delete this use and don't try to insert
8927 on the non-existent edge. */
8928 if (GET_CODE (PATTERN (insn)) != USE)
8930 /* We're not deleting it, we're moving it. */
8931 INSN_DELETED_P (insn) = 0;
8932 PREV_INSN (insn) = NULL_RTX;
8933 NEXT_INSN (insn) = NULL_RTX;
8935 insert_insn_on_edge (insn, e);
8939 else if (!BARRIER_P (insn))
8940 set_block_for_insn (insn, NULL);
8945 /* It may be that we don't find any such trapping insn. In this
8946 case we discovered quite late that the insn that had been
8947 marked as can_throw_internal in fact couldn't trap at all.
8948 So we should in fact delete the EH edges out of the block. */
8950 purge_dead_edges (bb);
8954 /* We've possibly turned single trapping insn into multiple ones. */
8955 if (flag_non_call_exceptions)
8958 blocks = sbitmap_alloc (last_basic_block);
8959 sbitmap_ones (blocks);
8960 find_many_sub_basic_blocks (blocks);
8961 sbitmap_free (blocks);
8965 commit_edge_insertions ();
8967 #ifdef ENABLE_CHECKING
8968 /* Verify that we didn't turn one trapping insn into many, and that
8969 we found and corrected all of the problems wrt fixups on the
8971 verify_flow_info ();
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