1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "insn-config.h"
26 #include "insn-flags.h"
27 #include "insn-codes.h"
31 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 /* This file contains the reload pass of the compiler, which is
38 run after register allocation has been done. It checks that
39 each insn is valid (operands required to be in registers really
40 are in registers of the proper class) and fixes up invalid ones
41 by copying values temporarily into registers for the insns
44 The results of register allocation are described by the vector
45 reg_renumber; the insns still contain pseudo regs, but reg_renumber
46 can be used to find which hard reg, if any, a pseudo reg is in.
48 The technique we always use is to free up a few hard regs that are
49 called ``reload regs'', and for each place where a pseudo reg
50 must be in a hard reg, copy it temporarily into one of the reload regs.
52 All the pseudos that were formerly allocated to the hard regs that
53 are now in use as reload regs must be ``spilled''. This means
54 that they go to other hard regs, or to stack slots if no other
55 available hard regs can be found. Spilling can invalidate more
56 insns, requiring additional need for reloads, so we must keep checking
57 until the process stabilizes.
59 For machines with different classes of registers, we must keep track
60 of the register class needed for each reload, and make sure that
61 we allocate enough reload registers of each class.
63 The file reload.c contains the code that checks one insn for
64 validity and reports the reloads that it needs. This file
65 is in charge of scanning the entire rtl code, accumulating the
66 reload needs, spilling, assigning reload registers to use for
67 fixing up each insn, and generating the new insns to copy values
68 into the reload registers. */
71 #ifndef REGISTER_MOVE_COST
72 #define REGISTER_MOVE_COST(x, y) 2
75 #ifndef MEMORY_MOVE_COST
76 #define MEMORY_MOVE_COST(x) 4
79 /* During reload_as_needed, element N contains a REG rtx for the hard reg
80 into which reg N has been reloaded (perhaps for a previous insn). */
81 static rtx *reg_last_reload_reg;
83 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
84 for an output reload that stores into reg N. */
85 static char *reg_has_output_reload;
87 /* Indicates which hard regs are reload-registers for an output reload
88 in the current insn. */
89 static HARD_REG_SET reg_is_output_reload;
91 /* Element N is the constant value to which pseudo reg N is equivalent,
92 or zero if pseudo reg N is not equivalent to a constant.
93 find_reloads looks at this in order to replace pseudo reg N
94 with the constant it stands for. */
95 rtx *reg_equiv_constant;
97 /* Element N is a memory location to which pseudo reg N is equivalent,
98 prior to any register elimination (such as frame pointer to stack
99 pointer). Depending on whether or not it is a valid address, this value
100 is transferred to either reg_equiv_address or reg_equiv_mem. */
101 rtx *reg_equiv_memory_loc;
103 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
104 This is used when the address is not valid as a memory address
105 (because its displacement is too big for the machine.) */
106 rtx *reg_equiv_address;
108 /* Element N is the memory slot to which pseudo reg N is equivalent,
109 or zero if pseudo reg N is not equivalent to a memory slot. */
112 /* Widest width in which each pseudo reg is referred to (via subreg). */
113 static int *reg_max_ref_width;
115 /* Element N is the insn that initialized reg N from its equivalent
116 constant or memory slot. */
117 static rtx *reg_equiv_init;
119 /* During reload_as_needed, element N contains the last pseudo regno
120 reloaded into the Nth reload register. This vector is in parallel
121 with spill_regs. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
126 /* During reload_as_needed, element N contains the insn for which
127 the Nth reload register was last used. This vector is in parallel
128 with spill_regs, and its contents are significant only when
129 reg_reloaded_contents is significant. */
130 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
132 /* Number of spill-regs so far; number of valid elements of spill_regs. */
135 /* In parallel with spill_regs, contains REG rtx's for those regs.
136 Holds the last rtx used for any given reg, or 0 if it has never
137 been used for spilling yet. This rtx is reused, provided it has
139 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
141 /* In parallel with spill_regs, contains nonzero for a spill reg
142 that was stored after the last time it was used.
143 The precise value is the insn generated to do the store. */
144 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
146 /* This table is the inverse mapping of spill_regs:
147 indexed by hard reg number,
148 it contains the position of that reg in spill_regs,
149 or -1 for something that is not in spill_regs. */
150 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
152 /* This reg set indicates registers that may not be used for retrying global
153 allocation. The registers that may not be used include all spill registers
154 and the frame pointer (if we are using one). */
155 HARD_REG_SET forbidden_regs;
157 /* This reg set indicates registers that are not good for spill registers.
158 They will not be used to complete groups of spill registers. This includes
159 all fixed registers, registers that may be eliminated, and, if
160 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
162 (spill_reg_order prevents these registers from being used to start a
164 static HARD_REG_SET bad_spill_regs;
166 /* Describes order of use of registers for reloading
167 of spilled pseudo-registers. `spills' is the number of
168 elements that are actually valid; new ones are added at the end. */
169 static short spill_regs[FIRST_PSEUDO_REGISTER];
171 /* Describes order of preference for putting regs into spill_regs.
172 Contains the numbers of all the hard regs, in order most preferred first.
173 This order is different for each function.
174 It is set up by order_regs_for_reload.
175 Empty elements at the end contain -1. */
176 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
178 /* 1 for a hard register that appears explicitly in the rtl
179 (for example, function value registers, special registers
180 used by insns, structure value pointer registers). */
181 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
183 /* Indicates if a register was counted against the need for
184 groups. 0 means it can count against max_nongroup instead. */
185 static HARD_REG_SET counted_for_groups;
187 /* Indicates if a register was counted against the need for
188 non-groups. 0 means it can become part of a new group.
189 During choose_reload_regs, 1 here means don't use this reg
190 as part of a group, even if it seems to be otherwise ok. */
191 static HARD_REG_SET counted_for_nongroups;
193 /* Indexed by pseudo reg number N,
194 says may not delete stores into the real (memory) home of pseudo N.
195 This is set if we already substituted a memory equivalent in some uses,
196 which happens when we have to eliminate the fp from it. */
197 static char *cannot_omit_stores;
199 /* Nonzero if indirect addressing is supported on the machine; this means
200 that spilling (REG n) does not require reloading it into a register in
201 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
202 value indicates the level of indirect addressing supported, e.g., two
203 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
206 static char spill_indirect_levels;
208 /* Nonzero if indirect addressing is supported when the innermost MEM is
209 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
210 which these are valid is the same as spill_indirect_levels, above. */
212 char indirect_symref_ok;
214 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
216 char double_reg_address_ok;
218 /* Record the stack slot for each spilled hard register. */
220 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
222 /* Width allocated so far for that stack slot. */
224 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
226 /* Indexed by register class and basic block number, nonzero if there is
227 any need for a spill register of that class in that basic block.
228 The pointer is 0 if we did stupid allocation and don't know
229 the structure of basic blocks. */
231 char *basic_block_needs[N_REG_CLASSES];
233 /* First uid used by insns created by reload in this function.
234 Used in find_equiv_reg. */
235 int reload_first_uid;
237 /* Flag set by local-alloc or global-alloc if anything is live in
238 a call-clobbered reg across calls. */
240 int caller_save_needed;
242 /* Set to 1 while reload_as_needed is operating.
243 Required by some machines to handle any generated moves differently. */
245 int reload_in_progress = 0;
247 /* These arrays record the insn_code of insns that may be needed to
248 perform input and output reloads of special objects. They provide a
249 place to pass a scratch register. */
251 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
252 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
254 /* This obstack is used for allocation of rtl during register elimination.
255 The allocated storage can be freed once find_reloads has processed the
258 struct obstack reload_obstack;
259 char *reload_firstobj;
261 #define obstack_chunk_alloc xmalloc
262 #define obstack_chunk_free free
264 /* List of labels that must never be deleted. */
265 extern rtx forced_labels;
267 /* This structure is used to record information about register eliminations.
268 Each array entry describes one possible way of eliminating a register
269 in favor of another. If there is more than one way of eliminating a
270 particular register, the most preferred should be specified first. */
272 static struct elim_table
274 int from; /* Register number to be eliminated. */
275 int to; /* Register number used as replacement. */
276 int initial_offset; /* Initial difference between values. */
277 int can_eliminate; /* Non-zero if this elimination can be done. */
278 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
279 insns made by reload. */
280 int offset; /* Current offset between the two regs. */
281 int max_offset; /* Maximum offset between the two regs. */
282 int previous_offset; /* Offset at end of previous insn. */
283 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
284 rtx from_rtx; /* REG rtx for the register to be eliminated.
285 We cannot simply compare the number since
286 we might then spuriously replace a hard
287 register corresponding to a pseudo
288 assigned to the reg to be eliminated. */
289 rtx to_rtx; /* REG rtx for the replacement. */
292 /* If a set of eliminable registers was specified, define the table from it.
293 Otherwise, default to the normal case of the frame pointer being
294 replaced by the stack pointer. */
296 #ifdef ELIMINABLE_REGS
299 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
302 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
304 /* Record the number of pending eliminations that have an offset not equal
305 to their initial offset. If non-zero, we use a new copy of each
306 replacement result in any insns encountered. */
307 static int num_not_at_initial_offset;
309 /* Count the number of registers that we may be able to eliminate. */
310 static int num_eliminable;
312 /* For each label, we record the offset of each elimination. If we reach
313 a label by more than one path and an offset differs, we cannot do the
314 elimination. This information is indexed by the number of the label.
315 The first table is an array of flags that records whether we have yet
316 encountered a label and the second table is an array of arrays, one
317 entry in the latter array for each elimination. */
319 static char *offsets_known_at;
320 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
322 /* Number of labels in the current function. */
324 static int num_labels;
326 struct hard_reg_n_uses { int regno; int uses; };
328 static int possible_group_p PROTO((int, int *));
329 static void count_possible_groups PROTO((int *, enum machine_mode *,
331 static int modes_equiv_for_class_p PROTO((enum machine_mode,
334 static void spill_failure PROTO((rtx));
335 static int new_spill_reg PROTO((int, int, int *, int *, int,
337 static void delete_dead_insn PROTO((rtx));
338 static void alter_reg PROTO((int, int));
339 static void mark_scratch_live PROTO((rtx));
340 static void set_label_offsets PROTO((rtx, rtx, int));
341 static int eliminate_regs_in_insn PROTO((rtx, int));
342 static void mark_not_eliminable PROTO((rtx, rtx));
343 static int spill_hard_reg PROTO((int, int, FILE *, int));
344 static void scan_paradoxical_subregs PROTO((rtx));
345 static int hard_reg_use_compare PROTO((struct hard_reg_n_uses *,
346 struct hard_reg_n_uses *));
347 static void order_regs_for_reload PROTO((void));
348 static void reload_as_needed PROTO((rtx, int));
349 static void forget_old_reloads_1 PROTO((rtx, rtx));
350 static int reload_reg_class_lower PROTO((short *, short *));
351 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
353 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
355 static int reload_reg_free_p PROTO((int, int, enum reload_type));
356 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
357 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
358 static int allocate_reload_reg PROTO((int, rtx, int, int));
359 static void choose_reload_regs PROTO((rtx, rtx));
360 static void merge_assigned_reloads PROTO((rtx));
361 static void emit_reload_insns PROTO((rtx));
362 static void delete_output_reload PROTO((rtx, int, rtx));
363 static void inc_for_reload PROTO((rtx, rtx, int));
364 static int constraint_accepts_reg_p PROTO((char *, rtx));
365 static int count_occurrences PROTO((rtx, rtx));
367 /* Initialize the reload pass once per compilation. */
374 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
375 Set spill_indirect_levels to the number of levels such addressing is
376 permitted, zero if it is not permitted at all. */
379 = gen_rtx (MEM, Pmode,
380 gen_rtx (PLUS, Pmode,
381 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
383 spill_indirect_levels = 0;
385 while (memory_address_p (QImode, tem))
387 spill_indirect_levels++;
388 tem = gen_rtx (MEM, Pmode, tem);
391 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
393 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
394 indirect_symref_ok = memory_address_p (QImode, tem);
396 /* See if reg+reg is a valid (and offsettable) address. */
398 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
400 tem = gen_rtx (PLUS, Pmode,
401 gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM),
402 gen_rtx (REG, Pmode, i));
403 /* This way, we make sure that reg+reg is an offsettable address. */
404 tem = plus_constant (tem, 4);
406 if (memory_address_p (QImode, tem))
408 double_reg_address_ok = 1;
413 /* Initialize obstack for our rtl allocation. */
414 gcc_obstack_init (&reload_obstack);
415 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
418 /* Main entry point for the reload pass.
420 FIRST is the first insn of the function being compiled.
422 GLOBAL nonzero means we were called from global_alloc
423 and should attempt to reallocate any pseudoregs that we
424 displace from hard regs we will use for reloads.
425 If GLOBAL is zero, we do not have enough information to do that,
426 so any pseudo reg that is spilled must go to the stack.
428 DUMPFILE is the global-reg debugging dump file stream, or 0.
429 If it is nonzero, messages are written to it to describe
430 which registers are seized as reload regs, which pseudo regs
431 are spilled from them, and where the pseudo regs are reallocated to.
433 Return value is nonzero if reload failed
434 and we must not do any more for this function. */
437 reload (first, global, dumpfile)
445 register struct elim_table *ep;
447 int something_changed;
448 int something_needs_reloads;
449 int something_needs_elimination;
450 int new_basic_block_needs;
451 enum reg_class caller_save_spill_class = NO_REGS;
452 int caller_save_group_size = 1;
454 /* Nonzero means we couldn't get enough spill regs. */
457 /* The basic block number currently being processed for INSN. */
460 /* Make sure even insns with volatile mem refs are recognizable. */
463 /* Enable find_equiv_reg to distinguish insns made by reload. */
464 reload_first_uid = get_max_uid ();
466 for (i = 0; i < N_REG_CLASSES; i++)
467 basic_block_needs[i] = 0;
469 #ifdef SECONDARY_MEMORY_NEEDED
470 /* Initialize the secondary memory table. */
471 clear_secondary_mem ();
474 /* Remember which hard regs appear explicitly
475 before we merge into `regs_ever_live' the ones in which
476 pseudo regs have been allocated. */
477 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
479 /* We don't have a stack slot for any spill reg yet. */
480 bzero (spill_stack_slot, sizeof spill_stack_slot);
481 bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
483 /* Initialize the save area information for caller-save, in case some
487 /* Compute which hard registers are now in use
488 as homes for pseudo registers.
489 This is done here rather than (eg) in global_alloc
490 because this point is reached even if not optimizing. */
492 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
495 for (i = 0; i < scratch_list_length; i++)
497 mark_scratch_live (scratch_list[i]);
499 /* Make sure that the last insn in the chain
500 is not something that needs reloading. */
501 emit_note (NULL_PTR, NOTE_INSN_DELETED);
503 /* Find all the pseudo registers that didn't get hard regs
504 but do have known equivalent constants or memory slots.
505 These include parameters (known equivalent to parameter slots)
506 and cse'd or loop-moved constant memory addresses.
508 Record constant equivalents in reg_equiv_constant
509 so they will be substituted by find_reloads.
510 Record memory equivalents in reg_mem_equiv so they can
511 be substituted eventually by altering the REG-rtx's. */
513 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
514 bzero (reg_equiv_constant, max_regno * sizeof (rtx));
515 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
516 bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
517 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
518 bzero (reg_equiv_mem, max_regno * sizeof (rtx));
519 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
520 bzero (reg_equiv_init, max_regno * sizeof (rtx));
521 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
522 bzero (reg_equiv_address, max_regno * sizeof (rtx));
523 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
524 bzero (reg_max_ref_width, max_regno * sizeof (int));
525 cannot_omit_stores = (char *) alloca (max_regno);
526 bzero (cannot_omit_stores, max_regno);
528 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
529 Also find all paradoxical subregs
530 and find largest such for each pseudo. */
532 for (insn = first; insn; insn = NEXT_INSN (insn))
534 rtx set = single_set (insn);
536 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
538 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
540 #ifdef LEGITIMATE_PIC_OPERAND_P
541 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
542 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
546 rtx x = XEXP (note, 0);
547 i = REGNO (SET_DEST (set));
548 if (i > LAST_VIRTUAL_REGISTER)
550 if (GET_CODE (x) == MEM)
551 reg_equiv_memory_loc[i] = x;
552 else if (CONSTANT_P (x))
554 if (LEGITIMATE_CONSTANT_P (x))
555 reg_equiv_constant[i] = x;
557 reg_equiv_memory_loc[i]
558 = force_const_mem (GET_MODE (SET_DEST (set)), x);
563 /* If this register is being made equivalent to a MEM
564 and the MEM is not SET_SRC, the equivalencing insn
565 is one with the MEM as a SET_DEST and it occurs later.
566 So don't mark this insn now. */
567 if (GET_CODE (x) != MEM
568 || rtx_equal_p (SET_SRC (set), x))
569 reg_equiv_init[i] = insn;
574 /* If this insn is setting a MEM from a register equivalent to it,
575 this is the equivalencing insn. */
576 else if (set && GET_CODE (SET_DEST (set)) == MEM
577 && GET_CODE (SET_SRC (set)) == REG
578 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
579 && rtx_equal_p (SET_DEST (set),
580 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
581 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
583 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
584 scan_paradoxical_subregs (PATTERN (insn));
587 /* Does this function require a frame pointer? */
589 frame_pointer_needed = (! flag_omit_frame_pointer
590 #ifdef EXIT_IGNORE_STACK
591 /* ?? If EXIT_IGNORE_STACK is set, we will not save
592 and restore sp for alloca. So we can't eliminate
593 the frame pointer in that case. At some point,
594 we should improve this by emitting the
595 sp-adjusting insns for this case. */
596 || (current_function_calls_alloca
597 && EXIT_IGNORE_STACK)
599 || FRAME_POINTER_REQUIRED);
603 /* Initialize the table of registers to eliminate. The way we do this
604 depends on how the eliminable registers were defined. */
605 #ifdef ELIMINABLE_REGS
606 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
608 ep->can_eliminate = ep->can_eliminate_previous
609 = (CAN_ELIMINATE (ep->from, ep->to)
610 && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed));
613 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
614 = ! frame_pointer_needed;
617 /* Count the number of eliminable registers and build the FROM and TO
618 REG rtx's. Note that code in gen_rtx will cause, e.g.,
619 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
620 We depend on this. */
621 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
623 num_eliminable += ep->can_eliminate;
624 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
625 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
628 num_labels = max_label_num () - get_first_label_num ();
630 /* Allocate the tables used to store offset information at labels. */
631 offsets_known_at = (char *) alloca (num_labels);
633 = (int (*)[NUM_ELIMINABLE_REGS])
634 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
636 offsets_known_at -= get_first_label_num ();
637 offsets_at -= get_first_label_num ();
639 /* Alter each pseudo-reg rtx to contain its hard reg number.
640 Assign stack slots to the pseudos that lack hard regs or equivalents.
641 Do not touch virtual registers. */
643 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
646 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
647 because the stack size may be a part of the offset computation for
648 register elimination. */
649 assign_stack_local (BLKmode, 0, 0);
651 /* If we have some registers we think can be eliminated, scan all insns to
652 see if there is an insn that sets one of these registers to something
653 other than itself plus a constant. If so, the register cannot be
654 eliminated. Doing this scan here eliminates an extra pass through the
655 main reload loop in the most common case where register elimination
657 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
658 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
659 || GET_CODE (insn) == CALL_INSN)
660 note_stores (PATTERN (insn), mark_not_eliminable);
662 #ifndef REGISTER_CONSTRAINTS
663 /* If all the pseudo regs have hard regs,
664 except for those that are never referenced,
665 we know that no reloads are needed. */
666 /* But that is not true if there are register constraints, since
667 in that case some pseudos might be in the wrong kind of hard reg. */
669 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
670 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
673 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
677 /* Compute the order of preference for hard registers to spill.
678 Store them by decreasing preference in potential_reload_regs. */
680 order_regs_for_reload ();
682 /* So far, no hard regs have been spilled. */
684 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
685 spill_reg_order[i] = -1;
687 /* On most machines, we can't use any register explicitly used in the
688 rtl as a spill register. But on some, we have to. Those will have
689 taken care to keep the life of hard regs as short as possible. */
691 #ifdef SMALL_REGISTER_CLASSES
692 CLEAR_HARD_REG_SET (forbidden_regs);
694 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
697 /* Spill any hard regs that we know we can't eliminate. */
698 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
699 if (! ep->can_eliminate)
701 spill_hard_reg (ep->from, global, dumpfile, 1);
702 regs_ever_live[ep->from] = 1;
706 for (i = 0; i < N_REG_CLASSES; i++)
708 basic_block_needs[i] = (char *)alloca (n_basic_blocks);
709 bzero (basic_block_needs[i], n_basic_blocks);
712 /* From now on, we need to emit any moves without making new pseudos. */
713 reload_in_progress = 1;
715 /* This loop scans the entire function each go-round
716 and repeats until one repetition spills no additional hard regs. */
718 /* This flag is set when a pseudo reg is spilled,
719 to require another pass. Note that getting an additional reload
720 reg does not necessarily imply any pseudo reg was spilled;
721 sometimes we find a reload reg that no pseudo reg was allocated in. */
722 something_changed = 1;
723 /* This flag is set if there are any insns that require reloading. */
724 something_needs_reloads = 0;
725 /* This flag is set if there are any insns that require register
727 something_needs_elimination = 0;
728 while (something_changed)
732 /* For each class, number of reload regs needed in that class.
733 This is the maximum over all insns of the needs in that class
734 of the individual insn. */
735 int max_needs[N_REG_CLASSES];
736 /* For each class, size of group of consecutive regs
737 that is needed for the reloads of this class. */
738 int group_size[N_REG_CLASSES];
739 /* For each class, max number of consecutive groups needed.
740 (Each group contains group_size[CLASS] consecutive registers.) */
741 int max_groups[N_REG_CLASSES];
742 /* For each class, max number needed of regs that don't belong
743 to any of the groups. */
744 int max_nongroups[N_REG_CLASSES];
745 /* For each class, the machine mode which requires consecutive
746 groups of regs of that class.
747 If two different modes ever require groups of one class,
748 they must be the same size and equally restrictive for that class,
749 otherwise we can't handle the complexity. */
750 enum machine_mode group_mode[N_REG_CLASSES];
751 /* Record the insn where each maximum need is first found. */
752 rtx max_needs_insn[N_REG_CLASSES];
753 rtx max_groups_insn[N_REG_CLASSES];
754 rtx max_nongroups_insn[N_REG_CLASSES];
756 int starting_frame_size = get_frame_size ();
757 static char *reg_class_names[] = REG_CLASS_NAMES;
759 something_changed = 0;
760 bzero (max_needs, sizeof max_needs);
761 bzero (max_groups, sizeof max_groups);
762 bzero (max_nongroups, sizeof max_nongroups);
763 bzero (max_needs_insn, sizeof max_needs_insn);
764 bzero (max_groups_insn, sizeof max_groups_insn);
765 bzero (max_nongroups_insn, sizeof max_nongroups_insn);
766 bzero (group_size, sizeof group_size);
767 for (i = 0; i < N_REG_CLASSES; i++)
768 group_mode[i] = VOIDmode;
770 /* Keep track of which basic blocks are needing the reloads. */
773 /* Remember whether any element of basic_block_needs
774 changes from 0 to 1 in this pass. */
775 new_basic_block_needs = 0;
777 /* Reset all offsets on eliminable registers to their initial values. */
778 #ifdef ELIMINABLE_REGS
779 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
781 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
782 ep->previous_offset = ep->offset
783 = ep->max_offset = ep->initial_offset;
786 #ifdef INITIAL_FRAME_POINTER_OFFSET
787 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
789 if (!FRAME_POINTER_REQUIRED)
791 reg_eliminate[0].initial_offset = 0;
793 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
794 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
797 num_not_at_initial_offset = 0;
799 bzero (&offsets_known_at[get_first_label_num ()], num_labels);
801 /* Set a known offset for each forced label to be at the initial offset
802 of each elimination. We do this because we assume that all
803 computed jumps occur from a location where each elimination is
804 at its initial offset. */
806 for (x = forced_labels; x; x = XEXP (x, 1))
808 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
810 /* For each pseudo register that has an equivalent location defined,
811 try to eliminate any eliminable registers (such as the frame pointer)
812 assuming initial offsets for the replacement register, which
815 If the resulting location is directly addressable, substitute
816 the MEM we just got directly for the old REG.
818 If it is not addressable but is a constant or the sum of a hard reg
819 and constant, it is probably not addressable because the constant is
820 out of range, in that case record the address; we will generate
821 hairy code to compute the address in a register each time it is
822 needed. Similarly if it is a hard register, but one that is not
823 valid as an address register.
825 If the location is not addressable, but does not have one of the
826 above forms, assign a stack slot. We have to do this to avoid the
827 potential of producing lots of reloads if, e.g., a location involves
828 a pseudo that didn't get a hard register and has an equivalent memory
829 location that also involves a pseudo that didn't get a hard register.
831 Perhaps at some point we will improve reload_when_needed handling
832 so this problem goes away. But that's very hairy. */
834 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
835 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
837 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
839 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
841 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
842 else if (CONSTANT_P (XEXP (x, 0))
843 || (GET_CODE (XEXP (x, 0)) == REG
844 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
845 || (GET_CODE (XEXP (x, 0)) == PLUS
846 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
847 && (REGNO (XEXP (XEXP (x, 0), 0))
848 < FIRST_PSEUDO_REGISTER)
849 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
850 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
853 /* Make a new stack slot. Then indicate that something
854 changed so we go back and recompute offsets for
855 eliminable registers because the allocation of memory
856 below might change some offset. reg_equiv_{mem,address}
857 will be set up for this pseudo on the next pass around
859 reg_equiv_memory_loc[i] = 0;
860 reg_equiv_init[i] = 0;
862 something_changed = 1;
866 /* If we allocated another pseudo to the stack, redo elimination
868 if (something_changed)
871 /* If caller-saves needs a group, initialize the group to include
872 the size and mode required for caller-saves. */
874 if (caller_save_group_size > 1)
876 group_mode[(int) caller_save_spill_class] = Pmode;
877 group_size[(int) caller_save_spill_class] = caller_save_group_size;
880 /* Compute the most additional registers needed by any instruction.
881 Collect information separately for each class of regs. */
883 for (insn = first; insn; insn = NEXT_INSN (insn))
885 if (global && this_block + 1 < n_basic_blocks
886 && insn == basic_block_head[this_block+1])
889 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
890 might include REG_LABEL), we need to see what effects this
891 has on the known offsets at labels. */
893 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
894 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
895 && REG_NOTES (insn) != 0))
896 set_label_offsets (insn, insn, 0);
898 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
900 /* Nonzero means don't use a reload reg that overlaps
901 the place where a function value can be returned. */
902 rtx avoid_return_reg = 0;
904 rtx old_body = PATTERN (insn);
905 int old_code = INSN_CODE (insn);
906 rtx old_notes = REG_NOTES (insn);
907 int did_elimination = 0;
908 int max_total_input_groups = 0, max_total_output_groups = 0;
910 /* To compute the number of reload registers of each class
911 needed for an insn, we must similate what choose_reload_regs
912 can do. We do this by splitting an insn into an "input" and
913 an "output" part. RELOAD_OTHER reloads are used in both.
914 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
915 which must be live over the entire input section of reloads,
916 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
917 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
920 The registers needed for output are RELOAD_OTHER and
921 RELOAD_FOR_OUTPUT, which are live for the entire output
922 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
923 reloads for each operand.
925 The total number of registers needed is the maximum of the
926 inputs and outputs. */
928 /* These just count RELOAD_OTHER. */
929 int insn_needs[N_REG_CLASSES];
930 int insn_groups[N_REG_CLASSES];
931 int insn_total_groups = 0;
933 /* Count RELOAD_FOR_INPUT reloads. */
934 int insn_needs_for_inputs[N_REG_CLASSES];
935 int insn_groups_for_inputs[N_REG_CLASSES];
936 int insn_total_groups_for_inputs = 0;
938 /* Count RELOAD_FOR_OUTPUT reloads. */
939 int insn_needs_for_outputs[N_REG_CLASSES];
940 int insn_groups_for_outputs[N_REG_CLASSES];
941 int insn_total_groups_for_outputs = 0;
943 /* Count RELOAD_FOR_INSN reloads. */
944 int insn_needs_for_insn[N_REG_CLASSES];
945 int insn_groups_for_insn[N_REG_CLASSES];
946 int insn_total_groups_for_insn = 0;
948 /* Count RELOAD_FOR_OTHER_ADDRESS reloads. */
949 int insn_needs_for_other_addr[N_REG_CLASSES];
950 int insn_groups_for_other_addr[N_REG_CLASSES];
951 int insn_total_groups_for_other_addr = 0;
953 /* Count RELOAD_FOR_INPUT_ADDRESS reloads. */
954 int insn_needs_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
955 int insn_groups_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
956 int insn_total_groups_for_in_addr[MAX_RECOG_OPERANDS];
958 /* Count RELOAD_FOR_OUTPUT_ADDRESS reloads. */
959 int insn_needs_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
960 int insn_groups_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
961 int insn_total_groups_for_out_addr[MAX_RECOG_OPERANDS];
963 /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
964 int insn_needs_for_op_addr[N_REG_CLASSES];
965 int insn_groups_for_op_addr[N_REG_CLASSES];
966 int insn_total_groups_for_op_addr = 0;
968 #if 0 /* This wouldn't work nowadays, since optimize_bit_field
969 looks for non-strict memory addresses. */
970 /* Optimization: a bit-field instruction whose field
971 happens to be a byte or halfword in memory
972 can be changed to a move instruction. */
974 if (GET_CODE (PATTERN (insn)) == SET)
976 rtx dest = SET_DEST (PATTERN (insn));
977 rtx src = SET_SRC (PATTERN (insn));
979 if (GET_CODE (dest) == ZERO_EXTRACT
980 || GET_CODE (dest) == SIGN_EXTRACT)
981 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
982 if (GET_CODE (src) == ZERO_EXTRACT
983 || GET_CODE (src) == SIGN_EXTRACT)
984 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
988 /* If needed, eliminate any eliminable registers. */
990 did_elimination = eliminate_regs_in_insn (insn, 0);
992 #ifdef SMALL_REGISTER_CLASSES
993 /* Set avoid_return_reg if this is an insn
994 that might use the value of a function call. */
995 if (GET_CODE (insn) == CALL_INSN)
997 if (GET_CODE (PATTERN (insn)) == SET)
998 after_call = SET_DEST (PATTERN (insn));
999 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1000 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1001 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
1005 else if (after_call != 0
1006 && !(GET_CODE (PATTERN (insn)) == SET
1007 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
1009 if (reg_mentioned_p (after_call, PATTERN (insn)))
1010 avoid_return_reg = after_call;
1013 #endif /* SMALL_REGISTER_CLASSES */
1015 /* Analyze the instruction. */
1016 find_reloads (insn, 0, spill_indirect_levels, global,
1019 /* Remember for later shortcuts which insns had any reloads or
1020 register eliminations.
1022 One might think that it would be worthwhile to mark insns
1023 that need register replacements but not reloads, but this is
1024 not safe because find_reloads may do some manipulation of
1025 the insn (such as swapping commutative operands), which would
1026 be lost when we restore the old pattern after register
1027 replacement. So the actions of find_reloads must be redone in
1028 subsequent passes or in reload_as_needed.
1030 However, it is safe to mark insns that need reloads
1031 but not register replacement. */
1033 PUT_MODE (insn, (did_elimination ? QImode
1034 : n_reloads ? HImode
1035 : GET_MODE (insn) == DImode ? DImode
1038 /* Discard any register replacements done. */
1039 if (did_elimination)
1041 obstack_free (&reload_obstack, reload_firstobj);
1042 PATTERN (insn) = old_body;
1043 INSN_CODE (insn) = old_code;
1044 REG_NOTES (insn) = old_notes;
1045 something_needs_elimination = 1;
1048 /* If this insn has no reloads, we need not do anything except
1049 in the case of a CALL_INSN when we have caller-saves and
1050 caller-save needs reloads. */
1053 && ! (GET_CODE (insn) == CALL_INSN
1054 && caller_save_spill_class != NO_REGS))
1057 something_needs_reloads = 1;
1059 for (i = 0; i < N_REG_CLASSES; i++)
1061 insn_needs[i] = 0, insn_groups[i] = 0;
1062 insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0;
1063 insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0;
1064 insn_needs_for_insn[i] = 0, insn_groups_for_insn[i] = 0;
1065 insn_needs_for_op_addr[i] = 0, insn_groups_for_op_addr[i] = 0;
1066 insn_needs_for_other_addr[i] = 0;
1067 insn_groups_for_other_addr[i] = 0;
1070 for (i = 0; i < reload_n_operands; i++)
1072 insn_total_groups_for_in_addr[i] = 0;
1073 insn_total_groups_for_out_addr[i] = 0;
1075 for (j = 0; j < N_REG_CLASSES; j++)
1077 insn_needs_for_in_addr[i][j] = 0;
1078 insn_needs_for_out_addr[i][j] = 0;
1079 insn_groups_for_in_addr[i][j] = 0;
1080 insn_groups_for_out_addr[i][j] = 0;
1084 /* Count each reload once in every class
1085 containing the reload's own class. */
1087 for (i = 0; i < n_reloads; i++)
1089 register enum reg_class *p;
1090 enum reg_class class = reload_reg_class[i];
1092 enum machine_mode mode;
1095 int *this_total_groups;
1097 /* Don't count the dummy reloads, for which one of the
1098 regs mentioned in the insn can be used for reloading.
1099 Don't count optional reloads.
1100 Don't count reloads that got combined with others. */
1101 if (reload_reg_rtx[i] != 0
1102 || reload_optional[i] != 0
1103 || (reload_out[i] == 0 && reload_in[i] == 0
1104 && ! reload_secondary_p[i]))
1107 /* Show that a reload register of this class is needed
1108 in this basic block. We do not use insn_needs and
1109 insn_groups because they are overly conservative for
1111 if (global && ! basic_block_needs[(int) class][this_block])
1113 basic_block_needs[(int) class][this_block] = 1;
1114 new_basic_block_needs = 1;
1117 /* Decide which time-of-use to count this reload for. */
1118 switch (reload_when_needed[i])
1121 this_needs = insn_needs;
1122 this_groups = insn_groups;
1123 this_total_groups = &insn_total_groups;
1126 case RELOAD_FOR_INPUT:
1127 this_needs = insn_needs_for_inputs;
1128 this_groups = insn_groups_for_inputs;
1129 this_total_groups = &insn_total_groups_for_inputs;
1132 case RELOAD_FOR_OUTPUT:
1133 this_needs = insn_needs_for_outputs;
1134 this_groups = insn_groups_for_outputs;
1135 this_total_groups = &insn_total_groups_for_outputs;
1138 case RELOAD_FOR_INSN:
1139 this_needs = insn_needs_for_insn;
1140 this_groups = insn_groups_for_outputs;
1141 this_total_groups = &insn_total_groups_for_insn;
1144 case RELOAD_FOR_OTHER_ADDRESS:
1145 this_needs = insn_needs_for_other_addr;
1146 this_groups = insn_groups_for_other_addr;
1147 this_total_groups = &insn_total_groups_for_other_addr;
1150 case RELOAD_FOR_INPUT_ADDRESS:
1151 this_needs = insn_needs_for_in_addr[reload_opnum[i]];
1152 this_groups = insn_groups_for_in_addr[reload_opnum[i]];
1154 = &insn_total_groups_for_in_addr[reload_opnum[i]];
1157 case RELOAD_FOR_OUTPUT_ADDRESS:
1158 this_needs = insn_needs_for_out_addr[reload_opnum[i]];
1159 this_groups = insn_groups_for_out_addr[reload_opnum[i]];
1161 = &insn_total_groups_for_out_addr[reload_opnum[i]];
1164 case RELOAD_FOR_OPERAND_ADDRESS:
1165 this_needs = insn_needs_for_op_addr;
1166 this_groups = insn_groups_for_op_addr;
1167 this_total_groups = &insn_total_groups_for_op_addr;
1171 mode = reload_inmode[i];
1172 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1173 mode = reload_outmode[i];
1174 size = CLASS_MAX_NREGS (class, mode);
1177 enum machine_mode other_mode, allocate_mode;
1179 /* Count number of groups needed separately from
1180 number of individual regs needed. */
1181 this_groups[(int) class]++;
1182 p = reg_class_superclasses[(int) class];
1183 while (*p != LIM_REG_CLASSES)
1184 this_groups[(int) *p++]++;
1185 (*this_total_groups)++;
1187 /* Record size and mode of a group of this class. */
1188 /* If more than one size group is needed,
1189 make all groups the largest needed size. */
1190 if (group_size[(int) class] < size)
1192 other_mode = group_mode[(int) class];
1193 allocate_mode = mode;
1195 group_size[(int) class] = size;
1196 group_mode[(int) class] = mode;
1201 allocate_mode = group_mode[(int) class];
1204 /* Crash if two dissimilar machine modes both need
1205 groups of consecutive regs of the same class. */
1207 if (other_mode != VOIDmode
1208 && other_mode != allocate_mode
1209 && ! modes_equiv_for_class_p (allocate_mode,
1216 this_needs[(int) class] += 1;
1217 p = reg_class_superclasses[(int) class];
1218 while (*p != LIM_REG_CLASSES)
1219 this_needs[(int) *p++] += 1;
1225 /* All reloads have been counted for this insn;
1226 now merge the various times of use.
1227 This sets insn_needs, etc., to the maximum total number
1228 of registers needed at any point in this insn. */
1230 for (i = 0; i < N_REG_CLASSES; i++)
1232 int in_max, out_max;
1234 for (in_max = 0, out_max = 0, j = 0;
1235 j < reload_n_operands; j++)
1237 in_max = MAX (in_max, insn_needs_for_in_addr[j][i]);
1238 out_max = MAX (out_max, insn_needs_for_out_addr[j][i]);
1241 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1242 and operand addresses but not things used to reload them.
1243 Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads don't
1244 conflict with things needed to reload inputs or
1247 in_max = MAX (in_max, insn_needs_for_op_addr[i]);
1248 out_max = MAX (out_max, insn_needs_for_insn[i]);
1250 insn_needs_for_inputs[i]
1251 = MAX (insn_needs_for_inputs[i]
1252 + insn_needs_for_op_addr[i]
1253 + insn_needs_for_insn[i],
1254 in_max + insn_needs_for_inputs[i]);
1256 insn_needs_for_outputs[i] += out_max;
1257 insn_needs[i] += MAX (MAX (insn_needs_for_inputs[i],
1258 insn_needs_for_outputs[i]),
1259 insn_needs_for_other_addr[i]);
1261 for (in_max = 0, out_max = 0, j = 0;
1262 j < reload_n_operands; j++)
1264 in_max = MAX (in_max, insn_groups_for_in_addr[j][i]);
1265 out_max = MAX (out_max, insn_groups_for_out_addr[j][i]);
1268 in_max = MAX (in_max, insn_groups_for_op_addr[i]);
1269 out_max = MAX (out_max, insn_groups_for_insn[i]);
1271 insn_groups_for_inputs[i]
1272 = MAX (insn_groups_for_inputs[i]
1273 + insn_groups_for_op_addr[i]
1274 + insn_groups_for_insn[i],
1275 in_max + insn_groups_for_inputs[i]);
1277 insn_groups_for_outputs[i] += out_max;
1278 insn_groups[i] += MAX (MAX (insn_groups_for_inputs[i],
1279 insn_groups_for_outputs[i]),
1280 insn_groups_for_other_addr[i]);
1283 for (i = 0; i < reload_n_operands; i++)
1285 max_total_input_groups
1286 = MAX (max_total_input_groups,
1287 insn_total_groups_for_in_addr[i]);
1288 max_total_output_groups
1289 = MAX (max_total_output_groups,
1290 insn_total_groups_for_out_addr[i]);
1293 max_total_input_groups = MAX (max_total_input_groups,
1294 insn_total_groups_for_op_addr);
1295 max_total_output_groups = MAX (max_total_output_groups,
1296 insn_total_groups_for_insn);
1298 insn_total_groups_for_inputs
1299 = MAX (max_total_input_groups + insn_total_groups_for_op_addr
1300 + insn_total_groups_for_insn,
1301 max_total_input_groups + insn_total_groups_for_inputs);
1303 insn_total_groups_for_outputs += max_total_output_groups;
1305 insn_total_groups += MAX (MAX (insn_total_groups_for_outputs,
1306 insn_total_groups_for_inputs),
1307 insn_total_groups_for_other_addr);
1309 /* If this is a CALL_INSN and caller-saves will need
1310 a spill register, act as if the spill register is
1311 needed for this insn. However, the spill register
1312 can be used by any reload of this insn, so we only
1313 need do something if no need for that class has
1316 The assumption that every CALL_INSN will trigger a
1317 caller-save is highly conservative, however, the number
1318 of cases where caller-saves will need a spill register but
1319 a block containing a CALL_INSN won't need a spill register
1320 of that class should be quite rare.
1322 If a group is needed, the size and mode of the group will
1323 have been set up at the beginning of this loop. */
1325 if (GET_CODE (insn) == CALL_INSN
1326 && caller_save_spill_class != NO_REGS)
1328 int *caller_save_needs
1329 = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1331 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1333 register enum reg_class *p
1334 = reg_class_superclasses[(int) caller_save_spill_class];
1336 caller_save_needs[(int) caller_save_spill_class]++;
1338 while (*p != LIM_REG_CLASSES)
1339 caller_save_needs[(int) *p++] += 1;
1342 if (caller_save_group_size > 1)
1343 insn_total_groups = MAX (insn_total_groups, 1);
1346 /* Show that this basic block will need a register of
1350 && ! (basic_block_needs[(int) caller_save_spill_class]
1353 basic_block_needs[(int) caller_save_spill_class]
1355 new_basic_block_needs = 1;
1359 #ifdef SMALL_REGISTER_CLASSES
1360 /* If this insn stores the value of a function call,
1361 and that value is in a register that has been spilled,
1362 and if the insn needs a reload in a class
1363 that might use that register as the reload register,
1364 then add add an extra need in that class.
1365 This makes sure we have a register available that does
1366 not overlap the return value. */
1367 if (avoid_return_reg)
1369 int regno = REGNO (avoid_return_reg);
1371 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1373 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1375 /* First compute the "basic needs", which counts a
1376 need only in the smallest class in which it
1379 bcopy (insn_needs, basic_needs, sizeof basic_needs);
1380 bcopy (insn_groups, basic_groups, sizeof basic_groups);
1382 for (i = 0; i < N_REG_CLASSES; i++)
1386 if (basic_needs[i] >= 0)
1387 for (p = reg_class_superclasses[i];
1388 *p != LIM_REG_CLASSES; p++)
1389 basic_needs[(int) *p] -= basic_needs[i];
1391 if (basic_groups[i] >= 0)
1392 for (p = reg_class_superclasses[i];
1393 *p != LIM_REG_CLASSES; p++)
1394 basic_groups[(int) *p] -= basic_groups[i];
1397 /* Now count extra regs if there might be a conflict with
1398 the return value register.
1400 ??? This is not quite correct because we don't properly
1401 handle the case of groups, but if we end up doing
1402 something wrong, it either will end up not mattering or
1403 we will abort elsewhere. */
1405 for (r = regno; r < regno + nregs; r++)
1406 if (spill_reg_order[r] >= 0)
1407 for (i = 0; i < N_REG_CLASSES; i++)
1408 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1410 if (basic_needs[i] > 0 || basic_groups[i] > 0)
1415 p = reg_class_superclasses[i];
1416 while (*p != LIM_REG_CLASSES)
1417 insn_needs[(int) *p++]++;
1421 #endif /* SMALL_REGISTER_CLASSES */
1423 /* For each class, collect maximum need of any insn. */
1425 for (i = 0; i < N_REG_CLASSES; i++)
1427 if (max_needs[i] < insn_needs[i])
1429 max_needs[i] = insn_needs[i];
1430 max_needs_insn[i] = insn;
1432 if (max_groups[i] < insn_groups[i])
1434 max_groups[i] = insn_groups[i];
1435 max_groups_insn[i] = insn;
1437 if (insn_total_groups > 0)
1438 if (max_nongroups[i] < insn_needs[i])
1440 max_nongroups[i] = insn_needs[i];
1441 max_nongroups_insn[i] = insn;
1445 /* Note that there is a continue statement above. */
1448 /* If we allocated any new memory locations, make another pass
1449 since it might have changed elimination offsets. */
1450 if (starting_frame_size != get_frame_size ())
1451 something_changed = 1;
1454 for (i = 0; i < N_REG_CLASSES; i++)
1456 if (max_needs[i] > 0)
1458 ";; Need %d reg%s of class %s (for insn %d).\n",
1459 max_needs[i], max_needs[i] == 1 ? "" : "s",
1460 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1461 if (max_nongroups[i] > 0)
1463 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1464 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1465 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1466 if (max_groups[i] > 0)
1468 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1469 max_groups[i], max_groups[i] == 1 ? "" : "s",
1470 mode_name[(int) group_mode[i]],
1471 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1474 /* If we have caller-saves, set up the save areas and see if caller-save
1475 will need a spill register. */
1477 if (caller_save_needed
1478 && ! setup_save_areas (&something_changed)
1479 && caller_save_spill_class == NO_REGS)
1481 /* The class we will need depends on whether the machine
1482 supports the sum of two registers for an address; see
1483 find_address_reloads for details. */
1485 caller_save_spill_class
1486 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1487 caller_save_group_size
1488 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1489 something_changed = 1;
1492 /* See if anything that happened changes which eliminations are valid.
1493 For example, on the Sparc, whether or not the frame pointer can
1494 be eliminated can depend on what registers have been used. We need
1495 not check some conditions again (such as flag_omit_frame_pointer)
1496 since they can't have changed. */
1498 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1499 if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1500 #ifdef ELIMINABLE_REGS
1501 || ! CAN_ELIMINATE (ep->from, ep->to)
1504 ep->can_eliminate = 0;
1506 /* Look for the case where we have discovered that we can't replace
1507 register A with register B and that means that we will now be
1508 trying to replace register A with register C. This means we can
1509 no longer replace register C with register B and we need to disable
1510 such an elimination, if it exists. This occurs often with A == ap,
1511 B == sp, and C == fp. */
1513 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1515 struct elim_table *op;
1516 register int new_to = -1;
1518 if (! ep->can_eliminate && ep->can_eliminate_previous)
1520 /* Find the current elimination for ep->from, if there is a
1522 for (op = reg_eliminate;
1523 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1524 if (op->from == ep->from && op->can_eliminate)
1530 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1532 for (op = reg_eliminate;
1533 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1534 if (op->from == new_to && op->to == ep->to)
1535 op->can_eliminate = 0;
1539 /* See if any registers that we thought we could eliminate the previous
1540 time are no longer eliminable. If so, something has changed and we
1541 must spill the register. Also, recompute the number of eliminable
1542 registers and see if the frame pointer is needed; it is if there is
1543 no elimination of the frame pointer that we can perform. */
1545 frame_pointer_needed = 1;
1546 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1548 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM)
1549 frame_pointer_needed = 0;
1551 if (! ep->can_eliminate && ep->can_eliminate_previous)
1553 ep->can_eliminate_previous = 0;
1554 spill_hard_reg (ep->from, global, dumpfile, 1);
1555 regs_ever_live[ep->from] = 1;
1556 something_changed = 1;
1561 /* If all needs are met, we win. */
1563 for (i = 0; i < N_REG_CLASSES; i++)
1564 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1566 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1569 /* Not all needs are met; must spill some hard regs. */
1571 /* Put all registers spilled so far back in potential_reload_regs, but
1572 put them at the front, since we've already spilled most of the
1573 psuedos in them (we might have left some pseudos unspilled if they
1574 were in a block that didn't need any spill registers of a conflicting
1575 class. We used to try to mark off the need for those registers,
1576 but doing so properly is very complex and reallocating them is the
1577 simpler approach. First, "pack" potential_reload_regs by pushing
1578 any nonnegative entries towards the end. That will leave room
1579 for the registers we already spilled.
1581 Also, undo the marking of the spill registers from the last time
1582 around in FORBIDDEN_REGS since we will be probably be allocating
1585 ??? It is theoretically possible that we might end up not using one
1586 of our previously-spilled registers in this allocation, even though
1587 they are at the head of the list. It's not clear what to do about
1588 this, but it was no better before, when we marked off the needs met
1589 by the previously-spilled registers. With the current code, globals
1590 can be allocated into these registers, but locals cannot. */
1594 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1595 if (potential_reload_regs[i] != -1)
1596 potential_reload_regs[j--] = potential_reload_regs[i];
1598 for (i = 0; i < n_spills; i++)
1600 potential_reload_regs[i] = spill_regs[i];
1601 spill_reg_order[spill_regs[i]] = -1;
1602 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1608 /* Now find more reload regs to satisfy the remaining need
1609 Do it by ascending class number, since otherwise a reg
1610 might be spilled for a big class and might fail to count
1611 for a smaller class even though it belongs to that class.
1613 Count spilled regs in `spills', and add entries to
1614 `spill_regs' and `spill_reg_order'.
1616 ??? Note there is a problem here.
1617 When there is a need for a group in a high-numbered class,
1618 and also need for non-group regs that come from a lower class,
1619 the non-group regs are chosen first. If there aren't many regs,
1620 they might leave no room for a group.
1622 This was happening on the 386. To fix it, we added the code
1623 that calls possible_group_p, so that the lower class won't
1624 break up the last possible group.
1626 Really fixing the problem would require changes above
1627 in counting the regs already spilled, and in choose_reload_regs.
1628 It might be hard to avoid introducing bugs there. */
1630 CLEAR_HARD_REG_SET (counted_for_groups);
1631 CLEAR_HARD_REG_SET (counted_for_nongroups);
1633 for (class = 0; class < N_REG_CLASSES; class++)
1635 /* First get the groups of registers.
1636 If we got single registers first, we might fragment
1638 while (max_groups[class] > 0)
1640 /* If any single spilled regs happen to form groups,
1641 count them now. Maybe we don't really need
1642 to spill another group. */
1643 count_possible_groups (group_size, group_mode, max_groups);
1645 if (max_groups[class] <= 0)
1648 /* Groups of size 2 (the only groups used on most machines)
1649 are treated specially. */
1650 if (group_size[class] == 2)
1652 /* First, look for a register that will complete a group. */
1653 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1657 j = potential_reload_regs[i];
1658 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1660 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1661 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1662 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1663 && HARD_REGNO_MODE_OK (other, group_mode[class])
1664 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1666 /* We don't want one part of another group.
1667 We could get "two groups" that overlap! */
1668 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1670 (j < FIRST_PSEUDO_REGISTER - 1
1671 && (other = j + 1, spill_reg_order[other] >= 0)
1672 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1673 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1674 && HARD_REGNO_MODE_OK (j, group_mode[class])
1675 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1677 && ! TEST_HARD_REG_BIT (counted_for_groups,
1680 register enum reg_class *p;
1682 /* We have found one that will complete a group,
1683 so count off one group as provided. */
1684 max_groups[class]--;
1685 p = reg_class_superclasses[class];
1686 while (*p != LIM_REG_CLASSES)
1687 max_groups[(int) *p++]--;
1689 /* Indicate both these regs are part of a group. */
1690 SET_HARD_REG_BIT (counted_for_groups, j);
1691 SET_HARD_REG_BIT (counted_for_groups, other);
1695 /* We can't complete a group, so start one. */
1696 if (i == FIRST_PSEUDO_REGISTER)
1697 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1700 j = potential_reload_regs[i];
1701 /* Verify that J+1 is a potential reload reg. */
1702 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++)
1703 if (potential_reload_regs[k] == j + 1)
1705 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1706 && k < FIRST_PSEUDO_REGISTER
1707 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1708 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1709 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1710 && HARD_REGNO_MODE_OK (j, group_mode[class])
1711 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1713 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1))
1717 /* I should be the index in potential_reload_regs
1718 of the new reload reg we have found. */
1720 if (i >= FIRST_PSEUDO_REGISTER)
1722 /* There are no groups left to spill. */
1723 spill_failure (max_groups_insn[class]);
1729 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1734 /* For groups of more than 2 registers,
1735 look for a sufficient sequence of unspilled registers,
1736 and spill them all at once. */
1737 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1741 j = potential_reload_regs[i];
1743 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1744 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1746 /* Check each reg in the sequence. */
1747 for (k = 0; k < group_size[class]; k++)
1748 if (! (spill_reg_order[j + k] < 0
1749 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1750 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1752 /* We got a full sequence, so spill them all. */
1753 if (k == group_size[class])
1755 register enum reg_class *p;
1756 for (k = 0; k < group_size[class]; k++)
1759 SET_HARD_REG_BIT (counted_for_groups, j + k);
1760 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1761 if (potential_reload_regs[idx] == j + k)
1764 |= new_spill_reg (idx, class,
1765 max_needs, NULL_PTR,
1769 /* We have found one that will complete a group,
1770 so count off one group as provided. */
1771 max_groups[class]--;
1772 p = reg_class_superclasses[class];
1773 while (*p != LIM_REG_CLASSES)
1774 max_groups[(int) *p++]--;
1780 /* We couldn't find any registers for this reload.
1781 Avoid going into an infinite loop. */
1782 if (i >= FIRST_PSEUDO_REGISTER)
1784 /* There are no groups left. */
1785 spill_failure (max_groups_insn[class]);
1792 /* Now similarly satisfy all need for single registers. */
1794 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1796 #ifdef SMALL_REGISTER_CLASSES
1797 /* This should be right for all machines, but only the 386
1798 is known to need it, so this conditional plays safe.
1799 ??? For 2.5, try making this unconditional. */
1800 /* If we spilled enough regs, but they weren't counted
1801 against the non-group need, see if we can count them now.
1802 If so, we can avoid some actual spilling. */
1803 if (max_needs[class] <= 0 && max_nongroups[class] > 0)
1804 for (i = 0; i < n_spills; i++)
1805 if (TEST_HARD_REG_BIT (reg_class_contents[class],
1807 && !TEST_HARD_REG_BIT (counted_for_groups,
1809 && !TEST_HARD_REG_BIT (counted_for_nongroups,
1811 && max_nongroups[class] > 0)
1813 register enum reg_class *p;
1815 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]);
1816 max_nongroups[class]--;
1817 p = reg_class_superclasses[class];
1818 while (*p != LIM_REG_CLASSES)
1819 max_nongroups[(int) *p++]--;
1821 if (max_needs[class] <= 0 && max_nongroups[class] <= 0)
1825 /* Consider the potential reload regs that aren't
1826 yet in use as reload regs, in order of preference.
1827 Find the most preferred one that's in this class. */
1829 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1830 if (potential_reload_regs[i] >= 0
1831 && TEST_HARD_REG_BIT (reg_class_contents[class],
1832 potential_reload_regs[i])
1833 /* If this reg will not be available for groups,
1834 pick one that does not foreclose possible groups.
1835 This is a kludge, and not very general,
1836 but it should be sufficient to make the 386 work,
1837 and the problem should not occur on machines with
1839 && (max_nongroups[class] == 0
1840 || possible_group_p (potential_reload_regs[i], max_groups)))
1843 /* If we couldn't get a register, try to get one even if we
1844 might foreclose possible groups. This may cause problems
1845 later, but that's better than aborting now, since it is
1846 possible that we will, in fact, be able to form the needed
1847 group even with this allocation. */
1849 if (i >= FIRST_PSEUDO_REGISTER
1850 && (asm_noperands (max_needs[class] > 0
1851 ? max_needs_insn[class]
1852 : max_nongroups_insn[class])
1854 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1855 if (potential_reload_regs[i] >= 0
1856 && TEST_HARD_REG_BIT (reg_class_contents[class],
1857 potential_reload_regs[i]))
1860 /* I should be the index in potential_reload_regs
1861 of the new reload reg we have found. */
1863 if (i >= FIRST_PSEUDO_REGISTER)
1865 /* There are no possible registers left to spill. */
1866 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1867 : max_nongroups_insn[class]);
1873 |= new_spill_reg (i, class, max_needs, max_nongroups,
1879 /* If global-alloc was run, notify it of any register eliminations we have
1882 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1883 if (ep->can_eliminate)
1884 mark_elimination (ep->from, ep->to);
1886 /* Insert code to save and restore call-clobbered hard regs
1887 around calls. Tell if what mode to use so that we will process
1888 those insns in reload_as_needed if we have to. */
1890 if (caller_save_needed)
1891 save_call_clobbered_regs (num_eliminable ? QImode
1892 : caller_save_spill_class != NO_REGS ? HImode
1895 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1896 If that insn didn't set the register (i.e., it copied the register to
1897 memory), just delete that insn instead of the equivalencing insn plus
1898 anything now dead. If we call delete_dead_insn on that insn, we may
1899 delete the insn that actually sets the register if the register die
1900 there and that is incorrect. */
1902 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1903 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1904 && GET_CODE (reg_equiv_init[i]) != NOTE)
1906 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1907 delete_dead_insn (reg_equiv_init[i]);
1910 PUT_CODE (reg_equiv_init[i], NOTE);
1911 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1912 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1916 /* Use the reload registers where necessary
1917 by generating move instructions to move the must-be-register
1918 values into or out of the reload registers. */
1920 if (something_needs_reloads || something_needs_elimination
1921 || (caller_save_needed && num_eliminable)
1922 || caller_save_spill_class != NO_REGS)
1923 reload_as_needed (first, global);
1925 /* If we were able to eliminate the frame pointer, show that it is no
1926 longer live at the start of any basic block. If it ls live by
1927 virtue of being in a pseudo, that pseudo will be marked live
1928 and hence the frame pointer will be known to be live via that
1931 if (! frame_pointer_needed)
1932 for (i = 0; i < n_basic_blocks; i++)
1933 basic_block_live_at_start[i][FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
1934 &= ~ ((REGSET_ELT_TYPE) 1 << (FRAME_POINTER_REGNUM % REGSET_ELT_BITS));
1936 /* Come here (with failure set nonzero) if we can't get enough spill regs
1937 and we decide not to abort about it. */
1940 reload_in_progress = 0;
1942 /* Now eliminate all pseudo regs by modifying them into
1943 their equivalent memory references.
1944 The REG-rtx's for the pseudos are modified in place,
1945 so all insns that used to refer to them now refer to memory.
1947 For a reg that has a reg_equiv_address, all those insns
1948 were changed by reloading so that no insns refer to it any longer;
1949 but the DECL_RTL of a variable decl may refer to it,
1950 and if so this causes the debugging info to mention the variable. */
1952 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1956 if (reg_equiv_mem[i])
1958 addr = XEXP (reg_equiv_mem[i], 0);
1959 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
1961 if (reg_equiv_address[i])
1962 addr = reg_equiv_address[i];
1965 if (reg_renumber[i] < 0)
1967 rtx reg = regno_reg_rtx[i];
1968 XEXP (reg, 0) = addr;
1969 REG_USERVAR_P (reg) = 0;
1970 MEM_IN_STRUCT_P (reg) = in_struct;
1971 PUT_CODE (reg, MEM);
1973 else if (reg_equiv_mem[i])
1974 XEXP (reg_equiv_mem[i], 0) = addr;
1978 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1979 /* Make a pass over all the insns and remove death notes for things that
1980 are no longer registers or no longer die in the insn (e.g., an input
1981 and output pseudo being tied). */
1983 for (insn = first; insn; insn = NEXT_INSN (insn))
1984 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1988 for (note = REG_NOTES (insn); note; note = next)
1990 next = XEXP (note, 1);
1991 if (REG_NOTE_KIND (note) == REG_DEAD
1992 && (GET_CODE (XEXP (note, 0)) != REG
1993 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
1994 remove_note (insn, note);
1999 /* Indicate that we no longer have known memory locations or constants. */
2000 reg_equiv_constant = 0;
2001 reg_equiv_memory_loc = 0;
2003 free (scratch_list);
2005 free (scratch_block);
2011 /* Nonzero if, after spilling reg REGNO for non-groups,
2012 it will still be possible to find a group if we still need one. */
2015 possible_group_p (regno, max_groups)
2020 int class = (int) NO_REGS;
2022 for (i = 0; i < (int) N_REG_CLASSES; i++)
2023 if (max_groups[i] > 0)
2029 if (class == (int) NO_REGS)
2032 /* Consider each pair of consecutive registers. */
2033 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
2035 /* Ignore pairs that include reg REGNO. */
2036 if (i == regno || i + 1 == regno)
2039 /* Ignore pairs that are outside the class that needs the group.
2040 ??? Here we fail to handle the case where two different classes
2041 independently need groups. But this never happens with our
2042 current machine descriptions. */
2043 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
2044 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
2047 /* A pair of consecutive regs we can still spill does the trick. */
2048 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
2049 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2050 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
2053 /* A pair of one already spilled and one we can spill does it
2054 provided the one already spilled is not otherwise reserved. */
2055 if (spill_reg_order[i] < 0
2056 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2057 && spill_reg_order[i + 1] >= 0
2058 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2059 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2061 if (spill_reg_order[i + 1] < 0
2062 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2063 && spill_reg_order[i] >= 0
2064 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2065 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2072 /* Count any groups that can be formed from the registers recently spilled.
2073 This is done class by class, in order of ascending class number. */
2076 count_possible_groups (group_size, group_mode, max_groups)
2078 enum machine_mode *group_mode;
2082 /* Now find all consecutive groups of spilled registers
2083 and mark each group off against the need for such groups.
2084 But don't count them against ordinary need, yet. */
2086 for (i = 0; i < N_REG_CLASSES; i++)
2087 if (group_size[i] > 1)
2092 CLEAR_HARD_REG_SET (new);
2094 /* Make a mask of all the regs that are spill regs in class I. */
2095 for (j = 0; j < n_spills; j++)
2096 if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
2097 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
2098 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
2100 SET_HARD_REG_BIT (new, spill_regs[j]);
2102 /* Find each consecutive group of them. */
2103 for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
2104 if (TEST_HARD_REG_BIT (new, j)
2105 && j + group_size[i] <= FIRST_PSEUDO_REGISTER
2106 /* Next line in case group-mode for this class
2107 demands an even-odd pair. */
2108 && HARD_REGNO_MODE_OK (j, group_mode[i]))
2111 for (k = 1; k < group_size[i]; k++)
2112 if (! TEST_HARD_REG_BIT (new, j + k))
2114 if (k == group_size[i])
2116 /* We found a group. Mark it off against this class's
2117 need for groups, and against each superclass too. */
2118 register enum reg_class *p;
2120 p = reg_class_superclasses[i];
2121 while (*p != LIM_REG_CLASSES)
2122 max_groups[(int) *p++]--;
2123 /* Don't count these registers again. */
2124 for (k = 0; k < group_size[i]; k++)
2125 SET_HARD_REG_BIT (counted_for_groups, j + k);
2127 /* Skip to the last reg in this group. When j is incremented
2128 above, it will then point to the first reg of the next
2136 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2137 another mode that needs to be reloaded for the same register class CLASS.
2138 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2139 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2141 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2142 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2143 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2144 causes unnecessary failures on machines requiring alignment of register
2145 groups when the two modes are different sizes, because the larger mode has
2146 more strict alignment rules than the smaller mode. */
2149 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2150 enum machine_mode allocate_mode, other_mode;
2151 enum reg_class class;
2154 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2156 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2157 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2158 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2164 /* Handle the failure to find a register to spill.
2165 INSN should be one of the insns which needed this particular spill reg. */
2168 spill_failure (insn)
2171 if (asm_noperands (PATTERN (insn)) >= 0)
2172 error_for_asm (insn, "`asm' needs too many reloads");
2177 /* Add a new register to the tables of available spill-registers
2178 (as well as spilling all pseudos allocated to the register).
2179 I is the index of this register in potential_reload_regs.
2180 CLASS is the regclass whose need is being satisfied.
2181 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2182 so that this register can count off against them.
2183 MAX_NONGROUPS is 0 if this register is part of a group.
2184 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2187 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2195 register enum reg_class *p;
2197 int regno = potential_reload_regs[i];
2199 if (i >= FIRST_PSEUDO_REGISTER)
2200 abort (); /* Caller failed to find any register. */
2202 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2203 fatal ("fixed or forbidden register was spilled.\n\
2204 This may be due to a compiler bug or to impossible asm statements.");
2206 /* Make reg REGNO an additional reload reg. */
2208 potential_reload_regs[i] = -1;
2209 spill_regs[n_spills] = regno;
2210 spill_reg_order[regno] = n_spills;
2212 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2214 /* Clear off the needs we just satisfied. */
2217 p = reg_class_superclasses[class];
2218 while (*p != LIM_REG_CLASSES)
2219 max_needs[(int) *p++]--;
2221 if (max_nongroups && max_nongroups[class] > 0)
2223 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2224 max_nongroups[class]--;
2225 p = reg_class_superclasses[class];
2226 while (*p != LIM_REG_CLASSES)
2227 max_nongroups[(int) *p++]--;
2230 /* Spill every pseudo reg that was allocated to this reg
2231 or to something that overlaps this reg. */
2233 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2235 /* If there are some registers still to eliminate and this register
2236 wasn't ever used before, additional stack space may have to be
2237 allocated to store this register. Thus, we may have changed the offset
2238 between the stack and frame pointers, so mark that something has changed.
2239 (If new pseudos were spilled, thus requiring more space, VAL would have
2240 been set non-zero by the call to spill_hard_reg above since additional
2241 reloads may be needed in that case.
2243 One might think that we need only set VAL to 1 if this is a call-used
2244 register. However, the set of registers that must be saved by the
2245 prologue is not identical to the call-used set. For example, the
2246 register used by the call insn for the return PC is a call-used register,
2247 but must be saved by the prologue. */
2248 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2251 regs_ever_live[spill_regs[n_spills]] = 1;
2257 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2258 data that is dead in INSN. */
2261 delete_dead_insn (insn)
2264 rtx prev = prev_real_insn (insn);
2267 /* If the previous insn sets a register that dies in our insn, delete it
2269 if (prev && GET_CODE (PATTERN (prev)) == SET
2270 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2271 && reg_mentioned_p (prev_dest, PATTERN (insn))
2272 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2273 delete_dead_insn (prev);
2275 PUT_CODE (insn, NOTE);
2276 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2277 NOTE_SOURCE_FILE (insn) = 0;
2280 /* Modify the home of pseudo-reg I.
2281 The new home is present in reg_renumber[I].
2283 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2284 or it may be -1, meaning there is none or it is not relevant.
2285 This is used so that all pseudos spilled from a given hard reg
2286 can share one stack slot. */
2289 alter_reg (i, from_reg)
2293 /* When outputting an inline function, this can happen
2294 for a reg that isn't actually used. */
2295 if (regno_reg_rtx[i] == 0)
2298 /* If the reg got changed to a MEM at rtl-generation time,
2300 if (GET_CODE (regno_reg_rtx[i]) != REG)
2303 /* Modify the reg-rtx to contain the new hard reg
2304 number or else to contain its pseudo reg number. */
2305 REGNO (regno_reg_rtx[i])
2306 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2308 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2309 allocate a stack slot for it. */
2311 if (reg_renumber[i] < 0
2312 && reg_n_refs[i] > 0
2313 && reg_equiv_constant[i] == 0
2314 && reg_equiv_memory_loc[i] == 0)
2317 int inherent_size = PSEUDO_REGNO_BYTES (i);
2318 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2321 /* Each pseudo reg has an inherent size which comes from its own mode,
2322 and a total size which provides room for paradoxical subregs
2323 which refer to the pseudo reg in wider modes.
2325 We can use a slot already allocated if it provides both
2326 enough inherent space and enough total space.
2327 Otherwise, we allocate a new slot, making sure that it has no less
2328 inherent space, and no less total space, then the previous slot. */
2331 /* No known place to spill from => no slot to reuse. */
2332 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2333 #if BYTES_BIG_ENDIAN
2334 /* Cancel the big-endian correction done in assign_stack_local.
2335 Get the address of the beginning of the slot.
2336 This is so we can do a big-endian correction unconditionally
2338 adjust = inherent_size - total_size;
2341 /* Reuse a stack slot if possible. */
2342 else if (spill_stack_slot[from_reg] != 0
2343 && spill_stack_slot_width[from_reg] >= total_size
2344 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2346 x = spill_stack_slot[from_reg];
2347 /* Allocate a bigger slot. */
2350 /* Compute maximum size needed, both for inherent size
2351 and for total size. */
2352 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2353 if (spill_stack_slot[from_reg])
2355 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2357 mode = GET_MODE (spill_stack_slot[from_reg]);
2358 if (spill_stack_slot_width[from_reg] > total_size)
2359 total_size = spill_stack_slot_width[from_reg];
2361 /* Make a slot with that size. */
2362 x = assign_stack_local (mode, total_size, -1);
2363 #if BYTES_BIG_ENDIAN
2364 /* Cancel the big-endian correction done in assign_stack_local.
2365 Get the address of the beginning of the slot.
2366 This is so we can do a big-endian correction unconditionally
2368 adjust = GET_MODE_SIZE (mode) - total_size;
2370 spill_stack_slot[from_reg] = x;
2371 spill_stack_slot_width[from_reg] = total_size;
2374 #if BYTES_BIG_ENDIAN
2375 /* On a big endian machine, the "address" of the slot
2376 is the address of the low part that fits its inherent mode. */
2377 if (inherent_size < total_size)
2378 adjust += (total_size - inherent_size);
2379 #endif /* BYTES_BIG_ENDIAN */
2381 /* If we have any adjustment to make, or if the stack slot is the
2382 wrong mode, make a new stack slot. */
2383 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2385 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2386 plus_constant (XEXP (x, 0), adjust));
2387 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2390 /* Save the stack slot for later. */
2391 reg_equiv_memory_loc[i] = x;
2395 /* Mark the slots in regs_ever_live for the hard regs
2396 used by pseudo-reg number REGNO. */
2399 mark_home_live (regno)
2402 register int i, lim;
2403 i = reg_renumber[regno];
2406 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2408 regs_ever_live[i++] = 1;
2411 /* Mark the registers used in SCRATCH as being live. */
2414 mark_scratch_live (scratch)
2418 int regno = REGNO (scratch);
2419 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch));
2421 for (i = regno; i < lim; i++)
2422 regs_ever_live[i] = 1;
2425 /* This function handles the tracking of elimination offsets around branches.
2427 X is a piece of RTL being scanned.
2429 INSN is the insn that it came from, if any.
2431 INITIAL_P is non-zero if we are to set the offset to be the initial
2432 offset and zero if we are setting the offset of the label to be the
2436 set_label_offsets (x, insn, initial_p)
2441 enum rtx_code code = GET_CODE (x);
2444 struct elim_table *p;
2449 if (LABEL_REF_NONLOCAL_P (x))
2454 /* ... fall through ... */
2457 /* If we know nothing about this label, set the desired offsets. Note
2458 that this sets the offset at a label to be the offset before a label
2459 if we don't know anything about the label. This is not correct for
2460 the label after a BARRIER, but is the best guess we can make. If
2461 we guessed wrong, we will suppress an elimination that might have
2462 been possible had we been able to guess correctly. */
2464 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2466 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2467 offsets_at[CODE_LABEL_NUMBER (x)][i]
2468 = (initial_p ? reg_eliminate[i].initial_offset
2469 : reg_eliminate[i].offset);
2470 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2473 /* Otherwise, if this is the definition of a label and it is
2474 preceded by a BARRIER, set our offsets to the known offset of
2478 && (tem = prev_nonnote_insn (insn)) != 0
2479 && GET_CODE (tem) == BARRIER)
2481 num_not_at_initial_offset = 0;
2482 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2484 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2485 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2486 if (reg_eliminate[i].can_eliminate
2487 && (reg_eliminate[i].offset
2488 != reg_eliminate[i].initial_offset))
2489 num_not_at_initial_offset++;
2494 /* If neither of the above cases is true, compare each offset
2495 with those previously recorded and suppress any eliminations
2496 where the offsets disagree. */
2498 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2499 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2500 != (initial_p ? reg_eliminate[i].initial_offset
2501 : reg_eliminate[i].offset))
2502 reg_eliminate[i].can_eliminate = 0;
2507 set_label_offsets (PATTERN (insn), insn, initial_p);
2509 /* ... fall through ... */
2513 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2514 and hence must have all eliminations at their initial offsets. */
2515 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2516 if (REG_NOTE_KIND (tem) == REG_LABEL)
2517 set_label_offsets (XEXP (tem, 0), insn, 1);
2522 /* Each of the labels in the address vector must be at their initial
2523 offsets. We want the first first for ADDR_VEC and the second
2524 field for ADDR_DIFF_VEC. */
2526 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2527 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2532 /* We only care about setting PC. If the source is not RETURN,
2533 IF_THEN_ELSE, or a label, disable any eliminations not at
2534 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2535 isn't one of those possibilities. For branches to a label,
2536 call ourselves recursively.
2538 Note that this can disable elimination unnecessarily when we have
2539 a non-local goto since it will look like a non-constant jump to
2540 someplace in the current function. This isn't a significant
2541 problem since such jumps will normally be when all elimination
2542 pairs are back to their initial offsets. */
2544 if (SET_DEST (x) != pc_rtx)
2547 switch (GET_CODE (SET_SRC (x)))
2554 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2558 tem = XEXP (SET_SRC (x), 1);
2559 if (GET_CODE (tem) == LABEL_REF)
2560 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2561 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2564 tem = XEXP (SET_SRC (x), 2);
2565 if (GET_CODE (tem) == LABEL_REF)
2566 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2567 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2572 /* If we reach here, all eliminations must be at their initial
2573 offset because we are doing a jump to a variable address. */
2574 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2575 if (p->offset != p->initial_offset)
2576 p->can_eliminate = 0;
2580 /* Used for communication between the next two function to properly share
2581 the vector for an ASM_OPERANDS. */
2583 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2585 /* Scan X and replace any eliminable registers (such as fp) with a
2586 replacement (such as sp), plus an offset.
2588 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2589 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2590 MEM, we are allowed to replace a sum of a register and the constant zero
2591 with the register, which we cannot do outside a MEM. In addition, we need
2592 to record the fact that a register is referenced outside a MEM.
2594 If INSN is nonzero, it is the insn containing X. If we replace a REG
2595 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2596 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2597 that the REG is being modified.
2599 If we see a modification to a register we know about, take the
2600 appropriate action (see case SET, below).
2602 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2603 replacements done assuming all offsets are at their initial values. If
2604 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2605 encounter, return the actual location so that find_reloads will do
2606 the proper thing. */
2609 eliminate_regs (x, mem_mode, insn)
2611 enum machine_mode mem_mode;
2614 enum rtx_code code = GET_CODE (x);
2615 struct elim_table *ep;
2640 /* First handle the case where we encounter a bare register that
2641 is eliminable. Replace it with a PLUS. */
2642 if (regno < FIRST_PSEUDO_REGISTER)
2644 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2646 if (ep->from_rtx == x && ep->can_eliminate)
2649 ep->ref_outside_mem = 1;
2650 return plus_constant (ep->to_rtx, ep->previous_offset);
2654 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2655 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2657 /* In this case, find_reloads would attempt to either use an
2658 incorrect address (if something is not at its initial offset)
2659 or substitute an replaced address into an insn (which loses
2660 if the offset is changed by some later action). So we simply
2661 return the replaced stack slot (assuming it is changed by
2662 elimination) and ignore the fact that this is actually a
2663 reference to the pseudo. Ensure we make a copy of the
2664 address in case it is shared. */
2665 new = eliminate_regs (reg_equiv_memory_loc[regno],
2666 mem_mode, NULL_RTX);
2667 if (new != reg_equiv_memory_loc[regno])
2669 cannot_omit_stores[regno] = 1;
2670 return copy_rtx (new);
2676 /* If this is the sum of an eliminable register and a constant, rework
2678 if (GET_CODE (XEXP (x, 0)) == REG
2679 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2680 && CONSTANT_P (XEXP (x, 1)))
2682 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2684 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2687 ep->ref_outside_mem = 1;
2689 /* The only time we want to replace a PLUS with a REG (this
2690 occurs when the constant operand of the PLUS is the negative
2691 of the offset) is when we are inside a MEM. We won't want
2692 to do so at other times because that would change the
2693 structure of the insn in a way that reload can't handle.
2694 We special-case the commonest situation in
2695 eliminate_regs_in_insn, so just replace a PLUS with a
2696 PLUS here, unless inside a MEM. */
2697 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2698 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2701 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2702 plus_constant (XEXP (x, 1),
2703 ep->previous_offset));
2706 /* If the register is not eliminable, we are done since the other
2707 operand is a constant. */
2711 /* If this is part of an address, we want to bring any constant to the
2712 outermost PLUS. We will do this by doing register replacement in
2713 our operands and seeing if a constant shows up in one of them.
2715 We assume here this is part of an address (or a "load address" insn)
2716 since an eliminable register is not likely to appear in any other
2719 If we have (plus (eliminable) (reg)), we want to produce
2720 (plus (plus (replacement) (reg) (const))). If this was part of a
2721 normal add insn, (plus (replacement) (reg)) will be pushed as a
2722 reload. This is the desired action. */
2725 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2726 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2728 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2730 /* If one side is a PLUS and the other side is a pseudo that
2731 didn't get a hard register but has a reg_equiv_constant,
2732 we must replace the constant here since it may no longer
2733 be in the position of any operand. */
2734 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2735 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2736 && reg_renumber[REGNO (new1)] < 0
2737 && reg_equiv_constant != 0
2738 && reg_equiv_constant[REGNO (new1)] != 0)
2739 new1 = reg_equiv_constant[REGNO (new1)];
2740 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2741 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2742 && reg_renumber[REGNO (new0)] < 0
2743 && reg_equiv_constant[REGNO (new0)] != 0)
2744 new0 = reg_equiv_constant[REGNO (new0)];
2746 new = form_sum (new0, new1);
2748 /* As above, if we are not inside a MEM we do not want to
2749 turn a PLUS into something else. We might try to do so here
2750 for an addition of 0 if we aren't optimizing. */
2751 if (! mem_mode && GET_CODE (new) != PLUS)
2752 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2760 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2763 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2764 if (new != XEXP (x, 0))
2765 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2768 /* ... fall through ... */
2771 /* Now do eliminations in the rest of the chain. If this was
2772 an EXPR_LIST, this might result in allocating more memory than is
2773 strictly needed, but it simplifies the code. */
2776 new = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2777 if (new != XEXP (x, 1))
2778 return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new);
2786 case DIV: case UDIV:
2787 case MOD: case UMOD:
2788 case AND: case IOR: case XOR:
2789 case LSHIFT: case ASHIFT: case ROTATE:
2790 case ASHIFTRT: case LSHIFTRT: case ROTATERT:
2792 case GE: case GT: case GEU: case GTU:
2793 case LE: case LT: case LEU: case LTU:
2795 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2797 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX) : 0;
2799 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2800 return gen_rtx (code, GET_MODE (x), new0, new1);
2808 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2809 if (ep->to_rtx == XEXP (x, 0))
2811 int size = GET_MODE_SIZE (mem_mode);
2813 /* If more bytes than MEM_MODE are pushed, account for them. */
2814 #ifdef PUSH_ROUNDING
2815 if (ep->to_rtx == stack_pointer_rtx)
2816 size = PUSH_ROUNDING (size);
2818 if (code == PRE_DEC || code == POST_DEC)
2824 /* Fall through to generic unary operation case. */
2826 case STRICT_LOW_PART:
2828 case SIGN_EXTEND: case ZERO_EXTEND:
2829 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2830 case FLOAT: case FIX:
2831 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2835 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2836 if (new != XEXP (x, 0))
2837 return gen_rtx (code, GET_MODE (x), new);
2841 /* Similar to above processing, but preserve SUBREG_WORD.
2842 Convert (subreg (mem)) to (mem) if not paradoxical.
2843 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2844 pseudo didn't get a hard reg, we must replace this with the
2845 eliminated version of the memory location because push_reloads
2846 may do the replacement in certain circumstances. */
2847 if (GET_CODE (SUBREG_REG (x)) == REG
2848 && (GET_MODE_SIZE (GET_MODE (x))
2849 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2850 && reg_equiv_memory_loc != 0
2851 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2853 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2854 mem_mode, NULL_RTX);
2856 /* If we didn't change anything, we must retain the pseudo. */
2857 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2860 /* Otherwise, ensure NEW isn't shared in case we have to reload
2862 new = copy_rtx (new);
2865 new = eliminate_regs (SUBREG_REG (x), mem_mode, NULL_RTX);
2867 if (new != XEXP (x, 0))
2869 if (GET_CODE (new) == MEM
2870 && (GET_MODE_SIZE (GET_MODE (x))
2871 <= GET_MODE_SIZE (GET_MODE (new)))
2872 #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
2873 /* On these machines we will be reloading what is
2874 inside the SUBREG if it originally was a pseudo and
2875 the inner and outer modes are both a word or
2876 smaller. So leave the SUBREG then. */
2877 && ! (GET_CODE (SUBREG_REG (x)) == REG
2878 && GET_MODE_SIZE (GET_MODE (x)) <= UNITS_PER_WORD
2879 && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD)
2883 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2884 enum machine_mode mode = GET_MODE (x);
2886 #if BYTES_BIG_ENDIAN
2887 offset += (MIN (UNITS_PER_WORD,
2888 GET_MODE_SIZE (GET_MODE (new)))
2889 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2892 PUT_MODE (new, mode);
2893 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2897 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2903 /* If clobbering a register that is the replacement register for an
2904 elimination we still think can be performed, note that it cannot
2905 be performed. Otherwise, we need not be concerned about it. */
2906 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2907 if (ep->to_rtx == XEXP (x, 0))
2908 ep->can_eliminate = 0;
2910 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2911 if (new != XEXP (x, 0))
2912 return gen_rtx (code, GET_MODE (x), new);
2918 /* Properly handle sharing input and constraint vectors. */
2919 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2921 /* When we come to a new vector not seen before,
2922 scan all its elements; keep the old vector if none
2923 of them changes; otherwise, make a copy. */
2924 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2925 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2926 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2927 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2928 mem_mode, NULL_RTX);
2930 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2931 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2934 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2935 new_asm_operands_vec = old_asm_operands_vec;
2937 new_asm_operands_vec
2938 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2941 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2942 if (new_asm_operands_vec == old_asm_operands_vec)
2945 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2946 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2947 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
2948 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2949 ASM_OPERANDS_SOURCE_FILE (x),
2950 ASM_OPERANDS_SOURCE_LINE (x));
2951 new->volatil = x->volatil;
2956 /* Check for setting a register that we know about. */
2957 if (GET_CODE (SET_DEST (x)) == REG)
2959 /* See if this is setting the replacement register for an
2962 If DEST is the frame pointer, we do nothing because we assume that
2963 all assignments to the frame pointer are for non-local gotos and
2964 are being done at a time when they are valid and do not disturb
2965 anything else. Some machines want to eliminate a fake argument
2966 pointer with either the frame or stack pointer. Assignments to
2967 the frame pointer must not prevent this elimination. */
2969 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2971 if (ep->to_rtx == SET_DEST (x)
2972 && SET_DEST (x) != frame_pointer_rtx)
2974 /* If it is being incremented, adjust the offset. Otherwise,
2975 this elimination can't be done. */
2976 rtx src = SET_SRC (x);
2978 if (GET_CODE (src) == PLUS
2979 && XEXP (src, 0) == SET_DEST (x)
2980 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2981 ep->offset -= INTVAL (XEXP (src, 1));
2983 ep->can_eliminate = 0;
2986 /* Now check to see we are assigning to a register that can be
2987 eliminated. If so, it must be as part of a PARALLEL, since we
2988 will not have been called if this is a single SET. So indicate
2989 that we can no longer eliminate this reg. */
2990 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2992 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
2993 ep->can_eliminate = 0;
2996 /* Now avoid the loop below in this common case. */
2998 rtx new0 = eliminate_regs (SET_DEST (x), 0, NULL_RTX);
2999 rtx new1 = eliminate_regs (SET_SRC (x), 0, NULL_RTX);
3001 /* If SET_DEST changed from a REG to a MEM and INSN is non-zero,
3002 write a CLOBBER insn. */
3003 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
3005 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
3007 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
3008 return gen_rtx (SET, VOIDmode, new0, new1);
3014 /* Our only special processing is to pass the mode of the MEM to our
3015 recursive call and copy the flags. While we are here, handle this
3016 case more efficiently. */
3017 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), NULL_RTX);
3018 if (new != XEXP (x, 0))
3020 new = gen_rtx (MEM, GET_MODE (x), new);
3021 new->volatil = x->volatil;
3022 new->unchanging = x->unchanging;
3023 new->in_struct = x->in_struct;
3030 /* Process each of our operands recursively. If any have changed, make a
3032 fmt = GET_RTX_FORMAT (code);
3033 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3037 new = eliminate_regs (XEXP (x, i), mem_mode, NULL_RTX);
3038 if (new != XEXP (x, i) && ! copied)
3040 rtx new_x = rtx_alloc (code);
3041 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
3042 + (sizeof (new_x->fld[0])
3043 * GET_RTX_LENGTH (code))));
3049 else if (*fmt == 'E')
3052 for (j = 0; j < XVECLEN (x, i); j++)
3054 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
3055 if (new != XVECEXP (x, i, j) && ! copied_vec)
3057 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
3058 &XVECEXP (x, i, 0));
3061 rtx new_x = rtx_alloc (code);
3062 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
3063 + (sizeof (new_x->fld[0])
3064 * GET_RTX_LENGTH (code))));
3068 XVEC (x, i) = new_v;
3071 XVECEXP (x, i, j) = new;
3079 /* Scan INSN and eliminate all eliminable registers in it.
3081 If REPLACE is nonzero, do the replacement destructively. Also
3082 delete the insn as dead it if it is setting an eliminable register.
3084 If REPLACE is zero, do all our allocations in reload_obstack.
3086 If no eliminations were done and this insn doesn't require any elimination
3087 processing (these are not identical conditions: it might be updating sp,
3088 but not referencing fp; this needs to be seen during reload_as_needed so
3089 that the offset between fp and sp can be taken into consideration), zero
3090 is returned. Otherwise, 1 is returned. */
3093 eliminate_regs_in_insn (insn, replace)
3097 rtx old_body = PATTERN (insn);
3100 struct elim_table *ep;
3103 push_obstacks (&reload_obstack, &reload_obstack);
3105 if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
3106 && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
3108 /* Check for setting an eliminable register. */
3109 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3110 if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
3112 /* In this case this insn isn't serving a useful purpose. We
3113 will delete it in reload_as_needed once we know that this
3114 elimination is, in fact, being done.
3116 If REPLACE isn't set, we can't delete this insn, but neededn't
3117 process it since it won't be used unless something changes. */
3119 delete_dead_insn (insn);
3124 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3125 in the insn is the negative of the offset in FROM. Substitute
3126 (set (reg) (reg to)) for the insn and change its code.
3128 We have to do this here, rather than in eliminate_regs, do that we can
3129 change the insn code. */
3131 if (GET_CODE (SET_SRC (old_body)) == PLUS
3132 && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
3133 && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
3134 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3136 if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
3137 && ep->can_eliminate)
3139 /* We must stop at the first elimination that will be used.
3140 If this one would replace the PLUS with a REG, do it
3141 now. Otherwise, quit the loop and let eliminate_regs
3142 do its normal replacement. */
3143 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
3145 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3146 SET_DEST (old_body), ep->to_rtx);
3147 INSN_CODE (insn) = -1;
3156 old_asm_operands_vec = 0;
3158 /* Replace the body of this insn with a substituted form. If we changed
3159 something, return non-zero. If this is the final call for this
3160 insn (REPLACE is non-zero), do the elimination in REG_NOTES as well.
3162 If we are replacing a body that was a (set X (plus Y Z)), try to
3163 re-recognize the insn. We do this in case we had a simple addition
3164 but now can do this as a load-address. This saves an insn in this
3167 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3168 if (new_body != old_body)
3170 /* If we aren't replacing things permanently and we changed something,
3171 make another copy to ensure that all the RTL is new. Otherwise
3172 things can go wrong if find_reload swaps commutative operands
3173 and one is inside RTL that has been copied while the other is not. */
3175 /* Don't copy an asm_operands because (1) there's no need and (2)
3176 copy_rtx can't do it properly when there are multiple outputs. */
3177 if (! replace && asm_noperands (old_body) < 0)
3178 new_body = copy_rtx (new_body);
3180 /* If we had a move insn but now we don't, rerecognize it. */
3181 if ((GET_CODE (old_body) == SET && GET_CODE (SET_SRC (old_body)) == REG
3182 && (GET_CODE (new_body) != SET
3183 || GET_CODE (SET_SRC (new_body)) != REG))
3184 /* If this was an add insn before, rerecognize. */
3186 (GET_CODE (old_body) == SET
3187 && GET_CODE (SET_SRC (old_body)) == PLUS))
3189 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3190 /* If recognition fails, store the new body anyway.
3191 It's normal to have recognition failures here
3192 due to bizarre memory addresses; reloading will fix them. */
3193 PATTERN (insn) = new_body;
3196 PATTERN (insn) = new_body;
3198 if (replace && REG_NOTES (insn))
3199 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, NULL_RTX);
3203 /* Loop through all elimination pairs. See if any have changed and
3204 recalculate the number not at initial offset.
3206 Compute the maximum offset (minimum offset if the stack does not
3207 grow downward) for each elimination pair.
3209 We also detect a cases where register elimination cannot be done,
3210 namely, if a register would be both changed and referenced outside a MEM
3211 in the resulting insn since such an insn is often undefined and, even if
3212 not, we cannot know what meaning will be given to it. Note that it is
3213 valid to have a register used in an address in an insn that changes it
3214 (presumably with a pre- or post-increment or decrement).
3216 If anything changes, return nonzero. */
3218 num_not_at_initial_offset = 0;
3219 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3221 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3222 ep->can_eliminate = 0;
3224 ep->ref_outside_mem = 0;
3226 if (ep->previous_offset != ep->offset)
3229 ep->previous_offset = ep->offset;
3230 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3231 num_not_at_initial_offset++;
3233 #ifdef STACK_GROWS_DOWNWARD
3234 ep->max_offset = MAX (ep->max_offset, ep->offset);
3236 ep->max_offset = MIN (ep->max_offset, ep->offset);
3247 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3248 replacement we currently believe is valid, mark it as not eliminable if X
3249 modifies DEST in any way other than by adding a constant integer to it.
3251 If DEST is the frame pointer, we do nothing because we assume that
3252 all assignments to the frame pointer are nonlocal gotos and are being done
3253 at a time when they are valid and do not disturb anything else.
3254 Some machines want to eliminate a fake argument pointer with either the
3255 frame or stack pointer. Assignments to the frame pointer must not prevent
3258 Called via note_stores from reload before starting its passes to scan
3259 the insns of the function. */
3262 mark_not_eliminable (dest, x)
3268 /* A SUBREG of a hard register here is just changing its mode. We should
3269 not see a SUBREG of an eliminable hard register, but check just in
3271 if (GET_CODE (dest) == SUBREG)
3272 dest = SUBREG_REG (dest);
3274 if (dest == frame_pointer_rtx)
3277 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3278 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3279 && (GET_CODE (x) != SET
3280 || GET_CODE (SET_SRC (x)) != PLUS
3281 || XEXP (SET_SRC (x), 0) != dest
3282 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3284 reg_eliminate[i].can_eliminate_previous
3285 = reg_eliminate[i].can_eliminate = 0;
3290 /* Kick all pseudos out of hard register REGNO.
3291 If GLOBAL is nonzero, try to find someplace else to put them.
3292 If DUMPFILE is nonzero, log actions taken on that file.
3294 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3295 because we found we can't eliminate some register. In the case, no pseudos
3296 are allowed to be in the register, even if they are only in a block that
3297 doesn't require spill registers, unlike the case when we are spilling this
3298 hard reg to produce another spill register.
3300 Return nonzero if any pseudos needed to be kicked out. */
3303 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3309 enum reg_class class = REGNO_REG_CLASS (regno);
3310 int something_changed = 0;
3313 SET_HARD_REG_BIT (forbidden_regs, regno);
3315 /* Spill every pseudo reg that was allocated to this reg
3316 or to something that overlaps this reg. */
3318 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3319 if (reg_renumber[i] >= 0
3320 && reg_renumber[i] <= regno
3322 + HARD_REGNO_NREGS (reg_renumber[i],
3323 PSEUDO_REGNO_MODE (i))
3326 /* If this register belongs solely to a basic block which needed no
3327 spilling of any class that this register is contained in,
3328 leave it be, unless we are spilling this register because
3329 it was a hard register that can't be eliminated. */
3331 if (! cant_eliminate
3332 && basic_block_needs[0]
3333 && reg_basic_block[i] >= 0
3334 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3338 for (p = reg_class_superclasses[(int) class];
3339 *p != LIM_REG_CLASSES; p++)
3340 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3343 if (*p == LIM_REG_CLASSES)
3347 /* Mark it as no longer having a hard register home. */
3348 reg_renumber[i] = -1;
3349 /* We will need to scan everything again. */
3350 something_changed = 1;
3352 retry_global_alloc (i, forbidden_regs);
3354 alter_reg (i, regno);
3357 if (reg_renumber[i] == -1)
3358 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3360 fprintf (dumpfile, " Register %d now in %d.\n\n",
3361 i, reg_renumber[i]);
3364 for (i = 0; i < scratch_list_length; i++)
3366 if (scratch_list[i] && REGNO (scratch_list[i]) == regno)
3368 if (! cant_eliminate && basic_block_needs[0]
3369 && ! basic_block_needs[(int) class][scratch_block[i]])
3373 for (p = reg_class_superclasses[(int) class];
3374 *p != LIM_REG_CLASSES; p++)
3375 if (basic_block_needs[(int) *p][scratch_block[i]] > 0)
3378 if (*p == LIM_REG_CLASSES)
3381 PUT_CODE (scratch_list[i], SCRATCH);
3382 scratch_list[i] = 0;
3383 something_changed = 1;
3388 return something_changed;
3391 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3394 scan_paradoxical_subregs (x)
3399 register enum rtx_code code = GET_CODE (x);
3416 if (GET_CODE (SUBREG_REG (x)) == REG
3417 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3418 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3419 = GET_MODE_SIZE (GET_MODE (x));
3423 fmt = GET_RTX_FORMAT (code);
3424 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3427 scan_paradoxical_subregs (XEXP (x, i));
3428 else if (fmt[i] == 'E')
3431 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3432 scan_paradoxical_subregs (XVECEXP (x, i, j));
3438 hard_reg_use_compare (p1, p2)
3439 struct hard_reg_n_uses *p1, *p2;
3441 int tem = p1->uses - p2->uses;
3442 if (tem != 0) return tem;
3443 /* If regs are equally good, sort by regno,
3444 so that the results of qsort leave nothing to chance. */
3445 return p1->regno - p2->regno;
3448 /* Choose the order to consider regs for use as reload registers
3449 based on how much trouble would be caused by spilling one.
3450 Store them in order of decreasing preference in potential_reload_regs. */
3453 order_regs_for_reload ()
3459 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3461 CLEAR_HARD_REG_SET (bad_spill_regs);
3463 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3464 potential_reload_regs[i] = -1;
3466 /* Count number of uses of each hard reg by pseudo regs allocated to it
3467 and then order them by decreasing use. */
3469 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3471 hard_reg_n_uses[i].uses = 0;
3472 hard_reg_n_uses[i].regno = i;
3475 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3477 int regno = reg_renumber[i];
3480 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3482 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3484 large += reg_n_refs[i];
3487 /* Now fixed registers (which cannot safely be used for reloading)
3488 get a very high use count so they will be considered least desirable.
3489 Registers used explicitly in the rtl code are almost as bad. */
3491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3495 hard_reg_n_uses[i].uses += 2 * large + 2;
3496 SET_HARD_REG_BIT (bad_spill_regs, i);
3498 else if (regs_explicitly_used[i])
3500 hard_reg_n_uses[i].uses += large + 1;
3501 #ifndef SMALL_REGISTER_CLASSES
3502 /* ??? We are doing this here because of the potential that
3503 bad code may be generated if a register explicitly used in
3504 an insn was used as a spill register for that insn. But
3505 not using these are spill registers may lose on some machine.
3506 We'll have to see how this works out. */
3507 SET_HARD_REG_BIT (bad_spill_regs, i);
3511 hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3512 SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM);
3514 #ifdef ELIMINABLE_REGS
3515 /* If registers other than the frame pointer are eliminable, mark them as
3517 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3519 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3520 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3524 /* Prefer registers not so far used, for use in temporary loading.
3525 Among them, if REG_ALLOC_ORDER is defined, use that order.
3526 Otherwise, prefer registers not preserved by calls. */
3528 #ifdef REG_ALLOC_ORDER
3529 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3531 int regno = reg_alloc_order[i];
3533 if (hard_reg_n_uses[regno].uses == 0)
3534 potential_reload_regs[o++] = regno;
3537 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3539 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3540 potential_reload_regs[o++] = i;
3542 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3544 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3545 potential_reload_regs[o++] = i;
3549 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3550 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3552 /* Now add the regs that are already used,
3553 preferring those used less often. The fixed and otherwise forbidden
3554 registers will be at the end of this list. */
3556 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3557 if (hard_reg_n_uses[i].uses != 0)
3558 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3561 /* Reload pseudo-registers into hard regs around each insn as needed.
3562 Additional register load insns are output before the insn that needs it
3563 and perhaps store insns after insns that modify the reloaded pseudo reg.
3565 reg_last_reload_reg and reg_reloaded_contents keep track of
3566 which registers are already available in reload registers.
3567 We update these for the reloads that we perform,
3568 as the insns are scanned. */
3571 reload_as_needed (first, live_known)
3581 bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3582 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3583 bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3584 reg_has_output_reload = (char *) alloca (max_regno);
3585 for (i = 0; i < n_spills; i++)
3587 reg_reloaded_contents[i] = -1;
3588 reg_reloaded_insn[i] = 0;
3591 /* Reset all offsets on eliminable registers to their initial values. */
3592 #ifdef ELIMINABLE_REGS
3593 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3595 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3596 reg_eliminate[i].initial_offset);
3597 reg_eliminate[i].previous_offset
3598 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3601 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3602 reg_eliminate[0].previous_offset
3603 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3606 num_not_at_initial_offset = 0;
3608 for (insn = first; insn;)
3610 register rtx next = NEXT_INSN (insn);
3612 /* Notice when we move to a new basic block. */
3613 if (live_known && this_block + 1 < n_basic_blocks
3614 && insn == basic_block_head[this_block+1])
3617 /* If we pass a label, copy the offsets from the label information
3618 into the current offsets of each elimination. */
3619 if (GET_CODE (insn) == CODE_LABEL)
3621 num_not_at_initial_offset = 0;
3622 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3624 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3625 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3626 if (reg_eliminate[i].can_eliminate
3627 && (reg_eliminate[i].offset
3628 != reg_eliminate[i].initial_offset))
3629 num_not_at_initial_offset++;
3633 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3635 rtx avoid_return_reg = 0;
3637 #ifdef SMALL_REGISTER_CLASSES
3638 /* Set avoid_return_reg if this is an insn
3639 that might use the value of a function call. */
3640 if (GET_CODE (insn) == CALL_INSN)
3642 if (GET_CODE (PATTERN (insn)) == SET)
3643 after_call = SET_DEST (PATTERN (insn));
3644 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3645 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3646 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3650 else if (after_call != 0
3651 && !(GET_CODE (PATTERN (insn)) == SET
3652 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3654 if (reg_mentioned_p (after_call, PATTERN (insn)))
3655 avoid_return_reg = after_call;
3658 #endif /* SMALL_REGISTER_CLASSES */
3660 /* If this is a USE and CLOBBER of a MEM, ensure that any
3661 references to eliminable registers have been removed. */
3663 if ((GET_CODE (PATTERN (insn)) == USE
3664 || GET_CODE (PATTERN (insn)) == CLOBBER)
3665 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3666 XEXP (XEXP (PATTERN (insn), 0), 0)
3667 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3668 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3670 /* If we need to do register elimination processing, do so.
3671 This might delete the insn, in which case we are done. */
3672 if (num_eliminable && GET_MODE (insn) == QImode)
3674 eliminate_regs_in_insn (insn, 1);
3675 if (GET_CODE (insn) == NOTE)
3682 if (GET_MODE (insn) == VOIDmode)
3684 /* First find the pseudo regs that must be reloaded for this insn.
3685 This info is returned in the tables reload_... (see reload.h).
3686 Also modify the body of INSN by substituting RELOAD
3687 rtx's for those pseudo regs. */
3690 bzero (reg_has_output_reload, max_regno);
3691 CLEAR_HARD_REG_SET (reg_is_output_reload);
3693 find_reloads (insn, 1, spill_indirect_levels, live_known,
3699 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3703 /* If this block has not had spilling done for a
3704 particular clas and we have any non-optionals that need a
3705 spill reg in that class, abort. */
3707 for (class = 0; class < N_REG_CLASSES; class++)
3708 if (basic_block_needs[class] != 0
3709 && basic_block_needs[class][this_block] == 0)
3710 for (i = 0; i < n_reloads; i++)
3711 if (class == (int) reload_reg_class[i]
3712 && reload_reg_rtx[i] == 0
3713 && ! reload_optional[i]
3714 && (reload_in[i] != 0 || reload_out[i] != 0
3715 || reload_secondary_p[i] != 0))
3718 /* Now compute which reload regs to reload them into. Perhaps
3719 reusing reload regs from previous insns, or else output
3720 load insns to reload them. Maybe output store insns too.
3721 Record the choices of reload reg in reload_reg_rtx. */
3722 choose_reload_regs (insn, avoid_return_reg);
3724 #ifdef SMALL_REGISTER_CLASSES
3725 /* Merge any reloads that we didn't combine for fear of
3726 increasing the number of spill registers needed but now
3727 discover can be safely merged. */
3728 merge_assigned_reloads (insn);
3731 /* Generate the insns to reload operands into or out of
3732 their reload regs. */
3733 emit_reload_insns (insn);
3735 /* Substitute the chosen reload regs from reload_reg_rtx
3736 into the insn's body (or perhaps into the bodies of other
3737 load and store insn that we just made for reloading
3738 and that we moved the structure into). */
3741 /* If this was an ASM, make sure that all the reload insns
3742 we have generated are valid. If not, give an error
3745 if (asm_noperands (PATTERN (insn)) >= 0)
3746 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3747 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3748 && (recog_memoized (p) < 0
3749 || (insn_extract (p),
3750 ! constrain_operands (INSN_CODE (p), 1))))
3752 error_for_asm (insn,
3753 "`asm' operand requires impossible reload");
3755 NOTE_SOURCE_FILE (p) = 0;
3756 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3759 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3760 is no longer validly lying around to save a future reload.
3761 Note that this does not detect pseudos that were reloaded
3762 for this insn in order to be stored in
3763 (obeying register constraints). That is correct; such reload
3764 registers ARE still valid. */
3765 note_stores (PATTERN (insn), forget_old_reloads_1);
3767 /* There may have been CLOBBER insns placed after INSN. So scan
3768 between INSN and NEXT and use them to forget old reloads. */
3769 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3770 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3771 note_stores (PATTERN (x), forget_old_reloads_1);
3774 /* Likewise for regs altered by auto-increment in this insn.
3775 But note that the reg-notes are not changed by reloading:
3776 they still contain the pseudo-regs, not the spill regs. */
3777 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3778 if (REG_NOTE_KIND (x) == REG_INC)
3780 /* See if this pseudo reg was reloaded in this insn.
3781 If so, its last-reload info is still valid
3782 because it is based on this insn's reload. */
3783 for (i = 0; i < n_reloads; i++)
3784 if (reload_out[i] == XEXP (x, 0))
3788 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
3792 /* A reload reg's contents are unknown after a label. */
3793 if (GET_CODE (insn) == CODE_LABEL)
3794 for (i = 0; i < n_spills; i++)
3796 reg_reloaded_contents[i] = -1;
3797 reg_reloaded_insn[i] = 0;
3800 /* Don't assume a reload reg is still good after a call insn
3801 if it is a call-used reg. */
3802 else if (GET_CODE (insn) == CALL_INSN)
3803 for (i = 0; i < n_spills; i++)
3804 if (call_used_regs[spill_regs[i]])
3806 reg_reloaded_contents[i] = -1;
3807 reg_reloaded_insn[i] = 0;
3810 /* In case registers overlap, allow certain insns to invalidate
3811 particular hard registers. */
3813 #ifdef INSN_CLOBBERS_REGNO_P
3814 for (i = 0 ; i < n_spills ; i++)
3815 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3817 reg_reloaded_contents[i] = -1;
3818 reg_reloaded_insn[i] = 0;
3830 /* Discard all record of any value reloaded from X,
3831 or reloaded in X from someplace else;
3832 unless X is an output reload reg of the current insn.
3834 X may be a hard reg (the reload reg)
3835 or it may be a pseudo reg that was reloaded from. */
3838 forget_old_reloads_1 (x, ignored)
3846 /* note_stores does give us subregs of hard regs. */
3847 while (GET_CODE (x) == SUBREG)
3849 offset += SUBREG_WORD (x);
3853 if (GET_CODE (x) != REG)
3856 regno = REGNO (x) + offset;
3858 if (regno >= FIRST_PSEUDO_REGISTER)
3863 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3864 /* Storing into a spilled-reg invalidates its contents.
3865 This can happen if a block-local pseudo is allocated to that reg
3866 and it wasn't spilled because this block's total need is 0.
3867 Then some insn might have an optional reload and use this reg. */
3868 for (i = 0; i < nr; i++)
3869 if (spill_reg_order[regno + i] >= 0
3870 /* But don't do this if the reg actually serves as an output
3871 reload reg in the current instruction. */
3873 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
3875 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
3876 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
3880 /* Since value of X has changed,
3881 forget any value previously copied from it. */
3884 /* But don't forget a copy if this is the output reload
3885 that establishes the copy's validity. */
3886 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3887 reg_last_reload_reg[regno + nr] = 0;
3890 /* For each reload, the mode of the reload register. */
3891 static enum machine_mode reload_mode[MAX_RELOADS];
3893 /* For each reload, the largest number of registers it will require. */
3894 static int reload_nregs[MAX_RELOADS];
3896 /* Comparison function for qsort to decide which of two reloads
3897 should be handled first. *P1 and *P2 are the reload numbers. */
3900 reload_reg_class_lower (p1, p2)
3903 register int r1 = *p1, r2 = *p2;
3906 /* Consider required reloads before optional ones. */
3907 t = reload_optional[r1] - reload_optional[r2];
3911 /* Count all solitary classes before non-solitary ones. */
3912 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
3913 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
3917 /* Aside from solitaires, consider all multi-reg groups first. */
3918 t = reload_nregs[r2] - reload_nregs[r1];
3922 /* Consider reloads in order of increasing reg-class number. */
3923 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
3927 /* If reloads are equally urgent, sort by reload number,
3928 so that the results of qsort leave nothing to chance. */
3932 /* The following HARD_REG_SETs indicate when each hard register is
3933 used for a reload of various parts of the current insn. */
3935 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3936 static HARD_REG_SET reload_reg_used;
3937 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
3938 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
3939 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
3940 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
3941 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
3942 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
3943 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
3944 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
3945 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3946 static HARD_REG_SET reload_reg_used_in_op_addr;
3947 /* If reg is in use for a RELOAD_FOR_INSN reload. */
3948 static HARD_REG_SET reload_reg_used_in_insn;
3949 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
3950 static HARD_REG_SET reload_reg_used_in_other_addr;
3952 /* If reg is in use as a reload reg for any sort of reload. */
3953 static HARD_REG_SET reload_reg_used_at_all;
3955 /* If reg is use as an inherited reload. We just mark the first register
3957 static HARD_REG_SET reload_reg_used_for_inherit;
3959 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
3960 TYPE. MODE is used to indicate how many consecutive regs are
3964 mark_reload_reg_in_use (regno, opnum, type, mode)
3967 enum reload_type type;
3968 enum machine_mode mode;
3970 int nregs = HARD_REGNO_NREGS (regno, mode);
3973 for (i = regno; i < nregs + regno; i++)
3978 SET_HARD_REG_BIT (reload_reg_used, i);
3981 case RELOAD_FOR_INPUT_ADDRESS:
3982 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
3985 case RELOAD_FOR_OUTPUT_ADDRESS:
3986 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
3989 case RELOAD_FOR_OPERAND_ADDRESS:
3990 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3993 case RELOAD_FOR_OTHER_ADDRESS:
3994 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
3997 case RELOAD_FOR_INPUT:
3998 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4001 case RELOAD_FOR_OUTPUT:
4002 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4005 case RELOAD_FOR_INSN:
4006 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4010 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4014 /* Similarly, but show REGNO is no longer in use for a reload. */
4017 clear_reload_reg_in_use (regno, opnum, type, mode)
4020 enum reload_type type;
4021 enum machine_mode mode;
4023 int nregs = HARD_REGNO_NREGS (regno, mode);
4026 for (i = regno; i < nregs + regno; i++)
4031 CLEAR_HARD_REG_BIT (reload_reg_used, i);
4034 case RELOAD_FOR_INPUT_ADDRESS:
4035 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4038 case RELOAD_FOR_OUTPUT_ADDRESS:
4039 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4042 case RELOAD_FOR_OPERAND_ADDRESS:
4043 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4046 case RELOAD_FOR_OTHER_ADDRESS:
4047 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4050 case RELOAD_FOR_INPUT:
4051 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4054 case RELOAD_FOR_OUTPUT:
4055 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4058 case RELOAD_FOR_INSN:
4059 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
4065 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4066 specified by OPNUM and TYPE. */
4069 reload_reg_free_p (regno, opnum, type)
4072 enum reload_type type;
4076 /* In use for a RELOAD_OTHER means it's not available for anything except
4077 RELOAD_FOR_OTHER_ADDRESS. Recall that RELOAD_FOR_OTHER_ADDRESS is known
4078 to be used only for inputs. */
4080 if (type != RELOAD_FOR_OTHER_ADDRESS
4081 && TEST_HARD_REG_BIT (reload_reg_used, regno))
4087 /* In use for anything means not available for a RELOAD_OTHER. */
4088 return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
4090 /* The other kinds of use can sometimes share a register. */
4091 case RELOAD_FOR_INPUT:
4092 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4093 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4096 /* If it is used for some other input, can't use it. */
4097 for (i = 0; i < reload_n_operands; i++)
4098 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4101 /* If it is used in a later operand's address, can't use it. */
4102 for (i = opnum + 1; i < reload_n_operands; i++)
4103 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4108 case RELOAD_FOR_INPUT_ADDRESS:
4109 /* Can't use a register if it is used for an input address for this
4110 operand or used as an input in an earlier one. */
4111 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
4114 for (i = 0; i < opnum; i++)
4115 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4120 case RELOAD_FOR_OUTPUT_ADDRESS:
4121 /* Can't use a register if it is used for an output address for this
4122 operand or used as an output in this or a later operand. */
4123 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4126 for (i = opnum; i < reload_n_operands; i++)
4127 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4132 case RELOAD_FOR_OPERAND_ADDRESS:
4133 for (i = 0; i < reload_n_operands; i++)
4134 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4137 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4138 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4140 case RELOAD_FOR_OUTPUT:
4141 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4142 outputs, or an operand address for this or an earlier output. */
4143 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4146 for (i = 0; i < reload_n_operands; i++)
4147 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4150 for (i = 0; i <= opnum; i++)
4151 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4156 case RELOAD_FOR_INSN:
4157 for (i = 0; i < reload_n_operands; i++)
4158 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4159 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4162 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4163 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4165 case RELOAD_FOR_OTHER_ADDRESS:
4166 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4171 /* Return 1 if the value in reload reg REGNO, as used by a reload
4172 needed for the part of the insn specified by OPNUM and TYPE,
4173 is not in use for a reload in any prior part of the insn.
4175 We can assume that the reload reg was already tested for availability
4176 at the time it is needed, and we should not check this again,
4177 in case the reg has already been marked in use. */
4180 reload_reg_free_before_p (regno, opnum, type)
4183 enum reload_type type;
4189 case RELOAD_FOR_OTHER_ADDRESS:
4190 /* These always come first. */
4194 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4196 /* If this use is for part of the insn,
4197 check the reg is not in use for any prior part. It is tempting
4198 to try to do this by falling through from objecs that occur
4199 later in the insn to ones that occur earlier, but that will not
4200 correctly take into account the fact that here we MUST ignore
4201 things that would prevent the register from being allocated in
4202 the first place, since we know that it was allocated. */
4204 case RELOAD_FOR_OUTPUT_ADDRESS:
4205 /* Earlier reloads are for earlier outputs or their addresses,
4206 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4207 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4209 for (i = 0; i < opnum; i++)
4210 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4211 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4214 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4217 for (i = 0; i < reload_n_operands; i++)
4218 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4219 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4222 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4223 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4224 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4226 case RELOAD_FOR_OUTPUT:
4227 /* This can't be used in the output address for this operand and
4228 anything that can't be used for it, except that we've already
4229 tested for RELOAD_FOR_INSN objects. */
4231 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4234 for (i = 0; i < opnum; i++)
4235 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4236 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4239 for (i = 0; i < reload_n_operands; i++)
4240 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4241 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4242 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4245 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4247 case RELOAD_FOR_OPERAND_ADDRESS:
4248 case RELOAD_FOR_INSN:
4249 /* These can't conflict with inputs, or each other, so all we have to
4250 test is input addresses and the addresses of OTHER items. */
4252 for (i = 0; i < reload_n_operands; i++)
4253 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4256 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4258 case RELOAD_FOR_INPUT:
4259 /* The only things earlier are the address for this and
4260 earlier inputs, other inputs (which we know we don't conflict
4261 with), and addresses of RELOAD_OTHER objects. */
4263 for (i = 0; i <= opnum; i++)
4264 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4267 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4269 case RELOAD_FOR_INPUT_ADDRESS:
4270 /* Similarly, all we have to check is for use in earlier inputs'
4272 for (i = 0; i < opnum; i++)
4273 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4276 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4281 /* Return 1 if the value in reload reg REGNO, as used by a reload
4282 needed for the part of the insn specified by OPNUM and TYPE,
4283 is still available in REGNO at the end of the insn.
4285 We can assume that the reload reg was already tested for availability
4286 at the time it is needed, and we should not check this again,
4287 in case the reg has already been marked in use. */
4290 reload_reg_reaches_end_p (regno, opnum, type)
4293 enum reload_type type;
4300 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4301 its value must reach the end. */
4304 /* If this use is for part of the insn,
4305 its value reaches if no subsequent part uses the same register.
4306 Just like the above function, don't try to do this with lots
4309 case RELOAD_FOR_OTHER_ADDRESS:
4310 /* Here we check for everything else, since these don't conflict
4311 with anything else and everything comes later. */
4313 for (i = 0; i < reload_n_operands; i++)
4314 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4315 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4316 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4317 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4320 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4321 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4322 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4324 case RELOAD_FOR_INPUT_ADDRESS:
4325 /* Similar, except that we check only for this and subsequent inputs
4326 and the address of only subsequent inputs and we do not need
4327 to check for RELOAD_OTHER objects since they are known not to
4330 for (i = opnum; i < reload_n_operands; i++)
4331 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4334 for (i = opnum + 1; i < reload_n_operands; i++)
4335 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4338 for (i = 0; i < reload_n_operands; i++)
4339 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4340 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4343 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4344 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4346 case RELOAD_FOR_INPUT:
4347 /* Similar to input address, except we start at the next operand for
4348 both input and input address and we do not check for
4349 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4352 for (i = opnum + 1; i < reload_n_operands; i++)
4353 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4354 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4357 /* ... fall through ... */
4359 case RELOAD_FOR_OPERAND_ADDRESS:
4360 /* Check outputs and their addresses. */
4362 for (i = 0; i < reload_n_operands; i++)
4363 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4364 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4369 case RELOAD_FOR_INSN:
4370 /* These conflict with other outputs with with RELOAD_OTHER. So
4371 we need only check for output addresses. */
4375 /* ... fall through ... */
4377 case RELOAD_FOR_OUTPUT:
4378 case RELOAD_FOR_OUTPUT_ADDRESS:
4379 /* We already know these can't conflict with a later output. So the
4380 only thing to check are later output addresses. */
4381 for (i = opnum + 1; i < reload_n_operands; i++)
4382 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4391 /* Vector of reload-numbers showing the order in which the reloads should
4393 short reload_order[MAX_RELOADS];
4395 /* Indexed by reload number, 1 if incoming value
4396 inherited from previous insns. */
4397 char reload_inherited[MAX_RELOADS];
4399 /* For an inherited reload, this is the insn the reload was inherited from,
4400 if we know it. Otherwise, this is 0. */
4401 rtx reload_inheritance_insn[MAX_RELOADS];
4403 /* If non-zero, this is a place to get the value of the reload,
4404 rather than using reload_in. */
4405 rtx reload_override_in[MAX_RELOADS];
4407 /* For each reload, the index in spill_regs of the spill register used,
4408 or -1 if we did not need one of the spill registers for this reload. */
4409 int reload_spill_index[MAX_RELOADS];
4411 /* Index of last register assigned as a spill register. We allocate in
4412 a round-robin fashio. */
4414 static int last_spill_reg = 0;
4416 /* Find a spill register to use as a reload register for reload R.
4417 LAST_RELOAD is non-zero if this is the last reload for the insn being
4420 Set reload_reg_rtx[R] to the register allocated.
4422 If NOERROR is nonzero, we return 1 if successful,
4423 or 0 if we couldn't find a spill reg and we didn't change anything. */
4426 allocate_reload_reg (r, insn, last_reload, noerror)
4438 /* If we put this reload ahead, thinking it is a group,
4439 then insist on finding a group. Otherwise we can grab a
4440 reg that some other reload needs.
4441 (That can happen when we have a 68000 DATA_OR_FP_REG
4442 which is a group of data regs or one fp reg.)
4443 We need not be so restrictive if there are no more reloads
4446 ??? Really it would be nicer to have smarter handling
4447 for that kind of reg class, where a problem like this is normal.
4448 Perhaps those classes should be avoided for reloading
4449 by use of more alternatives. */
4451 int force_group = reload_nregs[r] > 1 && ! last_reload;
4453 /* If we want a single register and haven't yet found one,
4454 take any reg in the right class and not in use.
4455 If we want a consecutive group, here is where we look for it.
4457 We use two passes so we can first look for reload regs to
4458 reuse, which are already in use for other reloads in this insn,
4459 and only then use additional registers.
4460 I think that maximizing reuse is needed to make sure we don't
4461 run out of reload regs. Suppose we have three reloads, and
4462 reloads A and B can share regs. These need two regs.
4463 Suppose A and B are given different regs.
4464 That leaves none for C. */
4465 for (pass = 0; pass < 2; pass++)
4467 /* I is the index in spill_regs.
4468 We advance it round-robin between insns to use all spill regs
4469 equally, so that inherited reloads have a chance
4470 of leapfrogging each other. */
4472 for (count = 0, i = last_spill_reg; count < n_spills; count++)
4474 int class = (int) reload_reg_class[r];
4476 i = (i + 1) % n_spills;
4478 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
4479 reload_when_needed[r])
4480 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
4481 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4482 /* Look first for regs to share, then for unshared. But
4483 don't share regs used for inherited reloads; they are
4484 the ones we want to preserve. */
4486 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4488 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4491 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4492 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4493 (on 68000) got us two FP regs. If NR is 1,
4494 we would reject both of them. */
4496 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
4497 /* If we need only one reg, we have already won. */
4500 /* But reject a single reg if we demand a group. */
4505 /* Otherwise check that as many consecutive regs as we need
4507 Also, don't use for a group registers that are
4508 needed for nongroups. */
4509 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
4512 regno = spill_regs[i] + nr - 1;
4513 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4514 && spill_reg_order[regno] >= 0
4515 && reload_reg_free_p (regno, reload_opnum[r],
4516 reload_when_needed[r])
4517 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
4527 /* If we found something on pass 1, omit pass 2. */
4528 if (count < n_spills)
4532 /* We should have found a spill register by now. */
4533 if (count == n_spills)
4540 /* I is the index in SPILL_REG_RTX of the reload register we are to
4541 allocate. Get an rtx for it and find its register number. */
4543 new = spill_reg_rtx[i];
4545 if (new == 0 || GET_MODE (new) != reload_mode[r])
4546 spill_reg_rtx[i] = new
4547 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
4549 regno = true_regnum (new);
4551 /* Detect when the reload reg can't hold the reload mode.
4552 This used to be one `if', but Sequent compiler can't handle that. */
4553 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4555 enum machine_mode test_mode = VOIDmode;
4557 test_mode = GET_MODE (reload_in[r]);
4558 /* If reload_in[r] has VOIDmode, it means we will load it
4559 in whatever mode the reload reg has: to wit, reload_mode[r].
4560 We have already tested that for validity. */
4561 /* Aside from that, we need to test that the expressions
4562 to reload from or into have modes which are valid for this
4563 reload register. Otherwise the reload insns would be invalid. */
4564 if (! (reload_in[r] != 0 && test_mode != VOIDmode
4565 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4566 if (! (reload_out[r] != 0
4567 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
4569 /* The reg is OK. */
4572 /* Mark as in use for this insn the reload regs we use
4574 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
4575 reload_when_needed[r], reload_mode[r]);
4577 reload_reg_rtx[r] = new;
4578 reload_spill_index[r] = i;
4583 /* The reg is not OK. */
4588 if (asm_noperands (PATTERN (insn)) < 0)
4589 /* It's the compiler's fault. */
4592 /* It's the user's fault; the operand's mode and constraint
4593 don't match. Disable this reload so we don't crash in final. */
4594 error_for_asm (insn,
4595 "`asm' operand constraint incompatible with operand size");
4598 reload_reg_rtx[r] = 0;
4599 reload_optional[r] = 1;
4600 reload_secondary_p[r] = 1;
4605 /* Assign hard reg targets for the pseudo-registers we must reload
4606 into hard regs for this insn.
4607 Also output the instructions to copy them in and out of the hard regs.
4609 For machines with register classes, we are responsible for
4610 finding a reload reg in the proper class. */
4613 choose_reload_regs (insn, avoid_return_reg)
4615 rtx avoid_return_reg;
4618 int max_group_size = 1;
4619 enum reg_class group_class = NO_REGS;
4622 rtx save_reload_reg_rtx[MAX_RELOADS];
4623 char save_reload_inherited[MAX_RELOADS];
4624 rtx save_reload_inheritance_insn[MAX_RELOADS];
4625 rtx save_reload_override_in[MAX_RELOADS];
4626 int save_reload_spill_index[MAX_RELOADS];
4627 HARD_REG_SET save_reload_reg_used;
4628 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4629 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4630 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4631 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4632 HARD_REG_SET save_reload_reg_used_in_op_addr;
4633 HARD_REG_SET save_reload_reg_used_in_insn;
4634 HARD_REG_SET save_reload_reg_used_in_other_addr;
4635 HARD_REG_SET save_reload_reg_used_at_all;
4637 bzero (reload_inherited, MAX_RELOADS);
4638 bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4639 bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
4641 CLEAR_HARD_REG_SET (reload_reg_used);
4642 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4643 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4644 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
4645 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
4647 for (i = 0; i < reload_n_operands; i++)
4649 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
4650 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
4651 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
4652 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
4655 #ifdef SMALL_REGISTER_CLASSES
4656 /* Don't bother with avoiding the return reg
4657 if we have no mandatory reload that could use it. */
4658 if (avoid_return_reg)
4661 int regno = REGNO (avoid_return_reg);
4663 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4666 for (r = regno; r < regno + nregs; r++)
4667 if (spill_reg_order[r] >= 0)
4668 for (j = 0; j < n_reloads; j++)
4669 if (!reload_optional[j] && reload_reg_rtx[j] == 0
4670 && (reload_in[j] != 0 || reload_out[j] != 0
4671 || reload_secondary_p[j])
4673 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4676 avoid_return_reg = 0;
4678 #endif /* SMALL_REGISTER_CLASSES */
4680 #if 0 /* Not needed, now that we can always retry without inheritance. */
4681 /* See if we have more mandatory reloads than spill regs.
4682 If so, then we cannot risk optimizations that could prevent
4683 reloads from sharing one spill register.
4685 Since we will try finding a better register than reload_reg_rtx
4686 unless it is equal to reload_in or reload_out, count such reloads. */
4690 #ifdef SMALL_REGISTER_CLASSES
4691 int tem = (avoid_return_reg != 0);
4693 for (j = 0; j < n_reloads; j++)
4694 if (! reload_optional[j]
4695 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4696 && (reload_reg_rtx[j] == 0
4697 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4698 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4705 #ifdef SMALL_REGISTER_CLASSES
4706 /* Don't use the subroutine call return reg for a reload
4707 if we are supposed to avoid it. */
4708 if (avoid_return_reg)
4710 int regno = REGNO (avoid_return_reg);
4712 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4715 for (r = regno; r < regno + nregs; r++)
4716 if (spill_reg_order[r] >= 0)
4717 SET_HARD_REG_BIT (reload_reg_used, r);
4719 #endif /* SMALL_REGISTER_CLASSES */
4721 /* In order to be certain of getting the registers we need,
4722 we must sort the reloads into order of increasing register class.
4723 Then our grabbing of reload registers will parallel the process
4724 that provided the reload registers.
4726 Also note whether any of the reloads wants a consecutive group of regs.
4727 If so, record the maximum size of the group desired and what
4728 register class contains all the groups needed by this insn. */
4730 for (j = 0; j < n_reloads; j++)
4732 reload_order[j] = j;
4733 reload_spill_index[j] = -1;
4736 = (reload_inmode[j] == VOIDmode
4737 || (GET_MODE_SIZE (reload_outmode[j])
4738 > GET_MODE_SIZE (reload_inmode[j])))
4739 ? reload_outmode[j] : reload_inmode[j];
4741 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4743 if (reload_nregs[j] > 1)
4745 max_group_size = MAX (reload_nregs[j], max_group_size);
4746 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4749 /* If we have already decided to use a certain register,
4750 don't use it in another way. */
4751 if (reload_reg_rtx[j])
4752 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
4753 reload_when_needed[j], reload_mode[j]);
4757 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
4759 bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
4760 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
4761 bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
4762 sizeof reload_inheritance_insn);
4763 bcopy (reload_override_in, save_reload_override_in,
4764 sizeof reload_override_in);
4765 bcopy (reload_spill_index, save_reload_spill_index,
4766 sizeof reload_spill_index);
4767 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
4768 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
4769 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
4770 reload_reg_used_in_op_addr);
4771 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
4772 reload_reg_used_in_insn);
4773 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
4774 reload_reg_used_in_other_addr);
4776 for (i = 0; i < reload_n_operands; i++)
4778 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
4779 reload_reg_used_in_output[i]);
4780 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
4781 reload_reg_used_in_input[i]);
4782 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
4783 reload_reg_used_in_input_addr[i]);
4784 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
4785 reload_reg_used_in_output_addr[i]);
4788 /* If -O, try first with inheritance, then turning it off.
4789 If not -O, don't do inheritance.
4790 Using inheritance when not optimizing leads to paradoxes
4791 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
4792 because one side of the comparison might be inherited. */
4794 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
4796 /* Process the reloads in order of preference just found.
4797 Beyond this point, subregs can be found in reload_reg_rtx.
4799 This used to look for an existing reloaded home for all
4800 of the reloads, and only then perform any new reloads.
4801 But that could lose if the reloads were done out of reg-class order
4802 because a later reload with a looser constraint might have an old
4803 home in a register needed by an earlier reload with a tighter constraint.
4805 To solve this, we make two passes over the reloads, in the order
4806 described above. In the first pass we try to inherit a reload
4807 from a previous insn. If there is a later reload that needs a
4808 class that is a proper subset of the class being processed, we must
4809 also allocate a spill register during the first pass.
4811 Then make a second pass over the reloads to allocate any reloads
4812 that haven't been given registers yet. */
4814 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
4816 for (j = 0; j < n_reloads; j++)
4818 register int r = reload_order[j];
4820 /* Ignore reloads that got marked inoperative. */
4821 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4824 /* If find_reloads chose a to use reload_in or reload_out as a reload
4825 register, we don't need to chose one. Otherwise, try even if it found
4826 one since we might save an insn if we find the value lying around. */
4827 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
4828 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
4829 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
4832 #if 0 /* No longer needed for correct operation.
4833 It might give better code, or might not; worth an experiment? */
4834 /* If this is an optional reload, we can't inherit from earlier insns
4835 until we are sure that any non-optional reloads have been allocated.
4836 The following code takes advantage of the fact that optional reloads
4837 are at the end of reload_order. */
4838 if (reload_optional[r] != 0)
4839 for (i = 0; i < j; i++)
4840 if ((reload_out[reload_order[i]] != 0
4841 || reload_in[reload_order[i]] != 0
4842 || reload_secondary_p[reload_order[i]])
4843 && ! reload_optional[reload_order[i]]
4844 && reload_reg_rtx[reload_order[i]] == 0)
4845 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
4848 /* First see if this pseudo is already available as reloaded
4849 for a previous insn. We cannot try to inherit for reloads
4850 that are smaller than the maximum number of registers needed
4851 for groups unless the register we would allocate cannot be used
4854 We could check here to see if this is a secondary reload for
4855 an object that is already in a register of the desired class.
4856 This would avoid the need for the secondary reload register.
4857 But this is complex because we can't easily determine what
4858 objects might want to be loaded via this reload. So let a register
4859 be allocated here. In `emit_reload_insns' we suppress one of the
4860 loads in the case described above. */
4864 register int regno = -1;
4865 enum machine_mode mode;
4867 if (reload_in[r] == 0)
4869 else if (GET_CODE (reload_in[r]) == REG)
4871 regno = REGNO (reload_in[r]);
4872 mode = GET_MODE (reload_in[r]);
4874 else if (GET_CODE (reload_in_reg[r]) == REG)
4876 regno = REGNO (reload_in_reg[r]);
4877 mode = GET_MODE (reload_in_reg[r]);
4880 /* This won't work, since REGNO can be a pseudo reg number.
4881 Also, it takes much more hair to keep track of all the things
4882 that can invalidate an inherited reload of part of a pseudoreg. */
4883 else if (GET_CODE (reload_in[r]) == SUBREG
4884 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
4885 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
4888 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
4890 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
4892 if (reg_reloaded_contents[i] == regno
4893 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
4894 >= GET_MODE_SIZE (mode))
4895 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4896 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4898 && (reload_nregs[r] == max_group_size
4899 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
4901 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
4902 reload_when_needed[r])
4903 && reload_reg_free_before_p (spill_regs[i],
4905 reload_when_needed[r]))
4907 /* If a group is needed, verify that all the subsequent
4908 registers still have their values intact. */
4910 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4913 for (k = 1; k < nr; k++)
4914 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
4922 /* We found a register that contains the
4923 value we need. If this register is the
4924 same as an `earlyclobber' operand of the
4925 current insn, just mark it as a place to
4926 reload from since we can't use it as the
4927 reload register itself. */
4929 for (i1 = 0; i1 < n_earlyclobbers; i1++)
4930 if (reg_overlap_mentioned_for_reload_p
4931 (reg_last_reload_reg[regno],
4932 reload_earlyclobbers[i1]))
4935 if (i1 != n_earlyclobbers
4936 /* Don't really use the inherited spill reg
4937 if we need it wider than we've got it. */
4938 || (GET_MODE_SIZE (reload_mode[r])
4939 > GET_MODE_SIZE (mode)))
4940 reload_override_in[r] = reg_last_reload_reg[regno];
4943 /* We can use this as a reload reg. */
4944 /* Mark the register as in use for this part of
4946 mark_reload_reg_in_use (spill_regs[i],
4948 reload_when_needed[r],
4950 reload_reg_rtx[r] = reg_last_reload_reg[regno];
4951 reload_inherited[r] = 1;
4952 reload_inheritance_insn[r]
4953 = reg_reloaded_insn[i];
4954 reload_spill_index[r] = i;
4955 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
4963 /* Here's another way to see if the value is already lying around. */
4965 && reload_in[r] != 0
4966 && ! reload_inherited[r]
4967 && reload_out[r] == 0
4968 && (CONSTANT_P (reload_in[r])
4969 || GET_CODE (reload_in[r]) == PLUS
4970 || GET_CODE (reload_in[r]) == REG
4971 || GET_CODE (reload_in[r]) == MEM)
4972 && (reload_nregs[r] == max_group_size
4973 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
4976 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
4977 -1, NULL_PTR, 0, reload_mode[r]);
4982 if (GET_CODE (equiv) == REG)
4983 regno = REGNO (equiv);
4984 else if (GET_CODE (equiv) == SUBREG)
4986 regno = REGNO (SUBREG_REG (equiv));
4987 if (regno < FIRST_PSEUDO_REGISTER)
4988 regno += SUBREG_WORD (equiv);
4994 /* If we found a spill reg, reject it unless it is free
4995 and of the desired class. */
4997 && ((spill_reg_order[regno] >= 0
4998 && ! reload_reg_free_before_p (regno, reload_opnum[r],
4999 reload_when_needed[r]))
5000 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
5004 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
5007 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
5010 /* We found a register that contains the value we need.
5011 If this register is the same as an `earlyclobber' operand
5012 of the current insn, just mark it as a place to reload from
5013 since we can't use it as the reload register itself. */
5016 for (i = 0; i < n_earlyclobbers; i++)
5017 if (reg_overlap_mentioned_for_reload_p (equiv,
5018 reload_earlyclobbers[i]))
5020 reload_override_in[r] = equiv;
5025 /* JRV: If the equiv register we have found is explicitly
5026 clobbered in the current insn, mark but don't use, as above. */
5028 if (equiv != 0 && regno_clobbered_p (regno, insn))
5030 reload_override_in[r] = equiv;
5034 /* If we found an equivalent reg, say no code need be generated
5035 to load it, and use it as our reload reg. */
5036 if (equiv != 0 && regno != FRAME_POINTER_REGNUM)
5038 reload_reg_rtx[r] = equiv;
5039 reload_inherited[r] = 1;
5040 /* If it is a spill reg,
5041 mark the spill reg as in use for this insn. */
5042 i = spill_reg_order[regno];
5045 mark_reload_reg_in_use (regno, reload_opnum[r],
5046 reload_when_needed[r],
5048 SET_HARD_REG_BIT (reload_reg_used_for_inherit, regno);
5053 /* If we found a register to use already, or if this is an optional
5054 reload, we are done. */
5055 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
5058 #if 0 /* No longer needed for correct operation. Might or might not
5059 give better code on the average. Want to experiment? */
5061 /* See if there is a later reload that has a class different from our
5062 class that intersects our class or that requires less register
5063 than our reload. If so, we must allocate a register to this
5064 reload now, since that reload might inherit a previous reload
5065 and take the only available register in our class. Don't do this
5066 for optional reloads since they will force all previous reloads
5067 to be allocated. Also don't do this for reloads that have been
5070 for (i = j + 1; i < n_reloads; i++)
5072 int s = reload_order[i];
5074 if ((reload_in[s] == 0 && reload_out[s] == 0
5075 && ! reload_secondary_p[s])
5076 || reload_optional[s])
5079 if ((reload_reg_class[s] != reload_reg_class[r]
5080 && reg_classes_intersect_p (reload_reg_class[r],
5081 reload_reg_class[s]))
5082 || reload_nregs[s] < reload_nregs[r])
5089 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
5093 /* Now allocate reload registers for anything non-optional that
5094 didn't get one yet. */
5095 for (j = 0; j < n_reloads; j++)
5097 register int r = reload_order[j];
5099 /* Ignore reloads that got marked inoperative. */
5100 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
5103 /* Skip reloads that already have a register allocated or are
5105 if (reload_reg_rtx[r] != 0 || reload_optional[r])
5108 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
5112 /* If that loop got all the way, we have won. */
5117 /* Loop around and try without any inheritance. */
5118 /* First undo everything done by the failed attempt
5119 to allocate with inheritance. */
5120 bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
5121 bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
5122 bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
5123 sizeof reload_inheritance_insn);
5124 bcopy (save_reload_override_in, reload_override_in,
5125 sizeof reload_override_in);
5126 bcopy (save_reload_spill_index, reload_spill_index,
5127 sizeof reload_spill_index);
5128 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
5129 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
5130 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
5131 save_reload_reg_used_in_op_addr);
5132 COPY_HARD_REG_SET (reload_reg_used_in_insn,
5133 save_reload_reg_used_in_insn);
5134 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
5135 save_reload_reg_used_in_other_addr);
5137 for (i = 0; i < reload_n_operands; i++)
5139 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
5140 save_reload_reg_used_in_input[i]);
5141 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
5142 save_reload_reg_used_in_output[i]);
5143 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
5144 save_reload_reg_used_in_input_addr[i]);
5145 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
5146 save_reload_reg_used_in_output_addr[i]);
5150 /* If we thought we could inherit a reload, because it seemed that
5151 nothing else wanted the same reload register earlier in the insn,
5152 verify that assumption, now that all reloads have been assigned. */
5154 for (j = 0; j < n_reloads; j++)
5156 register int r = reload_order[j];
5158 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5159 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5161 reload_when_needed[r]))
5162 reload_inherited[r] = 0;
5164 /* If we found a better place to reload from,
5165 validate it in the same fashion, if it is a reload reg. */
5166 if (reload_override_in[r]
5167 && (GET_CODE (reload_override_in[r]) == REG
5168 || GET_CODE (reload_override_in[r]) == SUBREG))
5170 int regno = true_regnum (reload_override_in[r]);
5171 if (spill_reg_order[regno] >= 0
5172 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5173 reload_when_needed[r]))
5174 reload_override_in[r] = 0;
5178 /* Now that reload_override_in is known valid,
5179 actually override reload_in. */
5180 for (j = 0; j < n_reloads; j++)
5181 if (reload_override_in[j])
5182 reload_in[j] = reload_override_in[j];
5184 /* If this reload won't be done because it has been cancelled or is
5185 optional and not inherited, clear reload_reg_rtx so other
5186 routines (such as subst_reloads) don't get confused. */
5187 for (j = 0; j < n_reloads; j++)
5188 if (reload_reg_rtx[j] != 0
5189 && ((reload_optional[j] && ! reload_inherited[j])
5190 || (reload_in[j] == 0 && reload_out[j] == 0
5191 && ! reload_secondary_p[j])))
5193 int regno = true_regnum (reload_reg_rtx[j]);
5195 if (spill_reg_order[regno] >= 0)
5196 clear_reload_reg_in_use (regno, reload_opnum[j],
5197 reload_when_needed[j], reload_mode[j]);
5198 reload_reg_rtx[j] = 0;
5201 /* Record which pseudos and which spill regs have output reloads. */
5202 for (j = 0; j < n_reloads; j++)
5204 register int r = reload_order[j];
5206 i = reload_spill_index[r];
5208 /* I is nonneg if this reload used one of the spill regs.
5209 If reload_reg_rtx[r] is 0, this is an optional reload
5210 that we opted to ignore. */
5211 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5212 && reload_reg_rtx[r] != 0)
5214 register int nregno = REGNO (reload_out[r]);
5217 if (nregno < FIRST_PSEUDO_REGISTER)
5218 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5221 reg_has_output_reload[nregno + nr] = 1;
5225 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5227 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5230 if (reload_when_needed[r] != RELOAD_OTHER
5231 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5232 && reload_when_needed[r] != RELOAD_FOR_INSN)
5238 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5239 reloads of the same item for fear that we might not have enough reload
5240 registers. However, normally they will get the same reload register
5241 and hence actually need not be loaded twice.
5243 Here we check for the most common case of this phenomenon: when we have
5244 a number of reloads for the same object, each of which were allocated
5245 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5246 reload, and is not modified in the insn itself. If we find such,
5247 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5248 This will not increase the number of spill registers needed and will
5249 prevent redundant code. */
5251 #ifdef SMALL_REGISTER_CLASSES
5254 merge_assigned_reloads (insn)
5259 /* Scan all the reloads looking for ones that only load values and
5260 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5261 assigned and not modified by INSN. */
5263 for (i = 0; i < n_reloads; i++)
5265 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5266 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5267 || reg_set_p (reload_reg_rtx[i], insn))
5270 /* Look at all other reloads. Ensure that the only use of this
5271 reload_reg_rtx is in a reload that just loads the same value
5272 as we do. Note that any secondary reloads must be of the identical
5273 class since the values, modes, and result registers are the
5274 same, so we need not do anything with any secondary reloads. */
5276 for (j = 0; j < n_reloads; j++)
5278 if (i == j || reload_reg_rtx[j] == 0
5279 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5283 /* If the reload regs aren't exactly the same (e.g, different modes)
5284 or if the values are different, we can't merge anything with this
5287 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5288 || reload_out[j] != 0 || reload_in[j] == 0
5289 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5293 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5294 we, in fact, found any matching reloads. */
5298 for (j = 0; j < n_reloads; j++)
5299 if (i != j && reload_reg_rtx[j] != 0
5300 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5302 reload_when_needed[i] = RELOAD_OTHER;
5304 transfer_replacements (i, j);
5307 /* If this is now RELOAD_OTHER, look for any reloads that load
5308 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5309 if they were for inputs, RELOAD_OTHER for outputs. Note that
5310 this test is equivalent to looking for reloads for this operand
5313 if (reload_when_needed[i] == RELOAD_OTHER)
5314 for (j = 0; j < n_reloads; j++)
5315 if (reload_in[j] != 0
5316 && reload_when_needed[i] != RELOAD_OTHER
5317 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5319 reload_when_needed[j]
5320 = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5321 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER;
5325 #endif /* SMALL_RELOAD_CLASSES */
5327 /* Output insns to reload values in and out of the chosen reload regs. */
5330 emit_reload_insns (insn)
5334 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5335 rtx other_input_address_reload_insns = 0;
5336 rtx other_input_reload_insns = 0;
5337 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5338 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5339 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5340 rtx operand_reload_insns = 0;
5341 rtx following_insn = NEXT_INSN (insn);
5342 rtx before_insn = insn;
5344 /* Values to be put in spill_reg_store are put here first. */
5345 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5347 for (j = 0; j < reload_n_operands; j++)
5348 input_reload_insns[j] = input_address_reload_insns[j]
5349 = output_reload_insns[j] = output_address_reload_insns[j] = 0;
5351 /* If this is a CALL_INSN preceded by USE insns, any reload insns
5352 must go in front of the first USE insn, not in front of INSN. */
5354 if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
5355 && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
5356 while (GET_CODE (PREV_INSN (before_insn)) == INSN
5357 && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
5358 before_insn = PREV_INSN (before_insn);
5360 /* If INSN is followed by any CLOBBER insns made by find_reloads,
5361 put our reloads after them since they may otherwise be
5364 while (GET_CODE (following_insn) == INSN
5365 && GET_MODE (following_insn) == DImode
5366 && GET_CODE (PATTERN (following_insn)) == CLOBBER
5367 && NEXT_INSN (following_insn) != 0)
5368 following_insn = NEXT_INSN (following_insn);
5370 /* Now output the instructions to copy the data into and out of the
5371 reload registers. Do these in the order that the reloads were reported,
5372 since reloads of base and index registers precede reloads of operands
5373 and the operands may need the base and index registers reloaded. */
5375 for (j = 0; j < n_reloads; j++)
5378 rtx oldequiv_reg = 0;
5382 if (old != 0 && ! reload_inherited[j]
5383 && ! rtx_equal_p (reload_reg_rtx[j], old)
5384 && reload_reg_rtx[j] != 0)
5386 register rtx reloadreg = reload_reg_rtx[j];
5388 enum machine_mode mode;
5391 /* Determine the mode to reload in.
5392 This is very tricky because we have three to choose from.
5393 There is the mode the insn operand wants (reload_inmode[J]).
5394 There is the mode of the reload register RELOADREG.
5395 There is the intrinsic mode of the operand, which we could find
5396 by stripping some SUBREGs.
5397 It turns out that RELOADREG's mode is irrelevant:
5398 we can change that arbitrarily.
5400 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5401 then the reload reg may not support QImode moves, so use SImode.
5402 If foo is in memory due to spilling a pseudo reg, this is safe,
5403 because the QImode value is in the least significant part of a
5404 slot big enough for a SImode. If foo is some other sort of
5405 memory reference, then it is impossible to reload this case,
5406 so previous passes had better make sure this never happens.
5408 Then consider a one-word union which has SImode and one of its
5409 members is a float, being fetched as (SUBREG:SF union:SI).
5410 We must fetch that as SFmode because we could be loading into
5411 a float-only register. In this case OLD's mode is correct.
5413 Consider an immediate integer: it has VOIDmode. Here we need
5414 to get a mode from something else.
5416 In some cases, there is a fourth mode, the operand's
5417 containing mode. If the insn specifies a containing mode for
5418 this operand, it overrides all others.
5420 I am not sure whether the algorithm here is always right,
5421 but it does the right things in those cases. */
5423 mode = GET_MODE (old);
5424 if (mode == VOIDmode)
5425 mode = reload_inmode[j];
5427 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5428 /* If we need a secondary register for this operation, see if
5429 the value is already in a register in that class. Don't
5430 do this if the secondary register will be used as a scratch
5433 if (reload_secondary_reload[j] >= 0
5434 && reload_secondary_icode[j] == CODE_FOR_nothing
5437 = find_equiv_reg (old, insn,
5438 reload_reg_class[reload_secondary_reload[j]],
5439 -1, NULL_PTR, 0, mode);
5442 /* If reloading from memory, see if there is a register
5443 that already holds the same value. If so, reload from there.
5444 We can pass 0 as the reload_reg_p argument because
5445 any other reload has either already been emitted,
5446 in which case find_equiv_reg will see the reload-insn,
5447 or has yet to be emitted, in which case it doesn't matter
5448 because we will use this equiv reg right away. */
5450 if (oldequiv == 0 && optimize
5451 && (GET_CODE (old) == MEM
5452 || (GET_CODE (old) == REG
5453 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5454 && reg_renumber[REGNO (old)] < 0)))
5455 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5456 -1, NULL_PTR, 0, mode);
5460 int regno = true_regnum (oldequiv);
5462 /* If OLDEQUIV is a spill register, don't use it for this
5463 if any other reload needs it at an earlier stage of this insn
5464 or at this stage. */
5465 if (spill_reg_order[regno] >= 0
5466 && (! reload_reg_free_p (regno, reload_opnum[j],
5467 reload_when_needed[j])
5468 || ! reload_reg_free_before_p (regno, reload_opnum[j],
5469 reload_when_needed[j])))
5472 /* If OLDEQUIV is not a spill register,
5473 don't use it if any other reload wants it. */
5474 if (spill_reg_order[regno] < 0)
5477 for (k = 0; k < n_reloads; k++)
5478 if (reload_reg_rtx[k] != 0 && k != j
5479 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
5487 /* If it is no cheaper to copy from OLDEQUIV into the
5488 reload register than it would be to move from memory,
5489 don't use it. Likewise, if we need a secondary register
5493 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
5494 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5495 reload_reg_class[j])
5496 >= MEMORY_MOVE_COST (mode)))
5497 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5498 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5502 #ifdef SECONDARY_MEMORY_NEEDED
5503 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
5504 REGNO_REG_CLASS (regno),
5513 else if (GET_CODE (oldequiv) == REG)
5514 oldequiv_reg = oldequiv;
5515 else if (GET_CODE (oldequiv) == SUBREG)
5516 oldequiv_reg = SUBREG_REG (oldequiv);
5518 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
5519 then load RELOADREG from OLDEQUIV. */
5521 if (GET_MODE (reloadreg) != mode)
5522 reloadreg = gen_lowpart_common (mode, reloadreg);
5523 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
5524 oldequiv = SUBREG_REG (oldequiv);
5525 if (GET_MODE (oldequiv) != VOIDmode
5526 && mode != GET_MODE (oldequiv))
5527 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
5529 /* Switch to the right place to emit the reload insns. */
5530 switch (reload_when_needed[j])
5533 where = &other_input_reload_insns;
5535 case RELOAD_FOR_INPUT:
5536 where = &input_reload_insns[reload_opnum[j]];
5538 case RELOAD_FOR_INPUT_ADDRESS:
5539 where = &input_address_reload_insns[reload_opnum[j]];
5541 case RELOAD_FOR_OUTPUT_ADDRESS:
5542 where = &output_address_reload_insns[reload_opnum[j]];
5544 case RELOAD_FOR_OPERAND_ADDRESS:
5545 where = &operand_reload_insns;
5547 case RELOAD_FOR_OTHER_ADDRESS:
5548 where = &other_input_address_reload_insns;
5554 push_to_sequence (*where);
5557 /* Auto-increment addresses must be reloaded in a special way. */
5558 if (GET_CODE (oldequiv) == POST_INC
5559 || GET_CODE (oldequiv) == POST_DEC
5560 || GET_CODE (oldequiv) == PRE_INC
5561 || GET_CODE (oldequiv) == PRE_DEC)
5563 /* We are not going to bother supporting the case where a
5564 incremented register can't be copied directly from
5565 OLDEQUIV since this seems highly unlikely. */
5566 if (reload_secondary_reload[j] >= 0)
5568 /* Prevent normal processing of this reload. */
5570 /* Output a special code sequence for this case. */
5571 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
5574 /* If we are reloading a pseudo-register that was set by the previous
5575 insn, see if we can get rid of that pseudo-register entirely
5576 by redirecting the previous insn into our reload register. */
5578 else if (optimize && GET_CODE (old) == REG
5579 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5580 && dead_or_set_p (insn, old)
5581 /* This is unsafe if some other reload
5582 uses the same reg first. */
5583 && reload_reg_free_before_p (REGNO (reloadreg),
5585 reload_when_needed[j]))
5587 rtx temp = PREV_INSN (insn);
5588 while (temp && GET_CODE (temp) == NOTE)
5589 temp = PREV_INSN (temp);
5591 && GET_CODE (temp) == INSN
5592 && GET_CODE (PATTERN (temp)) == SET
5593 && SET_DEST (PATTERN (temp)) == old
5594 /* Make sure we can access insn_operand_constraint. */
5595 && asm_noperands (PATTERN (temp)) < 0
5596 /* This is unsafe if prev insn rejects our reload reg. */
5597 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
5599 /* This is unsafe if operand occurs more than once in current
5600 insn. Perhaps some occurrences aren't reloaded. */
5601 && count_occurrences (PATTERN (insn), old) == 1
5602 /* Don't risk splitting a matching pair of operands. */
5603 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
5605 /* Store into the reload register instead of the pseudo. */
5606 SET_DEST (PATTERN (temp)) = reloadreg;
5607 /* If these are the only uses of the pseudo reg,
5608 pretend for GDB it lives in the reload reg we used. */
5609 if (reg_n_deaths[REGNO (old)] == 1
5610 && reg_n_sets[REGNO (old)] == 1)
5612 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
5613 alter_reg (REGNO (old), -1);
5619 /* We can't do that, so output an insn to load RELOADREG. */
5623 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5624 rtx second_reload_reg = 0;
5625 enum insn_code icode;
5627 /* If we have a secondary reload, pick up the secondary register
5628 and icode, if any. If OLDEQUIV and OLD are different or
5629 if this is an in-out reload, recompute whether or not we
5630 still need a secondary register and what the icode should
5631 be. If we still need a secondary register and the class or
5632 icode is different, go back to reloading from OLD if using
5633 OLDEQUIV means that we got the wrong type of register. We
5634 cannot have different class or icode due to an in-out reload
5635 because we don't make such reloads when both the input and
5636 output need secondary reload registers. */
5638 if (reload_secondary_reload[j] >= 0)
5640 int secondary_reload = reload_secondary_reload[j];
5641 rtx real_oldequiv = oldequiv;
5644 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
5645 and similarly for OLD.
5646 See comments in find_secondary_reload in reload.c. */
5647 if (GET_CODE (oldequiv) == REG
5648 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
5649 && reg_equiv_mem[REGNO (oldequiv)] != 0)
5650 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
5652 if (GET_CODE (old) == REG
5653 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5654 && reg_equiv_mem[REGNO (old)] != 0)
5655 real_old = reg_equiv_mem[REGNO (old)];
5657 second_reload_reg = reload_reg_rtx[secondary_reload];
5658 icode = reload_secondary_icode[j];
5660 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
5661 || (reload_in[j] != 0 && reload_out[j] != 0))
5663 enum reg_class new_class
5664 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5665 mode, real_oldequiv);
5667 if (new_class == NO_REGS)
5668 second_reload_reg = 0;
5671 enum insn_code new_icode;
5672 enum machine_mode new_mode;
5674 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
5675 REGNO (second_reload_reg)))
5676 oldequiv = old, real_oldequiv = real_old;
5679 new_icode = reload_in_optab[(int) mode];
5680 if (new_icode != CODE_FOR_nothing
5681 && ((insn_operand_predicate[(int) new_icode][0]
5682 && ! ((*insn_operand_predicate[(int) new_icode][0])
5684 || (insn_operand_predicate[(int) new_icode][1]
5685 && ! ((*insn_operand_predicate[(int) new_icode][1])
5686 (real_oldequiv, mode)))))
5687 new_icode = CODE_FOR_nothing;
5689 if (new_icode == CODE_FOR_nothing)
5692 new_mode = insn_operand_mode[(int) new_icode][2];
5694 if (GET_MODE (second_reload_reg) != new_mode)
5696 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
5698 oldequiv = old, real_oldequiv = real_old;
5701 = gen_rtx (REG, new_mode,
5702 REGNO (second_reload_reg));
5708 /* If we still need a secondary reload register, check
5709 to see if it is being used as a scratch or intermediate
5710 register and generate code appropriately. If we need
5711 a scratch register, use REAL_OLDEQUIV since the form of
5712 the insn may depend on the actual address if it is
5715 if (second_reload_reg)
5717 if (icode != CODE_FOR_nothing)
5719 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
5720 second_reload_reg));
5725 /* See if we need a scratch register to load the
5726 intermediate register (a tertiary reload). */
5727 enum insn_code tertiary_icode
5728 = reload_secondary_icode[secondary_reload];
5730 if (tertiary_icode != CODE_FOR_nothing)
5732 rtx third_reload_reg
5733 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5735 emit_insn ((GEN_FCN (tertiary_icode)
5736 (second_reload_reg, real_oldequiv,
5737 third_reload_reg)));
5740 gen_input_reload (second_reload_reg, oldequiv,
5742 reload_when_needed[j]);
5744 oldequiv = second_reload_reg;
5751 gen_input_reload (reloadreg, oldequiv, reload_opnum[j],
5752 reload_when_needed[j]);
5754 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
5755 /* We may have to make a REG_DEAD note for the secondary reload
5756 register in the insns we just made. Find the last insn that
5757 mentioned the register. */
5758 if (! special && second_reload_reg
5759 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
5763 for (prev = get_last_insn (); prev;
5764 prev = PREV_INSN (prev))
5765 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
5766 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
5769 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
5778 /* End this sequence. */
5779 *where = get_insns ();
5783 /* Add a note saying the input reload reg
5784 dies in this insn, if anyone cares. */
5785 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5787 && reload_reg_rtx[j] != old
5788 && reload_reg_rtx[j] != 0
5789 && reload_out[j] == 0
5790 && ! reload_inherited[j]
5791 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
5793 register rtx reloadreg = reload_reg_rtx[j];
5796 /* We can't abort here because we need to support this for sched.c.
5797 It's not terrible to miss a REG_DEAD note, but we should try
5798 to figure out how to do this correctly. */
5799 /* The code below is incorrect for address-only reloads. */
5800 if (reload_when_needed[j] != RELOAD_OTHER
5801 && reload_when_needed[j] != RELOAD_FOR_INPUT)
5805 /* Add a death note to this insn, for an input reload. */
5807 if ((reload_when_needed[j] == RELOAD_OTHER
5808 || reload_when_needed[j] == RELOAD_FOR_INPUT)
5809 && ! dead_or_set_p (insn, reloadreg))
5811 = gen_rtx (EXPR_LIST, REG_DEAD,
5812 reloadreg, REG_NOTES (insn));
5815 /* When we inherit a reload, the last marked death of the reload reg
5816 may no longer really be a death. */
5817 if (reload_reg_rtx[j] != 0
5818 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
5819 && reload_inherited[j])
5821 /* Handle inheriting an output reload.
5822 Remove the death note from the output reload insn. */
5823 if (reload_spill_index[j] >= 0
5824 && GET_CODE (reload_in[j]) == REG
5825 && spill_reg_store[reload_spill_index[j]] != 0
5826 && find_regno_note (spill_reg_store[reload_spill_index[j]],
5827 REG_DEAD, REGNO (reload_reg_rtx[j])))
5828 remove_death (REGNO (reload_reg_rtx[j]),
5829 spill_reg_store[reload_spill_index[j]]);
5830 /* Likewise for input reloads that were inherited. */
5831 else if (reload_spill_index[j] >= 0
5832 && GET_CODE (reload_in[j]) == REG
5833 && spill_reg_store[reload_spill_index[j]] == 0
5834 && reload_inheritance_insn[j] != 0
5835 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
5836 REGNO (reload_reg_rtx[j])))
5837 remove_death (REGNO (reload_reg_rtx[j]),
5838 reload_inheritance_insn[j]);
5843 /* We got this register from find_equiv_reg.
5844 Search back for its last death note and get rid of it.
5845 But don't search back too far.
5846 Don't go past a place where this reg is set,
5847 since a death note before that remains valid. */
5848 for (prev = PREV_INSN (insn);
5849 prev && GET_CODE (prev) != CODE_LABEL;
5850 prev = PREV_INSN (prev))
5851 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5852 && dead_or_set_p (prev, reload_reg_rtx[j]))
5854 if (find_regno_note (prev, REG_DEAD,
5855 REGNO (reload_reg_rtx[j])))
5856 remove_death (REGNO (reload_reg_rtx[j]), prev);
5862 /* We might have used find_equiv_reg above to choose an alternate
5863 place from which to reload. If so, and it died, we need to remove
5864 that death and move it to one of the insns we just made. */
5866 if (oldequiv_reg != 0
5867 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
5871 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
5872 prev = PREV_INSN (prev))
5873 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5874 && dead_or_set_p (prev, oldequiv_reg))
5876 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
5878 for (prev1 = this_reload_insn;
5879 prev1; prev1 = PREV_INSN (prev1))
5880 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
5881 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
5884 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
5889 remove_death (REGNO (oldequiv_reg), prev);
5896 /* If we are reloading a register that was recently stored in with an
5897 output-reload, see if we can prove there was
5898 actually no need to store the old value in it. */
5900 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
5901 && reload_in[j] != 0
5902 && GET_CODE (reload_in[j]) == REG
5904 /* There doesn't seem to be any reason to restrict this to pseudos
5905 and doing so loses in the case where we are copying from a
5906 register of the wrong class. */
5907 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
5909 && spill_reg_store[reload_spill_index[j]] != 0
5910 /* This is unsafe if some other reload uses the same reg first. */
5911 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
5912 reload_opnum[j], reload_when_needed[j])
5913 && dead_or_set_p (insn, reload_in[j])
5914 /* This is unsafe if operand occurs more than once in current
5915 insn. Perhaps some occurrences weren't reloaded. */
5916 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5917 delete_output_reload (insn, j,
5918 spill_reg_store[reload_spill_index[j]]);
5920 /* Input-reloading is done. Now do output-reloading,
5921 storing the value from the reload-register after the main insn
5922 if reload_out[j] is nonzero.
5924 ??? At some point we need to support handling output reloads of
5925 JUMP_INSNs or insns that set cc0. */
5926 old = reload_out[j];
5928 && reload_reg_rtx[j] != old
5929 && reload_reg_rtx[j] != 0)
5931 register rtx reloadreg = reload_reg_rtx[j];
5932 register rtx second_reloadreg = 0;
5934 enum machine_mode mode;
5937 /* An output operand that dies right away does need a reload,
5938 but need not be copied from it. Show the new location in the
5940 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
5941 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
5943 XEXP (note, 0) = reload_reg_rtx[j];
5946 else if (GET_CODE (old) == SCRATCH)
5947 /* If we aren't optimizing, there won't be a REG_UNUSED note,
5948 but we don't want to make an output reload. */
5952 /* Strip off of OLD any size-increasing SUBREGs such as
5953 (SUBREG:SI foo:QI 0). */
5955 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
5956 && (GET_MODE_SIZE (GET_MODE (old))
5957 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
5958 old = SUBREG_REG (old);
5961 /* If is a JUMP_INSN, we can't support output reloads yet. */
5962 if (GET_CODE (insn) == JUMP_INSN)
5965 push_to_sequence (output_reload_insns[reload_opnum[j]]);
5967 /* Determine the mode to reload in.
5968 See comments above (for input reloading). */
5970 mode = GET_MODE (old);
5971 if (mode == VOIDmode)
5973 /* VOIDmode should never happen for an output. */
5974 if (asm_noperands (PATTERN (insn)) < 0)
5975 /* It's the compiler's fault. */
5977 error_for_asm (insn, "output operand is constant in `asm'");
5978 /* Prevent crash--use something we know is valid. */
5980 old = gen_rtx (REG, mode, REGNO (reloadreg));
5983 if (GET_MODE (reloadreg) != mode)
5984 reloadreg = gen_lowpart_common (mode, reloadreg);
5986 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5988 /* If we need two reload regs, set RELOADREG to the intermediate
5989 one, since it will be stored into OUT. We might need a secondary
5990 register only for an input reload, so check again here. */
5992 if (reload_secondary_reload[j] >= 0)
5996 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
5997 && reg_equiv_mem[REGNO (old)] != 0)
5998 real_old = reg_equiv_mem[REGNO (old)];
6000 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
6004 second_reloadreg = reloadreg;
6005 reloadreg = reload_reg_rtx[reload_secondary_reload[j]];
6007 /* See if RELOADREG is to be used as a scratch register
6008 or as an intermediate register. */
6009 if (reload_secondary_icode[j] != CODE_FOR_nothing)
6011 emit_insn ((GEN_FCN (reload_secondary_icode[j])
6012 (real_old, second_reloadreg, reloadreg)));
6017 /* See if we need both a scratch and intermediate reload
6019 int secondary_reload = reload_secondary_reload[j];
6020 enum insn_code tertiary_icode
6021 = reload_secondary_icode[secondary_reload];
6024 if (GET_MODE (reloadreg) != mode)
6025 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
6027 if (tertiary_icode != CODE_FOR_nothing)
6030 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
6031 pat = (GEN_FCN (tertiary_icode)
6032 (reloadreg, second_reloadreg, third_reloadreg));
6034 #ifdef SECONDARY_MEMORY_NEEDED
6035 /* If we need a memory location to do the move, do it that way. */
6036 else if (GET_CODE (reloadreg) == REG
6037 && REGNO (reloadreg) < FIRST_PSEUDO_REGISTER
6038 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg)),
6039 REGNO_REG_CLASS (REGNO (second_reloadreg)),
6040 GET_MODE (second_reloadreg)))
6042 /* Get the memory to use and rewrite both registers
6045 = get_secondary_mem (reloadreg,
6046 GET_MODE (second_reloadreg),
6048 reload_when_needed[j]);
6051 if (GET_MODE (loc) != GET_MODE (second_reloadreg))
6052 second_reloadreg = gen_rtx (REG, GET_MODE (loc),
6053 REGNO (second_reloadreg));
6055 if (GET_MODE (loc) != GET_MODE (reloadreg))
6056 tmp_reloadreg = gen_rtx (REG, GET_MODE (loc),
6059 tmp_reloadreg = reloadreg;
6061 emit_move_insn (loc, second_reloadreg);
6062 pat = gen_move_insn (tmp_reloadreg, loc);
6066 pat = gen_move_insn (reloadreg, second_reloadreg);
6074 /* Output the last reload insn. */
6077 #ifdef SECONDARY_MEMORY_NEEDED
6078 /* If we need a memory location to do the move, do it that way. */
6079 if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER
6080 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)),
6081 REGNO_REG_CLASS (REGNO (reloadreg)),
6082 GET_MODE (reloadreg)))
6084 /* Get the memory to use and rewrite both registers to
6086 rtx loc = get_secondary_mem (old, GET_MODE (reloadreg),
6088 reload_when_needed[j]);
6090 if (GET_MODE (loc) != GET_MODE (reloadreg))
6091 reloadreg = gen_rtx (REG, GET_MODE (loc),
6094 if (GET_MODE (loc) != GET_MODE (old))
6095 old = gen_rtx (REG, GET_MODE (loc), REGNO (old));
6097 emit_insn (gen_move_insn (loc, reloadreg));
6098 emit_insn (gen_move_insn (old, loc));
6102 emit_insn (gen_move_insn (old, reloadreg));
6105 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6106 /* If final will look at death notes for this reg,
6107 put one on the last output-reload insn to use it. Similarly
6108 for any secondary register. */
6109 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
6110 for (p = get_last_insn (); p; p = PREV_INSN (p))
6111 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6112 && reg_overlap_mentioned_for_reload_p (reloadreg,
6114 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6115 reloadreg, REG_NOTES (p));
6117 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6119 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
6120 for (p = get_last_insn (); p; p = PREV_INSN (p))
6121 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
6122 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
6124 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
6125 second_reloadreg, REG_NOTES (p));
6128 /* Look at all insns we emitted, just to be safe. */
6129 for (p = get_insns (); p; p = NEXT_INSN (p))
6130 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
6132 /* If this output reload doesn't come from a spill reg,
6133 clear any memory of reloaded copies of the pseudo reg.
6134 If this output reload comes from a spill reg,
6135 reg_has_output_reload will make this do nothing. */
6136 note_stores (PATTERN (p), forget_old_reloads_1);
6138 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
6142 output_reload_insns[reload_opnum[j]] = get_insns ();
6147 if (reload_spill_index[j] >= 0)
6148 new_spill_reg_store[reload_spill_index[j]] = store_insn;
6151 /* Now write all the insns we made for reloads in the order expected by
6152 the allocation functions. Prior to the insn being reloaded, we write
6153 the following reloads:
6155 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6157 RELOAD_OTHER reloads.
6159 For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by
6160 the RELOAD_FOR_INPUT reload for the operand.
6162 RELOAD_FOR_OPERAND_ADDRESS reloads.
6164 After the insn being reloaded, we write the following:
6166 For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by
6167 the RELOAD_FOR_OUTPUT reload for that operand. */
6169 emit_insns_before (other_input_address_reload_insns, before_insn);
6170 emit_insns_before (other_input_reload_insns, before_insn);
6172 for (j = 0; j < reload_n_operands; j++)
6174 emit_insns_before (input_address_reload_insns[j], before_insn);
6175 emit_insns_before (input_reload_insns[j], before_insn);
6178 emit_insns_before (operand_reload_insns, before_insn);
6180 for (j = 0; j < reload_n_operands; j++)
6182 emit_insns_before (output_address_reload_insns[j], following_insn);
6183 emit_insns_before (output_reload_insns[j], following_insn);
6186 /* Move death notes from INSN
6187 to output-operand-address and output reload insns. */
6188 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6191 /* Loop over those insns, last ones first. */
6192 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6193 insn1 = PREV_INSN (insn1))
6194 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6196 rtx source = SET_SRC (PATTERN (insn1));
6197 rtx dest = SET_DEST (PATTERN (insn1));
6199 /* The note we will examine next. */
6200 rtx reg_notes = REG_NOTES (insn);
6201 /* The place that pointed to this note. */
6202 rtx *prev_reg_note = ®_NOTES (insn);
6204 /* If the note is for something used in the source of this
6205 reload insn, or in the output address, move the note. */
6208 rtx next_reg_notes = XEXP (reg_notes, 1);
6209 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6210 && GET_CODE (XEXP (reg_notes, 0)) == REG
6211 && ((GET_CODE (dest) != REG
6212 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6214 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6217 *prev_reg_note = next_reg_notes;
6218 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6219 REG_NOTES (insn1) = reg_notes;
6222 prev_reg_note = &XEXP (reg_notes, 1);
6224 reg_notes = next_reg_notes;
6230 /* For all the spill regs newly reloaded in this instruction,
6231 record what they were reloaded from, so subsequent instructions
6232 can inherit the reloads.
6234 Update spill_reg_store for the reloads of this insn.
6235 Copy the elements that were updated in the loop above. */
6237 for (j = 0; j < n_reloads; j++)
6239 register int r = reload_order[j];
6240 register int i = reload_spill_index[r];
6242 /* I is nonneg if this reload used one of the spill regs.
6243 If reload_reg_rtx[r] is 0, this is an optional reload
6244 that we opted to ignore.
6246 Also ignore reloads that don't reach the end of the insn,
6247 since we will eventually see the one that does. */
6249 if (i >= 0 && reload_reg_rtx[r] != 0
6250 && reload_reg_reaches_end_p (spill_regs[i], reload_opnum[r],
6251 reload_when_needed[r]))
6253 /* First, clear out memory of what used to be in this spill reg.
6254 If consecutive registers are used, clear them all. */
6256 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6259 for (k = 0; k < nr; k++)
6261 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6262 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6265 /* Maybe the spill reg contains a copy of reload_out. */
6266 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6268 register int nregno = REGNO (reload_out[r]);
6269 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6270 : HARD_REGNO_NREGS (nregno,
6271 GET_MODE (reload_reg_rtx[r])));
6273 spill_reg_store[i] = new_spill_reg_store[i];
6274 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6276 /* If NREGNO is a hard register, it may occupy more than
6277 one register. If it does, say what is in the
6278 rest of the registers assuming that both registers
6279 agree on how many words the object takes. If not,
6280 invalidate the subsequent registers. */
6282 if (nregno < FIRST_PSEUDO_REGISTER)
6283 for (k = 1; k < nnr; k++)
6284 reg_last_reload_reg[nregno + k]
6285 = (nr == nnr ? gen_rtx (REG, word_mode,
6286 REGNO (reload_reg_rtx[r]) + k)
6289 /* Now do the inverse operation. */
6290 for (k = 0; k < nr; k++)
6292 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6293 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6295 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6299 /* Maybe the spill reg contains a copy of reload_in. Only do
6300 something if there will not be an output reload for
6301 the register being reloaded. */
6302 else if (reload_out[r] == 0
6303 && reload_in[r] != 0
6304 && ((GET_CODE (reload_in[r]) == REG
6305 && ! reg_has_output_reload[REGNO (reload_in[r])]
6306 || (GET_CODE (reload_in_reg[r]) == REG
6307 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))))
6309 register int nregno;
6312 if (GET_CODE (reload_in[r]) == REG)
6313 nregno = REGNO (reload_in[r]);
6315 nregno = REGNO (reload_in_reg[r]);
6317 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6318 : HARD_REGNO_NREGS (nregno,
6319 GET_MODE (reload_reg_rtx[r])));
6321 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6323 if (nregno < FIRST_PSEUDO_REGISTER)
6324 for (k = 1; k < nnr; k++)
6325 reg_last_reload_reg[nregno + k]
6326 = (nr == nnr ? gen_rtx (REG, word_mode,
6327 REGNO (reload_reg_rtx[r]) + k)
6330 /* Unless we inherited this reload, show we haven't
6331 recently done a store. */
6332 if (! reload_inherited[r])
6333 spill_reg_store[i] = 0;
6335 for (k = 0; k < nr; k++)
6337 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6338 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6340 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6346 /* The following if-statement was #if 0'd in 1.34 (or before...).
6347 It's reenabled in 1.35 because supposedly nothing else
6348 deals with this problem. */
6350 /* If a register gets output-reloaded from a non-spill register,
6351 that invalidates any previous reloaded copy of it.
6352 But forget_old_reloads_1 won't get to see it, because
6353 it thinks only about the original insn. So invalidate it here. */
6354 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6356 register int nregno = REGNO (reload_out[r]);
6357 reg_last_reload_reg[nregno] = 0;
6362 /* Emit code to perform an input reload of IN to RELOADREG. IN is from
6363 operand OPNUM with reload type TYPE.
6365 Returns first insn emitted. */
6368 gen_input_reload (reloadreg, in, opnum, type)
6372 enum reload_type type;
6374 rtx last = get_last_insn ();
6376 /* How to do this reload can get quite tricky. Normally, we are being
6377 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
6378 register that didn't get a hard register. In that case we can just
6379 call emit_move_insn.
6381 We can also be asked to reload a PLUS that adds either two registers, or
6382 a register and a constant or MEM, or a MEM and a constant. This can
6383 occur during frame pointer elimination and while reloading addresses.
6384 This case is handled by trying to emit a single insn
6385 to perform the add. If it is not valid, we use a two insn sequence.
6387 Finally, we could be called to handle an 'o' constraint by putting
6388 an address into a register. In that case, we first try to do this
6389 with a named pattern of "reload_load_address". If no such pattern
6390 exists, we just emit a SET insn and hope for the best (it will normally
6391 be valid on machines that use 'o').
6393 This entire process is made complex because reload will never
6394 process the insns we generate here and so we must ensure that
6395 they will fit their constraints and also by the fact that parts of
6396 IN might be being reloaded separately and replaced with spill registers.
6397 Because of this, we are, in some sense, just guessing the right approach
6398 here. The one listed above seems to work.
6400 ??? At some point, this whole thing needs to be rethought. */
6402 if (GET_CODE (in) == PLUS
6403 && ((GET_CODE (XEXP (in, 0)) == REG
6404 && (GET_CODE (XEXP (in, 1)) == REG
6405 || CONSTANT_P (XEXP (in, 1))
6406 || GET_CODE (XEXP (in, 1)) == MEM))
6407 || (GET_CODE (XEXP (in, 0)) == MEM
6408 && CONSTANT_P (XEXP (in, 1)))))
6410 /* We need to compute the sum of what is either a register and a
6411 constant, a register and memory, a hard register and a pseudo
6412 register, or memory and a constant and put it into the reload
6413 register. The best possible way of doing this is if the machine
6414 has a three-operand ADD insn that accepts the required operands.
6416 The simplest approach is to try to generate such an insn and see if it
6417 is recognized and matches its constraints. If so, it can be used.
6419 It might be better not to actually emit the insn unless it is valid,
6420 but we need to pass the insn as an operand to `recog' and
6421 `insn_extract' and it is simpler to emit and then delete the insn if
6422 not valid than to dummy things up. */
6424 rtx op0, op1, tem, insn;
6427 op0 = find_replacement (&XEXP (in, 0));
6428 op1 = find_replacement (&XEXP (in, 1));
6430 /* Since constraint checking is strict, commutativity won't be
6431 checked, so we need to do that here to avoid spurious failure
6432 if the add instruction is two-address and the second operand
6433 of the add is the same as the reload reg, which is frequently
6434 the case. If the insn would be A = B + A, rearrange it so
6435 it will be A = A + B as constrain_operands expects. */
6437 if (GET_CODE (XEXP (in, 1)) == REG
6438 && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
6439 tem = op0, op0 = op1, op1 = tem;
6441 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
6442 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
6444 insn = emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6445 code = recog_memoized (insn);
6449 insn_extract (insn);
6450 /* We want constrain operands to treat this insn strictly in
6451 its validity determination, i.e., the way it would after reload
6453 if (constrain_operands (code, 1))
6457 delete_insns_since (last);
6459 /* If that failed, we must use a conservative two-insn sequence.
6460 use move to copy constant, MEM, or pseudo register to the reload
6461 register since "move" will be able to handle an arbitrary operand,
6462 unlike add which can't, in general. Then add the registers.
6464 If there is another way to do this for a specific machine, a
6465 DEFINE_PEEPHOLE should be specified that recognizes the sequence
6468 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
6469 || (GET_CODE (op1) == REG
6470 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
6471 tem = op0, op0 = op1, op1 = tem;
6473 emit_insn (gen_move_insn (reloadreg, op0));
6475 /* If OP0 and OP1 are the same, we can use RELOADREG for OP1.
6476 This fixes a problem on the 32K where the stack pointer cannot
6477 be used as an operand of an add insn. */
6479 if (rtx_equal_p (op0, op1))
6482 emit_insn (gen_add2_insn (reloadreg, op1));
6485 #ifdef SECONDARY_MEMORY_NEEDED
6486 /* If we need a memory location to do the move, do it that way. */
6487 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
6488 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
6489 REGNO_REG_CLASS (REGNO (reloadreg)),
6490 GET_MODE (reloadreg)))
6492 /* Get the memory to use and rewrite both registers to its mode. */
6493 rtx loc = get_secondary_mem (in, GET_MODE (reloadreg), opnum, type);
6495 if (GET_MODE (loc) != GET_MODE (reloadreg))
6496 reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg));
6498 if (GET_MODE (loc) != GET_MODE (in))
6499 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
6501 emit_insn (gen_move_insn (loc, in));
6502 emit_insn (gen_move_insn (reloadreg, loc));
6506 /* If IN is a simple operand, use gen_move_insn. */
6507 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
6508 emit_insn (gen_move_insn (reloadreg, in));
6510 #ifdef HAVE_reload_load_address
6511 else if (HAVE_reload_load_address)
6512 emit_insn (gen_reload_load_address (reloadreg, in));
6515 /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
6517 emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6519 /* Return the first insn emitted.
6520 We can not just return get_last_insn, because there may have
6521 been multiple instructions emitted. Also note that gen_move_insn may
6522 emit more than one insn itself, so we can not assume that there is one
6523 insn emitted per emit_insn_before call. */
6525 return last ? NEXT_INSN (last) : get_insns ();
6528 /* Delete a previously made output-reload
6529 whose result we now believe is not needed.
6530 First we double-check.
6532 INSN is the insn now being processed.
6533 OUTPUT_RELOAD_INSN is the insn of the output reload.
6534 J is the reload-number for this insn. */
6537 delete_output_reload (insn, j, output_reload_insn)
6540 rtx output_reload_insn;
6544 /* Get the raw pseudo-register referred to. */
6546 rtx reg = reload_in[j];
6547 while (GET_CODE (reg) == SUBREG)
6548 reg = SUBREG_REG (reg);
6550 /* If the pseudo-reg we are reloading is no longer referenced
6551 anywhere between the store into it and here,
6552 and no jumps or labels intervene, then the value can get
6553 here through the reload reg alone.
6554 Otherwise, give up--return. */
6555 for (i1 = NEXT_INSN (output_reload_insn);
6556 i1 != insn; i1 = NEXT_INSN (i1))
6558 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
6560 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
6561 && reg_mentioned_p (reg, PATTERN (i1)))
6565 if (cannot_omit_stores[REGNO (reg)])
6568 /* If this insn will store in the pseudo again,
6569 the previous store can be removed. */
6570 if (reload_out[j] == reload_in[j])
6571 delete_insn (output_reload_insn);
6573 /* See if the pseudo reg has been completely replaced
6574 with reload regs. If so, delete the store insn
6575 and forget we had a stack slot for the pseudo. */
6576 else if (reg_n_deaths[REGNO (reg)] == 1
6577 && reg_basic_block[REGNO (reg)] >= 0
6578 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
6582 /* We know that it was used only between here
6583 and the beginning of the current basic block.
6584 (We also know that the last use before INSN was
6585 the output reload we are thinking of deleting, but never mind that.)
6586 Search that range; see if any ref remains. */
6587 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6589 rtx set = single_set (i2);
6591 /* Uses which just store in the pseudo don't count,
6592 since if they are the only uses, they are dead. */
6593 if (set != 0 && SET_DEST (set) == reg)
6595 if (GET_CODE (i2) == CODE_LABEL
6596 || GET_CODE (i2) == JUMP_INSN)
6598 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
6599 && reg_mentioned_p (reg, PATTERN (i2)))
6600 /* Some other ref remains;
6601 we can't do anything. */
6605 /* Delete the now-dead stores into this pseudo. */
6606 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6608 rtx set = single_set (i2);
6610 if (set != 0 && SET_DEST (set) == reg)
6612 if (GET_CODE (i2) == CODE_LABEL
6613 || GET_CODE (i2) == JUMP_INSN)
6617 /* For the debugging info,
6618 say the pseudo lives in this reload reg. */
6619 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
6620 alter_reg (REGNO (reg), -1);
6624 /* Output reload-insns to reload VALUE into RELOADREG.
6625 VALUE is an autoincrement or autodecrement RTX whose operand
6626 is a register or memory location;
6627 so reloading involves incrementing that location.
6629 INC_AMOUNT is the number to increment or decrement by (always positive).
6630 This cannot be deduced from VALUE. */
6633 inc_for_reload (reloadreg, value, inc_amount)
6638 /* REG or MEM to be copied and incremented. */
6639 rtx incloc = XEXP (value, 0);
6640 /* Nonzero if increment after copying. */
6641 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
6647 /* No hard register is equivalent to this register after
6648 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
6649 we could inc/dec that register as well (maybe even using it for
6650 the source), but I'm not sure it's worth worrying about. */
6651 if (GET_CODE (incloc) == REG)
6652 reg_last_reload_reg[REGNO (incloc)] = 0;
6654 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
6655 inc_amount = - inc_amount;
6657 inc = GEN_INT (inc_amount);
6659 /* If this is post-increment, first copy the location to the reload reg. */
6661 emit_insn (gen_move_insn (reloadreg, incloc));
6663 /* See if we can directly increment INCLOC. Use a method similar to that
6664 in gen_input_reload. */
6666 last = get_last_insn ();
6667 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
6668 gen_rtx (PLUS, GET_MODE (incloc),
6671 code = recog_memoized (add_insn);
6674 insn_extract (add_insn);
6675 if (constrain_operands (code, 1))
6677 /* If this is a pre-increment and we have incremented the value
6678 where it lives, copy the incremented value to RELOADREG to
6679 be used as an address. */
6682 emit_insn (gen_move_insn (reloadreg, incloc));
6688 delete_insns_since (last);
6690 /* If couldn't do the increment directly, must increment in RELOADREG.
6691 The way we do this depends on whether this is pre- or post-increment.
6692 For pre-increment, copy INCLOC to the reload register, increment it
6693 there, then save back. */
6697 emit_insn (gen_move_insn (reloadreg, incloc));
6698 emit_insn (gen_add2_insn (reloadreg, inc));
6699 emit_insn (gen_move_insn (incloc, reloadreg));
6704 Because this might be a jump insn or a compare, and because RELOADREG
6705 may not be available after the insn in an input reload, we must do
6706 the incrementation before the insn being reloaded for.
6708 We have already copied INCLOC to RELOADREG. Increment the copy in
6709 RELOADREG, save that back, then decrement RELOADREG so it has
6710 the original value. */
6712 emit_insn (gen_add2_insn (reloadreg, inc));
6713 emit_insn (gen_move_insn (incloc, reloadreg));
6714 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
6720 /* Return 1 if we are certain that the constraint-string STRING allows
6721 the hard register REG. Return 0 if we can't be sure of this. */
6724 constraint_accepts_reg_p (string, reg)
6729 int regno = true_regnum (reg);
6732 /* Initialize for first alternative. */
6734 /* Check that each alternative contains `g' or `r'. */
6736 switch (c = *string++)
6739 /* If an alternative lacks `g' or `r', we lose. */
6742 /* If an alternative lacks `g' or `r', we lose. */
6745 /* Initialize for next alternative. */
6750 /* Any general reg wins for this alternative. */
6751 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
6755 /* Any reg in specified class wins for this alternative. */
6757 enum reg_class class = REG_CLASS_FROM_LETTER (c);
6759 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
6765 /* Return the number of places FIND appears within X, but don't count
6766 an occurrence if some SET_DEST is FIND. */
6769 count_occurrences (x, find)
6770 register rtx x, find;
6773 register enum rtx_code code;
6774 register char *format_ptr;
6782 code = GET_CODE (x);
6797 if (SET_DEST (x) == find)
6798 return count_occurrences (SET_SRC (x), find);
6802 format_ptr = GET_RTX_FORMAT (code);
6805 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6807 switch (*format_ptr++)
6810 count += count_occurrences (XEXP (x, i), find);
6814 if (XVEC (x, i) != NULL)
6816 for (j = 0; j < XVECLEN (x, i); j++)
6817 count += count_occurrences (XVECEXP (x, i, j), find);
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