1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 static struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 static char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 static char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static bool verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void scan_paradoxical_subregs (rtx);
394 static void count_pseudo (int);
395 static void order_regs_for_reload (struct insn_chain *);
396 static void reload_as_needed (int);
397 static void forget_old_reloads_1 (rtx, rtx, void *);
398 static int reload_reg_class_lower (const void *, const void *);
399 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
401 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
403 static int reload_reg_free_p (unsigned int, int, enum reload_type);
404 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
406 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
408 static int function_invariant_p (rtx);
409 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
410 static int allocate_reload_reg (struct insn_chain *, int, int);
411 static int conflicts_with_override (rtx);
412 static void failed_reload (rtx, int);
413 static int set_reload_reg (int, int);
414 static void choose_reload_regs_init (struct insn_chain *, rtx *);
415 static void choose_reload_regs (struct insn_chain *);
416 static void merge_assigned_reloads (rtx);
417 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
419 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
421 static void do_input_reload (struct insn_chain *, struct reload *, int);
422 static void do_output_reload (struct insn_chain *, struct reload *, int);
423 static bool inherit_piecemeal_p (int, int);
424 static void emit_reload_insns (struct insn_chain *);
425 static void delete_output_reload (rtx, int, int);
426 static void delete_address_reloads (rtx, rtx);
427 static void delete_address_reloads_1 (rtx, rtx, rtx);
428 static rtx inc_for_reload (rtx, rtx, rtx, int);
430 static void add_auto_inc_notes (rtx, rtx);
432 static void copy_eh_notes (rtx, rtx);
433 static int reloads_conflict (int, int);
434 static rtx gen_reload (rtx, rtx, int, enum reload_type);
436 /* Initialize the reload pass once per compilation. */
443 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
444 Set spill_indirect_levels to the number of levels such addressing is
445 permitted, zero if it is not permitted at all. */
448 = gen_rtx_MEM (Pmode,
451 LAST_VIRTUAL_REGISTER + 1),
453 spill_indirect_levels = 0;
455 while (memory_address_p (QImode, tem))
457 spill_indirect_levels++;
458 tem = gen_rtx_MEM (Pmode, tem);
461 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
463 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
464 indirect_symref_ok = memory_address_p (QImode, tem);
466 /* See if reg+reg is a valid (and offsettable) address. */
468 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
470 tem = gen_rtx_PLUS (Pmode,
471 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
472 gen_rtx_REG (Pmode, i));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem = plus_constant (tem, 4);
477 if (memory_address_p (QImode, tem))
479 double_reg_address_ok = 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack);
486 reload_startobj = obstack_alloc (&reload_obstack, 0);
488 INIT_REG_SET (&spilled_pseudos);
489 INIT_REG_SET (&pseudos_counted);
490 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
493 /* List of insn chains that are currently unused. */
494 static struct insn_chain *unused_insn_chains = 0;
496 /* Allocate an empty insn_chain structure. */
498 new_insn_chain (void)
500 struct insn_chain *c;
502 if (unused_insn_chains == 0)
504 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
505 INIT_REG_SET (&c->live_throughout);
506 INIT_REG_SET (&c->dead_or_set);
510 c = unused_insn_chains;
511 unused_insn_chains = c->next;
513 c->is_caller_save_insn = 0;
514 c->need_operand_change = 0;
520 /* Small utility function to set all regs in hard reg set TO which are
521 allocated to pseudos in regset FROM. */
524 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 reg_set_iterator rsi;
529 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
531 int r = reg_renumber[regno];
536 /* reload_combine uses the information from
537 BASIC_BLOCK->global_live_at_start, which might still
538 contain registers that have not actually been allocated
539 since they have an equivalence. */
540 gcc_assert (reload_completed);
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
589 gcc_assert (!REG_P (regno_reg_rtx[regno])
590 || REGNO (regno_reg_rtx[regno]) != regno);
591 *loc = regno_reg_rtx[regno];
596 else if (code == MEM)
598 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
602 /* Process each of our operands recursively. */
603 fmt = GET_RTX_FORMAT (code);
604 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
606 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
607 else if (*fmt == 'E')
608 for (j = 0; j < XVECLEN (x, i); j++)
609 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
613 /* Global variables used by reload and its subroutines. */
615 /* Set during calculate_needs if an insn needs register elimination. */
616 static int something_needs_elimination;
617 /* Set during calculate_needs if an insn needs an operand changed. */
618 static int something_needs_operands_changed;
620 /* Nonzero means we couldn't get enough spill regs. */
623 /* Main entry point for the reload pass.
625 FIRST is the first insn of the function being compiled.
627 GLOBAL nonzero means we were called from global_alloc
628 and should attempt to reallocate any pseudoregs that we
629 displace from hard regs we will use for reloads.
630 If GLOBAL is zero, we do not have enough information to do that,
631 so any pseudo reg that is spilled must go to the stack.
633 Return value is nonzero if reload failed
634 and we must not do any more for this function. */
637 reload (rtx first, int global)
641 struct elim_table *ep;
644 /* Make sure even insns with volatile mem refs are recognizable. */
649 reload_firstobj = obstack_alloc (&reload_obstack, 0);
651 /* Make sure that the last insn in the chain
652 is not something that needs reloading. */
653 emit_note (NOTE_INSN_DELETED);
655 /* Enable find_equiv_reg to distinguish insns made by reload. */
656 reload_first_uid = get_max_uid ();
658 #ifdef SECONDARY_MEMORY_NEEDED
659 /* Initialize the secondary memory table. */
660 clear_secondary_mem ();
663 /* We don't have a stack slot for any spill reg yet. */
664 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
665 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
667 /* Initialize the save area information for caller-save, in case some
671 /* Compute which hard registers are now in use
672 as homes for pseudo registers.
673 This is done here rather than (eg) in global_alloc
674 because this point is reached even if not optimizing. */
675 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
678 /* A function that receives a nonlocal goto must save all call-saved
680 if (current_function_has_nonlocal_label)
681 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
682 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
683 regs_ever_live[i] = 1;
685 /* Find all the pseudo registers that didn't get hard regs
686 but do have known equivalent constants or memory slots.
687 These include parameters (known equivalent to parameter slots)
688 and cse'd or loop-moved constant memory addresses.
690 Record constant equivalents in reg_equiv_constant
691 so they will be substituted by find_reloads.
692 Record memory equivalents in reg_mem_equiv so they can
693 be substituted eventually by altering the REG-rtx's. */
695 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
696 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
697 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
698 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
699 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
700 reg_old_renumber = xcalloc (max_regno, sizeof (short));
701 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
702 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
703 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
705 CLEAR_HARD_REG_SET (bad_spill_regs_global);
707 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
708 to. Also find all paradoxical subregs and find largest such for
711 num_eliminable_invariants = 0;
712 for (insn = first; insn; insn = NEXT_INSN (insn))
714 rtx set = single_set (insn);
716 /* We may introduce USEs that we want to remove at the end, so
717 we'll mark them with QImode. Make sure there are no
718 previously-marked insns left by say regmove. */
719 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
720 && GET_MODE (insn) != VOIDmode)
721 PUT_MODE (insn, VOIDmode);
723 if (set != 0 && REG_P (SET_DEST (set)))
725 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
727 && (! function_invariant_p (XEXP (note, 0))
729 /* A function invariant is often CONSTANT_P but may
730 include a register. We promise to only pass
731 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
732 || (CONSTANT_P (XEXP (note, 0))
733 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))))
735 rtx x = XEXP (note, 0);
736 i = REGNO (SET_DEST (set));
737 if (i > LAST_VIRTUAL_REGISTER)
739 /* It can happen that a REG_EQUIV note contains a MEM
740 that is not a legitimate memory operand. As later
741 stages of reload assume that all addresses found
742 in the reg_equiv_* arrays were originally legitimate,
744 It can also happen that a REG_EQUIV note contains a
745 readonly memory location. If the destination pseudo
746 is set from some other value (typically a different
747 pseudo), and the destination pseudo does not get a
748 hard reg, then reload will replace the destination
749 pseudo with its equivalent memory location. This
750 is horribly bad as it creates a store to a readonly
751 memory location and a runtime segfault. To avoid
752 this problem we reject readonly memory locations
753 for equivalences. This is overly conservative as
754 we could find all sets of the destination pseudo
755 and remove them as they should be redundant. */
756 if (memory_operand (x, VOIDmode) && ! MEM_READONLY_P (x))
758 /* Always unshare the equivalence, so we can
759 substitute into this insn without touching the
761 reg_equiv_memory_loc[i] = copy_rtx (x);
763 else if (function_invariant_p (x))
765 if (GET_CODE (x) == PLUS)
767 /* This is PLUS of frame pointer and a constant,
768 and might be shared. Unshare it. */
769 reg_equiv_constant[i] = copy_rtx (x);
770 num_eliminable_invariants++;
772 else if (x == frame_pointer_rtx
773 || x == arg_pointer_rtx)
775 reg_equiv_constant[i] = x;
776 num_eliminable_invariants++;
778 else if (LEGITIMATE_CONSTANT_P (x))
779 reg_equiv_constant[i] = x;
782 reg_equiv_memory_loc[i]
783 = force_const_mem (GET_MODE (SET_DEST (set)), x);
784 if (!reg_equiv_memory_loc[i])
791 /* If this register is being made equivalent to a MEM
792 and the MEM is not SET_SRC, the equivalencing insn
793 is one with the MEM as a SET_DEST and it occurs later.
794 So don't mark this insn now. */
796 || rtx_equal_p (SET_SRC (set), x))
798 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
803 /* If this insn is setting a MEM from a register equivalent to it,
804 this is the equivalencing insn. */
805 else if (set && MEM_P (SET_DEST (set))
806 && REG_P (SET_SRC (set))
807 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
808 && rtx_equal_p (SET_DEST (set),
809 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
810 reg_equiv_init[REGNO (SET_SRC (set))]
811 = gen_rtx_INSN_LIST (VOIDmode, insn,
812 reg_equiv_init[REGNO (SET_SRC (set))]);
815 scan_paradoxical_subregs (PATTERN (insn));
820 first_label_num = get_first_label_num ();
821 num_labels = max_label_num () - first_label_num;
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at = xmalloc (num_labels);
828 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
834 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
843 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
847 maybe_fix_stack_asms ();
849 insns_need_reload = 0;
850 something_needs_elimination = 0;
852 /* Initialize to -1, which means take the first spill register. */
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
863 int can_eliminate = 0;
866 can_eliminate |= ep->can_eliminate;
869 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
871 spill_hard_reg (from, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed;
892 HOST_WIDE_INT starting_frame_size;
894 /* Round size of stack frame to stack_alignment_needed. This must be done
895 here because the stack size may be a part of the offset computation
896 for register elimination, and there might have been new stack slots
897 created in the last iteration of this loop. */
898 if (cfun->stack_alignment_needed)
899 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
901 starting_frame_size = get_frame_size ();
903 set_initial_elim_offsets ();
904 set_initial_label_offsets ();
906 /* For each pseudo register that has an equivalent location defined,
907 try to eliminate any eliminable registers (such as the frame pointer)
908 assuming initial offsets for the replacement register, which
911 If the resulting location is directly addressable, substitute
912 the MEM we just got directly for the old REG.
914 If it is not addressable but is a constant or the sum of a hard reg
915 and constant, it is probably not addressable because the constant is
916 out of range, in that case record the address; we will generate
917 hairy code to compute the address in a register each time it is
918 needed. Similarly if it is a hard register, but one that is not
919 valid as an address register.
921 If the location is not addressable, but does not have one of the
922 above forms, assign a stack slot. We have to do this to avoid the
923 potential of producing lots of reloads if, e.g., a location involves
924 a pseudo that didn't get a hard register and has an equivalent memory
925 location that also involves a pseudo that didn't get a hard register.
927 Perhaps at some point we will improve reload_when_needed handling
928 so this problem goes away. But that's very hairy. */
930 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
931 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
933 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
935 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
937 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
938 else if (CONSTANT_P (XEXP (x, 0))
939 || (REG_P (XEXP (x, 0))
940 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
941 || (GET_CODE (XEXP (x, 0)) == PLUS
942 && REG_P (XEXP (XEXP (x, 0), 0))
943 && (REGNO (XEXP (XEXP (x, 0), 0))
944 < FIRST_PSEUDO_REGISTER)
945 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
946 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
949 /* Make a new stack slot. Then indicate that something
950 changed so we go back and recompute offsets for
951 eliminable registers because the allocation of memory
952 below might change some offset. reg_equiv_{mem,address}
953 will be set up for this pseudo on the next pass around
955 reg_equiv_memory_loc[i] = 0;
956 reg_equiv_init[i] = 0;
961 if (caller_save_needed)
964 /* If we allocated another stack slot, redo elimination bookkeeping. */
965 if (starting_frame_size != get_frame_size ())
968 if (caller_save_needed)
970 save_call_clobbered_regs ();
971 /* That might have allocated new insn_chain structures. */
972 reload_firstobj = obstack_alloc (&reload_obstack, 0);
975 calculate_needs_all_insns (global);
977 CLEAR_REG_SET (&spilled_pseudos);
980 something_changed = 0;
982 /* If we allocated any new memory locations, make another pass
983 since it might have changed elimination offsets. */
984 if (starting_frame_size != get_frame_size ())
985 something_changed = 1;
987 /* Even if the frame size remained the same, we might still have
988 changed elimination offsets, e.g. if find_reloads called
989 force_const_mem requiring the back end to allocate a constant
990 pool base register that needs to be saved on the stack. */
991 else if (!verify_initial_elim_offsets ())
992 something_changed = 1;
995 HARD_REG_SET to_spill;
996 CLEAR_HARD_REG_SET (to_spill);
997 update_eliminables (&to_spill);
998 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
999 if (TEST_HARD_REG_BIT (to_spill, i))
1001 spill_hard_reg (i, 1);
1004 /* Regardless of the state of spills, if we previously had
1005 a register that we thought we could eliminate, but now can
1006 not eliminate, we must run another pass.
1008 Consider pseudos which have an entry in reg_equiv_* which
1009 reference an eliminable register. We must make another pass
1010 to update reg_equiv_* so that we do not substitute in the
1011 old value from when we thought the elimination could be
1013 something_changed = 1;
1017 select_reload_regs ();
1021 if (insns_need_reload != 0 || did_spill)
1022 something_changed |= finish_spills (global);
1024 if (! something_changed)
1027 if (caller_save_needed)
1028 delete_caller_save_insns ();
1030 obstack_free (&reload_obstack, reload_firstobj);
1033 /* If global-alloc was run, notify it of any register eliminations we have
1036 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1037 if (ep->can_eliminate)
1038 mark_elimination (ep->from, ep->to);
1040 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1041 If that insn didn't set the register (i.e., it copied the register to
1042 memory), just delete that insn instead of the equivalencing insn plus
1043 anything now dead. If we call delete_dead_insn on that insn, we may
1044 delete the insn that actually sets the register if the register dies
1045 there and that is incorrect. */
1047 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1049 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1052 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1054 rtx equiv_insn = XEXP (list, 0);
1056 /* If we already deleted the insn or if it may trap, we can't
1057 delete it. The latter case shouldn't happen, but can
1058 if an insn has a variable address, gets a REG_EH_REGION
1059 note added to it, and then gets converted into an load
1060 from a constant address. */
1061 if (NOTE_P (equiv_insn)
1062 || can_throw_internal (equiv_insn))
1064 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1065 delete_dead_insn (equiv_insn);
1067 SET_INSN_DELETED (equiv_insn);
1072 /* Use the reload registers where necessary
1073 by generating move instructions to move the must-be-register
1074 values into or out of the reload registers. */
1076 if (insns_need_reload != 0 || something_needs_elimination
1077 || something_needs_operands_changed)
1079 HOST_WIDE_INT old_frame_size = get_frame_size ();
1081 reload_as_needed (global);
1083 gcc_assert (old_frame_size == get_frame_size ());
1085 gcc_assert (verify_initial_elim_offsets ());
1088 /* If we were able to eliminate the frame pointer, show that it is no
1089 longer live at the start of any basic block. If it ls live by
1090 virtue of being in a pseudo, that pseudo will be marked live
1091 and hence the frame pointer will be known to be live via that
1094 if (! frame_pointer_needed)
1096 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1097 HARD_FRAME_POINTER_REGNUM);
1099 /* Come here (with failure set nonzero) if we can't get enough spill
1103 CLEAR_REG_SET (&spilled_pseudos);
1104 reload_in_progress = 0;
1106 /* Now eliminate all pseudo regs by modifying them into
1107 their equivalent memory references.
1108 The REG-rtx's for the pseudos are modified in place,
1109 so all insns that used to refer to them now refer to memory.
1111 For a reg that has a reg_equiv_address, all those insns
1112 were changed by reloading so that no insns refer to it any longer;
1113 but the DECL_RTL of a variable decl may refer to it,
1114 and if so this causes the debugging info to mention the variable. */
1116 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1120 if (reg_equiv_mem[i])
1121 addr = XEXP (reg_equiv_mem[i], 0);
1123 if (reg_equiv_address[i])
1124 addr = reg_equiv_address[i];
1128 if (reg_renumber[i] < 0)
1130 rtx reg = regno_reg_rtx[i];
1132 REG_USERVAR_P (reg) = 0;
1133 PUT_CODE (reg, MEM);
1134 XEXP (reg, 0) = addr;
1135 if (reg_equiv_memory_loc[i])
1136 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1139 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1140 MEM_ATTRS (reg) = 0;
1143 else if (reg_equiv_mem[i])
1144 XEXP (reg_equiv_mem[i], 0) = addr;
1148 /* We must set reload_completed now since the cleanup_subreg_operands call
1149 below will re-recognize each insn and reload may have generated insns
1150 which are only valid during and after reload. */
1151 reload_completed = 1;
1153 /* Make a pass over all the insns and delete all USEs which we inserted
1154 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1155 notes. Delete all CLOBBER insns, except those that refer to the return
1156 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1157 from misarranging variable-array code, and simplify (subreg (reg))
1158 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1159 are no longer useful or accurate. Strip and regenerate REG_INC notes
1160 that may have been moved around. */
1162 for (insn = first; insn; insn = NEXT_INSN (insn))
1168 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1169 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1171 if ((GET_CODE (PATTERN (insn)) == USE
1172 /* We mark with QImode USEs introduced by reload itself. */
1173 && (GET_MODE (insn) == QImode
1174 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1175 || (GET_CODE (PATTERN (insn)) == CLOBBER
1176 && (!MEM_P (XEXP (PATTERN (insn), 0))
1177 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1178 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1179 && XEXP (XEXP (PATTERN (insn), 0), 0)
1180 != stack_pointer_rtx))
1181 && (!REG_P (XEXP (PATTERN (insn), 0))
1182 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1188 /* Some CLOBBERs may survive until here and still reference unassigned
1189 pseudos with const equivalent, which may in turn cause ICE in later
1190 passes if the reference remains in place. */
1191 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1192 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1193 VOIDmode, PATTERN (insn));
1195 /* Discard obvious no-ops, even without -O. This optimization
1196 is fast and doesn't interfere with debugging. */
1197 if (NONJUMP_INSN_P (insn)
1198 && GET_CODE (PATTERN (insn)) == SET
1199 && REG_P (SET_SRC (PATTERN (insn)))
1200 && REG_P (SET_DEST (PATTERN (insn)))
1201 && (REGNO (SET_SRC (PATTERN (insn)))
1202 == REGNO (SET_DEST (PATTERN (insn)))))
1208 pnote = ®_NOTES (insn);
1211 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1212 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1213 || REG_NOTE_KIND (*pnote) == REG_INC
1214 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1215 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1216 *pnote = XEXP (*pnote, 1);
1218 pnote = &XEXP (*pnote, 1);
1222 add_auto_inc_notes (insn, PATTERN (insn));
1225 /* And simplify (subreg (reg)) if it appears as an operand. */
1226 cleanup_subreg_operands (insn);
1229 /* If we are doing stack checking, give a warning if this function's
1230 frame size is larger than we expect. */
1231 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1233 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1234 static int verbose_warned = 0;
1236 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1237 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1238 size += UNITS_PER_WORD;
1240 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1242 warning (0, "frame size too large for reliable stack checking");
1243 if (! verbose_warned)
1245 warning (0, "try reducing the number of local variables");
1251 /* Indicate that we no longer have known memory locations or constants. */
1252 if (reg_equiv_constant)
1253 free (reg_equiv_constant);
1254 reg_equiv_constant = 0;
1255 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1256 reg_equiv_memory_loc = 0;
1258 if (offsets_known_at)
1259 free (offsets_known_at);
1263 free (reg_equiv_mem);
1264 free (reg_equiv_init);
1265 free (reg_equiv_address);
1266 free (reg_max_ref_width);
1267 free (reg_old_renumber);
1268 free (pseudo_previous_regs);
1269 free (pseudo_forbidden_regs);
1271 CLEAR_HARD_REG_SET (used_spill_regs);
1272 for (i = 0; i < n_spills; i++)
1273 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1275 /* Free all the insn_chain structures at once. */
1276 obstack_free (&reload_obstack, reload_startobj);
1277 unused_insn_chains = 0;
1278 fixup_abnormal_edges ();
1280 /* Replacing pseudos with their memory equivalents might have
1281 created shared rtx. Subsequent passes would get confused
1282 by this, so unshare everything here. */
1283 unshare_all_rtl_again (first);
1285 #ifdef STACK_BOUNDARY
1286 /* init_emit has set the alignment of the hard frame pointer
1287 to STACK_BOUNDARY. It is very likely no longer valid if
1288 the hard frame pointer was used for register allocation. */
1289 if (!frame_pointer_needed)
1290 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1296 /* Yet another special case. Unfortunately, reg-stack forces people to
1297 write incorrect clobbers in asm statements. These clobbers must not
1298 cause the register to appear in bad_spill_regs, otherwise we'll call
1299 fatal_insn later. We clear the corresponding regnos in the live
1300 register sets to avoid this.
1301 The whole thing is rather sick, I'm afraid. */
1304 maybe_fix_stack_asms (void)
1307 const char *constraints[MAX_RECOG_OPERANDS];
1308 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1309 struct insn_chain *chain;
1311 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1314 HARD_REG_SET clobbered, allowed;
1317 if (! INSN_P (chain->insn)
1318 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1320 pat = PATTERN (chain->insn);
1321 if (GET_CODE (pat) != PARALLEL)
1324 CLEAR_HARD_REG_SET (clobbered);
1325 CLEAR_HARD_REG_SET (allowed);
1327 /* First, make a mask of all stack regs that are clobbered. */
1328 for (i = 0; i < XVECLEN (pat, 0); i++)
1330 rtx t = XVECEXP (pat, 0, i);
1331 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1332 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1335 /* Get the operand values and constraints out of the insn. */
1336 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1337 constraints, operand_mode);
1339 /* For every operand, see what registers are allowed. */
1340 for (i = 0; i < noperands; i++)
1342 const char *p = constraints[i];
1343 /* For every alternative, we compute the class of registers allowed
1344 for reloading in CLS, and merge its contents into the reg set
1346 int cls = (int) NO_REGS;
1352 if (c == '\0' || c == ',' || c == '#')
1354 /* End of one alternative - mark the regs in the current
1355 class, and reset the class. */
1356 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1362 } while (c != '\0' && c != ',');
1370 case '=': case '+': case '*': case '%': case '?': case '!':
1371 case '0': case '1': case '2': case '3': case '4': case 'm':
1372 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1373 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1374 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1379 cls = (int) reg_class_subunion[cls]
1380 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1385 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1389 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1390 cls = (int) reg_class_subunion[cls]
1391 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1393 cls = (int) reg_class_subunion[cls]
1394 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1396 p += CONSTRAINT_LEN (c, p);
1399 /* Those of the registers which are clobbered, but allowed by the
1400 constraints, must be usable as reload registers. So clear them
1401 out of the life information. */
1402 AND_HARD_REG_SET (allowed, clobbered);
1403 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1404 if (TEST_HARD_REG_BIT (allowed, i))
1406 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1407 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1414 /* Copy the global variables n_reloads and rld into the corresponding elts
1417 copy_reloads (struct insn_chain *chain)
1419 chain->n_reloads = n_reloads;
1420 chain->rld = obstack_alloc (&reload_obstack,
1421 n_reloads * sizeof (struct reload));
1422 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1423 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1426 /* Walk the chain of insns, and determine for each whether it needs reloads
1427 and/or eliminations. Build the corresponding insns_need_reload list, and
1428 set something_needs_elimination as appropriate. */
1430 calculate_needs_all_insns (int global)
1432 struct insn_chain **pprev_reload = &insns_need_reload;
1433 struct insn_chain *chain, *next = 0;
1435 something_needs_elimination = 0;
1437 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1438 for (chain = reload_insn_chain; chain != 0; chain = next)
1440 rtx insn = chain->insn;
1444 /* Clear out the shortcuts. */
1445 chain->n_reloads = 0;
1446 chain->need_elim = 0;
1447 chain->need_reload = 0;
1448 chain->need_operand_change = 0;
1450 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1451 include REG_LABEL), we need to see what effects this has on the
1452 known offsets at labels. */
1454 if (LABEL_P (insn) || JUMP_P (insn)
1455 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1456 set_label_offsets (insn, insn, 0);
1460 rtx old_body = PATTERN (insn);
1461 int old_code = INSN_CODE (insn);
1462 rtx old_notes = REG_NOTES (insn);
1463 int did_elimination = 0;
1464 int operands_changed = 0;
1465 rtx set = single_set (insn);
1467 /* Skip insns that only set an equivalence. */
1468 if (set && REG_P (SET_DEST (set))
1469 && reg_renumber[REGNO (SET_DEST (set))] < 0
1470 && reg_equiv_constant[REGNO (SET_DEST (set))])
1473 /* If needed, eliminate any eliminable registers. */
1474 if (num_eliminable || num_eliminable_invariants)
1475 did_elimination = eliminate_regs_in_insn (insn, 0);
1477 /* Analyze the instruction. */
1478 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1479 global, spill_reg_order);
1481 /* If a no-op set needs more than one reload, this is likely
1482 to be something that needs input address reloads. We
1483 can't get rid of this cleanly later, and it is of no use
1484 anyway, so discard it now.
1485 We only do this when expensive_optimizations is enabled,
1486 since this complements reload inheritance / output
1487 reload deletion, and it can make debugging harder. */
1488 if (flag_expensive_optimizations && n_reloads > 1)
1490 rtx set = single_set (insn);
1492 && SET_SRC (set) == SET_DEST (set)
1493 && REG_P (SET_SRC (set))
1494 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1497 /* Delete it from the reload chain. */
1499 chain->prev->next = next;
1501 reload_insn_chain = next;
1503 next->prev = chain->prev;
1504 chain->next = unused_insn_chains;
1505 unused_insn_chains = chain;
1510 update_eliminable_offsets ();
1512 /* Remember for later shortcuts which insns had any reloads or
1513 register eliminations. */
1514 chain->need_elim = did_elimination;
1515 chain->need_reload = n_reloads > 0;
1516 chain->need_operand_change = operands_changed;
1518 /* Discard any register replacements done. */
1519 if (did_elimination)
1521 obstack_free (&reload_obstack, reload_insn_firstobj);
1522 PATTERN (insn) = old_body;
1523 INSN_CODE (insn) = old_code;
1524 REG_NOTES (insn) = old_notes;
1525 something_needs_elimination = 1;
1528 something_needs_operands_changed |= operands_changed;
1532 copy_reloads (chain);
1533 *pprev_reload = chain;
1534 pprev_reload = &chain->next_need_reload;
1541 /* Comparison function for qsort to decide which of two reloads
1542 should be handled first. *P1 and *P2 are the reload numbers. */
1545 reload_reg_class_lower (const void *r1p, const void *r2p)
1547 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1550 /* Consider required reloads before optional ones. */
1551 t = rld[r1].optional - rld[r2].optional;
1555 /* Count all solitary classes before non-solitary ones. */
1556 t = ((reg_class_size[(int) rld[r2].class] == 1)
1557 - (reg_class_size[(int) rld[r1].class] == 1));
1561 /* Aside from solitaires, consider all multi-reg groups first. */
1562 t = rld[r2].nregs - rld[r1].nregs;
1566 /* Consider reloads in order of increasing reg-class number. */
1567 t = (int) rld[r1].class - (int) rld[r2].class;
1571 /* If reloads are equally urgent, sort by reload number,
1572 so that the results of qsort leave nothing to chance. */
1576 /* The cost of spilling each hard reg. */
1577 static int spill_cost[FIRST_PSEUDO_REGISTER];
1579 /* When spilling multiple hard registers, we use SPILL_COST for the first
1580 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1581 only the first hard reg for a multi-reg pseudo. */
1582 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1584 /* Update the spill cost arrays, considering that pseudo REG is live. */
1587 count_pseudo (int reg)
1589 int freq = REG_FREQ (reg);
1590 int r = reg_renumber[reg];
1593 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1594 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1597 SET_REGNO_REG_SET (&pseudos_counted, reg);
1599 gcc_assert (r >= 0);
1601 spill_add_cost[r] += freq;
1603 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1605 spill_cost[r + nregs] += freq;
1608 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1609 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1612 order_regs_for_reload (struct insn_chain *chain)
1615 HARD_REG_SET used_by_pseudos;
1616 HARD_REG_SET used_by_pseudos2;
1617 reg_set_iterator rsi;
1619 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1621 memset (spill_cost, 0, sizeof spill_cost);
1622 memset (spill_add_cost, 0, sizeof spill_add_cost);
1624 /* Count number of uses of each hard reg by pseudo regs allocated to it
1625 and then order them by decreasing use. First exclude hard registers
1626 that are live in or across this insn. */
1628 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1629 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1630 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1631 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1633 /* Now find out which pseudos are allocated to it, and update
1635 CLEAR_REG_SET (&pseudos_counted);
1637 EXECUTE_IF_SET_IN_REG_SET
1638 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1642 EXECUTE_IF_SET_IN_REG_SET
1643 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1647 CLEAR_REG_SET (&pseudos_counted);
1650 /* Vector of reload-numbers showing the order in which the reloads should
1652 static short reload_order[MAX_RELOADS];
1654 /* This is used to keep track of the spill regs used in one insn. */
1655 static HARD_REG_SET used_spill_regs_local;
1657 /* We decided to spill hard register SPILLED, which has a size of
1658 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1659 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1660 update SPILL_COST/SPILL_ADD_COST. */
1663 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1665 int r = reg_renumber[reg];
1666 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1668 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1669 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1672 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1674 spill_add_cost[r] -= REG_FREQ (reg);
1676 spill_cost[r + nregs] -= REG_FREQ (reg);
1679 /* Find reload register to use for reload number ORDER. */
1682 find_reg (struct insn_chain *chain, int order)
1684 int rnum = reload_order[order];
1685 struct reload *rl = rld + rnum;
1686 int best_cost = INT_MAX;
1690 HARD_REG_SET not_usable;
1691 HARD_REG_SET used_by_other_reload;
1692 reg_set_iterator rsi;
1694 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1695 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1696 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1698 CLEAR_HARD_REG_SET (used_by_other_reload);
1699 for (k = 0; k < order; k++)
1701 int other = reload_order[k];
1703 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1704 for (j = 0; j < rld[other].nregs; j++)
1705 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1708 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1710 unsigned int regno = i;
1712 if (! TEST_HARD_REG_BIT (not_usable, regno)
1713 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1714 && HARD_REGNO_MODE_OK (regno, rl->mode))
1716 int this_cost = spill_cost[regno];
1718 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1720 for (j = 1; j < this_nregs; j++)
1722 this_cost += spill_add_cost[regno + j];
1723 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1724 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1729 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1731 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1733 if (this_cost < best_cost
1734 /* Among registers with equal cost, prefer caller-saved ones, or
1735 use REG_ALLOC_ORDER if it is defined. */
1736 || (this_cost == best_cost
1737 #ifdef REG_ALLOC_ORDER
1738 && (inv_reg_alloc_order[regno]
1739 < inv_reg_alloc_order[best_reg])
1741 && call_used_regs[regno]
1742 && ! call_used_regs[best_reg]
1747 best_cost = this_cost;
1755 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1757 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1758 rl->regno = best_reg;
1760 EXECUTE_IF_SET_IN_REG_SET
1761 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1763 count_spilled_pseudo (best_reg, rl->nregs, j);
1766 EXECUTE_IF_SET_IN_REG_SET
1767 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1769 count_spilled_pseudo (best_reg, rl->nregs, j);
1772 for (i = 0; i < rl->nregs; i++)
1774 gcc_assert (spill_cost[best_reg + i] == 0);
1775 gcc_assert (spill_add_cost[best_reg + i] == 0);
1776 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1781 /* Find more reload regs to satisfy the remaining need of an insn, which
1783 Do it by ascending class number, since otherwise a reg
1784 might be spilled for a big class and might fail to count
1785 for a smaller class even though it belongs to that class. */
1788 find_reload_regs (struct insn_chain *chain)
1792 /* In order to be certain of getting the registers we need,
1793 we must sort the reloads into order of increasing register class.
1794 Then our grabbing of reload registers will parallel the process
1795 that provided the reload registers. */
1796 for (i = 0; i < chain->n_reloads; i++)
1798 /* Show whether this reload already has a hard reg. */
1799 if (chain->rld[i].reg_rtx)
1801 int regno = REGNO (chain->rld[i].reg_rtx);
1802 chain->rld[i].regno = regno;
1804 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1807 chain->rld[i].regno = -1;
1808 reload_order[i] = i;
1811 n_reloads = chain->n_reloads;
1812 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1814 CLEAR_HARD_REG_SET (used_spill_regs_local);
1817 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1819 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1821 /* Compute the order of preference for hard registers to spill. */
1823 order_regs_for_reload (chain);
1825 for (i = 0; i < n_reloads; i++)
1827 int r = reload_order[i];
1829 /* Ignore reloads that got marked inoperative. */
1830 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1831 && ! rld[r].optional
1832 && rld[r].regno == -1)
1833 if (! find_reg (chain, i))
1835 spill_failure (chain->insn, rld[r].class);
1841 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1842 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1844 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1848 select_reload_regs (void)
1850 struct insn_chain *chain;
1852 /* Try to satisfy the needs for each insn. */
1853 for (chain = insns_need_reload; chain != 0;
1854 chain = chain->next_need_reload)
1855 find_reload_regs (chain);
1858 /* Delete all insns that were inserted by emit_caller_save_insns during
1861 delete_caller_save_insns (void)
1863 struct insn_chain *c = reload_insn_chain;
1867 while (c != 0 && c->is_caller_save_insn)
1869 struct insn_chain *next = c->next;
1872 if (c == reload_insn_chain)
1873 reload_insn_chain = next;
1877 next->prev = c->prev;
1879 c->prev->next = next;
1880 c->next = unused_insn_chains;
1881 unused_insn_chains = c;
1889 /* Handle the failure to find a register to spill.
1890 INSN should be one of the insns which needed this particular spill reg. */
1893 spill_failure (rtx insn, enum reg_class class)
1895 if (asm_noperands (PATTERN (insn)) >= 0)
1896 error_for_asm (insn, "can't find a register in class %qs while "
1897 "reloading %<asm%>",
1898 reg_class_names[class]);
1901 error ("unable to find a register to spill in class %qs",
1902 reg_class_names[class]);
1903 fatal_insn ("this is the insn:", insn);
1907 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1908 data that is dead in INSN. */
1911 delete_dead_insn (rtx insn)
1913 rtx prev = prev_real_insn (insn);
1916 /* If the previous insn sets a register that dies in our insn, delete it
1918 if (prev && GET_CODE (PATTERN (prev)) == SET
1919 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1920 && reg_mentioned_p (prev_dest, PATTERN (insn))
1921 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1922 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1923 delete_dead_insn (prev);
1925 SET_INSN_DELETED (insn);
1928 /* Modify the home of pseudo-reg I.
1929 The new home is present in reg_renumber[I].
1931 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1932 or it may be -1, meaning there is none or it is not relevant.
1933 This is used so that all pseudos spilled from a given hard reg
1934 can share one stack slot. */
1937 alter_reg (int i, int from_reg)
1939 /* When outputting an inline function, this can happen
1940 for a reg that isn't actually used. */
1941 if (regno_reg_rtx[i] == 0)
1944 /* If the reg got changed to a MEM at rtl-generation time,
1946 if (!REG_P (regno_reg_rtx[i]))
1949 /* Modify the reg-rtx to contain the new hard reg
1950 number or else to contain its pseudo reg number. */
1951 REGNO (regno_reg_rtx[i])
1952 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1954 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1955 allocate a stack slot for it. */
1957 if (reg_renumber[i] < 0
1958 && REG_N_REFS (i) > 0
1959 && reg_equiv_constant[i] == 0
1960 && reg_equiv_memory_loc[i] == 0)
1963 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1964 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1967 /* Each pseudo reg has an inherent size which comes from its own mode,
1968 and a total size which provides room for paradoxical subregs
1969 which refer to the pseudo reg in wider modes.
1971 We can use a slot already allocated if it provides both
1972 enough inherent space and enough total space.
1973 Otherwise, we allocate a new slot, making sure that it has no less
1974 inherent space, and no less total space, then the previous slot. */
1977 /* No known place to spill from => no slot to reuse. */
1978 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1979 inherent_size == total_size ? 0 : -1);
1980 if (BYTES_BIG_ENDIAN)
1981 /* Cancel the big-endian correction done in assign_stack_local.
1982 Get the address of the beginning of the slot.
1983 This is so we can do a big-endian correction unconditionally
1985 adjust = inherent_size - total_size;
1987 /* Nothing can alias this slot except this pseudo. */
1988 set_mem_alias_set (x, new_alias_set ());
1991 /* Reuse a stack slot if possible. */
1992 else if (spill_stack_slot[from_reg] != 0
1993 && spill_stack_slot_width[from_reg] >= total_size
1994 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1996 x = spill_stack_slot[from_reg];
1998 /* Allocate a bigger slot. */
2001 /* Compute maximum size needed, both for inherent size
2002 and for total size. */
2003 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2006 if (spill_stack_slot[from_reg])
2008 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2010 mode = GET_MODE (spill_stack_slot[from_reg]);
2011 if (spill_stack_slot_width[from_reg] > total_size)
2012 total_size = spill_stack_slot_width[from_reg];
2015 /* Make a slot with that size. */
2016 x = assign_stack_local (mode, total_size,
2017 inherent_size == total_size ? 0 : -1);
2020 /* All pseudos mapped to this slot can alias each other. */
2021 if (spill_stack_slot[from_reg])
2022 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2024 set_mem_alias_set (x, new_alias_set ());
2026 if (BYTES_BIG_ENDIAN)
2028 /* Cancel the big-endian correction done in assign_stack_local.
2029 Get the address of the beginning of the slot.
2030 This is so we can do a big-endian correction unconditionally
2032 adjust = GET_MODE_SIZE (mode) - total_size;
2035 = adjust_address_nv (x, mode_for_size (total_size
2041 spill_stack_slot[from_reg] = stack_slot;
2042 spill_stack_slot_width[from_reg] = total_size;
2045 /* On a big endian machine, the "address" of the slot
2046 is the address of the low part that fits its inherent mode. */
2047 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2048 adjust += (total_size - inherent_size);
2050 /* If we have any adjustment to make, or if the stack slot is the
2051 wrong mode, make a new stack slot. */
2052 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2054 /* If we have a decl for the original register, set it for the
2055 memory. If this is a shared MEM, make a copy. */
2056 if (REG_EXPR (regno_reg_rtx[i])
2057 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2059 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2061 /* We can do this only for the DECLs home pseudo, not for
2062 any copies of it, since otherwise when the stack slot
2063 is reused, nonoverlapping_memrefs_p might think they
2065 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2067 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2070 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2074 /* Save the stack slot for later. */
2075 reg_equiv_memory_loc[i] = x;
2079 /* Mark the slots in regs_ever_live for the hard regs
2080 used by pseudo-reg number REGNO. */
2083 mark_home_live (int regno)
2087 i = reg_renumber[regno];
2090 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2092 regs_ever_live[i++] = 1;
2095 /* This function handles the tracking of elimination offsets around branches.
2097 X is a piece of RTL being scanned.
2099 INSN is the insn that it came from, if any.
2101 INITIAL_P is nonzero if we are to set the offset to be the initial
2102 offset and zero if we are setting the offset of the label to be the
2106 set_label_offsets (rtx x, rtx insn, int initial_p)
2108 enum rtx_code code = GET_CODE (x);
2111 struct elim_table *p;
2116 if (LABEL_REF_NONLOCAL_P (x))
2121 /* ... fall through ... */
2124 /* If we know nothing about this label, set the desired offsets. Note
2125 that this sets the offset at a label to be the offset before a label
2126 if we don't know anything about the label. This is not correct for
2127 the label after a BARRIER, but is the best guess we can make. If
2128 we guessed wrong, we will suppress an elimination that might have
2129 been possible had we been able to guess correctly. */
2131 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2133 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2134 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2135 = (initial_p ? reg_eliminate[i].initial_offset
2136 : reg_eliminate[i].offset);
2137 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2140 /* Otherwise, if this is the definition of a label and it is
2141 preceded by a BARRIER, set our offsets to the known offset of
2145 && (tem = prev_nonnote_insn (insn)) != 0
2147 set_offsets_for_label (insn);
2149 /* If neither of the above cases is true, compare each offset
2150 with those previously recorded and suppress any eliminations
2151 where the offsets disagree. */
2153 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2154 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2155 != (initial_p ? reg_eliminate[i].initial_offset
2156 : reg_eliminate[i].offset))
2157 reg_eliminate[i].can_eliminate = 0;
2162 set_label_offsets (PATTERN (insn), insn, initial_p);
2164 /* ... fall through ... */
2168 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2169 and hence must have all eliminations at their initial offsets. */
2170 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2171 if (REG_NOTE_KIND (tem) == REG_LABEL)
2172 set_label_offsets (XEXP (tem, 0), insn, 1);
2178 /* Each of the labels in the parallel or address vector must be
2179 at their initial offsets. We want the first field for PARALLEL
2180 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2182 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2183 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2188 /* We only care about setting PC. If the source is not RETURN,
2189 IF_THEN_ELSE, or a label, disable any eliminations not at
2190 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2191 isn't one of those possibilities. For branches to a label,
2192 call ourselves recursively.
2194 Note that this can disable elimination unnecessarily when we have
2195 a non-local goto since it will look like a non-constant jump to
2196 someplace in the current function. This isn't a significant
2197 problem since such jumps will normally be when all elimination
2198 pairs are back to their initial offsets. */
2200 if (SET_DEST (x) != pc_rtx)
2203 switch (GET_CODE (SET_SRC (x)))
2210 set_label_offsets (SET_SRC (x), insn, initial_p);
2214 tem = XEXP (SET_SRC (x), 1);
2215 if (GET_CODE (tem) == LABEL_REF)
2216 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2217 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2220 tem = XEXP (SET_SRC (x), 2);
2221 if (GET_CODE (tem) == LABEL_REF)
2222 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2223 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2231 /* If we reach here, all eliminations must be at their initial
2232 offset because we are doing a jump to a variable address. */
2233 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2234 if (p->offset != p->initial_offset)
2235 p->can_eliminate = 0;
2243 /* Scan X and replace any eliminable registers (such as fp) with a
2244 replacement (such as sp), plus an offset.
2246 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2247 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2248 MEM, we are allowed to replace a sum of a register and the constant zero
2249 with the register, which we cannot do outside a MEM. In addition, we need
2250 to record the fact that a register is referenced outside a MEM.
2252 If INSN is an insn, it is the insn containing X. If we replace a REG
2253 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2254 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2255 the REG is being modified.
2257 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2258 That's used when we eliminate in expressions stored in notes.
2259 This means, do not set ref_outside_mem even if the reference
2262 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2263 replacements done assuming all offsets are at their initial values. If
2264 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2265 encounter, return the actual location so that find_reloads will do
2266 the proper thing. */
2269 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2271 enum rtx_code code = GET_CODE (x);
2272 struct elim_table *ep;
2279 if (! current_function_decl)
2301 /* First handle the case where we encounter a bare register that
2302 is eliminable. Replace it with a PLUS. */
2303 if (regno < FIRST_PSEUDO_REGISTER)
2305 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2307 if (ep->from_rtx == x && ep->can_eliminate)
2308 return plus_constant (ep->to_rtx, ep->previous_offset);
2311 else if (reg_renumber && reg_renumber[regno] < 0
2312 && reg_equiv_constant && reg_equiv_constant[regno]
2313 && ! CONSTANT_P (reg_equiv_constant[regno]))
2314 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2318 /* You might think handling MINUS in a manner similar to PLUS is a
2319 good idea. It is not. It has been tried multiple times and every
2320 time the change has had to have been reverted.
2322 Other parts of reload know a PLUS is special (gen_reload for example)
2323 and require special code to handle code a reloaded PLUS operand.
2325 Also consider backends where the flags register is clobbered by a
2326 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2327 lea instruction comes to mind). If we try to reload a MINUS, we
2328 may kill the flags register that was holding a useful value.
2330 So, please before trying to handle MINUS, consider reload as a
2331 whole instead of this little section as well as the backend issues. */
2333 /* If this is the sum of an eliminable register and a constant, rework
2335 if (REG_P (XEXP (x, 0))
2336 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2337 && CONSTANT_P (XEXP (x, 1)))
2339 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2341 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2343 /* The only time we want to replace a PLUS with a REG (this
2344 occurs when the constant operand of the PLUS is the negative
2345 of the offset) is when we are inside a MEM. We won't want
2346 to do so at other times because that would change the
2347 structure of the insn in a way that reload can't handle.
2348 We special-case the commonest situation in
2349 eliminate_regs_in_insn, so just replace a PLUS with a
2350 PLUS here, unless inside a MEM. */
2351 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2352 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2355 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2356 plus_constant (XEXP (x, 1),
2357 ep->previous_offset));
2360 /* If the register is not eliminable, we are done since the other
2361 operand is a constant. */
2365 /* If this is part of an address, we want to bring any constant to the
2366 outermost PLUS. We will do this by doing register replacement in
2367 our operands and seeing if a constant shows up in one of them.
2369 Note that there is no risk of modifying the structure of the insn,
2370 since we only get called for its operands, thus we are either
2371 modifying the address inside a MEM, or something like an address
2372 operand of a load-address insn. */
2375 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2376 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2378 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2380 /* If one side is a PLUS and the other side is a pseudo that
2381 didn't get a hard register but has a reg_equiv_constant,
2382 we must replace the constant here since it may no longer
2383 be in the position of any operand. */
2384 if (GET_CODE (new0) == PLUS && REG_P (new1)
2385 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2386 && reg_renumber[REGNO (new1)] < 0
2387 && reg_equiv_constant != 0
2388 && reg_equiv_constant[REGNO (new1)] != 0)
2389 new1 = reg_equiv_constant[REGNO (new1)];
2390 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2391 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2392 && reg_renumber[REGNO (new0)] < 0
2393 && reg_equiv_constant[REGNO (new0)] != 0)
2394 new0 = reg_equiv_constant[REGNO (new0)];
2396 new = form_sum (new0, new1);
2398 /* As above, if we are not inside a MEM we do not want to
2399 turn a PLUS into something else. We might try to do so here
2400 for an addition of 0 if we aren't optimizing. */
2401 if (! mem_mode && GET_CODE (new) != PLUS)
2402 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2410 /* If this is the product of an eliminable register and a
2411 constant, apply the distribute law and move the constant out
2412 so that we have (plus (mult ..) ..). This is needed in order
2413 to keep load-address insns valid. This case is pathological.
2414 We ignore the possibility of overflow here. */
2415 if (REG_P (XEXP (x, 0))
2416 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2417 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2418 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2420 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2423 /* Refs inside notes don't count for this purpose. */
2424 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2425 || GET_CODE (insn) == INSN_LIST)))
2426 ep->ref_outside_mem = 1;
2429 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2430 ep->previous_offset * INTVAL (XEXP (x, 1)));
2433 /* ... fall through ... */
2437 /* See comments before PLUS about handling MINUS. */
2439 case DIV: case UDIV:
2440 case MOD: case UMOD:
2441 case AND: case IOR: case XOR:
2442 case ROTATERT: case ROTATE:
2443 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2445 case GE: case GT: case GEU: case GTU:
2446 case LE: case LT: case LEU: case LTU:
2448 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2450 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2452 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2453 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2458 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2461 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2462 if (new != XEXP (x, 0))
2464 /* If this is a REG_DEAD note, it is not valid anymore.
2465 Using the eliminated version could result in creating a
2466 REG_DEAD note for the stack or frame pointer. */
2467 if (GET_MODE (x) == REG_DEAD)
2469 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2472 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2476 /* ... fall through ... */
2479 /* Now do eliminations in the rest of the chain. If this was
2480 an EXPR_LIST, this might result in allocating more memory than is
2481 strictly needed, but it simplifies the code. */
2484 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2485 if (new != XEXP (x, 1))
2487 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2495 case STRICT_LOW_PART:
2497 case SIGN_EXTEND: case ZERO_EXTEND:
2498 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2499 case FLOAT: case FIX:
2500 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2508 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2509 if (new != XEXP (x, 0))
2510 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2514 /* Similar to above processing, but preserve SUBREG_BYTE.
2515 Convert (subreg (mem)) to (mem) if not paradoxical.
2516 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2517 pseudo didn't get a hard reg, we must replace this with the
2518 eliminated version of the memory location because push_reload
2519 may do the replacement in certain circumstances. */
2520 if (REG_P (SUBREG_REG (x))
2521 && (GET_MODE_SIZE (GET_MODE (x))
2522 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2523 && reg_equiv_memory_loc != 0
2524 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2526 new = SUBREG_REG (x);
2529 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2531 if (new != SUBREG_REG (x))
2533 int x_size = GET_MODE_SIZE (GET_MODE (x));
2534 int new_size = GET_MODE_SIZE (GET_MODE (new));
2537 && ((x_size < new_size
2538 #ifdef WORD_REGISTER_OPERATIONS
2539 /* On these machines, combine can create rtl of the form
2540 (set (subreg:m1 (reg:m2 R) 0) ...)
2541 where m1 < m2, and expects something interesting to
2542 happen to the entire word. Moreover, it will use the
2543 (reg:m2 R) later, expecting all bits to be preserved.
2544 So if the number of words is the same, preserve the
2545 subreg so that push_reload can see it. */
2546 && ! ((x_size - 1) / UNITS_PER_WORD
2547 == (new_size -1 ) / UNITS_PER_WORD)
2550 || x_size == new_size)
2552 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2554 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2560 /* Our only special processing is to pass the mode of the MEM to our
2561 recursive call and copy the flags. While we are here, handle this
2562 case more efficiently. */
2564 replace_equiv_address_nv (x,
2565 eliminate_regs (XEXP (x, 0),
2566 GET_MODE (x), insn));
2569 /* Handle insn_list USE that a call to a pure function may generate. */
2570 new = eliminate_regs (XEXP (x, 0), 0, insn);
2571 if (new != XEXP (x, 0))
2572 return gen_rtx_USE (GET_MODE (x), new);
2584 /* Process each of our operands recursively. If any have changed, make a
2586 fmt = GET_RTX_FORMAT (code);
2587 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2591 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2592 if (new != XEXP (x, i) && ! copied)
2594 rtx new_x = rtx_alloc (code);
2595 memcpy (new_x, x, RTX_SIZE (code));
2601 else if (*fmt == 'E')
2604 for (j = 0; j < XVECLEN (x, i); j++)
2606 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2607 if (new != XVECEXP (x, i, j) && ! copied_vec)
2609 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2613 rtx new_x = rtx_alloc (code);
2614 memcpy (new_x, x, RTX_SIZE (code));
2618 XVEC (x, i) = new_v;
2621 XVECEXP (x, i, j) = new;
2629 /* Scan rtx X for modifications of elimination target registers. Update
2630 the table of eliminables to reflect the changed state. MEM_MODE is
2631 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2634 elimination_effects (rtx x, enum machine_mode mem_mode)
2636 enum rtx_code code = GET_CODE (x);
2637 struct elim_table *ep;
2661 /* First handle the case where we encounter a bare register that
2662 is eliminable. Replace it with a PLUS. */
2663 if (regno < FIRST_PSEUDO_REGISTER)
2665 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2667 if (ep->from_rtx == x && ep->can_eliminate)
2670 ep->ref_outside_mem = 1;
2675 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2676 && reg_equiv_constant[regno]
2677 && ! function_invariant_p (reg_equiv_constant[regno]))
2678 elimination_effects (reg_equiv_constant[regno], mem_mode);
2687 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2688 if (ep->to_rtx == XEXP (x, 0))
2690 int size = GET_MODE_SIZE (mem_mode);
2692 /* If more bytes than MEM_MODE are pushed, account for them. */
2693 #ifdef PUSH_ROUNDING
2694 if (ep->to_rtx == stack_pointer_rtx)
2695 size = PUSH_ROUNDING (size);
2697 if (code == PRE_DEC || code == POST_DEC)
2699 else if (code == PRE_INC || code == POST_INC)
2701 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2702 && GET_CODE (XEXP (x, 1)) == PLUS
2703 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2704 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2705 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2708 /* These two aren't unary operators. */
2709 if (code == POST_MODIFY || code == PRE_MODIFY)
2712 /* Fall through to generic unary operation case. */
2713 case STRICT_LOW_PART:
2715 case SIGN_EXTEND: case ZERO_EXTEND:
2716 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2717 case FLOAT: case FIX:
2718 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2726 elimination_effects (XEXP (x, 0), mem_mode);
2730 if (REG_P (SUBREG_REG (x))
2731 && (GET_MODE_SIZE (GET_MODE (x))
2732 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2733 && reg_equiv_memory_loc != 0
2734 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2737 elimination_effects (SUBREG_REG (x), mem_mode);
2741 /* If using a register that is the source of an eliminate we still
2742 think can be performed, note it cannot be performed since we don't
2743 know how this register is used. */
2744 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2745 if (ep->from_rtx == XEXP (x, 0))
2746 ep->can_eliminate = 0;
2748 elimination_effects (XEXP (x, 0), mem_mode);
2752 /* If clobbering a register that is the replacement register for an
2753 elimination we still think can be performed, note that it cannot
2754 be performed. Otherwise, we need not be concerned about it. */
2755 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2756 if (ep->to_rtx == XEXP (x, 0))
2757 ep->can_eliminate = 0;
2759 elimination_effects (XEXP (x, 0), mem_mode);
2763 /* Check for setting a register that we know about. */
2764 if (REG_P (SET_DEST (x)))
2766 /* See if this is setting the replacement register for an
2769 If DEST is the hard frame pointer, we do nothing because we
2770 assume that all assignments to the frame pointer are for
2771 non-local gotos and are being done at a time when they are valid
2772 and do not disturb anything else. Some machines want to
2773 eliminate a fake argument pointer (or even a fake frame pointer)
2774 with either the real frame or the stack pointer. Assignments to
2775 the hard frame pointer must not prevent this elimination. */
2777 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2779 if (ep->to_rtx == SET_DEST (x)
2780 && SET_DEST (x) != hard_frame_pointer_rtx)
2782 /* If it is being incremented, adjust the offset. Otherwise,
2783 this elimination can't be done. */
2784 rtx src = SET_SRC (x);
2786 if (GET_CODE (src) == PLUS
2787 && XEXP (src, 0) == SET_DEST (x)
2788 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2789 ep->offset -= INTVAL (XEXP (src, 1));
2791 ep->can_eliminate = 0;
2795 elimination_effects (SET_DEST (x), 0);
2796 elimination_effects (SET_SRC (x), 0);
2800 /* Our only special processing is to pass the mode of the MEM to our
2802 elimination_effects (XEXP (x, 0), GET_MODE (x));
2809 fmt = GET_RTX_FORMAT (code);
2810 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2813 elimination_effects (XEXP (x, i), mem_mode);
2814 else if (*fmt == 'E')
2815 for (j = 0; j < XVECLEN (x, i); j++)
2816 elimination_effects (XVECEXP (x, i, j), mem_mode);
2820 /* Descend through rtx X and verify that no references to eliminable registers
2821 remain. If any do remain, mark the involved register as not
2825 check_eliminable_occurrences (rtx x)
2834 code = GET_CODE (x);
2836 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2838 struct elim_table *ep;
2840 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2841 if (ep->from_rtx == x)
2842 ep->can_eliminate = 0;
2846 fmt = GET_RTX_FORMAT (code);
2847 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2850 check_eliminable_occurrences (XEXP (x, i));
2851 else if (*fmt == 'E')
2854 for (j = 0; j < XVECLEN (x, i); j++)
2855 check_eliminable_occurrences (XVECEXP (x, i, j));
2860 /* Scan INSN and eliminate all eliminable registers in it.
2862 If REPLACE is nonzero, do the replacement destructively. Also
2863 delete the insn as dead it if it is setting an eliminable register.
2865 If REPLACE is zero, do all our allocations in reload_obstack.
2867 If no eliminations were done and this insn doesn't require any elimination
2868 processing (these are not identical conditions: it might be updating sp,
2869 but not referencing fp; this needs to be seen during reload_as_needed so
2870 that the offset between fp and sp can be taken into consideration), zero
2871 is returned. Otherwise, 1 is returned. */
2874 eliminate_regs_in_insn (rtx insn, int replace)
2876 int icode = recog_memoized (insn);
2877 rtx old_body = PATTERN (insn);
2878 int insn_is_asm = asm_noperands (old_body) >= 0;
2879 rtx old_set = single_set (insn);
2883 rtx substed_operand[MAX_RECOG_OPERANDS];
2884 rtx orig_operand[MAX_RECOG_OPERANDS];
2885 struct elim_table *ep;
2888 if (! insn_is_asm && icode < 0)
2890 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2891 || GET_CODE (PATTERN (insn)) == CLOBBER
2892 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2893 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2894 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2898 if (old_set != 0 && REG_P (SET_DEST (old_set))
2899 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2901 /* Check for setting an eliminable register. */
2902 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2903 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2905 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2906 /* If this is setting the frame pointer register to the
2907 hardware frame pointer register and this is an elimination
2908 that will be done (tested above), this insn is really
2909 adjusting the frame pointer downward to compensate for
2910 the adjustment done before a nonlocal goto. */
2911 if (ep->from == FRAME_POINTER_REGNUM
2912 && ep->to == HARD_FRAME_POINTER_REGNUM)
2914 rtx base = SET_SRC (old_set);
2915 rtx base_insn = insn;
2916 HOST_WIDE_INT offset = 0;
2918 while (base != ep->to_rtx)
2920 rtx prev_insn, prev_set;
2922 if (GET_CODE (base) == PLUS
2923 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2925 offset += INTVAL (XEXP (base, 1));
2926 base = XEXP (base, 0);
2928 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2929 && (prev_set = single_set (prev_insn)) != 0
2930 && rtx_equal_p (SET_DEST (prev_set), base))
2932 base = SET_SRC (prev_set);
2933 base_insn = prev_insn;
2939 if (base == ep->to_rtx)
2942 = plus_constant (ep->to_rtx, offset - ep->offset);
2944 new_body = old_body;
2947 new_body = copy_insn (old_body);
2948 if (REG_NOTES (insn))
2949 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2951 PATTERN (insn) = new_body;
2952 old_set = single_set (insn);
2954 /* First see if this insn remains valid when we
2955 make the change. If not, keep the INSN_CODE
2956 the same and let reload fit it up. */
2957 validate_change (insn, &SET_SRC (old_set), src, 1);
2958 validate_change (insn, &SET_DEST (old_set),
2960 if (! apply_change_group ())
2962 SET_SRC (old_set) = src;
2963 SET_DEST (old_set) = ep->to_rtx;
2972 /* In this case this insn isn't serving a useful purpose. We
2973 will delete it in reload_as_needed once we know that this
2974 elimination is, in fact, being done.
2976 If REPLACE isn't set, we can't delete this insn, but needn't
2977 process it since it won't be used unless something changes. */
2980 delete_dead_insn (insn);
2988 /* We allow one special case which happens to work on all machines we
2989 currently support: a single set with the source or a REG_EQUAL
2990 note being a PLUS of an eliminable register and a constant. */
2992 if (old_set && REG_P (SET_DEST (old_set)))
2994 /* First see if the source is of the form (plus (reg) CST). */
2995 if (GET_CODE (SET_SRC (old_set)) == PLUS
2996 && REG_P (XEXP (SET_SRC (old_set), 0))
2997 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2998 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2999 plus_src = SET_SRC (old_set);
3000 else if (REG_P (SET_SRC (old_set)))
3002 /* Otherwise, see if we have a REG_EQUAL note of the form
3003 (plus (reg) CST). */
3005 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3007 if (REG_NOTE_KIND (links) == REG_EQUAL
3008 && GET_CODE (XEXP (links, 0)) == PLUS
3009 && REG_P (XEXP (XEXP (links, 0), 0))
3010 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
3011 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
3013 plus_src = XEXP (links, 0);
3021 rtx reg = XEXP (plus_src, 0);
3022 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3024 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3025 if (ep->from_rtx == reg && ep->can_eliminate)
3027 offset += ep->offset;
3032 /* We assume here that if we need a PARALLEL with
3033 CLOBBERs for this assignment, we can do with the
3034 MATCH_SCRATCHes that add_clobbers allocates.
3035 There's not much we can do if that doesn't work. */
3036 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3040 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3043 rtvec vec = rtvec_alloc (num_clobbers + 1);
3045 vec->elem[0] = PATTERN (insn);
3046 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3047 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3049 gcc_assert (INSN_CODE (insn) >= 0);
3051 /* If we have a nonzero offset, and the source is already
3052 a simple REG, the following transformation would
3053 increase the cost of the insn by replacing a simple REG
3054 with (plus (reg sp) CST). So try only when plus_src
3055 comes from old_set proper, not REG_NOTES. */
3056 else if (SET_SRC (old_set) == plus_src)
3058 new_body = old_body;
3061 new_body = copy_insn (old_body);
3062 if (REG_NOTES (insn))
3063 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3065 PATTERN (insn) = new_body;
3066 old_set = single_set (insn);
3068 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3069 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3075 /* This can't have an effect on elimination offsets, so skip right
3081 /* Determine the effects of this insn on elimination offsets. */
3082 elimination_effects (old_body, 0);
3084 /* Eliminate all eliminable registers occurring in operands that
3085 can be handled by reload. */
3086 extract_insn (insn);
3087 for (i = 0; i < recog_data.n_operands; i++)
3089 orig_operand[i] = recog_data.operand[i];
3090 substed_operand[i] = recog_data.operand[i];
3092 /* For an asm statement, every operand is eliminable. */
3093 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3095 /* Check for setting a register that we know about. */
3096 if (recog_data.operand_type[i] != OP_IN
3097 && REG_P (orig_operand[i]))
3099 /* If we are assigning to a register that can be eliminated, it
3100 must be as part of a PARALLEL, since the code above handles
3101 single SETs. We must indicate that we can no longer
3102 eliminate this reg. */
3103 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3105 if (ep->from_rtx == orig_operand[i])
3106 ep->can_eliminate = 0;
3109 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3110 replace ? insn : NULL_RTX);
3111 if (substed_operand[i] != orig_operand[i])
3113 /* Terminate the search in check_eliminable_occurrences at
3115 *recog_data.operand_loc[i] = 0;
3117 /* If an output operand changed from a REG to a MEM and INSN is an
3118 insn, write a CLOBBER insn. */
3119 if (recog_data.operand_type[i] != OP_IN
3120 && REG_P (orig_operand[i])
3121 && MEM_P (substed_operand[i])
3123 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3128 for (i = 0; i < recog_data.n_dups; i++)
3129 *recog_data.dup_loc[i]
3130 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3132 /* If any eliminable remain, they aren't eliminable anymore. */
3133 check_eliminable_occurrences (old_body);
3135 /* Substitute the operands; the new values are in the substed_operand
3137 for (i = 0; i < recog_data.n_operands; i++)
3138 *recog_data.operand_loc[i] = substed_operand[i];
3139 for (i = 0; i < recog_data.n_dups; i++)
3140 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3142 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3143 re-recognize the insn. We do this in case we had a simple addition
3144 but now can do this as a load-address. This saves an insn in this
3146 If re-recognition fails, the old insn code number will still be used,
3147 and some register operands may have changed into PLUS expressions.
3148 These will be handled by find_reloads by loading them into a register
3153 /* If we aren't replacing things permanently and we changed something,
3154 make another copy to ensure that all the RTL is new. Otherwise
3155 things can go wrong if find_reload swaps commutative operands
3156 and one is inside RTL that has been copied while the other is not. */
3157 new_body = old_body;
3160 new_body = copy_insn (old_body);
3161 if (REG_NOTES (insn))
3162 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3164 PATTERN (insn) = new_body;
3166 /* If we had a move insn but now we don't, rerecognize it. This will
3167 cause spurious re-recognition if the old move had a PARALLEL since
3168 the new one still will, but we can't call single_set without
3169 having put NEW_BODY into the insn and the re-recognition won't
3170 hurt in this rare case. */
3171 /* ??? Why this huge if statement - why don't we just rerecognize the
3175 && ((REG_P (SET_SRC (old_set))
3176 && (GET_CODE (new_body) != SET
3177 || !REG_P (SET_SRC (new_body))))
3178 /* If this was a load from or store to memory, compare
3179 the MEM in recog_data.operand to the one in the insn.
3180 If they are not equal, then rerecognize the insn. */
3182 && ((MEM_P (SET_SRC (old_set))
3183 && SET_SRC (old_set) != recog_data.operand[1])
3184 || (MEM_P (SET_DEST (old_set))
3185 && SET_DEST (old_set) != recog_data.operand[0])))
3186 /* If this was an add insn before, rerecognize. */
3187 || GET_CODE (SET_SRC (old_set)) == PLUS))
3189 int new_icode = recog (PATTERN (insn), insn, 0);
3191 INSN_CODE (insn) = icode;
3195 /* Restore the old body. If there were any changes to it, we made a copy
3196 of it while the changes were still in place, so we'll correctly return
3197 a modified insn below. */
3200 /* Restore the old body. */
3201 for (i = 0; i < recog_data.n_operands; i++)
3202 *recog_data.operand_loc[i] = orig_operand[i];
3203 for (i = 0; i < recog_data.n_dups; i++)
3204 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3207 /* Update all elimination pairs to reflect the status after the current
3208 insn. The changes we make were determined by the earlier call to
3209 elimination_effects.
3211 We also detect cases where register elimination cannot be done,
3212 namely, if a register would be both changed and referenced outside a MEM
3213 in the resulting insn since such an insn is often undefined and, even if
3214 not, we cannot know what meaning will be given to it. Note that it is
3215 valid to have a register used in an address in an insn that changes it
3216 (presumably with a pre- or post-increment or decrement).
3218 If anything changes, return nonzero. */
3220 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3222 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3223 ep->can_eliminate = 0;
3225 ep->ref_outside_mem = 0;
3227 if (ep->previous_offset != ep->offset)
3232 /* If we changed something, perform elimination in REG_NOTES. This is
3233 needed even when REPLACE is zero because a REG_DEAD note might refer
3234 to a register that we eliminate and could cause a different number
3235 of spill registers to be needed in the final reload pass than in
3237 if (val && REG_NOTES (insn) != 0)
3238 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3243 /* Loop through all elimination pairs.
3244 Recalculate the number not at initial offset.
3246 Compute the maximum offset (minimum offset if the stack does not
3247 grow downward) for each elimination pair. */
3250 update_eliminable_offsets (void)
3252 struct elim_table *ep;
3254 num_not_at_initial_offset = 0;
3255 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3257 ep->previous_offset = ep->offset;
3258 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3259 num_not_at_initial_offset++;
3263 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3264 replacement we currently believe is valid, mark it as not eliminable if X
3265 modifies DEST in any way other than by adding a constant integer to it.
3267 If DEST is the frame pointer, we do nothing because we assume that
3268 all assignments to the hard frame pointer are nonlocal gotos and are being
3269 done at a time when they are valid and do not disturb anything else.
3270 Some machines want to eliminate a fake argument pointer with either the
3271 frame or stack pointer. Assignments to the hard frame pointer must not
3272 prevent this elimination.
3274 Called via note_stores from reload before starting its passes to scan
3275 the insns of the function. */
3278 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3282 /* A SUBREG of a hard register here is just changing its mode. We should
3283 not see a SUBREG of an eliminable hard register, but check just in
3285 if (GET_CODE (dest) == SUBREG)
3286 dest = SUBREG_REG (dest);
3288 if (dest == hard_frame_pointer_rtx)
3291 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3292 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3293 && (GET_CODE (x) != SET
3294 || GET_CODE (SET_SRC (x)) != PLUS
3295 || XEXP (SET_SRC (x), 0) != dest
3296 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3298 reg_eliminate[i].can_eliminate_previous
3299 = reg_eliminate[i].can_eliminate = 0;
3304 /* Verify that the initial elimination offsets did not change since the
3305 last call to set_initial_elim_offsets. This is used to catch cases
3306 where something illegal happened during reload_as_needed that could
3307 cause incorrect code to be generated if we did not check for it. */
3310 verify_initial_elim_offsets (void)
3314 if (!num_eliminable)
3317 #ifdef ELIMINABLE_REGS
3319 struct elim_table *ep;
3321 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3323 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3324 if (t != ep->initial_offset)
3329 INITIAL_FRAME_POINTER_OFFSET (t);
3330 if (t != reg_eliminate[0].initial_offset)
3337 /* Reset all offsets on eliminable registers to their initial values. */
3340 set_initial_elim_offsets (void)
3342 struct elim_table *ep = reg_eliminate;
3344 #ifdef ELIMINABLE_REGS
3345 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3347 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3348 ep->previous_offset = ep->offset = ep->initial_offset;
3351 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3352 ep->previous_offset = ep->offset = ep->initial_offset;
3355 num_not_at_initial_offset = 0;
3358 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3361 set_initial_eh_label_offset (rtx label)
3363 set_label_offsets (label, NULL_RTX, 1);
3366 /* Initialize the known label offsets.
3367 Set a known offset for each forced label to be at the initial offset
3368 of each elimination. We do this because we assume that all
3369 computed jumps occur from a location where each elimination is
3370 at its initial offset.
3371 For all other labels, show that we don't know the offsets. */
3374 set_initial_label_offsets (void)
3377 memset (offsets_known_at, 0, num_labels);
3379 for (x = forced_labels; x; x = XEXP (x, 1))
3381 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3383 for_each_eh_label (set_initial_eh_label_offset);
3386 /* Set all elimination offsets to the known values for the code label given
3390 set_offsets_for_label (rtx insn)
3393 int label_nr = CODE_LABEL_NUMBER (insn);
3394 struct elim_table *ep;
3396 num_not_at_initial_offset = 0;
3397 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3399 ep->offset = ep->previous_offset
3400 = offsets_at[label_nr - first_label_num][i];
3401 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3402 num_not_at_initial_offset++;
3406 /* See if anything that happened changes which eliminations are valid.
3407 For example, on the SPARC, whether or not the frame pointer can
3408 be eliminated can depend on what registers have been used. We need
3409 not check some conditions again (such as flag_omit_frame_pointer)
3410 since they can't have changed. */
3413 update_eliminables (HARD_REG_SET *pset)
3415 int previous_frame_pointer_needed = frame_pointer_needed;
3416 struct elim_table *ep;
3418 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3419 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3420 #ifdef ELIMINABLE_REGS
3421 || ! CAN_ELIMINATE (ep->from, ep->to)
3424 ep->can_eliminate = 0;
3426 /* Look for the case where we have discovered that we can't replace
3427 register A with register B and that means that we will now be
3428 trying to replace register A with register C. This means we can
3429 no longer replace register C with register B and we need to disable
3430 such an elimination, if it exists. This occurs often with A == ap,
3431 B == sp, and C == fp. */
3433 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3435 struct elim_table *op;
3438 if (! ep->can_eliminate && ep->can_eliminate_previous)
3440 /* Find the current elimination for ep->from, if there is a
3442 for (op = reg_eliminate;
3443 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3444 if (op->from == ep->from && op->can_eliminate)
3450 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3452 for (op = reg_eliminate;
3453 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3454 if (op->from == new_to && op->to == ep->to)
3455 op->can_eliminate = 0;
3459 /* See if any registers that we thought we could eliminate the previous
3460 time are no longer eliminable. If so, something has changed and we
3461 must spill the register. Also, recompute the number of eliminable
3462 registers and see if the frame pointer is needed; it is if there is
3463 no elimination of the frame pointer that we can perform. */
3465 frame_pointer_needed = 1;
3466 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3468 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3469 && ep->to != HARD_FRAME_POINTER_REGNUM)
3470 frame_pointer_needed = 0;
3472 if (! ep->can_eliminate && ep->can_eliminate_previous)
3474 ep->can_eliminate_previous = 0;
3475 SET_HARD_REG_BIT (*pset, ep->from);
3480 /* If we didn't need a frame pointer last time, but we do now, spill
3481 the hard frame pointer. */
3482 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3483 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3486 /* Initialize the table of registers to eliminate. */
3489 init_elim_table (void)
3491 struct elim_table *ep;
3492 #ifdef ELIMINABLE_REGS
3493 const struct elim_table_1 *ep1;
3497 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3499 /* Does this function require a frame pointer? */
3501 frame_pointer_needed = (! flag_omit_frame_pointer
3502 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3503 and restore sp for alloca. So we can't eliminate
3504 the frame pointer in that case. At some point,
3505 we should improve this by emitting the
3506 sp-adjusting insns for this case. */
3507 || (current_function_calls_alloca
3508 && EXIT_IGNORE_STACK)
3509 || FRAME_POINTER_REQUIRED);
3513 #ifdef ELIMINABLE_REGS
3514 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3515 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3517 ep->from = ep1->from;
3519 ep->can_eliminate = ep->can_eliminate_previous
3520 = (CAN_ELIMINATE (ep->from, ep->to)
3521 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3524 reg_eliminate[0].from = reg_eliminate_1[0].from;
3525 reg_eliminate[0].to = reg_eliminate_1[0].to;
3526 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3527 = ! frame_pointer_needed;
3530 /* Count the number of eliminable registers and build the FROM and TO
3531 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3532 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3533 We depend on this. */
3534 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3536 num_eliminable += ep->can_eliminate;
3537 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3538 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3542 /* Kick all pseudos out of hard register REGNO.
3544 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3545 because we found we can't eliminate some register. In the case, no pseudos
3546 are allowed to be in the register, even if they are only in a block that
3547 doesn't require spill registers, unlike the case when we are spilling this
3548 hard reg to produce another spill register.
3550 Return nonzero if any pseudos needed to be kicked out. */
3553 spill_hard_reg (unsigned int regno, int cant_eliminate)
3559 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3560 regs_ever_live[regno] = 1;
3563 /* Spill every pseudo reg that was allocated to this reg
3564 or to something that overlaps this reg. */
3566 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3567 if (reg_renumber[i] >= 0
3568 && (unsigned int) reg_renumber[i] <= regno
3569 && ((unsigned int) reg_renumber[i]
3570 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3571 [PSEUDO_REGNO_MODE (i)]
3573 SET_REGNO_REG_SET (&spilled_pseudos, i);
3576 /* After find_reload_regs has been run for all insn that need reloads,
3577 and/or spill_hard_regs was called, this function is used to actually
3578 spill pseudo registers and try to reallocate them. It also sets up the
3579 spill_regs array for use by choose_reload_regs. */
3582 finish_spills (int global)
3584 struct insn_chain *chain;
3585 int something_changed = 0;
3587 reg_set_iterator rsi;
3589 /* Build the spill_regs array for the function. */
3590 /* If there are some registers still to eliminate and one of the spill regs
3591 wasn't ever used before, additional stack space may have to be
3592 allocated to store this register. Thus, we may have changed the offset
3593 between the stack and frame pointers, so mark that something has changed.
3595 One might think that we need only set VAL to 1 if this is a call-used
3596 register. However, the set of registers that must be saved by the
3597 prologue is not identical to the call-used set. For example, the
3598 register used by the call insn for the return PC is a call-used register,
3599 but must be saved by the prologue. */
3602 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3603 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3605 spill_reg_order[i] = n_spills;
3606 spill_regs[n_spills++] = i;
3607 if (num_eliminable && ! regs_ever_live[i])
3608 something_changed = 1;
3609 regs_ever_live[i] = 1;
3612 spill_reg_order[i] = -1;
3614 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3616 /* Record the current hard register the pseudo is allocated to in
3617 pseudo_previous_regs so we avoid reallocating it to the same
3618 hard reg in a later pass. */
3619 gcc_assert (reg_renumber[i] >= 0);
3621 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3622 /* Mark it as no longer having a hard register home. */
3623 reg_renumber[i] = -1;
3624 /* We will need to scan everything again. */
3625 something_changed = 1;
3628 /* Retry global register allocation if possible. */
3631 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3632 /* For every insn that needs reloads, set the registers used as spill
3633 regs in pseudo_forbidden_regs for every pseudo live across the
3635 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3637 EXECUTE_IF_SET_IN_REG_SET
3638 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3640 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3641 chain->used_spill_regs);
3643 EXECUTE_IF_SET_IN_REG_SET
3644 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3646 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3647 chain->used_spill_regs);
3651 /* Retry allocating the spilled pseudos. For each reg, merge the
3652 various reg sets that indicate which hard regs can't be used,
3653 and call retry_global_alloc.
3654 We change spill_pseudos here to only contain pseudos that did not
3655 get a new hard register. */
3656 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3657 if (reg_old_renumber[i] != reg_renumber[i])
3659 HARD_REG_SET forbidden;
3660 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3661 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3662 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3663 retry_global_alloc (i, forbidden);
3664 if (reg_renumber[i] >= 0)
3665 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3669 /* Fix up the register information in the insn chain.
3670 This involves deleting those of the spilled pseudos which did not get
3671 a new hard register home from the live_{before,after} sets. */
3672 for (chain = reload_insn_chain; chain; chain = chain->next)
3674 HARD_REG_SET used_by_pseudos;
3675 HARD_REG_SET used_by_pseudos2;
3677 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3678 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3680 /* Mark any unallocated hard regs as available for spills. That
3681 makes inheritance work somewhat better. */
3682 if (chain->need_reload)
3684 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3685 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3686 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3688 /* Save the old value for the sanity test below. */
3689 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3691 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3692 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3693 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3694 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3696 /* Make sure we only enlarge the set. */
3697 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3703 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3704 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3706 int regno = reg_renumber[i];
3707 if (reg_old_renumber[i] == regno)
3710 alter_reg (i, reg_old_renumber[i]);
3711 reg_old_renumber[i] = regno;
3715 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3717 fprintf (dump_file, " Register %d now in %d.\n\n",
3718 i, reg_renumber[i]);
3722 return something_changed;
3725 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3728 scan_paradoxical_subregs (rtx x)
3732 enum rtx_code code = GET_CODE (x);
3742 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3750 if (REG_P (SUBREG_REG (x))
3751 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3752 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3753 = GET_MODE_SIZE (GET_MODE (x));
3760 fmt = GET_RTX_FORMAT (code);
3761 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3764 scan_paradoxical_subregs (XEXP (x, i));
3765 else if (fmt[i] == 'E')
3768 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3769 scan_paradoxical_subregs (XVECEXP (x, i, j));
3774 /* Reload pseudo-registers into hard regs around each insn as needed.
3775 Additional register load insns are output before the insn that needs it
3776 and perhaps store insns after insns that modify the reloaded pseudo reg.
3778 reg_last_reload_reg and reg_reloaded_contents keep track of
3779 which registers are already available in reload registers.
3780 We update these for the reloads that we perform,
3781 as the insns are scanned. */
3784 reload_as_needed (int live_known)
3786 struct insn_chain *chain;
3787 #if defined (AUTO_INC_DEC)
3792 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3793 memset (spill_reg_store, 0, sizeof spill_reg_store);
3794 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3795 reg_has_output_reload = xmalloc (max_regno);
3796 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3797 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3799 set_initial_elim_offsets ();
3801 for (chain = reload_insn_chain; chain; chain = chain->next)
3804 rtx insn = chain->insn;
3805 rtx old_next = NEXT_INSN (insn);
3807 /* If we pass a label, copy the offsets from the label information
3808 into the current offsets of each elimination. */
3810 set_offsets_for_label (insn);
3812 else if (INSN_P (insn))
3814 rtx oldpat = copy_rtx (PATTERN (insn));
3816 /* If this is a USE and CLOBBER of a MEM, ensure that any
3817 references to eliminable registers have been removed. */
3819 if ((GET_CODE (PATTERN (insn)) == USE
3820 || GET_CODE (PATTERN (insn)) == CLOBBER)
3821 && MEM_P (XEXP (PATTERN (insn), 0)))
3822 XEXP (XEXP (PATTERN (insn), 0), 0)
3823 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3824 GET_MODE (XEXP (PATTERN (insn), 0)),
3827 /* If we need to do register elimination processing, do so.
3828 This might delete the insn, in which case we are done. */
3829 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3831 eliminate_regs_in_insn (insn, 1);
3834 update_eliminable_offsets ();
3839 /* If need_elim is nonzero but need_reload is zero, one might think
3840 that we could simply set n_reloads to 0. However, find_reloads
3841 could have done some manipulation of the insn (such as swapping
3842 commutative operands), and these manipulations are lost during
3843 the first pass for every insn that needs register elimination.
3844 So the actions of find_reloads must be redone here. */
3846 if (! chain->need_elim && ! chain->need_reload
3847 && ! chain->need_operand_change)
3849 /* First find the pseudo regs that must be reloaded for this insn.
3850 This info is returned in the tables reload_... (see reload.h).
3851 Also modify the body of INSN by substituting RELOAD
3852 rtx's for those pseudo regs. */
3855 memset (reg_has_output_reload, 0, max_regno);
3856 CLEAR_HARD_REG_SET (reg_is_output_reload);
3858 find_reloads (insn, 1, spill_indirect_levels, live_known,
3864 rtx next = NEXT_INSN (insn);
3867 prev = PREV_INSN (insn);
3869 /* Now compute which reload regs to reload them into. Perhaps
3870 reusing reload regs from previous insns, or else output
3871 load insns to reload them. Maybe output store insns too.
3872 Record the choices of reload reg in reload_reg_rtx. */
3873 choose_reload_regs (chain);
3875 /* Merge any reloads that we didn't combine for fear of
3876 increasing the number of spill registers needed but now
3877 discover can be safely merged. */
3878 if (SMALL_REGISTER_CLASSES)
3879 merge_assigned_reloads (insn);
3881 /* Generate the insns to reload operands into or out of
3882 their reload regs. */
3883 emit_reload_insns (chain);
3885 /* Substitute the chosen reload regs from reload_reg_rtx
3886 into the insn's body (or perhaps into the bodies of other
3887 load and store insn that we just made for reloading
3888 and that we moved the structure into). */
3889 subst_reloads (insn);
3891 /* If this was an ASM, make sure that all the reload insns
3892 we have generated are valid. If not, give an error
3895 if (asm_noperands (PATTERN (insn)) >= 0)
3896 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3897 if (p != insn && INSN_P (p)
3898 && GET_CODE (PATTERN (p)) != USE
3899 && (recog_memoized (p) < 0
3900 || (extract_insn (p), ! constrain_operands (1))))
3902 error_for_asm (insn,
3903 "%<asm%> operand requires "
3904 "impossible reload");
3909 if (num_eliminable && chain->need_elim)
3910 update_eliminable_offsets ();
3912 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3913 is no longer validly lying around to save a future reload.
3914 Note that this does not detect pseudos that were reloaded
3915 for this insn in order to be stored in
3916 (obeying register constraints). That is correct; such reload
3917 registers ARE still valid. */
3918 note_stores (oldpat, forget_old_reloads_1, NULL);
3920 /* There may have been CLOBBER insns placed after INSN. So scan
3921 between INSN and NEXT and use them to forget old reloads. */
3922 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3923 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3924 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3927 /* Likewise for regs altered by auto-increment in this insn.
3928 REG_INC notes have been changed by reloading:
3929 find_reloads_address_1 records substitutions for them,
3930 which have been performed by subst_reloads above. */
3931 for (i = n_reloads - 1; i >= 0; i--)
3933 rtx in_reg = rld[i].in_reg;
3936 enum rtx_code code = GET_CODE (in_reg);
3937 /* PRE_INC / PRE_DEC will have the reload register ending up
3938 with the same value as the stack slot, but that doesn't
3939 hold true for POST_INC / POST_DEC. Either we have to
3940 convert the memory access to a true POST_INC / POST_DEC,
3941 or we can't use the reload register for inheritance. */
3942 if ((code == POST_INC || code == POST_DEC)
3943 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3944 REGNO (rld[i].reg_rtx))
3945 /* Make sure it is the inc/dec pseudo, and not
3946 some other (e.g. output operand) pseudo. */
3947 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3948 == REGNO (XEXP (in_reg, 0))))
3951 rtx reload_reg = rld[i].reg_rtx;
3952 enum machine_mode mode = GET_MODE (reload_reg);
3956 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3958 /* We really want to ignore REG_INC notes here, so
3959 use PATTERN (p) as argument to reg_set_p . */
3960 if (reg_set_p (reload_reg, PATTERN (p)))
3962 n = count_occurrences (PATTERN (p), reload_reg, 0);
3967 n = validate_replace_rtx (reload_reg,
3968 gen_rtx_fmt_e (code,
3973 /* We must also verify that the constraints
3974 are met after the replacement. */
3977 n = constrain_operands (1);
3981 /* If the constraints were not met, then
3982 undo the replacement. */
3985 validate_replace_rtx (gen_rtx_fmt_e (code,
3998 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4000 /* Mark this as having an output reload so that the
4001 REG_INC processing code below won't invalidate
4002 the reload for inheritance. */
4003 SET_HARD_REG_BIT (reg_is_output_reload,
4004 REGNO (reload_reg));
4005 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4008 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4011 else if ((code == PRE_INC || code == PRE_DEC)
4012 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4013 REGNO (rld[i].reg_rtx))
4014 /* Make sure it is the inc/dec pseudo, and not
4015 some other (e.g. output operand) pseudo. */
4016 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4017 == REGNO (XEXP (in_reg, 0))))
4019 SET_HARD_REG_BIT (reg_is_output_reload,
4020 REGNO (rld[i].reg_rtx));
4021 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4025 /* If a pseudo that got a hard register is auto-incremented,
4026 we must purge records of copying it into pseudos without
4028 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4029 if (REG_NOTE_KIND (x) == REG_INC)
4031 /* See if this pseudo reg was reloaded in this insn.
4032 If so, its last-reload info is still valid
4033 because it is based on this insn's reload. */
4034 for (i = 0; i < n_reloads; i++)
4035 if (rld[i].out == XEXP (x, 0))
4039 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4043 /* A reload reg's contents are unknown after a label. */
4045 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4047 /* Don't assume a reload reg is still good after a call insn
4048 if it is a call-used reg, or if it contains a value that will
4049 be partially clobbered by the call. */
4050 else if (CALL_P (insn))
4052 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4053 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4058 free (reg_last_reload_reg);
4059 free (reg_has_output_reload);
4062 /* Discard all record of any value reloaded from X,
4063 or reloaded in X from someplace else;
4064 unless X is an output reload reg of the current insn.
4066 X may be a hard reg (the reload reg)
4067 or it may be a pseudo reg that was reloaded from. */
4070 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4071 void *data ATTRIBUTE_UNUSED)
4076 /* note_stores does give us subregs of hard regs,
4077 subreg_regno_offset requires a hard reg. */
4078 while (GET_CODE (x) == SUBREG)
4080 /* We ignore the subreg offset when calculating the regno,
4081 because we are using the entire underlying hard register
4091 if (regno >= FIRST_PSEUDO_REGISTER)
4097 nr = hard_regno_nregs[regno][GET_MODE (x)];
4098 /* Storing into a spilled-reg invalidates its contents.
4099 This can happen if a block-local pseudo is allocated to that reg
4100 and it wasn't spilled because this block's total need is 0.
4101 Then some insn might have an optional reload and use this reg. */
4102 for (i = 0; i < nr; i++)
4103 /* But don't do this if the reg actually serves as an output
4104 reload reg in the current instruction. */
4106 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4108 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4109 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4110 spill_reg_store[regno + i] = 0;
4114 /* Since value of X has changed,
4115 forget any value previously copied from it. */
4118 /* But don't forget a copy if this is the output reload
4119 that establishes the copy's validity. */
4120 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4121 reg_last_reload_reg[regno + nr] = 0;
4124 /* The following HARD_REG_SETs indicate when each hard register is
4125 used for a reload of various parts of the current insn. */
4127 /* If reg is unavailable for all reloads. */
4128 static HARD_REG_SET reload_reg_unavailable;
4129 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4130 static HARD_REG_SET reload_reg_used;
4131 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4132 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4133 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4134 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4135 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4136 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4137 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4138 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4139 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4140 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4141 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4142 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4143 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4144 static HARD_REG_SET reload_reg_used_in_op_addr;
4145 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4146 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4147 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4148 static HARD_REG_SET reload_reg_used_in_insn;
4149 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4150 static HARD_REG_SET reload_reg_used_in_other_addr;
4152 /* If reg is in use as a reload reg for any sort of reload. */
4153 static HARD_REG_SET reload_reg_used_at_all;
4155 /* If reg is use as an inherited reload. We just mark the first register
4157 static HARD_REG_SET reload_reg_used_for_inherit;
4159 /* Records which hard regs are used in any way, either as explicit use or
4160 by being allocated to a pseudo during any point of the current insn. */
4161 static HARD_REG_SET reg_used_in_insn;
4163 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4164 TYPE. MODE is used to indicate how many consecutive regs are
4168 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4169 enum machine_mode mode)
4171 unsigned int nregs = hard_regno_nregs[regno][mode];
4174 for (i = regno; i < nregs + regno; i++)
4179 SET_HARD_REG_BIT (reload_reg_used, i);
4182 case RELOAD_FOR_INPUT_ADDRESS:
4183 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4186 case RELOAD_FOR_INPADDR_ADDRESS:
4187 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4190 case RELOAD_FOR_OUTPUT_ADDRESS:
4191 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4194 case RELOAD_FOR_OUTADDR_ADDRESS:
4195 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4198 case RELOAD_FOR_OPERAND_ADDRESS:
4199 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4202 case RELOAD_FOR_OPADDR_ADDR:
4203 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4206 case RELOAD_FOR_OTHER_ADDRESS:
4207 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4210 case RELOAD_FOR_INPUT:
4211 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4214 case RELOAD_FOR_OUTPUT:
4215 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4218 case RELOAD_FOR_INSN:
4219 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4223 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4227 /* Similarly, but show REGNO is no longer in use for a reload. */
4230 clear_reload_reg_in_use (unsigned int regno, int opnum,
4231 enum reload_type type, enum machine_mode mode)
4233 unsigned int nregs = hard_regno_nregs[regno][mode];
4234 unsigned int start_regno, end_regno, r;
4236 /* A complication is that for some reload types, inheritance might
4237 allow multiple reloads of the same types to share a reload register.
4238 We set check_opnum if we have to check only reloads with the same
4239 operand number, and check_any if we have to check all reloads. */
4240 int check_opnum = 0;
4242 HARD_REG_SET *used_in_set;
4247 used_in_set = &reload_reg_used;
4250 case RELOAD_FOR_INPUT_ADDRESS:
4251 used_in_set = &reload_reg_used_in_input_addr[opnum];
4254 case RELOAD_FOR_INPADDR_ADDRESS:
4256 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4259 case RELOAD_FOR_OUTPUT_ADDRESS:
4260 used_in_set = &reload_reg_used_in_output_addr[opnum];
4263 case RELOAD_FOR_OUTADDR_ADDRESS:
4265 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4268 case RELOAD_FOR_OPERAND_ADDRESS:
4269 used_in_set = &reload_reg_used_in_op_addr;
4272 case RELOAD_FOR_OPADDR_ADDR:
4274 used_in_set = &reload_reg_used_in_op_addr_reload;
4277 case RELOAD_FOR_OTHER_ADDRESS:
4278 used_in_set = &reload_reg_used_in_other_addr;
4282 case RELOAD_FOR_INPUT:
4283 used_in_set = &reload_reg_used_in_input[opnum];
4286 case RELOAD_FOR_OUTPUT:
4287 used_in_set = &reload_reg_used_in_output[opnum];
4290 case RELOAD_FOR_INSN:
4291 used_in_set = &reload_reg_used_in_insn;
4296 /* We resolve conflicts with remaining reloads of the same type by
4297 excluding the intervals of reload registers by them from the
4298 interval of freed reload registers. Since we only keep track of
4299 one set of interval bounds, we might have to exclude somewhat
4300 more than what would be necessary if we used a HARD_REG_SET here.
4301 But this should only happen very infrequently, so there should
4302 be no reason to worry about it. */
4304 start_regno = regno;
4305 end_regno = regno + nregs;
4306 if (check_opnum || check_any)
4308 for (i = n_reloads - 1; i >= 0; i--)
4310 if (rld[i].when_needed == type
4311 && (check_any || rld[i].opnum == opnum)
4314 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4315 unsigned int conflict_end
4317 + hard_regno_nregs[conflict_start][rld[i].mode]);
4319 /* If there is an overlap with the first to-be-freed register,
4320 adjust the interval start. */
4321 if (conflict_start <= start_regno && conflict_end > start_regno)
4322 start_regno = conflict_end;
4323 /* Otherwise, if there is a conflict with one of the other
4324 to-be-freed registers, adjust the interval end. */
4325 if (conflict_start > start_regno && conflict_start < end_regno)
4326 end_regno = conflict_start;
4331 for (r = start_regno; r < end_regno; r++)
4332 CLEAR_HARD_REG_BIT (*used_in_set, r);
4335 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4336 specified by OPNUM and TYPE. */
4339 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4343 /* In use for a RELOAD_OTHER means it's not available for anything. */
4344 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4345 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4351 /* In use for anything means we can't use it for RELOAD_OTHER. */
4352 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4353 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4354 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4355 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4358 for (i = 0; i < reload_n_operands; i++)
4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4360 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4361 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4362 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4363 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4364 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4369 case RELOAD_FOR_INPUT:
4370 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4371 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4374 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4377 /* If it is used for some other input, can't use it. */
4378 for (i = 0; i < reload_n_operands; i++)
4379 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4382 /* If it is used in a later operand's address, can't use it. */
4383 for (i = opnum + 1; i < reload_n_operands; i++)
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4385 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4390 case RELOAD_FOR_INPUT_ADDRESS:
4391 /* Can't use a register if it is used for an input address for this
4392 operand or used as an input in an earlier one. */
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4394 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4397 for (i = 0; i < opnum; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4403 case RELOAD_FOR_INPADDR_ADDRESS:
4404 /* Can't use a register if it is used for an input address
4405 for this operand or used as an input in an earlier
4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4410 for (i = 0; i < opnum; i++)
4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4416 case RELOAD_FOR_OUTPUT_ADDRESS:
4417 /* Can't use a register if it is used for an output address for this
4418 operand or used as an output in this or a later operand. Note
4419 that multiple output operands are emitted in reverse order, so
4420 the conflicting ones are those with lower indices. */
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4424 for (i = 0; i <= opnum; i++)
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4430 case RELOAD_FOR_OUTADDR_ADDRESS:
4431 /* Can't use a register if it is used for an output address
4432 for this operand or used as an output in this or a
4433 later operand. Note that multiple output operands are
4434 emitted in reverse order, so the conflicting ones are
4435 those with lower indices. */
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4439 for (i = 0; i <= opnum; i++)
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4445 case RELOAD_FOR_OPERAND_ADDRESS:
4446 for (i = 0; i < reload_n_operands; i++)
4447 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4450 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4451 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4453 case RELOAD_FOR_OPADDR_ADDR:
4454 for (i = 0; i < reload_n_operands; i++)
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4458 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4460 case RELOAD_FOR_OUTPUT:
4461 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4462 outputs, or an operand address for this or an earlier output.
4463 Note that multiple output operands are emitted in reverse order,
4464 so the conflicting ones are those with higher indices. */
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4468 for (i = 0; i < reload_n_operands; i++)
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4472 for (i = opnum; i < reload_n_operands; i++)
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4474 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4479 case RELOAD_FOR_INSN:
4480 for (i = 0; i < reload_n_operands; i++)
4481 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4485 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4486 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4488 case RELOAD_FOR_OTHER_ADDRESS:
4489 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4496 /* Return 1 if the value in reload reg REGNO, as used by a reload
4497 needed for the part of the insn specified by OPNUM and TYPE,
4498 is still available in REGNO at the end of the insn.
4500 We can assume that the reload reg was already tested for availability
4501 at the time it is needed, and we should not check this again,
4502 in case the reg has already been marked in use. */
4505 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4512 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4513 its value must reach the end. */
4516 /* If this use is for part of the insn,
4517 its value reaches if no subsequent part uses the same register.
4518 Just like the above function, don't try to do this with lots
4521 case RELOAD_FOR_OTHER_ADDRESS:
4522 /* Here we check for everything else, since these don't conflict
4523 with anything else and everything comes later. */
4525 for (i = 0; i < reload_n_operands; i++)
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4529 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4531 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4534 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4535 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4536 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4537 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4539 case RELOAD_FOR_INPUT_ADDRESS:
4540 case RELOAD_FOR_INPADDR_ADDRESS:
4541 /* Similar, except that we check only for this and subsequent inputs
4542 and the address of only subsequent inputs and we do not need
4543 to check for RELOAD_OTHER objects since they are known not to
4546 for (i = opnum; i < reload_n_operands; i++)
4547 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4550 for (i = opnum + 1; i < reload_n_operands; i++)
4551 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4552 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4555 for (i = 0; i < reload_n_operands; i++)
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4558 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4561 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4564 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4565 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4566 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4568 case RELOAD_FOR_INPUT:
4569 /* Similar to input address, except we start at the next operand for
4570 both input and input address and we do not check for
4571 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4574 for (i = opnum + 1; i < reload_n_operands; i++)
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4577 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4580 /* ... fall through ... */
4582 case RELOAD_FOR_OPERAND_ADDRESS:
4583 /* Check outputs and their addresses. */
4585 for (i = 0; i < reload_n_operands; i++)
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4587 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4588 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4591 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4593 case RELOAD_FOR_OPADDR_ADDR:
4594 for (i = 0; i < reload_n_operands; i++)
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4597 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4600 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4601 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4602 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4604 case RELOAD_FOR_INSN:
4605 /* These conflict with other outputs with RELOAD_OTHER. So
4606 we need only check for output addresses. */
4608 opnum = reload_n_operands;
4610 /* ... fall through ... */
4612 case RELOAD_FOR_OUTPUT:
4613 case RELOAD_FOR_OUTPUT_ADDRESS:
4614 case RELOAD_FOR_OUTADDR_ADDRESS:
4615 /* We already know these can't conflict with a later output. So the
4616 only thing to check are later output addresses.
4617 Note that multiple output operands are emitted in reverse order,
4618 so the conflicting ones are those with lower indices. */
4619 for (i = 0; i < opnum; i++)
4620 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4621 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4631 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4634 This function uses the same algorithm as reload_reg_free_p above. */
4637 reloads_conflict (int r1, int r2)
4639 enum reload_type r1_type = rld[r1].when_needed;
4640 enum reload_type r2_type = rld[r2].when_needed;
4641 int r1_opnum = rld[r1].opnum;
4642 int r2_opnum = rld[r2].opnum;
4644 /* RELOAD_OTHER conflicts with everything. */
4645 if (r2_type == RELOAD_OTHER)
4648 /* Otherwise, check conflicts differently for each type. */
4652 case RELOAD_FOR_INPUT:
4653 return (r2_type == RELOAD_FOR_INSN
4654 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4655 || r2_type == RELOAD_FOR_OPADDR_ADDR
4656 || r2_type == RELOAD_FOR_INPUT
4657 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4658 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4659 && r2_opnum > r1_opnum));
4661 case RELOAD_FOR_INPUT_ADDRESS:
4662 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4663 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4665 case RELOAD_FOR_INPADDR_ADDRESS:
4666 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4667 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4669 case RELOAD_FOR_OUTPUT_ADDRESS:
4670 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4671 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4673 case RELOAD_FOR_OUTADDR_ADDRESS:
4674 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4675 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4677 case RELOAD_FOR_OPERAND_ADDRESS:
4678 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4679 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4681 case RELOAD_FOR_OPADDR_ADDR:
4682 return (r2_type == RELOAD_FOR_INPUT
4683 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4685 case RELOAD_FOR_OUTPUT:
4686 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4687 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4688 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4689 && r2_opnum >= r1_opnum));
4691 case RELOAD_FOR_INSN:
4692 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4693 || r2_type == RELOAD_FOR_INSN
4694 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4696 case RELOAD_FOR_OTHER_ADDRESS:
4697 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4707 /* Indexed by reload number, 1 if incoming value
4708 inherited from previous insns. */
4709 static char reload_inherited[MAX_RELOADS];
4711 /* For an inherited reload, this is the insn the reload was inherited from,
4712 if we know it. Otherwise, this is 0. */
4713 static rtx reload_inheritance_insn[MAX_RELOADS];
4715 /* If nonzero, this is a place to get the value of the reload,
4716 rather than using reload_in. */
4717 static rtx reload_override_in[MAX_RELOADS];
4719 /* For each reload, the hard register number of the register used,
4720 or -1 if we did not need a register for this reload. */
4721 static int reload_spill_index[MAX_RELOADS];
4723 /* Subroutine of free_for_value_p, used to check a single register.
4724 START_REGNO is the starting regno of the full reload register
4725 (possibly comprising multiple hard registers) that we are considering. */
4728 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4729 enum reload_type type, rtx value, rtx out,
4730 int reloadnum, int ignore_address_reloads)
4733 /* Set if we see an input reload that must not share its reload register
4734 with any new earlyclobber, but might otherwise share the reload
4735 register with an output or input-output reload. */
4736 int check_earlyclobber = 0;
4740 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4743 if (out == const0_rtx)
4749 /* We use some pseudo 'time' value to check if the lifetimes of the
4750 new register use would overlap with the one of a previous reload
4751 that is not read-only or uses a different value.
4752 The 'time' used doesn't have to be linear in any shape or form, just
4754 Some reload types use different 'buckets' for each operand.
4755 So there are MAX_RECOG_OPERANDS different time values for each
4757 We compute TIME1 as the time when the register for the prospective
4758 new reload ceases to be live, and TIME2 for each existing
4759 reload as the time when that the reload register of that reload
4761 Where there is little to be gained by exact lifetime calculations,
4762 we just make conservative assumptions, i.e. a longer lifetime;
4763 this is done in the 'default:' cases. */
4766 case RELOAD_FOR_OTHER_ADDRESS:
4767 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4768 time1 = copy ? 0 : 1;
4771 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4773 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4774 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4775 respectively, to the time values for these, we get distinct time
4776 values. To get distinct time values for each operand, we have to
4777 multiply opnum by at least three. We round that up to four because
4778 multiply by four is often cheaper. */
4779 case RELOAD_FOR_INPADDR_ADDRESS:
4780 time1 = opnum * 4 + 2;
4782 case RELOAD_FOR_INPUT_ADDRESS:
4783 time1 = opnum * 4 + 3;
4785 case RELOAD_FOR_INPUT:
4786 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4787 executes (inclusive). */
4788 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4790 case RELOAD_FOR_OPADDR_ADDR:
4792 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4793 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4795 case RELOAD_FOR_OPERAND_ADDRESS:
4796 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4798 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4800 case RELOAD_FOR_OUTADDR_ADDRESS:
4801 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4803 case RELOAD_FOR_OUTPUT_ADDRESS:
4804 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4807 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4810 for (i = 0; i < n_reloads; i++)
4812 rtx reg = rld[i].reg_rtx;
4813 if (reg && REG_P (reg)
4814 && ((unsigned) regno - true_regnum (reg)
4815 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4818 rtx other_input = rld[i].in;
4820 /* If the other reload loads the same input value, that
4821 will not cause a conflict only if it's loading it into
4822 the same register. */
4823 if (true_regnum (reg) != start_regno)
4824 other_input = NULL_RTX;
4825 if (! other_input || ! rtx_equal_p (other_input, value)
4826 || rld[i].out || out)
4829 switch (rld[i].when_needed)
4831 case RELOAD_FOR_OTHER_ADDRESS:
4834 case RELOAD_FOR_INPADDR_ADDRESS:
4835 /* find_reloads makes sure that a
4836 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4837 by at most one - the first -
4838 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4839 address reload is inherited, the address address reload
4840 goes away, so we can ignore this conflict. */
4841 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4842 && ignore_address_reloads
4843 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4844 Then the address address is still needed to store
4845 back the new address. */
4846 && ! rld[reloadnum].out)
4848 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4849 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4851 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4852 && ignore_address_reloads
4853 /* Unless we are reloading an auto_inc expression. */
4854 && ! rld[reloadnum].out)
4856 time2 = rld[i].opnum * 4 + 2;
4858 case RELOAD_FOR_INPUT_ADDRESS:
4859 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4860 && ignore_address_reloads
4861 && ! rld[reloadnum].out)
4863 time2 = rld[i].opnum * 4 + 3;
4865 case RELOAD_FOR_INPUT:
4866 time2 = rld[i].opnum * 4 + 4;
4867 check_earlyclobber = 1;
4869 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4870 == MAX_RECOG_OPERAND * 4 */
4871 case RELOAD_FOR_OPADDR_ADDR:
4872 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4873 && ignore_address_reloads
4874 && ! rld[reloadnum].out)
4876 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4878 case RELOAD_FOR_OPERAND_ADDRESS:
4879 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4880 check_earlyclobber = 1;
4882 case RELOAD_FOR_INSN:
4883 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4885 case RELOAD_FOR_OUTPUT:
4886 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4887 instruction is executed. */
4888 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4890 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4891 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4893 case RELOAD_FOR_OUTADDR_ADDRESS:
4894 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4895 && ignore_address_reloads
4896 && ! rld[reloadnum].out)
4898 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4900 case RELOAD_FOR_OUTPUT_ADDRESS:
4901 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4904 /* If there is no conflict in the input part, handle this
4905 like an output reload. */
4906 if (! rld[i].in || rtx_equal_p (other_input, value))
4908 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4909 /* Earlyclobbered outputs must conflict with inputs. */
4910 if (earlyclobber_operand_p (rld[i].out))
4911 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4916 /* RELOAD_OTHER might be live beyond instruction execution,
4917 but this is not obvious when we set time2 = 1. So check
4918 here if there might be a problem with the new reload
4919 clobbering the register used by the RELOAD_OTHER. */
4927 && (! rld[i].in || rld[i].out
4928 || ! rtx_equal_p (other_input, value)))
4929 || (out && rld[reloadnum].out_reg
4930 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4936 /* Earlyclobbered outputs must conflict with inputs. */
4937 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4943 /* Return 1 if the value in reload reg REGNO, as used by a reload
4944 needed for the part of the insn specified by OPNUM and TYPE,
4945 may be used to load VALUE into it.
4947 MODE is the mode in which the register is used, this is needed to
4948 determine how many hard regs to test.
4950 Other read-only reloads with the same value do not conflict
4951 unless OUT is nonzero and these other reloads have to live while
4952 output reloads live.
4953 If OUT is CONST0_RTX, this is a special case: it means that the
4954 test should not be for using register REGNO as reload register, but
4955 for copying from register REGNO into the reload register.
4957 RELOADNUM is the number of the reload we want to load this value for;
4958 a reload does not conflict with itself.
4960 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4961 reloads that load an address for the very reload we are considering.
4963 The caller has to make sure that there is no conflict with the return
4967 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4968 enum reload_type type, rtx value, rtx out, int reloadnum,
4969 int ignore_address_reloads)
4971 int nregs = hard_regno_nregs[regno][mode];
4973 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4974 value, out, reloadnum,
4975 ignore_address_reloads))
4980 /* Return nonzero if the rtx X is invariant over the current function. */
4981 /* ??? Actually, the places where we use this expect exactly what is
4982 tested here, and not everything that is function invariant. In
4983 particular, the frame pointer and arg pointer are special cased;
4984 pic_offset_table_rtx is not, and we must not spill these things to
4988 function_invariant_p (rtx x)
4992 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4994 if (GET_CODE (x) == PLUS
4995 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4996 && CONSTANT_P (XEXP (x, 1)))
5001 /* Determine whether the reload reg X overlaps any rtx'es used for
5002 overriding inheritance. Return nonzero if so. */
5005 conflicts_with_override (rtx x)
5008 for (i = 0; i < n_reloads; i++)
5009 if (reload_override_in[i]
5010 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5015 /* Give an error message saying we failed to find a reload for INSN,
5016 and clear out reload R. */
5018 failed_reload (rtx insn, int r)
5020 if (asm_noperands (PATTERN (insn)) < 0)
5021 /* It's the compiler's fault. */
5022 fatal_insn ("could not find a spill register", insn);
5024 /* It's the user's fault; the operand's mode and constraint
5025 don't match. Disable this reload so we don't crash in final. */
5026 error_for_asm (insn,
5027 "%<asm%> operand constraint incompatible with operand size");
5031 rld[r].optional = 1;
5032 rld[r].secondary_p = 1;
5035 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5036 for reload R. If it's valid, get an rtx for it. Return nonzero if
5039 set_reload_reg (int i, int r)
5042 rtx reg = spill_reg_rtx[i];
5044 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5045 spill_reg_rtx[i] = reg
5046 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5048 regno = true_regnum (reg);
5050 /* Detect when the reload reg can't hold the reload mode.
5051 This used to be one `if', but Sequent compiler can't handle that. */
5052 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5054 enum machine_mode test_mode = VOIDmode;
5056 test_mode = GET_MODE (rld[r].in);
5057 /* If rld[r].in has VOIDmode, it means we will load it
5058 in whatever mode the reload reg has: to wit, rld[r].mode.
5059 We have already tested that for validity. */
5060 /* Aside from that, we need to test that the expressions
5061 to reload from or into have modes which are valid for this
5062 reload register. Otherwise the reload insns would be invalid. */
5063 if (! (rld[r].in != 0 && test_mode != VOIDmode
5064 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5065 if (! (rld[r].out != 0
5066 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5068 /* The reg is OK. */
5071 /* Mark as in use for this insn the reload regs we use
5073 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5074 rld[r].when_needed, rld[r].mode);
5076 rld[r].reg_rtx = reg;
5077 reload_spill_index[r] = spill_regs[i];
5084 /* Find a spill register to use as a reload register for reload R.
5085 LAST_RELOAD is nonzero if this is the last reload for the insn being
5088 Set rld[R].reg_rtx to the register allocated.
5090 We return 1 if successful, or 0 if we couldn't find a spill reg and
5091 we didn't change anything. */
5094 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5099 /* If we put this reload ahead, thinking it is a group,
5100 then insist on finding a group. Otherwise we can grab a
5101 reg that some other reload needs.
5102 (That can happen when we have a 68000 DATA_OR_FP_REG
5103 which is a group of data regs or one fp reg.)
5104 We need not be so restrictive if there are no more reloads
5107 ??? Really it would be nicer to have smarter handling
5108 for that kind of reg class, where a problem like this is normal.
5109 Perhaps those classes should be avoided for reloading
5110 by use of more alternatives. */
5112 int force_group = rld[r].nregs > 1 && ! last_reload;
5114 /* If we want a single register and haven't yet found one,
5115 take any reg in the right class and not in use.
5116 If we want a consecutive group, here is where we look for it.
5118 We use two passes so we can first look for reload regs to
5119 reuse, which are already in use for other reloads in this insn,
5120 and only then use additional registers.
5121 I think that maximizing reuse is needed to make sure we don't
5122 run out of reload regs. Suppose we have three reloads, and
5123 reloads A and B can share regs. These need two regs.
5124 Suppose A and B are given different regs.
5125 That leaves none for C. */
5126 for (pass = 0; pass < 2; pass++)
5128 /* I is the index in spill_regs.
5129 We advance it round-robin between insns to use all spill regs
5130 equally, so that inherited reloads have a chance
5131 of leapfrogging each other. */
5135 for (count = 0; count < n_spills; count++)
5137 int class = (int) rld[r].class;
5143 regnum = spill_regs[i];
5145 if ((reload_reg_free_p (regnum, rld[r].opnum,
5148 /* We check reload_reg_used to make sure we
5149 don't clobber the return register. */
5150 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5151 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5152 rld[r].when_needed, rld[r].in,
5154 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5155 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5156 /* Look first for regs to share, then for unshared. But
5157 don't share regs used for inherited reloads; they are
5158 the ones we want to preserve. */
5160 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5162 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5165 int nr = hard_regno_nregs[regnum][rld[r].mode];
5166 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5167 (on 68000) got us two FP regs. If NR is 1,
5168 we would reject both of them. */
5171 /* If we need only one reg, we have already won. */
5174 /* But reject a single reg if we demand a group. */
5179 /* Otherwise check that as many consecutive regs as we need
5180 are available here. */
5183 int regno = regnum + nr - 1;
5184 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5185 && spill_reg_order[regno] >= 0
5186 && reload_reg_free_p (regno, rld[r].opnum,
5187 rld[r].when_needed)))
5196 /* If we found something on pass 1, omit pass 2. */
5197 if (count < n_spills)
5201 /* We should have found a spill register by now. */
5202 if (count >= n_spills)
5205 /* I is the index in SPILL_REG_RTX of the reload register we are to
5206 allocate. Get an rtx for it and find its register number. */
5208 return set_reload_reg (i, r);
5211 /* Initialize all the tables needed to allocate reload registers.
5212 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5213 is the array we use to restore the reg_rtx field for every reload. */
5216 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5220 for (i = 0; i < n_reloads; i++)
5221 rld[i].reg_rtx = save_reload_reg_rtx[i];
5223 memset (reload_inherited, 0, MAX_RELOADS);
5224 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5225 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5227 CLEAR_HARD_REG_SET (reload_reg_used);
5228 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5229 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5230 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5231 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5232 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5234 CLEAR_HARD_REG_SET (reg_used_in_insn);
5237 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5238 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5239 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5240 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5241 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5242 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5245 for (i = 0; i < reload_n_operands; i++)
5247 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5248 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5249 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5250 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5251 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5252 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5255 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5257 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5259 for (i = 0; i < n_reloads; i++)
5260 /* If we have already decided to use a certain register,
5261 don't use it in another way. */
5263 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5264 rld[i].when_needed, rld[i].mode);
5267 /* Assign hard reg targets for the pseudo-registers we must reload
5268 into hard regs for this insn.
5269 Also output the instructions to copy them in and out of the hard regs.
5271 For machines with register classes, we are responsible for
5272 finding a reload reg in the proper class. */
5275 choose_reload_regs (struct insn_chain *chain)
5277 rtx insn = chain->insn;
5279 unsigned int max_group_size = 1;
5280 enum reg_class group_class = NO_REGS;
5281 int pass, win, inheritance;
5283 rtx save_reload_reg_rtx[MAX_RELOADS];
5285 /* In order to be certain of getting the registers we need,
5286 we must sort the reloads into order of increasing register class.
5287 Then our grabbing of reload registers will parallel the process
5288 that provided the reload registers.
5290 Also note whether any of the reloads wants a consecutive group of regs.
5291 If so, record the maximum size of the group desired and what
5292 register class contains all the groups needed by this insn. */
5294 for (j = 0; j < n_reloads; j++)
5296 reload_order[j] = j;
5297 reload_spill_index[j] = -1;
5299 if (rld[j].nregs > 1)
5301 max_group_size = MAX (rld[j].nregs, max_group_size);
5303 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5306 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5310 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5312 /* If -O, try first with inheritance, then turning it off.
5313 If not -O, don't do inheritance.
5314 Using inheritance when not optimizing leads to paradoxes
5315 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5316 because one side of the comparison might be inherited. */
5318 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5320 choose_reload_regs_init (chain, save_reload_reg_rtx);
5322 /* Process the reloads in order of preference just found.
5323 Beyond this point, subregs can be found in reload_reg_rtx.
5325 This used to look for an existing reloaded home for all of the
5326 reloads, and only then perform any new reloads. But that could lose
5327 if the reloads were done out of reg-class order because a later
5328 reload with a looser constraint might have an old home in a register
5329 needed by an earlier reload with a tighter constraint.
5331 To solve this, we make two passes over the reloads, in the order
5332 described above. In the first pass we try to inherit a reload
5333 from a previous insn. If there is a later reload that needs a
5334 class that is a proper subset of the class being processed, we must
5335 also allocate a spill register during the first pass.
5337 Then make a second pass over the reloads to allocate any reloads
5338 that haven't been given registers yet. */
5340 for (j = 0; j < n_reloads; j++)
5342 int r = reload_order[j];
5343 rtx search_equiv = NULL_RTX;
5345 /* Ignore reloads that got marked inoperative. */
5346 if (rld[r].out == 0 && rld[r].in == 0
5347 && ! rld[r].secondary_p)
5350 /* If find_reloads chose to use reload_in or reload_out as a reload
5351 register, we don't need to chose one. Otherwise, try even if it
5352 found one since we might save an insn if we find the value lying
5354 Try also when reload_in is a pseudo without a hard reg. */
5355 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5356 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5357 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5358 && !MEM_P (rld[r].in)
5359 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5362 #if 0 /* No longer needed for correct operation.
5363 It might give better code, or might not; worth an experiment? */
5364 /* If this is an optional reload, we can't inherit from earlier insns
5365 until we are sure that any non-optional reloads have been allocated.
5366 The following code takes advantage of the fact that optional reloads
5367 are at the end of reload_order. */
5368 if (rld[r].optional != 0)
5369 for (i = 0; i < j; i++)
5370 if ((rld[reload_order[i]].out != 0
5371 || rld[reload_order[i]].in != 0
5372 || rld[reload_order[i]].secondary_p)
5373 && ! rld[reload_order[i]].optional
5374 && rld[reload_order[i]].reg_rtx == 0)
5375 allocate_reload_reg (chain, reload_order[i], 0);
5378 /* First see if this pseudo is already available as reloaded
5379 for a previous insn. We cannot try to inherit for reloads
5380 that are smaller than the maximum number of registers needed
5381 for groups unless the register we would allocate cannot be used
5384 We could check here to see if this is a secondary reload for
5385 an object that is already in a register of the desired class.
5386 This would avoid the need for the secondary reload register.
5387 But this is complex because we can't easily determine what
5388 objects might want to be loaded via this reload. So let a
5389 register be allocated here. In `emit_reload_insns' we suppress
5390 one of the loads in the case described above. */
5396 enum machine_mode mode = VOIDmode;
5400 else if (REG_P (rld[r].in))
5402 regno = REGNO (rld[r].in);
5403 mode = GET_MODE (rld[r].in);
5405 else if (REG_P (rld[r].in_reg))
5407 regno = REGNO (rld[r].in_reg);
5408 mode = GET_MODE (rld[r].in_reg);
5410 else if (GET_CODE (rld[r].in_reg) == SUBREG
5411 && REG_P (SUBREG_REG (rld[r].in_reg)))
5413 byte = SUBREG_BYTE (rld[r].in_reg);
5414 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5415 if (regno < FIRST_PSEUDO_REGISTER)
5416 regno = subreg_regno (rld[r].in_reg);
5417 mode = GET_MODE (rld[r].in_reg);
5420 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5421 || GET_CODE (rld[r].in_reg) == PRE_DEC
5422 || GET_CODE (rld[r].in_reg) == POST_INC
5423 || GET_CODE (rld[r].in_reg) == POST_DEC)
5424 && REG_P (XEXP (rld[r].in_reg, 0)))
5426 regno = REGNO (XEXP (rld[r].in_reg, 0));
5427 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5428 rld[r].out = rld[r].in;
5432 /* This won't work, since REGNO can be a pseudo reg number.
5433 Also, it takes much more hair to keep track of all the things
5434 that can invalidate an inherited reload of part of a pseudoreg. */
5435 else if (GET_CODE (rld[r].in) == SUBREG
5436 && REG_P (SUBREG_REG (rld[r].in)))
5437 regno = subreg_regno (rld[r].in);
5440 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5442 enum reg_class class = rld[r].class, last_class;
5443 rtx last_reg = reg_last_reload_reg[regno];
5444 enum machine_mode need_mode;
5446 i = REGNO (last_reg);
5447 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5448 last_class = REGNO_REG_CLASS (i);
5454 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5455 + byte * BITS_PER_UNIT,
5456 GET_MODE_CLASS (mode));
5458 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5459 >= GET_MODE_SIZE (need_mode))
5460 #ifdef CANNOT_CHANGE_MODE_CLASS
5461 /* Verify that the register in "i" can be obtained
5463 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5464 GET_MODE (last_reg),
5467 && reg_reloaded_contents[i] == regno
5468 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5469 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5470 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5471 /* Even if we can't use this register as a reload
5472 register, we might use it for reload_override_in,
5473 if copying it to the desired class is cheap
5475 || ((REGISTER_MOVE_COST (mode, last_class, class)
5476 < MEMORY_MOVE_COST (mode, class, 1))
5477 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5478 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5482 #ifdef SECONDARY_MEMORY_NEEDED
5483 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5488 && (rld[r].nregs == max_group_size
5489 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5491 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5492 rld[r].when_needed, rld[r].in,
5495 /* If a group is needed, verify that all the subsequent
5496 registers still have their values intact. */
5497 int nr = hard_regno_nregs[i][rld[r].mode];
5500 for (k = 1; k < nr; k++)
5501 if (reg_reloaded_contents[i + k] != regno
5502 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5510 last_reg = (GET_MODE (last_reg) == mode
5511 ? last_reg : gen_rtx_REG (mode, i));
5514 for (k = 0; k < nr; k++)
5515 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5518 /* We found a register that contains the
5519 value we need. If this register is the
5520 same as an `earlyclobber' operand of the
5521 current insn, just mark it as a place to
5522 reload from since we can't use it as the
5523 reload register itself. */
5525 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5526 if (reg_overlap_mentioned_for_reload_p
5527 (reg_last_reload_reg[regno],
5528 reload_earlyclobbers[i1]))
5531 if (i1 != n_earlyclobbers
5532 || ! (free_for_value_p (i, rld[r].mode,
5534 rld[r].when_needed, rld[r].in,
5536 /* Don't use it if we'd clobber a pseudo reg. */
5537 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5539 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5540 /* Don't clobber the frame pointer. */
5541 || (i == HARD_FRAME_POINTER_REGNUM
5542 && frame_pointer_needed
5544 /* Don't really use the inherited spill reg
5545 if we need it wider than we've got it. */
5546 || (GET_MODE_SIZE (rld[r].mode)
5547 > GET_MODE_SIZE (mode))
5550 /* If find_reloads chose reload_out as reload
5551 register, stay with it - that leaves the
5552 inherited register for subsequent reloads. */
5553 || (rld[r].out && rld[r].reg_rtx
5554 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5556 if (! rld[r].optional)
5558 reload_override_in[r] = last_reg;
5559 reload_inheritance_insn[r]
5560 = reg_reloaded_insn[i];
5566 /* We can use this as a reload reg. */
5567 /* Mark the register as in use for this part of
5569 mark_reload_reg_in_use (i,
5573 rld[r].reg_rtx = last_reg;
5574 reload_inherited[r] = 1;
5575 reload_inheritance_insn[r]
5576 = reg_reloaded_insn[i];
5577 reload_spill_index[r] = i;
5578 for (k = 0; k < nr; k++)
5579 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5587 /* Here's another way to see if the value is already lying around. */
5590 && ! reload_inherited[r]
5592 && (CONSTANT_P (rld[r].in)
5593 || GET_CODE (rld[r].in) == PLUS
5594 || REG_P (rld[r].in)
5595 || MEM_P (rld[r].in))
5596 && (rld[r].nregs == max_group_size
5597 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5598 search_equiv = rld[r].in;
5599 /* If this is an output reload from a simple move insn, look
5600 if an equivalence for the input is available. */
5601 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5603 rtx set = single_set (insn);
5606 && rtx_equal_p (rld[r].out, SET_DEST (set))
5607 && CONSTANT_P (SET_SRC (set)))
5608 search_equiv = SET_SRC (set);
5614 = find_equiv_reg (search_equiv, insn, rld[r].class,
5615 -1, NULL, 0, rld[r].mode);
5621 regno = REGNO (equiv);
5624 /* This must be a SUBREG of a hard register.
5625 Make a new REG since this might be used in an
5626 address and not all machines support SUBREGs
5628 gcc_assert (GET_CODE (equiv) == SUBREG);
5629 regno = subreg_regno (equiv);
5630 equiv = gen_rtx_REG (rld[r].mode, regno);
5631 /* If we choose EQUIV as the reload register, but the
5632 loop below decides to cancel the inheritance, we'll
5633 end up reloading EQUIV in rld[r].mode, not the mode
5634 it had originally. That isn't safe when EQUIV isn't
5635 available as a spill register since its value might
5636 still be live at this point. */
5637 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5638 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5643 /* If we found a spill reg, reject it unless it is free
5644 and of the desired class. */
5648 int bad_for_class = 0;
5649 int max_regno = regno + rld[r].nregs;
5651 for (i = regno; i < max_regno; i++)
5653 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5655 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5660 && ! free_for_value_p (regno, rld[r].mode,
5661 rld[r].opnum, rld[r].when_needed,
5662 rld[r].in, rld[r].out, r, 1))
5667 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5670 /* We found a register that contains the value we need.
5671 If this register is the same as an `earlyclobber' operand
5672 of the current insn, just mark it as a place to reload from
5673 since we can't use it as the reload register itself. */
5676 for (i = 0; i < n_earlyclobbers; i++)
5677 if (reg_overlap_mentioned_for_reload_p (equiv,
5678 reload_earlyclobbers[i]))
5680 if (! rld[r].optional)
5681 reload_override_in[r] = equiv;
5686 /* If the equiv register we have found is explicitly clobbered
5687 in the current insn, it depends on the reload type if we
5688 can use it, use it for reload_override_in, or not at all.
5689 In particular, we then can't use EQUIV for a
5690 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5694 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5695 switch (rld[r].when_needed)
5697 case RELOAD_FOR_OTHER_ADDRESS:
5698 case RELOAD_FOR_INPADDR_ADDRESS:
5699 case RELOAD_FOR_INPUT_ADDRESS:
5700 case RELOAD_FOR_OPADDR_ADDR:
5703 case RELOAD_FOR_INPUT:
5704 case RELOAD_FOR_OPERAND_ADDRESS:
5705 if (! rld[r].optional)
5706 reload_override_in[r] = equiv;
5712 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5713 switch (rld[r].when_needed)
5715 case RELOAD_FOR_OTHER_ADDRESS:
5716 case RELOAD_FOR_INPADDR_ADDRESS:
5717 case RELOAD_FOR_INPUT_ADDRESS:
5718 case RELOAD_FOR_OPADDR_ADDR:
5719 case RELOAD_FOR_OPERAND_ADDRESS:
5720 case RELOAD_FOR_INPUT:
5723 if (! rld[r].optional)
5724 reload_override_in[r] = equiv;
5732 /* If we found an equivalent reg, say no code need be generated
5733 to load it, and use it as our reload reg. */
5735 && (regno != HARD_FRAME_POINTER_REGNUM
5736 || !frame_pointer_needed))
5738 int nr = hard_regno_nregs[regno][rld[r].mode];
5740 rld[r].reg_rtx = equiv;
5741 reload_inherited[r] = 1;
5743 /* If reg_reloaded_valid is not set for this register,
5744 there might be a stale spill_reg_store lying around.
5745 We must clear it, since otherwise emit_reload_insns
5746 might delete the store. */
5747 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5748 spill_reg_store[regno] = NULL_RTX;
5749 /* If any of the hard registers in EQUIV are spill
5750 registers, mark them as in use for this insn. */
5751 for (k = 0; k < nr; k++)
5753 i = spill_reg_order[regno + k];
5756 mark_reload_reg_in_use (regno, rld[r].opnum,
5759 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5766 /* If we found a register to use already, or if this is an optional
5767 reload, we are done. */
5768 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5772 /* No longer needed for correct operation. Might or might
5773 not give better code on the average. Want to experiment? */
5775 /* See if there is a later reload that has a class different from our
5776 class that intersects our class or that requires less register
5777 than our reload. If so, we must allocate a register to this
5778 reload now, since that reload might inherit a previous reload
5779 and take the only available register in our class. Don't do this
5780 for optional reloads since they will force all previous reloads
5781 to be allocated. Also don't do this for reloads that have been
5784 for (i = j + 1; i < n_reloads; i++)
5786 int s = reload_order[i];
5788 if ((rld[s].in == 0 && rld[s].out == 0
5789 && ! rld[s].secondary_p)
5793 if ((rld[s].class != rld[r].class
5794 && reg_classes_intersect_p (rld[r].class,
5796 || rld[s].nregs < rld[r].nregs)
5803 allocate_reload_reg (chain, r, j == n_reloads - 1);
5807 /* Now allocate reload registers for anything non-optional that
5808 didn't get one yet. */
5809 for (j = 0; j < n_reloads; j++)
5811 int r = reload_order[j];
5813 /* Ignore reloads that got marked inoperative. */
5814 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5817 /* Skip reloads that already have a register allocated or are
5819 if (rld[r].reg_rtx != 0 || rld[r].optional)
5822 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5826 /* If that loop got all the way, we have won. */
5833 /* Loop around and try without any inheritance. */
5838 /* First undo everything done by the failed attempt
5839 to allocate with inheritance. */
5840 choose_reload_regs_init (chain, save_reload_reg_rtx);
5842 /* Some sanity tests to verify that the reloads found in the first
5843 pass are identical to the ones we have now. */
5844 gcc_assert (chain->n_reloads == n_reloads);
5846 for (i = 0; i < n_reloads; i++)
5848 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5850 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5851 for (j = 0; j < n_spills; j++)
5852 if (spill_regs[j] == chain->rld[i].regno)
5853 if (! set_reload_reg (j, i))
5854 failed_reload (chain->insn, i);
5858 /* If we thought we could inherit a reload, because it seemed that
5859 nothing else wanted the same reload register earlier in the insn,
5860 verify that assumption, now that all reloads have been assigned.
5861 Likewise for reloads where reload_override_in has been set. */
5863 /* If doing expensive optimizations, do one preliminary pass that doesn't
5864 cancel any inheritance, but removes reloads that have been needed only
5865 for reloads that we know can be inherited. */
5866 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5868 for (j = 0; j < n_reloads; j++)
5870 int r = reload_order[j];
5872 if (reload_inherited[r] && rld[r].reg_rtx)
5873 check_reg = rld[r].reg_rtx;
5874 else if (reload_override_in[r]
5875 && (REG_P (reload_override_in[r])
5876 || GET_CODE (reload_override_in[r]) == SUBREG))
5877 check_reg = reload_override_in[r];
5880 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5881 rld[r].opnum, rld[r].when_needed, rld[r].in,
5882 (reload_inherited[r]
5883 ? rld[r].out : const0_rtx),
5888 reload_inherited[r] = 0;
5889 reload_override_in[r] = 0;
5891 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5892 reload_override_in, then we do not need its related
5893 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5894 likewise for other reload types.
5895 We handle this by removing a reload when its only replacement
5896 is mentioned in reload_in of the reload we are going to inherit.
5897 A special case are auto_inc expressions; even if the input is
5898 inherited, we still need the address for the output. We can
5899 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5900 If we succeeded removing some reload and we are doing a preliminary
5901 pass just to remove such reloads, make another pass, since the
5902 removal of one reload might allow us to inherit another one. */
5904 && rld[r].out != rld[r].in
5905 && remove_address_replacements (rld[r].in) && pass)
5910 /* Now that reload_override_in is known valid,
5911 actually override reload_in. */
5912 for (j = 0; j < n_reloads; j++)
5913 if (reload_override_in[j])
5914 rld[j].in = reload_override_in[j];
5916 /* If this reload won't be done because it has been canceled or is
5917 optional and not inherited, clear reload_reg_rtx so other
5918 routines (such as subst_reloads) don't get confused. */
5919 for (j = 0; j < n_reloads; j++)
5920 if (rld[j].reg_rtx != 0
5921 && ((rld[j].optional && ! reload_inherited[j])
5922 || (rld[j].in == 0 && rld[j].out == 0
5923 && ! rld[j].secondary_p)))
5925 int regno = true_regnum (rld[j].reg_rtx);
5927 if (spill_reg_order[regno] >= 0)
5928 clear_reload_reg_in_use (regno, rld[j].opnum,
5929 rld[j].when_needed, rld[j].mode);
5931 reload_spill_index[j] = -1;
5934 /* Record which pseudos and which spill regs have output reloads. */
5935 for (j = 0; j < n_reloads; j++)
5937 int r = reload_order[j];
5939 i = reload_spill_index[r];
5941 /* I is nonneg if this reload uses a register.
5942 If rld[r].reg_rtx is 0, this is an optional reload
5943 that we opted to ignore. */
5944 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5945 && rld[r].reg_rtx != 0)
5947 int nregno = REGNO (rld[r].out_reg);
5950 if (nregno < FIRST_PSEUDO_REGISTER)
5951 nr = hard_regno_nregs[nregno][rld[r].mode];
5954 reg_has_output_reload[nregno + nr] = 1;
5958 nr = hard_regno_nregs[i][rld[r].mode];
5960 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5963 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5964 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5965 || rld[r].when_needed == RELOAD_FOR_INSN);
5970 /* Deallocate the reload register for reload R. This is called from
5971 remove_address_replacements. */
5974 deallocate_reload_reg (int r)
5978 if (! rld[r].reg_rtx)
5980 regno = true_regnum (rld[r].reg_rtx);
5982 if (spill_reg_order[regno] >= 0)
5983 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5985 reload_spill_index[r] = -1;
5988 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5989 reloads of the same item for fear that we might not have enough reload
5990 registers. However, normally they will get the same reload register
5991 and hence actually need not be loaded twice.
5993 Here we check for the most common case of this phenomenon: when we have
5994 a number of reloads for the same object, each of which were allocated
5995 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5996 reload, and is not modified in the insn itself. If we find such,
5997 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5998 This will not increase the number of spill registers needed and will
5999 prevent redundant code. */
6002 merge_assigned_reloads (rtx insn)
6006 /* Scan all the reloads looking for ones that only load values and
6007 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6008 assigned and not modified by INSN. */
6010 for (i = 0; i < n_reloads; i++)
6012 int conflicting_input = 0;
6013 int max_input_address_opnum = -1;
6014 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6016 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6017 || rld[i].out != 0 || rld[i].reg_rtx == 0
6018 || reg_set_p (rld[i].reg_rtx, insn))
6021 /* Look at all other reloads. Ensure that the only use of this
6022 reload_reg_rtx is in a reload that just loads the same value
6023 as we do. Note that any secondary reloads must be of the identical
6024 class since the values, modes, and result registers are the
6025 same, so we need not do anything with any secondary reloads. */
6027 for (j = 0; j < n_reloads; j++)
6029 if (i == j || rld[j].reg_rtx == 0
6030 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6034 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6035 && rld[j].opnum > max_input_address_opnum)
6036 max_input_address_opnum = rld[j].opnum;
6038 /* If the reload regs aren't exactly the same (e.g, different modes)
6039 or if the values are different, we can't merge this reload.
6040 But if it is an input reload, we might still merge
6041 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6043 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6044 || rld[j].out != 0 || rld[j].in == 0
6045 || ! rtx_equal_p (rld[i].in, rld[j].in))
6047 if (rld[j].when_needed != RELOAD_FOR_INPUT
6048 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6049 || rld[i].opnum > rld[j].opnum)
6050 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6052 conflicting_input = 1;
6053 if (min_conflicting_input_opnum > rld[j].opnum)
6054 min_conflicting_input_opnum = rld[j].opnum;
6058 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6059 we, in fact, found any matching reloads. */
6062 && max_input_address_opnum <= min_conflicting_input_opnum)
6064 for (j = 0; j < n_reloads; j++)
6065 if (i != j && rld[j].reg_rtx != 0
6066 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6067 && (! conflicting_input
6068 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6069 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6071 rld[i].when_needed = RELOAD_OTHER;
6073 reload_spill_index[j] = -1;
6074 transfer_replacements (i, j);
6077 /* If this is now RELOAD_OTHER, look for any reloads that load
6078 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6079 if they were for inputs, RELOAD_OTHER for outputs. Note that
6080 this test is equivalent to looking for reloads for this operand
6082 /* We must take special care when there are two or more reloads to
6083 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6084 same value or a part of it; we must not change its type if there
6085 is a conflicting input. */
6087 if (rld[i].when_needed == RELOAD_OTHER)
6088 for (j = 0; j < n_reloads; j++)
6090 && rld[j].when_needed != RELOAD_OTHER
6091 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6092 && (! conflicting_input
6093 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6094 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6095 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6101 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6102 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6103 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6105 /* Check to see if we accidentally converted two
6106 reloads that use the same reload register with
6107 different inputs to the same type. If so, the
6108 resulting code won't work. */
6110 for (k = 0; k < j; k++)
6111 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6112 || rld[k].when_needed != rld[j].when_needed
6113 || !rtx_equal_p (rld[k].reg_rtx,
6115 || rtx_equal_p (rld[k].in,
6122 /* These arrays are filled by emit_reload_insns and its subroutines. */
6123 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6124 static rtx other_input_address_reload_insns = 0;
6125 static rtx other_input_reload_insns = 0;
6126 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6127 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6128 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6129 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6130 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6131 static rtx operand_reload_insns = 0;
6132 static rtx other_operand_reload_insns = 0;
6133 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6135 /* Values to be put in spill_reg_store are put here first. */
6136 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6137 static HARD_REG_SET reg_reloaded_died;
6139 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6140 has the number J. OLD contains the value to be used as input. */
6143 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6146 rtx insn = chain->insn;
6147 rtx reloadreg = rl->reg_rtx;
6148 rtx oldequiv_reg = 0;
6151 enum machine_mode mode;
6154 /* Determine the mode to reload in.
6155 This is very tricky because we have three to choose from.
6156 There is the mode the insn operand wants (rl->inmode).
6157 There is the mode of the reload register RELOADREG.
6158 There is the intrinsic mode of the operand, which we could find
6159 by stripping some SUBREGs.
6160 It turns out that RELOADREG's mode is irrelevant:
6161 we can change that arbitrarily.
6163 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6164 then the reload reg may not support QImode moves, so use SImode.
6165 If foo is in memory due to spilling a pseudo reg, this is safe,
6166 because the QImode value is in the least significant part of a
6167 slot big enough for a SImode. If foo is some other sort of
6168 memory reference, then it is impossible to reload this case,
6169 so previous passes had better make sure this never happens.
6171 Then consider a one-word union which has SImode and one of its
6172 members is a float, being fetched as (SUBREG:SF union:SI).
6173 We must fetch that as SFmode because we could be loading into
6174 a float-only register. In this case OLD's mode is correct.
6176 Consider an immediate integer: it has VOIDmode. Here we need
6177 to get a mode from something else.
6179 In some cases, there is a fourth mode, the operand's
6180 containing mode. If the insn specifies a containing mode for
6181 this operand, it overrides all others.
6183 I am not sure whether the algorithm here is always right,
6184 but it does the right things in those cases. */
6186 mode = GET_MODE (old);
6187 if (mode == VOIDmode)
6190 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6191 /* If we need a secondary register for this operation, see if
6192 the value is already in a register in that class. Don't
6193 do this if the secondary register will be used as a scratch
6196 if (rl->secondary_in_reload >= 0
6197 && rl->secondary_in_icode == CODE_FOR_nothing
6200 = find_equiv_reg (old, insn,
6201 rld[rl->secondary_in_reload].class,
6205 /* If reloading from memory, see if there is a register
6206 that already holds the same value. If so, reload from there.
6207 We can pass 0 as the reload_reg_p argument because
6208 any other reload has either already been emitted,
6209 in which case find_equiv_reg will see the reload-insn,
6210 or has yet to be emitted, in which case it doesn't matter
6211 because we will use this equiv reg right away. */
6213 if (oldequiv == 0 && optimize
6216 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6217 && reg_renumber[REGNO (old)] < 0)))
6218 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6222 unsigned int regno = true_regnum (oldequiv);
6224 /* Don't use OLDEQUIV if any other reload changes it at an
6225 earlier stage of this insn or at this stage. */
6226 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6227 rl->in, const0_rtx, j, 0))
6230 /* If it is no cheaper to copy from OLDEQUIV into the
6231 reload register than it would be to move from memory,
6232 don't use it. Likewise, if we need a secondary register
6236 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6237 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6239 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6240 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6241 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6245 #ifdef SECONDARY_MEMORY_NEEDED
6246 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6254 /* delete_output_reload is only invoked properly if old contains
6255 the original pseudo register. Since this is replaced with a
6256 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6257 find the pseudo in RELOAD_IN_REG. */
6259 && reload_override_in[j]
6260 && REG_P (rl->in_reg))
6267 else if (REG_P (oldequiv))
6268 oldequiv_reg = oldequiv;
6269 else if (GET_CODE (oldequiv) == SUBREG)
6270 oldequiv_reg = SUBREG_REG (oldequiv);
6272 /* If we are reloading from a register that was recently stored in
6273 with an output-reload, see if we can prove there was
6274 actually no need to store the old value in it. */
6276 if (optimize && REG_P (oldequiv)
6277 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6278 && spill_reg_store[REGNO (oldequiv)]
6280 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6281 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6283 delete_output_reload (insn, j, REGNO (oldequiv));
6285 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6286 then load RELOADREG from OLDEQUIV. Note that we cannot use
6287 gen_lowpart_common since it can do the wrong thing when
6288 RELOADREG has a multi-word mode. Note that RELOADREG
6289 must always be a REG here. */
6291 if (GET_MODE (reloadreg) != mode)
6292 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6293 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6294 oldequiv = SUBREG_REG (oldequiv);
6295 if (GET_MODE (oldequiv) != VOIDmode
6296 && mode != GET_MODE (oldequiv))
6297 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6299 /* Switch to the right place to emit the reload insns. */
6300 switch (rl->when_needed)
6303 where = &other_input_reload_insns;
6305 case RELOAD_FOR_INPUT:
6306 where = &input_reload_insns[rl->opnum];
6308 case RELOAD_FOR_INPUT_ADDRESS:
6309 where = &input_address_reload_insns[rl->opnum];
6311 case RELOAD_FOR_INPADDR_ADDRESS:
6312 where = &inpaddr_address_reload_insns[rl->opnum];
6314 case RELOAD_FOR_OUTPUT_ADDRESS:
6315 where = &output_address_reload_insns[rl->opnum];
6317 case RELOAD_FOR_OUTADDR_ADDRESS:
6318 where = &outaddr_address_reload_insns[rl->opnum];
6320 case RELOAD_FOR_OPERAND_ADDRESS:
6321 where = &operand_reload_insns;
6323 case RELOAD_FOR_OPADDR_ADDR:
6324 where = &other_operand_reload_insns;
6326 case RELOAD_FOR_OTHER_ADDRESS:
6327 where = &other_input_address_reload_insns;
6333 push_to_sequence (*where);
6335 /* Auto-increment addresses must be reloaded in a special way. */
6336 if (rl->out && ! rl->out_reg)
6338 /* We are not going to bother supporting the case where a
6339 incremented register can't be copied directly from
6340 OLDEQUIV since this seems highly unlikely. */
6341 gcc_assert (rl->secondary_in_reload < 0);
6343 if (reload_inherited[j])
6344 oldequiv = reloadreg;
6346 old = XEXP (rl->in_reg, 0);
6348 if (optimize && REG_P (oldequiv)
6349 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6350 && spill_reg_store[REGNO (oldequiv)]
6352 && (dead_or_set_p (insn,
6353 spill_reg_stored_to[REGNO (oldequiv)])
6354 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6356 delete_output_reload (insn, j, REGNO (oldequiv));
6358 /* Prevent normal processing of this reload. */
6360 /* Output a special code sequence for this case. */
6361 new_spill_reg_store[REGNO (reloadreg)]
6362 = inc_for_reload (reloadreg, oldequiv, rl->out,
6366 /* If we are reloading a pseudo-register that was set by the previous
6367 insn, see if we can get rid of that pseudo-register entirely
6368 by redirecting the previous insn into our reload register. */
6370 else if (optimize && REG_P (old)
6371 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6372 && dead_or_set_p (insn, old)
6373 /* This is unsafe if some other reload
6374 uses the same reg first. */
6375 && ! conflicts_with_override (reloadreg)
6376 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6377 rl->when_needed, old, rl->out, j, 0))
6379 rtx temp = PREV_INSN (insn);
6380 while (temp && NOTE_P (temp))
6381 temp = PREV_INSN (temp);
6383 && NONJUMP_INSN_P (temp)
6384 && GET_CODE (PATTERN (temp)) == SET
6385 && SET_DEST (PATTERN (temp)) == old
6386 /* Make sure we can access insn_operand_constraint. */
6387 && asm_noperands (PATTERN (temp)) < 0
6388 /* This is unsafe if operand occurs more than once in current
6389 insn. Perhaps some occurrences aren't reloaded. */
6390 && count_occurrences (PATTERN (insn), old, 0) == 1)
6392 rtx old = SET_DEST (PATTERN (temp));
6393 /* Store into the reload register instead of the pseudo. */
6394 SET_DEST (PATTERN (temp)) = reloadreg;
6396 /* Verify that resulting insn is valid. */
6397 extract_insn (temp);
6398 if (constrain_operands (1))
6400 /* If the previous insn is an output reload, the source is
6401 a reload register, and its spill_reg_store entry will
6402 contain the previous destination. This is now
6404 if (REG_P (SET_SRC (PATTERN (temp)))
6405 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6407 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6408 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6411 /* If these are the only uses of the pseudo reg,
6412 pretend for GDB it lives in the reload reg we used. */
6413 if (REG_N_DEATHS (REGNO (old)) == 1
6414 && REG_N_SETS (REGNO (old)) == 1)
6416 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6417 alter_reg (REGNO (old), -1);
6423 SET_DEST (PATTERN (temp)) = old;
6428 /* We can't do that, so output an insn to load RELOADREG. */
6430 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6431 /* If we have a secondary reload, pick up the secondary register
6432 and icode, if any. If OLDEQUIV and OLD are different or
6433 if this is an in-out reload, recompute whether or not we
6434 still need a secondary register and what the icode should
6435 be. If we still need a secondary register and the class or
6436 icode is different, go back to reloading from OLD if using
6437 OLDEQUIV means that we got the wrong type of register. We
6438 cannot have different class or icode due to an in-out reload
6439 because we don't make such reloads when both the input and
6440 output need secondary reload registers. */
6442 if (! special && rl->secondary_in_reload >= 0)
6444 rtx second_reload_reg = 0;
6445 int secondary_reload = rl->secondary_in_reload;
6446 rtx real_oldequiv = oldequiv;
6449 enum insn_code icode;
6451 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6452 and similarly for OLD.
6453 See comments in get_secondary_reload in reload.c. */
6454 /* If it is a pseudo that cannot be replaced with its
6455 equivalent MEM, we must fall back to reload_in, which
6456 will have all the necessary substitutions registered.
6457 Likewise for a pseudo that can't be replaced with its
6458 equivalent constant.
6460 Take extra care for subregs of such pseudos. Note that
6461 we cannot use reg_equiv_mem in this case because it is
6462 not in the right mode. */
6465 if (GET_CODE (tmp) == SUBREG)
6466 tmp = SUBREG_REG (tmp);
6468 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6469 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6470 || reg_equiv_constant[REGNO (tmp)] != 0))
6472 if (! reg_equiv_mem[REGNO (tmp)]
6473 || num_not_at_initial_offset
6474 || GET_CODE (oldequiv) == SUBREG)
6475 real_oldequiv = rl->in;
6477 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6481 if (GET_CODE (tmp) == SUBREG)
6482 tmp = SUBREG_REG (tmp);
6484 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6485 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6486 || reg_equiv_constant[REGNO (tmp)] != 0))
6488 if (! reg_equiv_mem[REGNO (tmp)]
6489 || num_not_at_initial_offset
6490 || GET_CODE (old) == SUBREG)
6493 real_old = reg_equiv_mem[REGNO (tmp)];
6496 second_reload_reg = rld[secondary_reload].reg_rtx;
6497 icode = rl->secondary_in_icode;
6499 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6500 || (rl->in != 0 && rl->out != 0))
6502 enum reg_class new_class
6503 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6504 mode, real_oldequiv);
6506 if (new_class == NO_REGS)
6507 second_reload_reg = 0;
6510 enum insn_code new_icode;
6511 enum machine_mode new_mode;
6513 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6514 REGNO (second_reload_reg)))
6515 oldequiv = old, real_oldequiv = real_old;
6518 new_icode = reload_in_optab[(int) mode];
6519 if (new_icode != CODE_FOR_nothing
6520 && ((insn_data[(int) new_icode].operand[0].predicate
6521 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6523 || (insn_data[(int) new_icode].operand[1].predicate
6524 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6525 (real_oldequiv, mode)))))
6526 new_icode = CODE_FOR_nothing;
6528 if (new_icode == CODE_FOR_nothing)
6531 new_mode = insn_data[(int) new_icode].operand[2].mode;
6533 if (GET_MODE (second_reload_reg) != new_mode)
6535 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6537 oldequiv = old, real_oldequiv = real_old;
6540 = reload_adjust_reg_for_mode (second_reload_reg,
6547 /* If we still need a secondary reload register, check
6548 to see if it is being used as a scratch or intermediate
6549 register and generate code appropriately. If we need
6550 a scratch register, use REAL_OLDEQUIV since the form of
6551 the insn may depend on the actual address if it is
6554 if (second_reload_reg)
6556 if (icode != CODE_FOR_nothing)
6558 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6559 second_reload_reg));
6564 /* See if we need a scratch register to load the
6565 intermediate register (a tertiary reload). */
6566 enum insn_code tertiary_icode
6567 = rld[secondary_reload].secondary_in_icode;
6569 if (tertiary_icode != CODE_FOR_nothing)
6571 rtx third_reload_reg
6572 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6574 emit_insn ((GEN_FCN (tertiary_icode)
6575 (second_reload_reg, real_oldequiv,
6576 third_reload_reg)));
6579 gen_reload (second_reload_reg, real_oldequiv,
6583 oldequiv = second_reload_reg;
6589 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6591 rtx real_oldequiv = oldequiv;
6593 if ((REG_P (oldequiv)
6594 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6595 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6596 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6597 || (GET_CODE (oldequiv) == SUBREG
6598 && REG_P (SUBREG_REG (oldequiv))
6599 && (REGNO (SUBREG_REG (oldequiv))
6600 >= FIRST_PSEUDO_REGISTER)
6601 && ((reg_equiv_memory_loc
6602 [REGNO (SUBREG_REG (oldequiv))] != 0)
6603 || (reg_equiv_constant
6604 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6605 || (CONSTANT_P (oldequiv)
6606 && (PREFERRED_RELOAD_CLASS (oldequiv,
6607 REGNO_REG_CLASS (REGNO (reloadreg)))
6609 real_oldequiv = rl->in;
6610 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6614 if (flag_non_call_exceptions)
6615 copy_eh_notes (insn, get_insns ());
6617 /* End this sequence. */
6618 *where = get_insns ();
6621 /* Update reload_override_in so that delete_address_reloads_1
6622 can see the actual register usage. */
6624 reload_override_in[j] = oldequiv;
6627 /* Generate insns to for the output reload RL, which is for the insn described
6628 by CHAIN and has the number J. */
6630 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6633 rtx reloadreg = rl->reg_rtx;
6634 rtx insn = chain->insn;
6637 enum machine_mode mode = GET_MODE (old);
6640 if (rl->when_needed == RELOAD_OTHER)
6643 push_to_sequence (output_reload_insns[rl->opnum]);
6645 /* Determine the mode to reload in.
6646 See comments above (for input reloading). */
6648 if (mode == VOIDmode)
6650 /* VOIDmode should never happen for an output. */
6651 if (asm_noperands (PATTERN (insn)) < 0)
6652 /* It's the compiler's fault. */
6653 fatal_insn ("VOIDmode on an output", insn);
6654 error_for_asm (insn, "output operand is constant in %<asm%>");
6655 /* Prevent crash--use something we know is valid. */
6657 old = gen_rtx_REG (mode, REGNO (reloadreg));
6660 if (GET_MODE (reloadreg) != mode)
6661 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6663 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6665 /* If we need two reload regs, set RELOADREG to the intermediate
6666 one, since it will be stored into OLD. We might need a secondary
6667 register only for an input reload, so check again here. */
6669 if (rl->secondary_out_reload >= 0)
6673 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6674 && reg_equiv_mem[REGNO (old)] != 0)
6675 real_old = reg_equiv_mem[REGNO (old)];
6677 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6681 rtx second_reloadreg = reloadreg;
6682 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6684 /* See if RELOADREG is to be used as a scratch register
6685 or as an intermediate register. */
6686 if (rl->secondary_out_icode != CODE_FOR_nothing)
6688 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6689 (real_old, second_reloadreg, reloadreg)));
6694 /* See if we need both a scratch and intermediate reload
6697 int secondary_reload = rl->secondary_out_reload;
6698 enum insn_code tertiary_icode
6699 = rld[secondary_reload].secondary_out_icode;
6701 if (GET_MODE (reloadreg) != mode)
6702 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6704 if (tertiary_icode != CODE_FOR_nothing)
6707 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6710 /* Copy primary reload reg to secondary reload reg.
6711 (Note that these have been swapped above, then
6712 secondary reload reg to OLD using our insn.) */
6714 /* If REAL_OLD is a paradoxical SUBREG, remove it
6715 and try to put the opposite SUBREG on
6717 if (GET_CODE (real_old) == SUBREG
6718 && (GET_MODE_SIZE (GET_MODE (real_old))
6719 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6720 && 0 != (tem = gen_lowpart_common
6721 (GET_MODE (SUBREG_REG (real_old)),
6723 real_old = SUBREG_REG (real_old), reloadreg = tem;
6725 gen_reload (reloadreg, second_reloadreg,
6726 rl->opnum, rl->when_needed);
6727 emit_insn ((GEN_FCN (tertiary_icode)
6728 (real_old, reloadreg, third_reloadreg)));
6733 /* Copy between the reload regs here and then to
6736 gen_reload (reloadreg, second_reloadreg,
6737 rl->opnum, rl->when_needed);
6743 /* Output the last reload insn. */
6748 /* Don't output the last reload if OLD is not the dest of
6749 INSN and is in the src and is clobbered by INSN. */
6750 if (! flag_expensive_optimizations
6752 || !(set = single_set (insn))
6753 || rtx_equal_p (old, SET_DEST (set))
6754 || !reg_mentioned_p (old, SET_SRC (set))
6755 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6756 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6757 gen_reload (old, reloadreg, rl->opnum,
6761 /* Look at all insns we emitted, just to be safe. */
6762 for (p = get_insns (); p; p = NEXT_INSN (p))
6765 rtx pat = PATTERN (p);
6767 /* If this output reload doesn't come from a spill reg,
6768 clear any memory of reloaded copies of the pseudo reg.
6769 If this output reload comes from a spill reg,
6770 reg_has_output_reload will make this do nothing. */
6771 note_stores (pat, forget_old_reloads_1, NULL);
6773 if (reg_mentioned_p (rl->reg_rtx, pat))
6775 rtx set = single_set (insn);
6776 if (reload_spill_index[j] < 0
6778 && SET_SRC (set) == rl->reg_rtx)
6780 int src = REGNO (SET_SRC (set));
6782 reload_spill_index[j] = src;
6783 SET_HARD_REG_BIT (reg_is_output_reload, src);
6784 if (find_regno_note (insn, REG_DEAD, src))
6785 SET_HARD_REG_BIT (reg_reloaded_died, src);
6787 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6789 int s = rl->secondary_out_reload;
6790 set = single_set (p);
6791 /* If this reload copies only to the secondary reload
6792 register, the secondary reload does the actual
6794 if (s >= 0 && set == NULL_RTX)
6795 /* We can't tell what function the secondary reload
6796 has and where the actual store to the pseudo is
6797 made; leave new_spill_reg_store alone. */
6800 && SET_SRC (set) == rl->reg_rtx
6801 && SET_DEST (set) == rld[s].reg_rtx)
6803 /* Usually the next instruction will be the
6804 secondary reload insn; if we can confirm
6805 that it is, setting new_spill_reg_store to
6806 that insn will allow an extra optimization. */
6807 rtx s_reg = rld[s].reg_rtx;
6808 rtx next = NEXT_INSN (p);
6809 rld[s].out = rl->out;
6810 rld[s].out_reg = rl->out_reg;
6811 set = single_set (next);
6812 if (set && SET_SRC (set) == s_reg
6813 && ! new_spill_reg_store[REGNO (s_reg)])
6815 SET_HARD_REG_BIT (reg_is_output_reload,
6817 new_spill_reg_store[REGNO (s_reg)] = next;
6821 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6826 if (rl->when_needed == RELOAD_OTHER)
6828 emit_insn (other_output_reload_insns[rl->opnum]);
6829 other_output_reload_insns[rl->opnum] = get_insns ();
6832 output_reload_insns[rl->opnum] = get_insns ();
6834 if (flag_non_call_exceptions)
6835 copy_eh_notes (insn, get_insns ());
6840 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6841 and has the number J. */
6843 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6845 rtx insn = chain->insn;
6846 rtx old = (rl->in && MEM_P (rl->in)
6847 ? rl->in_reg : rl->in);
6850 /* AUTO_INC reloads need to be handled even if inherited. We got an
6851 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6852 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6853 && ! rtx_equal_p (rl->reg_rtx, old)
6854 && rl->reg_rtx != 0)
6855 emit_input_reload_insns (chain, rld + j, old, j);
6857 /* When inheriting a wider reload, we have a MEM in rl->in,
6858 e.g. inheriting a SImode output reload for
6859 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6860 if (optimize && reload_inherited[j] && rl->in
6862 && MEM_P (rl->in_reg)
6863 && reload_spill_index[j] >= 0
6864 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6865 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6867 /* If we are reloading a register that was recently stored in with an
6868 output-reload, see if we can prove there was
6869 actually no need to store the old value in it. */
6872 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6873 that there may be multiple uses of the previous output reload.
6874 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6875 && rl->when_needed == RELOAD_FOR_INPUT
6876 && (reload_inherited[j] || reload_override_in[j])
6878 && REG_P (rl->reg_rtx)
6879 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6881 /* There doesn't seem to be any reason to restrict this to pseudos
6882 and doing so loses in the case where we are copying from a
6883 register of the wrong class. */
6884 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6885 >= FIRST_PSEUDO_REGISTER)
6887 /* The insn might have already some references to stackslots
6888 replaced by MEMs, while reload_out_reg still names the
6890 && (dead_or_set_p (insn,
6891 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6892 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6894 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6897 /* Do output reloading for reload RL, which is for the insn described by
6898 CHAIN and has the number J.
6899 ??? At some point we need to support handling output reloads of
6900 JUMP_INSNs or insns that set cc0. */
6902 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6905 rtx insn = chain->insn;
6906 /* If this is an output reload that stores something that is
6907 not loaded in this same reload, see if we can eliminate a previous
6909 rtx pseudo = rl->out_reg;
6914 && ! rtx_equal_p (rl->in_reg, pseudo)
6915 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6916 && reg_last_reload_reg[REGNO (pseudo)])
6918 int pseudo_no = REGNO (pseudo);
6919 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6921 /* We don't need to test full validity of last_regno for
6922 inherit here; we only want to know if the store actually
6923 matches the pseudo. */
6924 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6925 && reg_reloaded_contents[last_regno] == pseudo_no
6926 && spill_reg_store[last_regno]
6927 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6928 delete_output_reload (insn, j, last_regno);
6933 || rl->reg_rtx == old
6934 || rl->reg_rtx == 0)
6937 /* An output operand that dies right away does need a reload,
6938 but need not be copied from it. Show the new location in the
6940 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6941 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6943 XEXP (note, 0) = rl->reg_rtx;
6946 /* Likewise for a SUBREG of an operand that dies. */
6947 else if (GET_CODE (old) == SUBREG
6948 && REG_P (SUBREG_REG (old))
6949 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6952 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6956 else if (GET_CODE (old) == SCRATCH)
6957 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6958 but we don't want to make an output reload. */
6961 /* If is a JUMP_INSN, we can't support output reloads yet. */
6962 gcc_assert (!JUMP_P (insn));
6964 emit_output_reload_insns (chain, rld + j, j);
6967 /* Reload number R reloads from or to a group of hard registers starting at
6968 register REGNO. Return true if it can be treated for inheritance purposes
6969 like a group of reloads, each one reloading a single hard register.
6970 The caller has already checked that the spill register and REGNO use
6971 the same number of registers to store the reload value. */
6974 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6976 #ifdef CANNOT_CHANGE_MODE_CLASS
6977 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6978 GET_MODE (rld[r].reg_rtx),
6979 reg_raw_mode[reload_spill_index[r]])
6980 && !REG_CANNOT_CHANGE_MODE_P (regno,
6981 GET_MODE (rld[r].reg_rtx),
6982 reg_raw_mode[regno]));
6988 /* Output insns to reload values in and out of the chosen reload regs. */
6991 emit_reload_insns (struct insn_chain *chain)
6993 rtx insn = chain->insn;
6997 CLEAR_HARD_REG_SET (reg_reloaded_died);
6999 for (j = 0; j < reload_n_operands; j++)
7000 input_reload_insns[j] = input_address_reload_insns[j]
7001 = inpaddr_address_reload_insns[j]
7002 = output_reload_insns[j] = output_address_reload_insns[j]
7003 = outaddr_address_reload_insns[j]
7004 = other_output_reload_insns[j] = 0;
7005 other_input_address_reload_insns = 0;
7006 other_input_reload_insns = 0;
7007 operand_reload_insns = 0;
7008 other_operand_reload_insns = 0;
7010 /* Dump reloads into the dump file. */
7013 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7014 debug_reload_to_stream (dump_file);
7017 /* Now output the instructions to copy the data into and out of the
7018 reload registers. Do these in the order that the reloads were reported,
7019 since reloads of base and index registers precede reloads of operands
7020 and the operands may need the base and index registers reloaded. */
7022 for (j = 0; j < n_reloads; j++)
7025 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7026 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7028 do_input_reload (chain, rld + j, j);
7029 do_output_reload (chain, rld + j, j);
7032 /* Now write all the insns we made for reloads in the order expected by
7033 the allocation functions. Prior to the insn being reloaded, we write
7034 the following reloads:
7036 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7038 RELOAD_OTHER reloads.
7040 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7041 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7042 RELOAD_FOR_INPUT reload for the operand.
7044 RELOAD_FOR_OPADDR_ADDRS reloads.
7046 RELOAD_FOR_OPERAND_ADDRESS reloads.
7048 After the insn being reloaded, we write the following:
7050 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7051 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7052 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7053 reloads for the operand. The RELOAD_OTHER output reloads are
7054 output in descending order by reload number. */
7056 emit_insn_before (other_input_address_reload_insns, insn);
7057 emit_insn_before (other_input_reload_insns, insn);
7059 for (j = 0; j < reload_n_operands; j++)
7061 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7062 emit_insn_before (input_address_reload_insns[j], insn);
7063 emit_insn_before (input_reload_insns[j], insn);
7066 emit_insn_before (other_operand_reload_insns, insn);
7067 emit_insn_before (operand_reload_insns, insn);
7069 for (j = 0; j < reload_n_operands; j++)
7071 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7072 x = emit_insn_after (output_address_reload_insns[j], x);
7073 x = emit_insn_after (output_reload_insns[j], x);
7074 emit_insn_after (other_output_reload_insns[j], x);
7077 /* For all the spill regs newly reloaded in this instruction,
7078 record what they were reloaded from, so subsequent instructions
7079 can inherit the reloads.
7081 Update spill_reg_store for the reloads of this insn.
7082 Copy the elements that were updated in the loop above. */
7084 for (j = 0; j < n_reloads; j++)
7086 int r = reload_order[j];
7087 int i = reload_spill_index[r];
7089 /* If this is a non-inherited input reload from a pseudo, we must
7090 clear any memory of a previous store to the same pseudo. Only do
7091 something if there will not be an output reload for the pseudo
7093 if (rld[r].in_reg != 0
7094 && ! (reload_inherited[r] || reload_override_in[r]))
7096 rtx reg = rld[r].in_reg;
7098 if (GET_CODE (reg) == SUBREG)
7099 reg = SUBREG_REG (reg);
7102 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7103 && ! reg_has_output_reload[REGNO (reg)])
7105 int nregno = REGNO (reg);
7107 if (reg_last_reload_reg[nregno])
7109 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7111 if (reg_reloaded_contents[last_regno] == nregno)
7112 spill_reg_store[last_regno] = 0;
7117 /* I is nonneg if this reload used a register.
7118 If rld[r].reg_rtx is 0, this is an optional reload
7119 that we opted to ignore. */
7121 if (i >= 0 && rld[r].reg_rtx != 0)
7123 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7125 int part_reaches_end = 0;
7126 int all_reaches_end = 1;
7128 /* For a multi register reload, we need to check if all or part
7129 of the value lives to the end. */
7130 for (k = 0; k < nr; k++)
7132 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7133 rld[r].when_needed))
7134 part_reaches_end = 1;
7136 all_reaches_end = 0;
7139 /* Ignore reloads that don't reach the end of the insn in
7141 if (all_reaches_end)
7143 /* First, clear out memory of what used to be in this spill reg.
7144 If consecutive registers are used, clear them all. */
7146 for (k = 0; k < nr; k++)
7148 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7149 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7152 /* Maybe the spill reg contains a copy of reload_out. */
7154 && (REG_P (rld[r].out)
7158 || REG_P (rld[r].out_reg)))
7160 rtx out = (REG_P (rld[r].out)
7164 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7165 int nregno = REGNO (out);
7166 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7167 : hard_regno_nregs[nregno]
7168 [GET_MODE (rld[r].reg_rtx)]);
7171 spill_reg_store[i] = new_spill_reg_store[i];
7172 spill_reg_stored_to[i] = out;
7173 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7175 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7177 && inherit_piecemeal_p (r, nregno));
7179 /* If NREGNO is a hard register, it may occupy more than
7180 one register. If it does, say what is in the
7181 rest of the registers assuming that both registers
7182 agree on how many words the object takes. If not,
7183 invalidate the subsequent registers. */
7185 if (nregno < FIRST_PSEUDO_REGISTER)
7186 for (k = 1; k < nnr; k++)
7187 reg_last_reload_reg[nregno + k]
7189 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7192 /* Now do the inverse operation. */
7193 for (k = 0; k < nr; k++)
7195 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7196 reg_reloaded_contents[i + k]
7197 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7200 reg_reloaded_insn[i + k] = insn;
7201 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7202 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7203 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7207 /* Maybe the spill reg contains a copy of reload_in. Only do
7208 something if there will not be an output reload for
7209 the register being reloaded. */
7210 else if (rld[r].out_reg == 0
7212 && ((REG_P (rld[r].in)
7213 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7214 && ! reg_has_output_reload[REGNO (rld[r].in)])
7215 || (REG_P (rld[r].in_reg)
7216 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7217 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7224 if (REG_P (rld[r].in)
7225 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7227 else if (REG_P (rld[r].in_reg))
7230 in = XEXP (rld[r].in_reg, 0);
7231 nregno = REGNO (in);
7233 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7234 : hard_regno_nregs[nregno]
7235 [GET_MODE (rld[r].reg_rtx)]);
7237 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7239 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7241 && inherit_piecemeal_p (r, nregno));
7243 if (nregno < FIRST_PSEUDO_REGISTER)
7244 for (k = 1; k < nnr; k++)
7245 reg_last_reload_reg[nregno + k]
7247 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7250 /* Unless we inherited this reload, show we haven't
7251 recently done a store.
7252 Previous stores of inherited auto_inc expressions
7253 also have to be discarded. */
7254 if (! reload_inherited[r]
7255 || (rld[r].out && ! rld[r].out_reg))
7256 spill_reg_store[i] = 0;
7258 for (k = 0; k < nr; k++)
7260 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7261 reg_reloaded_contents[i + k]
7262 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7265 reg_reloaded_insn[i + k] = insn;
7266 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7267 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7268 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7273 /* However, if part of the reload reaches the end, then we must
7274 invalidate the old info for the part that survives to the end. */
7275 else if (part_reaches_end)
7277 for (k = 0; k < nr; k++)
7278 if (reload_reg_reaches_end_p (i + k,
7280 rld[r].when_needed))
7281 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7285 /* The following if-statement was #if 0'd in 1.34 (or before...).
7286 It's reenabled in 1.35 because supposedly nothing else
7287 deals with this problem. */
7289 /* If a register gets output-reloaded from a non-spill register,
7290 that invalidates any previous reloaded copy of it.
7291 But forget_old_reloads_1 won't get to see it, because
7292 it thinks only about the original insn. So invalidate it here. */
7293 if (i < 0 && rld[r].out != 0
7294 && (REG_P (rld[r].out)
7295 || (MEM_P (rld[r].out)
7296 && REG_P (rld[r].out_reg))))
7298 rtx out = (REG_P (rld[r].out)
7299 ? rld[r].out : rld[r].out_reg);
7300 int nregno = REGNO (out);
7301 if (nregno >= FIRST_PSEUDO_REGISTER)
7303 rtx src_reg, store_insn = NULL_RTX;
7305 reg_last_reload_reg[nregno] = 0;
7307 /* If we can find a hard register that is stored, record
7308 the storing insn so that we may delete this insn with
7309 delete_output_reload. */
7310 src_reg = rld[r].reg_rtx;
7312 /* If this is an optional reload, try to find the source reg
7313 from an input reload. */
7316 rtx set = single_set (insn);
7317 if (set && SET_DEST (set) == rld[r].out)
7321 src_reg = SET_SRC (set);
7323 for (k = 0; k < n_reloads; k++)
7325 if (rld[k].in == src_reg)
7327 src_reg = rld[k].reg_rtx;
7334 store_insn = new_spill_reg_store[REGNO (src_reg)];
7335 if (src_reg && REG_P (src_reg)
7336 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7338 int src_regno = REGNO (src_reg);
7339 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7340 /* The place where to find a death note varies with
7341 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7342 necessarily checked exactly in the code that moves
7343 notes, so just check both locations. */
7344 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7345 if (! note && store_insn)
7346 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7349 spill_reg_store[src_regno + nr] = store_insn;
7350 spill_reg_stored_to[src_regno + nr] = out;
7351 reg_reloaded_contents[src_regno + nr] = nregno;
7352 reg_reloaded_insn[src_regno + nr] = store_insn;
7353 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7354 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7355 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7356 GET_MODE (src_reg)))
7357 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7359 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7361 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7363 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7365 reg_last_reload_reg[nregno] = src_reg;
7366 /* We have to set reg_has_output_reload here, or else
7367 forget_old_reloads_1 will clear reg_last_reload_reg
7369 reg_has_output_reload[nregno] = 1;
7374 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7376 while (num_regs-- > 0)
7377 reg_last_reload_reg[nregno + num_regs] = 0;
7381 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7384 /* Emit code to perform a reload from IN (which may be a reload register) to
7385 OUT (which may also be a reload register). IN or OUT is from operand
7386 OPNUM with reload type TYPE.
7388 Returns first insn emitted. */
7391 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7393 rtx last = get_last_insn ();
7396 /* If IN is a paradoxical SUBREG, remove it and try to put the
7397 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7398 if (GET_CODE (in) == SUBREG
7399 && (GET_MODE_SIZE (GET_MODE (in))
7400 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7401 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7402 in = SUBREG_REG (in), out = tem;
7403 else if (GET_CODE (out) == SUBREG
7404 && (GET_MODE_SIZE (GET_MODE (out))
7405 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7406 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7407 out = SUBREG_REG (out), in = tem;
7409 /* How to do this reload can get quite tricky. Normally, we are being
7410 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7411 register that didn't get a hard register. In that case we can just
7412 call emit_move_insn.
7414 We can also be asked to reload a PLUS that adds a register or a MEM to
7415 another register, constant or MEM. This can occur during frame pointer
7416 elimination and while reloading addresses. This case is handled by
7417 trying to emit a single insn to perform the add. If it is not valid,
7418 we use a two insn sequence.
7420 Finally, we could be called to handle an 'o' constraint by putting
7421 an address into a register. In that case, we first try to do this
7422 with a named pattern of "reload_load_address". If no such pattern
7423 exists, we just emit a SET insn and hope for the best (it will normally
7424 be valid on machines that use 'o').
7426 This entire process is made complex because reload will never
7427 process the insns we generate here and so we must ensure that
7428 they will fit their constraints and also by the fact that parts of
7429 IN might be being reloaded separately and replaced with spill registers.
7430 Because of this, we are, in some sense, just guessing the right approach
7431 here. The one listed above seems to work.
7433 ??? At some point, this whole thing needs to be rethought. */
7435 if (GET_CODE (in) == PLUS
7436 && (REG_P (XEXP (in, 0))
7437 || GET_CODE (XEXP (in, 0)) == SUBREG
7438 || MEM_P (XEXP (in, 0)))
7439 && (REG_P (XEXP (in, 1))
7440 || GET_CODE (XEXP (in, 1)) == SUBREG
7441 || CONSTANT_P (XEXP (in, 1))
7442 || MEM_P (XEXP (in, 1))))
7444 /* We need to compute the sum of a register or a MEM and another
7445 register, constant, or MEM, and put it into the reload
7446 register. The best possible way of doing this is if the machine
7447 has a three-operand ADD insn that accepts the required operands.
7449 The simplest approach is to try to generate such an insn and see if it
7450 is recognized and matches its constraints. If so, it can be used.
7452 It might be better not to actually emit the insn unless it is valid,
7453 but we need to pass the insn as an operand to `recog' and
7454 `extract_insn' and it is simpler to emit and then delete the insn if
7455 not valid than to dummy things up. */
7457 rtx op0, op1, tem, insn;
7460 op0 = find_replacement (&XEXP (in, 0));
7461 op1 = find_replacement (&XEXP (in, 1));
7463 /* Since constraint checking is strict, commutativity won't be
7464 checked, so we need to do that here to avoid spurious failure
7465 if the add instruction is two-address and the second operand
7466 of the add is the same as the reload reg, which is frequently
7467 the case. If the insn would be A = B + A, rearrange it so
7468 it will be A = A + B as constrain_operands expects. */
7470 if (REG_P (XEXP (in, 1))
7471 && REGNO (out) == REGNO (XEXP (in, 1)))
7472 tem = op0, op0 = op1, op1 = tem;
7474 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7475 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7477 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7478 code = recog_memoized (insn);
7482 extract_insn (insn);
7483 /* We want constrain operands to treat this insn strictly in
7484 its validity determination, i.e., the way it would after reload
7486 if (constrain_operands (1))
7490 delete_insns_since (last);
7492 /* If that failed, we must use a conservative two-insn sequence.
7494 Use a move to copy one operand into the reload register. Prefer
7495 to reload a constant, MEM or pseudo since the move patterns can
7496 handle an arbitrary operand. If OP1 is not a constant, MEM or
7497 pseudo and OP1 is not a valid operand for an add instruction, then
7500 After reloading one of the operands into the reload register, add
7501 the reload register to the output register.
7503 If there is another way to do this for a specific machine, a
7504 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7507 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7509 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7511 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7512 || (code != CODE_FOR_nothing
7513 && ! ((*insn_data[code].operand[2].predicate)
7514 (op1, insn_data[code].operand[2].mode))))
7515 tem = op0, op0 = op1, op1 = tem;
7517 gen_reload (out, op0, opnum, type);
7519 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7520 This fixes a problem on the 32K where the stack pointer cannot
7521 be used as an operand of an add insn. */
7523 if (rtx_equal_p (op0, op1))
7526 insn = emit_insn (gen_add2_insn (out, op1));
7528 /* If that failed, copy the address register to the reload register.
7529 Then add the constant to the reload register. */
7531 code = recog_memoized (insn);
7535 extract_insn (insn);
7536 /* We want constrain operands to treat this insn strictly in
7537 its validity determination, i.e., the way it would after reload
7539 if (constrain_operands (1))
7541 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7543 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7548 delete_insns_since (last);
7550 gen_reload (out, op1, opnum, type);
7551 insn = emit_insn (gen_add2_insn (out, op0));
7552 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7555 #ifdef SECONDARY_MEMORY_NEEDED
7556 /* If we need a memory location to do the move, do it that way. */
7557 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7558 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7559 && (REG_P (out) || GET_CODE (out) == SUBREG)
7560 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7561 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7562 REGNO_REG_CLASS (reg_or_subregno (out)),
7565 /* Get the memory to use and rewrite both registers to its mode. */
7566 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7568 if (GET_MODE (loc) != GET_MODE (out))
7569 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7571 if (GET_MODE (loc) != GET_MODE (in))
7572 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7574 gen_reload (loc, in, opnum, type);
7575 gen_reload (out, loc, opnum, type);
7579 /* If IN is a simple operand, use gen_move_insn. */
7580 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7581 emit_insn (gen_move_insn (out, in));
7583 #ifdef HAVE_reload_load_address
7584 else if (HAVE_reload_load_address)
7585 emit_insn (gen_reload_load_address (out, in));
7588 /* Otherwise, just write (set OUT IN) and hope for the best. */
7590 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7592 /* Return the first insn emitted.
7593 We can not just return get_last_insn, because there may have
7594 been multiple instructions emitted. Also note that gen_move_insn may
7595 emit more than one insn itself, so we can not assume that there is one
7596 insn emitted per emit_insn_before call. */
7598 return last ? NEXT_INSN (last) : get_insns ();
7601 /* Delete a previously made output-reload whose result we now believe
7602 is not needed. First we double-check.
7604 INSN is the insn now being processed.
7605 LAST_RELOAD_REG is the hard register number for which we want to delete
7606 the last output reload.
7607 J is the reload-number that originally used REG. The caller has made
7608 certain that reload J doesn't use REG any longer for input. */
7611 delete_output_reload (rtx insn, int j, int last_reload_reg)
7613 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7614 rtx reg = spill_reg_stored_to[last_reload_reg];
7617 int n_inherited = 0;
7621 /* It is possible that this reload has been only used to set another reload
7622 we eliminated earlier and thus deleted this instruction too. */
7623 if (INSN_DELETED_P (output_reload_insn))
7626 /* Get the raw pseudo-register referred to. */
7628 while (GET_CODE (reg) == SUBREG)
7629 reg = SUBREG_REG (reg);
7630 substed = reg_equiv_memory_loc[REGNO (reg)];
7632 /* This is unsafe if the operand occurs more often in the current
7633 insn than it is inherited. */
7634 for (k = n_reloads - 1; k >= 0; k--)
7636 rtx reg2 = rld[k].in;
7639 if (MEM_P (reg2) || reload_override_in[k])
7640 reg2 = rld[k].in_reg;
7642 if (rld[k].out && ! rld[k].out_reg)
7643 reg2 = XEXP (rld[k].in_reg, 0);
7645 while (GET_CODE (reg2) == SUBREG)
7646 reg2 = SUBREG_REG (reg2);
7647 if (rtx_equal_p (reg2, reg))
7649 if (reload_inherited[k] || reload_override_in[k] || k == j)
7652 reg2 = rld[k].out_reg;
7655 while (GET_CODE (reg2) == SUBREG)
7656 reg2 = XEXP (reg2, 0);
7657 if (rtx_equal_p (reg2, reg))
7664 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7666 n_occurrences += count_occurrences (PATTERN (insn),
7667 eliminate_regs (substed, 0,
7669 if (n_occurrences > n_inherited)
7672 /* If the pseudo-reg we are reloading is no longer referenced
7673 anywhere between the store into it and here,
7674 and we're within the same basic block, then the value can only
7675 pass through the reload reg and end up here.
7676 Otherwise, give up--return. */
7677 for (i1 = NEXT_INSN (output_reload_insn);
7678 i1 != insn; i1 = NEXT_INSN (i1))
7680 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7682 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7683 && reg_mentioned_p (reg, PATTERN (i1)))
7685 /* If this is USE in front of INSN, we only have to check that
7686 there are no more references than accounted for by inheritance. */
7687 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7689 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7690 i1 = NEXT_INSN (i1);
7692 if (n_occurrences <= n_inherited && i1 == insn)
7698 /* We will be deleting the insn. Remove the spill reg information. */
7699 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7701 spill_reg_store[last_reload_reg + k] = 0;
7702 spill_reg_stored_to[last_reload_reg + k] = 0;
7705 /* The caller has already checked that REG dies or is set in INSN.
7706 It has also checked that we are optimizing, and thus some
7707 inaccuracies in the debugging information are acceptable.
7708 So we could just delete output_reload_insn. But in some cases
7709 we can improve the debugging information without sacrificing
7710 optimization - maybe even improving the code: See if the pseudo
7711 reg has been completely replaced with reload regs. If so, delete
7712 the store insn and forget we had a stack slot for the pseudo. */
7713 if (rld[j].out != rld[j].in
7714 && REG_N_DEATHS (REGNO (reg)) == 1
7715 && REG_N_SETS (REGNO (reg)) == 1
7716 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7717 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7721 /* We know that it was used only between here and the beginning of
7722 the current basic block. (We also know that the last use before
7723 INSN was the output reload we are thinking of deleting, but never
7724 mind that.) Search that range; see if any ref remains. */
7725 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7727 rtx set = single_set (i2);
7729 /* Uses which just store in the pseudo don't count,
7730 since if they are the only uses, they are dead. */
7731 if (set != 0 && SET_DEST (set) == reg)
7736 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7737 && reg_mentioned_p (reg, PATTERN (i2)))
7739 /* Some other ref remains; just delete the output reload we
7741 delete_address_reloads (output_reload_insn, insn);
7742 delete_insn (output_reload_insn);
7747 /* Delete the now-dead stores into this pseudo. Note that this
7748 loop also takes care of deleting output_reload_insn. */
7749 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7751 rtx set = single_set (i2);
7753 if (set != 0 && SET_DEST (set) == reg)
7755 delete_address_reloads (i2, insn);
7763 /* For the debugging info, say the pseudo lives in this reload reg. */
7764 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7765 alter_reg (REGNO (reg), -1);
7769 delete_address_reloads (output_reload_insn, insn);
7770 delete_insn (output_reload_insn);
7774 /* We are going to delete DEAD_INSN. Recursively delete loads of
7775 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7776 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7778 delete_address_reloads (rtx dead_insn, rtx current_insn)
7780 rtx set = single_set (dead_insn);
7781 rtx set2, dst, prev, next;
7784 rtx dst = SET_DEST (set);
7786 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7788 /* If we deleted the store from a reloaded post_{in,de}c expression,
7789 we can delete the matching adds. */
7790 prev = PREV_INSN (dead_insn);
7791 next = NEXT_INSN (dead_insn);
7792 if (! prev || ! next)
7794 set = single_set (next);
7795 set2 = single_set (prev);
7797 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7798 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7799 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7801 dst = SET_DEST (set);
7802 if (! rtx_equal_p (dst, SET_DEST (set2))
7803 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7804 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7805 || (INTVAL (XEXP (SET_SRC (set), 1))
7806 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7808 delete_related_insns (prev);
7809 delete_related_insns (next);
7812 /* Subfunction of delete_address_reloads: process registers found in X. */
7814 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7816 rtx prev, set, dst, i2;
7818 enum rtx_code code = GET_CODE (x);
7822 const char *fmt = GET_RTX_FORMAT (code);
7823 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7826 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7827 else if (fmt[i] == 'E')
7829 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7830 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7837 if (spill_reg_order[REGNO (x)] < 0)
7840 /* Scan backwards for the insn that sets x. This might be a way back due
7842 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7844 code = GET_CODE (prev);
7845 if (code == CODE_LABEL || code == JUMP_INSN)
7849 if (reg_set_p (x, PATTERN (prev)))
7851 if (reg_referenced_p (x, PATTERN (prev)))
7854 if (! prev || INSN_UID (prev) < reload_first_uid)
7856 /* Check that PREV only sets the reload register. */
7857 set = single_set (prev);
7860 dst = SET_DEST (set);
7862 || ! rtx_equal_p (dst, x))
7864 if (! reg_set_p (dst, PATTERN (dead_insn)))
7866 /* Check if DST was used in a later insn -
7867 it might have been inherited. */
7868 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7874 if (reg_referenced_p (dst, PATTERN (i2)))
7876 /* If there is a reference to the register in the current insn,
7877 it might be loaded in a non-inherited reload. If no other
7878 reload uses it, that means the register is set before
7880 if (i2 == current_insn)
7882 for (j = n_reloads - 1; j >= 0; j--)
7883 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7884 || reload_override_in[j] == dst)
7886 for (j = n_reloads - 1; j >= 0; j--)
7887 if (rld[j].in && rld[j].reg_rtx == dst)
7896 /* If DST is still live at CURRENT_INSN, check if it is used for
7897 any reload. Note that even if CURRENT_INSN sets DST, we still
7898 have to check the reloads. */
7899 if (i2 == current_insn)
7901 for (j = n_reloads - 1; j >= 0; j--)
7902 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7903 || reload_override_in[j] == dst)
7905 /* ??? We can't finish the loop here, because dst might be
7906 allocated to a pseudo in this block if no reload in this
7907 block needs any of the classes containing DST - see
7908 spill_hard_reg. There is no easy way to tell this, so we
7909 have to scan till the end of the basic block. */
7911 if (reg_set_p (dst, PATTERN (i2)))
7915 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7916 reg_reloaded_contents[REGNO (dst)] = -1;
7920 /* Output reload-insns to reload VALUE into RELOADREG.
7921 VALUE is an autoincrement or autodecrement RTX whose operand
7922 is a register or memory location;
7923 so reloading involves incrementing that location.
7924 IN is either identical to VALUE, or some cheaper place to reload from.
7926 INC_AMOUNT is the number to increment or decrement by (always positive).
7927 This cannot be deduced from VALUE.
7929 Return the instruction that stores into RELOADREG. */
7932 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7934 /* REG or MEM to be copied and incremented. */
7935 rtx incloc = XEXP (value, 0);
7936 /* Nonzero if increment after copying. */
7937 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7943 rtx real_in = in == value ? XEXP (in, 0) : in;
7945 /* No hard register is equivalent to this register after
7946 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7947 we could inc/dec that register as well (maybe even using it for
7948 the source), but I'm not sure it's worth worrying about. */
7950 reg_last_reload_reg[REGNO (incloc)] = 0;
7952 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7953 inc_amount = -inc_amount;
7955 inc = GEN_INT (inc_amount);
7957 /* If this is post-increment, first copy the location to the reload reg. */
7958 if (post && real_in != reloadreg)
7959 emit_insn (gen_move_insn (reloadreg, real_in));
7963 /* See if we can directly increment INCLOC. Use a method similar to
7964 that in gen_reload. */
7966 last = get_last_insn ();
7967 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7968 gen_rtx_PLUS (GET_MODE (incloc),
7971 code = recog_memoized (add_insn);
7974 extract_insn (add_insn);
7975 if (constrain_operands (1))
7977 /* If this is a pre-increment and we have incremented the value
7978 where it lives, copy the incremented value to RELOADREG to
7979 be used as an address. */
7982 emit_insn (gen_move_insn (reloadreg, incloc));
7987 delete_insns_since (last);
7990 /* If couldn't do the increment directly, must increment in RELOADREG.
7991 The way we do this depends on whether this is pre- or post-increment.
7992 For pre-increment, copy INCLOC to the reload register, increment it
7993 there, then save back. */
7997 if (in != reloadreg)
7998 emit_insn (gen_move_insn (reloadreg, real_in));
7999 emit_insn (gen_add2_insn (reloadreg, inc));
8000 store = emit_insn (gen_move_insn (incloc, reloadreg));
8005 Because this might be a jump insn or a compare, and because RELOADREG
8006 may not be available after the insn in an input reload, we must do
8007 the incrementation before the insn being reloaded for.
8009 We have already copied IN to RELOADREG. Increment the copy in
8010 RELOADREG, save that back, then decrement RELOADREG so it has
8011 the original value. */
8013 emit_insn (gen_add2_insn (reloadreg, inc));
8014 store = emit_insn (gen_move_insn (incloc, reloadreg));
8015 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8023 add_auto_inc_notes (rtx insn, rtx x)
8025 enum rtx_code code = GET_CODE (x);
8029 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8032 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8036 /* Scan all the operand sub-expressions. */
8037 fmt = GET_RTX_FORMAT (code);
8038 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8041 add_auto_inc_notes (insn, XEXP (x, i));
8042 else if (fmt[i] == 'E')
8043 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8044 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8049 /* Copy EH notes from an insn to its reloads. */
8051 copy_eh_notes (rtx insn, rtx x)
8053 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8056 for (; x != 0; x = NEXT_INSN (x))
8058 if (may_trap_p (PATTERN (x)))
8060 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8066 /* This is used by reload pass, that does emit some instructions after
8067 abnormal calls moving basic block end, but in fact it wants to emit
8068 them on the edge. Looks for abnormal call edges, find backward the
8069 proper call and fix the damage.
8071 Similar handle instructions throwing exceptions internally. */
8073 fixup_abnormal_edges (void)
8075 bool inserted = false;
8083 /* Look for cases we are interested in - calls or instructions causing
8085 FOR_EACH_EDGE (e, ei, bb->succs)
8087 if (e->flags & EDGE_ABNORMAL_CALL)
8089 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8090 == (EDGE_ABNORMAL | EDGE_EH))
8093 if (e && !CALL_P (BB_END (bb))
8094 && !can_throw_internal (BB_END (bb)))
8096 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8098 FOR_EACH_EDGE (e, ei, bb->succs)
8099 if (e->flags & EDGE_FALLTHRU)
8101 /* Get past the new insns generated. Allow notes, as the insns may
8102 be already deleted. */
8103 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8104 && !can_throw_internal (insn)
8105 && insn != BB_HEAD (bb))
8106 insn = PREV_INSN (insn);
8107 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8110 insn = NEXT_INSN (insn);
8111 while (insn && insn != stop)
8113 next = NEXT_INSN (insn);
8118 /* Sometimes there's still the return value USE.
8119 If it's placed after a trapping call (i.e. that
8120 call is the last insn anyway), we have no fallthru
8121 edge. Simply delete this use and don't try to insert
8122 on the non-existent edge. */
8123 if (GET_CODE (PATTERN (insn)) != USE)
8125 /* We're not deleting it, we're moving it. */
8126 INSN_DELETED_P (insn) = 0;
8127 PREV_INSN (insn) = NULL_RTX;
8128 NEXT_INSN (insn) = NULL_RTX;
8130 insert_insn_on_edge (insn, e);
8137 /* We've possibly turned single trapping insn into multiple ones. */
8138 if (flag_non_call_exceptions)
8141 blocks = sbitmap_alloc (last_basic_block);
8142 sbitmap_ones (blocks);
8143 find_many_sub_basic_blocks (blocks);
8146 commit_edge_insertions ();
OSDN Git Service
