1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "rtl-error.h"
32 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 struct target_reload default_target_reload;
87 struct target_reload *this_target_reload = &default_target_reload;
90 #define spill_indirect_levels \
91 (this_target_reload->x_spill_indirect_levels)
93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
94 into which reg N has been reloaded (perhaps for a previous insn). */
95 static rtx *reg_last_reload_reg;
97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
98 for an output reload that stores into reg N. */
99 static regset_head reg_has_output_reload;
101 /* Indicates which hard regs are reload-registers for an output reload
102 in the current insn. */
103 static HARD_REG_SET reg_is_output_reload;
105 /* Widest width in which each pseudo reg is referred to (via subreg). */
106 static unsigned int *reg_max_ref_width;
108 /* Vector to remember old contents of reg_renumber before spilling. */
109 static short *reg_old_renumber;
111 /* During reload_as_needed, element N contains the last pseudo regno reloaded
112 into hard register N. If that pseudo reg occupied more than one register,
113 reg_reloaded_contents points to that pseudo for each spill register in
114 use; all of these must remain set for an inheritance to occur. */
115 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
117 /* During reload_as_needed, element N contains the insn for which
118 hard register N was last used. Its contents are significant only
119 when reg_reloaded_valid is set for this register. */
120 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
122 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
123 static HARD_REG_SET reg_reloaded_valid;
124 /* Indicate if the register was dead at the end of the reload.
125 This is only valid if reg_reloaded_contents is set and valid. */
126 static HARD_REG_SET reg_reloaded_dead;
128 /* Indicate whether the register's current value is one that is not
129 safe to retain across a call, even for registers that are normally
130 call-saved. This is only meaningful for members of reg_reloaded_valid. */
131 static HARD_REG_SET reg_reloaded_call_part_clobbered;
133 /* Number of spill-regs so far; number of valid elements of spill_regs. */
136 /* In parallel with spill_regs, contains REG rtx's for those regs.
137 Holds the last rtx used for any given reg, or 0 if it has never
138 been used for spilling yet. This rtx is reused, provided it has
140 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
142 /* In parallel with spill_regs, contains nonzero for a spill reg
143 that was stored after the last time it was used.
144 The precise value is the insn generated to do the store. */
145 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
147 /* This is the register that was stored with spill_reg_store. This is a
148 copy of reload_out / reload_out_reg when the value was stored; if
149 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
150 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
152 /* This table is the inverse mapping of spill_regs:
153 indexed by hard reg number,
154 it contains the position of that reg in spill_regs,
155 or -1 for something that is not in spill_regs.
157 ?!? This is no longer accurate. */
158 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
160 /* This reg set indicates registers that can't be used as spill registers for
161 the currently processed insn. These are the hard registers which are live
162 during the insn, but not allocated to pseudos, as well as fixed
164 static HARD_REG_SET bad_spill_regs;
166 /* These are the hard registers that can't be used as spill register for any
167 insn. This includes registers used for user variables and registers that
168 we can't eliminate. A register that appears in this set also can't be used
169 to retry register allocation. */
170 static HARD_REG_SET bad_spill_regs_global;
172 /* Describes order of use of registers for reloading
173 of spilled pseudo-registers. `n_spills' is the number of
174 elements that are actually valid; new ones are added at the end.
176 Both spill_regs and spill_reg_order are used on two occasions:
177 once during find_reload_regs, where they keep track of the spill registers
178 for a single insn, but also during reload_as_needed where they show all
179 the registers ever used by reload. For the latter case, the information
180 is calculated during finish_spills. */
181 static short spill_regs[FIRST_PSEUDO_REGISTER];
183 /* This vector of reg sets indicates, for each pseudo, which hard registers
184 may not be used for retrying global allocation because the register was
185 formerly spilled from one of them. If we allowed reallocating a pseudo to
186 a register that it was already allocated to, reload might not
188 static HARD_REG_SET *pseudo_previous_regs;
190 /* This vector of reg sets indicates, for each pseudo, which hard
191 registers may not be used for retrying global allocation because they
192 are used as spill registers during one of the insns in which the
194 static HARD_REG_SET *pseudo_forbidden_regs;
196 /* All hard regs that have been used as spill registers for any insn are
197 marked in this set. */
198 static HARD_REG_SET used_spill_regs;
200 /* Index of last register assigned as a spill register. We allocate in
201 a round-robin fashion. */
202 static int last_spill_reg;
204 /* Record the stack slot for each spilled hard register. */
205 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
207 /* Width allocated so far for that stack slot. */
208 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
210 /* Record which pseudos needed to be spilled. */
211 static regset_head spilled_pseudos;
213 /* Record which pseudos changed their allocation in finish_spills. */
214 static regset_head changed_allocation_pseudos;
216 /* Used for communication between order_regs_for_reload and count_pseudo.
217 Used to avoid counting one pseudo twice. */
218 static regset_head pseudos_counted;
220 /* First uid used by insns created by reload in this function.
221 Used in find_equiv_reg. */
222 int reload_first_uid;
224 /* Flag set by local-alloc or global-alloc if anything is live in
225 a call-clobbered reg across calls. */
226 int caller_save_needed;
228 /* Set to 1 while reload_as_needed is operating.
229 Required by some machines to handle any generated moves differently. */
230 int reload_in_progress = 0;
232 /* This obstack is used for allocation of rtl during register elimination.
233 The allocated storage can be freed once find_reloads has processed the
235 static struct obstack reload_obstack;
237 /* Points to the beginning of the reload_obstack. All insn_chain structures
238 are allocated first. */
239 static char *reload_startobj;
241 /* The point after all insn_chain structures. Used to quickly deallocate
242 memory allocated in copy_reloads during calculate_needs_all_insns. */
243 static char *reload_firstobj;
245 /* This points before all local rtl generated by register elimination.
246 Used to quickly free all memory after processing one insn. */
247 static char *reload_insn_firstobj;
249 /* List of insn_chain instructions, one for every insn that reload needs to
251 struct insn_chain *reload_insn_chain;
253 /* TRUE if we potentially left dead insns in the insn stream and want to
254 run DCE immediately after reload, FALSE otherwise. */
255 static bool need_dce;
257 /* List of all insns needing reloads. */
258 static struct insn_chain *insns_need_reload;
260 /* This structure is used to record information about register eliminations.
261 Each array entry describes one possible way of eliminating a register
262 in favor of another. If there is more than one way of eliminating a
263 particular register, the most preferred should be specified first. */
267 int from; /* Register number to be eliminated. */
268 int to; /* Register number used as replacement. */
269 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
270 int can_eliminate; /* Nonzero if this elimination can be done. */
271 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
272 target hook in previous scan over insns
274 HOST_WIDE_INT offset; /* Current offset between the two regs. */
275 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
276 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
277 rtx from_rtx; /* REG rtx for the register to be eliminated.
278 We cannot simply compare the number since
279 we might then spuriously replace a hard
280 register corresponding to a pseudo
281 assigned to the reg to be eliminated. */
282 rtx to_rtx; /* REG rtx for the replacement. */
285 static struct elim_table *reg_eliminate = 0;
287 /* This is an intermediate structure to initialize the table. It has
288 exactly the members provided by ELIMINABLE_REGS. */
289 static const struct elim_table_1
293 } reg_eliminate_1[] =
295 /* If a set of eliminable registers was specified, define the table from it.
296 Otherwise, default to the normal case of the frame pointer being
297 replaced by the stack pointer. */
299 #ifdef ELIMINABLE_REGS
302 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
305 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
307 /* Record the number of pending eliminations that have an offset not equal
308 to their initial offset. If nonzero, we use a new copy of each
309 replacement result in any insns encountered. */
310 int num_not_at_initial_offset;
312 /* Count the number of registers that we may be able to eliminate. */
313 static int num_eliminable;
314 /* And the number of registers that are equivalent to a constant that
315 can be eliminated to frame_pointer / arg_pointer + constant. */
316 static int num_eliminable_invariants;
318 /* For each label, we record the offset of each elimination. If we reach
319 a label by more than one path and an offset differs, we cannot do the
320 elimination. This information is indexed by the difference of the
321 number of the label and the first label number. We can't offset the
322 pointer itself as this can cause problems on machines with segmented
323 memory. The first table is an array of flags that records whether we
324 have yet encountered a label and the second table is an array of arrays,
325 one entry in the latter array for each elimination. */
327 static int first_label_num;
328 static char *offsets_known_at;
329 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
331 VEC(reg_equivs_t,gc) *reg_equivs;
333 /* Stack of addresses where an rtx has been changed. We can undo the
334 changes by popping items off the stack and restoring the original
335 value at each location.
337 We use this simplistic undo capability rather than copy_rtx as copy_rtx
338 will not make a deep copy of a normally sharable rtx, such as
339 (const (plus (symbol_ref) (const_int))). If such an expression appears
340 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
341 rtx expression would be changed. See PR 42431. */
345 DEF_VEC_ALLOC_P(rtx_p,heap);
346 static VEC(rtx_p,heap) *substitute_stack;
348 /* Number of labels in the current function. */
350 static int num_labels;
352 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
353 static void maybe_fix_stack_asms (void);
354 static void copy_reloads (struct insn_chain *);
355 static void calculate_needs_all_insns (int);
356 static int find_reg (struct insn_chain *, int);
357 static void find_reload_regs (struct insn_chain *);
358 static void select_reload_regs (void);
359 static void delete_caller_save_insns (void);
361 static void spill_failure (rtx, enum reg_class);
362 static void count_spilled_pseudo (int, int, int);
363 static void delete_dead_insn (rtx);
364 static void alter_reg (int, int, bool);
365 static void set_label_offsets (rtx, rtx, int);
366 static void check_eliminable_occurrences (rtx);
367 static void elimination_effects (rtx, enum machine_mode);
368 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
369 static int eliminate_regs_in_insn (rtx, int);
370 static void update_eliminable_offsets (void);
371 static void mark_not_eliminable (rtx, const_rtx, void *);
372 static void set_initial_elim_offsets (void);
373 static bool verify_initial_elim_offsets (void);
374 static void set_initial_label_offsets (void);
375 static void set_offsets_for_label (rtx);
376 static void init_eliminable_invariants (rtx, bool);
377 static void init_elim_table (void);
378 static void free_reg_equiv (void);
379 static void update_eliminables (HARD_REG_SET *);
380 static void elimination_costs_in_insn (rtx);
381 static void spill_hard_reg (unsigned int, int);
382 static int finish_spills (int);
383 static void scan_paradoxical_subregs (rtx);
384 static void count_pseudo (int);
385 static void order_regs_for_reload (struct insn_chain *);
386 static void reload_as_needed (int);
387 static void forget_old_reloads_1 (rtx, const_rtx, void *);
388 static void forget_marked_reloads (regset);
389 static int reload_reg_class_lower (const void *, const void *);
390 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
392 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
394 static int reload_reg_free_p (unsigned int, int, enum reload_type);
395 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
397 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
399 static int allocate_reload_reg (struct insn_chain *, int, int);
400 static int conflicts_with_override (rtx);
401 static void failed_reload (rtx, int);
402 static int set_reload_reg (int, int);
403 static void choose_reload_regs_init (struct insn_chain *, rtx *);
404 static void choose_reload_regs (struct insn_chain *);
405 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
407 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
409 static void do_input_reload (struct insn_chain *, struct reload *, int);
410 static void do_output_reload (struct insn_chain *, struct reload *, int);
411 static void emit_reload_insns (struct insn_chain *);
412 static void delete_output_reload (rtx, int, int, rtx);
413 static void delete_address_reloads (rtx, rtx);
414 static void delete_address_reloads_1 (rtx, rtx, rtx);
415 static void inc_for_reload (rtx, rtx, rtx, int);
417 static void add_auto_inc_notes (rtx, rtx);
419 static void substitute (rtx *, const_rtx, rtx);
420 static bool gen_reload_chain_without_interm_reg_p (int, int);
421 static int reloads_conflict (int, int);
422 static rtx gen_reload (rtx, rtx, int, enum reload_type);
423 static rtx emit_insn_if_valid_for_reload (rtx);
425 /* Initialize the reload pass. This is called at the beginning of compilation
426 and may be called again if the target is reinitialized. */
433 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
434 Set spill_indirect_levels to the number of levels such addressing is
435 permitted, zero if it is not permitted at all. */
438 = gen_rtx_MEM (Pmode,
441 LAST_VIRTUAL_REGISTER + 1),
443 spill_indirect_levels = 0;
445 while (memory_address_p (QImode, tem))
447 spill_indirect_levels++;
448 tem = gen_rtx_MEM (Pmode, tem);
451 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
453 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
454 indirect_symref_ok = memory_address_p (QImode, tem);
456 /* See if reg+reg is a valid (and offsettable) address. */
458 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
460 tem = gen_rtx_PLUS (Pmode,
461 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
462 gen_rtx_REG (Pmode, i));
464 /* This way, we make sure that reg+reg is an offsettable address. */
465 tem = plus_constant (tem, 4);
467 if (memory_address_p (QImode, tem))
469 double_reg_address_ok = 1;
474 /* Initialize obstack for our rtl allocation. */
475 gcc_obstack_init (&reload_obstack);
476 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
478 INIT_REG_SET (&spilled_pseudos);
479 INIT_REG_SET (&changed_allocation_pseudos);
480 INIT_REG_SET (&pseudos_counted);
483 /* List of insn chains that are currently unused. */
484 static struct insn_chain *unused_insn_chains = 0;
486 /* Allocate an empty insn_chain structure. */
488 new_insn_chain (void)
490 struct insn_chain *c;
492 if (unused_insn_chains == 0)
494 c = XOBNEW (&reload_obstack, struct insn_chain);
495 INIT_REG_SET (&c->live_throughout);
496 INIT_REG_SET (&c->dead_or_set);
500 c = unused_insn_chains;
501 unused_insn_chains = c->next;
503 c->is_caller_save_insn = 0;
504 c->need_operand_change = 0;
510 /* Small utility function to set all regs in hard reg set TO which are
511 allocated to pseudos in regset FROM. */
514 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
517 reg_set_iterator rsi;
519 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
521 int r = reg_renumber[regno];
525 /* reload_combine uses the information from DF_LIVE_IN,
526 which might still contain registers that have not
527 actually been allocated since they have an
529 gcc_assert (ira_conflicts_p || reload_completed);
532 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
536 /* Replace all pseudos found in LOC with their corresponding
540 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
553 unsigned int regno = REGNO (x);
555 if (regno < FIRST_PSEUDO_REGISTER)
558 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
562 replace_pseudos_in (loc, mem_mode, usage);
566 if (reg_equiv_constant (regno))
567 *loc = reg_equiv_constant (regno);
568 else if (reg_equiv_invariant (regno))
569 *loc = reg_equiv_invariant (regno);
570 else if (reg_equiv_mem (regno))
571 *loc = reg_equiv_mem (regno);
572 else if (reg_equiv_address (regno))
573 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
576 gcc_assert (!REG_P (regno_reg_rtx[regno])
577 || REGNO (regno_reg_rtx[regno]) != regno);
578 *loc = regno_reg_rtx[regno];
583 else if (code == MEM)
585 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
589 /* Process each of our operands recursively. */
590 fmt = GET_RTX_FORMAT (code);
591 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
593 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
594 else if (*fmt == 'E')
595 for (j = 0; j < XVECLEN (x, i); j++)
596 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
599 /* Determine if the current function has an exception receiver block
600 that reaches the exit block via non-exceptional edges */
603 has_nonexceptional_receiver (void)
607 basic_block *tos, *worklist, bb;
609 /* If we're not optimizing, then just err on the safe side. */
613 /* First determine which blocks can reach exit via normal paths. */
614 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
617 bb->flags &= ~BB_REACHABLE;
619 /* Place the exit block on our worklist. */
620 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
621 *tos++ = EXIT_BLOCK_PTR;
623 /* Iterate: find everything reachable from what we've already seen. */
624 while (tos != worklist)
628 FOR_EACH_EDGE (e, ei, bb->preds)
629 if (!(e->flags & EDGE_ABNORMAL))
631 basic_block src = e->src;
633 if (!(src->flags & BB_REACHABLE))
635 src->flags |= BB_REACHABLE;
642 /* Now see if there's a reachable block with an exceptional incoming
645 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
648 /* No exceptional block reached exit unexceptionally. */
652 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
653 zero elements) to MAX_REG_NUM elements.
655 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
657 grow_reg_equivs (void)
659 int old_size = VEC_length (reg_equivs_t, reg_equivs);
660 int max_regno = max_reg_num ();
663 VEC_reserve (reg_equivs_t, gc, reg_equivs, max_regno);
664 for (i = old_size; i < max_regno; i++)
666 VEC_quick_insert (reg_equivs_t, reg_equivs, i, 0);
667 memset (VEC_index (reg_equivs_t, reg_equivs, i), 0, sizeof (reg_equivs_t));
673 /* Global variables used by reload and its subroutines. */
675 /* The current basic block while in calculate_elim_costs_all_insns. */
676 static basic_block elim_bb;
678 /* Set during calculate_needs if an insn needs register elimination. */
679 static int something_needs_elimination;
680 /* Set during calculate_needs if an insn needs an operand changed. */
681 static int something_needs_operands_changed;
682 /* Set by alter_regs if we spilled a register to the stack. */
683 static bool something_was_spilled;
685 /* Nonzero means we couldn't get enough spill regs. */
688 /* Temporary array of pseudo-register number. */
689 static int *temp_pseudo_reg_arr;
691 /* Main entry point for the reload pass.
693 FIRST is the first insn of the function being compiled.
695 GLOBAL nonzero means we were called from global_alloc
696 and should attempt to reallocate any pseudoregs that we
697 displace from hard regs we will use for reloads.
698 If GLOBAL is zero, we do not have enough information to do that,
699 so any pseudo reg that is spilled must go to the stack.
701 Return value is TRUE if reload likely left dead insns in the
702 stream and a DCE pass should be run to elimiante them. Else the
703 return value is FALSE. */
706 reload (rtx first, int global)
710 struct elim_table *ep;
714 /* Make sure even insns with volatile mem refs are recognizable. */
719 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
721 /* Make sure that the last insn in the chain
722 is not something that needs reloading. */
723 emit_note (NOTE_INSN_DELETED);
725 /* Enable find_equiv_reg to distinguish insns made by reload. */
726 reload_first_uid = get_max_uid ();
728 #ifdef SECONDARY_MEMORY_NEEDED
729 /* Initialize the secondary memory table. */
730 clear_secondary_mem ();
733 /* We don't have a stack slot for any spill reg yet. */
734 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
735 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
737 /* Initialize the save area information for caller-save, in case some
741 /* Compute which hard registers are now in use
742 as homes for pseudo registers.
743 This is done here rather than (eg) in global_alloc
744 because this point is reached even if not optimizing. */
745 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
748 /* A function that has a nonlocal label that can reach the exit
749 block via non-exceptional paths must save all call-saved
751 if (cfun->has_nonlocal_label
752 && has_nonexceptional_receiver ())
753 crtl->saves_all_registers = 1;
755 if (crtl->saves_all_registers)
756 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
757 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
758 df_set_regs_ever_live (i, true);
760 /* Find all the pseudo registers that didn't get hard regs
761 but do have known equivalent constants or memory slots.
762 These include parameters (known equivalent to parameter slots)
763 and cse'd or loop-moved constant memory addresses.
765 Record constant equivalents in reg_equiv_constant
766 so they will be substituted by find_reloads.
767 Record memory equivalents in reg_mem_equiv so they can
768 be substituted eventually by altering the REG-rtx's. */
771 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
772 reg_old_renumber = XCNEWVEC (short, max_regno);
773 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
774 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
775 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
777 CLEAR_HARD_REG_SET (bad_spill_regs_global);
779 init_eliminable_invariants (first, true);
782 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
783 stack slots to the pseudos that lack hard regs or equivalents.
784 Do not touch virtual registers. */
786 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
787 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
788 temp_pseudo_reg_arr[n++] = i;
791 /* Ask IRA to order pseudo-registers for better stack slot
793 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
795 for (i = 0; i < n; i++)
796 alter_reg (temp_pseudo_reg_arr[i], -1, false);
798 /* If we have some registers we think can be eliminated, scan all insns to
799 see if there is an insn that sets one of these registers to something
800 other than itself plus a constant. If so, the register cannot be
801 eliminated. Doing this scan here eliminates an extra pass through the
802 main reload loop in the most common case where register elimination
804 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
806 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
808 maybe_fix_stack_asms ();
810 insns_need_reload = 0;
811 something_needs_elimination = 0;
813 /* Initialize to -1, which means take the first spill register. */
816 /* Spill any hard regs that we know we can't eliminate. */
817 CLEAR_HARD_REG_SET (used_spill_regs);
818 /* There can be multiple ways to eliminate a register;
819 they should be listed adjacently.
820 Elimination for any register fails only if all possible ways fail. */
821 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
824 int can_eliminate = 0;
827 can_eliminate |= ep->can_eliminate;
830 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
832 spill_hard_reg (from, 1);
835 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
836 if (frame_pointer_needed)
837 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
839 finish_spills (global);
841 /* From now on, we may need to generate moves differently. We may also
842 allow modifications of insns which cause them to not be recognized.
843 Any such modifications will be cleaned up during reload itself. */
844 reload_in_progress = 1;
846 /* This loop scans the entire function each go-round
847 and repeats until one repetition spills no additional hard regs. */
850 int something_changed;
852 HOST_WIDE_INT starting_frame_size;
854 starting_frame_size = get_frame_size ();
855 something_was_spilled = false;
857 set_initial_elim_offsets ();
858 set_initial_label_offsets ();
860 /* For each pseudo register that has an equivalent location defined,
861 try to eliminate any eliminable registers (such as the frame pointer)
862 assuming initial offsets for the replacement register, which
865 If the resulting location is directly addressable, substitute
866 the MEM we just got directly for the old REG.
868 If it is not addressable but is a constant or the sum of a hard reg
869 and constant, it is probably not addressable because the constant is
870 out of range, in that case record the address; we will generate
871 hairy code to compute the address in a register each time it is
872 needed. Similarly if it is a hard register, but one that is not
873 valid as an address register.
875 If the location is not addressable, but does not have one of the
876 above forms, assign a stack slot. We have to do this to avoid the
877 potential of producing lots of reloads if, e.g., a location involves
878 a pseudo that didn't get a hard register and has an equivalent memory
879 location that also involves a pseudo that didn't get a hard register.
881 Perhaps at some point we will improve reload_when_needed handling
882 so this problem goes away. But that's very hairy. */
884 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
885 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
887 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
890 if (strict_memory_address_addr_space_p
891 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
893 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
894 else if (CONSTANT_P (XEXP (x, 0))
895 || (REG_P (XEXP (x, 0))
896 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
897 || (GET_CODE (XEXP (x, 0)) == PLUS
898 && REG_P (XEXP (XEXP (x, 0), 0))
899 && (REGNO (XEXP (XEXP (x, 0), 0))
900 < FIRST_PSEUDO_REGISTER)
901 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
902 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
905 /* Make a new stack slot. Then indicate that something
906 changed so we go back and recompute offsets for
907 eliminable registers because the allocation of memory
908 below might change some offset. reg_equiv_{mem,address}
909 will be set up for this pseudo on the next pass around
911 reg_equiv_memory_loc (i) = 0;
912 reg_equiv_init (i) = 0;
913 alter_reg (i, -1, true);
917 if (caller_save_needed)
920 /* If we allocated another stack slot, redo elimination bookkeeping. */
921 if (something_was_spilled || starting_frame_size != get_frame_size ())
923 if (starting_frame_size && crtl->stack_alignment_needed)
925 /* If we have a stack frame, we must align it now. The
926 stack size may be a part of the offset computation for
927 register elimination. So if this changes the stack size,
928 then repeat the elimination bookkeeping. We don't
929 realign when there is no stack, as that will cause a
930 stack frame when none is needed should
931 STARTING_FRAME_OFFSET not be already aligned to
933 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
934 if (starting_frame_size != get_frame_size ())
938 if (caller_save_needed)
940 save_call_clobbered_regs ();
941 /* That might have allocated new insn_chain structures. */
942 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
945 calculate_needs_all_insns (global);
947 if (! ira_conflicts_p)
948 /* Don't do it for IRA. We need this info because we don't
949 change live_throughout and dead_or_set for chains when IRA
951 CLEAR_REG_SET (&spilled_pseudos);
955 something_changed = 0;
957 /* If we allocated any new memory locations, make another pass
958 since it might have changed elimination offsets. */
959 if (something_was_spilled || starting_frame_size != get_frame_size ())
960 something_changed = 1;
962 /* Even if the frame size remained the same, we might still have
963 changed elimination offsets, e.g. if find_reloads called
964 force_const_mem requiring the back end to allocate a constant
965 pool base register that needs to be saved on the stack. */
966 else if (!verify_initial_elim_offsets ())
967 something_changed = 1;
970 HARD_REG_SET to_spill;
971 CLEAR_HARD_REG_SET (to_spill);
972 update_eliminables (&to_spill);
973 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
975 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
976 if (TEST_HARD_REG_BIT (to_spill, i))
978 spill_hard_reg (i, 1);
981 /* Regardless of the state of spills, if we previously had
982 a register that we thought we could eliminate, but now can
983 not eliminate, we must run another pass.
985 Consider pseudos which have an entry in reg_equiv_* which
986 reference an eliminable register. We must make another pass
987 to update reg_equiv_* so that we do not substitute in the
988 old value from when we thought the elimination could be
990 something_changed = 1;
994 select_reload_regs ();
998 if (insns_need_reload != 0 || did_spill)
999 something_changed |= finish_spills (global);
1001 if (! something_changed)
1004 if (caller_save_needed)
1005 delete_caller_save_insns ();
1007 obstack_free (&reload_obstack, reload_firstobj);
1010 /* If global-alloc was run, notify it of any register eliminations we have
1013 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1014 if (ep->can_eliminate)
1015 mark_elimination (ep->from, ep->to);
1017 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1018 If that insn didn't set the register (i.e., it copied the register to
1019 memory), just delete that insn instead of the equivalencing insn plus
1020 anything now dead. If we call delete_dead_insn on that insn, we may
1021 delete the insn that actually sets the register if the register dies
1022 there and that is incorrect. */
1024 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1026 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
1029 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
1031 rtx equiv_insn = XEXP (list, 0);
1033 /* If we already deleted the insn or if it may trap, we can't
1034 delete it. The latter case shouldn't happen, but can
1035 if an insn has a variable address, gets a REG_EH_REGION
1036 note added to it, and then gets converted into a load
1037 from a constant address. */
1038 if (NOTE_P (equiv_insn)
1039 || can_throw_internal (equiv_insn))
1041 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1042 delete_dead_insn (equiv_insn);
1044 SET_INSN_DELETED (equiv_insn);
1049 /* Use the reload registers where necessary
1050 by generating move instructions to move the must-be-register
1051 values into or out of the reload registers. */
1053 if (insns_need_reload != 0 || something_needs_elimination
1054 || something_needs_operands_changed)
1056 HOST_WIDE_INT old_frame_size = get_frame_size ();
1058 reload_as_needed (global);
1060 gcc_assert (old_frame_size == get_frame_size ());
1062 gcc_assert (verify_initial_elim_offsets ());
1065 /* If we were able to eliminate the frame pointer, show that it is no
1066 longer live at the start of any basic block. If it ls live by
1067 virtue of being in a pseudo, that pseudo will be marked live
1068 and hence the frame pointer will be known to be live via that
1071 if (! frame_pointer_needed)
1073 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1075 /* Come here (with failure set nonzero) if we can't get enough spill
1079 CLEAR_REG_SET (&changed_allocation_pseudos);
1080 CLEAR_REG_SET (&spilled_pseudos);
1081 reload_in_progress = 0;
1083 /* Now eliminate all pseudo regs by modifying them into
1084 their equivalent memory references.
1085 The REG-rtx's for the pseudos are modified in place,
1086 so all insns that used to refer to them now refer to memory.
1088 For a reg that has a reg_equiv_address, all those insns
1089 were changed by reloading so that no insns refer to it any longer;
1090 but the DECL_RTL of a variable decl may refer to it,
1091 and if so this causes the debugging info to mention the variable. */
1093 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1097 if (reg_equiv_mem (i))
1098 addr = XEXP (reg_equiv_mem (i), 0);
1100 if (reg_equiv_address (i))
1101 addr = reg_equiv_address (i);
1105 if (reg_renumber[i] < 0)
1107 rtx reg = regno_reg_rtx[i];
1109 REG_USERVAR_P (reg) = 0;
1110 PUT_CODE (reg, MEM);
1111 XEXP (reg, 0) = addr;
1112 if (reg_equiv_memory_loc (i))
1113 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1116 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1117 MEM_ATTRS (reg) = 0;
1119 MEM_NOTRAP_P (reg) = 1;
1121 else if (reg_equiv_mem (i))
1122 XEXP (reg_equiv_mem (i), 0) = addr;
1125 /* We don't want complex addressing modes in debug insns
1126 if simpler ones will do, so delegitimize equivalences
1128 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1130 rtx reg = regno_reg_rtx[i];
1134 if (reg_equiv_constant (i))
1135 equiv = reg_equiv_constant (i);
1136 else if (reg_equiv_invariant (i))
1137 equiv = reg_equiv_invariant (i);
1138 else if (reg && MEM_P (reg))
1139 equiv = targetm.delegitimize_address (reg);
1140 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1146 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1148 insn = DF_REF_INSN (use);
1150 /* Make sure the next ref is for a different instruction,
1151 so that we're not affected by the rescan. */
1152 next = DF_REF_NEXT_REG (use);
1153 while (next && DF_REF_INSN (next) == insn)
1154 next = DF_REF_NEXT_REG (next);
1156 if (DEBUG_INSN_P (insn))
1160 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1161 df_insn_rescan_debug_internal (insn);
1164 INSN_VAR_LOCATION_LOC (insn)
1165 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1172 /* We must set reload_completed now since the cleanup_subreg_operands call
1173 below will re-recognize each insn and reload may have generated insns
1174 which are only valid during and after reload. */
1175 reload_completed = 1;
1177 /* Make a pass over all the insns and delete all USEs which we inserted
1178 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1179 notes. Delete all CLOBBER insns, except those that refer to the return
1180 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1181 from misarranging variable-array code, and simplify (subreg (reg))
1182 operands. Strip and regenerate REG_INC notes that may have been moved
1185 for (insn = first; insn; insn = NEXT_INSN (insn))
1191 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1192 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1194 if ((GET_CODE (PATTERN (insn)) == USE
1195 /* We mark with QImode USEs introduced by reload itself. */
1196 && (GET_MODE (insn) == QImode
1197 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1198 || (GET_CODE (PATTERN (insn)) == CLOBBER
1199 && (!MEM_P (XEXP (PATTERN (insn), 0))
1200 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1201 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1202 && XEXP (XEXP (PATTERN (insn), 0), 0)
1203 != stack_pointer_rtx))
1204 && (!REG_P (XEXP (PATTERN (insn), 0))
1205 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1211 /* Some CLOBBERs may survive until here and still reference unassigned
1212 pseudos with const equivalent, which may in turn cause ICE in later
1213 passes if the reference remains in place. */
1214 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1215 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1216 VOIDmode, PATTERN (insn));
1218 /* Discard obvious no-ops, even without -O. This optimization
1219 is fast and doesn't interfere with debugging. */
1220 if (NONJUMP_INSN_P (insn)
1221 && GET_CODE (PATTERN (insn)) == SET
1222 && REG_P (SET_SRC (PATTERN (insn)))
1223 && REG_P (SET_DEST (PATTERN (insn)))
1224 && (REGNO (SET_SRC (PATTERN (insn)))
1225 == REGNO (SET_DEST (PATTERN (insn)))))
1231 pnote = ®_NOTES (insn);
1234 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1235 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1236 || REG_NOTE_KIND (*pnote) == REG_INC)
1237 *pnote = XEXP (*pnote, 1);
1239 pnote = &XEXP (*pnote, 1);
1243 add_auto_inc_notes (insn, PATTERN (insn));
1246 /* Simplify (subreg (reg)) if it appears as an operand. */
1247 cleanup_subreg_operands (insn);
1249 /* Clean up invalid ASMs so that they don't confuse later passes.
1251 if (asm_noperands (PATTERN (insn)) >= 0)
1253 extract_insn (insn);
1254 if (!constrain_operands (1))
1256 error_for_asm (insn,
1257 "%<asm%> operand has impossible constraints");
1264 /* If we are doing generic stack checking, give a warning if this
1265 function's frame size is larger than we expect. */
1266 if (flag_stack_check == GENERIC_STACK_CHECK)
1268 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1269 static int verbose_warned = 0;
1271 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1272 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1273 size += UNITS_PER_WORD;
1275 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1277 warning (0, "frame size too large for reliable stack checking");
1278 if (! verbose_warned)
1280 warning (0, "try reducing the number of local variables");
1286 free (temp_pseudo_reg_arr);
1288 /* Indicate that we no longer have known memory locations or constants. */
1291 free (reg_max_ref_width);
1292 free (reg_old_renumber);
1293 free (pseudo_previous_regs);
1294 free (pseudo_forbidden_regs);
1296 CLEAR_HARD_REG_SET (used_spill_regs);
1297 for (i = 0; i < n_spills; i++)
1298 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1300 /* Free all the insn_chain structures at once. */
1301 obstack_free (&reload_obstack, reload_startobj);
1302 unused_insn_chains = 0;
1304 inserted = fixup_abnormal_edges ();
1306 /* We've possibly turned single trapping insn into multiple ones. */
1307 if (cfun->can_throw_non_call_exceptions)
1310 blocks = sbitmap_alloc (last_basic_block);
1311 sbitmap_ones (blocks);
1312 find_many_sub_basic_blocks (blocks);
1313 sbitmap_free (blocks);
1317 commit_edge_insertions ();
1319 /* Replacing pseudos with their memory equivalents might have
1320 created shared rtx. Subsequent passes would get confused
1321 by this, so unshare everything here. */
1322 unshare_all_rtl_again (first);
1324 #ifdef STACK_BOUNDARY
1325 /* init_emit has set the alignment of the hard frame pointer
1326 to STACK_BOUNDARY. It is very likely no longer valid if
1327 the hard frame pointer was used for register allocation. */
1328 if (!frame_pointer_needed)
1329 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1332 VEC_free (rtx_p, heap, substitute_stack);
1334 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1336 reload_completed = !failure;
1341 /* Yet another special case. Unfortunately, reg-stack forces people to
1342 write incorrect clobbers in asm statements. These clobbers must not
1343 cause the register to appear in bad_spill_regs, otherwise we'll call
1344 fatal_insn later. We clear the corresponding regnos in the live
1345 register sets to avoid this.
1346 The whole thing is rather sick, I'm afraid. */
1349 maybe_fix_stack_asms (void)
1352 const char *constraints[MAX_RECOG_OPERANDS];
1353 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1354 struct insn_chain *chain;
1356 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1359 HARD_REG_SET clobbered, allowed;
1362 if (! INSN_P (chain->insn)
1363 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1365 pat = PATTERN (chain->insn);
1366 if (GET_CODE (pat) != PARALLEL)
1369 CLEAR_HARD_REG_SET (clobbered);
1370 CLEAR_HARD_REG_SET (allowed);
1372 /* First, make a mask of all stack regs that are clobbered. */
1373 for (i = 0; i < XVECLEN (pat, 0); i++)
1375 rtx t = XVECEXP (pat, 0, i);
1376 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1377 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1380 /* Get the operand values and constraints out of the insn. */
1381 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1382 constraints, operand_mode, NULL);
1384 /* For every operand, see what registers are allowed. */
1385 for (i = 0; i < noperands; i++)
1387 const char *p = constraints[i];
1388 /* For every alternative, we compute the class of registers allowed
1389 for reloading in CLS, and merge its contents into the reg set
1391 int cls = (int) NO_REGS;
1397 if (c == '\0' || c == ',' || c == '#')
1399 /* End of one alternative - mark the regs in the current
1400 class, and reset the class. */
1401 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1407 } while (c != '\0' && c != ',');
1415 case '=': case '+': case '*': case '%': case '?': case '!':
1416 case '0': case '1': case '2': case '3': case '4': case '<':
1417 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1418 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1419 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1420 case TARGET_MEM_CONSTRAINT:
1424 cls = (int) reg_class_subunion[cls]
1425 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1430 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1434 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1435 cls = (int) reg_class_subunion[cls]
1436 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1438 cls = (int) reg_class_subunion[cls]
1439 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1441 p += CONSTRAINT_LEN (c, p);
1444 /* Those of the registers which are clobbered, but allowed by the
1445 constraints, must be usable as reload registers. So clear them
1446 out of the life information. */
1447 AND_HARD_REG_SET (allowed, clobbered);
1448 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1449 if (TEST_HARD_REG_BIT (allowed, i))
1451 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1452 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1459 /* Copy the global variables n_reloads and rld into the corresponding elts
1462 copy_reloads (struct insn_chain *chain)
1464 chain->n_reloads = n_reloads;
1465 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1466 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1467 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1470 /* Walk the chain of insns, and determine for each whether it needs reloads
1471 and/or eliminations. Build the corresponding insns_need_reload list, and
1472 set something_needs_elimination as appropriate. */
1474 calculate_needs_all_insns (int global)
1476 struct insn_chain **pprev_reload = &insns_need_reload;
1477 struct insn_chain *chain, *next = 0;
1479 something_needs_elimination = 0;
1481 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1482 for (chain = reload_insn_chain; chain != 0; chain = next)
1484 rtx insn = chain->insn;
1488 /* Clear out the shortcuts. */
1489 chain->n_reloads = 0;
1490 chain->need_elim = 0;
1491 chain->need_reload = 0;
1492 chain->need_operand_change = 0;
1494 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1495 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1496 what effects this has on the known offsets at labels. */
1498 if (LABEL_P (insn) || JUMP_P (insn)
1499 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1500 set_label_offsets (insn, insn, 0);
1504 rtx old_body = PATTERN (insn);
1505 int old_code = INSN_CODE (insn);
1506 rtx old_notes = REG_NOTES (insn);
1507 int did_elimination = 0;
1508 int operands_changed = 0;
1509 rtx set = single_set (insn);
1511 /* Skip insns that only set an equivalence. */
1512 if (set && REG_P (SET_DEST (set))
1513 && reg_renumber[REGNO (SET_DEST (set))] < 0
1514 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1515 || (reg_equiv_invariant (REGNO (SET_DEST (set)))))
1516 && reg_equiv_init (REGNO (SET_DEST (set))))
1519 /* If needed, eliminate any eliminable registers. */
1520 if (num_eliminable || num_eliminable_invariants)
1521 did_elimination = eliminate_regs_in_insn (insn, 0);
1523 /* Analyze the instruction. */
1524 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1525 global, spill_reg_order);
1527 /* If a no-op set needs more than one reload, this is likely
1528 to be something that needs input address reloads. We
1529 can't get rid of this cleanly later, and it is of no use
1530 anyway, so discard it now.
1531 We only do this when expensive_optimizations is enabled,
1532 since this complements reload inheritance / output
1533 reload deletion, and it can make debugging harder. */
1534 if (flag_expensive_optimizations && n_reloads > 1)
1536 rtx set = single_set (insn);
1539 ((SET_SRC (set) == SET_DEST (set)
1540 && REG_P (SET_SRC (set))
1541 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1542 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1543 && reg_renumber[REGNO (SET_SRC (set))] < 0
1544 && reg_renumber[REGNO (SET_DEST (set))] < 0
1545 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1546 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1547 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1548 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1550 if (ira_conflicts_p)
1551 /* Inform IRA about the insn deletion. */
1552 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1553 REGNO (SET_SRC (set)));
1555 /* Delete it from the reload chain. */
1557 chain->prev->next = next;
1559 reload_insn_chain = next;
1561 next->prev = chain->prev;
1562 chain->next = unused_insn_chains;
1563 unused_insn_chains = chain;
1568 update_eliminable_offsets ();
1570 /* Remember for later shortcuts which insns had any reloads or
1571 register eliminations. */
1572 chain->need_elim = did_elimination;
1573 chain->need_reload = n_reloads > 0;
1574 chain->need_operand_change = operands_changed;
1576 /* Discard any register replacements done. */
1577 if (did_elimination)
1579 obstack_free (&reload_obstack, reload_insn_firstobj);
1580 PATTERN (insn) = old_body;
1581 INSN_CODE (insn) = old_code;
1582 REG_NOTES (insn) = old_notes;
1583 something_needs_elimination = 1;
1586 something_needs_operands_changed |= operands_changed;
1590 copy_reloads (chain);
1591 *pprev_reload = chain;
1592 pprev_reload = &chain->next_need_reload;
1599 /* This function is called from the register allocator to set up estimates
1600 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1601 an invariant. The structure is similar to calculate_needs_all_insns. */
1604 calculate_elim_costs_all_insns (void)
1606 int *reg_equiv_init_cost;
1610 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1612 init_eliminable_invariants (get_insns (), false);
1614 set_initial_elim_offsets ();
1615 set_initial_label_offsets ();
1622 FOR_BB_INSNS (bb, insn)
1624 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1625 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1626 what effects this has on the known offsets at labels. */
1628 if (LABEL_P (insn) || JUMP_P (insn)
1629 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1630 set_label_offsets (insn, insn, 0);
1634 rtx set = single_set (insn);
1636 /* Skip insns that only set an equivalence. */
1637 if (set && REG_P (SET_DEST (set))
1638 && reg_renumber[REGNO (SET_DEST (set))] < 0
1639 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1640 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1642 unsigned regno = REGNO (SET_DEST (set));
1643 rtx init = reg_equiv_init (regno);
1646 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1648 int cost = set_src_cost (t, optimize_bb_for_speed_p (bb));
1649 int freq = REG_FREQ_FROM_BB (bb);
1651 reg_equiv_init_cost[regno] = cost * freq;
1655 /* If needed, eliminate any eliminable registers. */
1656 if (num_eliminable || num_eliminable_invariants)
1657 elimination_costs_in_insn (insn);
1660 update_eliminable_offsets ();
1664 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1666 if (reg_equiv_invariant (i))
1668 if (reg_equiv_init (i))
1670 int cost = reg_equiv_init_cost[i];
1673 "Reg %d has equivalence, initial gains %d\n", i, cost);
1675 ira_adjust_equiv_reg_cost (i, cost);
1681 "Reg %d had equivalence, but can't be eliminated\n",
1683 ira_adjust_equiv_reg_cost (i, 0);
1688 free (reg_equiv_init_cost);
1691 /* Comparison function for qsort to decide which of two reloads
1692 should be handled first. *P1 and *P2 are the reload numbers. */
1695 reload_reg_class_lower (const void *r1p, const void *r2p)
1697 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1700 /* Consider required reloads before optional ones. */
1701 t = rld[r1].optional - rld[r2].optional;
1705 /* Count all solitary classes before non-solitary ones. */
1706 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1707 - (reg_class_size[(int) rld[r1].rclass] == 1));
1711 /* Aside from solitaires, consider all multi-reg groups first. */
1712 t = rld[r2].nregs - rld[r1].nregs;
1716 /* Consider reloads in order of increasing reg-class number. */
1717 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1721 /* If reloads are equally urgent, sort by reload number,
1722 so that the results of qsort leave nothing to chance. */
1726 /* The cost of spilling each hard reg. */
1727 static int spill_cost[FIRST_PSEUDO_REGISTER];
1729 /* When spilling multiple hard registers, we use SPILL_COST for the first
1730 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1731 only the first hard reg for a multi-reg pseudo. */
1732 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1734 /* Map of hard regno to pseudo regno currently occupying the hard
1736 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1738 /* Update the spill cost arrays, considering that pseudo REG is live. */
1741 count_pseudo (int reg)
1743 int freq = REG_FREQ (reg);
1744 int r = reg_renumber[reg];
1747 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1748 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1749 /* Ignore spilled pseudo-registers which can be here only if IRA
1751 || (ira_conflicts_p && r < 0))
1754 SET_REGNO_REG_SET (&pseudos_counted, reg);
1756 gcc_assert (r >= 0);
1758 spill_add_cost[r] += freq;
1759 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1762 hard_regno_to_pseudo_regno[r + nregs] = reg;
1763 spill_cost[r + nregs] += freq;
1767 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1768 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1771 order_regs_for_reload (struct insn_chain *chain)
1774 HARD_REG_SET used_by_pseudos;
1775 HARD_REG_SET used_by_pseudos2;
1776 reg_set_iterator rsi;
1778 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1780 memset (spill_cost, 0, sizeof spill_cost);
1781 memset (spill_add_cost, 0, sizeof spill_add_cost);
1782 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1783 hard_regno_to_pseudo_regno[i] = -1;
1785 /* Count number of uses of each hard reg by pseudo regs allocated to it
1786 and then order them by decreasing use. First exclude hard registers
1787 that are live in or across this insn. */
1789 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1790 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1791 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1792 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1794 /* Now find out which pseudos are allocated to it, and update
1796 CLEAR_REG_SET (&pseudos_counted);
1798 EXECUTE_IF_SET_IN_REG_SET
1799 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1803 EXECUTE_IF_SET_IN_REG_SET
1804 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1808 CLEAR_REG_SET (&pseudos_counted);
1811 /* Vector of reload-numbers showing the order in which the reloads should
1813 static short reload_order[MAX_RELOADS];
1815 /* This is used to keep track of the spill regs used in one insn. */
1816 static HARD_REG_SET used_spill_regs_local;
1818 /* We decided to spill hard register SPILLED, which has a size of
1819 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1820 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1821 update SPILL_COST/SPILL_ADD_COST. */
1824 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1826 int freq = REG_FREQ (reg);
1827 int r = reg_renumber[reg];
1828 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1830 /* Ignore spilled pseudo-registers which can be here only if IRA is
1832 if ((ira_conflicts_p && r < 0)
1833 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1834 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1837 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1839 spill_add_cost[r] -= freq;
1842 hard_regno_to_pseudo_regno[r + nregs] = -1;
1843 spill_cost[r + nregs] -= freq;
1847 /* Find reload register to use for reload number ORDER. */
1850 find_reg (struct insn_chain *chain, int order)
1852 int rnum = reload_order[order];
1853 struct reload *rl = rld + rnum;
1854 int best_cost = INT_MAX;
1856 unsigned int i, j, n;
1858 HARD_REG_SET not_usable;
1859 HARD_REG_SET used_by_other_reload;
1860 reg_set_iterator rsi;
1861 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1862 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1864 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1865 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1866 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1868 CLEAR_HARD_REG_SET (used_by_other_reload);
1869 for (k = 0; k < order; k++)
1871 int other = reload_order[k];
1873 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1874 for (j = 0; j < rld[other].nregs; j++)
1875 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1878 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1880 #ifdef REG_ALLOC_ORDER
1881 unsigned int regno = reg_alloc_order[i];
1883 unsigned int regno = i;
1886 if (! TEST_HARD_REG_BIT (not_usable, regno)
1887 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1888 && HARD_REGNO_MODE_OK (regno, rl->mode))
1890 int this_cost = spill_cost[regno];
1892 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1894 for (j = 1; j < this_nregs; j++)
1896 this_cost += spill_add_cost[regno + j];
1897 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1898 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1904 if (ira_conflicts_p)
1906 /* Ask IRA to find a better pseudo-register for
1908 for (n = j = 0; j < this_nregs; j++)
1910 int r = hard_regno_to_pseudo_regno[regno + j];
1914 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1915 regno_pseudo_regs[n++] = r;
1917 regno_pseudo_regs[n++] = -1;
1919 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1920 best_regno_pseudo_regs,
1927 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1928 if (regno_pseudo_regs[j] < 0)
1935 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1937 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1939 if (this_cost < best_cost
1940 /* Among registers with equal cost, prefer caller-saved ones, or
1941 use REG_ALLOC_ORDER if it is defined. */
1942 || (this_cost == best_cost
1943 #ifdef REG_ALLOC_ORDER
1944 && (inv_reg_alloc_order[regno]
1945 < inv_reg_alloc_order[best_reg])
1947 && call_used_regs[regno]
1948 && ! call_used_regs[best_reg]
1953 best_cost = this_cost;
1961 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1963 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1964 rl->regno = best_reg;
1966 EXECUTE_IF_SET_IN_REG_SET
1967 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1969 count_spilled_pseudo (best_reg, rl->nregs, j);
1972 EXECUTE_IF_SET_IN_REG_SET
1973 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1975 count_spilled_pseudo (best_reg, rl->nregs, j);
1978 for (i = 0; i < rl->nregs; i++)
1980 gcc_assert (spill_cost[best_reg + i] == 0);
1981 gcc_assert (spill_add_cost[best_reg + i] == 0);
1982 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1983 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1988 /* Find more reload regs to satisfy the remaining need of an insn, which
1990 Do it by ascending class number, since otherwise a reg
1991 might be spilled for a big class and might fail to count
1992 for a smaller class even though it belongs to that class. */
1995 find_reload_regs (struct insn_chain *chain)
1999 /* In order to be certain of getting the registers we need,
2000 we must sort the reloads into order of increasing register class.
2001 Then our grabbing of reload registers will parallel the process
2002 that provided the reload registers. */
2003 for (i = 0; i < chain->n_reloads; i++)
2005 /* Show whether this reload already has a hard reg. */
2006 if (chain->rld[i].reg_rtx)
2008 int regno = REGNO (chain->rld[i].reg_rtx);
2009 chain->rld[i].regno = regno;
2011 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2014 chain->rld[i].regno = -1;
2015 reload_order[i] = i;
2018 n_reloads = chain->n_reloads;
2019 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2021 CLEAR_HARD_REG_SET (used_spill_regs_local);
2024 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2026 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2028 /* Compute the order of preference for hard registers to spill. */
2030 order_regs_for_reload (chain);
2032 for (i = 0; i < n_reloads; i++)
2034 int r = reload_order[i];
2036 /* Ignore reloads that got marked inoperative. */
2037 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2038 && ! rld[r].optional
2039 && rld[r].regno == -1)
2040 if (! find_reg (chain, i))
2043 fprintf (dump_file, "reload failure for reload %d\n", r);
2044 spill_failure (chain->insn, rld[r].rclass);
2050 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2051 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2053 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2057 select_reload_regs (void)
2059 struct insn_chain *chain;
2061 /* Try to satisfy the needs for each insn. */
2062 for (chain = insns_need_reload; chain != 0;
2063 chain = chain->next_need_reload)
2064 find_reload_regs (chain);
2067 /* Delete all insns that were inserted by emit_caller_save_insns during
2070 delete_caller_save_insns (void)
2072 struct insn_chain *c = reload_insn_chain;
2076 while (c != 0 && c->is_caller_save_insn)
2078 struct insn_chain *next = c->next;
2081 if (c == reload_insn_chain)
2082 reload_insn_chain = next;
2086 next->prev = c->prev;
2088 c->prev->next = next;
2089 c->next = unused_insn_chains;
2090 unused_insn_chains = c;
2098 /* Handle the failure to find a register to spill.
2099 INSN should be one of the insns which needed this particular spill reg. */
2102 spill_failure (rtx insn, enum reg_class rclass)
2104 if (asm_noperands (PATTERN (insn)) >= 0)
2105 error_for_asm (insn, "can%'t find a register in class %qs while "
2106 "reloading %<asm%>",
2107 reg_class_names[rclass]);
2110 error ("unable to find a register to spill in class %qs",
2111 reg_class_names[rclass]);
2115 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2116 debug_reload_to_stream (dump_file);
2118 fatal_insn ("this is the insn:", insn);
2122 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2123 data that is dead in INSN. */
2126 delete_dead_insn (rtx insn)
2128 rtx prev = prev_active_insn (insn);
2131 /* If the previous insn sets a register that dies in our insn make
2132 a note that we want to run DCE immediately after reload.
2134 We used to delete the previous insn & recurse, but that's wrong for
2135 block local equivalences. Instead of trying to figure out the exact
2136 circumstances where we can delete the potentially dead insns, just
2137 let DCE do the job. */
2138 if (prev && GET_CODE (PATTERN (prev)) == SET
2139 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2140 && reg_mentioned_p (prev_dest, PATTERN (insn))
2141 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2142 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2145 SET_INSN_DELETED (insn);
2148 /* Modify the home of pseudo-reg I.
2149 The new home is present in reg_renumber[I].
2151 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2152 or it may be -1, meaning there is none or it is not relevant.
2153 This is used so that all pseudos spilled from a given hard reg
2154 can share one stack slot. */
2157 alter_reg (int i, int from_reg, bool dont_share_p)
2159 /* When outputting an inline function, this can happen
2160 for a reg that isn't actually used. */
2161 if (regno_reg_rtx[i] == 0)
2164 /* If the reg got changed to a MEM at rtl-generation time,
2166 if (!REG_P (regno_reg_rtx[i]))
2169 /* Modify the reg-rtx to contain the new hard reg
2170 number or else to contain its pseudo reg number. */
2171 SET_REGNO (regno_reg_rtx[i],
2172 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2174 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2175 allocate a stack slot for it. */
2177 if (reg_renumber[i] < 0
2178 && REG_N_REFS (i) > 0
2179 && reg_equiv_constant (i) == 0
2180 && (reg_equiv_invariant (i) == 0
2181 || reg_equiv_init (i) == 0)
2182 && reg_equiv_memory_loc (i) == 0)
2185 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2186 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2187 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2188 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2189 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2192 something_was_spilled = true;
2194 if (ira_conflicts_p)
2196 /* Mark the spill for IRA. */
2197 SET_REGNO_REG_SET (&spilled_pseudos, i);
2199 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2205 /* Each pseudo reg has an inherent size which comes from its own mode,
2206 and a total size which provides room for paradoxical subregs
2207 which refer to the pseudo reg in wider modes.
2209 We can use a slot already allocated if it provides both
2210 enough inherent space and enough total space.
2211 Otherwise, we allocate a new slot, making sure that it has no less
2212 inherent space, and no less total space, then the previous slot. */
2213 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2217 /* No known place to spill from => no slot to reuse. */
2218 x = assign_stack_local (mode, total_size,
2219 min_align > inherent_align
2220 || total_size > inherent_size ? -1 : 0);
2224 /* Cancel the big-endian correction done in assign_stack_local.
2225 Get the address of the beginning of the slot. This is so we
2226 can do a big-endian correction unconditionally below. */
2227 if (BYTES_BIG_ENDIAN)
2229 adjust = inherent_size - total_size;
2232 = adjust_address_nv (x, mode_for_size (total_size
2238 if (! dont_share_p && ira_conflicts_p)
2239 /* Inform IRA about allocation a new stack slot. */
2240 ira_mark_new_stack_slot (stack_slot, i, total_size);
2243 /* Reuse a stack slot if possible. */
2244 else if (spill_stack_slot[from_reg] != 0
2245 && spill_stack_slot_width[from_reg] >= total_size
2246 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2248 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2249 x = spill_stack_slot[from_reg];
2251 /* Allocate a bigger slot. */
2254 /* Compute maximum size needed, both for inherent size
2255 and for total size. */
2258 if (spill_stack_slot[from_reg])
2260 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2262 mode = GET_MODE (spill_stack_slot[from_reg]);
2263 if (spill_stack_slot_width[from_reg] > total_size)
2264 total_size = spill_stack_slot_width[from_reg];
2265 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2266 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2269 /* Make a slot with that size. */
2270 x = assign_stack_local (mode, total_size,
2271 min_align > inherent_align
2272 || total_size > inherent_size ? -1 : 0);
2275 /* Cancel the big-endian correction done in assign_stack_local.
2276 Get the address of the beginning of the slot. This is so we
2277 can do a big-endian correction unconditionally below. */
2278 if (BYTES_BIG_ENDIAN)
2280 adjust = GET_MODE_SIZE (mode) - total_size;
2283 = adjust_address_nv (x, mode_for_size (total_size
2289 spill_stack_slot[from_reg] = stack_slot;
2290 spill_stack_slot_width[from_reg] = total_size;
2293 /* On a big endian machine, the "address" of the slot
2294 is the address of the low part that fits its inherent mode. */
2295 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2296 adjust += (total_size - inherent_size);
2298 /* If we have any adjustment to make, or if the stack slot is the
2299 wrong mode, make a new stack slot. */
2300 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2302 /* Set all of the memory attributes as appropriate for a spill. */
2303 set_mem_attrs_for_spill (x);
2305 /* Save the stack slot for later. */
2306 reg_equiv_memory_loc (i) = x;
2310 /* Mark the slots in regs_ever_live for the hard regs used by
2311 pseudo-reg number REGNO, accessed in MODE. */
2314 mark_home_live_1 (int regno, enum machine_mode mode)
2318 i = reg_renumber[regno];
2321 lim = end_hard_regno (mode, i);
2323 df_set_regs_ever_live(i++, true);
2326 /* Mark the slots in regs_ever_live for the hard regs
2327 used by pseudo-reg number REGNO. */
2330 mark_home_live (int regno)
2332 if (reg_renumber[regno] >= 0)
2333 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2336 /* This function handles the tracking of elimination offsets around branches.
2338 X is a piece of RTL being scanned.
2340 INSN is the insn that it came from, if any.
2342 INITIAL_P is nonzero if we are to set the offset to be the initial
2343 offset and zero if we are setting the offset of the label to be the
2347 set_label_offsets (rtx x, rtx insn, int initial_p)
2349 enum rtx_code code = GET_CODE (x);
2352 struct elim_table *p;
2357 if (LABEL_REF_NONLOCAL_P (x))
2362 /* ... fall through ... */
2365 /* If we know nothing about this label, set the desired offsets. Note
2366 that this sets the offset at a label to be the offset before a label
2367 if we don't know anything about the label. This is not correct for
2368 the label after a BARRIER, but is the best guess we can make. If
2369 we guessed wrong, we will suppress an elimination that might have
2370 been possible had we been able to guess correctly. */
2372 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2374 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2375 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2376 = (initial_p ? reg_eliminate[i].initial_offset
2377 : reg_eliminate[i].offset);
2378 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2381 /* Otherwise, if this is the definition of a label and it is
2382 preceded by a BARRIER, set our offsets to the known offset of
2386 && (tem = prev_nonnote_insn (insn)) != 0
2388 set_offsets_for_label (insn);
2390 /* If neither of the above cases is true, compare each offset
2391 with those previously recorded and suppress any eliminations
2392 where the offsets disagree. */
2394 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2395 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2396 != (initial_p ? reg_eliminate[i].initial_offset
2397 : reg_eliminate[i].offset))
2398 reg_eliminate[i].can_eliminate = 0;
2403 set_label_offsets (PATTERN (insn), insn, initial_p);
2405 /* ... fall through ... */
2409 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2410 to indirectly and hence must have all eliminations at their
2412 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2413 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2414 set_label_offsets (XEXP (tem, 0), insn, 1);
2420 /* Each of the labels in the parallel or address vector must be
2421 at their initial offsets. We want the first field for PARALLEL
2422 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2424 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2425 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2430 /* We only care about setting PC. If the source is not RETURN,
2431 IF_THEN_ELSE, or a label, disable any eliminations not at
2432 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2433 isn't one of those possibilities. For branches to a label,
2434 call ourselves recursively.
2436 Note that this can disable elimination unnecessarily when we have
2437 a non-local goto since it will look like a non-constant jump to
2438 someplace in the current function. This isn't a significant
2439 problem since such jumps will normally be when all elimination
2440 pairs are back to their initial offsets. */
2442 if (SET_DEST (x) != pc_rtx)
2445 switch (GET_CODE (SET_SRC (x)))
2452 set_label_offsets (SET_SRC (x), insn, initial_p);
2456 tem = XEXP (SET_SRC (x), 1);
2457 if (GET_CODE (tem) == LABEL_REF)
2458 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2459 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2462 tem = XEXP (SET_SRC (x), 2);
2463 if (GET_CODE (tem) == LABEL_REF)
2464 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2465 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2473 /* If we reach here, all eliminations must be at their initial
2474 offset because we are doing a jump to a variable address. */
2475 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2476 if (p->offset != p->initial_offset)
2477 p->can_eliminate = 0;
2485 /* Called through for_each_rtx, this function examines every reg that occurs
2486 in PX and adjusts the costs for its elimination which are gathered by IRA.
2487 DATA is the insn in which PX occurs. We do not recurse into MEM
2491 note_reg_elim_costly (rtx *px, void *data)
2493 rtx insn = (rtx)data;
2500 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2501 && reg_equiv_init (REGNO (x))
2502 && reg_equiv_invariant (REGNO (x)))
2504 rtx t = reg_equiv_invariant (REGNO (x));
2505 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2506 int cost = set_src_cost (new_rtx, optimize_bb_for_speed_p (elim_bb));
2507 int freq = REG_FREQ_FROM_BB (elim_bb);
2510 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2515 /* Scan X and replace any eliminable registers (such as fp) with a
2516 replacement (such as sp), plus an offset.
2518 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2519 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2520 MEM, we are allowed to replace a sum of a register and the constant zero
2521 with the register, which we cannot do outside a MEM. In addition, we need
2522 to record the fact that a register is referenced outside a MEM.
2524 If INSN is an insn, it is the insn containing X. If we replace a REG
2525 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2526 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2527 the REG is being modified.
2529 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2530 That's used when we eliminate in expressions stored in notes.
2531 This means, do not set ref_outside_mem even if the reference
2534 If FOR_COSTS is true, we are being called before reload in order to
2535 estimate the costs of keeping registers with an equivalence unallocated.
2537 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2538 replacements done assuming all offsets are at their initial values. If
2539 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2540 encounter, return the actual location so that find_reloads will do
2541 the proper thing. */
2544 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2545 bool may_use_invariant, bool for_costs)
2547 enum rtx_code code = GET_CODE (x);
2548 struct elim_table *ep;
2555 if (! current_function_decl)
2578 /* First handle the case where we encounter a bare register that
2579 is eliminable. Replace it with a PLUS. */
2580 if (regno < FIRST_PSEUDO_REGISTER)
2582 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2584 if (ep->from_rtx == x && ep->can_eliminate)
2585 return plus_constant (ep->to_rtx, ep->previous_offset);
2588 else if (reg_renumber && reg_renumber[regno] < 0
2590 && reg_equiv_invariant (regno))
2592 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2593 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2594 mem_mode, insn, true, for_costs);
2595 /* There exists at least one use of REGNO that cannot be
2596 eliminated. Prevent the defining insn from being deleted. */
2597 reg_equiv_init (regno) = NULL_RTX;
2599 alter_reg (regno, -1, true);
2603 /* You might think handling MINUS in a manner similar to PLUS is a
2604 good idea. It is not. It has been tried multiple times and every
2605 time the change has had to have been reverted.
2607 Other parts of reload know a PLUS is special (gen_reload for example)
2608 and require special code to handle code a reloaded PLUS operand.
2610 Also consider backends where the flags register is clobbered by a
2611 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2612 lea instruction comes to mind). If we try to reload a MINUS, we
2613 may kill the flags register that was holding a useful value.
2615 So, please before trying to handle MINUS, consider reload as a
2616 whole instead of this little section as well as the backend issues. */
2618 /* If this is the sum of an eliminable register and a constant, rework
2620 if (REG_P (XEXP (x, 0))
2621 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2622 && CONSTANT_P (XEXP (x, 1)))
2624 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2626 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2628 /* The only time we want to replace a PLUS with a REG (this
2629 occurs when the constant operand of the PLUS is the negative
2630 of the offset) is when we are inside a MEM. We won't want
2631 to do so at other times because that would change the
2632 structure of the insn in a way that reload can't handle.
2633 We special-case the commonest situation in
2634 eliminate_regs_in_insn, so just replace a PLUS with a
2635 PLUS here, unless inside a MEM. */
2636 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2637 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2640 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2641 plus_constant (XEXP (x, 1),
2642 ep->previous_offset));
2645 /* If the register is not eliminable, we are done since the other
2646 operand is a constant. */
2650 /* If this is part of an address, we want to bring any constant to the
2651 outermost PLUS. We will do this by doing register replacement in
2652 our operands and seeing if a constant shows up in one of them.
2654 Note that there is no risk of modifying the structure of the insn,
2655 since we only get called for its operands, thus we are either
2656 modifying the address inside a MEM, or something like an address
2657 operand of a load-address insn. */
2660 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2662 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2665 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2667 /* If one side is a PLUS and the other side is a pseudo that
2668 didn't get a hard register but has a reg_equiv_constant,
2669 we must replace the constant here since it may no longer
2670 be in the position of any operand. */
2671 if (GET_CODE (new0) == PLUS && REG_P (new1)
2672 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2673 && reg_renumber[REGNO (new1)] < 0
2675 && reg_equiv_constant (REGNO (new1)) != 0)
2676 new1 = reg_equiv_constant (REGNO (new1));
2677 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2678 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2679 && reg_renumber[REGNO (new0)] < 0
2680 && reg_equiv_constant (REGNO (new0)) != 0)
2681 new0 = reg_equiv_constant (REGNO (new0));
2683 new_rtx = form_sum (GET_MODE (x), new0, new1);
2685 /* As above, if we are not inside a MEM we do not want to
2686 turn a PLUS into something else. We might try to do so here
2687 for an addition of 0 if we aren't optimizing. */
2688 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2689 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2697 /* If this is the product of an eliminable register and a
2698 constant, apply the distribute law and move the constant out
2699 so that we have (plus (mult ..) ..). This is needed in order
2700 to keep load-address insns valid. This case is pathological.
2701 We ignore the possibility of overflow here. */
2702 if (REG_P (XEXP (x, 0))
2703 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2704 && CONST_INT_P (XEXP (x, 1)))
2705 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2707 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2710 /* Refs inside notes or in DEBUG_INSNs don't count for
2712 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2713 || GET_CODE (insn) == INSN_LIST
2714 || DEBUG_INSN_P (insn))))
2715 ep->ref_outside_mem = 1;
2718 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2719 ep->previous_offset * INTVAL (XEXP (x, 1)));
2722 /* ... fall through ... */
2726 /* See comments before PLUS about handling MINUS. */
2728 case DIV: case UDIV:
2729 case MOD: case UMOD:
2730 case AND: case IOR: case XOR:
2731 case ROTATERT: case ROTATE:
2732 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2734 case GE: case GT: case GEU: case GTU:
2735 case LE: case LT: case LEU: case LTU:
2737 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2739 rtx new1 = XEXP (x, 1)
2740 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2743 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2744 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2749 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2752 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2754 if (new_rtx != XEXP (x, 0))
2756 /* If this is a REG_DEAD note, it is not valid anymore.
2757 Using the eliminated version could result in creating a
2758 REG_DEAD note for the stack or frame pointer. */
2759 if (REG_NOTE_KIND (x) == REG_DEAD)
2761 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2765 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2769 /* ... fall through ... */
2772 /* Now do eliminations in the rest of the chain. If this was
2773 an EXPR_LIST, this might result in allocating more memory than is
2774 strictly needed, but it simplifies the code. */
2777 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2779 if (new_rtx != XEXP (x, 1))
2781 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2789 /* We do not support elimination of a register that is modified.
2790 elimination_effects has already make sure that this does not
2796 /* We do not support elimination of a register that is modified.
2797 elimination_effects has already make sure that this does not
2798 happen. The only remaining case we need to consider here is
2799 that the increment value may be an eliminable register. */
2800 if (GET_CODE (XEXP (x, 1)) == PLUS
2801 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2803 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2804 insn, true, for_costs);
2806 if (new_rtx != XEXP (XEXP (x, 1), 1))
2807 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2808 gen_rtx_PLUS (GET_MODE (x),
2809 XEXP (x, 0), new_rtx));
2813 case STRICT_LOW_PART:
2815 case SIGN_EXTEND: case ZERO_EXTEND:
2816 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2817 case FLOAT: case FIX:
2818 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2827 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2829 if (new_rtx != XEXP (x, 0))
2830 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2834 /* Similar to above processing, but preserve SUBREG_BYTE.
2835 Convert (subreg (mem)) to (mem) if not paradoxical.
2836 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2837 pseudo didn't get a hard reg, we must replace this with the
2838 eliminated version of the memory location because push_reload
2839 may do the replacement in certain circumstances. */
2840 if (REG_P (SUBREG_REG (x))
2841 && !paradoxical_subreg_p (x)
2843 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2845 new_rtx = SUBREG_REG (x);
2848 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2850 if (new_rtx != SUBREG_REG (x))
2852 int x_size = GET_MODE_SIZE (GET_MODE (x));
2853 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2856 && ((x_size < new_size
2857 #ifdef WORD_REGISTER_OPERATIONS
2858 /* On these machines, combine can create rtl of the form
2859 (set (subreg:m1 (reg:m2 R) 0) ...)
2860 where m1 < m2, and expects something interesting to
2861 happen to the entire word. Moreover, it will use the
2862 (reg:m2 R) later, expecting all bits to be preserved.
2863 So if the number of words is the same, preserve the
2864 subreg so that push_reload can see it. */
2865 && ! ((x_size - 1) / UNITS_PER_WORD
2866 == (new_size -1 ) / UNITS_PER_WORD)
2869 || x_size == new_size)
2871 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2873 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2879 /* Our only special processing is to pass the mode of the MEM to our
2880 recursive call and copy the flags. While we are here, handle this
2881 case more efficiently. */
2883 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2886 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2887 && !memory_address_p (GET_MODE (x), new_rtx))
2888 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2890 return replace_equiv_address_nv (x, new_rtx);
2893 /* Handle insn_list USE that a call to a pure function may generate. */
2894 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2896 if (new_rtx != XEXP (x, 0))
2897 return gen_rtx_USE (GET_MODE (x), new_rtx);
2902 gcc_assert (insn && DEBUG_INSN_P (insn));
2912 /* Process each of our operands recursively. If any have changed, make a
2914 fmt = GET_RTX_FORMAT (code);
2915 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2919 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2921 if (new_rtx != XEXP (x, i) && ! copied)
2923 x = shallow_copy_rtx (x);
2926 XEXP (x, i) = new_rtx;
2928 else if (*fmt == 'E')
2931 for (j = 0; j < XVECLEN (x, i); j++)
2933 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2935 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2937 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2941 x = shallow_copy_rtx (x);
2944 XVEC (x, i) = new_v;
2947 XVECEXP (x, i, j) = new_rtx;
2956 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2958 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2961 /* Scan rtx X for modifications of elimination target registers. Update
2962 the table of eliminables to reflect the changed state. MEM_MODE is
2963 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2966 elimination_effects (rtx x, enum machine_mode mem_mode)
2968 enum rtx_code code = GET_CODE (x);
2969 struct elim_table *ep;
2994 /* First handle the case where we encounter a bare register that
2995 is eliminable. Replace it with a PLUS. */
2996 if (regno < FIRST_PSEUDO_REGISTER)
2998 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3000 if (ep->from_rtx == x && ep->can_eliminate)
3003 ep->ref_outside_mem = 1;
3008 else if (reg_renumber[regno] < 0
3010 && reg_equiv_constant (regno)
3011 && ! function_invariant_p (reg_equiv_constant (regno)))
3012 elimination_effects (reg_equiv_constant (regno), mem_mode);
3021 /* If we modify the source of an elimination rule, disable it. */
3022 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3023 if (ep->from_rtx == XEXP (x, 0))
3024 ep->can_eliminate = 0;
3026 /* If we modify the target of an elimination rule by adding a constant,
3027 update its offset. If we modify the target in any other way, we'll
3028 have to disable the rule as well. */
3029 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3030 if (ep->to_rtx == XEXP (x, 0))
3032 int size = GET_MODE_SIZE (mem_mode);
3034 /* If more bytes than MEM_MODE are pushed, account for them. */
3035 #ifdef PUSH_ROUNDING
3036 if (ep->to_rtx == stack_pointer_rtx)
3037 size = PUSH_ROUNDING (size);
3039 if (code == PRE_DEC || code == POST_DEC)
3041 else if (code == PRE_INC || code == POST_INC)
3043 else if (code == PRE_MODIFY || code == POST_MODIFY)
3045 if (GET_CODE (XEXP (x, 1)) == PLUS
3046 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3047 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3048 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3050 ep->can_eliminate = 0;
3054 /* These two aren't unary operators. */
3055 if (code == POST_MODIFY || code == PRE_MODIFY)
3058 /* Fall through to generic unary operation case. */
3059 case STRICT_LOW_PART:
3061 case SIGN_EXTEND: case ZERO_EXTEND:
3062 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3063 case FLOAT: case FIX:
3064 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3073 elimination_effects (XEXP (x, 0), mem_mode);
3077 if (REG_P (SUBREG_REG (x))
3078 && (GET_MODE_SIZE (GET_MODE (x))
3079 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3081 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3084 elimination_effects (SUBREG_REG (x), mem_mode);
3088 /* If using a register that is the source of an eliminate we still
3089 think can be performed, note it cannot be performed since we don't
3090 know how this register is used. */
3091 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3092 if (ep->from_rtx == XEXP (x, 0))
3093 ep->can_eliminate = 0;
3095 elimination_effects (XEXP (x, 0), mem_mode);
3099 /* If clobbering a register that is the replacement register for an
3100 elimination we still think can be performed, note that it cannot
3101 be performed. Otherwise, we need not be concerned about it. */
3102 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3103 if (ep->to_rtx == XEXP (x, 0))
3104 ep->can_eliminate = 0;
3106 elimination_effects (XEXP (x, 0), mem_mode);
3110 /* Check for setting a register that we know about. */
3111 if (REG_P (SET_DEST (x)))
3113 /* See if this is setting the replacement register for an
3116 If DEST is the hard frame pointer, we do nothing because we
3117 assume that all assignments to the frame pointer are for
3118 non-local gotos and are being done at a time when they are valid
3119 and do not disturb anything else. Some machines want to
3120 eliminate a fake argument pointer (or even a fake frame pointer)
3121 with either the real frame or the stack pointer. Assignments to
3122 the hard frame pointer must not prevent this elimination. */
3124 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3126 if (ep->to_rtx == SET_DEST (x)
3127 && SET_DEST (x) != hard_frame_pointer_rtx)
3129 /* If it is being incremented, adjust the offset. Otherwise,
3130 this elimination can't be done. */
3131 rtx src = SET_SRC (x);
3133 if (GET_CODE (src) == PLUS
3134 && XEXP (src, 0) == SET_DEST (x)
3135 && CONST_INT_P (XEXP (src, 1)))
3136 ep->offset -= INTVAL (XEXP (src, 1));
3138 ep->can_eliminate = 0;
3142 elimination_effects (SET_DEST (x), VOIDmode);
3143 elimination_effects (SET_SRC (x), VOIDmode);
3147 /* Our only special processing is to pass the mode of the MEM to our
3149 elimination_effects (XEXP (x, 0), GET_MODE (x));
3156 fmt = GET_RTX_FORMAT (code);
3157 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3160 elimination_effects (XEXP (x, i), mem_mode);
3161 else if (*fmt == 'E')
3162 for (j = 0; j < XVECLEN (x, i); j++)
3163 elimination_effects (XVECEXP (x, i, j), mem_mode);
3167 /* Descend through rtx X and verify that no references to eliminable registers
3168 remain. If any do remain, mark the involved register as not
3172 check_eliminable_occurrences (rtx x)
3181 code = GET_CODE (x);
3183 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3185 struct elim_table *ep;
3187 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3188 if (ep->from_rtx == x)
3189 ep->can_eliminate = 0;
3193 fmt = GET_RTX_FORMAT (code);
3194 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3197 check_eliminable_occurrences (XEXP (x, i));
3198 else if (*fmt == 'E')
3201 for (j = 0; j < XVECLEN (x, i); j++)
3202 check_eliminable_occurrences (XVECEXP (x, i, j));
3207 /* Scan INSN and eliminate all eliminable registers in it.
3209 If REPLACE is nonzero, do the replacement destructively. Also
3210 delete the insn as dead it if it is setting an eliminable register.
3212 If REPLACE is zero, do all our allocations in reload_obstack.
3214 If no eliminations were done and this insn doesn't require any elimination
3215 processing (these are not identical conditions: it might be updating sp,
3216 but not referencing fp; this needs to be seen during reload_as_needed so
3217 that the offset between fp and sp can be taken into consideration), zero
3218 is returned. Otherwise, 1 is returned. */
3221 eliminate_regs_in_insn (rtx insn, int replace)
3223 int icode = recog_memoized (insn);
3224 rtx old_body = PATTERN (insn);
3225 int insn_is_asm = asm_noperands (old_body) >= 0;
3226 rtx old_set = single_set (insn);
3230 rtx substed_operand[MAX_RECOG_OPERANDS];
3231 rtx orig_operand[MAX_RECOG_OPERANDS];
3232 struct elim_table *ep;
3233 rtx plus_src, plus_cst_src;
3235 if (! insn_is_asm && icode < 0)
3237 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3238 || GET_CODE (PATTERN (insn)) == CLOBBER
3239 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3240 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3241 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3242 || DEBUG_INSN_P (insn));
3243 if (DEBUG_INSN_P (insn))
3244 INSN_VAR_LOCATION_LOC (insn)
3245 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3249 if (old_set != 0 && REG_P (SET_DEST (old_set))
3250 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3252 /* Check for setting an eliminable register. */
3253 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3254 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3256 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3257 /* If this is setting the frame pointer register to the
3258 hardware frame pointer register and this is an elimination
3259 that will be done (tested above), this insn is really
3260 adjusting the frame pointer downward to compensate for
3261 the adjustment done before a nonlocal goto. */
3262 if (ep->from == FRAME_POINTER_REGNUM
3263 && ep->to == HARD_FRAME_POINTER_REGNUM)
3265 rtx base = SET_SRC (old_set);
3266 rtx base_insn = insn;
3267 HOST_WIDE_INT offset = 0;
3269 while (base != ep->to_rtx)
3271 rtx prev_insn, prev_set;
3273 if (GET_CODE (base) == PLUS
3274 && CONST_INT_P (XEXP (base, 1)))
3276 offset += INTVAL (XEXP (base, 1));
3277 base = XEXP (base, 0);
3279 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3280 && (prev_set = single_set (prev_insn)) != 0
3281 && rtx_equal_p (SET_DEST (prev_set), base))
3283 base = SET_SRC (prev_set);
3284 base_insn = prev_insn;
3290 if (base == ep->to_rtx)
3293 = plus_constant (ep->to_rtx, offset - ep->offset);
3295 new_body = old_body;
3298 new_body = copy_insn (old_body);
3299 if (REG_NOTES (insn))
3300 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3302 PATTERN (insn) = new_body;
3303 old_set = single_set (insn);
3305 /* First see if this insn remains valid when we
3306 make the change. If not, keep the INSN_CODE
3307 the same and let reload fit it up. */
3308 validate_change (insn, &SET_SRC (old_set), src, 1);
3309 validate_change (insn, &SET_DEST (old_set),
3311 if (! apply_change_group ())
3313 SET_SRC (old_set) = src;
3314 SET_DEST (old_set) = ep->to_rtx;
3323 /* In this case this insn isn't serving a useful purpose. We
3324 will delete it in reload_as_needed once we know that this
3325 elimination is, in fact, being done.
3327 If REPLACE isn't set, we can't delete this insn, but needn't
3328 process it since it won't be used unless something changes. */
3331 delete_dead_insn (insn);
3339 /* We allow one special case which happens to work on all machines we
3340 currently support: a single set with the source or a REG_EQUAL
3341 note being a PLUS of an eliminable register and a constant. */
3342 plus_src = plus_cst_src = 0;
3343 if (old_set && REG_P (SET_DEST (old_set)))
3345 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3346 plus_src = SET_SRC (old_set);
3347 /* First see if the source is of the form (plus (...) CST). */
3349 && CONST_INT_P (XEXP (plus_src, 1)))
3350 plus_cst_src = plus_src;
3351 else if (REG_P (SET_SRC (old_set))
3354 /* Otherwise, see if we have a REG_EQUAL note of the form
3355 (plus (...) CST). */
3357 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3359 if ((REG_NOTE_KIND (links) == REG_EQUAL
3360 || REG_NOTE_KIND (links) == REG_EQUIV)
3361 && GET_CODE (XEXP (links, 0)) == PLUS
3362 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3364 plus_cst_src = XEXP (links, 0);
3370 /* Check that the first operand of the PLUS is a hard reg or
3371 the lowpart subreg of one. */
3374 rtx reg = XEXP (plus_cst_src, 0);
3375 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3376 reg = SUBREG_REG (reg);
3378 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3384 rtx reg = XEXP (plus_cst_src, 0);
3385 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3387 if (GET_CODE (reg) == SUBREG)
3388 reg = SUBREG_REG (reg);
3390 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3391 if (ep->from_rtx == reg && ep->can_eliminate)
3393 rtx to_rtx = ep->to_rtx;
3394 offset += ep->offset;
3395 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3397 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3398 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3400 /* If we have a nonzero offset, and the source is already
3401 a simple REG, the following transformation would
3402 increase the cost of the insn by replacing a simple REG
3403 with (plus (reg sp) CST). So try only when we already
3404 had a PLUS before. */
3405 if (offset == 0 || plus_src)
3407 rtx new_src = plus_constant (to_rtx, offset);
3409 new_body = old_body;
3412 new_body = copy_insn (old_body);
3413 if (REG_NOTES (insn))
3414 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3416 PATTERN (insn) = new_body;
3417 old_set = single_set (insn);
3419 /* First see if this insn remains valid when we make the
3420 change. If not, try to replace the whole pattern with
3421 a simple set (this may help if the original insn was a
3422 PARALLEL that was only recognized as single_set due to
3423 REG_UNUSED notes). If this isn't valid either, keep
3424 the INSN_CODE the same and let reload fix it up. */
3425 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3427 rtx new_pat = gen_rtx_SET (VOIDmode,
3428 SET_DEST (old_set), new_src);
3430 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3431 SET_SRC (old_set) = new_src;
3438 /* This can't have an effect on elimination offsets, so skip right
3444 /* Determine the effects of this insn on elimination offsets. */
3445 elimination_effects (old_body, VOIDmode);
3447 /* Eliminate all eliminable registers occurring in operands that
3448 can be handled by reload. */
3449 extract_insn (insn);
3450 for (i = 0; i < recog_data.n_operands; i++)
3452 orig_operand[i] = recog_data.operand[i];
3453 substed_operand[i] = recog_data.operand[i];
3455 /* For an asm statement, every operand is eliminable. */
3456 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3458 bool is_set_src, in_plus;
3460 /* Check for setting a register that we know about. */
3461 if (recog_data.operand_type[i] != OP_IN
3462 && REG_P (orig_operand[i]))
3464 /* If we are assigning to a register that can be eliminated, it
3465 must be as part of a PARALLEL, since the code above handles
3466 single SETs. We must indicate that we can no longer
3467 eliminate this reg. */
3468 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3470 if (ep->from_rtx == orig_operand[i])
3471 ep->can_eliminate = 0;
3474 /* Companion to the above plus substitution, we can allow
3475 invariants as the source of a plain move. */
3478 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3482 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3483 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3487 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3488 replace ? insn : NULL_RTX,
3489 is_set_src || in_plus, false);
3490 if (substed_operand[i] != orig_operand[i])
3492 /* Terminate the search in check_eliminable_occurrences at
3494 *recog_data.operand_loc[i] = 0;
3496 /* If an output operand changed from a REG to a MEM and INSN is an
3497 insn, write a CLOBBER insn. */
3498 if (recog_data.operand_type[i] != OP_IN
3499 && REG_P (orig_operand[i])
3500 && MEM_P (substed_operand[i])
3502 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3506 for (i = 0; i < recog_data.n_dups; i++)
3507 *recog_data.dup_loc[i]
3508 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3510 /* If any eliminable remain, they aren't eliminable anymore. */
3511 check_eliminable_occurrences (old_body);
3513 /* Substitute the operands; the new values are in the substed_operand
3515 for (i = 0; i < recog_data.n_operands; i++)
3516 *recog_data.operand_loc[i] = substed_operand[i];
3517 for (i = 0; i < recog_data.n_dups; i++)
3518 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3520 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3521 re-recognize the insn. We do this in case we had a simple addition
3522 but now can do this as a load-address. This saves an insn in this
3524 If re-recognition fails, the old insn code number will still be used,
3525 and some register operands may have changed into PLUS expressions.
3526 These will be handled by find_reloads by loading them into a register
3531 /* If we aren't replacing things permanently and we changed something,
3532 make another copy to ensure that all the RTL is new. Otherwise
3533 things can go wrong if find_reload swaps commutative operands
3534 and one is inside RTL that has been copied while the other is not. */
3535 new_body = old_body;
3538 new_body = copy_insn (old_body);
3539 if (REG_NOTES (insn))
3540 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3542 PATTERN (insn) = new_body;
3544 /* If we had a move insn but now we don't, rerecognize it. This will
3545 cause spurious re-recognition if the old move had a PARALLEL since
3546 the new one still will, but we can't call single_set without
3547 having put NEW_BODY into the insn and the re-recognition won't
3548 hurt in this rare case. */
3549 /* ??? Why this huge if statement - why don't we just rerecognize the
3553 && ((REG_P (SET_SRC (old_set))
3554 && (GET_CODE (new_body) != SET
3555 || !REG_P (SET_SRC (new_body))))
3556 /* If this was a load from or store to memory, compare
3557 the MEM in recog_data.operand to the one in the insn.
3558 If they are not equal, then rerecognize the insn. */
3560 && ((MEM_P (SET_SRC (old_set))
3561 && SET_SRC (old_set) != recog_data.operand[1])
3562 || (MEM_P (SET_DEST (old_set))
3563 && SET_DEST (old_set) != recog_data.operand[0])))
3564 /* If this was an add insn before, rerecognize. */
3565 || GET_CODE (SET_SRC (old_set)) == PLUS))
3567 int new_icode = recog (PATTERN (insn), insn, 0);
3569 INSN_CODE (insn) = new_icode;
3573 /* Restore the old body. If there were any changes to it, we made a copy
3574 of it while the changes were still in place, so we'll correctly return
3575 a modified insn below. */
3578 /* Restore the old body. */
3579 for (i = 0; i < recog_data.n_operands; i++)
3580 /* Restoring a top-level match_parallel would clobber the new_body
3581 we installed in the insn. */
3582 if (recog_data.operand_loc[i] != &PATTERN (insn))
3583 *recog_data.operand_loc[i] = orig_operand[i];
3584 for (i = 0; i < recog_data.n_dups; i++)
3585 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3588 /* Update all elimination pairs to reflect the status after the current
3589 insn. The changes we make were determined by the earlier call to
3590 elimination_effects.
3592 We also detect cases where register elimination cannot be done,
3593 namely, if a register would be both changed and referenced outside a MEM
3594 in the resulting insn since such an insn is often undefined and, even if
3595 not, we cannot know what meaning will be given to it. Note that it is
3596 valid to have a register used in an address in an insn that changes it
3597 (presumably with a pre- or post-increment or decrement).
3599 If anything changes, return nonzero. */
3601 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3603 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3604 ep->can_eliminate = 0;
3606 ep->ref_outside_mem = 0;
3608 if (ep->previous_offset != ep->offset)
3613 /* If we changed something, perform elimination in REG_NOTES. This is
3614 needed even when REPLACE is zero because a REG_DEAD note might refer
3615 to a register that we eliminate and could cause a different number
3616 of spill registers to be needed in the final reload pass than in
3618 if (val && REG_NOTES (insn) != 0)
3620 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3626 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3627 register allocator. INSN is the instruction we need to examine, we perform
3628 eliminations in its operands and record cases where eliminating a reg with
3629 an invariant equivalence would add extra cost. */
3632 elimination_costs_in_insn (rtx insn)
3634 int icode = recog_memoized (insn);
3635 rtx old_body = PATTERN (insn);
3636 int insn_is_asm = asm_noperands (old_body) >= 0;
3637 rtx old_set = single_set (insn);
3639 rtx orig_operand[MAX_RECOG_OPERANDS];
3640 rtx orig_dup[MAX_RECOG_OPERANDS];
3641 struct elim_table *ep;
3642 rtx plus_src, plus_cst_src;
3645 if (! insn_is_asm && icode < 0)
3647 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3648 || GET_CODE (PATTERN (insn)) == CLOBBER
3649 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3650 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3651 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3652 || DEBUG_INSN_P (insn));
3656 if (old_set != 0 && REG_P (SET_DEST (old_set))
3657 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3659 /* Check for setting an eliminable register. */
3660 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3661 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3665 /* We allow one special case which happens to work on all machines we
3666 currently support: a single set with the source or a REG_EQUAL
3667 note being a PLUS of an eliminable register and a constant. */
3668 plus_src = plus_cst_src = 0;
3670 if (old_set && REG_P (SET_DEST (old_set)))
3673 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3674 plus_src = SET_SRC (old_set);
3675 /* First see if the source is of the form (plus (...) CST). */
3677 && CONST_INT_P (XEXP (plus_src, 1)))
3678 plus_cst_src = plus_src;
3679 else if (REG_P (SET_SRC (old_set))
3682 /* Otherwise, see if we have a REG_EQUAL note of the form
3683 (plus (...) CST). */
3685 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3687 if ((REG_NOTE_KIND (links) == REG_EQUAL
3688 || REG_NOTE_KIND (links) == REG_EQUIV)
3689 && GET_CODE (XEXP (links, 0)) == PLUS
3690 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3692 plus_cst_src = XEXP (links, 0);
3699 /* Determine the effects of this insn on elimination offsets. */
3700 elimination_effects (old_body, VOIDmode);
3702 /* Eliminate all eliminable registers occurring in operands that
3703 can be handled by reload. */
3704 extract_insn (insn);
3705 for (i = 0; i < recog_data.n_dups; i++)
3706 orig_dup[i] = *recog_data.dup_loc[i];
3708 for (i = 0; i < recog_data.n_operands; i++)
3710 orig_operand[i] = recog_data.operand[i];
3712 /* For an asm statement, every operand is eliminable. */
3713 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3715 bool is_set_src, in_plus;
3717 /* Check for setting a register that we know about. */
3718 if (recog_data.operand_type[i] != OP_IN
3719 && REG_P (orig_operand[i]))
3721 /* If we are assigning to a register that can be eliminated, it
3722 must be as part of a PARALLEL, since the code above handles
3723 single SETs. We must indicate that we can no longer
3724 eliminate this reg. */
3725 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3727 if (ep->from_rtx == orig_operand[i])
3728 ep->can_eliminate = 0;
3731 /* Companion to the above plus substitution, we can allow
3732 invariants as the source of a plain move. */
3734 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3736 if (is_set_src && !sets_reg_p)
3737 note_reg_elim_costly (&SET_SRC (old_set), insn);
3739 if (plus_src && sets_reg_p
3740 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3741 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3744 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3746 is_set_src || in_plus, true);
3747 /* Terminate the search in check_eliminable_occurrences at
3749 *recog_data.operand_loc[i] = 0;
3753 for (i = 0; i < recog_data.n_dups; i++)
3754 *recog_data.dup_loc[i]
3755 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3757 /* If any eliminable remain, they aren't eliminable anymore. */
3758 check_eliminable_occurrences (old_body);
3760 /* Restore the old body. */
3761 for (i = 0; i < recog_data.n_operands; i++)
3762 *recog_data.operand_loc[i] = orig_operand[i];
3763 for (i = 0; i < recog_data.n_dups; i++)
3764 *recog_data.dup_loc[i] = orig_dup[i];
3766 /* Update all elimination pairs to reflect the status after the current
3767 insn. The changes we make were determined by the earlier call to
3768 elimination_effects. */
3770 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3772 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3773 ep->can_eliminate = 0;
3775 ep->ref_outside_mem = 0;
3781 /* Loop through all elimination pairs.
3782 Recalculate the number not at initial offset.
3784 Compute the maximum offset (minimum offset if the stack does not
3785 grow downward) for each elimination pair. */
3788 update_eliminable_offsets (void)
3790 struct elim_table *ep;
3792 num_not_at_initial_offset = 0;
3793 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3795 ep->previous_offset = ep->offset;
3796 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3797 num_not_at_initial_offset++;
3801 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3802 replacement we currently believe is valid, mark it as not eliminable if X
3803 modifies DEST in any way other than by adding a constant integer to it.
3805 If DEST is the frame pointer, we do nothing because we assume that
3806 all assignments to the hard frame pointer are nonlocal gotos and are being
3807 done at a time when they are valid and do not disturb anything else.
3808 Some machines want to eliminate a fake argument pointer with either the
3809 frame or stack pointer. Assignments to the hard frame pointer must not
3810 prevent this elimination.
3812 Called via note_stores from reload before starting its passes to scan
3813 the insns of the function. */
3816 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3820 /* A SUBREG of a hard register here is just changing its mode. We should
3821 not see a SUBREG of an eliminable hard register, but check just in
3823 if (GET_CODE (dest) == SUBREG)
3824 dest = SUBREG_REG (dest);
3826 if (dest == hard_frame_pointer_rtx)
3829 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3830 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3831 && (GET_CODE (x) != SET
3832 || GET_CODE (SET_SRC (x)) != PLUS
3833 || XEXP (SET_SRC (x), 0) != dest
3834 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3836 reg_eliminate[i].can_eliminate_previous
3837 = reg_eliminate[i].can_eliminate = 0;
3842 /* Verify that the initial elimination offsets did not change since the
3843 last call to set_initial_elim_offsets. This is used to catch cases
3844 where something illegal happened during reload_as_needed that could
3845 cause incorrect code to be generated if we did not check for it. */
3848 verify_initial_elim_offsets (void)
3852 if (!num_eliminable)
3855 #ifdef ELIMINABLE_REGS
3857 struct elim_table *ep;
3859 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3861 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3862 if (t != ep->initial_offset)
3867 INITIAL_FRAME_POINTER_OFFSET (t);
3868 if (t != reg_eliminate[0].initial_offset)
3875 /* Reset all offsets on eliminable registers to their initial values. */
3878 set_initial_elim_offsets (void)
3880 struct elim_table *ep = reg_eliminate;
3882 #ifdef ELIMINABLE_REGS
3883 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3885 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3886 ep->previous_offset = ep->offset = ep->initial_offset;
3889 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3890 ep->previous_offset = ep->offset = ep->initial_offset;
3893 num_not_at_initial_offset = 0;
3896 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3899 set_initial_eh_label_offset (rtx label)
3901 set_label_offsets (label, NULL_RTX, 1);
3904 /* Initialize the known label offsets.
3905 Set a known offset for each forced label to be at the initial offset
3906 of each elimination. We do this because we assume that all
3907 computed jumps occur from a location where each elimination is
3908 at its initial offset.
3909 For all other labels, show that we don't know the offsets. */
3912 set_initial_label_offsets (void)
3915 memset (offsets_known_at, 0, num_labels);
3917 for (x = forced_labels; x; x = XEXP (x, 1))
3919 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3921 for_each_eh_label (set_initial_eh_label_offset);
3924 /* Set all elimination offsets to the known values for the code label given
3928 set_offsets_for_label (rtx insn)
3931 int label_nr = CODE_LABEL_NUMBER (insn);
3932 struct elim_table *ep;
3934 num_not_at_initial_offset = 0;
3935 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3937 ep->offset = ep->previous_offset
3938 = offsets_at[label_nr - first_label_num][i];
3939 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3940 num_not_at_initial_offset++;
3944 /* See if anything that happened changes which eliminations are valid.
3945 For example, on the SPARC, whether or not the frame pointer can
3946 be eliminated can depend on what registers have been used. We need
3947 not check some conditions again (such as flag_omit_frame_pointer)
3948 since they can't have changed. */
3951 update_eliminables (HARD_REG_SET *pset)
3953 int previous_frame_pointer_needed = frame_pointer_needed;
3954 struct elim_table *ep;
3956 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3957 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3958 && targetm.frame_pointer_required ())
3959 #ifdef ELIMINABLE_REGS
3960 || ! targetm.can_eliminate (ep->from, ep->to)
3963 ep->can_eliminate = 0;
3965 /* Look for the case where we have discovered that we can't replace
3966 register A with register B and that means that we will now be
3967 trying to replace register A with register C. This means we can
3968 no longer replace register C with register B and we need to disable
3969 such an elimination, if it exists. This occurs often with A == ap,
3970 B == sp, and C == fp. */
3972 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3974 struct elim_table *op;
3977 if (! ep->can_eliminate && ep->can_eliminate_previous)
3979 /* Find the current elimination for ep->from, if there is a
3981 for (op = reg_eliminate;
3982 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3983 if (op->from == ep->from && op->can_eliminate)
3989 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3991 for (op = reg_eliminate;
3992 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3993 if (op->from == new_to && op->to == ep->to)
3994 op->can_eliminate = 0;
3998 /* See if any registers that we thought we could eliminate the previous
3999 time are no longer eliminable. If so, something has changed and we
4000 must spill the register. Also, recompute the number of eliminable
4001 registers and see if the frame pointer is needed; it is if there is
4002 no elimination of the frame pointer that we can perform. */
4004 frame_pointer_needed = 1;
4005 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4007 if (ep->can_eliminate
4008 && ep->from == FRAME_POINTER_REGNUM
4009 && ep->to != HARD_FRAME_POINTER_REGNUM
4010 && (! SUPPORTS_STACK_ALIGNMENT
4011 || ! crtl->stack_realign_needed))
4012 frame_pointer_needed = 0;
4014 if (! ep->can_eliminate && ep->can_eliminate_previous)
4016 ep->can_eliminate_previous = 0;
4017 SET_HARD_REG_BIT (*pset, ep->from);
4022 /* If we didn't need a frame pointer last time, but we do now, spill
4023 the hard frame pointer. */
4024 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4025 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4028 /* Return true if X is used as the target register of an elimination. */
4031 elimination_target_reg_p (rtx x)
4033 struct elim_table *ep;
4035 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4036 if (ep->to_rtx == x && ep->can_eliminate)
4042 /* Initialize the table of registers to eliminate.
4043 Pre-condition: global flag frame_pointer_needed has been set before
4044 calling this function. */
4047 init_elim_table (void)
4049 struct elim_table *ep;
4050 #ifdef ELIMINABLE_REGS
4051 const struct elim_table_1 *ep1;
4055 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4059 #ifdef ELIMINABLE_REGS
4060 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4061 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4063 ep->from = ep1->from;
4065 ep->can_eliminate = ep->can_eliminate_previous
4066 = (targetm.can_eliminate (ep->from, ep->to)
4067 && ! (ep->to == STACK_POINTER_REGNUM
4068 && frame_pointer_needed
4069 && (! SUPPORTS_STACK_ALIGNMENT
4070 || ! stack_realign_fp)));
4073 reg_eliminate[0].from = reg_eliminate_1[0].from;
4074 reg_eliminate[0].to = reg_eliminate_1[0].to;
4075 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4076 = ! frame_pointer_needed;
4079 /* Count the number of eliminable registers and build the FROM and TO
4080 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4081 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4082 We depend on this. */
4083 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4085 num_eliminable += ep->can_eliminate;
4086 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4087 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4091 /* Find all the pseudo registers that didn't get hard regs
4092 but do have known equivalent constants or memory slots.
4093 These include parameters (known equivalent to parameter slots)
4094 and cse'd or loop-moved constant memory addresses.
4096 Record constant equivalents in reg_equiv_constant
4097 so they will be substituted by find_reloads.
4098 Record memory equivalents in reg_mem_equiv so they can
4099 be substituted eventually by altering the REG-rtx's. */
4102 init_eliminable_invariants (rtx first, bool do_subregs)
4109 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4111 reg_max_ref_width = NULL;
4113 num_eliminable_invariants = 0;
4115 first_label_num = get_first_label_num ();
4116 num_labels = max_label_num () - first_label_num;
4118 /* Allocate the tables used to store offset information at labels. */
4119 offsets_known_at = XNEWVEC (char, num_labels);
4120 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4122 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4123 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4124 find largest such for each pseudo. FIRST is the head of the insn
4127 for (insn = first; insn; insn = NEXT_INSN (insn))
4129 rtx set = single_set (insn);
4131 /* We may introduce USEs that we want to remove at the end, so
4132 we'll mark them with QImode. Make sure there are no
4133 previously-marked insns left by say regmove. */
4134 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4135 && GET_MODE (insn) != VOIDmode)
4136 PUT_MODE (insn, VOIDmode);
4138 if (do_subregs && NONDEBUG_INSN_P (insn))
4139 scan_paradoxical_subregs (PATTERN (insn));
4141 if (set != 0 && REG_P (SET_DEST (set)))
4143 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4149 i = REGNO (SET_DEST (set));
4152 if (i <= LAST_VIRTUAL_REGISTER)
4155 /* If flag_pic and we have constant, verify it's legitimate. */
4157 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4159 /* It can happen that a REG_EQUIV note contains a MEM
4160 that is not a legitimate memory operand. As later
4161 stages of reload assume that all addresses found
4162 in the reg_equiv_* arrays were originally legitimate,
4163 we ignore such REG_EQUIV notes. */
4164 if (memory_operand (x, VOIDmode))
4166 /* Always unshare the equivalence, so we can
4167 substitute into this insn without touching the
4169 reg_equiv_memory_loc (i) = copy_rtx (x);
4171 else if (function_invariant_p (x))
4173 enum machine_mode mode;
4175 mode = GET_MODE (SET_DEST (set));
4176 if (GET_CODE (x) == PLUS)
4178 /* This is PLUS of frame pointer and a constant,
4179 and might be shared. Unshare it. */
4180 reg_equiv_invariant (i) = copy_rtx (x);
4181 num_eliminable_invariants++;
4183 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4185 reg_equiv_invariant (i) = x;
4186 num_eliminable_invariants++;
4188 else if (targetm.legitimate_constant_p (mode, x))
4189 reg_equiv_constant (i) = x;
4192 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4193 if (! reg_equiv_memory_loc (i))
4194 reg_equiv_init (i) = NULL_RTX;
4199 reg_equiv_init (i) = NULL_RTX;
4204 reg_equiv_init (i) = NULL_RTX;
4209 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4210 if (reg_equiv_init (i))
4212 fprintf (dump_file, "init_insns for %u: ", i);
4213 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4214 fprintf (dump_file, "\n");
4218 /* Indicate that we no longer have known memory locations or constants.
4219 Free all data involved in tracking these. */
4222 free_reg_equiv (void)
4227 free (offsets_known_at);
4230 offsets_known_at = 0;
4232 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4233 if (reg_equiv_alt_mem_list (i))
4234 free_EXPR_LIST_list (®_equiv_alt_mem_list (i));
4235 VEC_free (reg_equivs_t, gc, reg_equivs);
4240 /* Kick all pseudos out of hard register REGNO.
4242 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4243 because we found we can't eliminate some register. In the case, no pseudos
4244 are allowed to be in the register, even if they are only in a block that
4245 doesn't require spill registers, unlike the case when we are spilling this
4246 hard reg to produce another spill register.
4248 Return nonzero if any pseudos needed to be kicked out. */
4251 spill_hard_reg (unsigned int regno, int cant_eliminate)
4257 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4258 df_set_regs_ever_live (regno, true);
4261 /* Spill every pseudo reg that was allocated to this reg
4262 or to something that overlaps this reg. */
4264 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4265 if (reg_renumber[i] >= 0
4266 && (unsigned int) reg_renumber[i] <= regno
4267 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4268 SET_REGNO_REG_SET (&spilled_pseudos, i);
4271 /* After find_reload_regs has been run for all insn that need reloads,
4272 and/or spill_hard_regs was called, this function is used to actually
4273 spill pseudo registers and try to reallocate them. It also sets up the
4274 spill_regs array for use by choose_reload_regs. */
4277 finish_spills (int global)
4279 struct insn_chain *chain;
4280 int something_changed = 0;
4282 reg_set_iterator rsi;
4284 /* Build the spill_regs array for the function. */
4285 /* If there are some registers still to eliminate and one of the spill regs
4286 wasn't ever used before, additional stack space may have to be
4287 allocated to store this register. Thus, we may have changed the offset
4288 between the stack and frame pointers, so mark that something has changed.
4290 One might think that we need only set VAL to 1 if this is a call-used
4291 register. However, the set of registers that must be saved by the
4292 prologue is not identical to the call-used set. For example, the
4293 register used by the call insn for the return PC is a call-used register,
4294 but must be saved by the prologue. */
4297 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4298 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4300 spill_reg_order[i] = n_spills;
4301 spill_regs[n_spills++] = i;
4302 if (num_eliminable && ! df_regs_ever_live_p (i))
4303 something_changed = 1;
4304 df_set_regs_ever_live (i, true);
4307 spill_reg_order[i] = -1;
4309 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4310 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4312 /* Record the current hard register the pseudo is allocated to
4313 in pseudo_previous_regs so we avoid reallocating it to the
4314 same hard reg in a later pass. */
4315 gcc_assert (reg_renumber[i] >= 0);
4317 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4318 /* Mark it as no longer having a hard register home. */
4319 reg_renumber[i] = -1;
4320 if (ira_conflicts_p)
4321 /* Inform IRA about the change. */
4322 ira_mark_allocation_change (i);
4323 /* We will need to scan everything again. */
4324 something_changed = 1;
4327 /* Retry global register allocation if possible. */
4328 if (global && ira_conflicts_p)
4332 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4333 /* For every insn that needs reloads, set the registers used as spill
4334 regs in pseudo_forbidden_regs for every pseudo live across the
4336 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4338 EXECUTE_IF_SET_IN_REG_SET
4339 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4341 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4342 chain->used_spill_regs);
4344 EXECUTE_IF_SET_IN_REG_SET
4345 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4347 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4348 chain->used_spill_regs);
4352 /* Retry allocating the pseudos spilled in IRA and the
4353 reload. For each reg, merge the various reg sets that
4354 indicate which hard regs can't be used, and call
4355 ira_reassign_pseudos. */
4356 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4357 if (reg_old_renumber[i] != reg_renumber[i])
4359 if (reg_renumber[i] < 0)
4360 temp_pseudo_reg_arr[n++] = i;
4362 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4364 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4365 bad_spill_regs_global,
4366 pseudo_forbidden_regs, pseudo_previous_regs,
4368 something_changed = 1;
4370 /* Fix up the register information in the insn chain.
4371 This involves deleting those of the spilled pseudos which did not get
4372 a new hard register home from the live_{before,after} sets. */
4373 for (chain = reload_insn_chain; chain; chain = chain->next)
4375 HARD_REG_SET used_by_pseudos;
4376 HARD_REG_SET used_by_pseudos2;
4378 if (! ira_conflicts_p)
4380 /* Don't do it for IRA because IRA and the reload still can
4381 assign hard registers to the spilled pseudos on next
4382 reload iterations. */
4383 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4384 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4386 /* Mark any unallocated hard regs as available for spills. That
4387 makes inheritance work somewhat better. */
4388 if (chain->need_reload)
4390 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4391 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4392 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4394 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4395 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4396 /* Value of chain->used_spill_regs from previous iteration
4397 may be not included in the value calculated here because
4398 of possible removing caller-saves insns (see function
4399 delete_caller_save_insns. */
4400 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4401 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4405 CLEAR_REG_SET (&changed_allocation_pseudos);
4406 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4407 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4409 int regno = reg_renumber[i];
4410 if (reg_old_renumber[i] == regno)
4413 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4415 alter_reg (i, reg_old_renumber[i], false);
4416 reg_old_renumber[i] = regno;
4420 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4422 fprintf (dump_file, " Register %d now in %d.\n\n",
4423 i, reg_renumber[i]);
4427 return something_changed;
4430 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4433 scan_paradoxical_subregs (rtx x)
4437 enum rtx_code code = GET_CODE (x);
4448 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4456 if (REG_P (SUBREG_REG (x))
4457 && (GET_MODE_SIZE (GET_MODE (x))
4458 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4460 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4461 = GET_MODE_SIZE (GET_MODE (x));
4462 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4470 fmt = GET_RTX_FORMAT (code);
4471 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4474 scan_paradoxical_subregs (XEXP (x, i));
4475 else if (fmt[i] == 'E')
4478 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4479 scan_paradoxical_subregs (XVECEXP (x, i, j));
4484 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4485 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4486 and apply the corresponding narrowing subreg to *OTHER_PTR.
4487 Return true if the operands were changed, false otherwise. */
4490 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4492 rtx op, inner, other, tem;
4495 if (!paradoxical_subreg_p (op))
4497 inner = SUBREG_REG (op);
4500 tem = gen_lowpart_common (GET_MODE (inner), other);
4504 /* If the lowpart operation turned a hard register into a subreg,
4505 rather than simplifying it to another hard register, then the
4506 mode change cannot be properly represented. For example, OTHER
4507 might be valid in its current mode, but not in the new one. */
4508 if (GET_CODE (tem) == SUBREG
4510 && HARD_REGISTER_P (other))
4518 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4519 examine all of the reload insns between PREV and NEXT exclusive, and
4520 annotate all that may trap. */
4523 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4525 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4528 if (!insn_could_throw_p (insn))
4529 remove_note (insn, note);
4530 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4533 /* Reload pseudo-registers into hard regs around each insn as needed.
4534 Additional register load insns are output before the insn that needs it
4535 and perhaps store insns after insns that modify the reloaded pseudo reg.
4537 reg_last_reload_reg and reg_reloaded_contents keep track of
4538 which registers are already available in reload registers.
4539 We update these for the reloads that we perform,
4540 as the insns are scanned. */
4543 reload_as_needed (int live_known)
4545 struct insn_chain *chain;
4546 #if defined (AUTO_INC_DEC)
4551 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4552 memset (spill_reg_store, 0, sizeof spill_reg_store);
4553 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4554 INIT_REG_SET (®_has_output_reload);
4555 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4556 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4558 set_initial_elim_offsets ();
4560 /* Generate a marker insn that we will move around. */
4561 marker = emit_note (NOTE_INSN_DELETED);
4562 unlink_insn_chain (marker, marker);
4564 for (chain = reload_insn_chain; chain; chain = chain->next)
4567 rtx insn = chain->insn;
4568 rtx old_next = NEXT_INSN (insn);
4570 rtx old_prev = PREV_INSN (insn);
4573 /* If we pass a label, copy the offsets from the label information
4574 into the current offsets of each elimination. */
4576 set_offsets_for_label (insn);
4578 else if (INSN_P (insn))
4580 regset_head regs_to_forget;
4581 INIT_REG_SET (®s_to_forget);
4582 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4584 /* If this is a USE and CLOBBER of a MEM, ensure that any
4585 references to eliminable registers have been removed. */
4587 if ((GET_CODE (PATTERN (insn)) == USE
4588 || GET_CODE (PATTERN (insn)) == CLOBBER)
4589 && MEM_P (XEXP (PATTERN (insn), 0)))
4590 XEXP (XEXP (PATTERN (insn), 0), 0)
4591 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4592 GET_MODE (XEXP (PATTERN (insn), 0)),
4595 /* If we need to do register elimination processing, do so.
4596 This might delete the insn, in which case we are done. */
4597 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4599 eliminate_regs_in_insn (insn, 1);
4602 update_eliminable_offsets ();
4603 CLEAR_REG_SET (®s_to_forget);
4608 /* If need_elim is nonzero but need_reload is zero, one might think
4609 that we could simply set n_reloads to 0. However, find_reloads
4610 could have done some manipulation of the insn (such as swapping
4611 commutative operands), and these manipulations are lost during
4612 the first pass for every insn that needs register elimination.
4613 So the actions of find_reloads must be redone here. */
4615 if (! chain->need_elim && ! chain->need_reload
4616 && ! chain->need_operand_change)
4618 /* First find the pseudo regs that must be reloaded for this insn.
4619 This info is returned in the tables reload_... (see reload.h).
4620 Also modify the body of INSN by substituting RELOAD
4621 rtx's for those pseudo regs. */
4624 CLEAR_REG_SET (®_has_output_reload);
4625 CLEAR_HARD_REG_SET (reg_is_output_reload);
4627 find_reloads (insn, 1, spill_indirect_levels, live_known,
4633 rtx next = NEXT_INSN (insn);
4636 /* ??? PREV can get deleted by reload inheritance.
4637 Work around this by emitting a marker note. */
4638 prev = PREV_INSN (insn);
4639 reorder_insns_nobb (marker, marker, prev);
4641 /* Now compute which reload regs to reload them into. Perhaps
4642 reusing reload regs from previous insns, or else output
4643 load insns to reload them. Maybe output store insns too.
4644 Record the choices of reload reg in reload_reg_rtx. */
4645 choose_reload_regs (chain);
4647 /* Generate the insns to reload operands into or out of
4648 their reload regs. */
4649 emit_reload_insns (chain);
4651 /* Substitute the chosen reload regs from reload_reg_rtx
4652 into the insn's body (or perhaps into the bodies of other
4653 load and store insn that we just made for reloading
4654 and that we moved the structure into). */
4655 subst_reloads (insn);
4657 prev = PREV_INSN (marker);
4658 unlink_insn_chain (marker, marker);
4660 /* Adjust the exception region notes for loads and stores. */
4661 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4662 fixup_eh_region_note (insn, prev, next);
4664 /* Adjust the location of REG_ARGS_SIZE. */
4665 p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4668 remove_note (insn, p);
4669 fixup_args_size_notes (prev, PREV_INSN (next),
4670 INTVAL (XEXP (p, 0)));
4673 /* If this was an ASM, make sure that all the reload insns
4674 we have generated are valid. If not, give an error
4676 if (asm_noperands (PATTERN (insn)) >= 0)
4677 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4678 if (p != insn && INSN_P (p)
4679 && GET_CODE (PATTERN (p)) != USE
4680 && (recog_memoized (p) < 0
4681 || (extract_insn (p), ! constrain_operands (1))))
4683 error_for_asm (insn,
4684 "%<asm%> operand requires "
4685 "impossible reload");
4690 if (num_eliminable && chain->need_elim)
4691 update_eliminable_offsets ();
4693 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4694 is no longer validly lying around to save a future reload.
4695 Note that this does not detect pseudos that were reloaded
4696 for this insn in order to be stored in
4697 (obeying register constraints). That is correct; such reload
4698 registers ARE still valid. */
4699 forget_marked_reloads (®s_to_forget);
4700 CLEAR_REG_SET (®s_to_forget);
4702 /* There may have been CLOBBER insns placed after INSN. So scan
4703 between INSN and NEXT and use them to forget old reloads. */
4704 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4705 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4706 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4709 /* Likewise for regs altered by auto-increment in this insn.
4710 REG_INC notes have been changed by reloading:
4711 find_reloads_address_1 records substitutions for them,
4712 which have been performed by subst_reloads above. */
4713 for (i = n_reloads - 1; i >= 0; i--)
4715 rtx in_reg = rld[i].in_reg;
4718 enum rtx_code code = GET_CODE (in_reg);
4719 /* PRE_INC / PRE_DEC will have the reload register ending up
4720 with the same value as the stack slot, but that doesn't
4721 hold true for POST_INC / POST_DEC. Either we have to
4722 convert the memory access to a true POST_INC / POST_DEC,
4723 or we can't use the reload register for inheritance. */
4724 if ((code == POST_INC || code == POST_DEC)
4725 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4726 REGNO (rld[i].reg_rtx))
4727 /* Make sure it is the inc/dec pseudo, and not
4728 some other (e.g. output operand) pseudo. */
4729 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4730 == REGNO (XEXP (in_reg, 0))))
4733 rtx reload_reg = rld[i].reg_rtx;
4734 enum machine_mode mode = GET_MODE (reload_reg);
4738 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4740 /* We really want to ignore REG_INC notes here, so
4741 use PATTERN (p) as argument to reg_set_p . */
4742 if (reg_set_p (reload_reg, PATTERN (p)))
4744 n = count_occurrences (PATTERN (p), reload_reg, 0);
4750 = gen_rtx_fmt_e (code, mode, reload_reg);
4752 validate_replace_rtx_group (reload_reg,
4754 n = verify_changes (0);
4756 /* We must also verify that the constraints
4757 are met after the replacement. Make sure
4758 extract_insn is only called for an insn
4759 where the replacements were found to be
4764 n = constrain_operands (1);
4767 /* If the constraints were not met, then
4768 undo the replacement, else confirm it. */
4772 confirm_change_group ();
4778 add_reg_note (p, REG_INC, reload_reg);
4779 /* Mark this as having an output reload so that the
4780 REG_INC processing code below won't invalidate
4781 the reload for inheritance. */
4782 SET_HARD_REG_BIT (reg_is_output_reload,
4783 REGNO (reload_reg));
4784 SET_REGNO_REG_SET (®_has_output_reload,
4785 REGNO (XEXP (in_reg, 0)));
4788 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4791 else if ((code == PRE_INC || code == PRE_DEC)
4792 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4793 REGNO (rld[i].reg_rtx))
4794 /* Make sure it is the inc/dec pseudo, and not
4795 some other (e.g. output operand) pseudo. */
4796 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4797 == REGNO (XEXP (in_reg, 0))))
4799 SET_HARD_REG_BIT (reg_is_output_reload,
4800 REGNO (rld[i].reg_rtx));
4801 SET_REGNO_REG_SET (®_has_output_reload,
4802 REGNO (XEXP (in_reg, 0)));
4804 else if (code == PRE_INC || code == PRE_DEC
4805 || code == POST_INC || code == POST_DEC)
4807 int in_regno = REGNO (XEXP (in_reg, 0));
4809 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4812 bool forget_p = true;
4814 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4815 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4818 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4821 if (x == reg_reloaded_insn[in_hard_regno])
4827 /* If for some reasons, we didn't set up
4828 reg_last_reload_reg in this insn,
4829 invalidate inheritance from previous
4830 insns for the incremented/decremented
4831 register. Such registers will be not in
4832 reg_has_output_reload. Invalidate it
4833 also if the corresponding element in
4834 reg_reloaded_insn is also
4837 forget_old_reloads_1 (XEXP (in_reg, 0),
4843 /* If a pseudo that got a hard register is auto-incremented,
4844 we must purge records of copying it into pseudos without
4846 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4847 if (REG_NOTE_KIND (x) == REG_INC)
4849 /* See if this pseudo reg was reloaded in this insn.
4850 If so, its last-reload info is still valid
4851 because it is based on this insn's reload. */
4852 for (i = 0; i < n_reloads; i++)
4853 if (rld[i].out == XEXP (x, 0))
4857 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4861 /* A reload reg's contents are unknown after a label. */
4863 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4865 /* Don't assume a reload reg is still good after a call insn
4866 if it is a call-used reg, or if it contains a value that will
4867 be partially clobbered by the call. */
4868 else if (CALL_P (insn))
4870 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4871 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4873 /* If this is a call to a setjmp-type function, we must not
4874 reuse any reload reg contents across the call; that will
4875 just be clobbered by other uses of the register in later
4876 code, before the longjmp. */
4877 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4878 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4883 free (reg_last_reload_reg);
4884 CLEAR_REG_SET (®_has_output_reload);
4887 /* Discard all record of any value reloaded from X,
4888 or reloaded in X from someplace else;
4889 unless X is an output reload reg of the current insn.
4891 X may be a hard reg (the reload reg)
4892 or it may be a pseudo reg that was reloaded from.
4894 When DATA is non-NULL just mark the registers in regset
4895 to be forgotten later. */
4898 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4903 regset regs = (regset) data;
4905 /* note_stores does give us subregs of hard regs,
4906 subreg_regno_offset requires a hard reg. */
4907 while (GET_CODE (x) == SUBREG)
4909 /* We ignore the subreg offset when calculating the regno,
4910 because we are using the entire underlying hard register
4920 if (regno >= FIRST_PSEUDO_REGISTER)
4926 nr = hard_regno_nregs[regno][GET_MODE (x)];
4927 /* Storing into a spilled-reg invalidates its contents.
4928 This can happen if a block-local pseudo is allocated to that reg
4929 and it wasn't spilled because this block's total need is 0.
4930 Then some insn might have an optional reload and use this reg. */
4932 for (i = 0; i < nr; i++)
4933 /* But don't do this if the reg actually serves as an output
4934 reload reg in the current instruction. */
4936 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4938 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4939 spill_reg_store[regno + i] = 0;
4945 SET_REGNO_REG_SET (regs, regno + nr);
4948 /* Since value of X has changed,
4949 forget any value previously copied from it. */
4952 /* But don't forget a copy if this is the output reload
4953 that establishes the copy's validity. */
4955 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4956 reg_last_reload_reg[regno + nr] = 0;
4960 /* Forget the reloads marked in regset by previous function. */
4962 forget_marked_reloads (regset regs)
4965 reg_set_iterator rsi;
4966 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4968 if (reg < FIRST_PSEUDO_REGISTER
4969 /* But don't do this if the reg actually serves as an output
4970 reload reg in the current instruction. */
4972 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4974 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4975 spill_reg_store[reg] = 0;
4978 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4979 reg_last_reload_reg[reg] = 0;
4983 /* The following HARD_REG_SETs indicate when each hard register is
4984 used for a reload of various parts of the current insn. */
4986 /* If reg is unavailable for all reloads. */
4987 static HARD_REG_SET reload_reg_unavailable;
4988 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4989 static HARD_REG_SET reload_reg_used;
4990 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4991 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4992 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4993 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4994 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4995 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4996 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4997 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4998 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4999 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5000 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5001 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5002 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5003 static HARD_REG_SET reload_reg_used_in_op_addr;
5004 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5005 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5006 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5007 static HARD_REG_SET reload_reg_used_in_insn;
5008 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5009 static HARD_REG_SET reload_reg_used_in_other_addr;
5011 /* If reg is in use as a reload reg for any sort of reload. */
5012 static HARD_REG_SET reload_reg_used_at_all;
5014 /* If reg is use as an inherited reload. We just mark the first register
5016 static HARD_REG_SET reload_reg_used_for_inherit;
5018 /* Records which hard regs are used in any way, either as explicit use or
5019 by being allocated to a pseudo during any point of the current insn. */
5020 static HARD_REG_SET reg_used_in_insn;
5022 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5023 TYPE. MODE is used to indicate how many consecutive regs are
5027 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5028 enum machine_mode mode)
5033 add_to_hard_reg_set (&reload_reg_used, mode, regno);
5036 case RELOAD_FOR_INPUT_ADDRESS:
5037 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5040 case RELOAD_FOR_INPADDR_ADDRESS:
5041 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5044 case RELOAD_FOR_OUTPUT_ADDRESS:
5045 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5048 case RELOAD_FOR_OUTADDR_ADDRESS:
5049 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5052 case RELOAD_FOR_OPERAND_ADDRESS:
5053 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5056 case RELOAD_FOR_OPADDR_ADDR:
5057 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5060 case RELOAD_FOR_OTHER_ADDRESS:
5061 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5064 case RELOAD_FOR_INPUT:
5065 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5068 case RELOAD_FOR_OUTPUT:
5069 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5072 case RELOAD_FOR_INSN:
5073 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5077 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5080 /* Similarly, but show REGNO is no longer in use for a reload. */
5083 clear_reload_reg_in_use (unsigned int regno, int opnum,
5084 enum reload_type type, enum machine_mode mode)
5086 unsigned int nregs = hard_regno_nregs[regno][mode];
5087 unsigned int start_regno, end_regno, r;
5089 /* A complication is that for some reload types, inheritance might
5090 allow multiple reloads of the same types to share a reload register.
5091 We set check_opnum if we have to check only reloads with the same
5092 operand number, and check_any if we have to check all reloads. */
5093 int check_opnum = 0;
5095 HARD_REG_SET *used_in_set;
5100 used_in_set = &reload_reg_used;
5103 case RELOAD_FOR_INPUT_ADDRESS:
5104 used_in_set = &reload_reg_used_in_input_addr[opnum];
5107 case RELOAD_FOR_INPADDR_ADDRESS:
5109 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5112 case RELOAD_FOR_OUTPUT_ADDRESS:
5113 used_in_set = &reload_reg_used_in_output_addr[opnum];
5116 case RELOAD_FOR_OUTADDR_ADDRESS:
5118 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5121 case RELOAD_FOR_OPERAND_ADDRESS:
5122 used_in_set = &reload_reg_used_in_op_addr;
5125 case RELOAD_FOR_OPADDR_ADDR:
5127 used_in_set = &reload_reg_used_in_op_addr_reload;
5130 case RELOAD_FOR_OTHER_ADDRESS:
5131 used_in_set = &reload_reg_used_in_other_addr;
5135 case RELOAD_FOR_INPUT:
5136 used_in_set = &reload_reg_used_in_input[opnum];
5139 case RELOAD_FOR_OUTPUT:
5140 used_in_set = &reload_reg_used_in_output[opnum];
5143 case RELOAD_FOR_INSN:
5144 used_in_set = &reload_reg_used_in_insn;
5149 /* We resolve conflicts with remaining reloads of the same type by
5150 excluding the intervals of reload registers by them from the
5151 interval of freed reload registers. Since we only keep track of
5152 one set of interval bounds, we might have to exclude somewhat
5153 more than what would be necessary if we used a HARD_REG_SET here.
5154 But this should only happen very infrequently, so there should
5155 be no reason to worry about it. */
5157 start_regno = regno;
5158 end_regno = regno + nregs;
5159 if (check_opnum || check_any)
5161 for (i = n_reloads - 1; i >= 0; i--)
5163 if (rld[i].when_needed == type
5164 && (check_any || rld[i].opnum == opnum)
5167 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5168 unsigned int conflict_end
5169 = end_hard_regno (rld[i].mode, conflict_start);
5171 /* If there is an overlap with the first to-be-freed register,
5172 adjust the interval start. */
5173 if (conflict_start <= start_regno && conflict_end > start_regno)
5174 start_regno = conflict_end;
5175 /* Otherwise, if there is a conflict with one of the other
5176 to-be-freed registers, adjust the interval end. */
5177 if (conflict_start > start_regno && conflict_start < end_regno)
5178 end_regno = conflict_start;
5183 for (r = start_regno; r < end_regno; r++)
5184 CLEAR_HARD_REG_BIT (*used_in_set, r);
5187 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5188 specified by OPNUM and TYPE. */
5191 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5195 /* In use for a RELOAD_OTHER means it's not available for anything. */
5196 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5197 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5203 /* In use for anything means we can't use it for RELOAD_OTHER. */
5204 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5205 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5206 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5207 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5210 for (i = 0; i < reload_n_operands; i++)
5211 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5212 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5213 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5214 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5215 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5216 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5221 case RELOAD_FOR_INPUT:
5222 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5223 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5226 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5229 /* If it is used for some other input, can't use it. */
5230 for (i = 0; i < reload_n_operands; i++)
5231 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5234 /* If it is used in a later operand's address, can't use it. */
5235 for (i = opnum + 1; i < reload_n_operands; i++)
5236 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5237 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5242 case RELOAD_FOR_INPUT_ADDRESS:
5243 /* Can't use a register if it is used for an input address for this
5244 operand or used as an input in an earlier one. */
5245 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5246 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5249 for (i = 0; i < opnum; i++)
5250 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5255 case RELOAD_FOR_INPADDR_ADDRESS:
5256 /* Can't use a register if it is used for an input address
5257 for this operand or used as an input in an earlier
5259 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5262 for (i = 0; i < opnum; i++)
5263 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5268 case RELOAD_FOR_OUTPUT_ADDRESS:
5269 /* Can't use a register if it is used for an output address for this
5270 operand or used as an output in this or a later operand. Note
5271 that multiple output operands are emitted in reverse order, so
5272 the conflicting ones are those with lower indices. */
5273 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5276 for (i = 0; i <= opnum; i++)
5277 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5282 case RELOAD_FOR_OUTADDR_ADDRESS:
5283 /* Can't use a register if it is used for an output address
5284 for this operand or used as an output in this or a
5285 later operand. Note that multiple output operands are
5286 emitted in reverse order, so the conflicting ones are
5287 those with lower indices. */
5288 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5291 for (i = 0; i <= opnum; i++)
5292 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5297 case RELOAD_FOR_OPERAND_ADDRESS:
5298 for (i = 0; i < reload_n_operands; i++)
5299 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5302 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5303 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5305 case RELOAD_FOR_OPADDR_ADDR:
5306 for (i = 0; i < reload_n_operands; i++)
5307 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5310 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5312 case RELOAD_FOR_OUTPUT:
5313 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5314 outputs, or an operand address for this or an earlier output.
5315 Note that multiple output operands are emitted in reverse order,
5316 so the conflicting ones are those with higher indices. */
5317 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5320 for (i = 0; i < reload_n_operands; i++)
5321 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5324 for (i = opnum; i < reload_n_operands; i++)
5325 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5326 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5331 case RELOAD_FOR_INSN:
5332 for (i = 0; i < reload_n_operands; i++)
5333 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5334 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5337 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5338 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5340 case RELOAD_FOR_OTHER_ADDRESS:
5341 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5348 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5349 the number RELOADNUM, is still available in REGNO at the end of the insn.
5351 We can assume that the reload reg was already tested for availability
5352 at the time it is needed, and we should not check this again,
5353 in case the reg has already been marked in use. */
5356 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5358 int opnum = rld[reloadnum].opnum;
5359 enum reload_type type = rld[reloadnum].when_needed;
5362 /* See if there is a reload with the same type for this operand, using
5363 the same register. This case is not handled by the code below. */
5364 for (i = reloadnum + 1; i < n_reloads; i++)
5369 if (rld[i].opnum != opnum || rld[i].when_needed != type)
5371 reg = rld[i].reg_rtx;
5372 if (reg == NULL_RTX)
5374 nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5375 if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5382 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5383 its value must reach the end. */
5386 /* If this use is for part of the insn,
5387 its value reaches if no subsequent part uses the same register.
5388 Just like the above function, don't try to do this with lots
5391 case RELOAD_FOR_OTHER_ADDRESS:
5392 /* Here we check for everything else, since these don't conflict
5393 with anything else and everything comes later. */
5395 for (i = 0; i < reload_n_operands; i++)
5396 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5397 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5398 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5399 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5400 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5401 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5404 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5405 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5406 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5407 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5409 case RELOAD_FOR_INPUT_ADDRESS:
5410 case RELOAD_FOR_INPADDR_ADDRESS:
5411 /* Similar, except that we check only for this and subsequent inputs
5412 and the address of only subsequent inputs and we do not need
5413 to check for RELOAD_OTHER objects since they are known not to
5416 for (i = opnum; i < reload_n_operands; i++)
5417 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5420 for (i = opnum + 1; i < reload_n_operands; i++)
5421 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5422 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5425 for (i = 0; i < reload_n_operands; i++)
5426 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5427 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5428 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5431 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5434 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5435 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5436 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5438 case RELOAD_FOR_INPUT:
5439 /* Similar to input address, except we start at the next operand for
5440 both input and input address and we do not check for
5441 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5444 for (i = opnum + 1; i < reload_n_operands; i++)
5445 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5446 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5447 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5450 /* ... fall through ... */
5452 case RELOAD_FOR_OPERAND_ADDRESS:
5453 /* Check outputs and their addresses. */
5455 for (i = 0; i < reload_n_operands; i++)
5456 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5457 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5458 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5461 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5463 case RELOAD_FOR_OPADDR_ADDR:
5464 for (i = 0; i < reload_n_operands; i++)
5465 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5466 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5467 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5470 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5471 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5472 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5474 case RELOAD_FOR_INSN:
5475 /* These conflict with other outputs with RELOAD_OTHER. So
5476 we need only check for output addresses. */
5478 opnum = reload_n_operands;
5480 /* ... fall through ... */
5482 case RELOAD_FOR_OUTPUT:
5483 case RELOAD_FOR_OUTPUT_ADDRESS:
5484 case RELOAD_FOR_OUTADDR_ADDRESS:
5485 /* We already know these can't conflict with a later output. So the
5486 only thing to check are later output addresses.
5487 Note that multiple output operands are emitted in reverse order,
5488 so the conflicting ones are those with lower indices. */
5489 for (i = 0; i < opnum; i++)
5490 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5491 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5501 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5502 every register in the range [REGNO, REGNO + NREGS). */
5505 reload_regs_reach_end_p (unsigned int regno, int nregs, int reloadnum)
5509 for (i = 0; i < nregs; i++)
5510 if (!reload_reg_reaches_end_p (regno + i, reloadnum))
5516 /* Returns whether R1 and R2 are uniquely chained: the value of one
5517 is used by the other, and that value is not used by any other
5518 reload for this insn. This is used to partially undo the decision
5519 made in find_reloads when in the case of multiple
5520 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5521 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5522 reloads. This code tries to avoid the conflict created by that
5523 change. It might be cleaner to explicitly keep track of which
5524 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5525 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5526 this after the fact. */
5528 reloads_unique_chain_p (int r1, int r2)
5532 /* We only check input reloads. */
5533 if (! rld[r1].in || ! rld[r2].in)
5536 /* Avoid anything with output reloads. */
5537 if (rld[r1].out || rld[r2].out)
5540 /* "chained" means one reload is a component of the other reload,
5541 not the same as the other reload. */
5542 if (rld[r1].opnum != rld[r2].opnum
5543 || rtx_equal_p (rld[r1].in, rld[r2].in)
5544 || rld[r1].optional || rld[r2].optional
5545 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5546 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5549 for (i = 0; i < n_reloads; i ++)
5550 /* Look for input reloads that aren't our two */
5551 if (i != r1 && i != r2 && rld[i].in)
5553 /* If our reload is mentioned at all, it isn't a simple chain. */
5554 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5560 /* The recursive function change all occurrences of WHAT in *WHERE
5563 substitute (rtx *where, const_rtx what, rtx repl)
5572 if (*where == what || rtx_equal_p (*where, what))
5574 /* Record the location of the changed rtx. */
5575 VEC_safe_push (rtx_p, heap, substitute_stack, where);
5580 code = GET_CODE (*where);
5581 fmt = GET_RTX_FORMAT (code);
5582 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5588 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5589 substitute (&XVECEXP (*where, i, j), what, repl);
5591 else if (fmt[i] == 'e')
5592 substitute (&XEXP (*where, i), what, repl);
5596 /* The function returns TRUE if chain of reload R1 and R2 (in any
5597 order) can be evaluated without usage of intermediate register for
5598 the reload containing another reload. It is important to see
5599 gen_reload to understand what the function is trying to do. As an
5600 example, let us have reload chain
5603 r1: <something> + const
5605 and reload R2 got reload reg HR. The function returns true if
5606 there is a correct insn HR = HR + <something>. Otherwise,
5607 gen_reload will use intermediate register (and this is the reload
5608 reg for R1) to reload <something>.
5610 We need this function to find a conflict for chain reloads. In our
5611 example, if HR = HR + <something> is incorrect insn, then we cannot
5612 use HR as a reload register for R2. If we do use it then we get a
5621 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5623 /* Assume other cases in gen_reload are not possible for
5624 chain reloads or do need an intermediate hard registers. */
5628 rtx last = get_last_insn ();
5630 /* Make r2 a component of r1. */
5631 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5637 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5638 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5639 gcc_assert (regno >= 0);
5640 out = gen_rtx_REG (rld[r1].mode, regno);
5642 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5644 /* If IN is a paradoxical SUBREG, remove it and try to put the
5645 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5646 strip_paradoxical_subreg (&in, &out);
5648 if (GET_CODE (in) == PLUS
5649 && (REG_P (XEXP (in, 0))
5650 || GET_CODE (XEXP (in, 0)) == SUBREG
5651 || MEM_P (XEXP (in, 0)))
5652 && (REG_P (XEXP (in, 1))
5653 || GET_CODE (XEXP (in, 1)) == SUBREG
5654 || CONSTANT_P (XEXP (in, 1))
5655 || MEM_P (XEXP (in, 1))))
5657 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5658 code = recog_memoized (insn);
5663 extract_insn (insn);
5664 /* We want constrain operands to treat this insn strictly in
5665 its validity determination, i.e., the way it would after
5666 reload has completed. */
5667 result = constrain_operands (1);
5670 delete_insns_since (last);
5673 /* Restore the original value at each changed address within R1. */
5674 while (!VEC_empty (rtx_p, substitute_stack))
5676 rtx *where = VEC_pop (rtx_p, substitute_stack);
5677 *where = rld[r2].in;
5683 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5686 This function uses the same algorithm as reload_reg_free_p above. */
5689 reloads_conflict (int r1, int r2)
5691 enum reload_type r1_type = rld[r1].when_needed;
5692 enum reload_type r2_type = rld[r2].when_needed;
5693 int r1_opnum = rld[r1].opnum;
5694 int r2_opnum = rld[r2].opnum;
5696 /* RELOAD_OTHER conflicts with everything. */
5697 if (r2_type == RELOAD_OTHER)
5700 /* Otherwise, check conflicts differently for each type. */
5704 case RELOAD_FOR_INPUT:
5705 return (r2_type == RELOAD_FOR_INSN
5706 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5707 || r2_type == RELOAD_FOR_OPADDR_ADDR
5708 || r2_type == RELOAD_FOR_INPUT
5709 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5710 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5711 && r2_opnum > r1_opnum));
5713 case RELOAD_FOR_INPUT_ADDRESS:
5714 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5715 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5717 case RELOAD_FOR_INPADDR_ADDRESS:
5718 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5719 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5721 case RELOAD_FOR_OUTPUT_ADDRESS:
5722 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5723 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5725 case RELOAD_FOR_OUTADDR_ADDRESS:
5726 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5727 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5729 case RELOAD_FOR_OPERAND_ADDRESS:
5730 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5731 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5732 && (!reloads_unique_chain_p (r1, r2)
5733 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5735 case RELOAD_FOR_OPADDR_ADDR:
5736 return (r2_type == RELOAD_FOR_INPUT
5737 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5739 case RELOAD_FOR_OUTPUT:
5740 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5741 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5742 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5743 && r2_opnum >= r1_opnum));
5745 case RELOAD_FOR_INSN:
5746 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5747 || r2_type == RELOAD_FOR_INSN
5748 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5750 case RELOAD_FOR_OTHER_ADDRESS:
5751 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5761 /* Indexed by reload number, 1 if incoming value
5762 inherited from previous insns. */
5763 static char reload_inherited[MAX_RELOADS];
5765 /* For an inherited reload, this is the insn the reload was inherited from,
5766 if we know it. Otherwise, this is 0. */
5767 static rtx reload_inheritance_insn[MAX_RELOADS];
5769 /* If nonzero, this is a place to get the value of the reload,
5770 rather than using reload_in. */
5771 static rtx reload_override_in[MAX_RELOADS];
5773 /* For each reload, the hard register number of the register used,
5774 or -1 if we did not need a register for this reload. */
5775 static int reload_spill_index[MAX_RELOADS];
5777 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5778 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5780 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5781 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5783 /* Subroutine of free_for_value_p, used to check a single register.
5784 START_REGNO is the starting regno of the full reload register
5785 (possibly comprising multiple hard registers) that we are considering. */
5788 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5789 enum reload_type type, rtx value, rtx out,
5790 int reloadnum, int ignore_address_reloads)
5793 /* Set if we see an input reload that must not share its reload register
5794 with any new earlyclobber, but might otherwise share the reload
5795 register with an output or input-output reload. */
5796 int check_earlyclobber = 0;
5800 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5803 if (out == const0_rtx)
5809 /* We use some pseudo 'time' value to check if the lifetimes of the
5810 new register use would overlap with the one of a previous reload
5811 that is not read-only or uses a different value.
5812 The 'time' used doesn't have to be linear in any shape or form, just
5814 Some reload types use different 'buckets' for each operand.
5815 So there are MAX_RECOG_OPERANDS different time values for each
5817 We compute TIME1 as the time when the register for the prospective
5818 new reload ceases to be live, and TIME2 for each existing
5819 reload as the time when that the reload register of that reload
5821 Where there is little to be gained by exact lifetime calculations,
5822 we just make conservative assumptions, i.e. a longer lifetime;
5823 this is done in the 'default:' cases. */
5826 case RELOAD_FOR_OTHER_ADDRESS:
5827 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5828 time1 = copy ? 0 : 1;
5831 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5833 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5834 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5835 respectively, to the time values for these, we get distinct time
5836 values. To get distinct time values for each operand, we have to
5837 multiply opnum by at least three. We round that up to four because
5838 multiply by four is often cheaper. */
5839 case RELOAD_FOR_INPADDR_ADDRESS:
5840 time1 = opnum * 4 + 2;
5842 case RELOAD_FOR_INPUT_ADDRESS:
5843 time1 = opnum * 4 + 3;
5845 case RELOAD_FOR_INPUT:
5846 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5847 executes (inclusive). */
5848 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5850 case RELOAD_FOR_OPADDR_ADDR:
5852 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5853 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5855 case RELOAD_FOR_OPERAND_ADDRESS:
5856 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5858 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5860 case RELOAD_FOR_OUTADDR_ADDRESS:
5861 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5863 case RELOAD_FOR_OUTPUT_ADDRESS:
5864 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5867 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5870 for (i = 0; i < n_reloads; i++)
5872 rtx reg = rld[i].reg_rtx;
5873 if (reg && REG_P (reg)
5874 && ((unsigned) regno - true_regnum (reg)
5875 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5878 rtx other_input = rld[i].in;
5880 /* If the other reload loads the same input value, that
5881 will not cause a conflict only if it's loading it into
5882 the same register. */
5883 if (true_regnum (reg) != start_regno)
5884 other_input = NULL_RTX;
5885 if (! other_input || ! rtx_equal_p (other_input, value)
5886 || rld[i].out || out)
5889 switch (rld[i].when_needed)
5891 case RELOAD_FOR_OTHER_ADDRESS:
5894 case RELOAD_FOR_INPADDR_ADDRESS:
5895 /* find_reloads makes sure that a
5896 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5897 by at most one - the first -
5898 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5899 address reload is inherited, the address address reload
5900 goes away, so we can ignore this conflict. */
5901 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5902 && ignore_address_reloads
5903 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5904 Then the address address is still needed to store
5905 back the new address. */
5906 && ! rld[reloadnum].out)
5908 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5909 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5911 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5912 && ignore_address_reloads
5913 /* Unless we are reloading an auto_inc expression. */
5914 && ! rld[reloadnum].out)
5916 time2 = rld[i].opnum * 4 + 2;
5918 case RELOAD_FOR_INPUT_ADDRESS:
5919 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5920 && ignore_address_reloads
5921 && ! rld[reloadnum].out)
5923 time2 = rld[i].opnum * 4 + 3;
5925 case RELOAD_FOR_INPUT:
5926 time2 = rld[i].opnum * 4 + 4;
5927 check_earlyclobber = 1;
5929 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5930 == MAX_RECOG_OPERAND * 4 */
5931 case RELOAD_FOR_OPADDR_ADDR:
5932 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5933 && ignore_address_reloads
5934 && ! rld[reloadnum].out)
5936 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5938 case RELOAD_FOR_OPERAND_ADDRESS:
5939 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5940 check_earlyclobber = 1;
5942 case RELOAD_FOR_INSN:
5943 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5945 case RELOAD_FOR_OUTPUT:
5946 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5947 instruction is executed. */
5948 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5950 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5951 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5953 case RELOAD_FOR_OUTADDR_ADDRESS:
5954 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5955 && ignore_address_reloads
5956 && ! rld[reloadnum].out)
5958 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5960 case RELOAD_FOR_OUTPUT_ADDRESS:
5961 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5964 /* If there is no conflict in the input part, handle this
5965 like an output reload. */
5966 if (! rld[i].in || rtx_equal_p (other_input, value))
5968 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5969 /* Earlyclobbered outputs must conflict with inputs. */
5970 if (earlyclobber_operand_p (rld[i].out))
5971 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5976 /* RELOAD_OTHER might be live beyond instruction execution,
5977 but this is not obvious when we set time2 = 1. So check
5978 here if there might be a problem with the new reload
5979 clobbering the register used by the RELOAD_OTHER. */
5987 && (! rld[i].in || rld[i].out
5988 || ! rtx_equal_p (other_input, value)))
5989 || (out && rld[reloadnum].out_reg
5990 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5996 /* Earlyclobbered outputs must conflict with inputs. */
5997 if (check_earlyclobber && out && earlyclobber_operand_p (out))
6003 /* Return 1 if the value in reload reg REGNO, as used by a reload
6004 needed for the part of the insn specified by OPNUM and TYPE,
6005 may be used to load VALUE into it.
6007 MODE is the mode in which the register is used, this is needed to
6008 determine how many hard regs to test.
6010 Other read-only reloads with the same value do not conflict
6011 unless OUT is nonzero and these other reloads have to live while
6012 output reloads live.
6013 If OUT is CONST0_RTX, this is a special case: it means that the
6014 test should not be for using register REGNO as reload register, but
6015 for copying from register REGNO into the reload register.
6017 RELOADNUM is the number of the reload we want to load this value for;
6018 a reload does not conflict with itself.
6020 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6021 reloads that load an address for the very reload we are considering.
6023 The caller has to make sure that there is no conflict with the return
6027 free_for_value_p (int regno, enum machine_mode mode, int opnum,
6028 enum reload_type type, rtx value, rtx out, int reloadnum,
6029 int ignore_address_reloads)
6031 int nregs = hard_regno_nregs[regno][mode];
6033 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6034 value, out, reloadnum,
6035 ignore_address_reloads))
6040 /* Return nonzero if the rtx X is invariant over the current function. */
6041 /* ??? Actually, the places where we use this expect exactly what is
6042 tested here, and not everything that is function invariant. In
6043 particular, the frame pointer and arg pointer are special cased;
6044 pic_offset_table_rtx is not, and we must not spill these things to
6048 function_invariant_p (const_rtx x)
6052 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6054 if (GET_CODE (x) == PLUS
6055 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6056 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6061 /* Determine whether the reload reg X overlaps any rtx'es used for
6062 overriding inheritance. Return nonzero if so. */
6065 conflicts_with_override (rtx x)
6068 for (i = 0; i < n_reloads; i++)
6069 if (reload_override_in[i]
6070 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6075 /* Give an error message saying we failed to find a reload for INSN,
6076 and clear out reload R. */
6078 failed_reload (rtx insn, int r)
6080 if (asm_noperands (PATTERN (insn)) < 0)
6081 /* It's the compiler's fault. */
6082 fatal_insn ("could not find a spill register", insn);
6084 /* It's the user's fault; the operand's mode and constraint
6085 don't match. Disable this reload so we don't crash in final. */
6086 error_for_asm (insn,
6087 "%<asm%> operand constraint incompatible with operand size");
6091 rld[r].optional = 1;
6092 rld[r].secondary_p = 1;
6095 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6096 for reload R. If it's valid, get an rtx for it. Return nonzero if
6099 set_reload_reg (int i, int r)
6101 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6103 int regno ATTRIBUTE_UNUSED;
6104 rtx reg = spill_reg_rtx[i];
6106 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6107 spill_reg_rtx[i] = reg
6108 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6110 regno = true_regnum (reg);
6112 /* Detect when the reload reg can't hold the reload mode.
6113 This used to be one `if', but Sequent compiler can't handle that. */
6114 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6116 enum machine_mode test_mode = VOIDmode;
6118 test_mode = GET_MODE (rld[r].in);
6119 /* If rld[r].in has VOIDmode, it means we will load it
6120 in whatever mode the reload reg has: to wit, rld[r].mode.
6121 We have already tested that for validity. */
6122 /* Aside from that, we need to test that the expressions
6123 to reload from or into have modes which are valid for this
6124 reload register. Otherwise the reload insns would be invalid. */
6125 if (! (rld[r].in != 0 && test_mode != VOIDmode
6126 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6127 if (! (rld[r].out != 0
6128 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6130 /* The reg is OK. */
6133 /* Mark as in use for this insn the reload regs we use
6135 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6136 rld[r].when_needed, rld[r].mode);
6138 rld[r].reg_rtx = reg;
6139 reload_spill_index[r] = spill_regs[i];
6146 /* Find a spill register to use as a reload register for reload R.
6147 LAST_RELOAD is nonzero if this is the last reload for the insn being
6150 Set rld[R].reg_rtx to the register allocated.
6152 We return 1 if successful, or 0 if we couldn't find a spill reg and
6153 we didn't change anything. */
6156 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6161 /* If we put this reload ahead, thinking it is a group,
6162 then insist on finding a group. Otherwise we can grab a
6163 reg that some other reload needs.
6164 (That can happen when we have a 68000 DATA_OR_FP_REG
6165 which is a group of data regs or one fp reg.)
6166 We need not be so restrictive if there are no more reloads
6169 ??? Really it would be nicer to have smarter handling
6170 for that kind of reg class, where a problem like this is normal.
6171 Perhaps those classes should be avoided for reloading
6172 by use of more alternatives. */
6174 int force_group = rld[r].nregs > 1 && ! last_reload;
6176 /* If we want a single register and haven't yet found one,
6177 take any reg in the right class and not in use.
6178 If we want a consecutive group, here is where we look for it.
6180 We use three passes so we can first look for reload regs to
6181 reuse, which are already in use for other reloads in this insn,
6182 and only then use additional registers which are not "bad", then
6183 finally any register.
6185 I think that maximizing reuse is needed to make sure we don't
6186 run out of reload regs. Suppose we have three reloads, and
6187 reloads A and B can share regs. These need two regs.
6188 Suppose A and B are given different regs.
6189 That leaves none for C. */
6190 for (pass = 0; pass < 3; pass++)
6192 /* I is the index in spill_regs.
6193 We advance it round-robin between insns to use all spill regs
6194 equally, so that inherited reloads have a chance
6195 of leapfrogging each other. */
6199 for (count = 0; count < n_spills; count++)
6201 int rclass = (int) rld[r].rclass;
6207 regnum = spill_regs[i];
6209 if ((reload_reg_free_p (regnum, rld[r].opnum,
6212 /* We check reload_reg_used to make sure we
6213 don't clobber the return register. */
6214 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6215 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6216 rld[r].when_needed, rld[r].in,
6218 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6219 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6220 /* Look first for regs to share, then for unshared. But
6221 don't share regs used for inherited reloads; they are
6222 the ones we want to preserve. */
6224 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6226 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6229 int nr = hard_regno_nregs[regnum][rld[r].mode];
6231 /* During the second pass we want to avoid reload registers
6232 which are "bad" for this reload. */
6234 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6237 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6238 (on 68000) got us two FP regs. If NR is 1,
6239 we would reject both of them. */
6242 /* If we need only one reg, we have already won. */
6245 /* But reject a single reg if we demand a group. */
6250 /* Otherwise check that as many consecutive regs as we need
6251 are available here. */
6254 int regno = regnum + nr - 1;
6255 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6256 && spill_reg_order[regno] >= 0
6257 && reload_reg_free_p (regno, rld[r].opnum,
6258 rld[r].when_needed)))
6267 /* If we found something on the current pass, omit later passes. */
6268 if (count < n_spills)
6272 /* We should have found a spill register by now. */
6273 if (count >= n_spills)
6276 /* I is the index in SPILL_REG_RTX of the reload register we are to
6277 allocate. Get an rtx for it and find its register number. */
6279 return set_reload_reg (i, r);
6282 /* Initialize all the tables needed to allocate reload registers.
6283 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6284 is the array we use to restore the reg_rtx field for every reload. */
6287 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6291 for (i = 0; i < n_reloads; i++)
6292 rld[i].reg_rtx = save_reload_reg_rtx[i];
6294 memset (reload_inherited, 0, MAX_RELOADS);
6295 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6296 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6298 CLEAR_HARD_REG_SET (reload_reg_used);
6299 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6300 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6301 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6302 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6303 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6305 CLEAR_HARD_REG_SET (reg_used_in_insn);
6308 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6309 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6310 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6311 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6312 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
6313 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
6316 for (i = 0; i < reload_n_operands; i++)
6318 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6319 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6320 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6321 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6322 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6323 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6326 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6328 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6330 for (i = 0; i < n_reloads; i++)
6331 /* If we have already decided to use a certain register,
6332 don't use it in another way. */
6334 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6335 rld[i].when_needed, rld[i].mode);
6338 /* Assign hard reg targets for the pseudo-registers we must reload
6339 into hard regs for this insn.
6340 Also output the instructions to copy them in and out of the hard regs.
6342 For machines with register classes, we are responsible for
6343 finding a reload reg in the proper class. */
6346 choose_reload_regs (struct insn_chain *chain)
6348 rtx insn = chain->insn;
6350 unsigned int max_group_size = 1;
6351 enum reg_class group_class = NO_REGS;
6352 int pass, win, inheritance;
6354 rtx save_reload_reg_rtx[MAX_RELOADS];
6356 /* In order to be certain of getting the registers we need,
6357 we must sort the reloads into order of increasing register class.
6358 Then our grabbing of reload registers will parallel the process
6359 that provided the reload registers.
6361 Also note whether any of the reloads wants a consecutive group of regs.
6362 If so, record the maximum size of the group desired and what
6363 register class contains all the groups needed by this insn. */
6365 for (j = 0; j < n_reloads; j++)
6367 reload_order[j] = j;
6368 if (rld[j].reg_rtx != NULL_RTX)
6370 gcc_assert (REG_P (rld[j].reg_rtx)
6371 && HARD_REGISTER_P (rld[j].reg_rtx));
6372 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6375 reload_spill_index[j] = -1;
6377 if (rld[j].nregs > 1)
6379 max_group_size = MAX (rld[j].nregs, max_group_size);
6381 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6384 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6388 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6390 /* If -O, try first with inheritance, then turning it off.
6391 If not -O, don't do inheritance.
6392 Using inheritance when not optimizing leads to paradoxes
6393 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6394 because one side of the comparison might be inherited. */
6396 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6398 choose_reload_regs_init (chain, save_reload_reg_rtx);
6400 /* Process the reloads in order of preference just found.
6401 Beyond this point, subregs can be found in reload_reg_rtx.
6403 This used to look for an existing reloaded home for all of the
6404 reloads, and only then perform any new reloads. But that could lose
6405 if the reloads were done out of reg-class order because a later
6406 reload with a looser constraint might have an old home in a register
6407 needed by an earlier reload with a tighter constraint.
6409 To solve this, we make two passes over the reloads, in the order
6410 described above. In the first pass we try to inherit a reload
6411 from a previous insn. If there is a later reload that needs a
6412 class that is a proper subset of the class being processed, we must
6413 also allocate a spill register during the first pass.
6415 Then make a second pass over the reloads to allocate any reloads
6416 that haven't been given registers yet. */
6418 for (j = 0; j < n_reloads; j++)
6420 int r = reload_order[j];
6421 rtx search_equiv = NULL_RTX;
6423 /* Ignore reloads that got marked inoperative. */
6424 if (rld[r].out == 0 && rld[r].in == 0
6425 && ! rld[r].secondary_p)
6428 /* If find_reloads chose to use reload_in or reload_out as a reload
6429 register, we don't need to chose one. Otherwise, try even if it
6430 found one since we might save an insn if we find the value lying
6432 Try also when reload_in is a pseudo without a hard reg. */
6433 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6434 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6435 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6436 && !MEM_P (rld[r].in)
6437 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6440 #if 0 /* No longer needed for correct operation.
6441 It might give better code, or might not; worth an experiment? */
6442 /* If this is an optional reload, we can't inherit from earlier insns
6443 until we are sure that any non-optional reloads have been allocated.
6444 The following code takes advantage of the fact that optional reloads
6445 are at the end of reload_order. */
6446 if (rld[r].optional != 0)
6447 for (i = 0; i < j; i++)
6448 if ((rld[reload_order[i]].out != 0
6449 || rld[reload_order[i]].in != 0
6450 || rld[reload_order[i]].secondary_p)
6451 && ! rld[reload_order[i]].optional
6452 && rld[reload_order[i]].reg_rtx == 0)
6453 allocate_reload_reg (chain, reload_order[i], 0);
6456 /* First see if this pseudo is already available as reloaded
6457 for a previous insn. We cannot try to inherit for reloads
6458 that are smaller than the maximum number of registers needed
6459 for groups unless the register we would allocate cannot be used
6462 We could check here to see if this is a secondary reload for
6463 an object that is already in a register of the desired class.
6464 This would avoid the need for the secondary reload register.
6465 But this is complex because we can't easily determine what
6466 objects might want to be loaded via this reload. So let a
6467 register be allocated here. In `emit_reload_insns' we suppress
6468 one of the loads in the case described above. */
6474 enum machine_mode mode = VOIDmode;
6478 else if (REG_P (rld[r].in))
6480 regno = REGNO (rld[r].in);
6481 mode = GET_MODE (rld[r].in);
6483 else if (REG_P (rld[r].in_reg))
6485 regno = REGNO (rld[r].in_reg);
6486 mode = GET_MODE (rld[r].in_reg);
6488 else if (GET_CODE (rld[r].in_reg) == SUBREG
6489 && REG_P (SUBREG_REG (rld[r].in_reg)))
6491 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6492 if (regno < FIRST_PSEUDO_REGISTER)
6493 regno = subreg_regno (rld[r].in_reg);
6495 byte = SUBREG_BYTE (rld[r].in_reg);
6496 mode = GET_MODE (rld[r].in_reg);
6499 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6500 && REG_P (XEXP (rld[r].in_reg, 0)))
6502 regno = REGNO (XEXP (rld[r].in_reg, 0));
6503 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6504 rld[r].out = rld[r].in;
6508 /* This won't work, since REGNO can be a pseudo reg number.
6509 Also, it takes much more hair to keep track of all the things
6510 that can invalidate an inherited reload of part of a pseudoreg. */
6511 else if (GET_CODE (rld[r].in) == SUBREG
6512 && REG_P (SUBREG_REG (rld[r].in)))
6513 regno = subreg_regno (rld[r].in);
6517 && reg_last_reload_reg[regno] != 0
6518 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6519 >= GET_MODE_SIZE (mode) + byte)
6520 #ifdef CANNOT_CHANGE_MODE_CLASS
6521 /* Verify that the register it's in can be used in
6523 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6524 GET_MODE (reg_last_reload_reg[regno]),
6529 enum reg_class rclass = rld[r].rclass, last_class;
6530 rtx last_reg = reg_last_reload_reg[regno];
6532 i = REGNO (last_reg);
6533 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6534 last_class = REGNO_REG_CLASS (i);
6536 if (reg_reloaded_contents[i] == regno
6537 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6538 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6539 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6540 /* Even if we can't use this register as a reload
6541 register, we might use it for reload_override_in,
6542 if copying it to the desired class is cheap
6544 || ((register_move_cost (mode, last_class, rclass)
6545 < memory_move_cost (mode, rclass, true))
6546 && (secondary_reload_class (1, rclass, mode,
6549 #ifdef SECONDARY_MEMORY_NEEDED
6550 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6555 && (rld[r].nregs == max_group_size
6556 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6558 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6559 rld[r].when_needed, rld[r].in,
6562 /* If a group is needed, verify that all the subsequent
6563 registers still have their values intact. */
6564 int nr = hard_regno_nregs[i][rld[r].mode];
6567 for (k = 1; k < nr; k++)
6568 if (reg_reloaded_contents[i + k] != regno
6569 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6577 last_reg = (GET_MODE (last_reg) == mode
6578 ? last_reg : gen_rtx_REG (mode, i));
6581 for (k = 0; k < nr; k++)
6582 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6585 /* We found a register that contains the
6586 value we need. If this register is the
6587 same as an `earlyclobber' operand of the
6588 current insn, just mark it as a place to
6589 reload from since we can't use it as the
6590 reload register itself. */
6592 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6593 if (reg_overlap_mentioned_for_reload_p
6594 (reg_last_reload_reg[regno],
6595 reload_earlyclobbers[i1]))
6598 if (i1 != n_earlyclobbers
6599 || ! (free_for_value_p (i, rld[r].mode,
6601 rld[r].when_needed, rld[r].in,
6603 /* Don't use it if we'd clobber a pseudo reg. */
6604 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6606 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6607 /* Don't clobber the frame pointer. */
6608 || (i == HARD_FRAME_POINTER_REGNUM
6609 && frame_pointer_needed
6611 /* Don't really use the inherited spill reg
6612 if we need it wider than we've got it. */
6613 || (GET_MODE_SIZE (rld[r].mode)
6614 > GET_MODE_SIZE (mode))
6617 /* If find_reloads chose reload_out as reload
6618 register, stay with it - that leaves the
6619 inherited register for subsequent reloads. */
6620 || (rld[r].out && rld[r].reg_rtx
6621 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6623 if (! rld[r].optional)
6625 reload_override_in[r] = last_reg;
6626 reload_inheritance_insn[r]
6627 = reg_reloaded_insn[i];
6633 /* We can use this as a reload reg. */
6634 /* Mark the register as in use for this part of
6636 mark_reload_reg_in_use (i,
6640 rld[r].reg_rtx = last_reg;
6641 reload_inherited[r] = 1;
6642 reload_inheritance_insn[r]
6643 = reg_reloaded_insn[i];
6644 reload_spill_index[r] = i;
6645 for (k = 0; k < nr; k++)
6646 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6654 /* Here's another way to see if the value is already lying around. */
6657 && ! reload_inherited[r]
6659 && (CONSTANT_P (rld[r].in)
6660 || GET_CODE (rld[r].in) == PLUS
6661 || REG_P (rld[r].in)
6662 || MEM_P (rld[r].in))
6663 && (rld[r].nregs == max_group_size
6664 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6665 search_equiv = rld[r].in;
6670 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6671 -1, NULL, 0, rld[r].mode);
6677 regno = REGNO (equiv);
6680 /* This must be a SUBREG of a hard register.
6681 Make a new REG since this might be used in an
6682 address and not all machines support SUBREGs
6684 gcc_assert (GET_CODE (equiv) == SUBREG);
6685 regno = subreg_regno (equiv);
6686 equiv = gen_rtx_REG (rld[r].mode, regno);
6687 /* If we choose EQUIV as the reload register, but the
6688 loop below decides to cancel the inheritance, we'll
6689 end up reloading EQUIV in rld[r].mode, not the mode
6690 it had originally. That isn't safe when EQUIV isn't
6691 available as a spill register since its value might
6692 still be live at this point. */
6693 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6694 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6699 /* If we found a spill reg, reject it unless it is free
6700 and of the desired class. */
6704 int bad_for_class = 0;
6705 int max_regno = regno + rld[r].nregs;
6707 for (i = regno; i < max_regno; i++)
6709 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6711 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6716 && ! free_for_value_p (regno, rld[r].mode,
6717 rld[r].opnum, rld[r].when_needed,
6718 rld[r].in, rld[r].out, r, 1))
6723 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6726 /* We found a register that contains the value we need.
6727 If this register is the same as an `earlyclobber' operand
6728 of the current insn, just mark it as a place to reload from
6729 since we can't use it as the reload register itself. */
6732 for (i = 0; i < n_earlyclobbers; i++)
6733 if (reg_overlap_mentioned_for_reload_p (equiv,
6734 reload_earlyclobbers[i]))
6736 if (! rld[r].optional)
6737 reload_override_in[r] = equiv;
6742 /* If the equiv register we have found is explicitly clobbered
6743 in the current insn, it depends on the reload type if we
6744 can use it, use it for reload_override_in, or not at all.
6745 In particular, we then can't use EQUIV for a
6746 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6750 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6751 switch (rld[r].when_needed)
6753 case RELOAD_FOR_OTHER_ADDRESS:
6754 case RELOAD_FOR_INPADDR_ADDRESS:
6755 case RELOAD_FOR_INPUT_ADDRESS:
6756 case RELOAD_FOR_OPADDR_ADDR:
6759 case RELOAD_FOR_INPUT:
6760 case RELOAD_FOR_OPERAND_ADDRESS:
6761 if (! rld[r].optional)
6762 reload_override_in[r] = equiv;
6768 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6769 switch (rld[r].when_needed)
6771 case RELOAD_FOR_OTHER_ADDRESS:
6772 case RELOAD_FOR_INPADDR_ADDRESS:
6773 case RELOAD_FOR_INPUT_ADDRESS:
6774 case RELOAD_FOR_OPADDR_ADDR:
6775 case RELOAD_FOR_OPERAND_ADDRESS:
6776 case RELOAD_FOR_INPUT:
6779 if (! rld[r].optional)
6780 reload_override_in[r] = equiv;
6788 /* If we found an equivalent reg, say no code need be generated
6789 to load it, and use it as our reload reg. */
6791 && (regno != HARD_FRAME_POINTER_REGNUM
6792 || !frame_pointer_needed))
6794 int nr = hard_regno_nregs[regno][rld[r].mode];
6796 rld[r].reg_rtx = equiv;
6797 reload_spill_index[r] = regno;
6798 reload_inherited[r] = 1;
6800 /* If reg_reloaded_valid is not set for this register,
6801 there might be a stale spill_reg_store lying around.
6802 We must clear it, since otherwise emit_reload_insns
6803 might delete the store. */
6804 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6805 spill_reg_store[regno] = NULL_RTX;
6806 /* If any of the hard registers in EQUIV are spill
6807 registers, mark them as in use for this insn. */
6808 for (k = 0; k < nr; k++)
6810 i = spill_reg_order[regno + k];
6813 mark_reload_reg_in_use (regno, rld[r].opnum,
6816 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6823 /* If we found a register to use already, or if this is an optional
6824 reload, we are done. */
6825 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6829 /* No longer needed for correct operation. Might or might
6830 not give better code on the average. Want to experiment? */
6832 /* See if there is a later reload that has a class different from our
6833 class that intersects our class or that requires less register
6834 than our reload. If so, we must allocate a register to this
6835 reload now, since that reload might inherit a previous reload
6836 and take the only available register in our class. Don't do this
6837 for optional reloads since they will force all previous reloads
6838 to be allocated. Also don't do this for reloads that have been
6841 for (i = j + 1; i < n_reloads; i++)
6843 int s = reload_order[i];
6845 if ((rld[s].in == 0 && rld[s].out == 0
6846 && ! rld[s].secondary_p)
6850 if ((rld[s].rclass != rld[r].rclass
6851 && reg_classes_intersect_p (rld[r].rclass,
6853 || rld[s].nregs < rld[r].nregs)
6860 allocate_reload_reg (chain, r, j == n_reloads - 1);
6864 /* Now allocate reload registers for anything non-optional that
6865 didn't get one yet. */
6866 for (j = 0; j < n_reloads; j++)
6868 int r = reload_order[j];
6870 /* Ignore reloads that got marked inoperative. */
6871 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6874 /* Skip reloads that already have a register allocated or are
6876 if (rld[r].reg_rtx != 0 || rld[r].optional)
6879 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6883 /* If that loop got all the way, we have won. */
6890 /* Loop around and try without any inheritance. */
6895 /* First undo everything done by the failed attempt
6896 to allocate with inheritance. */
6897 choose_reload_regs_init (chain, save_reload_reg_rtx);
6899 /* Some sanity tests to verify that the reloads found in the first
6900 pass are identical to the ones we have now. */
6901 gcc_assert (chain->n_reloads == n_reloads);
6903 for (i = 0; i < n_reloads; i++)
6905 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6907 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6908 for (j = 0; j < n_spills; j++)
6909 if (spill_regs[j] == chain->rld[i].regno)
6910 if (! set_reload_reg (j, i))
6911 failed_reload (chain->insn, i);
6915 /* If we thought we could inherit a reload, because it seemed that
6916 nothing else wanted the same reload register earlier in the insn,
6917 verify that assumption, now that all reloads have been assigned.
6918 Likewise for reloads where reload_override_in has been set. */
6920 /* If doing expensive optimizations, do one preliminary pass that doesn't
6921 cancel any inheritance, but removes reloads that have been needed only
6922 for reloads that we know can be inherited. */
6923 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6925 for (j = 0; j < n_reloads; j++)
6927 int r = reload_order[j];
6929 if (reload_inherited[r] && rld[r].reg_rtx)
6930 check_reg = rld[r].reg_rtx;
6931 else if (reload_override_in[r]
6932 && (REG_P (reload_override_in[r])
6933 || GET_CODE (reload_override_in[r]) == SUBREG))
6934 check_reg = reload_override_in[r];
6937 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6938 rld[r].opnum, rld[r].when_needed, rld[r].in,
6939 (reload_inherited[r]
6940 ? rld[r].out : const0_rtx),
6945 reload_inherited[r] = 0;
6946 reload_override_in[r] = 0;
6948 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6949 reload_override_in, then we do not need its related
6950 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6951 likewise for other reload types.
6952 We handle this by removing a reload when its only replacement
6953 is mentioned in reload_in of the reload we are going to inherit.
6954 A special case are auto_inc expressions; even if the input is
6955 inherited, we still need the address for the output. We can
6956 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6957 If we succeeded removing some reload and we are doing a preliminary
6958 pass just to remove such reloads, make another pass, since the
6959 removal of one reload might allow us to inherit another one. */
6961 && rld[r].out != rld[r].in
6962 && remove_address_replacements (rld[r].in) && pass)
6967 /* Now that reload_override_in is known valid,
6968 actually override reload_in. */
6969 for (j = 0; j < n_reloads; j++)
6970 if (reload_override_in[j])
6971 rld[j].in = reload_override_in[j];
6973 /* If this reload won't be done because it has been canceled or is
6974 optional and not inherited, clear reload_reg_rtx so other
6975 routines (such as subst_reloads) don't get confused. */
6976 for (j = 0; j < n_reloads; j++)
6977 if (rld[j].reg_rtx != 0
6978 && ((rld[j].optional && ! reload_inherited[j])
6979 || (rld[j].in == 0 && rld[j].out == 0
6980 && ! rld[j].secondary_p)))
6982 int regno = true_regnum (rld[j].reg_rtx);
6984 if (spill_reg_order[regno] >= 0)
6985 clear_reload_reg_in_use (regno, rld[j].opnum,
6986 rld[j].when_needed, rld[j].mode);
6988 reload_spill_index[j] = -1;
6991 /* Record which pseudos and which spill regs have output reloads. */
6992 for (j = 0; j < n_reloads; j++)
6994 int r = reload_order[j];
6996 i = reload_spill_index[r];
6998 /* I is nonneg if this reload uses a register.
6999 If rld[r].reg_rtx is 0, this is an optional reload
7000 that we opted to ignore. */
7001 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7002 && rld[r].reg_rtx != 0)
7004 int nregno = REGNO (rld[r].out_reg);
7007 if (nregno < FIRST_PSEUDO_REGISTER)
7008 nr = hard_regno_nregs[nregno][rld[r].mode];
7011 SET_REGNO_REG_SET (®_has_output_reload,
7015 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i);
7017 gcc_assert (rld[r].when_needed == RELOAD_OTHER
7018 || rld[r].when_needed == RELOAD_FOR_OUTPUT
7019 || rld[r].when_needed == RELOAD_FOR_INSN);
7024 /* Deallocate the reload register for reload R. This is called from
7025 remove_address_replacements. */
7028 deallocate_reload_reg (int r)
7032 if (! rld[r].reg_rtx)
7034 regno = true_regnum (rld[r].reg_rtx);
7036 if (spill_reg_order[regno] >= 0)
7037 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7039 reload_spill_index[r] = -1;
7042 /* These arrays are filled by emit_reload_insns and its subroutines. */
7043 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
7044 static rtx other_input_address_reload_insns = 0;
7045 static rtx other_input_reload_insns = 0;
7046 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
7047 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7048 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7049 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7050 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7051 static rtx operand_reload_insns = 0;
7052 static rtx other_operand_reload_insns = 0;
7053 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7055 /* Values to be put in spill_reg_store are put here first. */
7056 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7057 static HARD_REG_SET reg_reloaded_died;
7059 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7060 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7061 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7062 adjusted register, and return true. Otherwise, return false. */
7064 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7065 enum reg_class new_class,
7066 enum machine_mode new_mode)
7071 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7073 unsigned regno = REGNO (reg);
7075 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7077 if (GET_MODE (reg) != new_mode)
7079 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7081 if (hard_regno_nregs[regno][new_mode]
7082 > hard_regno_nregs[regno][GET_MODE (reg)])
7084 reg = reload_adjust_reg_for_mode (reg, new_mode);
7092 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7093 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7094 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7095 adjusted register, and return true. Otherwise, return false. */
7097 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7098 enum insn_code icode)
7101 enum reg_class new_class = scratch_reload_class (icode);
7102 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7104 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7105 new_class, new_mode);
7108 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7109 has the number J. OLD contains the value to be used as input. */
7112 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7115 rtx insn = chain->insn;
7117 rtx oldequiv_reg = 0;
7120 enum machine_mode mode;
7123 /* delete_output_reload is only invoked properly if old contains
7124 the original pseudo register. Since this is replaced with a
7125 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7126 find the pseudo in RELOAD_IN_REG. */
7127 if (reload_override_in[j]
7128 && REG_P (rl->in_reg))
7135 else if (REG_P (oldequiv))
7136 oldequiv_reg = oldequiv;
7137 else if (GET_CODE (oldequiv) == SUBREG)
7138 oldequiv_reg = SUBREG_REG (oldequiv);
7140 reloadreg = reload_reg_rtx_for_input[j];
7141 mode = GET_MODE (reloadreg);
7143 /* If we are reloading from a register that was recently stored in
7144 with an output-reload, see if we can prove there was
7145 actually no need to store the old value in it. */
7147 if (optimize && REG_P (oldequiv)
7148 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7149 && spill_reg_store[REGNO (oldequiv)]
7151 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7152 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7154 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7156 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7159 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7160 oldequiv = SUBREG_REG (oldequiv);
7161 if (GET_MODE (oldequiv) != VOIDmode
7162 && mode != GET_MODE (oldequiv))
7163 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7165 /* Switch to the right place to emit the reload insns. */
7166 switch (rl->when_needed)
7169 where = &other_input_reload_insns;
7171 case RELOAD_FOR_INPUT:
7172 where = &input_reload_insns[rl->opnum];
7174 case RELOAD_FOR_INPUT_ADDRESS:
7175 where = &input_address_reload_insns[rl->opnum];
7177 case RELOAD_FOR_INPADDR_ADDRESS:
7178 where = &inpaddr_address_reload_insns[rl->opnum];
7180 case RELOAD_FOR_OUTPUT_ADDRESS:
7181 where = &output_address_reload_insns[rl->opnum];
7183 case RELOAD_FOR_OUTADDR_ADDRESS:
7184 where = &outaddr_address_reload_insns[rl->opnum];
7186 case RELOAD_FOR_OPERAND_ADDRESS:
7187 where = &operand_reload_insns;
7189 case RELOAD_FOR_OPADDR_ADDR:
7190 where = &other_operand_reload_insns;
7192 case RELOAD_FOR_OTHER_ADDRESS:
7193 where = &other_input_address_reload_insns;
7199 push_to_sequence (*where);
7201 /* Auto-increment addresses must be reloaded in a special way. */
7202 if (rl->out && ! rl->out_reg)
7204 /* We are not going to bother supporting the case where a
7205 incremented register can't be copied directly from
7206 OLDEQUIV since this seems highly unlikely. */
7207 gcc_assert (rl->secondary_in_reload < 0);
7209 if (reload_inherited[j])
7210 oldequiv = reloadreg;
7212 old = XEXP (rl->in_reg, 0);
7214 /* Prevent normal processing of this reload. */
7216 /* Output a special code sequence for this case, and forget about
7217 spill reg information. */
7218 new_spill_reg_store[REGNO (reloadreg)] = NULL;
7219 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7222 /* If we are reloading a pseudo-register that was set by the previous
7223 insn, see if we can get rid of that pseudo-register entirely
7224 by redirecting the previous insn into our reload register. */
7226 else if (optimize && REG_P (old)
7227 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7228 && dead_or_set_p (insn, old)
7229 /* This is unsafe if some other reload
7230 uses the same reg first. */
7231 && ! conflicts_with_override (reloadreg)
7232 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7233 rl->when_needed, old, rl->out, j, 0))
7235 rtx temp = PREV_INSN (insn);
7236 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7237 temp = PREV_INSN (temp);
7239 && NONJUMP_INSN_P (temp)
7240 && GET_CODE (PATTERN (temp)) == SET
7241 && SET_DEST (PATTERN (temp)) == old
7242 /* Make sure we can access insn_operand_constraint. */
7243 && asm_noperands (PATTERN (temp)) < 0
7244 /* This is unsafe if operand occurs more than once in current
7245 insn. Perhaps some occurrences aren't reloaded. */
7246 && count_occurrences (PATTERN (insn), old, 0) == 1)
7248 rtx old = SET_DEST (PATTERN (temp));
7249 /* Store into the reload register instead of the pseudo. */
7250 SET_DEST (PATTERN (temp)) = reloadreg;
7252 /* Verify that resulting insn is valid. */
7253 extract_insn (temp);
7254 if (constrain_operands (1))
7256 /* If the previous insn is an output reload, the source is
7257 a reload register, and its spill_reg_store entry will
7258 contain the previous destination. This is now
7260 if (REG_P (SET_SRC (PATTERN (temp)))
7261 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7263 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7264 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7267 /* If these are the only uses of the pseudo reg,
7268 pretend for GDB it lives in the reload reg we used. */
7269 if (REG_N_DEATHS (REGNO (old)) == 1
7270 && REG_N_SETS (REGNO (old)) == 1)
7272 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7273 if (ira_conflicts_p)
7274 /* Inform IRA about the change. */
7275 ira_mark_allocation_change (REGNO (old));
7276 alter_reg (REGNO (old), -1, false);
7280 /* Adjust any debug insns between temp and insn. */
7281 while ((temp = NEXT_INSN (temp)) != insn)
7282 if (DEBUG_INSN_P (temp))
7283 replace_rtx (PATTERN (temp), old, reloadreg);
7285 gcc_assert (NOTE_P (temp));
7289 SET_DEST (PATTERN (temp)) = old;
7294 /* We can't do that, so output an insn to load RELOADREG. */
7296 /* If we have a secondary reload, pick up the secondary register
7297 and icode, if any. If OLDEQUIV and OLD are different or
7298 if this is an in-out reload, recompute whether or not we
7299 still need a secondary register and what the icode should
7300 be. If we still need a secondary register and the class or
7301 icode is different, go back to reloading from OLD if using
7302 OLDEQUIV means that we got the wrong type of register. We
7303 cannot have different class or icode due to an in-out reload
7304 because we don't make such reloads when both the input and
7305 output need secondary reload registers. */
7307 if (! special && rl->secondary_in_reload >= 0)
7309 rtx second_reload_reg = 0;
7310 rtx third_reload_reg = 0;
7311 int secondary_reload = rl->secondary_in_reload;
7312 rtx real_oldequiv = oldequiv;
7315 enum insn_code icode;
7316 enum insn_code tertiary_icode = CODE_FOR_nothing;
7318 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7319 and similarly for OLD.
7320 See comments in get_secondary_reload in reload.c. */
7321 /* If it is a pseudo that cannot be replaced with its
7322 equivalent MEM, we must fall back to reload_in, which
7323 will have all the necessary substitutions registered.
7324 Likewise for a pseudo that can't be replaced with its
7325 equivalent constant.
7327 Take extra care for subregs of such pseudos. Note that
7328 we cannot use reg_equiv_mem in this case because it is
7329 not in the right mode. */
7332 if (GET_CODE (tmp) == SUBREG)
7333 tmp = SUBREG_REG (tmp);
7335 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7336 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7337 || reg_equiv_constant (REGNO (tmp)) != 0))
7339 if (! reg_equiv_mem (REGNO (tmp))
7340 || num_not_at_initial_offset
7341 || GET_CODE (oldequiv) == SUBREG)
7342 real_oldequiv = rl->in;
7344 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7348 if (GET_CODE (tmp) == SUBREG)
7349 tmp = SUBREG_REG (tmp);
7351 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7352 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7353 || reg_equiv_constant (REGNO (tmp)) != 0))
7355 if (! reg_equiv_mem (REGNO (tmp))
7356 || num_not_at_initial_offset
7357 || GET_CODE (old) == SUBREG)
7360 real_old = reg_equiv_mem (REGNO (tmp));
7363 second_reload_reg = rld[secondary_reload].reg_rtx;
7364 if (rld[secondary_reload].secondary_in_reload >= 0)
7366 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7368 third_reload_reg = rld[tertiary_reload].reg_rtx;
7369 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7370 /* We'd have to add more code for quartary reloads. */
7371 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7373 icode = rl->secondary_in_icode;
7375 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7376 || (rl->in != 0 && rl->out != 0))
7378 secondary_reload_info sri, sri2;
7379 enum reg_class new_class, new_t_class;
7381 sri.icode = CODE_FOR_nothing;
7382 sri.prev_sri = NULL;
7384 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7388 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7389 second_reload_reg = 0;
7390 else if (new_class == NO_REGS)
7392 if (reload_adjust_reg_for_icode (&second_reload_reg,
7394 (enum insn_code) sri.icode))
7396 icode = (enum insn_code) sri.icode;
7397 third_reload_reg = 0;
7402 real_oldequiv = real_old;
7405 else if (sri.icode != CODE_FOR_nothing)
7406 /* We currently lack a way to express this in reloads. */
7410 sri2.icode = CODE_FOR_nothing;
7411 sri2.prev_sri = &sri;
7413 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7416 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7418 if (reload_adjust_reg_for_temp (&second_reload_reg,
7422 third_reload_reg = 0;
7423 tertiary_icode = (enum insn_code) sri2.icode;
7428 real_oldequiv = real_old;
7431 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7433 rtx intermediate = second_reload_reg;
7435 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7437 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7441 second_reload_reg = intermediate;
7442 tertiary_icode = (enum insn_code) sri2.icode;
7447 real_oldequiv = real_old;
7450 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7452 rtx intermediate = second_reload_reg;
7454 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7456 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7459 second_reload_reg = intermediate;
7460 tertiary_icode = (enum insn_code) sri2.icode;
7465 real_oldequiv = real_old;
7470 /* This could be handled more intelligently too. */
7472 real_oldequiv = real_old;
7477 /* If we still need a secondary reload register, check
7478 to see if it is being used as a scratch or intermediate
7479 register and generate code appropriately. If we need
7480 a scratch register, use REAL_OLDEQUIV since the form of
7481 the insn may depend on the actual address if it is
7484 if (second_reload_reg)
7486 if (icode != CODE_FOR_nothing)
7488 /* We'd have to add extra code to handle this case. */
7489 gcc_assert (!third_reload_reg);
7491 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7492 second_reload_reg));
7497 /* See if we need a scratch register to load the
7498 intermediate register (a tertiary reload). */
7499 if (tertiary_icode != CODE_FOR_nothing)
7501 emit_insn ((GEN_FCN (tertiary_icode)
7502 (second_reload_reg, real_oldequiv,
7503 third_reload_reg)));
7505 else if (third_reload_reg)
7507 gen_reload (third_reload_reg, real_oldequiv,
7510 gen_reload (second_reload_reg, third_reload_reg,
7515 gen_reload (second_reload_reg, real_oldequiv,
7519 oldequiv = second_reload_reg;
7524 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7526 rtx real_oldequiv = oldequiv;
7528 if ((REG_P (oldequiv)
7529 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7530 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7531 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7532 || (GET_CODE (oldequiv) == SUBREG
7533 && REG_P (SUBREG_REG (oldequiv))
7534 && (REGNO (SUBREG_REG (oldequiv))
7535 >= FIRST_PSEUDO_REGISTER)
7536 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7537 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7538 || (CONSTANT_P (oldequiv)
7539 && (targetm.preferred_reload_class (oldequiv,
7540 REGNO_REG_CLASS (REGNO (reloadreg)))
7542 real_oldequiv = rl->in;
7543 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7547 if (cfun->can_throw_non_call_exceptions)
7548 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7550 /* End this sequence. */
7551 *where = get_insns ();
7554 /* Update reload_override_in so that delete_address_reloads_1
7555 can see the actual register usage. */
7557 reload_override_in[j] = oldequiv;
7560 /* Generate insns to for the output reload RL, which is for the insn described
7561 by CHAIN and has the number J. */
7563 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7567 rtx insn = chain->insn;
7570 enum machine_mode mode;
7574 if (rl->when_needed == RELOAD_OTHER)
7577 push_to_sequence (output_reload_insns[rl->opnum]);
7579 rl_reg_rtx = reload_reg_rtx_for_output[j];
7580 mode = GET_MODE (rl_reg_rtx);
7582 reloadreg = rl_reg_rtx;
7584 /* If we need two reload regs, set RELOADREG to the intermediate
7585 one, since it will be stored into OLD. We might need a secondary
7586 register only for an input reload, so check again here. */
7588 if (rl->secondary_out_reload >= 0)
7591 int secondary_reload = rl->secondary_out_reload;
7592 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7594 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7595 && reg_equiv_mem (REGNO (old)) != 0)
7596 real_old = reg_equiv_mem (REGNO (old));
7598 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7600 rtx second_reloadreg = reloadreg;
7601 reloadreg = rld[secondary_reload].reg_rtx;
7603 /* See if RELOADREG is to be used as a scratch register
7604 or as an intermediate register. */
7605 if (rl->secondary_out_icode != CODE_FOR_nothing)
7607 /* We'd have to add extra code to handle this case. */
7608 gcc_assert (tertiary_reload < 0);
7610 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7611 (real_old, second_reloadreg, reloadreg)));
7616 /* See if we need both a scratch and intermediate reload
7619 enum insn_code tertiary_icode
7620 = rld[secondary_reload].secondary_out_icode;
7622 /* We'd have to add more code for quartary reloads. */
7623 gcc_assert (tertiary_reload < 0
7624 || rld[tertiary_reload].secondary_out_reload < 0);
7626 if (GET_MODE (reloadreg) != mode)
7627 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7629 if (tertiary_icode != CODE_FOR_nothing)
7631 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7633 /* Copy primary reload reg to secondary reload reg.
7634 (Note that these have been swapped above, then
7635 secondary reload reg to OLD using our insn.) */
7637 /* If REAL_OLD is a paradoxical SUBREG, remove it
7638 and try to put the opposite SUBREG on
7640 strip_paradoxical_subreg (&real_old, &reloadreg);
7642 gen_reload (reloadreg, second_reloadreg,
7643 rl->opnum, rl->when_needed);
7644 emit_insn ((GEN_FCN (tertiary_icode)
7645 (real_old, reloadreg, third_reloadreg)));
7651 /* Copy between the reload regs here and then to
7654 gen_reload (reloadreg, second_reloadreg,
7655 rl->opnum, rl->when_needed);
7656 if (tertiary_reload >= 0)
7658 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7660 gen_reload (third_reloadreg, reloadreg,
7661 rl->opnum, rl->when_needed);
7662 reloadreg = third_reloadreg;
7669 /* Output the last reload insn. */
7674 /* Don't output the last reload if OLD is not the dest of
7675 INSN and is in the src and is clobbered by INSN. */
7676 if (! flag_expensive_optimizations
7678 || !(set = single_set (insn))
7679 || rtx_equal_p (old, SET_DEST (set))
7680 || !reg_mentioned_p (old, SET_SRC (set))
7681 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7682 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7683 gen_reload (old, reloadreg, rl->opnum,
7687 /* Look at all insns we emitted, just to be safe. */
7688 for (p = get_insns (); p; p = NEXT_INSN (p))
7691 rtx pat = PATTERN (p);
7693 /* If this output reload doesn't come from a spill reg,
7694 clear any memory of reloaded copies of the pseudo reg.
7695 If this output reload comes from a spill reg,
7696 reg_has_output_reload will make this do nothing. */
7697 note_stores (pat, forget_old_reloads_1, NULL);
7699 if (reg_mentioned_p (rl_reg_rtx, pat))
7701 rtx set = single_set (insn);
7702 if (reload_spill_index[j] < 0
7704 && SET_SRC (set) == rl_reg_rtx)
7706 int src = REGNO (SET_SRC (set));
7708 reload_spill_index[j] = src;
7709 SET_HARD_REG_BIT (reg_is_output_reload, src);
7710 if (find_regno_note (insn, REG_DEAD, src))
7711 SET_HARD_REG_BIT (reg_reloaded_died, src);
7713 if (HARD_REGISTER_P (rl_reg_rtx))
7715 int s = rl->secondary_out_reload;
7716 set = single_set (p);
7717 /* If this reload copies only to the secondary reload
7718 register, the secondary reload does the actual
7720 if (s >= 0 && set == NULL_RTX)
7721 /* We can't tell what function the secondary reload
7722 has and where the actual store to the pseudo is
7723 made; leave new_spill_reg_store alone. */
7726 && SET_SRC (set) == rl_reg_rtx
7727 && SET_DEST (set) == rld[s].reg_rtx)
7729 /* Usually the next instruction will be the
7730 secondary reload insn; if we can confirm
7731 that it is, setting new_spill_reg_store to
7732 that insn will allow an extra optimization. */
7733 rtx s_reg = rld[s].reg_rtx;
7734 rtx next = NEXT_INSN (p);
7735 rld[s].out = rl->out;
7736 rld[s].out_reg = rl->out_reg;
7737 set = single_set (next);
7738 if (set && SET_SRC (set) == s_reg
7739 && ! new_spill_reg_store[REGNO (s_reg)])
7741 SET_HARD_REG_BIT (reg_is_output_reload,
7743 new_spill_reg_store[REGNO (s_reg)] = next;
7747 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7752 if (rl->when_needed == RELOAD_OTHER)
7754 emit_insn (other_output_reload_insns[rl->opnum]);
7755 other_output_reload_insns[rl->opnum] = get_insns ();
7758 output_reload_insns[rl->opnum] = get_insns ();
7760 if (cfun->can_throw_non_call_exceptions)
7761 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7766 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7767 and has the number J. */
7769 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7771 rtx insn = chain->insn;
7772 rtx old = (rl->in && MEM_P (rl->in)
7773 ? rl->in_reg : rl->in);
7774 rtx reg_rtx = rl->reg_rtx;
7778 enum machine_mode mode;
7780 /* Determine the mode to reload in.
7781 This is very tricky because we have three to choose from.
7782 There is the mode the insn operand wants (rl->inmode).
7783 There is the mode of the reload register RELOADREG.
7784 There is the intrinsic mode of the operand, which we could find
7785 by stripping some SUBREGs.
7786 It turns out that RELOADREG's mode is irrelevant:
7787 we can change that arbitrarily.
7789 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7790 then the reload reg may not support QImode moves, so use SImode.
7791 If foo is in memory due to spilling a pseudo reg, this is safe,
7792 because the QImode value is in the least significant part of a
7793 slot big enough for a SImode. If foo is some other sort of
7794 memory reference, then it is impossible to reload this case,
7795 so previous passes had better make sure this never happens.
7797 Then consider a one-word union which has SImode and one of its
7798 members is a float, being fetched as (SUBREG:SF union:SI).
7799 We must fetch that as SFmode because we could be loading into
7800 a float-only register. In this case OLD's mode is correct.
7802 Consider an immediate integer: it has VOIDmode. Here we need
7803 to get a mode from something else.
7805 In some cases, there is a fourth mode, the operand's
7806 containing mode. If the insn specifies a containing mode for
7807 this operand, it overrides all others.
7809 I am not sure whether the algorithm here is always right,
7810 but it does the right things in those cases. */
7812 mode = GET_MODE (old);
7813 if (mode == VOIDmode)
7816 /* We cannot use gen_lowpart_common since it can do the wrong thing
7817 when REG_RTX has a multi-word mode. Note that REG_RTX must
7818 always be a REG here. */
7819 if (GET_MODE (reg_rtx) != mode)
7820 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7822 reload_reg_rtx_for_input[j] = reg_rtx;
7825 /* AUTO_INC reloads need to be handled even if inherited. We got an
7826 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7827 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7828 && ! rtx_equal_p (reg_rtx, old)
7830 emit_input_reload_insns (chain, rld + j, old, j);
7832 /* When inheriting a wider reload, we have a MEM in rl->in,
7833 e.g. inheriting a SImode output reload for
7834 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7835 if (optimize && reload_inherited[j] && rl->in
7837 && MEM_P (rl->in_reg)
7838 && reload_spill_index[j] >= 0
7839 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7840 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7842 /* If we are reloading a register that was recently stored in with an
7843 output-reload, see if we can prove there was
7844 actually no need to store the old value in it. */
7847 && (reload_inherited[j] || reload_override_in[j])
7850 && spill_reg_store[REGNO (reg_rtx)] != 0
7852 /* There doesn't seem to be any reason to restrict this to pseudos
7853 and doing so loses in the case where we are copying from a
7854 register of the wrong class. */
7855 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7857 /* The insn might have already some references to stackslots
7858 replaced by MEMs, while reload_out_reg still names the
7860 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7861 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7862 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7865 /* Do output reloading for reload RL, which is for the insn described by
7866 CHAIN and has the number J.
7867 ??? At some point we need to support handling output reloads of
7868 JUMP_INSNs or insns that set cc0. */
7870 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7873 rtx insn = chain->insn;
7874 /* If this is an output reload that stores something that is
7875 not loaded in this same reload, see if we can eliminate a previous
7877 rtx pseudo = rl->out_reg;
7878 rtx reg_rtx = rl->reg_rtx;
7880 if (rl->out && reg_rtx)
7882 enum machine_mode mode;
7884 /* Determine the mode to reload in.
7885 See comments above (for input reloading). */
7886 mode = GET_MODE (rl->out);
7887 if (mode == VOIDmode)
7889 /* VOIDmode should never happen for an output. */
7890 if (asm_noperands (PATTERN (insn)) < 0)
7891 /* It's the compiler's fault. */
7892 fatal_insn ("VOIDmode on an output", insn);
7893 error_for_asm (insn, "output operand is constant in %<asm%>");
7894 /* Prevent crash--use something we know is valid. */
7896 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7898 if (GET_MODE (reg_rtx) != mode)
7899 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7901 reload_reg_rtx_for_output[j] = reg_rtx;
7906 && ! rtx_equal_p (rl->in_reg, pseudo)
7907 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7908 && reg_last_reload_reg[REGNO (pseudo)])
7910 int pseudo_no = REGNO (pseudo);
7911 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7913 /* We don't need to test full validity of last_regno for
7914 inherit here; we only want to know if the store actually
7915 matches the pseudo. */
7916 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7917 && reg_reloaded_contents[last_regno] == pseudo_no
7918 && spill_reg_store[last_regno]
7919 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7920 delete_output_reload (insn, j, last_regno, reg_rtx);
7926 || rtx_equal_p (old, reg_rtx))
7929 /* An output operand that dies right away does need a reload,
7930 but need not be copied from it. Show the new location in the
7932 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7933 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7935 XEXP (note, 0) = reg_rtx;
7938 /* Likewise for a SUBREG of an operand that dies. */
7939 else if (GET_CODE (old) == SUBREG
7940 && REG_P (SUBREG_REG (old))
7941 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7944 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7947 else if (GET_CODE (old) == SCRATCH)
7948 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7949 but we don't want to make an output reload. */
7952 /* If is a JUMP_INSN, we can't support output reloads yet. */
7953 gcc_assert (NONJUMP_INSN_P (insn));
7955 emit_output_reload_insns (chain, rld + j, j);
7958 /* A reload copies values of MODE from register SRC to register DEST.
7959 Return true if it can be treated for inheritance purposes like a
7960 group of reloads, each one reloading a single hard register. The
7961 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7962 occupy the same number of hard registers. */
7965 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7966 int src ATTRIBUTE_UNUSED,
7967 enum machine_mode mode ATTRIBUTE_UNUSED)
7969 #ifdef CANNOT_CHANGE_MODE_CLASS
7970 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7971 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7977 /* Output insns to reload values in and out of the chosen reload regs. */
7980 emit_reload_insns (struct insn_chain *chain)
7982 rtx insn = chain->insn;
7986 CLEAR_HARD_REG_SET (reg_reloaded_died);
7988 for (j = 0; j < reload_n_operands; j++)
7989 input_reload_insns[j] = input_address_reload_insns[j]
7990 = inpaddr_address_reload_insns[j]
7991 = output_reload_insns[j] = output_address_reload_insns[j]
7992 = outaddr_address_reload_insns[j]
7993 = other_output_reload_insns[j] = 0;
7994 other_input_address_reload_insns = 0;
7995 other_input_reload_insns = 0;
7996 operand_reload_insns = 0;
7997 other_operand_reload_insns = 0;
7999 /* Dump reloads into the dump file. */
8002 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8003 debug_reload_to_stream (dump_file);
8006 /* Now output the instructions to copy the data into and out of the
8007 reload registers. Do these in the order that the reloads were reported,
8008 since reloads of base and index registers precede reloads of operands
8009 and the operands may need the base and index registers reloaded. */
8011 for (j = 0; j < n_reloads; j++)
8013 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8017 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8018 new_spill_reg_store[i] = 0;
8021 do_input_reload (chain, rld + j, j);
8022 do_output_reload (chain, rld + j, j);
8025 /* Now write all the insns we made for reloads in the order expected by
8026 the allocation functions. Prior to the insn being reloaded, we write
8027 the following reloads:
8029 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8031 RELOAD_OTHER reloads.
8033 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8034 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8035 RELOAD_FOR_INPUT reload for the operand.
8037 RELOAD_FOR_OPADDR_ADDRS reloads.
8039 RELOAD_FOR_OPERAND_ADDRESS reloads.
8041 After the insn being reloaded, we write the following:
8043 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8044 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8045 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8046 reloads for the operand. The RELOAD_OTHER output reloads are
8047 output in descending order by reload number. */
8049 emit_insn_before (other_input_address_reload_insns, insn);
8050 emit_insn_before (other_input_reload_insns, insn);
8052 for (j = 0; j < reload_n_operands; j++)
8054 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8055 emit_insn_before (input_address_reload_insns[j], insn);
8056 emit_insn_before (input_reload_insns[j], insn);
8059 emit_insn_before (other_operand_reload_insns, insn);
8060 emit_insn_before (operand_reload_insns, insn);
8062 for (j = 0; j < reload_n_operands; j++)
8064 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8065 x = emit_insn_after (output_address_reload_insns[j], x);
8066 x = emit_insn_after (output_reload_insns[j], x);
8067 emit_insn_after (other_output_reload_insns[j], x);
8070 /* For all the spill regs newly reloaded in this instruction,
8071 record what they were reloaded from, so subsequent instructions
8072 can inherit the reloads.
8074 Update spill_reg_store for the reloads of this insn.
8075 Copy the elements that were updated in the loop above. */
8077 for (j = 0; j < n_reloads; j++)
8079 int r = reload_order[j];
8080 int i = reload_spill_index[r];
8082 /* If this is a non-inherited input reload from a pseudo, we must
8083 clear any memory of a previous store to the same pseudo. Only do
8084 something if there will not be an output reload for the pseudo
8086 if (rld[r].in_reg != 0
8087 && ! (reload_inherited[r] || reload_override_in[r]))
8089 rtx reg = rld[r].in_reg;
8091 if (GET_CODE (reg) == SUBREG)
8092 reg = SUBREG_REG (reg);
8095 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8096 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
8098 int nregno = REGNO (reg);
8100 if (reg_last_reload_reg[nregno])
8102 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8104 if (reg_reloaded_contents[last_regno] == nregno)
8105 spill_reg_store[last_regno] = 0;
8110 /* I is nonneg if this reload used a register.
8111 If rld[r].reg_rtx is 0, this is an optional reload
8112 that we opted to ignore. */
8114 if (i >= 0 && rld[r].reg_rtx != 0)
8116 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8119 /* For a multi register reload, we need to check if all or part
8120 of the value lives to the end. */
8121 for (k = 0; k < nr; k++)
8122 if (reload_reg_reaches_end_p (i + k, r))
8123 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8125 /* Maybe the spill reg contains a copy of reload_out. */
8127 && (REG_P (rld[r].out)
8129 ? REG_P (rld[r].out_reg)
8130 /* The reload value is an auto-modification of
8131 some kind. For PRE_INC, POST_INC, PRE_DEC
8132 and POST_DEC, we record an equivalence
8133 between the reload register and the operand
8134 on the optimistic assumption that we can make
8135 the equivalence hold. reload_as_needed must
8136 then either make it hold or invalidate the
8139 PRE_MODIFY and POST_MODIFY addresses are reloaded
8140 somewhat differently, and allowing them here leads
8142 : (GET_CODE (rld[r].out) != POST_MODIFY
8143 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8146 enum machine_mode mode;
8149 reg = reload_reg_rtx_for_output[r];
8150 mode = GET_MODE (reg);
8151 regno = REGNO (reg);
8152 nregs = hard_regno_nregs[regno][mode];
8153 if (reload_regs_reach_end_p (regno, nregs, r))
8155 rtx out = (REG_P (rld[r].out)
8159 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8160 int out_regno = REGNO (out);
8161 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8162 : hard_regno_nregs[out_regno][mode]);
8165 spill_reg_store[regno] = new_spill_reg_store[regno];
8166 spill_reg_stored_to[regno] = out;
8167 reg_last_reload_reg[out_regno] = reg;
8169 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8170 && nregs == out_nregs
8171 && inherit_piecemeal_p (out_regno, regno, mode));
8173 /* If OUT_REGNO is a hard register, it may occupy more than
8174 one register. If it does, say what is in the
8175 rest of the registers assuming that both registers
8176 agree on how many words the object takes. If not,
8177 invalidate the subsequent registers. */
8179 if (HARD_REGISTER_NUM_P (out_regno))
8180 for (k = 1; k < out_nregs; k++)
8181 reg_last_reload_reg[out_regno + k]
8182 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8184 /* Now do the inverse operation. */
8185 for (k = 0; k < nregs; k++)
8187 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8188 reg_reloaded_contents[regno + k]
8189 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8192 reg_reloaded_insn[regno + k] = insn;
8193 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8194 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8195 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8198 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8203 /* Maybe the spill reg contains a copy of reload_in. Only do
8204 something if there will not be an output reload for
8205 the register being reloaded. */
8206 else if (rld[r].out_reg == 0
8208 && ((REG_P (rld[r].in)
8209 && !HARD_REGISTER_P (rld[r].in)
8210 && !REGNO_REG_SET_P (®_has_output_reload,
8212 || (REG_P (rld[r].in_reg)
8213 && !REGNO_REG_SET_P (®_has_output_reload,
8214 REGNO (rld[r].in_reg))))
8215 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8218 enum machine_mode mode;
8221 reg = reload_reg_rtx_for_input[r];
8222 mode = GET_MODE (reg);
8223 regno = REGNO (reg);
8224 nregs = hard_regno_nregs[regno][mode];
8225 if (reload_regs_reach_end_p (regno, nregs, r))
8232 if (REG_P (rld[r].in)
8233 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8235 else if (REG_P (rld[r].in_reg))
8238 in = XEXP (rld[r].in_reg, 0);
8239 in_regno = REGNO (in);
8241 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8242 : hard_regno_nregs[in_regno][mode]);
8244 reg_last_reload_reg[in_regno] = reg;
8246 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8247 && nregs == in_nregs
8248 && inherit_piecemeal_p (regno, in_regno, mode));
8250 if (HARD_REGISTER_NUM_P (in_regno))
8251 for (k = 1; k < in_nregs; k++)
8252 reg_last_reload_reg[in_regno + k]
8253 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8255 /* Unless we inherited this reload, show we haven't
8256 recently done a store.
8257 Previous stores of inherited auto_inc expressions
8258 also have to be discarded. */
8259 if (! reload_inherited[r]
8260 || (rld[r].out && ! rld[r].out_reg))
8261 spill_reg_store[regno] = 0;
8263 for (k = 0; k < nregs; k++)
8265 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8266 reg_reloaded_contents[regno + k]
8267 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8270 reg_reloaded_insn[regno + k] = insn;
8271 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8272 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8273 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8276 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8283 /* The following if-statement was #if 0'd in 1.34 (or before...).
8284 It's reenabled in 1.35 because supposedly nothing else
8285 deals with this problem. */
8287 /* If a register gets output-reloaded from a non-spill register,
8288 that invalidates any previous reloaded copy of it.
8289 But forget_old_reloads_1 won't get to see it, because
8290 it thinks only about the original insn. So invalidate it here.
8291 Also do the same thing for RELOAD_OTHER constraints where the
8292 output is discarded. */
8294 && ((rld[r].out != 0
8295 && (REG_P (rld[r].out)
8296 || (MEM_P (rld[r].out)
8297 && REG_P (rld[r].out_reg))))
8298 || (rld[r].out == 0 && rld[r].out_reg
8299 && REG_P (rld[r].out_reg))))
8301 rtx out = ((rld[r].out && REG_P (rld[r].out))
8302 ? rld[r].out : rld[r].out_reg);
8303 int out_regno = REGNO (out);
8304 enum machine_mode mode = GET_MODE (out);
8306 /* REG_RTX is now set or clobbered by the main instruction.
8307 As the comment above explains, forget_old_reloads_1 only
8308 sees the original instruction, and there is no guarantee
8309 that the original instruction also clobbered REG_RTX.
8310 For example, if find_reloads sees that the input side of
8311 a matched operand pair dies in this instruction, it may
8312 use the input register as the reload register.
8314 Calling forget_old_reloads_1 is a waste of effort if
8315 REG_RTX is also the output register.
8317 If we know that REG_RTX holds the value of a pseudo
8318 register, the code after the call will record that fact. */
8319 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8320 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8322 if (!HARD_REGISTER_NUM_P (out_regno))
8324 rtx src_reg, store_insn = NULL_RTX;
8326 reg_last_reload_reg[out_regno] = 0;
8328 /* If we can find a hard register that is stored, record
8329 the storing insn so that we may delete this insn with
8330 delete_output_reload. */
8331 src_reg = reload_reg_rtx_for_output[r];
8333 /* If this is an optional reload, try to find the source reg
8334 from an input reload. */
8337 rtx set = single_set (insn);
8338 if (set && SET_DEST (set) == rld[r].out)
8342 src_reg = SET_SRC (set);
8344 for (k = 0; k < n_reloads; k++)
8346 if (rld[k].in == src_reg)
8348 src_reg = reload_reg_rtx_for_input[k];
8355 store_insn = new_spill_reg_store[REGNO (src_reg)];
8356 if (src_reg && REG_P (src_reg)
8357 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8359 int src_regno, src_nregs, k;
8362 gcc_assert (GET_MODE (src_reg) == mode);
8363 src_regno = REGNO (src_reg);
8364 src_nregs = hard_regno_nregs[src_regno][mode];
8365 /* The place where to find a death note varies with
8366 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8367 necessarily checked exactly in the code that moves
8368 notes, so just check both locations. */
8369 note = find_regno_note (insn, REG_DEAD, src_regno);
8370 if (! note && store_insn)
8371 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8372 for (k = 0; k < src_nregs; k++)
8374 spill_reg_store[src_regno + k] = store_insn;
8375 spill_reg_stored_to[src_regno + k] = out;
8376 reg_reloaded_contents[src_regno + k] = out_regno;
8377 reg_reloaded_insn[src_regno + k] = store_insn;
8378 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8379 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8380 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8382 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8385 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8387 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8389 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8391 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8393 reg_last_reload_reg[out_regno] = src_reg;
8394 /* We have to set reg_has_output_reload here, or else
8395 forget_old_reloads_1 will clear reg_last_reload_reg
8397 SET_REGNO_REG_SET (®_has_output_reload,
8403 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8405 for (k = 0; k < out_nregs; k++)
8406 reg_last_reload_reg[out_regno + k] = 0;
8410 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8413 /* Go through the motions to emit INSN and test if it is strictly valid.
8414 Return the emitted insn if valid, else return NULL. */
8417 emit_insn_if_valid_for_reload (rtx insn)
8419 rtx last = get_last_insn ();
8422 insn = emit_insn (insn);
8423 code = recog_memoized (insn);
8427 extract_insn (insn);
8428 /* We want constrain operands to treat this insn strictly in its
8429 validity determination, i.e., the way it would after reload has
8431 if (constrain_operands (1))
8435 delete_insns_since (last);
8439 /* Emit code to perform a reload from IN (which may be a reload register) to
8440 OUT (which may also be a reload register). IN or OUT is from operand
8441 OPNUM with reload type TYPE.
8443 Returns first insn emitted. */
8446 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8448 rtx last = get_last_insn ();
8451 /* If IN is a paradoxical SUBREG, remove it and try to put the
8452 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8453 if (!strip_paradoxical_subreg (&in, &out))
8454 strip_paradoxical_subreg (&out, &in);
8456 /* How to do this reload can get quite tricky. Normally, we are being
8457 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8458 register that didn't get a hard register. In that case we can just
8459 call emit_move_insn.
8461 We can also be asked to reload a PLUS that adds a register or a MEM to
8462 another register, constant or MEM. This can occur during frame pointer
8463 elimination and while reloading addresses. This case is handled by
8464 trying to emit a single insn to perform the add. If it is not valid,
8465 we use a two insn sequence.
8467 Or we can be asked to reload an unary operand that was a fragment of
8468 an addressing mode, into a register. If it isn't recognized as-is,
8469 we try making the unop operand and the reload-register the same:
8470 (set reg:X (unop:X expr:Y))
8471 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8473 Finally, we could be called to handle an 'o' constraint by putting
8474 an address into a register. In that case, we first try to do this
8475 with a named pattern of "reload_load_address". If no such pattern
8476 exists, we just emit a SET insn and hope for the best (it will normally
8477 be valid on machines that use 'o').
8479 This entire process is made complex because reload will never
8480 process the insns we generate here and so we must ensure that
8481 they will fit their constraints and also by the fact that parts of
8482 IN might be being reloaded separately and replaced with spill registers.
8483 Because of this, we are, in some sense, just guessing the right approach
8484 here. The one listed above seems to work.
8486 ??? At some point, this whole thing needs to be rethought. */
8488 if (GET_CODE (in) == PLUS
8489 && (REG_P (XEXP (in, 0))
8490 || GET_CODE (XEXP (in, 0)) == SUBREG
8491 || MEM_P (XEXP (in, 0)))
8492 && (REG_P (XEXP (in, 1))
8493 || GET_CODE (XEXP (in, 1)) == SUBREG
8494 || CONSTANT_P (XEXP (in, 1))
8495 || MEM_P (XEXP (in, 1))))
8497 /* We need to compute the sum of a register or a MEM and another
8498 register, constant, or MEM, and put it into the reload
8499 register. The best possible way of doing this is if the machine
8500 has a three-operand ADD insn that accepts the required operands.
8502 The simplest approach is to try to generate such an insn and see if it
8503 is recognized and matches its constraints. If so, it can be used.
8505 It might be better not to actually emit the insn unless it is valid,
8506 but we need to pass the insn as an operand to `recog' and
8507 `extract_insn' and it is simpler to emit and then delete the insn if
8508 not valid than to dummy things up. */
8510 rtx op0, op1, tem, insn;
8511 enum insn_code code;
8513 op0 = find_replacement (&XEXP (in, 0));
8514 op1 = find_replacement (&XEXP (in, 1));
8516 /* Since constraint checking is strict, commutativity won't be
8517 checked, so we need to do that here to avoid spurious failure
8518 if the add instruction is two-address and the second operand
8519 of the add is the same as the reload reg, which is frequently
8520 the case. If the insn would be A = B + A, rearrange it so
8521 it will be A = A + B as constrain_operands expects. */
8523 if (REG_P (XEXP (in, 1))
8524 && REGNO (out) == REGNO (XEXP (in, 1)))
8525 tem = op0, op0 = op1, op1 = tem;
8527 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8528 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8530 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8534 /* If that failed, we must use a conservative two-insn sequence.
8536 Use a move to copy one operand into the reload register. Prefer
8537 to reload a constant, MEM or pseudo since the move patterns can
8538 handle an arbitrary operand. If OP1 is not a constant, MEM or
8539 pseudo and OP1 is not a valid operand for an add instruction, then
8542 After reloading one of the operands into the reload register, add
8543 the reload register to the output register.
8545 If there is another way to do this for a specific machine, a
8546 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8549 code = optab_handler (add_optab, GET_MODE (out));
8551 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8553 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8554 || (code != CODE_FOR_nothing
8555 && !insn_operand_matches (code, 2, op1)))
8556 tem = op0, op0 = op1, op1 = tem;
8558 gen_reload (out, op0, opnum, type);
8560 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8561 This fixes a problem on the 32K where the stack pointer cannot
8562 be used as an operand of an add insn. */
8564 if (rtx_equal_p (op0, op1))
8567 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8570 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8571 set_unique_reg_note (insn, REG_EQUIV, in);
8575 /* If that failed, copy the address register to the reload register.
8576 Then add the constant to the reload register. */
8578 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8579 gen_reload (out, op1, opnum, type);
8580 insn = emit_insn (gen_add2_insn (out, op0));
8581 set_unique_reg_note (insn, REG_EQUIV, in);
8584 #ifdef SECONDARY_MEMORY_NEEDED
8585 /* If we need a memory location to do the move, do it that way. */
8586 else if ((REG_P (in)
8587 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8588 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8590 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8591 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8592 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8593 REGNO_REG_CLASS (reg_or_subregno (out)),
8596 /* Get the memory to use and rewrite both registers to its mode. */
8597 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8599 if (GET_MODE (loc) != GET_MODE (out))
8600 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8602 if (GET_MODE (loc) != GET_MODE (in))
8603 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8605 gen_reload (loc, in, opnum, type);
8606 gen_reload (out, loc, opnum, type);
8609 else if (REG_P (out) && UNARY_P (in))
8616 op1 = find_replacement (&XEXP (in, 0));
8617 if (op1 != XEXP (in, 0))
8618 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8620 /* First, try a plain SET. */
8621 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8625 /* If that failed, move the inner operand to the reload
8626 register, and try the same unop with the inner expression
8627 replaced with the reload register. */
8629 if (GET_MODE (op1) != GET_MODE (out))
8630 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8634 gen_reload (out_moded, op1, opnum, type);
8637 = gen_rtx_SET (VOIDmode, out,
8638 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8640 insn = emit_insn_if_valid_for_reload (insn);
8643 set_unique_reg_note (insn, REG_EQUIV, in);
8647 fatal_insn ("failure trying to reload:", set);
8649 /* If IN is a simple operand, use gen_move_insn. */
8650 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8652 tem = emit_insn (gen_move_insn (out, in));
8653 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8654 mark_jump_label (in, tem, 0);
8657 #ifdef HAVE_reload_load_address
8658 else if (HAVE_reload_load_address)
8659 emit_insn (gen_reload_load_address (out, in));
8662 /* Otherwise, just write (set OUT IN) and hope for the best. */
8664 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8666 /* Return the first insn emitted.
8667 We can not just return get_last_insn, because there may have
8668 been multiple instructions emitted. Also note that gen_move_insn may
8669 emit more than one insn itself, so we can not assume that there is one
8670 insn emitted per emit_insn_before call. */
8672 return last ? NEXT_INSN (last) : get_insns ();
8675 /* Delete a previously made output-reload whose result we now believe
8676 is not needed. First we double-check.
8678 INSN is the insn now being processed.
8679 LAST_RELOAD_REG is the hard register number for which we want to delete
8680 the last output reload.
8681 J is the reload-number that originally used REG. The caller has made
8682 certain that reload J doesn't use REG any longer for input.
8683 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8686 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8688 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8689 rtx reg = spill_reg_stored_to[last_reload_reg];
8692 int n_inherited = 0;
8698 /* It is possible that this reload has been only used to set another reload
8699 we eliminated earlier and thus deleted this instruction too. */
8700 if (INSN_DELETED_P (output_reload_insn))
8703 /* Get the raw pseudo-register referred to. */
8705 while (GET_CODE (reg) == SUBREG)
8706 reg = SUBREG_REG (reg);
8707 substed = reg_equiv_memory_loc (REGNO (reg));
8709 /* This is unsafe if the operand occurs more often in the current
8710 insn than it is inherited. */
8711 for (k = n_reloads - 1; k >= 0; k--)
8713 rtx reg2 = rld[k].in;
8716 if (MEM_P (reg2) || reload_override_in[k])
8717 reg2 = rld[k].in_reg;
8719 if (rld[k].out && ! rld[k].out_reg)
8720 reg2 = XEXP (rld[k].in_reg, 0);
8722 while (GET_CODE (reg2) == SUBREG)
8723 reg2 = SUBREG_REG (reg2);
8724 if (rtx_equal_p (reg2, reg))
8726 if (reload_inherited[k] || reload_override_in[k] || k == j)
8732 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8733 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8734 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8737 n_occurrences += count_occurrences (PATTERN (insn),
8738 eliminate_regs (substed, VOIDmode,
8740 for (i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8742 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8743 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8745 if (n_occurrences > n_inherited)
8748 regno = REGNO (reg);
8749 if (regno >= FIRST_PSEUDO_REGISTER)
8752 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8754 /* If the pseudo-reg we are reloading is no longer referenced
8755 anywhere between the store into it and here,
8756 and we're within the same basic block, then the value can only
8757 pass through the reload reg and end up here.
8758 Otherwise, give up--return. */
8759 for (i1 = NEXT_INSN (output_reload_insn);
8760 i1 != insn; i1 = NEXT_INSN (i1))
8762 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8764 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8765 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8767 /* If this is USE in front of INSN, we only have to check that
8768 there are no more references than accounted for by inheritance. */
8769 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8771 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8772 i1 = NEXT_INSN (i1);
8774 if (n_occurrences <= n_inherited && i1 == insn)
8780 /* We will be deleting the insn. Remove the spill reg information. */
8781 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8783 spill_reg_store[last_reload_reg + k] = 0;
8784 spill_reg_stored_to[last_reload_reg + k] = 0;
8787 /* The caller has already checked that REG dies or is set in INSN.
8788 It has also checked that we are optimizing, and thus some
8789 inaccuracies in the debugging information are acceptable.
8790 So we could just delete output_reload_insn. But in some cases
8791 we can improve the debugging information without sacrificing
8792 optimization - maybe even improving the code: See if the pseudo
8793 reg has been completely replaced with reload regs. If so, delete
8794 the store insn and forget we had a stack slot for the pseudo. */
8795 if (rld[j].out != rld[j].in
8796 && REG_N_DEATHS (REGNO (reg)) == 1
8797 && REG_N_SETS (REGNO (reg)) == 1
8798 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8799 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8803 /* We know that it was used only between here and the beginning of
8804 the current basic block. (We also know that the last use before
8805 INSN was the output reload we are thinking of deleting, but never
8806 mind that.) Search that range; see if any ref remains. */
8807 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8809 rtx set = single_set (i2);
8811 /* Uses which just store in the pseudo don't count,
8812 since if they are the only uses, they are dead. */
8813 if (set != 0 && SET_DEST (set) == reg)
8818 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8819 && reg_mentioned_p (reg, PATTERN (i2)))
8821 /* Some other ref remains; just delete the output reload we
8823 delete_address_reloads (output_reload_insn, insn);
8824 delete_insn (output_reload_insn);
8829 /* Delete the now-dead stores into this pseudo. Note that this
8830 loop also takes care of deleting output_reload_insn. */
8831 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8833 rtx set = single_set (i2);
8835 if (set != 0 && SET_DEST (set) == reg)
8837 delete_address_reloads (i2, insn);
8845 /* For the debugging info, say the pseudo lives in this reload reg. */
8846 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8847 if (ira_conflicts_p)
8848 /* Inform IRA about the change. */
8849 ira_mark_allocation_change (REGNO (reg));
8850 alter_reg (REGNO (reg), -1, false);
8854 delete_address_reloads (output_reload_insn, insn);
8855 delete_insn (output_reload_insn);
8859 /* We are going to delete DEAD_INSN. Recursively delete loads of
8860 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8861 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8863 delete_address_reloads (rtx dead_insn, rtx current_insn)
8865 rtx set = single_set (dead_insn);
8866 rtx set2, dst, prev, next;
8869 rtx dst = SET_DEST (set);
8871 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8873 /* If we deleted the store from a reloaded post_{in,de}c expression,
8874 we can delete the matching adds. */
8875 prev = PREV_INSN (dead_insn);
8876 next = NEXT_INSN (dead_insn);
8877 if (! prev || ! next)
8879 set = single_set (next);
8880 set2 = single_set (prev);
8882 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8883 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8884 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8886 dst = SET_DEST (set);
8887 if (! rtx_equal_p (dst, SET_DEST (set2))
8888 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8889 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8890 || (INTVAL (XEXP (SET_SRC (set), 1))
8891 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8893 delete_related_insns (prev);
8894 delete_related_insns (next);
8897 /* Subfunction of delete_address_reloads: process registers found in X. */
8899 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8901 rtx prev, set, dst, i2;
8903 enum rtx_code code = GET_CODE (x);
8907 const char *fmt = GET_RTX_FORMAT (code);
8908 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8911 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8912 else if (fmt[i] == 'E')
8914 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8915 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8922 if (spill_reg_order[REGNO (x)] < 0)
8925 /* Scan backwards for the insn that sets x. This might be a way back due
8927 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8929 code = GET_CODE (prev);
8930 if (code == CODE_LABEL || code == JUMP_INSN)
8934 if (reg_set_p (x, PATTERN (prev)))
8936 if (reg_referenced_p (x, PATTERN (prev)))
8939 if (! prev || INSN_UID (prev) < reload_first_uid)
8941 /* Check that PREV only sets the reload register. */
8942 set = single_set (prev);
8945 dst = SET_DEST (set);
8947 || ! rtx_equal_p (dst, x))
8949 if (! reg_set_p (dst, PATTERN (dead_insn)))
8951 /* Check if DST was used in a later insn -
8952 it might have been inherited. */
8953 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8959 if (reg_referenced_p (dst, PATTERN (i2)))
8961 /* If there is a reference to the register in the current insn,
8962 it might be loaded in a non-inherited reload. If no other
8963 reload uses it, that means the register is set before
8965 if (i2 == current_insn)
8967 for (j = n_reloads - 1; j >= 0; j--)
8968 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8969 || reload_override_in[j] == dst)
8971 for (j = n_reloads - 1; j >= 0; j--)
8972 if (rld[j].in && rld[j].reg_rtx == dst)
8981 /* If DST is still live at CURRENT_INSN, check if it is used for
8982 any reload. Note that even if CURRENT_INSN sets DST, we still
8983 have to check the reloads. */
8984 if (i2 == current_insn)
8986 for (j = n_reloads - 1; j >= 0; j--)
8987 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8988 || reload_override_in[j] == dst)
8990 /* ??? We can't finish the loop here, because dst might be
8991 allocated to a pseudo in this block if no reload in this
8992 block needs any of the classes containing DST - see
8993 spill_hard_reg. There is no easy way to tell this, so we
8994 have to scan till the end of the basic block. */
8996 if (reg_set_p (dst, PATTERN (i2)))
9000 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9001 reg_reloaded_contents[REGNO (dst)] = -1;
9005 /* Output reload-insns to reload VALUE into RELOADREG.
9006 VALUE is an autoincrement or autodecrement RTX whose operand
9007 is a register or memory location;
9008 so reloading involves incrementing that location.
9009 IN is either identical to VALUE, or some cheaper place to reload from.
9011 INC_AMOUNT is the number to increment or decrement by (always positive).
9012 This cannot be deduced from VALUE. */
9015 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9017 /* REG or MEM to be copied and incremented. */
9018 rtx incloc = find_replacement (&XEXP (value, 0));
9019 /* Nonzero if increment after copying. */
9020 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9021 || GET_CODE (value) == POST_MODIFY);
9026 rtx real_in = in == value ? incloc : in;
9028 /* No hard register is equivalent to this register after
9029 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9030 we could inc/dec that register as well (maybe even using it for
9031 the source), but I'm not sure it's worth worrying about. */
9033 reg_last_reload_reg[REGNO (incloc)] = 0;
9035 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9037 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9038 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9042 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9043 inc_amount = -inc_amount;
9045 inc = GEN_INT (inc_amount);
9048 /* If this is post-increment, first copy the location to the reload reg. */
9049 if (post && real_in != reloadreg)
9050 emit_insn (gen_move_insn (reloadreg, real_in));
9054 /* See if we can directly increment INCLOC. Use a method similar to
9055 that in gen_reload. */
9057 last = get_last_insn ();
9058 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9059 gen_rtx_PLUS (GET_MODE (incloc),
9062 code = recog_memoized (add_insn);
9065 extract_insn (add_insn);
9066 if (constrain_operands (1))
9068 /* If this is a pre-increment and we have incremented the value
9069 where it lives, copy the incremented value to RELOADREG to
9070 be used as an address. */
9073 emit_insn (gen_move_insn (reloadreg, incloc));
9077 delete_insns_since (last);
9080 /* If couldn't do the increment directly, must increment in RELOADREG.
9081 The way we do this depends on whether this is pre- or post-increment.
9082 For pre-increment, copy INCLOC to the reload register, increment it
9083 there, then save back. */
9087 if (in != reloadreg)
9088 emit_insn (gen_move_insn (reloadreg, real_in));
9089 emit_insn (gen_add2_insn (reloadreg, inc));
9090 emit_insn (gen_move_insn (incloc, reloadreg));
9095 Because this might be a jump insn or a compare, and because RELOADREG
9096 may not be available after the insn in an input reload, we must do
9097 the incrementation before the insn being reloaded for.
9099 We have already copied IN to RELOADREG. Increment the copy in
9100 RELOADREG, save that back, then decrement RELOADREG so it has
9101 the original value. */
9103 emit_insn (gen_add2_insn (reloadreg, inc));
9104 emit_insn (gen_move_insn (incloc, reloadreg));
9105 if (CONST_INT_P (inc))
9106 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
9108 emit_insn (gen_sub2_insn (reloadreg, inc));
9114 add_auto_inc_notes (rtx insn, rtx x)
9116 enum rtx_code code = GET_CODE (x);
9120 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9122 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9126 /* Scan all the operand sub-expressions. */
9127 fmt = GET_RTX_FORMAT (code);
9128 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9131 add_auto_inc_notes (insn, XEXP (x, i));
9132 else if (fmt[i] == 'E')
9133 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9134 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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