1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
45 /* This file contains the reload pass of the compiler, which is
46 run after register allocation has been done. It checks that
47 each insn is valid (operands required to be in registers really
48 are in registers of the proper class) and fixes up invalid ones
49 by copying values temporarily into registers for the insns
52 The results of register allocation are described by the vector
53 reg_renumber; the insns still contain pseudo regs, but reg_renumber
54 can be used to find which hard reg, if any, a pseudo reg is in.
56 The technique we always use is to free up a few hard regs that are
57 called ``reload regs'', and for each place where a pseudo reg
58 must be in a hard reg, copy it temporarily into one of the reload regs.
60 Reload regs are allocated locally for every instruction that needs
61 reloads. When there are pseudos which are allocated to a register that
62 has been chosen as a reload reg, such pseudos must be ``spilled''.
63 This means that they go to other hard regs, or to stack slots if no other
64 available hard regs can be found. Spilling can invalidate more
65 insns, requiring additional need for reloads, so we must keep checking
66 until the process stabilizes.
68 For machines with different classes of registers, we must keep track
69 of the register class needed for each reload, and make sure that
70 we allocate enough reload registers of each class.
72 The file reload.c contains the code that checks one insn for
73 validity and reports the reloads that it needs. This file
74 is in charge of scanning the entire rtl code, accumulating the
75 reload needs, spilling, assigning reload registers to use for
76 fixing up each insn, and generating the new insns to copy values
77 into the reload registers. */
79 #ifndef REGISTER_MOVE_COST
80 #define REGISTER_MOVE_COST(m, x, y) 2
84 #define LOCAL_REGNO(REGNO) 0
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static unsigned int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Nonzero if indirect addressing is supported on the machine; this means
219 that spilling (REG n) does not require reloading it into a register in
220 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
221 value indicates the level of indirect addressing supported, e.g., two
222 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
224 static char spill_indirect_levels;
226 /* Nonzero if indirect addressing is supported when the innermost MEM is
227 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
228 which these are valid is the same as spill_indirect_levels, above. */
229 char indirect_symref_ok;
231 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
232 char double_reg_address_ok;
234 /* Record the stack slot for each spilled hard register. */
235 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
237 /* Width allocated so far for that stack slot. */
238 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Record which pseudos needed to be spilled. */
241 static regset_head spilled_pseudos;
243 /* Used for communication between order_regs_for_reload and count_pseudo.
244 Used to avoid counting one pseudo twice. */
245 static regset_head pseudos_counted;
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
253 int caller_save_needed;
255 /* Set to 1 while reload_as_needed is operating.
256 Required by some machines to handle any generated moves differently. */
257 int reload_in_progress = 0;
259 /* These arrays record the insn_code of insns that may be needed to
260 perform input and output reloads of special objects. They provide a
261 place to pass a scratch register. */
262 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
263 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
265 /* This obstack is used for allocation of rtl during register elimination.
266 The allocated storage can be freed once find_reloads has processed the
268 struct obstack reload_obstack;
270 /* Points to the beginning of the reload_obstack. All insn_chain structures
271 are allocated first. */
272 char *reload_startobj;
274 /* The point after all insn_chain structures. Used to quickly deallocate
275 memory allocated in copy_reloads during calculate_needs_all_insns. */
276 char *reload_firstobj;
278 /* This points before all local rtl generated by register elimination.
279 Used to quickly free all memory after processing one insn. */
280 static char *reload_insn_firstobj;
282 #define obstack_chunk_alloc xmalloc
283 #define obstack_chunk_free free
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Non-zero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If non-zero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 static void replace_pseudos_in_call_usage PARAMS((rtx *,
372 static void maybe_fix_stack_asms PARAMS ((void));
373 static void copy_reloads PARAMS ((struct insn_chain *));
374 static void calculate_needs_all_insns PARAMS ((int));
375 static int find_reg PARAMS ((struct insn_chain *, int));
376 static void find_reload_regs PARAMS ((struct insn_chain *));
377 static void select_reload_regs PARAMS ((void));
378 static void delete_caller_save_insns PARAMS ((void));
380 static void spill_failure PARAMS ((rtx, enum reg_class));
381 static void count_spilled_pseudo PARAMS ((int, int, int));
382 static void delete_dead_insn PARAMS ((rtx));
383 static void alter_reg PARAMS ((int, int));
384 static void set_label_offsets PARAMS ((rtx, rtx, int));
385 static void check_eliminable_occurrences PARAMS ((rtx));
386 static void elimination_effects PARAMS ((rtx, enum machine_mode));
387 static int eliminate_regs_in_insn PARAMS ((rtx, int));
388 static void update_eliminable_offsets PARAMS ((void));
389 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
390 static void set_initial_elim_offsets PARAMS ((void));
391 static void verify_initial_elim_offsets PARAMS ((void));
392 static void set_initial_label_offsets PARAMS ((void));
393 static void set_offsets_for_label PARAMS ((rtx));
394 static void init_elim_table PARAMS ((void));
395 static void update_eliminables PARAMS ((HARD_REG_SET *));
396 static void spill_hard_reg PARAMS ((unsigned int, int));
397 static int finish_spills PARAMS ((int));
398 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
399 static void scan_paradoxical_subregs PARAMS ((rtx));
400 static void count_pseudo PARAMS ((int));
401 static void order_regs_for_reload PARAMS ((struct insn_chain *));
402 static void reload_as_needed PARAMS ((int));
403 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
404 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
405 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
411 static int reload_reg_free_p PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
415 rtx, rtx, int, int));
416 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
417 enum reload_type, rtx, rtx,
419 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
421 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
423 static int conflicts_with_override PARAMS ((rtx));
424 static void failed_reload PARAMS ((rtx, int));
425 static int set_reload_reg PARAMS ((int, int));
426 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
427 static void choose_reload_regs PARAMS ((struct insn_chain *));
428 static void merge_assigned_reloads PARAMS ((rtx));
429 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
430 struct reload *, rtx, int));
431 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void do_input_reload PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_output_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void emit_reload_insns PARAMS ((struct insn_chain *));
438 static void delete_output_reload PARAMS ((rtx, int, int));
439 static void delete_address_reloads PARAMS ((rtx, rtx));
440 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
441 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
442 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
443 static void reload_cse_regs_1 PARAMS ((rtx));
444 static int reload_cse_noop_set_p PARAMS ((rtx));
445 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
446 static int reload_cse_simplify_operands PARAMS ((rtx));
447 static void reload_combine PARAMS ((void));
448 static void reload_combine_note_use PARAMS ((rtx *, rtx));
449 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
450 static void reload_cse_move2add PARAMS ((rtx));
451 static void move2add_note_store PARAMS ((rtx, rtx, void *));
453 static void add_auto_inc_notes PARAMS ((rtx, rtx));
455 static void copy_eh_notes PARAMS ((rtx, rtx));
456 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
458 static void failed_reload PARAMS ((rtx, int));
459 static int set_reload_reg PARAMS ((int, int));
460 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
461 static void reload_cse_simplify PARAMS ((rtx));
462 static void fixup_abnormal_edges PARAMS ((void));
463 extern void dump_needs PARAMS ((struct insn_chain *));
465 /* Initialize the reload pass once per compilation. */
472 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
473 Set spill_indirect_levels to the number of levels such addressing is
474 permitted, zero if it is not permitted at all. */
477 = gen_rtx_MEM (Pmode,
480 LAST_VIRTUAL_REGISTER + 1),
482 spill_indirect_levels = 0;
484 while (memory_address_p (QImode, tem))
486 spill_indirect_levels++;
487 tem = gen_rtx_MEM (Pmode, tem);
490 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
492 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
493 indirect_symref_ok = memory_address_p (QImode, tem);
495 /* See if reg+reg is a valid (and offsettable) address. */
497 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
499 tem = gen_rtx_PLUS (Pmode,
500 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
501 gen_rtx_REG (Pmode, i));
503 /* This way, we make sure that reg+reg is an offsettable address. */
504 tem = plus_constant (tem, 4);
506 if (memory_address_p (QImode, tem))
508 double_reg_address_ok = 1;
513 /* Initialize obstack for our rtl allocation. */
514 gcc_obstack_init (&reload_obstack);
515 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
517 INIT_REG_SET (&spilled_pseudos);
518 INIT_REG_SET (&pseudos_counted);
521 /* List of insn chains that are currently unused. */
522 static struct insn_chain *unused_insn_chains = 0;
524 /* Allocate an empty insn_chain structure. */
528 struct insn_chain *c;
530 if (unused_insn_chains == 0)
532 c = (struct insn_chain *)
533 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
534 INIT_REG_SET (&c->live_throughout);
535 INIT_REG_SET (&c->dead_or_set);
539 c = unused_insn_chains;
540 unused_insn_chains = c->next;
542 c->is_caller_save_insn = 0;
543 c->need_operand_change = 0;
549 /* Small utility function to set all regs in hard reg set TO which are
550 allocated to pseudos in regset FROM. */
553 compute_use_by_pseudos (to, from)
559 EXECUTE_IF_SET_IN_REG_SET
560 (from, FIRST_PSEUDO_REGISTER, regno,
562 int r = reg_renumber[regno];
567 /* reload_combine uses the information from
568 BASIC_BLOCK->global_live_at_start, which might still
569 contain registers that have not actually been allocated
570 since they have an equivalence. */
571 if (! reload_completed)
576 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
578 SET_HARD_REG_BIT (*to, r + nregs);
583 /* Replace all pseudos found in LOC with their corresponding
587 replace_pseudos_in_call_usage (loc, mem_mode, usage)
589 enum machine_mode mem_mode;
603 unsigned int regno = REGNO (x);
605 if (regno < FIRST_PSEUDO_REGISTER)
608 x = eliminate_regs (x, mem_mode, usage);
612 replace_pseudos_in_call_usage (loc, mem_mode, usage);
616 if (reg_equiv_constant[regno])
617 *loc = reg_equiv_constant[regno];
618 else if (reg_equiv_mem[regno])
619 *loc = reg_equiv_mem[regno];
620 else if (reg_equiv_address[regno])
621 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
622 else if (GET_CODE (regno_reg_rtx[regno]) != REG
623 || REGNO (regno_reg_rtx[regno]) != regno)
624 *loc = regno_reg_rtx[regno];
630 else if (code == MEM)
632 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
636 /* Process each of our operands recursively. */
637 fmt = GET_RTX_FORMAT (code);
638 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
640 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
641 else if (*fmt == 'E')
642 for (j = 0; j < XVECLEN (x, i); j++)
643 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
647 /* Global variables used by reload and its subroutines. */
649 /* Set during calculate_needs if an insn needs register elimination. */
650 static int something_needs_elimination;
651 /* Set during calculate_needs if an insn needs an operand changed. */
652 int something_needs_operands_changed;
654 /* Nonzero means we couldn't get enough spill regs. */
657 /* Main entry point for the reload pass.
659 FIRST is the first insn of the function being compiled.
661 GLOBAL nonzero means we were called from global_alloc
662 and should attempt to reallocate any pseudoregs that we
663 displace from hard regs we will use for reloads.
664 If GLOBAL is zero, we do not have enough information to do that,
665 so any pseudo reg that is spilled must go to the stack.
667 Return value is nonzero if reload failed
668 and we must not do any more for this function. */
671 reload (first, global)
677 struct elim_table *ep;
679 /* The two pointers used to track the true location of the memory used
680 for label offsets. */
681 char *real_known_ptr = NULL;
682 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
684 /* Make sure even insns with volatile mem refs are recognizable. */
689 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
691 /* Make sure that the last insn in the chain
692 is not something that needs reloading. */
693 emit_note (NULL, NOTE_INSN_DELETED);
695 /* Enable find_equiv_reg to distinguish insns made by reload. */
696 reload_first_uid = get_max_uid ();
698 #ifdef SECONDARY_MEMORY_NEEDED
699 /* Initialize the secondary memory table. */
700 clear_secondary_mem ();
703 /* We don't have a stack slot for any spill reg yet. */
704 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
705 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
707 /* Initialize the save area information for caller-save, in case some
711 /* Compute which hard registers are now in use
712 as homes for pseudo registers.
713 This is done here rather than (eg) in global_alloc
714 because this point is reached even if not optimizing. */
715 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
718 /* A function that receives a nonlocal goto must save all call-saved
720 if (current_function_has_nonlocal_label)
721 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
722 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
723 regs_ever_live[i] = 1;
725 /* Find all the pseudo registers that didn't get hard regs
726 but do have known equivalent constants or memory slots.
727 These include parameters (known equivalent to parameter slots)
728 and cse'd or loop-moved constant memory addresses.
730 Record constant equivalents in reg_equiv_constant
731 so they will be substituted by find_reloads.
732 Record memory equivalents in reg_mem_equiv so they can
733 be substituted eventually by altering the REG-rtx's. */
735 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
740 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
741 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
742 pseudo_forbidden_regs
743 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
745 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
747 CLEAR_HARD_REG_SET (bad_spill_regs_global);
749 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
750 Also find all paradoxical subregs and find largest such for each pseudo.
751 On machines with small register classes, record hard registers that
752 are used for user variables. These can never be used for spills.
753 Also look for a "constant" REG_SETJMP. This means that all
754 caller-saved registers must be marked live. */
756 num_eliminable_invariants = 0;
757 for (insn = first; insn; insn = NEXT_INSN (insn))
759 rtx set = single_set (insn);
761 /* We may introduce USEs that we want to remove at the end, so
762 we'll mark them with QImode. Make sure there are no
763 previously-marked insns left by say regmove. */
764 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
765 && GET_MODE (insn) != VOIDmode)
766 PUT_MODE (insn, VOIDmode);
768 if (GET_CODE (insn) == CALL_INSN
769 && find_reg_note (insn, REG_SETJMP, NULL))
770 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
771 if (! call_used_regs[i])
772 regs_ever_live[i] = 1;
774 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
776 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
778 #ifdef LEGITIMATE_PIC_OPERAND_P
779 && (! function_invariant_p (XEXP (note, 0))
781 /* A function invariant is often CONSTANT_P but may
782 include a register. We promise to only pass
783 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
784 || (CONSTANT_P (XEXP (note, 0))
785 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
789 rtx x = XEXP (note, 0);
790 i = REGNO (SET_DEST (set));
791 if (i > LAST_VIRTUAL_REGISTER)
793 if (GET_CODE (x) == MEM)
795 /* Always unshare the equivalence, so we can
796 substitute into this insn without touching the
798 reg_equiv_memory_loc[i] = copy_rtx (x);
800 else if (function_invariant_p (x))
802 if (GET_CODE (x) == PLUS)
804 /* This is PLUS of frame pointer and a constant,
805 and might be shared. Unshare it. */
806 reg_equiv_constant[i] = copy_rtx (x);
807 num_eliminable_invariants++;
809 else if (x == frame_pointer_rtx
810 || x == arg_pointer_rtx)
812 reg_equiv_constant[i] = x;
813 num_eliminable_invariants++;
815 else if (LEGITIMATE_CONSTANT_P (x))
816 reg_equiv_constant[i] = x;
818 reg_equiv_memory_loc[i]
819 = force_const_mem (GET_MODE (SET_DEST (set)), x);
824 /* If this register is being made equivalent to a MEM
825 and the MEM is not SET_SRC, the equivalencing insn
826 is one with the MEM as a SET_DEST and it occurs later.
827 So don't mark this insn now. */
828 if (GET_CODE (x) != MEM
829 || rtx_equal_p (SET_SRC (set), x))
831 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
836 /* If this insn is setting a MEM from a register equivalent to it,
837 this is the equivalencing insn. */
838 else if (set && GET_CODE (SET_DEST (set)) == MEM
839 && GET_CODE (SET_SRC (set)) == REG
840 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
841 && rtx_equal_p (SET_DEST (set),
842 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
843 reg_equiv_init[REGNO (SET_SRC (set))]
844 = gen_rtx_INSN_LIST (VOIDmode, insn,
845 reg_equiv_init[REGNO (SET_SRC (set))]);
848 scan_paradoxical_subregs (PATTERN (insn));
853 num_labels = max_label_num () - get_first_label_num ();
855 /* Allocate the tables used to store offset information at labels. */
856 /* We used to use alloca here, but the size of what it would try to
857 allocate would occasionally cause it to exceed the stack limit and
858 cause a core dump. */
859 real_known_ptr = xmalloc (num_labels);
861 = (int (*)[NUM_ELIMINABLE_REGS])
862 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
864 offsets_known_at = real_known_ptr - get_first_label_num ();
866 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
868 /* Alter each pseudo-reg rtx to contain its hard reg number.
869 Assign stack slots to the pseudos that lack hard regs or equivalents.
870 Do not touch virtual registers. */
872 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
875 /* If we have some registers we think can be eliminated, scan all insns to
876 see if there is an insn that sets one of these registers to something
877 other than itself plus a constant. If so, the register cannot be
878 eliminated. Doing this scan here eliminates an extra pass through the
879 main reload loop in the most common case where register elimination
881 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
882 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
883 || GET_CODE (insn) == CALL_INSN)
884 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
886 maybe_fix_stack_asms ();
888 insns_need_reload = 0;
889 something_needs_elimination = 0;
891 /* Initialize to -1, which means take the first spill register. */
894 /* Spill any hard regs that we know we can't eliminate. */
895 CLEAR_HARD_REG_SET (used_spill_regs);
896 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
897 if (! ep->can_eliminate)
898 spill_hard_reg (ep->from, 1);
900 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
901 if (frame_pointer_needed)
902 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
904 finish_spills (global);
906 /* From now on, we may need to generate moves differently. We may also
907 allow modifications of insns which cause them to not be recognized.
908 Any such modifications will be cleaned up during reload itself. */
909 reload_in_progress = 1;
911 /* This loop scans the entire function each go-round
912 and repeats until one repetition spills no additional hard regs. */
915 int something_changed;
918 HOST_WIDE_INT starting_frame_size;
920 /* Round size of stack frame to stack_alignment_needed. This must be done
921 here because the stack size may be a part of the offset computation
922 for register elimination, and there might have been new stack slots
923 created in the last iteration of this loop. */
924 if (cfun->stack_alignment_needed)
925 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
927 starting_frame_size = get_frame_size ();
929 set_initial_elim_offsets ();
930 set_initial_label_offsets ();
932 /* For each pseudo register that has an equivalent location defined,
933 try to eliminate any eliminable registers (such as the frame pointer)
934 assuming initial offsets for the replacement register, which
937 If the resulting location is directly addressable, substitute
938 the MEM we just got directly for the old REG.
940 If it is not addressable but is a constant or the sum of a hard reg
941 and constant, it is probably not addressable because the constant is
942 out of range, in that case record the address; we will generate
943 hairy code to compute the address in a register each time it is
944 needed. Similarly if it is a hard register, but one that is not
945 valid as an address register.
947 If the location is not addressable, but does not have one of the
948 above forms, assign a stack slot. We have to do this to avoid the
949 potential of producing lots of reloads if, e.g., a location involves
950 a pseudo that didn't get a hard register and has an equivalent memory
951 location that also involves a pseudo that didn't get a hard register.
953 Perhaps at some point we will improve reload_when_needed handling
954 so this problem goes away. But that's very hairy. */
956 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
957 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
959 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
961 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
963 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
964 else if (CONSTANT_P (XEXP (x, 0))
965 || (GET_CODE (XEXP (x, 0)) == REG
966 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
967 || (GET_CODE (XEXP (x, 0)) == PLUS
968 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
969 && (REGNO (XEXP (XEXP (x, 0), 0))
970 < FIRST_PSEUDO_REGISTER)
971 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
972 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
975 /* Make a new stack slot. Then indicate that something
976 changed so we go back and recompute offsets for
977 eliminable registers because the allocation of memory
978 below might change some offset. reg_equiv_{mem,address}
979 will be set up for this pseudo on the next pass around
981 reg_equiv_memory_loc[i] = 0;
982 reg_equiv_init[i] = 0;
987 if (caller_save_needed)
990 /* If we allocated another stack slot, redo elimination bookkeeping. */
991 if (starting_frame_size != get_frame_size ())
994 if (caller_save_needed)
996 save_call_clobbered_regs ();
997 /* That might have allocated new insn_chain structures. */
998 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1001 calculate_needs_all_insns (global);
1003 CLEAR_REG_SET (&spilled_pseudos);
1006 something_changed = 0;
1008 /* If we allocated any new memory locations, make another pass
1009 since it might have changed elimination offsets. */
1010 if (starting_frame_size != get_frame_size ())
1011 something_changed = 1;
1014 HARD_REG_SET to_spill;
1015 CLEAR_HARD_REG_SET (to_spill);
1016 update_eliminables (&to_spill);
1017 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1018 if (TEST_HARD_REG_BIT (to_spill, i))
1020 spill_hard_reg (i, 1);
1023 /* Regardless of the state of spills, if we previously had
1024 a register that we thought we could eliminate, but no can
1025 not eliminate, we must run another pass.
1027 Consider pseudos which have an entry in reg_equiv_* which
1028 reference an eliminable register. We must make another pass
1029 to update reg_equiv_* so that we do not substitute in the
1030 old value from when we thought the elimination could be
1032 something_changed = 1;
1036 select_reload_regs ();
1040 if (insns_need_reload != 0 || did_spill)
1041 something_changed |= finish_spills (global);
1043 if (! something_changed)
1046 if (caller_save_needed)
1047 delete_caller_save_insns ();
1049 obstack_free (&reload_obstack, reload_firstobj);
1052 /* If global-alloc was run, notify it of any register eliminations we have
1055 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1056 if (ep->can_eliminate)
1057 mark_elimination (ep->from, ep->to);
1059 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1060 If that insn didn't set the register (i.e., it copied the register to
1061 memory), just delete that insn instead of the equivalencing insn plus
1062 anything now dead. If we call delete_dead_insn on that insn, we may
1063 delete the insn that actually sets the register if the register dies
1064 there and that is incorrect. */
1066 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1068 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1071 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1073 rtx equiv_insn = XEXP (list, 0);
1075 /* If we already deleted the insn or if it may trap, we can't
1076 delete it. The latter case shouldn't happen, but can
1077 if an insn has a variable address, gets a REG_EH_REGION
1078 note added to it, and then gets converted into an load
1079 from a constant address. */
1080 if (GET_CODE (equiv_insn) == NOTE
1081 || can_throw_internal (equiv_insn))
1083 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1084 delete_dead_insn (equiv_insn);
1087 PUT_CODE (equiv_insn, NOTE);
1088 NOTE_SOURCE_FILE (equiv_insn) = 0;
1089 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1095 /* Use the reload registers where necessary
1096 by generating move instructions to move the must-be-register
1097 values into or out of the reload registers. */
1099 if (insns_need_reload != 0 || something_needs_elimination
1100 || something_needs_operands_changed)
1102 HOST_WIDE_INT old_frame_size = get_frame_size ();
1104 reload_as_needed (global);
1106 if (old_frame_size != get_frame_size ())
1110 verify_initial_elim_offsets ();
1113 /* If we were able to eliminate the frame pointer, show that it is no
1114 longer live at the start of any basic block. If it ls live by
1115 virtue of being in a pseudo, that pseudo will be marked live
1116 and hence the frame pointer will be known to be live via that
1119 if (! frame_pointer_needed)
1120 for (i = 0; i < n_basic_blocks; i++)
1121 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1122 HARD_FRAME_POINTER_REGNUM);
1124 /* Come here (with failure set nonzero) if we can't get enough spill regs
1125 and we decide not to abort about it. */
1128 CLEAR_REG_SET (&spilled_pseudos);
1129 reload_in_progress = 0;
1131 /* Now eliminate all pseudo regs by modifying them into
1132 their equivalent memory references.
1133 The REG-rtx's for the pseudos are modified in place,
1134 so all insns that used to refer to them now refer to memory.
1136 For a reg that has a reg_equiv_address, all those insns
1137 were changed by reloading so that no insns refer to it any longer;
1138 but the DECL_RTL of a variable decl may refer to it,
1139 and if so this causes the debugging info to mention the variable. */
1141 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1145 if (reg_equiv_mem[i])
1146 addr = XEXP (reg_equiv_mem[i], 0);
1148 if (reg_equiv_address[i])
1149 addr = reg_equiv_address[i];
1153 if (reg_renumber[i] < 0)
1155 rtx reg = regno_reg_rtx[i];
1157 PUT_CODE (reg, MEM);
1158 XEXP (reg, 0) = addr;
1159 REG_USERVAR_P (reg) = 0;
1160 if (reg_equiv_memory_loc[i])
1161 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1164 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1165 = MEM_SCALAR_P (reg) = 0;
1166 MEM_ATTRS (reg) = 0;
1169 else if (reg_equiv_mem[i])
1170 XEXP (reg_equiv_mem[i], 0) = addr;
1174 /* We must set reload_completed now since the cleanup_subreg_operands call
1175 below will re-recognize each insn and reload may have generated insns
1176 which are only valid during and after reload. */
1177 reload_completed = 1;
1179 /* Make a pass over all the insns and delete all USEs which we inserted
1180 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1181 notes. Delete all CLOBBER insns that don't refer to the return value
1182 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1183 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1184 and regenerate REG_INC notes that may have been moved around. */
1186 for (insn = first; insn; insn = NEXT_INSN (insn))
1191 if (GET_CODE (insn) == CALL_INSN)
1192 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1194 CALL_INSN_FUNCTION_USAGE (insn));
1196 if ((GET_CODE (PATTERN (insn)) == USE
1197 /* We mark with QImode USEs introduced by reload itself. */
1198 && (GET_MODE (insn) == QImode
1199 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1200 || (GET_CODE (PATTERN (insn)) == CLOBBER
1201 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1202 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1208 pnote = ®_NOTES (insn);
1211 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1212 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1213 || REG_NOTE_KIND (*pnote) == REG_INC
1214 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1215 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1216 *pnote = XEXP (*pnote, 1);
1218 pnote = &XEXP (*pnote, 1);
1222 add_auto_inc_notes (insn, PATTERN (insn));
1225 /* And simplify (subreg (reg)) if it appears as an operand. */
1226 cleanup_subreg_operands (insn);
1229 /* If we are doing stack checking, give a warning if this function's
1230 frame size is larger than we expect. */
1231 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1233 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1234 static int verbose_warned = 0;
1236 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1237 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1238 size += UNITS_PER_WORD;
1240 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1242 warning ("frame size too large for reliable stack checking");
1243 if (! verbose_warned)
1245 warning ("try reducing the number of local variables");
1251 /* Indicate that we no longer have known memory locations or constants. */
1252 if (reg_equiv_constant)
1253 free (reg_equiv_constant);
1254 reg_equiv_constant = 0;
1255 if (reg_equiv_memory_loc)
1256 free (reg_equiv_memory_loc);
1257 reg_equiv_memory_loc = 0;
1260 free (real_known_ptr);
1264 free (reg_equiv_mem);
1265 free (reg_equiv_init);
1266 free (reg_equiv_address);
1267 free (reg_max_ref_width);
1268 free (reg_old_renumber);
1269 free (pseudo_previous_regs);
1270 free (pseudo_forbidden_regs);
1272 CLEAR_HARD_REG_SET (used_spill_regs);
1273 for (i = 0; i < n_spills; i++)
1274 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1276 /* Free all the insn_chain structures at once. */
1277 obstack_free (&reload_obstack, reload_startobj);
1278 unused_insn_chains = 0;
1279 fixup_abnormal_edges ();
1284 /* Yet another special case. Unfortunately, reg-stack forces people to
1285 write incorrect clobbers in asm statements. These clobbers must not
1286 cause the register to appear in bad_spill_regs, otherwise we'll call
1287 fatal_insn later. We clear the corresponding regnos in the live
1288 register sets to avoid this.
1289 The whole thing is rather sick, I'm afraid. */
1292 maybe_fix_stack_asms ()
1295 const char *constraints[MAX_RECOG_OPERANDS];
1296 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1297 struct insn_chain *chain;
1299 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1302 HARD_REG_SET clobbered, allowed;
1305 if (! INSN_P (chain->insn)
1306 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1308 pat = PATTERN (chain->insn);
1309 if (GET_CODE (pat) != PARALLEL)
1312 CLEAR_HARD_REG_SET (clobbered);
1313 CLEAR_HARD_REG_SET (allowed);
1315 /* First, make a mask of all stack regs that are clobbered. */
1316 for (i = 0; i < XVECLEN (pat, 0); i++)
1318 rtx t = XVECEXP (pat, 0, i);
1319 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1320 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1323 /* Get the operand values and constraints out of the insn. */
1324 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1325 constraints, operand_mode);
1327 /* For every operand, see what registers are allowed. */
1328 for (i = 0; i < noperands; i++)
1330 const char *p = constraints[i];
1331 /* For every alternative, we compute the class of registers allowed
1332 for reloading in CLS, and merge its contents into the reg set
1334 int cls = (int) NO_REGS;
1340 if (c == '\0' || c == ',' || c == '#')
1342 /* End of one alternative - mark the regs in the current
1343 class, and reset the class. */
1344 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1349 } while (c != '\0' && c != ',');
1357 case '=': case '+': case '*': case '%': case '?': case '!':
1358 case '0': case '1': case '2': case '3': case '4': case 'm':
1359 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1360 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1361 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1366 cls = (int) reg_class_subunion[cls]
1367 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1372 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1376 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1381 /* Those of the registers which are clobbered, but allowed by the
1382 constraints, must be usable as reload registers. So clear them
1383 out of the life information. */
1384 AND_HARD_REG_SET (allowed, clobbered);
1385 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1386 if (TEST_HARD_REG_BIT (allowed, i))
1388 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1389 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1396 /* Copy the global variables n_reloads and rld into the corresponding elts
1399 copy_reloads (chain)
1400 struct insn_chain *chain;
1402 chain->n_reloads = n_reloads;
1404 = (struct reload *) obstack_alloc (&reload_obstack,
1405 n_reloads * sizeof (struct reload));
1406 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1407 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1410 /* Walk the chain of insns, and determine for each whether it needs reloads
1411 and/or eliminations. Build the corresponding insns_need_reload list, and
1412 set something_needs_elimination as appropriate. */
1414 calculate_needs_all_insns (global)
1417 struct insn_chain **pprev_reload = &insns_need_reload;
1418 struct insn_chain *chain, *next = 0;
1420 something_needs_elimination = 0;
1422 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1423 for (chain = reload_insn_chain; chain != 0; chain = next)
1425 rtx insn = chain->insn;
1429 /* Clear out the shortcuts. */
1430 chain->n_reloads = 0;
1431 chain->need_elim = 0;
1432 chain->need_reload = 0;
1433 chain->need_operand_change = 0;
1435 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1436 include REG_LABEL), we need to see what effects this has on the
1437 known offsets at labels. */
1439 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1440 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1441 set_label_offsets (insn, insn, 0);
1445 rtx old_body = PATTERN (insn);
1446 int old_code = INSN_CODE (insn);
1447 rtx old_notes = REG_NOTES (insn);
1448 int did_elimination = 0;
1449 int operands_changed = 0;
1450 rtx set = single_set (insn);
1452 /* Skip insns that only set an equivalence. */
1453 if (set && GET_CODE (SET_DEST (set)) == REG
1454 && reg_renumber[REGNO (SET_DEST (set))] < 0
1455 && reg_equiv_constant[REGNO (SET_DEST (set))])
1458 /* If needed, eliminate any eliminable registers. */
1459 if (num_eliminable || num_eliminable_invariants)
1460 did_elimination = eliminate_regs_in_insn (insn, 0);
1462 /* Analyze the instruction. */
1463 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1464 global, spill_reg_order);
1466 /* If a no-op set needs more than one reload, this is likely
1467 to be something that needs input address reloads. We
1468 can't get rid of this cleanly later, and it is of no use
1469 anyway, so discard it now.
1470 We only do this when expensive_optimizations is enabled,
1471 since this complements reload inheritance / output
1472 reload deletion, and it can make debugging harder. */
1473 if (flag_expensive_optimizations && n_reloads > 1)
1475 rtx set = single_set (insn);
1477 && SET_SRC (set) == SET_DEST (set)
1478 && GET_CODE (SET_SRC (set)) == REG
1479 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1482 /* Delete it from the reload chain */
1484 chain->prev->next = next;
1486 reload_insn_chain = next;
1488 next->prev = chain->prev;
1489 chain->next = unused_insn_chains;
1490 unused_insn_chains = chain;
1495 update_eliminable_offsets ();
1497 /* Remember for later shortcuts which insns had any reloads or
1498 register eliminations. */
1499 chain->need_elim = did_elimination;
1500 chain->need_reload = n_reloads > 0;
1501 chain->need_operand_change = operands_changed;
1503 /* Discard any register replacements done. */
1504 if (did_elimination)
1506 obstack_free (&reload_obstack, reload_insn_firstobj);
1507 PATTERN (insn) = old_body;
1508 INSN_CODE (insn) = old_code;
1509 REG_NOTES (insn) = old_notes;
1510 something_needs_elimination = 1;
1513 something_needs_operands_changed |= operands_changed;
1517 copy_reloads (chain);
1518 *pprev_reload = chain;
1519 pprev_reload = &chain->next_need_reload;
1526 /* Comparison function for qsort to decide which of two reloads
1527 should be handled first. *P1 and *P2 are the reload numbers. */
1530 reload_reg_class_lower (r1p, r2p)
1534 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1537 /* Consider required reloads before optional ones. */
1538 t = rld[r1].optional - rld[r2].optional;
1542 /* Count all solitary classes before non-solitary ones. */
1543 t = ((reg_class_size[(int) rld[r2].class] == 1)
1544 - (reg_class_size[(int) rld[r1].class] == 1));
1548 /* Aside from solitaires, consider all multi-reg groups first. */
1549 t = rld[r2].nregs - rld[r1].nregs;
1553 /* Consider reloads in order of increasing reg-class number. */
1554 t = (int) rld[r1].class - (int) rld[r2].class;
1558 /* If reloads are equally urgent, sort by reload number,
1559 so that the results of qsort leave nothing to chance. */
1563 /* The cost of spilling each hard reg. */
1564 static int spill_cost[FIRST_PSEUDO_REGISTER];
1566 /* When spilling multiple hard registers, we use SPILL_COST for the first
1567 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1568 only the first hard reg for a multi-reg pseudo. */
1569 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1571 /* Update the spill cost arrays, considering that pseudo REG is live. */
1577 int freq = REG_FREQ (reg);
1578 int r = reg_renumber[reg];
1581 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1582 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1585 SET_REGNO_REG_SET (&pseudos_counted, reg);
1590 spill_add_cost[r] += freq;
1592 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1594 spill_cost[r + nregs] += freq;
1597 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1598 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1601 order_regs_for_reload (chain)
1602 struct insn_chain *chain;
1605 HARD_REG_SET used_by_pseudos;
1606 HARD_REG_SET used_by_pseudos2;
1608 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1610 memset (spill_cost, 0, sizeof spill_cost);
1611 memset (spill_add_cost, 0, sizeof spill_add_cost);
1613 /* Count number of uses of each hard reg by pseudo regs allocated to it
1614 and then order them by decreasing use. First exclude hard registers
1615 that are live in or across this insn. */
1617 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1618 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1619 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1620 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1622 /* Now find out which pseudos are allocated to it, and update
1624 CLEAR_REG_SET (&pseudos_counted);
1626 EXECUTE_IF_SET_IN_REG_SET
1627 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1631 EXECUTE_IF_SET_IN_REG_SET
1632 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1636 CLEAR_REG_SET (&pseudos_counted);
1639 /* Vector of reload-numbers showing the order in which the reloads should
1641 static short reload_order[MAX_RELOADS];
1643 /* This is used to keep track of the spill regs used in one insn. */
1644 static HARD_REG_SET used_spill_regs_local;
1646 /* We decided to spill hard register SPILLED, which has a size of
1647 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1648 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1649 update SPILL_COST/SPILL_ADD_COST. */
1652 count_spilled_pseudo (spilled, spilled_nregs, reg)
1653 int spilled, spilled_nregs, reg;
1655 int r = reg_renumber[reg];
1656 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1658 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1659 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1662 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1664 spill_add_cost[r] -= REG_FREQ (reg);
1666 spill_cost[r + nregs] -= REG_FREQ (reg);
1669 /* Find reload register to use for reload number ORDER. */
1672 find_reg (chain, order)
1673 struct insn_chain *chain;
1676 int rnum = reload_order[order];
1677 struct reload *rl = rld + rnum;
1678 int best_cost = INT_MAX;
1682 HARD_REG_SET not_usable;
1683 HARD_REG_SET used_by_other_reload;
1685 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1686 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1687 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1689 CLEAR_HARD_REG_SET (used_by_other_reload);
1690 for (k = 0; k < order; k++)
1692 int other = reload_order[k];
1694 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1695 for (j = 0; j < rld[other].nregs; j++)
1696 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1699 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1701 unsigned int regno = i;
1703 if (! TEST_HARD_REG_BIT (not_usable, regno)
1704 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1705 && HARD_REGNO_MODE_OK (regno, rl->mode))
1707 int this_cost = spill_cost[regno];
1709 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1711 for (j = 1; j < this_nregs; j++)
1713 this_cost += spill_add_cost[regno + j];
1714 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1715 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1720 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1722 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1724 if (this_cost < best_cost
1725 /* Among registers with equal cost, prefer caller-saved ones, or
1726 use REG_ALLOC_ORDER if it is defined. */
1727 || (this_cost == best_cost
1728 #ifdef REG_ALLOC_ORDER
1729 && (inv_reg_alloc_order[regno]
1730 < inv_reg_alloc_order[best_reg])
1732 && call_used_regs[regno]
1733 && ! call_used_regs[best_reg]
1738 best_cost = this_cost;
1746 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1748 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1749 rl->regno = best_reg;
1751 EXECUTE_IF_SET_IN_REG_SET
1752 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1754 count_spilled_pseudo (best_reg, rl->nregs, j);
1757 EXECUTE_IF_SET_IN_REG_SET
1758 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1760 count_spilled_pseudo (best_reg, rl->nregs, j);
1763 for (i = 0; i < rl->nregs; i++)
1765 if (spill_cost[best_reg + i] != 0
1766 || spill_add_cost[best_reg + i] != 0)
1768 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1773 /* Find more reload regs to satisfy the remaining need of an insn, which
1775 Do it by ascending class number, since otherwise a reg
1776 might be spilled for a big class and might fail to count
1777 for a smaller class even though it belongs to that class. */
1780 find_reload_regs (chain)
1781 struct insn_chain *chain;
1785 /* In order to be certain of getting the registers we need,
1786 we must sort the reloads into order of increasing register class.
1787 Then our grabbing of reload registers will parallel the process
1788 that provided the reload registers. */
1789 for (i = 0; i < chain->n_reloads; i++)
1791 /* Show whether this reload already has a hard reg. */
1792 if (chain->rld[i].reg_rtx)
1794 int regno = REGNO (chain->rld[i].reg_rtx);
1795 chain->rld[i].regno = regno;
1797 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1800 chain->rld[i].regno = -1;
1801 reload_order[i] = i;
1804 n_reloads = chain->n_reloads;
1805 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1807 CLEAR_HARD_REG_SET (used_spill_regs_local);
1810 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1812 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1814 /* Compute the order of preference for hard registers to spill. */
1816 order_regs_for_reload (chain);
1818 for (i = 0; i < n_reloads; i++)
1820 int r = reload_order[i];
1822 /* Ignore reloads that got marked inoperative. */
1823 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1824 && ! rld[r].optional
1825 && rld[r].regno == -1)
1826 if (! find_reg (chain, i))
1828 spill_failure (chain->insn, rld[r].class);
1834 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1835 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1837 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1841 select_reload_regs ()
1843 struct insn_chain *chain;
1845 /* Try to satisfy the needs for each insn. */
1846 for (chain = insns_need_reload; chain != 0;
1847 chain = chain->next_need_reload)
1848 find_reload_regs (chain);
1851 /* Delete all insns that were inserted by emit_caller_save_insns during
1854 delete_caller_save_insns ()
1856 struct insn_chain *c = reload_insn_chain;
1860 while (c != 0 && c->is_caller_save_insn)
1862 struct insn_chain *next = c->next;
1865 if (c == reload_insn_chain)
1866 reload_insn_chain = next;
1870 next->prev = c->prev;
1872 c->prev->next = next;
1873 c->next = unused_insn_chains;
1874 unused_insn_chains = c;
1882 /* Handle the failure to find a register to spill.
1883 INSN should be one of the insns which needed this particular spill reg. */
1886 spill_failure (insn, class)
1888 enum reg_class class;
1890 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1891 if (asm_noperands (PATTERN (insn)) >= 0)
1892 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1893 reg_class_names[class]);
1896 error ("unable to find a register to spill in class `%s'",
1897 reg_class_names[class]);
1898 fatal_insn ("this is the insn:", insn);
1902 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1903 data that is dead in INSN. */
1906 delete_dead_insn (insn)
1909 rtx prev = prev_real_insn (insn);
1912 /* If the previous insn sets a register that dies in our insn, delete it
1914 if (prev && GET_CODE (PATTERN (prev)) == SET
1915 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1916 && reg_mentioned_p (prev_dest, PATTERN (insn))
1917 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1918 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1919 delete_dead_insn (prev);
1921 PUT_CODE (insn, NOTE);
1922 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1923 NOTE_SOURCE_FILE (insn) = 0;
1926 /* Modify the home of pseudo-reg I.
1927 The new home is present in reg_renumber[I].
1929 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1930 or it may be -1, meaning there is none or it is not relevant.
1931 This is used so that all pseudos spilled from a given hard reg
1932 can share one stack slot. */
1935 alter_reg (i, from_reg)
1939 /* When outputting an inline function, this can happen
1940 for a reg that isn't actually used. */
1941 if (regno_reg_rtx[i] == 0)
1944 /* If the reg got changed to a MEM at rtl-generation time,
1946 if (GET_CODE (regno_reg_rtx[i]) != REG)
1949 /* Modify the reg-rtx to contain the new hard reg
1950 number or else to contain its pseudo reg number. */
1951 REGNO (regno_reg_rtx[i])
1952 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1954 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1955 allocate a stack slot for it. */
1957 if (reg_renumber[i] < 0
1958 && REG_N_REFS (i) > 0
1959 && reg_equiv_constant[i] == 0
1960 && reg_equiv_memory_loc[i] == 0)
1963 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1964 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1967 /* Each pseudo reg has an inherent size which comes from its own mode,
1968 and a total size which provides room for paradoxical subregs
1969 which refer to the pseudo reg in wider modes.
1971 We can use a slot already allocated if it provides both
1972 enough inherent space and enough total space.
1973 Otherwise, we allocate a new slot, making sure that it has no less
1974 inherent space, and no less total space, then the previous slot. */
1977 /* No known place to spill from => no slot to reuse. */
1978 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1979 inherent_size == total_size ? 0 : -1);
1980 if (BYTES_BIG_ENDIAN)
1981 /* Cancel the big-endian correction done in assign_stack_local.
1982 Get the address of the beginning of the slot.
1983 This is so we can do a big-endian correction unconditionally
1985 adjust = inherent_size - total_size;
1987 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1989 /* Nothing can alias this slot except this pseudo. */
1990 set_mem_alias_set (x, new_alias_set ());
1993 /* Reuse a stack slot if possible. */
1994 else if (spill_stack_slot[from_reg] != 0
1995 && spill_stack_slot_width[from_reg] >= total_size
1996 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1998 x = spill_stack_slot[from_reg];
2000 /* Allocate a bigger slot. */
2003 /* Compute maximum size needed, both for inherent size
2004 and for total size. */
2005 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2008 if (spill_stack_slot[from_reg])
2010 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2012 mode = GET_MODE (spill_stack_slot[from_reg]);
2013 if (spill_stack_slot_width[from_reg] > total_size)
2014 total_size = spill_stack_slot_width[from_reg];
2017 /* Make a slot with that size. */
2018 x = assign_stack_local (mode, total_size,
2019 inherent_size == total_size ? 0 : -1);
2022 /* All pseudos mapped to this slot can alias each other. */
2023 if (spill_stack_slot[from_reg])
2024 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2026 set_mem_alias_set (x, new_alias_set ());
2028 if (BYTES_BIG_ENDIAN)
2030 /* Cancel the big-endian correction done in assign_stack_local.
2031 Get the address of the beginning of the slot.
2032 This is so we can do a big-endian correction unconditionally
2034 adjust = GET_MODE_SIZE (mode) - total_size;
2037 = adjust_address_nv (x, mode_for_size (total_size
2043 spill_stack_slot[from_reg] = stack_slot;
2044 spill_stack_slot_width[from_reg] = total_size;
2047 /* On a big endian machine, the "address" of the slot
2048 is the address of the low part that fits its inherent mode. */
2049 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2050 adjust += (total_size - inherent_size);
2052 /* If we have any adjustment to make, or if the stack slot is the
2053 wrong mode, make a new stack slot. */
2054 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2056 /* If we have a decl for the original register, set it for the
2057 memory. If this is a shared MEM, make a copy. */
2060 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2063 set_mem_expr (x, REGNO_DECL (i));
2066 /* Save the stack slot for later. */
2067 reg_equiv_memory_loc[i] = x;
2071 /* Mark the slots in regs_ever_live for the hard regs
2072 used by pseudo-reg number REGNO. */
2075 mark_home_live (regno)
2080 i = reg_renumber[regno];
2083 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2085 regs_ever_live[i++] = 1;
2088 /* This function handles the tracking of elimination offsets around branches.
2090 X is a piece of RTL being scanned.
2092 INSN is the insn that it came from, if any.
2094 INITIAL_P is non-zero if we are to set the offset to be the initial
2095 offset and zero if we are setting the offset of the label to be the
2099 set_label_offsets (x, insn, initial_p)
2104 enum rtx_code code = GET_CODE (x);
2107 struct elim_table *p;
2112 if (LABEL_REF_NONLOCAL_P (x))
2117 /* ... fall through ... */
2120 /* If we know nothing about this label, set the desired offsets. Note
2121 that this sets the offset at a label to be the offset before a label
2122 if we don't know anything about the label. This is not correct for
2123 the label after a BARRIER, but is the best guess we can make. If
2124 we guessed wrong, we will suppress an elimination that might have
2125 been possible had we been able to guess correctly. */
2127 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2129 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2130 offsets_at[CODE_LABEL_NUMBER (x)][i]
2131 = (initial_p ? reg_eliminate[i].initial_offset
2132 : reg_eliminate[i].offset);
2133 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2136 /* Otherwise, if this is the definition of a label and it is
2137 preceded by a BARRIER, set our offsets to the known offset of
2141 && (tem = prev_nonnote_insn (insn)) != 0
2142 && GET_CODE (tem) == BARRIER)
2143 set_offsets_for_label (insn);
2145 /* If neither of the above cases is true, compare each offset
2146 with those previously recorded and suppress any eliminations
2147 where the offsets disagree. */
2149 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2150 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2151 != (initial_p ? reg_eliminate[i].initial_offset
2152 : reg_eliminate[i].offset))
2153 reg_eliminate[i].can_eliminate = 0;
2158 set_label_offsets (PATTERN (insn), insn, initial_p);
2160 /* ... fall through ... */
2164 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2165 and hence must have all eliminations at their initial offsets. */
2166 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2167 if (REG_NOTE_KIND (tem) == REG_LABEL)
2168 set_label_offsets (XEXP (tem, 0), insn, 1);
2174 /* Each of the labels in the parallel or address vector must be
2175 at their initial offsets. We want the first field for PARALLEL
2176 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2178 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2179 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2184 /* We only care about setting PC. If the source is not RETURN,
2185 IF_THEN_ELSE, or a label, disable any eliminations not at
2186 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2187 isn't one of those possibilities. For branches to a label,
2188 call ourselves recursively.
2190 Note that this can disable elimination unnecessarily when we have
2191 a non-local goto since it will look like a non-constant jump to
2192 someplace in the current function. This isn't a significant
2193 problem since such jumps will normally be when all elimination
2194 pairs are back to their initial offsets. */
2196 if (SET_DEST (x) != pc_rtx)
2199 switch (GET_CODE (SET_SRC (x)))
2206 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2210 tem = XEXP (SET_SRC (x), 1);
2211 if (GET_CODE (tem) == LABEL_REF)
2212 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2213 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2216 tem = XEXP (SET_SRC (x), 2);
2217 if (GET_CODE (tem) == LABEL_REF)
2218 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2219 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2227 /* If we reach here, all eliminations must be at their initial
2228 offset because we are doing a jump to a variable address. */
2229 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2230 if (p->offset != p->initial_offset)
2231 p->can_eliminate = 0;
2239 /* Scan X and replace any eliminable registers (such as fp) with a
2240 replacement (such as sp), plus an offset.
2242 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2243 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2244 MEM, we are allowed to replace a sum of a register and the constant zero
2245 with the register, which we cannot do outside a MEM. In addition, we need
2246 to record the fact that a register is referenced outside a MEM.
2248 If INSN is an insn, it is the insn containing X. If we replace a REG
2249 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2250 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2251 the REG is being modified.
2253 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2254 That's used when we eliminate in expressions stored in notes.
2255 This means, do not set ref_outside_mem even if the reference
2258 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2259 replacements done assuming all offsets are at their initial values. If
2260 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2261 encounter, return the actual location so that find_reloads will do
2262 the proper thing. */
2265 eliminate_regs (x, mem_mode, insn)
2267 enum machine_mode mem_mode;
2270 enum rtx_code code = GET_CODE (x);
2271 struct elim_table *ep;
2278 if (! current_function_decl)
2297 /* This is only for the benefit of the debugging backends, which call
2298 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2299 removed after CSE. */
2300 new = eliminate_regs (XEXP (x, 0), 0, insn);
2301 if (GET_CODE (new) == MEM)
2302 return XEXP (new, 0);
2308 /* First handle the case where we encounter a bare register that
2309 is eliminable. Replace it with a PLUS. */
2310 if (regno < FIRST_PSEUDO_REGISTER)
2312 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2314 if (ep->from_rtx == x && ep->can_eliminate)
2315 return plus_constant (ep->to_rtx, ep->previous_offset);
2318 else if (reg_renumber && reg_renumber[regno] < 0
2319 && reg_equiv_constant && reg_equiv_constant[regno]
2320 && ! CONSTANT_P (reg_equiv_constant[regno]))
2321 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2325 /* You might think handling MINUS in a manner similar to PLUS is a
2326 good idea. It is not. It has been tried multiple times and every
2327 time the change has had to have been reverted.
2329 Other parts of reload know a PLUS is special (gen_reload for example)
2330 and require special code to handle code a reloaded PLUS operand.
2332 Also consider backends where the flags register is clobbered by a
2333 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2334 lea instruction comes to mind). If we try to reload a MINUS, we
2335 may kill the flags register that was holding a useful value.
2337 So, please before trying to handle MINUS, consider reload as a
2338 whole instead of this little section as well as the backend issues. */
2340 /* If this is the sum of an eliminable register and a constant, rework
2342 if (GET_CODE (XEXP (x, 0)) == REG
2343 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2344 && CONSTANT_P (XEXP (x, 1)))
2346 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2348 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2350 /* The only time we want to replace a PLUS with a REG (this
2351 occurs when the constant operand of the PLUS is the negative
2352 of the offset) is when we are inside a MEM. We won't want
2353 to do so at other times because that would change the
2354 structure of the insn in a way that reload can't handle.
2355 We special-case the commonest situation in
2356 eliminate_regs_in_insn, so just replace a PLUS with a
2357 PLUS here, unless inside a MEM. */
2358 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2359 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2362 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2363 plus_constant (XEXP (x, 1),
2364 ep->previous_offset));
2367 /* If the register is not eliminable, we are done since the other
2368 operand is a constant. */
2372 /* If this is part of an address, we want to bring any constant to the
2373 outermost PLUS. We will do this by doing register replacement in
2374 our operands and seeing if a constant shows up in one of them.
2376 Note that there is no risk of modifying the structure of the insn,
2377 since we only get called for its operands, thus we are either
2378 modifying the address inside a MEM, or something like an address
2379 operand of a load-address insn. */
2382 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2383 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2385 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2387 /* If one side is a PLUS and the other side is a pseudo that
2388 didn't get a hard register but has a reg_equiv_constant,
2389 we must replace the constant here since it may no longer
2390 be in the position of any operand. */
2391 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2392 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2393 && reg_renumber[REGNO (new1)] < 0
2394 && reg_equiv_constant != 0
2395 && reg_equiv_constant[REGNO (new1)] != 0)
2396 new1 = reg_equiv_constant[REGNO (new1)];
2397 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2398 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2399 && reg_renumber[REGNO (new0)] < 0
2400 && reg_equiv_constant[REGNO (new0)] != 0)
2401 new0 = reg_equiv_constant[REGNO (new0)];
2403 new = form_sum (new0, new1);
2405 /* As above, if we are not inside a MEM we do not want to
2406 turn a PLUS into something else. We might try to do so here
2407 for an addition of 0 if we aren't optimizing. */
2408 if (! mem_mode && GET_CODE (new) != PLUS)
2409 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2417 /* If this is the product of an eliminable register and a
2418 constant, apply the distribute law and move the constant out
2419 so that we have (plus (mult ..) ..). This is needed in order
2420 to keep load-address insns valid. This case is pathological.
2421 We ignore the possibility of overflow here. */
2422 if (GET_CODE (XEXP (x, 0)) == REG
2423 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2424 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2425 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2427 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2430 /* Refs inside notes don't count for this purpose. */
2431 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2432 || GET_CODE (insn) == INSN_LIST)))
2433 ep->ref_outside_mem = 1;
2436 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2437 ep->previous_offset * INTVAL (XEXP (x, 1)));
2440 /* ... fall through ... */
2444 /* See comments before PLUS about handling MINUS. */
2446 case DIV: case UDIV:
2447 case MOD: case UMOD:
2448 case AND: case IOR: case XOR:
2449 case ROTATERT: case ROTATE:
2450 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2452 case GE: case GT: case GEU: case GTU:
2453 case LE: case LT: case LEU: case LTU:
2455 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2457 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2459 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2460 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2465 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2468 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2469 if (new != XEXP (x, 0))
2471 /* If this is a REG_DEAD note, it is not valid anymore.
2472 Using the eliminated version could result in creating a
2473 REG_DEAD note for the stack or frame pointer. */
2474 if (GET_MODE (x) == REG_DEAD)
2476 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2479 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2483 /* ... fall through ... */
2486 /* Now do eliminations in the rest of the chain. If this was
2487 an EXPR_LIST, this might result in allocating more memory than is
2488 strictly needed, but it simplifies the code. */
2491 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2492 if (new != XEXP (x, 1))
2494 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2502 case STRICT_LOW_PART:
2504 case SIGN_EXTEND: case ZERO_EXTEND:
2505 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2506 case FLOAT: case FIX:
2507 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2511 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2512 if (new != XEXP (x, 0))
2513 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2517 /* Similar to above processing, but preserve SUBREG_BYTE.
2518 Convert (subreg (mem)) to (mem) if not paradoxical.
2519 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2520 pseudo didn't get a hard reg, we must replace this with the
2521 eliminated version of the memory location because push_reloads
2522 may do the replacement in certain circumstances. */
2523 if (GET_CODE (SUBREG_REG (x)) == REG
2524 && (GET_MODE_SIZE (GET_MODE (x))
2525 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2526 && reg_equiv_memory_loc != 0
2527 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2529 new = SUBREG_REG (x);
2532 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2534 if (new != SUBREG_REG (x))
2536 int x_size = GET_MODE_SIZE (GET_MODE (x));
2537 int new_size = GET_MODE_SIZE (GET_MODE (new));
2539 if (GET_CODE (new) == MEM
2540 && ((x_size < new_size
2541 #ifdef WORD_REGISTER_OPERATIONS
2542 /* On these machines, combine can create rtl of the form
2543 (set (subreg:m1 (reg:m2 R) 0) ...)
2544 where m1 < m2, and expects something interesting to
2545 happen to the entire word. Moreover, it will use the
2546 (reg:m2 R) later, expecting all bits to be preserved.
2547 So if the number of words is the same, preserve the
2548 subreg so that push_reloads can see it. */
2549 && ! ((x_size - 1) / UNITS_PER_WORD
2550 == (new_size -1 ) / UNITS_PER_WORD)
2553 || x_size == new_size)
2555 return adjust_address_nv (x, GET_MODE (x), SUBREG_BYTE (x));
2557 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2563 /* This is only for the benefit of the debugging backends, which call
2564 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2565 removed after CSE. */
2566 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2567 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2569 /* Our only special processing is to pass the mode of the MEM to our
2570 recursive call and copy the flags. While we are here, handle this
2571 case more efficiently. */
2573 replace_equiv_address_nv (x,
2574 eliminate_regs (XEXP (x, 0),
2575 GET_MODE (x), insn));
2578 /* Handle insn_list USE that a call to a pure function may generate. */
2579 new = eliminate_regs (XEXP (x, 0), 0, insn);
2580 if (new != XEXP (x, 0))
2581 return gen_rtx_USE (GET_MODE (x), new);
2593 /* Process each of our operands recursively. If any have changed, make a
2595 fmt = GET_RTX_FORMAT (code);
2596 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2600 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2601 if (new != XEXP (x, i) && ! copied)
2603 rtx new_x = rtx_alloc (code);
2605 (sizeof (*new_x) - sizeof (new_x->fld)
2606 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2612 else if (*fmt == 'E')
2615 for (j = 0; j < XVECLEN (x, i); j++)
2617 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2618 if (new != XVECEXP (x, i, j) && ! copied_vec)
2620 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2624 rtx new_x = rtx_alloc (code);
2626 (sizeof (*new_x) - sizeof (new_x->fld)
2627 + (sizeof (new_x->fld[0])
2628 * GET_RTX_LENGTH (code))));
2632 XVEC (x, i) = new_v;
2635 XVECEXP (x, i, j) = new;
2643 /* Scan rtx X for modifications of elimination target registers. Update
2644 the table of eliminables to reflect the changed state. MEM_MODE is
2645 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2648 elimination_effects (x, mem_mode)
2650 enum machine_mode mem_mode;
2653 enum rtx_code code = GET_CODE (x);
2654 struct elim_table *ep;
2680 /* First handle the case where we encounter a bare register that
2681 is eliminable. Replace it with a PLUS. */
2682 if (regno < FIRST_PSEUDO_REGISTER)
2684 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2686 if (ep->from_rtx == x && ep->can_eliminate)
2689 ep->ref_outside_mem = 1;
2694 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2695 && reg_equiv_constant[regno]
2696 && ! function_invariant_p (reg_equiv_constant[regno]))
2697 elimination_effects (reg_equiv_constant[regno], mem_mode);
2706 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2707 if (ep->to_rtx == XEXP (x, 0))
2709 int size = GET_MODE_SIZE (mem_mode);
2711 /* If more bytes than MEM_MODE are pushed, account for them. */
2712 #ifdef PUSH_ROUNDING
2713 if (ep->to_rtx == stack_pointer_rtx)
2714 size = PUSH_ROUNDING (size);
2716 if (code == PRE_DEC || code == POST_DEC)
2718 else if (code == PRE_INC || code == POST_INC)
2720 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2721 && GET_CODE (XEXP (x, 1)) == PLUS
2722 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2723 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2724 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2727 /* These two aren't unary operators. */
2728 if (code == POST_MODIFY || code == PRE_MODIFY)
2731 /* Fall through to generic unary operation case. */
2732 case STRICT_LOW_PART:
2734 case SIGN_EXTEND: case ZERO_EXTEND:
2735 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2736 case FLOAT: case FIX:
2737 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2741 elimination_effects (XEXP (x, 0), mem_mode);
2745 if (GET_CODE (SUBREG_REG (x)) == REG
2746 && (GET_MODE_SIZE (GET_MODE (x))
2747 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2748 && reg_equiv_memory_loc != 0
2749 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2752 elimination_effects (SUBREG_REG (x), mem_mode);
2756 /* If using a register that is the source of an eliminate we still
2757 think can be performed, note it cannot be performed since we don't
2758 know how this register is used. */
2759 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2760 if (ep->from_rtx == XEXP (x, 0))
2761 ep->can_eliminate = 0;
2763 elimination_effects (XEXP (x, 0), mem_mode);
2767 /* If clobbering a register that is the replacement register for an
2768 elimination we still think can be performed, note that it cannot
2769 be performed. Otherwise, we need not be concerned about it. */
2770 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2771 if (ep->to_rtx == XEXP (x, 0))
2772 ep->can_eliminate = 0;
2774 elimination_effects (XEXP (x, 0), mem_mode);
2778 /* Check for setting a register that we know about. */
2779 if (GET_CODE (SET_DEST (x)) == REG)
2781 /* See if this is setting the replacement register for an
2784 If DEST is the hard frame pointer, we do nothing because we
2785 assume that all assignments to the frame pointer are for
2786 non-local gotos and are being done at a time when they are valid
2787 and do not disturb anything else. Some machines want to
2788 eliminate a fake argument pointer (or even a fake frame pointer)
2789 with either the real frame or the stack pointer. Assignments to
2790 the hard frame pointer must not prevent this elimination. */
2792 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2794 if (ep->to_rtx == SET_DEST (x)
2795 && SET_DEST (x) != hard_frame_pointer_rtx)
2797 /* If it is being incremented, adjust the offset. Otherwise,
2798 this elimination can't be done. */
2799 rtx src = SET_SRC (x);
2801 if (GET_CODE (src) == PLUS
2802 && XEXP (src, 0) == SET_DEST (x)
2803 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2804 ep->offset -= INTVAL (XEXP (src, 1));
2806 ep->can_eliminate = 0;
2810 elimination_effects (SET_DEST (x), 0);
2811 elimination_effects (SET_SRC (x), 0);
2815 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2818 /* Our only special processing is to pass the mode of the MEM to our
2820 elimination_effects (XEXP (x, 0), GET_MODE (x));
2827 fmt = GET_RTX_FORMAT (code);
2828 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2831 elimination_effects (XEXP (x, i), mem_mode);
2832 else if (*fmt == 'E')
2833 for (j = 0; j < XVECLEN (x, i); j++)
2834 elimination_effects (XVECEXP (x, i, j), mem_mode);
2838 /* Descend through rtx X and verify that no references to eliminable registers
2839 remain. If any do remain, mark the involved register as not
2843 check_eliminable_occurrences (x)
2853 code = GET_CODE (x);
2855 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2857 struct elim_table *ep;
2859 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2860 if (ep->from_rtx == x && ep->can_eliminate)
2861 ep->can_eliminate = 0;
2865 fmt = GET_RTX_FORMAT (code);
2866 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2869 check_eliminable_occurrences (XEXP (x, i));
2870 else if (*fmt == 'E')
2873 for (j = 0; j < XVECLEN (x, i); j++)
2874 check_eliminable_occurrences (XVECEXP (x, i, j));
2879 /* Scan INSN and eliminate all eliminable registers in it.
2881 If REPLACE is nonzero, do the replacement destructively. Also
2882 delete the insn as dead it if it is setting an eliminable register.
2884 If REPLACE is zero, do all our allocations in reload_obstack.
2886 If no eliminations were done and this insn doesn't require any elimination
2887 processing (these are not identical conditions: it might be updating sp,
2888 but not referencing fp; this needs to be seen during reload_as_needed so
2889 that the offset between fp and sp can be taken into consideration), zero
2890 is returned. Otherwise, 1 is returned. */
2893 eliminate_regs_in_insn (insn, replace)
2897 int icode = recog_memoized (insn);
2898 rtx old_body = PATTERN (insn);
2899 int insn_is_asm = asm_noperands (old_body) >= 0;
2900 rtx old_set = single_set (insn);
2904 rtx substed_operand[MAX_RECOG_OPERANDS];
2905 rtx orig_operand[MAX_RECOG_OPERANDS];
2906 struct elim_table *ep;
2908 if (! insn_is_asm && icode < 0)
2910 if (GET_CODE (PATTERN (insn)) == USE
2911 || GET_CODE (PATTERN (insn)) == CLOBBER
2912 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2913 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2914 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2919 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2920 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2922 /* Check for setting an eliminable register. */
2923 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2924 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2926 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2927 /* If this is setting the frame pointer register to the
2928 hardware frame pointer register and this is an elimination
2929 that will be done (tested above), this insn is really
2930 adjusting the frame pointer downward to compensate for
2931 the adjustment done before a nonlocal goto. */
2932 if (ep->from == FRAME_POINTER_REGNUM
2933 && ep->to == HARD_FRAME_POINTER_REGNUM)
2935 rtx src = SET_SRC (old_set);
2936 int offset = 0, ok = 0;
2937 rtx prev_insn, prev_set;
2939 if (src == ep->to_rtx)
2941 else if (GET_CODE (src) == PLUS
2942 && GET_CODE (XEXP (src, 0)) == CONST_INT
2943 && XEXP (src, 1) == ep->to_rtx)
2944 offset = INTVAL (XEXP (src, 0)), ok = 1;
2945 else if (GET_CODE (src) == PLUS
2946 && GET_CODE (XEXP (src, 1)) == CONST_INT
2947 && XEXP (src, 0) == ep->to_rtx)
2948 offset = INTVAL (XEXP (src, 1)), ok = 1;
2949 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2950 && (prev_set = single_set (prev_insn)) != 0
2951 && rtx_equal_p (SET_DEST (prev_set), src))
2953 src = SET_SRC (prev_set);
2954 if (src == ep->to_rtx)
2956 else if (GET_CODE (src) == PLUS
2957 && GET_CODE (XEXP (src, 0)) == CONST_INT
2958 && XEXP (src, 1) == ep->to_rtx)
2959 offset = INTVAL (XEXP (src, 0)), ok = 1;
2960 else if (GET_CODE (src) == PLUS
2961 && GET_CODE (XEXP (src, 1)) == CONST_INT
2962 && XEXP (src, 0) == ep->to_rtx)
2963 offset = INTVAL (XEXP (src, 1)), ok = 1;
2969 = plus_constant (ep->to_rtx, offset - ep->offset);
2971 new_body = old_body;
2974 new_body = copy_insn (old_body);
2975 if (REG_NOTES (insn))
2976 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2978 PATTERN (insn) = new_body;
2979 old_set = single_set (insn);
2981 /* First see if this insn remains valid when we
2982 make the change. If not, keep the INSN_CODE
2983 the same and let reload fit it up. */
2984 validate_change (insn, &SET_SRC (old_set), src, 1);
2985 validate_change (insn, &SET_DEST (old_set),
2987 if (! apply_change_group ())
2989 SET_SRC (old_set) = src;
2990 SET_DEST (old_set) = ep->to_rtx;
2999 /* In this case this insn isn't serving a useful purpose. We
3000 will delete it in reload_as_needed once we know that this
3001 elimination is, in fact, being done.
3003 If REPLACE isn't set, we can't delete this insn, but needn't
3004 process it since it won't be used unless something changes. */
3007 delete_dead_insn (insn);
3015 /* We allow one special case which happens to work on all machines we
3016 currently support: a single set with the source being a PLUS of an
3017 eliminable register and a constant. */
3019 && GET_CODE (SET_DEST (old_set)) == REG
3020 && GET_CODE (SET_SRC (old_set)) == PLUS
3021 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3022 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3023 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3025 rtx reg = XEXP (SET_SRC (old_set), 0);
3026 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3028 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3029 if (ep->from_rtx == reg && ep->can_eliminate)
3031 offset += ep->offset;
3036 /* We assume here that if we need a PARALLEL with
3037 CLOBBERs for this assignment, we can do with the
3038 MATCH_SCRATCHes that add_clobbers allocates.
3039 There's not much we can do if that doesn't work. */
3040 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3044 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3047 rtvec vec = rtvec_alloc (num_clobbers + 1);
3049 vec->elem[0] = PATTERN (insn);
3050 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3051 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3053 if (INSN_CODE (insn) < 0)
3058 new_body = old_body;
3061 new_body = copy_insn (old_body);
3062 if (REG_NOTES (insn))
3063 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3065 PATTERN (insn) = new_body;
3066 old_set = single_set (insn);
3068 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3069 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3072 /* This can't have an effect on elimination offsets, so skip right
3078 /* Determine the effects of this insn on elimination offsets. */
3079 elimination_effects (old_body, 0);
3081 /* Eliminate all eliminable registers occurring in operands that
3082 can be handled by reload. */
3083 extract_insn (insn);
3085 for (i = 0; i < recog_data.n_operands; i++)
3087 orig_operand[i] = recog_data.operand[i];
3088 substed_operand[i] = recog_data.operand[i];
3090 /* For an asm statement, every operand is eliminable. */
3091 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3093 /* Check for setting a register that we know about. */
3094 if (recog_data.operand_type[i] != OP_IN
3095 && GET_CODE (orig_operand[i]) == REG)
3097 /* If we are assigning to a register that can be eliminated, it
3098 must be as part of a PARALLEL, since the code above handles
3099 single SETs. We must indicate that we can no longer
3100 eliminate this reg. */
3101 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3103 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3104 ep->can_eliminate = 0;
3107 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3108 replace ? insn : NULL_RTX);
3109 if (substed_operand[i] != orig_operand[i])
3110 val = any_changes = 1;
3111 /* Terminate the search in check_eliminable_occurrences at
3113 *recog_data.operand_loc[i] = 0;
3115 /* If an output operand changed from a REG to a MEM and INSN is an
3116 insn, write a CLOBBER insn. */
3117 if (recog_data.operand_type[i] != OP_IN
3118 && GET_CODE (orig_operand[i]) == REG
3119 && GET_CODE (substed_operand[i]) == MEM
3121 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3126 for (i = 0; i < recog_data.n_dups; i++)
3127 *recog_data.dup_loc[i]
3128 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3130 /* If any eliminable remain, they aren't eliminable anymore. */
3131 check_eliminable_occurrences (old_body);
3133 /* Substitute the operands; the new values are in the substed_operand
3135 for (i = 0; i < recog_data.n_operands; i++)
3136 *recog_data.operand_loc[i] = substed_operand[i];
3137 for (i = 0; i < recog_data.n_dups; i++)
3138 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3140 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3141 re-recognize the insn. We do this in case we had a simple addition
3142 but now can do this as a load-address. This saves an insn in this
3144 If re-recognition fails, the old insn code number will still be used,
3145 and some register operands may have changed into PLUS expressions.
3146 These will be handled by find_reloads by loading them into a register
3151 /* If we aren't replacing things permanently and we changed something,
3152 make another copy to ensure that all the RTL is new. Otherwise
3153 things can go wrong if find_reload swaps commutative operands
3154 and one is inside RTL that has been copied while the other is not. */
3155 new_body = old_body;
3158 new_body = copy_insn (old_body);
3159 if (REG_NOTES (insn))
3160 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3162 PATTERN (insn) = new_body;
3164 /* If we had a move insn but now we don't, rerecognize it. This will
3165 cause spurious re-recognition if the old move had a PARALLEL since
3166 the new one still will, but we can't call single_set without
3167 having put NEW_BODY into the insn and the re-recognition won't
3168 hurt in this rare case. */
3169 /* ??? Why this huge if statement - why don't we just rerecognize the
3173 && ((GET_CODE (SET_SRC (old_set)) == REG
3174 && (GET_CODE (new_body) != SET
3175 || GET_CODE (SET_SRC (new_body)) != REG))
3176 /* If this was a load from or store to memory, compare
3177 the MEM in recog_data.operand to the one in the insn.
3178 If they are not equal, then rerecognize the insn. */
3180 && ((GET_CODE (SET_SRC (old_set)) == MEM
3181 && SET_SRC (old_set) != recog_data.operand[1])
3182 || (GET_CODE (SET_DEST (old_set)) == MEM
3183 && SET_DEST (old_set) != recog_data.operand[0])))
3184 /* If this was an add insn before, rerecognize. */
3185 || GET_CODE (SET_SRC (old_set)) == PLUS))
3187 int new_icode = recog (PATTERN (insn), insn, 0);
3189 INSN_CODE (insn) = icode;
3193 /* Restore the old body. If there were any changes to it, we made a copy
3194 of it while the changes were still in place, so we'll correctly return
3195 a modified insn below. */
3198 /* Restore the old body. */
3199 for (i = 0; i < recog_data.n_operands; i++)
3200 *recog_data.operand_loc[i] = orig_operand[i];
3201 for (i = 0; i < recog_data.n_dups; i++)
3202 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3205 /* Update all elimination pairs to reflect the status after the current
3206 insn. The changes we make were determined by the earlier call to
3207 elimination_effects.
3209 We also detect a cases where register elimination cannot be done,
3210 namely, if a register would be both changed and referenced outside a MEM
3211 in the resulting insn since such an insn is often undefined and, even if
3212 not, we cannot know what meaning will be given to it. Note that it is
3213 valid to have a register used in an address in an insn that changes it
3214 (presumably with a pre- or post-increment or decrement).
3216 If anything changes, return nonzero. */
3218 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3220 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3221 ep->can_eliminate = 0;
3223 ep->ref_outside_mem = 0;
3225 if (ep->previous_offset != ep->offset)
3230 /* If we changed something, perform elimination in REG_NOTES. This is
3231 needed even when REPLACE is zero because a REG_DEAD note might refer
3232 to a register that we eliminate and could cause a different number
3233 of spill registers to be needed in the final reload pass than in
3235 if (val && REG_NOTES (insn) != 0)
3236 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3241 /* Loop through all elimination pairs.
3242 Recalculate the number not at initial offset.
3244 Compute the maximum offset (minimum offset if the stack does not
3245 grow downward) for each elimination pair. */
3248 update_eliminable_offsets ()
3250 struct elim_table *ep;
3252 num_not_at_initial_offset = 0;
3253 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3255 ep->previous_offset = ep->offset;
3256 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3257 num_not_at_initial_offset++;
3261 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3262 replacement we currently believe is valid, mark it as not eliminable if X
3263 modifies DEST in any way other than by adding a constant integer to it.
3265 If DEST is the frame pointer, we do nothing because we assume that
3266 all assignments to the hard frame pointer are nonlocal gotos and are being
3267 done at a time when they are valid and do not disturb anything else.
3268 Some machines want to eliminate a fake argument pointer with either the
3269 frame or stack pointer. Assignments to the hard frame pointer must not
3270 prevent this elimination.
3272 Called via note_stores from reload before starting its passes to scan
3273 the insns of the function. */
3276 mark_not_eliminable (dest, x, data)
3279 void *data ATTRIBUTE_UNUSED;
3283 /* A SUBREG of a hard register here is just changing its mode. We should
3284 not see a SUBREG of an eliminable hard register, but check just in
3286 if (GET_CODE (dest) == SUBREG)
3287 dest = SUBREG_REG (dest);
3289 if (dest == hard_frame_pointer_rtx)
3292 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3293 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3294 && (GET_CODE (x) != SET
3295 || GET_CODE (SET_SRC (x)) != PLUS
3296 || XEXP (SET_SRC (x), 0) != dest
3297 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3299 reg_eliminate[i].can_eliminate_previous
3300 = reg_eliminate[i].can_eliminate = 0;
3305 /* Verify that the initial elimination offsets did not change since the
3306 last call to set_initial_elim_offsets. This is used to catch cases
3307 where something illegal happened during reload_as_needed that could
3308 cause incorrect code to be generated if we did not check for it. */
3311 verify_initial_elim_offsets ()
3315 #ifdef ELIMINABLE_REGS
3316 struct elim_table *ep;
3318 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3320 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3321 if (t != ep->initial_offset)
3325 INITIAL_FRAME_POINTER_OFFSET (t);
3326 if (t != reg_eliminate[0].initial_offset)
3331 /* Reset all offsets on eliminable registers to their initial values. */
3334 set_initial_elim_offsets ()
3336 struct elim_table *ep = reg_eliminate;
3338 #ifdef ELIMINABLE_REGS
3339 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3341 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3342 ep->previous_offset = ep->offset = ep->initial_offset;
3345 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3346 ep->previous_offset = ep->offset = ep->initial_offset;
3349 num_not_at_initial_offset = 0;
3352 /* Initialize the known label offsets.
3353 Set a known offset for each forced label to be at the initial offset
3354 of each elimination. We do this because we assume that all
3355 computed jumps occur from a location where each elimination is
3356 at its initial offset.
3357 For all other labels, show that we don't know the offsets. */
3360 set_initial_label_offsets ()
3363 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3365 for (x = forced_labels; x; x = XEXP (x, 1))
3367 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3370 /* Set all elimination offsets to the known values for the code label given
3374 set_offsets_for_label (insn)
3378 int label_nr = CODE_LABEL_NUMBER (insn);
3379 struct elim_table *ep;
3381 num_not_at_initial_offset = 0;
3382 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3384 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3385 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3386 num_not_at_initial_offset++;
3390 /* See if anything that happened changes which eliminations are valid.
3391 For example, on the Sparc, whether or not the frame pointer can
3392 be eliminated can depend on what registers have been used. We need
3393 not check some conditions again (such as flag_omit_frame_pointer)
3394 since they can't have changed. */
3397 update_eliminables (pset)
3400 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3401 int previous_frame_pointer_needed = frame_pointer_needed;
3403 struct elim_table *ep;
3405 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3406 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3407 #ifdef ELIMINABLE_REGS
3408 || ! CAN_ELIMINATE (ep->from, ep->to)
3411 ep->can_eliminate = 0;
3413 /* Look for the case where we have discovered that we can't replace
3414 register A with register B and that means that we will now be
3415 trying to replace register A with register C. This means we can
3416 no longer replace register C with register B and we need to disable
3417 such an elimination, if it exists. This occurs often with A == ap,
3418 B == sp, and C == fp. */
3420 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3422 struct elim_table *op;
3425 if (! ep->can_eliminate && ep->can_eliminate_previous)
3427 /* Find the current elimination for ep->from, if there is a
3429 for (op = reg_eliminate;
3430 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3431 if (op->from == ep->from && op->can_eliminate)
3437 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3439 for (op = reg_eliminate;
3440 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3441 if (op->from == new_to && op->to == ep->to)
3442 op->can_eliminate = 0;
3446 /* See if any registers that we thought we could eliminate the previous
3447 time are no longer eliminable. If so, something has changed and we
3448 must spill the register. Also, recompute the number of eliminable
3449 registers and see if the frame pointer is needed; it is if there is
3450 no elimination of the frame pointer that we can perform. */
3452 frame_pointer_needed = 1;
3453 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3455 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3456 && ep->to != HARD_FRAME_POINTER_REGNUM)
3457 frame_pointer_needed = 0;
3459 if (! ep->can_eliminate && ep->can_eliminate_previous)
3461 ep->can_eliminate_previous = 0;
3462 SET_HARD_REG_BIT (*pset, ep->from);
3467 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3468 /* If we didn't need a frame pointer last time, but we do now, spill
3469 the hard frame pointer. */
3470 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3471 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3475 /* Initialize the table of registers to eliminate. */
3480 struct elim_table *ep;
3481 #ifdef ELIMINABLE_REGS
3482 const struct elim_table_1 *ep1;
3486 reg_eliminate = (struct elim_table *)
3487 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3489 /* Does this function require a frame pointer? */
3491 frame_pointer_needed = (! flag_omit_frame_pointer
3492 #ifdef EXIT_IGNORE_STACK
3493 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3494 and restore sp for alloca. So we can't eliminate
3495 the frame pointer in that case. At some point,
3496 we should improve this by emitting the
3497 sp-adjusting insns for this case. */
3498 || (current_function_calls_alloca
3499 && EXIT_IGNORE_STACK)
3501 || FRAME_POINTER_REQUIRED);
3505 #ifdef ELIMINABLE_REGS
3506 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3507 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3509 ep->from = ep1->from;
3511 ep->can_eliminate = ep->can_eliminate_previous
3512 = (CAN_ELIMINATE (ep->from, ep->to)
3513 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3516 reg_eliminate[0].from = reg_eliminate_1[0].from;
3517 reg_eliminate[0].to = reg_eliminate_1[0].to;
3518 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3519 = ! frame_pointer_needed;
3522 /* Count the number of eliminable registers and build the FROM and TO
3523 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3524 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3525 We depend on this. */
3526 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3528 num_eliminable += ep->can_eliminate;
3529 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3530 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3534 /* Kick all pseudos out of hard register REGNO.
3536 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3537 because we found we can't eliminate some register. In the case, no pseudos
3538 are allowed to be in the register, even if they are only in a block that
3539 doesn't require spill registers, unlike the case when we are spilling this
3540 hard reg to produce another spill register.
3542 Return nonzero if any pseudos needed to be kicked out. */
3545 spill_hard_reg (regno, cant_eliminate)
3553 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3554 regs_ever_live[regno] = 1;
3557 /* Spill every pseudo reg that was allocated to this reg
3558 or to something that overlaps this reg. */
3560 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3561 if (reg_renumber[i] >= 0
3562 && (unsigned int) reg_renumber[i] <= regno
3563 && ((unsigned int) reg_renumber[i]
3564 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3565 PSEUDO_REGNO_MODE (i))
3567 SET_REGNO_REG_SET (&spilled_pseudos, i);
3570 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3571 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3574 ior_hard_reg_set (set1, set2)
3575 HARD_REG_SET *set1, *set2;
3577 IOR_HARD_REG_SET (*set1, *set2);
3580 /* After find_reload_regs has been run for all insn that need reloads,
3581 and/or spill_hard_regs was called, this function is used to actually
3582 spill pseudo registers and try to reallocate them. It also sets up the
3583 spill_regs array for use by choose_reload_regs. */
3586 finish_spills (global)
3589 struct insn_chain *chain;
3590 int something_changed = 0;
3593 /* Build the spill_regs array for the function. */
3594 /* If there are some registers still to eliminate and one of the spill regs
3595 wasn't ever used before, additional stack space may have to be
3596 allocated to store this register. Thus, we may have changed the offset
3597 between the stack and frame pointers, so mark that something has changed.
3599 One might think that we need only set VAL to 1 if this is a call-used
3600 register. However, the set of registers that must be saved by the
3601 prologue is not identical to the call-used set. For example, the
3602 register used by the call insn for the return PC is a call-used register,
3603 but must be saved by the prologue. */
3606 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3607 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3609 spill_reg_order[i] = n_spills;
3610 spill_regs[n_spills++] = i;
3611 if (num_eliminable && ! regs_ever_live[i])
3612 something_changed = 1;
3613 regs_ever_live[i] = 1;
3616 spill_reg_order[i] = -1;
3618 EXECUTE_IF_SET_IN_REG_SET
3619 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3621 /* Record the current hard register the pseudo is allocated to in
3622 pseudo_previous_regs so we avoid reallocating it to the same
3623 hard reg in a later pass. */
3624 if (reg_renumber[i] < 0)
3627 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3628 /* Mark it as no longer having a hard register home. */
3629 reg_renumber[i] = -1;
3630 /* We will need to scan everything again. */
3631 something_changed = 1;
3634 /* Retry global register allocation if possible. */
3637 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3638 /* For every insn that needs reloads, set the registers used as spill
3639 regs in pseudo_forbidden_regs for every pseudo live across the
3641 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3643 EXECUTE_IF_SET_IN_REG_SET
3644 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3646 ior_hard_reg_set (pseudo_forbidden_regs + i,
3647 &chain->used_spill_regs);
3649 EXECUTE_IF_SET_IN_REG_SET
3650 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3652 ior_hard_reg_set (pseudo_forbidden_regs + i,
3653 &chain->used_spill_regs);
3657 /* Retry allocating the spilled pseudos. For each reg, merge the
3658 various reg sets that indicate which hard regs can't be used,
3659 and call retry_global_alloc.
3660 We change spill_pseudos here to only contain pseudos that did not
3661 get a new hard register. */
3662 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3663 if (reg_old_renumber[i] != reg_renumber[i])
3665 HARD_REG_SET forbidden;
3666 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3667 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3668 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3669 retry_global_alloc (i, forbidden);
3670 if (reg_renumber[i] >= 0)
3671 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3675 /* Fix up the register information in the insn chain.
3676 This involves deleting those of the spilled pseudos which did not get
3677 a new hard register home from the live_{before,after} sets. */
3678 for (chain = reload_insn_chain; chain; chain = chain->next)
3680 HARD_REG_SET used_by_pseudos;
3681 HARD_REG_SET used_by_pseudos2;
3683 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3684 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3686 /* Mark any unallocated hard regs as available for spills. That
3687 makes inheritance work somewhat better. */
3688 if (chain->need_reload)
3690 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3691 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3692 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3694 /* Save the old value for the sanity test below. */
3695 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3697 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3698 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3699 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3700 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3702 /* Make sure we only enlarge the set. */
3703 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3709 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3710 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3712 int regno = reg_renumber[i];
3713 if (reg_old_renumber[i] == regno)
3716 alter_reg (i, reg_old_renumber[i]);
3717 reg_old_renumber[i] = regno;
3721 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3723 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3724 i, reg_renumber[i]);
3728 return something_changed;
3731 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3732 Also mark any hard registers used to store user variables as
3733 forbidden from being used for spill registers. */
3736 scan_paradoxical_subregs (x)
3741 enum rtx_code code = GET_CODE (x);
3747 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3748 && REG_USERVAR_P (x))
3749 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3765 if (GET_CODE (SUBREG_REG (x)) == REG
3766 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3767 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3768 = GET_MODE_SIZE (GET_MODE (x));
3775 fmt = GET_RTX_FORMAT (code);
3776 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3779 scan_paradoxical_subregs (XEXP (x, i));
3780 else if (fmt[i] == 'E')
3783 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3784 scan_paradoxical_subregs (XVECEXP (x, i, j));
3789 /* Reload pseudo-registers into hard regs around each insn as needed.
3790 Additional register load insns are output before the insn that needs it
3791 and perhaps store insns after insns that modify the reloaded pseudo reg.
3793 reg_last_reload_reg and reg_reloaded_contents keep track of
3794 which registers are already available in reload registers.
3795 We update these for the reloads that we perform,
3796 as the insns are scanned. */
3799 reload_as_needed (live_known)
3802 struct insn_chain *chain;
3803 #if defined (AUTO_INC_DEC)
3808 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3809 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3810 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3811 reg_has_output_reload = (char *) xmalloc (max_regno);
3812 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3814 set_initial_elim_offsets ();
3816 for (chain = reload_insn_chain; chain; chain = chain->next)
3819 rtx insn = chain->insn;
3820 rtx old_next = NEXT_INSN (insn);
3822 /* If we pass a label, copy the offsets from the label information
3823 into the current offsets of each elimination. */
3824 if (GET_CODE (insn) == CODE_LABEL)
3825 set_offsets_for_label (insn);
3827 else if (INSN_P (insn))
3829 rtx oldpat = PATTERN (insn);
3831 /* If this is a USE and CLOBBER of a MEM, ensure that any
3832 references to eliminable registers have been removed. */
3834 if ((GET_CODE (PATTERN (insn)) == USE
3835 || GET_CODE (PATTERN (insn)) == CLOBBER)
3836 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3837 XEXP (XEXP (PATTERN (insn), 0), 0)
3838 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3839 GET_MODE (XEXP (PATTERN (insn), 0)),
3842 /* If we need to do register elimination processing, do so.
3843 This might delete the insn, in which case we are done. */
3844 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3846 eliminate_regs_in_insn (insn, 1);
3847 if (GET_CODE (insn) == NOTE)
3849 update_eliminable_offsets ();
3854 /* If need_elim is nonzero but need_reload is zero, one might think
3855 that we could simply set n_reloads to 0. However, find_reloads
3856 could have done some manipulation of the insn (such as swapping
3857 commutative operands), and these manipulations are lost during
3858 the first pass for every insn that needs register elimination.
3859 So the actions of find_reloads must be redone here. */
3861 if (! chain->need_elim && ! chain->need_reload
3862 && ! chain->need_operand_change)
3864 /* First find the pseudo regs that must be reloaded for this insn.
3865 This info is returned in the tables reload_... (see reload.h).
3866 Also modify the body of INSN by substituting RELOAD
3867 rtx's for those pseudo regs. */
3870 memset (reg_has_output_reload, 0, max_regno);
3871 CLEAR_HARD_REG_SET (reg_is_output_reload);
3873 find_reloads (insn, 1, spill_indirect_levels, live_known,
3879 rtx next = NEXT_INSN (insn);
3882 prev = PREV_INSN (insn);
3884 /* Now compute which reload regs to reload them into. Perhaps
3885 reusing reload regs from previous insns, or else output
3886 load insns to reload them. Maybe output store insns too.
3887 Record the choices of reload reg in reload_reg_rtx. */
3888 choose_reload_regs (chain);
3890 /* Merge any reloads that we didn't combine for fear of
3891 increasing the number of spill registers needed but now
3892 discover can be safely merged. */
3893 if (SMALL_REGISTER_CLASSES)
3894 merge_assigned_reloads (insn);
3896 /* Generate the insns to reload operands into or out of
3897 their reload regs. */
3898 emit_reload_insns (chain);
3900 /* Substitute the chosen reload regs from reload_reg_rtx
3901 into the insn's body (or perhaps into the bodies of other
3902 load and store insn that we just made for reloading
3903 and that we moved the structure into). */
3904 subst_reloads (insn);
3906 /* If this was an ASM, make sure that all the reload insns
3907 we have generated are valid. If not, give an error
3910 if (asm_noperands (PATTERN (insn)) >= 0)
3911 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3912 if (p != insn && INSN_P (p)
3913 && (recog_memoized (p) < 0
3914 || (extract_insn (p), ! constrain_operands (1))))
3916 error_for_asm (insn,
3917 "`asm' operand requires impossible reload");
3922 if (num_eliminable && chain->need_elim)
3923 update_eliminable_offsets ();
3925 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3926 is no longer validly lying around to save a future reload.
3927 Note that this does not detect pseudos that were reloaded
3928 for this insn in order to be stored in
3929 (obeying register constraints). That is correct; such reload
3930 registers ARE still valid. */
3931 note_stores (oldpat, forget_old_reloads_1, NULL);
3933 /* There may have been CLOBBER insns placed after INSN. So scan
3934 between INSN and NEXT and use them to forget old reloads. */
3935 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3936 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3937 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3940 /* Likewise for regs altered by auto-increment in this insn.
3941 REG_INC notes have been changed by reloading:
3942 find_reloads_address_1 records substitutions for them,
3943 which have been performed by subst_reloads above. */
3944 for (i = n_reloads - 1; i >= 0; i--)
3946 rtx in_reg = rld[i].in_reg;
3949 enum rtx_code code = GET_CODE (in_reg);
3950 /* PRE_INC / PRE_DEC will have the reload register ending up
3951 with the same value as the stack slot, but that doesn't
3952 hold true for POST_INC / POST_DEC. Either we have to
3953 convert the memory access to a true POST_INC / POST_DEC,
3954 or we can't use the reload register for inheritance. */
3955 if ((code == POST_INC || code == POST_DEC)
3956 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3957 REGNO (rld[i].reg_rtx))
3958 /* Make sure it is the inc/dec pseudo, and not
3959 some other (e.g. output operand) pseudo. */
3960 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3961 == REGNO (XEXP (in_reg, 0))))
3964 rtx reload_reg = rld[i].reg_rtx;
3965 enum machine_mode mode = GET_MODE (reload_reg);
3969 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3971 /* We really want to ignore REG_INC notes here, so
3972 use PATTERN (p) as argument to reg_set_p . */
3973 if (reg_set_p (reload_reg, PATTERN (p)))
3975 n = count_occurrences (PATTERN (p), reload_reg, 0);
3980 n = validate_replace_rtx (reload_reg,
3981 gen_rtx (code, mode,
3985 /* We must also verify that the constraints
3986 are met after the replacement. */
3989 n = constrain_operands (1);
3993 /* If the constraints were not met, then
3994 undo the replacement. */
3997 validate_replace_rtx (gen_rtx (code, mode,
4009 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4011 /* Mark this as having an output reload so that the
4012 REG_INC processing code below won't invalidate
4013 the reload for inheritance. */
4014 SET_HARD_REG_BIT (reg_is_output_reload,
4015 REGNO (reload_reg));
4016 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4019 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4022 else if ((code == PRE_INC || code == PRE_DEC)
4023 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4024 REGNO (rld[i].reg_rtx))
4025 /* Make sure it is the inc/dec pseudo, and not
4026 some other (e.g. output operand) pseudo. */
4027 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4028 == REGNO (XEXP (in_reg, 0))))
4030 SET_HARD_REG_BIT (reg_is_output_reload,
4031 REGNO (rld[i].reg_rtx));
4032 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4036 /* If a pseudo that got a hard register is auto-incremented,
4037 we must purge records of copying it into pseudos without
4039 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4040 if (REG_NOTE_KIND (x) == REG_INC)
4042 /* See if this pseudo reg was reloaded in this insn.
4043 If so, its last-reload info is still valid
4044 because it is based on this insn's reload. */
4045 for (i = 0; i < n_reloads; i++)
4046 if (rld[i].out == XEXP (x, 0))
4050 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4054 /* A reload reg's contents are unknown after a label. */
4055 if (GET_CODE (insn) == CODE_LABEL)
4056 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4058 /* Don't assume a reload reg is still good after a call insn
4059 if it is a call-used reg. */
4060 else if (GET_CODE (insn) == CALL_INSN)
4061 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4065 free (reg_last_reload_reg);
4066 free (reg_has_output_reload);
4069 /* Discard all record of any value reloaded from X,
4070 or reloaded in X from someplace else;
4071 unless X is an output reload reg of the current insn.
4073 X may be a hard reg (the reload reg)
4074 or it may be a pseudo reg that was reloaded from. */
4077 forget_old_reloads_1 (x, ignored, data)
4079 rtx ignored ATTRIBUTE_UNUSED;
4080 void *data ATTRIBUTE_UNUSED;
4086 /* note_stores does give us subregs of hard regs,
4087 subreg_regno_offset will abort if it is not a hard reg. */
4088 while (GET_CODE (x) == SUBREG)
4090 offset += subreg_regno_offset (REGNO (SUBREG_REG (x)),
4091 GET_MODE (SUBREG_REG (x)),
4097 if (GET_CODE (x) != REG)
4100 regno = REGNO (x) + offset;
4102 if (regno >= FIRST_PSEUDO_REGISTER)
4108 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4109 /* Storing into a spilled-reg invalidates its contents.
4110 This can happen if a block-local pseudo is allocated to that reg
4111 and it wasn't spilled because this block's total need is 0.
4112 Then some insn might have an optional reload and use this reg. */
4113 for (i = 0; i < nr; i++)
4114 /* But don't do this if the reg actually serves as an output
4115 reload reg in the current instruction. */
4117 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4119 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4120 spill_reg_store[regno + i] = 0;
4124 /* Since value of X has changed,
4125 forget any value previously copied from it. */
4128 /* But don't forget a copy if this is the output reload
4129 that establishes the copy's validity. */
4130 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4131 reg_last_reload_reg[regno + nr] = 0;
4134 /* The following HARD_REG_SETs indicate when each hard register is
4135 used for a reload of various parts of the current insn. */
4137 /* If reg is unavailable for all reloads. */
4138 static HARD_REG_SET reload_reg_unavailable;
4139 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4140 static HARD_REG_SET reload_reg_used;
4141 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4142 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4143 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4144 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4145 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4146 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4147 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4148 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4149 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4150 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4151 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4152 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4153 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4154 static HARD_REG_SET reload_reg_used_in_op_addr;
4155 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4156 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4157 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4158 static HARD_REG_SET reload_reg_used_in_insn;
4159 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4160 static HARD_REG_SET reload_reg_used_in_other_addr;
4162 /* If reg is in use as a reload reg for any sort of reload. */
4163 static HARD_REG_SET reload_reg_used_at_all;
4165 /* If reg is use as an inherited reload. We just mark the first register
4167 static HARD_REG_SET reload_reg_used_for_inherit;
4169 /* Records which hard regs are used in any way, either as explicit use or
4170 by being allocated to a pseudo during any point of the current insn. */
4171 static HARD_REG_SET reg_used_in_insn;
4173 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4174 TYPE. MODE is used to indicate how many consecutive regs are
4178 mark_reload_reg_in_use (regno, opnum, type, mode)
4181 enum reload_type type;
4182 enum machine_mode mode;
4184 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4187 for (i = regno; i < nregs + regno; i++)
4192 SET_HARD_REG_BIT (reload_reg_used, i);
4195 case RELOAD_FOR_INPUT_ADDRESS:
4196 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4199 case RELOAD_FOR_INPADDR_ADDRESS:
4200 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4203 case RELOAD_FOR_OUTPUT_ADDRESS:
4204 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4207 case RELOAD_FOR_OUTADDR_ADDRESS:
4208 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4211 case RELOAD_FOR_OPERAND_ADDRESS:
4212 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4215 case RELOAD_FOR_OPADDR_ADDR:
4216 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4219 case RELOAD_FOR_OTHER_ADDRESS:
4220 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4223 case RELOAD_FOR_INPUT:
4224 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4227 case RELOAD_FOR_OUTPUT:
4228 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4231 case RELOAD_FOR_INSN:
4232 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4236 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4240 /* Similarly, but show REGNO is no longer in use for a reload. */
4243 clear_reload_reg_in_use (regno, opnum, type, mode)
4246 enum reload_type type;
4247 enum machine_mode mode;
4249 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4250 unsigned int start_regno, end_regno, r;
4252 /* A complication is that for some reload types, inheritance might
4253 allow multiple reloads of the same types to share a reload register.
4254 We set check_opnum if we have to check only reloads with the same
4255 operand number, and check_any if we have to check all reloads. */
4256 int check_opnum = 0;
4258 HARD_REG_SET *used_in_set;
4263 used_in_set = &reload_reg_used;
4266 case RELOAD_FOR_INPUT_ADDRESS:
4267 used_in_set = &reload_reg_used_in_input_addr[opnum];
4270 case RELOAD_FOR_INPADDR_ADDRESS:
4272 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4275 case RELOAD_FOR_OUTPUT_ADDRESS:
4276 used_in_set = &reload_reg_used_in_output_addr[opnum];
4279 case RELOAD_FOR_OUTADDR_ADDRESS:
4281 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4284 case RELOAD_FOR_OPERAND_ADDRESS:
4285 used_in_set = &reload_reg_used_in_op_addr;
4288 case RELOAD_FOR_OPADDR_ADDR:
4290 used_in_set = &reload_reg_used_in_op_addr_reload;
4293 case RELOAD_FOR_OTHER_ADDRESS:
4294 used_in_set = &reload_reg_used_in_other_addr;
4298 case RELOAD_FOR_INPUT:
4299 used_in_set = &reload_reg_used_in_input[opnum];
4302 case RELOAD_FOR_OUTPUT:
4303 used_in_set = &reload_reg_used_in_output[opnum];
4306 case RELOAD_FOR_INSN:
4307 used_in_set = &reload_reg_used_in_insn;
4312 /* We resolve conflicts with remaining reloads of the same type by
4313 excluding the intervals of of reload registers by them from the
4314 interval of freed reload registers. Since we only keep track of
4315 one set of interval bounds, we might have to exclude somewhat
4316 more then what would be necessary if we used a HARD_REG_SET here.
4317 But this should only happen very infrequently, so there should
4318 be no reason to worry about it. */
4320 start_regno = regno;
4321 end_regno = regno + nregs;
4322 if (check_opnum || check_any)
4324 for (i = n_reloads - 1; i >= 0; i--)
4326 if (rld[i].when_needed == type
4327 && (check_any || rld[i].opnum == opnum)
4330 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4331 unsigned int conflict_end
4333 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4335 /* If there is an overlap with the first to-be-freed register,
4336 adjust the interval start. */
4337 if (conflict_start <= start_regno && conflict_end > start_regno)
4338 start_regno = conflict_end;
4339 /* Otherwise, if there is a conflict with one of the other
4340 to-be-freed registers, adjust the interval end. */
4341 if (conflict_start > start_regno && conflict_start < end_regno)
4342 end_regno = conflict_start;
4347 for (r = start_regno; r < end_regno; r++)
4348 CLEAR_HARD_REG_BIT (*used_in_set, r);
4351 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4352 specified by OPNUM and TYPE. */
4355 reload_reg_free_p (regno, opnum, type)
4358 enum reload_type type;
4362 /* In use for a RELOAD_OTHER means it's not available for anything. */
4363 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4364 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4370 /* In use for anything means we can't use it for RELOAD_OTHER. */
4371 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4372 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4373 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4376 for (i = 0; i < reload_n_operands; i++)
4377 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4378 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4380 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4382 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4387 case RELOAD_FOR_INPUT:
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4389 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4395 /* If it is used for some other input, can't use it. */
4396 for (i = 0; i < reload_n_operands; i++)
4397 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4400 /* If it is used in a later operand's address, can't use it. */
4401 for (i = opnum + 1; i < reload_n_operands; i++)
4402 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4403 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4408 case RELOAD_FOR_INPUT_ADDRESS:
4409 /* Can't use a register if it is used for an input address for this
4410 operand or used as an input in an earlier one. */
4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4412 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4415 for (i = 0; i < opnum; i++)
4416 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4421 case RELOAD_FOR_INPADDR_ADDRESS:
4422 /* Can't use a register if it is used for an input address
4423 for this operand or used as an input in an earlier
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4428 for (i = 0; i < opnum; i++)
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4434 case RELOAD_FOR_OUTPUT_ADDRESS:
4435 /* Can't use a register if it is used for an output address for this
4436 operand or used as an output in this or a later operand. Note
4437 that multiple output operands are emitted in reverse order, so
4438 the conflicting ones are those with lower indices. */
4439 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4442 for (i = 0; i <= opnum; i++)
4443 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4448 case RELOAD_FOR_OUTADDR_ADDRESS:
4449 /* Can't use a register if it is used for an output address
4450 for this operand or used as an output in this or a
4451 later operand. Note that multiple output operands are
4452 emitted in reverse order, so the conflicting ones are
4453 those with lower indices. */
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4457 for (i = 0; i <= opnum; i++)
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4463 case RELOAD_FOR_OPERAND_ADDRESS:
4464 for (i = 0; i < reload_n_operands; i++)
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4468 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4469 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4471 case RELOAD_FOR_OPADDR_ADDR:
4472 for (i = 0; i < reload_n_operands; i++)
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4476 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4478 case RELOAD_FOR_OUTPUT:
4479 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4480 outputs, or an operand address for this or an earlier output.
4481 Note that multiple output operands are emitted in reverse order,
4482 so the conflicting ones are those with higher indices. */
4483 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4486 for (i = 0; i < reload_n_operands; i++)
4487 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4490 for (i = opnum; i < reload_n_operands; i++)
4491 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4492 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4497 case RELOAD_FOR_INSN:
4498 for (i = 0; i < reload_n_operands; i++)
4499 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4500 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4503 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4504 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4506 case RELOAD_FOR_OTHER_ADDRESS:
4507 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4512 /* Return 1 if the value in reload reg REGNO, as used by a reload
4513 needed for the part of the insn specified by OPNUM and TYPE,
4514 is still available in REGNO at the end of the insn.
4516 We can assume that the reload reg was already tested for availability
4517 at the time it is needed, and we should not check this again,
4518 in case the reg has already been marked in use. */
4521 reload_reg_reaches_end_p (regno, opnum, type)
4524 enum reload_type type;
4531 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4532 its value must reach the end. */
4535 /* If this use is for part of the insn,
4536 its value reaches if no subsequent part uses the same register.
4537 Just like the above function, don't try to do this with lots
4540 case RELOAD_FOR_OTHER_ADDRESS:
4541 /* Here we check for everything else, since these don't conflict
4542 with anything else and everything comes later. */
4544 for (i = 0; i < reload_n_operands; i++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4546 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4547 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4548 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4549 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4550 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4553 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4554 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4555 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4557 case RELOAD_FOR_INPUT_ADDRESS:
4558 case RELOAD_FOR_INPADDR_ADDRESS:
4559 /* Similar, except that we check only for this and subsequent inputs
4560 and the address of only subsequent inputs and we do not need
4561 to check for RELOAD_OTHER objects since they are known not to
4564 for (i = opnum; i < reload_n_operands; i++)
4565 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4568 for (i = opnum + 1; i < reload_n_operands; i++)
4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4573 for (i = 0; i < reload_n_operands; i++)
4574 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4575 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4579 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4582 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4583 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4584 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4586 case RELOAD_FOR_INPUT:
4587 /* Similar to input address, except we start at the next operand for
4588 both input and input address and we do not check for
4589 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4592 for (i = opnum + 1; i < reload_n_operands; i++)
4593 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4594 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4595 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4598 /* ... fall through ... */
4600 case RELOAD_FOR_OPERAND_ADDRESS:
4601 /* Check outputs and their addresses. */
4603 for (i = 0; i < reload_n_operands; i++)
4604 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4605 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4606 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4609 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4611 case RELOAD_FOR_OPADDR_ADDR:
4612 for (i = 0; i < reload_n_operands; i++)
4613 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4614 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4615 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4618 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4619 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4620 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4622 case RELOAD_FOR_INSN:
4623 /* These conflict with other outputs with RELOAD_OTHER. So
4624 we need only check for output addresses. */
4626 opnum = reload_n_operands;
4628 /* ... fall through ... */
4630 case RELOAD_FOR_OUTPUT:
4631 case RELOAD_FOR_OUTPUT_ADDRESS:
4632 case RELOAD_FOR_OUTADDR_ADDRESS:
4633 /* We already know these can't conflict with a later output. So the
4634 only thing to check are later output addresses.
4635 Note that multiple output operands are emitted in reverse order,
4636 so the conflicting ones are those with lower indices. */
4637 for (i = 0; i < opnum; i++)
4638 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4639 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4648 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4651 This function uses the same algorithm as reload_reg_free_p above. */
4654 reloads_conflict (r1, r2)
4657 enum reload_type r1_type = rld[r1].when_needed;
4658 enum reload_type r2_type = rld[r2].when_needed;
4659 int r1_opnum = rld[r1].opnum;
4660 int r2_opnum = rld[r2].opnum;
4662 /* RELOAD_OTHER conflicts with everything. */
4663 if (r2_type == RELOAD_OTHER)
4666 /* Otherwise, check conflicts differently for each type. */
4670 case RELOAD_FOR_INPUT:
4671 return (r2_type == RELOAD_FOR_INSN
4672 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4673 || r2_type == RELOAD_FOR_OPADDR_ADDR
4674 || r2_type == RELOAD_FOR_INPUT
4675 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4676 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4677 && r2_opnum > r1_opnum));
4679 case RELOAD_FOR_INPUT_ADDRESS:
4680 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4681 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4683 case RELOAD_FOR_INPADDR_ADDRESS:
4684 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4685 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4687 case RELOAD_FOR_OUTPUT_ADDRESS:
4688 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4689 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4691 case RELOAD_FOR_OUTADDR_ADDRESS:
4692 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4693 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4695 case RELOAD_FOR_OPERAND_ADDRESS:
4696 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4697 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4699 case RELOAD_FOR_OPADDR_ADDR:
4700 return (r2_type == RELOAD_FOR_INPUT
4701 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4703 case RELOAD_FOR_OUTPUT:
4704 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4705 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4706 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4707 && r2_opnum >= r1_opnum));
4709 case RELOAD_FOR_INSN:
4710 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4711 || r2_type == RELOAD_FOR_INSN
4712 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4714 case RELOAD_FOR_OTHER_ADDRESS:
4715 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4725 /* Indexed by reload number, 1 if incoming value
4726 inherited from previous insns. */
4727 char reload_inherited[MAX_RELOADS];
4729 /* For an inherited reload, this is the insn the reload was inherited from,
4730 if we know it. Otherwise, this is 0. */
4731 rtx reload_inheritance_insn[MAX_RELOADS];
4733 /* If non-zero, this is a place to get the value of the reload,
4734 rather than using reload_in. */
4735 rtx reload_override_in[MAX_RELOADS];
4737 /* For each reload, the hard register number of the register used,
4738 or -1 if we did not need a register for this reload. */
4739 int reload_spill_index[MAX_RELOADS];
4741 /* Subroutine of free_for_value_p, used to check a single register.
4742 START_REGNO is the starting regno of the full reload register
4743 (possibly comprising multiple hard registers) that we are considering. */
4746 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4747 reloadnum, ignore_address_reloads)
4748 int start_regno, regno;
4750 enum reload_type type;
4753 int ignore_address_reloads;
4756 /* Set if we see an input reload that must not share its reload register
4757 with any new earlyclobber, but might otherwise share the reload
4758 register with an output or input-output reload. */
4759 int check_earlyclobber = 0;
4763 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4766 if (out == const0_rtx)
4772 /* We use some pseudo 'time' value to check if the lifetimes of the
4773 new register use would overlap with the one of a previous reload
4774 that is not read-only or uses a different value.
4775 The 'time' used doesn't have to be linear in any shape or form, just
4777 Some reload types use different 'buckets' for each operand.
4778 So there are MAX_RECOG_OPERANDS different time values for each
4780 We compute TIME1 as the time when the register for the prospective
4781 new reload ceases to be live, and TIME2 for each existing
4782 reload as the time when that the reload register of that reload
4784 Where there is little to be gained by exact lifetime calculations,
4785 we just make conservative assumptions, i.e. a longer lifetime;
4786 this is done in the 'default:' cases. */
4789 case RELOAD_FOR_OTHER_ADDRESS:
4790 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4791 time1 = copy ? 0 : 1;
4794 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4796 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4797 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4798 respectively, to the time values for these, we get distinct time
4799 values. To get distinct time values for each operand, we have to
4800 multiply opnum by at least three. We round that up to four because
4801 multiply by four is often cheaper. */
4802 case RELOAD_FOR_INPADDR_ADDRESS:
4803 time1 = opnum * 4 + 2;
4805 case RELOAD_FOR_INPUT_ADDRESS:
4806 time1 = opnum * 4 + 3;
4808 case RELOAD_FOR_INPUT:
4809 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4810 executes (inclusive). */
4811 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4813 case RELOAD_FOR_OPADDR_ADDR:
4815 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4816 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4818 case RELOAD_FOR_OPERAND_ADDRESS:
4819 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4821 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4823 case RELOAD_FOR_OUTADDR_ADDRESS:
4824 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4826 case RELOAD_FOR_OUTPUT_ADDRESS:
4827 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4830 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4833 for (i = 0; i < n_reloads; i++)
4835 rtx reg = rld[i].reg_rtx;
4836 if (reg && GET_CODE (reg) == REG
4837 && ((unsigned) regno - true_regnum (reg)
4838 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4841 rtx other_input = rld[i].in;
4843 /* If the other reload loads the same input value, that
4844 will not cause a conflict only if it's loading it into
4845 the same register. */
4846 if (true_regnum (reg) != start_regno)
4847 other_input = NULL_RTX;
4848 if (! other_input || ! rtx_equal_p (other_input, value)
4849 || rld[i].out || out)
4852 switch (rld[i].when_needed)
4854 case RELOAD_FOR_OTHER_ADDRESS:
4857 case RELOAD_FOR_INPADDR_ADDRESS:
4858 /* find_reloads makes sure that a
4859 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4860 by at most one - the first -
4861 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4862 address reload is inherited, the address address reload
4863 goes away, so we can ignore this conflict. */
4864 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4865 && ignore_address_reloads
4866 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4867 Then the address address is still needed to store
4868 back the new address. */
4869 && ! rld[reloadnum].out)
4871 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4872 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4874 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4875 && ignore_address_reloads
4876 /* Unless we are reloading an auto_inc expression. */
4877 && ! rld[reloadnum].out)
4879 time2 = rld[i].opnum * 4 + 2;
4881 case RELOAD_FOR_INPUT_ADDRESS:
4882 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4883 && ignore_address_reloads
4884 && ! rld[reloadnum].out)
4886 time2 = rld[i].opnum * 4 + 3;
4888 case RELOAD_FOR_INPUT:
4889 time2 = rld[i].opnum * 4 + 4;
4890 check_earlyclobber = 1;
4892 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4893 == MAX_RECOG_OPERAND * 4 */
4894 case RELOAD_FOR_OPADDR_ADDR:
4895 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4896 && ignore_address_reloads
4897 && ! rld[reloadnum].out)
4899 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4901 case RELOAD_FOR_OPERAND_ADDRESS:
4902 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4903 check_earlyclobber = 1;
4905 case RELOAD_FOR_INSN:
4906 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4908 case RELOAD_FOR_OUTPUT:
4909 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4910 instruction is executed. */
4911 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4913 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4914 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4916 case RELOAD_FOR_OUTADDR_ADDRESS:
4917 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4918 && ignore_address_reloads
4919 && ! rld[reloadnum].out)
4921 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4923 case RELOAD_FOR_OUTPUT_ADDRESS:
4924 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4927 /* If there is no conflict in the input part, handle this
4928 like an output reload. */
4929 if (! rld[i].in || rtx_equal_p (other_input, value))
4931 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4932 /* Earlyclobbered outputs must conflict with inputs. */
4933 if (earlyclobber_operand_p (rld[i].out))
4934 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4939 /* RELOAD_OTHER might be live beyond instruction execution,
4940 but this is not obvious when we set time2 = 1. So check
4941 here if there might be a problem with the new reload
4942 clobbering the register used by the RELOAD_OTHER. */
4950 && (! rld[i].in || rld[i].out
4951 || ! rtx_equal_p (other_input, value)))
4952 || (out && rld[reloadnum].out_reg
4953 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4959 /* Earlyclobbered outputs must conflict with inputs. */
4960 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4966 /* Return 1 if the value in reload reg REGNO, as used by a reload
4967 needed for the part of the insn specified by OPNUM and TYPE,
4968 may be used to load VALUE into it.
4970 MODE is the mode in which the register is used, this is needed to
4971 determine how many hard regs to test.
4973 Other read-only reloads with the same value do not conflict
4974 unless OUT is non-zero and these other reloads have to live while
4975 output reloads live.
4976 If OUT is CONST0_RTX, this is a special case: it means that the
4977 test should not be for using register REGNO as reload register, but
4978 for copying from register REGNO into the reload register.
4980 RELOADNUM is the number of the reload we want to load this value for;
4981 a reload does not conflict with itself.
4983 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4984 reloads that load an address for the very reload we are considering.
4986 The caller has to make sure that there is no conflict with the return
4990 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4991 ignore_address_reloads)
4993 enum machine_mode mode;
4995 enum reload_type type;
4998 int ignore_address_reloads;
5000 int nregs = HARD_REGNO_NREGS (regno, mode);
5002 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5003 value, out, reloadnum,
5004 ignore_address_reloads))
5009 /* Determine whether the reload reg X overlaps any rtx'es used for
5010 overriding inheritance. Return nonzero if so. */
5013 conflicts_with_override (x)
5017 for (i = 0; i < n_reloads; i++)
5018 if (reload_override_in[i]
5019 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5024 /* Give an error message saying we failed to find a reload for INSN,
5025 and clear out reload R. */
5027 failed_reload (insn, r)
5031 if (asm_noperands (PATTERN (insn)) < 0)
5032 /* It's the compiler's fault. */
5033 fatal_insn ("could not find a spill register", insn);
5035 /* It's the user's fault; the operand's mode and constraint
5036 don't match. Disable this reload so we don't crash in final. */
5037 error_for_asm (insn,
5038 "`asm' operand constraint incompatible with operand size");
5042 rld[r].optional = 1;
5043 rld[r].secondary_p = 1;
5046 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5047 for reload R. If it's valid, get an rtx for it. Return nonzero if
5050 set_reload_reg (i, r)
5054 rtx reg = spill_reg_rtx[i];
5056 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5057 spill_reg_rtx[i] = reg
5058 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5060 regno = true_regnum (reg);
5062 /* Detect when the reload reg can't hold the reload mode.
5063 This used to be one `if', but Sequent compiler can't handle that. */
5064 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5066 enum machine_mode test_mode = VOIDmode;
5068 test_mode = GET_MODE (rld[r].in);
5069 /* If rld[r].in has VOIDmode, it means we will load it
5070 in whatever mode the reload reg has: to wit, rld[r].mode.
5071 We have already tested that for validity. */
5072 /* Aside from that, we need to test that the expressions
5073 to reload from or into have modes which are valid for this
5074 reload register. Otherwise the reload insns would be invalid. */
5075 if (! (rld[r].in != 0 && test_mode != VOIDmode
5076 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5077 if (! (rld[r].out != 0
5078 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5080 /* The reg is OK. */
5083 /* Mark as in use for this insn the reload regs we use
5085 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5086 rld[r].when_needed, rld[r].mode);
5088 rld[r].reg_rtx = reg;
5089 reload_spill_index[r] = spill_regs[i];
5096 /* Find a spill register to use as a reload register for reload R.
5097 LAST_RELOAD is non-zero if this is the last reload for the insn being
5100 Set rld[R].reg_rtx to the register allocated.
5102 We return 1 if successful, or 0 if we couldn't find a spill reg and
5103 we didn't change anything. */
5106 allocate_reload_reg (chain, r, last_reload)
5107 struct insn_chain *chain ATTRIBUTE_UNUSED;
5113 /* If we put this reload ahead, thinking it is a group,
5114 then insist on finding a group. Otherwise we can grab a
5115 reg that some other reload needs.
5116 (That can happen when we have a 68000 DATA_OR_FP_REG
5117 which is a group of data regs or one fp reg.)
5118 We need not be so restrictive if there are no more reloads
5121 ??? Really it would be nicer to have smarter handling
5122 for that kind of reg class, where a problem like this is normal.
5123 Perhaps those classes should be avoided for reloading
5124 by use of more alternatives. */
5126 int force_group = rld[r].nregs > 1 && ! last_reload;
5128 /* If we want a single register and haven't yet found one,
5129 take any reg in the right class and not in use.
5130 If we want a consecutive group, here is where we look for it.
5132 We use two passes so we can first look for reload regs to
5133 reuse, which are already in use for other reloads in this insn,
5134 and only then use additional registers.
5135 I think that maximizing reuse is needed to make sure we don't
5136 run out of reload regs. Suppose we have three reloads, and
5137 reloads A and B can share regs. These need two regs.
5138 Suppose A and B are given different regs.
5139 That leaves none for C. */
5140 for (pass = 0; pass < 2; pass++)
5142 /* I is the index in spill_regs.
5143 We advance it round-robin between insns to use all spill regs
5144 equally, so that inherited reloads have a chance
5145 of leapfrogging each other. */
5149 for (count = 0; count < n_spills; count++)
5151 int class = (int) rld[r].class;
5157 regnum = spill_regs[i];
5159 if ((reload_reg_free_p (regnum, rld[r].opnum,
5162 /* We check reload_reg_used to make sure we
5163 don't clobber the return register. */
5164 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5165 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5166 rld[r].when_needed, rld[r].in,
5168 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5169 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5170 /* Look first for regs to share, then for unshared. But
5171 don't share regs used for inherited reloads; they are
5172 the ones we want to preserve. */
5174 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5176 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5179 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5180 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5181 (on 68000) got us two FP regs. If NR is 1,
5182 we would reject both of them. */
5185 /* If we need only one reg, we have already won. */
5188 /* But reject a single reg if we demand a group. */
5193 /* Otherwise check that as many consecutive regs as we need
5194 are available here. */
5197 int regno = regnum + nr - 1;
5198 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5199 && spill_reg_order[regno] >= 0
5200 && reload_reg_free_p (regno, rld[r].opnum,
5201 rld[r].when_needed)))
5210 /* If we found something on pass 1, omit pass 2. */
5211 if (count < n_spills)
5215 /* We should have found a spill register by now. */
5216 if (count >= n_spills)
5219 /* I is the index in SPILL_REG_RTX of the reload register we are to
5220 allocate. Get an rtx for it and find its register number. */
5222 return set_reload_reg (i, r);
5225 /* Initialize all the tables needed to allocate reload registers.
5226 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5227 is the array we use to restore the reg_rtx field for every reload. */
5230 choose_reload_regs_init (chain, save_reload_reg_rtx)
5231 struct insn_chain *chain;
5232 rtx *save_reload_reg_rtx;
5236 for (i = 0; i < n_reloads; i++)
5237 rld[i].reg_rtx = save_reload_reg_rtx[i];
5239 memset (reload_inherited, 0, MAX_RELOADS);
5240 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5241 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5243 CLEAR_HARD_REG_SET (reload_reg_used);
5244 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5245 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5246 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5247 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5248 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5250 CLEAR_HARD_REG_SET (reg_used_in_insn);
5253 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5254 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5255 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5256 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5257 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5258 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5261 for (i = 0; i < reload_n_operands; i++)
5263 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5264 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5265 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5266 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5267 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5268 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5271 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5273 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5275 for (i = 0; i < n_reloads; i++)
5276 /* If we have already decided to use a certain register,
5277 don't use it in another way. */
5279 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5280 rld[i].when_needed, rld[i].mode);
5283 /* Assign hard reg targets for the pseudo-registers we must reload
5284 into hard regs for this insn.
5285 Also output the instructions to copy them in and out of the hard regs.
5287 For machines with register classes, we are responsible for
5288 finding a reload reg in the proper class. */
5291 choose_reload_regs (chain)
5292 struct insn_chain *chain;
5294 rtx insn = chain->insn;
5296 unsigned int max_group_size = 1;
5297 enum reg_class group_class = NO_REGS;
5298 int pass, win, inheritance;
5300 rtx save_reload_reg_rtx[MAX_RELOADS];
5302 /* In order to be certain of getting the registers we need,
5303 we must sort the reloads into order of increasing register class.
5304 Then our grabbing of reload registers will parallel the process
5305 that provided the reload registers.
5307 Also note whether any of the reloads wants a consecutive group of regs.
5308 If so, record the maximum size of the group desired and what
5309 register class contains all the groups needed by this insn. */
5311 for (j = 0; j < n_reloads; j++)
5313 reload_order[j] = j;
5314 reload_spill_index[j] = -1;
5316 if (rld[j].nregs > 1)
5318 max_group_size = MAX (rld[j].nregs, max_group_size);
5320 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5323 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5327 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5329 /* If -O, try first with inheritance, then turning it off.
5330 If not -O, don't do inheritance.
5331 Using inheritance when not optimizing leads to paradoxes
5332 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5333 because one side of the comparison might be inherited. */
5335 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5337 choose_reload_regs_init (chain, save_reload_reg_rtx);
5339 /* Process the reloads in order of preference just found.
5340 Beyond this point, subregs can be found in reload_reg_rtx.
5342 This used to look for an existing reloaded home for all of the
5343 reloads, and only then perform any new reloads. But that could lose
5344 if the reloads were done out of reg-class order because a later
5345 reload with a looser constraint might have an old home in a register
5346 needed by an earlier reload with a tighter constraint.
5348 To solve this, we make two passes over the reloads, in the order
5349 described above. In the first pass we try to inherit a reload
5350 from a previous insn. If there is a later reload that needs a
5351 class that is a proper subset of the class being processed, we must
5352 also allocate a spill register during the first pass.
5354 Then make a second pass over the reloads to allocate any reloads
5355 that haven't been given registers yet. */
5357 for (j = 0; j < n_reloads; j++)
5359 int r = reload_order[j];
5360 rtx search_equiv = NULL_RTX;
5362 /* Ignore reloads that got marked inoperative. */
5363 if (rld[r].out == 0 && rld[r].in == 0
5364 && ! rld[r].secondary_p)
5367 /* If find_reloads chose to use reload_in or reload_out as a reload
5368 register, we don't need to chose one. Otherwise, try even if it
5369 found one since we might save an insn if we find the value lying
5371 Try also when reload_in is a pseudo without a hard reg. */
5372 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5373 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5374 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5375 && GET_CODE (rld[r].in) != MEM
5376 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5379 #if 0 /* No longer needed for correct operation.
5380 It might give better code, or might not; worth an experiment? */
5381 /* If this is an optional reload, we can't inherit from earlier insns
5382 until we are sure that any non-optional reloads have been allocated.
5383 The following code takes advantage of the fact that optional reloads
5384 are at the end of reload_order. */
5385 if (rld[r].optional != 0)
5386 for (i = 0; i < j; i++)
5387 if ((rld[reload_order[i]].out != 0
5388 || rld[reload_order[i]].in != 0
5389 || rld[reload_order[i]].secondary_p)
5390 && ! rld[reload_order[i]].optional
5391 && rld[reload_order[i]].reg_rtx == 0)
5392 allocate_reload_reg (chain, reload_order[i], 0);
5395 /* First see if this pseudo is already available as reloaded
5396 for a previous insn. We cannot try to inherit for reloads
5397 that are smaller than the maximum number of registers needed
5398 for groups unless the register we would allocate cannot be used
5401 We could check here to see if this is a secondary reload for
5402 an object that is already in a register of the desired class.
5403 This would avoid the need for the secondary reload register.
5404 But this is complex because we can't easily determine what
5405 objects might want to be loaded via this reload. So let a
5406 register be allocated here. In `emit_reload_insns' we suppress
5407 one of the loads in the case described above. */
5413 enum machine_mode mode = VOIDmode;
5417 else if (GET_CODE (rld[r].in) == REG)
5419 regno = REGNO (rld[r].in);
5420 mode = GET_MODE (rld[r].in);
5422 else if (GET_CODE (rld[r].in_reg) == REG)
5424 regno = REGNO (rld[r].in_reg);
5425 mode = GET_MODE (rld[r].in_reg);
5427 else if (GET_CODE (rld[r].in_reg) == SUBREG
5428 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5430 byte = SUBREG_BYTE (rld[r].in_reg);
5431 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5432 if (regno < FIRST_PSEUDO_REGISTER)
5433 regno = subreg_regno (rld[r].in_reg);
5434 mode = GET_MODE (rld[r].in_reg);
5437 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5438 || GET_CODE (rld[r].in_reg) == PRE_DEC
5439 || GET_CODE (rld[r].in_reg) == POST_INC
5440 || GET_CODE (rld[r].in_reg) == POST_DEC)
5441 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5443 regno = REGNO (XEXP (rld[r].in_reg, 0));
5444 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5445 rld[r].out = rld[r].in;
5449 /* This won't work, since REGNO can be a pseudo reg number.
5450 Also, it takes much more hair to keep track of all the things
5451 that can invalidate an inherited reload of part of a pseudoreg. */
5452 else if (GET_CODE (rld[r].in) == SUBREG
5453 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5454 regno = subreg_regno (rld[r].in);
5457 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5459 enum reg_class class = rld[r].class, last_class;
5460 rtx last_reg = reg_last_reload_reg[regno];
5461 enum machine_mode need_mode;
5463 i = REGNO (last_reg);
5464 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5465 last_class = REGNO_REG_CLASS (i);
5471 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5472 GET_MODE_CLASS (mode));
5475 #ifdef CLASS_CANNOT_CHANGE_MODE
5477 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5478 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5480 : (GET_MODE_SIZE (GET_MODE (last_reg))
5481 >= GET_MODE_SIZE (need_mode)))
5483 (GET_MODE_SIZE (GET_MODE (last_reg))
5484 >= GET_MODE_SIZE (need_mode))
5486 && reg_reloaded_contents[i] == regno
5487 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5488 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5489 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5490 /* Even if we can't use this register as a reload
5491 register, we might use it for reload_override_in,
5492 if copying it to the desired class is cheap
5494 || ((REGISTER_MOVE_COST (mode, last_class, class)
5495 < MEMORY_MOVE_COST (mode, class, 1))
5496 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5497 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5501 #ifdef SECONDARY_MEMORY_NEEDED
5502 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5507 && (rld[r].nregs == max_group_size
5508 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5510 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5511 rld[r].when_needed, rld[r].in,
5514 /* If a group is needed, verify that all the subsequent
5515 registers still have their values intact. */
5516 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5519 for (k = 1; k < nr; k++)
5520 if (reg_reloaded_contents[i + k] != regno
5521 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5529 last_reg = (GET_MODE (last_reg) == mode
5530 ? last_reg : gen_rtx_REG (mode, i));
5533 for (k = 0; k < nr; k++)
5534 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5537 /* We found a register that contains the
5538 value we need. If this register is the
5539 same as an `earlyclobber' operand of the
5540 current insn, just mark it as a place to
5541 reload from since we can't use it as the
5542 reload register itself. */
5544 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5545 if (reg_overlap_mentioned_for_reload_p
5546 (reg_last_reload_reg[regno],
5547 reload_earlyclobbers[i1]))
5550 if (i1 != n_earlyclobbers
5551 || ! (free_for_value_p (i, rld[r].mode,
5553 rld[r].when_needed, rld[r].in,
5555 /* Don't use it if we'd clobber a pseudo reg. */
5556 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5558 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5559 /* Don't clobber the frame pointer. */
5560 || (i == HARD_FRAME_POINTER_REGNUM
5562 /* Don't really use the inherited spill reg
5563 if we need it wider than we've got it. */
5564 || (GET_MODE_SIZE (rld[r].mode)
5565 > GET_MODE_SIZE (mode))
5568 /* If find_reloads chose reload_out as reload
5569 register, stay with it - that leaves the
5570 inherited register for subsequent reloads. */
5571 || (rld[r].out && rld[r].reg_rtx
5572 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5574 if (! rld[r].optional)
5576 reload_override_in[r] = last_reg;
5577 reload_inheritance_insn[r]
5578 = reg_reloaded_insn[i];
5584 /* We can use this as a reload reg. */
5585 /* Mark the register as in use for this part of
5587 mark_reload_reg_in_use (i,
5591 rld[r].reg_rtx = last_reg;
5592 reload_inherited[r] = 1;
5593 reload_inheritance_insn[r]
5594 = reg_reloaded_insn[i];
5595 reload_spill_index[r] = i;
5596 for (k = 0; k < nr; k++)
5597 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5605 /* Here's another way to see if the value is already lying around. */
5608 && ! reload_inherited[r]
5610 && (CONSTANT_P (rld[r].in)
5611 || GET_CODE (rld[r].in) == PLUS
5612 || GET_CODE (rld[r].in) == REG
5613 || GET_CODE (rld[r].in) == MEM)
5614 && (rld[r].nregs == max_group_size
5615 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5616 search_equiv = rld[r].in;
5617 /* If this is an output reload from a simple move insn, look
5618 if an equivalence for the input is available. */
5619 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5621 rtx set = single_set (insn);
5624 && rtx_equal_p (rld[r].out, SET_DEST (set))
5625 && CONSTANT_P (SET_SRC (set)))
5626 search_equiv = SET_SRC (set);
5632 = find_equiv_reg (search_equiv, insn, rld[r].class,
5633 -1, NULL, 0, rld[r].mode);
5638 if (GET_CODE (equiv) == REG)
5639 regno = REGNO (equiv);
5640 else if (GET_CODE (equiv) == SUBREG)
5642 /* This must be a SUBREG of a hard register.
5643 Make a new REG since this might be used in an
5644 address and not all machines support SUBREGs
5646 regno = subreg_regno (equiv);
5647 equiv = gen_rtx_REG (rld[r].mode, regno);
5653 /* If we found a spill reg, reject it unless it is free
5654 and of the desired class. */
5656 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5657 && ! free_for_value_p (regno, rld[r].mode,
5658 rld[r].opnum, rld[r].when_needed,
5659 rld[r].in, rld[r].out, r, 1))
5660 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5664 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5667 /* We found a register that contains the value we need.
5668 If this register is the same as an `earlyclobber' operand
5669 of the current insn, just mark it as a place to reload from
5670 since we can't use it as the reload register itself. */
5673 for (i = 0; i < n_earlyclobbers; i++)
5674 if (reg_overlap_mentioned_for_reload_p (equiv,
5675 reload_earlyclobbers[i]))
5677 if (! rld[r].optional)
5678 reload_override_in[r] = equiv;
5683 /* If the equiv register we have found is explicitly clobbered
5684 in the current insn, it depends on the reload type if we
5685 can use it, use it for reload_override_in, or not at all.
5686 In particular, we then can't use EQUIV for a
5687 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5691 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5692 switch (rld[r].when_needed)
5694 case RELOAD_FOR_OTHER_ADDRESS:
5695 case RELOAD_FOR_INPADDR_ADDRESS:
5696 case RELOAD_FOR_INPUT_ADDRESS:
5697 case RELOAD_FOR_OPADDR_ADDR:
5700 case RELOAD_FOR_INPUT:
5701 case RELOAD_FOR_OPERAND_ADDRESS:
5702 if (! rld[r].optional)
5703 reload_override_in[r] = equiv;
5709 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5710 switch (rld[r].when_needed)
5712 case RELOAD_FOR_OTHER_ADDRESS:
5713 case RELOAD_FOR_INPADDR_ADDRESS:
5714 case RELOAD_FOR_INPUT_ADDRESS:
5715 case RELOAD_FOR_OPADDR_ADDR:
5716 case RELOAD_FOR_OPERAND_ADDRESS:
5717 case RELOAD_FOR_INPUT:
5720 if (! rld[r].optional)
5721 reload_override_in[r] = equiv;
5729 /* If we found an equivalent reg, say no code need be generated
5730 to load it, and use it as our reload reg. */
5731 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5733 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5735 rld[r].reg_rtx = equiv;
5736 reload_inherited[r] = 1;
5738 /* If reg_reloaded_valid is not set for this register,
5739 there might be a stale spill_reg_store lying around.
5740 We must clear it, since otherwise emit_reload_insns
5741 might delete the store. */
5742 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5743 spill_reg_store[regno] = NULL_RTX;
5744 /* If any of the hard registers in EQUIV are spill
5745 registers, mark them as in use for this insn. */
5746 for (k = 0; k < nr; k++)
5748 i = spill_reg_order[regno + k];
5751 mark_reload_reg_in_use (regno, rld[r].opnum,
5754 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5761 /* If we found a register to use already, or if this is an optional
5762 reload, we are done. */
5763 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5767 /* No longer needed for correct operation. Might or might
5768 not give better code on the average. Want to experiment? */
5770 /* See if there is a later reload that has a class different from our
5771 class that intersects our class or that requires less register
5772 than our reload. If so, we must allocate a register to this
5773 reload now, since that reload might inherit a previous reload
5774 and take the only available register in our class. Don't do this
5775 for optional reloads since they will force all previous reloads
5776 to be allocated. Also don't do this for reloads that have been
5779 for (i = j + 1; i < n_reloads; i++)
5781 int s = reload_order[i];
5783 if ((rld[s].in == 0 && rld[s].out == 0
5784 && ! rld[s].secondary_p)
5788 if ((rld[s].class != rld[r].class
5789 && reg_classes_intersect_p (rld[r].class,
5791 || rld[s].nregs < rld[r].nregs)
5798 allocate_reload_reg (chain, r, j == n_reloads - 1);
5802 /* Now allocate reload registers for anything non-optional that
5803 didn't get one yet. */
5804 for (j = 0; j < n_reloads; j++)
5806 int r = reload_order[j];
5808 /* Ignore reloads that got marked inoperative. */
5809 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5812 /* Skip reloads that already have a register allocated or are
5814 if (rld[r].reg_rtx != 0 || rld[r].optional)
5817 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5821 /* If that loop got all the way, we have won. */
5828 /* Loop around and try without any inheritance. */
5833 /* First undo everything done by the failed attempt
5834 to allocate with inheritance. */
5835 choose_reload_regs_init (chain, save_reload_reg_rtx);
5837 /* Some sanity tests to verify that the reloads found in the first
5838 pass are identical to the ones we have now. */
5839 if (chain->n_reloads != n_reloads)
5842 for (i = 0; i < n_reloads; i++)
5844 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5846 if (chain->rld[i].when_needed != rld[i].when_needed)
5848 for (j = 0; j < n_spills; j++)
5849 if (spill_regs[j] == chain->rld[i].regno)
5850 if (! set_reload_reg (j, i))
5851 failed_reload (chain->insn, i);
5855 /* If we thought we could inherit a reload, because it seemed that
5856 nothing else wanted the same reload register earlier in the insn,
5857 verify that assumption, now that all reloads have been assigned.
5858 Likewise for reloads where reload_override_in has been set. */
5860 /* If doing expensive optimizations, do one preliminary pass that doesn't
5861 cancel any inheritance, but removes reloads that have been needed only
5862 for reloads that we know can be inherited. */
5863 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5865 for (j = 0; j < n_reloads; j++)
5867 int r = reload_order[j];
5869 if (reload_inherited[r] && rld[r].reg_rtx)
5870 check_reg = rld[r].reg_rtx;
5871 else if (reload_override_in[r]
5872 && (GET_CODE (reload_override_in[r]) == REG
5873 || GET_CODE (reload_override_in[r]) == SUBREG))
5874 check_reg = reload_override_in[r];
5877 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5878 rld[r].opnum, rld[r].when_needed, rld[r].in,
5879 (reload_inherited[r]
5880 ? rld[r].out : const0_rtx),
5885 reload_inherited[r] = 0;
5886 reload_override_in[r] = 0;
5888 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5889 reload_override_in, then we do not need its related
5890 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5891 likewise for other reload types.
5892 We handle this by removing a reload when its only replacement
5893 is mentioned in reload_in of the reload we are going to inherit.
5894 A special case are auto_inc expressions; even if the input is
5895 inherited, we still need the address for the output. We can
5896 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5897 If we succeeded removing some reload and we are doing a preliminary
5898 pass just to remove such reloads, make another pass, since the
5899 removal of one reload might allow us to inherit another one. */
5901 && rld[r].out != rld[r].in
5902 && remove_address_replacements (rld[r].in) && pass)
5907 /* Now that reload_override_in is known valid,
5908 actually override reload_in. */
5909 for (j = 0; j < n_reloads; j++)
5910 if (reload_override_in[j])
5911 rld[j].in = reload_override_in[j];
5913 /* If this reload won't be done because it has been cancelled or is
5914 optional and not inherited, clear reload_reg_rtx so other
5915 routines (such as subst_reloads) don't get confused. */
5916 for (j = 0; j < n_reloads; j++)
5917 if (rld[j].reg_rtx != 0
5918 && ((rld[j].optional && ! reload_inherited[j])
5919 || (rld[j].in == 0 && rld[j].out == 0
5920 && ! rld[j].secondary_p)))
5922 int regno = true_regnum (rld[j].reg_rtx);
5924 if (spill_reg_order[regno] >= 0)
5925 clear_reload_reg_in_use (regno, rld[j].opnum,
5926 rld[j].when_needed, rld[j].mode);
5928 reload_spill_index[j] = -1;
5931 /* Record which pseudos and which spill regs have output reloads. */
5932 for (j = 0; j < n_reloads; j++)
5934 int r = reload_order[j];
5936 i = reload_spill_index[r];
5938 /* I is nonneg if this reload uses a register.
5939 If rld[r].reg_rtx is 0, this is an optional reload
5940 that we opted to ignore. */
5941 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5942 && rld[r].reg_rtx != 0)
5944 int nregno = REGNO (rld[r].out_reg);
5947 if (nregno < FIRST_PSEUDO_REGISTER)
5948 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5951 reg_has_output_reload[nregno + nr] = 1;
5955 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5957 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5960 if (rld[r].when_needed != RELOAD_OTHER
5961 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5962 && rld[r].when_needed != RELOAD_FOR_INSN)
5968 /* Deallocate the reload register for reload R. This is called from
5969 remove_address_replacements. */
5972 deallocate_reload_reg (r)
5977 if (! rld[r].reg_rtx)
5979 regno = true_regnum (rld[r].reg_rtx);
5981 if (spill_reg_order[regno] >= 0)
5982 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5984 reload_spill_index[r] = -1;
5987 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5988 reloads of the same item for fear that we might not have enough reload
5989 registers. However, normally they will get the same reload register
5990 and hence actually need not be loaded twice.
5992 Here we check for the most common case of this phenomenon: when we have
5993 a number of reloads for the same object, each of which were allocated
5994 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5995 reload, and is not modified in the insn itself. If we find such,
5996 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5997 This will not increase the number of spill registers needed and will
5998 prevent redundant code. */
6001 merge_assigned_reloads (insn)
6006 /* Scan all the reloads looking for ones that only load values and
6007 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6008 assigned and not modified by INSN. */
6010 for (i = 0; i < n_reloads; i++)
6012 int conflicting_input = 0;
6013 int max_input_address_opnum = -1;
6014 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6016 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6017 || rld[i].out != 0 || rld[i].reg_rtx == 0
6018 || reg_set_p (rld[i].reg_rtx, insn))
6021 /* Look at all other reloads. Ensure that the only use of this
6022 reload_reg_rtx is in a reload that just loads the same value
6023 as we do. Note that any secondary reloads must be of the identical
6024 class since the values, modes, and result registers are the
6025 same, so we need not do anything with any secondary reloads. */
6027 for (j = 0; j < n_reloads; j++)
6029 if (i == j || rld[j].reg_rtx == 0
6030 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6034 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6035 && rld[j].opnum > max_input_address_opnum)
6036 max_input_address_opnum = rld[j].opnum;
6038 /* If the reload regs aren't exactly the same (e.g, different modes)
6039 or if the values are different, we can't merge this reload.
6040 But if it is an input reload, we might still merge
6041 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6043 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6044 || rld[j].out != 0 || rld[j].in == 0
6045 || ! rtx_equal_p (rld[i].in, rld[j].in))
6047 if (rld[j].when_needed != RELOAD_FOR_INPUT
6048 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6049 || rld[i].opnum > rld[j].opnum)
6050 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6052 conflicting_input = 1;
6053 if (min_conflicting_input_opnum > rld[j].opnum)
6054 min_conflicting_input_opnum = rld[j].opnum;
6058 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6059 we, in fact, found any matching reloads. */
6062 && max_input_address_opnum <= min_conflicting_input_opnum)
6064 for (j = 0; j < n_reloads; j++)
6065 if (i != j && rld[j].reg_rtx != 0
6066 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6067 && (! conflicting_input
6068 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6069 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6071 rld[i].when_needed = RELOAD_OTHER;
6073 reload_spill_index[j] = -1;
6074 transfer_replacements (i, j);
6077 /* If this is now RELOAD_OTHER, look for any reloads that load
6078 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6079 if they were for inputs, RELOAD_OTHER for outputs. Note that
6080 this test is equivalent to looking for reloads for this operand
6083 if (rld[i].when_needed == RELOAD_OTHER)
6084 for (j = 0; j < n_reloads; j++)
6086 && rld[j].when_needed != RELOAD_OTHER
6087 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6090 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6091 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6092 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6097 /* These arrays are filled by emit_reload_insns and its subroutines. */
6098 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6099 static rtx other_input_address_reload_insns = 0;
6100 static rtx other_input_reload_insns = 0;
6101 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6102 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6103 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6104 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6105 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6106 static rtx operand_reload_insns = 0;
6107 static rtx other_operand_reload_insns = 0;
6108 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6110 /* Values to be put in spill_reg_store are put here first. */
6111 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6112 static HARD_REG_SET reg_reloaded_died;
6114 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6115 has the number J. OLD contains the value to be used as input. */
6118 emit_input_reload_insns (chain, rl, old, j)
6119 struct insn_chain *chain;
6124 rtx insn = chain->insn;
6125 rtx reloadreg = rl->reg_rtx;
6126 rtx oldequiv_reg = 0;
6129 enum machine_mode mode;
6132 /* Determine the mode to reload in.
6133 This is very tricky because we have three to choose from.
6134 There is the mode the insn operand wants (rl->inmode).
6135 There is the mode of the reload register RELOADREG.
6136 There is the intrinsic mode of the operand, which we could find
6137 by stripping some SUBREGs.
6138 It turns out that RELOADREG's mode is irrelevant:
6139 we can change that arbitrarily.
6141 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6142 then the reload reg may not support QImode moves, so use SImode.
6143 If foo is in memory due to spilling a pseudo reg, this is safe,
6144 because the QImode value is in the least significant part of a
6145 slot big enough for a SImode. If foo is some other sort of
6146 memory reference, then it is impossible to reload this case,
6147 so previous passes had better make sure this never happens.
6149 Then consider a one-word union which has SImode and one of its
6150 members is a float, being fetched as (SUBREG:SF union:SI).
6151 We must fetch that as SFmode because we could be loading into
6152 a float-only register. In this case OLD's mode is correct.
6154 Consider an immediate integer: it has VOIDmode. Here we need
6155 to get a mode from something else.
6157 In some cases, there is a fourth mode, the operand's
6158 containing mode. If the insn specifies a containing mode for
6159 this operand, it overrides all others.
6161 I am not sure whether the algorithm here is always right,
6162 but it does the right things in those cases. */
6164 mode = GET_MODE (old);
6165 if (mode == VOIDmode)
6168 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6169 /* If we need a secondary register for this operation, see if
6170 the value is already in a register in that class. Don't
6171 do this if the secondary register will be used as a scratch
6174 if (rl->secondary_in_reload >= 0
6175 && rl->secondary_in_icode == CODE_FOR_nothing
6178 = find_equiv_reg (old, insn,
6179 rld[rl->secondary_in_reload].class,
6183 /* If reloading from memory, see if there is a register
6184 that already holds the same value. If so, reload from there.
6185 We can pass 0 as the reload_reg_p argument because
6186 any other reload has either already been emitted,
6187 in which case find_equiv_reg will see the reload-insn,
6188 or has yet to be emitted, in which case it doesn't matter
6189 because we will use this equiv reg right away. */
6191 if (oldequiv == 0 && optimize
6192 && (GET_CODE (old) == MEM
6193 || (GET_CODE (old) == REG
6194 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6195 && reg_renumber[REGNO (old)] < 0)))
6196 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6200 unsigned int regno = true_regnum (oldequiv);
6202 /* Don't use OLDEQUIV if any other reload changes it at an
6203 earlier stage of this insn or at this stage. */
6204 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6205 rl->in, const0_rtx, j, 0))
6208 /* If it is no cheaper to copy from OLDEQUIV into the
6209 reload register than it would be to move from memory,
6210 don't use it. Likewise, if we need a secondary register
6214 && ((REGNO_REG_CLASS (regno) != rl->class
6215 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6217 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6218 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6219 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6223 #ifdef SECONDARY_MEMORY_NEEDED
6224 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6232 /* delete_output_reload is only invoked properly if old contains
6233 the original pseudo register. Since this is replaced with a
6234 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6235 find the pseudo in RELOAD_IN_REG. */
6237 && reload_override_in[j]
6238 && GET_CODE (rl->in_reg) == REG)
6245 else if (GET_CODE (oldequiv) == REG)
6246 oldequiv_reg = oldequiv;
6247 else if (GET_CODE (oldequiv) == SUBREG)
6248 oldequiv_reg = SUBREG_REG (oldequiv);
6250 /* If we are reloading from a register that was recently stored in
6251 with an output-reload, see if we can prove there was
6252 actually no need to store the old value in it. */
6254 if (optimize && GET_CODE (oldequiv) == REG
6255 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6256 && spill_reg_store[REGNO (oldequiv)]
6257 && GET_CODE (old) == REG
6258 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6259 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6261 delete_output_reload (insn, j, REGNO (oldequiv));
6263 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6264 then load RELOADREG from OLDEQUIV. Note that we cannot use
6265 gen_lowpart_common since it can do the wrong thing when
6266 RELOADREG has a multi-word mode. Note that RELOADREG
6267 must always be a REG here. */
6269 if (GET_MODE (reloadreg) != mode)
6270 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6271 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6272 oldequiv = SUBREG_REG (oldequiv);
6273 if (GET_MODE (oldequiv) != VOIDmode
6274 && mode != GET_MODE (oldequiv))
6275 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6277 /* Switch to the right place to emit the reload insns. */
6278 switch (rl->when_needed)
6281 where = &other_input_reload_insns;
6283 case RELOAD_FOR_INPUT:
6284 where = &input_reload_insns[rl->opnum];
6286 case RELOAD_FOR_INPUT_ADDRESS:
6287 where = &input_address_reload_insns[rl->opnum];
6289 case RELOAD_FOR_INPADDR_ADDRESS:
6290 where = &inpaddr_address_reload_insns[rl->opnum];
6292 case RELOAD_FOR_OUTPUT_ADDRESS:
6293 where = &output_address_reload_insns[rl->opnum];
6295 case RELOAD_FOR_OUTADDR_ADDRESS:
6296 where = &outaddr_address_reload_insns[rl->opnum];
6298 case RELOAD_FOR_OPERAND_ADDRESS:
6299 where = &operand_reload_insns;
6301 case RELOAD_FOR_OPADDR_ADDR:
6302 where = &other_operand_reload_insns;
6304 case RELOAD_FOR_OTHER_ADDRESS:
6305 where = &other_input_address_reload_insns;
6311 push_to_sequence (*where);
6313 /* Auto-increment addresses must be reloaded in a special way. */
6314 if (rl->out && ! rl->out_reg)
6316 /* We are not going to bother supporting the case where a
6317 incremented register can't be copied directly from
6318 OLDEQUIV since this seems highly unlikely. */
6319 if (rl->secondary_in_reload >= 0)
6322 if (reload_inherited[j])
6323 oldequiv = reloadreg;
6325 old = XEXP (rl->in_reg, 0);
6327 if (optimize && GET_CODE (oldequiv) == REG
6328 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6329 && spill_reg_store[REGNO (oldequiv)]
6330 && GET_CODE (old) == REG
6331 && (dead_or_set_p (insn,
6332 spill_reg_stored_to[REGNO (oldequiv)])
6333 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6335 delete_output_reload (insn, j, REGNO (oldequiv));
6337 /* Prevent normal processing of this reload. */
6339 /* Output a special code sequence for this case. */
6340 new_spill_reg_store[REGNO (reloadreg)]
6341 = inc_for_reload (reloadreg, oldequiv, rl->out,
6345 /* If we are reloading a pseudo-register that was set by the previous
6346 insn, see if we can get rid of that pseudo-register entirely
6347 by redirecting the previous insn into our reload register. */
6349 else if (optimize && GET_CODE (old) == REG
6350 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6351 && dead_or_set_p (insn, old)
6352 /* This is unsafe if some other reload
6353 uses the same reg first. */
6354 && ! conflicts_with_override (reloadreg)
6355 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6356 rl->when_needed, old, rl->out, j, 0))
6358 rtx temp = PREV_INSN (insn);
6359 while (temp && GET_CODE (temp) == NOTE)
6360 temp = PREV_INSN (temp);
6362 && GET_CODE (temp) == INSN
6363 && GET_CODE (PATTERN (temp)) == SET
6364 && SET_DEST (PATTERN (temp)) == old
6365 /* Make sure we can access insn_operand_constraint. */
6366 && asm_noperands (PATTERN (temp)) < 0
6367 /* This is unsafe if prev insn rejects our reload reg. */
6368 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6370 /* This is unsafe if operand occurs more than once in current
6371 insn. Perhaps some occurrences aren't reloaded. */
6372 && count_occurrences (PATTERN (insn), old, 0) == 1
6373 /* Don't risk splitting a matching pair of operands. */
6374 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6376 /* Store into the reload register instead of the pseudo. */
6377 SET_DEST (PATTERN (temp)) = reloadreg;
6379 /* If the previous insn is an output reload, the source is
6380 a reload register, and its spill_reg_store entry will
6381 contain the previous destination. This is now
6383 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6384 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6386 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6387 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6390 /* If these are the only uses of the pseudo reg,
6391 pretend for GDB it lives in the reload reg we used. */
6392 if (REG_N_DEATHS (REGNO (old)) == 1
6393 && REG_N_SETS (REGNO (old)) == 1)
6395 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6396 alter_reg (REGNO (old), -1);
6402 /* We can't do that, so output an insn to load RELOADREG. */
6404 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6405 /* If we have a secondary reload, pick up the secondary register
6406 and icode, if any. If OLDEQUIV and OLD are different or
6407 if this is an in-out reload, recompute whether or not we
6408 still need a secondary register and what the icode should
6409 be. If we still need a secondary register and the class or
6410 icode is different, go back to reloading from OLD if using
6411 OLDEQUIV means that we got the wrong type of register. We
6412 cannot have different class or icode due to an in-out reload
6413 because we don't make such reloads when both the input and
6414 output need secondary reload registers. */
6416 if (! special && rl->secondary_in_reload >= 0)
6418 rtx second_reload_reg = 0;
6419 int secondary_reload = rl->secondary_in_reload;
6420 rtx real_oldequiv = oldequiv;
6423 enum insn_code icode;
6425 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6426 and similarly for OLD.
6427 See comments in get_secondary_reload in reload.c. */
6428 /* If it is a pseudo that cannot be replaced with its
6429 equivalent MEM, we must fall back to reload_in, which
6430 will have all the necessary substitutions registered.
6431 Likewise for a pseudo that can't be replaced with its
6432 equivalent constant.
6434 Take extra care for subregs of such pseudos. Note that
6435 we cannot use reg_equiv_mem in this case because it is
6436 not in the right mode. */
6439 if (GET_CODE (tmp) == SUBREG)
6440 tmp = SUBREG_REG (tmp);
6441 if (GET_CODE (tmp) == REG
6442 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6443 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6444 || reg_equiv_constant[REGNO (tmp)] != 0))
6446 if (! reg_equiv_mem[REGNO (tmp)]
6447 || num_not_at_initial_offset
6448 || GET_CODE (oldequiv) == SUBREG)
6449 real_oldequiv = rl->in;
6451 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6455 if (GET_CODE (tmp) == SUBREG)
6456 tmp = SUBREG_REG (tmp);
6457 if (GET_CODE (tmp) == REG
6458 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6459 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6460 || reg_equiv_constant[REGNO (tmp)] != 0))
6462 if (! reg_equiv_mem[REGNO (tmp)]
6463 || num_not_at_initial_offset
6464 || GET_CODE (old) == SUBREG)
6467 real_old = reg_equiv_mem[REGNO (tmp)];
6470 second_reload_reg = rld[secondary_reload].reg_rtx;
6471 icode = rl->secondary_in_icode;
6473 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6474 || (rl->in != 0 && rl->out != 0))
6476 enum reg_class new_class
6477 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6478 mode, real_oldequiv);
6480 if (new_class == NO_REGS)
6481 second_reload_reg = 0;
6484 enum insn_code new_icode;
6485 enum machine_mode new_mode;
6487 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6488 REGNO (second_reload_reg)))
6489 oldequiv = old, real_oldequiv = real_old;
6492 new_icode = reload_in_optab[(int) mode];
6493 if (new_icode != CODE_FOR_nothing
6494 && ((insn_data[(int) new_icode].operand[0].predicate
6495 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6497 || (insn_data[(int) new_icode].operand[1].predicate
6498 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6499 (real_oldequiv, mode)))))
6500 new_icode = CODE_FOR_nothing;
6502 if (new_icode == CODE_FOR_nothing)
6505 new_mode = insn_data[(int) new_icode].operand[2].mode;
6507 if (GET_MODE (second_reload_reg) != new_mode)
6509 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6511 oldequiv = old, real_oldequiv = real_old;
6514 = gen_rtx_REG (new_mode,
6515 REGNO (second_reload_reg));
6521 /* If we still need a secondary reload register, check
6522 to see if it is being used as a scratch or intermediate
6523 register and generate code appropriately. If we need
6524 a scratch register, use REAL_OLDEQUIV since the form of
6525 the insn may depend on the actual address if it is
6528 if (second_reload_reg)
6530 if (icode != CODE_FOR_nothing)
6532 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6533 second_reload_reg));
6538 /* See if we need a scratch register to load the
6539 intermediate register (a tertiary reload). */
6540 enum insn_code tertiary_icode
6541 = rld[secondary_reload].secondary_in_icode;
6543 if (tertiary_icode != CODE_FOR_nothing)
6545 rtx third_reload_reg
6546 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6548 emit_insn ((GEN_FCN (tertiary_icode)
6549 (second_reload_reg, real_oldequiv,
6550 third_reload_reg)));
6553 gen_reload (second_reload_reg, real_oldequiv,
6557 oldequiv = second_reload_reg;
6563 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6565 rtx real_oldequiv = oldequiv;
6567 if ((GET_CODE (oldequiv) == REG
6568 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6569 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6570 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6571 || (GET_CODE (oldequiv) == SUBREG
6572 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6573 && (REGNO (SUBREG_REG (oldequiv))
6574 >= FIRST_PSEUDO_REGISTER)
6575 && ((reg_equiv_memory_loc
6576 [REGNO (SUBREG_REG (oldequiv))] != 0)
6577 || (reg_equiv_constant
6578 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6579 || (CONSTANT_P (oldequiv)
6580 && (PREFERRED_RELOAD_CLASS (oldequiv,
6581 REGNO_REG_CLASS (REGNO (reloadreg)))
6583 real_oldequiv = rl->in;
6584 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6588 if (flag_non_call_exceptions)
6589 copy_eh_notes (insn, get_insns ());
6591 /* End this sequence. */
6592 *where = get_insns ();
6595 /* Update reload_override_in so that delete_address_reloads_1
6596 can see the actual register usage. */
6598 reload_override_in[j] = oldequiv;
6601 /* Generate insns to for the output reload RL, which is for the insn described
6602 by CHAIN and has the number J. */
6604 emit_output_reload_insns (chain, rl, j)
6605 struct insn_chain *chain;
6609 rtx reloadreg = rl->reg_rtx;
6610 rtx insn = chain->insn;
6613 enum machine_mode mode = GET_MODE (old);
6616 if (rl->when_needed == RELOAD_OTHER)
6619 push_to_sequence (output_reload_insns[rl->opnum]);
6621 /* Determine the mode to reload in.
6622 See comments above (for input reloading). */
6624 if (mode == VOIDmode)
6626 /* VOIDmode should never happen for an output. */
6627 if (asm_noperands (PATTERN (insn)) < 0)
6628 /* It's the compiler's fault. */
6629 fatal_insn ("VOIDmode on an output", insn);
6630 error_for_asm (insn, "output operand is constant in `asm'");
6631 /* Prevent crash--use something we know is valid. */
6633 old = gen_rtx_REG (mode, REGNO (reloadreg));
6636 if (GET_MODE (reloadreg) != mode)
6637 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6639 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6641 /* If we need two reload regs, set RELOADREG to the intermediate
6642 one, since it will be stored into OLD. We might need a secondary
6643 register only for an input reload, so check again here. */
6645 if (rl->secondary_out_reload >= 0)
6649 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6650 && reg_equiv_mem[REGNO (old)] != 0)
6651 real_old = reg_equiv_mem[REGNO (old)];
6653 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6657 rtx second_reloadreg = reloadreg;
6658 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6660 /* See if RELOADREG is to be used as a scratch register
6661 or as an intermediate register. */
6662 if (rl->secondary_out_icode != CODE_FOR_nothing)
6664 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6665 (real_old, second_reloadreg, reloadreg)));
6670 /* See if we need both a scratch and intermediate reload
6673 int secondary_reload = rl->secondary_out_reload;
6674 enum insn_code tertiary_icode
6675 = rld[secondary_reload].secondary_out_icode;
6677 if (GET_MODE (reloadreg) != mode)
6678 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6680 if (tertiary_icode != CODE_FOR_nothing)
6683 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6686 /* Copy primary reload reg to secondary reload reg.
6687 (Note that these have been swapped above, then
6688 secondary reload reg to OLD using our insn.) */
6690 /* If REAL_OLD is a paradoxical SUBREG, remove it
6691 and try to put the opposite SUBREG on
6693 if (GET_CODE (real_old) == SUBREG
6694 && (GET_MODE_SIZE (GET_MODE (real_old))
6695 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6696 && 0 != (tem = gen_lowpart_common
6697 (GET_MODE (SUBREG_REG (real_old)),
6699 real_old = SUBREG_REG (real_old), reloadreg = tem;
6701 gen_reload (reloadreg, second_reloadreg,
6702 rl->opnum, rl->when_needed);
6703 emit_insn ((GEN_FCN (tertiary_icode)
6704 (real_old, reloadreg, third_reloadreg)));
6709 /* Copy between the reload regs here and then to
6712 gen_reload (reloadreg, second_reloadreg,
6713 rl->opnum, rl->when_needed);
6719 /* Output the last reload insn. */
6724 /* Don't output the last reload if OLD is not the dest of
6725 INSN and is in the src and is clobbered by INSN. */
6726 if (! flag_expensive_optimizations
6727 || GET_CODE (old) != REG
6728 || !(set = single_set (insn))
6729 || rtx_equal_p (old, SET_DEST (set))
6730 || !reg_mentioned_p (old, SET_SRC (set))
6731 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6732 gen_reload (old, reloadreg, rl->opnum,
6736 /* Look at all insns we emitted, just to be safe. */
6737 for (p = get_insns (); p; p = NEXT_INSN (p))
6740 rtx pat = PATTERN (p);
6742 /* If this output reload doesn't come from a spill reg,
6743 clear any memory of reloaded copies of the pseudo reg.
6744 If this output reload comes from a spill reg,
6745 reg_has_output_reload will make this do nothing. */
6746 note_stores (pat, forget_old_reloads_1, NULL);
6748 if (reg_mentioned_p (rl->reg_rtx, pat))
6750 rtx set = single_set (insn);
6751 if (reload_spill_index[j] < 0
6753 && SET_SRC (set) == rl->reg_rtx)
6755 int src = REGNO (SET_SRC (set));
6757 reload_spill_index[j] = src;
6758 SET_HARD_REG_BIT (reg_is_output_reload, src);
6759 if (find_regno_note (insn, REG_DEAD, src))
6760 SET_HARD_REG_BIT (reg_reloaded_died, src);
6762 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6764 int s = rl->secondary_out_reload;
6765 set = single_set (p);
6766 /* If this reload copies only to the secondary reload
6767 register, the secondary reload does the actual
6769 if (s >= 0 && set == NULL_RTX)
6770 /* We can't tell what function the secondary reload
6771 has and where the actual store to the pseudo is
6772 made; leave new_spill_reg_store alone. */
6775 && SET_SRC (set) == rl->reg_rtx
6776 && SET_DEST (set) == rld[s].reg_rtx)
6778 /* Usually the next instruction will be the
6779 secondary reload insn; if we can confirm
6780 that it is, setting new_spill_reg_store to
6781 that insn will allow an extra optimization. */
6782 rtx s_reg = rld[s].reg_rtx;
6783 rtx next = NEXT_INSN (p);
6784 rld[s].out = rl->out;
6785 rld[s].out_reg = rl->out_reg;
6786 set = single_set (next);
6787 if (set && SET_SRC (set) == s_reg
6788 && ! new_spill_reg_store[REGNO (s_reg)])
6790 SET_HARD_REG_BIT (reg_is_output_reload,
6792 new_spill_reg_store[REGNO (s_reg)] = next;
6796 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6801 if (rl->when_needed == RELOAD_OTHER)
6803 emit_insns (other_output_reload_insns[rl->opnum]);
6804 other_output_reload_insns[rl->opnum] = get_insns ();
6807 output_reload_insns[rl->opnum] = get_insns ();
6809 if (flag_non_call_exceptions)
6810 copy_eh_notes (insn, get_insns ());
6815 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6816 and has the number J. */
6818 do_input_reload (chain, rl, j)
6819 struct insn_chain *chain;
6823 int expect_occurrences = 1;
6824 rtx insn = chain->insn;
6825 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6826 ? rl->in_reg : rl->in);
6829 /* AUTO_INC reloads need to be handled even if inherited. We got an
6830 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6831 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6832 && ! rtx_equal_p (rl->reg_rtx, old)
6833 && rl->reg_rtx != 0)
6834 emit_input_reload_insns (chain, rld + j, old, j);
6836 /* When inheriting a wider reload, we have a MEM in rl->in,
6837 e.g. inheriting a SImode output reload for
6838 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6839 if (optimize && reload_inherited[j] && rl->in
6840 && GET_CODE (rl->in) == MEM
6841 && GET_CODE (rl->in_reg) == MEM
6842 && reload_spill_index[j] >= 0
6843 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6846 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6847 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6850 /* If we are reloading a register that was recently stored in with an
6851 output-reload, see if we can prove there was
6852 actually no need to store the old value in it. */
6855 && (reload_inherited[j] || reload_override_in[j])
6857 && GET_CODE (rl->reg_rtx) == REG
6858 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6860 /* There doesn't seem to be any reason to restrict this to pseudos
6861 and doing so loses in the case where we are copying from a
6862 register of the wrong class. */
6863 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6864 >= FIRST_PSEUDO_REGISTER)
6866 /* The insn might have already some references to stackslots
6867 replaced by MEMs, while reload_out_reg still names the
6869 && (dead_or_set_p (insn,
6870 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6871 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6873 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6876 /* Do output reloading for reload RL, which is for the insn described by
6877 CHAIN and has the number J.
6878 ??? At some point we need to support handling output reloads of
6879 JUMP_INSNs or insns that set cc0. */
6881 do_output_reload (chain, rl, j)
6882 struct insn_chain *chain;
6887 rtx insn = chain->insn;
6888 /* If this is an output reload that stores something that is
6889 not loaded in this same reload, see if we can eliminate a previous
6891 rtx pseudo = rl->out_reg;
6894 && GET_CODE (pseudo) == REG
6895 && ! rtx_equal_p (rl->in_reg, pseudo)
6896 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6897 && reg_last_reload_reg[REGNO (pseudo)])
6899 int pseudo_no = REGNO (pseudo);
6900 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6902 /* We don't need to test full validity of last_regno for
6903 inherit here; we only want to know if the store actually
6904 matches the pseudo. */
6905 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6906 && reg_reloaded_contents[last_regno] == pseudo_no
6907 && spill_reg_store[last_regno]
6908 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6909 delete_output_reload (insn, j, last_regno);
6914 || rl->reg_rtx == old
6915 || rl->reg_rtx == 0)
6918 /* An output operand that dies right away does need a reload,
6919 but need not be copied from it. Show the new location in the
6921 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6922 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6924 XEXP (note, 0) = rl->reg_rtx;
6927 /* Likewise for a SUBREG of an operand that dies. */
6928 else if (GET_CODE (old) == SUBREG
6929 && GET_CODE (SUBREG_REG (old)) == REG
6930 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6933 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6937 else if (GET_CODE (old) == SCRATCH)
6938 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6939 but we don't want to make an output reload. */
6942 /* If is a JUMP_INSN, we can't support output reloads yet. */
6943 if (GET_CODE (insn) == JUMP_INSN)
6946 emit_output_reload_insns (chain, rld + j, j);
6949 /* Output insns to reload values in and out of the chosen reload regs. */
6952 emit_reload_insns (chain)
6953 struct insn_chain *chain;
6955 rtx insn = chain->insn;
6959 CLEAR_HARD_REG_SET (reg_reloaded_died);
6961 for (j = 0; j < reload_n_operands; j++)
6962 input_reload_insns[j] = input_address_reload_insns[j]
6963 = inpaddr_address_reload_insns[j]
6964 = output_reload_insns[j] = output_address_reload_insns[j]
6965 = outaddr_address_reload_insns[j]
6966 = other_output_reload_insns[j] = 0;
6967 other_input_address_reload_insns = 0;
6968 other_input_reload_insns = 0;
6969 operand_reload_insns = 0;
6970 other_operand_reload_insns = 0;
6972 /* Dump reloads into the dump file. */
6975 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6976 debug_reload_to_stream (rtl_dump_file);
6979 /* Now output the instructions to copy the data into and out of the
6980 reload registers. Do these in the order that the reloads were reported,
6981 since reloads of base and index registers precede reloads of operands
6982 and the operands may need the base and index registers reloaded. */
6984 for (j = 0; j < n_reloads; j++)
6987 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6988 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6990 do_input_reload (chain, rld + j, j);
6991 do_output_reload (chain, rld + j, j);
6994 /* Now write all the insns we made for reloads in the order expected by
6995 the allocation functions. Prior to the insn being reloaded, we write
6996 the following reloads:
6998 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7000 RELOAD_OTHER reloads.
7002 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7003 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7004 RELOAD_FOR_INPUT reload for the operand.
7006 RELOAD_FOR_OPADDR_ADDRS reloads.
7008 RELOAD_FOR_OPERAND_ADDRESS reloads.
7010 After the insn being reloaded, we write the following:
7012 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7013 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7014 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7015 reloads for the operand. The RELOAD_OTHER output reloads are
7016 output in descending order by reload number. */
7018 emit_insns_before (other_input_address_reload_insns, insn);
7019 emit_insns_before (other_input_reload_insns, insn);
7021 for (j = 0; j < reload_n_operands; j++)
7023 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7024 emit_insns_before (input_address_reload_insns[j], insn);
7025 emit_insns_before (input_reload_insns[j], insn);
7028 emit_insns_before (other_operand_reload_insns, insn);
7029 emit_insns_before (operand_reload_insns, insn);
7031 for (j = 0; j < reload_n_operands; j++)
7033 rtx x = emit_insns_after (outaddr_address_reload_insns[j], insn);
7034 x = emit_insns_after (output_address_reload_insns[j], x);
7035 x = emit_insns_after (output_reload_insns[j], x);
7036 emit_insns_after (other_output_reload_insns[j], x);
7039 /* For all the spill regs newly reloaded in this instruction,
7040 record what they were reloaded from, so subsequent instructions
7041 can inherit the reloads.
7043 Update spill_reg_store for the reloads of this insn.
7044 Copy the elements that were updated in the loop above. */
7046 for (j = 0; j < n_reloads; j++)
7048 int r = reload_order[j];
7049 int i = reload_spill_index[r];
7051 /* If this is a non-inherited input reload from a pseudo, we must
7052 clear any memory of a previous store to the same pseudo. Only do
7053 something if there will not be an output reload for the pseudo
7055 if (rld[r].in_reg != 0
7056 && ! (reload_inherited[r] || reload_override_in[r]))
7058 rtx reg = rld[r].in_reg;
7060 if (GET_CODE (reg) == SUBREG)
7061 reg = SUBREG_REG (reg);
7063 if (GET_CODE (reg) == REG
7064 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7065 && ! reg_has_output_reload[REGNO (reg)])
7067 int nregno = REGNO (reg);
7069 if (reg_last_reload_reg[nregno])
7071 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7073 if (reg_reloaded_contents[last_regno] == nregno)
7074 spill_reg_store[last_regno] = 0;
7079 /* I is nonneg if this reload used a register.
7080 If rld[r].reg_rtx is 0, this is an optional reload
7081 that we opted to ignore. */
7083 if (i >= 0 && rld[r].reg_rtx != 0)
7085 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7087 int part_reaches_end = 0;
7088 int all_reaches_end = 1;
7090 /* For a multi register reload, we need to check if all or part
7091 of the value lives to the end. */
7092 for (k = 0; k < nr; k++)
7094 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7095 rld[r].when_needed))
7096 part_reaches_end = 1;
7098 all_reaches_end = 0;
7101 /* Ignore reloads that don't reach the end of the insn in
7103 if (all_reaches_end)
7105 /* First, clear out memory of what used to be in this spill reg.
7106 If consecutive registers are used, clear them all. */
7108 for (k = 0; k < nr; k++)
7109 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7111 /* Maybe the spill reg contains a copy of reload_out. */
7113 && (GET_CODE (rld[r].out) == REG
7117 || GET_CODE (rld[r].out_reg) == REG))
7119 rtx out = (GET_CODE (rld[r].out) == REG
7123 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7124 int nregno = REGNO (out);
7125 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7126 : HARD_REGNO_NREGS (nregno,
7127 GET_MODE (rld[r].reg_rtx)));
7129 spill_reg_store[i] = new_spill_reg_store[i];
7130 spill_reg_stored_to[i] = out;
7131 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7133 /* If NREGNO is a hard register, it may occupy more than
7134 one register. If it does, say what is in the
7135 rest of the registers assuming that both registers
7136 agree on how many words the object takes. If not,
7137 invalidate the subsequent registers. */
7139 if (nregno < FIRST_PSEUDO_REGISTER)
7140 for (k = 1; k < nnr; k++)
7141 reg_last_reload_reg[nregno + k]
7143 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7144 REGNO (rld[r].reg_rtx) + k)
7147 /* Now do the inverse operation. */
7148 for (k = 0; k < nr; k++)
7150 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7151 reg_reloaded_contents[i + k]
7152 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7155 reg_reloaded_insn[i + k] = insn;
7156 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7160 /* Maybe the spill reg contains a copy of reload_in. Only do
7161 something if there will not be an output reload for
7162 the register being reloaded. */
7163 else if (rld[r].out_reg == 0
7165 && ((GET_CODE (rld[r].in) == REG
7166 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7167 && ! reg_has_output_reload[REGNO (rld[r].in)])
7168 || (GET_CODE (rld[r].in_reg) == REG
7169 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7170 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7175 if (GET_CODE (rld[r].in) == REG
7176 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7177 nregno = REGNO (rld[r].in);
7178 else if (GET_CODE (rld[r].in_reg) == REG)
7179 nregno = REGNO (rld[r].in_reg);
7181 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7183 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7184 : HARD_REGNO_NREGS (nregno,
7185 GET_MODE (rld[r].reg_rtx)));
7187 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7189 if (nregno < FIRST_PSEUDO_REGISTER)
7190 for (k = 1; k < nnr; k++)
7191 reg_last_reload_reg[nregno + k]
7193 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7194 REGNO (rld[r].reg_rtx) + k)
7197 /* Unless we inherited this reload, show we haven't
7198 recently done a store.
7199 Previous stores of inherited auto_inc expressions
7200 also have to be discarded. */
7201 if (! reload_inherited[r]
7202 || (rld[r].out && ! rld[r].out_reg))
7203 spill_reg_store[i] = 0;
7205 for (k = 0; k < nr; k++)
7207 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7208 reg_reloaded_contents[i + k]
7209 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7212 reg_reloaded_insn[i + k] = insn;
7213 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7218 /* However, if part of the reload reaches the end, then we must
7219 invalidate the old info for the part that survives to the end. */
7220 else if (part_reaches_end)
7222 for (k = 0; k < nr; k++)
7223 if (reload_reg_reaches_end_p (i + k,
7225 rld[r].when_needed))
7226 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7230 /* The following if-statement was #if 0'd in 1.34 (or before...).
7231 It's reenabled in 1.35 because supposedly nothing else
7232 deals with this problem. */
7234 /* If a register gets output-reloaded from a non-spill register,
7235 that invalidates any previous reloaded copy of it.
7236 But forget_old_reloads_1 won't get to see it, because
7237 it thinks only about the original insn. So invalidate it here. */
7238 if (i < 0 && rld[r].out != 0
7239 && (GET_CODE (rld[r].out) == REG
7240 || (GET_CODE (rld[r].out) == MEM
7241 && GET_CODE (rld[r].out_reg) == REG)))
7243 rtx out = (GET_CODE (rld[r].out) == REG
7244 ? rld[r].out : rld[r].out_reg);
7245 int nregno = REGNO (out);
7246 if (nregno >= FIRST_PSEUDO_REGISTER)
7248 rtx src_reg, store_insn = NULL_RTX;
7250 reg_last_reload_reg[nregno] = 0;
7252 /* If we can find a hard register that is stored, record
7253 the storing insn so that we may delete this insn with
7254 delete_output_reload. */
7255 src_reg = rld[r].reg_rtx;
7257 /* If this is an optional reload, try to find the source reg
7258 from an input reload. */
7261 rtx set = single_set (insn);
7262 if (set && SET_DEST (set) == rld[r].out)
7266 src_reg = SET_SRC (set);
7268 for (k = 0; k < n_reloads; k++)
7270 if (rld[k].in == src_reg)
7272 src_reg = rld[k].reg_rtx;
7279 store_insn = new_spill_reg_store[REGNO (src_reg)];
7280 if (src_reg && GET_CODE (src_reg) == REG
7281 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7283 int src_regno = REGNO (src_reg);
7284 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7285 /* The place where to find a death note varies with
7286 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7287 necessarily checked exactly in the code that moves
7288 notes, so just check both locations. */
7289 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7290 if (! note && store_insn)
7291 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7294 spill_reg_store[src_regno + nr] = store_insn;
7295 spill_reg_stored_to[src_regno + nr] = out;
7296 reg_reloaded_contents[src_regno + nr] = nregno;
7297 reg_reloaded_insn[src_regno + nr] = store_insn;
7298 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7299 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7300 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7302 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7304 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7306 reg_last_reload_reg[nregno] = src_reg;
7311 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7313 while (num_regs-- > 0)
7314 reg_last_reload_reg[nregno + num_regs] = 0;
7318 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7321 /* Emit code to perform a reload from IN (which may be a reload register) to
7322 OUT (which may also be a reload register). IN or OUT is from operand
7323 OPNUM with reload type TYPE.
7325 Returns first insn emitted. */
7328 gen_reload (out, in, opnum, type)
7332 enum reload_type type;
7334 rtx last = get_last_insn ();
7337 /* If IN is a paradoxical SUBREG, remove it and try to put the
7338 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7339 if (GET_CODE (in) == SUBREG
7340 && (GET_MODE_SIZE (GET_MODE (in))
7341 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7342 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7343 in = SUBREG_REG (in), out = tem;
7344 else if (GET_CODE (out) == SUBREG
7345 && (GET_MODE_SIZE (GET_MODE (out))
7346 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7347 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7348 out = SUBREG_REG (out), in = tem;
7350 /* How to do this reload can get quite tricky. Normally, we are being
7351 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7352 register that didn't get a hard register. In that case we can just
7353 call emit_move_insn.
7355 We can also be asked to reload a PLUS that adds a register or a MEM to
7356 another register, constant or MEM. This can occur during frame pointer
7357 elimination and while reloading addresses. This case is handled by
7358 trying to emit a single insn to perform the add. If it is not valid,
7359 we use a two insn sequence.
7361 Finally, we could be called to handle an 'o' constraint by putting
7362 an address into a register. In that case, we first try to do this
7363 with a named pattern of "reload_load_address". If no such pattern
7364 exists, we just emit a SET insn and hope for the best (it will normally
7365 be valid on machines that use 'o').
7367 This entire process is made complex because reload will never
7368 process the insns we generate here and so we must ensure that
7369 they will fit their constraints and also by the fact that parts of
7370 IN might be being reloaded separately and replaced with spill registers.
7371 Because of this, we are, in some sense, just guessing the right approach
7372 here. The one listed above seems to work.
7374 ??? At some point, this whole thing needs to be rethought. */
7376 if (GET_CODE (in) == PLUS
7377 && (GET_CODE (XEXP (in, 0)) == REG
7378 || GET_CODE (XEXP (in, 0)) == SUBREG
7379 || GET_CODE (XEXP (in, 0)) == MEM)
7380 && (GET_CODE (XEXP (in, 1)) == REG
7381 || GET_CODE (XEXP (in, 1)) == SUBREG
7382 || CONSTANT_P (XEXP (in, 1))
7383 || GET_CODE (XEXP (in, 1)) == MEM))
7385 /* We need to compute the sum of a register or a MEM and another
7386 register, constant, or MEM, and put it into the reload
7387 register. The best possible way of doing this is if the machine
7388 has a three-operand ADD insn that accepts the required operands.
7390 The simplest approach is to try to generate such an insn and see if it
7391 is recognized and matches its constraints. If so, it can be used.
7393 It might be better not to actually emit the insn unless it is valid,
7394 but we need to pass the insn as an operand to `recog' and
7395 `extract_insn' and it is simpler to emit and then delete the insn if
7396 not valid than to dummy things up. */
7398 rtx op0, op1, tem, insn;
7401 op0 = find_replacement (&XEXP (in, 0));
7402 op1 = find_replacement (&XEXP (in, 1));
7404 /* Since constraint checking is strict, commutativity won't be
7405 checked, so we need to do that here to avoid spurious failure
7406 if the add instruction is two-address and the second operand
7407 of the add is the same as the reload reg, which is frequently
7408 the case. If the insn would be A = B + A, rearrange it so
7409 it will be A = A + B as constrain_operands expects. */
7411 if (GET_CODE (XEXP (in, 1)) == REG
7412 && REGNO (out) == REGNO (XEXP (in, 1)))
7413 tem = op0, op0 = op1, op1 = tem;
7415 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7416 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7418 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7419 code = recog_memoized (insn);
7423 extract_insn (insn);
7424 /* We want constrain operands to treat this insn strictly in
7425 its validity determination, i.e., the way it would after reload
7427 if (constrain_operands (1))
7431 delete_insns_since (last);
7433 /* If that failed, we must use a conservative two-insn sequence.
7435 Use a move to copy one operand into the reload register. Prefer
7436 to reload a constant, MEM or pseudo since the move patterns can
7437 handle an arbitrary operand. If OP1 is not a constant, MEM or
7438 pseudo and OP1 is not a valid operand for an add instruction, then
7441 After reloading one of the operands into the reload register, add
7442 the reload register to the output register.
7444 If there is another way to do this for a specific machine, a
7445 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7448 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7450 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7451 || (GET_CODE (op1) == REG
7452 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7453 || (code != CODE_FOR_nothing
7454 && ! ((*insn_data[code].operand[2].predicate)
7455 (op1, insn_data[code].operand[2].mode))))
7456 tem = op0, op0 = op1, op1 = tem;
7458 gen_reload (out, op0, opnum, type);
7460 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7461 This fixes a problem on the 32K where the stack pointer cannot
7462 be used as an operand of an add insn. */
7464 if (rtx_equal_p (op0, op1))
7467 insn = emit_insn (gen_add2_insn (out, op1));
7469 /* If that failed, copy the address register to the reload register.
7470 Then add the constant to the reload register. */
7472 code = recog_memoized (insn);
7476 extract_insn (insn);
7477 /* We want constrain operands to treat this insn strictly in
7478 its validity determination, i.e., the way it would after reload
7480 if (constrain_operands (1))
7482 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7484 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7489 delete_insns_since (last);
7491 gen_reload (out, op1, opnum, type);
7492 insn = emit_insn (gen_add2_insn (out, op0));
7493 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7496 #ifdef SECONDARY_MEMORY_NEEDED
7497 /* If we need a memory location to do the move, do it that way. */
7498 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7499 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7500 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7501 REGNO_REG_CLASS (REGNO (out)),
7504 /* Get the memory to use and rewrite both registers to its mode. */
7505 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7507 if (GET_MODE (loc) != GET_MODE (out))
7508 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7510 if (GET_MODE (loc) != GET_MODE (in))
7511 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7513 gen_reload (loc, in, opnum, type);
7514 gen_reload (out, loc, opnum, type);
7518 /* If IN is a simple operand, use gen_move_insn. */
7519 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7520 emit_insn (gen_move_insn (out, in));
7522 #ifdef HAVE_reload_load_address
7523 else if (HAVE_reload_load_address)
7524 emit_insn (gen_reload_load_address (out, in));
7527 /* Otherwise, just write (set OUT IN) and hope for the best. */
7529 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7531 /* Return the first insn emitted.
7532 We can not just return get_last_insn, because there may have
7533 been multiple instructions emitted. Also note that gen_move_insn may
7534 emit more than one insn itself, so we can not assume that there is one
7535 insn emitted per emit_insn_before call. */
7537 return last ? NEXT_INSN (last) : get_insns ();
7540 /* Delete a previously made output-reload
7541 whose result we now believe is not needed.
7542 First we double-check.
7544 INSN is the insn now being processed.
7545 LAST_RELOAD_REG is the hard register number for which we want to delete
7546 the last output reload.
7547 J is the reload-number that originally used REG. The caller has made
7548 certain that reload J doesn't use REG any longer for input. */
7551 delete_output_reload (insn, j, last_reload_reg)
7554 int last_reload_reg;
7556 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7557 rtx reg = spill_reg_stored_to[last_reload_reg];
7560 int n_inherited = 0;
7564 /* Get the raw pseudo-register referred to. */
7566 while (GET_CODE (reg) == SUBREG)
7567 reg = SUBREG_REG (reg);
7568 substed = reg_equiv_memory_loc[REGNO (reg)];
7570 /* This is unsafe if the operand occurs more often in the current
7571 insn than it is inherited. */
7572 for (k = n_reloads - 1; k >= 0; k--)
7574 rtx reg2 = rld[k].in;
7577 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7578 reg2 = rld[k].in_reg;
7580 if (rld[k].out && ! rld[k].out_reg)
7581 reg2 = XEXP (rld[k].in_reg, 0);
7583 while (GET_CODE (reg2) == SUBREG)
7584 reg2 = SUBREG_REG (reg2);
7585 if (rtx_equal_p (reg2, reg))
7587 if (reload_inherited[k] || reload_override_in[k] || k == j)
7590 reg2 = rld[k].out_reg;
7593 while (GET_CODE (reg2) == SUBREG)
7594 reg2 = XEXP (reg2, 0);
7595 if (rtx_equal_p (reg2, reg))
7602 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7604 n_occurrences += count_occurrences (PATTERN (insn),
7605 eliminate_regs (substed, 0,
7607 if (n_occurrences > n_inherited)
7610 /* If the pseudo-reg we are reloading is no longer referenced
7611 anywhere between the store into it and here,
7612 and no jumps or labels intervene, then the value can get
7613 here through the reload reg alone.
7614 Otherwise, give up--return. */
7615 for (i1 = NEXT_INSN (output_reload_insn);
7616 i1 != insn; i1 = NEXT_INSN (i1))
7618 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7620 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7621 && reg_mentioned_p (reg, PATTERN (i1)))
7623 /* If this is USE in front of INSN, we only have to check that
7624 there are no more references than accounted for by inheritance. */
7625 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7627 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7628 i1 = NEXT_INSN (i1);
7630 if (n_occurrences <= n_inherited && i1 == insn)
7636 /* The caller has already checked that REG dies or is set in INSN.
7637 It has also checked that we are optimizing, and thus some inaccurancies
7638 in the debugging information are acceptable.
7639 So we could just delete output_reload_insn.
7640 But in some cases we can improve the debugging information without
7641 sacrificing optimization - maybe even improving the code:
7642 See if the pseudo reg has been completely replaced
7643 with reload regs. If so, delete the store insn
7644 and forget we had a stack slot for the pseudo. */
7645 if (rld[j].out != rld[j].in
7646 && REG_N_DEATHS (REGNO (reg)) == 1
7647 && REG_N_SETS (REGNO (reg)) == 1
7648 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7649 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7653 /* We know that it was used only between here
7654 and the beginning of the current basic block.
7655 (We also know that the last use before INSN was
7656 the output reload we are thinking of deleting, but never mind that.)
7657 Search that range; see if any ref remains. */
7658 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7660 rtx set = single_set (i2);
7662 /* Uses which just store in the pseudo don't count,
7663 since if they are the only uses, they are dead. */
7664 if (set != 0 && SET_DEST (set) == reg)
7666 if (GET_CODE (i2) == CODE_LABEL
7667 || GET_CODE (i2) == JUMP_INSN)
7669 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7670 && reg_mentioned_p (reg, PATTERN (i2)))
7672 /* Some other ref remains; just delete the output reload we
7674 delete_address_reloads (output_reload_insn, insn);
7675 delete_insn (output_reload_insn);
7680 /* Delete the now-dead stores into this pseudo. */
7681 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7683 rtx set = single_set (i2);
7685 if (set != 0 && SET_DEST (set) == reg)
7687 delete_address_reloads (i2, insn);
7688 /* This might be a basic block head,
7689 thus don't use delete_insn. */
7692 if (GET_CODE (i2) == CODE_LABEL
7693 || GET_CODE (i2) == JUMP_INSN)
7697 /* For the debugging info,
7698 say the pseudo lives in this reload reg. */
7699 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7700 alter_reg (REGNO (reg), -1);
7702 delete_address_reloads (output_reload_insn, insn);
7703 delete_insn (output_reload_insn);
7707 /* We are going to delete DEAD_INSN. Recursively delete loads of
7708 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7709 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7711 delete_address_reloads (dead_insn, current_insn)
7712 rtx dead_insn, current_insn;
7714 rtx set = single_set (dead_insn);
7715 rtx set2, dst, prev, next;
7718 rtx dst = SET_DEST (set);
7719 if (GET_CODE (dst) == MEM)
7720 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7722 /* If we deleted the store from a reloaded post_{in,de}c expression,
7723 we can delete the matching adds. */
7724 prev = PREV_INSN (dead_insn);
7725 next = NEXT_INSN (dead_insn);
7726 if (! prev || ! next)
7728 set = single_set (next);
7729 set2 = single_set (prev);
7731 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7732 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7733 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7735 dst = SET_DEST (set);
7736 if (! rtx_equal_p (dst, SET_DEST (set2))
7737 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7738 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7739 || (INTVAL (XEXP (SET_SRC (set), 1))
7740 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7742 delete_related_insns (prev);
7743 delete_related_insns (next);
7746 /* Subfunction of delete_address_reloads: process registers found in X. */
7748 delete_address_reloads_1 (dead_insn, x, current_insn)
7749 rtx dead_insn, x, current_insn;
7751 rtx prev, set, dst, i2;
7753 enum rtx_code code = GET_CODE (x);
7757 const char *fmt = GET_RTX_FORMAT (code);
7758 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7761 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7762 else if (fmt[i] == 'E')
7764 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7765 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7772 if (spill_reg_order[REGNO (x)] < 0)
7775 /* Scan backwards for the insn that sets x. This might be a way back due
7777 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7779 code = GET_CODE (prev);
7780 if (code == CODE_LABEL || code == JUMP_INSN)
7782 if (GET_RTX_CLASS (code) != 'i')
7784 if (reg_set_p (x, PATTERN (prev)))
7786 if (reg_referenced_p (x, PATTERN (prev)))
7789 if (! prev || INSN_UID (prev) < reload_first_uid)
7791 /* Check that PREV only sets the reload register. */
7792 set = single_set (prev);
7795 dst = SET_DEST (set);
7796 if (GET_CODE (dst) != REG
7797 || ! rtx_equal_p (dst, x))
7799 if (! reg_set_p (dst, PATTERN (dead_insn)))
7801 /* Check if DST was used in a later insn -
7802 it might have been inherited. */
7803 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7805 if (GET_CODE (i2) == CODE_LABEL)
7809 if (reg_referenced_p (dst, PATTERN (i2)))
7811 /* If there is a reference to the register in the current insn,
7812 it might be loaded in a non-inherited reload. If no other
7813 reload uses it, that means the register is set before
7815 if (i2 == current_insn)
7817 for (j = n_reloads - 1; j >= 0; j--)
7818 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7819 || reload_override_in[j] == dst)
7821 for (j = n_reloads - 1; j >= 0; j--)
7822 if (rld[j].in && rld[j].reg_rtx == dst)
7829 if (GET_CODE (i2) == JUMP_INSN)
7831 /* If DST is still live at CURRENT_INSN, check if it is used for
7832 any reload. Note that even if CURRENT_INSN sets DST, we still
7833 have to check the reloads. */
7834 if (i2 == current_insn)
7836 for (j = n_reloads - 1; j >= 0; j--)
7837 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7838 || reload_override_in[j] == dst)
7840 /* ??? We can't finish the loop here, because dst might be
7841 allocated to a pseudo in this block if no reload in this
7842 block needs any of the clsses containing DST - see
7843 spill_hard_reg. There is no easy way to tell this, so we
7844 have to scan till the end of the basic block. */
7846 if (reg_set_p (dst, PATTERN (i2)))
7850 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7851 reg_reloaded_contents[REGNO (dst)] = -1;
7855 /* Output reload-insns to reload VALUE into RELOADREG.
7856 VALUE is an autoincrement or autodecrement RTX whose operand
7857 is a register or memory location;
7858 so reloading involves incrementing that location.
7859 IN is either identical to VALUE, or some cheaper place to reload from.
7861 INC_AMOUNT is the number to increment or decrement by (always positive).
7862 This cannot be deduced from VALUE.
7864 Return the instruction that stores into RELOADREG. */
7867 inc_for_reload (reloadreg, in, value, inc_amount)
7872 /* REG or MEM to be copied and incremented. */
7873 rtx incloc = XEXP (value, 0);
7874 /* Nonzero if increment after copying. */
7875 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7881 rtx real_in = in == value ? XEXP (in, 0) : in;
7883 /* No hard register is equivalent to this register after
7884 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7885 we could inc/dec that register as well (maybe even using it for
7886 the source), but I'm not sure it's worth worrying about. */
7887 if (GET_CODE (incloc) == REG)
7888 reg_last_reload_reg[REGNO (incloc)] = 0;
7890 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7891 inc_amount = -inc_amount;
7893 inc = GEN_INT (inc_amount);
7895 /* If this is post-increment, first copy the location to the reload reg. */
7896 if (post && real_in != reloadreg)
7897 emit_insn (gen_move_insn (reloadreg, real_in));
7901 /* See if we can directly increment INCLOC. Use a method similar to
7902 that in gen_reload. */
7904 last = get_last_insn ();
7905 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7906 gen_rtx_PLUS (GET_MODE (incloc),
7909 code = recog_memoized (add_insn);
7912 extract_insn (add_insn);
7913 if (constrain_operands (1))
7915 /* If this is a pre-increment and we have incremented the value
7916 where it lives, copy the incremented value to RELOADREG to
7917 be used as an address. */
7920 emit_insn (gen_move_insn (reloadreg, incloc));
7925 delete_insns_since (last);
7928 /* If couldn't do the increment directly, must increment in RELOADREG.
7929 The way we do this depends on whether this is pre- or post-increment.
7930 For pre-increment, copy INCLOC to the reload register, increment it
7931 there, then save back. */
7935 if (in != reloadreg)
7936 emit_insn (gen_move_insn (reloadreg, real_in));
7937 emit_insn (gen_add2_insn (reloadreg, inc));
7938 store = emit_insn (gen_move_insn (incloc, reloadreg));
7943 Because this might be a jump insn or a compare, and because RELOADREG
7944 may not be available after the insn in an input reload, we must do
7945 the incrementation before the insn being reloaded for.
7947 We have already copied IN to RELOADREG. Increment the copy in
7948 RELOADREG, save that back, then decrement RELOADREG so it has
7949 the original value. */
7951 emit_insn (gen_add2_insn (reloadreg, inc));
7952 store = emit_insn (gen_move_insn (incloc, reloadreg));
7953 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7959 /* Return 1 if we are certain that the constraint-string STRING allows
7960 the hard register REG. Return 0 if we can't be sure of this. */
7963 constraint_accepts_reg_p (string, reg)
7968 int regno = true_regnum (reg);
7971 /* Initialize for first alternative. */
7973 /* Check that each alternative contains `g' or `r'. */
7975 switch (c = *string++)
7978 /* If an alternative lacks `g' or `r', we lose. */
7981 /* If an alternative lacks `g' or `r', we lose. */
7984 /* Initialize for next alternative. */
7989 /* Any general reg wins for this alternative. */
7990 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7994 /* Any reg in specified class wins for this alternative. */
7996 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7998 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8004 /* INSN is a no-op; delete it.
8005 If this sets the return value of the function, we must keep a USE around,
8006 in case this is in a different basic block than the final USE. Otherwise,
8007 we could loose important register lifeness information on
8008 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8009 spills: subsequent passes assume that spill registers are dead at the end
8011 VALUE must be the return value in such a case, NULL otherwise. */
8013 reload_cse_delete_noop_set (insn, value)
8018 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8019 INSN_CODE (insn) = -1;
8020 REG_NOTES (insn) = NULL_RTX;
8026 /* See whether a single set SET is a noop. */
8028 reload_cse_noop_set_p (set)
8031 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8034 /* Try to simplify INSN. */
8036 reload_cse_simplify (insn)
8039 rtx body = PATTERN (insn);
8041 if (GET_CODE (body) == SET)
8045 /* Simplify even if we may think it is a no-op.
8046 We may think a memory load of a value smaller than WORD_SIZE
8047 is redundant because we haven't taken into account possible
8048 implicit extension. reload_cse_simplify_set() will bring
8049 this out, so it's safer to simplify before we delete. */
8050 count += reload_cse_simplify_set (body, insn);
8052 if (!count && reload_cse_noop_set_p (body))
8054 rtx value = SET_DEST (body);
8055 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8057 reload_cse_delete_noop_set (insn, value);
8062 apply_change_group ();
8064 reload_cse_simplify_operands (insn);
8066 else if (GET_CODE (body) == PARALLEL)
8070 rtx value = NULL_RTX;
8072 /* If every action in a PARALLEL is a noop, we can delete
8073 the entire PARALLEL. */
8074 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8076 rtx part = XVECEXP (body, 0, i);
8077 if (GET_CODE (part) == SET)
8079 if (! reload_cse_noop_set_p (part))
8081 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8085 value = SET_DEST (part);
8088 else if (GET_CODE (part) != CLOBBER)
8094 reload_cse_delete_noop_set (insn, value);
8095 /* We're done with this insn. */
8099 /* It's not a no-op, but we can try to simplify it. */
8100 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8101 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8102 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8105 apply_change_group ();
8107 reload_cse_simplify_operands (insn);
8111 /* Do a very simple CSE pass over the hard registers.
8113 This function detects no-op moves where we happened to assign two
8114 different pseudo-registers to the same hard register, and then
8115 copied one to the other. Reload will generate a useless
8116 instruction copying a register to itself.
8118 This function also detects cases where we load a value from memory
8119 into two different registers, and (if memory is more expensive than
8120 registers) changes it to simply copy the first register into the
8123 Another optimization is performed that scans the operands of each
8124 instruction to see whether the value is already available in a
8125 hard register. It then replaces the operand with the hard register
8126 if possible, much like an optional reload would. */
8129 reload_cse_regs_1 (first)
8135 init_alias_analysis ();
8137 for (insn = first; insn; insn = NEXT_INSN (insn))
8140 reload_cse_simplify (insn);
8142 cselib_process_insn (insn);
8146 end_alias_analysis ();
8150 /* Call cse / combine like post-reload optimization phases.
8151 FIRST is the first instruction. */
8153 reload_cse_regs (first)
8156 reload_cse_regs_1 (first);
8158 reload_cse_move2add (first);
8159 if (flag_expensive_optimizations)
8160 reload_cse_regs_1 (first);
8163 /* Try to simplify a single SET instruction. SET is the set pattern.
8164 INSN is the instruction it came from.
8165 This function only handles one case: if we set a register to a value
8166 which is not a register, we try to find that value in some other register
8167 and change the set into a register copy. */
8170 reload_cse_simplify_set (set, insn)
8177 enum reg_class dclass;
8180 struct elt_loc_list *l;
8181 #ifdef LOAD_EXTEND_OP
8182 enum rtx_code extend_op = NIL;
8185 dreg = true_regnum (SET_DEST (set));
8189 src = SET_SRC (set);
8190 if (side_effects_p (src) || true_regnum (src) >= 0)
8193 dclass = REGNO_REG_CLASS (dreg);
8195 #ifdef LOAD_EXTEND_OP
8196 /* When replacing a memory with a register, we need to honor assumptions
8197 that combine made wrt the contents of sign bits. We'll do this by
8198 generating an extend instruction instead of a reg->reg copy. Thus
8199 the destination must be a register that we can widen. */
8200 if (GET_CODE (src) == MEM
8201 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8202 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8203 && GET_CODE (SET_DEST (set)) != REG)
8207 /* If memory loads are cheaper than register copies, don't change them. */
8208 if (GET_CODE (src) == MEM)
8209 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8210 else if (CONSTANT_P (src))
8211 old_cost = rtx_cost (src, SET);
8212 else if (GET_CODE (src) == REG)
8213 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8214 REGNO_REG_CLASS (REGNO (src)), dclass);
8217 old_cost = rtx_cost (src, SET);
8219 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8222 for (l = val->locs; l; l = l->next)
8224 rtx this_rtx = l->loc;
8227 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8229 #ifdef LOAD_EXTEND_OP
8230 if (extend_op != NIL)
8232 HOST_WIDE_INT this_val;
8234 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8235 constants, such as SYMBOL_REF, cannot be extended. */
8236 if (GET_CODE (this_rtx) != CONST_INT)
8239 this_val = INTVAL (this_rtx);
8243 this_val &= GET_MODE_MASK (GET_MODE (src));
8246 /* ??? In theory we're already extended. */
8247 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8252 this_rtx = GEN_INT (this_val);
8255 this_cost = rtx_cost (this_rtx, SET);
8257 else if (GET_CODE (this_rtx) == REG)
8259 #ifdef LOAD_EXTEND_OP
8260 if (extend_op != NIL)
8262 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8263 this_cost = rtx_cost (this_rtx, SET);
8267 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8268 REGNO_REG_CLASS (REGNO (this_rtx)),
8274 /* If equal costs, prefer registers over anything else. That
8275 tends to lead to smaller instructions on some machines. */
8276 if (this_cost < old_cost
8277 || (this_cost == old_cost
8278 && GET_CODE (this_rtx) == REG
8279 && GET_CODE (SET_SRC (set)) != REG))
8281 #ifdef LOAD_EXTEND_OP
8282 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8283 && extend_op != NIL)
8285 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8286 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8287 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8291 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8292 old_cost = this_cost, did_change = 1;
8299 /* Try to replace operands in INSN with equivalent values that are already
8300 in registers. This can be viewed as optional reloading.
8302 For each non-register operand in the insn, see if any hard regs are
8303 known to be equivalent to that operand. Record the alternatives which
8304 can accept these hard registers. Among all alternatives, select the
8305 ones which are better or equal to the one currently matching, where
8306 "better" is in terms of '?' and '!' constraints. Among the remaining
8307 alternatives, select the one which replaces most operands with
8311 reload_cse_simplify_operands (insn)
8316 /* For each operand, all registers that are equivalent to it. */
8317 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8319 const char *constraints[MAX_RECOG_OPERANDS];
8321 /* Vector recording how bad an alternative is. */
8322 int *alternative_reject;
8323 /* Vector recording how many registers can be introduced by choosing
8324 this alternative. */
8325 int *alternative_nregs;
8326 /* Array of vectors recording, for each operand and each alternative,
8327 which hard register to substitute, or -1 if the operand should be
8329 int *op_alt_regno[MAX_RECOG_OPERANDS];
8330 /* Array of alternatives, sorted in order of decreasing desirability. */
8331 int *alternative_order;
8332 rtx reg = gen_rtx_REG (VOIDmode, -1);
8334 extract_insn (insn);
8336 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8339 /* Figure out which alternative currently matches. */
8340 if (! constrain_operands (1))
8341 fatal_insn_not_found (insn);
8343 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8344 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8345 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8346 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8347 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8349 /* For each operand, find out which regs are equivalent. */
8350 for (i = 0; i < recog_data.n_operands; i++)
8353 struct elt_loc_list *l;
8355 CLEAR_HARD_REG_SET (equiv_regs[i]);
8357 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8358 right, so avoid the problem here. Likewise if we have a constant
8359 and the insn pattern doesn't tell us the mode we need. */
8360 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8361 || (CONSTANT_P (recog_data.operand[i])
8362 && recog_data.operand_mode[i] == VOIDmode))
8365 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8369 for (l = v->locs; l; l = l->next)
8370 if (GET_CODE (l->loc) == REG)
8371 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8374 for (i = 0; i < recog_data.n_operands; i++)
8376 enum machine_mode mode;
8380 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8381 for (j = 0; j < recog_data.n_alternatives; j++)
8382 op_alt_regno[i][j] = -1;
8384 p = constraints[i] = recog_data.constraints[i];
8385 mode = recog_data.operand_mode[i];
8387 /* Add the reject values for each alternative given by the constraints
8388 for this operand. */
8396 alternative_reject[j] += 3;
8398 alternative_reject[j] += 300;
8401 /* We won't change operands which are already registers. We
8402 also don't want to modify output operands. */
8403 regno = true_regnum (recog_data.operand[i]);
8405 || constraints[i][0] == '='
8406 || constraints[i][0] == '+')
8409 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8411 int class = (int) NO_REGS;
8413 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8416 REGNO (reg) = regno;
8417 PUT_MODE (reg, mode);
8419 /* We found a register equal to this operand. Now look for all
8420 alternatives that can accept this register and have not been
8421 assigned a register they can use yet. */
8430 case '=': case '+': case '?':
8431 case '#': case '&': case '!':
8433 case '0': case '1': case '2': case '3': case '4':
8434 case '5': case '6': case '7': case '8': case '9':
8435 case 'm': case '<': case '>': case 'V': case 'o':
8436 case 'E': case 'F': case 'G': case 'H':
8437 case 's': case 'i': case 'n':
8438 case 'I': case 'J': case 'K': case 'L':
8439 case 'M': case 'N': case 'O': case 'P':
8441 /* These don't say anything we care about. */
8445 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8450 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8453 case ',': case '\0':
8454 /* See if REGNO fits this alternative, and set it up as the
8455 replacement register if we don't have one for this
8456 alternative yet and the operand being replaced is not
8457 a cheap CONST_INT. */
8458 if (op_alt_regno[i][j] == -1
8459 && reg_fits_class_p (reg, class, 0, mode)
8460 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8461 || (rtx_cost (recog_data.operand[i], SET)
8462 > rtx_cost (reg, SET))))
8464 alternative_nregs[j]++;
8465 op_alt_regno[i][j] = regno;
8477 /* Record all alternatives which are better or equal to the currently
8478 matching one in the alternative_order array. */
8479 for (i = j = 0; i < recog_data.n_alternatives; i++)
8480 if (alternative_reject[i] <= alternative_reject[which_alternative])
8481 alternative_order[j++] = i;
8482 recog_data.n_alternatives = j;
8484 /* Sort it. Given a small number of alternatives, a dumb algorithm
8485 won't hurt too much. */
8486 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8489 int best_reject = alternative_reject[alternative_order[i]];
8490 int best_nregs = alternative_nregs[alternative_order[i]];
8493 for (j = i + 1; j < recog_data.n_alternatives; j++)
8495 int this_reject = alternative_reject[alternative_order[j]];
8496 int this_nregs = alternative_nregs[alternative_order[j]];
8498 if (this_reject < best_reject
8499 || (this_reject == best_reject && this_nregs < best_nregs))
8502 best_reject = this_reject;
8503 best_nregs = this_nregs;
8507 tmp = alternative_order[best];
8508 alternative_order[best] = alternative_order[i];
8509 alternative_order[i] = tmp;
8512 /* Substitute the operands as determined by op_alt_regno for the best
8514 j = alternative_order[0];
8516 for (i = 0; i < recog_data.n_operands; i++)
8518 enum machine_mode mode = recog_data.operand_mode[i];
8519 if (op_alt_regno[i][j] == -1)
8522 validate_change (insn, recog_data.operand_loc[i],
8523 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8526 for (i = recog_data.n_dups - 1; i >= 0; i--)
8528 int op = recog_data.dup_num[i];
8529 enum machine_mode mode = recog_data.operand_mode[op];
8531 if (op_alt_regno[op][j] == -1)
8534 validate_change (insn, recog_data.dup_loc[i],
8535 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8538 return apply_change_group ();
8541 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8543 This code might also be useful when reload gave up on reg+reg addresssing
8544 because of clashes between the return register and INDEX_REG_CLASS. */
8546 /* The maximum number of uses of a register we can keep track of to
8547 replace them with reg+reg addressing. */
8548 #define RELOAD_COMBINE_MAX_USES 6
8550 /* INSN is the insn where a register has ben used, and USEP points to the
8551 location of the register within the rtl. */
8552 struct reg_use { rtx insn, *usep; };
8554 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8555 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8556 indicates where it becomes live again.
8557 Otherwise, USE_INDEX is the index of the last encountered use of the
8558 register (which is first among these we have seen since we scan backwards),
8559 OFFSET contains the constant offset that is added to the register in
8560 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8561 last, of these uses.
8562 STORE_RUID is always meaningful if we only want to use a value in a
8563 register in a different place: it denotes the next insn in the insn
8564 stream (i.e. the last ecountered) that sets or clobbers the register. */
8567 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8572 } reg_state[FIRST_PSEUDO_REGISTER];
8574 /* Reverse linear uid. This is increased in reload_combine while scanning
8575 the instructions from last to first. It is used to set last_label_ruid
8576 and the store_ruid / use_ruid fields in reg_state. */
8577 static int reload_combine_ruid;
8579 #define LABEL_LIVE(LABEL) \
8580 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8586 int first_index_reg = -1;
8587 int last_index_reg = 0;
8590 int last_label_ruid;
8591 int min_labelno, n_labels;
8592 HARD_REG_SET ever_live_at_start, *label_live;
8594 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8595 reload has already used it where appropriate, so there is no use in
8596 trying to generate it now. */
8597 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8600 /* To avoid wasting too much time later searching for an index register,
8601 determine the minimum and maximum index register numbers. */
8602 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8603 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8605 if (first_index_reg == -1)
8606 first_index_reg = r;
8611 /* If no index register is available, we can quit now. */
8612 if (first_index_reg == -1)
8615 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8616 information is a bit fuzzy immediately after reload, but it's
8617 still good enough to determine which registers are live at a jump
8619 min_labelno = get_first_label_num ();
8620 n_labels = max_label_num () - min_labelno;
8621 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8622 CLEAR_HARD_REG_SET (ever_live_at_start);
8624 for (i = n_basic_blocks - 1; i >= 0; i--)
8626 insn = BLOCK_HEAD (i);
8627 if (GET_CODE (insn) == CODE_LABEL)
8631 REG_SET_TO_HARD_REG_SET (live,
8632 BASIC_BLOCK (i)->global_live_at_start);
8633 compute_use_by_pseudos (&live,
8634 BASIC_BLOCK (i)->global_live_at_start);
8635 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8636 IOR_HARD_REG_SET (ever_live_at_start, live);
8640 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8641 last_label_ruid = reload_combine_ruid = 0;
8642 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8644 reg_state[r].store_ruid = reload_combine_ruid;
8646 reg_state[r].use_index = -1;
8648 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8651 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8655 /* We cannot do our optimization across labels. Invalidating all the use
8656 information we have would be costly, so we just note where the label
8657 is and then later disable any optimization that would cross it. */
8658 if (GET_CODE (insn) == CODE_LABEL)
8659 last_label_ruid = reload_combine_ruid;
8660 else if (GET_CODE (insn) == BARRIER)
8661 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8662 if (! fixed_regs[r])
8663 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8665 if (! INSN_P (insn))
8668 reload_combine_ruid++;
8670 /* Look for (set (REGX) (CONST_INT))
8671 (set (REGX) (PLUS (REGX) (REGY)))
8673 ... (MEM (REGX)) ...
8675 (set (REGZ) (CONST_INT))
8677 ... (MEM (PLUS (REGZ) (REGY)))... .
8679 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8680 and that we know all uses of REGX before it dies. */
8681 set = single_set (insn);
8683 && GET_CODE (SET_DEST (set)) == REG
8684 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8685 GET_MODE (SET_DEST (set)))
8687 && GET_CODE (SET_SRC (set)) == PLUS
8688 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8689 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8690 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8692 rtx reg = SET_DEST (set);
8693 rtx plus = SET_SRC (set);
8694 rtx base = XEXP (plus, 1);
8695 rtx prev = prev_nonnote_insn (insn);
8696 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8697 unsigned int regno = REGNO (reg);
8698 rtx const_reg = NULL_RTX;
8699 rtx reg_sum = NULL_RTX;
8701 /* Now, we need an index register.
8702 We'll set index_reg to this index register, const_reg to the
8703 register that is to be loaded with the constant
8704 (denoted as REGZ in the substitution illustration above),
8705 and reg_sum to the register-register that we want to use to
8706 substitute uses of REG (typically in MEMs) with.
8707 First check REG and BASE for being index registers;
8708 we can use them even if they are not dead. */
8709 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8710 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8718 /* Otherwise, look for a free index register. Since we have
8719 checked above that neiter REG nor BASE are index registers,
8720 if we find anything at all, it will be different from these
8722 for (i = first_index_reg; i <= last_index_reg; i++)
8724 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8726 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8727 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8728 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8730 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8732 const_reg = index_reg;
8733 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8739 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8740 (REGY), i.e. BASE, is not clobbered before the last use we'll
8743 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8744 && rtx_equal_p (SET_DEST (prev_set), reg)
8745 && reg_state[regno].use_index >= 0
8746 && (reg_state[REGNO (base)].store_ruid
8747 <= reg_state[regno].use_ruid)
8752 /* Change destination register and, if necessary, the
8753 constant value in PREV, the constant loading instruction. */
8754 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8755 if (reg_state[regno].offset != const0_rtx)
8756 validate_change (prev,
8757 &SET_SRC (prev_set),
8758 GEN_INT (INTVAL (SET_SRC (prev_set))
8759 + INTVAL (reg_state[regno].offset)),
8762 /* Now for every use of REG that we have recorded, replace REG
8764 for (i = reg_state[regno].use_index;
8765 i < RELOAD_COMBINE_MAX_USES; i++)
8766 validate_change (reg_state[regno].reg_use[i].insn,
8767 reg_state[regno].reg_use[i].usep,
8770 if (apply_change_group ())
8774 /* Delete the reg-reg addition. */
8777 if (reg_state[regno].offset != const0_rtx)
8778 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8780 for (np = ®_NOTES (prev); *np;)
8782 if (REG_NOTE_KIND (*np) == REG_EQUAL
8783 || REG_NOTE_KIND (*np) == REG_EQUIV)
8784 *np = XEXP (*np, 1);
8786 np = &XEXP (*np, 1);
8789 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8790 reg_state[REGNO (const_reg)].store_ruid
8791 = reload_combine_ruid;
8797 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8799 if (GET_CODE (insn) == CALL_INSN)
8803 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8804 if (call_used_regs[r])
8806 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8807 reg_state[r].store_ruid = reload_combine_ruid;
8810 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8811 link = XEXP (link, 1))
8813 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8814 if (GET_CODE (usage_rtx) == REG)
8817 unsigned int start_reg = REGNO (usage_rtx);
8818 unsigned int num_regs =
8819 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8820 unsigned int end_reg = start_reg + num_regs - 1;
8821 for (i = start_reg; i <= end_reg; i++)
8822 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8824 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8825 reg_state[i].store_ruid = reload_combine_ruid;
8828 reg_state[i].use_index = -1;
8833 else if (GET_CODE (insn) == JUMP_INSN
8834 && GET_CODE (PATTERN (insn)) != RETURN)
8836 /* Non-spill registers might be used at the call destination in
8837 some unknown fashion, so we have to mark the unknown use. */
8840 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8841 && JUMP_LABEL (insn))
8842 live = &LABEL_LIVE (JUMP_LABEL (insn));
8844 live = &ever_live_at_start;
8846 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8847 if (TEST_HARD_REG_BIT (*live, i))
8848 reg_state[i].use_index = -1;
8851 reload_combine_note_use (&PATTERN (insn), insn);
8852 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8854 if (REG_NOTE_KIND (note) == REG_INC
8855 && GET_CODE (XEXP (note, 0)) == REG)
8857 int regno = REGNO (XEXP (note, 0));
8859 reg_state[regno].store_ruid = reload_combine_ruid;
8860 reg_state[regno].use_index = -1;
8868 /* Check if DST is a register or a subreg of a register; if it is,
8869 update reg_state[regno].store_ruid and reg_state[regno].use_index
8870 accordingly. Called via note_stores from reload_combine. */
8873 reload_combine_note_store (dst, set, data)
8875 void *data ATTRIBUTE_UNUSED;
8879 enum machine_mode mode = GET_MODE (dst);
8881 if (GET_CODE (dst) == SUBREG)
8883 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8884 GET_MODE (SUBREG_REG (dst)),
8887 dst = SUBREG_REG (dst);
8889 if (GET_CODE (dst) != REG)
8891 regno += REGNO (dst);
8893 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8894 careful with registers / register parts that are not full words.
8896 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8897 if (GET_CODE (set) != SET
8898 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8899 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8900 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8902 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8904 reg_state[i].use_index = -1;
8905 reg_state[i].store_ruid = reload_combine_ruid;
8910 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8912 reg_state[i].store_ruid = reload_combine_ruid;
8913 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8918 /* XP points to a piece of rtl that has to be checked for any uses of
8920 *XP is the pattern of INSN, or a part of it.
8921 Called from reload_combine, and recursively by itself. */
8923 reload_combine_note_use (xp, insn)
8927 enum rtx_code code = x->code;
8930 rtx offset = const0_rtx; /* For the REG case below. */
8935 if (GET_CODE (SET_DEST (x)) == REG)
8937 reload_combine_note_use (&SET_SRC (x), insn);
8943 /* If this is the USE of a return value, we can't change it. */
8944 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8946 /* Mark the return register as used in an unknown fashion. */
8947 rtx reg = XEXP (x, 0);
8948 int regno = REGNO (reg);
8949 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8951 while (--nregs >= 0)
8952 reg_state[regno + nregs].use_index = -1;
8958 if (GET_CODE (SET_DEST (x)) == REG)
8960 /* No spurious CLOBBERs of pseudo registers may remain. */
8961 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8968 /* We are interested in (plus (reg) (const_int)) . */
8969 if (GET_CODE (XEXP (x, 0)) != REG
8970 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8972 offset = XEXP (x, 1);
8977 int regno = REGNO (x);
8981 /* No spurious USEs of pseudo registers may remain. */
8982 if (regno >= FIRST_PSEUDO_REGISTER)
8985 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8987 /* We can't substitute into multi-hard-reg uses. */
8990 while (--nregs >= 0)
8991 reg_state[regno + nregs].use_index = -1;
8995 /* If this register is already used in some unknown fashion, we
8997 If we decrement the index from zero to -1, we can't store more
8998 uses, so this register becomes used in an unknown fashion. */
8999 use_index = --reg_state[regno].use_index;
9003 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9005 /* We have found another use for a register that is already
9006 used later. Check if the offsets match; if not, mark the
9007 register as used in an unknown fashion. */
9008 if (! rtx_equal_p (offset, reg_state[regno].offset))
9010 reg_state[regno].use_index = -1;
9016 /* This is the first use of this register we have seen since we
9017 marked it as dead. */
9018 reg_state[regno].offset = offset;
9019 reg_state[regno].use_ruid = reload_combine_ruid;
9021 reg_state[regno].reg_use[use_index].insn = insn;
9022 reg_state[regno].reg_use[use_index].usep = xp;
9030 /* Recursively process the components of X. */
9031 fmt = GET_RTX_FORMAT (code);
9032 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9035 reload_combine_note_use (&XEXP (x, i), insn);
9036 else if (fmt[i] == 'E')
9038 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9039 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9044 /* See if we can reduce the cost of a constant by replacing a move
9045 with an add. We track situations in which a register is set to a
9046 constant or to a register plus a constant. */
9047 /* We cannot do our optimization across labels. Invalidating all the
9048 information about register contents we have would be costly, so we
9049 use move2add_last_label_luid to note where the label is and then
9050 later disable any optimization that would cross it.
9051 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9052 reg_set_luid[n] is greater than last_label_luid[n] . */
9053 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9055 /* If reg_base_reg[n] is negative, register n has been set to
9056 reg_offset[n] in mode reg_mode[n] .
9057 If reg_base_reg[n] is non-negative, register n has been set to the
9058 sum of reg_offset[n] and the value of register reg_base_reg[n]
9059 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9060 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9061 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9062 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9064 /* move2add_luid is linearily increased while scanning the instructions
9065 from first to last. It is used to set reg_set_luid in
9066 reload_cse_move2add and move2add_note_store. */
9067 static int move2add_luid;
9069 /* move2add_last_label_luid is set whenever a label is found. Labels
9070 invalidate all previously collected reg_offset data. */
9071 static int move2add_last_label_luid;
9073 /* Generate a CONST_INT and force it in the range of MODE. */
9075 static HOST_WIDE_INT
9076 sext_for_mode (mode, value)
9077 enum machine_mode mode;
9078 HOST_WIDE_INT value;
9080 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9081 int width = GET_MODE_BITSIZE (mode);
9083 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9085 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9086 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9087 cval |= (HOST_WIDE_INT) -1 << width;
9092 /* ??? We don't know how zero / sign extension is handled, hence we
9093 can't go from a narrower to a wider mode. */
9094 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9095 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9096 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9097 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9098 GET_MODE_BITSIZE (INMODE))))
9101 reload_cse_move2add (first)
9107 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9108 reg_set_luid[i] = 0;
9110 move2add_last_label_luid = 0;
9112 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9116 if (GET_CODE (insn) == CODE_LABEL)
9118 move2add_last_label_luid = move2add_luid;
9119 /* We're going to increment move2add_luid twice after a
9120 label, so that we can use move2add_last_label_luid + 1 as
9121 the luid for constants. */
9125 if (! INSN_P (insn))
9127 pat = PATTERN (insn);
9128 /* For simplicity, we only perform this optimization on
9129 straightforward SETs. */
9130 if (GET_CODE (pat) == SET
9131 && GET_CODE (SET_DEST (pat)) == REG)
9133 rtx reg = SET_DEST (pat);
9134 int regno = REGNO (reg);
9135 rtx src = SET_SRC (pat);
9137 /* Check if we have valid information on the contents of this
9138 register in the mode of REG. */
9139 if (reg_set_luid[regno] > move2add_last_label_luid
9140 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9142 /* Try to transform (set (REGX) (CONST_INT A))
9144 (set (REGX) (CONST_INT B))
9146 (set (REGX) (CONST_INT A))
9148 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9150 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9153 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9155 - reg_offset[regno]));
9156 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9157 use (set (reg) (reg)) instead.
9158 We don't delete this insn, nor do we convert it into a
9159 note, to avoid losing register notes or the return
9160 value flag. jump2 already knowns how to get rid of
9162 if (new_src == const0_rtx)
9163 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9164 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9165 && have_add2_insn (reg, new_src))
9166 success = validate_change (insn, &PATTERN (insn),
9167 gen_add2_insn (reg, new_src), 0);
9168 reg_set_luid[regno] = move2add_luid;
9169 reg_mode[regno] = GET_MODE (reg);
9170 reg_offset[regno] = INTVAL (src);
9174 /* Try to transform (set (REGX) (REGY))
9175 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9178 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9181 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9183 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9184 else if (GET_CODE (src) == REG
9185 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9186 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9187 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9188 reg_mode[REGNO (src)]))
9190 rtx next = next_nonnote_insn (insn);
9193 set = single_set (next);
9195 && SET_DEST (set) == reg
9196 && GET_CODE (SET_SRC (set)) == PLUS
9197 && XEXP (SET_SRC (set), 0) == reg
9198 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9200 rtx src3 = XEXP (SET_SRC (set), 1);
9201 HOST_WIDE_INT added_offset = INTVAL (src3);
9202 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9203 HOST_WIDE_INT regno_offset = reg_offset[regno];
9204 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9210 if (new_src == const0_rtx)
9211 /* See above why we create (set (reg) (reg)) here. */
9213 = validate_change (next, &SET_SRC (set), reg, 0);
9214 else if ((rtx_cost (new_src, PLUS)
9215 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9216 && have_add2_insn (reg, new_src))
9218 = validate_change (next, &PATTERN (next),
9219 gen_add2_insn (reg, new_src), 0);
9223 reg_mode[regno] = GET_MODE (reg);
9224 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9233 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9235 if (REG_NOTE_KIND (note) == REG_INC
9236 && GET_CODE (XEXP (note, 0)) == REG)
9238 /* Reset the information about this register. */
9239 int regno = REGNO (XEXP (note, 0));
9240 if (regno < FIRST_PSEUDO_REGISTER)
9241 reg_set_luid[regno] = 0;
9244 note_stores (PATTERN (insn), move2add_note_store, NULL);
9245 /* If this is a CALL_INSN, all call used registers are stored with
9247 if (GET_CODE (insn) == CALL_INSN)
9249 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9251 if (call_used_regs[i])
9252 /* Reset the information about this register. */
9253 reg_set_luid[i] = 0;
9259 /* SET is a SET or CLOBBER that sets DST.
9260 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9261 Called from reload_cse_move2add via note_stores. */
9264 move2add_note_store (dst, set, data)
9266 void *data ATTRIBUTE_UNUSED;
9268 unsigned int regno = 0;
9270 enum machine_mode mode = GET_MODE (dst);
9272 if (GET_CODE (dst) == SUBREG)
9274 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9275 GET_MODE (SUBREG_REG (dst)),
9278 dst = SUBREG_REG (dst);
9281 /* Some targets do argument pushes without adding REG_INC notes. */
9283 if (GET_CODE (dst) == MEM)
9285 dst = XEXP (dst, 0);
9286 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9287 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9288 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9291 if (GET_CODE (dst) != REG)
9294 regno += REGNO (dst);
9296 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9297 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9298 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9299 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9301 rtx src = SET_SRC (set);
9303 HOST_WIDE_INT offset;
9305 /* This may be different from mode, if SET_DEST (set) is a
9307 enum machine_mode dst_mode = GET_MODE (dst);
9309 switch (GET_CODE (src))
9312 if (GET_CODE (XEXP (src, 0)) == REG)
9314 base_reg = XEXP (src, 0);
9316 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9317 offset = INTVAL (XEXP (src, 1));
9318 else if (GET_CODE (XEXP (src, 1)) == REG
9319 && (reg_set_luid[REGNO (XEXP (src, 1))]
9320 > move2add_last_label_luid)
9321 && (MODES_OK_FOR_MOVE2ADD
9322 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9324 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9325 offset = reg_offset[REGNO (XEXP (src, 1))];
9326 /* Maybe the first register is known to be a
9328 else if (reg_set_luid[REGNO (base_reg)]
9329 > move2add_last_label_luid
9330 && (MODES_OK_FOR_MOVE2ADD
9331 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9332 && reg_base_reg[REGNO (base_reg)] < 0)
9334 offset = reg_offset[REGNO (base_reg)];
9335 base_reg = XEXP (src, 1);
9354 /* Start tracking the register as a constant. */
9355 reg_base_reg[regno] = -1;
9356 reg_offset[regno] = INTVAL (SET_SRC (set));
9357 /* We assign the same luid to all registers set to constants. */
9358 reg_set_luid[regno] = move2add_last_label_luid + 1;
9359 reg_mode[regno] = mode;
9364 /* Invalidate the contents of the register. */
9365 reg_set_luid[regno] = 0;
9369 base_regno = REGNO (base_reg);
9370 /* If information about the base register is not valid, set it
9371 up as a new base register, pretending its value is known
9372 starting from the current insn. */
9373 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9375 reg_base_reg[base_regno] = base_regno;
9376 reg_offset[base_regno] = 0;
9377 reg_set_luid[base_regno] = move2add_luid;
9378 reg_mode[base_regno] = mode;
9380 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9381 reg_mode[base_regno]))
9384 reg_mode[regno] = mode;
9386 /* Copy base information from our base register. */
9387 reg_set_luid[regno] = reg_set_luid[base_regno];
9388 reg_base_reg[regno] = reg_base_reg[base_regno];
9390 /* Compute the sum of the offsets or constants. */
9391 reg_offset[regno] = sext_for_mode (dst_mode,
9393 + reg_offset[base_regno]);
9397 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9399 for (i = regno; i < endregno; i++)
9400 /* Reset the information about this register. */
9401 reg_set_luid[i] = 0;
9407 add_auto_inc_notes (insn, x)
9411 enum rtx_code code = GET_CODE (x);
9415 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9418 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9422 /* Scan all the operand sub-expressions. */
9423 fmt = GET_RTX_FORMAT (code);
9424 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9427 add_auto_inc_notes (insn, XEXP (x, i));
9428 else if (fmt[i] == 'E')
9429 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9430 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9435 /* Copy EH notes from an insn to its reloads. */
9437 copy_eh_notes (insn, x)
9441 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9444 for (; x != 0; x = NEXT_INSN (x))
9446 if (may_trap_p (PATTERN (x)))
9448 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9454 /* This is used by reload pass, that does emit some instructions after
9455 abnormal calls moving basic block end, but in fact it wants to emit
9456 them on the edge. Looks for abnormal call edges, find backward the
9457 proper call and fix the damage.
9459 Similar handle instructions throwing exceptions internally. */
9461 fixup_abnormal_edges ()
9464 bool inserted = false;
9466 for (i = 0; i < n_basic_blocks; i++)
9468 basic_block bb = BASIC_BLOCK (i);
9471 /* Look for cases we are interested in - an calls or instructions causing
9473 for (e = bb->succ; e; e = e->succ_next)
9475 if (e->flags & EDGE_ABNORMAL_CALL)
9477 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9478 == (EDGE_ABNORMAL | EDGE_EH))
9481 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9483 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9485 for (e = bb->succ; e; e = e->succ_next)
9486 if (e->flags & EDGE_FALLTHRU)
9488 /* Get past the new insns generated. Allow notes, as the insns may
9489 be already deleted. */
9490 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9491 && !can_throw_internal (insn)
9492 && insn != bb->head)
9493 insn = PREV_INSN (insn);
9494 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9498 insn = NEXT_INSN (insn);
9499 while (insn && insn != stop)
9501 next = NEXT_INSN (insn);
9504 insert_insn_on_edge (PATTERN (insn), e);
9512 commit_edge_insertions ();
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