1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
45 /* This file contains the reload pass of the compiler, which is
46 run after register allocation has been done. It checks that
47 each insn is valid (operands required to be in registers really
48 are in registers of the proper class) and fixes up invalid ones
49 by copying values temporarily into registers for the insns
52 The results of register allocation are described by the vector
53 reg_renumber; the insns still contain pseudo regs, but reg_renumber
54 can be used to find which hard reg, if any, a pseudo reg is in.
56 The technique we always use is to free up a few hard regs that are
57 called ``reload regs'', and for each place where a pseudo reg
58 must be in a hard reg, copy it temporarily into one of the reload regs.
60 Reload regs are allocated locally for every instruction that needs
61 reloads. When there are pseudos which are allocated to a register that
62 has been chosen as a reload reg, such pseudos must be ``spilled''.
63 This means that they go to other hard regs, or to stack slots if no other
64 available hard regs can be found. Spilling can invalidate more
65 insns, requiring additional need for reloads, so we must keep checking
66 until the process stabilizes.
68 For machines with different classes of registers, we must keep track
69 of the register class needed for each reload, and make sure that
70 we allocate enough reload registers of each class.
72 The file reload.c contains the code that checks one insn for
73 validity and reports the reloads that it needs. This file
74 is in charge of scanning the entire rtl code, accumulating the
75 reload needs, spilling, assigning reload registers to use for
76 fixing up each insn, and generating the new insns to copy values
77 into the reload registers. */
79 #ifndef REGISTER_MOVE_COST
80 #define REGISTER_MOVE_COST(m, x, y) 2
84 #define LOCAL_REGNO(REGNO) 0
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static unsigned int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Nonzero if indirect addressing is supported on the machine; this means
219 that spilling (REG n) does not require reloading it into a register in
220 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
221 value indicates the level of indirect addressing supported, e.g., two
222 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
224 static char spill_indirect_levels;
226 /* Nonzero if indirect addressing is supported when the innermost MEM is
227 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
228 which these are valid is the same as spill_indirect_levels, above. */
229 char indirect_symref_ok;
231 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
232 char double_reg_address_ok;
234 /* Record the stack slot for each spilled hard register. */
235 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
237 /* Width allocated so far for that stack slot. */
238 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Record which pseudos needed to be spilled. */
241 static regset_head spilled_pseudos;
243 /* Used for communication between order_regs_for_reload and count_pseudo.
244 Used to avoid counting one pseudo twice. */
245 static regset_head pseudos_counted;
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
253 int caller_save_needed;
255 /* Set to 1 while reload_as_needed is operating.
256 Required by some machines to handle any generated moves differently. */
257 int reload_in_progress = 0;
259 /* These arrays record the insn_code of insns that may be needed to
260 perform input and output reloads of special objects. They provide a
261 place to pass a scratch register. */
262 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
263 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
265 /* This obstack is used for allocation of rtl during register elimination.
266 The allocated storage can be freed once find_reloads has processed the
268 struct obstack reload_obstack;
270 /* Points to the beginning of the reload_obstack. All insn_chain structures
271 are allocated first. */
272 char *reload_startobj;
274 /* The point after all insn_chain structures. Used to quickly deallocate
275 memory allocated in copy_reloads during calculate_needs_all_insns. */
276 char *reload_firstobj;
278 /* This points before all local rtl generated by register elimination.
279 Used to quickly free all memory after processing one insn. */
280 static char *reload_insn_firstobj;
282 #define obstack_chunk_alloc xmalloc
283 #define obstack_chunk_free free
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Non-zero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If non-zero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 static void replace_pseudos_in_call_usage PARAMS((rtx *,
372 static void maybe_fix_stack_asms PARAMS ((void));
373 static void copy_reloads PARAMS ((struct insn_chain *));
374 static void calculate_needs_all_insns PARAMS ((int));
375 static int find_reg PARAMS ((struct insn_chain *, int));
376 static void find_reload_regs PARAMS ((struct insn_chain *));
377 static void select_reload_regs PARAMS ((void));
378 static void delete_caller_save_insns PARAMS ((void));
380 static void spill_failure PARAMS ((rtx, enum reg_class));
381 static void count_spilled_pseudo PARAMS ((int, int, int));
382 static void delete_dead_insn PARAMS ((rtx));
383 static void alter_reg PARAMS ((int, int));
384 static void set_label_offsets PARAMS ((rtx, rtx, int));
385 static void check_eliminable_occurrences PARAMS ((rtx));
386 static void elimination_effects PARAMS ((rtx, enum machine_mode));
387 static int eliminate_regs_in_insn PARAMS ((rtx, int));
388 static void update_eliminable_offsets PARAMS ((void));
389 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
390 static void set_initial_elim_offsets PARAMS ((void));
391 static void verify_initial_elim_offsets PARAMS ((void));
392 static void set_initial_label_offsets PARAMS ((void));
393 static void set_offsets_for_label PARAMS ((rtx));
394 static void init_elim_table PARAMS ((void));
395 static void update_eliminables PARAMS ((HARD_REG_SET *));
396 static void spill_hard_reg PARAMS ((unsigned int, int));
397 static int finish_spills PARAMS ((int));
398 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
399 static void scan_paradoxical_subregs PARAMS ((rtx));
400 static void count_pseudo PARAMS ((int));
401 static void order_regs_for_reload PARAMS ((struct insn_chain *));
402 static void reload_as_needed PARAMS ((int));
403 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
404 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
405 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
411 static int reload_reg_free_p PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
415 rtx, rtx, int, int));
416 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
417 enum reload_type, rtx, rtx,
419 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
421 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
423 static int conflicts_with_override PARAMS ((rtx));
424 static void failed_reload PARAMS ((rtx, int));
425 static int set_reload_reg PARAMS ((int, int));
426 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
427 static void choose_reload_regs PARAMS ((struct insn_chain *));
428 static void merge_assigned_reloads PARAMS ((rtx));
429 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
430 struct reload *, rtx, int));
431 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void do_input_reload PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_output_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void emit_reload_insns PARAMS ((struct insn_chain *));
438 static void delete_output_reload PARAMS ((rtx, int, int));
439 static void delete_address_reloads PARAMS ((rtx, rtx));
440 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
441 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
442 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
443 static void reload_cse_regs_1 PARAMS ((rtx));
444 static int reload_cse_noop_set_p PARAMS ((rtx));
445 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
446 static int reload_cse_simplify_operands PARAMS ((rtx));
447 static void reload_combine PARAMS ((void));
448 static void reload_combine_note_use PARAMS ((rtx *, rtx));
449 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
450 static void reload_cse_move2add PARAMS ((rtx));
451 static void move2add_note_store PARAMS ((rtx, rtx, void *));
453 static void add_auto_inc_notes PARAMS ((rtx, rtx));
455 static void copy_eh_notes PARAMS ((rtx, rtx));
456 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
458 static void failed_reload PARAMS ((rtx, int));
459 static int set_reload_reg PARAMS ((int, int));
460 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
461 static void reload_cse_simplify PARAMS ((rtx));
462 static void fixup_abnormal_edges PARAMS ((void));
463 extern void dump_needs PARAMS ((struct insn_chain *));
465 /* Initialize the reload pass once per compilation. */
472 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
473 Set spill_indirect_levels to the number of levels such addressing is
474 permitted, zero if it is not permitted at all. */
477 = gen_rtx_MEM (Pmode,
480 LAST_VIRTUAL_REGISTER + 1),
482 spill_indirect_levels = 0;
484 while (memory_address_p (QImode, tem))
486 spill_indirect_levels++;
487 tem = gen_rtx_MEM (Pmode, tem);
490 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
492 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
493 indirect_symref_ok = memory_address_p (QImode, tem);
495 /* See if reg+reg is a valid (and offsettable) address. */
497 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
499 tem = gen_rtx_PLUS (Pmode,
500 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
501 gen_rtx_REG (Pmode, i));
503 /* This way, we make sure that reg+reg is an offsettable address. */
504 tem = plus_constant (tem, 4);
506 if (memory_address_p (QImode, tem))
508 double_reg_address_ok = 1;
513 /* Initialize obstack for our rtl allocation. */
514 gcc_obstack_init (&reload_obstack);
515 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
517 INIT_REG_SET (&spilled_pseudos);
518 INIT_REG_SET (&pseudos_counted);
521 /* List of insn chains that are currently unused. */
522 static struct insn_chain *unused_insn_chains = 0;
524 /* Allocate an empty insn_chain structure. */
528 struct insn_chain *c;
530 if (unused_insn_chains == 0)
532 c = (struct insn_chain *)
533 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
534 INIT_REG_SET (&c->live_throughout);
535 INIT_REG_SET (&c->dead_or_set);
539 c = unused_insn_chains;
540 unused_insn_chains = c->next;
542 c->is_caller_save_insn = 0;
543 c->need_operand_change = 0;
549 /* Small utility function to set all regs in hard reg set TO which are
550 allocated to pseudos in regset FROM. */
553 compute_use_by_pseudos (to, from)
559 EXECUTE_IF_SET_IN_REG_SET
560 (from, FIRST_PSEUDO_REGISTER, regno,
562 int r = reg_renumber[regno];
567 /* reload_combine uses the information from
568 BASIC_BLOCK->global_live_at_start, which might still
569 contain registers that have not actually been allocated
570 since they have an equivalence. */
571 if (! reload_completed)
576 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
578 SET_HARD_REG_BIT (*to, r + nregs);
583 /* Replace all pseudos found in LOC with their corresponding
587 replace_pseudos_in_call_usage (loc, mem_mode, usage)
589 enum machine_mode mem_mode;
603 unsigned int regno = REGNO (x);
605 if (regno < FIRST_PSEUDO_REGISTER)
608 x = eliminate_regs (x, mem_mode, usage);
612 replace_pseudos_in_call_usage (loc, mem_mode, usage);
616 if (reg_equiv_constant[regno])
617 *loc = reg_equiv_constant[regno];
618 else if (reg_equiv_mem[regno])
619 *loc = reg_equiv_mem[regno];
620 else if (reg_equiv_address[regno])
621 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
622 else if (GET_CODE (regno_reg_rtx[regno]) != REG
623 || REGNO (regno_reg_rtx[regno]) != regno)
624 *loc = regno_reg_rtx[regno];
630 else if (code == MEM)
632 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
636 /* Process each of our operands recursively. */
637 fmt = GET_RTX_FORMAT (code);
638 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
640 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
641 else if (*fmt == 'E')
642 for (j = 0; j < XVECLEN (x, i); j++)
643 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
647 /* Global variables used by reload and its subroutines. */
649 /* Set during calculate_needs if an insn needs register elimination. */
650 static int something_needs_elimination;
651 /* Set during calculate_needs if an insn needs an operand changed. */
652 int something_needs_operands_changed;
654 /* Nonzero means we couldn't get enough spill regs. */
657 /* Main entry point for the reload pass.
659 FIRST is the first insn of the function being compiled.
661 GLOBAL nonzero means we were called from global_alloc
662 and should attempt to reallocate any pseudoregs that we
663 displace from hard regs we will use for reloads.
664 If GLOBAL is zero, we do not have enough information to do that,
665 so any pseudo reg that is spilled must go to the stack.
667 Return value is nonzero if reload failed
668 and we must not do any more for this function. */
671 reload (first, global)
677 struct elim_table *ep;
679 /* The two pointers used to track the true location of the memory used
680 for label offsets. */
681 char *real_known_ptr = NULL;
682 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
684 /* Make sure even insns with volatile mem refs are recognizable. */
689 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
691 /* Make sure that the last insn in the chain
692 is not something that needs reloading. */
693 emit_note (NULL, NOTE_INSN_DELETED);
695 /* Enable find_equiv_reg to distinguish insns made by reload. */
696 reload_first_uid = get_max_uid ();
698 #ifdef SECONDARY_MEMORY_NEEDED
699 /* Initialize the secondary memory table. */
700 clear_secondary_mem ();
703 /* We don't have a stack slot for any spill reg yet. */
704 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
705 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
707 /* Initialize the save area information for caller-save, in case some
711 /* Compute which hard registers are now in use
712 as homes for pseudo registers.
713 This is done here rather than (eg) in global_alloc
714 because this point is reached even if not optimizing. */
715 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
718 /* A function that receives a nonlocal goto must save all call-saved
720 if (current_function_has_nonlocal_label)
721 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
722 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
723 regs_ever_live[i] = 1;
725 /* Find all the pseudo registers that didn't get hard regs
726 but do have known equivalent constants or memory slots.
727 These include parameters (known equivalent to parameter slots)
728 and cse'd or loop-moved constant memory addresses.
730 Record constant equivalents in reg_equiv_constant
731 so they will be substituted by find_reloads.
732 Record memory equivalents in reg_mem_equiv so they can
733 be substituted eventually by altering the REG-rtx's. */
735 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
740 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
741 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
742 pseudo_forbidden_regs
743 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
745 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
747 CLEAR_HARD_REG_SET (bad_spill_regs_global);
749 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
750 Also find all paradoxical subregs and find largest such for each pseudo.
751 On machines with small register classes, record hard registers that
752 are used for user variables. These can never be used for spills.
753 Also look for a "constant" REG_SETJMP. This means that all
754 caller-saved registers must be marked live. */
756 num_eliminable_invariants = 0;
757 for (insn = first; insn; insn = NEXT_INSN (insn))
759 rtx set = single_set (insn);
761 /* We may introduce USEs that we want to remove at the end, so
762 we'll mark them with QImode. Make sure there are no
763 previously-marked insns left by say regmove. */
764 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
765 && GET_MODE (insn) != VOIDmode)
766 PUT_MODE (insn, VOIDmode);
768 if (GET_CODE (insn) == CALL_INSN
769 && find_reg_note (insn, REG_SETJMP, NULL))
770 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
771 if (! call_used_regs[i])
772 regs_ever_live[i] = 1;
774 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
776 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
778 #ifdef LEGITIMATE_PIC_OPERAND_P
779 && (! function_invariant_p (XEXP (note, 0))
781 /* A function invariant is often CONSTANT_P but may
782 include a register. We promise to only pass
783 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
784 || (CONSTANT_P (XEXP (note, 0))
785 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
789 rtx x = XEXP (note, 0);
790 i = REGNO (SET_DEST (set));
791 if (i > LAST_VIRTUAL_REGISTER)
793 if (GET_CODE (x) == MEM)
795 /* Always unshare the equivalence, so we can
796 substitute into this insn without touching the
798 reg_equiv_memory_loc[i] = copy_rtx (x);
800 else if (function_invariant_p (x))
802 if (GET_CODE (x) == PLUS)
804 /* This is PLUS of frame pointer and a constant,
805 and might be shared. Unshare it. */
806 reg_equiv_constant[i] = copy_rtx (x);
807 num_eliminable_invariants++;
809 else if (x == frame_pointer_rtx
810 || x == arg_pointer_rtx)
812 reg_equiv_constant[i] = x;
813 num_eliminable_invariants++;
815 else if (LEGITIMATE_CONSTANT_P (x))
816 reg_equiv_constant[i] = x;
818 reg_equiv_memory_loc[i]
819 = force_const_mem (GET_MODE (SET_DEST (set)), x);
824 /* If this register is being made equivalent to a MEM
825 and the MEM is not SET_SRC, the equivalencing insn
826 is one with the MEM as a SET_DEST and it occurs later.
827 So don't mark this insn now. */
828 if (GET_CODE (x) != MEM
829 || rtx_equal_p (SET_SRC (set), x))
831 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
836 /* If this insn is setting a MEM from a register equivalent to it,
837 this is the equivalencing insn. */
838 else if (set && GET_CODE (SET_DEST (set)) == MEM
839 && GET_CODE (SET_SRC (set)) == REG
840 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
841 && rtx_equal_p (SET_DEST (set),
842 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
843 reg_equiv_init[REGNO (SET_SRC (set))]
844 = gen_rtx_INSN_LIST (VOIDmode, insn,
845 reg_equiv_init[REGNO (SET_SRC (set))]);
848 scan_paradoxical_subregs (PATTERN (insn));
853 num_labels = max_label_num () - get_first_label_num ();
855 /* Allocate the tables used to store offset information at labels. */
856 /* We used to use alloca here, but the size of what it would try to
857 allocate would occasionally cause it to exceed the stack limit and
858 cause a core dump. */
859 real_known_ptr = xmalloc (num_labels);
861 = (int (*)[NUM_ELIMINABLE_REGS])
862 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
864 offsets_known_at = real_known_ptr - get_first_label_num ();
866 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
868 /* Alter each pseudo-reg rtx to contain its hard reg number.
869 Assign stack slots to the pseudos that lack hard regs or equivalents.
870 Do not touch virtual registers. */
872 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
875 /* If we have some registers we think can be eliminated, scan all insns to
876 see if there is an insn that sets one of these registers to something
877 other than itself plus a constant. If so, the register cannot be
878 eliminated. Doing this scan here eliminates an extra pass through the
879 main reload loop in the most common case where register elimination
881 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
882 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
883 || GET_CODE (insn) == CALL_INSN)
884 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
886 maybe_fix_stack_asms ();
888 insns_need_reload = 0;
889 something_needs_elimination = 0;
891 /* Initialize to -1, which means take the first spill register. */
894 /* Spill any hard regs that we know we can't eliminate. */
895 CLEAR_HARD_REG_SET (used_spill_regs);
896 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
897 if (! ep->can_eliminate)
898 spill_hard_reg (ep->from, 1);
900 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
901 if (frame_pointer_needed)
902 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
904 finish_spills (global);
906 /* From now on, we may need to generate moves differently. We may also
907 allow modifications of insns which cause them to not be recognized.
908 Any such modifications will be cleaned up during reload itself. */
909 reload_in_progress = 1;
911 /* This loop scans the entire function each go-round
912 and repeats until one repetition spills no additional hard regs. */
915 int something_changed;
918 HOST_WIDE_INT starting_frame_size;
920 /* Round size of stack frame to stack_alignment_needed. This must be done
921 here because the stack size may be a part of the offset computation
922 for register elimination, and there might have been new stack slots
923 created in the last iteration of this loop. */
924 if (cfun->stack_alignment_needed)
925 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
927 starting_frame_size = get_frame_size ();
929 set_initial_elim_offsets ();
930 set_initial_label_offsets ();
932 /* For each pseudo register that has an equivalent location defined,
933 try to eliminate any eliminable registers (such as the frame pointer)
934 assuming initial offsets for the replacement register, which
937 If the resulting location is directly addressable, substitute
938 the MEM we just got directly for the old REG.
940 If it is not addressable but is a constant or the sum of a hard reg
941 and constant, it is probably not addressable because the constant is
942 out of range, in that case record the address; we will generate
943 hairy code to compute the address in a register each time it is
944 needed. Similarly if it is a hard register, but one that is not
945 valid as an address register.
947 If the location is not addressable, but does not have one of the
948 above forms, assign a stack slot. We have to do this to avoid the
949 potential of producing lots of reloads if, e.g., a location involves
950 a pseudo that didn't get a hard register and has an equivalent memory
951 location that also involves a pseudo that didn't get a hard register.
953 Perhaps at some point we will improve reload_when_needed handling
954 so this problem goes away. But that's very hairy. */
956 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
957 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
959 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
961 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
963 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
964 else if (CONSTANT_P (XEXP (x, 0))
965 || (GET_CODE (XEXP (x, 0)) == REG
966 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
967 || (GET_CODE (XEXP (x, 0)) == PLUS
968 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
969 && (REGNO (XEXP (XEXP (x, 0), 0))
970 < FIRST_PSEUDO_REGISTER)
971 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
972 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
975 /* Make a new stack slot. Then indicate that something
976 changed so we go back and recompute offsets for
977 eliminable registers because the allocation of memory
978 below might change some offset. reg_equiv_{mem,address}
979 will be set up for this pseudo on the next pass around
981 reg_equiv_memory_loc[i] = 0;
982 reg_equiv_init[i] = 0;
987 if (caller_save_needed)
990 /* If we allocated another stack slot, redo elimination bookkeeping. */
991 if (starting_frame_size != get_frame_size ())
994 if (caller_save_needed)
996 save_call_clobbered_regs ();
997 /* That might have allocated new insn_chain structures. */
998 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1001 calculate_needs_all_insns (global);
1003 CLEAR_REG_SET (&spilled_pseudos);
1006 something_changed = 0;
1008 /* If we allocated any new memory locations, make another pass
1009 since it might have changed elimination offsets. */
1010 if (starting_frame_size != get_frame_size ())
1011 something_changed = 1;
1014 HARD_REG_SET to_spill;
1015 CLEAR_HARD_REG_SET (to_spill);
1016 update_eliminables (&to_spill);
1017 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1018 if (TEST_HARD_REG_BIT (to_spill, i))
1020 spill_hard_reg (i, 1);
1023 /* Regardless of the state of spills, if we previously had
1024 a register that we thought we could eliminate, but no can
1025 not eliminate, we must run another pass.
1027 Consider pseudos which have an entry in reg_equiv_* which
1028 reference an eliminable register. We must make another pass
1029 to update reg_equiv_* so that we do not substitute in the
1030 old value from when we thought the elimination could be
1032 something_changed = 1;
1036 select_reload_regs ();
1040 if (insns_need_reload != 0 || did_spill)
1041 something_changed |= finish_spills (global);
1043 if (! something_changed)
1046 if (caller_save_needed)
1047 delete_caller_save_insns ();
1049 obstack_free (&reload_obstack, reload_firstobj);
1052 /* If global-alloc was run, notify it of any register eliminations we have
1055 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1056 if (ep->can_eliminate)
1057 mark_elimination (ep->from, ep->to);
1059 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1060 If that insn didn't set the register (i.e., it copied the register to
1061 memory), just delete that insn instead of the equivalencing insn plus
1062 anything now dead. If we call delete_dead_insn on that insn, we may
1063 delete the insn that actually sets the register if the register dies
1064 there and that is incorrect. */
1066 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1068 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1071 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1073 rtx equiv_insn = XEXP (list, 0);
1075 /* If we already deleted the insn or if it may trap, we can't
1076 delete it. The latter case shouldn't happen, but can
1077 if an insn has a variable address, gets a REG_EH_REGION
1078 note added to it, and then gets converted into an load
1079 from a constant address. */
1080 if (GET_CODE (equiv_insn) == NOTE
1081 || can_throw_internal (equiv_insn))
1083 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1084 delete_dead_insn (equiv_insn);
1087 PUT_CODE (equiv_insn, NOTE);
1088 NOTE_SOURCE_FILE (equiv_insn) = 0;
1089 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1095 /* Use the reload registers where necessary
1096 by generating move instructions to move the must-be-register
1097 values into or out of the reload registers. */
1099 if (insns_need_reload != 0 || something_needs_elimination
1100 || something_needs_operands_changed)
1102 HOST_WIDE_INT old_frame_size = get_frame_size ();
1104 reload_as_needed (global);
1106 if (old_frame_size != get_frame_size ())
1110 verify_initial_elim_offsets ();
1113 /* If we were able to eliminate the frame pointer, show that it is no
1114 longer live at the start of any basic block. If it ls live by
1115 virtue of being in a pseudo, that pseudo will be marked live
1116 and hence the frame pointer will be known to be live via that
1119 if (! frame_pointer_needed)
1120 for (i = 0; i < n_basic_blocks; i++)
1121 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1122 HARD_FRAME_POINTER_REGNUM);
1124 /* Come here (with failure set nonzero) if we can't get enough spill regs
1125 and we decide not to abort about it. */
1128 CLEAR_REG_SET (&spilled_pseudos);
1129 reload_in_progress = 0;
1131 /* Now eliminate all pseudo regs by modifying them into
1132 their equivalent memory references.
1133 The REG-rtx's for the pseudos are modified in place,
1134 so all insns that used to refer to them now refer to memory.
1136 For a reg that has a reg_equiv_address, all those insns
1137 were changed by reloading so that no insns refer to it any longer;
1138 but the DECL_RTL of a variable decl may refer to it,
1139 and if so this causes the debugging info to mention the variable. */
1141 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1145 if (reg_equiv_mem[i])
1146 addr = XEXP (reg_equiv_mem[i], 0);
1148 if (reg_equiv_address[i])
1149 addr = reg_equiv_address[i];
1153 if (reg_renumber[i] < 0)
1155 rtx reg = regno_reg_rtx[i];
1157 PUT_CODE (reg, MEM);
1158 XEXP (reg, 0) = addr;
1159 REG_USERVAR_P (reg) = 0;
1160 if (reg_equiv_memory_loc[i])
1161 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1164 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1165 = MEM_SCALAR_P (reg) = 0;
1166 MEM_ATTRS (reg) = 0;
1169 else if (reg_equiv_mem[i])
1170 XEXP (reg_equiv_mem[i], 0) = addr;
1174 /* We must set reload_completed now since the cleanup_subreg_operands call
1175 below will re-recognize each insn and reload may have generated insns
1176 which are only valid during and after reload. */
1177 reload_completed = 1;
1179 /* Make a pass over all the insns and delete all USEs which we inserted
1180 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1181 notes. Delete all CLOBBER insns that don't refer to the return value
1182 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1183 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1184 and regenerate REG_INC notes that may have been moved around. */
1186 for (insn = first; insn; insn = NEXT_INSN (insn))
1191 if (GET_CODE (insn) == CALL_INSN)
1192 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1194 CALL_INSN_FUNCTION_USAGE (insn));
1196 if ((GET_CODE (PATTERN (insn)) == USE
1197 /* We mark with QImode USEs introduced by reload itself. */
1198 && (GET_MODE (insn) == QImode
1199 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1200 || (GET_CODE (PATTERN (insn)) == CLOBBER
1201 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1202 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1208 pnote = ®_NOTES (insn);
1211 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1212 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1213 || REG_NOTE_KIND (*pnote) == REG_INC
1214 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1215 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1216 *pnote = XEXP (*pnote, 1);
1218 pnote = &XEXP (*pnote, 1);
1222 add_auto_inc_notes (insn, PATTERN (insn));
1225 /* And simplify (subreg (reg)) if it appears as an operand. */
1226 cleanup_subreg_operands (insn);
1229 /* If we are doing stack checking, give a warning if this function's
1230 frame size is larger than we expect. */
1231 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1233 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1234 static int verbose_warned = 0;
1236 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1237 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1238 size += UNITS_PER_WORD;
1240 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1242 warning ("frame size too large for reliable stack checking");
1243 if (! verbose_warned)
1245 warning ("try reducing the number of local variables");
1251 /* Indicate that we no longer have known memory locations or constants. */
1252 if (reg_equiv_constant)
1253 free (reg_equiv_constant);
1254 reg_equiv_constant = 0;
1255 if (reg_equiv_memory_loc)
1256 free (reg_equiv_memory_loc);
1257 reg_equiv_memory_loc = 0;
1260 free (real_known_ptr);
1264 free (reg_equiv_mem);
1265 free (reg_equiv_init);
1266 free (reg_equiv_address);
1267 free (reg_max_ref_width);
1268 free (reg_old_renumber);
1269 free (pseudo_previous_regs);
1270 free (pseudo_forbidden_regs);
1272 CLEAR_HARD_REG_SET (used_spill_regs);
1273 for (i = 0; i < n_spills; i++)
1274 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1276 /* Free all the insn_chain structures at once. */
1277 obstack_free (&reload_obstack, reload_startobj);
1278 unused_insn_chains = 0;
1279 fixup_abnormal_edges ();
1284 /* Yet another special case. Unfortunately, reg-stack forces people to
1285 write incorrect clobbers in asm statements. These clobbers must not
1286 cause the register to appear in bad_spill_regs, otherwise we'll call
1287 fatal_insn later. We clear the corresponding regnos in the live
1288 register sets to avoid this.
1289 The whole thing is rather sick, I'm afraid. */
1292 maybe_fix_stack_asms ()
1295 const char *constraints[MAX_RECOG_OPERANDS];
1296 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1297 struct insn_chain *chain;
1299 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1302 HARD_REG_SET clobbered, allowed;
1305 if (! INSN_P (chain->insn)
1306 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1308 pat = PATTERN (chain->insn);
1309 if (GET_CODE (pat) != PARALLEL)
1312 CLEAR_HARD_REG_SET (clobbered);
1313 CLEAR_HARD_REG_SET (allowed);
1315 /* First, make a mask of all stack regs that are clobbered. */
1316 for (i = 0; i < XVECLEN (pat, 0); i++)
1318 rtx t = XVECEXP (pat, 0, i);
1319 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1320 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1323 /* Get the operand values and constraints out of the insn. */
1324 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1325 constraints, operand_mode);
1327 /* For every operand, see what registers are allowed. */
1328 for (i = 0; i < noperands; i++)
1330 const char *p = constraints[i];
1331 /* For every alternative, we compute the class of registers allowed
1332 for reloading in CLS, and merge its contents into the reg set
1334 int cls = (int) NO_REGS;
1340 if (c == '\0' || c == ',' || c == '#')
1342 /* End of one alternative - mark the regs in the current
1343 class, and reset the class. */
1344 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1349 } while (c != '\0' && c != ',');
1357 case '=': case '+': case '*': case '%': case '?': case '!':
1358 case '0': case '1': case '2': case '3': case '4': case 'm':
1359 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1360 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1361 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1366 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1371 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1375 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1380 /* Those of the registers which are clobbered, but allowed by the
1381 constraints, must be usable as reload registers. So clear them
1382 out of the life information. */
1383 AND_HARD_REG_SET (allowed, clobbered);
1384 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1385 if (TEST_HARD_REG_BIT (allowed, i))
1387 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1388 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1395 /* Copy the global variables n_reloads and rld into the corresponding elts
1398 copy_reloads (chain)
1399 struct insn_chain *chain;
1401 chain->n_reloads = n_reloads;
1403 = (struct reload *) obstack_alloc (&reload_obstack,
1404 n_reloads * sizeof (struct reload));
1405 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1406 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1409 /* Walk the chain of insns, and determine for each whether it needs reloads
1410 and/or eliminations. Build the corresponding insns_need_reload list, and
1411 set something_needs_elimination as appropriate. */
1413 calculate_needs_all_insns (global)
1416 struct insn_chain **pprev_reload = &insns_need_reload;
1417 struct insn_chain *chain, *next = 0;
1419 something_needs_elimination = 0;
1421 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1422 for (chain = reload_insn_chain; chain != 0; chain = next)
1424 rtx insn = chain->insn;
1428 /* Clear out the shortcuts. */
1429 chain->n_reloads = 0;
1430 chain->need_elim = 0;
1431 chain->need_reload = 0;
1432 chain->need_operand_change = 0;
1434 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1435 include REG_LABEL), we need to see what effects this has on the
1436 known offsets at labels. */
1438 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1439 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1440 set_label_offsets (insn, insn, 0);
1444 rtx old_body = PATTERN (insn);
1445 int old_code = INSN_CODE (insn);
1446 rtx old_notes = REG_NOTES (insn);
1447 int did_elimination = 0;
1448 int operands_changed = 0;
1449 rtx set = single_set (insn);
1451 /* Skip insns that only set an equivalence. */
1452 if (set && GET_CODE (SET_DEST (set)) == REG
1453 && reg_renumber[REGNO (SET_DEST (set))] < 0
1454 && reg_equiv_constant[REGNO (SET_DEST (set))])
1457 /* If needed, eliminate any eliminable registers. */
1458 if (num_eliminable || num_eliminable_invariants)
1459 did_elimination = eliminate_regs_in_insn (insn, 0);
1461 /* Analyze the instruction. */
1462 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1463 global, spill_reg_order);
1465 /* If a no-op set needs more than one reload, this is likely
1466 to be something that needs input address reloads. We
1467 can't get rid of this cleanly later, and it is of no use
1468 anyway, so discard it now.
1469 We only do this when expensive_optimizations is enabled,
1470 since this complements reload inheritance / output
1471 reload deletion, and it can make debugging harder. */
1472 if (flag_expensive_optimizations && n_reloads > 1)
1474 rtx set = single_set (insn);
1476 && SET_SRC (set) == SET_DEST (set)
1477 && GET_CODE (SET_SRC (set)) == REG
1478 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1481 /* Delete it from the reload chain */
1483 chain->prev->next = next;
1485 reload_insn_chain = next;
1487 next->prev = chain->prev;
1488 chain->next = unused_insn_chains;
1489 unused_insn_chains = chain;
1494 update_eliminable_offsets ();
1496 /* Remember for later shortcuts which insns had any reloads or
1497 register eliminations. */
1498 chain->need_elim = did_elimination;
1499 chain->need_reload = n_reloads > 0;
1500 chain->need_operand_change = operands_changed;
1502 /* Discard any register replacements done. */
1503 if (did_elimination)
1505 obstack_free (&reload_obstack, reload_insn_firstobj);
1506 PATTERN (insn) = old_body;
1507 INSN_CODE (insn) = old_code;
1508 REG_NOTES (insn) = old_notes;
1509 something_needs_elimination = 1;
1512 something_needs_operands_changed |= operands_changed;
1516 copy_reloads (chain);
1517 *pprev_reload = chain;
1518 pprev_reload = &chain->next_need_reload;
1525 /* Comparison function for qsort to decide which of two reloads
1526 should be handled first. *P1 and *P2 are the reload numbers. */
1529 reload_reg_class_lower (r1p, r2p)
1533 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1536 /* Consider required reloads before optional ones. */
1537 t = rld[r1].optional - rld[r2].optional;
1541 /* Count all solitary classes before non-solitary ones. */
1542 t = ((reg_class_size[(int) rld[r2].class] == 1)
1543 - (reg_class_size[(int) rld[r1].class] == 1));
1547 /* Aside from solitaires, consider all multi-reg groups first. */
1548 t = rld[r2].nregs - rld[r1].nregs;
1552 /* Consider reloads in order of increasing reg-class number. */
1553 t = (int) rld[r1].class - (int) rld[r2].class;
1557 /* If reloads are equally urgent, sort by reload number,
1558 so that the results of qsort leave nothing to chance. */
1562 /* The cost of spilling each hard reg. */
1563 static int spill_cost[FIRST_PSEUDO_REGISTER];
1565 /* When spilling multiple hard registers, we use SPILL_COST for the first
1566 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1567 only the first hard reg for a multi-reg pseudo. */
1568 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1570 /* Update the spill cost arrays, considering that pseudo REG is live. */
1576 int freq = REG_FREQ (reg);
1577 int r = reg_renumber[reg];
1580 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1581 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1584 SET_REGNO_REG_SET (&pseudos_counted, reg);
1589 spill_add_cost[r] += freq;
1591 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1593 spill_cost[r + nregs] += freq;
1596 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1597 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1600 order_regs_for_reload (chain)
1601 struct insn_chain *chain;
1604 HARD_REG_SET used_by_pseudos;
1605 HARD_REG_SET used_by_pseudos2;
1607 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1609 memset (spill_cost, 0, sizeof spill_cost);
1610 memset (spill_add_cost, 0, sizeof spill_add_cost);
1612 /* Count number of uses of each hard reg by pseudo regs allocated to it
1613 and then order them by decreasing use. First exclude hard registers
1614 that are live in or across this insn. */
1616 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1617 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1618 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1619 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1621 /* Now find out which pseudos are allocated to it, and update
1623 CLEAR_REG_SET (&pseudos_counted);
1625 EXECUTE_IF_SET_IN_REG_SET
1626 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1630 EXECUTE_IF_SET_IN_REG_SET
1631 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1635 CLEAR_REG_SET (&pseudos_counted);
1638 /* Vector of reload-numbers showing the order in which the reloads should
1640 static short reload_order[MAX_RELOADS];
1642 /* This is used to keep track of the spill regs used in one insn. */
1643 static HARD_REG_SET used_spill_regs_local;
1645 /* We decided to spill hard register SPILLED, which has a size of
1646 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1647 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1648 update SPILL_COST/SPILL_ADD_COST. */
1651 count_spilled_pseudo (spilled, spilled_nregs, reg)
1652 int spilled, spilled_nregs, reg;
1654 int r = reg_renumber[reg];
1655 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1657 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1658 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1661 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1663 spill_add_cost[r] -= REG_FREQ (reg);
1665 spill_cost[r + nregs] -= REG_FREQ (reg);
1668 /* Find reload register to use for reload number ORDER. */
1671 find_reg (chain, order)
1672 struct insn_chain *chain;
1675 int rnum = reload_order[order];
1676 struct reload *rl = rld + rnum;
1677 int best_cost = INT_MAX;
1681 HARD_REG_SET not_usable;
1682 HARD_REG_SET used_by_other_reload;
1684 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1685 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1686 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1688 CLEAR_HARD_REG_SET (used_by_other_reload);
1689 for (k = 0; k < order; k++)
1691 int other = reload_order[k];
1693 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1694 for (j = 0; j < rld[other].nregs; j++)
1695 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1698 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1700 unsigned int regno = i;
1702 if (! TEST_HARD_REG_BIT (not_usable, regno)
1703 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1704 && HARD_REGNO_MODE_OK (regno, rl->mode))
1706 int this_cost = spill_cost[regno];
1708 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1710 for (j = 1; j < this_nregs; j++)
1712 this_cost += spill_add_cost[regno + j];
1713 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1714 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1719 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1721 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1723 if (this_cost < best_cost
1724 /* Among registers with equal cost, prefer caller-saved ones, or
1725 use REG_ALLOC_ORDER if it is defined. */
1726 || (this_cost == best_cost
1727 #ifdef REG_ALLOC_ORDER
1728 && (inv_reg_alloc_order[regno]
1729 < inv_reg_alloc_order[best_reg])
1731 && call_used_regs[regno]
1732 && ! call_used_regs[best_reg]
1737 best_cost = this_cost;
1745 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1747 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1748 rl->regno = best_reg;
1750 EXECUTE_IF_SET_IN_REG_SET
1751 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1753 count_spilled_pseudo (best_reg, rl->nregs, j);
1756 EXECUTE_IF_SET_IN_REG_SET
1757 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1759 count_spilled_pseudo (best_reg, rl->nregs, j);
1762 for (i = 0; i < rl->nregs; i++)
1764 if (spill_cost[best_reg + i] != 0
1765 || spill_add_cost[best_reg + i] != 0)
1767 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1772 /* Find more reload regs to satisfy the remaining need of an insn, which
1774 Do it by ascending class number, since otherwise a reg
1775 might be spilled for a big class and might fail to count
1776 for a smaller class even though it belongs to that class. */
1779 find_reload_regs (chain)
1780 struct insn_chain *chain;
1784 /* In order to be certain of getting the registers we need,
1785 we must sort the reloads into order of increasing register class.
1786 Then our grabbing of reload registers will parallel the process
1787 that provided the reload registers. */
1788 for (i = 0; i < chain->n_reloads; i++)
1790 /* Show whether this reload already has a hard reg. */
1791 if (chain->rld[i].reg_rtx)
1793 int regno = REGNO (chain->rld[i].reg_rtx);
1794 chain->rld[i].regno = regno;
1796 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1799 chain->rld[i].regno = -1;
1800 reload_order[i] = i;
1803 n_reloads = chain->n_reloads;
1804 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1806 CLEAR_HARD_REG_SET (used_spill_regs_local);
1809 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1811 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1813 /* Compute the order of preference for hard registers to spill. */
1815 order_regs_for_reload (chain);
1817 for (i = 0; i < n_reloads; i++)
1819 int r = reload_order[i];
1821 /* Ignore reloads that got marked inoperative. */
1822 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1823 && ! rld[r].optional
1824 && rld[r].regno == -1)
1825 if (! find_reg (chain, i))
1827 spill_failure (chain->insn, rld[r].class);
1833 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1834 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1836 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1840 select_reload_regs ()
1842 struct insn_chain *chain;
1844 /* Try to satisfy the needs for each insn. */
1845 for (chain = insns_need_reload; chain != 0;
1846 chain = chain->next_need_reload)
1847 find_reload_regs (chain);
1850 /* Delete all insns that were inserted by emit_caller_save_insns during
1853 delete_caller_save_insns ()
1855 struct insn_chain *c = reload_insn_chain;
1859 while (c != 0 && c->is_caller_save_insn)
1861 struct insn_chain *next = c->next;
1864 if (c == reload_insn_chain)
1865 reload_insn_chain = next;
1869 next->prev = c->prev;
1871 c->prev->next = next;
1872 c->next = unused_insn_chains;
1873 unused_insn_chains = c;
1881 /* Handle the failure to find a register to spill.
1882 INSN should be one of the insns which needed this particular spill reg. */
1885 spill_failure (insn, class)
1887 enum reg_class class;
1889 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1890 if (asm_noperands (PATTERN (insn)) >= 0)
1891 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1892 reg_class_names[class]);
1895 error ("unable to find a register to spill in class `%s'",
1896 reg_class_names[class]);
1897 fatal_insn ("this is the insn:", insn);
1901 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1902 data that is dead in INSN. */
1905 delete_dead_insn (insn)
1908 rtx prev = prev_real_insn (insn);
1911 /* If the previous insn sets a register that dies in our insn, delete it
1913 if (prev && GET_CODE (PATTERN (prev)) == SET
1914 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1915 && reg_mentioned_p (prev_dest, PATTERN (insn))
1916 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1917 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1918 delete_dead_insn (prev);
1920 PUT_CODE (insn, NOTE);
1921 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1922 NOTE_SOURCE_FILE (insn) = 0;
1925 /* Modify the home of pseudo-reg I.
1926 The new home is present in reg_renumber[I].
1928 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1929 or it may be -1, meaning there is none or it is not relevant.
1930 This is used so that all pseudos spilled from a given hard reg
1931 can share one stack slot. */
1934 alter_reg (i, from_reg)
1938 /* When outputting an inline function, this can happen
1939 for a reg that isn't actually used. */
1940 if (regno_reg_rtx[i] == 0)
1943 /* If the reg got changed to a MEM at rtl-generation time,
1945 if (GET_CODE (regno_reg_rtx[i]) != REG)
1948 /* Modify the reg-rtx to contain the new hard reg
1949 number or else to contain its pseudo reg number. */
1950 REGNO (regno_reg_rtx[i])
1951 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1953 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1954 allocate a stack slot for it. */
1956 if (reg_renumber[i] < 0
1957 && REG_N_REFS (i) > 0
1958 && reg_equiv_constant[i] == 0
1959 && reg_equiv_memory_loc[i] == 0)
1962 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1963 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1966 /* Each pseudo reg has an inherent size which comes from its own mode,
1967 and a total size which provides room for paradoxical subregs
1968 which refer to the pseudo reg in wider modes.
1970 We can use a slot already allocated if it provides both
1971 enough inherent space and enough total space.
1972 Otherwise, we allocate a new slot, making sure that it has no less
1973 inherent space, and no less total space, then the previous slot. */
1976 /* No known place to spill from => no slot to reuse. */
1977 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1978 inherent_size == total_size ? 0 : -1);
1979 if (BYTES_BIG_ENDIAN)
1980 /* Cancel the big-endian correction done in assign_stack_local.
1981 Get the address of the beginning of the slot.
1982 This is so we can do a big-endian correction unconditionally
1984 adjust = inherent_size - total_size;
1986 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1988 /* Nothing can alias this slot except this pseudo. */
1989 set_mem_alias_set (x, new_alias_set ());
1992 /* Reuse a stack slot if possible. */
1993 else if (spill_stack_slot[from_reg] != 0
1994 && spill_stack_slot_width[from_reg] >= total_size
1995 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1997 x = spill_stack_slot[from_reg];
1999 /* Allocate a bigger slot. */
2002 /* Compute maximum size needed, both for inherent size
2003 and for total size. */
2004 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2007 if (spill_stack_slot[from_reg])
2009 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2011 mode = GET_MODE (spill_stack_slot[from_reg]);
2012 if (spill_stack_slot_width[from_reg] > total_size)
2013 total_size = spill_stack_slot_width[from_reg];
2016 /* Make a slot with that size. */
2017 x = assign_stack_local (mode, total_size,
2018 inherent_size == total_size ? 0 : -1);
2021 /* All pseudos mapped to this slot can alias each other. */
2022 if (spill_stack_slot[from_reg])
2023 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2025 set_mem_alias_set (x, new_alias_set ());
2027 if (BYTES_BIG_ENDIAN)
2029 /* Cancel the big-endian correction done in assign_stack_local.
2030 Get the address of the beginning of the slot.
2031 This is so we can do a big-endian correction unconditionally
2033 adjust = GET_MODE_SIZE (mode) - total_size;
2036 = adjust_address_nv (x, mode_for_size (total_size
2042 spill_stack_slot[from_reg] = stack_slot;
2043 spill_stack_slot_width[from_reg] = total_size;
2046 /* On a big endian machine, the "address" of the slot
2047 is the address of the low part that fits its inherent mode. */
2048 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2049 adjust += (total_size - inherent_size);
2051 /* If we have any adjustment to make, or if the stack slot is the
2052 wrong mode, make a new stack slot. */
2053 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2055 /* If we have a decl for the original register, set it for the
2056 memory. If this is a shared MEM, make a copy. */
2059 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2062 set_mem_expr (x, REGNO_DECL (i));
2065 /* Save the stack slot for later. */
2066 reg_equiv_memory_loc[i] = x;
2070 /* Mark the slots in regs_ever_live for the hard regs
2071 used by pseudo-reg number REGNO. */
2074 mark_home_live (regno)
2079 i = reg_renumber[regno];
2082 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2084 regs_ever_live[i++] = 1;
2087 /* This function handles the tracking of elimination offsets around branches.
2089 X is a piece of RTL being scanned.
2091 INSN is the insn that it came from, if any.
2093 INITIAL_P is non-zero if we are to set the offset to be the initial
2094 offset and zero if we are setting the offset of the label to be the
2098 set_label_offsets (x, insn, initial_p)
2103 enum rtx_code code = GET_CODE (x);
2106 struct elim_table *p;
2111 if (LABEL_REF_NONLOCAL_P (x))
2116 /* ... fall through ... */
2119 /* If we know nothing about this label, set the desired offsets. Note
2120 that this sets the offset at a label to be the offset before a label
2121 if we don't know anything about the label. This is not correct for
2122 the label after a BARRIER, but is the best guess we can make. If
2123 we guessed wrong, we will suppress an elimination that might have
2124 been possible had we been able to guess correctly. */
2126 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2128 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2129 offsets_at[CODE_LABEL_NUMBER (x)][i]
2130 = (initial_p ? reg_eliminate[i].initial_offset
2131 : reg_eliminate[i].offset);
2132 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2135 /* Otherwise, if this is the definition of a label and it is
2136 preceded by a BARRIER, set our offsets to the known offset of
2140 && (tem = prev_nonnote_insn (insn)) != 0
2141 && GET_CODE (tem) == BARRIER)
2142 set_offsets_for_label (insn);
2144 /* If neither of the above cases is true, compare each offset
2145 with those previously recorded and suppress any eliminations
2146 where the offsets disagree. */
2148 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2149 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2150 != (initial_p ? reg_eliminate[i].initial_offset
2151 : reg_eliminate[i].offset))
2152 reg_eliminate[i].can_eliminate = 0;
2157 set_label_offsets (PATTERN (insn), insn, initial_p);
2159 /* ... fall through ... */
2163 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2164 and hence must have all eliminations at their initial offsets. */
2165 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2166 if (REG_NOTE_KIND (tem) == REG_LABEL)
2167 set_label_offsets (XEXP (tem, 0), insn, 1);
2173 /* Each of the labels in the parallel or address vector must be
2174 at their initial offsets. We want the first field for PARALLEL
2175 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2177 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2178 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2183 /* We only care about setting PC. If the source is not RETURN,
2184 IF_THEN_ELSE, or a label, disable any eliminations not at
2185 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2186 isn't one of those possibilities. For branches to a label,
2187 call ourselves recursively.
2189 Note that this can disable elimination unnecessarily when we have
2190 a non-local goto since it will look like a non-constant jump to
2191 someplace in the current function. This isn't a significant
2192 problem since such jumps will normally be when all elimination
2193 pairs are back to their initial offsets. */
2195 if (SET_DEST (x) != pc_rtx)
2198 switch (GET_CODE (SET_SRC (x)))
2205 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2209 tem = XEXP (SET_SRC (x), 1);
2210 if (GET_CODE (tem) == LABEL_REF)
2211 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2212 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2215 tem = XEXP (SET_SRC (x), 2);
2216 if (GET_CODE (tem) == LABEL_REF)
2217 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2218 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2226 /* If we reach here, all eliminations must be at their initial
2227 offset because we are doing a jump to a variable address. */
2228 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2229 if (p->offset != p->initial_offset)
2230 p->can_eliminate = 0;
2238 /* Scan X and replace any eliminable registers (such as fp) with a
2239 replacement (such as sp), plus an offset.
2241 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2242 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2243 MEM, we are allowed to replace a sum of a register and the constant zero
2244 with the register, which we cannot do outside a MEM. In addition, we need
2245 to record the fact that a register is referenced outside a MEM.
2247 If INSN is an insn, it is the insn containing X. If we replace a REG
2248 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2249 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2250 the REG is being modified.
2252 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2253 That's used when we eliminate in expressions stored in notes.
2254 This means, do not set ref_outside_mem even if the reference
2257 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2258 replacements done assuming all offsets are at their initial values. If
2259 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2260 encounter, return the actual location so that find_reloads will do
2261 the proper thing. */
2264 eliminate_regs (x, mem_mode, insn)
2266 enum machine_mode mem_mode;
2269 enum rtx_code code = GET_CODE (x);
2270 struct elim_table *ep;
2277 if (! current_function_decl)
2296 /* This is only for the benefit of the debugging backends, which call
2297 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2298 removed after CSE. */
2299 new = eliminate_regs (XEXP (x, 0), 0, insn);
2300 if (GET_CODE (new) == MEM)
2301 return XEXP (new, 0);
2307 /* First handle the case where we encounter a bare register that
2308 is eliminable. Replace it with a PLUS. */
2309 if (regno < FIRST_PSEUDO_REGISTER)
2311 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2313 if (ep->from_rtx == x && ep->can_eliminate)
2314 return plus_constant (ep->to_rtx, ep->previous_offset);
2317 else if (reg_renumber && reg_renumber[regno] < 0
2318 && reg_equiv_constant && reg_equiv_constant[regno]
2319 && ! CONSTANT_P (reg_equiv_constant[regno]))
2320 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2324 /* You might think handling MINUS in a manner similar to PLUS is a
2325 good idea. It is not. It has been tried multiple times and every
2326 time the change has had to have been reverted.
2328 Other parts of reload know a PLUS is special (gen_reload for example)
2329 and require special code to handle code a reloaded PLUS operand.
2331 Also consider backends where the flags register is clobbered by a
2332 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2333 lea instruction comes to mind). If we try to reload a MINUS, we
2334 may kill the flags register that was holding a useful value.
2336 So, please before trying to handle MINUS, consider reload as a
2337 whole instead of this little section as well as the backend issues. */
2339 /* If this is the sum of an eliminable register and a constant, rework
2341 if (GET_CODE (XEXP (x, 0)) == REG
2342 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2343 && CONSTANT_P (XEXP (x, 1)))
2345 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2347 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2349 /* The only time we want to replace a PLUS with a REG (this
2350 occurs when the constant operand of the PLUS is the negative
2351 of the offset) is when we are inside a MEM. We won't want
2352 to do so at other times because that would change the
2353 structure of the insn in a way that reload can't handle.
2354 We special-case the commonest situation in
2355 eliminate_regs_in_insn, so just replace a PLUS with a
2356 PLUS here, unless inside a MEM. */
2357 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2358 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2361 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2362 plus_constant (XEXP (x, 1),
2363 ep->previous_offset));
2366 /* If the register is not eliminable, we are done since the other
2367 operand is a constant. */
2371 /* If this is part of an address, we want to bring any constant to the
2372 outermost PLUS. We will do this by doing register replacement in
2373 our operands and seeing if a constant shows up in one of them.
2375 Note that there is no risk of modifying the structure of the insn,
2376 since we only get called for its operands, thus we are either
2377 modifying the address inside a MEM, or something like an address
2378 operand of a load-address insn. */
2381 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2382 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2384 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2386 /* If one side is a PLUS and the other side is a pseudo that
2387 didn't get a hard register but has a reg_equiv_constant,
2388 we must replace the constant here since it may no longer
2389 be in the position of any operand. */
2390 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2391 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2392 && reg_renumber[REGNO (new1)] < 0
2393 && reg_equiv_constant != 0
2394 && reg_equiv_constant[REGNO (new1)] != 0)
2395 new1 = reg_equiv_constant[REGNO (new1)];
2396 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2397 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2398 && reg_renumber[REGNO (new0)] < 0
2399 && reg_equiv_constant[REGNO (new0)] != 0)
2400 new0 = reg_equiv_constant[REGNO (new0)];
2402 new = form_sum (new0, new1);
2404 /* As above, if we are not inside a MEM we do not want to
2405 turn a PLUS into something else. We might try to do so here
2406 for an addition of 0 if we aren't optimizing. */
2407 if (! mem_mode && GET_CODE (new) != PLUS)
2408 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2416 /* If this is the product of an eliminable register and a
2417 constant, apply the distribute law and move the constant out
2418 so that we have (plus (mult ..) ..). This is needed in order
2419 to keep load-address insns valid. This case is pathological.
2420 We ignore the possibility of overflow here. */
2421 if (GET_CODE (XEXP (x, 0)) == REG
2422 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2423 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2424 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2426 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2429 /* Refs inside notes don't count for this purpose. */
2430 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2431 || GET_CODE (insn) == INSN_LIST)))
2432 ep->ref_outside_mem = 1;
2435 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2436 ep->previous_offset * INTVAL (XEXP (x, 1)));
2439 /* ... fall through ... */
2443 /* See comments before PLUS about handling MINUS. */
2445 case DIV: case UDIV:
2446 case MOD: case UMOD:
2447 case AND: case IOR: case XOR:
2448 case ROTATERT: case ROTATE:
2449 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2451 case GE: case GT: case GEU: case GTU:
2452 case LE: case LT: case LEU: case LTU:
2454 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2456 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2458 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2459 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2464 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2467 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2468 if (new != XEXP (x, 0))
2470 /* If this is a REG_DEAD note, it is not valid anymore.
2471 Using the eliminated version could result in creating a
2472 REG_DEAD note for the stack or frame pointer. */
2473 if (GET_MODE (x) == REG_DEAD)
2475 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2478 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2482 /* ... fall through ... */
2485 /* Now do eliminations in the rest of the chain. If this was
2486 an EXPR_LIST, this might result in allocating more memory than is
2487 strictly needed, but it simplifies the code. */
2490 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2491 if (new != XEXP (x, 1))
2493 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2501 case STRICT_LOW_PART:
2503 case SIGN_EXTEND: case ZERO_EXTEND:
2504 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2505 case FLOAT: case FIX:
2506 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2510 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2511 if (new != XEXP (x, 0))
2512 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2516 /* Similar to above processing, but preserve SUBREG_BYTE.
2517 Convert (subreg (mem)) to (mem) if not paradoxical.
2518 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2519 pseudo didn't get a hard reg, we must replace this with the
2520 eliminated version of the memory location because push_reloads
2521 may do the replacement in certain circumstances. */
2522 if (GET_CODE (SUBREG_REG (x)) == REG
2523 && (GET_MODE_SIZE (GET_MODE (x))
2524 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2525 && reg_equiv_memory_loc != 0
2526 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2528 new = SUBREG_REG (x);
2531 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2533 if (new != SUBREG_REG (x))
2535 int x_size = GET_MODE_SIZE (GET_MODE (x));
2536 int new_size = GET_MODE_SIZE (GET_MODE (new));
2538 if (GET_CODE (new) == MEM
2539 && ((x_size < new_size
2540 #ifdef WORD_REGISTER_OPERATIONS
2541 /* On these machines, combine can create rtl of the form
2542 (set (subreg:m1 (reg:m2 R) 0) ...)
2543 where m1 < m2, and expects something interesting to
2544 happen to the entire word. Moreover, it will use the
2545 (reg:m2 R) later, expecting all bits to be preserved.
2546 So if the number of words is the same, preserve the
2547 subreg so that push_reloads can see it. */
2548 && ! ((x_size - 1) / UNITS_PER_WORD
2549 == (new_size -1 ) / UNITS_PER_WORD)
2552 || x_size == new_size)
2555 int offset = SUBREG_BYTE (x);
2556 enum machine_mode mode = GET_MODE (x);
2558 PUT_MODE (new, mode);
2559 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2563 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2569 /* This is only for the benefit of the debugging backends, which call
2570 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2571 removed after CSE. */
2572 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2573 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2575 /* Our only special processing is to pass the mode of the MEM to our
2576 recursive call and copy the flags. While we are here, handle this
2577 case more efficiently. */
2579 replace_equiv_address_nv (x,
2580 eliminate_regs (XEXP (x, 0),
2581 GET_MODE (x), insn));
2584 /* Handle insn_list USE that a call to a pure function may generate. */
2585 new = eliminate_regs (XEXP (x, 0), 0, insn);
2586 if (new != XEXP (x, 0))
2587 return gen_rtx_USE (GET_MODE (x), new);
2599 /* Process each of our operands recursively. If any have changed, make a
2601 fmt = GET_RTX_FORMAT (code);
2602 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2606 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2607 if (new != XEXP (x, i) && ! copied)
2609 rtx new_x = rtx_alloc (code);
2611 (sizeof (*new_x) - sizeof (new_x->fld)
2612 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2618 else if (*fmt == 'E')
2621 for (j = 0; j < XVECLEN (x, i); j++)
2623 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2624 if (new != XVECEXP (x, i, j) && ! copied_vec)
2626 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2630 rtx new_x = rtx_alloc (code);
2632 (sizeof (*new_x) - sizeof (new_x->fld)
2633 + (sizeof (new_x->fld[0])
2634 * GET_RTX_LENGTH (code))));
2638 XVEC (x, i) = new_v;
2641 XVECEXP (x, i, j) = new;
2649 /* Scan rtx X for modifications of elimination target registers. Update
2650 the table of eliminables to reflect the changed state. MEM_MODE is
2651 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2654 elimination_effects (x, mem_mode)
2656 enum machine_mode mem_mode;
2659 enum rtx_code code = GET_CODE (x);
2660 struct elim_table *ep;
2686 /* First handle the case where we encounter a bare register that
2687 is eliminable. Replace it with a PLUS. */
2688 if (regno < FIRST_PSEUDO_REGISTER)
2690 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2692 if (ep->from_rtx == x && ep->can_eliminate)
2695 ep->ref_outside_mem = 1;
2700 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2701 && reg_equiv_constant[regno]
2702 && ! function_invariant_p (reg_equiv_constant[regno]))
2703 elimination_effects (reg_equiv_constant[regno], mem_mode);
2712 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2713 if (ep->to_rtx == XEXP (x, 0))
2715 int size = GET_MODE_SIZE (mem_mode);
2717 /* If more bytes than MEM_MODE are pushed, account for them. */
2718 #ifdef PUSH_ROUNDING
2719 if (ep->to_rtx == stack_pointer_rtx)
2720 size = PUSH_ROUNDING (size);
2722 if (code == PRE_DEC || code == POST_DEC)
2724 else if (code == PRE_INC || code == POST_INC)
2726 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2727 && GET_CODE (XEXP (x, 1)) == PLUS
2728 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2729 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2730 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2733 /* These two aren't unary operators. */
2734 if (code == POST_MODIFY || code == PRE_MODIFY)
2737 /* Fall through to generic unary operation case. */
2738 case STRICT_LOW_PART:
2740 case SIGN_EXTEND: case ZERO_EXTEND:
2741 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2742 case FLOAT: case FIX:
2743 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2747 elimination_effects (XEXP (x, 0), mem_mode);
2751 if (GET_CODE (SUBREG_REG (x)) == REG
2752 && (GET_MODE_SIZE (GET_MODE (x))
2753 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2754 && reg_equiv_memory_loc != 0
2755 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2758 elimination_effects (SUBREG_REG (x), mem_mode);
2762 /* If using a register that is the source of an eliminate we still
2763 think can be performed, note it cannot be performed since we don't
2764 know how this register is used. */
2765 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2766 if (ep->from_rtx == XEXP (x, 0))
2767 ep->can_eliminate = 0;
2769 elimination_effects (XEXP (x, 0), mem_mode);
2773 /* If clobbering a register that is the replacement register for an
2774 elimination we still think can be performed, note that it cannot
2775 be performed. Otherwise, we need not be concerned about it. */
2776 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2777 if (ep->to_rtx == XEXP (x, 0))
2778 ep->can_eliminate = 0;
2780 elimination_effects (XEXP (x, 0), mem_mode);
2784 /* Check for setting a register that we know about. */
2785 if (GET_CODE (SET_DEST (x)) == REG)
2787 /* See if this is setting the replacement register for an
2790 If DEST is the hard frame pointer, we do nothing because we
2791 assume that all assignments to the frame pointer are for
2792 non-local gotos and are being done at a time when they are valid
2793 and do not disturb anything else. Some machines want to
2794 eliminate a fake argument pointer (or even a fake frame pointer)
2795 with either the real frame or the stack pointer. Assignments to
2796 the hard frame pointer must not prevent this elimination. */
2798 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2800 if (ep->to_rtx == SET_DEST (x)
2801 && SET_DEST (x) != hard_frame_pointer_rtx)
2803 /* If it is being incremented, adjust the offset. Otherwise,
2804 this elimination can't be done. */
2805 rtx src = SET_SRC (x);
2807 if (GET_CODE (src) == PLUS
2808 && XEXP (src, 0) == SET_DEST (x)
2809 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2810 ep->offset -= INTVAL (XEXP (src, 1));
2812 ep->can_eliminate = 0;
2816 elimination_effects (SET_DEST (x), 0);
2817 elimination_effects (SET_SRC (x), 0);
2821 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2824 /* Our only special processing is to pass the mode of the MEM to our
2826 elimination_effects (XEXP (x, 0), GET_MODE (x));
2833 fmt = GET_RTX_FORMAT (code);
2834 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2837 elimination_effects (XEXP (x, i), mem_mode);
2838 else if (*fmt == 'E')
2839 for (j = 0; j < XVECLEN (x, i); j++)
2840 elimination_effects (XVECEXP (x, i, j), mem_mode);
2844 /* Descend through rtx X and verify that no references to eliminable registers
2845 remain. If any do remain, mark the involved register as not
2849 check_eliminable_occurrences (x)
2859 code = GET_CODE (x);
2861 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2863 struct elim_table *ep;
2865 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2866 if (ep->from_rtx == x && ep->can_eliminate)
2867 ep->can_eliminate = 0;
2871 fmt = GET_RTX_FORMAT (code);
2872 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2875 check_eliminable_occurrences (XEXP (x, i));
2876 else if (*fmt == 'E')
2879 for (j = 0; j < XVECLEN (x, i); j++)
2880 check_eliminable_occurrences (XVECEXP (x, i, j));
2885 /* Scan INSN and eliminate all eliminable registers in it.
2887 If REPLACE is nonzero, do the replacement destructively. Also
2888 delete the insn as dead it if it is setting an eliminable register.
2890 If REPLACE is zero, do all our allocations in reload_obstack.
2892 If no eliminations were done and this insn doesn't require any elimination
2893 processing (these are not identical conditions: it might be updating sp,
2894 but not referencing fp; this needs to be seen during reload_as_needed so
2895 that the offset between fp and sp can be taken into consideration), zero
2896 is returned. Otherwise, 1 is returned. */
2899 eliminate_regs_in_insn (insn, replace)
2903 int icode = recog_memoized (insn);
2904 rtx old_body = PATTERN (insn);
2905 int insn_is_asm = asm_noperands (old_body) >= 0;
2906 rtx old_set = single_set (insn);
2910 rtx substed_operand[MAX_RECOG_OPERANDS];
2911 rtx orig_operand[MAX_RECOG_OPERANDS];
2912 struct elim_table *ep;
2914 if (! insn_is_asm && icode < 0)
2916 if (GET_CODE (PATTERN (insn)) == USE
2917 || GET_CODE (PATTERN (insn)) == CLOBBER
2918 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2919 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2920 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2925 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2926 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2928 /* Check for setting an eliminable register. */
2929 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2930 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2932 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2933 /* If this is setting the frame pointer register to the
2934 hardware frame pointer register and this is an elimination
2935 that will be done (tested above), this insn is really
2936 adjusting the frame pointer downward to compensate for
2937 the adjustment done before a nonlocal goto. */
2938 if (ep->from == FRAME_POINTER_REGNUM
2939 && ep->to == HARD_FRAME_POINTER_REGNUM)
2941 rtx src = SET_SRC (old_set);
2942 int offset = 0, ok = 0;
2943 rtx prev_insn, prev_set;
2945 if (src == ep->to_rtx)
2947 else if (GET_CODE (src) == PLUS
2948 && GET_CODE (XEXP (src, 0)) == CONST_INT
2949 && XEXP (src, 1) == ep->to_rtx)
2950 offset = INTVAL (XEXP (src, 0)), ok = 1;
2951 else if (GET_CODE (src) == PLUS
2952 && GET_CODE (XEXP (src, 1)) == CONST_INT
2953 && XEXP (src, 0) == ep->to_rtx)
2954 offset = INTVAL (XEXP (src, 1)), ok = 1;
2955 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2956 && (prev_set = single_set (prev_insn)) != 0
2957 && rtx_equal_p (SET_DEST (prev_set), src))
2959 src = SET_SRC (prev_set);
2960 if (src == ep->to_rtx)
2962 else if (GET_CODE (src) == PLUS
2963 && GET_CODE (XEXP (src, 0)) == CONST_INT
2964 && XEXP (src, 1) == ep->to_rtx)
2965 offset = INTVAL (XEXP (src, 0)), ok = 1;
2966 else if (GET_CODE (src) == PLUS
2967 && GET_CODE (XEXP (src, 1)) == CONST_INT
2968 && XEXP (src, 0) == ep->to_rtx)
2969 offset = INTVAL (XEXP (src, 1)), ok = 1;
2975 = plus_constant (ep->to_rtx, offset - ep->offset);
2977 new_body = old_body;
2980 new_body = copy_insn (old_body);
2981 if (REG_NOTES (insn))
2982 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2984 PATTERN (insn) = new_body;
2985 old_set = single_set (insn);
2987 /* First see if this insn remains valid when we
2988 make the change. If not, keep the INSN_CODE
2989 the same and let reload fit it up. */
2990 validate_change (insn, &SET_SRC (old_set), src, 1);
2991 validate_change (insn, &SET_DEST (old_set),
2993 if (! apply_change_group ())
2995 SET_SRC (old_set) = src;
2996 SET_DEST (old_set) = ep->to_rtx;
3005 /* In this case this insn isn't serving a useful purpose. We
3006 will delete it in reload_as_needed once we know that this
3007 elimination is, in fact, being done.
3009 If REPLACE isn't set, we can't delete this insn, but needn't
3010 process it since it won't be used unless something changes. */
3013 delete_dead_insn (insn);
3021 /* We allow one special case which happens to work on all machines we
3022 currently support: a single set with the source being a PLUS of an
3023 eliminable register and a constant. */
3025 && GET_CODE (SET_DEST (old_set)) == REG
3026 && GET_CODE (SET_SRC (old_set)) == PLUS
3027 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3028 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3029 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3031 rtx reg = XEXP (SET_SRC (old_set), 0);
3032 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3034 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3035 if (ep->from_rtx == reg && ep->can_eliminate)
3037 offset += ep->offset;
3042 /* We assume here that if we need a PARALLEL with
3043 CLOBBERs for this assignment, we can do with the
3044 MATCH_SCRATCHes that add_clobbers allocates.
3045 There's not much we can do if that doesn't work. */
3046 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3050 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3053 rtvec vec = rtvec_alloc (num_clobbers + 1);
3055 vec->elem[0] = PATTERN (insn);
3056 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3057 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3059 if (INSN_CODE (insn) < 0)
3064 new_body = old_body;
3067 new_body = copy_insn (old_body);
3068 if (REG_NOTES (insn))
3069 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3071 PATTERN (insn) = new_body;
3072 old_set = single_set (insn);
3074 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3075 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3078 /* This can't have an effect on elimination offsets, so skip right
3084 /* Determine the effects of this insn on elimination offsets. */
3085 elimination_effects (old_body, 0);
3087 /* Eliminate all eliminable registers occurring in operands that
3088 can be handled by reload. */
3089 extract_insn (insn);
3091 for (i = 0; i < recog_data.n_operands; i++)
3093 orig_operand[i] = recog_data.operand[i];
3094 substed_operand[i] = recog_data.operand[i];
3096 /* For an asm statement, every operand is eliminable. */
3097 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3099 /* Check for setting a register that we know about. */
3100 if (recog_data.operand_type[i] != OP_IN
3101 && GET_CODE (orig_operand[i]) == REG)
3103 /* If we are assigning to a register that can be eliminated, it
3104 must be as part of a PARALLEL, since the code above handles
3105 single SETs. We must indicate that we can no longer
3106 eliminate this reg. */
3107 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3109 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3110 ep->can_eliminate = 0;
3113 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3114 replace ? insn : NULL_RTX);
3115 if (substed_operand[i] != orig_operand[i])
3116 val = any_changes = 1;
3117 /* Terminate the search in check_eliminable_occurrences at
3119 *recog_data.operand_loc[i] = 0;
3121 /* If an output operand changed from a REG to a MEM and INSN is an
3122 insn, write a CLOBBER insn. */
3123 if (recog_data.operand_type[i] != OP_IN
3124 && GET_CODE (orig_operand[i]) == REG
3125 && GET_CODE (substed_operand[i]) == MEM
3127 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3132 for (i = 0; i < recog_data.n_dups; i++)
3133 *recog_data.dup_loc[i]
3134 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3136 /* If any eliminable remain, they aren't eliminable anymore. */
3137 check_eliminable_occurrences (old_body);
3139 /* Substitute the operands; the new values are in the substed_operand
3141 for (i = 0; i < recog_data.n_operands; i++)
3142 *recog_data.operand_loc[i] = substed_operand[i];
3143 for (i = 0; i < recog_data.n_dups; i++)
3144 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3146 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3147 re-recognize the insn. We do this in case we had a simple addition
3148 but now can do this as a load-address. This saves an insn in this
3150 If re-recognition fails, the old insn code number will still be used,
3151 and some register operands may have changed into PLUS expressions.
3152 These will be handled by find_reloads by loading them into a register
3157 /* If we aren't replacing things permanently and we changed something,
3158 make another copy to ensure that all the RTL is new. Otherwise
3159 things can go wrong if find_reload swaps commutative operands
3160 and one is inside RTL that has been copied while the other is not. */
3161 new_body = old_body;
3164 new_body = copy_insn (old_body);
3165 if (REG_NOTES (insn))
3166 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3168 PATTERN (insn) = new_body;
3170 /* If we had a move insn but now we don't, rerecognize it. This will
3171 cause spurious re-recognition if the old move had a PARALLEL since
3172 the new one still will, but we can't call single_set without
3173 having put NEW_BODY into the insn and the re-recognition won't
3174 hurt in this rare case. */
3175 /* ??? Why this huge if statement - why don't we just rerecognize the
3179 && ((GET_CODE (SET_SRC (old_set)) == REG
3180 && (GET_CODE (new_body) != SET
3181 || GET_CODE (SET_SRC (new_body)) != REG))
3182 /* If this was a load from or store to memory, compare
3183 the MEM in recog_data.operand to the one in the insn.
3184 If they are not equal, then rerecognize the insn. */
3186 && ((GET_CODE (SET_SRC (old_set)) == MEM
3187 && SET_SRC (old_set) != recog_data.operand[1])
3188 || (GET_CODE (SET_DEST (old_set)) == MEM
3189 && SET_DEST (old_set) != recog_data.operand[0])))
3190 /* If this was an add insn before, rerecognize. */
3191 || GET_CODE (SET_SRC (old_set)) == PLUS))
3193 int new_icode = recog (PATTERN (insn), insn, 0);
3195 INSN_CODE (insn) = icode;
3199 /* Restore the old body. If there were any changes to it, we made a copy
3200 of it while the changes were still in place, so we'll correctly return
3201 a modified insn below. */
3204 /* Restore the old body. */
3205 for (i = 0; i < recog_data.n_operands; i++)
3206 *recog_data.operand_loc[i] = orig_operand[i];
3207 for (i = 0; i < recog_data.n_dups; i++)
3208 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3211 /* Update all elimination pairs to reflect the status after the current
3212 insn. The changes we make were determined by the earlier call to
3213 elimination_effects.
3215 We also detect a cases where register elimination cannot be done,
3216 namely, if a register would be both changed and referenced outside a MEM
3217 in the resulting insn since such an insn is often undefined and, even if
3218 not, we cannot know what meaning will be given to it. Note that it is
3219 valid to have a register used in an address in an insn that changes it
3220 (presumably with a pre- or post-increment or decrement).
3222 If anything changes, return nonzero. */
3224 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3226 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3227 ep->can_eliminate = 0;
3229 ep->ref_outside_mem = 0;
3231 if (ep->previous_offset != ep->offset)
3236 /* If we changed something, perform elimination in REG_NOTES. This is
3237 needed even when REPLACE is zero because a REG_DEAD note might refer
3238 to a register that we eliminate and could cause a different number
3239 of spill registers to be needed in the final reload pass than in
3241 if (val && REG_NOTES (insn) != 0)
3242 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3247 /* Loop through all elimination pairs.
3248 Recalculate the number not at initial offset.
3250 Compute the maximum offset (minimum offset if the stack does not
3251 grow downward) for each elimination pair. */
3254 update_eliminable_offsets ()
3256 struct elim_table *ep;
3258 num_not_at_initial_offset = 0;
3259 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3261 ep->previous_offset = ep->offset;
3262 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3263 num_not_at_initial_offset++;
3267 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3268 replacement we currently believe is valid, mark it as not eliminable if X
3269 modifies DEST in any way other than by adding a constant integer to it.
3271 If DEST is the frame pointer, we do nothing because we assume that
3272 all assignments to the hard frame pointer are nonlocal gotos and are being
3273 done at a time when they are valid and do not disturb anything else.
3274 Some machines want to eliminate a fake argument pointer with either the
3275 frame or stack pointer. Assignments to the hard frame pointer must not
3276 prevent this elimination.
3278 Called via note_stores from reload before starting its passes to scan
3279 the insns of the function. */
3282 mark_not_eliminable (dest, x, data)
3285 void *data ATTRIBUTE_UNUSED;
3289 /* A SUBREG of a hard register here is just changing its mode. We should
3290 not see a SUBREG of an eliminable hard register, but check just in
3292 if (GET_CODE (dest) == SUBREG)
3293 dest = SUBREG_REG (dest);
3295 if (dest == hard_frame_pointer_rtx)
3298 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3299 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3300 && (GET_CODE (x) != SET
3301 || GET_CODE (SET_SRC (x)) != PLUS
3302 || XEXP (SET_SRC (x), 0) != dest
3303 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3305 reg_eliminate[i].can_eliminate_previous
3306 = reg_eliminate[i].can_eliminate = 0;
3311 /* Verify that the initial elimination offsets did not change since the
3312 last call to set_initial_elim_offsets. This is used to catch cases
3313 where something illegal happened during reload_as_needed that could
3314 cause incorrect code to be generated if we did not check for it. */
3317 verify_initial_elim_offsets ()
3321 #ifdef ELIMINABLE_REGS
3322 struct elim_table *ep;
3324 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3326 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3327 if (t != ep->initial_offset)
3331 INITIAL_FRAME_POINTER_OFFSET (t);
3332 if (t != reg_eliminate[0].initial_offset)
3337 /* Reset all offsets on eliminable registers to their initial values. */
3340 set_initial_elim_offsets ()
3342 struct elim_table *ep = reg_eliminate;
3344 #ifdef ELIMINABLE_REGS
3345 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3347 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3348 ep->previous_offset = ep->offset = ep->initial_offset;
3351 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3352 ep->previous_offset = ep->offset = ep->initial_offset;
3355 num_not_at_initial_offset = 0;
3358 /* Initialize the known label offsets.
3359 Set a known offset for each forced label to be at the initial offset
3360 of each elimination. We do this because we assume that all
3361 computed jumps occur from a location where each elimination is
3362 at its initial offset.
3363 For all other labels, show that we don't know the offsets. */
3366 set_initial_label_offsets ()
3369 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3371 for (x = forced_labels; x; x = XEXP (x, 1))
3373 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3376 /* Set all elimination offsets to the known values for the code label given
3380 set_offsets_for_label (insn)
3384 int label_nr = CODE_LABEL_NUMBER (insn);
3385 struct elim_table *ep;
3387 num_not_at_initial_offset = 0;
3388 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3390 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3391 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3392 num_not_at_initial_offset++;
3396 /* See if anything that happened changes which eliminations are valid.
3397 For example, on the Sparc, whether or not the frame pointer can
3398 be eliminated can depend on what registers have been used. We need
3399 not check some conditions again (such as flag_omit_frame_pointer)
3400 since they can't have changed. */
3403 update_eliminables (pset)
3406 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3407 int previous_frame_pointer_needed = frame_pointer_needed;
3409 struct elim_table *ep;
3411 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3412 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3413 #ifdef ELIMINABLE_REGS
3414 || ! CAN_ELIMINATE (ep->from, ep->to)
3417 ep->can_eliminate = 0;
3419 /* Look for the case where we have discovered that we can't replace
3420 register A with register B and that means that we will now be
3421 trying to replace register A with register C. This means we can
3422 no longer replace register C with register B and we need to disable
3423 such an elimination, if it exists. This occurs often with A == ap,
3424 B == sp, and C == fp. */
3426 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3428 struct elim_table *op;
3431 if (! ep->can_eliminate && ep->can_eliminate_previous)
3433 /* Find the current elimination for ep->from, if there is a
3435 for (op = reg_eliminate;
3436 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3437 if (op->from == ep->from && op->can_eliminate)
3443 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3445 for (op = reg_eliminate;
3446 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3447 if (op->from == new_to && op->to == ep->to)
3448 op->can_eliminate = 0;
3452 /* See if any registers that we thought we could eliminate the previous
3453 time are no longer eliminable. If so, something has changed and we
3454 must spill the register. Also, recompute the number of eliminable
3455 registers and see if the frame pointer is needed; it is if there is
3456 no elimination of the frame pointer that we can perform. */
3458 frame_pointer_needed = 1;
3459 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3461 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3462 && ep->to != HARD_FRAME_POINTER_REGNUM)
3463 frame_pointer_needed = 0;
3465 if (! ep->can_eliminate && ep->can_eliminate_previous)
3467 ep->can_eliminate_previous = 0;
3468 SET_HARD_REG_BIT (*pset, ep->from);
3473 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3474 /* If we didn't need a frame pointer last time, but we do now, spill
3475 the hard frame pointer. */
3476 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3477 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3481 /* Initialize the table of registers to eliminate. */
3486 struct elim_table *ep;
3487 #ifdef ELIMINABLE_REGS
3488 struct elim_table_1 *ep1;
3492 reg_eliminate = (struct elim_table *)
3493 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3495 /* Does this function require a frame pointer? */
3497 frame_pointer_needed = (! flag_omit_frame_pointer
3498 #ifdef EXIT_IGNORE_STACK
3499 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3500 and restore sp for alloca. So we can't eliminate
3501 the frame pointer in that case. At some point,
3502 we should improve this by emitting the
3503 sp-adjusting insns for this case. */
3504 || (current_function_calls_alloca
3505 && EXIT_IGNORE_STACK)
3507 || FRAME_POINTER_REQUIRED);
3511 #ifdef ELIMINABLE_REGS
3512 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3513 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3515 ep->from = ep1->from;
3517 ep->can_eliminate = ep->can_eliminate_previous
3518 = (CAN_ELIMINATE (ep->from, ep->to)
3519 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3522 reg_eliminate[0].from = reg_eliminate_1[0].from;
3523 reg_eliminate[0].to = reg_eliminate_1[0].to;
3524 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3525 = ! frame_pointer_needed;
3528 /* Count the number of eliminable registers and build the FROM and TO
3529 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3530 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3531 We depend on this. */
3532 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3534 num_eliminable += ep->can_eliminate;
3535 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3536 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3540 /* Kick all pseudos out of hard register REGNO.
3542 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3543 because we found we can't eliminate some register. In the case, no pseudos
3544 are allowed to be in the register, even if they are only in a block that
3545 doesn't require spill registers, unlike the case when we are spilling this
3546 hard reg to produce another spill register.
3548 Return nonzero if any pseudos needed to be kicked out. */
3551 spill_hard_reg (regno, cant_eliminate)
3559 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3560 regs_ever_live[regno] = 1;
3563 /* Spill every pseudo reg that was allocated to this reg
3564 or to something that overlaps this reg. */
3566 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3567 if (reg_renumber[i] >= 0
3568 && (unsigned int) reg_renumber[i] <= regno
3569 && ((unsigned int) reg_renumber[i]
3570 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3571 PSEUDO_REGNO_MODE (i))
3573 SET_REGNO_REG_SET (&spilled_pseudos, i);
3576 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3577 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3580 ior_hard_reg_set (set1, set2)
3581 HARD_REG_SET *set1, *set2;
3583 IOR_HARD_REG_SET (*set1, *set2);
3586 /* After find_reload_regs has been run for all insn that need reloads,
3587 and/or spill_hard_regs was called, this function is used to actually
3588 spill pseudo registers and try to reallocate them. It also sets up the
3589 spill_regs array for use by choose_reload_regs. */
3592 finish_spills (global)
3595 struct insn_chain *chain;
3596 int something_changed = 0;
3599 /* Build the spill_regs array for the function. */
3600 /* If there are some registers still to eliminate and one of the spill regs
3601 wasn't ever used before, additional stack space may have to be
3602 allocated to store this register. Thus, we may have changed the offset
3603 between the stack and frame pointers, so mark that something has changed.
3605 One might think that we need only set VAL to 1 if this is a call-used
3606 register. However, the set of registers that must be saved by the
3607 prologue is not identical to the call-used set. For example, the
3608 register used by the call insn for the return PC is a call-used register,
3609 but must be saved by the prologue. */
3612 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3613 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3615 spill_reg_order[i] = n_spills;
3616 spill_regs[n_spills++] = i;
3617 if (num_eliminable && ! regs_ever_live[i])
3618 something_changed = 1;
3619 regs_ever_live[i] = 1;
3622 spill_reg_order[i] = -1;
3624 EXECUTE_IF_SET_IN_REG_SET
3625 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3627 /* Record the current hard register the pseudo is allocated to in
3628 pseudo_previous_regs so we avoid reallocating it to the same
3629 hard reg in a later pass. */
3630 if (reg_renumber[i] < 0)
3633 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3634 /* Mark it as no longer having a hard register home. */
3635 reg_renumber[i] = -1;
3636 /* We will need to scan everything again. */
3637 something_changed = 1;
3640 /* Retry global register allocation if possible. */
3643 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3644 /* For every insn that needs reloads, set the registers used as spill
3645 regs in pseudo_forbidden_regs for every pseudo live across the
3647 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3649 EXECUTE_IF_SET_IN_REG_SET
3650 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3652 ior_hard_reg_set (pseudo_forbidden_regs + i,
3653 &chain->used_spill_regs);
3655 EXECUTE_IF_SET_IN_REG_SET
3656 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3658 ior_hard_reg_set (pseudo_forbidden_regs + i,
3659 &chain->used_spill_regs);
3663 /* Retry allocating the spilled pseudos. For each reg, merge the
3664 various reg sets that indicate which hard regs can't be used,
3665 and call retry_global_alloc.
3666 We change spill_pseudos here to only contain pseudos that did not
3667 get a new hard register. */
3668 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3669 if (reg_old_renumber[i] != reg_renumber[i])
3671 HARD_REG_SET forbidden;
3672 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3673 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3674 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3675 retry_global_alloc (i, forbidden);
3676 if (reg_renumber[i] >= 0)
3677 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3681 /* Fix up the register information in the insn chain.
3682 This involves deleting those of the spilled pseudos which did not get
3683 a new hard register home from the live_{before,after} sets. */
3684 for (chain = reload_insn_chain; chain; chain = chain->next)
3686 HARD_REG_SET used_by_pseudos;
3687 HARD_REG_SET used_by_pseudos2;
3689 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3690 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3692 /* Mark any unallocated hard regs as available for spills. That
3693 makes inheritance work somewhat better. */
3694 if (chain->need_reload)
3696 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3697 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3698 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3700 /* Save the old value for the sanity test below. */
3701 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3703 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3704 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3705 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3706 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3708 /* Make sure we only enlarge the set. */
3709 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3715 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3716 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3718 int regno = reg_renumber[i];
3719 if (reg_old_renumber[i] == regno)
3722 alter_reg (i, reg_old_renumber[i]);
3723 reg_old_renumber[i] = regno;
3727 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3729 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3730 i, reg_renumber[i]);
3734 return something_changed;
3737 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3738 Also mark any hard registers used to store user variables as
3739 forbidden from being used for spill registers. */
3742 scan_paradoxical_subregs (x)
3747 enum rtx_code code = GET_CODE (x);
3753 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3754 && REG_USERVAR_P (x))
3755 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3771 if (GET_CODE (SUBREG_REG (x)) == REG
3772 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3773 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3774 = GET_MODE_SIZE (GET_MODE (x));
3781 fmt = GET_RTX_FORMAT (code);
3782 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3785 scan_paradoxical_subregs (XEXP (x, i));
3786 else if (fmt[i] == 'E')
3789 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3790 scan_paradoxical_subregs (XVECEXP (x, i, j));
3795 /* Reload pseudo-registers into hard regs around each insn as needed.
3796 Additional register load insns are output before the insn that needs it
3797 and perhaps store insns after insns that modify the reloaded pseudo reg.
3799 reg_last_reload_reg and reg_reloaded_contents keep track of
3800 which registers are already available in reload registers.
3801 We update these for the reloads that we perform,
3802 as the insns are scanned. */
3805 reload_as_needed (live_known)
3808 struct insn_chain *chain;
3809 #if defined (AUTO_INC_DEC)
3814 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3815 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3816 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3817 reg_has_output_reload = (char *) xmalloc (max_regno);
3818 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3820 set_initial_elim_offsets ();
3822 for (chain = reload_insn_chain; chain; chain = chain->next)
3825 rtx insn = chain->insn;
3826 rtx old_next = NEXT_INSN (insn);
3828 /* If we pass a label, copy the offsets from the label information
3829 into the current offsets of each elimination. */
3830 if (GET_CODE (insn) == CODE_LABEL)
3831 set_offsets_for_label (insn);
3833 else if (INSN_P (insn))
3835 rtx oldpat = PATTERN (insn);
3837 /* If this is a USE and CLOBBER of a MEM, ensure that any
3838 references to eliminable registers have been removed. */
3840 if ((GET_CODE (PATTERN (insn)) == USE
3841 || GET_CODE (PATTERN (insn)) == CLOBBER)
3842 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3843 XEXP (XEXP (PATTERN (insn), 0), 0)
3844 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3845 GET_MODE (XEXP (PATTERN (insn), 0)),
3848 /* If we need to do register elimination processing, do so.
3849 This might delete the insn, in which case we are done. */
3850 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3852 eliminate_regs_in_insn (insn, 1);
3853 if (GET_CODE (insn) == NOTE)
3855 update_eliminable_offsets ();
3860 /* If need_elim is nonzero but need_reload is zero, one might think
3861 that we could simply set n_reloads to 0. However, find_reloads
3862 could have done some manipulation of the insn (such as swapping
3863 commutative operands), and these manipulations are lost during
3864 the first pass for every insn that needs register elimination.
3865 So the actions of find_reloads must be redone here. */
3867 if (! chain->need_elim && ! chain->need_reload
3868 && ! chain->need_operand_change)
3870 /* First find the pseudo regs that must be reloaded for this insn.
3871 This info is returned in the tables reload_... (see reload.h).
3872 Also modify the body of INSN by substituting RELOAD
3873 rtx's for those pseudo regs. */
3876 memset (reg_has_output_reload, 0, max_regno);
3877 CLEAR_HARD_REG_SET (reg_is_output_reload);
3879 find_reloads (insn, 1, spill_indirect_levels, live_known,
3885 rtx next = NEXT_INSN (insn);
3888 prev = PREV_INSN (insn);
3890 /* Now compute which reload regs to reload them into. Perhaps
3891 reusing reload regs from previous insns, or else output
3892 load insns to reload them. Maybe output store insns too.
3893 Record the choices of reload reg in reload_reg_rtx. */
3894 choose_reload_regs (chain);
3896 /* Merge any reloads that we didn't combine for fear of
3897 increasing the number of spill registers needed but now
3898 discover can be safely merged. */
3899 if (SMALL_REGISTER_CLASSES)
3900 merge_assigned_reloads (insn);
3902 /* Generate the insns to reload operands into or out of
3903 their reload regs. */
3904 emit_reload_insns (chain);
3906 /* Substitute the chosen reload regs from reload_reg_rtx
3907 into the insn's body (or perhaps into the bodies of other
3908 load and store insn that we just made for reloading
3909 and that we moved the structure into). */
3910 subst_reloads (insn);
3912 /* If this was an ASM, make sure that all the reload insns
3913 we have generated are valid. If not, give an error
3916 if (asm_noperands (PATTERN (insn)) >= 0)
3917 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3918 if (p != insn && INSN_P (p)
3919 && (recog_memoized (p) < 0
3920 || (extract_insn (p), ! constrain_operands (1))))
3922 error_for_asm (insn,
3923 "`asm' operand requires impossible reload");
3928 if (num_eliminable && chain->need_elim)
3929 update_eliminable_offsets ();
3931 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3932 is no longer validly lying around to save a future reload.
3933 Note that this does not detect pseudos that were reloaded
3934 for this insn in order to be stored in
3935 (obeying register constraints). That is correct; such reload
3936 registers ARE still valid. */
3937 note_stores (oldpat, forget_old_reloads_1, NULL);
3939 /* There may have been CLOBBER insns placed after INSN. So scan
3940 between INSN and NEXT and use them to forget old reloads. */
3941 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3942 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3943 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3946 /* Likewise for regs altered by auto-increment in this insn.
3947 REG_INC notes have been changed by reloading:
3948 find_reloads_address_1 records substitutions for them,
3949 which have been performed by subst_reloads above. */
3950 for (i = n_reloads - 1; i >= 0; i--)
3952 rtx in_reg = rld[i].in_reg;
3955 enum rtx_code code = GET_CODE (in_reg);
3956 /* PRE_INC / PRE_DEC will have the reload register ending up
3957 with the same value as the stack slot, but that doesn't
3958 hold true for POST_INC / POST_DEC. Either we have to
3959 convert the memory access to a true POST_INC / POST_DEC,
3960 or we can't use the reload register for inheritance. */
3961 if ((code == POST_INC || code == POST_DEC)
3962 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3963 REGNO (rld[i].reg_rtx))
3964 /* Make sure it is the inc/dec pseudo, and not
3965 some other (e.g. output operand) pseudo. */
3966 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3967 == REGNO (XEXP (in_reg, 0))))
3970 rtx reload_reg = rld[i].reg_rtx;
3971 enum machine_mode mode = GET_MODE (reload_reg);
3975 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3977 /* We really want to ignore REG_INC notes here, so
3978 use PATTERN (p) as argument to reg_set_p . */
3979 if (reg_set_p (reload_reg, PATTERN (p)))
3981 n = count_occurrences (PATTERN (p), reload_reg, 0);
3986 n = validate_replace_rtx (reload_reg,
3987 gen_rtx (code, mode,
3991 /* We must also verify that the constraints
3992 are met after the replacement. */
3995 n = constrain_operands (1);
3999 /* If the constraints were not met, then
4000 undo the replacement. */
4003 validate_replace_rtx (gen_rtx (code, mode,
4015 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4017 /* Mark this as having an output reload so that the
4018 REG_INC processing code below won't invalidate
4019 the reload for inheritance. */
4020 SET_HARD_REG_BIT (reg_is_output_reload,
4021 REGNO (reload_reg));
4022 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4025 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4028 else if ((code == PRE_INC || code == PRE_DEC)
4029 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4030 REGNO (rld[i].reg_rtx))
4031 /* Make sure it is the inc/dec pseudo, and not
4032 some other (e.g. output operand) pseudo. */
4033 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4034 == REGNO (XEXP (in_reg, 0))))
4036 SET_HARD_REG_BIT (reg_is_output_reload,
4037 REGNO (rld[i].reg_rtx));
4038 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4042 /* If a pseudo that got a hard register is auto-incremented,
4043 we must purge records of copying it into pseudos without
4045 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4046 if (REG_NOTE_KIND (x) == REG_INC)
4048 /* See if this pseudo reg was reloaded in this insn.
4049 If so, its last-reload info is still valid
4050 because it is based on this insn's reload. */
4051 for (i = 0; i < n_reloads; i++)
4052 if (rld[i].out == XEXP (x, 0))
4056 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4060 /* A reload reg's contents are unknown after a label. */
4061 if (GET_CODE (insn) == CODE_LABEL)
4062 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4064 /* Don't assume a reload reg is still good after a call insn
4065 if it is a call-used reg. */
4066 else if (GET_CODE (insn) == CALL_INSN)
4067 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4071 free (reg_last_reload_reg);
4072 free (reg_has_output_reload);
4075 /* Discard all record of any value reloaded from X,
4076 or reloaded in X from someplace else;
4077 unless X is an output reload reg of the current insn.
4079 X may be a hard reg (the reload reg)
4080 or it may be a pseudo reg that was reloaded from. */
4083 forget_old_reloads_1 (x, ignored, data)
4085 rtx ignored ATTRIBUTE_UNUSED;
4086 void *data ATTRIBUTE_UNUSED;
4092 /* note_stores does give us subregs of hard regs,
4093 subreg_regno_offset will abort if it is not a hard reg. */
4094 while (GET_CODE (x) == SUBREG)
4096 offset += subreg_regno_offset (REGNO (SUBREG_REG (x)),
4097 GET_MODE (SUBREG_REG (x)),
4103 if (GET_CODE (x) != REG)
4106 regno = REGNO (x) + offset;
4108 if (regno >= FIRST_PSEUDO_REGISTER)
4114 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4115 /* Storing into a spilled-reg invalidates its contents.
4116 This can happen if a block-local pseudo is allocated to that reg
4117 and it wasn't spilled because this block's total need is 0.
4118 Then some insn might have an optional reload and use this reg. */
4119 for (i = 0; i < nr; i++)
4120 /* But don't do this if the reg actually serves as an output
4121 reload reg in the current instruction. */
4123 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4125 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4126 spill_reg_store[regno + i] = 0;
4130 /* Since value of X has changed,
4131 forget any value previously copied from it. */
4134 /* But don't forget a copy if this is the output reload
4135 that establishes the copy's validity. */
4136 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4137 reg_last_reload_reg[regno + nr] = 0;
4140 /* The following HARD_REG_SETs indicate when each hard register is
4141 used for a reload of various parts of the current insn. */
4143 /* If reg is unavailable for all reloads. */
4144 static HARD_REG_SET reload_reg_unavailable;
4145 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4146 static HARD_REG_SET reload_reg_used;
4147 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4148 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4149 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4150 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4151 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4152 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4153 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4154 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4155 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4156 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4157 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4158 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4159 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4160 static HARD_REG_SET reload_reg_used_in_op_addr;
4161 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4162 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4163 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4164 static HARD_REG_SET reload_reg_used_in_insn;
4165 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4166 static HARD_REG_SET reload_reg_used_in_other_addr;
4168 /* If reg is in use as a reload reg for any sort of reload. */
4169 static HARD_REG_SET reload_reg_used_at_all;
4171 /* If reg is use as an inherited reload. We just mark the first register
4173 static HARD_REG_SET reload_reg_used_for_inherit;
4175 /* Records which hard regs are used in any way, either as explicit use or
4176 by being allocated to a pseudo during any point of the current insn. */
4177 static HARD_REG_SET reg_used_in_insn;
4179 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4180 TYPE. MODE is used to indicate how many consecutive regs are
4184 mark_reload_reg_in_use (regno, opnum, type, mode)
4187 enum reload_type type;
4188 enum machine_mode mode;
4190 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4193 for (i = regno; i < nregs + regno; i++)
4198 SET_HARD_REG_BIT (reload_reg_used, i);
4201 case RELOAD_FOR_INPUT_ADDRESS:
4202 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4205 case RELOAD_FOR_INPADDR_ADDRESS:
4206 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4209 case RELOAD_FOR_OUTPUT_ADDRESS:
4210 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4213 case RELOAD_FOR_OUTADDR_ADDRESS:
4214 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4217 case RELOAD_FOR_OPERAND_ADDRESS:
4218 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4221 case RELOAD_FOR_OPADDR_ADDR:
4222 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4225 case RELOAD_FOR_OTHER_ADDRESS:
4226 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4229 case RELOAD_FOR_INPUT:
4230 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4233 case RELOAD_FOR_OUTPUT:
4234 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4237 case RELOAD_FOR_INSN:
4238 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4242 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4246 /* Similarly, but show REGNO is no longer in use for a reload. */
4249 clear_reload_reg_in_use (regno, opnum, type, mode)
4252 enum reload_type type;
4253 enum machine_mode mode;
4255 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4256 unsigned int start_regno, end_regno, r;
4258 /* A complication is that for some reload types, inheritance might
4259 allow multiple reloads of the same types to share a reload register.
4260 We set check_opnum if we have to check only reloads with the same
4261 operand number, and check_any if we have to check all reloads. */
4262 int check_opnum = 0;
4264 HARD_REG_SET *used_in_set;
4269 used_in_set = &reload_reg_used;
4272 case RELOAD_FOR_INPUT_ADDRESS:
4273 used_in_set = &reload_reg_used_in_input_addr[opnum];
4276 case RELOAD_FOR_INPADDR_ADDRESS:
4278 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4281 case RELOAD_FOR_OUTPUT_ADDRESS:
4282 used_in_set = &reload_reg_used_in_output_addr[opnum];
4285 case RELOAD_FOR_OUTADDR_ADDRESS:
4287 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4290 case RELOAD_FOR_OPERAND_ADDRESS:
4291 used_in_set = &reload_reg_used_in_op_addr;
4294 case RELOAD_FOR_OPADDR_ADDR:
4296 used_in_set = &reload_reg_used_in_op_addr_reload;
4299 case RELOAD_FOR_OTHER_ADDRESS:
4300 used_in_set = &reload_reg_used_in_other_addr;
4304 case RELOAD_FOR_INPUT:
4305 used_in_set = &reload_reg_used_in_input[opnum];
4308 case RELOAD_FOR_OUTPUT:
4309 used_in_set = &reload_reg_used_in_output[opnum];
4312 case RELOAD_FOR_INSN:
4313 used_in_set = &reload_reg_used_in_insn;
4318 /* We resolve conflicts with remaining reloads of the same type by
4319 excluding the intervals of of reload registers by them from the
4320 interval of freed reload registers. Since we only keep track of
4321 one set of interval bounds, we might have to exclude somewhat
4322 more then what would be necessary if we used a HARD_REG_SET here.
4323 But this should only happen very infrequently, so there should
4324 be no reason to worry about it. */
4326 start_regno = regno;
4327 end_regno = regno + nregs;
4328 if (check_opnum || check_any)
4330 for (i = n_reloads - 1; i >= 0; i--)
4332 if (rld[i].when_needed == type
4333 && (check_any || rld[i].opnum == opnum)
4336 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4337 unsigned int conflict_end
4339 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4341 /* If there is an overlap with the first to-be-freed register,
4342 adjust the interval start. */
4343 if (conflict_start <= start_regno && conflict_end > start_regno)
4344 start_regno = conflict_end;
4345 /* Otherwise, if there is a conflict with one of the other
4346 to-be-freed registers, adjust the interval end. */
4347 if (conflict_start > start_regno && conflict_start < end_regno)
4348 end_regno = conflict_start;
4353 for (r = start_regno; r < end_regno; r++)
4354 CLEAR_HARD_REG_BIT (*used_in_set, r);
4357 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4358 specified by OPNUM and TYPE. */
4361 reload_reg_free_p (regno, opnum, type)
4364 enum reload_type type;
4368 /* In use for a RELOAD_OTHER means it's not available for anything. */
4369 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4370 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4376 /* In use for anything means we can't use it for RELOAD_OTHER. */
4377 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4378 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4382 for (i = 0; i < reload_n_operands; i++)
4383 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4384 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4385 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4386 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4387 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4388 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4393 case RELOAD_FOR_INPUT:
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4395 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4401 /* If it is used for some other input, can't use it. */
4402 for (i = 0; i < reload_n_operands; i++)
4403 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4406 /* If it is used in a later operand's address, can't use it. */
4407 for (i = opnum + 1; i < reload_n_operands; i++)
4408 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4409 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4414 case RELOAD_FOR_INPUT_ADDRESS:
4415 /* Can't use a register if it is used for an input address for this
4416 operand or used as an input in an earlier one. */
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4418 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4421 for (i = 0; i < opnum; i++)
4422 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4427 case RELOAD_FOR_INPADDR_ADDRESS:
4428 /* Can't use a register if it is used for an input address
4429 for this operand or used as an input in an earlier
4431 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4434 for (i = 0; i < opnum; i++)
4435 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4440 case RELOAD_FOR_OUTPUT_ADDRESS:
4441 /* Can't use a register if it is used for an output address for this
4442 operand or used as an output in this or a later operand. Note
4443 that multiple output operands are emitted in reverse order, so
4444 the conflicting ones are those with lower indices. */
4445 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4448 for (i = 0; i <= opnum; i++)
4449 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4454 case RELOAD_FOR_OUTADDR_ADDRESS:
4455 /* Can't use a register if it is used for an output address
4456 for this operand or used as an output in this or a
4457 later operand. Note that multiple output operands are
4458 emitted in reverse order, so the conflicting ones are
4459 those with lower indices. */
4460 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4463 for (i = 0; i <= opnum; i++)
4464 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4469 case RELOAD_FOR_OPERAND_ADDRESS:
4470 for (i = 0; i < reload_n_operands; i++)
4471 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4474 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4475 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4477 case RELOAD_FOR_OPADDR_ADDR:
4478 for (i = 0; i < reload_n_operands; i++)
4479 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4482 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4484 case RELOAD_FOR_OUTPUT:
4485 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4486 outputs, or an operand address for this or an earlier output.
4487 Note that multiple output operands are emitted in reverse order,
4488 so the conflicting ones are those with higher indices. */
4489 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4492 for (i = 0; i < reload_n_operands; i++)
4493 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4496 for (i = opnum; i < reload_n_operands; i++)
4497 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4498 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4503 case RELOAD_FOR_INSN:
4504 for (i = 0; i < reload_n_operands; i++)
4505 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4506 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4509 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4510 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4512 case RELOAD_FOR_OTHER_ADDRESS:
4513 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4518 /* Return 1 if the value in reload reg REGNO, as used by a reload
4519 needed for the part of the insn specified by OPNUM and TYPE,
4520 is still available in REGNO at the end of the insn.
4522 We can assume that the reload reg was already tested for availability
4523 at the time it is needed, and we should not check this again,
4524 in case the reg has already been marked in use. */
4527 reload_reg_reaches_end_p (regno, opnum, type)
4530 enum reload_type type;
4537 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4538 its value must reach the end. */
4541 /* If this use is for part of the insn,
4542 its value reaches if no subsequent part uses the same register.
4543 Just like the above function, don't try to do this with lots
4546 case RELOAD_FOR_OTHER_ADDRESS:
4547 /* Here we check for everything else, since these don't conflict
4548 with anything else and everything comes later. */
4550 for (i = 0; i < reload_n_operands; i++)
4551 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4552 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4553 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4554 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4555 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4556 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4559 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4560 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4561 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4563 case RELOAD_FOR_INPUT_ADDRESS:
4564 case RELOAD_FOR_INPADDR_ADDRESS:
4565 /* Similar, except that we check only for this and subsequent inputs
4566 and the address of only subsequent inputs and we do not need
4567 to check for RELOAD_OTHER objects since they are known not to
4570 for (i = opnum; i < reload_n_operands; i++)
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4574 for (i = opnum + 1; i < reload_n_operands; i++)
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4579 for (i = 0; i < reload_n_operands; i++)
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4581 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4582 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4585 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4588 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4589 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4590 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4592 case RELOAD_FOR_INPUT:
4593 /* Similar to input address, except we start at the next operand for
4594 both input and input address and we do not check for
4595 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4598 for (i = opnum + 1; i < reload_n_operands; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4600 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4601 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4604 /* ... fall through ... */
4606 case RELOAD_FOR_OPERAND_ADDRESS:
4607 /* Check outputs and their addresses. */
4609 for (i = 0; i < reload_n_operands; i++)
4610 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4611 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4612 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4615 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4617 case RELOAD_FOR_OPADDR_ADDR:
4618 for (i = 0; i < reload_n_operands; i++)
4619 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4620 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4621 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4624 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4625 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4626 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4628 case RELOAD_FOR_INSN:
4629 /* These conflict with other outputs with RELOAD_OTHER. So
4630 we need only check for output addresses. */
4632 opnum = reload_n_operands;
4634 /* ... fall through ... */
4636 case RELOAD_FOR_OUTPUT:
4637 case RELOAD_FOR_OUTPUT_ADDRESS:
4638 case RELOAD_FOR_OUTADDR_ADDRESS:
4639 /* We already know these can't conflict with a later output. So the
4640 only thing to check are later output addresses.
4641 Note that multiple output operands are emitted in reverse order,
4642 so the conflicting ones are those with lower indices. */
4643 for (i = 0; i < opnum; i++)
4644 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4645 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4654 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4657 This function uses the same algorithm as reload_reg_free_p above. */
4660 reloads_conflict (r1, r2)
4663 enum reload_type r1_type = rld[r1].when_needed;
4664 enum reload_type r2_type = rld[r2].when_needed;
4665 int r1_opnum = rld[r1].opnum;
4666 int r2_opnum = rld[r2].opnum;
4668 /* RELOAD_OTHER conflicts with everything. */
4669 if (r2_type == RELOAD_OTHER)
4672 /* Otherwise, check conflicts differently for each type. */
4676 case RELOAD_FOR_INPUT:
4677 return (r2_type == RELOAD_FOR_INSN
4678 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4679 || r2_type == RELOAD_FOR_OPADDR_ADDR
4680 || r2_type == RELOAD_FOR_INPUT
4681 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4682 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4683 && r2_opnum > r1_opnum));
4685 case RELOAD_FOR_INPUT_ADDRESS:
4686 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4687 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4689 case RELOAD_FOR_INPADDR_ADDRESS:
4690 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4691 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4693 case RELOAD_FOR_OUTPUT_ADDRESS:
4694 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4695 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4697 case RELOAD_FOR_OUTADDR_ADDRESS:
4698 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4699 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4701 case RELOAD_FOR_OPERAND_ADDRESS:
4702 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4703 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4705 case RELOAD_FOR_OPADDR_ADDR:
4706 return (r2_type == RELOAD_FOR_INPUT
4707 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4709 case RELOAD_FOR_OUTPUT:
4710 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4711 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4712 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4713 && r2_opnum >= r1_opnum));
4715 case RELOAD_FOR_INSN:
4716 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4717 || r2_type == RELOAD_FOR_INSN
4718 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4720 case RELOAD_FOR_OTHER_ADDRESS:
4721 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4731 /* Indexed by reload number, 1 if incoming value
4732 inherited from previous insns. */
4733 char reload_inherited[MAX_RELOADS];
4735 /* For an inherited reload, this is the insn the reload was inherited from,
4736 if we know it. Otherwise, this is 0. */
4737 rtx reload_inheritance_insn[MAX_RELOADS];
4739 /* If non-zero, this is a place to get the value of the reload,
4740 rather than using reload_in. */
4741 rtx reload_override_in[MAX_RELOADS];
4743 /* For each reload, the hard register number of the register used,
4744 or -1 if we did not need a register for this reload. */
4745 int reload_spill_index[MAX_RELOADS];
4747 /* Subroutine of free_for_value_p, used to check a single register.
4748 START_REGNO is the starting regno of the full reload register
4749 (possibly comprising multiple hard registers) that we are considering. */
4752 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4753 reloadnum, ignore_address_reloads)
4754 int start_regno, regno;
4756 enum reload_type type;
4759 int ignore_address_reloads;
4762 /* Set if we see an input reload that must not share its reload register
4763 with any new earlyclobber, but might otherwise share the reload
4764 register with an output or input-output reload. */
4765 int check_earlyclobber = 0;
4769 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4772 if (out == const0_rtx)
4778 /* We use some pseudo 'time' value to check if the lifetimes of the
4779 new register use would overlap with the one of a previous reload
4780 that is not read-only or uses a different value.
4781 The 'time' used doesn't have to be linear in any shape or form, just
4783 Some reload types use different 'buckets' for each operand.
4784 So there are MAX_RECOG_OPERANDS different time values for each
4786 We compute TIME1 as the time when the register for the prospective
4787 new reload ceases to be live, and TIME2 for each existing
4788 reload as the time when that the reload register of that reload
4790 Where there is little to be gained by exact lifetime calculations,
4791 we just make conservative assumptions, i.e. a longer lifetime;
4792 this is done in the 'default:' cases. */
4795 case RELOAD_FOR_OTHER_ADDRESS:
4796 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4797 time1 = copy ? 0 : 1;
4800 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4802 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4803 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4804 respectively, to the time values for these, we get distinct time
4805 values. To get distinct time values for each operand, we have to
4806 multiply opnum by at least three. We round that up to four because
4807 multiply by four is often cheaper. */
4808 case RELOAD_FOR_INPADDR_ADDRESS:
4809 time1 = opnum * 4 + 2;
4811 case RELOAD_FOR_INPUT_ADDRESS:
4812 time1 = opnum * 4 + 3;
4814 case RELOAD_FOR_INPUT:
4815 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4816 executes (inclusive). */
4817 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4819 case RELOAD_FOR_OPADDR_ADDR:
4821 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4822 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4824 case RELOAD_FOR_OPERAND_ADDRESS:
4825 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4827 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4829 case RELOAD_FOR_OUTADDR_ADDRESS:
4830 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4832 case RELOAD_FOR_OUTPUT_ADDRESS:
4833 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4836 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4839 for (i = 0; i < n_reloads; i++)
4841 rtx reg = rld[i].reg_rtx;
4842 if (reg && GET_CODE (reg) == REG
4843 && ((unsigned) regno - true_regnum (reg)
4844 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4847 rtx other_input = rld[i].in;
4849 /* If the other reload loads the same input value, that
4850 will not cause a conflict only if it's loading it into
4851 the same register. */
4852 if (true_regnum (reg) != start_regno)
4853 other_input = NULL_RTX;
4854 if (! other_input || ! rtx_equal_p (other_input, value)
4855 || rld[i].out || out)
4858 switch (rld[i].when_needed)
4860 case RELOAD_FOR_OTHER_ADDRESS:
4863 case RELOAD_FOR_INPADDR_ADDRESS:
4864 /* find_reloads makes sure that a
4865 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4866 by at most one - the first -
4867 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4868 address reload is inherited, the address address reload
4869 goes away, so we can ignore this conflict. */
4870 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4871 && ignore_address_reloads
4872 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4873 Then the address address is still needed to store
4874 back the new address. */
4875 && ! rld[reloadnum].out)
4877 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4878 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4880 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4881 && ignore_address_reloads
4882 /* Unless we are reloading an auto_inc expression. */
4883 && ! rld[reloadnum].out)
4885 time2 = rld[i].opnum * 4 + 2;
4887 case RELOAD_FOR_INPUT_ADDRESS:
4888 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4889 && ignore_address_reloads
4890 && ! rld[reloadnum].out)
4892 time2 = rld[i].opnum * 4 + 3;
4894 case RELOAD_FOR_INPUT:
4895 time2 = rld[i].opnum * 4 + 4;
4896 check_earlyclobber = 1;
4898 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4899 == MAX_RECOG_OPERAND * 4 */
4900 case RELOAD_FOR_OPADDR_ADDR:
4901 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4902 && ignore_address_reloads
4903 && ! rld[reloadnum].out)
4905 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4907 case RELOAD_FOR_OPERAND_ADDRESS:
4908 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4909 check_earlyclobber = 1;
4911 case RELOAD_FOR_INSN:
4912 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4914 case RELOAD_FOR_OUTPUT:
4915 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4916 instruction is executed. */
4917 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4919 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4920 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4922 case RELOAD_FOR_OUTADDR_ADDRESS:
4923 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4924 && ignore_address_reloads
4925 && ! rld[reloadnum].out)
4927 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4929 case RELOAD_FOR_OUTPUT_ADDRESS:
4930 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4933 /* If there is no conflict in the input part, handle this
4934 like an output reload. */
4935 if (! rld[i].in || rtx_equal_p (other_input, value))
4937 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4938 /* Earlyclobbered outputs must conflict with inputs. */
4939 if (earlyclobber_operand_p (rld[i].out))
4940 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4945 /* RELOAD_OTHER might be live beyond instruction execution,
4946 but this is not obvious when we set time2 = 1. So check
4947 here if there might be a problem with the new reload
4948 clobbering the register used by the RELOAD_OTHER. */
4956 && (! rld[i].in || rld[i].out
4957 || ! rtx_equal_p (other_input, value)))
4958 || (out && rld[reloadnum].out_reg
4959 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4965 /* Earlyclobbered outputs must conflict with inputs. */
4966 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4972 /* Return 1 if the value in reload reg REGNO, as used by a reload
4973 needed for the part of the insn specified by OPNUM and TYPE,
4974 may be used to load VALUE into it.
4976 MODE is the mode in which the register is used, this is needed to
4977 determine how many hard regs to test.
4979 Other read-only reloads with the same value do not conflict
4980 unless OUT is non-zero and these other reloads have to live while
4981 output reloads live.
4982 If OUT is CONST0_RTX, this is a special case: it means that the
4983 test should not be for using register REGNO as reload register, but
4984 for copying from register REGNO into the reload register.
4986 RELOADNUM is the number of the reload we want to load this value for;
4987 a reload does not conflict with itself.
4989 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4990 reloads that load an address for the very reload we are considering.
4992 The caller has to make sure that there is no conflict with the return
4996 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4997 ignore_address_reloads)
4999 enum machine_mode mode;
5001 enum reload_type type;
5004 int ignore_address_reloads;
5006 int nregs = HARD_REGNO_NREGS (regno, mode);
5008 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5009 value, out, reloadnum,
5010 ignore_address_reloads))
5015 /* Determine whether the reload reg X overlaps any rtx'es used for
5016 overriding inheritance. Return nonzero if so. */
5019 conflicts_with_override (x)
5023 for (i = 0; i < n_reloads; i++)
5024 if (reload_override_in[i]
5025 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5030 /* Give an error message saying we failed to find a reload for INSN,
5031 and clear out reload R. */
5033 failed_reload (insn, r)
5037 if (asm_noperands (PATTERN (insn)) < 0)
5038 /* It's the compiler's fault. */
5039 fatal_insn ("could not find a spill register", insn);
5041 /* It's the user's fault; the operand's mode and constraint
5042 don't match. Disable this reload so we don't crash in final. */
5043 error_for_asm (insn,
5044 "`asm' operand constraint incompatible with operand size");
5048 rld[r].optional = 1;
5049 rld[r].secondary_p = 1;
5052 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5053 for reload R. If it's valid, get an rtx for it. Return nonzero if
5056 set_reload_reg (i, r)
5060 rtx reg = spill_reg_rtx[i];
5062 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5063 spill_reg_rtx[i] = reg
5064 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5066 regno = true_regnum (reg);
5068 /* Detect when the reload reg can't hold the reload mode.
5069 This used to be one `if', but Sequent compiler can't handle that. */
5070 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5072 enum machine_mode test_mode = VOIDmode;
5074 test_mode = GET_MODE (rld[r].in);
5075 /* If rld[r].in has VOIDmode, it means we will load it
5076 in whatever mode the reload reg has: to wit, rld[r].mode.
5077 We have already tested that for validity. */
5078 /* Aside from that, we need to test that the expressions
5079 to reload from or into have modes which are valid for this
5080 reload register. Otherwise the reload insns would be invalid. */
5081 if (! (rld[r].in != 0 && test_mode != VOIDmode
5082 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5083 if (! (rld[r].out != 0
5084 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5086 /* The reg is OK. */
5089 /* Mark as in use for this insn the reload regs we use
5091 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5092 rld[r].when_needed, rld[r].mode);
5094 rld[r].reg_rtx = reg;
5095 reload_spill_index[r] = spill_regs[i];
5102 /* Find a spill register to use as a reload register for reload R.
5103 LAST_RELOAD is non-zero if this is the last reload for the insn being
5106 Set rld[R].reg_rtx to the register allocated.
5108 We return 1 if successful, or 0 if we couldn't find a spill reg and
5109 we didn't change anything. */
5112 allocate_reload_reg (chain, r, last_reload)
5113 struct insn_chain *chain ATTRIBUTE_UNUSED;
5119 /* If we put this reload ahead, thinking it is a group,
5120 then insist on finding a group. Otherwise we can grab a
5121 reg that some other reload needs.
5122 (That can happen when we have a 68000 DATA_OR_FP_REG
5123 which is a group of data regs or one fp reg.)
5124 We need not be so restrictive if there are no more reloads
5127 ??? Really it would be nicer to have smarter handling
5128 for that kind of reg class, where a problem like this is normal.
5129 Perhaps those classes should be avoided for reloading
5130 by use of more alternatives. */
5132 int force_group = rld[r].nregs > 1 && ! last_reload;
5134 /* If we want a single register and haven't yet found one,
5135 take any reg in the right class and not in use.
5136 If we want a consecutive group, here is where we look for it.
5138 We use two passes so we can first look for reload regs to
5139 reuse, which are already in use for other reloads in this insn,
5140 and only then use additional registers.
5141 I think that maximizing reuse is needed to make sure we don't
5142 run out of reload regs. Suppose we have three reloads, and
5143 reloads A and B can share regs. These need two regs.
5144 Suppose A and B are given different regs.
5145 That leaves none for C. */
5146 for (pass = 0; pass < 2; pass++)
5148 /* I is the index in spill_regs.
5149 We advance it round-robin between insns to use all spill regs
5150 equally, so that inherited reloads have a chance
5151 of leapfrogging each other. */
5155 for (count = 0; count < n_spills; count++)
5157 int class = (int) rld[r].class;
5163 regnum = spill_regs[i];
5165 if ((reload_reg_free_p (regnum, rld[r].opnum,
5168 /* We check reload_reg_used to make sure we
5169 don't clobber the return register. */
5170 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5171 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5172 rld[r].when_needed, rld[r].in,
5174 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5175 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5176 /* Look first for regs to share, then for unshared. But
5177 don't share regs used for inherited reloads; they are
5178 the ones we want to preserve. */
5180 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5182 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5185 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5186 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5187 (on 68000) got us two FP regs. If NR is 1,
5188 we would reject both of them. */
5191 /* If we need only one reg, we have already won. */
5194 /* But reject a single reg if we demand a group. */
5199 /* Otherwise check that as many consecutive regs as we need
5200 are available here. */
5203 int regno = regnum + nr - 1;
5204 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5205 && spill_reg_order[regno] >= 0
5206 && reload_reg_free_p (regno, rld[r].opnum,
5207 rld[r].when_needed)))
5216 /* If we found something on pass 1, omit pass 2. */
5217 if (count < n_spills)
5221 /* We should have found a spill register by now. */
5222 if (count >= n_spills)
5225 /* I is the index in SPILL_REG_RTX of the reload register we are to
5226 allocate. Get an rtx for it and find its register number. */
5228 return set_reload_reg (i, r);
5231 /* Initialize all the tables needed to allocate reload registers.
5232 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5233 is the array we use to restore the reg_rtx field for every reload. */
5236 choose_reload_regs_init (chain, save_reload_reg_rtx)
5237 struct insn_chain *chain;
5238 rtx *save_reload_reg_rtx;
5242 for (i = 0; i < n_reloads; i++)
5243 rld[i].reg_rtx = save_reload_reg_rtx[i];
5245 memset (reload_inherited, 0, MAX_RELOADS);
5246 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5247 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5249 CLEAR_HARD_REG_SET (reload_reg_used);
5250 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5251 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5252 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5253 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5254 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5256 CLEAR_HARD_REG_SET (reg_used_in_insn);
5259 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5260 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5261 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5262 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5263 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5264 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5267 for (i = 0; i < reload_n_operands; i++)
5269 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5270 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5271 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5272 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5273 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5274 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5277 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5279 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5281 for (i = 0; i < n_reloads; i++)
5282 /* If we have already decided to use a certain register,
5283 don't use it in another way. */
5285 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5286 rld[i].when_needed, rld[i].mode);
5289 /* Assign hard reg targets for the pseudo-registers we must reload
5290 into hard regs for this insn.
5291 Also output the instructions to copy them in and out of the hard regs.
5293 For machines with register classes, we are responsible for
5294 finding a reload reg in the proper class. */
5297 choose_reload_regs (chain)
5298 struct insn_chain *chain;
5300 rtx insn = chain->insn;
5302 unsigned int max_group_size = 1;
5303 enum reg_class group_class = NO_REGS;
5304 int pass, win, inheritance;
5306 rtx save_reload_reg_rtx[MAX_RELOADS];
5308 /* In order to be certain of getting the registers we need,
5309 we must sort the reloads into order of increasing register class.
5310 Then our grabbing of reload registers will parallel the process
5311 that provided the reload registers.
5313 Also note whether any of the reloads wants a consecutive group of regs.
5314 If so, record the maximum size of the group desired and what
5315 register class contains all the groups needed by this insn. */
5317 for (j = 0; j < n_reloads; j++)
5319 reload_order[j] = j;
5320 reload_spill_index[j] = -1;
5322 if (rld[j].nregs > 1)
5324 max_group_size = MAX (rld[j].nregs, max_group_size);
5326 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5329 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5333 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5335 /* If -O, try first with inheritance, then turning it off.
5336 If not -O, don't do inheritance.
5337 Using inheritance when not optimizing leads to paradoxes
5338 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5339 because one side of the comparison might be inherited. */
5341 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5343 choose_reload_regs_init (chain, save_reload_reg_rtx);
5345 /* Process the reloads in order of preference just found.
5346 Beyond this point, subregs can be found in reload_reg_rtx.
5348 This used to look for an existing reloaded home for all of the
5349 reloads, and only then perform any new reloads. But that could lose
5350 if the reloads were done out of reg-class order because a later
5351 reload with a looser constraint might have an old home in a register
5352 needed by an earlier reload with a tighter constraint.
5354 To solve this, we make two passes over the reloads, in the order
5355 described above. In the first pass we try to inherit a reload
5356 from a previous insn. If there is a later reload that needs a
5357 class that is a proper subset of the class being processed, we must
5358 also allocate a spill register during the first pass.
5360 Then make a second pass over the reloads to allocate any reloads
5361 that haven't been given registers yet. */
5363 for (j = 0; j < n_reloads; j++)
5365 int r = reload_order[j];
5366 rtx search_equiv = NULL_RTX;
5368 /* Ignore reloads that got marked inoperative. */
5369 if (rld[r].out == 0 && rld[r].in == 0
5370 && ! rld[r].secondary_p)
5373 /* If find_reloads chose to use reload_in or reload_out as a reload
5374 register, we don't need to chose one. Otherwise, try even if it
5375 found one since we might save an insn if we find the value lying
5377 Try also when reload_in is a pseudo without a hard reg. */
5378 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5379 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5380 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5381 && GET_CODE (rld[r].in) != MEM
5382 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5385 #if 0 /* No longer needed for correct operation.
5386 It might give better code, or might not; worth an experiment? */
5387 /* If this is an optional reload, we can't inherit from earlier insns
5388 until we are sure that any non-optional reloads have been allocated.
5389 The following code takes advantage of the fact that optional reloads
5390 are at the end of reload_order. */
5391 if (rld[r].optional != 0)
5392 for (i = 0; i < j; i++)
5393 if ((rld[reload_order[i]].out != 0
5394 || rld[reload_order[i]].in != 0
5395 || rld[reload_order[i]].secondary_p)
5396 && ! rld[reload_order[i]].optional
5397 && rld[reload_order[i]].reg_rtx == 0)
5398 allocate_reload_reg (chain, reload_order[i], 0);
5401 /* First see if this pseudo is already available as reloaded
5402 for a previous insn. We cannot try to inherit for reloads
5403 that are smaller than the maximum number of registers needed
5404 for groups unless the register we would allocate cannot be used
5407 We could check here to see if this is a secondary reload for
5408 an object that is already in a register of the desired class.
5409 This would avoid the need for the secondary reload register.
5410 But this is complex because we can't easily determine what
5411 objects might want to be loaded via this reload. So let a
5412 register be allocated here. In `emit_reload_insns' we suppress
5413 one of the loads in the case described above. */
5419 enum machine_mode mode = VOIDmode;
5423 else if (GET_CODE (rld[r].in) == REG)
5425 regno = REGNO (rld[r].in);
5426 mode = GET_MODE (rld[r].in);
5428 else if (GET_CODE (rld[r].in_reg) == REG)
5430 regno = REGNO (rld[r].in_reg);
5431 mode = GET_MODE (rld[r].in_reg);
5433 else if (GET_CODE (rld[r].in_reg) == SUBREG
5434 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5436 byte = SUBREG_BYTE (rld[r].in_reg);
5437 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5438 if (regno < FIRST_PSEUDO_REGISTER)
5439 regno = subreg_regno (rld[r].in_reg);
5440 mode = GET_MODE (rld[r].in_reg);
5443 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5444 || GET_CODE (rld[r].in_reg) == PRE_DEC
5445 || GET_CODE (rld[r].in_reg) == POST_INC
5446 || GET_CODE (rld[r].in_reg) == POST_DEC)
5447 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5449 regno = REGNO (XEXP (rld[r].in_reg, 0));
5450 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5451 rld[r].out = rld[r].in;
5455 /* This won't work, since REGNO can be a pseudo reg number.
5456 Also, it takes much more hair to keep track of all the things
5457 that can invalidate an inherited reload of part of a pseudoreg. */
5458 else if (GET_CODE (rld[r].in) == SUBREG
5459 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5460 regno = subreg_regno (rld[r].in);
5463 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5465 enum reg_class class = rld[r].class, last_class;
5466 rtx last_reg = reg_last_reload_reg[regno];
5467 enum machine_mode need_mode;
5469 i = REGNO (last_reg);
5470 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5471 last_class = REGNO_REG_CLASS (i);
5477 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5478 GET_MODE_CLASS (mode));
5481 #ifdef CLASS_CANNOT_CHANGE_MODE
5483 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5484 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5486 : (GET_MODE_SIZE (GET_MODE (last_reg))
5487 >= GET_MODE_SIZE (need_mode)))
5489 (GET_MODE_SIZE (GET_MODE (last_reg))
5490 >= GET_MODE_SIZE (need_mode))
5492 && reg_reloaded_contents[i] == regno
5493 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5494 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5495 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5496 /* Even if we can't use this register as a reload
5497 register, we might use it for reload_override_in,
5498 if copying it to the desired class is cheap
5500 || ((REGISTER_MOVE_COST (mode, last_class, class)
5501 < MEMORY_MOVE_COST (mode, class, 1))
5502 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5503 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5507 #ifdef SECONDARY_MEMORY_NEEDED
5508 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5513 && (rld[r].nregs == max_group_size
5514 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5516 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5517 rld[r].when_needed, rld[r].in,
5520 /* If a group is needed, verify that all the subsequent
5521 registers still have their values intact. */
5522 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5525 for (k = 1; k < nr; k++)
5526 if (reg_reloaded_contents[i + k] != regno
5527 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5535 last_reg = (GET_MODE (last_reg) == mode
5536 ? last_reg : gen_rtx_REG (mode, i));
5539 for (k = 0; k < nr; k++)
5540 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5543 /* We found a register that contains the
5544 value we need. If this register is the
5545 same as an `earlyclobber' operand of the
5546 current insn, just mark it as a place to
5547 reload from since we can't use it as the
5548 reload register itself. */
5550 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5551 if (reg_overlap_mentioned_for_reload_p
5552 (reg_last_reload_reg[regno],
5553 reload_earlyclobbers[i1]))
5556 if (i1 != n_earlyclobbers
5557 || ! (free_for_value_p (i, rld[r].mode,
5559 rld[r].when_needed, rld[r].in,
5561 /* Don't use it if we'd clobber a pseudo reg. */
5562 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5564 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5565 /* Don't clobber the frame pointer. */
5566 || (i == HARD_FRAME_POINTER_REGNUM
5568 /* Don't really use the inherited spill reg
5569 if we need it wider than we've got it. */
5570 || (GET_MODE_SIZE (rld[r].mode)
5571 > GET_MODE_SIZE (mode))
5574 /* If find_reloads chose reload_out as reload
5575 register, stay with it - that leaves the
5576 inherited register for subsequent reloads. */
5577 || (rld[r].out && rld[r].reg_rtx
5578 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5580 if (! rld[r].optional)
5582 reload_override_in[r] = last_reg;
5583 reload_inheritance_insn[r]
5584 = reg_reloaded_insn[i];
5590 /* We can use this as a reload reg. */
5591 /* Mark the register as in use for this part of
5593 mark_reload_reg_in_use (i,
5597 rld[r].reg_rtx = last_reg;
5598 reload_inherited[r] = 1;
5599 reload_inheritance_insn[r]
5600 = reg_reloaded_insn[i];
5601 reload_spill_index[r] = i;
5602 for (k = 0; k < nr; k++)
5603 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5611 /* Here's another way to see if the value is already lying around. */
5614 && ! reload_inherited[r]
5616 && (CONSTANT_P (rld[r].in)
5617 || GET_CODE (rld[r].in) == PLUS
5618 || GET_CODE (rld[r].in) == REG
5619 || GET_CODE (rld[r].in) == MEM)
5620 && (rld[r].nregs == max_group_size
5621 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5622 search_equiv = rld[r].in;
5623 /* If this is an output reload from a simple move insn, look
5624 if an equivalence for the input is available. */
5625 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5627 rtx set = single_set (insn);
5630 && rtx_equal_p (rld[r].out, SET_DEST (set))
5631 && CONSTANT_P (SET_SRC (set)))
5632 search_equiv = SET_SRC (set);
5638 = find_equiv_reg (search_equiv, insn, rld[r].class,
5639 -1, NULL, 0, rld[r].mode);
5644 if (GET_CODE (equiv) == REG)
5645 regno = REGNO (equiv);
5646 else if (GET_CODE (equiv) == SUBREG)
5648 /* This must be a SUBREG of a hard register.
5649 Make a new REG since this might be used in an
5650 address and not all machines support SUBREGs
5652 regno = subreg_regno (equiv);
5653 equiv = gen_rtx_REG (rld[r].mode, regno);
5659 /* If we found a spill reg, reject it unless it is free
5660 and of the desired class. */
5662 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5663 && ! free_for_value_p (regno, rld[r].mode,
5664 rld[r].opnum, rld[r].when_needed,
5665 rld[r].in, rld[r].out, r, 1))
5666 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5670 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5673 /* We found a register that contains the value we need.
5674 If this register is the same as an `earlyclobber' operand
5675 of the current insn, just mark it as a place to reload from
5676 since we can't use it as the reload register itself. */
5679 for (i = 0; i < n_earlyclobbers; i++)
5680 if (reg_overlap_mentioned_for_reload_p (equiv,
5681 reload_earlyclobbers[i]))
5683 if (! rld[r].optional)
5684 reload_override_in[r] = equiv;
5689 /* If the equiv register we have found is explicitly clobbered
5690 in the current insn, it depends on the reload type if we
5691 can use it, use it for reload_override_in, or not at all.
5692 In particular, we then can't use EQUIV for a
5693 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5697 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5698 switch (rld[r].when_needed)
5700 case RELOAD_FOR_OTHER_ADDRESS:
5701 case RELOAD_FOR_INPADDR_ADDRESS:
5702 case RELOAD_FOR_INPUT_ADDRESS:
5703 case RELOAD_FOR_OPADDR_ADDR:
5706 case RELOAD_FOR_INPUT:
5707 case RELOAD_FOR_OPERAND_ADDRESS:
5708 if (! rld[r].optional)
5709 reload_override_in[r] = equiv;
5715 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5716 switch (rld[r].when_needed)
5718 case RELOAD_FOR_OTHER_ADDRESS:
5719 case RELOAD_FOR_INPADDR_ADDRESS:
5720 case RELOAD_FOR_INPUT_ADDRESS:
5721 case RELOAD_FOR_OPADDR_ADDR:
5722 case RELOAD_FOR_OPERAND_ADDRESS:
5723 case RELOAD_FOR_INPUT:
5726 if (! rld[r].optional)
5727 reload_override_in[r] = equiv;
5735 /* If we found an equivalent reg, say no code need be generated
5736 to load it, and use it as our reload reg. */
5737 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5739 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5741 rld[r].reg_rtx = equiv;
5742 reload_inherited[r] = 1;
5744 /* If reg_reloaded_valid is not set for this register,
5745 there might be a stale spill_reg_store lying around.
5746 We must clear it, since otherwise emit_reload_insns
5747 might delete the store. */
5748 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5749 spill_reg_store[regno] = NULL_RTX;
5750 /* If any of the hard registers in EQUIV are spill
5751 registers, mark them as in use for this insn. */
5752 for (k = 0; k < nr; k++)
5754 i = spill_reg_order[regno + k];
5757 mark_reload_reg_in_use (regno, rld[r].opnum,
5760 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5767 /* If we found a register to use already, or if this is an optional
5768 reload, we are done. */
5769 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5773 /* No longer needed for correct operation. Might or might
5774 not give better code on the average. Want to experiment? */
5776 /* See if there is a later reload that has a class different from our
5777 class that intersects our class or that requires less register
5778 than our reload. If so, we must allocate a register to this
5779 reload now, since that reload might inherit a previous reload
5780 and take the only available register in our class. Don't do this
5781 for optional reloads since they will force all previous reloads
5782 to be allocated. Also don't do this for reloads that have been
5785 for (i = j + 1; i < n_reloads; i++)
5787 int s = reload_order[i];
5789 if ((rld[s].in == 0 && rld[s].out == 0
5790 && ! rld[s].secondary_p)
5794 if ((rld[s].class != rld[r].class
5795 && reg_classes_intersect_p (rld[r].class,
5797 || rld[s].nregs < rld[r].nregs)
5804 allocate_reload_reg (chain, r, j == n_reloads - 1);
5808 /* Now allocate reload registers for anything non-optional that
5809 didn't get one yet. */
5810 for (j = 0; j < n_reloads; j++)
5812 int r = reload_order[j];
5814 /* Ignore reloads that got marked inoperative. */
5815 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5818 /* Skip reloads that already have a register allocated or are
5820 if (rld[r].reg_rtx != 0 || rld[r].optional)
5823 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5827 /* If that loop got all the way, we have won. */
5834 /* Loop around and try without any inheritance. */
5839 /* First undo everything done by the failed attempt
5840 to allocate with inheritance. */
5841 choose_reload_regs_init (chain, save_reload_reg_rtx);
5843 /* Some sanity tests to verify that the reloads found in the first
5844 pass are identical to the ones we have now. */
5845 if (chain->n_reloads != n_reloads)
5848 for (i = 0; i < n_reloads; i++)
5850 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5852 if (chain->rld[i].when_needed != rld[i].when_needed)
5854 for (j = 0; j < n_spills; j++)
5855 if (spill_regs[j] == chain->rld[i].regno)
5856 if (! set_reload_reg (j, i))
5857 failed_reload (chain->insn, i);
5861 /* If we thought we could inherit a reload, because it seemed that
5862 nothing else wanted the same reload register earlier in the insn,
5863 verify that assumption, now that all reloads have been assigned.
5864 Likewise for reloads where reload_override_in has been set. */
5866 /* If doing expensive optimizations, do one preliminary pass that doesn't
5867 cancel any inheritance, but removes reloads that have been needed only
5868 for reloads that we know can be inherited. */
5869 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5871 for (j = 0; j < n_reloads; j++)
5873 int r = reload_order[j];
5875 if (reload_inherited[r] && rld[r].reg_rtx)
5876 check_reg = rld[r].reg_rtx;
5877 else if (reload_override_in[r]
5878 && (GET_CODE (reload_override_in[r]) == REG
5879 || GET_CODE (reload_override_in[r]) == SUBREG))
5880 check_reg = reload_override_in[r];
5883 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5884 rld[r].opnum, rld[r].when_needed, rld[r].in,
5885 (reload_inherited[r]
5886 ? rld[r].out : const0_rtx),
5891 reload_inherited[r] = 0;
5892 reload_override_in[r] = 0;
5894 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5895 reload_override_in, then we do not need its related
5896 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5897 likewise for other reload types.
5898 We handle this by removing a reload when its only replacement
5899 is mentioned in reload_in of the reload we are going to inherit.
5900 A special case are auto_inc expressions; even if the input is
5901 inherited, we still need the address for the output. We can
5902 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5903 If we succeeded removing some reload and we are doing a preliminary
5904 pass just to remove such reloads, make another pass, since the
5905 removal of one reload might allow us to inherit another one. */
5907 && rld[r].out != rld[r].in
5908 && remove_address_replacements (rld[r].in) && pass)
5913 /* Now that reload_override_in is known valid,
5914 actually override reload_in. */
5915 for (j = 0; j < n_reloads; j++)
5916 if (reload_override_in[j])
5917 rld[j].in = reload_override_in[j];
5919 /* If this reload won't be done because it has been cancelled or is
5920 optional and not inherited, clear reload_reg_rtx so other
5921 routines (such as subst_reloads) don't get confused. */
5922 for (j = 0; j < n_reloads; j++)
5923 if (rld[j].reg_rtx != 0
5924 && ((rld[j].optional && ! reload_inherited[j])
5925 || (rld[j].in == 0 && rld[j].out == 0
5926 && ! rld[j].secondary_p)))
5928 int regno = true_regnum (rld[j].reg_rtx);
5930 if (spill_reg_order[regno] >= 0)
5931 clear_reload_reg_in_use (regno, rld[j].opnum,
5932 rld[j].when_needed, rld[j].mode);
5934 reload_spill_index[j] = -1;
5937 /* Record which pseudos and which spill regs have output reloads. */
5938 for (j = 0; j < n_reloads; j++)
5940 int r = reload_order[j];
5942 i = reload_spill_index[r];
5944 /* I is nonneg if this reload uses a register.
5945 If rld[r].reg_rtx is 0, this is an optional reload
5946 that we opted to ignore. */
5947 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5948 && rld[r].reg_rtx != 0)
5950 int nregno = REGNO (rld[r].out_reg);
5953 if (nregno < FIRST_PSEUDO_REGISTER)
5954 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5957 reg_has_output_reload[nregno + nr] = 1;
5961 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5963 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5966 if (rld[r].when_needed != RELOAD_OTHER
5967 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5968 && rld[r].when_needed != RELOAD_FOR_INSN)
5974 /* Deallocate the reload register for reload R. This is called from
5975 remove_address_replacements. */
5978 deallocate_reload_reg (r)
5983 if (! rld[r].reg_rtx)
5985 regno = true_regnum (rld[r].reg_rtx);
5987 if (spill_reg_order[regno] >= 0)
5988 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5990 reload_spill_index[r] = -1;
5993 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5994 reloads of the same item for fear that we might not have enough reload
5995 registers. However, normally they will get the same reload register
5996 and hence actually need not be loaded twice.
5998 Here we check for the most common case of this phenomenon: when we have
5999 a number of reloads for the same object, each of which were allocated
6000 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6001 reload, and is not modified in the insn itself. If we find such,
6002 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6003 This will not increase the number of spill registers needed and will
6004 prevent redundant code. */
6007 merge_assigned_reloads (insn)
6012 /* Scan all the reloads looking for ones that only load values and
6013 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6014 assigned and not modified by INSN. */
6016 for (i = 0; i < n_reloads; i++)
6018 int conflicting_input = 0;
6019 int max_input_address_opnum = -1;
6020 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6022 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6023 || rld[i].out != 0 || rld[i].reg_rtx == 0
6024 || reg_set_p (rld[i].reg_rtx, insn))
6027 /* Look at all other reloads. Ensure that the only use of this
6028 reload_reg_rtx is in a reload that just loads the same value
6029 as we do. Note that any secondary reloads must be of the identical
6030 class since the values, modes, and result registers are the
6031 same, so we need not do anything with any secondary reloads. */
6033 for (j = 0; j < n_reloads; j++)
6035 if (i == j || rld[j].reg_rtx == 0
6036 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6040 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6041 && rld[j].opnum > max_input_address_opnum)
6042 max_input_address_opnum = rld[j].opnum;
6044 /* If the reload regs aren't exactly the same (e.g, different modes)
6045 or if the values are different, we can't merge this reload.
6046 But if it is an input reload, we might still merge
6047 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6049 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6050 || rld[j].out != 0 || rld[j].in == 0
6051 || ! rtx_equal_p (rld[i].in, rld[j].in))
6053 if (rld[j].when_needed != RELOAD_FOR_INPUT
6054 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6055 || rld[i].opnum > rld[j].opnum)
6056 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6058 conflicting_input = 1;
6059 if (min_conflicting_input_opnum > rld[j].opnum)
6060 min_conflicting_input_opnum = rld[j].opnum;
6064 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6065 we, in fact, found any matching reloads. */
6068 && max_input_address_opnum <= min_conflicting_input_opnum)
6070 for (j = 0; j < n_reloads; j++)
6071 if (i != j && rld[j].reg_rtx != 0
6072 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6073 && (! conflicting_input
6074 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6075 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6077 rld[i].when_needed = RELOAD_OTHER;
6079 reload_spill_index[j] = -1;
6080 transfer_replacements (i, j);
6083 /* If this is now RELOAD_OTHER, look for any reloads that load
6084 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6085 if they were for inputs, RELOAD_OTHER for outputs. Note that
6086 this test is equivalent to looking for reloads for this operand
6089 if (rld[i].when_needed == RELOAD_OTHER)
6090 for (j = 0; j < n_reloads; j++)
6092 && rld[j].when_needed != RELOAD_OTHER
6093 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6096 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6097 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6098 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6103 /* These arrays are filled by emit_reload_insns and its subroutines. */
6104 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6105 static rtx other_input_address_reload_insns = 0;
6106 static rtx other_input_reload_insns = 0;
6107 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6108 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6109 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6110 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6111 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6112 static rtx operand_reload_insns = 0;
6113 static rtx other_operand_reload_insns = 0;
6114 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6116 /* Values to be put in spill_reg_store are put here first. */
6117 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6118 static HARD_REG_SET reg_reloaded_died;
6120 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6121 has the number J. OLD contains the value to be used as input. */
6124 emit_input_reload_insns (chain, rl, old, j)
6125 struct insn_chain *chain;
6130 rtx insn = chain->insn;
6131 rtx reloadreg = rl->reg_rtx;
6132 rtx oldequiv_reg = 0;
6135 enum machine_mode mode;
6138 /* Determine the mode to reload in.
6139 This is very tricky because we have three to choose from.
6140 There is the mode the insn operand wants (rl->inmode).
6141 There is the mode of the reload register RELOADREG.
6142 There is the intrinsic mode of the operand, which we could find
6143 by stripping some SUBREGs.
6144 It turns out that RELOADREG's mode is irrelevant:
6145 we can change that arbitrarily.
6147 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6148 then the reload reg may not support QImode moves, so use SImode.
6149 If foo is in memory due to spilling a pseudo reg, this is safe,
6150 because the QImode value is in the least significant part of a
6151 slot big enough for a SImode. If foo is some other sort of
6152 memory reference, then it is impossible to reload this case,
6153 so previous passes had better make sure this never happens.
6155 Then consider a one-word union which has SImode and one of its
6156 members is a float, being fetched as (SUBREG:SF union:SI).
6157 We must fetch that as SFmode because we could be loading into
6158 a float-only register. In this case OLD's mode is correct.
6160 Consider an immediate integer: it has VOIDmode. Here we need
6161 to get a mode from something else.
6163 In some cases, there is a fourth mode, the operand's
6164 containing mode. If the insn specifies a containing mode for
6165 this operand, it overrides all others.
6167 I am not sure whether the algorithm here is always right,
6168 but it does the right things in those cases. */
6170 mode = GET_MODE (old);
6171 if (mode == VOIDmode)
6174 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6175 /* If we need a secondary register for this operation, see if
6176 the value is already in a register in that class. Don't
6177 do this if the secondary register will be used as a scratch
6180 if (rl->secondary_in_reload >= 0
6181 && rl->secondary_in_icode == CODE_FOR_nothing
6184 = find_equiv_reg (old, insn,
6185 rld[rl->secondary_in_reload].class,
6189 /* If reloading from memory, see if there is a register
6190 that already holds the same value. If so, reload from there.
6191 We can pass 0 as the reload_reg_p argument because
6192 any other reload has either already been emitted,
6193 in which case find_equiv_reg will see the reload-insn,
6194 or has yet to be emitted, in which case it doesn't matter
6195 because we will use this equiv reg right away. */
6197 if (oldequiv == 0 && optimize
6198 && (GET_CODE (old) == MEM
6199 || (GET_CODE (old) == REG
6200 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6201 && reg_renumber[REGNO (old)] < 0)))
6202 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6206 unsigned int regno = true_regnum (oldequiv);
6208 /* Don't use OLDEQUIV if any other reload changes it at an
6209 earlier stage of this insn or at this stage. */
6210 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6211 rl->in, const0_rtx, j, 0))
6214 /* If it is no cheaper to copy from OLDEQUIV into the
6215 reload register than it would be to move from memory,
6216 don't use it. Likewise, if we need a secondary register
6220 && ((REGNO_REG_CLASS (regno) != rl->class
6221 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6223 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6224 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6225 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6229 #ifdef SECONDARY_MEMORY_NEEDED
6230 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6238 /* delete_output_reload is only invoked properly if old contains
6239 the original pseudo register. Since this is replaced with a
6240 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6241 find the pseudo in RELOAD_IN_REG. */
6243 && reload_override_in[j]
6244 && GET_CODE (rl->in_reg) == REG)
6251 else if (GET_CODE (oldequiv) == REG)
6252 oldequiv_reg = oldequiv;
6253 else if (GET_CODE (oldequiv) == SUBREG)
6254 oldequiv_reg = SUBREG_REG (oldequiv);
6256 /* If we are reloading from a register that was recently stored in
6257 with an output-reload, see if we can prove there was
6258 actually no need to store the old value in it. */
6260 if (optimize && GET_CODE (oldequiv) == REG
6261 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6262 && spill_reg_store[REGNO (oldequiv)]
6263 && GET_CODE (old) == REG
6264 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6265 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6267 delete_output_reload (insn, j, REGNO (oldequiv));
6269 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6270 then load RELOADREG from OLDEQUIV. Note that we cannot use
6271 gen_lowpart_common since it can do the wrong thing when
6272 RELOADREG has a multi-word mode. Note that RELOADREG
6273 must always be a REG here. */
6275 if (GET_MODE (reloadreg) != mode)
6276 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6277 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6278 oldequiv = SUBREG_REG (oldequiv);
6279 if (GET_MODE (oldequiv) != VOIDmode
6280 && mode != GET_MODE (oldequiv))
6281 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6283 /* Switch to the right place to emit the reload insns. */
6284 switch (rl->when_needed)
6287 where = &other_input_reload_insns;
6289 case RELOAD_FOR_INPUT:
6290 where = &input_reload_insns[rl->opnum];
6292 case RELOAD_FOR_INPUT_ADDRESS:
6293 where = &input_address_reload_insns[rl->opnum];
6295 case RELOAD_FOR_INPADDR_ADDRESS:
6296 where = &inpaddr_address_reload_insns[rl->opnum];
6298 case RELOAD_FOR_OUTPUT_ADDRESS:
6299 where = &output_address_reload_insns[rl->opnum];
6301 case RELOAD_FOR_OUTADDR_ADDRESS:
6302 where = &outaddr_address_reload_insns[rl->opnum];
6304 case RELOAD_FOR_OPERAND_ADDRESS:
6305 where = &operand_reload_insns;
6307 case RELOAD_FOR_OPADDR_ADDR:
6308 where = &other_operand_reload_insns;
6310 case RELOAD_FOR_OTHER_ADDRESS:
6311 where = &other_input_address_reload_insns;
6317 push_to_sequence (*where);
6319 /* Auto-increment addresses must be reloaded in a special way. */
6320 if (rl->out && ! rl->out_reg)
6322 /* We are not going to bother supporting the case where a
6323 incremented register can't be copied directly from
6324 OLDEQUIV since this seems highly unlikely. */
6325 if (rl->secondary_in_reload >= 0)
6328 if (reload_inherited[j])
6329 oldequiv = reloadreg;
6331 old = XEXP (rl->in_reg, 0);
6333 if (optimize && GET_CODE (oldequiv) == REG
6334 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6335 && spill_reg_store[REGNO (oldequiv)]
6336 && GET_CODE (old) == REG
6337 && (dead_or_set_p (insn,
6338 spill_reg_stored_to[REGNO (oldequiv)])
6339 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6341 delete_output_reload (insn, j, REGNO (oldequiv));
6343 /* Prevent normal processing of this reload. */
6345 /* Output a special code sequence for this case. */
6346 new_spill_reg_store[REGNO (reloadreg)]
6347 = inc_for_reload (reloadreg, oldequiv, rl->out,
6351 /* If we are reloading a pseudo-register that was set by the previous
6352 insn, see if we can get rid of that pseudo-register entirely
6353 by redirecting the previous insn into our reload register. */
6355 else if (optimize && GET_CODE (old) == REG
6356 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6357 && dead_or_set_p (insn, old)
6358 /* This is unsafe if some other reload
6359 uses the same reg first. */
6360 && ! conflicts_with_override (reloadreg)
6361 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6362 rl->when_needed, old, rl->out, j, 0))
6364 rtx temp = PREV_INSN (insn);
6365 while (temp && GET_CODE (temp) == NOTE)
6366 temp = PREV_INSN (temp);
6368 && GET_CODE (temp) == INSN
6369 && GET_CODE (PATTERN (temp)) == SET
6370 && SET_DEST (PATTERN (temp)) == old
6371 /* Make sure we can access insn_operand_constraint. */
6372 && asm_noperands (PATTERN (temp)) < 0
6373 /* This is unsafe if prev insn rejects our reload reg. */
6374 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6376 /* This is unsafe if operand occurs more than once in current
6377 insn. Perhaps some occurrences aren't reloaded. */
6378 && count_occurrences (PATTERN (insn), old, 0) == 1
6379 /* Don't risk splitting a matching pair of operands. */
6380 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6382 /* Store into the reload register instead of the pseudo. */
6383 SET_DEST (PATTERN (temp)) = reloadreg;
6385 /* If the previous insn is an output reload, the source is
6386 a reload register, and its spill_reg_store entry will
6387 contain the previous destination. This is now
6389 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6390 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6392 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6393 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6396 /* If these are the only uses of the pseudo reg,
6397 pretend for GDB it lives in the reload reg we used. */
6398 if (REG_N_DEATHS (REGNO (old)) == 1
6399 && REG_N_SETS (REGNO (old)) == 1)
6401 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6402 alter_reg (REGNO (old), -1);
6408 /* We can't do that, so output an insn to load RELOADREG. */
6410 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6411 /* If we have a secondary reload, pick up the secondary register
6412 and icode, if any. If OLDEQUIV and OLD are different or
6413 if this is an in-out reload, recompute whether or not we
6414 still need a secondary register and what the icode should
6415 be. If we still need a secondary register and the class or
6416 icode is different, go back to reloading from OLD if using
6417 OLDEQUIV means that we got the wrong type of register. We
6418 cannot have different class or icode due to an in-out reload
6419 because we don't make such reloads when both the input and
6420 output need secondary reload registers. */
6422 if (! special && rl->secondary_in_reload >= 0)
6424 rtx second_reload_reg = 0;
6425 int secondary_reload = rl->secondary_in_reload;
6426 rtx real_oldequiv = oldequiv;
6429 enum insn_code icode;
6431 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6432 and similarly for OLD.
6433 See comments in get_secondary_reload in reload.c. */
6434 /* If it is a pseudo that cannot be replaced with its
6435 equivalent MEM, we must fall back to reload_in, which
6436 will have all the necessary substitutions registered.
6437 Likewise for a pseudo that can't be replaced with its
6438 equivalent constant.
6440 Take extra care for subregs of such pseudos. Note that
6441 we cannot use reg_equiv_mem in this case because it is
6442 not in the right mode. */
6445 if (GET_CODE (tmp) == SUBREG)
6446 tmp = SUBREG_REG (tmp);
6447 if (GET_CODE (tmp) == REG
6448 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6449 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6450 || reg_equiv_constant[REGNO (tmp)] != 0))
6452 if (! reg_equiv_mem[REGNO (tmp)]
6453 || num_not_at_initial_offset
6454 || GET_CODE (oldequiv) == SUBREG)
6455 real_oldequiv = rl->in;
6457 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6461 if (GET_CODE (tmp) == SUBREG)
6462 tmp = SUBREG_REG (tmp);
6463 if (GET_CODE (tmp) == REG
6464 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6465 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6466 || reg_equiv_constant[REGNO (tmp)] != 0))
6468 if (! reg_equiv_mem[REGNO (tmp)]
6469 || num_not_at_initial_offset
6470 || GET_CODE (old) == SUBREG)
6473 real_old = reg_equiv_mem[REGNO (tmp)];
6476 second_reload_reg = rld[secondary_reload].reg_rtx;
6477 icode = rl->secondary_in_icode;
6479 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6480 || (rl->in != 0 && rl->out != 0))
6482 enum reg_class new_class
6483 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6484 mode, real_oldequiv);
6486 if (new_class == NO_REGS)
6487 second_reload_reg = 0;
6490 enum insn_code new_icode;
6491 enum machine_mode new_mode;
6493 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6494 REGNO (second_reload_reg)))
6495 oldequiv = old, real_oldequiv = real_old;
6498 new_icode = reload_in_optab[(int) mode];
6499 if (new_icode != CODE_FOR_nothing
6500 && ((insn_data[(int) new_icode].operand[0].predicate
6501 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6503 || (insn_data[(int) new_icode].operand[1].predicate
6504 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6505 (real_oldequiv, mode)))))
6506 new_icode = CODE_FOR_nothing;
6508 if (new_icode == CODE_FOR_nothing)
6511 new_mode = insn_data[(int) new_icode].operand[2].mode;
6513 if (GET_MODE (second_reload_reg) != new_mode)
6515 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6517 oldequiv = old, real_oldequiv = real_old;
6520 = gen_rtx_REG (new_mode,
6521 REGNO (second_reload_reg));
6527 /* If we still need a secondary reload register, check
6528 to see if it is being used as a scratch or intermediate
6529 register and generate code appropriately. If we need
6530 a scratch register, use REAL_OLDEQUIV since the form of
6531 the insn may depend on the actual address if it is
6534 if (second_reload_reg)
6536 if (icode != CODE_FOR_nothing)
6538 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6539 second_reload_reg));
6544 /* See if we need a scratch register to load the
6545 intermediate register (a tertiary reload). */
6546 enum insn_code tertiary_icode
6547 = rld[secondary_reload].secondary_in_icode;
6549 if (tertiary_icode != CODE_FOR_nothing)
6551 rtx third_reload_reg
6552 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6554 emit_insn ((GEN_FCN (tertiary_icode)
6555 (second_reload_reg, real_oldequiv,
6556 third_reload_reg)));
6559 gen_reload (second_reload_reg, real_oldequiv,
6563 oldequiv = second_reload_reg;
6569 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6571 rtx real_oldequiv = oldequiv;
6573 if ((GET_CODE (oldequiv) == REG
6574 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6575 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6576 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6577 || (GET_CODE (oldequiv) == SUBREG
6578 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6579 && (REGNO (SUBREG_REG (oldequiv))
6580 >= FIRST_PSEUDO_REGISTER)
6581 && ((reg_equiv_memory_loc
6582 [REGNO (SUBREG_REG (oldequiv))] != 0)
6583 || (reg_equiv_constant
6584 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6585 || (CONSTANT_P (oldequiv)
6586 && (PREFERRED_RELOAD_CLASS (oldequiv,
6587 REGNO_REG_CLASS (REGNO (reloadreg)))
6589 real_oldequiv = rl->in;
6590 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6594 if (flag_non_call_exceptions)
6595 copy_eh_notes (insn, get_insns ());
6597 /* End this sequence. */
6598 *where = get_insns ();
6601 /* Update reload_override_in so that delete_address_reloads_1
6602 can see the actual register usage. */
6604 reload_override_in[j] = oldequiv;
6607 /* Generate insns to for the output reload RL, which is for the insn described
6608 by CHAIN and has the number J. */
6610 emit_output_reload_insns (chain, rl, j)
6611 struct insn_chain *chain;
6615 rtx reloadreg = rl->reg_rtx;
6616 rtx insn = chain->insn;
6619 enum machine_mode mode = GET_MODE (old);
6622 if (rl->when_needed == RELOAD_OTHER)
6625 push_to_sequence (output_reload_insns[rl->opnum]);
6627 /* Determine the mode to reload in.
6628 See comments above (for input reloading). */
6630 if (mode == VOIDmode)
6632 /* VOIDmode should never happen for an output. */
6633 if (asm_noperands (PATTERN (insn)) < 0)
6634 /* It's the compiler's fault. */
6635 fatal_insn ("VOIDmode on an output", insn);
6636 error_for_asm (insn, "output operand is constant in `asm'");
6637 /* Prevent crash--use something we know is valid. */
6639 old = gen_rtx_REG (mode, REGNO (reloadreg));
6642 if (GET_MODE (reloadreg) != mode)
6643 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6645 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6647 /* If we need two reload regs, set RELOADREG to the intermediate
6648 one, since it will be stored into OLD. We might need a secondary
6649 register only for an input reload, so check again here. */
6651 if (rl->secondary_out_reload >= 0)
6655 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6656 && reg_equiv_mem[REGNO (old)] != 0)
6657 real_old = reg_equiv_mem[REGNO (old)];
6659 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6663 rtx second_reloadreg = reloadreg;
6664 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6666 /* See if RELOADREG is to be used as a scratch register
6667 or as an intermediate register. */
6668 if (rl->secondary_out_icode != CODE_FOR_nothing)
6670 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6671 (real_old, second_reloadreg, reloadreg)));
6676 /* See if we need both a scratch and intermediate reload
6679 int secondary_reload = rl->secondary_out_reload;
6680 enum insn_code tertiary_icode
6681 = rld[secondary_reload].secondary_out_icode;
6683 if (GET_MODE (reloadreg) != mode)
6684 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6686 if (tertiary_icode != CODE_FOR_nothing)
6689 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6692 /* Copy primary reload reg to secondary reload reg.
6693 (Note that these have been swapped above, then
6694 secondary reload reg to OLD using our insn.) */
6696 /* If REAL_OLD is a paradoxical SUBREG, remove it
6697 and try to put the opposite SUBREG on
6699 if (GET_CODE (real_old) == SUBREG
6700 && (GET_MODE_SIZE (GET_MODE (real_old))
6701 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6702 && 0 != (tem = gen_lowpart_common
6703 (GET_MODE (SUBREG_REG (real_old)),
6705 real_old = SUBREG_REG (real_old), reloadreg = tem;
6707 gen_reload (reloadreg, second_reloadreg,
6708 rl->opnum, rl->when_needed);
6709 emit_insn ((GEN_FCN (tertiary_icode)
6710 (real_old, reloadreg, third_reloadreg)));
6715 /* Copy between the reload regs here and then to
6718 gen_reload (reloadreg, second_reloadreg,
6719 rl->opnum, rl->when_needed);
6725 /* Output the last reload insn. */
6730 /* Don't output the last reload if OLD is not the dest of
6731 INSN and is in the src and is clobbered by INSN. */
6732 if (! flag_expensive_optimizations
6733 || GET_CODE (old) != REG
6734 || !(set = single_set (insn))
6735 || rtx_equal_p (old, SET_DEST (set))
6736 || !reg_mentioned_p (old, SET_SRC (set))
6737 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6738 gen_reload (old, reloadreg, rl->opnum,
6742 /* Look at all insns we emitted, just to be safe. */
6743 for (p = get_insns (); p; p = NEXT_INSN (p))
6746 rtx pat = PATTERN (p);
6748 /* If this output reload doesn't come from a spill reg,
6749 clear any memory of reloaded copies of the pseudo reg.
6750 If this output reload comes from a spill reg,
6751 reg_has_output_reload will make this do nothing. */
6752 note_stores (pat, forget_old_reloads_1, NULL);
6754 if (reg_mentioned_p (rl->reg_rtx, pat))
6756 rtx set = single_set (insn);
6757 if (reload_spill_index[j] < 0
6759 && SET_SRC (set) == rl->reg_rtx)
6761 int src = REGNO (SET_SRC (set));
6763 reload_spill_index[j] = src;
6764 SET_HARD_REG_BIT (reg_is_output_reload, src);
6765 if (find_regno_note (insn, REG_DEAD, src))
6766 SET_HARD_REG_BIT (reg_reloaded_died, src);
6768 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6770 int s = rl->secondary_out_reload;
6771 set = single_set (p);
6772 /* If this reload copies only to the secondary reload
6773 register, the secondary reload does the actual
6775 if (s >= 0 && set == NULL_RTX)
6776 /* We can't tell what function the secondary reload
6777 has and where the actual store to the pseudo is
6778 made; leave new_spill_reg_store alone. */
6781 && SET_SRC (set) == rl->reg_rtx
6782 && SET_DEST (set) == rld[s].reg_rtx)
6784 /* Usually the next instruction will be the
6785 secondary reload insn; if we can confirm
6786 that it is, setting new_spill_reg_store to
6787 that insn will allow an extra optimization. */
6788 rtx s_reg = rld[s].reg_rtx;
6789 rtx next = NEXT_INSN (p);
6790 rld[s].out = rl->out;
6791 rld[s].out_reg = rl->out_reg;
6792 set = single_set (next);
6793 if (set && SET_SRC (set) == s_reg
6794 && ! new_spill_reg_store[REGNO (s_reg)])
6796 SET_HARD_REG_BIT (reg_is_output_reload,
6798 new_spill_reg_store[REGNO (s_reg)] = next;
6802 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6807 if (rl->when_needed == RELOAD_OTHER)
6809 emit_insns (other_output_reload_insns[rl->opnum]);
6810 other_output_reload_insns[rl->opnum] = get_insns ();
6813 output_reload_insns[rl->opnum] = get_insns ();
6815 if (flag_non_call_exceptions)
6816 copy_eh_notes (insn, get_insns ());
6821 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6822 and has the number J. */
6824 do_input_reload (chain, rl, j)
6825 struct insn_chain *chain;
6829 int expect_occurrences = 1;
6830 rtx insn = chain->insn;
6831 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6832 ? rl->in_reg : rl->in);
6835 /* AUTO_INC reloads need to be handled even if inherited. We got an
6836 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6837 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6838 && ! rtx_equal_p (rl->reg_rtx, old)
6839 && rl->reg_rtx != 0)
6840 emit_input_reload_insns (chain, rld + j, old, j);
6842 /* When inheriting a wider reload, we have a MEM in rl->in,
6843 e.g. inheriting a SImode output reload for
6844 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6845 if (optimize && reload_inherited[j] && rl->in
6846 && GET_CODE (rl->in) == MEM
6847 && GET_CODE (rl->in_reg) == MEM
6848 && reload_spill_index[j] >= 0
6849 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6852 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6853 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6856 /* If we are reloading a register that was recently stored in with an
6857 output-reload, see if we can prove there was
6858 actually no need to store the old value in it. */
6861 && (reload_inherited[j] || reload_override_in[j])
6863 && GET_CODE (rl->reg_rtx) == REG
6864 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6866 /* There doesn't seem to be any reason to restrict this to pseudos
6867 and doing so loses in the case where we are copying from a
6868 register of the wrong class. */
6869 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6870 >= FIRST_PSEUDO_REGISTER)
6872 /* The insn might have already some references to stackslots
6873 replaced by MEMs, while reload_out_reg still names the
6875 && (dead_or_set_p (insn,
6876 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6877 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6879 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6882 /* Do output reloading for reload RL, which is for the insn described by
6883 CHAIN and has the number J.
6884 ??? At some point we need to support handling output reloads of
6885 JUMP_INSNs or insns that set cc0. */
6887 do_output_reload (chain, rl, j)
6888 struct insn_chain *chain;
6893 rtx insn = chain->insn;
6894 /* If this is an output reload that stores something that is
6895 not loaded in this same reload, see if we can eliminate a previous
6897 rtx pseudo = rl->out_reg;
6900 && GET_CODE (pseudo) == REG
6901 && ! rtx_equal_p (rl->in_reg, pseudo)
6902 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6903 && reg_last_reload_reg[REGNO (pseudo)])
6905 int pseudo_no = REGNO (pseudo);
6906 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6908 /* We don't need to test full validity of last_regno for
6909 inherit here; we only want to know if the store actually
6910 matches the pseudo. */
6911 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6912 && reg_reloaded_contents[last_regno] == pseudo_no
6913 && spill_reg_store[last_regno]
6914 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6915 delete_output_reload (insn, j, last_regno);
6920 || rl->reg_rtx == old
6921 || rl->reg_rtx == 0)
6924 /* An output operand that dies right away does need a reload,
6925 but need not be copied from it. Show the new location in the
6927 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6928 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6930 XEXP (note, 0) = rl->reg_rtx;
6933 /* Likewise for a SUBREG of an operand that dies. */
6934 else if (GET_CODE (old) == SUBREG
6935 && GET_CODE (SUBREG_REG (old)) == REG
6936 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6939 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6943 else if (GET_CODE (old) == SCRATCH)
6944 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6945 but we don't want to make an output reload. */
6948 /* If is a JUMP_INSN, we can't support output reloads yet. */
6949 if (GET_CODE (insn) == JUMP_INSN)
6952 emit_output_reload_insns (chain, rld + j, j);
6955 /* Output insns to reload values in and out of the chosen reload regs. */
6958 emit_reload_insns (chain)
6959 struct insn_chain *chain;
6961 rtx insn = chain->insn;
6965 CLEAR_HARD_REG_SET (reg_reloaded_died);
6967 for (j = 0; j < reload_n_operands; j++)
6968 input_reload_insns[j] = input_address_reload_insns[j]
6969 = inpaddr_address_reload_insns[j]
6970 = output_reload_insns[j] = output_address_reload_insns[j]
6971 = outaddr_address_reload_insns[j]
6972 = other_output_reload_insns[j] = 0;
6973 other_input_address_reload_insns = 0;
6974 other_input_reload_insns = 0;
6975 operand_reload_insns = 0;
6976 other_operand_reload_insns = 0;
6978 /* Dump reloads into the dump file. */
6981 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6982 debug_reload_to_stream (rtl_dump_file);
6985 /* Now output the instructions to copy the data into and out of the
6986 reload registers. Do these in the order that the reloads were reported,
6987 since reloads of base and index registers precede reloads of operands
6988 and the operands may need the base and index registers reloaded. */
6990 for (j = 0; j < n_reloads; j++)
6993 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6994 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6996 do_input_reload (chain, rld + j, j);
6997 do_output_reload (chain, rld + j, j);
7000 /* Now write all the insns we made for reloads in the order expected by
7001 the allocation functions. Prior to the insn being reloaded, we write
7002 the following reloads:
7004 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7006 RELOAD_OTHER reloads.
7008 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7009 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7010 RELOAD_FOR_INPUT reload for the operand.
7012 RELOAD_FOR_OPADDR_ADDRS reloads.
7014 RELOAD_FOR_OPERAND_ADDRESS reloads.
7016 After the insn being reloaded, we write the following:
7018 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7019 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7020 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7021 reloads for the operand. The RELOAD_OTHER output reloads are
7022 output in descending order by reload number. */
7024 emit_insns_before (other_input_address_reload_insns, insn);
7025 emit_insns_before (other_input_reload_insns, insn);
7027 for (j = 0; j < reload_n_operands; j++)
7029 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7030 emit_insns_before (input_address_reload_insns[j], insn);
7031 emit_insns_before (input_reload_insns[j], insn);
7034 emit_insns_before (other_operand_reload_insns, insn);
7035 emit_insns_before (operand_reload_insns, insn);
7037 for (j = 0; j < reload_n_operands; j++)
7039 rtx x = emit_insns_after (outaddr_address_reload_insns[j], insn);
7040 x = emit_insns_after (output_address_reload_insns[j], x);
7041 x = emit_insns_after (output_reload_insns[j], x);
7042 emit_insns_after (other_output_reload_insns[j], x);
7045 /* For all the spill regs newly reloaded in this instruction,
7046 record what they were reloaded from, so subsequent instructions
7047 can inherit the reloads.
7049 Update spill_reg_store for the reloads of this insn.
7050 Copy the elements that were updated in the loop above. */
7052 for (j = 0; j < n_reloads; j++)
7054 int r = reload_order[j];
7055 int i = reload_spill_index[r];
7057 /* If this is a non-inherited input reload from a pseudo, we must
7058 clear any memory of a previous store to the same pseudo. Only do
7059 something if there will not be an output reload for the pseudo
7061 if (rld[r].in_reg != 0
7062 && ! (reload_inherited[r] || reload_override_in[r]))
7064 rtx reg = rld[r].in_reg;
7066 if (GET_CODE (reg) == SUBREG)
7067 reg = SUBREG_REG (reg);
7069 if (GET_CODE (reg) == REG
7070 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7071 && ! reg_has_output_reload[REGNO (reg)])
7073 int nregno = REGNO (reg);
7075 if (reg_last_reload_reg[nregno])
7077 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7079 if (reg_reloaded_contents[last_regno] == nregno)
7080 spill_reg_store[last_regno] = 0;
7085 /* I is nonneg if this reload used a register.
7086 If rld[r].reg_rtx is 0, this is an optional reload
7087 that we opted to ignore. */
7089 if (i >= 0 && rld[r].reg_rtx != 0)
7091 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7093 int part_reaches_end = 0;
7094 int all_reaches_end = 1;
7096 /* For a multi register reload, we need to check if all or part
7097 of the value lives to the end. */
7098 for (k = 0; k < nr; k++)
7100 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7101 rld[r].when_needed))
7102 part_reaches_end = 1;
7104 all_reaches_end = 0;
7107 /* Ignore reloads that don't reach the end of the insn in
7109 if (all_reaches_end)
7111 /* First, clear out memory of what used to be in this spill reg.
7112 If consecutive registers are used, clear them all. */
7114 for (k = 0; k < nr; k++)
7115 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7117 /* Maybe the spill reg contains a copy of reload_out. */
7119 && (GET_CODE (rld[r].out) == REG
7123 || GET_CODE (rld[r].out_reg) == REG))
7125 rtx out = (GET_CODE (rld[r].out) == REG
7129 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7130 int nregno = REGNO (out);
7131 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7132 : HARD_REGNO_NREGS (nregno,
7133 GET_MODE (rld[r].reg_rtx)));
7135 spill_reg_store[i] = new_spill_reg_store[i];
7136 spill_reg_stored_to[i] = out;
7137 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7139 /* If NREGNO is a hard register, it may occupy more than
7140 one register. If it does, say what is in the
7141 rest of the registers assuming that both registers
7142 agree on how many words the object takes. If not,
7143 invalidate the subsequent registers. */
7145 if (nregno < FIRST_PSEUDO_REGISTER)
7146 for (k = 1; k < nnr; k++)
7147 reg_last_reload_reg[nregno + k]
7149 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7150 REGNO (rld[r].reg_rtx) + k)
7153 /* Now do the inverse operation. */
7154 for (k = 0; k < nr; k++)
7156 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7157 reg_reloaded_contents[i + k]
7158 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7161 reg_reloaded_insn[i + k] = insn;
7162 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7166 /* Maybe the spill reg contains a copy of reload_in. Only do
7167 something if there will not be an output reload for
7168 the register being reloaded. */
7169 else if (rld[r].out_reg == 0
7171 && ((GET_CODE (rld[r].in) == REG
7172 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7173 && ! reg_has_output_reload[REGNO (rld[r].in)])
7174 || (GET_CODE (rld[r].in_reg) == REG
7175 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7176 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7181 if (GET_CODE (rld[r].in) == REG
7182 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7183 nregno = REGNO (rld[r].in);
7184 else if (GET_CODE (rld[r].in_reg) == REG)
7185 nregno = REGNO (rld[r].in_reg);
7187 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7189 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7190 : HARD_REGNO_NREGS (nregno,
7191 GET_MODE (rld[r].reg_rtx)));
7193 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7195 if (nregno < FIRST_PSEUDO_REGISTER)
7196 for (k = 1; k < nnr; k++)
7197 reg_last_reload_reg[nregno + k]
7199 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7200 REGNO (rld[r].reg_rtx) + k)
7203 /* Unless we inherited this reload, show we haven't
7204 recently done a store.
7205 Previous stores of inherited auto_inc expressions
7206 also have to be discarded. */
7207 if (! reload_inherited[r]
7208 || (rld[r].out && ! rld[r].out_reg))
7209 spill_reg_store[i] = 0;
7211 for (k = 0; k < nr; k++)
7213 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7214 reg_reloaded_contents[i + k]
7215 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7218 reg_reloaded_insn[i + k] = insn;
7219 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7224 /* However, if part of the reload reaches the end, then we must
7225 invalidate the old info for the part that survives to the end. */
7226 else if (part_reaches_end)
7228 for (k = 0; k < nr; k++)
7229 if (reload_reg_reaches_end_p (i + k,
7231 rld[r].when_needed))
7232 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7236 /* The following if-statement was #if 0'd in 1.34 (or before...).
7237 It's reenabled in 1.35 because supposedly nothing else
7238 deals with this problem. */
7240 /* If a register gets output-reloaded from a non-spill register,
7241 that invalidates any previous reloaded copy of it.
7242 But forget_old_reloads_1 won't get to see it, because
7243 it thinks only about the original insn. So invalidate it here. */
7244 if (i < 0 && rld[r].out != 0
7245 && (GET_CODE (rld[r].out) == REG
7246 || (GET_CODE (rld[r].out) == MEM
7247 && GET_CODE (rld[r].out_reg) == REG)))
7249 rtx out = (GET_CODE (rld[r].out) == REG
7250 ? rld[r].out : rld[r].out_reg);
7251 int nregno = REGNO (out);
7252 if (nregno >= FIRST_PSEUDO_REGISTER)
7254 rtx src_reg, store_insn = NULL_RTX;
7256 reg_last_reload_reg[nregno] = 0;
7258 /* If we can find a hard register that is stored, record
7259 the storing insn so that we may delete this insn with
7260 delete_output_reload. */
7261 src_reg = rld[r].reg_rtx;
7263 /* If this is an optional reload, try to find the source reg
7264 from an input reload. */
7267 rtx set = single_set (insn);
7268 if (set && SET_DEST (set) == rld[r].out)
7272 src_reg = SET_SRC (set);
7274 for (k = 0; k < n_reloads; k++)
7276 if (rld[k].in == src_reg)
7278 src_reg = rld[k].reg_rtx;
7285 store_insn = new_spill_reg_store[REGNO (src_reg)];
7286 if (src_reg && GET_CODE (src_reg) == REG
7287 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7289 int src_regno = REGNO (src_reg);
7290 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7291 /* The place where to find a death note varies with
7292 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7293 necessarily checked exactly in the code that moves
7294 notes, so just check both locations. */
7295 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7296 if (! note && store_insn)
7297 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7300 spill_reg_store[src_regno + nr] = store_insn;
7301 spill_reg_stored_to[src_regno + nr] = out;
7302 reg_reloaded_contents[src_regno + nr] = nregno;
7303 reg_reloaded_insn[src_regno + nr] = store_insn;
7304 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7305 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7306 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7308 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7310 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7312 reg_last_reload_reg[nregno] = src_reg;
7317 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7319 while (num_regs-- > 0)
7320 reg_last_reload_reg[nregno + num_regs] = 0;
7324 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7327 /* Emit code to perform a reload from IN (which may be a reload register) to
7328 OUT (which may also be a reload register). IN or OUT is from operand
7329 OPNUM with reload type TYPE.
7331 Returns first insn emitted. */
7334 gen_reload (out, in, opnum, type)
7338 enum reload_type type;
7340 rtx last = get_last_insn ();
7343 /* If IN is a paradoxical SUBREG, remove it and try to put the
7344 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7345 if (GET_CODE (in) == SUBREG
7346 && (GET_MODE_SIZE (GET_MODE (in))
7347 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7348 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7349 in = SUBREG_REG (in), out = tem;
7350 else if (GET_CODE (out) == SUBREG
7351 && (GET_MODE_SIZE (GET_MODE (out))
7352 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7353 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7354 out = SUBREG_REG (out), in = tem;
7356 /* How to do this reload can get quite tricky. Normally, we are being
7357 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7358 register that didn't get a hard register. In that case we can just
7359 call emit_move_insn.
7361 We can also be asked to reload a PLUS that adds a register or a MEM to
7362 another register, constant or MEM. This can occur during frame pointer
7363 elimination and while reloading addresses. This case is handled by
7364 trying to emit a single insn to perform the add. If it is not valid,
7365 we use a two insn sequence.
7367 Finally, we could be called to handle an 'o' constraint by putting
7368 an address into a register. In that case, we first try to do this
7369 with a named pattern of "reload_load_address". If no such pattern
7370 exists, we just emit a SET insn and hope for the best (it will normally
7371 be valid on machines that use 'o').
7373 This entire process is made complex because reload will never
7374 process the insns we generate here and so we must ensure that
7375 they will fit their constraints and also by the fact that parts of
7376 IN might be being reloaded separately and replaced with spill registers.
7377 Because of this, we are, in some sense, just guessing the right approach
7378 here. The one listed above seems to work.
7380 ??? At some point, this whole thing needs to be rethought. */
7382 if (GET_CODE (in) == PLUS
7383 && (GET_CODE (XEXP (in, 0)) == REG
7384 || GET_CODE (XEXP (in, 0)) == SUBREG
7385 || GET_CODE (XEXP (in, 0)) == MEM)
7386 && (GET_CODE (XEXP (in, 1)) == REG
7387 || GET_CODE (XEXP (in, 1)) == SUBREG
7388 || CONSTANT_P (XEXP (in, 1))
7389 || GET_CODE (XEXP (in, 1)) == MEM))
7391 /* We need to compute the sum of a register or a MEM and another
7392 register, constant, or MEM, and put it into the reload
7393 register. The best possible way of doing this is if the machine
7394 has a three-operand ADD insn that accepts the required operands.
7396 The simplest approach is to try to generate such an insn and see if it
7397 is recognized and matches its constraints. If so, it can be used.
7399 It might be better not to actually emit the insn unless it is valid,
7400 but we need to pass the insn as an operand to `recog' and
7401 `extract_insn' and it is simpler to emit and then delete the insn if
7402 not valid than to dummy things up. */
7404 rtx op0, op1, tem, insn;
7407 op0 = find_replacement (&XEXP (in, 0));
7408 op1 = find_replacement (&XEXP (in, 1));
7410 /* Since constraint checking is strict, commutativity won't be
7411 checked, so we need to do that here to avoid spurious failure
7412 if the add instruction is two-address and the second operand
7413 of the add is the same as the reload reg, which is frequently
7414 the case. If the insn would be A = B + A, rearrange it so
7415 it will be A = A + B as constrain_operands expects. */
7417 if (GET_CODE (XEXP (in, 1)) == REG
7418 && REGNO (out) == REGNO (XEXP (in, 1)))
7419 tem = op0, op0 = op1, op1 = tem;
7421 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7422 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7424 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7425 code = recog_memoized (insn);
7429 extract_insn (insn);
7430 /* We want constrain operands to treat this insn strictly in
7431 its validity determination, i.e., the way it would after reload
7433 if (constrain_operands (1))
7437 delete_insns_since (last);
7439 /* If that failed, we must use a conservative two-insn sequence.
7441 Use a move to copy one operand into the reload register. Prefer
7442 to reload a constant, MEM or pseudo since the move patterns can
7443 handle an arbitrary operand. If OP1 is not a constant, MEM or
7444 pseudo and OP1 is not a valid operand for an add instruction, then
7447 After reloading one of the operands into the reload register, add
7448 the reload register to the output register.
7450 If there is another way to do this for a specific machine, a
7451 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7454 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7456 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7457 || (GET_CODE (op1) == REG
7458 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7459 || (code != CODE_FOR_nothing
7460 && ! ((*insn_data[code].operand[2].predicate)
7461 (op1, insn_data[code].operand[2].mode))))
7462 tem = op0, op0 = op1, op1 = tem;
7464 gen_reload (out, op0, opnum, type);
7466 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7467 This fixes a problem on the 32K where the stack pointer cannot
7468 be used as an operand of an add insn. */
7470 if (rtx_equal_p (op0, op1))
7473 insn = emit_insn (gen_add2_insn (out, op1));
7475 /* If that failed, copy the address register to the reload register.
7476 Then add the constant to the reload register. */
7478 code = recog_memoized (insn);
7482 extract_insn (insn);
7483 /* We want constrain operands to treat this insn strictly in
7484 its validity determination, i.e., the way it would after reload
7486 if (constrain_operands (1))
7488 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7490 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7495 delete_insns_since (last);
7497 gen_reload (out, op1, opnum, type);
7498 insn = emit_insn (gen_add2_insn (out, op0));
7499 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7502 #ifdef SECONDARY_MEMORY_NEEDED
7503 /* If we need a memory location to do the move, do it that way. */
7504 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7505 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7506 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7507 REGNO_REG_CLASS (REGNO (out)),
7510 /* Get the memory to use and rewrite both registers to its mode. */
7511 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7513 if (GET_MODE (loc) != GET_MODE (out))
7514 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7516 if (GET_MODE (loc) != GET_MODE (in))
7517 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7519 gen_reload (loc, in, opnum, type);
7520 gen_reload (out, loc, opnum, type);
7524 /* If IN is a simple operand, use gen_move_insn. */
7525 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7526 emit_insn (gen_move_insn (out, in));
7528 #ifdef HAVE_reload_load_address
7529 else if (HAVE_reload_load_address)
7530 emit_insn (gen_reload_load_address (out, in));
7533 /* Otherwise, just write (set OUT IN) and hope for the best. */
7535 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7537 /* Return the first insn emitted.
7538 We can not just return get_last_insn, because there may have
7539 been multiple instructions emitted. Also note that gen_move_insn may
7540 emit more than one insn itself, so we can not assume that there is one
7541 insn emitted per emit_insn_before call. */
7543 return last ? NEXT_INSN (last) : get_insns ();
7546 /* Delete a previously made output-reload
7547 whose result we now believe is not needed.
7548 First we double-check.
7550 INSN is the insn now being processed.
7551 LAST_RELOAD_REG is the hard register number for which we want to delete
7552 the last output reload.
7553 J is the reload-number that originally used REG. The caller has made
7554 certain that reload J doesn't use REG any longer for input. */
7557 delete_output_reload (insn, j, last_reload_reg)
7560 int last_reload_reg;
7562 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7563 rtx reg = spill_reg_stored_to[last_reload_reg];
7566 int n_inherited = 0;
7570 /* Get the raw pseudo-register referred to. */
7572 while (GET_CODE (reg) == SUBREG)
7573 reg = SUBREG_REG (reg);
7574 substed = reg_equiv_memory_loc[REGNO (reg)];
7576 /* This is unsafe if the operand occurs more often in the current
7577 insn than it is inherited. */
7578 for (k = n_reloads - 1; k >= 0; k--)
7580 rtx reg2 = rld[k].in;
7583 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7584 reg2 = rld[k].in_reg;
7586 if (rld[k].out && ! rld[k].out_reg)
7587 reg2 = XEXP (rld[k].in_reg, 0);
7589 while (GET_CODE (reg2) == SUBREG)
7590 reg2 = SUBREG_REG (reg2);
7591 if (rtx_equal_p (reg2, reg))
7593 if (reload_inherited[k] || reload_override_in[k] || k == j)
7596 reg2 = rld[k].out_reg;
7599 while (GET_CODE (reg2) == SUBREG)
7600 reg2 = XEXP (reg2, 0);
7601 if (rtx_equal_p (reg2, reg))
7608 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7610 n_occurrences += count_occurrences (PATTERN (insn),
7611 eliminate_regs (substed, 0,
7613 if (n_occurrences > n_inherited)
7616 /* If the pseudo-reg we are reloading is no longer referenced
7617 anywhere between the store into it and here,
7618 and no jumps or labels intervene, then the value can get
7619 here through the reload reg alone.
7620 Otherwise, give up--return. */
7621 for (i1 = NEXT_INSN (output_reload_insn);
7622 i1 != insn; i1 = NEXT_INSN (i1))
7624 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7626 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7627 && reg_mentioned_p (reg, PATTERN (i1)))
7629 /* If this is USE in front of INSN, we only have to check that
7630 there are no more references than accounted for by inheritance. */
7631 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7633 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7634 i1 = NEXT_INSN (i1);
7636 if (n_occurrences <= n_inherited && i1 == insn)
7642 /* The caller has already checked that REG dies or is set in INSN.
7643 It has also checked that we are optimizing, and thus some inaccurancies
7644 in the debugging information are acceptable.
7645 So we could just delete output_reload_insn.
7646 But in some cases we can improve the debugging information without
7647 sacrificing optimization - maybe even improving the code:
7648 See if the pseudo reg has been completely replaced
7649 with reload regs. If so, delete the store insn
7650 and forget we had a stack slot for the pseudo. */
7651 if (rld[j].out != rld[j].in
7652 && REG_N_DEATHS (REGNO (reg)) == 1
7653 && REG_N_SETS (REGNO (reg)) == 1
7654 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7655 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7659 /* We know that it was used only between here
7660 and the beginning of the current basic block.
7661 (We also know that the last use before INSN was
7662 the output reload we are thinking of deleting, but never mind that.)
7663 Search that range; see if any ref remains. */
7664 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7666 rtx set = single_set (i2);
7668 /* Uses which just store in the pseudo don't count,
7669 since if they are the only uses, they are dead. */
7670 if (set != 0 && SET_DEST (set) == reg)
7672 if (GET_CODE (i2) == CODE_LABEL
7673 || GET_CODE (i2) == JUMP_INSN)
7675 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7676 && reg_mentioned_p (reg, PATTERN (i2)))
7678 /* Some other ref remains; just delete the output reload we
7680 delete_address_reloads (output_reload_insn, insn);
7681 delete_insn (output_reload_insn);
7686 /* Delete the now-dead stores into this pseudo. */
7687 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7689 rtx set = single_set (i2);
7691 if (set != 0 && SET_DEST (set) == reg)
7693 delete_address_reloads (i2, insn);
7694 /* This might be a basic block head,
7695 thus don't use delete_insn. */
7698 if (GET_CODE (i2) == CODE_LABEL
7699 || GET_CODE (i2) == JUMP_INSN)
7703 /* For the debugging info,
7704 say the pseudo lives in this reload reg. */
7705 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7706 alter_reg (REGNO (reg), -1);
7708 delete_address_reloads (output_reload_insn, insn);
7709 delete_insn (output_reload_insn);
7713 /* We are going to delete DEAD_INSN. Recursively delete loads of
7714 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7715 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7717 delete_address_reloads (dead_insn, current_insn)
7718 rtx dead_insn, current_insn;
7720 rtx set = single_set (dead_insn);
7721 rtx set2, dst, prev, next;
7724 rtx dst = SET_DEST (set);
7725 if (GET_CODE (dst) == MEM)
7726 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7728 /* If we deleted the store from a reloaded post_{in,de}c expression,
7729 we can delete the matching adds. */
7730 prev = PREV_INSN (dead_insn);
7731 next = NEXT_INSN (dead_insn);
7732 if (! prev || ! next)
7734 set = single_set (next);
7735 set2 = single_set (prev);
7737 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7738 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7739 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7741 dst = SET_DEST (set);
7742 if (! rtx_equal_p (dst, SET_DEST (set2))
7743 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7744 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7745 || (INTVAL (XEXP (SET_SRC (set), 1))
7746 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7748 delete_related_insns (prev);
7749 delete_related_insns (next);
7752 /* Subfunction of delete_address_reloads: process registers found in X. */
7754 delete_address_reloads_1 (dead_insn, x, current_insn)
7755 rtx dead_insn, x, current_insn;
7757 rtx prev, set, dst, i2;
7759 enum rtx_code code = GET_CODE (x);
7763 const char *fmt = GET_RTX_FORMAT (code);
7764 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7767 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7768 else if (fmt[i] == 'E')
7770 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7771 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7778 if (spill_reg_order[REGNO (x)] < 0)
7781 /* Scan backwards for the insn that sets x. This might be a way back due
7783 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7785 code = GET_CODE (prev);
7786 if (code == CODE_LABEL || code == JUMP_INSN)
7788 if (GET_RTX_CLASS (code) != 'i')
7790 if (reg_set_p (x, PATTERN (prev)))
7792 if (reg_referenced_p (x, PATTERN (prev)))
7795 if (! prev || INSN_UID (prev) < reload_first_uid)
7797 /* Check that PREV only sets the reload register. */
7798 set = single_set (prev);
7801 dst = SET_DEST (set);
7802 if (GET_CODE (dst) != REG
7803 || ! rtx_equal_p (dst, x))
7805 if (! reg_set_p (dst, PATTERN (dead_insn)))
7807 /* Check if DST was used in a later insn -
7808 it might have been inherited. */
7809 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7811 if (GET_CODE (i2) == CODE_LABEL)
7815 if (reg_referenced_p (dst, PATTERN (i2)))
7817 /* If there is a reference to the register in the current insn,
7818 it might be loaded in a non-inherited reload. If no other
7819 reload uses it, that means the register is set before
7821 if (i2 == current_insn)
7823 for (j = n_reloads - 1; j >= 0; j--)
7824 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7825 || reload_override_in[j] == dst)
7827 for (j = n_reloads - 1; j >= 0; j--)
7828 if (rld[j].in && rld[j].reg_rtx == dst)
7835 if (GET_CODE (i2) == JUMP_INSN)
7837 /* If DST is still live at CURRENT_INSN, check if it is used for
7838 any reload. Note that even if CURRENT_INSN sets DST, we still
7839 have to check the reloads. */
7840 if (i2 == current_insn)
7842 for (j = n_reloads - 1; j >= 0; j--)
7843 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7844 || reload_override_in[j] == dst)
7846 /* ??? We can't finish the loop here, because dst might be
7847 allocated to a pseudo in this block if no reload in this
7848 block needs any of the clsses containing DST - see
7849 spill_hard_reg. There is no easy way to tell this, so we
7850 have to scan till the end of the basic block. */
7852 if (reg_set_p (dst, PATTERN (i2)))
7856 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7857 reg_reloaded_contents[REGNO (dst)] = -1;
7861 /* Output reload-insns to reload VALUE into RELOADREG.
7862 VALUE is an autoincrement or autodecrement RTX whose operand
7863 is a register or memory location;
7864 so reloading involves incrementing that location.
7865 IN is either identical to VALUE, or some cheaper place to reload from.
7867 INC_AMOUNT is the number to increment or decrement by (always positive).
7868 This cannot be deduced from VALUE.
7870 Return the instruction that stores into RELOADREG. */
7873 inc_for_reload (reloadreg, in, value, inc_amount)
7878 /* REG or MEM to be copied and incremented. */
7879 rtx incloc = XEXP (value, 0);
7880 /* Nonzero if increment after copying. */
7881 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7887 rtx real_in = in == value ? XEXP (in, 0) : in;
7889 /* No hard register is equivalent to this register after
7890 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7891 we could inc/dec that register as well (maybe even using it for
7892 the source), but I'm not sure it's worth worrying about. */
7893 if (GET_CODE (incloc) == REG)
7894 reg_last_reload_reg[REGNO (incloc)] = 0;
7896 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7897 inc_amount = -inc_amount;
7899 inc = GEN_INT (inc_amount);
7901 /* If this is post-increment, first copy the location to the reload reg. */
7902 if (post && real_in != reloadreg)
7903 emit_insn (gen_move_insn (reloadreg, real_in));
7907 /* See if we can directly increment INCLOC. Use a method similar to
7908 that in gen_reload. */
7910 last = get_last_insn ();
7911 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7912 gen_rtx_PLUS (GET_MODE (incloc),
7915 code = recog_memoized (add_insn);
7918 extract_insn (add_insn);
7919 if (constrain_operands (1))
7921 /* If this is a pre-increment and we have incremented the value
7922 where it lives, copy the incremented value to RELOADREG to
7923 be used as an address. */
7926 emit_insn (gen_move_insn (reloadreg, incloc));
7931 delete_insns_since (last);
7934 /* If couldn't do the increment directly, must increment in RELOADREG.
7935 The way we do this depends on whether this is pre- or post-increment.
7936 For pre-increment, copy INCLOC to the reload register, increment it
7937 there, then save back. */
7941 if (in != reloadreg)
7942 emit_insn (gen_move_insn (reloadreg, real_in));
7943 emit_insn (gen_add2_insn (reloadreg, inc));
7944 store = emit_insn (gen_move_insn (incloc, reloadreg));
7949 Because this might be a jump insn or a compare, and because RELOADREG
7950 may not be available after the insn in an input reload, we must do
7951 the incrementation before the insn being reloaded for.
7953 We have already copied IN to RELOADREG. Increment the copy in
7954 RELOADREG, save that back, then decrement RELOADREG so it has
7955 the original value. */
7957 emit_insn (gen_add2_insn (reloadreg, inc));
7958 store = emit_insn (gen_move_insn (incloc, reloadreg));
7959 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7965 /* Return 1 if we are certain that the constraint-string STRING allows
7966 the hard register REG. Return 0 if we can't be sure of this. */
7969 constraint_accepts_reg_p (string, reg)
7974 int regno = true_regnum (reg);
7977 /* Initialize for first alternative. */
7979 /* Check that each alternative contains `g' or `r'. */
7981 switch (c = *string++)
7984 /* If an alternative lacks `g' or `r', we lose. */
7987 /* If an alternative lacks `g' or `r', we lose. */
7990 /* Initialize for next alternative. */
7995 /* Any general reg wins for this alternative. */
7996 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
8000 /* Any reg in specified class wins for this alternative. */
8002 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8004 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8010 /* INSN is a no-op; delete it.
8011 If this sets the return value of the function, we must keep a USE around,
8012 in case this is in a different basic block than the final USE. Otherwise,
8013 we could loose important register lifeness information on
8014 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8015 spills: subsequent passes assume that spill registers are dead at the end
8017 VALUE must be the return value in such a case, NULL otherwise. */
8019 reload_cse_delete_noop_set (insn, value)
8024 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8025 INSN_CODE (insn) = -1;
8026 REG_NOTES (insn) = NULL_RTX;
8032 /* See whether a single set SET is a noop. */
8034 reload_cse_noop_set_p (set)
8037 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8040 /* Try to simplify INSN. */
8042 reload_cse_simplify (insn)
8045 rtx body = PATTERN (insn);
8047 if (GET_CODE (body) == SET)
8051 /* Simplify even if we may think it is a no-op.
8052 We may think a memory load of a value smaller than WORD_SIZE
8053 is redundant because we haven't taken into account possible
8054 implicit extension. reload_cse_simplify_set() will bring
8055 this out, so it's safer to simplify before we delete. */
8056 count += reload_cse_simplify_set (body, insn);
8058 if (!count && reload_cse_noop_set_p (body))
8060 rtx value = SET_DEST (body);
8061 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8063 reload_cse_delete_noop_set (insn, value);
8068 apply_change_group ();
8070 reload_cse_simplify_operands (insn);
8072 else if (GET_CODE (body) == PARALLEL)
8076 rtx value = NULL_RTX;
8078 /* If every action in a PARALLEL is a noop, we can delete
8079 the entire PARALLEL. */
8080 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8082 rtx part = XVECEXP (body, 0, i);
8083 if (GET_CODE (part) == SET)
8085 if (! reload_cse_noop_set_p (part))
8087 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8091 value = SET_DEST (part);
8094 else if (GET_CODE (part) != CLOBBER)
8100 reload_cse_delete_noop_set (insn, value);
8101 /* We're done with this insn. */
8105 /* It's not a no-op, but we can try to simplify it. */
8106 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8107 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8108 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8111 apply_change_group ();
8113 reload_cse_simplify_operands (insn);
8117 /* Do a very simple CSE pass over the hard registers.
8119 This function detects no-op moves where we happened to assign two
8120 different pseudo-registers to the same hard register, and then
8121 copied one to the other. Reload will generate a useless
8122 instruction copying a register to itself.
8124 This function also detects cases where we load a value from memory
8125 into two different registers, and (if memory is more expensive than
8126 registers) changes it to simply copy the first register into the
8129 Another optimization is performed that scans the operands of each
8130 instruction to see whether the value is already available in a
8131 hard register. It then replaces the operand with the hard register
8132 if possible, much like an optional reload would. */
8135 reload_cse_regs_1 (first)
8141 init_alias_analysis ();
8143 for (insn = first; insn; insn = NEXT_INSN (insn))
8146 reload_cse_simplify (insn);
8148 cselib_process_insn (insn);
8152 end_alias_analysis ();
8156 /* Call cse / combine like post-reload optimization phases.
8157 FIRST is the first instruction. */
8159 reload_cse_regs (first)
8162 reload_cse_regs_1 (first);
8164 reload_cse_move2add (first);
8165 if (flag_expensive_optimizations)
8166 reload_cse_regs_1 (first);
8169 /* Try to simplify a single SET instruction. SET is the set pattern.
8170 INSN is the instruction it came from.
8171 This function only handles one case: if we set a register to a value
8172 which is not a register, we try to find that value in some other register
8173 and change the set into a register copy. */
8176 reload_cse_simplify_set (set, insn)
8183 enum reg_class dclass;
8186 struct elt_loc_list *l;
8187 #ifdef LOAD_EXTEND_OP
8188 enum rtx_code extend_op = NIL;
8191 dreg = true_regnum (SET_DEST (set));
8195 src = SET_SRC (set);
8196 if (side_effects_p (src) || true_regnum (src) >= 0)
8199 dclass = REGNO_REG_CLASS (dreg);
8201 #ifdef LOAD_EXTEND_OP
8202 /* When replacing a memory with a register, we need to honor assumptions
8203 that combine made wrt the contents of sign bits. We'll do this by
8204 generating an extend instruction instead of a reg->reg copy. Thus
8205 the destination must be a register that we can widen. */
8206 if (GET_CODE (src) == MEM
8207 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8208 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8209 && GET_CODE (SET_DEST (set)) != REG)
8213 /* If memory loads are cheaper than register copies, don't change them. */
8214 if (GET_CODE (src) == MEM)
8215 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8216 else if (CONSTANT_P (src))
8217 old_cost = rtx_cost (src, SET);
8218 else if (GET_CODE (src) == REG)
8219 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8220 REGNO_REG_CLASS (REGNO (src)), dclass);
8223 old_cost = rtx_cost (src, SET);
8225 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8228 for (l = val->locs; l; l = l->next)
8230 rtx this_rtx = l->loc;
8233 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8235 #ifdef LOAD_EXTEND_OP
8236 if (extend_op != NIL)
8238 HOST_WIDE_INT this_val;
8240 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8241 constants, such as SYMBOL_REF, cannot be extended. */
8242 if (GET_CODE (this_rtx) != CONST_INT)
8245 this_val = INTVAL (this_rtx);
8249 this_val &= GET_MODE_MASK (GET_MODE (src));
8252 /* ??? In theory we're already extended. */
8253 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8258 this_rtx = GEN_INT (this_val);
8261 this_cost = rtx_cost (this_rtx, SET);
8263 else if (GET_CODE (this_rtx) == REG)
8265 #ifdef LOAD_EXTEND_OP
8266 if (extend_op != NIL)
8268 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8269 this_cost = rtx_cost (this_rtx, SET);
8273 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8274 REGNO_REG_CLASS (REGNO (this_rtx)),
8280 /* If equal costs, prefer registers over anything else. That
8281 tends to lead to smaller instructions on some machines. */
8282 if (this_cost < old_cost
8283 || (this_cost == old_cost
8284 && GET_CODE (this_rtx) == REG
8285 && GET_CODE (SET_SRC (set)) != REG))
8287 #ifdef LOAD_EXTEND_OP
8288 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8289 && extend_op != NIL)
8291 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8292 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8293 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8297 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8298 old_cost = this_cost, did_change = 1;
8305 /* Try to replace operands in INSN with equivalent values that are already
8306 in registers. This can be viewed as optional reloading.
8308 For each non-register operand in the insn, see if any hard regs are
8309 known to be equivalent to that operand. Record the alternatives which
8310 can accept these hard registers. Among all alternatives, select the
8311 ones which are better or equal to the one currently matching, where
8312 "better" is in terms of '?' and '!' constraints. Among the remaining
8313 alternatives, select the one which replaces most operands with
8317 reload_cse_simplify_operands (insn)
8322 /* For each operand, all registers that are equivalent to it. */
8323 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8325 const char *constraints[MAX_RECOG_OPERANDS];
8327 /* Vector recording how bad an alternative is. */
8328 int *alternative_reject;
8329 /* Vector recording how many registers can be introduced by choosing
8330 this alternative. */
8331 int *alternative_nregs;
8332 /* Array of vectors recording, for each operand and each alternative,
8333 which hard register to substitute, or -1 if the operand should be
8335 int *op_alt_regno[MAX_RECOG_OPERANDS];
8336 /* Array of alternatives, sorted in order of decreasing desirability. */
8337 int *alternative_order;
8338 rtx reg = gen_rtx_REG (VOIDmode, -1);
8340 extract_insn (insn);
8342 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8345 /* Figure out which alternative currently matches. */
8346 if (! constrain_operands (1))
8347 fatal_insn_not_found (insn);
8349 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8350 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8351 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8352 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8353 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8355 /* For each operand, find out which regs are equivalent. */
8356 for (i = 0; i < recog_data.n_operands; i++)
8359 struct elt_loc_list *l;
8361 CLEAR_HARD_REG_SET (equiv_regs[i]);
8363 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8364 right, so avoid the problem here. Likewise if we have a constant
8365 and the insn pattern doesn't tell us the mode we need. */
8366 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8367 || (CONSTANT_P (recog_data.operand[i])
8368 && recog_data.operand_mode[i] == VOIDmode))
8371 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8375 for (l = v->locs; l; l = l->next)
8376 if (GET_CODE (l->loc) == REG)
8377 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8380 for (i = 0; i < recog_data.n_operands; i++)
8382 enum machine_mode mode;
8386 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8387 for (j = 0; j < recog_data.n_alternatives; j++)
8388 op_alt_regno[i][j] = -1;
8390 p = constraints[i] = recog_data.constraints[i];
8391 mode = recog_data.operand_mode[i];
8393 /* Add the reject values for each alternative given by the constraints
8394 for this operand. */
8402 alternative_reject[j] += 3;
8404 alternative_reject[j] += 300;
8407 /* We won't change operands which are already registers. We
8408 also don't want to modify output operands. */
8409 regno = true_regnum (recog_data.operand[i]);
8411 || constraints[i][0] == '='
8412 || constraints[i][0] == '+')
8415 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8417 int class = (int) NO_REGS;
8419 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8422 REGNO (reg) = regno;
8423 PUT_MODE (reg, mode);
8425 /* We found a register equal to this operand. Now look for all
8426 alternatives that can accept this register and have not been
8427 assigned a register they can use yet. */
8436 case '=': case '+': case '?':
8437 case '#': case '&': case '!':
8439 case '0': case '1': case '2': case '3': case '4':
8440 case '5': case '6': case '7': case '8': case '9':
8441 case 'm': case '<': case '>': case 'V': case 'o':
8442 case 'E': case 'F': case 'G': case 'H':
8443 case 's': case 'i': case 'n':
8444 case 'I': case 'J': case 'K': case 'L':
8445 case 'M': case 'N': case 'O': case 'P':
8447 /* These don't say anything we care about. */
8451 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8456 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8459 case ',': case '\0':
8460 /* See if REGNO fits this alternative, and set it up as the
8461 replacement register if we don't have one for this
8462 alternative yet and the operand being replaced is not
8463 a cheap CONST_INT. */
8464 if (op_alt_regno[i][j] == -1
8465 && reg_fits_class_p (reg, class, 0, mode)
8466 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8467 || (rtx_cost (recog_data.operand[i], SET)
8468 > rtx_cost (reg, SET))))
8470 alternative_nregs[j]++;
8471 op_alt_regno[i][j] = regno;
8483 /* Record all alternatives which are better or equal to the currently
8484 matching one in the alternative_order array. */
8485 for (i = j = 0; i < recog_data.n_alternatives; i++)
8486 if (alternative_reject[i] <= alternative_reject[which_alternative])
8487 alternative_order[j++] = i;
8488 recog_data.n_alternatives = j;
8490 /* Sort it. Given a small number of alternatives, a dumb algorithm
8491 won't hurt too much. */
8492 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8495 int best_reject = alternative_reject[alternative_order[i]];
8496 int best_nregs = alternative_nregs[alternative_order[i]];
8499 for (j = i + 1; j < recog_data.n_alternatives; j++)
8501 int this_reject = alternative_reject[alternative_order[j]];
8502 int this_nregs = alternative_nregs[alternative_order[j]];
8504 if (this_reject < best_reject
8505 || (this_reject == best_reject && this_nregs < best_nregs))
8508 best_reject = this_reject;
8509 best_nregs = this_nregs;
8513 tmp = alternative_order[best];
8514 alternative_order[best] = alternative_order[i];
8515 alternative_order[i] = tmp;
8518 /* Substitute the operands as determined by op_alt_regno for the best
8520 j = alternative_order[0];
8522 for (i = 0; i < recog_data.n_operands; i++)
8524 enum machine_mode mode = recog_data.operand_mode[i];
8525 if (op_alt_regno[i][j] == -1)
8528 validate_change (insn, recog_data.operand_loc[i],
8529 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8532 for (i = recog_data.n_dups - 1; i >= 0; i--)
8534 int op = recog_data.dup_num[i];
8535 enum machine_mode mode = recog_data.operand_mode[op];
8537 if (op_alt_regno[op][j] == -1)
8540 validate_change (insn, recog_data.dup_loc[i],
8541 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8544 return apply_change_group ();
8547 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8549 This code might also be useful when reload gave up on reg+reg addresssing
8550 because of clashes between the return register and INDEX_REG_CLASS. */
8552 /* The maximum number of uses of a register we can keep track of to
8553 replace them with reg+reg addressing. */
8554 #define RELOAD_COMBINE_MAX_USES 6
8556 /* INSN is the insn where a register has ben used, and USEP points to the
8557 location of the register within the rtl. */
8558 struct reg_use { rtx insn, *usep; };
8560 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8561 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8562 indicates where it becomes live again.
8563 Otherwise, USE_INDEX is the index of the last encountered use of the
8564 register (which is first among these we have seen since we scan backwards),
8565 OFFSET contains the constant offset that is added to the register in
8566 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8567 last, of these uses.
8568 STORE_RUID is always meaningful if we only want to use a value in a
8569 register in a different place: it denotes the next insn in the insn
8570 stream (i.e. the last ecountered) that sets or clobbers the register. */
8573 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8578 } reg_state[FIRST_PSEUDO_REGISTER];
8580 /* Reverse linear uid. This is increased in reload_combine while scanning
8581 the instructions from last to first. It is used to set last_label_ruid
8582 and the store_ruid / use_ruid fields in reg_state. */
8583 static int reload_combine_ruid;
8585 #define LABEL_LIVE(LABEL) \
8586 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8592 int first_index_reg = -1;
8593 int last_index_reg = 0;
8596 int last_label_ruid;
8597 int min_labelno, n_labels;
8598 HARD_REG_SET ever_live_at_start, *label_live;
8600 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8601 reload has already used it where appropriate, so there is no use in
8602 trying to generate it now. */
8603 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8606 /* To avoid wasting too much time later searching for an index register,
8607 determine the minimum and maximum index register numbers. */
8608 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8609 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8611 if (first_index_reg == -1)
8612 first_index_reg = r;
8617 /* If no index register is available, we can quit now. */
8618 if (first_index_reg == -1)
8621 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8622 information is a bit fuzzy immediately after reload, but it's
8623 still good enough to determine which registers are live at a jump
8625 min_labelno = get_first_label_num ();
8626 n_labels = max_label_num () - min_labelno;
8627 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8628 CLEAR_HARD_REG_SET (ever_live_at_start);
8630 for (i = n_basic_blocks - 1; i >= 0; i--)
8632 insn = BLOCK_HEAD (i);
8633 if (GET_CODE (insn) == CODE_LABEL)
8637 REG_SET_TO_HARD_REG_SET (live,
8638 BASIC_BLOCK (i)->global_live_at_start);
8639 compute_use_by_pseudos (&live,
8640 BASIC_BLOCK (i)->global_live_at_start);
8641 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8642 IOR_HARD_REG_SET (ever_live_at_start, live);
8646 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8647 last_label_ruid = reload_combine_ruid = 0;
8648 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8650 reg_state[r].store_ruid = reload_combine_ruid;
8652 reg_state[r].use_index = -1;
8654 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8657 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8661 /* We cannot do our optimization across labels. Invalidating all the use
8662 information we have would be costly, so we just note where the label
8663 is and then later disable any optimization that would cross it. */
8664 if (GET_CODE (insn) == CODE_LABEL)
8665 last_label_ruid = reload_combine_ruid;
8666 else if (GET_CODE (insn) == BARRIER)
8667 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8668 if (! fixed_regs[r])
8669 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8671 if (! INSN_P (insn))
8674 reload_combine_ruid++;
8676 /* Look for (set (REGX) (CONST_INT))
8677 (set (REGX) (PLUS (REGX) (REGY)))
8679 ... (MEM (REGX)) ...
8681 (set (REGZ) (CONST_INT))
8683 ... (MEM (PLUS (REGZ) (REGY)))... .
8685 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8686 and that we know all uses of REGX before it dies. */
8687 set = single_set (insn);
8689 && GET_CODE (SET_DEST (set)) == REG
8690 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8691 GET_MODE (SET_DEST (set)))
8693 && GET_CODE (SET_SRC (set)) == PLUS
8694 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8695 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8696 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8698 rtx reg = SET_DEST (set);
8699 rtx plus = SET_SRC (set);
8700 rtx base = XEXP (plus, 1);
8701 rtx prev = prev_nonnote_insn (insn);
8702 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8703 unsigned int regno = REGNO (reg);
8704 rtx const_reg = NULL_RTX;
8705 rtx reg_sum = NULL_RTX;
8707 /* Now, we need an index register.
8708 We'll set index_reg to this index register, const_reg to the
8709 register that is to be loaded with the constant
8710 (denoted as REGZ in the substitution illustration above),
8711 and reg_sum to the register-register that we want to use to
8712 substitute uses of REG (typically in MEMs) with.
8713 First check REG and BASE for being index registers;
8714 we can use them even if they are not dead. */
8715 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8716 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8724 /* Otherwise, look for a free index register. Since we have
8725 checked above that neiter REG nor BASE are index registers,
8726 if we find anything at all, it will be different from these
8728 for (i = first_index_reg; i <= last_index_reg; i++)
8730 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8732 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8733 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8734 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8736 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8738 const_reg = index_reg;
8739 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8745 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8746 (REGY), i.e. BASE, is not clobbered before the last use we'll
8749 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8750 && rtx_equal_p (SET_DEST (prev_set), reg)
8751 && reg_state[regno].use_index >= 0
8752 && (reg_state[REGNO (base)].store_ruid
8753 <= reg_state[regno].use_ruid)
8758 /* Change destination register and, if necessary, the
8759 constant value in PREV, the constant loading instruction. */
8760 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8761 if (reg_state[regno].offset != const0_rtx)
8762 validate_change (prev,
8763 &SET_SRC (prev_set),
8764 GEN_INT (INTVAL (SET_SRC (prev_set))
8765 + INTVAL (reg_state[regno].offset)),
8768 /* Now for every use of REG that we have recorded, replace REG
8770 for (i = reg_state[regno].use_index;
8771 i < RELOAD_COMBINE_MAX_USES; i++)
8772 validate_change (reg_state[regno].reg_use[i].insn,
8773 reg_state[regno].reg_use[i].usep,
8776 if (apply_change_group ())
8780 /* Delete the reg-reg addition. */
8783 if (reg_state[regno].offset != const0_rtx)
8784 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8786 for (np = ®_NOTES (prev); *np;)
8788 if (REG_NOTE_KIND (*np) == REG_EQUAL
8789 || REG_NOTE_KIND (*np) == REG_EQUIV)
8790 *np = XEXP (*np, 1);
8792 np = &XEXP (*np, 1);
8795 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8796 reg_state[REGNO (const_reg)].store_ruid
8797 = reload_combine_ruid;
8803 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8805 if (GET_CODE (insn) == CALL_INSN)
8809 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8810 if (call_used_regs[r])
8812 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8813 reg_state[r].store_ruid = reload_combine_ruid;
8816 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8817 link = XEXP (link, 1))
8819 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8820 if (GET_CODE (usage_rtx) == REG)
8823 unsigned int start_reg = REGNO (usage_rtx);
8824 unsigned int num_regs =
8825 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8826 unsigned int end_reg = start_reg + num_regs - 1;
8827 for (i = start_reg; i <= end_reg; i++)
8828 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8830 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8831 reg_state[i].store_ruid = reload_combine_ruid;
8834 reg_state[i].use_index = -1;
8839 else if (GET_CODE (insn) == JUMP_INSN
8840 && GET_CODE (PATTERN (insn)) != RETURN)
8842 /* Non-spill registers might be used at the call destination in
8843 some unknown fashion, so we have to mark the unknown use. */
8846 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8847 && JUMP_LABEL (insn))
8848 live = &LABEL_LIVE (JUMP_LABEL (insn));
8850 live = &ever_live_at_start;
8852 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8853 if (TEST_HARD_REG_BIT (*live, i))
8854 reg_state[i].use_index = -1;
8857 reload_combine_note_use (&PATTERN (insn), insn);
8858 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8860 if (REG_NOTE_KIND (note) == REG_INC
8861 && GET_CODE (XEXP (note, 0)) == REG)
8863 int regno = REGNO (XEXP (note, 0));
8865 reg_state[regno].store_ruid = reload_combine_ruid;
8866 reg_state[regno].use_index = -1;
8874 /* Check if DST is a register or a subreg of a register; if it is,
8875 update reg_state[regno].store_ruid and reg_state[regno].use_index
8876 accordingly. Called via note_stores from reload_combine. */
8879 reload_combine_note_store (dst, set, data)
8881 void *data ATTRIBUTE_UNUSED;
8885 enum machine_mode mode = GET_MODE (dst);
8887 if (GET_CODE (dst) == SUBREG)
8889 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8890 GET_MODE (SUBREG_REG (dst)),
8893 dst = SUBREG_REG (dst);
8895 if (GET_CODE (dst) != REG)
8897 regno += REGNO (dst);
8899 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8900 careful with registers / register parts that are not full words.
8902 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8903 if (GET_CODE (set) != SET
8904 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8905 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8906 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8908 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8910 reg_state[i].use_index = -1;
8911 reg_state[i].store_ruid = reload_combine_ruid;
8916 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8918 reg_state[i].store_ruid = reload_combine_ruid;
8919 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8924 /* XP points to a piece of rtl that has to be checked for any uses of
8926 *XP is the pattern of INSN, or a part of it.
8927 Called from reload_combine, and recursively by itself. */
8929 reload_combine_note_use (xp, insn)
8933 enum rtx_code code = x->code;
8936 rtx offset = const0_rtx; /* For the REG case below. */
8941 if (GET_CODE (SET_DEST (x)) == REG)
8943 reload_combine_note_use (&SET_SRC (x), insn);
8949 /* If this is the USE of a return value, we can't change it. */
8950 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8952 /* Mark the return register as used in an unknown fashion. */
8953 rtx reg = XEXP (x, 0);
8954 int regno = REGNO (reg);
8955 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8957 while (--nregs >= 0)
8958 reg_state[regno + nregs].use_index = -1;
8964 if (GET_CODE (SET_DEST (x)) == REG)
8966 /* No spurious CLOBBERs of pseudo registers may remain. */
8967 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
8974 /* We are interested in (plus (reg) (const_int)) . */
8975 if (GET_CODE (XEXP (x, 0)) != REG
8976 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8978 offset = XEXP (x, 1);
8983 int regno = REGNO (x);
8987 /* No spurious USEs of pseudo registers may remain. */
8988 if (regno >= FIRST_PSEUDO_REGISTER)
8991 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8993 /* We can't substitute into multi-hard-reg uses. */
8996 while (--nregs >= 0)
8997 reg_state[regno + nregs].use_index = -1;
9001 /* If this register is already used in some unknown fashion, we
9003 If we decrement the index from zero to -1, we can't store more
9004 uses, so this register becomes used in an unknown fashion. */
9005 use_index = --reg_state[regno].use_index;
9009 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9011 /* We have found another use for a register that is already
9012 used later. Check if the offsets match; if not, mark the
9013 register as used in an unknown fashion. */
9014 if (! rtx_equal_p (offset, reg_state[regno].offset))
9016 reg_state[regno].use_index = -1;
9022 /* This is the first use of this register we have seen since we
9023 marked it as dead. */
9024 reg_state[regno].offset = offset;
9025 reg_state[regno].use_ruid = reload_combine_ruid;
9027 reg_state[regno].reg_use[use_index].insn = insn;
9028 reg_state[regno].reg_use[use_index].usep = xp;
9036 /* Recursively process the components of X. */
9037 fmt = GET_RTX_FORMAT (code);
9038 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9041 reload_combine_note_use (&XEXP (x, i), insn);
9042 else if (fmt[i] == 'E')
9044 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9045 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9050 /* See if we can reduce the cost of a constant by replacing a move
9051 with an add. We track situations in which a register is set to a
9052 constant or to a register plus a constant. */
9053 /* We cannot do our optimization across labels. Invalidating all the
9054 information about register contents we have would be costly, so we
9055 use move2add_last_label_luid to note where the label is and then
9056 later disable any optimization that would cross it.
9057 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9058 reg_set_luid[n] is greater than last_label_luid[n] . */
9059 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9061 /* If reg_base_reg[n] is negative, register n has been set to
9062 reg_offset[n] in mode reg_mode[n] .
9063 If reg_base_reg[n] is non-negative, register n has been set to the
9064 sum of reg_offset[n] and the value of register reg_base_reg[n]
9065 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9066 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9067 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9068 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9070 /* move2add_luid is linearily increased while scanning the instructions
9071 from first to last. It is used to set reg_set_luid in
9072 reload_cse_move2add and move2add_note_store. */
9073 static int move2add_luid;
9075 /* move2add_last_label_luid is set whenever a label is found. Labels
9076 invalidate all previously collected reg_offset data. */
9077 static int move2add_last_label_luid;
9079 /* Generate a CONST_INT and force it in the range of MODE. */
9081 static HOST_WIDE_INT
9082 sext_for_mode (mode, value)
9083 enum machine_mode mode;
9084 HOST_WIDE_INT value;
9086 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9087 int width = GET_MODE_BITSIZE (mode);
9089 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9091 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9092 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9093 cval |= (HOST_WIDE_INT) -1 << width;
9098 /* ??? We don't know how zero / sign extension is handled, hence we
9099 can't go from a narrower to a wider mode. */
9100 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9101 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9102 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9103 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9104 GET_MODE_BITSIZE (INMODE))))
9107 reload_cse_move2add (first)
9113 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9114 reg_set_luid[i] = 0;
9116 move2add_last_label_luid = 0;
9118 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9122 if (GET_CODE (insn) == CODE_LABEL)
9124 move2add_last_label_luid = move2add_luid;
9125 /* We're going to increment move2add_luid twice after a
9126 label, so that we can use move2add_last_label_luid + 1 as
9127 the luid for constants. */
9131 if (! INSN_P (insn))
9133 pat = PATTERN (insn);
9134 /* For simplicity, we only perform this optimization on
9135 straightforward SETs. */
9136 if (GET_CODE (pat) == SET
9137 && GET_CODE (SET_DEST (pat)) == REG)
9139 rtx reg = SET_DEST (pat);
9140 int regno = REGNO (reg);
9141 rtx src = SET_SRC (pat);
9143 /* Check if we have valid information on the contents of this
9144 register in the mode of REG. */
9145 if (reg_set_luid[regno] > move2add_last_label_luid
9146 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9148 /* Try to transform (set (REGX) (CONST_INT A))
9150 (set (REGX) (CONST_INT B))
9152 (set (REGX) (CONST_INT A))
9154 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9156 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9159 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9161 - reg_offset[regno]));
9162 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9163 use (set (reg) (reg)) instead.
9164 We don't delete this insn, nor do we convert it into a
9165 note, to avoid losing register notes or the return
9166 value flag. jump2 already knowns how to get rid of
9168 if (new_src == const0_rtx)
9169 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9170 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9171 && have_add2_insn (reg, new_src))
9172 success = validate_change (insn, &PATTERN (insn),
9173 gen_add2_insn (reg, new_src), 0);
9174 reg_set_luid[regno] = move2add_luid;
9175 reg_mode[regno] = GET_MODE (reg);
9176 reg_offset[regno] = INTVAL (src);
9180 /* Try to transform (set (REGX) (REGY))
9181 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9184 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9187 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9189 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9190 else if (GET_CODE (src) == REG
9191 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9192 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9193 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9194 reg_mode[REGNO (src)]))
9196 rtx next = next_nonnote_insn (insn);
9199 set = single_set (next);
9201 && SET_DEST (set) == reg
9202 && GET_CODE (SET_SRC (set)) == PLUS
9203 && XEXP (SET_SRC (set), 0) == reg
9204 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9206 rtx src3 = XEXP (SET_SRC (set), 1);
9207 HOST_WIDE_INT added_offset = INTVAL (src3);
9208 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9209 HOST_WIDE_INT regno_offset = reg_offset[regno];
9210 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9216 if (new_src == const0_rtx)
9217 /* See above why we create (set (reg) (reg)) here. */
9219 = validate_change (next, &SET_SRC (set), reg, 0);
9220 else if ((rtx_cost (new_src, PLUS)
9221 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9222 && have_add2_insn (reg, new_src))
9224 = validate_change (next, &PATTERN (next),
9225 gen_add2_insn (reg, new_src), 0);
9229 reg_mode[regno] = GET_MODE (reg);
9230 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9239 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9241 if (REG_NOTE_KIND (note) == REG_INC
9242 && GET_CODE (XEXP (note, 0)) == REG)
9244 /* Reset the information about this register. */
9245 int regno = REGNO (XEXP (note, 0));
9246 if (regno < FIRST_PSEUDO_REGISTER)
9247 reg_set_luid[regno] = 0;
9250 note_stores (PATTERN (insn), move2add_note_store, NULL);
9251 /* If this is a CALL_INSN, all call used registers are stored with
9253 if (GET_CODE (insn) == CALL_INSN)
9255 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9257 if (call_used_regs[i])
9258 /* Reset the information about this register. */
9259 reg_set_luid[i] = 0;
9265 /* SET is a SET or CLOBBER that sets DST.
9266 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9267 Called from reload_cse_move2add via note_stores. */
9270 move2add_note_store (dst, set, data)
9272 void *data ATTRIBUTE_UNUSED;
9274 unsigned int regno = 0;
9276 enum machine_mode mode = GET_MODE (dst);
9278 if (GET_CODE (dst) == SUBREG)
9280 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9281 GET_MODE (SUBREG_REG (dst)),
9284 dst = SUBREG_REG (dst);
9287 /* Some targets do argument pushes without adding REG_INC notes. */
9289 if (GET_CODE (dst) == MEM)
9291 dst = XEXP (dst, 0);
9292 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9293 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9294 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9297 if (GET_CODE (dst) != REG)
9300 regno += REGNO (dst);
9302 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9303 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9304 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9305 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9307 rtx src = SET_SRC (set);
9309 HOST_WIDE_INT offset;
9311 /* This may be different from mode, if SET_DEST (set) is a
9313 enum machine_mode dst_mode = GET_MODE (dst);
9315 switch (GET_CODE (src))
9318 if (GET_CODE (XEXP (src, 0)) == REG)
9320 base_reg = XEXP (src, 0);
9322 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9323 offset = INTVAL (XEXP (src, 1));
9324 else if (GET_CODE (XEXP (src, 1)) == REG
9325 && (reg_set_luid[REGNO (XEXP (src, 1))]
9326 > move2add_last_label_luid)
9327 && (MODES_OK_FOR_MOVE2ADD
9328 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9330 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9331 offset = reg_offset[REGNO (XEXP (src, 1))];
9332 /* Maybe the first register is known to be a
9334 else if (reg_set_luid[REGNO (base_reg)]
9335 > move2add_last_label_luid
9336 && (MODES_OK_FOR_MOVE2ADD
9337 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9338 && reg_base_reg[REGNO (base_reg)] < 0)
9340 offset = reg_offset[REGNO (base_reg)];
9341 base_reg = XEXP (src, 1);
9360 /* Start tracking the register as a constant. */
9361 reg_base_reg[regno] = -1;
9362 reg_offset[regno] = INTVAL (SET_SRC (set));
9363 /* We assign the same luid to all registers set to constants. */
9364 reg_set_luid[regno] = move2add_last_label_luid + 1;
9365 reg_mode[regno] = mode;
9370 /* Invalidate the contents of the register. */
9371 reg_set_luid[regno] = 0;
9375 base_regno = REGNO (base_reg);
9376 /* If information about the base register is not valid, set it
9377 up as a new base register, pretending its value is known
9378 starting from the current insn. */
9379 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9381 reg_base_reg[base_regno] = base_regno;
9382 reg_offset[base_regno] = 0;
9383 reg_set_luid[base_regno] = move2add_luid;
9384 reg_mode[base_regno] = mode;
9386 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9387 reg_mode[base_regno]))
9390 reg_mode[regno] = mode;
9392 /* Copy base information from our base register. */
9393 reg_set_luid[regno] = reg_set_luid[base_regno];
9394 reg_base_reg[regno] = reg_base_reg[base_regno];
9396 /* Compute the sum of the offsets or constants. */
9397 reg_offset[regno] = sext_for_mode (dst_mode,
9399 + reg_offset[base_regno]);
9403 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9405 for (i = regno; i < endregno; i++)
9406 /* Reset the information about this register. */
9407 reg_set_luid[i] = 0;
9413 add_auto_inc_notes (insn, x)
9417 enum rtx_code code = GET_CODE (x);
9421 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9424 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9428 /* Scan all the operand sub-expressions. */
9429 fmt = GET_RTX_FORMAT (code);
9430 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9433 add_auto_inc_notes (insn, XEXP (x, i));
9434 else if (fmt[i] == 'E')
9435 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9436 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9441 /* Copy EH notes from an insn to its reloads. */
9443 copy_eh_notes (insn, x)
9447 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9450 for (; x != 0; x = NEXT_INSN (x))
9452 if (may_trap_p (PATTERN (x)))
9454 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9460 /* This is used by reload pass, that does emit some instructions after
9461 abnormal calls moving basic block end, but in fact it wants to emit
9462 them on the edge. Looks for abnormal call edges, find backward the
9463 proper call and fix the damage.
9465 Similar handle instructions throwing exceptions internally. */
9467 fixup_abnormal_edges ()
9470 bool inserted = false;
9472 for (i = 0; i < n_basic_blocks; i++)
9474 basic_block bb = BASIC_BLOCK (i);
9477 /* Look for cases we are interested in - an calls or instructions causing
9479 for (e = bb->succ; e; e = e->succ_next)
9481 if (e->flags & EDGE_ABNORMAL_CALL)
9483 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9484 == (EDGE_ABNORMAL | EDGE_EH))
9487 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9489 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9491 for (e = bb->succ; e; e = e->succ_next)
9492 if (e->flags & EDGE_FALLTHRU)
9494 /* Get past the new insns generated. Allow notes, as the insns may
9495 be already deleted. */
9496 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9497 && !can_throw_internal (insn)
9498 && insn != bb->head)
9499 insn = PREV_INSN (insn);
9500 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9504 insn = NEXT_INSN (insn);
9505 while (insn && insn != stop)
9507 next = NEXT_INSN (insn);
9510 insert_insn_on_edge (PATTERN (insn), e);
9518 commit_edge_insertions ();
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