1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
82 #define LOCAL_REGNO(REGNO) 0
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static char *reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is a memory location to which pseudo reg N is equivalent,
104 prior to any register elimination (such as frame pointer to stack
105 pointer). Depending on whether or not it is a valid address, this value
106 is transferred to either reg_equiv_address or reg_equiv_mem. */
107 rtx *reg_equiv_memory_loc;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Number of spill-regs so far; number of valid elements of spill_regs. */
148 /* In parallel with spill_regs, contains REG rtx's for those regs.
149 Holds the last rtx used for any given reg, or 0 if it has never
150 been used for spilling yet. This rtx is reused, provided it has
152 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
154 /* In parallel with spill_regs, contains nonzero for a spill reg
155 that was stored after the last time it was used.
156 The precise value is the insn generated to do the store. */
157 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
159 /* This is the register that was stored with spill_reg_store. This is a
160 copy of reload_out / reload_out_reg when the value was stored; if
161 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
162 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
164 /* This table is the inverse mapping of spill_regs:
165 indexed by hard reg number,
166 it contains the position of that reg in spill_regs,
167 or -1 for something that is not in spill_regs.
169 ?!? This is no longer accurate. */
170 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
172 /* This reg set indicates registers that can't be used as spill registers for
173 the currently processed insn. These are the hard registers which are live
174 during the insn, but not allocated to pseudos, as well as fixed
176 static HARD_REG_SET bad_spill_regs;
178 /* These are the hard registers that can't be used as spill register for any
179 insn. This includes registers used for user variables and registers that
180 we can't eliminate. A register that appears in this set also can't be used
181 to retry register allocation. */
182 static HARD_REG_SET bad_spill_regs_global;
184 /* Describes order of use of registers for reloading
185 of spilled pseudo-registers. `n_spills' is the number of
186 elements that are actually valid; new ones are added at the end.
188 Both spill_regs and spill_reg_order are used on two occasions:
189 once during find_reload_regs, where they keep track of the spill registers
190 for a single insn, but also during reload_as_needed where they show all
191 the registers ever used by reload. For the latter case, the information
192 is calculated during finish_spills. */
193 static short spill_regs[FIRST_PSEUDO_REGISTER];
195 /* This vector of reg sets indicates, for each pseudo, which hard registers
196 may not be used for retrying global allocation because the register was
197 formerly spilled from one of them. If we allowed reallocating a pseudo to
198 a register that it was already allocated to, reload might not
200 static HARD_REG_SET *pseudo_previous_regs;
202 /* This vector of reg sets indicates, for each pseudo, which hard
203 registers may not be used for retrying global allocation because they
204 are used as spill registers during one of the insns in which the
206 static HARD_REG_SET *pseudo_forbidden_regs;
208 /* All hard regs that have been used as spill registers for any insn are
209 marked in this set. */
210 static HARD_REG_SET used_spill_regs;
212 /* Index of last register assigned as a spill register. We allocate in
213 a round-robin fashion. */
214 static int last_spill_reg;
216 /* Nonzero if indirect addressing is supported on the machine; this means
217 that spilling (REG n) does not require reloading it into a register in
218 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
219 value indicates the level of indirect addressing supported, e.g., two
220 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
222 static char spill_indirect_levels;
224 /* Nonzero if indirect addressing is supported when the innermost MEM is
225 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
226 which these are valid is the same as spill_indirect_levels, above. */
227 char indirect_symref_ok;
229 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
233 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
235 /* Width allocated so far for that stack slot. */
236 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
238 /* Record which pseudos needed to be spilled. */
239 static regset_head spilled_pseudos;
241 /* Used for communication between order_regs_for_reload and count_pseudo.
242 Used to avoid counting one pseudo twice. */
243 static regset_head pseudos_counted;
245 /* First uid used by insns created by reload in this function.
246 Used in find_equiv_reg. */
247 int reload_first_uid;
249 /* Flag set by local-alloc or global-alloc if anything is live in
250 a call-clobbered reg across calls. */
251 int caller_save_needed;
253 /* Set to 1 while reload_as_needed is operating.
254 Required by some machines to handle any generated moves differently. */
255 int reload_in_progress = 0;
257 /* These arrays record the insn_code of insns that may be needed to
258 perform input and output reloads of special objects. They provide a
259 place to pass a scratch register. */
260 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
261 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
263 /* This obstack is used for allocation of rtl during register elimination.
264 The allocated storage can be freed once find_reloads has processed the
266 struct obstack reload_obstack;
268 /* Points to the beginning of the reload_obstack. All insn_chain structures
269 are allocated first. */
270 char *reload_startobj;
272 /* The point after all insn_chain structures. Used to quickly deallocate
273 memory allocated in copy_reloads during calculate_needs_all_insns. */
274 char *reload_firstobj;
276 /* This points before all local rtl generated by register elimination.
277 Used to quickly free all memory after processing one insn. */
278 static char *reload_insn_firstobj;
280 /* List of insn_chain instructions, one for every insn that reload needs to
282 struct insn_chain *reload_insn_chain;
284 /* List of all insns needing reloads. */
285 static struct insn_chain *insns_need_reload;
287 /* This structure is used to record information about register eliminations.
288 Each array entry describes one possible way of eliminating a register
289 in favor of another. If there is more than one way of eliminating a
290 particular register, the most preferred should be specified first. */
294 int from; /* Register number to be eliminated. */
295 int to; /* Register number used as replacement. */
296 int initial_offset; /* Initial difference between values. */
297 int can_eliminate; /* Nonzero if this elimination can be done. */
298 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
299 insns made by reload. */
300 int offset; /* Current offset between the two regs. */
301 int previous_offset; /* Offset at end of previous insn. */
302 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
303 rtx from_rtx; /* REG rtx for the register to be eliminated.
304 We cannot simply compare the number since
305 we might then spuriously replace a hard
306 register corresponding to a pseudo
307 assigned to the reg to be eliminated. */
308 rtx to_rtx; /* REG rtx for the replacement. */
311 static struct elim_table *reg_eliminate = 0;
313 /* This is an intermediate structure to initialize the table. It has
314 exactly the members provided by ELIMINABLE_REGS. */
315 static const struct elim_table_1
319 } reg_eliminate_1[] =
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
331 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If nonzero, we use a new copy of each
335 replacement result in any insns encountered. */
336 int num_not_at_initial_offset;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable;
340 /* And the number of registers that are equivalent to a constant that
341 can be eliminated to frame_pointer / arg_pointer + constant. */
342 static int num_eliminable_invariants;
344 /* For each label, we record the offset of each elimination. If we reach
345 a label by more than one path and an offset differs, we cannot do the
346 elimination. This information is indexed by the difference of the
347 number of the label and the first label number. We can't offset the
348 pointer itself as this can cause problems on machines with segmented
349 memory. The first table is an array of flags that records whether we
350 have yet encountered a label and the second table is an array of arrays,
351 one entry in the latter array for each elimination. */
353 static int first_label_num;
354 static char *offsets_known_at;
355 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
357 /* Number of labels in the current function. */
359 static int num_labels;
361 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
362 static void maybe_fix_stack_asms (void);
363 static void copy_reloads (struct insn_chain *);
364 static void calculate_needs_all_insns (int);
365 static int find_reg (struct insn_chain *, int);
366 static void find_reload_regs (struct insn_chain *);
367 static void select_reload_regs (void);
368 static void delete_caller_save_insns (void);
370 static void spill_failure (rtx, enum reg_class);
371 static void count_spilled_pseudo (int, int, int);
372 static void delete_dead_insn (rtx);
373 static void alter_reg (int, int);
374 static void set_label_offsets (rtx, rtx, int);
375 static void check_eliminable_occurrences (rtx);
376 static void elimination_effects (rtx, enum machine_mode);
377 static int eliminate_regs_in_insn (rtx, int);
378 static void update_eliminable_offsets (void);
379 static void mark_not_eliminable (rtx, rtx, void *);
380 static void set_initial_elim_offsets (void);
381 static void verify_initial_elim_offsets (void);
382 static void set_initial_label_offsets (void);
383 static void set_offsets_for_label (rtx);
384 static void init_elim_table (void);
385 static void update_eliminables (HARD_REG_SET *);
386 static void spill_hard_reg (unsigned int, int);
387 static int finish_spills (int);
388 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
389 static void scan_paradoxical_subregs (rtx);
390 static void count_pseudo (int);
391 static void order_regs_for_reload (struct insn_chain *);
392 static void reload_as_needed (int);
393 static void forget_old_reloads_1 (rtx, rtx, void *);
394 static int reload_reg_class_lower (const void *, const void *);
395 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
397 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
399 static int reload_reg_free_p (unsigned int, int, enum reload_type);
400 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
402 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
404 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
405 static int allocate_reload_reg (struct insn_chain *, int, int);
406 static int conflicts_with_override (rtx);
407 static void failed_reload (rtx, int);
408 static int set_reload_reg (int, int);
409 static void choose_reload_regs_init (struct insn_chain *, rtx *);
410 static void choose_reload_regs (struct insn_chain *);
411 static void merge_assigned_reloads (rtx);
412 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
414 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
416 static void do_input_reload (struct insn_chain *, struct reload *, int);
417 static void do_output_reload (struct insn_chain *, struct reload *, int);
418 static void emit_reload_insns (struct insn_chain *);
419 static void delete_output_reload (rtx, int, int);
420 static void delete_address_reloads (rtx, rtx);
421 static void delete_address_reloads_1 (rtx, rtx, rtx);
422 static rtx inc_for_reload (rtx, rtx, rtx, int);
424 static void add_auto_inc_notes (rtx, rtx);
426 static void copy_eh_notes (rtx, rtx);
428 /* Initialize the reload pass once per compilation. */
435 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
436 Set spill_indirect_levels to the number of levels such addressing is
437 permitted, zero if it is not permitted at all. */
440 = gen_rtx_MEM (Pmode,
443 LAST_VIRTUAL_REGISTER + 1),
445 spill_indirect_levels = 0;
447 while (memory_address_p (QImode, tem))
449 spill_indirect_levels++;
450 tem = gen_rtx_MEM (Pmode, tem);
453 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
455 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
456 indirect_symref_ok = memory_address_p (QImode, tem);
458 /* See if reg+reg is a valid (and offsettable) address. */
460 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
462 tem = gen_rtx_PLUS (Pmode,
463 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
464 gen_rtx_REG (Pmode, i));
466 /* This way, we make sure that reg+reg is an offsettable address. */
467 tem = plus_constant (tem, 4);
469 if (memory_address_p (QImode, tem))
471 double_reg_address_ok = 1;
476 /* Initialize obstack for our rtl allocation. */
477 gcc_obstack_init (&reload_obstack);
478 reload_startobj = obstack_alloc (&reload_obstack, 0);
480 INIT_REG_SET (&spilled_pseudos);
481 INIT_REG_SET (&pseudos_counted);
484 /* List of insn chains that are currently unused. */
485 static struct insn_chain *unused_insn_chains = 0;
487 /* Allocate an empty insn_chain structure. */
489 new_insn_chain (void)
491 struct insn_chain *c;
493 if (unused_insn_chains == 0)
495 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
496 INIT_REG_SET (&c->live_throughout);
497 INIT_REG_SET (&c->dead_or_set);
501 c = unused_insn_chains;
502 unused_insn_chains = c->next;
504 c->is_caller_save_insn = 0;
505 c->need_operand_change = 0;
511 /* Small utility function to set all regs in hard reg set TO which are
512 allocated to pseudos in regset FROM. */
515 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
519 EXECUTE_IF_SET_IN_REG_SET
520 (from, FIRST_PSEUDO_REGISTER, regno,
522 int r = reg_renumber[regno];
527 /* reload_combine uses the information from
528 BASIC_BLOCK->global_live_at_start, which might still
529 contain registers that have not actually been allocated
530 since they have an equivalence. */
531 if (! reload_completed)
536 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
538 SET_HARD_REG_BIT (*to, r + nregs);
543 /* Replace all pseudos found in LOC with their corresponding
547 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
560 unsigned int regno = REGNO (x);
562 if (regno < FIRST_PSEUDO_REGISTER)
565 x = eliminate_regs (x, mem_mode, usage);
569 replace_pseudos_in (loc, mem_mode, usage);
573 if (reg_equiv_constant[regno])
574 *loc = reg_equiv_constant[regno];
575 else if (reg_equiv_mem[regno])
576 *loc = reg_equiv_mem[regno];
577 else if (reg_equiv_address[regno])
578 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
579 else if (GET_CODE (regno_reg_rtx[regno]) != REG
580 || REGNO (regno_reg_rtx[regno]) != regno)
581 *loc = regno_reg_rtx[regno];
587 else if (code == MEM)
589 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
593 /* Process each of our operands recursively. */
594 fmt = GET_RTX_FORMAT (code);
595 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
597 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
598 else if (*fmt == 'E')
599 for (j = 0; j < XVECLEN (x, i); j++)
600 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
604 /* Global variables used by reload and its subroutines. */
606 /* Set during calculate_needs if an insn needs register elimination. */
607 static int something_needs_elimination;
608 /* Set during calculate_needs if an insn needs an operand changed. */
609 int something_needs_operands_changed;
611 /* Nonzero means we couldn't get enough spill regs. */
614 /* Main entry point for the reload pass.
616 FIRST is the first insn of the function being compiled.
618 GLOBAL nonzero means we were called from global_alloc
619 and should attempt to reallocate any pseudoregs that we
620 displace from hard regs we will use for reloads.
621 If GLOBAL is zero, we do not have enough information to do that,
622 so any pseudo reg that is spilled must go to the stack.
624 Return value is nonzero if reload failed
625 and we must not do any more for this function. */
628 reload (rtx first, int global)
632 struct elim_table *ep;
635 /* Make sure even insns with volatile mem refs are recognizable. */
640 reload_firstobj = obstack_alloc (&reload_obstack, 0);
642 /* Make sure that the last insn in the chain
643 is not something that needs reloading. */
644 emit_note (NOTE_INSN_DELETED);
646 /* Enable find_equiv_reg to distinguish insns made by reload. */
647 reload_first_uid = get_max_uid ();
649 #ifdef SECONDARY_MEMORY_NEEDED
650 /* Initialize the secondary memory table. */
651 clear_secondary_mem ();
654 /* We don't have a stack slot for any spill reg yet. */
655 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
656 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
658 /* Initialize the save area information for caller-save, in case some
662 /* Compute which hard registers are now in use
663 as homes for pseudo registers.
664 This is done here rather than (eg) in global_alloc
665 because this point is reached even if not optimizing. */
666 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
669 /* A function that receives a nonlocal goto must save all call-saved
671 if (current_function_has_nonlocal_label)
672 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
673 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
674 regs_ever_live[i] = 1;
676 /* Find all the pseudo registers that didn't get hard regs
677 but do have known equivalent constants or memory slots.
678 These include parameters (known equivalent to parameter slots)
679 and cse'd or loop-moved constant memory addresses.
681 Record constant equivalents in reg_equiv_constant
682 so they will be substituted by find_reloads.
683 Record memory equivalents in reg_mem_equiv so they can
684 be substituted eventually by altering the REG-rtx's. */
686 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
687 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
688 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
689 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
690 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
691 reg_old_renumber = xcalloc (max_regno, sizeof (short));
692 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
693 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
694 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
696 CLEAR_HARD_REG_SET (bad_spill_regs_global);
698 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
699 Also find all paradoxical subregs and find largest such for each pseudo.
700 On machines with small register classes, record hard registers that
701 are used for user variables. These can never be used for spills.
702 Also look for a "constant" REG_SETJMP. This means that all
703 caller-saved registers must be marked live. */
705 num_eliminable_invariants = 0;
706 for (insn = first; insn; insn = NEXT_INSN (insn))
708 rtx set = single_set (insn);
710 /* We may introduce USEs that we want to remove at the end, so
711 we'll mark them with QImode. Make sure there are no
712 previously-marked insns left by say regmove. */
713 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
714 && GET_MODE (insn) != VOIDmode)
715 PUT_MODE (insn, VOIDmode);
717 if (GET_CODE (insn) == CALL_INSN
718 && find_reg_note (insn, REG_SETJMP, NULL))
719 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
720 if (! call_used_regs[i])
721 regs_ever_live[i] = 1;
723 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
725 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
727 #ifdef LEGITIMATE_PIC_OPERAND_P
728 && (! function_invariant_p (XEXP (note, 0))
730 /* A function invariant is often CONSTANT_P but may
731 include a register. We promise to only pass
732 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
733 || (CONSTANT_P (XEXP (note, 0))
734 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
738 rtx x = XEXP (note, 0);
739 i = REGNO (SET_DEST (set));
740 if (i > LAST_VIRTUAL_REGISTER)
742 /* It can happen that a REG_EQUIV note contains a MEM
743 that is not a legitimate memory operand. As later
744 stages of reload assume that all addresses found
745 in the reg_equiv_* arrays were originally legitimate,
746 we ignore such REG_EQUIV notes. */
747 if (memory_operand (x, VOIDmode))
749 /* Always unshare the equivalence, so we can
750 substitute into this insn without touching the
752 reg_equiv_memory_loc[i] = copy_rtx (x);
754 else if (function_invariant_p (x))
756 if (GET_CODE (x) == PLUS)
758 /* This is PLUS of frame pointer and a constant,
759 and might be shared. Unshare it. */
760 reg_equiv_constant[i] = copy_rtx (x);
761 num_eliminable_invariants++;
763 else if (x == frame_pointer_rtx
764 || x == arg_pointer_rtx)
766 reg_equiv_constant[i] = x;
767 num_eliminable_invariants++;
769 else if (LEGITIMATE_CONSTANT_P (x))
770 reg_equiv_constant[i] = x;
773 reg_equiv_memory_loc[i]
774 = force_const_mem (GET_MODE (SET_DEST (set)), x);
775 if (!reg_equiv_memory_loc[i])
782 /* If this register is being made equivalent to a MEM
783 and the MEM is not SET_SRC, the equivalencing insn
784 is one with the MEM as a SET_DEST and it occurs later.
785 So don't mark this insn now. */
786 if (GET_CODE (x) != MEM
787 || rtx_equal_p (SET_SRC (set), x))
789 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
794 /* If this insn is setting a MEM from a register equivalent to it,
795 this is the equivalencing insn. */
796 else if (set && GET_CODE (SET_DEST (set)) == MEM
797 && GET_CODE (SET_SRC (set)) == REG
798 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
799 && rtx_equal_p (SET_DEST (set),
800 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
801 reg_equiv_init[REGNO (SET_SRC (set))]
802 = gen_rtx_INSN_LIST (VOIDmode, insn,
803 reg_equiv_init[REGNO (SET_SRC (set))]);
806 scan_paradoxical_subregs (PATTERN (insn));
811 first_label_num = get_first_label_num ();
812 num_labels = max_label_num () - first_label_num;
814 /* Allocate the tables used to store offset information at labels. */
815 /* We used to use alloca here, but the size of what it would try to
816 allocate would occasionally cause it to exceed the stack limit and
817 cause a core dump. */
818 offsets_known_at = xmalloc (num_labels);
819 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
821 /* Alter each pseudo-reg rtx to contain its hard reg number.
822 Assign stack slots to the pseudos that lack hard regs or equivalents.
823 Do not touch virtual registers. */
825 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
828 /* If we have some registers we think can be eliminated, scan all insns to
829 see if there is an insn that sets one of these registers to something
830 other than itself plus a constant. If so, the register cannot be
831 eliminated. Doing this scan here eliminates an extra pass through the
832 main reload loop in the most common case where register elimination
834 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
835 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
836 || GET_CODE (insn) == CALL_INSN)
837 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
839 maybe_fix_stack_asms ();
841 insns_need_reload = 0;
842 something_needs_elimination = 0;
844 /* Initialize to -1, which means take the first spill register. */
847 /* Spill any hard regs that we know we can't eliminate. */
848 CLEAR_HARD_REG_SET (used_spill_regs);
849 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
850 if (! ep->can_eliminate)
851 spill_hard_reg (ep->from, 1);
853 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
854 if (frame_pointer_needed)
855 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
857 finish_spills (global);
859 /* From now on, we may need to generate moves differently. We may also
860 allow modifications of insns which cause them to not be recognized.
861 Any such modifications will be cleaned up during reload itself. */
862 reload_in_progress = 1;
864 /* This loop scans the entire function each go-round
865 and repeats until one repetition spills no additional hard regs. */
868 int something_changed;
871 HOST_WIDE_INT starting_frame_size;
873 /* Round size of stack frame to stack_alignment_needed. This must be done
874 here because the stack size may be a part of the offset computation
875 for register elimination, and there might have been new stack slots
876 created in the last iteration of this loop. */
877 if (cfun->stack_alignment_needed)
878 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
880 starting_frame_size = get_frame_size ();
882 set_initial_elim_offsets ();
883 set_initial_label_offsets ();
885 /* For each pseudo register that has an equivalent location defined,
886 try to eliminate any eliminable registers (such as the frame pointer)
887 assuming initial offsets for the replacement register, which
890 If the resulting location is directly addressable, substitute
891 the MEM we just got directly for the old REG.
893 If it is not addressable but is a constant or the sum of a hard reg
894 and constant, it is probably not addressable because the constant is
895 out of range, in that case record the address; we will generate
896 hairy code to compute the address in a register each time it is
897 needed. Similarly if it is a hard register, but one that is not
898 valid as an address register.
900 If the location is not addressable, but does not have one of the
901 above forms, assign a stack slot. We have to do this to avoid the
902 potential of producing lots of reloads if, e.g., a location involves
903 a pseudo that didn't get a hard register and has an equivalent memory
904 location that also involves a pseudo that didn't get a hard register.
906 Perhaps at some point we will improve reload_when_needed handling
907 so this problem goes away. But that's very hairy. */
909 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
910 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
912 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
914 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
916 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
917 else if (CONSTANT_P (XEXP (x, 0))
918 || (GET_CODE (XEXP (x, 0)) == REG
919 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
920 || (GET_CODE (XEXP (x, 0)) == PLUS
921 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
922 && (REGNO (XEXP (XEXP (x, 0), 0))
923 < FIRST_PSEUDO_REGISTER)
924 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
925 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
928 /* Make a new stack slot. Then indicate that something
929 changed so we go back and recompute offsets for
930 eliminable registers because the allocation of memory
931 below might change some offset. reg_equiv_{mem,address}
932 will be set up for this pseudo on the next pass around
934 reg_equiv_memory_loc[i] = 0;
935 reg_equiv_init[i] = 0;
940 if (caller_save_needed)
943 /* If we allocated another stack slot, redo elimination bookkeeping. */
944 if (starting_frame_size != get_frame_size ())
947 if (caller_save_needed)
949 save_call_clobbered_regs ();
950 /* That might have allocated new insn_chain structures. */
951 reload_firstobj = obstack_alloc (&reload_obstack, 0);
954 calculate_needs_all_insns (global);
956 CLEAR_REG_SET (&spilled_pseudos);
959 something_changed = 0;
961 /* If we allocated any new memory locations, make another pass
962 since it might have changed elimination offsets. */
963 if (starting_frame_size != get_frame_size ())
964 something_changed = 1;
967 HARD_REG_SET to_spill;
968 CLEAR_HARD_REG_SET (to_spill);
969 update_eliminables (&to_spill);
970 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
971 if (TEST_HARD_REG_BIT (to_spill, i))
973 spill_hard_reg (i, 1);
976 /* Regardless of the state of spills, if we previously had
977 a register that we thought we could eliminate, but now can
978 not eliminate, we must run another pass.
980 Consider pseudos which have an entry in reg_equiv_* which
981 reference an eliminable register. We must make another pass
982 to update reg_equiv_* so that we do not substitute in the
983 old value from when we thought the elimination could be
985 something_changed = 1;
989 select_reload_regs ();
993 if (insns_need_reload != 0 || did_spill)
994 something_changed |= finish_spills (global);
996 if (! something_changed)
999 if (caller_save_needed)
1000 delete_caller_save_insns ();
1002 obstack_free (&reload_obstack, reload_firstobj);
1005 /* If global-alloc was run, notify it of any register eliminations we have
1008 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1009 if (ep->can_eliminate)
1010 mark_elimination (ep->from, ep->to);
1012 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1013 If that insn didn't set the register (i.e., it copied the register to
1014 memory), just delete that insn instead of the equivalencing insn plus
1015 anything now dead. If we call delete_dead_insn on that insn, we may
1016 delete the insn that actually sets the register if the register dies
1017 there and that is incorrect. */
1019 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1021 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1024 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1026 rtx equiv_insn = XEXP (list, 0);
1028 /* If we already deleted the insn or if it may trap, we can't
1029 delete it. The latter case shouldn't happen, but can
1030 if an insn has a variable address, gets a REG_EH_REGION
1031 note added to it, and then gets converted into an load
1032 from a constant address. */
1033 if (GET_CODE (equiv_insn) == NOTE
1034 || can_throw_internal (equiv_insn))
1036 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1037 delete_dead_insn (equiv_insn);
1040 PUT_CODE (equiv_insn, NOTE);
1041 NOTE_SOURCE_FILE (equiv_insn) = 0;
1042 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1048 /* Use the reload registers where necessary
1049 by generating move instructions to move the must-be-register
1050 values into or out of the reload registers. */
1052 if (insns_need_reload != 0 || something_needs_elimination
1053 || something_needs_operands_changed)
1055 HOST_WIDE_INT old_frame_size = get_frame_size ();
1057 reload_as_needed (global);
1059 if (old_frame_size != get_frame_size ())
1063 verify_initial_elim_offsets ();
1066 /* If we were able to eliminate the frame pointer, show that it is no
1067 longer live at the start of any basic block. If it ls live by
1068 virtue of being in a pseudo, that pseudo will be marked live
1069 and hence the frame pointer will be known to be live via that
1072 if (! frame_pointer_needed)
1074 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1075 HARD_FRAME_POINTER_REGNUM);
1077 /* Come here (with failure set nonzero) if we can't get enough spill regs
1078 and we decide not to abort about it. */
1081 CLEAR_REG_SET (&spilled_pseudos);
1082 reload_in_progress = 0;
1084 /* Now eliminate all pseudo regs by modifying them into
1085 their equivalent memory references.
1086 The REG-rtx's for the pseudos are modified in place,
1087 so all insns that used to refer to them now refer to memory.
1089 For a reg that has a reg_equiv_address, all those insns
1090 were changed by reloading so that no insns refer to it any longer;
1091 but the DECL_RTL of a variable decl may refer to it,
1092 and if so this causes the debugging info to mention the variable. */
1094 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1098 if (reg_equiv_mem[i])
1099 addr = XEXP (reg_equiv_mem[i], 0);
1101 if (reg_equiv_address[i])
1102 addr = reg_equiv_address[i];
1106 if (reg_renumber[i] < 0)
1108 rtx reg = regno_reg_rtx[i];
1110 REG_USERVAR_P (reg) = 0;
1111 PUT_CODE (reg, MEM);
1112 XEXP (reg, 0) = addr;
1113 if (reg_equiv_memory_loc[i])
1114 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1117 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1118 = MEM_SCALAR_P (reg) = 0;
1119 MEM_ATTRS (reg) = 0;
1122 else if (reg_equiv_mem[i])
1123 XEXP (reg_equiv_mem[i], 0) = addr;
1127 /* We must set reload_completed now since the cleanup_subreg_operands call
1128 below will re-recognize each insn and reload may have generated insns
1129 which are only valid during and after reload. */
1130 reload_completed = 1;
1132 /* Make a pass over all the insns and delete all USEs which we inserted
1133 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1134 notes. Delete all CLOBBER insns, except those that refer to the return
1135 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1136 from misarranging variable-array code, and simplify (subreg (reg))
1137 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1138 are no longer useful or accurate. Strip and regenerate REG_INC notes
1139 that may have been moved around. */
1141 for (insn = first; insn; insn = NEXT_INSN (insn))
1146 if (GET_CODE (insn) == CALL_INSN)
1147 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1148 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1150 if ((GET_CODE (PATTERN (insn)) == USE
1151 /* We mark with QImode USEs introduced by reload itself. */
1152 && (GET_MODE (insn) == QImode
1153 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1154 || (GET_CODE (PATTERN (insn)) == CLOBBER
1155 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1156 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1157 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1158 && XEXP (XEXP (PATTERN (insn), 0), 0)
1159 != stack_pointer_rtx))
1160 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1161 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1167 /* Some CLOBBERs may survive until here and still reference unassigned
1168 pseudos with const equivalent, which may in turn cause ICE in later
1169 passes if the reference remains in place. */
1170 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1171 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1172 VOIDmode, PATTERN (insn));
1174 pnote = ®_NOTES (insn);
1177 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1178 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1179 || REG_NOTE_KIND (*pnote) == REG_INC
1180 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1181 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1182 *pnote = XEXP (*pnote, 1);
1184 pnote = &XEXP (*pnote, 1);
1188 add_auto_inc_notes (insn, PATTERN (insn));
1191 /* And simplify (subreg (reg)) if it appears as an operand. */
1192 cleanup_subreg_operands (insn);
1195 /* If we are doing stack checking, give a warning if this function's
1196 frame size is larger than we expect. */
1197 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1199 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1200 static int verbose_warned = 0;
1202 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1203 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1204 size += UNITS_PER_WORD;
1206 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1208 warning ("frame size too large for reliable stack checking");
1209 if (! verbose_warned)
1211 warning ("try reducing the number of local variables");
1217 /* Indicate that we no longer have known memory locations or constants. */
1218 if (reg_equiv_constant)
1219 free (reg_equiv_constant);
1220 reg_equiv_constant = 0;
1221 if (reg_equiv_memory_loc)
1222 free (reg_equiv_memory_loc);
1223 reg_equiv_memory_loc = 0;
1225 if (offsets_known_at)
1226 free (offsets_known_at);
1230 free (reg_equiv_mem);
1231 free (reg_equiv_init);
1232 free (reg_equiv_address);
1233 free (reg_max_ref_width);
1234 free (reg_old_renumber);
1235 free (pseudo_previous_regs);
1236 free (pseudo_forbidden_regs);
1238 CLEAR_HARD_REG_SET (used_spill_regs);
1239 for (i = 0; i < n_spills; i++)
1240 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1242 /* Free all the insn_chain structures at once. */
1243 obstack_free (&reload_obstack, reload_startobj);
1244 unused_insn_chains = 0;
1245 fixup_abnormal_edges ();
1247 /* Replacing pseudos with their memory equivalents might have
1248 created shared rtx. Subsequent passes would get confused
1249 by this, so unshare everything here. */
1250 unshare_all_rtl_again (first);
1255 /* Yet another special case. Unfortunately, reg-stack forces people to
1256 write incorrect clobbers in asm statements. These clobbers must not
1257 cause the register to appear in bad_spill_regs, otherwise we'll call
1258 fatal_insn later. We clear the corresponding regnos in the live
1259 register sets to avoid this.
1260 The whole thing is rather sick, I'm afraid. */
1263 maybe_fix_stack_asms (void)
1266 const char *constraints[MAX_RECOG_OPERANDS];
1267 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1268 struct insn_chain *chain;
1270 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1273 HARD_REG_SET clobbered, allowed;
1276 if (! INSN_P (chain->insn)
1277 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1279 pat = PATTERN (chain->insn);
1280 if (GET_CODE (pat) != PARALLEL)
1283 CLEAR_HARD_REG_SET (clobbered);
1284 CLEAR_HARD_REG_SET (allowed);
1286 /* First, make a mask of all stack regs that are clobbered. */
1287 for (i = 0; i < XVECLEN (pat, 0); i++)
1289 rtx t = XVECEXP (pat, 0, i);
1290 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1291 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1294 /* Get the operand values and constraints out of the insn. */
1295 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1296 constraints, operand_mode);
1298 /* For every operand, see what registers are allowed. */
1299 for (i = 0; i < noperands; i++)
1301 const char *p = constraints[i];
1302 /* For every alternative, we compute the class of registers allowed
1303 for reloading in CLS, and merge its contents into the reg set
1305 int cls = (int) NO_REGS;
1311 if (c == '\0' || c == ',' || c == '#')
1313 /* End of one alternative - mark the regs in the current
1314 class, and reset the class. */
1315 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1321 } while (c != '\0' && c != ',');
1329 case '=': case '+': case '*': case '%': case '?': case '!':
1330 case '0': case '1': case '2': case '3': case '4': case 'm':
1331 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1332 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1333 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1338 cls = (int) reg_class_subunion[cls]
1339 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1344 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1348 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1349 cls = (int) reg_class_subunion[cls]
1350 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1352 cls = (int) reg_class_subunion[cls]
1353 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1355 p += CONSTRAINT_LEN (c, p);
1358 /* Those of the registers which are clobbered, but allowed by the
1359 constraints, must be usable as reload registers. So clear them
1360 out of the life information. */
1361 AND_HARD_REG_SET (allowed, clobbered);
1362 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1363 if (TEST_HARD_REG_BIT (allowed, i))
1365 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1366 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1373 /* Copy the global variables n_reloads and rld into the corresponding elts
1376 copy_reloads (struct insn_chain *chain)
1378 chain->n_reloads = n_reloads;
1379 chain->rld = obstack_alloc (&reload_obstack,
1380 n_reloads * sizeof (struct reload));
1381 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1382 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1385 /* Walk the chain of insns, and determine for each whether it needs reloads
1386 and/or eliminations. Build the corresponding insns_need_reload list, and
1387 set something_needs_elimination as appropriate. */
1389 calculate_needs_all_insns (int global)
1391 struct insn_chain **pprev_reload = &insns_need_reload;
1392 struct insn_chain *chain, *next = 0;
1394 something_needs_elimination = 0;
1396 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1397 for (chain = reload_insn_chain; chain != 0; chain = next)
1399 rtx insn = chain->insn;
1403 /* Clear out the shortcuts. */
1404 chain->n_reloads = 0;
1405 chain->need_elim = 0;
1406 chain->need_reload = 0;
1407 chain->need_operand_change = 0;
1409 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1410 include REG_LABEL), we need to see what effects this has on the
1411 known offsets at labels. */
1413 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1414 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1415 set_label_offsets (insn, insn, 0);
1419 rtx old_body = PATTERN (insn);
1420 int old_code = INSN_CODE (insn);
1421 rtx old_notes = REG_NOTES (insn);
1422 int did_elimination = 0;
1423 int operands_changed = 0;
1424 rtx set = single_set (insn);
1426 /* Skip insns that only set an equivalence. */
1427 if (set && GET_CODE (SET_DEST (set)) == REG
1428 && reg_renumber[REGNO (SET_DEST (set))] < 0
1429 && reg_equiv_constant[REGNO (SET_DEST (set))])
1432 /* If needed, eliminate any eliminable registers. */
1433 if (num_eliminable || num_eliminable_invariants)
1434 did_elimination = eliminate_regs_in_insn (insn, 0);
1436 /* Analyze the instruction. */
1437 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1438 global, spill_reg_order);
1440 /* If a no-op set needs more than one reload, this is likely
1441 to be something that needs input address reloads. We
1442 can't get rid of this cleanly later, and it is of no use
1443 anyway, so discard it now.
1444 We only do this when expensive_optimizations is enabled,
1445 since this complements reload inheritance / output
1446 reload deletion, and it can make debugging harder. */
1447 if (flag_expensive_optimizations && n_reloads > 1)
1449 rtx set = single_set (insn);
1451 && SET_SRC (set) == SET_DEST (set)
1452 && GET_CODE (SET_SRC (set)) == REG
1453 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1456 /* Delete it from the reload chain. */
1458 chain->prev->next = next;
1460 reload_insn_chain = next;
1462 next->prev = chain->prev;
1463 chain->next = unused_insn_chains;
1464 unused_insn_chains = chain;
1469 update_eliminable_offsets ();
1471 /* Remember for later shortcuts which insns had any reloads or
1472 register eliminations. */
1473 chain->need_elim = did_elimination;
1474 chain->need_reload = n_reloads > 0;
1475 chain->need_operand_change = operands_changed;
1477 /* Discard any register replacements done. */
1478 if (did_elimination)
1480 obstack_free (&reload_obstack, reload_insn_firstobj);
1481 PATTERN (insn) = old_body;
1482 INSN_CODE (insn) = old_code;
1483 REG_NOTES (insn) = old_notes;
1484 something_needs_elimination = 1;
1487 something_needs_operands_changed |= operands_changed;
1491 copy_reloads (chain);
1492 *pprev_reload = chain;
1493 pprev_reload = &chain->next_need_reload;
1500 /* Comparison function for qsort to decide which of two reloads
1501 should be handled first. *P1 and *P2 are the reload numbers. */
1504 reload_reg_class_lower (const void *r1p, const void *r2p)
1506 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1509 /* Consider required reloads before optional ones. */
1510 t = rld[r1].optional - rld[r2].optional;
1514 /* Count all solitary classes before non-solitary ones. */
1515 t = ((reg_class_size[(int) rld[r2].class] == 1)
1516 - (reg_class_size[(int) rld[r1].class] == 1));
1520 /* Aside from solitaires, consider all multi-reg groups first. */
1521 t = rld[r2].nregs - rld[r1].nregs;
1525 /* Consider reloads in order of increasing reg-class number. */
1526 t = (int) rld[r1].class - (int) rld[r2].class;
1530 /* If reloads are equally urgent, sort by reload number,
1531 so that the results of qsort leave nothing to chance. */
1535 /* The cost of spilling each hard reg. */
1536 static int spill_cost[FIRST_PSEUDO_REGISTER];
1538 /* When spilling multiple hard registers, we use SPILL_COST for the first
1539 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1540 only the first hard reg for a multi-reg pseudo. */
1541 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1543 /* Update the spill cost arrays, considering that pseudo REG is live. */
1546 count_pseudo (int reg)
1548 int freq = REG_FREQ (reg);
1549 int r = reg_renumber[reg];
1552 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1553 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1556 SET_REGNO_REG_SET (&pseudos_counted, reg);
1561 spill_add_cost[r] += freq;
1563 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1565 spill_cost[r + nregs] += freq;
1568 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1569 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1572 order_regs_for_reload (struct insn_chain *chain)
1575 HARD_REG_SET used_by_pseudos;
1576 HARD_REG_SET used_by_pseudos2;
1578 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1580 memset (spill_cost, 0, sizeof spill_cost);
1581 memset (spill_add_cost, 0, sizeof spill_add_cost);
1583 /* Count number of uses of each hard reg by pseudo regs allocated to it
1584 and then order them by decreasing use. First exclude hard registers
1585 that are live in or across this insn. */
1587 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1588 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1589 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1590 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1592 /* Now find out which pseudos are allocated to it, and update
1594 CLEAR_REG_SET (&pseudos_counted);
1596 EXECUTE_IF_SET_IN_REG_SET
1597 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1601 EXECUTE_IF_SET_IN_REG_SET
1602 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1606 CLEAR_REG_SET (&pseudos_counted);
1609 /* Vector of reload-numbers showing the order in which the reloads should
1611 static short reload_order[MAX_RELOADS];
1613 /* This is used to keep track of the spill regs used in one insn. */
1614 static HARD_REG_SET used_spill_regs_local;
1616 /* We decided to spill hard register SPILLED, which has a size of
1617 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1618 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1619 update SPILL_COST/SPILL_ADD_COST. */
1622 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1624 int r = reg_renumber[reg];
1625 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1627 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1628 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1631 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1633 spill_add_cost[r] -= REG_FREQ (reg);
1635 spill_cost[r + nregs] -= REG_FREQ (reg);
1638 /* Find reload register to use for reload number ORDER. */
1641 find_reg (struct insn_chain *chain, int order)
1643 int rnum = reload_order[order];
1644 struct reload *rl = rld + rnum;
1645 int best_cost = INT_MAX;
1649 HARD_REG_SET not_usable;
1650 HARD_REG_SET used_by_other_reload;
1652 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1653 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1654 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1656 CLEAR_HARD_REG_SET (used_by_other_reload);
1657 for (k = 0; k < order; k++)
1659 int other = reload_order[k];
1661 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1662 for (j = 0; j < rld[other].nregs; j++)
1663 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1666 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1668 unsigned int regno = i;
1670 if (! TEST_HARD_REG_BIT (not_usable, regno)
1671 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1672 && HARD_REGNO_MODE_OK (regno, rl->mode))
1674 int this_cost = spill_cost[regno];
1676 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1678 for (j = 1; j < this_nregs; j++)
1680 this_cost += spill_add_cost[regno + j];
1681 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1682 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1687 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1689 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1691 if (this_cost < best_cost
1692 /* Among registers with equal cost, prefer caller-saved ones, or
1693 use REG_ALLOC_ORDER if it is defined. */
1694 || (this_cost == best_cost
1695 #ifdef REG_ALLOC_ORDER
1696 && (inv_reg_alloc_order[regno]
1697 < inv_reg_alloc_order[best_reg])
1699 && call_used_regs[regno]
1700 && ! call_used_regs[best_reg]
1705 best_cost = this_cost;
1713 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1715 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1716 rl->regno = best_reg;
1718 EXECUTE_IF_SET_IN_REG_SET
1719 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1721 count_spilled_pseudo (best_reg, rl->nregs, j);
1724 EXECUTE_IF_SET_IN_REG_SET
1725 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1727 count_spilled_pseudo (best_reg, rl->nregs, j);
1730 for (i = 0; i < rl->nregs; i++)
1732 if (spill_cost[best_reg + i] != 0
1733 || spill_add_cost[best_reg + i] != 0)
1735 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1740 /* Find more reload regs to satisfy the remaining need of an insn, which
1742 Do it by ascending class number, since otherwise a reg
1743 might be spilled for a big class and might fail to count
1744 for a smaller class even though it belongs to that class. */
1747 find_reload_regs (struct insn_chain *chain)
1751 /* In order to be certain of getting the registers we need,
1752 we must sort the reloads into order of increasing register class.
1753 Then our grabbing of reload registers will parallel the process
1754 that provided the reload registers. */
1755 for (i = 0; i < chain->n_reloads; i++)
1757 /* Show whether this reload already has a hard reg. */
1758 if (chain->rld[i].reg_rtx)
1760 int regno = REGNO (chain->rld[i].reg_rtx);
1761 chain->rld[i].regno = regno;
1763 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1766 chain->rld[i].regno = -1;
1767 reload_order[i] = i;
1770 n_reloads = chain->n_reloads;
1771 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1773 CLEAR_HARD_REG_SET (used_spill_regs_local);
1776 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1778 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1780 /* Compute the order of preference for hard registers to spill. */
1782 order_regs_for_reload (chain);
1784 for (i = 0; i < n_reloads; i++)
1786 int r = reload_order[i];
1788 /* Ignore reloads that got marked inoperative. */
1789 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1790 && ! rld[r].optional
1791 && rld[r].regno == -1)
1792 if (! find_reg (chain, i))
1794 spill_failure (chain->insn, rld[r].class);
1800 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1801 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1803 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1807 select_reload_regs (void)
1809 struct insn_chain *chain;
1811 /* Try to satisfy the needs for each insn. */
1812 for (chain = insns_need_reload; chain != 0;
1813 chain = chain->next_need_reload)
1814 find_reload_regs (chain);
1817 /* Delete all insns that were inserted by emit_caller_save_insns during
1820 delete_caller_save_insns (void)
1822 struct insn_chain *c = reload_insn_chain;
1826 while (c != 0 && c->is_caller_save_insn)
1828 struct insn_chain *next = c->next;
1831 if (c == reload_insn_chain)
1832 reload_insn_chain = next;
1836 next->prev = c->prev;
1838 c->prev->next = next;
1839 c->next = unused_insn_chains;
1840 unused_insn_chains = c;
1848 /* Handle the failure to find a register to spill.
1849 INSN should be one of the insns which needed this particular spill reg. */
1852 spill_failure (rtx insn, enum reg_class class)
1854 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1855 if (asm_noperands (PATTERN (insn)) >= 0)
1856 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1857 reg_class_names[class]);
1860 error ("unable to find a register to spill in class `%s'",
1861 reg_class_names[class]);
1862 fatal_insn ("this is the insn:", insn);
1866 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1867 data that is dead in INSN. */
1870 delete_dead_insn (rtx insn)
1872 rtx prev = prev_real_insn (insn);
1875 /* If the previous insn sets a register that dies in our insn, delete it
1877 if (prev && GET_CODE (PATTERN (prev)) == SET
1878 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1879 && reg_mentioned_p (prev_dest, PATTERN (insn))
1880 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1881 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1882 delete_dead_insn (prev);
1884 PUT_CODE (insn, NOTE);
1885 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1886 NOTE_SOURCE_FILE (insn) = 0;
1889 /* Modify the home of pseudo-reg I.
1890 The new home is present in reg_renumber[I].
1892 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1893 or it may be -1, meaning there is none or it is not relevant.
1894 This is used so that all pseudos spilled from a given hard reg
1895 can share one stack slot. */
1898 alter_reg (int i, int from_reg)
1900 /* When outputting an inline function, this can happen
1901 for a reg that isn't actually used. */
1902 if (regno_reg_rtx[i] == 0)
1905 /* If the reg got changed to a MEM at rtl-generation time,
1907 if (GET_CODE (regno_reg_rtx[i]) != REG)
1910 /* Modify the reg-rtx to contain the new hard reg
1911 number or else to contain its pseudo reg number. */
1912 REGNO (regno_reg_rtx[i])
1913 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1915 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1916 allocate a stack slot for it. */
1918 if (reg_renumber[i] < 0
1919 && REG_N_REFS (i) > 0
1920 && reg_equiv_constant[i] == 0
1921 && reg_equiv_memory_loc[i] == 0)
1924 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1925 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1928 /* Each pseudo reg has an inherent size which comes from its own mode,
1929 and a total size which provides room for paradoxical subregs
1930 which refer to the pseudo reg in wider modes.
1932 We can use a slot already allocated if it provides both
1933 enough inherent space and enough total space.
1934 Otherwise, we allocate a new slot, making sure that it has no less
1935 inherent space, and no less total space, then the previous slot. */
1938 /* No known place to spill from => no slot to reuse. */
1939 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1940 inherent_size == total_size ? 0 : -1);
1941 if (BYTES_BIG_ENDIAN)
1942 /* Cancel the big-endian correction done in assign_stack_local.
1943 Get the address of the beginning of the slot.
1944 This is so we can do a big-endian correction unconditionally
1946 adjust = inherent_size - total_size;
1948 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1950 /* Nothing can alias this slot except this pseudo. */
1951 set_mem_alias_set (x, new_alias_set ());
1954 /* Reuse a stack slot if possible. */
1955 else if (spill_stack_slot[from_reg] != 0
1956 && spill_stack_slot_width[from_reg] >= total_size
1957 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1959 x = spill_stack_slot[from_reg];
1961 /* Allocate a bigger slot. */
1964 /* Compute maximum size needed, both for inherent size
1965 and for total size. */
1966 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1969 if (spill_stack_slot[from_reg])
1971 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1973 mode = GET_MODE (spill_stack_slot[from_reg]);
1974 if (spill_stack_slot_width[from_reg] > total_size)
1975 total_size = spill_stack_slot_width[from_reg];
1978 /* Make a slot with that size. */
1979 x = assign_stack_local (mode, total_size,
1980 inherent_size == total_size ? 0 : -1);
1983 /* All pseudos mapped to this slot can alias each other. */
1984 if (spill_stack_slot[from_reg])
1985 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
1987 set_mem_alias_set (x, new_alias_set ());
1989 if (BYTES_BIG_ENDIAN)
1991 /* Cancel the big-endian correction done in assign_stack_local.
1992 Get the address of the beginning of the slot.
1993 This is so we can do a big-endian correction unconditionally
1995 adjust = GET_MODE_SIZE (mode) - total_size;
1998 = adjust_address_nv (x, mode_for_size (total_size
2004 spill_stack_slot[from_reg] = stack_slot;
2005 spill_stack_slot_width[from_reg] = total_size;
2008 /* On a big endian machine, the "address" of the slot
2009 is the address of the low part that fits its inherent mode. */
2010 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2011 adjust += (total_size - inherent_size);
2013 /* If we have any adjustment to make, or if the stack slot is the
2014 wrong mode, make a new stack slot. */
2015 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2017 /* If we have a decl for the original register, set it for the
2018 memory. If this is a shared MEM, make a copy. */
2019 if (REG_EXPR (regno_reg_rtx[i])
2020 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2022 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2024 /* We can do this only for the DECLs home pseudo, not for
2025 any copies of it, since otherwise when the stack slot
2026 is reused, nonoverlapping_memrefs_p might think they
2028 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2030 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2033 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2037 /* Save the stack slot for later. */
2038 reg_equiv_memory_loc[i] = x;
2042 /* Mark the slots in regs_ever_live for the hard regs
2043 used by pseudo-reg number REGNO. */
2046 mark_home_live (int regno)
2050 i = reg_renumber[regno];
2053 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2055 regs_ever_live[i++] = 1;
2058 /* This function handles the tracking of elimination offsets around branches.
2060 X is a piece of RTL being scanned.
2062 INSN is the insn that it came from, if any.
2064 INITIAL_P is nonzero if we are to set the offset to be the initial
2065 offset and zero if we are setting the offset of the label to be the
2069 set_label_offsets (rtx x, rtx insn, int initial_p)
2071 enum rtx_code code = GET_CODE (x);
2074 struct elim_table *p;
2079 if (LABEL_REF_NONLOCAL_P (x))
2084 /* ... fall through ... */
2087 /* If we know nothing about this label, set the desired offsets. Note
2088 that this sets the offset at a label to be the offset before a label
2089 if we don't know anything about the label. This is not correct for
2090 the label after a BARRIER, but is the best guess we can make. If
2091 we guessed wrong, we will suppress an elimination that might have
2092 been possible had we been able to guess correctly. */
2094 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2096 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2097 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2098 = (initial_p ? reg_eliminate[i].initial_offset
2099 : reg_eliminate[i].offset);
2100 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2103 /* Otherwise, if this is the definition of a label and it is
2104 preceded by a BARRIER, set our offsets to the known offset of
2108 && (tem = prev_nonnote_insn (insn)) != 0
2109 && GET_CODE (tem) == BARRIER)
2110 set_offsets_for_label (insn);
2112 /* If neither of the above cases is true, compare each offset
2113 with those previously recorded and suppress any eliminations
2114 where the offsets disagree. */
2116 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2117 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2118 != (initial_p ? reg_eliminate[i].initial_offset
2119 : reg_eliminate[i].offset))
2120 reg_eliminate[i].can_eliminate = 0;
2125 set_label_offsets (PATTERN (insn), insn, initial_p);
2127 /* ... fall through ... */
2131 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2132 and hence must have all eliminations at their initial offsets. */
2133 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2134 if (REG_NOTE_KIND (tem) == REG_LABEL)
2135 set_label_offsets (XEXP (tem, 0), insn, 1);
2141 /* Each of the labels in the parallel or address vector must be
2142 at their initial offsets. We want the first field for PARALLEL
2143 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2145 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2146 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2151 /* We only care about setting PC. If the source is not RETURN,
2152 IF_THEN_ELSE, or a label, disable any eliminations not at
2153 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2154 isn't one of those possibilities. For branches to a label,
2155 call ourselves recursively.
2157 Note that this can disable elimination unnecessarily when we have
2158 a non-local goto since it will look like a non-constant jump to
2159 someplace in the current function. This isn't a significant
2160 problem since such jumps will normally be when all elimination
2161 pairs are back to their initial offsets. */
2163 if (SET_DEST (x) != pc_rtx)
2166 switch (GET_CODE (SET_SRC (x)))
2173 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2177 tem = XEXP (SET_SRC (x), 1);
2178 if (GET_CODE (tem) == LABEL_REF)
2179 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2180 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2183 tem = XEXP (SET_SRC (x), 2);
2184 if (GET_CODE (tem) == LABEL_REF)
2185 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2186 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2194 /* If we reach here, all eliminations must be at their initial
2195 offset because we are doing a jump to a variable address. */
2196 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2197 if (p->offset != p->initial_offset)
2198 p->can_eliminate = 0;
2206 /* Scan X and replace any eliminable registers (such as fp) with a
2207 replacement (such as sp), plus an offset.
2209 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2210 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2211 MEM, we are allowed to replace a sum of a register and the constant zero
2212 with the register, which we cannot do outside a MEM. In addition, we need
2213 to record the fact that a register is referenced outside a MEM.
2215 If INSN is an insn, it is the insn containing X. If we replace a REG
2216 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2217 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2218 the REG is being modified.
2220 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2221 That's used when we eliminate in expressions stored in notes.
2222 This means, do not set ref_outside_mem even if the reference
2225 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2226 replacements done assuming all offsets are at their initial values. If
2227 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2228 encounter, return the actual location so that find_reloads will do
2229 the proper thing. */
2232 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2234 enum rtx_code code = GET_CODE (x);
2235 struct elim_table *ep;
2242 if (! current_function_decl)
2262 /* This is only for the benefit of the debugging backends, which call
2263 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2264 removed after CSE. */
2265 new = eliminate_regs (XEXP (x, 0), 0, insn);
2266 if (GET_CODE (new) == MEM)
2267 return XEXP (new, 0);
2273 /* First handle the case where we encounter a bare register that
2274 is eliminable. Replace it with a PLUS. */
2275 if (regno < FIRST_PSEUDO_REGISTER)
2277 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2279 if (ep->from_rtx == x && ep->can_eliminate)
2280 return plus_constant (ep->to_rtx, ep->previous_offset);
2283 else if (reg_renumber && reg_renumber[regno] < 0
2284 && reg_equiv_constant && reg_equiv_constant[regno]
2285 && ! CONSTANT_P (reg_equiv_constant[regno]))
2286 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2290 /* You might think handling MINUS in a manner similar to PLUS is a
2291 good idea. It is not. It has been tried multiple times and every
2292 time the change has had to have been reverted.
2294 Other parts of reload know a PLUS is special (gen_reload for example)
2295 and require special code to handle code a reloaded PLUS operand.
2297 Also consider backends where the flags register is clobbered by a
2298 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2299 lea instruction comes to mind). If we try to reload a MINUS, we
2300 may kill the flags register that was holding a useful value.
2302 So, please before trying to handle MINUS, consider reload as a
2303 whole instead of this little section as well as the backend issues. */
2305 /* If this is the sum of an eliminable register and a constant, rework
2307 if (GET_CODE (XEXP (x, 0)) == REG
2308 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2309 && CONSTANT_P (XEXP (x, 1)))
2311 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2313 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2315 /* The only time we want to replace a PLUS with a REG (this
2316 occurs when the constant operand of the PLUS is the negative
2317 of the offset) is when we are inside a MEM. We won't want
2318 to do so at other times because that would change the
2319 structure of the insn in a way that reload can't handle.
2320 We special-case the commonest situation in
2321 eliminate_regs_in_insn, so just replace a PLUS with a
2322 PLUS here, unless inside a MEM. */
2323 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2324 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2327 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2328 plus_constant (XEXP (x, 1),
2329 ep->previous_offset));
2332 /* If the register is not eliminable, we are done since the other
2333 operand is a constant. */
2337 /* If this is part of an address, we want to bring any constant to the
2338 outermost PLUS. We will do this by doing register replacement in
2339 our operands and seeing if a constant shows up in one of them.
2341 Note that there is no risk of modifying the structure of the insn,
2342 since we only get called for its operands, thus we are either
2343 modifying the address inside a MEM, or something like an address
2344 operand of a load-address insn. */
2347 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2348 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2350 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2352 /* If one side is a PLUS and the other side is a pseudo that
2353 didn't get a hard register but has a reg_equiv_constant,
2354 we must replace the constant here since it may no longer
2355 be in the position of any operand. */
2356 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2357 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2358 && reg_renumber[REGNO (new1)] < 0
2359 && reg_equiv_constant != 0
2360 && reg_equiv_constant[REGNO (new1)] != 0)
2361 new1 = reg_equiv_constant[REGNO (new1)];
2362 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2363 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2364 && reg_renumber[REGNO (new0)] < 0
2365 && reg_equiv_constant[REGNO (new0)] != 0)
2366 new0 = reg_equiv_constant[REGNO (new0)];
2368 new = form_sum (new0, new1);
2370 /* As above, if we are not inside a MEM we do not want to
2371 turn a PLUS into something else. We might try to do so here
2372 for an addition of 0 if we aren't optimizing. */
2373 if (! mem_mode && GET_CODE (new) != PLUS)
2374 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2382 /* If this is the product of an eliminable register and a
2383 constant, apply the distribute law and move the constant out
2384 so that we have (plus (mult ..) ..). This is needed in order
2385 to keep load-address insns valid. This case is pathological.
2386 We ignore the possibility of overflow here. */
2387 if (GET_CODE (XEXP (x, 0)) == REG
2388 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2389 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2390 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2392 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2395 /* Refs inside notes don't count for this purpose. */
2396 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2397 || GET_CODE (insn) == INSN_LIST)))
2398 ep->ref_outside_mem = 1;
2401 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2402 ep->previous_offset * INTVAL (XEXP (x, 1)));
2405 /* ... fall through ... */
2409 /* See comments before PLUS about handling MINUS. */
2411 case DIV: case UDIV:
2412 case MOD: case UMOD:
2413 case AND: case IOR: case XOR:
2414 case ROTATERT: case ROTATE:
2415 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2417 case GE: case GT: case GEU: case GTU:
2418 case LE: case LT: case LEU: case LTU:
2420 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2422 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2424 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2425 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2430 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2433 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2434 if (new != XEXP (x, 0))
2436 /* If this is a REG_DEAD note, it is not valid anymore.
2437 Using the eliminated version could result in creating a
2438 REG_DEAD note for the stack or frame pointer. */
2439 if (GET_MODE (x) == REG_DEAD)
2441 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2444 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2448 /* ... fall through ... */
2451 /* Now do eliminations in the rest of the chain. If this was
2452 an EXPR_LIST, this might result in allocating more memory than is
2453 strictly needed, but it simplifies the code. */
2456 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2457 if (new != XEXP (x, 1))
2459 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2467 case STRICT_LOW_PART:
2469 case SIGN_EXTEND: case ZERO_EXTEND:
2470 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2471 case FLOAT: case FIX:
2472 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2480 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2481 if (new != XEXP (x, 0))
2482 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2486 /* Similar to above processing, but preserve SUBREG_BYTE.
2487 Convert (subreg (mem)) to (mem) if not paradoxical.
2488 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2489 pseudo didn't get a hard reg, we must replace this with the
2490 eliminated version of the memory location because push_reload
2491 may do the replacement in certain circumstances. */
2492 if (GET_CODE (SUBREG_REG (x)) == REG
2493 && (GET_MODE_SIZE (GET_MODE (x))
2494 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2495 && reg_equiv_memory_loc != 0
2496 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2498 new = SUBREG_REG (x);
2501 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2503 if (new != SUBREG_REG (x))
2505 int x_size = GET_MODE_SIZE (GET_MODE (x));
2506 int new_size = GET_MODE_SIZE (GET_MODE (new));
2508 if (GET_CODE (new) == MEM
2509 && ((x_size < new_size
2510 #ifdef WORD_REGISTER_OPERATIONS
2511 /* On these machines, combine can create rtl of the form
2512 (set (subreg:m1 (reg:m2 R) 0) ...)
2513 where m1 < m2, and expects something interesting to
2514 happen to the entire word. Moreover, it will use the
2515 (reg:m2 R) later, expecting all bits to be preserved.
2516 So if the number of words is the same, preserve the
2517 subreg so that push_reload can see it. */
2518 && ! ((x_size - 1) / UNITS_PER_WORD
2519 == (new_size -1 ) / UNITS_PER_WORD)
2522 || x_size == new_size)
2524 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2526 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2532 /* This is only for the benefit of the debugging backends, which call
2533 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2534 removed after CSE. */
2535 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2536 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2538 /* Our only special processing is to pass the mode of the MEM to our
2539 recursive call and copy the flags. While we are here, handle this
2540 case more efficiently. */
2542 replace_equiv_address_nv (x,
2543 eliminate_regs (XEXP (x, 0),
2544 GET_MODE (x), insn));
2547 /* Handle insn_list USE that a call to a pure function may generate. */
2548 new = eliminate_regs (XEXP (x, 0), 0, insn);
2549 if (new != XEXP (x, 0))
2550 return gen_rtx_USE (GET_MODE (x), new);
2562 /* Process each of our operands recursively. If any have changed, make a
2564 fmt = GET_RTX_FORMAT (code);
2565 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2569 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2570 if (new != XEXP (x, i) && ! copied)
2572 rtx new_x = rtx_alloc (code);
2574 (sizeof (*new_x) - sizeof (new_x->fld)
2575 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2581 else if (*fmt == 'E')
2584 for (j = 0; j < XVECLEN (x, i); j++)
2586 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2587 if (new != XVECEXP (x, i, j) && ! copied_vec)
2589 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2593 rtx new_x = rtx_alloc (code);
2595 (sizeof (*new_x) - sizeof (new_x->fld)
2596 + (sizeof (new_x->fld[0])
2597 * GET_RTX_LENGTH (code))));
2601 XVEC (x, i) = new_v;
2604 XVECEXP (x, i, j) = new;
2612 /* Scan rtx X for modifications of elimination target registers. Update
2613 the table of eliminables to reflect the changed state. MEM_MODE is
2614 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2617 elimination_effects (rtx x, enum machine_mode mem_mode)
2619 enum rtx_code code = GET_CODE (x);
2620 struct elim_table *ep;
2647 /* First handle the case where we encounter a bare register that
2648 is eliminable. Replace it with a PLUS. */
2649 if (regno < FIRST_PSEUDO_REGISTER)
2651 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2653 if (ep->from_rtx == x && ep->can_eliminate)
2656 ep->ref_outside_mem = 1;
2661 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2662 && reg_equiv_constant[regno]
2663 && ! function_invariant_p (reg_equiv_constant[regno]))
2664 elimination_effects (reg_equiv_constant[regno], mem_mode);
2673 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2674 if (ep->to_rtx == XEXP (x, 0))
2676 int size = GET_MODE_SIZE (mem_mode);
2678 /* If more bytes than MEM_MODE are pushed, account for them. */
2679 #ifdef PUSH_ROUNDING
2680 if (ep->to_rtx == stack_pointer_rtx)
2681 size = PUSH_ROUNDING (size);
2683 if (code == PRE_DEC || code == POST_DEC)
2685 else if (code == PRE_INC || code == POST_INC)
2687 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2688 && GET_CODE (XEXP (x, 1)) == PLUS
2689 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2690 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2691 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2694 /* These two aren't unary operators. */
2695 if (code == POST_MODIFY || code == PRE_MODIFY)
2698 /* Fall through to generic unary operation case. */
2699 case STRICT_LOW_PART:
2701 case SIGN_EXTEND: case ZERO_EXTEND:
2702 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2703 case FLOAT: case FIX:
2704 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2712 elimination_effects (XEXP (x, 0), mem_mode);
2716 if (GET_CODE (SUBREG_REG (x)) == REG
2717 && (GET_MODE_SIZE (GET_MODE (x))
2718 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2719 && reg_equiv_memory_loc != 0
2720 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2723 elimination_effects (SUBREG_REG (x), mem_mode);
2727 /* If using a register that is the source of an eliminate we still
2728 think can be performed, note it cannot be performed since we don't
2729 know how this register is used. */
2730 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2731 if (ep->from_rtx == XEXP (x, 0))
2732 ep->can_eliminate = 0;
2734 elimination_effects (XEXP (x, 0), mem_mode);
2738 /* If clobbering a register that is the replacement register for an
2739 elimination we still think can be performed, note that it cannot
2740 be performed. Otherwise, we need not be concerned about it. */
2741 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2742 if (ep->to_rtx == XEXP (x, 0))
2743 ep->can_eliminate = 0;
2745 elimination_effects (XEXP (x, 0), mem_mode);
2749 /* Check for setting a register that we know about. */
2750 if (GET_CODE (SET_DEST (x)) == REG)
2752 /* See if this is setting the replacement register for an
2755 If DEST is the hard frame pointer, we do nothing because we
2756 assume that all assignments to the frame pointer are for
2757 non-local gotos and are being done at a time when they are valid
2758 and do not disturb anything else. Some machines want to
2759 eliminate a fake argument pointer (or even a fake frame pointer)
2760 with either the real frame or the stack pointer. Assignments to
2761 the hard frame pointer must not prevent this elimination. */
2763 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2765 if (ep->to_rtx == SET_DEST (x)
2766 && SET_DEST (x) != hard_frame_pointer_rtx)
2768 /* If it is being incremented, adjust the offset. Otherwise,
2769 this elimination can't be done. */
2770 rtx src = SET_SRC (x);
2772 if (GET_CODE (src) == PLUS
2773 && XEXP (src, 0) == SET_DEST (x)
2774 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2775 ep->offset -= INTVAL (XEXP (src, 1));
2777 ep->can_eliminate = 0;
2781 elimination_effects (SET_DEST (x), 0);
2782 elimination_effects (SET_SRC (x), 0);
2786 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2789 /* Our only special processing is to pass the mode of the MEM to our
2791 elimination_effects (XEXP (x, 0), GET_MODE (x));
2798 fmt = GET_RTX_FORMAT (code);
2799 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2802 elimination_effects (XEXP (x, i), mem_mode);
2803 else if (*fmt == 'E')
2804 for (j = 0; j < XVECLEN (x, i); j++)
2805 elimination_effects (XVECEXP (x, i, j), mem_mode);
2809 /* Descend through rtx X and verify that no references to eliminable registers
2810 remain. If any do remain, mark the involved register as not
2814 check_eliminable_occurrences (rtx x)
2823 code = GET_CODE (x);
2825 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2827 struct elim_table *ep;
2829 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2830 if (ep->from_rtx == x && ep->can_eliminate)
2831 ep->can_eliminate = 0;
2835 fmt = GET_RTX_FORMAT (code);
2836 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2839 check_eliminable_occurrences (XEXP (x, i));
2840 else if (*fmt == 'E')
2843 for (j = 0; j < XVECLEN (x, i); j++)
2844 check_eliminable_occurrences (XVECEXP (x, i, j));
2849 /* Scan INSN and eliminate all eliminable registers in it.
2851 If REPLACE is nonzero, do the replacement destructively. Also
2852 delete the insn as dead it if it is setting an eliminable register.
2854 If REPLACE is zero, do all our allocations in reload_obstack.
2856 If no eliminations were done and this insn doesn't require any elimination
2857 processing (these are not identical conditions: it might be updating sp,
2858 but not referencing fp; this needs to be seen during reload_as_needed so
2859 that the offset between fp and sp can be taken into consideration), zero
2860 is returned. Otherwise, 1 is returned. */
2863 eliminate_regs_in_insn (rtx insn, int replace)
2865 int icode = recog_memoized (insn);
2866 rtx old_body = PATTERN (insn);
2867 int insn_is_asm = asm_noperands (old_body) >= 0;
2868 rtx old_set = single_set (insn);
2872 rtx substed_operand[MAX_RECOG_OPERANDS];
2873 rtx orig_operand[MAX_RECOG_OPERANDS];
2874 struct elim_table *ep;
2876 if (! insn_is_asm && icode < 0)
2878 if (GET_CODE (PATTERN (insn)) == USE
2879 || GET_CODE (PATTERN (insn)) == CLOBBER
2880 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2881 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2882 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2887 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2888 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2890 /* Check for setting an eliminable register. */
2891 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2892 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2894 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2895 /* If this is setting the frame pointer register to the
2896 hardware frame pointer register and this is an elimination
2897 that will be done (tested above), this insn is really
2898 adjusting the frame pointer downward to compensate for
2899 the adjustment done before a nonlocal goto. */
2900 if (ep->from == FRAME_POINTER_REGNUM
2901 && ep->to == HARD_FRAME_POINTER_REGNUM)
2903 rtx base = SET_SRC (old_set);
2904 rtx base_insn = insn;
2907 while (base != ep->to_rtx)
2909 rtx prev_insn, prev_set;
2911 if (GET_CODE (base) == PLUS
2912 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2914 offset += INTVAL (XEXP (base, 1));
2915 base = XEXP (base, 0);
2917 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2918 && (prev_set = single_set (prev_insn)) != 0
2919 && rtx_equal_p (SET_DEST (prev_set), base))
2921 base = SET_SRC (prev_set);
2922 base_insn = prev_insn;
2928 if (base == ep->to_rtx)
2931 = plus_constant (ep->to_rtx, offset - ep->offset);
2933 new_body = old_body;
2936 new_body = copy_insn (old_body);
2937 if (REG_NOTES (insn))
2938 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2940 PATTERN (insn) = new_body;
2941 old_set = single_set (insn);
2943 /* First see if this insn remains valid when we
2944 make the change. If not, keep the INSN_CODE
2945 the same and let reload fit it up. */
2946 validate_change (insn, &SET_SRC (old_set), src, 1);
2947 validate_change (insn, &SET_DEST (old_set),
2949 if (! apply_change_group ())
2951 SET_SRC (old_set) = src;
2952 SET_DEST (old_set) = ep->to_rtx;
2961 /* In this case this insn isn't serving a useful purpose. We
2962 will delete it in reload_as_needed once we know that this
2963 elimination is, in fact, being done.
2965 If REPLACE isn't set, we can't delete this insn, but needn't
2966 process it since it won't be used unless something changes. */
2969 delete_dead_insn (insn);
2977 /* We allow one special case which happens to work on all machines we
2978 currently support: a single set with the source being a PLUS of an
2979 eliminable register and a constant. */
2981 && GET_CODE (SET_DEST (old_set)) == REG
2982 && GET_CODE (SET_SRC (old_set)) == PLUS
2983 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2984 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2985 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2987 rtx reg = XEXP (SET_SRC (old_set), 0);
2988 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2990 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2991 if (ep->from_rtx == reg && ep->can_eliminate)
2993 offset += ep->offset;
2998 /* We assume here that if we need a PARALLEL with
2999 CLOBBERs for this assignment, we can do with the
3000 MATCH_SCRATCHes that add_clobbers allocates.
3001 There's not much we can do if that doesn't work. */
3002 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3006 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3009 rtvec vec = rtvec_alloc (num_clobbers + 1);
3011 vec->elem[0] = PATTERN (insn);
3012 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3013 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3015 if (INSN_CODE (insn) < 0)
3020 new_body = old_body;
3023 new_body = copy_insn (old_body);
3024 if (REG_NOTES (insn))
3025 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3027 PATTERN (insn) = new_body;
3028 old_set = single_set (insn);
3030 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3031 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3034 /* This can't have an effect on elimination offsets, so skip right
3040 /* Determine the effects of this insn on elimination offsets. */
3041 elimination_effects (old_body, 0);
3043 /* Eliminate all eliminable registers occurring in operands that
3044 can be handled by reload. */
3045 extract_insn (insn);
3046 for (i = 0; i < recog_data.n_operands; i++)
3048 orig_operand[i] = recog_data.operand[i];
3049 substed_operand[i] = recog_data.operand[i];
3051 /* For an asm statement, every operand is eliminable. */
3052 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3054 /* Check for setting a register that we know about. */
3055 if (recog_data.operand_type[i] != OP_IN
3056 && GET_CODE (orig_operand[i]) == REG)
3058 /* If we are assigning to a register that can be eliminated, it
3059 must be as part of a PARALLEL, since the code above handles
3060 single SETs. We must indicate that we can no longer
3061 eliminate this reg. */
3062 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3064 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3065 ep->can_eliminate = 0;
3068 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3069 replace ? insn : NULL_RTX);
3070 if (substed_operand[i] != orig_operand[i])
3072 /* Terminate the search in check_eliminable_occurrences at
3074 *recog_data.operand_loc[i] = 0;
3076 /* If an output operand changed from a REG to a MEM and INSN is an
3077 insn, write a CLOBBER insn. */
3078 if (recog_data.operand_type[i] != OP_IN
3079 && GET_CODE (orig_operand[i]) == REG
3080 && GET_CODE (substed_operand[i]) == MEM
3082 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3087 for (i = 0; i < recog_data.n_dups; i++)
3088 *recog_data.dup_loc[i]
3089 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3091 /* If any eliminable remain, they aren't eliminable anymore. */
3092 check_eliminable_occurrences (old_body);
3094 /* Substitute the operands; the new values are in the substed_operand
3096 for (i = 0; i < recog_data.n_operands; i++)
3097 *recog_data.operand_loc[i] = substed_operand[i];
3098 for (i = 0; i < recog_data.n_dups; i++)
3099 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3101 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3102 re-recognize the insn. We do this in case we had a simple addition
3103 but now can do this as a load-address. This saves an insn in this
3105 If re-recognition fails, the old insn code number will still be used,
3106 and some register operands may have changed into PLUS expressions.
3107 These will be handled by find_reloads by loading them into a register
3112 /* If we aren't replacing things permanently and we changed something,
3113 make another copy to ensure that all the RTL is new. Otherwise
3114 things can go wrong if find_reload swaps commutative operands
3115 and one is inside RTL that has been copied while the other is not. */
3116 new_body = old_body;
3119 new_body = copy_insn (old_body);
3120 if (REG_NOTES (insn))
3121 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3123 PATTERN (insn) = new_body;
3125 /* If we had a move insn but now we don't, rerecognize it. This will
3126 cause spurious re-recognition if the old move had a PARALLEL since
3127 the new one still will, but we can't call single_set without
3128 having put NEW_BODY into the insn and the re-recognition won't
3129 hurt in this rare case. */
3130 /* ??? Why this huge if statement - why don't we just rerecognize the
3134 && ((GET_CODE (SET_SRC (old_set)) == REG
3135 && (GET_CODE (new_body) != SET
3136 || GET_CODE (SET_SRC (new_body)) != REG))
3137 /* If this was a load from or store to memory, compare
3138 the MEM in recog_data.operand to the one in the insn.
3139 If they are not equal, then rerecognize the insn. */
3141 && ((GET_CODE (SET_SRC (old_set)) == MEM
3142 && SET_SRC (old_set) != recog_data.operand[1])
3143 || (GET_CODE (SET_DEST (old_set)) == MEM
3144 && SET_DEST (old_set) != recog_data.operand[0])))
3145 /* If this was an add insn before, rerecognize. */
3146 || GET_CODE (SET_SRC (old_set)) == PLUS))
3148 int new_icode = recog (PATTERN (insn), insn, 0);
3150 INSN_CODE (insn) = icode;
3154 /* Restore the old body. If there were any changes to it, we made a copy
3155 of it while the changes were still in place, so we'll correctly return
3156 a modified insn below. */
3159 /* Restore the old body. */
3160 for (i = 0; i < recog_data.n_operands; i++)
3161 *recog_data.operand_loc[i] = orig_operand[i];
3162 for (i = 0; i < recog_data.n_dups; i++)
3163 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3166 /* Update all elimination pairs to reflect the status after the current
3167 insn. The changes we make were determined by the earlier call to
3168 elimination_effects.
3170 We also detect cases where register elimination cannot be done,
3171 namely, if a register would be both changed and referenced outside a MEM
3172 in the resulting insn since such an insn is often undefined and, even if
3173 not, we cannot know what meaning will be given to it. Note that it is
3174 valid to have a register used in an address in an insn that changes it
3175 (presumably with a pre- or post-increment or decrement).
3177 If anything changes, return nonzero. */
3179 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3181 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3182 ep->can_eliminate = 0;
3184 ep->ref_outside_mem = 0;
3186 if (ep->previous_offset != ep->offset)
3191 /* If we changed something, perform elimination in REG_NOTES. This is
3192 needed even when REPLACE is zero because a REG_DEAD note might refer
3193 to a register that we eliminate and could cause a different number
3194 of spill registers to be needed in the final reload pass than in
3196 if (val && REG_NOTES (insn) != 0)
3197 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3202 /* Loop through all elimination pairs.
3203 Recalculate the number not at initial offset.
3205 Compute the maximum offset (minimum offset if the stack does not
3206 grow downward) for each elimination pair. */
3209 update_eliminable_offsets (void)
3211 struct elim_table *ep;
3213 num_not_at_initial_offset = 0;
3214 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3216 ep->previous_offset = ep->offset;
3217 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3218 num_not_at_initial_offset++;
3222 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3223 replacement we currently believe is valid, mark it as not eliminable if X
3224 modifies DEST in any way other than by adding a constant integer to it.
3226 If DEST is the frame pointer, we do nothing because we assume that
3227 all assignments to the hard frame pointer are nonlocal gotos and are being
3228 done at a time when they are valid and do not disturb anything else.
3229 Some machines want to eliminate a fake argument pointer with either the
3230 frame or stack pointer. Assignments to the hard frame pointer must not
3231 prevent this elimination.
3233 Called via note_stores from reload before starting its passes to scan
3234 the insns of the function. */
3237 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3241 /* A SUBREG of a hard register here is just changing its mode. We should
3242 not see a SUBREG of an eliminable hard register, but check just in
3244 if (GET_CODE (dest) == SUBREG)
3245 dest = SUBREG_REG (dest);
3247 if (dest == hard_frame_pointer_rtx)
3250 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3251 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3252 && (GET_CODE (x) != SET
3253 || GET_CODE (SET_SRC (x)) != PLUS
3254 || XEXP (SET_SRC (x), 0) != dest
3255 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3257 reg_eliminate[i].can_eliminate_previous
3258 = reg_eliminate[i].can_eliminate = 0;
3263 /* Verify that the initial elimination offsets did not change since the
3264 last call to set_initial_elim_offsets. This is used to catch cases
3265 where something illegal happened during reload_as_needed that could
3266 cause incorrect code to be generated if we did not check for it. */
3269 verify_initial_elim_offsets (void)
3273 #ifdef ELIMINABLE_REGS
3274 struct elim_table *ep;
3276 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3278 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3279 if (t != ep->initial_offset)
3283 INITIAL_FRAME_POINTER_OFFSET (t);
3284 if (t != reg_eliminate[0].initial_offset)
3289 /* Reset all offsets on eliminable registers to their initial values. */
3292 set_initial_elim_offsets (void)
3294 struct elim_table *ep = reg_eliminate;
3296 #ifdef ELIMINABLE_REGS
3297 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3299 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3300 ep->previous_offset = ep->offset = ep->initial_offset;
3303 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3304 ep->previous_offset = ep->offset = ep->initial_offset;
3307 num_not_at_initial_offset = 0;
3310 /* Initialize the known label offsets.
3311 Set a known offset for each forced label to be at the initial offset
3312 of each elimination. We do this because we assume that all
3313 computed jumps occur from a location where each elimination is
3314 at its initial offset.
3315 For all other labels, show that we don't know the offsets. */
3318 set_initial_label_offsets (void)
3321 memset (offsets_known_at, 0, num_labels);
3323 for (x = forced_labels; x; x = XEXP (x, 1))
3325 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3328 /* Set all elimination offsets to the known values for the code label given
3332 set_offsets_for_label (rtx insn)
3335 int label_nr = CODE_LABEL_NUMBER (insn);
3336 struct elim_table *ep;
3338 num_not_at_initial_offset = 0;
3339 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3341 ep->offset = ep->previous_offset
3342 = offsets_at[label_nr - first_label_num][i];
3343 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3344 num_not_at_initial_offset++;
3348 /* See if anything that happened changes which eliminations are valid.
3349 For example, on the SPARC, whether or not the frame pointer can
3350 be eliminated can depend on what registers have been used. We need
3351 not check some conditions again (such as flag_omit_frame_pointer)
3352 since they can't have changed. */
3355 update_eliminables (HARD_REG_SET *pset)
3357 int previous_frame_pointer_needed = frame_pointer_needed;
3358 struct elim_table *ep;
3360 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3361 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3362 #ifdef ELIMINABLE_REGS
3363 || ! CAN_ELIMINATE (ep->from, ep->to)
3366 ep->can_eliminate = 0;
3368 /* Look for the case where we have discovered that we can't replace
3369 register A with register B and that means that we will now be
3370 trying to replace register A with register C. This means we can
3371 no longer replace register C with register B and we need to disable
3372 such an elimination, if it exists. This occurs often with A == ap,
3373 B == sp, and C == fp. */
3375 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3377 struct elim_table *op;
3380 if (! ep->can_eliminate && ep->can_eliminate_previous)
3382 /* Find the current elimination for ep->from, if there is a
3384 for (op = reg_eliminate;
3385 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3386 if (op->from == ep->from && op->can_eliminate)
3392 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3394 for (op = reg_eliminate;
3395 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3396 if (op->from == new_to && op->to == ep->to)
3397 op->can_eliminate = 0;
3401 /* See if any registers that we thought we could eliminate the previous
3402 time are no longer eliminable. If so, something has changed and we
3403 must spill the register. Also, recompute the number of eliminable
3404 registers and see if the frame pointer is needed; it is if there is
3405 no elimination of the frame pointer that we can perform. */
3407 frame_pointer_needed = 1;
3408 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3410 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3411 && ep->to != HARD_FRAME_POINTER_REGNUM)
3412 frame_pointer_needed = 0;
3414 if (! ep->can_eliminate && ep->can_eliminate_previous)
3416 ep->can_eliminate_previous = 0;
3417 SET_HARD_REG_BIT (*pset, ep->from);
3422 /* If we didn't need a frame pointer last time, but we do now, spill
3423 the hard frame pointer. */
3424 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3425 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3428 /* Initialize the table of registers to eliminate. */
3431 init_elim_table (void)
3433 struct elim_table *ep;
3434 #ifdef ELIMINABLE_REGS
3435 const struct elim_table_1 *ep1;
3439 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3441 /* Does this function require a frame pointer? */
3443 frame_pointer_needed = (! flag_omit_frame_pointer
3444 #ifdef EXIT_IGNORE_STACK
3445 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3446 and restore sp for alloca. So we can't eliminate
3447 the frame pointer in that case. At some point,
3448 we should improve this by emitting the
3449 sp-adjusting insns for this case. */
3450 || (current_function_calls_alloca
3451 && EXIT_IGNORE_STACK)
3453 || FRAME_POINTER_REQUIRED);
3457 #ifdef ELIMINABLE_REGS
3458 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3459 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3461 ep->from = ep1->from;
3463 ep->can_eliminate = ep->can_eliminate_previous
3464 = (CAN_ELIMINATE (ep->from, ep->to)
3465 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3468 reg_eliminate[0].from = reg_eliminate_1[0].from;
3469 reg_eliminate[0].to = reg_eliminate_1[0].to;
3470 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3471 = ! frame_pointer_needed;
3474 /* Count the number of eliminable registers and build the FROM and TO
3475 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3476 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3477 We depend on this. */
3478 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3480 num_eliminable += ep->can_eliminate;
3481 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3482 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3486 /* Kick all pseudos out of hard register REGNO.
3488 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3489 because we found we can't eliminate some register. In the case, no pseudos
3490 are allowed to be in the register, even if they are only in a block that
3491 doesn't require spill registers, unlike the case when we are spilling this
3492 hard reg to produce another spill register.
3494 Return nonzero if any pseudos needed to be kicked out. */
3497 spill_hard_reg (unsigned int regno, int cant_eliminate)
3503 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3504 regs_ever_live[regno] = 1;
3507 /* Spill every pseudo reg that was allocated to this reg
3508 or to something that overlaps this reg. */
3510 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3511 if (reg_renumber[i] >= 0
3512 && (unsigned int) reg_renumber[i] <= regno
3513 && ((unsigned int) reg_renumber[i]
3514 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3515 PSEUDO_REGNO_MODE (i))
3517 SET_REGNO_REG_SET (&spilled_pseudos, i);
3520 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3521 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3524 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3526 IOR_HARD_REG_SET (*set1, *set2);
3529 /* After find_reload_regs has been run for all insn that need reloads,
3530 and/or spill_hard_regs was called, this function is used to actually
3531 spill pseudo registers and try to reallocate them. It also sets up the
3532 spill_regs array for use by choose_reload_regs. */
3535 finish_spills (int global)
3537 struct insn_chain *chain;
3538 int something_changed = 0;
3541 /* Build the spill_regs array for the function. */
3542 /* If there are some registers still to eliminate and one of the spill regs
3543 wasn't ever used before, additional stack space may have to be
3544 allocated to store this register. Thus, we may have changed the offset
3545 between the stack and frame pointers, so mark that something has changed.
3547 One might think that we need only set VAL to 1 if this is a call-used
3548 register. However, the set of registers that must be saved by the
3549 prologue is not identical to the call-used set. For example, the
3550 register used by the call insn for the return PC is a call-used register,
3551 but must be saved by the prologue. */
3554 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3555 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3557 spill_reg_order[i] = n_spills;
3558 spill_regs[n_spills++] = i;
3559 if (num_eliminable && ! regs_ever_live[i])
3560 something_changed = 1;
3561 regs_ever_live[i] = 1;
3564 spill_reg_order[i] = -1;
3566 EXECUTE_IF_SET_IN_REG_SET
3567 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3569 /* Record the current hard register the pseudo is allocated to in
3570 pseudo_previous_regs so we avoid reallocating it to the same
3571 hard reg in a later pass. */
3572 if (reg_renumber[i] < 0)
3575 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3576 /* Mark it as no longer having a hard register home. */
3577 reg_renumber[i] = -1;
3578 /* We will need to scan everything again. */
3579 something_changed = 1;
3582 /* Retry global register allocation if possible. */
3585 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3586 /* For every insn that needs reloads, set the registers used as spill
3587 regs in pseudo_forbidden_regs for every pseudo live across the
3589 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3591 EXECUTE_IF_SET_IN_REG_SET
3592 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3594 ior_hard_reg_set (pseudo_forbidden_regs + i,
3595 &chain->used_spill_regs);
3597 EXECUTE_IF_SET_IN_REG_SET
3598 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3600 ior_hard_reg_set (pseudo_forbidden_regs + i,
3601 &chain->used_spill_regs);
3605 /* Retry allocating the spilled pseudos. For each reg, merge the
3606 various reg sets that indicate which hard regs can't be used,
3607 and call retry_global_alloc.
3608 We change spill_pseudos here to only contain pseudos that did not
3609 get a new hard register. */
3610 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3611 if (reg_old_renumber[i] != reg_renumber[i])
3613 HARD_REG_SET forbidden;
3614 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3615 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3616 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3617 retry_global_alloc (i, forbidden);
3618 if (reg_renumber[i] >= 0)
3619 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3623 /* Fix up the register information in the insn chain.
3624 This involves deleting those of the spilled pseudos which did not get
3625 a new hard register home from the live_{before,after} sets. */
3626 for (chain = reload_insn_chain; chain; chain = chain->next)
3628 HARD_REG_SET used_by_pseudos;
3629 HARD_REG_SET used_by_pseudos2;
3631 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3632 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3634 /* Mark any unallocated hard regs as available for spills. That
3635 makes inheritance work somewhat better. */
3636 if (chain->need_reload)
3638 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3639 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3640 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3642 /* Save the old value for the sanity test below. */
3643 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3645 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3646 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3647 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3648 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3650 /* Make sure we only enlarge the set. */
3651 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3657 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3658 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3660 int regno = reg_renumber[i];
3661 if (reg_old_renumber[i] == regno)
3664 alter_reg (i, reg_old_renumber[i]);
3665 reg_old_renumber[i] = regno;
3669 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3671 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3672 i, reg_renumber[i]);
3676 return something_changed;
3679 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3680 Also mark any hard registers used to store user variables as
3681 forbidden from being used for spill registers. */
3684 scan_paradoxical_subregs (rtx x)
3688 enum rtx_code code = GET_CODE (x);
3694 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3695 && REG_USERVAR_P (x))
3696 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3705 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3713 if (GET_CODE (SUBREG_REG (x)) == REG
3714 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3715 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3716 = GET_MODE_SIZE (GET_MODE (x));
3723 fmt = GET_RTX_FORMAT (code);
3724 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3727 scan_paradoxical_subregs (XEXP (x, i));
3728 else if (fmt[i] == 'E')
3731 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3732 scan_paradoxical_subregs (XVECEXP (x, i, j));
3737 /* Reload pseudo-registers into hard regs around each insn as needed.
3738 Additional register load insns are output before the insn that needs it
3739 and perhaps store insns after insns that modify the reloaded pseudo reg.
3741 reg_last_reload_reg and reg_reloaded_contents keep track of
3742 which registers are already available in reload registers.
3743 We update these for the reloads that we perform,
3744 as the insns are scanned. */
3747 reload_as_needed (int live_known)
3749 struct insn_chain *chain;
3750 #if defined (AUTO_INC_DEC)
3755 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3756 memset (spill_reg_store, 0, sizeof spill_reg_store);
3757 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3758 reg_has_output_reload = xmalloc (max_regno);
3759 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3761 set_initial_elim_offsets ();
3763 for (chain = reload_insn_chain; chain; chain = chain->next)
3766 rtx insn = chain->insn;
3767 rtx old_next = NEXT_INSN (insn);
3769 /* If we pass a label, copy the offsets from the label information
3770 into the current offsets of each elimination. */
3771 if (GET_CODE (insn) == CODE_LABEL)
3772 set_offsets_for_label (insn);
3774 else if (INSN_P (insn))
3776 rtx oldpat = copy_rtx (PATTERN (insn));
3778 /* If this is a USE and CLOBBER of a MEM, ensure that any
3779 references to eliminable registers have been removed. */
3781 if ((GET_CODE (PATTERN (insn)) == USE
3782 || GET_CODE (PATTERN (insn)) == CLOBBER)
3783 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3784 XEXP (XEXP (PATTERN (insn), 0), 0)
3785 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3786 GET_MODE (XEXP (PATTERN (insn), 0)),
3789 /* If we need to do register elimination processing, do so.
3790 This might delete the insn, in which case we are done. */
3791 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3793 eliminate_regs_in_insn (insn, 1);
3794 if (GET_CODE (insn) == NOTE)
3796 update_eliminable_offsets ();
3801 /* If need_elim is nonzero but need_reload is zero, one might think
3802 that we could simply set n_reloads to 0. However, find_reloads
3803 could have done some manipulation of the insn (such as swapping
3804 commutative operands), and these manipulations are lost during
3805 the first pass for every insn that needs register elimination.
3806 So the actions of find_reloads must be redone here. */
3808 if (! chain->need_elim && ! chain->need_reload
3809 && ! chain->need_operand_change)
3811 /* First find the pseudo regs that must be reloaded for this insn.
3812 This info is returned in the tables reload_... (see reload.h).
3813 Also modify the body of INSN by substituting RELOAD
3814 rtx's for those pseudo regs. */
3817 memset (reg_has_output_reload, 0, max_regno);
3818 CLEAR_HARD_REG_SET (reg_is_output_reload);
3820 find_reloads (insn, 1, spill_indirect_levels, live_known,
3826 rtx next = NEXT_INSN (insn);
3829 prev = PREV_INSN (insn);
3831 /* Now compute which reload regs to reload them into. Perhaps
3832 reusing reload regs from previous insns, or else output
3833 load insns to reload them. Maybe output store insns too.
3834 Record the choices of reload reg in reload_reg_rtx. */
3835 choose_reload_regs (chain);
3837 /* Merge any reloads that we didn't combine for fear of
3838 increasing the number of spill registers needed but now
3839 discover can be safely merged. */
3840 if (SMALL_REGISTER_CLASSES)
3841 merge_assigned_reloads (insn);
3843 /* Generate the insns to reload operands into or out of
3844 their reload regs. */
3845 emit_reload_insns (chain);
3847 /* Substitute the chosen reload regs from reload_reg_rtx
3848 into the insn's body (or perhaps into the bodies of other
3849 load and store insn that we just made for reloading
3850 and that we moved the structure into). */
3851 subst_reloads (insn);
3853 /* If this was an ASM, make sure that all the reload insns
3854 we have generated are valid. If not, give an error
3857 if (asm_noperands (PATTERN (insn)) >= 0)
3858 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3859 if (p != insn && INSN_P (p)
3860 && GET_CODE (PATTERN (p)) != USE
3861 && (recog_memoized (p) < 0
3862 || (extract_insn (p), ! constrain_operands (1))))
3864 error_for_asm (insn,
3865 "`asm' operand requires impossible reload");
3870 if (num_eliminable && chain->need_elim)
3871 update_eliminable_offsets ();
3873 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3874 is no longer validly lying around to save a future reload.
3875 Note that this does not detect pseudos that were reloaded
3876 for this insn in order to be stored in
3877 (obeying register constraints). That is correct; such reload
3878 registers ARE still valid. */
3879 note_stores (oldpat, forget_old_reloads_1, NULL);
3881 /* There may have been CLOBBER insns placed after INSN. So scan
3882 between INSN and NEXT and use them to forget old reloads. */
3883 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3884 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3885 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3888 /* Likewise for regs altered by auto-increment in this insn.
3889 REG_INC notes have been changed by reloading:
3890 find_reloads_address_1 records substitutions for them,
3891 which have been performed by subst_reloads above. */
3892 for (i = n_reloads - 1; i >= 0; i--)
3894 rtx in_reg = rld[i].in_reg;
3897 enum rtx_code code = GET_CODE (in_reg);
3898 /* PRE_INC / PRE_DEC will have the reload register ending up
3899 with the same value as the stack slot, but that doesn't
3900 hold true for POST_INC / POST_DEC. Either we have to
3901 convert the memory access to a true POST_INC / POST_DEC,
3902 or we can't use the reload register for inheritance. */
3903 if ((code == POST_INC || code == POST_DEC)
3904 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3905 REGNO (rld[i].reg_rtx))
3906 /* Make sure it is the inc/dec pseudo, and not
3907 some other (e.g. output operand) pseudo. */
3908 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3909 == REGNO (XEXP (in_reg, 0))))
3912 rtx reload_reg = rld[i].reg_rtx;
3913 enum machine_mode mode = GET_MODE (reload_reg);
3917 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3919 /* We really want to ignore REG_INC notes here, so
3920 use PATTERN (p) as argument to reg_set_p . */
3921 if (reg_set_p (reload_reg, PATTERN (p)))
3923 n = count_occurrences (PATTERN (p), reload_reg, 0);
3928 n = validate_replace_rtx (reload_reg,
3929 gen_rtx (code, mode,
3933 /* We must also verify that the constraints
3934 are met after the replacement. */
3937 n = constrain_operands (1);
3941 /* If the constraints were not met, then
3942 undo the replacement. */
3945 validate_replace_rtx (gen_rtx (code, mode,
3957 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3959 /* Mark this as having an output reload so that the
3960 REG_INC processing code below won't invalidate
3961 the reload for inheritance. */
3962 SET_HARD_REG_BIT (reg_is_output_reload,
3963 REGNO (reload_reg));
3964 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3967 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3970 else if ((code == PRE_INC || code == PRE_DEC)
3971 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3972 REGNO (rld[i].reg_rtx))
3973 /* Make sure it is the inc/dec pseudo, and not
3974 some other (e.g. output operand) pseudo. */
3975 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3976 == REGNO (XEXP (in_reg, 0))))
3978 SET_HARD_REG_BIT (reg_is_output_reload,
3979 REGNO (rld[i].reg_rtx));
3980 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3984 /* If a pseudo that got a hard register is auto-incremented,
3985 we must purge records of copying it into pseudos without
3987 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3988 if (REG_NOTE_KIND (x) == REG_INC)
3990 /* See if this pseudo reg was reloaded in this insn.
3991 If so, its last-reload info is still valid
3992 because it is based on this insn's reload. */
3993 for (i = 0; i < n_reloads; i++)
3994 if (rld[i].out == XEXP (x, 0))
3998 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4002 /* A reload reg's contents are unknown after a label. */
4003 if (GET_CODE (insn) == CODE_LABEL)
4004 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4006 /* Don't assume a reload reg is still good after a call insn
4007 if it is a call-used reg. */
4008 else if (GET_CODE (insn) == CALL_INSN)
4009 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4013 free (reg_last_reload_reg);
4014 free (reg_has_output_reload);
4017 /* Discard all record of any value reloaded from X,
4018 or reloaded in X from someplace else;
4019 unless X is an output reload reg of the current insn.
4021 X may be a hard reg (the reload reg)
4022 or it may be a pseudo reg that was reloaded from. */
4025 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4026 void *data ATTRIBUTE_UNUSED)
4031 /* note_stores does give us subregs of hard regs,
4032 subreg_regno_offset will abort if it is not a hard reg. */
4033 while (GET_CODE (x) == SUBREG)
4035 /* We ignore the subreg offset when calculating the regno,
4036 because we are using the entire underlying hard register
4041 if (GET_CODE (x) != REG)
4046 if (regno >= FIRST_PSEUDO_REGISTER)
4052 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4053 /* Storing into a spilled-reg invalidates its contents.
4054 This can happen if a block-local pseudo is allocated to that reg
4055 and it wasn't spilled because this block's total need is 0.
4056 Then some insn might have an optional reload and use this reg. */
4057 for (i = 0; i < nr; i++)
4058 /* But don't do this if the reg actually serves as an output
4059 reload reg in the current instruction. */
4061 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4063 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4064 spill_reg_store[regno + i] = 0;
4068 /* Since value of X has changed,
4069 forget any value previously copied from it. */
4072 /* But don't forget a copy if this is the output reload
4073 that establishes the copy's validity. */
4074 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4075 reg_last_reload_reg[regno + nr] = 0;
4078 /* The following HARD_REG_SETs indicate when each hard register is
4079 used for a reload of various parts of the current insn. */
4081 /* If reg is unavailable for all reloads. */
4082 static HARD_REG_SET reload_reg_unavailable;
4083 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4084 static HARD_REG_SET reload_reg_used;
4085 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4086 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4087 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4088 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4089 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4090 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4091 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4092 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4093 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4094 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4095 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4096 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4097 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4098 static HARD_REG_SET reload_reg_used_in_op_addr;
4099 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4100 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4101 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4102 static HARD_REG_SET reload_reg_used_in_insn;
4103 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4104 static HARD_REG_SET reload_reg_used_in_other_addr;
4106 /* If reg is in use as a reload reg for any sort of reload. */
4107 static HARD_REG_SET reload_reg_used_at_all;
4109 /* If reg is use as an inherited reload. We just mark the first register
4111 static HARD_REG_SET reload_reg_used_for_inherit;
4113 /* Records which hard regs are used in any way, either as explicit use or
4114 by being allocated to a pseudo during any point of the current insn. */
4115 static HARD_REG_SET reg_used_in_insn;
4117 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4118 TYPE. MODE is used to indicate how many consecutive regs are
4122 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4123 enum machine_mode mode)
4125 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4128 for (i = regno; i < nregs + regno; i++)
4133 SET_HARD_REG_BIT (reload_reg_used, i);
4136 case RELOAD_FOR_INPUT_ADDRESS:
4137 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4140 case RELOAD_FOR_INPADDR_ADDRESS:
4141 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4144 case RELOAD_FOR_OUTPUT_ADDRESS:
4145 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4148 case RELOAD_FOR_OUTADDR_ADDRESS:
4149 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4152 case RELOAD_FOR_OPERAND_ADDRESS:
4153 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4156 case RELOAD_FOR_OPADDR_ADDR:
4157 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4160 case RELOAD_FOR_OTHER_ADDRESS:
4161 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4164 case RELOAD_FOR_INPUT:
4165 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4168 case RELOAD_FOR_OUTPUT:
4169 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4172 case RELOAD_FOR_INSN:
4173 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4177 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4181 /* Similarly, but show REGNO is no longer in use for a reload. */
4184 clear_reload_reg_in_use (unsigned int regno, int opnum,
4185 enum reload_type type, enum machine_mode mode)
4187 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4188 unsigned int start_regno, end_regno, r;
4190 /* A complication is that for some reload types, inheritance might
4191 allow multiple reloads of the same types to share a reload register.
4192 We set check_opnum if we have to check only reloads with the same
4193 operand number, and check_any if we have to check all reloads. */
4194 int check_opnum = 0;
4196 HARD_REG_SET *used_in_set;
4201 used_in_set = &reload_reg_used;
4204 case RELOAD_FOR_INPUT_ADDRESS:
4205 used_in_set = &reload_reg_used_in_input_addr[opnum];
4208 case RELOAD_FOR_INPADDR_ADDRESS:
4210 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4213 case RELOAD_FOR_OUTPUT_ADDRESS:
4214 used_in_set = &reload_reg_used_in_output_addr[opnum];
4217 case RELOAD_FOR_OUTADDR_ADDRESS:
4219 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4222 case RELOAD_FOR_OPERAND_ADDRESS:
4223 used_in_set = &reload_reg_used_in_op_addr;
4226 case RELOAD_FOR_OPADDR_ADDR:
4228 used_in_set = &reload_reg_used_in_op_addr_reload;
4231 case RELOAD_FOR_OTHER_ADDRESS:
4232 used_in_set = &reload_reg_used_in_other_addr;
4236 case RELOAD_FOR_INPUT:
4237 used_in_set = &reload_reg_used_in_input[opnum];
4240 case RELOAD_FOR_OUTPUT:
4241 used_in_set = &reload_reg_used_in_output[opnum];
4244 case RELOAD_FOR_INSN:
4245 used_in_set = &reload_reg_used_in_insn;
4250 /* We resolve conflicts with remaining reloads of the same type by
4251 excluding the intervals of reload registers by them from the
4252 interval of freed reload registers. Since we only keep track of
4253 one set of interval bounds, we might have to exclude somewhat
4254 more than what would be necessary if we used a HARD_REG_SET here.
4255 But this should only happen very infrequently, so there should
4256 be no reason to worry about it. */
4258 start_regno = regno;
4259 end_regno = regno + nregs;
4260 if (check_opnum || check_any)
4262 for (i = n_reloads - 1; i >= 0; i--)
4264 if (rld[i].when_needed == type
4265 && (check_any || rld[i].opnum == opnum)
4268 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4269 unsigned int conflict_end
4271 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4273 /* If there is an overlap with the first to-be-freed register,
4274 adjust the interval start. */
4275 if (conflict_start <= start_regno && conflict_end > start_regno)
4276 start_regno = conflict_end;
4277 /* Otherwise, if there is a conflict with one of the other
4278 to-be-freed registers, adjust the interval end. */
4279 if (conflict_start > start_regno && conflict_start < end_regno)
4280 end_regno = conflict_start;
4285 for (r = start_regno; r < end_regno; r++)
4286 CLEAR_HARD_REG_BIT (*used_in_set, r);
4289 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4290 specified by OPNUM and TYPE. */
4293 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4297 /* In use for a RELOAD_OTHER means it's not available for anything. */
4298 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4299 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4305 /* In use for anything means we can't use it for RELOAD_OTHER. */
4306 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4307 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4308 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4311 for (i = 0; i < reload_n_operands; i++)
4312 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4313 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4314 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4315 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4316 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4317 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4322 case RELOAD_FOR_INPUT:
4323 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4324 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4327 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4330 /* If it is used for some other input, can't use it. */
4331 for (i = 0; i < reload_n_operands; i++)
4332 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4335 /* If it is used in a later operand's address, can't use it. */
4336 for (i = opnum + 1; i < reload_n_operands; i++)
4337 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4338 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4343 case RELOAD_FOR_INPUT_ADDRESS:
4344 /* Can't use a register if it is used for an input address for this
4345 operand or used as an input in an earlier one. */
4346 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4347 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4350 for (i = 0; i < opnum; i++)
4351 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4356 case RELOAD_FOR_INPADDR_ADDRESS:
4357 /* Can't use a register if it is used for an input address
4358 for this operand or used as an input in an earlier
4360 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4363 for (i = 0; i < opnum; i++)
4364 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4369 case RELOAD_FOR_OUTPUT_ADDRESS:
4370 /* Can't use a register if it is used for an output address for this
4371 operand or used as an output in this or a later operand. Note
4372 that multiple output operands are emitted in reverse order, so
4373 the conflicting ones are those with lower indices. */
4374 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4377 for (i = 0; i <= opnum; i++)
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4383 case RELOAD_FOR_OUTADDR_ADDRESS:
4384 /* Can't use a register if it is used for an output address
4385 for this operand or used as an output in this or a
4386 later operand. Note that multiple output operands are
4387 emitted in reverse order, so the conflicting ones are
4388 those with lower indices. */
4389 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4392 for (i = 0; i <= opnum; i++)
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4398 case RELOAD_FOR_OPERAND_ADDRESS:
4399 for (i = 0; i < reload_n_operands; i++)
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4403 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4404 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4406 case RELOAD_FOR_OPADDR_ADDR:
4407 for (i = 0; i < reload_n_operands; i++)
4408 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4411 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4413 case RELOAD_FOR_OUTPUT:
4414 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4415 outputs, or an operand address for this or an earlier output.
4416 Note that multiple output operands are emitted in reverse order,
4417 so the conflicting ones are those with higher indices. */
4418 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4421 for (i = 0; i < reload_n_operands; i++)
4422 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4425 for (i = opnum; i < reload_n_operands; i++)
4426 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4427 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4432 case RELOAD_FOR_INSN:
4433 for (i = 0; i < reload_n_operands; i++)
4434 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4435 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4438 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4439 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4441 case RELOAD_FOR_OTHER_ADDRESS:
4442 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4447 /* Return 1 if the value in reload reg REGNO, as used by a reload
4448 needed for the part of the insn specified by OPNUM and TYPE,
4449 is still available in REGNO at the end of the insn.
4451 We can assume that the reload reg was already tested for availability
4452 at the time it is needed, and we should not check this again,
4453 in case the reg has already been marked in use. */
4456 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4463 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4464 its value must reach the end. */
4467 /* If this use is for part of the insn,
4468 its value reaches if no subsequent part uses the same register.
4469 Just like the above function, don't try to do this with lots
4472 case RELOAD_FOR_OTHER_ADDRESS:
4473 /* Here we check for everything else, since these don't conflict
4474 with anything else and everything comes later. */
4476 for (i = 0; i < reload_n_operands; i++)
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4478 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4479 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4480 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4481 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4482 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4485 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4486 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4487 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4489 case RELOAD_FOR_INPUT_ADDRESS:
4490 case RELOAD_FOR_INPADDR_ADDRESS:
4491 /* Similar, except that we check only for this and subsequent inputs
4492 and the address of only subsequent inputs and we do not need
4493 to check for RELOAD_OTHER objects since they are known not to
4496 for (i = opnum; i < reload_n_operands; i++)
4497 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4500 for (i = opnum + 1; i < reload_n_operands; i++)
4501 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4502 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4505 for (i = 0; i < reload_n_operands; i++)
4506 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4507 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4508 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4511 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4514 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4515 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4516 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4518 case RELOAD_FOR_INPUT:
4519 /* Similar to input address, except we start at the next operand for
4520 both input and input address and we do not check for
4521 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4524 for (i = opnum + 1; i < reload_n_operands; i++)
4525 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4530 /* ... fall through ... */
4532 case RELOAD_FOR_OPERAND_ADDRESS:
4533 /* Check outputs and their addresses. */
4535 for (i = 0; i < reload_n_operands; i++)
4536 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4537 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4538 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4541 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4543 case RELOAD_FOR_OPADDR_ADDR:
4544 for (i = 0; i < reload_n_operands; i++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4546 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4547 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4550 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4551 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4552 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4554 case RELOAD_FOR_INSN:
4555 /* These conflict with other outputs with RELOAD_OTHER. So
4556 we need only check for output addresses. */
4558 opnum = reload_n_operands;
4560 /* ... fall through ... */
4562 case RELOAD_FOR_OUTPUT:
4563 case RELOAD_FOR_OUTPUT_ADDRESS:
4564 case RELOAD_FOR_OUTADDR_ADDRESS:
4565 /* We already know these can't conflict with a later output. So the
4566 only thing to check are later output addresses.
4567 Note that multiple output operands are emitted in reverse order,
4568 so the conflicting ones are those with lower indices. */
4569 for (i = 0; i < opnum; i++)
4570 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4580 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4583 This function uses the same algorithm as reload_reg_free_p above. */
4586 reloads_conflict (int r1, int r2)
4588 enum reload_type r1_type = rld[r1].when_needed;
4589 enum reload_type r2_type = rld[r2].when_needed;
4590 int r1_opnum = rld[r1].opnum;
4591 int r2_opnum = rld[r2].opnum;
4593 /* RELOAD_OTHER conflicts with everything. */
4594 if (r2_type == RELOAD_OTHER)
4597 /* Otherwise, check conflicts differently for each type. */
4601 case RELOAD_FOR_INPUT:
4602 return (r2_type == RELOAD_FOR_INSN
4603 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4604 || r2_type == RELOAD_FOR_OPADDR_ADDR
4605 || r2_type == RELOAD_FOR_INPUT
4606 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4607 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4608 && r2_opnum > r1_opnum));
4610 case RELOAD_FOR_INPUT_ADDRESS:
4611 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4612 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4614 case RELOAD_FOR_INPADDR_ADDRESS:
4615 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4616 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4618 case RELOAD_FOR_OUTPUT_ADDRESS:
4619 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4620 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4622 case RELOAD_FOR_OUTADDR_ADDRESS:
4623 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4624 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4626 case RELOAD_FOR_OPERAND_ADDRESS:
4627 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4628 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4630 case RELOAD_FOR_OPADDR_ADDR:
4631 return (r2_type == RELOAD_FOR_INPUT
4632 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4634 case RELOAD_FOR_OUTPUT:
4635 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4636 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4637 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4638 && r2_opnum >= r1_opnum));
4640 case RELOAD_FOR_INSN:
4641 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4642 || r2_type == RELOAD_FOR_INSN
4643 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4645 case RELOAD_FOR_OTHER_ADDRESS:
4646 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4656 /* Indexed by reload number, 1 if incoming value
4657 inherited from previous insns. */
4658 char reload_inherited[MAX_RELOADS];
4660 /* For an inherited reload, this is the insn the reload was inherited from,
4661 if we know it. Otherwise, this is 0. */
4662 rtx reload_inheritance_insn[MAX_RELOADS];
4664 /* If nonzero, this is a place to get the value of the reload,
4665 rather than using reload_in. */
4666 rtx reload_override_in[MAX_RELOADS];
4668 /* For each reload, the hard register number of the register used,
4669 or -1 if we did not need a register for this reload. */
4670 int reload_spill_index[MAX_RELOADS];
4672 /* Subroutine of free_for_value_p, used to check a single register.
4673 START_REGNO is the starting regno of the full reload register
4674 (possibly comprising multiple hard registers) that we are considering. */
4677 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4678 enum reload_type type, rtx value, rtx out,
4679 int reloadnum, int ignore_address_reloads)
4682 /* Set if we see an input reload that must not share its reload register
4683 with any new earlyclobber, but might otherwise share the reload
4684 register with an output or input-output reload. */
4685 int check_earlyclobber = 0;
4689 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4692 if (out == const0_rtx)
4698 /* We use some pseudo 'time' value to check if the lifetimes of the
4699 new register use would overlap with the one of a previous reload
4700 that is not read-only or uses a different value.
4701 The 'time' used doesn't have to be linear in any shape or form, just
4703 Some reload types use different 'buckets' for each operand.
4704 So there are MAX_RECOG_OPERANDS different time values for each
4706 We compute TIME1 as the time when the register for the prospective
4707 new reload ceases to be live, and TIME2 for each existing
4708 reload as the time when that the reload register of that reload
4710 Where there is little to be gained by exact lifetime calculations,
4711 we just make conservative assumptions, i.e. a longer lifetime;
4712 this is done in the 'default:' cases. */
4715 case RELOAD_FOR_OTHER_ADDRESS:
4716 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4717 time1 = copy ? 0 : 1;
4720 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4722 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4723 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4724 respectively, to the time values for these, we get distinct time
4725 values. To get distinct time values for each operand, we have to
4726 multiply opnum by at least three. We round that up to four because
4727 multiply by four is often cheaper. */
4728 case RELOAD_FOR_INPADDR_ADDRESS:
4729 time1 = opnum * 4 + 2;
4731 case RELOAD_FOR_INPUT_ADDRESS:
4732 time1 = opnum * 4 + 3;
4734 case RELOAD_FOR_INPUT:
4735 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4736 executes (inclusive). */
4737 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4739 case RELOAD_FOR_OPADDR_ADDR:
4741 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4742 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4744 case RELOAD_FOR_OPERAND_ADDRESS:
4745 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4747 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4749 case RELOAD_FOR_OUTADDR_ADDRESS:
4750 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4752 case RELOAD_FOR_OUTPUT_ADDRESS:
4753 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4756 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4759 for (i = 0; i < n_reloads; i++)
4761 rtx reg = rld[i].reg_rtx;
4762 if (reg && GET_CODE (reg) == REG
4763 && ((unsigned) regno - true_regnum (reg)
4764 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4767 rtx other_input = rld[i].in;
4769 /* If the other reload loads the same input value, that
4770 will not cause a conflict only if it's loading it into
4771 the same register. */
4772 if (true_regnum (reg) != start_regno)
4773 other_input = NULL_RTX;
4774 if (! other_input || ! rtx_equal_p (other_input, value)
4775 || rld[i].out || out)
4778 switch (rld[i].when_needed)
4780 case RELOAD_FOR_OTHER_ADDRESS:
4783 case RELOAD_FOR_INPADDR_ADDRESS:
4784 /* find_reloads makes sure that a
4785 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4786 by at most one - the first -
4787 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4788 address reload is inherited, the address address reload
4789 goes away, so we can ignore this conflict. */
4790 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4791 && ignore_address_reloads
4792 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4793 Then the address address is still needed to store
4794 back the new address. */
4795 && ! rld[reloadnum].out)
4797 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4798 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4800 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4801 && ignore_address_reloads
4802 /* Unless we are reloading an auto_inc expression. */
4803 && ! rld[reloadnum].out)
4805 time2 = rld[i].opnum * 4 + 2;
4807 case RELOAD_FOR_INPUT_ADDRESS:
4808 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4809 && ignore_address_reloads
4810 && ! rld[reloadnum].out)
4812 time2 = rld[i].opnum * 4 + 3;
4814 case RELOAD_FOR_INPUT:
4815 time2 = rld[i].opnum * 4 + 4;
4816 check_earlyclobber = 1;
4818 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4819 == MAX_RECOG_OPERAND * 4 */
4820 case RELOAD_FOR_OPADDR_ADDR:
4821 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4822 && ignore_address_reloads
4823 && ! rld[reloadnum].out)
4825 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4827 case RELOAD_FOR_OPERAND_ADDRESS:
4828 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4829 check_earlyclobber = 1;
4831 case RELOAD_FOR_INSN:
4832 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4834 case RELOAD_FOR_OUTPUT:
4835 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4836 instruction is executed. */
4837 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4839 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4840 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4842 case RELOAD_FOR_OUTADDR_ADDRESS:
4843 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4844 && ignore_address_reloads
4845 && ! rld[reloadnum].out)
4847 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4849 case RELOAD_FOR_OUTPUT_ADDRESS:
4850 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4853 /* If there is no conflict in the input part, handle this
4854 like an output reload. */
4855 if (! rld[i].in || rtx_equal_p (other_input, value))
4857 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4858 /* Earlyclobbered outputs must conflict with inputs. */
4859 if (earlyclobber_operand_p (rld[i].out))
4860 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4865 /* RELOAD_OTHER might be live beyond instruction execution,
4866 but this is not obvious when we set time2 = 1. So check
4867 here if there might be a problem with the new reload
4868 clobbering the register used by the RELOAD_OTHER. */
4876 && (! rld[i].in || rld[i].out
4877 || ! rtx_equal_p (other_input, value)))
4878 || (out && rld[reloadnum].out_reg
4879 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4885 /* Earlyclobbered outputs must conflict with inputs. */
4886 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4892 /* Return 1 if the value in reload reg REGNO, as used by a reload
4893 needed for the part of the insn specified by OPNUM and TYPE,
4894 may be used to load VALUE into it.
4896 MODE is the mode in which the register is used, this is needed to
4897 determine how many hard regs to test.
4899 Other read-only reloads with the same value do not conflict
4900 unless OUT is nonzero and these other reloads have to live while
4901 output reloads live.
4902 If OUT is CONST0_RTX, this is a special case: it means that the
4903 test should not be for using register REGNO as reload register, but
4904 for copying from register REGNO into the reload register.
4906 RELOADNUM is the number of the reload we want to load this value for;
4907 a reload does not conflict with itself.
4909 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4910 reloads that load an address for the very reload we are considering.
4912 The caller has to make sure that there is no conflict with the return
4916 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4917 enum reload_type type, rtx value, rtx out, int reloadnum,
4918 int ignore_address_reloads)
4920 int nregs = HARD_REGNO_NREGS (regno, mode);
4922 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4923 value, out, reloadnum,
4924 ignore_address_reloads))
4929 /* Determine whether the reload reg X overlaps any rtx'es used for
4930 overriding inheritance. Return nonzero if so. */
4933 conflicts_with_override (rtx x)
4936 for (i = 0; i < n_reloads; i++)
4937 if (reload_override_in[i]
4938 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4943 /* Give an error message saying we failed to find a reload for INSN,
4944 and clear out reload R. */
4946 failed_reload (rtx insn, int r)
4948 if (asm_noperands (PATTERN (insn)) < 0)
4949 /* It's the compiler's fault. */
4950 fatal_insn ("could not find a spill register", insn);
4952 /* It's the user's fault; the operand's mode and constraint
4953 don't match. Disable this reload so we don't crash in final. */
4954 error_for_asm (insn,
4955 "`asm' operand constraint incompatible with operand size");
4959 rld[r].optional = 1;
4960 rld[r].secondary_p = 1;
4963 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4964 for reload R. If it's valid, get an rtx for it. Return nonzero if
4967 set_reload_reg (int i, int r)
4970 rtx reg = spill_reg_rtx[i];
4972 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4973 spill_reg_rtx[i] = reg
4974 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4976 regno = true_regnum (reg);
4978 /* Detect when the reload reg can't hold the reload mode.
4979 This used to be one `if', but Sequent compiler can't handle that. */
4980 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4982 enum machine_mode test_mode = VOIDmode;
4984 test_mode = GET_MODE (rld[r].in);
4985 /* If rld[r].in has VOIDmode, it means we will load it
4986 in whatever mode the reload reg has: to wit, rld[r].mode.
4987 We have already tested that for validity. */
4988 /* Aside from that, we need to test that the expressions
4989 to reload from or into have modes which are valid for this
4990 reload register. Otherwise the reload insns would be invalid. */
4991 if (! (rld[r].in != 0 && test_mode != VOIDmode
4992 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4993 if (! (rld[r].out != 0
4994 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4996 /* The reg is OK. */
4999 /* Mark as in use for this insn the reload regs we use
5001 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5002 rld[r].when_needed, rld[r].mode);
5004 rld[r].reg_rtx = reg;
5005 reload_spill_index[r] = spill_regs[i];
5012 /* Find a spill register to use as a reload register for reload R.
5013 LAST_RELOAD is nonzero if this is the last reload for the insn being
5016 Set rld[R].reg_rtx to the register allocated.
5018 We return 1 if successful, or 0 if we couldn't find a spill reg and
5019 we didn't change anything. */
5022 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5027 /* If we put this reload ahead, thinking it is a group,
5028 then insist on finding a group. Otherwise we can grab a
5029 reg that some other reload needs.
5030 (That can happen when we have a 68000 DATA_OR_FP_REG
5031 which is a group of data regs or one fp reg.)
5032 We need not be so restrictive if there are no more reloads
5035 ??? Really it would be nicer to have smarter handling
5036 for that kind of reg class, where a problem like this is normal.
5037 Perhaps those classes should be avoided for reloading
5038 by use of more alternatives. */
5040 int force_group = rld[r].nregs > 1 && ! last_reload;
5042 /* If we want a single register and haven't yet found one,
5043 take any reg in the right class and not in use.
5044 If we want a consecutive group, here is where we look for it.
5046 We use two passes so we can first look for reload regs to
5047 reuse, which are already in use for other reloads in this insn,
5048 and only then use additional registers.
5049 I think that maximizing reuse is needed to make sure we don't
5050 run out of reload regs. Suppose we have three reloads, and
5051 reloads A and B can share regs. These need two regs.
5052 Suppose A and B are given different regs.
5053 That leaves none for C. */
5054 for (pass = 0; pass < 2; pass++)
5056 /* I is the index in spill_regs.
5057 We advance it round-robin between insns to use all spill regs
5058 equally, so that inherited reloads have a chance
5059 of leapfrogging each other. */
5063 for (count = 0; count < n_spills; count++)
5065 int class = (int) rld[r].class;
5071 regnum = spill_regs[i];
5073 if ((reload_reg_free_p (regnum, rld[r].opnum,
5076 /* We check reload_reg_used to make sure we
5077 don't clobber the return register. */
5078 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5079 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5080 rld[r].when_needed, rld[r].in,
5082 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5083 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5084 /* Look first for regs to share, then for unshared. But
5085 don't share regs used for inherited reloads; they are
5086 the ones we want to preserve. */
5088 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5090 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5093 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5094 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5095 (on 68000) got us two FP regs. If NR is 1,
5096 we would reject both of them. */
5099 /* If we need only one reg, we have already won. */
5102 /* But reject a single reg if we demand a group. */
5107 /* Otherwise check that as many consecutive regs as we need
5108 are available here. */
5111 int regno = regnum + nr - 1;
5112 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5113 && spill_reg_order[regno] >= 0
5114 && reload_reg_free_p (regno, rld[r].opnum,
5115 rld[r].when_needed)))
5124 /* If we found something on pass 1, omit pass 2. */
5125 if (count < n_spills)
5129 /* We should have found a spill register by now. */
5130 if (count >= n_spills)
5133 /* I is the index in SPILL_REG_RTX of the reload register we are to
5134 allocate. Get an rtx for it and find its register number. */
5136 return set_reload_reg (i, r);
5139 /* Initialize all the tables needed to allocate reload registers.
5140 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5141 is the array we use to restore the reg_rtx field for every reload. */
5144 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5148 for (i = 0; i < n_reloads; i++)
5149 rld[i].reg_rtx = save_reload_reg_rtx[i];
5151 memset (reload_inherited, 0, MAX_RELOADS);
5152 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5153 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5155 CLEAR_HARD_REG_SET (reload_reg_used);
5156 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5157 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5158 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5159 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5160 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5162 CLEAR_HARD_REG_SET (reg_used_in_insn);
5165 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5166 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5167 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5168 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5169 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5170 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5173 for (i = 0; i < reload_n_operands; i++)
5175 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5176 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5177 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5178 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5179 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5180 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5183 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5185 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5187 for (i = 0; i < n_reloads; i++)
5188 /* If we have already decided to use a certain register,
5189 don't use it in another way. */
5191 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5192 rld[i].when_needed, rld[i].mode);
5195 /* Assign hard reg targets for the pseudo-registers we must reload
5196 into hard regs for this insn.
5197 Also output the instructions to copy them in and out of the hard regs.
5199 For machines with register classes, we are responsible for
5200 finding a reload reg in the proper class. */
5203 choose_reload_regs (struct insn_chain *chain)
5205 rtx insn = chain->insn;
5207 unsigned int max_group_size = 1;
5208 enum reg_class group_class = NO_REGS;
5209 int pass, win, inheritance;
5211 rtx save_reload_reg_rtx[MAX_RELOADS];
5213 /* In order to be certain of getting the registers we need,
5214 we must sort the reloads into order of increasing register class.
5215 Then our grabbing of reload registers will parallel the process
5216 that provided the reload registers.
5218 Also note whether any of the reloads wants a consecutive group of regs.
5219 If so, record the maximum size of the group desired and what
5220 register class contains all the groups needed by this insn. */
5222 for (j = 0; j < n_reloads; j++)
5224 reload_order[j] = j;
5225 reload_spill_index[j] = -1;
5227 if (rld[j].nregs > 1)
5229 max_group_size = MAX (rld[j].nregs, max_group_size);
5231 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5234 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5238 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5240 /* If -O, try first with inheritance, then turning it off.
5241 If not -O, don't do inheritance.
5242 Using inheritance when not optimizing leads to paradoxes
5243 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5244 because one side of the comparison might be inherited. */
5246 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5248 choose_reload_regs_init (chain, save_reload_reg_rtx);
5250 /* Process the reloads in order of preference just found.
5251 Beyond this point, subregs can be found in reload_reg_rtx.
5253 This used to look for an existing reloaded home for all of the
5254 reloads, and only then perform any new reloads. But that could lose
5255 if the reloads were done out of reg-class order because a later
5256 reload with a looser constraint might have an old home in a register
5257 needed by an earlier reload with a tighter constraint.
5259 To solve this, we make two passes over the reloads, in the order
5260 described above. In the first pass we try to inherit a reload
5261 from a previous insn. If there is a later reload that needs a
5262 class that is a proper subset of the class being processed, we must
5263 also allocate a spill register during the first pass.
5265 Then make a second pass over the reloads to allocate any reloads
5266 that haven't been given registers yet. */
5268 for (j = 0; j < n_reloads; j++)
5270 int r = reload_order[j];
5271 rtx search_equiv = NULL_RTX;
5273 /* Ignore reloads that got marked inoperative. */
5274 if (rld[r].out == 0 && rld[r].in == 0
5275 && ! rld[r].secondary_p)
5278 /* If find_reloads chose to use reload_in or reload_out as a reload
5279 register, we don't need to chose one. Otherwise, try even if it
5280 found one since we might save an insn if we find the value lying
5282 Try also when reload_in is a pseudo without a hard reg. */
5283 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5284 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5285 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5286 && GET_CODE (rld[r].in) != MEM
5287 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5290 #if 0 /* No longer needed for correct operation.
5291 It might give better code, or might not; worth an experiment? */
5292 /* If this is an optional reload, we can't inherit from earlier insns
5293 until we are sure that any non-optional reloads have been allocated.
5294 The following code takes advantage of the fact that optional reloads
5295 are at the end of reload_order. */
5296 if (rld[r].optional != 0)
5297 for (i = 0; i < j; i++)
5298 if ((rld[reload_order[i]].out != 0
5299 || rld[reload_order[i]].in != 0
5300 || rld[reload_order[i]].secondary_p)
5301 && ! rld[reload_order[i]].optional
5302 && rld[reload_order[i]].reg_rtx == 0)
5303 allocate_reload_reg (chain, reload_order[i], 0);
5306 /* First see if this pseudo is already available as reloaded
5307 for a previous insn. We cannot try to inherit for reloads
5308 that are smaller than the maximum number of registers needed
5309 for groups unless the register we would allocate cannot be used
5312 We could check here to see if this is a secondary reload for
5313 an object that is already in a register of the desired class.
5314 This would avoid the need for the secondary reload register.
5315 But this is complex because we can't easily determine what
5316 objects might want to be loaded via this reload. So let a
5317 register be allocated here. In `emit_reload_insns' we suppress
5318 one of the loads in the case described above. */
5324 enum machine_mode mode = VOIDmode;
5328 else if (GET_CODE (rld[r].in) == REG)
5330 regno = REGNO (rld[r].in);
5331 mode = GET_MODE (rld[r].in);
5333 else if (GET_CODE (rld[r].in_reg) == REG)
5335 regno = REGNO (rld[r].in_reg);
5336 mode = GET_MODE (rld[r].in_reg);
5338 else if (GET_CODE (rld[r].in_reg) == SUBREG
5339 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5341 byte = SUBREG_BYTE (rld[r].in_reg);
5342 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5343 if (regno < FIRST_PSEUDO_REGISTER)
5344 regno = subreg_regno (rld[r].in_reg);
5345 mode = GET_MODE (rld[r].in_reg);
5348 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5349 || GET_CODE (rld[r].in_reg) == PRE_DEC
5350 || GET_CODE (rld[r].in_reg) == POST_INC
5351 || GET_CODE (rld[r].in_reg) == POST_DEC)
5352 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5354 regno = REGNO (XEXP (rld[r].in_reg, 0));
5355 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5356 rld[r].out = rld[r].in;
5360 /* This won't work, since REGNO can be a pseudo reg number.
5361 Also, it takes much more hair to keep track of all the things
5362 that can invalidate an inherited reload of part of a pseudoreg. */
5363 else if (GET_CODE (rld[r].in) == SUBREG
5364 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5365 regno = subreg_regno (rld[r].in);
5368 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5370 enum reg_class class = rld[r].class, last_class;
5371 rtx last_reg = reg_last_reload_reg[regno];
5372 enum machine_mode need_mode;
5374 i = REGNO (last_reg);
5375 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5376 last_class = REGNO_REG_CLASS (i);
5382 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5383 GET_MODE_CLASS (mode));
5386 #ifdef CANNOT_CHANGE_MODE_CLASS
5387 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5391 (GET_MODE_SIZE (GET_MODE (last_reg))
5392 >= GET_MODE_SIZE (need_mode))
5393 #ifdef CANNOT_CHANGE_MODE_CLASS
5396 && reg_reloaded_contents[i] == regno
5397 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5398 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5399 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5400 /* Even if we can't use this register as a reload
5401 register, we might use it for reload_override_in,
5402 if copying it to the desired class is cheap
5404 || ((REGISTER_MOVE_COST (mode, last_class, class)
5405 < MEMORY_MOVE_COST (mode, class, 1))
5406 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5407 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5411 #ifdef SECONDARY_MEMORY_NEEDED
5412 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5417 && (rld[r].nregs == max_group_size
5418 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5420 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5421 rld[r].when_needed, rld[r].in,
5424 /* If a group is needed, verify that all the subsequent
5425 registers still have their values intact. */
5426 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5429 for (k = 1; k < nr; k++)
5430 if (reg_reloaded_contents[i + k] != regno
5431 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5439 last_reg = (GET_MODE (last_reg) == mode
5440 ? last_reg : gen_rtx_REG (mode, i));
5443 for (k = 0; k < nr; k++)
5444 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5447 /* We found a register that contains the
5448 value we need. If this register is the
5449 same as an `earlyclobber' operand of the
5450 current insn, just mark it as a place to
5451 reload from since we can't use it as the
5452 reload register itself. */
5454 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5455 if (reg_overlap_mentioned_for_reload_p
5456 (reg_last_reload_reg[regno],
5457 reload_earlyclobbers[i1]))
5460 if (i1 != n_earlyclobbers
5461 || ! (free_for_value_p (i, rld[r].mode,
5463 rld[r].when_needed, rld[r].in,
5465 /* Don't use it if we'd clobber a pseudo reg. */
5466 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5468 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5469 /* Don't clobber the frame pointer. */
5470 || (i == HARD_FRAME_POINTER_REGNUM
5471 && frame_pointer_needed
5473 /* Don't really use the inherited spill reg
5474 if we need it wider than we've got it. */
5475 || (GET_MODE_SIZE (rld[r].mode)
5476 > GET_MODE_SIZE (mode))
5479 /* If find_reloads chose reload_out as reload
5480 register, stay with it - that leaves the
5481 inherited register for subsequent reloads. */
5482 || (rld[r].out && rld[r].reg_rtx
5483 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5485 if (! rld[r].optional)
5487 reload_override_in[r] = last_reg;
5488 reload_inheritance_insn[r]
5489 = reg_reloaded_insn[i];
5495 /* We can use this as a reload reg. */
5496 /* Mark the register as in use for this part of
5498 mark_reload_reg_in_use (i,
5502 rld[r].reg_rtx = last_reg;
5503 reload_inherited[r] = 1;
5504 reload_inheritance_insn[r]
5505 = reg_reloaded_insn[i];
5506 reload_spill_index[r] = i;
5507 for (k = 0; k < nr; k++)
5508 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5516 /* Here's another way to see if the value is already lying around. */
5519 && ! reload_inherited[r]
5521 && (CONSTANT_P (rld[r].in)
5522 || GET_CODE (rld[r].in) == PLUS
5523 || GET_CODE (rld[r].in) == REG
5524 || GET_CODE (rld[r].in) == MEM)
5525 && (rld[r].nregs == max_group_size
5526 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5527 search_equiv = rld[r].in;
5528 /* If this is an output reload from a simple move insn, look
5529 if an equivalence for the input is available. */
5530 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5532 rtx set = single_set (insn);
5535 && rtx_equal_p (rld[r].out, SET_DEST (set))
5536 && CONSTANT_P (SET_SRC (set)))
5537 search_equiv = SET_SRC (set);
5543 = find_equiv_reg (search_equiv, insn, rld[r].class,
5544 -1, NULL, 0, rld[r].mode);
5549 if (GET_CODE (equiv) == REG)
5550 regno = REGNO (equiv);
5551 else if (GET_CODE (equiv) == SUBREG)
5553 /* This must be a SUBREG of a hard register.
5554 Make a new REG since this might be used in an
5555 address and not all machines support SUBREGs
5557 regno = subreg_regno (equiv);
5558 equiv = gen_rtx_REG (rld[r].mode, regno);
5564 /* If we found a spill reg, reject it unless it is free
5565 and of the desired class. */
5569 int bad_for_class = 0;
5570 int max_regno = regno + rld[r].nregs;
5572 for (i = regno; i < max_regno; i++)
5574 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5576 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5581 && ! free_for_value_p (regno, rld[r].mode,
5582 rld[r].opnum, rld[r].when_needed,
5583 rld[r].in, rld[r].out, r, 1))
5588 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5591 /* We found a register that contains the value we need.
5592 If this register is the same as an `earlyclobber' operand
5593 of the current insn, just mark it as a place to reload from
5594 since we can't use it as the reload register itself. */
5597 for (i = 0; i < n_earlyclobbers; i++)
5598 if (reg_overlap_mentioned_for_reload_p (equiv,
5599 reload_earlyclobbers[i]))
5601 if (! rld[r].optional)
5602 reload_override_in[r] = equiv;
5607 /* If the equiv register we have found is explicitly clobbered
5608 in the current insn, it depends on the reload type if we
5609 can use it, use it for reload_override_in, or not at all.
5610 In particular, we then can't use EQUIV for a
5611 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5615 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5616 switch (rld[r].when_needed)
5618 case RELOAD_FOR_OTHER_ADDRESS:
5619 case RELOAD_FOR_INPADDR_ADDRESS:
5620 case RELOAD_FOR_INPUT_ADDRESS:
5621 case RELOAD_FOR_OPADDR_ADDR:
5624 case RELOAD_FOR_INPUT:
5625 case RELOAD_FOR_OPERAND_ADDRESS:
5626 if (! rld[r].optional)
5627 reload_override_in[r] = equiv;
5633 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5634 switch (rld[r].when_needed)
5636 case RELOAD_FOR_OTHER_ADDRESS:
5637 case RELOAD_FOR_INPADDR_ADDRESS:
5638 case RELOAD_FOR_INPUT_ADDRESS:
5639 case RELOAD_FOR_OPADDR_ADDR:
5640 case RELOAD_FOR_OPERAND_ADDRESS:
5641 case RELOAD_FOR_INPUT:
5644 if (! rld[r].optional)
5645 reload_override_in[r] = equiv;
5653 /* If we found an equivalent reg, say no code need be generated
5654 to load it, and use it as our reload reg. */
5656 && (regno != HARD_FRAME_POINTER_REGNUM
5657 || !frame_pointer_needed))
5659 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5661 rld[r].reg_rtx = equiv;
5662 reload_inherited[r] = 1;
5664 /* If reg_reloaded_valid is not set for this register,
5665 there might be a stale spill_reg_store lying around.
5666 We must clear it, since otherwise emit_reload_insns
5667 might delete the store. */
5668 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5669 spill_reg_store[regno] = NULL_RTX;
5670 /* If any of the hard registers in EQUIV are spill
5671 registers, mark them as in use for this insn. */
5672 for (k = 0; k < nr; k++)
5674 i = spill_reg_order[regno + k];
5677 mark_reload_reg_in_use (regno, rld[r].opnum,
5680 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5687 /* If we found a register to use already, or if this is an optional
5688 reload, we are done. */
5689 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5693 /* No longer needed for correct operation. Might or might
5694 not give better code on the average. Want to experiment? */
5696 /* See if there is a later reload that has a class different from our
5697 class that intersects our class or that requires less register
5698 than our reload. If so, we must allocate a register to this
5699 reload now, since that reload might inherit a previous reload
5700 and take the only available register in our class. Don't do this
5701 for optional reloads since they will force all previous reloads
5702 to be allocated. Also don't do this for reloads that have been
5705 for (i = j + 1; i < n_reloads; i++)
5707 int s = reload_order[i];
5709 if ((rld[s].in == 0 && rld[s].out == 0
5710 && ! rld[s].secondary_p)
5714 if ((rld[s].class != rld[r].class
5715 && reg_classes_intersect_p (rld[r].class,
5717 || rld[s].nregs < rld[r].nregs)
5724 allocate_reload_reg (chain, r, j == n_reloads - 1);
5728 /* Now allocate reload registers for anything non-optional that
5729 didn't get one yet. */
5730 for (j = 0; j < n_reloads; j++)
5732 int r = reload_order[j];
5734 /* Ignore reloads that got marked inoperative. */
5735 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5738 /* Skip reloads that already have a register allocated or are
5740 if (rld[r].reg_rtx != 0 || rld[r].optional)
5743 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5747 /* If that loop got all the way, we have won. */
5754 /* Loop around and try without any inheritance. */
5759 /* First undo everything done by the failed attempt
5760 to allocate with inheritance. */
5761 choose_reload_regs_init (chain, save_reload_reg_rtx);
5763 /* Some sanity tests to verify that the reloads found in the first
5764 pass are identical to the ones we have now. */
5765 if (chain->n_reloads != n_reloads)
5768 for (i = 0; i < n_reloads; i++)
5770 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5772 if (chain->rld[i].when_needed != rld[i].when_needed)
5774 for (j = 0; j < n_spills; j++)
5775 if (spill_regs[j] == chain->rld[i].regno)
5776 if (! set_reload_reg (j, i))
5777 failed_reload (chain->insn, i);
5781 /* If we thought we could inherit a reload, because it seemed that
5782 nothing else wanted the same reload register earlier in the insn,
5783 verify that assumption, now that all reloads have been assigned.
5784 Likewise for reloads where reload_override_in has been set. */
5786 /* If doing expensive optimizations, do one preliminary pass that doesn't
5787 cancel any inheritance, but removes reloads that have been needed only
5788 for reloads that we know can be inherited. */
5789 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5791 for (j = 0; j < n_reloads; j++)
5793 int r = reload_order[j];
5795 if (reload_inherited[r] && rld[r].reg_rtx)
5796 check_reg = rld[r].reg_rtx;
5797 else if (reload_override_in[r]
5798 && (GET_CODE (reload_override_in[r]) == REG
5799 || GET_CODE (reload_override_in[r]) == SUBREG))
5800 check_reg = reload_override_in[r];
5803 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5804 rld[r].opnum, rld[r].when_needed, rld[r].in,
5805 (reload_inherited[r]
5806 ? rld[r].out : const0_rtx),
5811 reload_inherited[r] = 0;
5812 reload_override_in[r] = 0;
5814 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5815 reload_override_in, then we do not need its related
5816 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5817 likewise for other reload types.
5818 We handle this by removing a reload when its only replacement
5819 is mentioned in reload_in of the reload we are going to inherit.
5820 A special case are auto_inc expressions; even if the input is
5821 inherited, we still need the address for the output. We can
5822 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5823 If we succeeded removing some reload and we are doing a preliminary
5824 pass just to remove such reloads, make another pass, since the
5825 removal of one reload might allow us to inherit another one. */
5827 && rld[r].out != rld[r].in
5828 && remove_address_replacements (rld[r].in) && pass)
5833 /* Now that reload_override_in is known valid,
5834 actually override reload_in. */
5835 for (j = 0; j < n_reloads; j++)
5836 if (reload_override_in[j])
5837 rld[j].in = reload_override_in[j];
5839 /* If this reload won't be done because it has been canceled or is
5840 optional and not inherited, clear reload_reg_rtx so other
5841 routines (such as subst_reloads) don't get confused. */
5842 for (j = 0; j < n_reloads; j++)
5843 if (rld[j].reg_rtx != 0
5844 && ((rld[j].optional && ! reload_inherited[j])
5845 || (rld[j].in == 0 && rld[j].out == 0
5846 && ! rld[j].secondary_p)))
5848 int regno = true_regnum (rld[j].reg_rtx);
5850 if (spill_reg_order[regno] >= 0)
5851 clear_reload_reg_in_use (regno, rld[j].opnum,
5852 rld[j].when_needed, rld[j].mode);
5854 reload_spill_index[j] = -1;
5857 /* Record which pseudos and which spill regs have output reloads. */
5858 for (j = 0; j < n_reloads; j++)
5860 int r = reload_order[j];
5862 i = reload_spill_index[r];
5864 /* I is nonneg if this reload uses a register.
5865 If rld[r].reg_rtx is 0, this is an optional reload
5866 that we opted to ignore. */
5867 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5868 && rld[r].reg_rtx != 0)
5870 int nregno = REGNO (rld[r].out_reg);
5873 if (nregno < FIRST_PSEUDO_REGISTER)
5874 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5877 reg_has_output_reload[nregno + nr] = 1;
5881 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5883 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5886 if (rld[r].when_needed != RELOAD_OTHER
5887 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5888 && rld[r].when_needed != RELOAD_FOR_INSN)
5894 /* Deallocate the reload register for reload R. This is called from
5895 remove_address_replacements. */
5898 deallocate_reload_reg (int r)
5902 if (! rld[r].reg_rtx)
5904 regno = true_regnum (rld[r].reg_rtx);
5906 if (spill_reg_order[regno] >= 0)
5907 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5909 reload_spill_index[r] = -1;
5912 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5913 reloads of the same item for fear that we might not have enough reload
5914 registers. However, normally they will get the same reload register
5915 and hence actually need not be loaded twice.
5917 Here we check for the most common case of this phenomenon: when we have
5918 a number of reloads for the same object, each of which were allocated
5919 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5920 reload, and is not modified in the insn itself. If we find such,
5921 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5922 This will not increase the number of spill registers needed and will
5923 prevent redundant code. */
5926 merge_assigned_reloads (rtx insn)
5930 /* Scan all the reloads looking for ones that only load values and
5931 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5932 assigned and not modified by INSN. */
5934 for (i = 0; i < n_reloads; i++)
5936 int conflicting_input = 0;
5937 int max_input_address_opnum = -1;
5938 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5940 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5941 || rld[i].out != 0 || rld[i].reg_rtx == 0
5942 || reg_set_p (rld[i].reg_rtx, insn))
5945 /* Look at all other reloads. Ensure that the only use of this
5946 reload_reg_rtx is in a reload that just loads the same value
5947 as we do. Note that any secondary reloads must be of the identical
5948 class since the values, modes, and result registers are the
5949 same, so we need not do anything with any secondary reloads. */
5951 for (j = 0; j < n_reloads; j++)
5953 if (i == j || rld[j].reg_rtx == 0
5954 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5958 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5959 && rld[j].opnum > max_input_address_opnum)
5960 max_input_address_opnum = rld[j].opnum;
5962 /* If the reload regs aren't exactly the same (e.g, different modes)
5963 or if the values are different, we can't merge this reload.
5964 But if it is an input reload, we might still merge
5965 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5967 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5968 || rld[j].out != 0 || rld[j].in == 0
5969 || ! rtx_equal_p (rld[i].in, rld[j].in))
5971 if (rld[j].when_needed != RELOAD_FOR_INPUT
5972 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5973 || rld[i].opnum > rld[j].opnum)
5974 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5976 conflicting_input = 1;
5977 if (min_conflicting_input_opnum > rld[j].opnum)
5978 min_conflicting_input_opnum = rld[j].opnum;
5982 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5983 we, in fact, found any matching reloads. */
5986 && max_input_address_opnum <= min_conflicting_input_opnum)
5988 for (j = 0; j < n_reloads; j++)
5989 if (i != j && rld[j].reg_rtx != 0
5990 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5991 && (! conflicting_input
5992 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5993 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5995 rld[i].when_needed = RELOAD_OTHER;
5997 reload_spill_index[j] = -1;
5998 transfer_replacements (i, j);
6001 /* If this is now RELOAD_OTHER, look for any reloads that load
6002 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6003 if they were for inputs, RELOAD_OTHER for outputs. Note that
6004 this test is equivalent to looking for reloads for this operand
6006 /* We must take special care when there are two or more reloads to
6007 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6008 same value or a part of it; we must not change its type if there
6009 is a conflicting input. */
6011 if (rld[i].when_needed == RELOAD_OTHER)
6012 for (j = 0; j < n_reloads; j++)
6014 && rld[j].when_needed != RELOAD_OTHER
6015 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6016 && (! conflicting_input
6017 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6018 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6019 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6025 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6026 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6027 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6029 /* Check to see if we accidentally converted two reloads
6030 that use the same reload register with different inputs
6031 to the same type. If so, the resulting code won't work,
6034 for (k = 0; k < j; k++)
6035 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6036 && rld[k].when_needed == rld[j].when_needed
6037 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6038 && ! rtx_equal_p (rld[k].in, rld[j].in))
6045 /* These arrays are filled by emit_reload_insns and its subroutines. */
6046 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6047 static rtx other_input_address_reload_insns = 0;
6048 static rtx other_input_reload_insns = 0;
6049 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6050 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6051 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6052 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6053 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6054 static rtx operand_reload_insns = 0;
6055 static rtx other_operand_reload_insns = 0;
6056 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6058 /* Values to be put in spill_reg_store are put here first. */
6059 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6060 static HARD_REG_SET reg_reloaded_died;
6062 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6063 has the number J. OLD contains the value to be used as input. */
6066 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6069 rtx insn = chain->insn;
6070 rtx reloadreg = rl->reg_rtx;
6071 rtx oldequiv_reg = 0;
6074 enum machine_mode mode;
6077 /* Determine the mode to reload in.
6078 This is very tricky because we have three to choose from.
6079 There is the mode the insn operand wants (rl->inmode).
6080 There is the mode of the reload register RELOADREG.
6081 There is the intrinsic mode of the operand, which we could find
6082 by stripping some SUBREGs.
6083 It turns out that RELOADREG's mode is irrelevant:
6084 we can change that arbitrarily.
6086 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6087 then the reload reg may not support QImode moves, so use SImode.
6088 If foo is in memory due to spilling a pseudo reg, this is safe,
6089 because the QImode value is in the least significant part of a
6090 slot big enough for a SImode. If foo is some other sort of
6091 memory reference, then it is impossible to reload this case,
6092 so previous passes had better make sure this never happens.
6094 Then consider a one-word union which has SImode and one of its
6095 members is a float, being fetched as (SUBREG:SF union:SI).
6096 We must fetch that as SFmode because we could be loading into
6097 a float-only register. In this case OLD's mode is correct.
6099 Consider an immediate integer: it has VOIDmode. Here we need
6100 to get a mode from something else.
6102 In some cases, there is a fourth mode, the operand's
6103 containing mode. If the insn specifies a containing mode for
6104 this operand, it overrides all others.
6106 I am not sure whether the algorithm here is always right,
6107 but it does the right things in those cases. */
6109 mode = GET_MODE (old);
6110 if (mode == VOIDmode)
6113 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6114 /* If we need a secondary register for this operation, see if
6115 the value is already in a register in that class. Don't
6116 do this if the secondary register will be used as a scratch
6119 if (rl->secondary_in_reload >= 0
6120 && rl->secondary_in_icode == CODE_FOR_nothing
6123 = find_equiv_reg (old, insn,
6124 rld[rl->secondary_in_reload].class,
6128 /* If reloading from memory, see if there is a register
6129 that already holds the same value. If so, reload from there.
6130 We can pass 0 as the reload_reg_p argument because
6131 any other reload has either already been emitted,
6132 in which case find_equiv_reg will see the reload-insn,
6133 or has yet to be emitted, in which case it doesn't matter
6134 because we will use this equiv reg right away. */
6136 if (oldequiv == 0 && optimize
6137 && (GET_CODE (old) == MEM
6138 || (GET_CODE (old) == REG
6139 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6140 && reg_renumber[REGNO (old)] < 0)))
6141 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6145 unsigned int regno = true_regnum (oldequiv);
6147 /* Don't use OLDEQUIV if any other reload changes it at an
6148 earlier stage of this insn or at this stage. */
6149 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6150 rl->in, const0_rtx, j, 0))
6153 /* If it is no cheaper to copy from OLDEQUIV into the
6154 reload register than it would be to move from memory,
6155 don't use it. Likewise, if we need a secondary register
6159 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6160 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6162 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6163 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6164 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6168 #ifdef SECONDARY_MEMORY_NEEDED
6169 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6177 /* delete_output_reload is only invoked properly if old contains
6178 the original pseudo register. Since this is replaced with a
6179 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6180 find the pseudo in RELOAD_IN_REG. */
6182 && reload_override_in[j]
6183 && GET_CODE (rl->in_reg) == REG)
6190 else if (GET_CODE (oldequiv) == REG)
6191 oldequiv_reg = oldequiv;
6192 else if (GET_CODE (oldequiv) == SUBREG)
6193 oldequiv_reg = SUBREG_REG (oldequiv);
6195 /* If we are reloading from a register that was recently stored in
6196 with an output-reload, see if we can prove there was
6197 actually no need to store the old value in it. */
6199 if (optimize && GET_CODE (oldequiv) == REG
6200 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6201 && spill_reg_store[REGNO (oldequiv)]
6202 && GET_CODE (old) == REG
6203 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6204 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6206 delete_output_reload (insn, j, REGNO (oldequiv));
6208 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6209 then load RELOADREG from OLDEQUIV. Note that we cannot use
6210 gen_lowpart_common since it can do the wrong thing when
6211 RELOADREG has a multi-word mode. Note that RELOADREG
6212 must always be a REG here. */
6214 if (GET_MODE (reloadreg) != mode)
6215 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6216 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6217 oldequiv = SUBREG_REG (oldequiv);
6218 if (GET_MODE (oldequiv) != VOIDmode
6219 && mode != GET_MODE (oldequiv))
6220 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6222 /* Switch to the right place to emit the reload insns. */
6223 switch (rl->when_needed)
6226 where = &other_input_reload_insns;
6228 case RELOAD_FOR_INPUT:
6229 where = &input_reload_insns[rl->opnum];
6231 case RELOAD_FOR_INPUT_ADDRESS:
6232 where = &input_address_reload_insns[rl->opnum];
6234 case RELOAD_FOR_INPADDR_ADDRESS:
6235 where = &inpaddr_address_reload_insns[rl->opnum];
6237 case RELOAD_FOR_OUTPUT_ADDRESS:
6238 where = &output_address_reload_insns[rl->opnum];
6240 case RELOAD_FOR_OUTADDR_ADDRESS:
6241 where = &outaddr_address_reload_insns[rl->opnum];
6243 case RELOAD_FOR_OPERAND_ADDRESS:
6244 where = &operand_reload_insns;
6246 case RELOAD_FOR_OPADDR_ADDR:
6247 where = &other_operand_reload_insns;
6249 case RELOAD_FOR_OTHER_ADDRESS:
6250 where = &other_input_address_reload_insns;
6256 push_to_sequence (*where);
6258 /* Auto-increment addresses must be reloaded in a special way. */
6259 if (rl->out && ! rl->out_reg)
6261 /* We are not going to bother supporting the case where a
6262 incremented register can't be copied directly from
6263 OLDEQUIV since this seems highly unlikely. */
6264 if (rl->secondary_in_reload >= 0)
6267 if (reload_inherited[j])
6268 oldequiv = reloadreg;
6270 old = XEXP (rl->in_reg, 0);
6272 if (optimize && GET_CODE (oldequiv) == REG
6273 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6274 && spill_reg_store[REGNO (oldequiv)]
6275 && GET_CODE (old) == REG
6276 && (dead_or_set_p (insn,
6277 spill_reg_stored_to[REGNO (oldequiv)])
6278 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6280 delete_output_reload (insn, j, REGNO (oldequiv));
6282 /* Prevent normal processing of this reload. */
6284 /* Output a special code sequence for this case. */
6285 new_spill_reg_store[REGNO (reloadreg)]
6286 = inc_for_reload (reloadreg, oldequiv, rl->out,
6290 /* If we are reloading a pseudo-register that was set by the previous
6291 insn, see if we can get rid of that pseudo-register entirely
6292 by redirecting the previous insn into our reload register. */
6294 else if (optimize && GET_CODE (old) == REG
6295 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6296 && dead_or_set_p (insn, old)
6297 /* This is unsafe if some other reload
6298 uses the same reg first. */
6299 && ! conflicts_with_override (reloadreg)
6300 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6301 rl->when_needed, old, rl->out, j, 0))
6303 rtx temp = PREV_INSN (insn);
6304 while (temp && GET_CODE (temp) == NOTE)
6305 temp = PREV_INSN (temp);
6307 && GET_CODE (temp) == INSN
6308 && GET_CODE (PATTERN (temp)) == SET
6309 && SET_DEST (PATTERN (temp)) == old
6310 /* Make sure we can access insn_operand_constraint. */
6311 && asm_noperands (PATTERN (temp)) < 0
6312 /* This is unsafe if operand occurs more than once in current
6313 insn. Perhaps some occurrences aren't reloaded. */
6314 && count_occurrences (PATTERN (insn), old, 0) == 1)
6316 rtx old = SET_DEST (PATTERN (temp));
6317 /* Store into the reload register instead of the pseudo. */
6318 SET_DEST (PATTERN (temp)) = reloadreg;
6320 /* Verify that resulting insn is valid. */
6321 extract_insn (temp);
6322 if (constrain_operands (1))
6324 /* If the previous insn is an output reload, the source is
6325 a reload register, and its spill_reg_store entry will
6326 contain the previous destination. This is now
6328 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6329 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6331 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6332 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6335 /* If these are the only uses of the pseudo reg,
6336 pretend for GDB it lives in the reload reg we used. */
6337 if (REG_N_DEATHS (REGNO (old)) == 1
6338 && REG_N_SETS (REGNO (old)) == 1)
6340 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6341 alter_reg (REGNO (old), -1);
6347 SET_DEST (PATTERN (temp)) = old;
6352 /* We can't do that, so output an insn to load RELOADREG. */
6354 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6355 /* If we have a secondary reload, pick up the secondary register
6356 and icode, if any. If OLDEQUIV and OLD are different or
6357 if this is an in-out reload, recompute whether or not we
6358 still need a secondary register and what the icode should
6359 be. If we still need a secondary register and the class or
6360 icode is different, go back to reloading from OLD if using
6361 OLDEQUIV means that we got the wrong type of register. We
6362 cannot have different class or icode due to an in-out reload
6363 because we don't make such reloads when both the input and
6364 output need secondary reload registers. */
6366 if (! special && rl->secondary_in_reload >= 0)
6368 rtx second_reload_reg = 0;
6369 int secondary_reload = rl->secondary_in_reload;
6370 rtx real_oldequiv = oldequiv;
6373 enum insn_code icode;
6375 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6376 and similarly for OLD.
6377 See comments in get_secondary_reload in reload.c. */
6378 /* If it is a pseudo that cannot be replaced with its
6379 equivalent MEM, we must fall back to reload_in, which
6380 will have all the necessary substitutions registered.
6381 Likewise for a pseudo that can't be replaced with its
6382 equivalent constant.
6384 Take extra care for subregs of such pseudos. Note that
6385 we cannot use reg_equiv_mem in this case because it is
6386 not in the right mode. */
6389 if (GET_CODE (tmp) == SUBREG)
6390 tmp = SUBREG_REG (tmp);
6391 if (GET_CODE (tmp) == REG
6392 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6393 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6394 || reg_equiv_constant[REGNO (tmp)] != 0))
6396 if (! reg_equiv_mem[REGNO (tmp)]
6397 || num_not_at_initial_offset
6398 || GET_CODE (oldequiv) == SUBREG)
6399 real_oldequiv = rl->in;
6401 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6405 if (GET_CODE (tmp) == SUBREG)
6406 tmp = SUBREG_REG (tmp);
6407 if (GET_CODE (tmp) == REG
6408 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6409 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6410 || reg_equiv_constant[REGNO (tmp)] != 0))
6412 if (! reg_equiv_mem[REGNO (tmp)]
6413 || num_not_at_initial_offset
6414 || GET_CODE (old) == SUBREG)
6417 real_old = reg_equiv_mem[REGNO (tmp)];
6420 second_reload_reg = rld[secondary_reload].reg_rtx;
6421 icode = rl->secondary_in_icode;
6423 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6424 || (rl->in != 0 && rl->out != 0))
6426 enum reg_class new_class
6427 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6428 mode, real_oldequiv);
6430 if (new_class == NO_REGS)
6431 second_reload_reg = 0;
6434 enum insn_code new_icode;
6435 enum machine_mode new_mode;
6437 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6438 REGNO (second_reload_reg)))
6439 oldequiv = old, real_oldequiv = real_old;
6442 new_icode = reload_in_optab[(int) mode];
6443 if (new_icode != CODE_FOR_nothing
6444 && ((insn_data[(int) new_icode].operand[0].predicate
6445 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6447 || (insn_data[(int) new_icode].operand[1].predicate
6448 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6449 (real_oldequiv, mode)))))
6450 new_icode = CODE_FOR_nothing;
6452 if (new_icode == CODE_FOR_nothing)
6455 new_mode = insn_data[(int) new_icode].operand[2].mode;
6457 if (GET_MODE (second_reload_reg) != new_mode)
6459 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6461 oldequiv = old, real_oldequiv = real_old;
6464 = reload_adjust_reg_for_mode (second_reload_reg,
6471 /* If we still need a secondary reload register, check
6472 to see if it is being used as a scratch or intermediate
6473 register and generate code appropriately. If we need
6474 a scratch register, use REAL_OLDEQUIV since the form of
6475 the insn may depend on the actual address if it is
6478 if (second_reload_reg)
6480 if (icode != CODE_FOR_nothing)
6482 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6483 second_reload_reg));
6488 /* See if we need a scratch register to load the
6489 intermediate register (a tertiary reload). */
6490 enum insn_code tertiary_icode
6491 = rld[secondary_reload].secondary_in_icode;
6493 if (tertiary_icode != CODE_FOR_nothing)
6495 rtx third_reload_reg
6496 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6498 emit_insn ((GEN_FCN (tertiary_icode)
6499 (second_reload_reg, real_oldequiv,
6500 third_reload_reg)));
6503 gen_reload (second_reload_reg, real_oldequiv,
6507 oldequiv = second_reload_reg;
6513 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6515 rtx real_oldequiv = oldequiv;
6517 if ((GET_CODE (oldequiv) == REG
6518 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6519 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6520 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6521 || (GET_CODE (oldequiv) == SUBREG
6522 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6523 && (REGNO (SUBREG_REG (oldequiv))
6524 >= FIRST_PSEUDO_REGISTER)
6525 && ((reg_equiv_memory_loc
6526 [REGNO (SUBREG_REG (oldequiv))] != 0)
6527 || (reg_equiv_constant
6528 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6529 || (CONSTANT_P (oldequiv)
6530 && (PREFERRED_RELOAD_CLASS (oldequiv,
6531 REGNO_REG_CLASS (REGNO (reloadreg)))
6533 real_oldequiv = rl->in;
6534 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6538 if (flag_non_call_exceptions)
6539 copy_eh_notes (insn, get_insns ());
6541 /* End this sequence. */
6542 *where = get_insns ();
6545 /* Update reload_override_in so that delete_address_reloads_1
6546 can see the actual register usage. */
6548 reload_override_in[j] = oldequiv;
6551 /* Generate insns to for the output reload RL, which is for the insn described
6552 by CHAIN and has the number J. */
6554 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6557 rtx reloadreg = rl->reg_rtx;
6558 rtx insn = chain->insn;
6561 enum machine_mode mode = GET_MODE (old);
6564 if (rl->when_needed == RELOAD_OTHER)
6567 push_to_sequence (output_reload_insns[rl->opnum]);
6569 /* Determine the mode to reload in.
6570 See comments above (for input reloading). */
6572 if (mode == VOIDmode)
6574 /* VOIDmode should never happen for an output. */
6575 if (asm_noperands (PATTERN (insn)) < 0)
6576 /* It's the compiler's fault. */
6577 fatal_insn ("VOIDmode on an output", insn);
6578 error_for_asm (insn, "output operand is constant in `asm'");
6579 /* Prevent crash--use something we know is valid. */
6581 old = gen_rtx_REG (mode, REGNO (reloadreg));
6584 if (GET_MODE (reloadreg) != mode)
6585 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6587 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6589 /* If we need two reload regs, set RELOADREG to the intermediate
6590 one, since it will be stored into OLD. We might need a secondary
6591 register only for an input reload, so check again here. */
6593 if (rl->secondary_out_reload >= 0)
6597 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6598 && reg_equiv_mem[REGNO (old)] != 0)
6599 real_old = reg_equiv_mem[REGNO (old)];
6601 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6605 rtx second_reloadreg = reloadreg;
6606 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6608 /* See if RELOADREG is to be used as a scratch register
6609 or as an intermediate register. */
6610 if (rl->secondary_out_icode != CODE_FOR_nothing)
6612 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6613 (real_old, second_reloadreg, reloadreg)));
6618 /* See if we need both a scratch and intermediate reload
6621 int secondary_reload = rl->secondary_out_reload;
6622 enum insn_code tertiary_icode
6623 = rld[secondary_reload].secondary_out_icode;
6625 if (GET_MODE (reloadreg) != mode)
6626 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6628 if (tertiary_icode != CODE_FOR_nothing)
6631 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6634 /* Copy primary reload reg to secondary reload reg.
6635 (Note that these have been swapped above, then
6636 secondary reload reg to OLD using our insn.) */
6638 /* If REAL_OLD is a paradoxical SUBREG, remove it
6639 and try to put the opposite SUBREG on
6641 if (GET_CODE (real_old) == SUBREG
6642 && (GET_MODE_SIZE (GET_MODE (real_old))
6643 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6644 && 0 != (tem = gen_lowpart_common
6645 (GET_MODE (SUBREG_REG (real_old)),
6647 real_old = SUBREG_REG (real_old), reloadreg = tem;
6649 gen_reload (reloadreg, second_reloadreg,
6650 rl->opnum, rl->when_needed);
6651 emit_insn ((GEN_FCN (tertiary_icode)
6652 (real_old, reloadreg, third_reloadreg)));
6657 /* Copy between the reload regs here and then to
6660 gen_reload (reloadreg, second_reloadreg,
6661 rl->opnum, rl->when_needed);
6667 /* Output the last reload insn. */
6672 /* Don't output the last reload if OLD is not the dest of
6673 INSN and is in the src and is clobbered by INSN. */
6674 if (! flag_expensive_optimizations
6675 || GET_CODE (old) != REG
6676 || !(set = single_set (insn))
6677 || rtx_equal_p (old, SET_DEST (set))
6678 || !reg_mentioned_p (old, SET_SRC (set))
6679 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6680 gen_reload (old, reloadreg, rl->opnum,
6684 /* Look at all insns we emitted, just to be safe. */
6685 for (p = get_insns (); p; p = NEXT_INSN (p))
6688 rtx pat = PATTERN (p);
6690 /* If this output reload doesn't come from a spill reg,
6691 clear any memory of reloaded copies of the pseudo reg.
6692 If this output reload comes from a spill reg,
6693 reg_has_output_reload will make this do nothing. */
6694 note_stores (pat, forget_old_reloads_1, NULL);
6696 if (reg_mentioned_p (rl->reg_rtx, pat))
6698 rtx set = single_set (insn);
6699 if (reload_spill_index[j] < 0
6701 && SET_SRC (set) == rl->reg_rtx)
6703 int src = REGNO (SET_SRC (set));
6705 reload_spill_index[j] = src;
6706 SET_HARD_REG_BIT (reg_is_output_reload, src);
6707 if (find_regno_note (insn, REG_DEAD, src))
6708 SET_HARD_REG_BIT (reg_reloaded_died, src);
6710 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6712 int s = rl->secondary_out_reload;
6713 set = single_set (p);
6714 /* If this reload copies only to the secondary reload
6715 register, the secondary reload does the actual
6717 if (s >= 0 && set == NULL_RTX)
6718 /* We can't tell what function the secondary reload
6719 has and where the actual store to the pseudo is
6720 made; leave new_spill_reg_store alone. */
6723 && SET_SRC (set) == rl->reg_rtx
6724 && SET_DEST (set) == rld[s].reg_rtx)
6726 /* Usually the next instruction will be the
6727 secondary reload insn; if we can confirm
6728 that it is, setting new_spill_reg_store to
6729 that insn will allow an extra optimization. */
6730 rtx s_reg = rld[s].reg_rtx;
6731 rtx next = NEXT_INSN (p);
6732 rld[s].out = rl->out;
6733 rld[s].out_reg = rl->out_reg;
6734 set = single_set (next);
6735 if (set && SET_SRC (set) == s_reg
6736 && ! new_spill_reg_store[REGNO (s_reg)])
6738 SET_HARD_REG_BIT (reg_is_output_reload,
6740 new_spill_reg_store[REGNO (s_reg)] = next;
6744 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6749 if (rl->when_needed == RELOAD_OTHER)
6751 emit_insn (other_output_reload_insns[rl->opnum]);
6752 other_output_reload_insns[rl->opnum] = get_insns ();
6755 output_reload_insns[rl->opnum] = get_insns ();
6757 if (flag_non_call_exceptions)
6758 copy_eh_notes (insn, get_insns ());
6763 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6764 and has the number J. */
6766 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6768 rtx insn = chain->insn;
6769 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6770 ? rl->in_reg : rl->in);
6773 /* AUTO_INC reloads need to be handled even if inherited. We got an
6774 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6775 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6776 && ! rtx_equal_p (rl->reg_rtx, old)
6777 && rl->reg_rtx != 0)
6778 emit_input_reload_insns (chain, rld + j, old, j);
6780 /* When inheriting a wider reload, we have a MEM in rl->in,
6781 e.g. inheriting a SImode output reload for
6782 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6783 if (optimize && reload_inherited[j] && rl->in
6784 && GET_CODE (rl->in) == MEM
6785 && GET_CODE (rl->in_reg) == MEM
6786 && reload_spill_index[j] >= 0
6787 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6788 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6790 /* If we are reloading a register that was recently stored in with an
6791 output-reload, see if we can prove there was
6792 actually no need to store the old value in it. */
6795 && (reload_inherited[j] || reload_override_in[j])
6797 && GET_CODE (rl->reg_rtx) == REG
6798 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6800 /* There doesn't seem to be any reason to restrict this to pseudos
6801 and doing so loses in the case where we are copying from a
6802 register of the wrong class. */
6803 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6804 >= FIRST_PSEUDO_REGISTER)
6806 /* The insn might have already some references to stackslots
6807 replaced by MEMs, while reload_out_reg still names the
6809 && (dead_or_set_p (insn,
6810 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6811 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6813 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6816 /* Do output reloading for reload RL, which is for the insn described by
6817 CHAIN and has the number J.
6818 ??? At some point we need to support handling output reloads of
6819 JUMP_INSNs or insns that set cc0. */
6821 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6824 rtx insn = chain->insn;
6825 /* If this is an output reload that stores something that is
6826 not loaded in this same reload, see if we can eliminate a previous
6828 rtx pseudo = rl->out_reg;
6832 && GET_CODE (pseudo) == REG
6833 && ! rtx_equal_p (rl->in_reg, pseudo)
6834 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6835 && reg_last_reload_reg[REGNO (pseudo)])
6837 int pseudo_no = REGNO (pseudo);
6838 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6840 /* We don't need to test full validity of last_regno for
6841 inherit here; we only want to know if the store actually
6842 matches the pseudo. */
6843 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6844 && reg_reloaded_contents[last_regno] == pseudo_no
6845 && spill_reg_store[last_regno]
6846 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6847 delete_output_reload (insn, j, last_regno);
6852 || rl->reg_rtx == old
6853 || rl->reg_rtx == 0)
6856 /* An output operand that dies right away does need a reload,
6857 but need not be copied from it. Show the new location in the
6859 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6860 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6862 XEXP (note, 0) = rl->reg_rtx;
6865 /* Likewise for a SUBREG of an operand that dies. */
6866 else if (GET_CODE (old) == SUBREG
6867 && GET_CODE (SUBREG_REG (old)) == REG
6868 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6871 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6875 else if (GET_CODE (old) == SCRATCH)
6876 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6877 but we don't want to make an output reload. */
6880 /* If is a JUMP_INSN, we can't support output reloads yet. */
6881 if (GET_CODE (insn) == JUMP_INSN)
6884 emit_output_reload_insns (chain, rld + j, j);
6887 /* Output insns to reload values in and out of the chosen reload regs. */
6890 emit_reload_insns (struct insn_chain *chain)
6892 rtx insn = chain->insn;
6896 CLEAR_HARD_REG_SET (reg_reloaded_died);
6898 for (j = 0; j < reload_n_operands; j++)
6899 input_reload_insns[j] = input_address_reload_insns[j]
6900 = inpaddr_address_reload_insns[j]
6901 = output_reload_insns[j] = output_address_reload_insns[j]
6902 = outaddr_address_reload_insns[j]
6903 = other_output_reload_insns[j] = 0;
6904 other_input_address_reload_insns = 0;
6905 other_input_reload_insns = 0;
6906 operand_reload_insns = 0;
6907 other_operand_reload_insns = 0;
6909 /* Dump reloads into the dump file. */
6912 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6913 debug_reload_to_stream (rtl_dump_file);
6916 /* Now output the instructions to copy the data into and out of the
6917 reload registers. Do these in the order that the reloads were reported,
6918 since reloads of base and index registers precede reloads of operands
6919 and the operands may need the base and index registers reloaded. */
6921 for (j = 0; j < n_reloads; j++)
6924 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6925 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6927 do_input_reload (chain, rld + j, j);
6928 do_output_reload (chain, rld + j, j);
6931 /* Now write all the insns we made for reloads in the order expected by
6932 the allocation functions. Prior to the insn being reloaded, we write
6933 the following reloads:
6935 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6937 RELOAD_OTHER reloads.
6939 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6940 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6941 RELOAD_FOR_INPUT reload for the operand.
6943 RELOAD_FOR_OPADDR_ADDRS reloads.
6945 RELOAD_FOR_OPERAND_ADDRESS reloads.
6947 After the insn being reloaded, we write the following:
6949 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6950 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6951 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6952 reloads for the operand. The RELOAD_OTHER output reloads are
6953 output in descending order by reload number. */
6955 emit_insn_before (other_input_address_reload_insns, insn);
6956 emit_insn_before (other_input_reload_insns, insn);
6958 for (j = 0; j < reload_n_operands; j++)
6960 emit_insn_before (inpaddr_address_reload_insns[j], insn);
6961 emit_insn_before (input_address_reload_insns[j], insn);
6962 emit_insn_before (input_reload_insns[j], insn);
6965 emit_insn_before (other_operand_reload_insns, insn);
6966 emit_insn_before (operand_reload_insns, insn);
6968 for (j = 0; j < reload_n_operands; j++)
6970 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
6971 x = emit_insn_after (output_address_reload_insns[j], x);
6972 x = emit_insn_after (output_reload_insns[j], x);
6973 emit_insn_after (other_output_reload_insns[j], x);
6976 /* For all the spill regs newly reloaded in this instruction,
6977 record what they were reloaded from, so subsequent instructions
6978 can inherit the reloads.
6980 Update spill_reg_store for the reloads of this insn.
6981 Copy the elements that were updated in the loop above. */
6983 for (j = 0; j < n_reloads; j++)
6985 int r = reload_order[j];
6986 int i = reload_spill_index[r];
6988 /* If this is a non-inherited input reload from a pseudo, we must
6989 clear any memory of a previous store to the same pseudo. Only do
6990 something if there will not be an output reload for the pseudo
6992 if (rld[r].in_reg != 0
6993 && ! (reload_inherited[r] || reload_override_in[r]))
6995 rtx reg = rld[r].in_reg;
6997 if (GET_CODE (reg) == SUBREG)
6998 reg = SUBREG_REG (reg);
7000 if (GET_CODE (reg) == REG
7001 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7002 && ! reg_has_output_reload[REGNO (reg)])
7004 int nregno = REGNO (reg);
7006 if (reg_last_reload_reg[nregno])
7008 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7010 if (reg_reloaded_contents[last_regno] == nregno)
7011 spill_reg_store[last_regno] = 0;
7016 /* I is nonneg if this reload used a register.
7017 If rld[r].reg_rtx is 0, this is an optional reload
7018 that we opted to ignore. */
7020 if (i >= 0 && rld[r].reg_rtx != 0)
7022 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7024 int part_reaches_end = 0;
7025 int all_reaches_end = 1;
7027 /* For a multi register reload, we need to check if all or part
7028 of the value lives to the end. */
7029 for (k = 0; k < nr; k++)
7031 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7032 rld[r].when_needed))
7033 part_reaches_end = 1;
7035 all_reaches_end = 0;
7038 /* Ignore reloads that don't reach the end of the insn in
7040 if (all_reaches_end)
7042 /* First, clear out memory of what used to be in this spill reg.
7043 If consecutive registers are used, clear them all. */
7045 for (k = 0; k < nr; k++)
7046 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7048 /* Maybe the spill reg contains a copy of reload_out. */
7050 && (GET_CODE (rld[r].out) == REG
7054 || GET_CODE (rld[r].out_reg) == REG))
7056 rtx out = (GET_CODE (rld[r].out) == REG
7060 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7061 int nregno = REGNO (out);
7062 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7063 : HARD_REGNO_NREGS (nregno,
7064 GET_MODE (rld[r].reg_rtx)));
7066 spill_reg_store[i] = new_spill_reg_store[i];
7067 spill_reg_stored_to[i] = out;
7068 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7070 /* If NREGNO is a hard register, it may occupy more than
7071 one register. If it does, say what is in the
7072 rest of the registers assuming that both registers
7073 agree on how many words the object takes. If not,
7074 invalidate the subsequent registers. */
7076 if (nregno < FIRST_PSEUDO_REGISTER)
7077 for (k = 1; k < nnr; k++)
7078 reg_last_reload_reg[nregno + k]
7080 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7083 /* Now do the inverse operation. */
7084 for (k = 0; k < nr; k++)
7086 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7087 reg_reloaded_contents[i + k]
7088 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7091 reg_reloaded_insn[i + k] = insn;
7092 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7096 /* Maybe the spill reg contains a copy of reload_in. Only do
7097 something if there will not be an output reload for
7098 the register being reloaded. */
7099 else if (rld[r].out_reg == 0
7101 && ((GET_CODE (rld[r].in) == REG
7102 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7103 && ! reg_has_output_reload[REGNO (rld[r].in)])
7104 || (GET_CODE (rld[r].in_reg) == REG
7105 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7106 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7111 if (GET_CODE (rld[r].in) == REG
7112 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7113 nregno = REGNO (rld[r].in);
7114 else if (GET_CODE (rld[r].in_reg) == REG)
7115 nregno = REGNO (rld[r].in_reg);
7117 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7119 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7120 : HARD_REGNO_NREGS (nregno,
7121 GET_MODE (rld[r].reg_rtx)));
7123 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7125 if (nregno < FIRST_PSEUDO_REGISTER)
7126 for (k = 1; k < nnr; k++)
7127 reg_last_reload_reg[nregno + k]
7129 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7132 /* Unless we inherited this reload, show we haven't
7133 recently done a store.
7134 Previous stores of inherited auto_inc expressions
7135 also have to be discarded. */
7136 if (! reload_inherited[r]
7137 || (rld[r].out && ! rld[r].out_reg))
7138 spill_reg_store[i] = 0;
7140 for (k = 0; k < nr; k++)
7142 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7143 reg_reloaded_contents[i + k]
7144 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7147 reg_reloaded_insn[i + k] = insn;
7148 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7153 /* However, if part of the reload reaches the end, then we must
7154 invalidate the old info for the part that survives to the end. */
7155 else if (part_reaches_end)
7157 for (k = 0; k < nr; k++)
7158 if (reload_reg_reaches_end_p (i + k,
7160 rld[r].when_needed))
7161 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7165 /* The following if-statement was #if 0'd in 1.34 (or before...).
7166 It's reenabled in 1.35 because supposedly nothing else
7167 deals with this problem. */
7169 /* If a register gets output-reloaded from a non-spill register,
7170 that invalidates any previous reloaded copy of it.
7171 But forget_old_reloads_1 won't get to see it, because
7172 it thinks only about the original insn. So invalidate it here. */
7173 if (i < 0 && rld[r].out != 0
7174 && (GET_CODE (rld[r].out) == REG
7175 || (GET_CODE (rld[r].out) == MEM
7176 && GET_CODE (rld[r].out_reg) == REG)))
7178 rtx out = (GET_CODE (rld[r].out) == REG
7179 ? rld[r].out : rld[r].out_reg);
7180 int nregno = REGNO (out);
7181 if (nregno >= FIRST_PSEUDO_REGISTER)
7183 rtx src_reg, store_insn = NULL_RTX;
7185 reg_last_reload_reg[nregno] = 0;
7187 /* If we can find a hard register that is stored, record
7188 the storing insn so that we may delete this insn with
7189 delete_output_reload. */
7190 src_reg = rld[r].reg_rtx;
7192 /* If this is an optional reload, try to find the source reg
7193 from an input reload. */
7196 rtx set = single_set (insn);
7197 if (set && SET_DEST (set) == rld[r].out)
7201 src_reg = SET_SRC (set);
7203 for (k = 0; k < n_reloads; k++)
7205 if (rld[k].in == src_reg)
7207 src_reg = rld[k].reg_rtx;
7214 store_insn = new_spill_reg_store[REGNO (src_reg)];
7215 if (src_reg && GET_CODE (src_reg) == REG
7216 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7218 int src_regno = REGNO (src_reg);
7219 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7220 /* The place where to find a death note varies with
7221 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7222 necessarily checked exactly in the code that moves
7223 notes, so just check both locations. */
7224 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7225 if (! note && store_insn)
7226 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7229 spill_reg_store[src_regno + nr] = store_insn;
7230 spill_reg_stored_to[src_regno + nr] = out;
7231 reg_reloaded_contents[src_regno + nr] = nregno;
7232 reg_reloaded_insn[src_regno + nr] = store_insn;
7233 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7234 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7235 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7237 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7239 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7241 reg_last_reload_reg[nregno] = src_reg;
7246 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7248 while (num_regs-- > 0)
7249 reg_last_reload_reg[nregno + num_regs] = 0;
7253 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7256 /* Emit code to perform a reload from IN (which may be a reload register) to
7257 OUT (which may also be a reload register). IN or OUT is from operand
7258 OPNUM with reload type TYPE.
7260 Returns first insn emitted. */
7263 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7265 rtx last = get_last_insn ();
7268 /* If IN is a paradoxical SUBREG, remove it and try to put the
7269 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7270 if (GET_CODE (in) == SUBREG
7271 && (GET_MODE_SIZE (GET_MODE (in))
7272 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7273 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7274 in = SUBREG_REG (in), out = tem;
7275 else if (GET_CODE (out) == SUBREG
7276 && (GET_MODE_SIZE (GET_MODE (out))
7277 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7278 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7279 out = SUBREG_REG (out), in = tem;
7281 /* How to do this reload can get quite tricky. Normally, we are being
7282 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7283 register that didn't get a hard register. In that case we can just
7284 call emit_move_insn.
7286 We can also be asked to reload a PLUS that adds a register or a MEM to
7287 another register, constant or MEM. This can occur during frame pointer
7288 elimination and while reloading addresses. This case is handled by
7289 trying to emit a single insn to perform the add. If it is not valid,
7290 we use a two insn sequence.
7292 Finally, we could be called to handle an 'o' constraint by putting
7293 an address into a register. In that case, we first try to do this
7294 with a named pattern of "reload_load_address". If no such pattern
7295 exists, we just emit a SET insn and hope for the best (it will normally
7296 be valid on machines that use 'o').
7298 This entire process is made complex because reload will never
7299 process the insns we generate here and so we must ensure that
7300 they will fit their constraints and also by the fact that parts of
7301 IN might be being reloaded separately and replaced with spill registers.
7302 Because of this, we are, in some sense, just guessing the right approach
7303 here. The one listed above seems to work.
7305 ??? At some point, this whole thing needs to be rethought. */
7307 if (GET_CODE (in) == PLUS
7308 && (GET_CODE (XEXP (in, 0)) == REG
7309 || GET_CODE (XEXP (in, 0)) == SUBREG
7310 || GET_CODE (XEXP (in, 0)) == MEM)
7311 && (GET_CODE (XEXP (in, 1)) == REG
7312 || GET_CODE (XEXP (in, 1)) == SUBREG
7313 || CONSTANT_P (XEXP (in, 1))
7314 || GET_CODE (XEXP (in, 1)) == MEM))
7316 /* We need to compute the sum of a register or a MEM and another
7317 register, constant, or MEM, and put it into the reload
7318 register. The best possible way of doing this is if the machine
7319 has a three-operand ADD insn that accepts the required operands.
7321 The simplest approach is to try to generate such an insn and see if it
7322 is recognized and matches its constraints. If so, it can be used.
7324 It might be better not to actually emit the insn unless it is valid,
7325 but we need to pass the insn as an operand to `recog' and
7326 `extract_insn' and it is simpler to emit and then delete the insn if
7327 not valid than to dummy things up. */
7329 rtx op0, op1, tem, insn;
7332 op0 = find_replacement (&XEXP (in, 0));
7333 op1 = find_replacement (&XEXP (in, 1));
7335 /* Since constraint checking is strict, commutativity won't be
7336 checked, so we need to do that here to avoid spurious failure
7337 if the add instruction is two-address and the second operand
7338 of the add is the same as the reload reg, which is frequently
7339 the case. If the insn would be A = B + A, rearrange it so
7340 it will be A = A + B as constrain_operands expects. */
7342 if (GET_CODE (XEXP (in, 1)) == REG
7343 && REGNO (out) == REGNO (XEXP (in, 1)))
7344 tem = op0, op0 = op1, op1 = tem;
7346 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7347 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7349 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7350 code = recog_memoized (insn);
7354 extract_insn (insn);
7355 /* We want constrain operands to treat this insn strictly in
7356 its validity determination, i.e., the way it would after reload
7358 if (constrain_operands (1))
7362 delete_insns_since (last);
7364 /* If that failed, we must use a conservative two-insn sequence.
7366 Use a move to copy one operand into the reload register. Prefer
7367 to reload a constant, MEM or pseudo since the move patterns can
7368 handle an arbitrary operand. If OP1 is not a constant, MEM or
7369 pseudo and OP1 is not a valid operand for an add instruction, then
7372 After reloading one of the operands into the reload register, add
7373 the reload register to the output register.
7375 If there is another way to do this for a specific machine, a
7376 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7379 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7381 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7382 || (GET_CODE (op1) == REG
7383 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7384 || (code != CODE_FOR_nothing
7385 && ! ((*insn_data[code].operand[2].predicate)
7386 (op1, insn_data[code].operand[2].mode))))
7387 tem = op0, op0 = op1, op1 = tem;
7389 gen_reload (out, op0, opnum, type);
7391 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7392 This fixes a problem on the 32K where the stack pointer cannot
7393 be used as an operand of an add insn. */
7395 if (rtx_equal_p (op0, op1))
7398 insn = emit_insn (gen_add2_insn (out, op1));
7400 /* If that failed, copy the address register to the reload register.
7401 Then add the constant to the reload register. */
7403 code = recog_memoized (insn);
7407 extract_insn (insn);
7408 /* We want constrain operands to treat this insn strictly in
7409 its validity determination, i.e., the way it would after reload
7411 if (constrain_operands (1))
7413 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7415 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7420 delete_insns_since (last);
7422 gen_reload (out, op1, opnum, type);
7423 insn = emit_insn (gen_add2_insn (out, op0));
7424 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7427 #ifdef SECONDARY_MEMORY_NEEDED
7428 /* If we need a memory location to do the move, do it that way. */
7429 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7430 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7431 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7432 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7433 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7434 REGNO_REG_CLASS (reg_or_subregno (out)),
7437 /* Get the memory to use and rewrite both registers to its mode. */
7438 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7440 if (GET_MODE (loc) != GET_MODE (out))
7441 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7443 if (GET_MODE (loc) != GET_MODE (in))
7444 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7446 gen_reload (loc, in, opnum, type);
7447 gen_reload (out, loc, opnum, type);
7451 /* If IN is a simple operand, use gen_move_insn. */
7452 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7453 emit_insn (gen_move_insn (out, in));
7455 #ifdef HAVE_reload_load_address
7456 else if (HAVE_reload_load_address)
7457 emit_insn (gen_reload_load_address (out, in));
7460 /* Otherwise, just write (set OUT IN) and hope for the best. */
7462 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7464 /* Return the first insn emitted.
7465 We can not just return get_last_insn, because there may have
7466 been multiple instructions emitted. Also note that gen_move_insn may
7467 emit more than one insn itself, so we can not assume that there is one
7468 insn emitted per emit_insn_before call. */
7470 return last ? NEXT_INSN (last) : get_insns ();
7473 /* Delete a previously made output-reload whose result we now believe
7474 is not needed. First we double-check.
7476 INSN is the insn now being processed.
7477 LAST_RELOAD_REG is the hard register number for which we want to delete
7478 the last output reload.
7479 J is the reload-number that originally used REG. The caller has made
7480 certain that reload J doesn't use REG any longer for input. */
7483 delete_output_reload (rtx insn, int j, int last_reload_reg)
7485 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7486 rtx reg = spill_reg_stored_to[last_reload_reg];
7489 int n_inherited = 0;
7493 /* It is possible that this reload has been only used to set another reload
7494 we eliminated earlier and thus deleted this instruction too. */
7495 if (INSN_DELETED_P (output_reload_insn))
7498 /* Get the raw pseudo-register referred to. */
7500 while (GET_CODE (reg) == SUBREG)
7501 reg = SUBREG_REG (reg);
7502 substed = reg_equiv_memory_loc[REGNO (reg)];
7504 /* This is unsafe if the operand occurs more often in the current
7505 insn than it is inherited. */
7506 for (k = n_reloads - 1; k >= 0; k--)
7508 rtx reg2 = rld[k].in;
7511 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7512 reg2 = rld[k].in_reg;
7514 if (rld[k].out && ! rld[k].out_reg)
7515 reg2 = XEXP (rld[k].in_reg, 0);
7517 while (GET_CODE (reg2) == SUBREG)
7518 reg2 = SUBREG_REG (reg2);
7519 if (rtx_equal_p (reg2, reg))
7521 if (reload_inherited[k] || reload_override_in[k] || k == j)
7524 reg2 = rld[k].out_reg;
7527 while (GET_CODE (reg2) == SUBREG)
7528 reg2 = XEXP (reg2, 0);
7529 if (rtx_equal_p (reg2, reg))
7536 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7538 n_occurrences += count_occurrences (PATTERN (insn),
7539 eliminate_regs (substed, 0,
7541 if (n_occurrences > n_inherited)
7544 /* If the pseudo-reg we are reloading is no longer referenced
7545 anywhere between the store into it and here,
7546 and no jumps or labels intervene, then the value can get
7547 here through the reload reg alone.
7548 Otherwise, give up--return. */
7549 for (i1 = NEXT_INSN (output_reload_insn);
7550 i1 != insn; i1 = NEXT_INSN (i1))
7552 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7554 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7555 && reg_mentioned_p (reg, PATTERN (i1)))
7557 /* If this is USE in front of INSN, we only have to check that
7558 there are no more references than accounted for by inheritance. */
7559 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7561 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7562 i1 = NEXT_INSN (i1);
7564 if (n_occurrences <= n_inherited && i1 == insn)
7570 /* We will be deleting the insn. Remove the spill reg information. */
7571 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7573 spill_reg_store[last_reload_reg + k] = 0;
7574 spill_reg_stored_to[last_reload_reg + k] = 0;
7577 /* The caller has already checked that REG dies or is set in INSN.
7578 It has also checked that we are optimizing, and thus some
7579 inaccuracies in the debugging information are acceptable.
7580 So we could just delete output_reload_insn. But in some cases
7581 we can improve the debugging information without sacrificing
7582 optimization - maybe even improving the code: See if the pseudo
7583 reg has been completely replaced with reload regs. If so, delete
7584 the store insn and forget we had a stack slot for the pseudo. */
7585 if (rld[j].out != rld[j].in
7586 && REG_N_DEATHS (REGNO (reg)) == 1
7587 && REG_N_SETS (REGNO (reg)) == 1
7588 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7589 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7593 /* We know that it was used only between here and the beginning of
7594 the current basic block. (We also know that the last use before
7595 INSN was the output reload we are thinking of deleting, but never
7596 mind that.) Search that range; see if any ref remains. */
7597 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7599 rtx set = single_set (i2);
7601 /* Uses which just store in the pseudo don't count,
7602 since if they are the only uses, they are dead. */
7603 if (set != 0 && SET_DEST (set) == reg)
7605 if (GET_CODE (i2) == CODE_LABEL
7606 || GET_CODE (i2) == JUMP_INSN)
7608 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7609 && reg_mentioned_p (reg, PATTERN (i2)))
7611 /* Some other ref remains; just delete the output reload we
7613 delete_address_reloads (output_reload_insn, insn);
7614 delete_insn (output_reload_insn);
7619 /* Delete the now-dead stores into this pseudo. Note that this
7620 loop also takes care of deleting output_reload_insn. */
7621 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7623 rtx set = single_set (i2);
7625 if (set != 0 && SET_DEST (set) == reg)
7627 delete_address_reloads (i2, insn);
7630 if (GET_CODE (i2) == CODE_LABEL
7631 || GET_CODE (i2) == JUMP_INSN)
7635 /* For the debugging info, say the pseudo lives in this reload reg. */
7636 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7637 alter_reg (REGNO (reg), -1);
7641 delete_address_reloads (output_reload_insn, insn);
7642 delete_insn (output_reload_insn);
7646 /* We are going to delete DEAD_INSN. Recursively delete loads of
7647 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7648 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7650 delete_address_reloads (rtx dead_insn, rtx current_insn)
7652 rtx set = single_set (dead_insn);
7653 rtx set2, dst, prev, next;
7656 rtx dst = SET_DEST (set);
7657 if (GET_CODE (dst) == MEM)
7658 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7660 /* If we deleted the store from a reloaded post_{in,de}c expression,
7661 we can delete the matching adds. */
7662 prev = PREV_INSN (dead_insn);
7663 next = NEXT_INSN (dead_insn);
7664 if (! prev || ! next)
7666 set = single_set (next);
7667 set2 = single_set (prev);
7669 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7670 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7671 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7673 dst = SET_DEST (set);
7674 if (! rtx_equal_p (dst, SET_DEST (set2))
7675 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7676 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7677 || (INTVAL (XEXP (SET_SRC (set), 1))
7678 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7680 delete_related_insns (prev);
7681 delete_related_insns (next);
7684 /* Subfunction of delete_address_reloads: process registers found in X. */
7686 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7688 rtx prev, set, dst, i2;
7690 enum rtx_code code = GET_CODE (x);
7694 const char *fmt = GET_RTX_FORMAT (code);
7695 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7698 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7699 else if (fmt[i] == 'E')
7701 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7702 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7709 if (spill_reg_order[REGNO (x)] < 0)
7712 /* Scan backwards for the insn that sets x. This might be a way back due
7714 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7716 code = GET_CODE (prev);
7717 if (code == CODE_LABEL || code == JUMP_INSN)
7719 if (GET_RTX_CLASS (code) != 'i')
7721 if (reg_set_p (x, PATTERN (prev)))
7723 if (reg_referenced_p (x, PATTERN (prev)))
7726 if (! prev || INSN_UID (prev) < reload_first_uid)
7728 /* Check that PREV only sets the reload register. */
7729 set = single_set (prev);
7732 dst = SET_DEST (set);
7733 if (GET_CODE (dst) != REG
7734 || ! rtx_equal_p (dst, x))
7736 if (! reg_set_p (dst, PATTERN (dead_insn)))
7738 /* Check if DST was used in a later insn -
7739 it might have been inherited. */
7740 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7742 if (GET_CODE (i2) == CODE_LABEL)
7746 if (reg_referenced_p (dst, PATTERN (i2)))
7748 /* If there is a reference to the register in the current insn,
7749 it might be loaded in a non-inherited reload. If no other
7750 reload uses it, that means the register is set before
7752 if (i2 == current_insn)
7754 for (j = n_reloads - 1; j >= 0; j--)
7755 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7756 || reload_override_in[j] == dst)
7758 for (j = n_reloads - 1; j >= 0; j--)
7759 if (rld[j].in && rld[j].reg_rtx == dst)
7766 if (GET_CODE (i2) == JUMP_INSN)
7768 /* If DST is still live at CURRENT_INSN, check if it is used for
7769 any reload. Note that even if CURRENT_INSN sets DST, we still
7770 have to check the reloads. */
7771 if (i2 == current_insn)
7773 for (j = n_reloads - 1; j >= 0; j--)
7774 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7775 || reload_override_in[j] == dst)
7777 /* ??? We can't finish the loop here, because dst might be
7778 allocated to a pseudo in this block if no reload in this
7779 block needs any of the classes containing DST - see
7780 spill_hard_reg. There is no easy way to tell this, so we
7781 have to scan till the end of the basic block. */
7783 if (reg_set_p (dst, PATTERN (i2)))
7787 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7788 reg_reloaded_contents[REGNO (dst)] = -1;
7792 /* Output reload-insns to reload VALUE into RELOADREG.
7793 VALUE is an autoincrement or autodecrement RTX whose operand
7794 is a register or memory location;
7795 so reloading involves incrementing that location.
7796 IN is either identical to VALUE, or some cheaper place to reload from.
7798 INC_AMOUNT is the number to increment or decrement by (always positive).
7799 This cannot be deduced from VALUE.
7801 Return the instruction that stores into RELOADREG. */
7804 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7806 /* REG or MEM to be copied and incremented. */
7807 rtx incloc = XEXP (value, 0);
7808 /* Nonzero if increment after copying. */
7809 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7815 rtx real_in = in == value ? XEXP (in, 0) : in;
7817 /* No hard register is equivalent to this register after
7818 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7819 we could inc/dec that register as well (maybe even using it for
7820 the source), but I'm not sure it's worth worrying about. */
7821 if (GET_CODE (incloc) == REG)
7822 reg_last_reload_reg[REGNO (incloc)] = 0;
7824 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7825 inc_amount = -inc_amount;
7827 inc = GEN_INT (inc_amount);
7829 /* If this is post-increment, first copy the location to the reload reg. */
7830 if (post && real_in != reloadreg)
7831 emit_insn (gen_move_insn (reloadreg, real_in));
7835 /* See if we can directly increment INCLOC. Use a method similar to
7836 that in gen_reload. */
7838 last = get_last_insn ();
7839 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7840 gen_rtx_PLUS (GET_MODE (incloc),
7843 code = recog_memoized (add_insn);
7846 extract_insn (add_insn);
7847 if (constrain_operands (1))
7849 /* If this is a pre-increment and we have incremented the value
7850 where it lives, copy the incremented value to RELOADREG to
7851 be used as an address. */
7854 emit_insn (gen_move_insn (reloadreg, incloc));
7859 delete_insns_since (last);
7862 /* If couldn't do the increment directly, must increment in RELOADREG.
7863 The way we do this depends on whether this is pre- or post-increment.
7864 For pre-increment, copy INCLOC to the reload register, increment it
7865 there, then save back. */
7869 if (in != reloadreg)
7870 emit_insn (gen_move_insn (reloadreg, real_in));
7871 emit_insn (gen_add2_insn (reloadreg, inc));
7872 store = emit_insn (gen_move_insn (incloc, reloadreg));
7877 Because this might be a jump insn or a compare, and because RELOADREG
7878 may not be available after the insn in an input reload, we must do
7879 the incrementation before the insn being reloaded for.
7881 We have already copied IN to RELOADREG. Increment the copy in
7882 RELOADREG, save that back, then decrement RELOADREG so it has
7883 the original value. */
7885 emit_insn (gen_add2_insn (reloadreg, inc));
7886 store = emit_insn (gen_move_insn (incloc, reloadreg));
7887 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7895 add_auto_inc_notes (rtx insn, rtx x)
7897 enum rtx_code code = GET_CODE (x);
7901 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7904 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7908 /* Scan all the operand sub-expressions. */
7909 fmt = GET_RTX_FORMAT (code);
7910 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7913 add_auto_inc_notes (insn, XEXP (x, i));
7914 else if (fmt[i] == 'E')
7915 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7916 add_auto_inc_notes (insn, XVECEXP (x, i, j));
7921 /* Copy EH notes from an insn to its reloads. */
7923 copy_eh_notes (rtx insn, rtx x)
7925 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7928 for (; x != 0; x = NEXT_INSN (x))
7930 if (may_trap_p (PATTERN (x)))
7932 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
7938 /* This is used by reload pass, that does emit some instructions after
7939 abnormal calls moving basic block end, but in fact it wants to emit
7940 them on the edge. Looks for abnormal call edges, find backward the
7941 proper call and fix the damage.
7943 Similar handle instructions throwing exceptions internally. */
7945 fixup_abnormal_edges (void)
7947 bool inserted = false;
7954 /* Look for cases we are interested in - calls or instructions causing
7956 for (e = bb->succ; e; e = e->succ_next)
7958 if (e->flags & EDGE_ABNORMAL_CALL)
7960 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
7961 == (EDGE_ABNORMAL | EDGE_EH))
7964 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
7966 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
7968 for (e = bb->succ; e; e = e->succ_next)
7969 if (e->flags & EDGE_FALLTHRU)
7971 /* Get past the new insns generated. Allow notes, as the insns may
7972 be already deleted. */
7973 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
7974 && !can_throw_internal (insn)
7975 && insn != bb->head)
7976 insn = PREV_INSN (insn);
7977 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
7981 insn = NEXT_INSN (insn);
7982 while (insn && insn != stop)
7984 next = NEXT_INSN (insn);
7989 /* Sometimes there's still the return value USE.
7990 If it's placed after a trapping call (i.e. that
7991 call is the last insn anyway), we have no fallthru
7992 edge. Simply delete this use and don't try to insert
7993 on the non-existent edge. */
7994 if (GET_CODE (PATTERN (insn)) != USE)
7996 /* We're not deleting it, we're moving it. */
7997 INSN_DELETED_P (insn) = 0;
7998 PREV_INSN (insn) = NULL_RTX;
7999 NEXT_INSN (insn) = NULL_RTX;
8001 insert_insn_on_edge (insn, e);
8008 /* We've possibly turned single trapping insn into multiple ones. */
8009 if (flag_non_call_exceptions)
8012 blocks = sbitmap_alloc (last_basic_block);
8013 sbitmap_ones (blocks);
8014 find_many_sub_basic_blocks (blocks);
8017 commit_edge_insertions ();
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