1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static void verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
394 static void scan_paradoxical_subregs (rtx);
395 static void count_pseudo (int);
396 static void order_regs_for_reload (struct insn_chain *);
397 static void reload_as_needed (int);
398 static void forget_old_reloads_1 (rtx, rtx, void *);
399 static int reload_reg_class_lower (const void *, const void *);
400 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
402 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
404 static int reload_reg_free_p (unsigned int, int, enum reload_type);
405 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
407 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
409 static int function_invariant_p (rtx);
410 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
411 static int allocate_reload_reg (struct insn_chain *, int, int);
412 static int conflicts_with_override (rtx);
413 static void failed_reload (rtx, int);
414 static int set_reload_reg (int, int);
415 static void choose_reload_regs_init (struct insn_chain *, rtx *);
416 static void choose_reload_regs (struct insn_chain *);
417 static void merge_assigned_reloads (rtx);
418 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
420 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
422 static void do_input_reload (struct insn_chain *, struct reload *, int);
423 static void do_output_reload (struct insn_chain *, struct reload *, int);
424 static bool inherit_piecemeal_p (int, int);
425 static void emit_reload_insns (struct insn_chain *);
426 static void delete_output_reload (rtx, int, int);
427 static void delete_address_reloads (rtx, rtx);
428 static void delete_address_reloads_1 (rtx, rtx, rtx);
429 static rtx inc_for_reload (rtx, rtx, rtx, int);
431 static void add_auto_inc_notes (rtx, rtx);
433 static void copy_eh_notes (rtx, rtx);
435 /* Initialize the reload pass once per compilation. */
442 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
443 Set spill_indirect_levels to the number of levels such addressing is
444 permitted, zero if it is not permitted at all. */
447 = gen_rtx_MEM (Pmode,
450 LAST_VIRTUAL_REGISTER + 1),
452 spill_indirect_levels = 0;
454 while (memory_address_p (QImode, tem))
456 spill_indirect_levels++;
457 tem = gen_rtx_MEM (Pmode, tem);
460 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
462 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
463 indirect_symref_ok = memory_address_p (QImode, tem);
465 /* See if reg+reg is a valid (and offsettable) address. */
467 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
469 tem = gen_rtx_PLUS (Pmode,
470 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
471 gen_rtx_REG (Pmode, i));
473 /* This way, we make sure that reg+reg is an offsettable address. */
474 tem = plus_constant (tem, 4);
476 if (memory_address_p (QImode, tem))
478 double_reg_address_ok = 1;
483 /* Initialize obstack for our rtl allocation. */
484 gcc_obstack_init (&reload_obstack);
485 reload_startobj = obstack_alloc (&reload_obstack, 0);
487 INIT_REG_SET (&spilled_pseudos);
488 INIT_REG_SET (&pseudos_counted);
489 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
492 /* List of insn chains that are currently unused. */
493 static struct insn_chain *unused_insn_chains = 0;
495 /* Allocate an empty insn_chain structure. */
497 new_insn_chain (void)
499 struct insn_chain *c;
501 if (unused_insn_chains == 0)
503 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
504 INIT_REG_SET (&c->live_throughout);
505 INIT_REG_SET (&c->dead_or_set);
509 c = unused_insn_chains;
510 unused_insn_chains = c->next;
512 c->is_caller_save_insn = 0;
513 c->need_operand_change = 0;
519 /* Small utility function to set all regs in hard reg set TO which are
520 allocated to pseudos in regset FROM. */
523 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 EXECUTE_IF_SET_IN_REG_SET
528 (from, FIRST_PSEUDO_REGISTER, regno,
530 int r = reg_renumber[regno];
535 /* reload_combine uses the information from
536 BASIC_BLOCK->global_live_at_start, which might still
537 contain registers that have not actually been allocated
538 since they have an equivalence. */
539 if (! reload_completed)
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
587 else if (!REG_P (regno_reg_rtx[regno])
588 || REGNO (regno_reg_rtx[regno]) != regno)
589 *loc = regno_reg_rtx[regno];
595 else if (code == MEM)
597 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
601 /* Process each of our operands recursively. */
602 fmt = GET_RTX_FORMAT (code);
603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
605 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
606 else if (*fmt == 'E')
607 for (j = 0; j < XVECLEN (x, i); j++)
608 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
612 /* Global variables used by reload and its subroutines. */
614 /* Set during calculate_needs if an insn needs register elimination. */
615 static int something_needs_elimination;
616 /* Set during calculate_needs if an insn needs an operand changed. */
617 int something_needs_operands_changed;
619 /* Nonzero means we couldn't get enough spill regs. */
622 /* Main entry point for the reload pass.
624 FIRST is the first insn of the function being compiled.
626 GLOBAL nonzero means we were called from global_alloc
627 and should attempt to reallocate any pseudoregs that we
628 displace from hard regs we will use for reloads.
629 If GLOBAL is zero, we do not have enough information to do that,
630 so any pseudo reg that is spilled must go to the stack.
632 Return value is nonzero if reload failed
633 and we must not do any more for this function. */
636 reload (rtx first, int global)
640 struct elim_table *ep;
643 /* Make sure even insns with volatile mem refs are recognizable. */
648 reload_firstobj = obstack_alloc (&reload_obstack, 0);
650 /* Make sure that the last insn in the chain
651 is not something that needs reloading. */
652 emit_note (NOTE_INSN_DELETED);
654 /* Enable find_equiv_reg to distinguish insns made by reload. */
655 reload_first_uid = get_max_uid ();
657 #ifdef SECONDARY_MEMORY_NEEDED
658 /* Initialize the secondary memory table. */
659 clear_secondary_mem ();
662 /* We don't have a stack slot for any spill reg yet. */
663 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
664 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
666 /* Initialize the save area information for caller-save, in case some
670 /* Compute which hard registers are now in use
671 as homes for pseudo registers.
672 This is done here rather than (eg) in global_alloc
673 because this point is reached even if not optimizing. */
674 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
677 /* A function that receives a nonlocal goto must save all call-saved
679 if (current_function_has_nonlocal_label)
680 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
681 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
682 regs_ever_live[i] = 1;
684 #ifdef NON_SAVING_SETJMP
685 /* A function that calls setjmp should save and restore all the
686 call-saved registers on a system where longjmp clobbers them. */
687 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
690 if (! call_used_regs[i])
691 regs_ever_live[i] = 1;
695 /* Find all the pseudo registers that didn't get hard regs
696 but do have known equivalent constants or memory slots.
697 These include parameters (known equivalent to parameter slots)
698 and cse'd or loop-moved constant memory addresses.
700 Record constant equivalents in reg_equiv_constant
701 so they will be substituted by find_reloads.
702 Record memory equivalents in reg_mem_equiv so they can
703 be substituted eventually by altering the REG-rtx's. */
705 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
706 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
707 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
708 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
709 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
710 reg_old_renumber = xcalloc (max_regno, sizeof (short));
711 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
712 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
713 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
715 CLEAR_HARD_REG_SET (bad_spill_regs_global);
717 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
718 to. Also find all paradoxical subregs and find largest such for
721 num_eliminable_invariants = 0;
722 for (insn = first; insn; insn = NEXT_INSN (insn))
724 rtx set = single_set (insn);
726 /* We may introduce USEs that we want to remove at the end, so
727 we'll mark them with QImode. Make sure there are no
728 previously-marked insns left by say regmove. */
729 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
730 && GET_MODE (insn) != VOIDmode)
731 PUT_MODE (insn, VOIDmode);
733 if (set != 0 && REG_P (SET_DEST (set)))
735 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
737 #ifdef LEGITIMATE_PIC_OPERAND_P
738 && (! function_invariant_p (XEXP (note, 0))
740 /* A function invariant is often CONSTANT_P but may
741 include a register. We promise to only pass
742 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
743 || (CONSTANT_P (XEXP (note, 0))
744 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
748 rtx x = XEXP (note, 0);
749 i = REGNO (SET_DEST (set));
750 if (i > LAST_VIRTUAL_REGISTER)
752 /* It can happen that a REG_EQUIV note contains a MEM
753 that is not a legitimate memory operand. As later
754 stages of reload assume that all addresses found
755 in the reg_equiv_* arrays were originally legitimate,
756 we ignore such REG_EQUIV notes. */
757 if (memory_operand (x, VOIDmode))
759 /* Always unshare the equivalence, so we can
760 substitute into this insn without touching the
762 reg_equiv_memory_loc[i] = copy_rtx (x);
764 else if (function_invariant_p (x))
766 if (GET_CODE (x) == PLUS)
768 /* This is PLUS of frame pointer and a constant,
769 and might be shared. Unshare it. */
770 reg_equiv_constant[i] = copy_rtx (x);
771 num_eliminable_invariants++;
773 else if (x == frame_pointer_rtx
774 || x == arg_pointer_rtx)
776 reg_equiv_constant[i] = x;
777 num_eliminable_invariants++;
779 else if (LEGITIMATE_CONSTANT_P (x))
780 reg_equiv_constant[i] = x;
783 reg_equiv_memory_loc[i]
784 = force_const_mem (GET_MODE (SET_DEST (set)), x);
785 if (!reg_equiv_memory_loc[i])
792 /* If this register is being made equivalent to a MEM
793 and the MEM is not SET_SRC, the equivalencing insn
794 is one with the MEM as a SET_DEST and it occurs later.
795 So don't mark this insn now. */
797 || rtx_equal_p (SET_SRC (set), x))
799 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
804 /* If this insn is setting a MEM from a register equivalent to it,
805 this is the equivalencing insn. */
806 else if (set && MEM_P (SET_DEST (set))
807 && REG_P (SET_SRC (set))
808 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
809 && rtx_equal_p (SET_DEST (set),
810 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
811 reg_equiv_init[REGNO (SET_SRC (set))]
812 = gen_rtx_INSN_LIST (VOIDmode, insn,
813 reg_equiv_init[REGNO (SET_SRC (set))]);
816 scan_paradoxical_subregs (PATTERN (insn));
821 first_label_num = get_first_label_num ();
822 num_labels = max_label_num () - first_label_num;
824 /* Allocate the tables used to store offset information at labels. */
825 /* We used to use alloca here, but the size of what it would try to
826 allocate would occasionally cause it to exceed the stack limit and
827 cause a core dump. */
828 offsets_known_at = xmalloc (num_labels);
829 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
831 /* Alter each pseudo-reg rtx to contain its hard reg number.
832 Assign stack slots to the pseudos that lack hard regs or equivalents.
833 Do not touch virtual registers. */
835 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
838 /* If we have some registers we think can be eliminated, scan all insns to
839 see if there is an insn that sets one of these registers to something
840 other than itself plus a constant. If so, the register cannot be
841 eliminated. Doing this scan here eliminates an extra pass through the
842 main reload loop in the most common case where register elimination
844 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
846 || GET_CODE (insn) == CALL_INSN)
847 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
849 maybe_fix_stack_asms ();
851 insns_need_reload = 0;
852 something_needs_elimination = 0;
854 /* Initialize to -1, which means take the first spill register. */
857 /* Spill any hard regs that we know we can't eliminate. */
858 CLEAR_HARD_REG_SET (used_spill_regs);
859 /* There can be multiple ways to eliminate a register;
860 they should be listed adjacently.
861 Elimination for any register fails only if all possible ways fail. */
862 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
865 int can_eliminate = 0;
868 can_eliminate |= ep->can_eliminate;
871 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
873 spill_hard_reg (from, 1);
876 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
877 if (frame_pointer_needed)
878 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
880 finish_spills (global);
882 /* From now on, we may need to generate moves differently. We may also
883 allow modifications of insns which cause them to not be recognized.
884 Any such modifications will be cleaned up during reload itself. */
885 reload_in_progress = 1;
887 /* This loop scans the entire function each go-round
888 and repeats until one repetition spills no additional hard regs. */
891 int something_changed;
894 HOST_WIDE_INT starting_frame_size;
896 /* Round size of stack frame to stack_alignment_needed. This must be done
897 here because the stack size may be a part of the offset computation
898 for register elimination, and there might have been new stack slots
899 created in the last iteration of this loop. */
900 if (cfun->stack_alignment_needed)
901 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
903 starting_frame_size = get_frame_size ();
905 set_initial_elim_offsets ();
906 set_initial_label_offsets ();
908 /* For each pseudo register that has an equivalent location defined,
909 try to eliminate any eliminable registers (such as the frame pointer)
910 assuming initial offsets for the replacement register, which
913 If the resulting location is directly addressable, substitute
914 the MEM we just got directly for the old REG.
916 If it is not addressable but is a constant or the sum of a hard reg
917 and constant, it is probably not addressable because the constant is
918 out of range, in that case record the address; we will generate
919 hairy code to compute the address in a register each time it is
920 needed. Similarly if it is a hard register, but one that is not
921 valid as an address register.
923 If the location is not addressable, but does not have one of the
924 above forms, assign a stack slot. We have to do this to avoid the
925 potential of producing lots of reloads if, e.g., a location involves
926 a pseudo that didn't get a hard register and has an equivalent memory
927 location that also involves a pseudo that didn't get a hard register.
929 Perhaps at some point we will improve reload_when_needed handling
930 so this problem goes away. But that's very hairy. */
932 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
933 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
935 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
937 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
939 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
940 else if (CONSTANT_P (XEXP (x, 0))
941 || (REG_P (XEXP (x, 0))
942 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
943 || (GET_CODE (XEXP (x, 0)) == PLUS
944 && REG_P (XEXP (XEXP (x, 0), 0))
945 && (REGNO (XEXP (XEXP (x, 0), 0))
946 < FIRST_PSEUDO_REGISTER)
947 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
948 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
951 /* Make a new stack slot. Then indicate that something
952 changed so we go back and recompute offsets for
953 eliminable registers because the allocation of memory
954 below might change some offset. reg_equiv_{mem,address}
955 will be set up for this pseudo on the next pass around
957 reg_equiv_memory_loc[i] = 0;
958 reg_equiv_init[i] = 0;
963 if (caller_save_needed)
966 /* If we allocated another stack slot, redo elimination bookkeeping. */
967 if (starting_frame_size != get_frame_size ())
970 if (caller_save_needed)
972 save_call_clobbered_regs ();
973 /* That might have allocated new insn_chain structures. */
974 reload_firstobj = obstack_alloc (&reload_obstack, 0);
977 calculate_needs_all_insns (global);
979 CLEAR_REG_SET (&spilled_pseudos);
982 something_changed = 0;
984 /* If we allocated any new memory locations, make another pass
985 since it might have changed elimination offsets. */
986 if (starting_frame_size != get_frame_size ())
987 something_changed = 1;
990 HARD_REG_SET to_spill;
991 CLEAR_HARD_REG_SET (to_spill);
992 update_eliminables (&to_spill);
993 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
994 if (TEST_HARD_REG_BIT (to_spill, i))
996 spill_hard_reg (i, 1);
999 /* Regardless of the state of spills, if we previously had
1000 a register that we thought we could eliminate, but now can
1001 not eliminate, we must run another pass.
1003 Consider pseudos which have an entry in reg_equiv_* which
1004 reference an eliminable register. We must make another pass
1005 to update reg_equiv_* so that we do not substitute in the
1006 old value from when we thought the elimination could be
1008 something_changed = 1;
1012 select_reload_regs ();
1016 if (insns_need_reload != 0 || did_spill)
1017 something_changed |= finish_spills (global);
1019 if (! something_changed)
1022 if (caller_save_needed)
1023 delete_caller_save_insns ();
1025 obstack_free (&reload_obstack, reload_firstobj);
1028 /* If global-alloc was run, notify it of any register eliminations we have
1031 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1032 if (ep->can_eliminate)
1033 mark_elimination (ep->from, ep->to);
1035 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1036 If that insn didn't set the register (i.e., it copied the register to
1037 memory), just delete that insn instead of the equivalencing insn plus
1038 anything now dead. If we call delete_dead_insn on that insn, we may
1039 delete the insn that actually sets the register if the register dies
1040 there and that is incorrect. */
1042 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1044 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1047 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1049 rtx equiv_insn = XEXP (list, 0);
1051 /* If we already deleted the insn or if it may trap, we can't
1052 delete it. The latter case shouldn't happen, but can
1053 if an insn has a variable address, gets a REG_EH_REGION
1054 note added to it, and then gets converted into an load
1055 from a constant address. */
1056 if (GET_CODE (equiv_insn) == NOTE
1057 || can_throw_internal (equiv_insn))
1059 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1060 delete_dead_insn (equiv_insn);
1062 SET_INSN_DELETED (equiv_insn);
1067 /* Use the reload registers where necessary
1068 by generating move instructions to move the must-be-register
1069 values into or out of the reload registers. */
1071 if (insns_need_reload != 0 || something_needs_elimination
1072 || something_needs_operands_changed)
1074 HOST_WIDE_INT old_frame_size = get_frame_size ();
1076 reload_as_needed (global);
1078 if (old_frame_size != get_frame_size ())
1082 verify_initial_elim_offsets ();
1085 /* If we were able to eliminate the frame pointer, show that it is no
1086 longer live at the start of any basic block. If it ls live by
1087 virtue of being in a pseudo, that pseudo will be marked live
1088 and hence the frame pointer will be known to be live via that
1091 if (! frame_pointer_needed)
1093 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1094 HARD_FRAME_POINTER_REGNUM);
1096 /* Come here (with failure set nonzero) if we can't get enough spill regs
1097 and we decide not to abort about it. */
1100 CLEAR_REG_SET (&spilled_pseudos);
1101 reload_in_progress = 0;
1103 /* Now eliminate all pseudo regs by modifying them into
1104 their equivalent memory references.
1105 The REG-rtx's for the pseudos are modified in place,
1106 so all insns that used to refer to them now refer to memory.
1108 For a reg that has a reg_equiv_address, all those insns
1109 were changed by reloading so that no insns refer to it any longer;
1110 but the DECL_RTL of a variable decl may refer to it,
1111 and if so this causes the debugging info to mention the variable. */
1113 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1117 if (reg_equiv_mem[i])
1118 addr = XEXP (reg_equiv_mem[i], 0);
1120 if (reg_equiv_address[i])
1121 addr = reg_equiv_address[i];
1125 if (reg_renumber[i] < 0)
1127 rtx reg = regno_reg_rtx[i];
1129 REG_USERVAR_P (reg) = 0;
1130 PUT_CODE (reg, MEM);
1131 XEXP (reg, 0) = addr;
1132 if (reg_equiv_memory_loc[i])
1133 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1136 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1137 = MEM_SCALAR_P (reg) = 0;
1138 MEM_ATTRS (reg) = 0;
1141 else if (reg_equiv_mem[i])
1142 XEXP (reg_equiv_mem[i], 0) = addr;
1146 /* We must set reload_completed now since the cleanup_subreg_operands call
1147 below will re-recognize each insn and reload may have generated insns
1148 which are only valid during and after reload. */
1149 reload_completed = 1;
1151 /* Make a pass over all the insns and delete all USEs which we inserted
1152 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1153 notes. Delete all CLOBBER insns, except those that refer to the return
1154 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1155 from misarranging variable-array code, and simplify (subreg (reg))
1156 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1157 are no longer useful or accurate. Strip and regenerate REG_INC notes
1158 that may have been moved around. */
1160 for (insn = first; insn; insn = NEXT_INSN (insn))
1165 if (GET_CODE (insn) == CALL_INSN)
1166 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1167 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1169 if ((GET_CODE (PATTERN (insn)) == USE
1170 /* We mark with QImode USEs introduced by reload itself. */
1171 && (GET_MODE (insn) == QImode
1172 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1173 || (GET_CODE (PATTERN (insn)) == CLOBBER
1174 && (!MEM_P (XEXP (PATTERN (insn), 0))
1175 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1176 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1177 && XEXP (XEXP (PATTERN (insn), 0), 0)
1178 != stack_pointer_rtx))
1179 && (!REG_P (XEXP (PATTERN (insn), 0))
1180 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1186 /* Some CLOBBERs may survive until here and still reference unassigned
1187 pseudos with const equivalent, which may in turn cause ICE in later
1188 passes if the reference remains in place. */
1189 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1190 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1191 VOIDmode, PATTERN (insn));
1193 pnote = ®_NOTES (insn);
1196 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1197 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1198 || REG_NOTE_KIND (*pnote) == REG_INC
1199 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1200 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1201 *pnote = XEXP (*pnote, 1);
1203 pnote = &XEXP (*pnote, 1);
1207 add_auto_inc_notes (insn, PATTERN (insn));
1210 /* And simplify (subreg (reg)) if it appears as an operand. */
1211 cleanup_subreg_operands (insn);
1214 /* If we are doing stack checking, give a warning if this function's
1215 frame size is larger than we expect. */
1216 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1218 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1219 static int verbose_warned = 0;
1221 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1222 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1223 size += UNITS_PER_WORD;
1225 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1227 warning ("frame size too large for reliable stack checking");
1228 if (! verbose_warned)
1230 warning ("try reducing the number of local variables");
1236 /* Indicate that we no longer have known memory locations or constants. */
1237 if (reg_equiv_constant)
1238 free (reg_equiv_constant);
1239 reg_equiv_constant = 0;
1240 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1241 reg_equiv_memory_loc = 0;
1243 if (offsets_known_at)
1244 free (offsets_known_at);
1248 free (reg_equiv_mem);
1249 free (reg_equiv_init);
1250 free (reg_equiv_address);
1251 free (reg_max_ref_width);
1252 free (reg_old_renumber);
1253 free (pseudo_previous_regs);
1254 free (pseudo_forbidden_regs);
1256 CLEAR_HARD_REG_SET (used_spill_regs);
1257 for (i = 0; i < n_spills; i++)
1258 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1260 /* Free all the insn_chain structures at once. */
1261 obstack_free (&reload_obstack, reload_startobj);
1262 unused_insn_chains = 0;
1263 fixup_abnormal_edges ();
1265 /* Replacing pseudos with their memory equivalents might have
1266 created shared rtx. Subsequent passes would get confused
1267 by this, so unshare everything here. */
1268 unshare_all_rtl_again (first);
1270 #ifdef STACK_BOUNDARY
1271 /* init_emit has set the alignment of the hard frame pointer
1272 to STACK_BOUNDARY. It is very likely no longer valid if
1273 the hard frame pointer was used for register allocation. */
1274 if (!frame_pointer_needed)
1275 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1281 /* Yet another special case. Unfortunately, reg-stack forces people to
1282 write incorrect clobbers in asm statements. These clobbers must not
1283 cause the register to appear in bad_spill_regs, otherwise we'll call
1284 fatal_insn later. We clear the corresponding regnos in the live
1285 register sets to avoid this.
1286 The whole thing is rather sick, I'm afraid. */
1289 maybe_fix_stack_asms (void)
1292 const char *constraints[MAX_RECOG_OPERANDS];
1293 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1294 struct insn_chain *chain;
1296 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1299 HARD_REG_SET clobbered, allowed;
1302 if (! INSN_P (chain->insn)
1303 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1305 pat = PATTERN (chain->insn);
1306 if (GET_CODE (pat) != PARALLEL)
1309 CLEAR_HARD_REG_SET (clobbered);
1310 CLEAR_HARD_REG_SET (allowed);
1312 /* First, make a mask of all stack regs that are clobbered. */
1313 for (i = 0; i < XVECLEN (pat, 0); i++)
1315 rtx t = XVECEXP (pat, 0, i);
1316 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1317 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1320 /* Get the operand values and constraints out of the insn. */
1321 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1322 constraints, operand_mode);
1324 /* For every operand, see what registers are allowed. */
1325 for (i = 0; i < noperands; i++)
1327 const char *p = constraints[i];
1328 /* For every alternative, we compute the class of registers allowed
1329 for reloading in CLS, and merge its contents into the reg set
1331 int cls = (int) NO_REGS;
1337 if (c == '\0' || c == ',' || c == '#')
1339 /* End of one alternative - mark the regs in the current
1340 class, and reset the class. */
1341 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1347 } while (c != '\0' && c != ',');
1355 case '=': case '+': case '*': case '%': case '?': case '!':
1356 case '0': case '1': case '2': case '3': case '4': case 'm':
1357 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1358 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1359 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1364 cls = (int) reg_class_subunion[cls]
1365 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1370 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1374 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1375 cls = (int) reg_class_subunion[cls]
1376 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1378 cls = (int) reg_class_subunion[cls]
1379 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1381 p += CONSTRAINT_LEN (c, p);
1384 /* Those of the registers which are clobbered, but allowed by the
1385 constraints, must be usable as reload registers. So clear them
1386 out of the life information. */
1387 AND_HARD_REG_SET (allowed, clobbered);
1388 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1389 if (TEST_HARD_REG_BIT (allowed, i))
1391 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1392 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1399 /* Copy the global variables n_reloads and rld into the corresponding elts
1402 copy_reloads (struct insn_chain *chain)
1404 chain->n_reloads = n_reloads;
1405 chain->rld = obstack_alloc (&reload_obstack,
1406 n_reloads * sizeof (struct reload));
1407 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1408 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1411 /* Walk the chain of insns, and determine for each whether it needs reloads
1412 and/or eliminations. Build the corresponding insns_need_reload list, and
1413 set something_needs_elimination as appropriate. */
1415 calculate_needs_all_insns (int global)
1417 struct insn_chain **pprev_reload = &insns_need_reload;
1418 struct insn_chain *chain, *next = 0;
1420 something_needs_elimination = 0;
1422 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1423 for (chain = reload_insn_chain; chain != 0; chain = next)
1425 rtx insn = chain->insn;
1429 /* Clear out the shortcuts. */
1430 chain->n_reloads = 0;
1431 chain->need_elim = 0;
1432 chain->need_reload = 0;
1433 chain->need_operand_change = 0;
1435 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1436 include REG_LABEL), we need to see what effects this has on the
1437 known offsets at labels. */
1439 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1440 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1441 set_label_offsets (insn, insn, 0);
1445 rtx old_body = PATTERN (insn);
1446 int old_code = INSN_CODE (insn);
1447 rtx old_notes = REG_NOTES (insn);
1448 int did_elimination = 0;
1449 int operands_changed = 0;
1450 rtx set = single_set (insn);
1452 /* Skip insns that only set an equivalence. */
1453 if (set && REG_P (SET_DEST (set))
1454 && reg_renumber[REGNO (SET_DEST (set))] < 0
1455 && reg_equiv_constant[REGNO (SET_DEST (set))])
1458 /* If needed, eliminate any eliminable registers. */
1459 if (num_eliminable || num_eliminable_invariants)
1460 did_elimination = eliminate_regs_in_insn (insn, 0);
1462 /* Analyze the instruction. */
1463 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1464 global, spill_reg_order);
1466 /* If a no-op set needs more than one reload, this is likely
1467 to be something that needs input address reloads. We
1468 can't get rid of this cleanly later, and it is of no use
1469 anyway, so discard it now.
1470 We only do this when expensive_optimizations is enabled,
1471 since this complements reload inheritance / output
1472 reload deletion, and it can make debugging harder. */
1473 if (flag_expensive_optimizations && n_reloads > 1)
1475 rtx set = single_set (insn);
1477 && SET_SRC (set) == SET_DEST (set)
1478 && REG_P (SET_SRC (set))
1479 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1482 /* Delete it from the reload chain. */
1484 chain->prev->next = next;
1486 reload_insn_chain = next;
1488 next->prev = chain->prev;
1489 chain->next = unused_insn_chains;
1490 unused_insn_chains = chain;
1495 update_eliminable_offsets ();
1497 /* Remember for later shortcuts which insns had any reloads or
1498 register eliminations. */
1499 chain->need_elim = did_elimination;
1500 chain->need_reload = n_reloads > 0;
1501 chain->need_operand_change = operands_changed;
1503 /* Discard any register replacements done. */
1504 if (did_elimination)
1506 obstack_free (&reload_obstack, reload_insn_firstobj);
1507 PATTERN (insn) = old_body;
1508 INSN_CODE (insn) = old_code;
1509 REG_NOTES (insn) = old_notes;
1510 something_needs_elimination = 1;
1513 something_needs_operands_changed |= operands_changed;
1517 copy_reloads (chain);
1518 *pprev_reload = chain;
1519 pprev_reload = &chain->next_need_reload;
1526 /* Comparison function for qsort to decide which of two reloads
1527 should be handled first. *P1 and *P2 are the reload numbers. */
1530 reload_reg_class_lower (const void *r1p, const void *r2p)
1532 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1535 /* Consider required reloads before optional ones. */
1536 t = rld[r1].optional - rld[r2].optional;
1540 /* Count all solitary classes before non-solitary ones. */
1541 t = ((reg_class_size[(int) rld[r2].class] == 1)
1542 - (reg_class_size[(int) rld[r1].class] == 1));
1546 /* Aside from solitaires, consider all multi-reg groups first. */
1547 t = rld[r2].nregs - rld[r1].nregs;
1551 /* Consider reloads in order of increasing reg-class number. */
1552 t = (int) rld[r1].class - (int) rld[r2].class;
1556 /* If reloads are equally urgent, sort by reload number,
1557 so that the results of qsort leave nothing to chance. */
1561 /* The cost of spilling each hard reg. */
1562 static int spill_cost[FIRST_PSEUDO_REGISTER];
1564 /* When spilling multiple hard registers, we use SPILL_COST for the first
1565 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1566 only the first hard reg for a multi-reg pseudo. */
1567 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1569 /* Update the spill cost arrays, considering that pseudo REG is live. */
1572 count_pseudo (int reg)
1574 int freq = REG_FREQ (reg);
1575 int r = reg_renumber[reg];
1578 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1579 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1582 SET_REGNO_REG_SET (&pseudos_counted, reg);
1587 spill_add_cost[r] += freq;
1589 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1591 spill_cost[r + nregs] += freq;
1594 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1595 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1598 order_regs_for_reload (struct insn_chain *chain)
1601 HARD_REG_SET used_by_pseudos;
1602 HARD_REG_SET used_by_pseudos2;
1604 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1606 memset (spill_cost, 0, sizeof spill_cost);
1607 memset (spill_add_cost, 0, sizeof spill_add_cost);
1609 /* Count number of uses of each hard reg by pseudo regs allocated to it
1610 and then order them by decreasing use. First exclude hard registers
1611 that are live in or across this insn. */
1613 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1614 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1615 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1616 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1618 /* Now find out which pseudos are allocated to it, and update
1620 CLEAR_REG_SET (&pseudos_counted);
1622 EXECUTE_IF_SET_IN_REG_SET
1623 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1627 EXECUTE_IF_SET_IN_REG_SET
1628 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1632 CLEAR_REG_SET (&pseudos_counted);
1635 /* Vector of reload-numbers showing the order in which the reloads should
1637 static short reload_order[MAX_RELOADS];
1639 /* This is used to keep track of the spill regs used in one insn. */
1640 static HARD_REG_SET used_spill_regs_local;
1642 /* We decided to spill hard register SPILLED, which has a size of
1643 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1644 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1645 update SPILL_COST/SPILL_ADD_COST. */
1648 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1650 int r = reg_renumber[reg];
1651 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1653 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1654 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1657 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1659 spill_add_cost[r] -= REG_FREQ (reg);
1661 spill_cost[r + nregs] -= REG_FREQ (reg);
1664 /* Find reload register to use for reload number ORDER. */
1667 find_reg (struct insn_chain *chain, int order)
1669 int rnum = reload_order[order];
1670 struct reload *rl = rld + rnum;
1671 int best_cost = INT_MAX;
1675 HARD_REG_SET not_usable;
1676 HARD_REG_SET used_by_other_reload;
1678 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1679 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1680 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1682 CLEAR_HARD_REG_SET (used_by_other_reload);
1683 for (k = 0; k < order; k++)
1685 int other = reload_order[k];
1687 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1688 for (j = 0; j < rld[other].nregs; j++)
1689 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1692 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1694 unsigned int regno = i;
1696 if (! TEST_HARD_REG_BIT (not_usable, regno)
1697 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1698 && HARD_REGNO_MODE_OK (regno, rl->mode))
1700 int this_cost = spill_cost[regno];
1702 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1704 for (j = 1; j < this_nregs; j++)
1706 this_cost += spill_add_cost[regno + j];
1707 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1708 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1713 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1715 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1717 if (this_cost < best_cost
1718 /* Among registers with equal cost, prefer caller-saved ones, or
1719 use REG_ALLOC_ORDER if it is defined. */
1720 || (this_cost == best_cost
1721 #ifdef REG_ALLOC_ORDER
1722 && (inv_reg_alloc_order[regno]
1723 < inv_reg_alloc_order[best_reg])
1725 && call_used_regs[regno]
1726 && ! call_used_regs[best_reg]
1731 best_cost = this_cost;
1739 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1741 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1742 rl->regno = best_reg;
1744 EXECUTE_IF_SET_IN_REG_SET
1745 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1747 count_spilled_pseudo (best_reg, rl->nregs, j);
1750 EXECUTE_IF_SET_IN_REG_SET
1751 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1753 count_spilled_pseudo (best_reg, rl->nregs, j);
1756 for (i = 0; i < rl->nregs; i++)
1758 if (spill_cost[best_reg + i] != 0
1759 || spill_add_cost[best_reg + i] != 0)
1761 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1766 /* Find more reload regs to satisfy the remaining need of an insn, which
1768 Do it by ascending class number, since otherwise a reg
1769 might be spilled for a big class and might fail to count
1770 for a smaller class even though it belongs to that class. */
1773 find_reload_regs (struct insn_chain *chain)
1777 /* In order to be certain of getting the registers we need,
1778 we must sort the reloads into order of increasing register class.
1779 Then our grabbing of reload registers will parallel the process
1780 that provided the reload registers. */
1781 for (i = 0; i < chain->n_reloads; i++)
1783 /* Show whether this reload already has a hard reg. */
1784 if (chain->rld[i].reg_rtx)
1786 int regno = REGNO (chain->rld[i].reg_rtx);
1787 chain->rld[i].regno = regno;
1789 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1792 chain->rld[i].regno = -1;
1793 reload_order[i] = i;
1796 n_reloads = chain->n_reloads;
1797 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1799 CLEAR_HARD_REG_SET (used_spill_regs_local);
1802 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1804 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1806 /* Compute the order of preference for hard registers to spill. */
1808 order_regs_for_reload (chain);
1810 for (i = 0; i < n_reloads; i++)
1812 int r = reload_order[i];
1814 /* Ignore reloads that got marked inoperative. */
1815 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1816 && ! rld[r].optional
1817 && rld[r].regno == -1)
1818 if (! find_reg (chain, i))
1820 spill_failure (chain->insn, rld[r].class);
1826 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1827 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1829 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1833 select_reload_regs (void)
1835 struct insn_chain *chain;
1837 /* Try to satisfy the needs for each insn. */
1838 for (chain = insns_need_reload; chain != 0;
1839 chain = chain->next_need_reload)
1840 find_reload_regs (chain);
1843 /* Delete all insns that were inserted by emit_caller_save_insns during
1846 delete_caller_save_insns (void)
1848 struct insn_chain *c = reload_insn_chain;
1852 while (c != 0 && c->is_caller_save_insn)
1854 struct insn_chain *next = c->next;
1857 if (c == reload_insn_chain)
1858 reload_insn_chain = next;
1862 next->prev = c->prev;
1864 c->prev->next = next;
1865 c->next = unused_insn_chains;
1866 unused_insn_chains = c;
1874 /* Handle the failure to find a register to spill.
1875 INSN should be one of the insns which needed this particular spill reg. */
1878 spill_failure (rtx insn, enum reg_class class)
1880 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1881 if (asm_noperands (PATTERN (insn)) >= 0)
1882 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1883 reg_class_names[class]);
1886 error ("unable to find a register to spill in class `%s'",
1887 reg_class_names[class]);
1888 fatal_insn ("this is the insn:", insn);
1892 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1893 data that is dead in INSN. */
1896 delete_dead_insn (rtx insn)
1898 rtx prev = prev_real_insn (insn);
1901 /* If the previous insn sets a register that dies in our insn, delete it
1903 if (prev && GET_CODE (PATTERN (prev)) == SET
1904 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1905 && reg_mentioned_p (prev_dest, PATTERN (insn))
1906 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1907 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1908 delete_dead_insn (prev);
1910 SET_INSN_DELETED (insn);
1913 /* Modify the home of pseudo-reg I.
1914 The new home is present in reg_renumber[I].
1916 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1917 or it may be -1, meaning there is none or it is not relevant.
1918 This is used so that all pseudos spilled from a given hard reg
1919 can share one stack slot. */
1922 alter_reg (int i, int from_reg)
1924 /* When outputting an inline function, this can happen
1925 for a reg that isn't actually used. */
1926 if (regno_reg_rtx[i] == 0)
1929 /* If the reg got changed to a MEM at rtl-generation time,
1931 if (!REG_P (regno_reg_rtx[i]))
1934 /* Modify the reg-rtx to contain the new hard reg
1935 number or else to contain its pseudo reg number. */
1936 REGNO (regno_reg_rtx[i])
1937 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1939 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1940 allocate a stack slot for it. */
1942 if (reg_renumber[i] < 0
1943 && REG_N_REFS (i) > 0
1944 && reg_equiv_constant[i] == 0
1945 && reg_equiv_memory_loc[i] == 0)
1948 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1949 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1952 /* Each pseudo reg has an inherent size which comes from its own mode,
1953 and a total size which provides room for paradoxical subregs
1954 which refer to the pseudo reg in wider modes.
1956 We can use a slot already allocated if it provides both
1957 enough inherent space and enough total space.
1958 Otherwise, we allocate a new slot, making sure that it has no less
1959 inherent space, and no less total space, then the previous slot. */
1962 /* No known place to spill from => no slot to reuse. */
1963 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1964 inherent_size == total_size ? 0 : -1);
1965 if (BYTES_BIG_ENDIAN)
1966 /* Cancel the big-endian correction done in assign_stack_local.
1967 Get the address of the beginning of the slot.
1968 This is so we can do a big-endian correction unconditionally
1970 adjust = inherent_size - total_size;
1972 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1974 /* Nothing can alias this slot except this pseudo. */
1975 set_mem_alias_set (x, new_alias_set ());
1978 /* Reuse a stack slot if possible. */
1979 else if (spill_stack_slot[from_reg] != 0
1980 && spill_stack_slot_width[from_reg] >= total_size
1981 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1983 x = spill_stack_slot[from_reg];
1985 /* Allocate a bigger slot. */
1988 /* Compute maximum size needed, both for inherent size
1989 and for total size. */
1990 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1993 if (spill_stack_slot[from_reg])
1995 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1997 mode = GET_MODE (spill_stack_slot[from_reg]);
1998 if (spill_stack_slot_width[from_reg] > total_size)
1999 total_size = spill_stack_slot_width[from_reg];
2002 /* Make a slot with that size. */
2003 x = assign_stack_local (mode, total_size,
2004 inherent_size == total_size ? 0 : -1);
2007 /* All pseudos mapped to this slot can alias each other. */
2008 if (spill_stack_slot[from_reg])
2009 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2011 set_mem_alias_set (x, new_alias_set ());
2013 if (BYTES_BIG_ENDIAN)
2015 /* Cancel the big-endian correction done in assign_stack_local.
2016 Get the address of the beginning of the slot.
2017 This is so we can do a big-endian correction unconditionally
2019 adjust = GET_MODE_SIZE (mode) - total_size;
2022 = adjust_address_nv (x, mode_for_size (total_size
2028 spill_stack_slot[from_reg] = stack_slot;
2029 spill_stack_slot_width[from_reg] = total_size;
2032 /* On a big endian machine, the "address" of the slot
2033 is the address of the low part that fits its inherent mode. */
2034 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2035 adjust += (total_size - inherent_size);
2037 /* If we have any adjustment to make, or if the stack slot is the
2038 wrong mode, make a new stack slot. */
2039 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2041 /* If we have a decl for the original register, set it for the
2042 memory. If this is a shared MEM, make a copy. */
2043 if (REG_EXPR (regno_reg_rtx[i])
2044 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2046 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2048 /* We can do this only for the DECLs home pseudo, not for
2049 any copies of it, since otherwise when the stack slot
2050 is reused, nonoverlapping_memrefs_p might think they
2052 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2054 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2057 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2061 /* Save the stack slot for later. */
2062 reg_equiv_memory_loc[i] = x;
2066 /* Mark the slots in regs_ever_live for the hard regs
2067 used by pseudo-reg number REGNO. */
2070 mark_home_live (int regno)
2074 i = reg_renumber[regno];
2077 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2079 regs_ever_live[i++] = 1;
2082 /* This function handles the tracking of elimination offsets around branches.
2084 X is a piece of RTL being scanned.
2086 INSN is the insn that it came from, if any.
2088 INITIAL_P is nonzero if we are to set the offset to be the initial
2089 offset and zero if we are setting the offset of the label to be the
2093 set_label_offsets (rtx x, rtx insn, int initial_p)
2095 enum rtx_code code = GET_CODE (x);
2098 struct elim_table *p;
2103 if (LABEL_REF_NONLOCAL_P (x))
2108 /* ... fall through ... */
2111 /* If we know nothing about this label, set the desired offsets. Note
2112 that this sets the offset at a label to be the offset before a label
2113 if we don't know anything about the label. This is not correct for
2114 the label after a BARRIER, but is the best guess we can make. If
2115 we guessed wrong, we will suppress an elimination that might have
2116 been possible had we been able to guess correctly. */
2118 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2120 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2121 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2122 = (initial_p ? reg_eliminate[i].initial_offset
2123 : reg_eliminate[i].offset);
2124 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2127 /* Otherwise, if this is the definition of a label and it is
2128 preceded by a BARRIER, set our offsets to the known offset of
2132 && (tem = prev_nonnote_insn (insn)) != 0
2133 && GET_CODE (tem) == BARRIER)
2134 set_offsets_for_label (insn);
2136 /* If neither of the above cases is true, compare each offset
2137 with those previously recorded and suppress any eliminations
2138 where the offsets disagree. */
2140 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2141 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2142 != (initial_p ? reg_eliminate[i].initial_offset
2143 : reg_eliminate[i].offset))
2144 reg_eliminate[i].can_eliminate = 0;
2149 set_label_offsets (PATTERN (insn), insn, initial_p);
2151 /* ... fall through ... */
2155 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2156 and hence must have all eliminations at their initial offsets. */
2157 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2158 if (REG_NOTE_KIND (tem) == REG_LABEL)
2159 set_label_offsets (XEXP (tem, 0), insn, 1);
2165 /* Each of the labels in the parallel or address vector must be
2166 at their initial offsets. We want the first field for PARALLEL
2167 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2169 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2170 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2175 /* We only care about setting PC. If the source is not RETURN,
2176 IF_THEN_ELSE, or a label, disable any eliminations not at
2177 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2178 isn't one of those possibilities. For branches to a label,
2179 call ourselves recursively.
2181 Note that this can disable elimination unnecessarily when we have
2182 a non-local goto since it will look like a non-constant jump to
2183 someplace in the current function. This isn't a significant
2184 problem since such jumps will normally be when all elimination
2185 pairs are back to their initial offsets. */
2187 if (SET_DEST (x) != pc_rtx)
2190 switch (GET_CODE (SET_SRC (x)))
2197 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2201 tem = XEXP (SET_SRC (x), 1);
2202 if (GET_CODE (tem) == LABEL_REF)
2203 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2204 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2207 tem = XEXP (SET_SRC (x), 2);
2208 if (GET_CODE (tem) == LABEL_REF)
2209 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2210 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2218 /* If we reach here, all eliminations must be at their initial
2219 offset because we are doing a jump to a variable address. */
2220 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2221 if (p->offset != p->initial_offset)
2222 p->can_eliminate = 0;
2230 /* Scan X and replace any eliminable registers (such as fp) with a
2231 replacement (such as sp), plus an offset.
2233 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2234 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2235 MEM, we are allowed to replace a sum of a register and the constant zero
2236 with the register, which we cannot do outside a MEM. In addition, we need
2237 to record the fact that a register is referenced outside a MEM.
2239 If INSN is an insn, it is the insn containing X. If we replace a REG
2240 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2241 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2242 the REG is being modified.
2244 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2245 That's used when we eliminate in expressions stored in notes.
2246 This means, do not set ref_outside_mem even if the reference
2249 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2250 replacements done assuming all offsets are at their initial values. If
2251 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2252 encounter, return the actual location so that find_reloads will do
2253 the proper thing. */
2256 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2258 enum rtx_code code = GET_CODE (x);
2259 struct elim_table *ep;
2266 if (! current_function_decl)
2288 /* First handle the case where we encounter a bare register that
2289 is eliminable. Replace it with a PLUS. */
2290 if (regno < FIRST_PSEUDO_REGISTER)
2292 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2294 if (ep->from_rtx == x && ep->can_eliminate)
2295 return plus_constant (ep->to_rtx, ep->previous_offset);
2298 else if (reg_renumber && reg_renumber[regno] < 0
2299 && reg_equiv_constant && reg_equiv_constant[regno]
2300 && ! CONSTANT_P (reg_equiv_constant[regno]))
2301 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2305 /* You might think handling MINUS in a manner similar to PLUS is a
2306 good idea. It is not. It has been tried multiple times and every
2307 time the change has had to have been reverted.
2309 Other parts of reload know a PLUS is special (gen_reload for example)
2310 and require special code to handle code a reloaded PLUS operand.
2312 Also consider backends where the flags register is clobbered by a
2313 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2314 lea instruction comes to mind). If we try to reload a MINUS, we
2315 may kill the flags register that was holding a useful value.
2317 So, please before trying to handle MINUS, consider reload as a
2318 whole instead of this little section as well as the backend issues. */
2320 /* If this is the sum of an eliminable register and a constant, rework
2322 if (REG_P (XEXP (x, 0))
2323 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2324 && CONSTANT_P (XEXP (x, 1)))
2326 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2328 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2330 /* The only time we want to replace a PLUS with a REG (this
2331 occurs when the constant operand of the PLUS is the negative
2332 of the offset) is when we are inside a MEM. We won't want
2333 to do so at other times because that would change the
2334 structure of the insn in a way that reload can't handle.
2335 We special-case the commonest situation in
2336 eliminate_regs_in_insn, so just replace a PLUS with a
2337 PLUS here, unless inside a MEM. */
2338 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2339 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2342 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2343 plus_constant (XEXP (x, 1),
2344 ep->previous_offset));
2347 /* If the register is not eliminable, we are done since the other
2348 operand is a constant. */
2352 /* If this is part of an address, we want to bring any constant to the
2353 outermost PLUS. We will do this by doing register replacement in
2354 our operands and seeing if a constant shows up in one of them.
2356 Note that there is no risk of modifying the structure of the insn,
2357 since we only get called for its operands, thus we are either
2358 modifying the address inside a MEM, or something like an address
2359 operand of a load-address insn. */
2362 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2363 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2365 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2367 /* If one side is a PLUS and the other side is a pseudo that
2368 didn't get a hard register but has a reg_equiv_constant,
2369 we must replace the constant here since it may no longer
2370 be in the position of any operand. */
2371 if (GET_CODE (new0) == PLUS && REG_P (new1)
2372 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2373 && reg_renumber[REGNO (new1)] < 0
2374 && reg_equiv_constant != 0
2375 && reg_equiv_constant[REGNO (new1)] != 0)
2376 new1 = reg_equiv_constant[REGNO (new1)];
2377 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2378 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2379 && reg_renumber[REGNO (new0)] < 0
2380 && reg_equiv_constant[REGNO (new0)] != 0)
2381 new0 = reg_equiv_constant[REGNO (new0)];
2383 new = form_sum (new0, new1);
2385 /* As above, if we are not inside a MEM we do not want to
2386 turn a PLUS into something else. We might try to do so here
2387 for an addition of 0 if we aren't optimizing. */
2388 if (! mem_mode && GET_CODE (new) != PLUS)
2389 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2397 /* If this is the product of an eliminable register and a
2398 constant, apply the distribute law and move the constant out
2399 so that we have (plus (mult ..) ..). This is needed in order
2400 to keep load-address insns valid. This case is pathological.
2401 We ignore the possibility of overflow here. */
2402 if (REG_P (XEXP (x, 0))
2403 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2404 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2405 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2407 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2410 /* Refs inside notes don't count for this purpose. */
2411 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2412 || GET_CODE (insn) == INSN_LIST)))
2413 ep->ref_outside_mem = 1;
2416 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2417 ep->previous_offset * INTVAL (XEXP (x, 1)));
2420 /* ... fall through ... */
2424 /* See comments before PLUS about handling MINUS. */
2426 case DIV: case UDIV:
2427 case MOD: case UMOD:
2428 case AND: case IOR: case XOR:
2429 case ROTATERT: case ROTATE:
2430 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2432 case GE: case GT: case GEU: case GTU:
2433 case LE: case LT: case LEU: case LTU:
2435 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2437 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2439 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2440 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2445 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2448 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2449 if (new != XEXP (x, 0))
2451 /* If this is a REG_DEAD note, it is not valid anymore.
2452 Using the eliminated version could result in creating a
2453 REG_DEAD note for the stack or frame pointer. */
2454 if (GET_MODE (x) == REG_DEAD)
2456 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2459 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2463 /* ... fall through ... */
2466 /* Now do eliminations in the rest of the chain. If this was
2467 an EXPR_LIST, this might result in allocating more memory than is
2468 strictly needed, but it simplifies the code. */
2471 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2472 if (new != XEXP (x, 1))
2474 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2482 case STRICT_LOW_PART:
2484 case SIGN_EXTEND: case ZERO_EXTEND:
2485 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2486 case FLOAT: case FIX:
2487 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2495 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2496 if (new != XEXP (x, 0))
2497 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2501 /* Similar to above processing, but preserve SUBREG_BYTE.
2502 Convert (subreg (mem)) to (mem) if not paradoxical.
2503 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2504 pseudo didn't get a hard reg, we must replace this with the
2505 eliminated version of the memory location because push_reload
2506 may do the replacement in certain circumstances. */
2507 if (REG_P (SUBREG_REG (x))
2508 && (GET_MODE_SIZE (GET_MODE (x))
2509 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2510 && reg_equiv_memory_loc != 0
2511 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2513 new = SUBREG_REG (x);
2516 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2518 if (new != SUBREG_REG (x))
2520 int x_size = GET_MODE_SIZE (GET_MODE (x));
2521 int new_size = GET_MODE_SIZE (GET_MODE (new));
2524 && ((x_size < new_size
2525 #ifdef WORD_REGISTER_OPERATIONS
2526 /* On these machines, combine can create rtl of the form
2527 (set (subreg:m1 (reg:m2 R) 0) ...)
2528 where m1 < m2, and expects something interesting to
2529 happen to the entire word. Moreover, it will use the
2530 (reg:m2 R) later, expecting all bits to be preserved.
2531 So if the number of words is the same, preserve the
2532 subreg so that push_reload can see it. */
2533 && ! ((x_size - 1) / UNITS_PER_WORD
2534 == (new_size -1 ) / UNITS_PER_WORD)
2537 || x_size == new_size)
2539 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2541 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2547 /* Our only special processing is to pass the mode of the MEM to our
2548 recursive call and copy the flags. While we are here, handle this
2549 case more efficiently. */
2551 replace_equiv_address_nv (x,
2552 eliminate_regs (XEXP (x, 0),
2553 GET_MODE (x), insn));
2556 /* Handle insn_list USE that a call to a pure function may generate. */
2557 new = eliminate_regs (XEXP (x, 0), 0, insn);
2558 if (new != XEXP (x, 0))
2559 return gen_rtx_USE (GET_MODE (x), new);
2571 /* Process each of our operands recursively. If any have changed, make a
2573 fmt = GET_RTX_FORMAT (code);
2574 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2578 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2579 if (new != XEXP (x, i) && ! copied)
2581 rtx new_x = rtx_alloc (code);
2582 memcpy (new_x, x, RTX_SIZE (code));
2588 else if (*fmt == 'E')
2591 for (j = 0; j < XVECLEN (x, i); j++)
2593 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2594 if (new != XVECEXP (x, i, j) && ! copied_vec)
2596 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2600 rtx new_x = rtx_alloc (code);
2601 memcpy (new_x, x, RTX_SIZE (code));
2605 XVEC (x, i) = new_v;
2608 XVECEXP (x, i, j) = new;
2616 /* Scan rtx X for modifications of elimination target registers. Update
2617 the table of eliminables to reflect the changed state. MEM_MODE is
2618 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2621 elimination_effects (rtx x, enum machine_mode mem_mode)
2623 enum rtx_code code = GET_CODE (x);
2624 struct elim_table *ep;
2648 /* First handle the case where we encounter a bare register that
2649 is eliminable. Replace it with a PLUS. */
2650 if (regno < FIRST_PSEUDO_REGISTER)
2652 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2654 if (ep->from_rtx == x && ep->can_eliminate)
2657 ep->ref_outside_mem = 1;
2662 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2663 && reg_equiv_constant[regno]
2664 && ! function_invariant_p (reg_equiv_constant[regno]))
2665 elimination_effects (reg_equiv_constant[regno], mem_mode);
2674 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2675 if (ep->to_rtx == XEXP (x, 0))
2677 int size = GET_MODE_SIZE (mem_mode);
2679 /* If more bytes than MEM_MODE are pushed, account for them. */
2680 #ifdef PUSH_ROUNDING
2681 if (ep->to_rtx == stack_pointer_rtx)
2682 size = PUSH_ROUNDING (size);
2684 if (code == PRE_DEC || code == POST_DEC)
2686 else if (code == PRE_INC || code == POST_INC)
2688 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2689 && GET_CODE (XEXP (x, 1)) == PLUS
2690 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2691 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2692 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2695 /* These two aren't unary operators. */
2696 if (code == POST_MODIFY || code == PRE_MODIFY)
2699 /* Fall through to generic unary operation case. */
2700 case STRICT_LOW_PART:
2702 case SIGN_EXTEND: case ZERO_EXTEND:
2703 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2704 case FLOAT: case FIX:
2705 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2713 elimination_effects (XEXP (x, 0), mem_mode);
2717 if (REG_P (SUBREG_REG (x))
2718 && (GET_MODE_SIZE (GET_MODE (x))
2719 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2720 && reg_equiv_memory_loc != 0
2721 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2724 elimination_effects (SUBREG_REG (x), mem_mode);
2728 /* If using a register that is the source of an eliminate we still
2729 think can be performed, note it cannot be performed since we don't
2730 know how this register is used. */
2731 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2732 if (ep->from_rtx == XEXP (x, 0))
2733 ep->can_eliminate = 0;
2735 elimination_effects (XEXP (x, 0), mem_mode);
2739 /* If clobbering a register that is the replacement register for an
2740 elimination we still think can be performed, note that it cannot
2741 be performed. Otherwise, we need not be concerned about it. */
2742 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2743 if (ep->to_rtx == XEXP (x, 0))
2744 ep->can_eliminate = 0;
2746 elimination_effects (XEXP (x, 0), mem_mode);
2750 /* Check for setting a register that we know about. */
2751 if (REG_P (SET_DEST (x)))
2753 /* See if this is setting the replacement register for an
2756 If DEST is the hard frame pointer, we do nothing because we
2757 assume that all assignments to the frame pointer are for
2758 non-local gotos and are being done at a time when they are valid
2759 and do not disturb anything else. Some machines want to
2760 eliminate a fake argument pointer (or even a fake frame pointer)
2761 with either the real frame or the stack pointer. Assignments to
2762 the hard frame pointer must not prevent this elimination. */
2764 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2766 if (ep->to_rtx == SET_DEST (x)
2767 && SET_DEST (x) != hard_frame_pointer_rtx)
2769 /* If it is being incremented, adjust the offset. Otherwise,
2770 this elimination can't be done. */
2771 rtx src = SET_SRC (x);
2773 if (GET_CODE (src) == PLUS
2774 && XEXP (src, 0) == SET_DEST (x)
2775 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2776 ep->offset -= INTVAL (XEXP (src, 1));
2778 ep->can_eliminate = 0;
2782 elimination_effects (SET_DEST (x), 0);
2783 elimination_effects (SET_SRC (x), 0);
2787 /* Our only special processing is to pass the mode of the MEM to our
2789 elimination_effects (XEXP (x, 0), GET_MODE (x));
2796 fmt = GET_RTX_FORMAT (code);
2797 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2800 elimination_effects (XEXP (x, i), mem_mode);
2801 else if (*fmt == 'E')
2802 for (j = 0; j < XVECLEN (x, i); j++)
2803 elimination_effects (XVECEXP (x, i, j), mem_mode);
2807 /* Descend through rtx X and verify that no references to eliminable registers
2808 remain. If any do remain, mark the involved register as not
2812 check_eliminable_occurrences (rtx x)
2821 code = GET_CODE (x);
2823 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2825 struct elim_table *ep;
2827 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2828 if (ep->from_rtx == x)
2829 ep->can_eliminate = 0;
2833 fmt = GET_RTX_FORMAT (code);
2834 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2837 check_eliminable_occurrences (XEXP (x, i));
2838 else if (*fmt == 'E')
2841 for (j = 0; j < XVECLEN (x, i); j++)
2842 check_eliminable_occurrences (XVECEXP (x, i, j));
2847 /* Scan INSN and eliminate all eliminable registers in it.
2849 If REPLACE is nonzero, do the replacement destructively. Also
2850 delete the insn as dead it if it is setting an eliminable register.
2852 If REPLACE is zero, do all our allocations in reload_obstack.
2854 If no eliminations were done and this insn doesn't require any elimination
2855 processing (these are not identical conditions: it might be updating sp,
2856 but not referencing fp; this needs to be seen during reload_as_needed so
2857 that the offset between fp and sp can be taken into consideration), zero
2858 is returned. Otherwise, 1 is returned. */
2861 eliminate_regs_in_insn (rtx insn, int replace)
2863 int icode = recog_memoized (insn);
2864 rtx old_body = PATTERN (insn);
2865 int insn_is_asm = asm_noperands (old_body) >= 0;
2866 rtx old_set = single_set (insn);
2870 rtx substed_operand[MAX_RECOG_OPERANDS];
2871 rtx orig_operand[MAX_RECOG_OPERANDS];
2872 struct elim_table *ep;
2875 if (! insn_is_asm && icode < 0)
2877 if (GET_CODE (PATTERN (insn)) == USE
2878 || GET_CODE (PATTERN (insn)) == CLOBBER
2879 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2880 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2881 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2886 if (old_set != 0 && REG_P (SET_DEST (old_set))
2887 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2889 /* Check for setting an eliminable register. */
2890 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2891 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2893 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2894 /* If this is setting the frame pointer register to the
2895 hardware frame pointer register and this is an elimination
2896 that will be done (tested above), this insn is really
2897 adjusting the frame pointer downward to compensate for
2898 the adjustment done before a nonlocal goto. */
2899 if (ep->from == FRAME_POINTER_REGNUM
2900 && ep->to == HARD_FRAME_POINTER_REGNUM)
2902 rtx base = SET_SRC (old_set);
2903 rtx base_insn = insn;
2904 HOST_WIDE_INT offset = 0;
2906 while (base != ep->to_rtx)
2908 rtx prev_insn, prev_set;
2910 if (GET_CODE (base) == PLUS
2911 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2913 offset += INTVAL (XEXP (base, 1));
2914 base = XEXP (base, 0);
2916 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2917 && (prev_set = single_set (prev_insn)) != 0
2918 && rtx_equal_p (SET_DEST (prev_set), base))
2920 base = SET_SRC (prev_set);
2921 base_insn = prev_insn;
2927 if (base == ep->to_rtx)
2930 = plus_constant (ep->to_rtx, offset - ep->offset);
2932 new_body = old_body;
2935 new_body = copy_insn (old_body);
2936 if (REG_NOTES (insn))
2937 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2939 PATTERN (insn) = new_body;
2940 old_set = single_set (insn);
2942 /* First see if this insn remains valid when we
2943 make the change. If not, keep the INSN_CODE
2944 the same and let reload fit it up. */
2945 validate_change (insn, &SET_SRC (old_set), src, 1);
2946 validate_change (insn, &SET_DEST (old_set),
2948 if (! apply_change_group ())
2950 SET_SRC (old_set) = src;
2951 SET_DEST (old_set) = ep->to_rtx;
2960 /* In this case this insn isn't serving a useful purpose. We
2961 will delete it in reload_as_needed once we know that this
2962 elimination is, in fact, being done.
2964 If REPLACE isn't set, we can't delete this insn, but needn't
2965 process it since it won't be used unless something changes. */
2968 delete_dead_insn (insn);
2976 /* We allow one special case which happens to work on all machines we
2977 currently support: a single set with the source or a REG_EQUAL
2978 note being a PLUS of an eliminable register and a constant. */
2980 if (old_set && REG_P (SET_DEST (old_set)))
2982 /* First see if the source is of the form (plus (reg) CST). */
2983 if (GET_CODE (SET_SRC (old_set)) == PLUS
2984 && REG_P (XEXP (SET_SRC (old_set), 0))
2985 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2986 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2987 plus_src = SET_SRC (old_set);
2988 else if (REG_P (SET_SRC (old_set)))
2990 /* Otherwise, see if we have a REG_EQUAL note of the form
2991 (plus (reg) CST). */
2993 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
2995 if (REG_NOTE_KIND (links) == REG_EQUAL
2996 && GET_CODE (XEXP (links, 0)) == PLUS
2997 && REG_P (XEXP (XEXP (links, 0), 0))
2998 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
2999 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
3001 plus_src = XEXP (links, 0);
3009 rtx reg = XEXP (plus_src, 0);
3010 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3013 if (ep->from_rtx == reg && ep->can_eliminate)
3015 offset += ep->offset;
3020 /* We assume here that if we need a PARALLEL with
3021 CLOBBERs for this assignment, we can do with the
3022 MATCH_SCRATCHes that add_clobbers allocates.
3023 There's not much we can do if that doesn't work. */
3024 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3028 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3031 rtvec vec = rtvec_alloc (num_clobbers + 1);
3033 vec->elem[0] = PATTERN (insn);
3034 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3035 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3037 if (INSN_CODE (insn) < 0)
3040 /* If we have a nonzero offset, and the source is already
3041 a simple REG, the following transformation would
3042 increase the cost of the insn by replacing a simple REG
3043 with (plus (reg sp) CST). So try only when plus_src
3044 comes from old_set proper, not REG_NOTES. */
3045 else if (SET_SRC (old_set) == plus_src)
3047 new_body = old_body;
3050 new_body = copy_insn (old_body);
3051 if (REG_NOTES (insn))
3052 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3054 PATTERN (insn) = new_body;
3055 old_set = single_set (insn);
3057 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3058 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3064 /* This can't have an effect on elimination offsets, so skip right
3070 /* Determine the effects of this insn on elimination offsets. */
3071 elimination_effects (old_body, 0);
3073 /* Eliminate all eliminable registers occurring in operands that
3074 can be handled by reload. */
3075 extract_insn (insn);
3076 for (i = 0; i < recog_data.n_operands; i++)
3078 orig_operand[i] = recog_data.operand[i];
3079 substed_operand[i] = recog_data.operand[i];
3081 /* For an asm statement, every operand is eliminable. */
3082 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3084 /* Check for setting a register that we know about. */
3085 if (recog_data.operand_type[i] != OP_IN
3086 && REG_P (orig_operand[i]))
3088 /* If we are assigning to a register that can be eliminated, it
3089 must be as part of a PARALLEL, since the code above handles
3090 single SETs. We must indicate that we can no longer
3091 eliminate this reg. */
3092 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3094 if (ep->from_rtx == orig_operand[i])
3095 ep->can_eliminate = 0;
3098 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3099 replace ? insn : NULL_RTX);
3100 if (substed_operand[i] != orig_operand[i])
3102 /* Terminate the search in check_eliminable_occurrences at
3104 *recog_data.operand_loc[i] = 0;
3106 /* If an output operand changed from a REG to a MEM and INSN is an
3107 insn, write a CLOBBER insn. */
3108 if (recog_data.operand_type[i] != OP_IN
3109 && REG_P (orig_operand[i])
3110 && MEM_P (substed_operand[i])
3112 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3117 for (i = 0; i < recog_data.n_dups; i++)
3118 *recog_data.dup_loc[i]
3119 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3121 /* If any eliminable remain, they aren't eliminable anymore. */
3122 check_eliminable_occurrences (old_body);
3124 /* Substitute the operands; the new values are in the substed_operand
3126 for (i = 0; i < recog_data.n_operands; i++)
3127 *recog_data.operand_loc[i] = substed_operand[i];
3128 for (i = 0; i < recog_data.n_dups; i++)
3129 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3131 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3132 re-recognize the insn. We do this in case we had a simple addition
3133 but now can do this as a load-address. This saves an insn in this
3135 If re-recognition fails, the old insn code number will still be used,
3136 and some register operands may have changed into PLUS expressions.
3137 These will be handled by find_reloads by loading them into a register
3142 /* If we aren't replacing things permanently and we changed something,
3143 make another copy to ensure that all the RTL is new. Otherwise
3144 things can go wrong if find_reload swaps commutative operands
3145 and one is inside RTL that has been copied while the other is not. */
3146 new_body = old_body;
3149 new_body = copy_insn (old_body);
3150 if (REG_NOTES (insn))
3151 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3153 PATTERN (insn) = new_body;
3155 /* If we had a move insn but now we don't, rerecognize it. This will
3156 cause spurious re-recognition if the old move had a PARALLEL since
3157 the new one still will, but we can't call single_set without
3158 having put NEW_BODY into the insn and the re-recognition won't
3159 hurt in this rare case. */
3160 /* ??? Why this huge if statement - why don't we just rerecognize the
3164 && ((REG_P (SET_SRC (old_set))
3165 && (GET_CODE (new_body) != SET
3166 || !REG_P (SET_SRC (new_body))))
3167 /* If this was a load from or store to memory, compare
3168 the MEM in recog_data.operand to the one in the insn.
3169 If they are not equal, then rerecognize the insn. */
3171 && ((MEM_P (SET_SRC (old_set))
3172 && SET_SRC (old_set) != recog_data.operand[1])
3173 || (MEM_P (SET_DEST (old_set))
3174 && SET_DEST (old_set) != recog_data.operand[0])))
3175 /* If this was an add insn before, rerecognize. */
3176 || GET_CODE (SET_SRC (old_set)) == PLUS))
3178 int new_icode = recog (PATTERN (insn), insn, 0);
3180 INSN_CODE (insn) = icode;
3184 /* Restore the old body. If there were any changes to it, we made a copy
3185 of it while the changes were still in place, so we'll correctly return
3186 a modified insn below. */
3189 /* Restore the old body. */
3190 for (i = 0; i < recog_data.n_operands; i++)
3191 *recog_data.operand_loc[i] = orig_operand[i];
3192 for (i = 0; i < recog_data.n_dups; i++)
3193 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3196 /* Update all elimination pairs to reflect the status after the current
3197 insn. The changes we make were determined by the earlier call to
3198 elimination_effects.
3200 We also detect cases where register elimination cannot be done,
3201 namely, if a register would be both changed and referenced outside a MEM
3202 in the resulting insn since such an insn is often undefined and, even if
3203 not, we cannot know what meaning will be given to it. Note that it is
3204 valid to have a register used in an address in an insn that changes it
3205 (presumably with a pre- or post-increment or decrement).
3207 If anything changes, return nonzero. */
3209 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3211 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3212 ep->can_eliminate = 0;
3214 ep->ref_outside_mem = 0;
3216 if (ep->previous_offset != ep->offset)
3221 /* If we changed something, perform elimination in REG_NOTES. This is
3222 needed even when REPLACE is zero because a REG_DEAD note might refer
3223 to a register that we eliminate and could cause a different number
3224 of spill registers to be needed in the final reload pass than in
3226 if (val && REG_NOTES (insn) != 0)
3227 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3232 /* Loop through all elimination pairs.
3233 Recalculate the number not at initial offset.
3235 Compute the maximum offset (minimum offset if the stack does not
3236 grow downward) for each elimination pair. */
3239 update_eliminable_offsets (void)
3241 struct elim_table *ep;
3243 num_not_at_initial_offset = 0;
3244 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3246 ep->previous_offset = ep->offset;
3247 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3248 num_not_at_initial_offset++;
3252 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3253 replacement we currently believe is valid, mark it as not eliminable if X
3254 modifies DEST in any way other than by adding a constant integer to it.
3256 If DEST is the frame pointer, we do nothing because we assume that
3257 all assignments to the hard frame pointer are nonlocal gotos and are being
3258 done at a time when they are valid and do not disturb anything else.
3259 Some machines want to eliminate a fake argument pointer with either the
3260 frame or stack pointer. Assignments to the hard frame pointer must not
3261 prevent this elimination.
3263 Called via note_stores from reload before starting its passes to scan
3264 the insns of the function. */
3267 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3271 /* A SUBREG of a hard register here is just changing its mode. We should
3272 not see a SUBREG of an eliminable hard register, but check just in
3274 if (GET_CODE (dest) == SUBREG)
3275 dest = SUBREG_REG (dest);
3277 if (dest == hard_frame_pointer_rtx)
3280 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3281 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3282 && (GET_CODE (x) != SET
3283 || GET_CODE (SET_SRC (x)) != PLUS
3284 || XEXP (SET_SRC (x), 0) != dest
3285 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3287 reg_eliminate[i].can_eliminate_previous
3288 = reg_eliminate[i].can_eliminate = 0;
3293 /* Verify that the initial elimination offsets did not change since the
3294 last call to set_initial_elim_offsets. This is used to catch cases
3295 where something illegal happened during reload_as_needed that could
3296 cause incorrect code to be generated if we did not check for it. */
3299 verify_initial_elim_offsets (void)
3303 #ifdef ELIMINABLE_REGS
3304 struct elim_table *ep;
3306 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3308 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3309 if (t != ep->initial_offset)
3313 INITIAL_FRAME_POINTER_OFFSET (t);
3314 if (t != reg_eliminate[0].initial_offset)
3319 /* Reset all offsets on eliminable registers to their initial values. */
3322 set_initial_elim_offsets (void)
3324 struct elim_table *ep = reg_eliminate;
3326 #ifdef ELIMINABLE_REGS
3327 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3329 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3330 ep->previous_offset = ep->offset = ep->initial_offset;
3333 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3334 ep->previous_offset = ep->offset = ep->initial_offset;
3337 num_not_at_initial_offset = 0;
3340 /* Initialize the known label offsets.
3341 Set a known offset for each forced label to be at the initial offset
3342 of each elimination. We do this because we assume that all
3343 computed jumps occur from a location where each elimination is
3344 at its initial offset.
3345 For all other labels, show that we don't know the offsets. */
3348 set_initial_label_offsets (void)
3351 memset (offsets_known_at, 0, num_labels);
3353 for (x = forced_labels; x; x = XEXP (x, 1))
3355 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3358 /* Set all elimination offsets to the known values for the code label given
3362 set_offsets_for_label (rtx insn)
3365 int label_nr = CODE_LABEL_NUMBER (insn);
3366 struct elim_table *ep;
3368 num_not_at_initial_offset = 0;
3369 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3371 ep->offset = ep->previous_offset
3372 = offsets_at[label_nr - first_label_num][i];
3373 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3374 num_not_at_initial_offset++;
3378 /* See if anything that happened changes which eliminations are valid.
3379 For example, on the SPARC, whether or not the frame pointer can
3380 be eliminated can depend on what registers have been used. We need
3381 not check some conditions again (such as flag_omit_frame_pointer)
3382 since they can't have changed. */
3385 update_eliminables (HARD_REG_SET *pset)
3387 int previous_frame_pointer_needed = frame_pointer_needed;
3388 struct elim_table *ep;
3390 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3391 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3392 #ifdef ELIMINABLE_REGS
3393 || ! CAN_ELIMINATE (ep->from, ep->to)
3396 ep->can_eliminate = 0;
3398 /* Look for the case where we have discovered that we can't replace
3399 register A with register B and that means that we will now be
3400 trying to replace register A with register C. This means we can
3401 no longer replace register C with register B and we need to disable
3402 such an elimination, if it exists. This occurs often with A == ap,
3403 B == sp, and C == fp. */
3405 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3407 struct elim_table *op;
3410 if (! ep->can_eliminate && ep->can_eliminate_previous)
3412 /* Find the current elimination for ep->from, if there is a
3414 for (op = reg_eliminate;
3415 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3416 if (op->from == ep->from && op->can_eliminate)
3422 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3424 for (op = reg_eliminate;
3425 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3426 if (op->from == new_to && op->to == ep->to)
3427 op->can_eliminate = 0;
3431 /* See if any registers that we thought we could eliminate the previous
3432 time are no longer eliminable. If so, something has changed and we
3433 must spill the register. Also, recompute the number of eliminable
3434 registers and see if the frame pointer is needed; it is if there is
3435 no elimination of the frame pointer that we can perform. */
3437 frame_pointer_needed = 1;
3438 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3440 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3441 && ep->to != HARD_FRAME_POINTER_REGNUM)
3442 frame_pointer_needed = 0;
3444 if (! ep->can_eliminate && ep->can_eliminate_previous)
3446 ep->can_eliminate_previous = 0;
3447 SET_HARD_REG_BIT (*pset, ep->from);
3452 /* If we didn't need a frame pointer last time, but we do now, spill
3453 the hard frame pointer. */
3454 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3455 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3458 /* Initialize the table of registers to eliminate. */
3461 init_elim_table (void)
3463 struct elim_table *ep;
3464 #ifdef ELIMINABLE_REGS
3465 const struct elim_table_1 *ep1;
3469 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3471 /* Does this function require a frame pointer? */
3473 frame_pointer_needed = (! flag_omit_frame_pointer
3474 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3475 and restore sp for alloca. So we can't eliminate
3476 the frame pointer in that case. At some point,
3477 we should improve this by emitting the
3478 sp-adjusting insns for this case. */
3479 || (current_function_calls_alloca
3480 && EXIT_IGNORE_STACK)
3481 || FRAME_POINTER_REQUIRED);
3485 #ifdef ELIMINABLE_REGS
3486 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3487 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3489 ep->from = ep1->from;
3491 ep->can_eliminate = ep->can_eliminate_previous
3492 = (CAN_ELIMINATE (ep->from, ep->to)
3493 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3496 reg_eliminate[0].from = reg_eliminate_1[0].from;
3497 reg_eliminate[0].to = reg_eliminate_1[0].to;
3498 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3499 = ! frame_pointer_needed;
3502 /* Count the number of eliminable registers and build the FROM and TO
3503 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3504 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3505 We depend on this. */
3506 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3508 num_eliminable += ep->can_eliminate;
3509 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3510 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3514 /* Kick all pseudos out of hard register REGNO.
3516 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3517 because we found we can't eliminate some register. In the case, no pseudos
3518 are allowed to be in the register, even if they are only in a block that
3519 doesn't require spill registers, unlike the case when we are spilling this
3520 hard reg to produce another spill register.
3522 Return nonzero if any pseudos needed to be kicked out. */
3525 spill_hard_reg (unsigned int regno, int cant_eliminate)
3531 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3532 regs_ever_live[regno] = 1;
3535 /* Spill every pseudo reg that was allocated to this reg
3536 or to something that overlaps this reg. */
3538 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3539 if (reg_renumber[i] >= 0
3540 && (unsigned int) reg_renumber[i] <= regno
3541 && ((unsigned int) reg_renumber[i]
3542 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3543 [PSEUDO_REGNO_MODE (i)]
3545 SET_REGNO_REG_SET (&spilled_pseudos, i);
3548 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3549 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3552 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3554 IOR_HARD_REG_SET (*set1, *set2);
3557 /* After find_reload_regs has been run for all insn that need reloads,
3558 and/or spill_hard_regs was called, this function is used to actually
3559 spill pseudo registers and try to reallocate them. It also sets up the
3560 spill_regs array for use by choose_reload_regs. */
3563 finish_spills (int global)
3565 struct insn_chain *chain;
3566 int something_changed = 0;
3569 /* Build the spill_regs array for the function. */
3570 /* If there are some registers still to eliminate and one of the spill regs
3571 wasn't ever used before, additional stack space may have to be
3572 allocated to store this register. Thus, we may have changed the offset
3573 between the stack and frame pointers, so mark that something has changed.
3575 One might think that we need only set VAL to 1 if this is a call-used
3576 register. However, the set of registers that must be saved by the
3577 prologue is not identical to the call-used set. For example, the
3578 register used by the call insn for the return PC is a call-used register,
3579 but must be saved by the prologue. */
3582 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3583 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3585 spill_reg_order[i] = n_spills;
3586 spill_regs[n_spills++] = i;
3587 if (num_eliminable && ! regs_ever_live[i])
3588 something_changed = 1;
3589 regs_ever_live[i] = 1;
3592 spill_reg_order[i] = -1;
3594 EXECUTE_IF_SET_IN_REG_SET
3595 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3597 /* Record the current hard register the pseudo is allocated to in
3598 pseudo_previous_regs so we avoid reallocating it to the same
3599 hard reg in a later pass. */
3600 if (reg_renumber[i] < 0)
3603 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3604 /* Mark it as no longer having a hard register home. */
3605 reg_renumber[i] = -1;
3606 /* We will need to scan everything again. */
3607 something_changed = 1;
3610 /* Retry global register allocation if possible. */
3613 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3614 /* For every insn that needs reloads, set the registers used as spill
3615 regs in pseudo_forbidden_regs for every pseudo live across the
3617 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3619 EXECUTE_IF_SET_IN_REG_SET
3620 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3622 ior_hard_reg_set (pseudo_forbidden_regs + i,
3623 &chain->used_spill_regs);
3625 EXECUTE_IF_SET_IN_REG_SET
3626 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3628 ior_hard_reg_set (pseudo_forbidden_regs + i,
3629 &chain->used_spill_regs);
3633 /* Retry allocating the spilled pseudos. For each reg, merge the
3634 various reg sets that indicate which hard regs can't be used,
3635 and call retry_global_alloc.
3636 We change spill_pseudos here to only contain pseudos that did not
3637 get a new hard register. */
3638 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3639 if (reg_old_renumber[i] != reg_renumber[i])
3641 HARD_REG_SET forbidden;
3642 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3643 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3644 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3645 retry_global_alloc (i, forbidden);
3646 if (reg_renumber[i] >= 0)
3647 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3651 /* Fix up the register information in the insn chain.
3652 This involves deleting those of the spilled pseudos which did not get
3653 a new hard register home from the live_{before,after} sets. */
3654 for (chain = reload_insn_chain; chain; chain = chain->next)
3656 HARD_REG_SET used_by_pseudos;
3657 HARD_REG_SET used_by_pseudos2;
3659 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3660 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3662 /* Mark any unallocated hard regs as available for spills. That
3663 makes inheritance work somewhat better. */
3664 if (chain->need_reload)
3666 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3667 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3668 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3670 /* Save the old value for the sanity test below. */
3671 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3673 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3674 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3675 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3676 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3678 /* Make sure we only enlarge the set. */
3679 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3685 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3686 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3688 int regno = reg_renumber[i];
3689 if (reg_old_renumber[i] == regno)
3692 alter_reg (i, reg_old_renumber[i]);
3693 reg_old_renumber[i] = regno;
3697 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3699 fprintf (dump_file, " Register %d now in %d.\n\n",
3700 i, reg_renumber[i]);
3704 return something_changed;
3707 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3710 scan_paradoxical_subregs (rtx x)
3714 enum rtx_code code = GET_CODE (x);
3724 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3732 if (REG_P (SUBREG_REG (x))
3733 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3734 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3735 = GET_MODE_SIZE (GET_MODE (x));
3742 fmt = GET_RTX_FORMAT (code);
3743 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3746 scan_paradoxical_subregs (XEXP (x, i));
3747 else if (fmt[i] == 'E')
3750 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3751 scan_paradoxical_subregs (XVECEXP (x, i, j));
3756 /* Reload pseudo-registers into hard regs around each insn as needed.
3757 Additional register load insns are output before the insn that needs it
3758 and perhaps store insns after insns that modify the reloaded pseudo reg.
3760 reg_last_reload_reg and reg_reloaded_contents keep track of
3761 which registers are already available in reload registers.
3762 We update these for the reloads that we perform,
3763 as the insns are scanned. */
3766 reload_as_needed (int live_known)
3768 struct insn_chain *chain;
3769 #if defined (AUTO_INC_DEC)
3774 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3775 memset (spill_reg_store, 0, sizeof spill_reg_store);
3776 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3777 reg_has_output_reload = xmalloc (max_regno);
3778 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3779 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3781 set_initial_elim_offsets ();
3783 for (chain = reload_insn_chain; chain; chain = chain->next)
3786 rtx insn = chain->insn;
3787 rtx old_next = NEXT_INSN (insn);
3789 /* If we pass a label, copy the offsets from the label information
3790 into the current offsets of each elimination. */
3791 if (GET_CODE (insn) == CODE_LABEL)
3792 set_offsets_for_label (insn);
3794 else if (INSN_P (insn))
3796 rtx oldpat = copy_rtx (PATTERN (insn));
3798 /* If this is a USE and CLOBBER of a MEM, ensure that any
3799 references to eliminable registers have been removed. */
3801 if ((GET_CODE (PATTERN (insn)) == USE
3802 || GET_CODE (PATTERN (insn)) == CLOBBER)
3803 && MEM_P (XEXP (PATTERN (insn), 0)))
3804 XEXP (XEXP (PATTERN (insn), 0), 0)
3805 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3806 GET_MODE (XEXP (PATTERN (insn), 0)),
3809 /* If we need to do register elimination processing, do so.
3810 This might delete the insn, in which case we are done. */
3811 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3813 eliminate_regs_in_insn (insn, 1);
3814 if (GET_CODE (insn) == NOTE)
3816 update_eliminable_offsets ();
3821 /* If need_elim is nonzero but need_reload is zero, one might think
3822 that we could simply set n_reloads to 0. However, find_reloads
3823 could have done some manipulation of the insn (such as swapping
3824 commutative operands), and these manipulations are lost during
3825 the first pass for every insn that needs register elimination.
3826 So the actions of find_reloads must be redone here. */
3828 if (! chain->need_elim && ! chain->need_reload
3829 && ! chain->need_operand_change)
3831 /* First find the pseudo regs that must be reloaded for this insn.
3832 This info is returned in the tables reload_... (see reload.h).
3833 Also modify the body of INSN by substituting RELOAD
3834 rtx's for those pseudo regs. */
3837 memset (reg_has_output_reload, 0, max_regno);
3838 CLEAR_HARD_REG_SET (reg_is_output_reload);
3840 find_reloads (insn, 1, spill_indirect_levels, live_known,
3846 rtx next = NEXT_INSN (insn);
3849 prev = PREV_INSN (insn);
3851 /* Now compute which reload regs to reload them into. Perhaps
3852 reusing reload regs from previous insns, or else output
3853 load insns to reload them. Maybe output store insns too.
3854 Record the choices of reload reg in reload_reg_rtx. */
3855 choose_reload_regs (chain);
3857 /* Merge any reloads that we didn't combine for fear of
3858 increasing the number of spill registers needed but now
3859 discover can be safely merged. */
3860 if (SMALL_REGISTER_CLASSES)
3861 merge_assigned_reloads (insn);
3863 /* Generate the insns to reload operands into or out of
3864 their reload regs. */
3865 emit_reload_insns (chain);
3867 /* Substitute the chosen reload regs from reload_reg_rtx
3868 into the insn's body (or perhaps into the bodies of other
3869 load and store insn that we just made for reloading
3870 and that we moved the structure into). */
3871 subst_reloads (insn);
3873 /* If this was an ASM, make sure that all the reload insns
3874 we have generated are valid. If not, give an error
3877 if (asm_noperands (PATTERN (insn)) >= 0)
3878 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3879 if (p != insn && INSN_P (p)
3880 && GET_CODE (PATTERN (p)) != USE
3881 && (recog_memoized (p) < 0
3882 || (extract_insn (p), ! constrain_operands (1))))
3884 error_for_asm (insn,
3885 "`asm' operand requires impossible reload");
3890 if (num_eliminable && chain->need_elim)
3891 update_eliminable_offsets ();
3893 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3894 is no longer validly lying around to save a future reload.
3895 Note that this does not detect pseudos that were reloaded
3896 for this insn in order to be stored in
3897 (obeying register constraints). That is correct; such reload
3898 registers ARE still valid. */
3899 note_stores (oldpat, forget_old_reloads_1, NULL);
3901 /* There may have been CLOBBER insns placed after INSN. So scan
3902 between INSN and NEXT and use them to forget old reloads. */
3903 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3904 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3905 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3908 /* Likewise for regs altered by auto-increment in this insn.
3909 REG_INC notes have been changed by reloading:
3910 find_reloads_address_1 records substitutions for them,
3911 which have been performed by subst_reloads above. */
3912 for (i = n_reloads - 1; i >= 0; i--)
3914 rtx in_reg = rld[i].in_reg;
3917 enum rtx_code code = GET_CODE (in_reg);
3918 /* PRE_INC / PRE_DEC will have the reload register ending up
3919 with the same value as the stack slot, but that doesn't
3920 hold true for POST_INC / POST_DEC. Either we have to
3921 convert the memory access to a true POST_INC / POST_DEC,
3922 or we can't use the reload register for inheritance. */
3923 if ((code == POST_INC || code == POST_DEC)
3924 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3925 REGNO (rld[i].reg_rtx))
3926 /* Make sure it is the inc/dec pseudo, and not
3927 some other (e.g. output operand) pseudo. */
3928 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3929 == REGNO (XEXP (in_reg, 0))))
3932 rtx reload_reg = rld[i].reg_rtx;
3933 enum machine_mode mode = GET_MODE (reload_reg);
3937 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3939 /* We really want to ignore REG_INC notes here, so
3940 use PATTERN (p) as argument to reg_set_p . */
3941 if (reg_set_p (reload_reg, PATTERN (p)))
3943 n = count_occurrences (PATTERN (p), reload_reg, 0);
3948 n = validate_replace_rtx (reload_reg,
3949 gen_rtx_fmt_e (code,
3954 /* We must also verify that the constraints
3955 are met after the replacement. */
3958 n = constrain_operands (1);
3962 /* If the constraints were not met, then
3963 undo the replacement. */
3966 validate_replace_rtx (gen_rtx_fmt_e (code,
3979 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3981 /* Mark this as having an output reload so that the
3982 REG_INC processing code below won't invalidate
3983 the reload for inheritance. */
3984 SET_HARD_REG_BIT (reg_is_output_reload,
3985 REGNO (reload_reg));
3986 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3989 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3992 else if ((code == PRE_INC || code == PRE_DEC)
3993 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3994 REGNO (rld[i].reg_rtx))
3995 /* Make sure it is the inc/dec pseudo, and not
3996 some other (e.g. output operand) pseudo. */
3997 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3998 == REGNO (XEXP (in_reg, 0))))
4000 SET_HARD_REG_BIT (reg_is_output_reload,
4001 REGNO (rld[i].reg_rtx));
4002 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4006 /* If a pseudo that got a hard register is auto-incremented,
4007 we must purge records of copying it into pseudos without
4009 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4010 if (REG_NOTE_KIND (x) == REG_INC)
4012 /* See if this pseudo reg was reloaded in this insn.
4013 If so, its last-reload info is still valid
4014 because it is based on this insn's reload. */
4015 for (i = 0; i < n_reloads; i++)
4016 if (rld[i].out == XEXP (x, 0))
4020 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4024 /* A reload reg's contents are unknown after a label. */
4025 if (GET_CODE (insn) == CODE_LABEL)
4026 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4028 /* Don't assume a reload reg is still good after a call insn
4029 if it is a call-used reg, or if it contains a value that will
4030 be partially clobbered by the call. */
4031 else if (GET_CODE (insn) == CALL_INSN)
4033 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4034 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4039 free (reg_last_reload_reg);
4040 free (reg_has_output_reload);
4043 /* Discard all record of any value reloaded from X,
4044 or reloaded in X from someplace else;
4045 unless X is an output reload reg of the current insn.
4047 X may be a hard reg (the reload reg)
4048 or it may be a pseudo reg that was reloaded from. */
4051 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4052 void *data ATTRIBUTE_UNUSED)
4057 /* note_stores does give us subregs of hard regs,
4058 subreg_regno_offset will abort if it is not a hard reg. */
4059 while (GET_CODE (x) == SUBREG)
4061 /* We ignore the subreg offset when calculating the regno,
4062 because we are using the entire underlying hard register
4072 if (regno >= FIRST_PSEUDO_REGISTER)
4078 nr = hard_regno_nregs[regno][GET_MODE (x)];
4079 /* Storing into a spilled-reg invalidates its contents.
4080 This can happen if a block-local pseudo is allocated to that reg
4081 and it wasn't spilled because this block's total need is 0.
4082 Then some insn might have an optional reload and use this reg. */
4083 for (i = 0; i < nr; i++)
4084 /* But don't do this if the reg actually serves as an output
4085 reload reg in the current instruction. */
4087 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4089 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4090 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4091 spill_reg_store[regno + i] = 0;
4095 /* Since value of X has changed,
4096 forget any value previously copied from it. */
4099 /* But don't forget a copy if this is the output reload
4100 that establishes the copy's validity. */
4101 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4102 reg_last_reload_reg[regno + nr] = 0;
4105 /* The following HARD_REG_SETs indicate when each hard register is
4106 used for a reload of various parts of the current insn. */
4108 /* If reg is unavailable for all reloads. */
4109 static HARD_REG_SET reload_reg_unavailable;
4110 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4111 static HARD_REG_SET reload_reg_used;
4112 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4113 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4114 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4115 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4116 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4117 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4118 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4119 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4120 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4121 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4122 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4123 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4124 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4125 static HARD_REG_SET reload_reg_used_in_op_addr;
4126 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4127 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4128 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4129 static HARD_REG_SET reload_reg_used_in_insn;
4130 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4131 static HARD_REG_SET reload_reg_used_in_other_addr;
4133 /* If reg is in use as a reload reg for any sort of reload. */
4134 static HARD_REG_SET reload_reg_used_at_all;
4136 /* If reg is use as an inherited reload. We just mark the first register
4138 static HARD_REG_SET reload_reg_used_for_inherit;
4140 /* Records which hard regs are used in any way, either as explicit use or
4141 by being allocated to a pseudo during any point of the current insn. */
4142 static HARD_REG_SET reg_used_in_insn;
4144 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4145 TYPE. MODE is used to indicate how many consecutive regs are
4149 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4150 enum machine_mode mode)
4152 unsigned int nregs = hard_regno_nregs[regno][mode];
4155 for (i = regno; i < nregs + regno; i++)
4160 SET_HARD_REG_BIT (reload_reg_used, i);
4163 case RELOAD_FOR_INPUT_ADDRESS:
4164 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4167 case RELOAD_FOR_INPADDR_ADDRESS:
4168 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4171 case RELOAD_FOR_OUTPUT_ADDRESS:
4172 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4175 case RELOAD_FOR_OUTADDR_ADDRESS:
4176 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4179 case RELOAD_FOR_OPERAND_ADDRESS:
4180 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4183 case RELOAD_FOR_OPADDR_ADDR:
4184 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4187 case RELOAD_FOR_OTHER_ADDRESS:
4188 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4191 case RELOAD_FOR_INPUT:
4192 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4195 case RELOAD_FOR_OUTPUT:
4196 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4199 case RELOAD_FOR_INSN:
4200 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4204 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4208 /* Similarly, but show REGNO is no longer in use for a reload. */
4211 clear_reload_reg_in_use (unsigned int regno, int opnum,
4212 enum reload_type type, enum machine_mode mode)
4214 unsigned int nregs = hard_regno_nregs[regno][mode];
4215 unsigned int start_regno, end_regno, r;
4217 /* A complication is that for some reload types, inheritance might
4218 allow multiple reloads of the same types to share a reload register.
4219 We set check_opnum if we have to check only reloads with the same
4220 operand number, and check_any if we have to check all reloads. */
4221 int check_opnum = 0;
4223 HARD_REG_SET *used_in_set;
4228 used_in_set = &reload_reg_used;
4231 case RELOAD_FOR_INPUT_ADDRESS:
4232 used_in_set = &reload_reg_used_in_input_addr[opnum];
4235 case RELOAD_FOR_INPADDR_ADDRESS:
4237 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4240 case RELOAD_FOR_OUTPUT_ADDRESS:
4241 used_in_set = &reload_reg_used_in_output_addr[opnum];
4244 case RELOAD_FOR_OUTADDR_ADDRESS:
4246 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4249 case RELOAD_FOR_OPERAND_ADDRESS:
4250 used_in_set = &reload_reg_used_in_op_addr;
4253 case RELOAD_FOR_OPADDR_ADDR:
4255 used_in_set = &reload_reg_used_in_op_addr_reload;
4258 case RELOAD_FOR_OTHER_ADDRESS:
4259 used_in_set = &reload_reg_used_in_other_addr;
4263 case RELOAD_FOR_INPUT:
4264 used_in_set = &reload_reg_used_in_input[opnum];
4267 case RELOAD_FOR_OUTPUT:
4268 used_in_set = &reload_reg_used_in_output[opnum];
4271 case RELOAD_FOR_INSN:
4272 used_in_set = &reload_reg_used_in_insn;
4277 /* We resolve conflicts with remaining reloads of the same type by
4278 excluding the intervals of reload registers by them from the
4279 interval of freed reload registers. Since we only keep track of
4280 one set of interval bounds, we might have to exclude somewhat
4281 more than what would be necessary if we used a HARD_REG_SET here.
4282 But this should only happen very infrequently, so there should
4283 be no reason to worry about it. */
4285 start_regno = regno;
4286 end_regno = regno + nregs;
4287 if (check_opnum || check_any)
4289 for (i = n_reloads - 1; i >= 0; i--)
4291 if (rld[i].when_needed == type
4292 && (check_any || rld[i].opnum == opnum)
4295 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4296 unsigned int conflict_end
4298 + hard_regno_nregs[conflict_start][rld[i].mode]);
4300 /* If there is an overlap with the first to-be-freed register,
4301 adjust the interval start. */
4302 if (conflict_start <= start_regno && conflict_end > start_regno)
4303 start_regno = conflict_end;
4304 /* Otherwise, if there is a conflict with one of the other
4305 to-be-freed registers, adjust the interval end. */
4306 if (conflict_start > start_regno && conflict_start < end_regno)
4307 end_regno = conflict_start;
4312 for (r = start_regno; r < end_regno; r++)
4313 CLEAR_HARD_REG_BIT (*used_in_set, r);
4316 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4317 specified by OPNUM and TYPE. */
4320 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4324 /* In use for a RELOAD_OTHER means it's not available for anything. */
4325 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4326 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4332 /* In use for anything means we can't use it for RELOAD_OTHER. */
4333 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4334 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4335 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4336 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4339 for (i = 0; i < reload_n_operands; i++)
4340 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4341 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4342 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4343 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4344 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4345 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4350 case RELOAD_FOR_INPUT:
4351 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4352 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4355 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4358 /* If it is used for some other input, can't use it. */
4359 for (i = 0; i < reload_n_operands; i++)
4360 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4363 /* If it is used in a later operand's address, can't use it. */
4364 for (i = opnum + 1; i < reload_n_operands; i++)
4365 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4366 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4371 case RELOAD_FOR_INPUT_ADDRESS:
4372 /* Can't use a register if it is used for an input address for this
4373 operand or used as an input in an earlier one. */
4374 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4375 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4378 for (i = 0; i < opnum; i++)
4379 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4384 case RELOAD_FOR_INPADDR_ADDRESS:
4385 /* Can't use a register if it is used for an input address
4386 for this operand or used as an input in an earlier
4388 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4391 for (i = 0; i < opnum; i++)
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4397 case RELOAD_FOR_OUTPUT_ADDRESS:
4398 /* Can't use a register if it is used for an output address for this
4399 operand or used as an output in this or a later operand. Note
4400 that multiple output operands are emitted in reverse order, so
4401 the conflicting ones are those with lower indices. */
4402 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4405 for (i = 0; i <= opnum; i++)
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4411 case RELOAD_FOR_OUTADDR_ADDRESS:
4412 /* Can't use a register if it is used for an output address
4413 for this operand or used as an output in this or a
4414 later operand. Note that multiple output operands are
4415 emitted in reverse order, so the conflicting ones are
4416 those with lower indices. */
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4420 for (i = 0; i <= opnum; i++)
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4426 case RELOAD_FOR_OPERAND_ADDRESS:
4427 for (i = 0; i < reload_n_operands; i++)
4428 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4431 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4432 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4434 case RELOAD_FOR_OPADDR_ADDR:
4435 for (i = 0; i < reload_n_operands; i++)
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4439 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4441 case RELOAD_FOR_OUTPUT:
4442 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4443 outputs, or an operand address for this or an earlier output.
4444 Note that multiple output operands are emitted in reverse order,
4445 so the conflicting ones are those with higher indices. */
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4449 for (i = 0; i < reload_n_operands; i++)
4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4453 for (i = opnum; i < reload_n_operands; i++)
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4455 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4460 case RELOAD_FOR_INSN:
4461 for (i = 0; i < reload_n_operands; i++)
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4463 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4466 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4467 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4469 case RELOAD_FOR_OTHER_ADDRESS:
4470 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4475 /* Return 1 if the value in reload reg REGNO, as used by a reload
4476 needed for the part of the insn specified by OPNUM and TYPE,
4477 is still available in REGNO at the end of the insn.
4479 We can assume that the reload reg was already tested for availability
4480 at the time it is needed, and we should not check this again,
4481 in case the reg has already been marked in use. */
4484 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4491 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4492 its value must reach the end. */
4495 /* If this use is for part of the insn,
4496 its value reaches if no subsequent part uses the same register.
4497 Just like the above function, don't try to do this with lots
4500 case RELOAD_FOR_OTHER_ADDRESS:
4501 /* Here we check for everything else, since these don't conflict
4502 with anything else and everything comes later. */
4504 for (i = 0; i < reload_n_operands; i++)
4505 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4506 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4507 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4508 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4509 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4510 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4513 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4514 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4515 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4516 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4518 case RELOAD_FOR_INPUT_ADDRESS:
4519 case RELOAD_FOR_INPADDR_ADDRESS:
4520 /* Similar, except that we check only for this and subsequent inputs
4521 and the address of only subsequent inputs and we do not need
4522 to check for RELOAD_OTHER objects since they are known not to
4525 for (i = opnum; i < reload_n_operands; i++)
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4529 for (i = opnum + 1; i < reload_n_operands; i++)
4530 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4531 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4534 for (i = 0; i < reload_n_operands; i++)
4535 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4536 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4537 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4540 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4543 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4544 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4545 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4547 case RELOAD_FOR_INPUT:
4548 /* Similar to input address, except we start at the next operand for
4549 both input and input address and we do not check for
4550 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4553 for (i = opnum + 1; i < reload_n_operands; i++)
4554 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4555 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4556 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4559 /* ... fall through ... */
4561 case RELOAD_FOR_OPERAND_ADDRESS:
4562 /* Check outputs and their addresses. */
4564 for (i = 0; i < reload_n_operands; i++)
4565 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4566 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4567 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4570 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4572 case RELOAD_FOR_OPADDR_ADDR:
4573 for (i = 0; i < reload_n_operands; i++)
4574 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4575 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4579 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4580 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4581 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4583 case RELOAD_FOR_INSN:
4584 /* These conflict with other outputs with RELOAD_OTHER. So
4585 we need only check for output addresses. */
4587 opnum = reload_n_operands;
4589 /* ... fall through ... */
4591 case RELOAD_FOR_OUTPUT:
4592 case RELOAD_FOR_OUTPUT_ADDRESS:
4593 case RELOAD_FOR_OUTADDR_ADDRESS:
4594 /* We already know these can't conflict with a later output. So the
4595 only thing to check are later output addresses.
4596 Note that multiple output operands are emitted in reverse order,
4597 so the conflicting ones are those with lower indices. */
4598 for (i = 0; i < opnum; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4600 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4609 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4612 This function uses the same algorithm as reload_reg_free_p above. */
4615 reloads_conflict (int r1, int r2)
4617 enum reload_type r1_type = rld[r1].when_needed;
4618 enum reload_type r2_type = rld[r2].when_needed;
4619 int r1_opnum = rld[r1].opnum;
4620 int r2_opnum = rld[r2].opnum;
4622 /* RELOAD_OTHER conflicts with everything. */
4623 if (r2_type == RELOAD_OTHER)
4626 /* Otherwise, check conflicts differently for each type. */
4630 case RELOAD_FOR_INPUT:
4631 return (r2_type == RELOAD_FOR_INSN
4632 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4633 || r2_type == RELOAD_FOR_OPADDR_ADDR
4634 || r2_type == RELOAD_FOR_INPUT
4635 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4636 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4637 && r2_opnum > r1_opnum));
4639 case RELOAD_FOR_INPUT_ADDRESS:
4640 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4641 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4643 case RELOAD_FOR_INPADDR_ADDRESS:
4644 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4645 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4647 case RELOAD_FOR_OUTPUT_ADDRESS:
4648 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4649 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4651 case RELOAD_FOR_OUTADDR_ADDRESS:
4652 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4653 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4655 case RELOAD_FOR_OPERAND_ADDRESS:
4656 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4657 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4659 case RELOAD_FOR_OPADDR_ADDR:
4660 return (r2_type == RELOAD_FOR_INPUT
4661 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4663 case RELOAD_FOR_OUTPUT:
4664 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4665 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4666 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4667 && r2_opnum >= r1_opnum));
4669 case RELOAD_FOR_INSN:
4670 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4671 || r2_type == RELOAD_FOR_INSN
4672 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4674 case RELOAD_FOR_OTHER_ADDRESS:
4675 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4685 /* Indexed by reload number, 1 if incoming value
4686 inherited from previous insns. */
4687 char reload_inherited[MAX_RELOADS];
4689 /* For an inherited reload, this is the insn the reload was inherited from,
4690 if we know it. Otherwise, this is 0. */
4691 rtx reload_inheritance_insn[MAX_RELOADS];
4693 /* If nonzero, this is a place to get the value of the reload,
4694 rather than using reload_in. */
4695 rtx reload_override_in[MAX_RELOADS];
4697 /* For each reload, the hard register number of the register used,
4698 or -1 if we did not need a register for this reload. */
4699 int reload_spill_index[MAX_RELOADS];
4701 /* Subroutine of free_for_value_p, used to check a single register.
4702 START_REGNO is the starting regno of the full reload register
4703 (possibly comprising multiple hard registers) that we are considering. */
4706 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4707 enum reload_type type, rtx value, rtx out,
4708 int reloadnum, int ignore_address_reloads)
4711 /* Set if we see an input reload that must not share its reload register
4712 with any new earlyclobber, but might otherwise share the reload
4713 register with an output or input-output reload. */
4714 int check_earlyclobber = 0;
4718 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4721 if (out == const0_rtx)
4727 /* We use some pseudo 'time' value to check if the lifetimes of the
4728 new register use would overlap with the one of a previous reload
4729 that is not read-only or uses a different value.
4730 The 'time' used doesn't have to be linear in any shape or form, just
4732 Some reload types use different 'buckets' for each operand.
4733 So there are MAX_RECOG_OPERANDS different time values for each
4735 We compute TIME1 as the time when the register for the prospective
4736 new reload ceases to be live, and TIME2 for each existing
4737 reload as the time when that the reload register of that reload
4739 Where there is little to be gained by exact lifetime calculations,
4740 we just make conservative assumptions, i.e. a longer lifetime;
4741 this is done in the 'default:' cases. */
4744 case RELOAD_FOR_OTHER_ADDRESS:
4745 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4746 time1 = copy ? 0 : 1;
4749 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4751 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4752 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4753 respectively, to the time values for these, we get distinct time
4754 values. To get distinct time values for each operand, we have to
4755 multiply opnum by at least three. We round that up to four because
4756 multiply by four is often cheaper. */
4757 case RELOAD_FOR_INPADDR_ADDRESS:
4758 time1 = opnum * 4 + 2;
4760 case RELOAD_FOR_INPUT_ADDRESS:
4761 time1 = opnum * 4 + 3;
4763 case RELOAD_FOR_INPUT:
4764 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4765 executes (inclusive). */
4766 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4768 case RELOAD_FOR_OPADDR_ADDR:
4770 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4771 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4773 case RELOAD_FOR_OPERAND_ADDRESS:
4774 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4776 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4778 case RELOAD_FOR_OUTADDR_ADDRESS:
4779 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4781 case RELOAD_FOR_OUTPUT_ADDRESS:
4782 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4785 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4788 for (i = 0; i < n_reloads; i++)
4790 rtx reg = rld[i].reg_rtx;
4791 if (reg && REG_P (reg)
4792 && ((unsigned) regno - true_regnum (reg)
4793 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4796 rtx other_input = rld[i].in;
4798 /* If the other reload loads the same input value, that
4799 will not cause a conflict only if it's loading it into
4800 the same register. */
4801 if (true_regnum (reg) != start_regno)
4802 other_input = NULL_RTX;
4803 if (! other_input || ! rtx_equal_p (other_input, value)
4804 || rld[i].out || out)
4807 switch (rld[i].when_needed)
4809 case RELOAD_FOR_OTHER_ADDRESS:
4812 case RELOAD_FOR_INPADDR_ADDRESS:
4813 /* find_reloads makes sure that a
4814 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4815 by at most one - the first -
4816 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4817 address reload is inherited, the address address reload
4818 goes away, so we can ignore this conflict. */
4819 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4820 && ignore_address_reloads
4821 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4822 Then the address address is still needed to store
4823 back the new address. */
4824 && ! rld[reloadnum].out)
4826 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4827 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4829 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4830 && ignore_address_reloads
4831 /* Unless we are reloading an auto_inc expression. */
4832 && ! rld[reloadnum].out)
4834 time2 = rld[i].opnum * 4 + 2;
4836 case RELOAD_FOR_INPUT_ADDRESS:
4837 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4838 && ignore_address_reloads
4839 && ! rld[reloadnum].out)
4841 time2 = rld[i].opnum * 4 + 3;
4843 case RELOAD_FOR_INPUT:
4844 time2 = rld[i].opnum * 4 + 4;
4845 check_earlyclobber = 1;
4847 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4848 == MAX_RECOG_OPERAND * 4 */
4849 case RELOAD_FOR_OPADDR_ADDR:
4850 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4851 && ignore_address_reloads
4852 && ! rld[reloadnum].out)
4854 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4856 case RELOAD_FOR_OPERAND_ADDRESS:
4857 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4858 check_earlyclobber = 1;
4860 case RELOAD_FOR_INSN:
4861 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4863 case RELOAD_FOR_OUTPUT:
4864 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4865 instruction is executed. */
4866 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4868 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4869 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4871 case RELOAD_FOR_OUTADDR_ADDRESS:
4872 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4873 && ignore_address_reloads
4874 && ! rld[reloadnum].out)
4876 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4878 case RELOAD_FOR_OUTPUT_ADDRESS:
4879 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4882 /* If there is no conflict in the input part, handle this
4883 like an output reload. */
4884 if (! rld[i].in || rtx_equal_p (other_input, value))
4886 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4887 /* Earlyclobbered outputs must conflict with inputs. */
4888 if (earlyclobber_operand_p (rld[i].out))
4889 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4894 /* RELOAD_OTHER might be live beyond instruction execution,
4895 but this is not obvious when we set time2 = 1. So check
4896 here if there might be a problem with the new reload
4897 clobbering the register used by the RELOAD_OTHER. */
4905 && (! rld[i].in || rld[i].out
4906 || ! rtx_equal_p (other_input, value)))
4907 || (out && rld[reloadnum].out_reg
4908 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4914 /* Earlyclobbered outputs must conflict with inputs. */
4915 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4921 /* Return 1 if the value in reload reg REGNO, as used by a reload
4922 needed for the part of the insn specified by OPNUM and TYPE,
4923 may be used to load VALUE into it.
4925 MODE is the mode in which the register is used, this is needed to
4926 determine how many hard regs to test.
4928 Other read-only reloads with the same value do not conflict
4929 unless OUT is nonzero and these other reloads have to live while
4930 output reloads live.
4931 If OUT is CONST0_RTX, this is a special case: it means that the
4932 test should not be for using register REGNO as reload register, but
4933 for copying from register REGNO into the reload register.
4935 RELOADNUM is the number of the reload we want to load this value for;
4936 a reload does not conflict with itself.
4938 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4939 reloads that load an address for the very reload we are considering.
4941 The caller has to make sure that there is no conflict with the return
4945 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4946 enum reload_type type, rtx value, rtx out, int reloadnum,
4947 int ignore_address_reloads)
4949 int nregs = hard_regno_nregs[regno][mode];
4951 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4952 value, out, reloadnum,
4953 ignore_address_reloads))
4958 /* Return nonzero if the rtx X is invariant over the current function. */
4959 /* ??? Actually, the places where we use this expect exactly what
4960 * is tested here, and not everything that is function invariant. In
4961 * particular, the frame pointer and arg pointer are special cased;
4962 * pic_offset_table_rtx is not, and this will cause aborts when we
4963 * go to spill these things to memory. */
4966 function_invariant_p (rtx x)
4970 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4972 if (GET_CODE (x) == PLUS
4973 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4974 && CONSTANT_P (XEXP (x, 1)))
4979 /* Determine whether the reload reg X overlaps any rtx'es used for
4980 overriding inheritance. Return nonzero if so. */
4983 conflicts_with_override (rtx x)
4986 for (i = 0; i < n_reloads; i++)
4987 if (reload_override_in[i]
4988 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4993 /* Give an error message saying we failed to find a reload for INSN,
4994 and clear out reload R. */
4996 failed_reload (rtx insn, int r)
4998 if (asm_noperands (PATTERN (insn)) < 0)
4999 /* It's the compiler's fault. */
5000 fatal_insn ("could not find a spill register", insn);
5002 /* It's the user's fault; the operand's mode and constraint
5003 don't match. Disable this reload so we don't crash in final. */
5004 error_for_asm (insn,
5005 "`asm' operand constraint incompatible with operand size");
5009 rld[r].optional = 1;
5010 rld[r].secondary_p = 1;
5013 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5014 for reload R. If it's valid, get an rtx for it. Return nonzero if
5017 set_reload_reg (int i, int r)
5020 rtx reg = spill_reg_rtx[i];
5022 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5023 spill_reg_rtx[i] = reg
5024 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5026 regno = true_regnum (reg);
5028 /* Detect when the reload reg can't hold the reload mode.
5029 This used to be one `if', but Sequent compiler can't handle that. */
5030 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5032 enum machine_mode test_mode = VOIDmode;
5034 test_mode = GET_MODE (rld[r].in);
5035 /* If rld[r].in has VOIDmode, it means we will load it
5036 in whatever mode the reload reg has: to wit, rld[r].mode.
5037 We have already tested that for validity. */
5038 /* Aside from that, we need to test that the expressions
5039 to reload from or into have modes which are valid for this
5040 reload register. Otherwise the reload insns would be invalid. */
5041 if (! (rld[r].in != 0 && test_mode != VOIDmode
5042 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5043 if (! (rld[r].out != 0
5044 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5046 /* The reg is OK. */
5049 /* Mark as in use for this insn the reload regs we use
5051 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5052 rld[r].when_needed, rld[r].mode);
5054 rld[r].reg_rtx = reg;
5055 reload_spill_index[r] = spill_regs[i];
5062 /* Find a spill register to use as a reload register for reload R.
5063 LAST_RELOAD is nonzero if this is the last reload for the insn being
5066 Set rld[R].reg_rtx to the register allocated.
5068 We return 1 if successful, or 0 if we couldn't find a spill reg and
5069 we didn't change anything. */
5072 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5077 /* If we put this reload ahead, thinking it is a group,
5078 then insist on finding a group. Otherwise we can grab a
5079 reg that some other reload needs.
5080 (That can happen when we have a 68000 DATA_OR_FP_REG
5081 which is a group of data regs or one fp reg.)
5082 We need not be so restrictive if there are no more reloads
5085 ??? Really it would be nicer to have smarter handling
5086 for that kind of reg class, where a problem like this is normal.
5087 Perhaps those classes should be avoided for reloading
5088 by use of more alternatives. */
5090 int force_group = rld[r].nregs > 1 && ! last_reload;
5092 /* If we want a single register and haven't yet found one,
5093 take any reg in the right class and not in use.
5094 If we want a consecutive group, here is where we look for it.
5096 We use two passes so we can first look for reload regs to
5097 reuse, which are already in use for other reloads in this insn,
5098 and only then use additional registers.
5099 I think that maximizing reuse is needed to make sure we don't
5100 run out of reload regs. Suppose we have three reloads, and
5101 reloads A and B can share regs. These need two regs.
5102 Suppose A and B are given different regs.
5103 That leaves none for C. */
5104 for (pass = 0; pass < 2; pass++)
5106 /* I is the index in spill_regs.
5107 We advance it round-robin between insns to use all spill regs
5108 equally, so that inherited reloads have a chance
5109 of leapfrogging each other. */
5113 for (count = 0; count < n_spills; count++)
5115 int class = (int) rld[r].class;
5121 regnum = spill_regs[i];
5123 if ((reload_reg_free_p (regnum, rld[r].opnum,
5126 /* We check reload_reg_used to make sure we
5127 don't clobber the return register. */
5128 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5129 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5130 rld[r].when_needed, rld[r].in,
5132 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5133 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5134 /* Look first for regs to share, then for unshared. But
5135 don't share regs used for inherited reloads; they are
5136 the ones we want to preserve. */
5138 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5140 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5143 int nr = hard_regno_nregs[regnum][rld[r].mode];
5144 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5145 (on 68000) got us two FP regs. If NR is 1,
5146 we would reject both of them. */
5149 /* If we need only one reg, we have already won. */
5152 /* But reject a single reg if we demand a group. */
5157 /* Otherwise check that as many consecutive regs as we need
5158 are available here. */
5161 int regno = regnum + nr - 1;
5162 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5163 && spill_reg_order[regno] >= 0
5164 && reload_reg_free_p (regno, rld[r].opnum,
5165 rld[r].when_needed)))
5174 /* If we found something on pass 1, omit pass 2. */
5175 if (count < n_spills)
5179 /* We should have found a spill register by now. */
5180 if (count >= n_spills)
5183 /* I is the index in SPILL_REG_RTX of the reload register we are to
5184 allocate. Get an rtx for it and find its register number. */
5186 return set_reload_reg (i, r);
5189 /* Initialize all the tables needed to allocate reload registers.
5190 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5191 is the array we use to restore the reg_rtx field for every reload. */
5194 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5198 for (i = 0; i < n_reloads; i++)
5199 rld[i].reg_rtx = save_reload_reg_rtx[i];
5201 memset (reload_inherited, 0, MAX_RELOADS);
5202 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5203 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5205 CLEAR_HARD_REG_SET (reload_reg_used);
5206 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5207 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5208 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5209 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5210 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5212 CLEAR_HARD_REG_SET (reg_used_in_insn);
5215 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5216 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5217 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5218 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5219 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5220 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5223 for (i = 0; i < reload_n_operands; i++)
5225 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5226 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5227 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5228 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5229 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5230 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5233 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5235 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5237 for (i = 0; i < n_reloads; i++)
5238 /* If we have already decided to use a certain register,
5239 don't use it in another way. */
5241 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5242 rld[i].when_needed, rld[i].mode);
5245 /* Assign hard reg targets for the pseudo-registers we must reload
5246 into hard regs for this insn.
5247 Also output the instructions to copy them in and out of the hard regs.
5249 For machines with register classes, we are responsible for
5250 finding a reload reg in the proper class. */
5253 choose_reload_regs (struct insn_chain *chain)
5255 rtx insn = chain->insn;
5257 unsigned int max_group_size = 1;
5258 enum reg_class group_class = NO_REGS;
5259 int pass, win, inheritance;
5261 rtx save_reload_reg_rtx[MAX_RELOADS];
5263 /* In order to be certain of getting the registers we need,
5264 we must sort the reloads into order of increasing register class.
5265 Then our grabbing of reload registers will parallel the process
5266 that provided the reload registers.
5268 Also note whether any of the reloads wants a consecutive group of regs.
5269 If so, record the maximum size of the group desired and what
5270 register class contains all the groups needed by this insn. */
5272 for (j = 0; j < n_reloads; j++)
5274 reload_order[j] = j;
5275 reload_spill_index[j] = -1;
5277 if (rld[j].nregs > 1)
5279 max_group_size = MAX (rld[j].nregs, max_group_size);
5281 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5284 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5288 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5290 /* If -O, try first with inheritance, then turning it off.
5291 If not -O, don't do inheritance.
5292 Using inheritance when not optimizing leads to paradoxes
5293 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5294 because one side of the comparison might be inherited. */
5296 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5298 choose_reload_regs_init (chain, save_reload_reg_rtx);
5300 /* Process the reloads in order of preference just found.
5301 Beyond this point, subregs can be found in reload_reg_rtx.
5303 This used to look for an existing reloaded home for all of the
5304 reloads, and only then perform any new reloads. But that could lose
5305 if the reloads were done out of reg-class order because a later
5306 reload with a looser constraint might have an old home in a register
5307 needed by an earlier reload with a tighter constraint.
5309 To solve this, we make two passes over the reloads, in the order
5310 described above. In the first pass we try to inherit a reload
5311 from a previous insn. If there is a later reload that needs a
5312 class that is a proper subset of the class being processed, we must
5313 also allocate a spill register during the first pass.
5315 Then make a second pass over the reloads to allocate any reloads
5316 that haven't been given registers yet. */
5318 for (j = 0; j < n_reloads; j++)
5320 int r = reload_order[j];
5321 rtx search_equiv = NULL_RTX;
5323 /* Ignore reloads that got marked inoperative. */
5324 if (rld[r].out == 0 && rld[r].in == 0
5325 && ! rld[r].secondary_p)
5328 /* If find_reloads chose to use reload_in or reload_out as a reload
5329 register, we don't need to chose one. Otherwise, try even if it
5330 found one since we might save an insn if we find the value lying
5332 Try also when reload_in is a pseudo without a hard reg. */
5333 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5334 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5335 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5336 && !MEM_P (rld[r].in)
5337 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5340 #if 0 /* No longer needed for correct operation.
5341 It might give better code, or might not; worth an experiment? */
5342 /* If this is an optional reload, we can't inherit from earlier insns
5343 until we are sure that any non-optional reloads have been allocated.
5344 The following code takes advantage of the fact that optional reloads
5345 are at the end of reload_order. */
5346 if (rld[r].optional != 0)
5347 for (i = 0; i < j; i++)
5348 if ((rld[reload_order[i]].out != 0
5349 || rld[reload_order[i]].in != 0
5350 || rld[reload_order[i]].secondary_p)
5351 && ! rld[reload_order[i]].optional
5352 && rld[reload_order[i]].reg_rtx == 0)
5353 allocate_reload_reg (chain, reload_order[i], 0);
5356 /* First see if this pseudo is already available as reloaded
5357 for a previous insn. We cannot try to inherit for reloads
5358 that are smaller than the maximum number of registers needed
5359 for groups unless the register we would allocate cannot be used
5362 We could check here to see if this is a secondary reload for
5363 an object that is already in a register of the desired class.
5364 This would avoid the need for the secondary reload register.
5365 But this is complex because we can't easily determine what
5366 objects might want to be loaded via this reload. So let a
5367 register be allocated here. In `emit_reload_insns' we suppress
5368 one of the loads in the case described above. */
5374 enum machine_mode mode = VOIDmode;
5378 else if (REG_P (rld[r].in))
5380 regno = REGNO (rld[r].in);
5381 mode = GET_MODE (rld[r].in);
5383 else if (REG_P (rld[r].in_reg))
5385 regno = REGNO (rld[r].in_reg);
5386 mode = GET_MODE (rld[r].in_reg);
5388 else if (GET_CODE (rld[r].in_reg) == SUBREG
5389 && REG_P (SUBREG_REG (rld[r].in_reg)))
5391 byte = SUBREG_BYTE (rld[r].in_reg);
5392 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5393 if (regno < FIRST_PSEUDO_REGISTER)
5394 regno = subreg_regno (rld[r].in_reg);
5395 mode = GET_MODE (rld[r].in_reg);
5398 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5399 || GET_CODE (rld[r].in_reg) == PRE_DEC
5400 || GET_CODE (rld[r].in_reg) == POST_INC
5401 || GET_CODE (rld[r].in_reg) == POST_DEC)
5402 && REG_P (XEXP (rld[r].in_reg, 0)))
5404 regno = REGNO (XEXP (rld[r].in_reg, 0));
5405 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5406 rld[r].out = rld[r].in;
5410 /* This won't work, since REGNO can be a pseudo reg number.
5411 Also, it takes much more hair to keep track of all the things
5412 that can invalidate an inherited reload of part of a pseudoreg. */
5413 else if (GET_CODE (rld[r].in) == SUBREG
5414 && REG_P (SUBREG_REG (rld[r].in)))
5415 regno = subreg_regno (rld[r].in);
5418 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5420 enum reg_class class = rld[r].class, last_class;
5421 rtx last_reg = reg_last_reload_reg[regno];
5422 enum machine_mode need_mode;
5424 i = REGNO (last_reg);
5425 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5426 last_class = REGNO_REG_CLASS (i);
5432 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5433 GET_MODE_CLASS (mode));
5436 #ifdef CANNOT_CHANGE_MODE_CLASS
5437 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5441 (GET_MODE_SIZE (GET_MODE (last_reg))
5442 >= GET_MODE_SIZE (need_mode))
5443 #ifdef CANNOT_CHANGE_MODE_CLASS
5446 && reg_reloaded_contents[i] == regno
5447 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5448 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5449 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5450 /* Even if we can't use this register as a reload
5451 register, we might use it for reload_override_in,
5452 if copying it to the desired class is cheap
5454 || ((REGISTER_MOVE_COST (mode, last_class, class)
5455 < MEMORY_MOVE_COST (mode, class, 1))
5456 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5457 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5461 #ifdef SECONDARY_MEMORY_NEEDED
5462 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5467 && (rld[r].nregs == max_group_size
5468 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5470 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5471 rld[r].when_needed, rld[r].in,
5474 /* If a group is needed, verify that all the subsequent
5475 registers still have their values intact. */
5476 int nr = hard_regno_nregs[i][rld[r].mode];
5479 for (k = 1; k < nr; k++)
5480 if (reg_reloaded_contents[i + k] != regno
5481 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5489 last_reg = (GET_MODE (last_reg) == mode
5490 ? last_reg : gen_rtx_REG (mode, i));
5493 for (k = 0; k < nr; k++)
5494 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5497 /* We found a register that contains the
5498 value we need. If this register is the
5499 same as an `earlyclobber' operand of the
5500 current insn, just mark it as a place to
5501 reload from since we can't use it as the
5502 reload register itself. */
5504 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5505 if (reg_overlap_mentioned_for_reload_p
5506 (reg_last_reload_reg[regno],
5507 reload_earlyclobbers[i1]))
5510 if (i1 != n_earlyclobbers
5511 || ! (free_for_value_p (i, rld[r].mode,
5513 rld[r].when_needed, rld[r].in,
5515 /* Don't use it if we'd clobber a pseudo reg. */
5516 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5518 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5519 /* Don't clobber the frame pointer. */
5520 || (i == HARD_FRAME_POINTER_REGNUM
5521 && frame_pointer_needed
5523 /* Don't really use the inherited spill reg
5524 if we need it wider than we've got it. */
5525 || (GET_MODE_SIZE (rld[r].mode)
5526 > GET_MODE_SIZE (mode))
5529 /* If find_reloads chose reload_out as reload
5530 register, stay with it - that leaves the
5531 inherited register for subsequent reloads. */
5532 || (rld[r].out && rld[r].reg_rtx
5533 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5535 if (! rld[r].optional)
5537 reload_override_in[r] = last_reg;
5538 reload_inheritance_insn[r]
5539 = reg_reloaded_insn[i];
5545 /* We can use this as a reload reg. */
5546 /* Mark the register as in use for this part of
5548 mark_reload_reg_in_use (i,
5552 rld[r].reg_rtx = last_reg;
5553 reload_inherited[r] = 1;
5554 reload_inheritance_insn[r]
5555 = reg_reloaded_insn[i];
5556 reload_spill_index[r] = i;
5557 for (k = 0; k < nr; k++)
5558 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5566 /* Here's another way to see if the value is already lying around. */
5569 && ! reload_inherited[r]
5571 && (CONSTANT_P (rld[r].in)
5572 || GET_CODE (rld[r].in) == PLUS
5573 || REG_P (rld[r].in)
5574 || MEM_P (rld[r].in))
5575 && (rld[r].nregs == max_group_size
5576 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5577 search_equiv = rld[r].in;
5578 /* If this is an output reload from a simple move insn, look
5579 if an equivalence for the input is available. */
5580 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5582 rtx set = single_set (insn);
5585 && rtx_equal_p (rld[r].out, SET_DEST (set))
5586 && CONSTANT_P (SET_SRC (set)))
5587 search_equiv = SET_SRC (set);
5593 = find_equiv_reg (search_equiv, insn, rld[r].class,
5594 -1, NULL, 0, rld[r].mode);
5600 regno = REGNO (equiv);
5601 else if (GET_CODE (equiv) == SUBREG)
5603 /* This must be a SUBREG of a hard register.
5604 Make a new REG since this might be used in an
5605 address and not all machines support SUBREGs
5607 regno = subreg_regno (equiv);
5608 equiv = gen_rtx_REG (rld[r].mode, regno);
5614 /* If we found a spill reg, reject it unless it is free
5615 and of the desired class. */
5619 int bad_for_class = 0;
5620 int max_regno = regno + rld[r].nregs;
5622 for (i = regno; i < max_regno; i++)
5624 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5626 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5631 && ! free_for_value_p (regno, rld[r].mode,
5632 rld[r].opnum, rld[r].when_needed,
5633 rld[r].in, rld[r].out, r, 1))
5638 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5641 /* We found a register that contains the value we need.
5642 If this register is the same as an `earlyclobber' operand
5643 of the current insn, just mark it as a place to reload from
5644 since we can't use it as the reload register itself. */
5647 for (i = 0; i < n_earlyclobbers; i++)
5648 if (reg_overlap_mentioned_for_reload_p (equiv,
5649 reload_earlyclobbers[i]))
5651 if (! rld[r].optional)
5652 reload_override_in[r] = equiv;
5657 /* If the equiv register we have found is explicitly clobbered
5658 in the current insn, it depends on the reload type if we
5659 can use it, use it for reload_override_in, or not at all.
5660 In particular, we then can't use EQUIV for a
5661 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5665 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5666 switch (rld[r].when_needed)
5668 case RELOAD_FOR_OTHER_ADDRESS:
5669 case RELOAD_FOR_INPADDR_ADDRESS:
5670 case RELOAD_FOR_INPUT_ADDRESS:
5671 case RELOAD_FOR_OPADDR_ADDR:
5674 case RELOAD_FOR_INPUT:
5675 case RELOAD_FOR_OPERAND_ADDRESS:
5676 if (! rld[r].optional)
5677 reload_override_in[r] = equiv;
5683 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5684 switch (rld[r].when_needed)
5686 case RELOAD_FOR_OTHER_ADDRESS:
5687 case RELOAD_FOR_INPADDR_ADDRESS:
5688 case RELOAD_FOR_INPUT_ADDRESS:
5689 case RELOAD_FOR_OPADDR_ADDR:
5690 case RELOAD_FOR_OPERAND_ADDRESS:
5691 case RELOAD_FOR_INPUT:
5694 if (! rld[r].optional)
5695 reload_override_in[r] = equiv;
5703 /* If we found an equivalent reg, say no code need be generated
5704 to load it, and use it as our reload reg. */
5706 && (regno != HARD_FRAME_POINTER_REGNUM
5707 || !frame_pointer_needed))
5709 int nr = hard_regno_nregs[regno][rld[r].mode];
5711 rld[r].reg_rtx = equiv;
5712 reload_inherited[r] = 1;
5714 /* If reg_reloaded_valid is not set for this register,
5715 there might be a stale spill_reg_store lying around.
5716 We must clear it, since otherwise emit_reload_insns
5717 might delete the store. */
5718 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5719 spill_reg_store[regno] = NULL_RTX;
5720 /* If any of the hard registers in EQUIV are spill
5721 registers, mark them as in use for this insn. */
5722 for (k = 0; k < nr; k++)
5724 i = spill_reg_order[regno + k];
5727 mark_reload_reg_in_use (regno, rld[r].opnum,
5730 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5737 /* If we found a register to use already, or if this is an optional
5738 reload, we are done. */
5739 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5743 /* No longer needed for correct operation. Might or might
5744 not give better code on the average. Want to experiment? */
5746 /* See if there is a later reload that has a class different from our
5747 class that intersects our class or that requires less register
5748 than our reload. If so, we must allocate a register to this
5749 reload now, since that reload might inherit a previous reload
5750 and take the only available register in our class. Don't do this
5751 for optional reloads since they will force all previous reloads
5752 to be allocated. Also don't do this for reloads that have been
5755 for (i = j + 1; i < n_reloads; i++)
5757 int s = reload_order[i];
5759 if ((rld[s].in == 0 && rld[s].out == 0
5760 && ! rld[s].secondary_p)
5764 if ((rld[s].class != rld[r].class
5765 && reg_classes_intersect_p (rld[r].class,
5767 || rld[s].nregs < rld[r].nregs)
5774 allocate_reload_reg (chain, r, j == n_reloads - 1);
5778 /* Now allocate reload registers for anything non-optional that
5779 didn't get one yet. */
5780 for (j = 0; j < n_reloads; j++)
5782 int r = reload_order[j];
5784 /* Ignore reloads that got marked inoperative. */
5785 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5788 /* Skip reloads that already have a register allocated or are
5790 if (rld[r].reg_rtx != 0 || rld[r].optional)
5793 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5797 /* If that loop got all the way, we have won. */
5804 /* Loop around and try without any inheritance. */
5809 /* First undo everything done by the failed attempt
5810 to allocate with inheritance. */
5811 choose_reload_regs_init (chain, save_reload_reg_rtx);
5813 /* Some sanity tests to verify that the reloads found in the first
5814 pass are identical to the ones we have now. */
5815 if (chain->n_reloads != n_reloads)
5818 for (i = 0; i < n_reloads; i++)
5820 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5822 if (chain->rld[i].when_needed != rld[i].when_needed)
5824 for (j = 0; j < n_spills; j++)
5825 if (spill_regs[j] == chain->rld[i].regno)
5826 if (! set_reload_reg (j, i))
5827 failed_reload (chain->insn, i);
5831 /* If we thought we could inherit a reload, because it seemed that
5832 nothing else wanted the same reload register earlier in the insn,
5833 verify that assumption, now that all reloads have been assigned.
5834 Likewise for reloads where reload_override_in has been set. */
5836 /* If doing expensive optimizations, do one preliminary pass that doesn't
5837 cancel any inheritance, but removes reloads that have been needed only
5838 for reloads that we know can be inherited. */
5839 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5841 for (j = 0; j < n_reloads; j++)
5843 int r = reload_order[j];
5845 if (reload_inherited[r] && rld[r].reg_rtx)
5846 check_reg = rld[r].reg_rtx;
5847 else if (reload_override_in[r]
5848 && (REG_P (reload_override_in[r])
5849 || GET_CODE (reload_override_in[r]) == SUBREG))
5850 check_reg = reload_override_in[r];
5853 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5854 rld[r].opnum, rld[r].when_needed, rld[r].in,
5855 (reload_inherited[r]
5856 ? rld[r].out : const0_rtx),
5861 reload_inherited[r] = 0;
5862 reload_override_in[r] = 0;
5864 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5865 reload_override_in, then we do not need its related
5866 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5867 likewise for other reload types.
5868 We handle this by removing a reload when its only replacement
5869 is mentioned in reload_in of the reload we are going to inherit.
5870 A special case are auto_inc expressions; even if the input is
5871 inherited, we still need the address for the output. We can
5872 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5873 If we succeeded removing some reload and we are doing a preliminary
5874 pass just to remove such reloads, make another pass, since the
5875 removal of one reload might allow us to inherit another one. */
5877 && rld[r].out != rld[r].in
5878 && remove_address_replacements (rld[r].in) && pass)
5883 /* Now that reload_override_in is known valid,
5884 actually override reload_in. */
5885 for (j = 0; j < n_reloads; j++)
5886 if (reload_override_in[j])
5887 rld[j].in = reload_override_in[j];
5889 /* If this reload won't be done because it has been canceled or is
5890 optional and not inherited, clear reload_reg_rtx so other
5891 routines (such as subst_reloads) don't get confused. */
5892 for (j = 0; j < n_reloads; j++)
5893 if (rld[j].reg_rtx != 0
5894 && ((rld[j].optional && ! reload_inherited[j])
5895 || (rld[j].in == 0 && rld[j].out == 0
5896 && ! rld[j].secondary_p)))
5898 int regno = true_regnum (rld[j].reg_rtx);
5900 if (spill_reg_order[regno] >= 0)
5901 clear_reload_reg_in_use (regno, rld[j].opnum,
5902 rld[j].when_needed, rld[j].mode);
5904 reload_spill_index[j] = -1;
5907 /* Record which pseudos and which spill regs have output reloads. */
5908 for (j = 0; j < n_reloads; j++)
5910 int r = reload_order[j];
5912 i = reload_spill_index[r];
5914 /* I is nonneg if this reload uses a register.
5915 If rld[r].reg_rtx is 0, this is an optional reload
5916 that we opted to ignore. */
5917 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5918 && rld[r].reg_rtx != 0)
5920 int nregno = REGNO (rld[r].out_reg);
5923 if (nregno < FIRST_PSEUDO_REGISTER)
5924 nr = hard_regno_nregs[nregno][rld[r].mode];
5927 reg_has_output_reload[nregno + nr] = 1;
5931 nr = hard_regno_nregs[i][rld[r].mode];
5933 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5936 if (rld[r].when_needed != RELOAD_OTHER
5937 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5938 && rld[r].when_needed != RELOAD_FOR_INSN)
5944 /* Deallocate the reload register for reload R. This is called from
5945 remove_address_replacements. */
5948 deallocate_reload_reg (int r)
5952 if (! rld[r].reg_rtx)
5954 regno = true_regnum (rld[r].reg_rtx);
5956 if (spill_reg_order[regno] >= 0)
5957 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5959 reload_spill_index[r] = -1;
5962 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5963 reloads of the same item for fear that we might not have enough reload
5964 registers. However, normally they will get the same reload register
5965 and hence actually need not be loaded twice.
5967 Here we check for the most common case of this phenomenon: when we have
5968 a number of reloads for the same object, each of which were allocated
5969 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5970 reload, and is not modified in the insn itself. If we find such,
5971 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5972 This will not increase the number of spill registers needed and will
5973 prevent redundant code. */
5976 merge_assigned_reloads (rtx insn)
5980 /* Scan all the reloads looking for ones that only load values and
5981 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5982 assigned and not modified by INSN. */
5984 for (i = 0; i < n_reloads; i++)
5986 int conflicting_input = 0;
5987 int max_input_address_opnum = -1;
5988 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5990 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5991 || rld[i].out != 0 || rld[i].reg_rtx == 0
5992 || reg_set_p (rld[i].reg_rtx, insn))
5995 /* Look at all other reloads. Ensure that the only use of this
5996 reload_reg_rtx is in a reload that just loads the same value
5997 as we do. Note that any secondary reloads must be of the identical
5998 class since the values, modes, and result registers are the
5999 same, so we need not do anything with any secondary reloads. */
6001 for (j = 0; j < n_reloads; j++)
6003 if (i == j || rld[j].reg_rtx == 0
6004 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6008 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6009 && rld[j].opnum > max_input_address_opnum)
6010 max_input_address_opnum = rld[j].opnum;
6012 /* If the reload regs aren't exactly the same (e.g, different modes)
6013 or if the values are different, we can't merge this reload.
6014 But if it is an input reload, we might still merge
6015 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6017 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6018 || rld[j].out != 0 || rld[j].in == 0
6019 || ! rtx_equal_p (rld[i].in, rld[j].in))
6021 if (rld[j].when_needed != RELOAD_FOR_INPUT
6022 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6023 || rld[i].opnum > rld[j].opnum)
6024 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6026 conflicting_input = 1;
6027 if (min_conflicting_input_opnum > rld[j].opnum)
6028 min_conflicting_input_opnum = rld[j].opnum;
6032 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6033 we, in fact, found any matching reloads. */
6036 && max_input_address_opnum <= min_conflicting_input_opnum)
6038 for (j = 0; j < n_reloads; j++)
6039 if (i != j && rld[j].reg_rtx != 0
6040 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6041 && (! conflicting_input
6042 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6043 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6045 rld[i].when_needed = RELOAD_OTHER;
6047 reload_spill_index[j] = -1;
6048 transfer_replacements (i, j);
6051 /* If this is now RELOAD_OTHER, look for any reloads that load
6052 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6053 if they were for inputs, RELOAD_OTHER for outputs. Note that
6054 this test is equivalent to looking for reloads for this operand
6056 /* We must take special care when there are two or more reloads to
6057 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6058 same value or a part of it; we must not change its type if there
6059 is a conflicting input. */
6061 if (rld[i].when_needed == RELOAD_OTHER)
6062 for (j = 0; j < n_reloads; j++)
6064 && rld[j].when_needed != RELOAD_OTHER
6065 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6066 && (! conflicting_input
6067 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6068 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6069 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6075 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6076 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6077 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6079 /* Check to see if we accidentally converted two reloads
6080 that use the same reload register with different inputs
6081 to the same type. If so, the resulting code won't work,
6084 for (k = 0; k < j; k++)
6085 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6086 && rld[k].when_needed == rld[j].when_needed
6087 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6088 && ! rtx_equal_p (rld[k].in, rld[j].in))
6095 /* These arrays are filled by emit_reload_insns and its subroutines. */
6096 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6097 static rtx other_input_address_reload_insns = 0;
6098 static rtx other_input_reload_insns = 0;
6099 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6100 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6101 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6102 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6103 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6104 static rtx operand_reload_insns = 0;
6105 static rtx other_operand_reload_insns = 0;
6106 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6108 /* Values to be put in spill_reg_store are put here first. */
6109 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6110 static HARD_REG_SET reg_reloaded_died;
6112 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6113 has the number J. OLD contains the value to be used as input. */
6116 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6119 rtx insn = chain->insn;
6120 rtx reloadreg = rl->reg_rtx;
6121 rtx oldequiv_reg = 0;
6124 enum machine_mode mode;
6127 /* Determine the mode to reload in.
6128 This is very tricky because we have three to choose from.
6129 There is the mode the insn operand wants (rl->inmode).
6130 There is the mode of the reload register RELOADREG.
6131 There is the intrinsic mode of the operand, which we could find
6132 by stripping some SUBREGs.
6133 It turns out that RELOADREG's mode is irrelevant:
6134 we can change that arbitrarily.
6136 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6137 then the reload reg may not support QImode moves, so use SImode.
6138 If foo is in memory due to spilling a pseudo reg, this is safe,
6139 because the QImode value is in the least significant part of a
6140 slot big enough for a SImode. If foo is some other sort of
6141 memory reference, then it is impossible to reload this case,
6142 so previous passes had better make sure this never happens.
6144 Then consider a one-word union which has SImode and one of its
6145 members is a float, being fetched as (SUBREG:SF union:SI).
6146 We must fetch that as SFmode because we could be loading into
6147 a float-only register. In this case OLD's mode is correct.
6149 Consider an immediate integer: it has VOIDmode. Here we need
6150 to get a mode from something else.
6152 In some cases, there is a fourth mode, the operand's
6153 containing mode. If the insn specifies a containing mode for
6154 this operand, it overrides all others.
6156 I am not sure whether the algorithm here is always right,
6157 but it does the right things in those cases. */
6159 mode = GET_MODE (old);
6160 if (mode == VOIDmode)
6163 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6164 /* If we need a secondary register for this operation, see if
6165 the value is already in a register in that class. Don't
6166 do this if the secondary register will be used as a scratch
6169 if (rl->secondary_in_reload >= 0
6170 && rl->secondary_in_icode == CODE_FOR_nothing
6173 = find_equiv_reg (old, insn,
6174 rld[rl->secondary_in_reload].class,
6178 /* If reloading from memory, see if there is a register
6179 that already holds the same value. If so, reload from there.
6180 We can pass 0 as the reload_reg_p argument because
6181 any other reload has either already been emitted,
6182 in which case find_equiv_reg will see the reload-insn,
6183 or has yet to be emitted, in which case it doesn't matter
6184 because we will use this equiv reg right away. */
6186 if (oldequiv == 0 && optimize
6189 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6190 && reg_renumber[REGNO (old)] < 0)))
6191 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6195 unsigned int regno = true_regnum (oldequiv);
6197 /* Don't use OLDEQUIV if any other reload changes it at an
6198 earlier stage of this insn or at this stage. */
6199 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6200 rl->in, const0_rtx, j, 0))
6203 /* If it is no cheaper to copy from OLDEQUIV into the
6204 reload register than it would be to move from memory,
6205 don't use it. Likewise, if we need a secondary register
6209 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6210 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6212 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6213 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6214 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6218 #ifdef SECONDARY_MEMORY_NEEDED
6219 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6227 /* delete_output_reload is only invoked properly if old contains
6228 the original pseudo register. Since this is replaced with a
6229 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6230 find the pseudo in RELOAD_IN_REG. */
6232 && reload_override_in[j]
6233 && REG_P (rl->in_reg))
6240 else if (REG_P (oldequiv))
6241 oldequiv_reg = oldequiv;
6242 else if (GET_CODE (oldequiv) == SUBREG)
6243 oldequiv_reg = SUBREG_REG (oldequiv);
6245 /* If we are reloading from a register that was recently stored in
6246 with an output-reload, see if we can prove there was
6247 actually no need to store the old value in it. */
6249 if (optimize && REG_P (oldequiv)
6250 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6251 && spill_reg_store[REGNO (oldequiv)]
6253 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6254 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6256 delete_output_reload (insn, j, REGNO (oldequiv));
6258 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6259 then load RELOADREG from OLDEQUIV. Note that we cannot use
6260 gen_lowpart_common since it can do the wrong thing when
6261 RELOADREG has a multi-word mode. Note that RELOADREG
6262 must always be a REG here. */
6264 if (GET_MODE (reloadreg) != mode)
6265 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6266 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6267 oldequiv = SUBREG_REG (oldequiv);
6268 if (GET_MODE (oldequiv) != VOIDmode
6269 && mode != GET_MODE (oldequiv))
6270 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6272 /* Switch to the right place to emit the reload insns. */
6273 switch (rl->when_needed)
6276 where = &other_input_reload_insns;
6278 case RELOAD_FOR_INPUT:
6279 where = &input_reload_insns[rl->opnum];
6281 case RELOAD_FOR_INPUT_ADDRESS:
6282 where = &input_address_reload_insns[rl->opnum];
6284 case RELOAD_FOR_INPADDR_ADDRESS:
6285 where = &inpaddr_address_reload_insns[rl->opnum];
6287 case RELOAD_FOR_OUTPUT_ADDRESS:
6288 where = &output_address_reload_insns[rl->opnum];
6290 case RELOAD_FOR_OUTADDR_ADDRESS:
6291 where = &outaddr_address_reload_insns[rl->opnum];
6293 case RELOAD_FOR_OPERAND_ADDRESS:
6294 where = &operand_reload_insns;
6296 case RELOAD_FOR_OPADDR_ADDR:
6297 where = &other_operand_reload_insns;
6299 case RELOAD_FOR_OTHER_ADDRESS:
6300 where = &other_input_address_reload_insns;
6306 push_to_sequence (*where);
6308 /* Auto-increment addresses must be reloaded in a special way. */
6309 if (rl->out && ! rl->out_reg)
6311 /* We are not going to bother supporting the case where a
6312 incremented register can't be copied directly from
6313 OLDEQUIV since this seems highly unlikely. */
6314 if (rl->secondary_in_reload >= 0)
6317 if (reload_inherited[j])
6318 oldequiv = reloadreg;
6320 old = XEXP (rl->in_reg, 0);
6322 if (optimize && REG_P (oldequiv)
6323 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6324 && spill_reg_store[REGNO (oldequiv)]
6326 && (dead_or_set_p (insn,
6327 spill_reg_stored_to[REGNO (oldequiv)])
6328 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6330 delete_output_reload (insn, j, REGNO (oldequiv));
6332 /* Prevent normal processing of this reload. */
6334 /* Output a special code sequence for this case. */
6335 new_spill_reg_store[REGNO (reloadreg)]
6336 = inc_for_reload (reloadreg, oldequiv, rl->out,
6340 /* If we are reloading a pseudo-register that was set by the previous
6341 insn, see if we can get rid of that pseudo-register entirely
6342 by redirecting the previous insn into our reload register. */
6344 else if (optimize && REG_P (old)
6345 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6346 && dead_or_set_p (insn, old)
6347 /* This is unsafe if some other reload
6348 uses the same reg first. */
6349 && ! conflicts_with_override (reloadreg)
6350 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6351 rl->when_needed, old, rl->out, j, 0))
6353 rtx temp = PREV_INSN (insn);
6354 while (temp && GET_CODE (temp) == NOTE)
6355 temp = PREV_INSN (temp);
6357 && GET_CODE (temp) == INSN
6358 && GET_CODE (PATTERN (temp)) == SET
6359 && SET_DEST (PATTERN (temp)) == old
6360 /* Make sure we can access insn_operand_constraint. */
6361 && asm_noperands (PATTERN (temp)) < 0
6362 /* This is unsafe if operand occurs more than once in current
6363 insn. Perhaps some occurrences aren't reloaded. */
6364 && count_occurrences (PATTERN (insn), old, 0) == 1)
6366 rtx old = SET_DEST (PATTERN (temp));
6367 /* Store into the reload register instead of the pseudo. */
6368 SET_DEST (PATTERN (temp)) = reloadreg;
6370 /* Verify that resulting insn is valid. */
6371 extract_insn (temp);
6372 if (constrain_operands (1))
6374 /* If the previous insn is an output reload, the source is
6375 a reload register, and its spill_reg_store entry will
6376 contain the previous destination. This is now
6378 if (REG_P (SET_SRC (PATTERN (temp)))
6379 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6381 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6382 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6385 /* If these are the only uses of the pseudo reg,
6386 pretend for GDB it lives in the reload reg we used. */
6387 if (REG_N_DEATHS (REGNO (old)) == 1
6388 && REG_N_SETS (REGNO (old)) == 1)
6390 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6391 alter_reg (REGNO (old), -1);
6397 SET_DEST (PATTERN (temp)) = old;
6402 /* We can't do that, so output an insn to load RELOADREG. */
6404 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6405 /* If we have a secondary reload, pick up the secondary register
6406 and icode, if any. If OLDEQUIV and OLD are different or
6407 if this is an in-out reload, recompute whether or not we
6408 still need a secondary register and what the icode should
6409 be. If we still need a secondary register and the class or
6410 icode is different, go back to reloading from OLD if using
6411 OLDEQUIV means that we got the wrong type of register. We
6412 cannot have different class or icode due to an in-out reload
6413 because we don't make such reloads when both the input and
6414 output need secondary reload registers. */
6416 if (! special && rl->secondary_in_reload >= 0)
6418 rtx second_reload_reg = 0;
6419 int secondary_reload = rl->secondary_in_reload;
6420 rtx real_oldequiv = oldequiv;
6423 enum insn_code icode;
6425 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6426 and similarly for OLD.
6427 See comments in get_secondary_reload in reload.c. */
6428 /* If it is a pseudo that cannot be replaced with its
6429 equivalent MEM, we must fall back to reload_in, which
6430 will have all the necessary substitutions registered.
6431 Likewise for a pseudo that can't be replaced with its
6432 equivalent constant.
6434 Take extra care for subregs of such pseudos. Note that
6435 we cannot use reg_equiv_mem in this case because it is
6436 not in the right mode. */
6439 if (GET_CODE (tmp) == SUBREG)
6440 tmp = SUBREG_REG (tmp);
6442 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6443 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6444 || reg_equiv_constant[REGNO (tmp)] != 0))
6446 if (! reg_equiv_mem[REGNO (tmp)]
6447 || num_not_at_initial_offset
6448 || GET_CODE (oldequiv) == SUBREG)
6449 real_oldequiv = rl->in;
6451 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6455 if (GET_CODE (tmp) == SUBREG)
6456 tmp = SUBREG_REG (tmp);
6458 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6459 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6460 || reg_equiv_constant[REGNO (tmp)] != 0))
6462 if (! reg_equiv_mem[REGNO (tmp)]
6463 || num_not_at_initial_offset
6464 || GET_CODE (old) == SUBREG)
6467 real_old = reg_equiv_mem[REGNO (tmp)];
6470 second_reload_reg = rld[secondary_reload].reg_rtx;
6471 icode = rl->secondary_in_icode;
6473 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6474 || (rl->in != 0 && rl->out != 0))
6476 enum reg_class new_class
6477 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6478 mode, real_oldequiv);
6480 if (new_class == NO_REGS)
6481 second_reload_reg = 0;
6484 enum insn_code new_icode;
6485 enum machine_mode new_mode;
6487 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6488 REGNO (second_reload_reg)))
6489 oldequiv = old, real_oldequiv = real_old;
6492 new_icode = reload_in_optab[(int) mode];
6493 if (new_icode != CODE_FOR_nothing
6494 && ((insn_data[(int) new_icode].operand[0].predicate
6495 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6497 || (insn_data[(int) new_icode].operand[1].predicate
6498 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6499 (real_oldequiv, mode)))))
6500 new_icode = CODE_FOR_nothing;
6502 if (new_icode == CODE_FOR_nothing)
6505 new_mode = insn_data[(int) new_icode].operand[2].mode;
6507 if (GET_MODE (second_reload_reg) != new_mode)
6509 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6511 oldequiv = old, real_oldequiv = real_old;
6514 = reload_adjust_reg_for_mode (second_reload_reg,
6521 /* If we still need a secondary reload register, check
6522 to see if it is being used as a scratch or intermediate
6523 register and generate code appropriately. If we need
6524 a scratch register, use REAL_OLDEQUIV since the form of
6525 the insn may depend on the actual address if it is
6528 if (second_reload_reg)
6530 if (icode != CODE_FOR_nothing)
6532 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6533 second_reload_reg));
6538 /* See if we need a scratch register to load the
6539 intermediate register (a tertiary reload). */
6540 enum insn_code tertiary_icode
6541 = rld[secondary_reload].secondary_in_icode;
6543 if (tertiary_icode != CODE_FOR_nothing)
6545 rtx third_reload_reg
6546 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6548 emit_insn ((GEN_FCN (tertiary_icode)
6549 (second_reload_reg, real_oldequiv,
6550 third_reload_reg)));
6553 gen_reload (second_reload_reg, real_oldequiv,
6557 oldequiv = second_reload_reg;
6563 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6565 rtx real_oldequiv = oldequiv;
6567 if ((REG_P (oldequiv)
6568 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6569 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6570 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6571 || (GET_CODE (oldequiv) == SUBREG
6572 && REG_P (SUBREG_REG (oldequiv))
6573 && (REGNO (SUBREG_REG (oldequiv))
6574 >= FIRST_PSEUDO_REGISTER)
6575 && ((reg_equiv_memory_loc
6576 [REGNO (SUBREG_REG (oldequiv))] != 0)
6577 || (reg_equiv_constant
6578 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6579 || (CONSTANT_P (oldequiv)
6580 && (PREFERRED_RELOAD_CLASS (oldequiv,
6581 REGNO_REG_CLASS (REGNO (reloadreg)))
6583 real_oldequiv = rl->in;
6584 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6588 if (flag_non_call_exceptions)
6589 copy_eh_notes (insn, get_insns ());
6591 /* End this sequence. */
6592 *where = get_insns ();
6595 /* Update reload_override_in so that delete_address_reloads_1
6596 can see the actual register usage. */
6598 reload_override_in[j] = oldequiv;
6601 /* Generate insns to for the output reload RL, which is for the insn described
6602 by CHAIN and has the number J. */
6604 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6607 rtx reloadreg = rl->reg_rtx;
6608 rtx insn = chain->insn;
6611 enum machine_mode mode = GET_MODE (old);
6614 if (rl->when_needed == RELOAD_OTHER)
6617 push_to_sequence (output_reload_insns[rl->opnum]);
6619 /* Determine the mode to reload in.
6620 See comments above (for input reloading). */
6622 if (mode == VOIDmode)
6624 /* VOIDmode should never happen for an output. */
6625 if (asm_noperands (PATTERN (insn)) < 0)
6626 /* It's the compiler's fault. */
6627 fatal_insn ("VOIDmode on an output", insn);
6628 error_for_asm (insn, "output operand is constant in `asm'");
6629 /* Prevent crash--use something we know is valid. */
6631 old = gen_rtx_REG (mode, REGNO (reloadreg));
6634 if (GET_MODE (reloadreg) != mode)
6635 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6637 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6639 /* If we need two reload regs, set RELOADREG to the intermediate
6640 one, since it will be stored into OLD. We might need a secondary
6641 register only for an input reload, so check again here. */
6643 if (rl->secondary_out_reload >= 0)
6647 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6648 && reg_equiv_mem[REGNO (old)] != 0)
6649 real_old = reg_equiv_mem[REGNO (old)];
6651 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6655 rtx second_reloadreg = reloadreg;
6656 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6658 /* See if RELOADREG is to be used as a scratch register
6659 or as an intermediate register. */
6660 if (rl->secondary_out_icode != CODE_FOR_nothing)
6662 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6663 (real_old, second_reloadreg, reloadreg)));
6668 /* See if we need both a scratch and intermediate reload
6671 int secondary_reload = rl->secondary_out_reload;
6672 enum insn_code tertiary_icode
6673 = rld[secondary_reload].secondary_out_icode;
6675 if (GET_MODE (reloadreg) != mode)
6676 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6678 if (tertiary_icode != CODE_FOR_nothing)
6681 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6684 /* Copy primary reload reg to secondary reload reg.
6685 (Note that these have been swapped above, then
6686 secondary reload reg to OLD using our insn.) */
6688 /* If REAL_OLD is a paradoxical SUBREG, remove it
6689 and try to put the opposite SUBREG on
6691 if (GET_CODE (real_old) == SUBREG
6692 && (GET_MODE_SIZE (GET_MODE (real_old))
6693 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6694 && 0 != (tem = gen_lowpart_common
6695 (GET_MODE (SUBREG_REG (real_old)),
6697 real_old = SUBREG_REG (real_old), reloadreg = tem;
6699 gen_reload (reloadreg, second_reloadreg,
6700 rl->opnum, rl->when_needed);
6701 emit_insn ((GEN_FCN (tertiary_icode)
6702 (real_old, reloadreg, third_reloadreg)));
6707 /* Copy between the reload regs here and then to
6710 gen_reload (reloadreg, second_reloadreg,
6711 rl->opnum, rl->when_needed);
6717 /* Output the last reload insn. */
6722 /* Don't output the last reload if OLD is not the dest of
6723 INSN and is in the src and is clobbered by INSN. */
6724 if (! flag_expensive_optimizations
6726 || !(set = single_set (insn))
6727 || rtx_equal_p (old, SET_DEST (set))
6728 || !reg_mentioned_p (old, SET_SRC (set))
6729 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6730 gen_reload (old, reloadreg, rl->opnum,
6734 /* Look at all insns we emitted, just to be safe. */
6735 for (p = get_insns (); p; p = NEXT_INSN (p))
6738 rtx pat = PATTERN (p);
6740 /* If this output reload doesn't come from a spill reg,
6741 clear any memory of reloaded copies of the pseudo reg.
6742 If this output reload comes from a spill reg,
6743 reg_has_output_reload will make this do nothing. */
6744 note_stores (pat, forget_old_reloads_1, NULL);
6746 if (reg_mentioned_p (rl->reg_rtx, pat))
6748 rtx set = single_set (insn);
6749 if (reload_spill_index[j] < 0
6751 && SET_SRC (set) == rl->reg_rtx)
6753 int src = REGNO (SET_SRC (set));
6755 reload_spill_index[j] = src;
6756 SET_HARD_REG_BIT (reg_is_output_reload, src);
6757 if (find_regno_note (insn, REG_DEAD, src))
6758 SET_HARD_REG_BIT (reg_reloaded_died, src);
6760 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6762 int s = rl->secondary_out_reload;
6763 set = single_set (p);
6764 /* If this reload copies only to the secondary reload
6765 register, the secondary reload does the actual
6767 if (s >= 0 && set == NULL_RTX)
6768 /* We can't tell what function the secondary reload
6769 has and where the actual store to the pseudo is
6770 made; leave new_spill_reg_store alone. */
6773 && SET_SRC (set) == rl->reg_rtx
6774 && SET_DEST (set) == rld[s].reg_rtx)
6776 /* Usually the next instruction will be the
6777 secondary reload insn; if we can confirm
6778 that it is, setting new_spill_reg_store to
6779 that insn will allow an extra optimization. */
6780 rtx s_reg = rld[s].reg_rtx;
6781 rtx next = NEXT_INSN (p);
6782 rld[s].out = rl->out;
6783 rld[s].out_reg = rl->out_reg;
6784 set = single_set (next);
6785 if (set && SET_SRC (set) == s_reg
6786 && ! new_spill_reg_store[REGNO (s_reg)])
6788 SET_HARD_REG_BIT (reg_is_output_reload,
6790 new_spill_reg_store[REGNO (s_reg)] = next;
6794 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6799 if (rl->when_needed == RELOAD_OTHER)
6801 emit_insn (other_output_reload_insns[rl->opnum]);
6802 other_output_reload_insns[rl->opnum] = get_insns ();
6805 output_reload_insns[rl->opnum] = get_insns ();
6807 if (flag_non_call_exceptions)
6808 copy_eh_notes (insn, get_insns ());
6813 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6814 and has the number J. */
6816 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6818 rtx insn = chain->insn;
6819 rtx old = (rl->in && MEM_P (rl->in)
6820 ? rl->in_reg : rl->in);
6823 /* AUTO_INC reloads need to be handled even if inherited. We got an
6824 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6825 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6826 && ! rtx_equal_p (rl->reg_rtx, old)
6827 && rl->reg_rtx != 0)
6828 emit_input_reload_insns (chain, rld + j, old, j);
6830 /* When inheriting a wider reload, we have a MEM in rl->in,
6831 e.g. inheriting a SImode output reload for
6832 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6833 if (optimize && reload_inherited[j] && rl->in
6835 && MEM_P (rl->in_reg)
6836 && reload_spill_index[j] >= 0
6837 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6838 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6840 /* If we are reloading a register that was recently stored in with an
6841 output-reload, see if we can prove there was
6842 actually no need to store the old value in it. */
6845 && (reload_inherited[j] || reload_override_in[j])
6847 && REG_P (rl->reg_rtx)
6848 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6850 /* There doesn't seem to be any reason to restrict this to pseudos
6851 and doing so loses in the case where we are copying from a
6852 register of the wrong class. */
6853 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6854 >= FIRST_PSEUDO_REGISTER)
6856 /* The insn might have already some references to stackslots
6857 replaced by MEMs, while reload_out_reg still names the
6859 && (dead_or_set_p (insn,
6860 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6861 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6863 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6866 /* Do output reloading for reload RL, which is for the insn described by
6867 CHAIN and has the number J.
6868 ??? At some point we need to support handling output reloads of
6869 JUMP_INSNs or insns that set cc0. */
6871 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6874 rtx insn = chain->insn;
6875 /* If this is an output reload that stores something that is
6876 not loaded in this same reload, see if we can eliminate a previous
6878 rtx pseudo = rl->out_reg;
6883 && ! rtx_equal_p (rl->in_reg, pseudo)
6884 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6885 && reg_last_reload_reg[REGNO (pseudo)])
6887 int pseudo_no = REGNO (pseudo);
6888 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6890 /* We don't need to test full validity of last_regno for
6891 inherit here; we only want to know if the store actually
6892 matches the pseudo. */
6893 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6894 && reg_reloaded_contents[last_regno] == pseudo_no
6895 && spill_reg_store[last_regno]
6896 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6897 delete_output_reload (insn, j, last_regno);
6902 || rl->reg_rtx == old
6903 || rl->reg_rtx == 0)
6906 /* An output operand that dies right away does need a reload,
6907 but need not be copied from it. Show the new location in the
6909 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6910 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6912 XEXP (note, 0) = rl->reg_rtx;
6915 /* Likewise for a SUBREG of an operand that dies. */
6916 else if (GET_CODE (old) == SUBREG
6917 && REG_P (SUBREG_REG (old))
6918 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6921 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6925 else if (GET_CODE (old) == SCRATCH)
6926 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6927 but we don't want to make an output reload. */
6930 /* If is a JUMP_INSN, we can't support output reloads yet. */
6931 if (GET_CODE (insn) == JUMP_INSN)
6934 emit_output_reload_insns (chain, rld + j, j);
6937 /* Reload number R reloads from or to a group of hard registers starting at
6938 register REGNO. Return true if it can be treated for inheritance purposes
6939 like a group of reloads, each one reloading a single hard register.
6940 The caller has already checked that the spill register and REGNO use
6941 the same number of registers to store the reload value. */
6944 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6946 #ifdef CANNOT_CHANGE_MODE_CLASS
6947 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6948 GET_MODE (rld[r].reg_rtx),
6949 reg_raw_mode[reload_spill_index[r]])
6950 && !REG_CANNOT_CHANGE_MODE_P (regno,
6951 GET_MODE (rld[r].reg_rtx),
6952 reg_raw_mode[regno]));
6958 /* Output insns to reload values in and out of the chosen reload regs. */
6961 emit_reload_insns (struct insn_chain *chain)
6963 rtx insn = chain->insn;
6967 CLEAR_HARD_REG_SET (reg_reloaded_died);
6969 for (j = 0; j < reload_n_operands; j++)
6970 input_reload_insns[j] = input_address_reload_insns[j]
6971 = inpaddr_address_reload_insns[j]
6972 = output_reload_insns[j] = output_address_reload_insns[j]
6973 = outaddr_address_reload_insns[j]
6974 = other_output_reload_insns[j] = 0;
6975 other_input_address_reload_insns = 0;
6976 other_input_reload_insns = 0;
6977 operand_reload_insns = 0;
6978 other_operand_reload_insns = 0;
6980 /* Dump reloads into the dump file. */
6983 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6984 debug_reload_to_stream (dump_file);
6987 /* Now output the instructions to copy the data into and out of the
6988 reload registers. Do these in the order that the reloads were reported,
6989 since reloads of base and index registers precede reloads of operands
6990 and the operands may need the base and index registers reloaded. */
6992 for (j = 0; j < n_reloads; j++)
6995 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6996 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6998 do_input_reload (chain, rld + j, j);
6999 do_output_reload (chain, rld + j, j);
7002 /* Now write all the insns we made for reloads in the order expected by
7003 the allocation functions. Prior to the insn being reloaded, we write
7004 the following reloads:
7006 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7008 RELOAD_OTHER reloads.
7010 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7011 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7012 RELOAD_FOR_INPUT reload for the operand.
7014 RELOAD_FOR_OPADDR_ADDRS reloads.
7016 RELOAD_FOR_OPERAND_ADDRESS reloads.
7018 After the insn being reloaded, we write the following:
7020 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7021 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7022 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7023 reloads for the operand. The RELOAD_OTHER output reloads are
7024 output in descending order by reload number. */
7026 emit_insn_before_sameloc (other_input_address_reload_insns, insn);
7027 emit_insn_before_sameloc (other_input_reload_insns, insn);
7029 for (j = 0; j < reload_n_operands; j++)
7031 emit_insn_before_sameloc (inpaddr_address_reload_insns[j], insn);
7032 emit_insn_before_sameloc (input_address_reload_insns[j], insn);
7033 emit_insn_before_sameloc (input_reload_insns[j], insn);
7036 emit_insn_before_sameloc (other_operand_reload_insns, insn);
7037 emit_insn_before_sameloc (operand_reload_insns, insn);
7039 for (j = 0; j < reload_n_operands; j++)
7041 rtx x = emit_insn_after_sameloc (outaddr_address_reload_insns[j], insn);
7042 x = emit_insn_after_sameloc (output_address_reload_insns[j], x);
7043 x = emit_insn_after_sameloc (output_reload_insns[j], x);
7044 emit_insn_after_sameloc (other_output_reload_insns[j], x);
7047 /* For all the spill regs newly reloaded in this instruction,
7048 record what they were reloaded from, so subsequent instructions
7049 can inherit the reloads.
7051 Update spill_reg_store for the reloads of this insn.
7052 Copy the elements that were updated in the loop above. */
7054 for (j = 0; j < n_reloads; j++)
7056 int r = reload_order[j];
7057 int i = reload_spill_index[r];
7059 /* If this is a non-inherited input reload from a pseudo, we must
7060 clear any memory of a previous store to the same pseudo. Only do
7061 something if there will not be an output reload for the pseudo
7063 if (rld[r].in_reg != 0
7064 && ! (reload_inherited[r] || reload_override_in[r]))
7066 rtx reg = rld[r].in_reg;
7068 if (GET_CODE (reg) == SUBREG)
7069 reg = SUBREG_REG (reg);
7072 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7073 && ! reg_has_output_reload[REGNO (reg)])
7075 int nregno = REGNO (reg);
7077 if (reg_last_reload_reg[nregno])
7079 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7081 if (reg_reloaded_contents[last_regno] == nregno)
7082 spill_reg_store[last_regno] = 0;
7087 /* I is nonneg if this reload used a register.
7088 If rld[r].reg_rtx is 0, this is an optional reload
7089 that we opted to ignore. */
7091 if (i >= 0 && rld[r].reg_rtx != 0)
7093 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7095 int part_reaches_end = 0;
7096 int all_reaches_end = 1;
7098 /* For a multi register reload, we need to check if all or part
7099 of the value lives to the end. */
7100 for (k = 0; k < nr; k++)
7102 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7103 rld[r].when_needed))
7104 part_reaches_end = 1;
7106 all_reaches_end = 0;
7109 /* Ignore reloads that don't reach the end of the insn in
7111 if (all_reaches_end)
7113 /* First, clear out memory of what used to be in this spill reg.
7114 If consecutive registers are used, clear them all. */
7116 for (k = 0; k < nr; k++)
7118 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7119 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7122 /* Maybe the spill reg contains a copy of reload_out. */
7124 && (REG_P (rld[r].out)
7128 || REG_P (rld[r].out_reg)))
7130 rtx out = (REG_P (rld[r].out)
7134 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7135 int nregno = REGNO (out);
7136 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7137 : hard_regno_nregs[nregno]
7138 [GET_MODE (rld[r].reg_rtx)]);
7141 spill_reg_store[i] = new_spill_reg_store[i];
7142 spill_reg_stored_to[i] = out;
7143 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7145 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7147 && inherit_piecemeal_p (r, nregno));
7149 /* If NREGNO is a hard register, it may occupy more than
7150 one register. If it does, say what is in the
7151 rest of the registers assuming that both registers
7152 agree on how many words the object takes. If not,
7153 invalidate the subsequent registers. */
7155 if (nregno < FIRST_PSEUDO_REGISTER)
7156 for (k = 1; k < nnr; k++)
7157 reg_last_reload_reg[nregno + k]
7159 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7162 /* Now do the inverse operation. */
7163 for (k = 0; k < nr; k++)
7165 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7166 reg_reloaded_contents[i + k]
7167 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7170 reg_reloaded_insn[i + k] = insn;
7171 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7172 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7173 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7177 /* Maybe the spill reg contains a copy of reload_in. Only do
7178 something if there will not be an output reload for
7179 the register being reloaded. */
7180 else if (rld[r].out_reg == 0
7182 && ((REG_P (rld[r].in)
7183 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7184 && ! reg_has_output_reload[REGNO (rld[r].in)])
7185 || (REG_P (rld[r].in_reg)
7186 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7187 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7194 if (REG_P (rld[r].in)
7195 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7197 else if (REG_P (rld[r].in_reg))
7200 in = XEXP (rld[r].in_reg, 0);
7201 nregno = REGNO (in);
7203 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7204 : hard_regno_nregs[nregno]
7205 [GET_MODE (rld[r].reg_rtx)]);
7207 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7209 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7211 && inherit_piecemeal_p (r, nregno));
7213 if (nregno < FIRST_PSEUDO_REGISTER)
7214 for (k = 1; k < nnr; k++)
7215 reg_last_reload_reg[nregno + k]
7217 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7220 /* Unless we inherited this reload, show we haven't
7221 recently done a store.
7222 Previous stores of inherited auto_inc expressions
7223 also have to be discarded. */
7224 if (! reload_inherited[r]
7225 || (rld[r].out && ! rld[r].out_reg))
7226 spill_reg_store[i] = 0;
7228 for (k = 0; k < nr; k++)
7230 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7231 reg_reloaded_contents[i + k]
7232 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7235 reg_reloaded_insn[i + k] = insn;
7236 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7237 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7238 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7243 /* However, if part of the reload reaches the end, then we must
7244 invalidate the old info for the part that survives to the end. */
7245 else if (part_reaches_end)
7247 for (k = 0; k < nr; k++)
7248 if (reload_reg_reaches_end_p (i + k,
7250 rld[r].when_needed))
7251 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7255 /* The following if-statement was #if 0'd in 1.34 (or before...).
7256 It's reenabled in 1.35 because supposedly nothing else
7257 deals with this problem. */
7259 /* If a register gets output-reloaded from a non-spill register,
7260 that invalidates any previous reloaded copy of it.
7261 But forget_old_reloads_1 won't get to see it, because
7262 it thinks only about the original insn. So invalidate it here. */
7263 if (i < 0 && rld[r].out != 0
7264 && (REG_P (rld[r].out)
7265 || (MEM_P (rld[r].out)
7266 && REG_P (rld[r].out_reg))))
7268 rtx out = (REG_P (rld[r].out)
7269 ? rld[r].out : rld[r].out_reg);
7270 int nregno = REGNO (out);
7271 if (nregno >= FIRST_PSEUDO_REGISTER)
7273 rtx src_reg, store_insn = NULL_RTX;
7275 reg_last_reload_reg[nregno] = 0;
7277 /* If we can find a hard register that is stored, record
7278 the storing insn so that we may delete this insn with
7279 delete_output_reload. */
7280 src_reg = rld[r].reg_rtx;
7282 /* If this is an optional reload, try to find the source reg
7283 from an input reload. */
7286 rtx set = single_set (insn);
7287 if (set && SET_DEST (set) == rld[r].out)
7291 src_reg = SET_SRC (set);
7293 for (k = 0; k < n_reloads; k++)
7295 if (rld[k].in == src_reg)
7297 src_reg = rld[k].reg_rtx;
7304 store_insn = new_spill_reg_store[REGNO (src_reg)];
7305 if (src_reg && REG_P (src_reg)
7306 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7308 int src_regno = REGNO (src_reg);
7309 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7310 /* The place where to find a death note varies with
7311 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7312 necessarily checked exactly in the code that moves
7313 notes, so just check both locations. */
7314 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7315 if (! note && store_insn)
7316 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7319 spill_reg_store[src_regno + nr] = store_insn;
7320 spill_reg_stored_to[src_regno + nr] = out;
7321 reg_reloaded_contents[src_regno + nr] = nregno;
7322 reg_reloaded_insn[src_regno + nr] = store_insn;
7323 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7324 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7325 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7326 GET_MODE (src_reg)))
7327 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7329 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7331 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7333 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7335 reg_last_reload_reg[nregno] = src_reg;
7336 /* We have to set reg_has_output_reload here, or else
7337 forget_old_reloads_1 will clear reg_last_reload_reg
7339 reg_has_output_reload[nregno] = 1;
7344 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7346 while (num_regs-- > 0)
7347 reg_last_reload_reg[nregno + num_regs] = 0;
7351 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7354 /* Emit code to perform a reload from IN (which may be a reload register) to
7355 OUT (which may also be a reload register). IN or OUT is from operand
7356 OPNUM with reload type TYPE.
7358 Returns first insn emitted. */
7361 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7363 rtx last = get_last_insn ();
7366 /* If IN is a paradoxical SUBREG, remove it and try to put the
7367 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7368 if (GET_CODE (in) == SUBREG
7369 && (GET_MODE_SIZE (GET_MODE (in))
7370 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7371 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7372 in = SUBREG_REG (in), out = tem;
7373 else if (GET_CODE (out) == SUBREG
7374 && (GET_MODE_SIZE (GET_MODE (out))
7375 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7376 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7377 out = SUBREG_REG (out), in = tem;
7379 /* How to do this reload can get quite tricky. Normally, we are being
7380 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7381 register that didn't get a hard register. In that case we can just
7382 call emit_move_insn.
7384 We can also be asked to reload a PLUS that adds a register or a MEM to
7385 another register, constant or MEM. This can occur during frame pointer
7386 elimination and while reloading addresses. This case is handled by
7387 trying to emit a single insn to perform the add. If it is not valid,
7388 we use a two insn sequence.
7390 Finally, we could be called to handle an 'o' constraint by putting
7391 an address into a register. In that case, we first try to do this
7392 with a named pattern of "reload_load_address". If no such pattern
7393 exists, we just emit a SET insn and hope for the best (it will normally
7394 be valid on machines that use 'o').
7396 This entire process is made complex because reload will never
7397 process the insns we generate here and so we must ensure that
7398 they will fit their constraints and also by the fact that parts of
7399 IN might be being reloaded separately and replaced with spill registers.
7400 Because of this, we are, in some sense, just guessing the right approach
7401 here. The one listed above seems to work.
7403 ??? At some point, this whole thing needs to be rethought. */
7405 if (GET_CODE (in) == PLUS
7406 && (REG_P (XEXP (in, 0))
7407 || GET_CODE (XEXP (in, 0)) == SUBREG
7408 || MEM_P (XEXP (in, 0)))
7409 && (REG_P (XEXP (in, 1))
7410 || GET_CODE (XEXP (in, 1)) == SUBREG
7411 || CONSTANT_P (XEXP (in, 1))
7412 || MEM_P (XEXP (in, 1))))
7414 /* We need to compute the sum of a register or a MEM and another
7415 register, constant, or MEM, and put it into the reload
7416 register. The best possible way of doing this is if the machine
7417 has a three-operand ADD insn that accepts the required operands.
7419 The simplest approach is to try to generate such an insn and see if it
7420 is recognized and matches its constraints. If so, it can be used.
7422 It might be better not to actually emit the insn unless it is valid,
7423 but we need to pass the insn as an operand to `recog' and
7424 `extract_insn' and it is simpler to emit and then delete the insn if
7425 not valid than to dummy things up. */
7427 rtx op0, op1, tem, insn;
7430 op0 = find_replacement (&XEXP (in, 0));
7431 op1 = find_replacement (&XEXP (in, 1));
7433 /* Since constraint checking is strict, commutativity won't be
7434 checked, so we need to do that here to avoid spurious failure
7435 if the add instruction is two-address and the second operand
7436 of the add is the same as the reload reg, which is frequently
7437 the case. If the insn would be A = B + A, rearrange it so
7438 it will be A = A + B as constrain_operands expects. */
7440 if (REG_P (XEXP (in, 1))
7441 && REGNO (out) == REGNO (XEXP (in, 1)))
7442 tem = op0, op0 = op1, op1 = tem;
7444 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7445 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7447 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7448 code = recog_memoized (insn);
7452 extract_insn (insn);
7453 /* We want constrain operands to treat this insn strictly in
7454 its validity determination, i.e., the way it would after reload
7456 if (constrain_operands (1))
7460 delete_insns_since (last);
7462 /* If that failed, we must use a conservative two-insn sequence.
7464 Use a move to copy one operand into the reload register. Prefer
7465 to reload a constant, MEM or pseudo since the move patterns can
7466 handle an arbitrary operand. If OP1 is not a constant, MEM or
7467 pseudo and OP1 is not a valid operand for an add instruction, then
7470 After reloading one of the operands into the reload register, add
7471 the reload register to the output register.
7473 If there is another way to do this for a specific machine, a
7474 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7477 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7479 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7481 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7482 || (code != CODE_FOR_nothing
7483 && ! ((*insn_data[code].operand[2].predicate)
7484 (op1, insn_data[code].operand[2].mode))))
7485 tem = op0, op0 = op1, op1 = tem;
7487 gen_reload (out, op0, opnum, type);
7489 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7490 This fixes a problem on the 32K where the stack pointer cannot
7491 be used as an operand of an add insn. */
7493 if (rtx_equal_p (op0, op1))
7496 insn = emit_insn (gen_add2_insn (out, op1));
7498 /* If that failed, copy the address register to the reload register.
7499 Then add the constant to the reload register. */
7501 code = recog_memoized (insn);
7505 extract_insn (insn);
7506 /* We want constrain operands to treat this insn strictly in
7507 its validity determination, i.e., the way it would after reload
7509 if (constrain_operands (1))
7511 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7513 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7518 delete_insns_since (last);
7520 gen_reload (out, op1, opnum, type);
7521 insn = emit_insn (gen_add2_insn (out, op0));
7522 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7525 #ifdef SECONDARY_MEMORY_NEEDED
7526 /* If we need a memory location to do the move, do it that way. */
7527 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7528 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7529 && (REG_P (out) || GET_CODE (out) == SUBREG)
7530 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7531 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7532 REGNO_REG_CLASS (reg_or_subregno (out)),
7535 /* Get the memory to use and rewrite both registers to its mode. */
7536 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7538 if (GET_MODE (loc) != GET_MODE (out))
7539 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7541 if (GET_MODE (loc) != GET_MODE (in))
7542 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7544 gen_reload (loc, in, opnum, type);
7545 gen_reload (out, loc, opnum, type);
7549 /* If IN is a simple operand, use gen_move_insn. */
7550 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7551 emit_insn (gen_move_insn (out, in));
7553 #ifdef HAVE_reload_load_address
7554 else if (HAVE_reload_load_address)
7555 emit_insn (gen_reload_load_address (out, in));
7558 /* Otherwise, just write (set OUT IN) and hope for the best. */
7560 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7562 /* Return the first insn emitted.
7563 We can not just return get_last_insn, because there may have
7564 been multiple instructions emitted. Also note that gen_move_insn may
7565 emit more than one insn itself, so we can not assume that there is one
7566 insn emitted per emit_insn_before call. */
7568 return last ? NEXT_INSN (last) : get_insns ();
7571 /* Delete a previously made output-reload whose result we now believe
7572 is not needed. First we double-check.
7574 INSN is the insn now being processed.
7575 LAST_RELOAD_REG is the hard register number for which we want to delete
7576 the last output reload.
7577 J is the reload-number that originally used REG. The caller has made
7578 certain that reload J doesn't use REG any longer for input. */
7581 delete_output_reload (rtx insn, int j, int last_reload_reg)
7583 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7584 rtx reg = spill_reg_stored_to[last_reload_reg];
7587 int n_inherited = 0;
7591 /* It is possible that this reload has been only used to set another reload
7592 we eliminated earlier and thus deleted this instruction too. */
7593 if (INSN_DELETED_P (output_reload_insn))
7596 /* Get the raw pseudo-register referred to. */
7598 while (GET_CODE (reg) == SUBREG)
7599 reg = SUBREG_REG (reg);
7600 substed = reg_equiv_memory_loc[REGNO (reg)];
7602 /* This is unsafe if the operand occurs more often in the current
7603 insn than it is inherited. */
7604 for (k = n_reloads - 1; k >= 0; k--)
7606 rtx reg2 = rld[k].in;
7609 if (MEM_P (reg2) || reload_override_in[k])
7610 reg2 = rld[k].in_reg;
7612 if (rld[k].out && ! rld[k].out_reg)
7613 reg2 = XEXP (rld[k].in_reg, 0);
7615 while (GET_CODE (reg2) == SUBREG)
7616 reg2 = SUBREG_REG (reg2);
7617 if (rtx_equal_p (reg2, reg))
7619 if (reload_inherited[k] || reload_override_in[k] || k == j)
7622 reg2 = rld[k].out_reg;
7625 while (GET_CODE (reg2) == SUBREG)
7626 reg2 = XEXP (reg2, 0);
7627 if (rtx_equal_p (reg2, reg))
7634 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7636 n_occurrences += count_occurrences (PATTERN (insn),
7637 eliminate_regs (substed, 0,
7639 if (n_occurrences > n_inherited)
7642 /* If the pseudo-reg we are reloading is no longer referenced
7643 anywhere between the store into it and here,
7644 and no jumps or labels intervene, then the value can get
7645 here through the reload reg alone.
7646 Otherwise, give up--return. */
7647 for (i1 = NEXT_INSN (output_reload_insn);
7648 i1 != insn; i1 = NEXT_INSN (i1))
7650 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7652 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7653 && reg_mentioned_p (reg, PATTERN (i1)))
7655 /* If this is USE in front of INSN, we only have to check that
7656 there are no more references than accounted for by inheritance. */
7657 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7659 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7660 i1 = NEXT_INSN (i1);
7662 if (n_occurrences <= n_inherited && i1 == insn)
7668 /* We will be deleting the insn. Remove the spill reg information. */
7669 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7671 spill_reg_store[last_reload_reg + k] = 0;
7672 spill_reg_stored_to[last_reload_reg + k] = 0;
7675 /* The caller has already checked that REG dies or is set in INSN.
7676 It has also checked that we are optimizing, and thus some
7677 inaccuracies in the debugging information are acceptable.
7678 So we could just delete output_reload_insn. But in some cases
7679 we can improve the debugging information without sacrificing
7680 optimization - maybe even improving the code: See if the pseudo
7681 reg has been completely replaced with reload regs. If so, delete
7682 the store insn and forget we had a stack slot for the pseudo. */
7683 if (rld[j].out != rld[j].in
7684 && REG_N_DEATHS (REGNO (reg)) == 1
7685 && REG_N_SETS (REGNO (reg)) == 1
7686 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7687 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7691 /* We know that it was used only between here and the beginning of
7692 the current basic block. (We also know that the last use before
7693 INSN was the output reload we are thinking of deleting, but never
7694 mind that.) Search that range; see if any ref remains. */
7695 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7697 rtx set = single_set (i2);
7699 /* Uses which just store in the pseudo don't count,
7700 since if they are the only uses, they are dead. */
7701 if (set != 0 && SET_DEST (set) == reg)
7703 if (GET_CODE (i2) == CODE_LABEL
7704 || GET_CODE (i2) == JUMP_INSN)
7706 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7707 && reg_mentioned_p (reg, PATTERN (i2)))
7709 /* Some other ref remains; just delete the output reload we
7711 delete_address_reloads (output_reload_insn, insn);
7712 delete_insn (output_reload_insn);
7717 /* Delete the now-dead stores into this pseudo. Note that this
7718 loop also takes care of deleting output_reload_insn. */
7719 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7721 rtx set = single_set (i2);
7723 if (set != 0 && SET_DEST (set) == reg)
7725 delete_address_reloads (i2, insn);
7728 if (GET_CODE (i2) == CODE_LABEL
7729 || GET_CODE (i2) == JUMP_INSN)
7733 /* For the debugging info, say the pseudo lives in this reload reg. */
7734 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7735 alter_reg (REGNO (reg), -1);
7739 delete_address_reloads (output_reload_insn, insn);
7740 delete_insn (output_reload_insn);
7744 /* We are going to delete DEAD_INSN. Recursively delete loads of
7745 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7746 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7748 delete_address_reloads (rtx dead_insn, rtx current_insn)
7750 rtx set = single_set (dead_insn);
7751 rtx set2, dst, prev, next;
7754 rtx dst = SET_DEST (set);
7756 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7758 /* If we deleted the store from a reloaded post_{in,de}c expression,
7759 we can delete the matching adds. */
7760 prev = PREV_INSN (dead_insn);
7761 next = NEXT_INSN (dead_insn);
7762 if (! prev || ! next)
7764 set = single_set (next);
7765 set2 = single_set (prev);
7767 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7768 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7769 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7771 dst = SET_DEST (set);
7772 if (! rtx_equal_p (dst, SET_DEST (set2))
7773 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7774 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7775 || (INTVAL (XEXP (SET_SRC (set), 1))
7776 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7778 delete_related_insns (prev);
7779 delete_related_insns (next);
7782 /* Subfunction of delete_address_reloads: process registers found in X. */
7784 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7786 rtx prev, set, dst, i2;
7788 enum rtx_code code = GET_CODE (x);
7792 const char *fmt = GET_RTX_FORMAT (code);
7793 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7796 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7797 else if (fmt[i] == 'E')
7799 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7800 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7807 if (spill_reg_order[REGNO (x)] < 0)
7810 /* Scan backwards for the insn that sets x. This might be a way back due
7812 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7814 code = GET_CODE (prev);
7815 if (code == CODE_LABEL || code == JUMP_INSN)
7819 if (reg_set_p (x, PATTERN (prev)))
7821 if (reg_referenced_p (x, PATTERN (prev)))
7824 if (! prev || INSN_UID (prev) < reload_first_uid)
7826 /* Check that PREV only sets the reload register. */
7827 set = single_set (prev);
7830 dst = SET_DEST (set);
7832 || ! rtx_equal_p (dst, x))
7834 if (! reg_set_p (dst, PATTERN (dead_insn)))
7836 /* Check if DST was used in a later insn -
7837 it might have been inherited. */
7838 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7840 if (GET_CODE (i2) == CODE_LABEL)
7844 if (reg_referenced_p (dst, PATTERN (i2)))
7846 /* If there is a reference to the register in the current insn,
7847 it might be loaded in a non-inherited reload. If no other
7848 reload uses it, that means the register is set before
7850 if (i2 == current_insn)
7852 for (j = n_reloads - 1; j >= 0; j--)
7853 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7854 || reload_override_in[j] == dst)
7856 for (j = n_reloads - 1; j >= 0; j--)
7857 if (rld[j].in && rld[j].reg_rtx == dst)
7864 if (GET_CODE (i2) == JUMP_INSN)
7866 /* If DST is still live at CURRENT_INSN, check if it is used for
7867 any reload. Note that even if CURRENT_INSN sets DST, we still
7868 have to check the reloads. */
7869 if (i2 == current_insn)
7871 for (j = n_reloads - 1; j >= 0; j--)
7872 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7873 || reload_override_in[j] == dst)
7875 /* ??? We can't finish the loop here, because dst might be
7876 allocated to a pseudo in this block if no reload in this
7877 block needs any of the classes containing DST - see
7878 spill_hard_reg. There is no easy way to tell this, so we
7879 have to scan till the end of the basic block. */
7881 if (reg_set_p (dst, PATTERN (i2)))
7885 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7886 reg_reloaded_contents[REGNO (dst)] = -1;
7890 /* Output reload-insns to reload VALUE into RELOADREG.
7891 VALUE is an autoincrement or autodecrement RTX whose operand
7892 is a register or memory location;
7893 so reloading involves incrementing that location.
7894 IN is either identical to VALUE, or some cheaper place to reload from.
7896 INC_AMOUNT is the number to increment or decrement by (always positive).
7897 This cannot be deduced from VALUE.
7899 Return the instruction that stores into RELOADREG. */
7902 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7904 /* REG or MEM to be copied and incremented. */
7905 rtx incloc = XEXP (value, 0);
7906 /* Nonzero if increment after copying. */
7907 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7913 rtx real_in = in == value ? XEXP (in, 0) : in;
7915 /* No hard register is equivalent to this register after
7916 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7917 we could inc/dec that register as well (maybe even using it for
7918 the source), but I'm not sure it's worth worrying about. */
7920 reg_last_reload_reg[REGNO (incloc)] = 0;
7922 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7923 inc_amount = -inc_amount;
7925 inc = GEN_INT (inc_amount);
7927 /* If this is post-increment, first copy the location to the reload reg. */
7928 if (post && real_in != reloadreg)
7929 emit_insn (gen_move_insn (reloadreg, real_in));
7933 /* See if we can directly increment INCLOC. Use a method similar to
7934 that in gen_reload. */
7936 last = get_last_insn ();
7937 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7938 gen_rtx_PLUS (GET_MODE (incloc),
7941 code = recog_memoized (add_insn);
7944 extract_insn (add_insn);
7945 if (constrain_operands (1))
7947 /* If this is a pre-increment and we have incremented the value
7948 where it lives, copy the incremented value to RELOADREG to
7949 be used as an address. */
7952 emit_insn (gen_move_insn (reloadreg, incloc));
7957 delete_insns_since (last);
7960 /* If couldn't do the increment directly, must increment in RELOADREG.
7961 The way we do this depends on whether this is pre- or post-increment.
7962 For pre-increment, copy INCLOC to the reload register, increment it
7963 there, then save back. */
7967 if (in != reloadreg)
7968 emit_insn (gen_move_insn (reloadreg, real_in));
7969 emit_insn (gen_add2_insn (reloadreg, inc));
7970 store = emit_insn (gen_move_insn (incloc, reloadreg));
7975 Because this might be a jump insn or a compare, and because RELOADREG
7976 may not be available after the insn in an input reload, we must do
7977 the incrementation before the insn being reloaded for.
7979 We have already copied IN to RELOADREG. Increment the copy in
7980 RELOADREG, save that back, then decrement RELOADREG so it has
7981 the original value. */
7983 emit_insn (gen_add2_insn (reloadreg, inc));
7984 store = emit_insn (gen_move_insn (incloc, reloadreg));
7985 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7993 add_auto_inc_notes (rtx insn, rtx x)
7995 enum rtx_code code = GET_CODE (x);
7999 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8002 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8006 /* Scan all the operand sub-expressions. */
8007 fmt = GET_RTX_FORMAT (code);
8008 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8011 add_auto_inc_notes (insn, XEXP (x, i));
8012 else if (fmt[i] == 'E')
8013 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8014 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8019 /* Copy EH notes from an insn to its reloads. */
8021 copy_eh_notes (rtx insn, rtx x)
8023 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8026 for (; x != 0; x = NEXT_INSN (x))
8028 if (may_trap_p (PATTERN (x)))
8030 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8036 /* This is used by reload pass, that does emit some instructions after
8037 abnormal calls moving basic block end, but in fact it wants to emit
8038 them on the edge. Looks for abnormal call edges, find backward the
8039 proper call and fix the damage.
8041 Similar handle instructions throwing exceptions internally. */
8043 fixup_abnormal_edges (void)
8045 bool inserted = false;
8052 /* Look for cases we are interested in - calls or instructions causing
8054 for (e = bb->succ; e; e = e->succ_next)
8056 if (e->flags & EDGE_ABNORMAL_CALL)
8058 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8059 == (EDGE_ABNORMAL | EDGE_EH))
8062 if (e && GET_CODE (BB_END (bb)) != CALL_INSN
8063 && !can_throw_internal (BB_END (bb)))
8065 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8067 for (e = bb->succ; e; e = e->succ_next)
8068 if (e->flags & EDGE_FALLTHRU)
8070 /* Get past the new insns generated. Allow notes, as the insns may
8071 be already deleted. */
8072 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
8073 && !can_throw_internal (insn)
8074 && insn != BB_HEAD (bb))
8075 insn = PREV_INSN (insn);
8076 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
8080 insn = NEXT_INSN (insn);
8081 while (insn && insn != stop)
8083 next = NEXT_INSN (insn);
8088 /* Sometimes there's still the return value USE.
8089 If it's placed after a trapping call (i.e. that
8090 call is the last insn anyway), we have no fallthru
8091 edge. Simply delete this use and don't try to insert
8092 on the non-existent edge. */
8093 if (GET_CODE (PATTERN (insn)) != USE)
8095 /* We're not deleting it, we're moving it. */
8096 INSN_DELETED_P (insn) = 0;
8097 PREV_INSN (insn) = NULL_RTX;
8098 NEXT_INSN (insn) = NULL_RTX;
8100 insert_insn_on_edge (insn, e);
8107 /* We've possibly turned single trapping insn into multiple ones. */
8108 if (flag_non_call_exceptions)
8111 blocks = sbitmap_alloc (last_basic_block);
8112 sbitmap_ones (blocks);
8113 find_many_sub_basic_blocks (blocks);
8116 commit_edge_insertions ();
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