1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 #ifndef REGISTER_MOVE_COST
83 #define REGISTER_MOVE_COST(m, x, y) 2
87 #define LOCAL_REGNO(REGNO) 0
90 /* During reload_as_needed, element N contains a REG rtx for the hard reg
91 into which reg N has been reloaded (perhaps for a previous insn). */
92 static rtx *reg_last_reload_reg;
94 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
95 for an output reload that stores into reg N. */
96 static char *reg_has_output_reload;
98 /* Indicates which hard regs are reload-registers for an output reload
99 in the current insn. */
100 static HARD_REG_SET reg_is_output_reload;
102 /* Element N is the constant value to which pseudo reg N is equivalent,
103 or zero if pseudo reg N is not equivalent to a constant.
104 find_reloads looks at this in order to replace pseudo reg N
105 with the constant it stands for. */
106 rtx *reg_equiv_constant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx *reg_equiv_address;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
128 static rtx *reg_equiv_init;
130 /* Vector to remember old contents of reg_renumber before spilling. */
131 static short *reg_old_renumber;
133 /* During reload_as_needed, element N contains the last pseudo regno reloaded
134 into hard register N. If that pseudo reg occupied more than one register,
135 reg_reloaded_contents points to that pseudo for each spill register in
136 use; all of these must remain set for an inheritance to occur. */
137 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
139 /* During reload_as_needed, element N contains the insn for which
140 hard register N was last used. Its contents are significant only
141 when reg_reloaded_valid is set for this register. */
142 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
144 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
145 static HARD_REG_SET reg_reloaded_valid;
146 /* Indicate if the register was dead at the end of the reload.
147 This is only valid if reg_reloaded_contents is set and valid. */
148 static HARD_REG_SET reg_reloaded_dead;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Nonzero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If nonzero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the difference of the
358 number of the label and the first label number. We can't offset the
359 pointer itself as this can cause problems on machines with segmented
360 memory. The first table is an array of flags that records whether we
361 have yet encountered a label and the second table is an array of arrays,
362 one entry in the latter array for each elimination. */
364 static int first_label_num;
365 static char *offsets_known_at;
366 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
368 /* Number of labels in the current function. */
370 static int num_labels;
372 static void replace_pseudos_in PARAMS ((rtx *, enum machine_mode, rtx));
373 static void maybe_fix_stack_asms PARAMS ((void));
374 static void copy_reloads PARAMS ((struct insn_chain *));
375 static void calculate_needs_all_insns PARAMS ((int));
376 static int find_reg PARAMS ((struct insn_chain *, int));
377 static void find_reload_regs PARAMS ((struct insn_chain *));
378 static void select_reload_regs PARAMS ((void));
379 static void delete_caller_save_insns PARAMS ((void));
381 static void spill_failure PARAMS ((rtx, enum reg_class));
382 static void count_spilled_pseudo PARAMS ((int, int, int));
383 static void delete_dead_insn PARAMS ((rtx));
384 static void alter_reg PARAMS ((int, int));
385 static void set_label_offsets PARAMS ((rtx, rtx, int));
386 static void check_eliminable_occurrences PARAMS ((rtx));
387 static void elimination_effects PARAMS ((rtx, enum machine_mode));
388 static int eliminate_regs_in_insn PARAMS ((rtx, int));
389 static void update_eliminable_offsets PARAMS ((void));
390 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
391 static void set_initial_elim_offsets PARAMS ((void));
392 static void verify_initial_elim_offsets PARAMS ((void));
393 static void set_initial_label_offsets PARAMS ((void));
394 static void set_offsets_for_label PARAMS ((rtx));
395 static void init_elim_table PARAMS ((void));
396 static void update_eliminables PARAMS ((HARD_REG_SET *));
397 static void spill_hard_reg PARAMS ((unsigned int, int));
398 static int finish_spills PARAMS ((int));
399 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
400 static void scan_paradoxical_subregs PARAMS ((rtx));
401 static void count_pseudo PARAMS ((int));
402 static void order_regs_for_reload PARAMS ((struct insn_chain *));
403 static void reload_as_needed PARAMS ((int));
404 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
405 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
406 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
409 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
412 static int reload_reg_free_p PARAMS ((unsigned int, int,
414 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
416 rtx, rtx, int, int));
417 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
418 enum reload_type, rtx, rtx,
420 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
422 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
424 static int conflicts_with_override PARAMS ((rtx));
425 static void failed_reload PARAMS ((rtx, int));
426 static int set_reload_reg PARAMS ((int, int));
427 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
428 static void choose_reload_regs PARAMS ((struct insn_chain *));
429 static void merge_assigned_reloads PARAMS ((rtx));
430 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
431 struct reload *, rtx, int));
432 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
433 struct reload *, int));
434 static void do_input_reload PARAMS ((struct insn_chain *,
435 struct reload *, int));
436 static void do_output_reload PARAMS ((struct insn_chain *,
437 struct reload *, int));
438 static void emit_reload_insns PARAMS ((struct insn_chain *));
439 static void delete_output_reload PARAMS ((rtx, int, int));
440 static void delete_address_reloads PARAMS ((rtx, rtx));
441 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
442 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
443 static void reload_cse_regs_1 PARAMS ((rtx));
444 static int reload_cse_noop_set_p PARAMS ((rtx));
445 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
446 static int reload_cse_simplify_operands PARAMS ((rtx, rtx));
447 static void reload_combine PARAMS ((void));
448 static void reload_combine_note_use PARAMS ((rtx *, rtx));
449 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
450 static void reload_cse_move2add PARAMS ((rtx));
451 static void move2add_note_store PARAMS ((rtx, rtx, void *));
453 static void add_auto_inc_notes PARAMS ((rtx, rtx));
455 static void copy_eh_notes PARAMS ((rtx, rtx));
456 static void reload_cse_simplify PARAMS ((rtx, rtx));
457 extern void dump_needs PARAMS ((struct insn_chain *));
459 /* Initialize the reload pass once per compilation. */
466 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
467 Set spill_indirect_levels to the number of levels such addressing is
468 permitted, zero if it is not permitted at all. */
471 = gen_rtx_MEM (Pmode,
474 LAST_VIRTUAL_REGISTER + 1),
476 spill_indirect_levels = 0;
478 while (memory_address_p (QImode, tem))
480 spill_indirect_levels++;
481 tem = gen_rtx_MEM (Pmode, tem);
484 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
486 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
487 indirect_symref_ok = memory_address_p (QImode, tem);
489 /* See if reg+reg is a valid (and offsettable) address. */
491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
493 tem = gen_rtx_PLUS (Pmode,
494 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
495 gen_rtx_REG (Pmode, i));
497 /* This way, we make sure that reg+reg is an offsettable address. */
498 tem = plus_constant (tem, 4);
500 if (memory_address_p (QImode, tem))
502 double_reg_address_ok = 1;
507 /* Initialize obstack for our rtl allocation. */
508 gcc_obstack_init (&reload_obstack);
509 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
511 INIT_REG_SET (&spilled_pseudos);
512 INIT_REG_SET (&pseudos_counted);
515 /* List of insn chains that are currently unused. */
516 static struct insn_chain *unused_insn_chains = 0;
518 /* Allocate an empty insn_chain structure. */
522 struct insn_chain *c;
524 if (unused_insn_chains == 0)
526 c = (struct insn_chain *)
527 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
528 INIT_REG_SET (&c->live_throughout);
529 INIT_REG_SET (&c->dead_or_set);
533 c = unused_insn_chains;
534 unused_insn_chains = c->next;
536 c->is_caller_save_insn = 0;
537 c->need_operand_change = 0;
543 /* Small utility function to set all regs in hard reg set TO which are
544 allocated to pseudos in regset FROM. */
547 compute_use_by_pseudos (to, from)
553 EXECUTE_IF_SET_IN_REG_SET
554 (from, FIRST_PSEUDO_REGISTER, regno,
556 int r = reg_renumber[regno];
561 /* reload_combine uses the information from
562 BASIC_BLOCK->global_live_at_start, which might still
563 contain registers that have not actually been allocated
564 since they have an equivalence. */
565 if (! reload_completed)
570 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
572 SET_HARD_REG_BIT (*to, r + nregs);
577 /* Replace all pseudos found in LOC with their corresponding
581 replace_pseudos_in (loc, mem_mode, usage)
583 enum machine_mode mem_mode;
597 unsigned int regno = REGNO (x);
599 if (regno < FIRST_PSEUDO_REGISTER)
602 x = eliminate_regs (x, mem_mode, usage);
606 replace_pseudos_in (loc, mem_mode, usage);
610 if (reg_equiv_constant[regno])
611 *loc = reg_equiv_constant[regno];
612 else if (reg_equiv_mem[regno])
613 *loc = reg_equiv_mem[regno];
614 else if (reg_equiv_address[regno])
615 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
616 else if (GET_CODE (regno_reg_rtx[regno]) != REG
617 || REGNO (regno_reg_rtx[regno]) != regno)
618 *loc = regno_reg_rtx[regno];
624 else if (code == MEM)
626 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
630 /* Process each of our operands recursively. */
631 fmt = GET_RTX_FORMAT (code);
632 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
634 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
635 else if (*fmt == 'E')
636 for (j = 0; j < XVECLEN (x, i); j++)
637 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
641 /* Global variables used by reload and its subroutines. */
643 /* Set during calculate_needs if an insn needs register elimination. */
644 static int something_needs_elimination;
645 /* Set during calculate_needs if an insn needs an operand changed. */
646 int something_needs_operands_changed;
648 /* Nonzero means we couldn't get enough spill regs. */
651 /* Main entry point for the reload pass.
653 FIRST is the first insn of the function being compiled.
655 GLOBAL nonzero means we were called from global_alloc
656 and should attempt to reallocate any pseudoregs that we
657 displace from hard regs we will use for reloads.
658 If GLOBAL is zero, we do not have enough information to do that,
659 so any pseudo reg that is spilled must go to the stack.
661 Return value is nonzero if reload failed
662 and we must not do any more for this function. */
665 reload (first, global)
671 struct elim_table *ep;
674 /* Make sure even insns with volatile mem refs are recognizable. */
679 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
681 /* Make sure that the last insn in the chain
682 is not something that needs reloading. */
683 emit_note (NULL, NOTE_INSN_DELETED);
685 /* Enable find_equiv_reg to distinguish insns made by reload. */
686 reload_first_uid = get_max_uid ();
688 #ifdef SECONDARY_MEMORY_NEEDED
689 /* Initialize the secondary memory table. */
690 clear_secondary_mem ();
693 /* We don't have a stack slot for any spill reg yet. */
694 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
695 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
697 /* Initialize the save area information for caller-save, in case some
701 /* Compute which hard registers are now in use
702 as homes for pseudo registers.
703 This is done here rather than (eg) in global_alloc
704 because this point is reached even if not optimizing. */
705 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
708 /* A function that receives a nonlocal goto must save all call-saved
710 if (current_function_has_nonlocal_label)
711 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
712 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
713 regs_ever_live[i] = 1;
715 /* Find all the pseudo registers that didn't get hard regs
716 but do have known equivalent constants or memory slots.
717 These include parameters (known equivalent to parameter slots)
718 and cse'd or loop-moved constant memory addresses.
720 Record constant equivalents in reg_equiv_constant
721 so they will be substituted by find_reloads.
722 Record memory equivalents in reg_mem_equiv so they can
723 be substituted eventually by altering the REG-rtx's. */
725 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
726 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
727 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
728 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
729 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
730 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
731 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
732 pseudo_forbidden_regs
733 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
735 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
737 CLEAR_HARD_REG_SET (bad_spill_regs_global);
739 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
740 Also find all paradoxical subregs and find largest such for each pseudo.
741 On machines with small register classes, record hard registers that
742 are used for user variables. These can never be used for spills.
743 Also look for a "constant" REG_SETJMP. This means that all
744 caller-saved registers must be marked live. */
746 num_eliminable_invariants = 0;
747 for (insn = first; insn; insn = NEXT_INSN (insn))
749 rtx set = single_set (insn);
751 /* We may introduce USEs that we want to remove at the end, so
752 we'll mark them with QImode. Make sure there are no
753 previously-marked insns left by say regmove. */
754 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
755 && GET_MODE (insn) != VOIDmode)
756 PUT_MODE (insn, VOIDmode);
758 if (GET_CODE (insn) == CALL_INSN
759 && find_reg_note (insn, REG_SETJMP, NULL))
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i])
762 regs_ever_live[i] = 1;
764 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
766 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
768 #ifdef LEGITIMATE_PIC_OPERAND_P
769 && (! function_invariant_p (XEXP (note, 0))
771 /* A function invariant is often CONSTANT_P but may
772 include a register. We promise to only pass
773 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
774 || (CONSTANT_P (XEXP (note, 0))
775 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
779 rtx x = XEXP (note, 0);
780 i = REGNO (SET_DEST (set));
781 if (i > LAST_VIRTUAL_REGISTER)
783 /* It can happen that a REG_EQUIV note contains a MEM
784 that is not a legitimate memory operand. As later
785 stages of reload assume that all addresses found
786 in the reg_equiv_* arrays were originally legitimate,
787 we ignore such REG_EQUIV notes. */
788 if (memory_operand (x, VOIDmode))
790 /* Always unshare the equivalence, so we can
791 substitute into this insn without touching the
793 reg_equiv_memory_loc[i] = copy_rtx (x);
795 else if (function_invariant_p (x))
797 if (GET_CODE (x) == PLUS)
799 /* This is PLUS of frame pointer and a constant,
800 and might be shared. Unshare it. */
801 reg_equiv_constant[i] = copy_rtx (x);
802 num_eliminable_invariants++;
804 else if (x == frame_pointer_rtx
805 || x == arg_pointer_rtx)
807 reg_equiv_constant[i] = x;
808 num_eliminable_invariants++;
810 else if (LEGITIMATE_CONSTANT_P (x))
811 reg_equiv_constant[i] = x;
814 reg_equiv_memory_loc[i]
815 = force_const_mem (GET_MODE (SET_DEST (set)), x);
816 if (!reg_equiv_memory_loc[i])
823 /* If this register is being made equivalent to a MEM
824 and the MEM is not SET_SRC, the equivalencing insn
825 is one with the MEM as a SET_DEST and it occurs later.
826 So don't mark this insn now. */
827 if (GET_CODE (x) != MEM
828 || rtx_equal_p (SET_SRC (set), x))
830 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
835 /* If this insn is setting a MEM from a register equivalent to it,
836 this is the equivalencing insn. */
837 else if (set && GET_CODE (SET_DEST (set)) == MEM
838 && GET_CODE (SET_SRC (set)) == REG
839 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
840 && rtx_equal_p (SET_DEST (set),
841 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
842 reg_equiv_init[REGNO (SET_SRC (set))]
843 = gen_rtx_INSN_LIST (VOIDmode, insn,
844 reg_equiv_init[REGNO (SET_SRC (set))]);
847 scan_paradoxical_subregs (PATTERN (insn));
852 first_label_num = get_first_label_num ();
853 num_labels = max_label_num () - first_label_num;
855 /* Allocate the tables used to store offset information at labels. */
856 /* We used to use alloca here, but the size of what it would try to
857 allocate would occasionally cause it to exceed the stack limit and
858 cause a core dump. */
859 offsets_known_at = xmalloc (num_labels);
861 = (int (*)[NUM_ELIMINABLE_REGS])
862 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
864 /* Alter each pseudo-reg rtx to contain its hard reg number.
865 Assign stack slots to the pseudos that lack hard regs or equivalents.
866 Do not touch virtual registers. */
868 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
871 /* If we have some registers we think can be eliminated, scan all insns to
872 see if there is an insn that sets one of these registers to something
873 other than itself plus a constant. If so, the register cannot be
874 eliminated. Doing this scan here eliminates an extra pass through the
875 main reload loop in the most common case where register elimination
877 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
878 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
879 || GET_CODE (insn) == CALL_INSN)
880 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
882 maybe_fix_stack_asms ();
884 insns_need_reload = 0;
885 something_needs_elimination = 0;
887 /* Initialize to -1, which means take the first spill register. */
890 /* Spill any hard regs that we know we can't eliminate. */
891 CLEAR_HARD_REG_SET (used_spill_regs);
892 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
893 if (! ep->can_eliminate)
894 spill_hard_reg (ep->from, 1);
896 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
897 if (frame_pointer_needed)
898 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
900 finish_spills (global);
902 /* From now on, we may need to generate moves differently. We may also
903 allow modifications of insns which cause them to not be recognized.
904 Any such modifications will be cleaned up during reload itself. */
905 reload_in_progress = 1;
907 /* This loop scans the entire function each go-round
908 and repeats until one repetition spills no additional hard regs. */
911 int something_changed;
914 HOST_WIDE_INT starting_frame_size;
916 /* Round size of stack frame to stack_alignment_needed. This must be done
917 here because the stack size may be a part of the offset computation
918 for register elimination, and there might have been new stack slots
919 created in the last iteration of this loop. */
920 if (cfun->stack_alignment_needed)
921 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
923 starting_frame_size = get_frame_size ();
925 set_initial_elim_offsets ();
926 set_initial_label_offsets ();
928 /* For each pseudo register that has an equivalent location defined,
929 try to eliminate any eliminable registers (such as the frame pointer)
930 assuming initial offsets for the replacement register, which
933 If the resulting location is directly addressable, substitute
934 the MEM we just got directly for the old REG.
936 If it is not addressable but is a constant or the sum of a hard reg
937 and constant, it is probably not addressable because the constant is
938 out of range, in that case record the address; we will generate
939 hairy code to compute the address in a register each time it is
940 needed. Similarly if it is a hard register, but one that is not
941 valid as an address register.
943 If the location is not addressable, but does not have one of the
944 above forms, assign a stack slot. We have to do this to avoid the
945 potential of producing lots of reloads if, e.g., a location involves
946 a pseudo that didn't get a hard register and has an equivalent memory
947 location that also involves a pseudo that didn't get a hard register.
949 Perhaps at some point we will improve reload_when_needed handling
950 so this problem goes away. But that's very hairy. */
952 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
953 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
955 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
957 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
959 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
960 else if (CONSTANT_P (XEXP (x, 0))
961 || (GET_CODE (XEXP (x, 0)) == REG
962 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
963 || (GET_CODE (XEXP (x, 0)) == PLUS
964 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
965 && (REGNO (XEXP (XEXP (x, 0), 0))
966 < FIRST_PSEUDO_REGISTER)
967 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
968 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
971 /* Make a new stack slot. Then indicate that something
972 changed so we go back and recompute offsets for
973 eliminable registers because the allocation of memory
974 below might change some offset. reg_equiv_{mem,address}
975 will be set up for this pseudo on the next pass around
977 reg_equiv_memory_loc[i] = 0;
978 reg_equiv_init[i] = 0;
983 if (caller_save_needed)
986 /* If we allocated another stack slot, redo elimination bookkeeping. */
987 if (starting_frame_size != get_frame_size ())
990 if (caller_save_needed)
992 save_call_clobbered_regs ();
993 /* That might have allocated new insn_chain structures. */
994 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
997 calculate_needs_all_insns (global);
999 CLEAR_REG_SET (&spilled_pseudos);
1002 something_changed = 0;
1004 /* If we allocated any new memory locations, make another pass
1005 since it might have changed elimination offsets. */
1006 if (starting_frame_size != get_frame_size ())
1007 something_changed = 1;
1010 HARD_REG_SET to_spill;
1011 CLEAR_HARD_REG_SET (to_spill);
1012 update_eliminables (&to_spill);
1013 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1014 if (TEST_HARD_REG_BIT (to_spill, i))
1016 spill_hard_reg (i, 1);
1019 /* Regardless of the state of spills, if we previously had
1020 a register that we thought we could eliminate, but now can
1021 not eliminate, we must run another pass.
1023 Consider pseudos which have an entry in reg_equiv_* which
1024 reference an eliminable register. We must make another pass
1025 to update reg_equiv_* so that we do not substitute in the
1026 old value from when we thought the elimination could be
1028 something_changed = 1;
1032 select_reload_regs ();
1036 if (insns_need_reload != 0 || did_spill)
1037 something_changed |= finish_spills (global);
1039 if (! something_changed)
1042 if (caller_save_needed)
1043 delete_caller_save_insns ();
1045 obstack_free (&reload_obstack, reload_firstobj);
1048 /* If global-alloc was run, notify it of any register eliminations we have
1051 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1052 if (ep->can_eliminate)
1053 mark_elimination (ep->from, ep->to);
1055 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1056 If that insn didn't set the register (i.e., it copied the register to
1057 memory), just delete that insn instead of the equivalencing insn plus
1058 anything now dead. If we call delete_dead_insn on that insn, we may
1059 delete the insn that actually sets the register if the register dies
1060 there and that is incorrect. */
1062 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1064 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1067 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1069 rtx equiv_insn = XEXP (list, 0);
1071 /* If we already deleted the insn or if it may trap, we can't
1072 delete it. The latter case shouldn't happen, but can
1073 if an insn has a variable address, gets a REG_EH_REGION
1074 note added to it, and then gets converted into an load
1075 from a constant address. */
1076 if (GET_CODE (equiv_insn) == NOTE
1077 || can_throw_internal (equiv_insn))
1079 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1080 delete_dead_insn (equiv_insn);
1083 PUT_CODE (equiv_insn, NOTE);
1084 NOTE_SOURCE_FILE (equiv_insn) = 0;
1085 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1091 /* Use the reload registers where necessary
1092 by generating move instructions to move the must-be-register
1093 values into or out of the reload registers. */
1095 if (insns_need_reload != 0 || something_needs_elimination
1096 || something_needs_operands_changed)
1098 HOST_WIDE_INT old_frame_size = get_frame_size ();
1100 reload_as_needed (global);
1102 if (old_frame_size != get_frame_size ())
1106 verify_initial_elim_offsets ();
1109 /* If we were able to eliminate the frame pointer, show that it is no
1110 longer live at the start of any basic block. If it ls live by
1111 virtue of being in a pseudo, that pseudo will be marked live
1112 and hence the frame pointer will be known to be live via that
1115 if (! frame_pointer_needed)
1117 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1118 HARD_FRAME_POINTER_REGNUM);
1120 /* Come here (with failure set nonzero) if we can't get enough spill regs
1121 and we decide not to abort about it. */
1124 CLEAR_REG_SET (&spilled_pseudos);
1125 reload_in_progress = 0;
1127 /* Now eliminate all pseudo regs by modifying them into
1128 their equivalent memory references.
1129 The REG-rtx's for the pseudos are modified in place,
1130 so all insns that used to refer to them now refer to memory.
1132 For a reg that has a reg_equiv_address, all those insns
1133 were changed by reloading so that no insns refer to it any longer;
1134 but the DECL_RTL of a variable decl may refer to it,
1135 and if so this causes the debugging info to mention the variable. */
1137 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1141 if (reg_equiv_mem[i])
1142 addr = XEXP (reg_equiv_mem[i], 0);
1144 if (reg_equiv_address[i])
1145 addr = reg_equiv_address[i];
1149 if (reg_renumber[i] < 0)
1151 rtx reg = regno_reg_rtx[i];
1153 REG_USERVAR_P (reg) = 0;
1154 PUT_CODE (reg, MEM);
1155 XEXP (reg, 0) = addr;
1156 if (reg_equiv_memory_loc[i])
1157 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1160 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1161 = MEM_SCALAR_P (reg) = 0;
1162 MEM_ATTRS (reg) = 0;
1165 else if (reg_equiv_mem[i])
1166 XEXP (reg_equiv_mem[i], 0) = addr;
1170 /* We must set reload_completed now since the cleanup_subreg_operands call
1171 below will re-recognize each insn and reload may have generated insns
1172 which are only valid during and after reload. */
1173 reload_completed = 1;
1175 /* Make a pass over all the insns and delete all USEs which we inserted
1176 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1177 notes. Delete all CLOBBER insns, except those that refer to the return
1178 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1179 from misarranging variable-array code, and simplify (subreg (reg))
1180 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1181 are no longer useful or accurate. Strip and regenerate REG_INC notes
1182 that may have been moved around. */
1184 for (insn = first; insn; insn = NEXT_INSN (insn))
1189 if (GET_CODE (insn) == CALL_INSN)
1190 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1191 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1193 if ((GET_CODE (PATTERN (insn)) == USE
1194 /* We mark with QImode USEs introduced by reload itself. */
1195 && (GET_MODE (insn) == QImode
1196 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1197 || (GET_CODE (PATTERN (insn)) == CLOBBER
1198 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1199 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1200 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1201 && XEXP (XEXP (PATTERN (insn), 0), 0)
1202 != stack_pointer_rtx))
1203 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1204 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1210 /* Some CLOBBERs may survive until here and still reference unassigned
1211 pseudos with const equivalent, which may in turn cause ICE in later
1212 passes if the reference remains in place. */
1213 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1214 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1215 VOIDmode, PATTERN (insn));
1217 pnote = ®_NOTES (insn);
1220 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1221 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1222 || REG_NOTE_KIND (*pnote) == REG_INC
1223 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1224 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1225 *pnote = XEXP (*pnote, 1);
1227 pnote = &XEXP (*pnote, 1);
1231 add_auto_inc_notes (insn, PATTERN (insn));
1234 /* And simplify (subreg (reg)) if it appears as an operand. */
1235 cleanup_subreg_operands (insn);
1238 /* If we are doing stack checking, give a warning if this function's
1239 frame size is larger than we expect. */
1240 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1242 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1243 static int verbose_warned = 0;
1245 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1246 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1247 size += UNITS_PER_WORD;
1249 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1251 warning ("frame size too large for reliable stack checking");
1252 if (! verbose_warned)
1254 warning ("try reducing the number of local variables");
1260 /* Indicate that we no longer have known memory locations or constants. */
1261 if (reg_equiv_constant)
1262 free (reg_equiv_constant);
1263 reg_equiv_constant = 0;
1264 if (reg_equiv_memory_loc)
1265 free (reg_equiv_memory_loc);
1266 reg_equiv_memory_loc = 0;
1268 if (offsets_known_at)
1269 free (offsets_known_at);
1273 free (reg_equiv_mem);
1274 free (reg_equiv_init);
1275 free (reg_equiv_address);
1276 free (reg_max_ref_width);
1277 free (reg_old_renumber);
1278 free (pseudo_previous_regs);
1279 free (pseudo_forbidden_regs);
1281 CLEAR_HARD_REG_SET (used_spill_regs);
1282 for (i = 0; i < n_spills; i++)
1283 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1285 /* Free all the insn_chain structures at once. */
1286 obstack_free (&reload_obstack, reload_startobj);
1287 unused_insn_chains = 0;
1288 fixup_abnormal_edges ();
1290 /* Replacing pseudos with their memory equivalents might have
1291 created shared rtx. Subsequent passes would get confused
1292 by this, so unshare everything here. */
1293 unshare_all_rtl_again (first);
1298 /* Yet another special case. Unfortunately, reg-stack forces people to
1299 write incorrect clobbers in asm statements. These clobbers must not
1300 cause the register to appear in bad_spill_regs, otherwise we'll call
1301 fatal_insn later. We clear the corresponding regnos in the live
1302 register sets to avoid this.
1303 The whole thing is rather sick, I'm afraid. */
1306 maybe_fix_stack_asms ()
1309 const char *constraints[MAX_RECOG_OPERANDS];
1310 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1311 struct insn_chain *chain;
1313 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1316 HARD_REG_SET clobbered, allowed;
1319 if (! INSN_P (chain->insn)
1320 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1322 pat = PATTERN (chain->insn);
1323 if (GET_CODE (pat) != PARALLEL)
1326 CLEAR_HARD_REG_SET (clobbered);
1327 CLEAR_HARD_REG_SET (allowed);
1329 /* First, make a mask of all stack regs that are clobbered. */
1330 for (i = 0; i < XVECLEN (pat, 0); i++)
1332 rtx t = XVECEXP (pat, 0, i);
1333 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1334 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1337 /* Get the operand values and constraints out of the insn. */
1338 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1339 constraints, operand_mode);
1341 /* For every operand, see what registers are allowed. */
1342 for (i = 0; i < noperands; i++)
1344 const char *p = constraints[i];
1345 /* For every alternative, we compute the class of registers allowed
1346 for reloading in CLS, and merge its contents into the reg set
1348 int cls = (int) NO_REGS;
1354 if (c == '\0' || c == ',' || c == '#')
1356 /* End of one alternative - mark the regs in the current
1357 class, and reset the class. */
1358 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1364 } while (c != '\0' && c != ',');
1372 case '=': case '+': case '*': case '%': case '?': case '!':
1373 case '0': case '1': case '2': case '3': case '4': case 'm':
1374 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1375 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1376 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1381 cls = (int) reg_class_subunion[cls]
1382 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1387 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1391 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1392 cls = (int) reg_class_subunion[cls]
1393 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1395 cls = (int) reg_class_subunion[cls]
1396 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1398 p += CONSTRAINT_LEN (c, p);
1401 /* Those of the registers which are clobbered, but allowed by the
1402 constraints, must be usable as reload registers. So clear them
1403 out of the life information. */
1404 AND_HARD_REG_SET (allowed, clobbered);
1405 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1406 if (TEST_HARD_REG_BIT (allowed, i))
1408 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1409 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1416 /* Copy the global variables n_reloads and rld into the corresponding elts
1419 copy_reloads (chain)
1420 struct insn_chain *chain;
1422 chain->n_reloads = n_reloads;
1424 = (struct reload *) obstack_alloc (&reload_obstack,
1425 n_reloads * sizeof (struct reload));
1426 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1427 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1430 /* Walk the chain of insns, and determine for each whether it needs reloads
1431 and/or eliminations. Build the corresponding insns_need_reload list, and
1432 set something_needs_elimination as appropriate. */
1434 calculate_needs_all_insns (global)
1437 struct insn_chain **pprev_reload = &insns_need_reload;
1438 struct insn_chain *chain, *next = 0;
1440 something_needs_elimination = 0;
1442 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1443 for (chain = reload_insn_chain; chain != 0; chain = next)
1445 rtx insn = chain->insn;
1449 /* Clear out the shortcuts. */
1450 chain->n_reloads = 0;
1451 chain->need_elim = 0;
1452 chain->need_reload = 0;
1453 chain->need_operand_change = 0;
1455 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1456 include REG_LABEL), we need to see what effects this has on the
1457 known offsets at labels. */
1459 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1460 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1461 set_label_offsets (insn, insn, 0);
1465 rtx old_body = PATTERN (insn);
1466 int old_code = INSN_CODE (insn);
1467 rtx old_notes = REG_NOTES (insn);
1468 int did_elimination = 0;
1469 int operands_changed = 0;
1470 rtx set = single_set (insn);
1472 /* Skip insns that only set an equivalence. */
1473 if (set && GET_CODE (SET_DEST (set)) == REG
1474 && reg_renumber[REGNO (SET_DEST (set))] < 0
1475 && reg_equiv_constant[REGNO (SET_DEST (set))])
1478 /* If needed, eliminate any eliminable registers. */
1479 if (num_eliminable || num_eliminable_invariants)
1480 did_elimination = eliminate_regs_in_insn (insn, 0);
1482 /* Analyze the instruction. */
1483 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1484 global, spill_reg_order);
1486 /* If a no-op set needs more than one reload, this is likely
1487 to be something that needs input address reloads. We
1488 can't get rid of this cleanly later, and it is of no use
1489 anyway, so discard it now.
1490 We only do this when expensive_optimizations is enabled,
1491 since this complements reload inheritance / output
1492 reload deletion, and it can make debugging harder. */
1493 if (flag_expensive_optimizations && n_reloads > 1)
1495 rtx set = single_set (insn);
1497 && SET_SRC (set) == SET_DEST (set)
1498 && GET_CODE (SET_SRC (set)) == REG
1499 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1502 /* Delete it from the reload chain. */
1504 chain->prev->next = next;
1506 reload_insn_chain = next;
1508 next->prev = chain->prev;
1509 chain->next = unused_insn_chains;
1510 unused_insn_chains = chain;
1515 update_eliminable_offsets ();
1517 /* Remember for later shortcuts which insns had any reloads or
1518 register eliminations. */
1519 chain->need_elim = did_elimination;
1520 chain->need_reload = n_reloads > 0;
1521 chain->need_operand_change = operands_changed;
1523 /* Discard any register replacements done. */
1524 if (did_elimination)
1526 obstack_free (&reload_obstack, reload_insn_firstobj);
1527 PATTERN (insn) = old_body;
1528 INSN_CODE (insn) = old_code;
1529 REG_NOTES (insn) = old_notes;
1530 something_needs_elimination = 1;
1533 something_needs_operands_changed |= operands_changed;
1537 copy_reloads (chain);
1538 *pprev_reload = chain;
1539 pprev_reload = &chain->next_need_reload;
1546 /* Comparison function for qsort to decide which of two reloads
1547 should be handled first. *P1 and *P2 are the reload numbers. */
1550 reload_reg_class_lower (r1p, r2p)
1554 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1557 /* Consider required reloads before optional ones. */
1558 t = rld[r1].optional - rld[r2].optional;
1562 /* Count all solitary classes before non-solitary ones. */
1563 t = ((reg_class_size[(int) rld[r2].class] == 1)
1564 - (reg_class_size[(int) rld[r1].class] == 1));
1568 /* Aside from solitaires, consider all multi-reg groups first. */
1569 t = rld[r2].nregs - rld[r1].nregs;
1573 /* Consider reloads in order of increasing reg-class number. */
1574 t = (int) rld[r1].class - (int) rld[r2].class;
1578 /* If reloads are equally urgent, sort by reload number,
1579 so that the results of qsort leave nothing to chance. */
1583 /* The cost of spilling each hard reg. */
1584 static int spill_cost[FIRST_PSEUDO_REGISTER];
1586 /* When spilling multiple hard registers, we use SPILL_COST for the first
1587 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1588 only the first hard reg for a multi-reg pseudo. */
1589 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1591 /* Update the spill cost arrays, considering that pseudo REG is live. */
1597 int freq = REG_FREQ (reg);
1598 int r = reg_renumber[reg];
1601 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1602 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1605 SET_REGNO_REG_SET (&pseudos_counted, reg);
1610 spill_add_cost[r] += freq;
1612 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1614 spill_cost[r + nregs] += freq;
1617 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1618 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1621 order_regs_for_reload (chain)
1622 struct insn_chain *chain;
1625 HARD_REG_SET used_by_pseudos;
1626 HARD_REG_SET used_by_pseudos2;
1628 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1630 memset (spill_cost, 0, sizeof spill_cost);
1631 memset (spill_add_cost, 0, sizeof spill_add_cost);
1633 /* Count number of uses of each hard reg by pseudo regs allocated to it
1634 and then order them by decreasing use. First exclude hard registers
1635 that are live in or across this insn. */
1637 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1638 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1639 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1640 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1642 /* Now find out which pseudos are allocated to it, and update
1644 CLEAR_REG_SET (&pseudos_counted);
1646 EXECUTE_IF_SET_IN_REG_SET
1647 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1651 EXECUTE_IF_SET_IN_REG_SET
1652 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1656 CLEAR_REG_SET (&pseudos_counted);
1659 /* Vector of reload-numbers showing the order in which the reloads should
1661 static short reload_order[MAX_RELOADS];
1663 /* This is used to keep track of the spill regs used in one insn. */
1664 static HARD_REG_SET used_spill_regs_local;
1666 /* We decided to spill hard register SPILLED, which has a size of
1667 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1668 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1669 update SPILL_COST/SPILL_ADD_COST. */
1672 count_spilled_pseudo (spilled, spilled_nregs, reg)
1673 int spilled, spilled_nregs, reg;
1675 int r = reg_renumber[reg];
1676 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1678 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1679 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1682 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1684 spill_add_cost[r] -= REG_FREQ (reg);
1686 spill_cost[r + nregs] -= REG_FREQ (reg);
1689 /* Find reload register to use for reload number ORDER. */
1692 find_reg (chain, order)
1693 struct insn_chain *chain;
1696 int rnum = reload_order[order];
1697 struct reload *rl = rld + rnum;
1698 int best_cost = INT_MAX;
1702 HARD_REG_SET not_usable;
1703 HARD_REG_SET used_by_other_reload;
1705 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1706 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1707 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1709 CLEAR_HARD_REG_SET (used_by_other_reload);
1710 for (k = 0; k < order; k++)
1712 int other = reload_order[k];
1714 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1715 for (j = 0; j < rld[other].nregs; j++)
1716 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1719 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1721 unsigned int regno = i;
1723 if (! TEST_HARD_REG_BIT (not_usable, regno)
1724 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1725 && HARD_REGNO_MODE_OK (regno, rl->mode))
1727 int this_cost = spill_cost[regno];
1729 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1731 for (j = 1; j < this_nregs; j++)
1733 this_cost += spill_add_cost[regno + j];
1734 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1735 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1740 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1742 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1744 if (this_cost < best_cost
1745 /* Among registers with equal cost, prefer caller-saved ones, or
1746 use REG_ALLOC_ORDER if it is defined. */
1747 || (this_cost == best_cost
1748 #ifdef REG_ALLOC_ORDER
1749 && (inv_reg_alloc_order[regno]
1750 < inv_reg_alloc_order[best_reg])
1752 && call_used_regs[regno]
1753 && ! call_used_regs[best_reg]
1758 best_cost = this_cost;
1766 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1768 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1769 rl->regno = best_reg;
1771 EXECUTE_IF_SET_IN_REG_SET
1772 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1774 count_spilled_pseudo (best_reg, rl->nregs, j);
1777 EXECUTE_IF_SET_IN_REG_SET
1778 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1780 count_spilled_pseudo (best_reg, rl->nregs, j);
1783 for (i = 0; i < rl->nregs; i++)
1785 if (spill_cost[best_reg + i] != 0
1786 || spill_add_cost[best_reg + i] != 0)
1788 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1793 /* Find more reload regs to satisfy the remaining need of an insn, which
1795 Do it by ascending class number, since otherwise a reg
1796 might be spilled for a big class and might fail to count
1797 for a smaller class even though it belongs to that class. */
1800 find_reload_regs (chain)
1801 struct insn_chain *chain;
1805 /* In order to be certain of getting the registers we need,
1806 we must sort the reloads into order of increasing register class.
1807 Then our grabbing of reload registers will parallel the process
1808 that provided the reload registers. */
1809 for (i = 0; i < chain->n_reloads; i++)
1811 /* Show whether this reload already has a hard reg. */
1812 if (chain->rld[i].reg_rtx)
1814 int regno = REGNO (chain->rld[i].reg_rtx);
1815 chain->rld[i].regno = regno;
1817 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1820 chain->rld[i].regno = -1;
1821 reload_order[i] = i;
1824 n_reloads = chain->n_reloads;
1825 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1827 CLEAR_HARD_REG_SET (used_spill_regs_local);
1830 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1832 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1834 /* Compute the order of preference for hard registers to spill. */
1836 order_regs_for_reload (chain);
1838 for (i = 0; i < n_reloads; i++)
1840 int r = reload_order[i];
1842 /* Ignore reloads that got marked inoperative. */
1843 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1844 && ! rld[r].optional
1845 && rld[r].regno == -1)
1846 if (! find_reg (chain, i))
1848 spill_failure (chain->insn, rld[r].class);
1854 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1855 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1857 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1861 select_reload_regs ()
1863 struct insn_chain *chain;
1865 /* Try to satisfy the needs for each insn. */
1866 for (chain = insns_need_reload; chain != 0;
1867 chain = chain->next_need_reload)
1868 find_reload_regs (chain);
1871 /* Delete all insns that were inserted by emit_caller_save_insns during
1874 delete_caller_save_insns ()
1876 struct insn_chain *c = reload_insn_chain;
1880 while (c != 0 && c->is_caller_save_insn)
1882 struct insn_chain *next = c->next;
1885 if (c == reload_insn_chain)
1886 reload_insn_chain = next;
1890 next->prev = c->prev;
1892 c->prev->next = next;
1893 c->next = unused_insn_chains;
1894 unused_insn_chains = c;
1902 /* Handle the failure to find a register to spill.
1903 INSN should be one of the insns which needed this particular spill reg. */
1906 spill_failure (insn, class)
1908 enum reg_class class;
1910 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1911 if (asm_noperands (PATTERN (insn)) >= 0)
1912 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1913 reg_class_names[class]);
1916 error ("unable to find a register to spill in class `%s'",
1917 reg_class_names[class]);
1918 fatal_insn ("this is the insn:", insn);
1922 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1923 data that is dead in INSN. */
1926 delete_dead_insn (insn)
1929 rtx prev = prev_real_insn (insn);
1932 /* If the previous insn sets a register that dies in our insn, delete it
1934 if (prev && GET_CODE (PATTERN (prev)) == SET
1935 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1936 && reg_mentioned_p (prev_dest, PATTERN (insn))
1937 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1938 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1939 delete_dead_insn (prev);
1941 PUT_CODE (insn, NOTE);
1942 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1943 NOTE_SOURCE_FILE (insn) = 0;
1946 /* Modify the home of pseudo-reg I.
1947 The new home is present in reg_renumber[I].
1949 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1950 or it may be -1, meaning there is none or it is not relevant.
1951 This is used so that all pseudos spilled from a given hard reg
1952 can share one stack slot. */
1955 alter_reg (i, from_reg)
1959 /* When outputting an inline function, this can happen
1960 for a reg that isn't actually used. */
1961 if (regno_reg_rtx[i] == 0)
1964 /* If the reg got changed to a MEM at rtl-generation time,
1966 if (GET_CODE (regno_reg_rtx[i]) != REG)
1969 /* Modify the reg-rtx to contain the new hard reg
1970 number or else to contain its pseudo reg number. */
1971 REGNO (regno_reg_rtx[i])
1972 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1974 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1975 allocate a stack slot for it. */
1977 if (reg_renumber[i] < 0
1978 && REG_N_REFS (i) > 0
1979 && reg_equiv_constant[i] == 0
1980 && reg_equiv_memory_loc[i] == 0)
1983 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1984 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1987 /* Each pseudo reg has an inherent size which comes from its own mode,
1988 and a total size which provides room for paradoxical subregs
1989 which refer to the pseudo reg in wider modes.
1991 We can use a slot already allocated if it provides both
1992 enough inherent space and enough total space.
1993 Otherwise, we allocate a new slot, making sure that it has no less
1994 inherent space, and no less total space, then the previous slot. */
1997 /* No known place to spill from => no slot to reuse. */
1998 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1999 inherent_size == total_size ? 0 : -1);
2000 if (BYTES_BIG_ENDIAN)
2001 /* Cancel the big-endian correction done in assign_stack_local.
2002 Get the address of the beginning of the slot.
2003 This is so we can do a big-endian correction unconditionally
2005 adjust = inherent_size - total_size;
2007 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2009 /* Nothing can alias this slot except this pseudo. */
2010 set_mem_alias_set (x, new_alias_set ());
2013 /* Reuse a stack slot if possible. */
2014 else if (spill_stack_slot[from_reg] != 0
2015 && spill_stack_slot_width[from_reg] >= total_size
2016 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2018 x = spill_stack_slot[from_reg];
2020 /* Allocate a bigger slot. */
2023 /* Compute maximum size needed, both for inherent size
2024 and for total size. */
2025 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2028 if (spill_stack_slot[from_reg])
2030 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2032 mode = GET_MODE (spill_stack_slot[from_reg]);
2033 if (spill_stack_slot_width[from_reg] > total_size)
2034 total_size = spill_stack_slot_width[from_reg];
2037 /* Make a slot with that size. */
2038 x = assign_stack_local (mode, total_size,
2039 inherent_size == total_size ? 0 : -1);
2042 /* All pseudos mapped to this slot can alias each other. */
2043 if (spill_stack_slot[from_reg])
2044 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2046 set_mem_alias_set (x, new_alias_set ());
2048 if (BYTES_BIG_ENDIAN)
2050 /* Cancel the big-endian correction done in assign_stack_local.
2051 Get the address of the beginning of the slot.
2052 This is so we can do a big-endian correction unconditionally
2054 adjust = GET_MODE_SIZE (mode) - total_size;
2057 = adjust_address_nv (x, mode_for_size (total_size
2063 spill_stack_slot[from_reg] = stack_slot;
2064 spill_stack_slot_width[from_reg] = total_size;
2067 /* On a big endian machine, the "address" of the slot
2068 is the address of the low part that fits its inherent mode. */
2069 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2070 adjust += (total_size - inherent_size);
2072 /* If we have any adjustment to make, or if the stack slot is the
2073 wrong mode, make a new stack slot. */
2074 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2076 /* If we have a decl for the original register, set it for the
2077 memory. If this is a shared MEM, make a copy. */
2078 if (REG_EXPR (regno_reg_rtx[i])
2079 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2081 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2083 /* We can do this only for the DECLs home pseudo, not for
2084 any copies of it, since otherwise when the stack slot
2085 is reused, nonoverlapping_memrefs_p might think they
2087 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2089 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2092 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2096 /* Save the stack slot for later. */
2097 reg_equiv_memory_loc[i] = x;
2101 /* Mark the slots in regs_ever_live for the hard regs
2102 used by pseudo-reg number REGNO. */
2105 mark_home_live (regno)
2110 i = reg_renumber[regno];
2113 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2115 regs_ever_live[i++] = 1;
2118 /* This function handles the tracking of elimination offsets around branches.
2120 X is a piece of RTL being scanned.
2122 INSN is the insn that it came from, if any.
2124 INITIAL_P is nonzero if we are to set the offset to be the initial
2125 offset and zero if we are setting the offset of the label to be the
2129 set_label_offsets (x, insn, initial_p)
2134 enum rtx_code code = GET_CODE (x);
2137 struct elim_table *p;
2142 if (LABEL_REF_NONLOCAL_P (x))
2147 /* ... fall through ... */
2150 /* If we know nothing about this label, set the desired offsets. Note
2151 that this sets the offset at a label to be the offset before a label
2152 if we don't know anything about the label. This is not correct for
2153 the label after a BARRIER, but is the best guess we can make. If
2154 we guessed wrong, we will suppress an elimination that might have
2155 been possible had we been able to guess correctly. */
2157 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2159 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2160 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2161 = (initial_p ? reg_eliminate[i].initial_offset
2162 : reg_eliminate[i].offset);
2163 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2166 /* Otherwise, if this is the definition of a label and it is
2167 preceded by a BARRIER, set our offsets to the known offset of
2171 && (tem = prev_nonnote_insn (insn)) != 0
2172 && GET_CODE (tem) == BARRIER)
2173 set_offsets_for_label (insn);
2175 /* If neither of the above cases is true, compare each offset
2176 with those previously recorded and suppress any eliminations
2177 where the offsets disagree. */
2179 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2180 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2181 != (initial_p ? reg_eliminate[i].initial_offset
2182 : reg_eliminate[i].offset))
2183 reg_eliminate[i].can_eliminate = 0;
2188 set_label_offsets (PATTERN (insn), insn, initial_p);
2190 /* ... fall through ... */
2194 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2195 and hence must have all eliminations at their initial offsets. */
2196 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2197 if (REG_NOTE_KIND (tem) == REG_LABEL)
2198 set_label_offsets (XEXP (tem, 0), insn, 1);
2204 /* Each of the labels in the parallel or address vector must be
2205 at their initial offsets. We want the first field for PARALLEL
2206 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2208 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2209 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2214 /* We only care about setting PC. If the source is not RETURN,
2215 IF_THEN_ELSE, or a label, disable any eliminations not at
2216 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2217 isn't one of those possibilities. For branches to a label,
2218 call ourselves recursively.
2220 Note that this can disable elimination unnecessarily when we have
2221 a non-local goto since it will look like a non-constant jump to
2222 someplace in the current function. This isn't a significant
2223 problem since such jumps will normally be when all elimination
2224 pairs are back to their initial offsets. */
2226 if (SET_DEST (x) != pc_rtx)
2229 switch (GET_CODE (SET_SRC (x)))
2236 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2240 tem = XEXP (SET_SRC (x), 1);
2241 if (GET_CODE (tem) == LABEL_REF)
2242 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2243 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2246 tem = XEXP (SET_SRC (x), 2);
2247 if (GET_CODE (tem) == LABEL_REF)
2248 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2249 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2257 /* If we reach here, all eliminations must be at their initial
2258 offset because we are doing a jump to a variable address. */
2259 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2260 if (p->offset != p->initial_offset)
2261 p->can_eliminate = 0;
2269 /* Scan X and replace any eliminable registers (such as fp) with a
2270 replacement (such as sp), plus an offset.
2272 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2273 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2274 MEM, we are allowed to replace a sum of a register and the constant zero
2275 with the register, which we cannot do outside a MEM. In addition, we need
2276 to record the fact that a register is referenced outside a MEM.
2278 If INSN is an insn, it is the insn containing X. If we replace a REG
2279 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2280 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2281 the REG is being modified.
2283 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2284 That's used when we eliminate in expressions stored in notes.
2285 This means, do not set ref_outside_mem even if the reference
2288 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2289 replacements done assuming all offsets are at their initial values. If
2290 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2291 encounter, return the actual location so that find_reloads will do
2292 the proper thing. */
2295 eliminate_regs (x, mem_mode, insn)
2297 enum machine_mode mem_mode;
2300 enum rtx_code code = GET_CODE (x);
2301 struct elim_table *ep;
2308 if (! current_function_decl)
2328 /* This is only for the benefit of the debugging backends, which call
2329 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2330 removed after CSE. */
2331 new = eliminate_regs (XEXP (x, 0), 0, insn);
2332 if (GET_CODE (new) == MEM)
2333 return XEXP (new, 0);
2339 /* First handle the case where we encounter a bare register that
2340 is eliminable. Replace it with a PLUS. */
2341 if (regno < FIRST_PSEUDO_REGISTER)
2343 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2345 if (ep->from_rtx == x && ep->can_eliminate)
2346 return plus_constant (ep->to_rtx, ep->previous_offset);
2349 else if (reg_renumber && reg_renumber[regno] < 0
2350 && reg_equiv_constant && reg_equiv_constant[regno]
2351 && ! CONSTANT_P (reg_equiv_constant[regno]))
2352 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2356 /* You might think handling MINUS in a manner similar to PLUS is a
2357 good idea. It is not. It has been tried multiple times and every
2358 time the change has had to have been reverted.
2360 Other parts of reload know a PLUS is special (gen_reload for example)
2361 and require special code to handle code a reloaded PLUS operand.
2363 Also consider backends where the flags register is clobbered by a
2364 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2365 lea instruction comes to mind). If we try to reload a MINUS, we
2366 may kill the flags register that was holding a useful value.
2368 So, please before trying to handle MINUS, consider reload as a
2369 whole instead of this little section as well as the backend issues. */
2371 /* If this is the sum of an eliminable register and a constant, rework
2373 if (GET_CODE (XEXP (x, 0)) == REG
2374 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2375 && CONSTANT_P (XEXP (x, 1)))
2377 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2379 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2381 /* The only time we want to replace a PLUS with a REG (this
2382 occurs when the constant operand of the PLUS is the negative
2383 of the offset) is when we are inside a MEM. We won't want
2384 to do so at other times because that would change the
2385 structure of the insn in a way that reload can't handle.
2386 We special-case the commonest situation in
2387 eliminate_regs_in_insn, so just replace a PLUS with a
2388 PLUS here, unless inside a MEM. */
2389 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2390 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2393 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2394 plus_constant (XEXP (x, 1),
2395 ep->previous_offset));
2398 /* If the register is not eliminable, we are done since the other
2399 operand is a constant. */
2403 /* If this is part of an address, we want to bring any constant to the
2404 outermost PLUS. We will do this by doing register replacement in
2405 our operands and seeing if a constant shows up in one of them.
2407 Note that there is no risk of modifying the structure of the insn,
2408 since we only get called for its operands, thus we are either
2409 modifying the address inside a MEM, or something like an address
2410 operand of a load-address insn. */
2413 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2414 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2416 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2418 /* If one side is a PLUS and the other side is a pseudo that
2419 didn't get a hard register but has a reg_equiv_constant,
2420 we must replace the constant here since it may no longer
2421 be in the position of any operand. */
2422 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2423 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2424 && reg_renumber[REGNO (new1)] < 0
2425 && reg_equiv_constant != 0
2426 && reg_equiv_constant[REGNO (new1)] != 0)
2427 new1 = reg_equiv_constant[REGNO (new1)];
2428 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2429 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2430 && reg_renumber[REGNO (new0)] < 0
2431 && reg_equiv_constant[REGNO (new0)] != 0)
2432 new0 = reg_equiv_constant[REGNO (new0)];
2434 new = form_sum (new0, new1);
2436 /* As above, if we are not inside a MEM we do not want to
2437 turn a PLUS into something else. We might try to do so here
2438 for an addition of 0 if we aren't optimizing. */
2439 if (! mem_mode && GET_CODE (new) != PLUS)
2440 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2448 /* If this is the product of an eliminable register and a
2449 constant, apply the distribute law and move the constant out
2450 so that we have (plus (mult ..) ..). This is needed in order
2451 to keep load-address insns valid. This case is pathological.
2452 We ignore the possibility of overflow here. */
2453 if (GET_CODE (XEXP (x, 0)) == REG
2454 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2455 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2456 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2458 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2461 /* Refs inside notes don't count for this purpose. */
2462 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2463 || GET_CODE (insn) == INSN_LIST)))
2464 ep->ref_outside_mem = 1;
2467 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2468 ep->previous_offset * INTVAL (XEXP (x, 1)));
2471 /* ... fall through ... */
2475 /* See comments before PLUS about handling MINUS. */
2477 case DIV: case UDIV:
2478 case MOD: case UMOD:
2479 case AND: case IOR: case XOR:
2480 case ROTATERT: case ROTATE:
2481 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2483 case GE: case GT: case GEU: case GTU:
2484 case LE: case LT: case LEU: case LTU:
2486 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2488 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2490 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2491 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2496 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2499 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2500 if (new != XEXP (x, 0))
2502 /* If this is a REG_DEAD note, it is not valid anymore.
2503 Using the eliminated version could result in creating a
2504 REG_DEAD note for the stack or frame pointer. */
2505 if (GET_MODE (x) == REG_DEAD)
2507 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2510 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2514 /* ... fall through ... */
2517 /* Now do eliminations in the rest of the chain. If this was
2518 an EXPR_LIST, this might result in allocating more memory than is
2519 strictly needed, but it simplifies the code. */
2522 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2523 if (new != XEXP (x, 1))
2525 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2533 case STRICT_LOW_PART:
2535 case SIGN_EXTEND: case ZERO_EXTEND:
2536 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2537 case FLOAT: case FIX:
2538 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2546 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2547 if (new != XEXP (x, 0))
2548 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2552 /* Similar to above processing, but preserve SUBREG_BYTE.
2553 Convert (subreg (mem)) to (mem) if not paradoxical.
2554 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2555 pseudo didn't get a hard reg, we must replace this with the
2556 eliminated version of the memory location because push_reloads
2557 may do the replacement in certain circumstances. */
2558 if (GET_CODE (SUBREG_REG (x)) == REG
2559 && (GET_MODE_SIZE (GET_MODE (x))
2560 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2561 && reg_equiv_memory_loc != 0
2562 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2564 new = SUBREG_REG (x);
2567 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2569 if (new != SUBREG_REG (x))
2571 int x_size = GET_MODE_SIZE (GET_MODE (x));
2572 int new_size = GET_MODE_SIZE (GET_MODE (new));
2574 if (GET_CODE (new) == MEM
2575 && ((x_size < new_size
2576 #ifdef WORD_REGISTER_OPERATIONS
2577 /* On these machines, combine can create rtl of the form
2578 (set (subreg:m1 (reg:m2 R) 0) ...)
2579 where m1 < m2, and expects something interesting to
2580 happen to the entire word. Moreover, it will use the
2581 (reg:m2 R) later, expecting all bits to be preserved.
2582 So if the number of words is the same, preserve the
2583 subreg so that push_reloads can see it. */
2584 && ! ((x_size - 1) / UNITS_PER_WORD
2585 == (new_size -1 ) / UNITS_PER_WORD)
2588 || x_size == new_size)
2590 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2592 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2598 /* This is only for the benefit of the debugging backends, which call
2599 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2600 removed after CSE. */
2601 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2602 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2604 /* Our only special processing is to pass the mode of the MEM to our
2605 recursive call and copy the flags. While we are here, handle this
2606 case more efficiently. */
2608 replace_equiv_address_nv (x,
2609 eliminate_regs (XEXP (x, 0),
2610 GET_MODE (x), insn));
2613 /* Handle insn_list USE that a call to a pure function may generate. */
2614 new = eliminate_regs (XEXP (x, 0), 0, insn);
2615 if (new != XEXP (x, 0))
2616 return gen_rtx_USE (GET_MODE (x), new);
2628 /* Process each of our operands recursively. If any have changed, make a
2630 fmt = GET_RTX_FORMAT (code);
2631 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2635 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2636 if (new != XEXP (x, i) && ! copied)
2638 rtx new_x = rtx_alloc (code);
2640 (sizeof (*new_x) - sizeof (new_x->fld)
2641 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2647 else if (*fmt == 'E')
2650 for (j = 0; j < XVECLEN (x, i); j++)
2652 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2653 if (new != XVECEXP (x, i, j) && ! copied_vec)
2655 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2659 rtx new_x = rtx_alloc (code);
2661 (sizeof (*new_x) - sizeof (new_x->fld)
2662 + (sizeof (new_x->fld[0])
2663 * GET_RTX_LENGTH (code))));
2667 XVEC (x, i) = new_v;
2670 XVECEXP (x, i, j) = new;
2678 /* Scan rtx X for modifications of elimination target registers. Update
2679 the table of eliminables to reflect the changed state. MEM_MODE is
2680 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2683 elimination_effects (x, mem_mode)
2685 enum machine_mode mem_mode;
2688 enum rtx_code code = GET_CODE (x);
2689 struct elim_table *ep;
2716 /* First handle the case where we encounter a bare register that
2717 is eliminable. Replace it with a PLUS. */
2718 if (regno < FIRST_PSEUDO_REGISTER)
2720 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2722 if (ep->from_rtx == x && ep->can_eliminate)
2725 ep->ref_outside_mem = 1;
2730 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2731 && reg_equiv_constant[regno]
2732 && ! function_invariant_p (reg_equiv_constant[regno]))
2733 elimination_effects (reg_equiv_constant[regno], mem_mode);
2742 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2743 if (ep->to_rtx == XEXP (x, 0))
2745 int size = GET_MODE_SIZE (mem_mode);
2747 /* If more bytes than MEM_MODE are pushed, account for them. */
2748 #ifdef PUSH_ROUNDING
2749 if (ep->to_rtx == stack_pointer_rtx)
2750 size = PUSH_ROUNDING (size);
2752 if (code == PRE_DEC || code == POST_DEC)
2754 else if (code == PRE_INC || code == POST_INC)
2756 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2757 && GET_CODE (XEXP (x, 1)) == PLUS
2758 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2759 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2760 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2763 /* These two aren't unary operators. */
2764 if (code == POST_MODIFY || code == PRE_MODIFY)
2767 /* Fall through to generic unary operation case. */
2768 case STRICT_LOW_PART:
2770 case SIGN_EXTEND: case ZERO_EXTEND:
2771 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2772 case FLOAT: case FIX:
2773 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2781 elimination_effects (XEXP (x, 0), mem_mode);
2785 if (GET_CODE (SUBREG_REG (x)) == REG
2786 && (GET_MODE_SIZE (GET_MODE (x))
2787 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2788 && reg_equiv_memory_loc != 0
2789 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2792 elimination_effects (SUBREG_REG (x), mem_mode);
2796 /* If using a register that is the source of an eliminate we still
2797 think can be performed, note it cannot be performed since we don't
2798 know how this register is used. */
2799 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2800 if (ep->from_rtx == XEXP (x, 0))
2801 ep->can_eliminate = 0;
2803 elimination_effects (XEXP (x, 0), mem_mode);
2807 /* If clobbering a register that is the replacement register for an
2808 elimination we still think can be performed, note that it cannot
2809 be performed. Otherwise, we need not be concerned about it. */
2810 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2811 if (ep->to_rtx == XEXP (x, 0))
2812 ep->can_eliminate = 0;
2814 elimination_effects (XEXP (x, 0), mem_mode);
2818 /* Check for setting a register that we know about. */
2819 if (GET_CODE (SET_DEST (x)) == REG)
2821 /* See if this is setting the replacement register for an
2824 If DEST is the hard frame pointer, we do nothing because we
2825 assume that all assignments to the frame pointer are for
2826 non-local gotos and are being done at a time when they are valid
2827 and do not disturb anything else. Some machines want to
2828 eliminate a fake argument pointer (or even a fake frame pointer)
2829 with either the real frame or the stack pointer. Assignments to
2830 the hard frame pointer must not prevent this elimination. */
2832 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2834 if (ep->to_rtx == SET_DEST (x)
2835 && SET_DEST (x) != hard_frame_pointer_rtx)
2837 /* If it is being incremented, adjust the offset. Otherwise,
2838 this elimination can't be done. */
2839 rtx src = SET_SRC (x);
2841 if (GET_CODE (src) == PLUS
2842 && XEXP (src, 0) == SET_DEST (x)
2843 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2844 ep->offset -= INTVAL (XEXP (src, 1));
2846 ep->can_eliminate = 0;
2850 elimination_effects (SET_DEST (x), 0);
2851 elimination_effects (SET_SRC (x), 0);
2855 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2858 /* Our only special processing is to pass the mode of the MEM to our
2860 elimination_effects (XEXP (x, 0), GET_MODE (x));
2867 fmt = GET_RTX_FORMAT (code);
2868 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2871 elimination_effects (XEXP (x, i), mem_mode);
2872 else if (*fmt == 'E')
2873 for (j = 0; j < XVECLEN (x, i); j++)
2874 elimination_effects (XVECEXP (x, i, j), mem_mode);
2878 /* Descend through rtx X and verify that no references to eliminable registers
2879 remain. If any do remain, mark the involved register as not
2883 check_eliminable_occurrences (x)
2893 code = GET_CODE (x);
2895 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2897 struct elim_table *ep;
2899 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2900 if (ep->from_rtx == x && ep->can_eliminate)
2901 ep->can_eliminate = 0;
2905 fmt = GET_RTX_FORMAT (code);
2906 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2909 check_eliminable_occurrences (XEXP (x, i));
2910 else if (*fmt == 'E')
2913 for (j = 0; j < XVECLEN (x, i); j++)
2914 check_eliminable_occurrences (XVECEXP (x, i, j));
2919 /* Scan INSN and eliminate all eliminable registers in it.
2921 If REPLACE is nonzero, do the replacement destructively. Also
2922 delete the insn as dead it if it is setting an eliminable register.
2924 If REPLACE is zero, do all our allocations in reload_obstack.
2926 If no eliminations were done and this insn doesn't require any elimination
2927 processing (these are not identical conditions: it might be updating sp,
2928 but not referencing fp; this needs to be seen during reload_as_needed so
2929 that the offset between fp and sp can be taken into consideration), zero
2930 is returned. Otherwise, 1 is returned. */
2933 eliminate_regs_in_insn (insn, replace)
2937 int icode = recog_memoized (insn);
2938 rtx old_body = PATTERN (insn);
2939 int insn_is_asm = asm_noperands (old_body) >= 0;
2940 rtx old_set = single_set (insn);
2944 rtx substed_operand[MAX_RECOG_OPERANDS];
2945 rtx orig_operand[MAX_RECOG_OPERANDS];
2946 struct elim_table *ep;
2948 if (! insn_is_asm && icode < 0)
2950 if (GET_CODE (PATTERN (insn)) == USE
2951 || GET_CODE (PATTERN (insn)) == CLOBBER
2952 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2953 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2954 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2959 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2960 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2962 /* Check for setting an eliminable register. */
2963 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2964 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2966 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2967 /* If this is setting the frame pointer register to the
2968 hardware frame pointer register and this is an elimination
2969 that will be done (tested above), this insn is really
2970 adjusting the frame pointer downward to compensate for
2971 the adjustment done before a nonlocal goto. */
2972 if (ep->from == FRAME_POINTER_REGNUM
2973 && ep->to == HARD_FRAME_POINTER_REGNUM)
2975 rtx base = SET_SRC (old_set);
2976 rtx base_insn = insn;
2979 while (base != ep->to_rtx)
2981 rtx prev_insn, prev_set;
2983 if (GET_CODE (base) == PLUS
2984 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2986 offset += INTVAL (XEXP (base, 1));
2987 base = XEXP (base, 0);
2989 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2990 && (prev_set = single_set (prev_insn)) != 0
2991 && rtx_equal_p (SET_DEST (prev_set), base))
2993 base = SET_SRC (prev_set);
2994 base_insn = prev_insn;
3000 if (base == ep->to_rtx)
3003 = plus_constant (ep->to_rtx, offset - ep->offset);
3005 new_body = old_body;
3008 new_body = copy_insn (old_body);
3009 if (REG_NOTES (insn))
3010 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3012 PATTERN (insn) = new_body;
3013 old_set = single_set (insn);
3015 /* First see if this insn remains valid when we
3016 make the change. If not, keep the INSN_CODE
3017 the same and let reload fit it up. */
3018 validate_change (insn, &SET_SRC (old_set), src, 1);
3019 validate_change (insn, &SET_DEST (old_set),
3021 if (! apply_change_group ())
3023 SET_SRC (old_set) = src;
3024 SET_DEST (old_set) = ep->to_rtx;
3033 /* In this case this insn isn't serving a useful purpose. We
3034 will delete it in reload_as_needed once we know that this
3035 elimination is, in fact, being done.
3037 If REPLACE isn't set, we can't delete this insn, but needn't
3038 process it since it won't be used unless something changes. */
3041 delete_dead_insn (insn);
3049 /* We allow one special case which happens to work on all machines we
3050 currently support: a single set with the source being a PLUS of an
3051 eliminable register and a constant. */
3053 && GET_CODE (SET_DEST (old_set)) == REG
3054 && GET_CODE (SET_SRC (old_set)) == PLUS
3055 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3056 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3057 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3059 rtx reg = XEXP (SET_SRC (old_set), 0);
3060 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3062 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3063 if (ep->from_rtx == reg && ep->can_eliminate)
3065 offset += ep->offset;
3070 /* We assume here that if we need a PARALLEL with
3071 CLOBBERs for this assignment, we can do with the
3072 MATCH_SCRATCHes that add_clobbers allocates.
3073 There's not much we can do if that doesn't work. */
3074 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3078 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3081 rtvec vec = rtvec_alloc (num_clobbers + 1);
3083 vec->elem[0] = PATTERN (insn);
3084 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3085 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3087 if (INSN_CODE (insn) < 0)
3092 new_body = old_body;
3095 new_body = copy_insn (old_body);
3096 if (REG_NOTES (insn))
3097 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3099 PATTERN (insn) = new_body;
3100 old_set = single_set (insn);
3102 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3103 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3106 /* This can't have an effect on elimination offsets, so skip right
3112 /* Determine the effects of this insn on elimination offsets. */
3113 elimination_effects (old_body, 0);
3115 /* Eliminate all eliminable registers occurring in operands that
3116 can be handled by reload. */
3117 extract_insn (insn);
3118 for (i = 0; i < recog_data.n_operands; i++)
3120 orig_operand[i] = recog_data.operand[i];
3121 substed_operand[i] = recog_data.operand[i];
3123 /* For an asm statement, every operand is eliminable. */
3124 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3126 /* Check for setting a register that we know about. */
3127 if (recog_data.operand_type[i] != OP_IN
3128 && GET_CODE (orig_operand[i]) == REG)
3130 /* If we are assigning to a register that can be eliminated, it
3131 must be as part of a PARALLEL, since the code above handles
3132 single SETs. We must indicate that we can no longer
3133 eliminate this reg. */
3134 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3136 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3137 ep->can_eliminate = 0;
3140 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3141 replace ? insn : NULL_RTX);
3142 if (substed_operand[i] != orig_operand[i])
3144 /* Terminate the search in check_eliminable_occurrences at
3146 *recog_data.operand_loc[i] = 0;
3148 /* If an output operand changed from a REG to a MEM and INSN is an
3149 insn, write a CLOBBER insn. */
3150 if (recog_data.operand_type[i] != OP_IN
3151 && GET_CODE (orig_operand[i]) == REG
3152 && GET_CODE (substed_operand[i]) == MEM
3154 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3159 for (i = 0; i < recog_data.n_dups; i++)
3160 *recog_data.dup_loc[i]
3161 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3163 /* If any eliminable remain, they aren't eliminable anymore. */
3164 check_eliminable_occurrences (old_body);
3166 /* Substitute the operands; the new values are in the substed_operand
3168 for (i = 0; i < recog_data.n_operands; i++)
3169 *recog_data.operand_loc[i] = substed_operand[i];
3170 for (i = 0; i < recog_data.n_dups; i++)
3171 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3173 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3174 re-recognize the insn. We do this in case we had a simple addition
3175 but now can do this as a load-address. This saves an insn in this
3177 If re-recognition fails, the old insn code number will still be used,
3178 and some register operands may have changed into PLUS expressions.
3179 These will be handled by find_reloads by loading them into a register
3184 /* If we aren't replacing things permanently and we changed something,
3185 make another copy to ensure that all the RTL is new. Otherwise
3186 things can go wrong if find_reload swaps commutative operands
3187 and one is inside RTL that has been copied while the other is not. */
3188 new_body = old_body;
3191 new_body = copy_insn (old_body);
3192 if (REG_NOTES (insn))
3193 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3195 PATTERN (insn) = new_body;
3197 /* If we had a move insn but now we don't, rerecognize it. This will
3198 cause spurious re-recognition if the old move had a PARALLEL since
3199 the new one still will, but we can't call single_set without
3200 having put NEW_BODY into the insn and the re-recognition won't
3201 hurt in this rare case. */
3202 /* ??? Why this huge if statement - why don't we just rerecognize the
3206 && ((GET_CODE (SET_SRC (old_set)) == REG
3207 && (GET_CODE (new_body) != SET
3208 || GET_CODE (SET_SRC (new_body)) != REG))
3209 /* If this was a load from or store to memory, compare
3210 the MEM in recog_data.operand to the one in the insn.
3211 If they are not equal, then rerecognize the insn. */
3213 && ((GET_CODE (SET_SRC (old_set)) == MEM
3214 && SET_SRC (old_set) != recog_data.operand[1])
3215 || (GET_CODE (SET_DEST (old_set)) == MEM
3216 && SET_DEST (old_set) != recog_data.operand[0])))
3217 /* If this was an add insn before, rerecognize. */
3218 || GET_CODE (SET_SRC (old_set)) == PLUS))
3220 int new_icode = recog (PATTERN (insn), insn, 0);
3222 INSN_CODE (insn) = icode;
3226 /* Restore the old body. If there were any changes to it, we made a copy
3227 of it while the changes were still in place, so we'll correctly return
3228 a modified insn below. */
3231 /* Restore the old body. */
3232 for (i = 0; i < recog_data.n_operands; i++)
3233 *recog_data.operand_loc[i] = orig_operand[i];
3234 for (i = 0; i < recog_data.n_dups; i++)
3235 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3238 /* Update all elimination pairs to reflect the status after the current
3239 insn. The changes we make were determined by the earlier call to
3240 elimination_effects.
3242 We also detect cases where register elimination cannot be done,
3243 namely, if a register would be both changed and referenced outside a MEM
3244 in the resulting insn since such an insn is often undefined and, even if
3245 not, we cannot know what meaning will be given to it. Note that it is
3246 valid to have a register used in an address in an insn that changes it
3247 (presumably with a pre- or post-increment or decrement).
3249 If anything changes, return nonzero. */
3251 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3253 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3254 ep->can_eliminate = 0;
3256 ep->ref_outside_mem = 0;
3258 if (ep->previous_offset != ep->offset)
3263 /* If we changed something, perform elimination in REG_NOTES. This is
3264 needed even when REPLACE is zero because a REG_DEAD note might refer
3265 to a register that we eliminate and could cause a different number
3266 of spill registers to be needed in the final reload pass than in
3268 if (val && REG_NOTES (insn) != 0)
3269 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3274 /* Loop through all elimination pairs.
3275 Recalculate the number not at initial offset.
3277 Compute the maximum offset (minimum offset if the stack does not
3278 grow downward) for each elimination pair. */
3281 update_eliminable_offsets ()
3283 struct elim_table *ep;
3285 num_not_at_initial_offset = 0;
3286 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3288 ep->previous_offset = ep->offset;
3289 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3290 num_not_at_initial_offset++;
3294 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3295 replacement we currently believe is valid, mark it as not eliminable if X
3296 modifies DEST in any way other than by adding a constant integer to it.
3298 If DEST is the frame pointer, we do nothing because we assume that
3299 all assignments to the hard frame pointer are nonlocal gotos and are being
3300 done at a time when they are valid and do not disturb anything else.
3301 Some machines want to eliminate a fake argument pointer with either the
3302 frame or stack pointer. Assignments to the hard frame pointer must not
3303 prevent this elimination.
3305 Called via note_stores from reload before starting its passes to scan
3306 the insns of the function. */
3309 mark_not_eliminable (dest, x, data)
3312 void *data ATTRIBUTE_UNUSED;
3316 /* A SUBREG of a hard register here is just changing its mode. We should
3317 not see a SUBREG of an eliminable hard register, but check just in
3319 if (GET_CODE (dest) == SUBREG)
3320 dest = SUBREG_REG (dest);
3322 if (dest == hard_frame_pointer_rtx)
3325 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3326 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3327 && (GET_CODE (x) != SET
3328 || GET_CODE (SET_SRC (x)) != PLUS
3329 || XEXP (SET_SRC (x), 0) != dest
3330 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3332 reg_eliminate[i].can_eliminate_previous
3333 = reg_eliminate[i].can_eliminate = 0;
3338 /* Verify that the initial elimination offsets did not change since the
3339 last call to set_initial_elim_offsets. This is used to catch cases
3340 where something illegal happened during reload_as_needed that could
3341 cause incorrect code to be generated if we did not check for it. */
3344 verify_initial_elim_offsets ()
3348 #ifdef ELIMINABLE_REGS
3349 struct elim_table *ep;
3351 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3353 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3354 if (t != ep->initial_offset)
3358 INITIAL_FRAME_POINTER_OFFSET (t);
3359 if (t != reg_eliminate[0].initial_offset)
3364 /* Reset all offsets on eliminable registers to their initial values. */
3367 set_initial_elim_offsets ()
3369 struct elim_table *ep = reg_eliminate;
3371 #ifdef ELIMINABLE_REGS
3372 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3374 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3375 ep->previous_offset = ep->offset = ep->initial_offset;
3378 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3379 ep->previous_offset = ep->offset = ep->initial_offset;
3382 num_not_at_initial_offset = 0;
3385 /* Initialize the known label offsets.
3386 Set a known offset for each forced label to be at the initial offset
3387 of each elimination. We do this because we assume that all
3388 computed jumps occur from a location where each elimination is
3389 at its initial offset.
3390 For all other labels, show that we don't know the offsets. */
3393 set_initial_label_offsets ()
3396 memset (offsets_known_at, 0, num_labels);
3398 for (x = forced_labels; x; x = XEXP (x, 1))
3400 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3403 /* Set all elimination offsets to the known values for the code label given
3407 set_offsets_for_label (insn)
3411 int label_nr = CODE_LABEL_NUMBER (insn);
3412 struct elim_table *ep;
3414 num_not_at_initial_offset = 0;
3415 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3417 ep->offset = ep->previous_offset
3418 = offsets_at[label_nr - first_label_num][i];
3419 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3420 num_not_at_initial_offset++;
3424 /* See if anything that happened changes which eliminations are valid.
3425 For example, on the SPARC, whether or not the frame pointer can
3426 be eliminated can depend on what registers have been used. We need
3427 not check some conditions again (such as flag_omit_frame_pointer)
3428 since they can't have changed. */
3431 update_eliminables (pset)
3434 int previous_frame_pointer_needed = frame_pointer_needed;
3435 struct elim_table *ep;
3437 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3438 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3439 #ifdef ELIMINABLE_REGS
3440 || ! CAN_ELIMINATE (ep->from, ep->to)
3443 ep->can_eliminate = 0;
3445 /* Look for the case where we have discovered that we can't replace
3446 register A with register B and that means that we will now be
3447 trying to replace register A with register C. This means we can
3448 no longer replace register C with register B and we need to disable
3449 such an elimination, if it exists. This occurs often with A == ap,
3450 B == sp, and C == fp. */
3452 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3454 struct elim_table *op;
3457 if (! ep->can_eliminate && ep->can_eliminate_previous)
3459 /* Find the current elimination for ep->from, if there is a
3461 for (op = reg_eliminate;
3462 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3463 if (op->from == ep->from && op->can_eliminate)
3469 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3471 for (op = reg_eliminate;
3472 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3473 if (op->from == new_to && op->to == ep->to)
3474 op->can_eliminate = 0;
3478 /* See if any registers that we thought we could eliminate the previous
3479 time are no longer eliminable. If so, something has changed and we
3480 must spill the register. Also, recompute the number of eliminable
3481 registers and see if the frame pointer is needed; it is if there is
3482 no elimination of the frame pointer that we can perform. */
3484 frame_pointer_needed = 1;
3485 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3487 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3488 && ep->to != HARD_FRAME_POINTER_REGNUM)
3489 frame_pointer_needed = 0;
3491 if (! ep->can_eliminate && ep->can_eliminate_previous)
3493 ep->can_eliminate_previous = 0;
3494 SET_HARD_REG_BIT (*pset, ep->from);
3499 /* If we didn't need a frame pointer last time, but we do now, spill
3500 the hard frame pointer. */
3501 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3502 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3505 /* Initialize the table of registers to eliminate. */
3510 struct elim_table *ep;
3511 #ifdef ELIMINABLE_REGS
3512 const struct elim_table_1 *ep1;
3516 reg_eliminate = (struct elim_table *)
3517 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3519 /* Does this function require a frame pointer? */
3521 frame_pointer_needed = (! flag_omit_frame_pointer
3522 #ifdef EXIT_IGNORE_STACK
3523 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3524 and restore sp for alloca. So we can't eliminate
3525 the frame pointer in that case. At some point,
3526 we should improve this by emitting the
3527 sp-adjusting insns for this case. */
3528 || (current_function_calls_alloca
3529 && EXIT_IGNORE_STACK)
3531 || FRAME_POINTER_REQUIRED);
3535 #ifdef ELIMINABLE_REGS
3536 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3537 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3539 ep->from = ep1->from;
3541 ep->can_eliminate = ep->can_eliminate_previous
3542 = (CAN_ELIMINATE (ep->from, ep->to)
3543 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3546 reg_eliminate[0].from = reg_eliminate_1[0].from;
3547 reg_eliminate[0].to = reg_eliminate_1[0].to;
3548 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3549 = ! frame_pointer_needed;
3552 /* Count the number of eliminable registers and build the FROM and TO
3553 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3554 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3555 We depend on this. */
3556 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3558 num_eliminable += ep->can_eliminate;
3559 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3560 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3564 /* Kick all pseudos out of hard register REGNO.
3566 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3567 because we found we can't eliminate some register. In the case, no pseudos
3568 are allowed to be in the register, even if they are only in a block that
3569 doesn't require spill registers, unlike the case when we are spilling this
3570 hard reg to produce another spill register.
3572 Return nonzero if any pseudos needed to be kicked out. */
3575 spill_hard_reg (regno, cant_eliminate)
3583 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3584 regs_ever_live[regno] = 1;
3587 /* Spill every pseudo reg that was allocated to this reg
3588 or to something that overlaps this reg. */
3590 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3591 if (reg_renumber[i] >= 0
3592 && (unsigned int) reg_renumber[i] <= regno
3593 && ((unsigned int) reg_renumber[i]
3594 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3595 PSEUDO_REGNO_MODE (i))
3597 SET_REGNO_REG_SET (&spilled_pseudos, i);
3600 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3601 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3604 ior_hard_reg_set (set1, set2)
3605 HARD_REG_SET *set1, *set2;
3607 IOR_HARD_REG_SET (*set1, *set2);
3610 /* After find_reload_regs has been run for all insn that need reloads,
3611 and/or spill_hard_regs was called, this function is used to actually
3612 spill pseudo registers and try to reallocate them. It also sets up the
3613 spill_regs array for use by choose_reload_regs. */
3616 finish_spills (global)
3619 struct insn_chain *chain;
3620 int something_changed = 0;
3623 /* Build the spill_regs array for the function. */
3624 /* If there are some registers still to eliminate and one of the spill regs
3625 wasn't ever used before, additional stack space may have to be
3626 allocated to store this register. Thus, we may have changed the offset
3627 between the stack and frame pointers, so mark that something has changed.
3629 One might think that we need only set VAL to 1 if this is a call-used
3630 register. However, the set of registers that must be saved by the
3631 prologue is not identical to the call-used set. For example, the
3632 register used by the call insn for the return PC is a call-used register,
3633 but must be saved by the prologue. */
3636 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3637 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3639 spill_reg_order[i] = n_spills;
3640 spill_regs[n_spills++] = i;
3641 if (num_eliminable && ! regs_ever_live[i])
3642 something_changed = 1;
3643 regs_ever_live[i] = 1;
3646 spill_reg_order[i] = -1;
3648 EXECUTE_IF_SET_IN_REG_SET
3649 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3651 /* Record the current hard register the pseudo is allocated to in
3652 pseudo_previous_regs so we avoid reallocating it to the same
3653 hard reg in a later pass. */
3654 if (reg_renumber[i] < 0)
3657 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3658 /* Mark it as no longer having a hard register home. */
3659 reg_renumber[i] = -1;
3660 /* We will need to scan everything again. */
3661 something_changed = 1;
3664 /* Retry global register allocation if possible. */
3667 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3668 /* For every insn that needs reloads, set the registers used as spill
3669 regs in pseudo_forbidden_regs for every pseudo live across the
3671 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3673 EXECUTE_IF_SET_IN_REG_SET
3674 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3676 ior_hard_reg_set (pseudo_forbidden_regs + i,
3677 &chain->used_spill_regs);
3679 EXECUTE_IF_SET_IN_REG_SET
3680 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3682 ior_hard_reg_set (pseudo_forbidden_regs + i,
3683 &chain->used_spill_regs);
3687 /* Retry allocating the spilled pseudos. For each reg, merge the
3688 various reg sets that indicate which hard regs can't be used,
3689 and call retry_global_alloc.
3690 We change spill_pseudos here to only contain pseudos that did not
3691 get a new hard register. */
3692 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3693 if (reg_old_renumber[i] != reg_renumber[i])
3695 HARD_REG_SET forbidden;
3696 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3697 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3698 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3699 retry_global_alloc (i, forbidden);
3700 if (reg_renumber[i] >= 0)
3701 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3705 /* Fix up the register information in the insn chain.
3706 This involves deleting those of the spilled pseudos which did not get
3707 a new hard register home from the live_{before,after} sets. */
3708 for (chain = reload_insn_chain; chain; chain = chain->next)
3710 HARD_REG_SET used_by_pseudos;
3711 HARD_REG_SET used_by_pseudos2;
3713 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3714 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3716 /* Mark any unallocated hard regs as available for spills. That
3717 makes inheritance work somewhat better. */
3718 if (chain->need_reload)
3720 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3721 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3722 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3724 /* Save the old value for the sanity test below. */
3725 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3727 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3728 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3729 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3730 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3732 /* Make sure we only enlarge the set. */
3733 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3739 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3740 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3742 int regno = reg_renumber[i];
3743 if (reg_old_renumber[i] == regno)
3746 alter_reg (i, reg_old_renumber[i]);
3747 reg_old_renumber[i] = regno;
3751 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3753 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3754 i, reg_renumber[i]);
3758 return something_changed;
3761 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3762 Also mark any hard registers used to store user variables as
3763 forbidden from being used for spill registers. */
3766 scan_paradoxical_subregs (x)
3771 enum rtx_code code = GET_CODE (x);
3777 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3778 && REG_USERVAR_P (x))
3779 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3788 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3796 if (GET_CODE (SUBREG_REG (x)) == REG
3797 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3798 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3799 = GET_MODE_SIZE (GET_MODE (x));
3806 fmt = GET_RTX_FORMAT (code);
3807 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3810 scan_paradoxical_subregs (XEXP (x, i));
3811 else if (fmt[i] == 'E')
3814 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3815 scan_paradoxical_subregs (XVECEXP (x, i, j));
3820 /* Reload pseudo-registers into hard regs around each insn as needed.
3821 Additional register load insns are output before the insn that needs it
3822 and perhaps store insns after insns that modify the reloaded pseudo reg.
3824 reg_last_reload_reg and reg_reloaded_contents keep track of
3825 which registers are already available in reload registers.
3826 We update these for the reloads that we perform,
3827 as the insns are scanned. */
3830 reload_as_needed (live_known)
3833 struct insn_chain *chain;
3834 #if defined (AUTO_INC_DEC)
3839 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3840 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3841 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3842 reg_has_output_reload = (char *) xmalloc (max_regno);
3843 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3845 set_initial_elim_offsets ();
3847 for (chain = reload_insn_chain; chain; chain = chain->next)
3850 rtx insn = chain->insn;
3851 rtx old_next = NEXT_INSN (insn);
3853 /* If we pass a label, copy the offsets from the label information
3854 into the current offsets of each elimination. */
3855 if (GET_CODE (insn) == CODE_LABEL)
3856 set_offsets_for_label (insn);
3858 else if (INSN_P (insn))
3860 rtx oldpat = copy_rtx (PATTERN (insn));
3862 /* If this is a USE and CLOBBER of a MEM, ensure that any
3863 references to eliminable registers have been removed. */
3865 if ((GET_CODE (PATTERN (insn)) == USE
3866 || GET_CODE (PATTERN (insn)) == CLOBBER)
3867 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3868 XEXP (XEXP (PATTERN (insn), 0), 0)
3869 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3870 GET_MODE (XEXP (PATTERN (insn), 0)),
3873 /* If we need to do register elimination processing, do so.
3874 This might delete the insn, in which case we are done. */
3875 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3877 eliminate_regs_in_insn (insn, 1);
3878 if (GET_CODE (insn) == NOTE)
3880 update_eliminable_offsets ();
3885 /* If need_elim is nonzero but need_reload is zero, one might think
3886 that we could simply set n_reloads to 0. However, find_reloads
3887 could have done some manipulation of the insn (such as swapping
3888 commutative operands), and these manipulations are lost during
3889 the first pass for every insn that needs register elimination.
3890 So the actions of find_reloads must be redone here. */
3892 if (! chain->need_elim && ! chain->need_reload
3893 && ! chain->need_operand_change)
3895 /* First find the pseudo regs that must be reloaded for this insn.
3896 This info is returned in the tables reload_... (see reload.h).
3897 Also modify the body of INSN by substituting RELOAD
3898 rtx's for those pseudo regs. */
3901 memset (reg_has_output_reload, 0, max_regno);
3902 CLEAR_HARD_REG_SET (reg_is_output_reload);
3904 find_reloads (insn, 1, spill_indirect_levels, live_known,
3910 rtx next = NEXT_INSN (insn);
3913 prev = PREV_INSN (insn);
3915 /* Now compute which reload regs to reload them into. Perhaps
3916 reusing reload regs from previous insns, or else output
3917 load insns to reload them. Maybe output store insns too.
3918 Record the choices of reload reg in reload_reg_rtx. */
3919 choose_reload_regs (chain);
3921 /* Merge any reloads that we didn't combine for fear of
3922 increasing the number of spill registers needed but now
3923 discover can be safely merged. */
3924 if (SMALL_REGISTER_CLASSES)
3925 merge_assigned_reloads (insn);
3927 /* Generate the insns to reload operands into or out of
3928 their reload regs. */
3929 emit_reload_insns (chain);
3931 /* Substitute the chosen reload regs from reload_reg_rtx
3932 into the insn's body (or perhaps into the bodies of other
3933 load and store insn that we just made for reloading
3934 and that we moved the structure into). */
3935 subst_reloads (insn);
3937 /* If this was an ASM, make sure that all the reload insns
3938 we have generated are valid. If not, give an error
3941 if (asm_noperands (PATTERN (insn)) >= 0)
3942 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3943 if (p != insn && INSN_P (p)
3944 && GET_CODE (PATTERN (p)) != USE
3945 && (recog_memoized (p) < 0
3946 || (extract_insn (p), ! constrain_operands (1))))
3948 error_for_asm (insn,
3949 "`asm' operand requires impossible reload");
3954 if (num_eliminable && chain->need_elim)
3955 update_eliminable_offsets ();
3957 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3958 is no longer validly lying around to save a future reload.
3959 Note that this does not detect pseudos that were reloaded
3960 for this insn in order to be stored in
3961 (obeying register constraints). That is correct; such reload
3962 registers ARE still valid. */
3963 note_stores (oldpat, forget_old_reloads_1, NULL);
3965 /* There may have been CLOBBER insns placed after INSN. So scan
3966 between INSN and NEXT and use them to forget old reloads. */
3967 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3968 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3969 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3972 /* Likewise for regs altered by auto-increment in this insn.
3973 REG_INC notes have been changed by reloading:
3974 find_reloads_address_1 records substitutions for them,
3975 which have been performed by subst_reloads above. */
3976 for (i = n_reloads - 1; i >= 0; i--)
3978 rtx in_reg = rld[i].in_reg;
3981 enum rtx_code code = GET_CODE (in_reg);
3982 /* PRE_INC / PRE_DEC will have the reload register ending up
3983 with the same value as the stack slot, but that doesn't
3984 hold true for POST_INC / POST_DEC. Either we have to
3985 convert the memory access to a true POST_INC / POST_DEC,
3986 or we can't use the reload register for inheritance. */
3987 if ((code == POST_INC || code == POST_DEC)
3988 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3989 REGNO (rld[i].reg_rtx))
3990 /* Make sure it is the inc/dec pseudo, and not
3991 some other (e.g. output operand) pseudo. */
3992 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3993 == REGNO (XEXP (in_reg, 0))))
3996 rtx reload_reg = rld[i].reg_rtx;
3997 enum machine_mode mode = GET_MODE (reload_reg);
4001 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4003 /* We really want to ignore REG_INC notes here, so
4004 use PATTERN (p) as argument to reg_set_p . */
4005 if (reg_set_p (reload_reg, PATTERN (p)))
4007 n = count_occurrences (PATTERN (p), reload_reg, 0);
4012 n = validate_replace_rtx (reload_reg,
4013 gen_rtx (code, mode,
4017 /* We must also verify that the constraints
4018 are met after the replacement. */
4021 n = constrain_operands (1);
4025 /* If the constraints were not met, then
4026 undo the replacement. */
4029 validate_replace_rtx (gen_rtx (code, mode,
4041 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4043 /* Mark this as having an output reload so that the
4044 REG_INC processing code below won't invalidate
4045 the reload for inheritance. */
4046 SET_HARD_REG_BIT (reg_is_output_reload,
4047 REGNO (reload_reg));
4048 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4051 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4054 else if ((code == PRE_INC || code == PRE_DEC)
4055 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4056 REGNO (rld[i].reg_rtx))
4057 /* Make sure it is the inc/dec pseudo, and not
4058 some other (e.g. output operand) pseudo. */
4059 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4060 == REGNO (XEXP (in_reg, 0))))
4062 SET_HARD_REG_BIT (reg_is_output_reload,
4063 REGNO (rld[i].reg_rtx));
4064 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4068 /* If a pseudo that got a hard register is auto-incremented,
4069 we must purge records of copying it into pseudos without
4071 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4072 if (REG_NOTE_KIND (x) == REG_INC)
4074 /* See if this pseudo reg was reloaded in this insn.
4075 If so, its last-reload info is still valid
4076 because it is based on this insn's reload. */
4077 for (i = 0; i < n_reloads; i++)
4078 if (rld[i].out == XEXP (x, 0))
4082 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4086 /* A reload reg's contents are unknown after a label. */
4087 if (GET_CODE (insn) == CODE_LABEL)
4088 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4090 /* Don't assume a reload reg is still good after a call insn
4091 if it is a call-used reg. */
4092 else if (GET_CODE (insn) == CALL_INSN)
4093 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4097 free (reg_last_reload_reg);
4098 free (reg_has_output_reload);
4101 /* Discard all record of any value reloaded from X,
4102 or reloaded in X from someplace else;
4103 unless X is an output reload reg of the current insn.
4105 X may be a hard reg (the reload reg)
4106 or it may be a pseudo reg that was reloaded from. */
4109 forget_old_reloads_1 (x, ignored, data)
4111 rtx ignored ATTRIBUTE_UNUSED;
4112 void *data ATTRIBUTE_UNUSED;
4117 /* note_stores does give us subregs of hard regs,
4118 subreg_regno_offset will abort if it is not a hard reg. */
4119 while (GET_CODE (x) == SUBREG)
4121 /* We ignore the subreg offset when calculating the regno,
4122 because we are using the entire underlying hard register
4127 if (GET_CODE (x) != REG)
4132 if (regno >= FIRST_PSEUDO_REGISTER)
4138 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4139 /* Storing into a spilled-reg invalidates its contents.
4140 This can happen if a block-local pseudo is allocated to that reg
4141 and it wasn't spilled because this block's total need is 0.
4142 Then some insn might have an optional reload and use this reg. */
4143 for (i = 0; i < nr; i++)
4144 /* But don't do this if the reg actually serves as an output
4145 reload reg in the current instruction. */
4147 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4149 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4150 spill_reg_store[regno + i] = 0;
4154 /* Since value of X has changed,
4155 forget any value previously copied from it. */
4158 /* But don't forget a copy if this is the output reload
4159 that establishes the copy's validity. */
4160 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4161 reg_last_reload_reg[regno + nr] = 0;
4164 /* The following HARD_REG_SETs indicate when each hard register is
4165 used for a reload of various parts of the current insn. */
4167 /* If reg is unavailable for all reloads. */
4168 static HARD_REG_SET reload_reg_unavailable;
4169 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4170 static HARD_REG_SET reload_reg_used;
4171 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4172 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4173 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4174 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4175 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4176 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4177 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4178 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4179 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4180 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4181 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4182 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4183 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4184 static HARD_REG_SET reload_reg_used_in_op_addr;
4185 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4186 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4187 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4188 static HARD_REG_SET reload_reg_used_in_insn;
4189 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4190 static HARD_REG_SET reload_reg_used_in_other_addr;
4192 /* If reg is in use as a reload reg for any sort of reload. */
4193 static HARD_REG_SET reload_reg_used_at_all;
4195 /* If reg is use as an inherited reload. We just mark the first register
4197 static HARD_REG_SET reload_reg_used_for_inherit;
4199 /* Records which hard regs are used in any way, either as explicit use or
4200 by being allocated to a pseudo during any point of the current insn. */
4201 static HARD_REG_SET reg_used_in_insn;
4203 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4204 TYPE. MODE is used to indicate how many consecutive regs are
4208 mark_reload_reg_in_use (regno, opnum, type, mode)
4211 enum reload_type type;
4212 enum machine_mode mode;
4214 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4217 for (i = regno; i < nregs + regno; i++)
4222 SET_HARD_REG_BIT (reload_reg_used, i);
4225 case RELOAD_FOR_INPUT_ADDRESS:
4226 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4229 case RELOAD_FOR_INPADDR_ADDRESS:
4230 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4233 case RELOAD_FOR_OUTPUT_ADDRESS:
4234 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4237 case RELOAD_FOR_OUTADDR_ADDRESS:
4238 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4241 case RELOAD_FOR_OPERAND_ADDRESS:
4242 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4245 case RELOAD_FOR_OPADDR_ADDR:
4246 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4249 case RELOAD_FOR_OTHER_ADDRESS:
4250 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4253 case RELOAD_FOR_INPUT:
4254 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4257 case RELOAD_FOR_OUTPUT:
4258 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4261 case RELOAD_FOR_INSN:
4262 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4266 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4270 /* Similarly, but show REGNO is no longer in use for a reload. */
4273 clear_reload_reg_in_use (regno, opnum, type, mode)
4276 enum reload_type type;
4277 enum machine_mode mode;
4279 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4280 unsigned int start_regno, end_regno, r;
4282 /* A complication is that for some reload types, inheritance might
4283 allow multiple reloads of the same types to share a reload register.
4284 We set check_opnum if we have to check only reloads with the same
4285 operand number, and check_any if we have to check all reloads. */
4286 int check_opnum = 0;
4288 HARD_REG_SET *used_in_set;
4293 used_in_set = &reload_reg_used;
4296 case RELOAD_FOR_INPUT_ADDRESS:
4297 used_in_set = &reload_reg_used_in_input_addr[opnum];
4300 case RELOAD_FOR_INPADDR_ADDRESS:
4302 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4305 case RELOAD_FOR_OUTPUT_ADDRESS:
4306 used_in_set = &reload_reg_used_in_output_addr[opnum];
4309 case RELOAD_FOR_OUTADDR_ADDRESS:
4311 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4314 case RELOAD_FOR_OPERAND_ADDRESS:
4315 used_in_set = &reload_reg_used_in_op_addr;
4318 case RELOAD_FOR_OPADDR_ADDR:
4320 used_in_set = &reload_reg_used_in_op_addr_reload;
4323 case RELOAD_FOR_OTHER_ADDRESS:
4324 used_in_set = &reload_reg_used_in_other_addr;
4328 case RELOAD_FOR_INPUT:
4329 used_in_set = &reload_reg_used_in_input[opnum];
4332 case RELOAD_FOR_OUTPUT:
4333 used_in_set = &reload_reg_used_in_output[opnum];
4336 case RELOAD_FOR_INSN:
4337 used_in_set = &reload_reg_used_in_insn;
4342 /* We resolve conflicts with remaining reloads of the same type by
4343 excluding the intervals of reload registers by them from the
4344 interval of freed reload registers. Since we only keep track of
4345 one set of interval bounds, we might have to exclude somewhat
4346 more than what would be necessary if we used a HARD_REG_SET here.
4347 But this should only happen very infrequently, so there should
4348 be no reason to worry about it. */
4350 start_regno = regno;
4351 end_regno = regno + nregs;
4352 if (check_opnum || check_any)
4354 for (i = n_reloads - 1; i >= 0; i--)
4356 if (rld[i].when_needed == type
4357 && (check_any || rld[i].opnum == opnum)
4360 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4361 unsigned int conflict_end
4363 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4365 /* If there is an overlap with the first to-be-freed register,
4366 adjust the interval start. */
4367 if (conflict_start <= start_regno && conflict_end > start_regno)
4368 start_regno = conflict_end;
4369 /* Otherwise, if there is a conflict with one of the other
4370 to-be-freed registers, adjust the interval end. */
4371 if (conflict_start > start_regno && conflict_start < end_regno)
4372 end_regno = conflict_start;
4377 for (r = start_regno; r < end_regno; r++)
4378 CLEAR_HARD_REG_BIT (*used_in_set, r);
4381 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4382 specified by OPNUM and TYPE. */
4385 reload_reg_free_p (regno, opnum, type)
4388 enum reload_type type;
4392 /* In use for a RELOAD_OTHER means it's not available for anything. */
4393 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4394 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4400 /* In use for anything means we can't use it for RELOAD_OTHER. */
4401 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4402 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4403 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4406 for (i = 0; i < reload_n_operands; i++)
4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4408 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4409 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4410 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4411 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4412 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4417 case RELOAD_FOR_INPUT:
4418 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4419 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4422 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4425 /* If it is used for some other input, can't use it. */
4426 for (i = 0; i < reload_n_operands; i++)
4427 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4430 /* If it is used in a later operand's address, can't use it. */
4431 for (i = opnum + 1; i < reload_n_operands; i++)
4432 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4433 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4438 case RELOAD_FOR_INPUT_ADDRESS:
4439 /* Can't use a register if it is used for an input address for this
4440 operand or used as an input in an earlier one. */
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4445 for (i = 0; i < opnum; i++)
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4451 case RELOAD_FOR_INPADDR_ADDRESS:
4452 /* Can't use a register if it is used for an input address
4453 for this operand or used as an input in an earlier
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4458 for (i = 0; i < opnum; i++)
4459 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4464 case RELOAD_FOR_OUTPUT_ADDRESS:
4465 /* Can't use a register if it is used for an output address for this
4466 operand or used as an output in this or a later operand. Note
4467 that multiple output operands are emitted in reverse order, so
4468 the conflicting ones are those with lower indices. */
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4472 for (i = 0; i <= opnum; i++)
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4478 case RELOAD_FOR_OUTADDR_ADDRESS:
4479 /* Can't use a register if it is used for an output address
4480 for this operand or used as an output in this or a
4481 later operand. Note that multiple output operands are
4482 emitted in reverse order, so the conflicting ones are
4483 those with lower indices. */
4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4487 for (i = 0; i <= opnum; i++)
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4493 case RELOAD_FOR_OPERAND_ADDRESS:
4494 for (i = 0; i < reload_n_operands; i++)
4495 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4498 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4499 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4501 case RELOAD_FOR_OPADDR_ADDR:
4502 for (i = 0; i < reload_n_operands; i++)
4503 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4506 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4508 case RELOAD_FOR_OUTPUT:
4509 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4510 outputs, or an operand address for this or an earlier output.
4511 Note that multiple output operands are emitted in reverse order,
4512 so the conflicting ones are those with higher indices. */
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4516 for (i = 0; i < reload_n_operands; i++)
4517 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4520 for (i = opnum; i < reload_n_operands; i++)
4521 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4522 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4527 case RELOAD_FOR_INSN:
4528 for (i = 0; i < reload_n_operands; i++)
4529 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4533 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4534 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4536 case RELOAD_FOR_OTHER_ADDRESS:
4537 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4542 /* Return 1 if the value in reload reg REGNO, as used by a reload
4543 needed for the part of the insn specified by OPNUM and TYPE,
4544 is still available in REGNO at the end of the insn.
4546 We can assume that the reload reg was already tested for availability
4547 at the time it is needed, and we should not check this again,
4548 in case the reg has already been marked in use. */
4551 reload_reg_reaches_end_p (regno, opnum, type)
4554 enum reload_type type;
4561 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4562 its value must reach the end. */
4565 /* If this use is for part of the insn,
4566 its value reaches if no subsequent part uses the same register.
4567 Just like the above function, don't try to do this with lots
4570 case RELOAD_FOR_OTHER_ADDRESS:
4571 /* Here we check for everything else, since these don't conflict
4572 with anything else and everything comes later. */
4574 for (i = 0; i < reload_n_operands; i++)
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4577 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4578 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4579 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4580 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4583 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4584 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4585 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4587 case RELOAD_FOR_INPUT_ADDRESS:
4588 case RELOAD_FOR_INPADDR_ADDRESS:
4589 /* Similar, except that we check only for this and subsequent inputs
4590 and the address of only subsequent inputs and we do not need
4591 to check for RELOAD_OTHER objects since they are known not to
4594 for (i = opnum; i < reload_n_operands; i++)
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4598 for (i = opnum + 1; i < reload_n_operands; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4600 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4603 for (i = 0; i < reload_n_operands; i++)
4604 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4605 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4606 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4609 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4612 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4613 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4614 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4616 case RELOAD_FOR_INPUT:
4617 /* Similar to input address, except we start at the next operand for
4618 both input and input address and we do not check for
4619 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4622 for (i = opnum + 1; i < reload_n_operands; i++)
4623 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4624 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4625 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4628 /* ... fall through ... */
4630 case RELOAD_FOR_OPERAND_ADDRESS:
4631 /* Check outputs and their addresses. */
4633 for (i = 0; i < reload_n_operands; i++)
4634 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4635 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4636 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4639 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4641 case RELOAD_FOR_OPADDR_ADDR:
4642 for (i = 0; i < reload_n_operands; i++)
4643 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4644 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4645 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4648 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4649 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4650 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4652 case RELOAD_FOR_INSN:
4653 /* These conflict with other outputs with RELOAD_OTHER. So
4654 we need only check for output addresses. */
4656 opnum = reload_n_operands;
4658 /* ... fall through ... */
4660 case RELOAD_FOR_OUTPUT:
4661 case RELOAD_FOR_OUTPUT_ADDRESS:
4662 case RELOAD_FOR_OUTADDR_ADDRESS:
4663 /* We already know these can't conflict with a later output. So the
4664 only thing to check are later output addresses.
4665 Note that multiple output operands are emitted in reverse order,
4666 so the conflicting ones are those with lower indices. */
4667 for (i = 0; i < opnum; i++)
4668 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4669 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4678 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4681 This function uses the same algorithm as reload_reg_free_p above. */
4684 reloads_conflict (r1, r2)
4687 enum reload_type r1_type = rld[r1].when_needed;
4688 enum reload_type r2_type = rld[r2].when_needed;
4689 int r1_opnum = rld[r1].opnum;
4690 int r2_opnum = rld[r2].opnum;
4692 /* RELOAD_OTHER conflicts with everything. */
4693 if (r2_type == RELOAD_OTHER)
4696 /* Otherwise, check conflicts differently for each type. */
4700 case RELOAD_FOR_INPUT:
4701 return (r2_type == RELOAD_FOR_INSN
4702 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4703 || r2_type == RELOAD_FOR_OPADDR_ADDR
4704 || r2_type == RELOAD_FOR_INPUT
4705 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4706 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4707 && r2_opnum > r1_opnum));
4709 case RELOAD_FOR_INPUT_ADDRESS:
4710 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4711 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4713 case RELOAD_FOR_INPADDR_ADDRESS:
4714 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4715 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4717 case RELOAD_FOR_OUTPUT_ADDRESS:
4718 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4719 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4721 case RELOAD_FOR_OUTADDR_ADDRESS:
4722 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4723 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4725 case RELOAD_FOR_OPERAND_ADDRESS:
4726 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4727 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4729 case RELOAD_FOR_OPADDR_ADDR:
4730 return (r2_type == RELOAD_FOR_INPUT
4731 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4733 case RELOAD_FOR_OUTPUT:
4734 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4735 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4736 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4737 && r2_opnum >= r1_opnum));
4739 case RELOAD_FOR_INSN:
4740 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4741 || r2_type == RELOAD_FOR_INSN
4742 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4744 case RELOAD_FOR_OTHER_ADDRESS:
4745 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4755 /* Indexed by reload number, 1 if incoming value
4756 inherited from previous insns. */
4757 char reload_inherited[MAX_RELOADS];
4759 /* For an inherited reload, this is the insn the reload was inherited from,
4760 if we know it. Otherwise, this is 0. */
4761 rtx reload_inheritance_insn[MAX_RELOADS];
4763 /* If nonzero, this is a place to get the value of the reload,
4764 rather than using reload_in. */
4765 rtx reload_override_in[MAX_RELOADS];
4767 /* For each reload, the hard register number of the register used,
4768 or -1 if we did not need a register for this reload. */
4769 int reload_spill_index[MAX_RELOADS];
4771 /* Subroutine of free_for_value_p, used to check a single register.
4772 START_REGNO is the starting regno of the full reload register
4773 (possibly comprising multiple hard registers) that we are considering. */
4776 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4777 reloadnum, ignore_address_reloads)
4778 int start_regno, regno;
4780 enum reload_type type;
4783 int ignore_address_reloads;
4786 /* Set if we see an input reload that must not share its reload register
4787 with any new earlyclobber, but might otherwise share the reload
4788 register with an output or input-output reload. */
4789 int check_earlyclobber = 0;
4793 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4796 if (out == const0_rtx)
4802 /* We use some pseudo 'time' value to check if the lifetimes of the
4803 new register use would overlap with the one of a previous reload
4804 that is not read-only or uses a different value.
4805 The 'time' used doesn't have to be linear in any shape or form, just
4807 Some reload types use different 'buckets' for each operand.
4808 So there are MAX_RECOG_OPERANDS different time values for each
4810 We compute TIME1 as the time when the register for the prospective
4811 new reload ceases to be live, and TIME2 for each existing
4812 reload as the time when that the reload register of that reload
4814 Where there is little to be gained by exact lifetime calculations,
4815 we just make conservative assumptions, i.e. a longer lifetime;
4816 this is done in the 'default:' cases. */
4819 case RELOAD_FOR_OTHER_ADDRESS:
4820 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4821 time1 = copy ? 0 : 1;
4824 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4826 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4827 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4828 respectively, to the time values for these, we get distinct time
4829 values. To get distinct time values for each operand, we have to
4830 multiply opnum by at least three. We round that up to four because
4831 multiply by four is often cheaper. */
4832 case RELOAD_FOR_INPADDR_ADDRESS:
4833 time1 = opnum * 4 + 2;
4835 case RELOAD_FOR_INPUT_ADDRESS:
4836 time1 = opnum * 4 + 3;
4838 case RELOAD_FOR_INPUT:
4839 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4840 executes (inclusive). */
4841 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4843 case RELOAD_FOR_OPADDR_ADDR:
4845 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4846 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4848 case RELOAD_FOR_OPERAND_ADDRESS:
4849 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4851 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4853 case RELOAD_FOR_OUTADDR_ADDRESS:
4854 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4856 case RELOAD_FOR_OUTPUT_ADDRESS:
4857 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4860 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4863 for (i = 0; i < n_reloads; i++)
4865 rtx reg = rld[i].reg_rtx;
4866 if (reg && GET_CODE (reg) == REG
4867 && ((unsigned) regno - true_regnum (reg)
4868 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4871 rtx other_input = rld[i].in;
4873 /* If the other reload loads the same input value, that
4874 will not cause a conflict only if it's loading it into
4875 the same register. */
4876 if (true_regnum (reg) != start_regno)
4877 other_input = NULL_RTX;
4878 if (! other_input || ! rtx_equal_p (other_input, value)
4879 || rld[i].out || out)
4882 switch (rld[i].when_needed)
4884 case RELOAD_FOR_OTHER_ADDRESS:
4887 case RELOAD_FOR_INPADDR_ADDRESS:
4888 /* find_reloads makes sure that a
4889 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4890 by at most one - the first -
4891 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4892 address reload is inherited, the address address reload
4893 goes away, so we can ignore this conflict. */
4894 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4895 && ignore_address_reloads
4896 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4897 Then the address address is still needed to store
4898 back the new address. */
4899 && ! rld[reloadnum].out)
4901 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4902 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4904 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4905 && ignore_address_reloads
4906 /* Unless we are reloading an auto_inc expression. */
4907 && ! rld[reloadnum].out)
4909 time2 = rld[i].opnum * 4 + 2;
4911 case RELOAD_FOR_INPUT_ADDRESS:
4912 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4913 && ignore_address_reloads
4914 && ! rld[reloadnum].out)
4916 time2 = rld[i].opnum * 4 + 3;
4918 case RELOAD_FOR_INPUT:
4919 time2 = rld[i].opnum * 4 + 4;
4920 check_earlyclobber = 1;
4922 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4923 == MAX_RECOG_OPERAND * 4 */
4924 case RELOAD_FOR_OPADDR_ADDR:
4925 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4926 && ignore_address_reloads
4927 && ! rld[reloadnum].out)
4929 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4931 case RELOAD_FOR_OPERAND_ADDRESS:
4932 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4933 check_earlyclobber = 1;
4935 case RELOAD_FOR_INSN:
4936 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4938 case RELOAD_FOR_OUTPUT:
4939 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4940 instruction is executed. */
4941 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4943 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4944 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4946 case RELOAD_FOR_OUTADDR_ADDRESS:
4947 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4948 && ignore_address_reloads
4949 && ! rld[reloadnum].out)
4951 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4953 case RELOAD_FOR_OUTPUT_ADDRESS:
4954 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4957 /* If there is no conflict in the input part, handle this
4958 like an output reload. */
4959 if (! rld[i].in || rtx_equal_p (other_input, value))
4961 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4962 /* Earlyclobbered outputs must conflict with inputs. */
4963 if (earlyclobber_operand_p (rld[i].out))
4964 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4969 /* RELOAD_OTHER might be live beyond instruction execution,
4970 but this is not obvious when we set time2 = 1. So check
4971 here if there might be a problem with the new reload
4972 clobbering the register used by the RELOAD_OTHER. */
4980 && (! rld[i].in || rld[i].out
4981 || ! rtx_equal_p (other_input, value)))
4982 || (out && rld[reloadnum].out_reg
4983 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4989 /* Earlyclobbered outputs must conflict with inputs. */
4990 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4996 /* Return 1 if the value in reload reg REGNO, as used by a reload
4997 needed for the part of the insn specified by OPNUM and TYPE,
4998 may be used to load VALUE into it.
5000 MODE is the mode in which the register is used, this is needed to
5001 determine how many hard regs to test.
5003 Other read-only reloads with the same value do not conflict
5004 unless OUT is nonzero and these other reloads have to live while
5005 output reloads live.
5006 If OUT is CONST0_RTX, this is a special case: it means that the
5007 test should not be for using register REGNO as reload register, but
5008 for copying from register REGNO into the reload register.
5010 RELOADNUM is the number of the reload we want to load this value for;
5011 a reload does not conflict with itself.
5013 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5014 reloads that load an address for the very reload we are considering.
5016 The caller has to make sure that there is no conflict with the return
5020 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5021 ignore_address_reloads)
5023 enum machine_mode mode;
5025 enum reload_type type;
5028 int ignore_address_reloads;
5030 int nregs = HARD_REGNO_NREGS (regno, mode);
5032 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5033 value, out, reloadnum,
5034 ignore_address_reloads))
5039 /* Determine whether the reload reg X overlaps any rtx'es used for
5040 overriding inheritance. Return nonzero if so. */
5043 conflicts_with_override (x)
5047 for (i = 0; i < n_reloads; i++)
5048 if (reload_override_in[i]
5049 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5054 /* Give an error message saying we failed to find a reload for INSN,
5055 and clear out reload R. */
5057 failed_reload (insn, r)
5061 if (asm_noperands (PATTERN (insn)) < 0)
5062 /* It's the compiler's fault. */
5063 fatal_insn ("could not find a spill register", insn);
5065 /* It's the user's fault; the operand's mode and constraint
5066 don't match. Disable this reload so we don't crash in final. */
5067 error_for_asm (insn,
5068 "`asm' operand constraint incompatible with operand size");
5072 rld[r].optional = 1;
5073 rld[r].secondary_p = 1;
5076 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5077 for reload R. If it's valid, get an rtx for it. Return nonzero if
5080 set_reload_reg (i, r)
5084 rtx reg = spill_reg_rtx[i];
5086 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5087 spill_reg_rtx[i] = reg
5088 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5090 regno = true_regnum (reg);
5092 /* Detect when the reload reg can't hold the reload mode.
5093 This used to be one `if', but Sequent compiler can't handle that. */
5094 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5096 enum machine_mode test_mode = VOIDmode;
5098 test_mode = GET_MODE (rld[r].in);
5099 /* If rld[r].in has VOIDmode, it means we will load it
5100 in whatever mode the reload reg has: to wit, rld[r].mode.
5101 We have already tested that for validity. */
5102 /* Aside from that, we need to test that the expressions
5103 to reload from or into have modes which are valid for this
5104 reload register. Otherwise the reload insns would be invalid. */
5105 if (! (rld[r].in != 0 && test_mode != VOIDmode
5106 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5107 if (! (rld[r].out != 0
5108 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5110 /* The reg is OK. */
5113 /* Mark as in use for this insn the reload regs we use
5115 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5116 rld[r].when_needed, rld[r].mode);
5118 rld[r].reg_rtx = reg;
5119 reload_spill_index[r] = spill_regs[i];
5126 /* Find a spill register to use as a reload register for reload R.
5127 LAST_RELOAD is nonzero if this is the last reload for the insn being
5130 Set rld[R].reg_rtx to the register allocated.
5132 We return 1 if successful, or 0 if we couldn't find a spill reg and
5133 we didn't change anything. */
5136 allocate_reload_reg (chain, r, last_reload)
5137 struct insn_chain *chain ATTRIBUTE_UNUSED;
5143 /* If we put this reload ahead, thinking it is a group,
5144 then insist on finding a group. Otherwise we can grab a
5145 reg that some other reload needs.
5146 (That can happen when we have a 68000 DATA_OR_FP_REG
5147 which is a group of data regs or one fp reg.)
5148 We need not be so restrictive if there are no more reloads
5151 ??? Really it would be nicer to have smarter handling
5152 for that kind of reg class, where a problem like this is normal.
5153 Perhaps those classes should be avoided for reloading
5154 by use of more alternatives. */
5156 int force_group = rld[r].nregs > 1 && ! last_reload;
5158 /* If we want a single register and haven't yet found one,
5159 take any reg in the right class and not in use.
5160 If we want a consecutive group, here is where we look for it.
5162 We use two passes so we can first look for reload regs to
5163 reuse, which are already in use for other reloads in this insn,
5164 and only then use additional registers.
5165 I think that maximizing reuse is needed to make sure we don't
5166 run out of reload regs. Suppose we have three reloads, and
5167 reloads A and B can share regs. These need two regs.
5168 Suppose A and B are given different regs.
5169 That leaves none for C. */
5170 for (pass = 0; pass < 2; pass++)
5172 /* I is the index in spill_regs.
5173 We advance it round-robin between insns to use all spill regs
5174 equally, so that inherited reloads have a chance
5175 of leapfrogging each other. */
5179 for (count = 0; count < n_spills; count++)
5181 int class = (int) rld[r].class;
5187 regnum = spill_regs[i];
5189 if ((reload_reg_free_p (regnum, rld[r].opnum,
5192 /* We check reload_reg_used to make sure we
5193 don't clobber the return register. */
5194 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5195 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5196 rld[r].when_needed, rld[r].in,
5198 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5199 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5200 /* Look first for regs to share, then for unshared. But
5201 don't share regs used for inherited reloads; they are
5202 the ones we want to preserve. */
5204 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5206 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5209 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5210 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5211 (on 68000) got us two FP regs. If NR is 1,
5212 we would reject both of them. */
5215 /* If we need only one reg, we have already won. */
5218 /* But reject a single reg if we demand a group. */
5223 /* Otherwise check that as many consecutive regs as we need
5224 are available here. */
5227 int regno = regnum + nr - 1;
5228 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5229 && spill_reg_order[regno] >= 0
5230 && reload_reg_free_p (regno, rld[r].opnum,
5231 rld[r].when_needed)))
5240 /* If we found something on pass 1, omit pass 2. */
5241 if (count < n_spills)
5245 /* We should have found a spill register by now. */
5246 if (count >= n_spills)
5249 /* I is the index in SPILL_REG_RTX of the reload register we are to
5250 allocate. Get an rtx for it and find its register number. */
5252 return set_reload_reg (i, r);
5255 /* Initialize all the tables needed to allocate reload registers.
5256 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5257 is the array we use to restore the reg_rtx field for every reload. */
5260 choose_reload_regs_init (chain, save_reload_reg_rtx)
5261 struct insn_chain *chain;
5262 rtx *save_reload_reg_rtx;
5266 for (i = 0; i < n_reloads; i++)
5267 rld[i].reg_rtx = save_reload_reg_rtx[i];
5269 memset (reload_inherited, 0, MAX_RELOADS);
5270 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5271 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5273 CLEAR_HARD_REG_SET (reload_reg_used);
5274 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5275 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5276 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5277 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5278 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5280 CLEAR_HARD_REG_SET (reg_used_in_insn);
5283 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5284 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5285 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5286 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5287 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5288 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5291 for (i = 0; i < reload_n_operands; i++)
5293 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5294 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5295 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5296 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5297 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5298 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5301 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5303 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5305 for (i = 0; i < n_reloads; i++)
5306 /* If we have already decided to use a certain register,
5307 don't use it in another way. */
5309 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5310 rld[i].when_needed, rld[i].mode);
5313 /* Assign hard reg targets for the pseudo-registers we must reload
5314 into hard regs for this insn.
5315 Also output the instructions to copy them in and out of the hard regs.
5317 For machines with register classes, we are responsible for
5318 finding a reload reg in the proper class. */
5321 choose_reload_regs (chain)
5322 struct insn_chain *chain;
5324 rtx insn = chain->insn;
5326 unsigned int max_group_size = 1;
5327 enum reg_class group_class = NO_REGS;
5328 int pass, win, inheritance;
5330 rtx save_reload_reg_rtx[MAX_RELOADS];
5332 /* In order to be certain of getting the registers we need,
5333 we must sort the reloads into order of increasing register class.
5334 Then our grabbing of reload registers will parallel the process
5335 that provided the reload registers.
5337 Also note whether any of the reloads wants a consecutive group of regs.
5338 If so, record the maximum size of the group desired and what
5339 register class contains all the groups needed by this insn. */
5341 for (j = 0; j < n_reloads; j++)
5343 reload_order[j] = j;
5344 reload_spill_index[j] = -1;
5346 if (rld[j].nregs > 1)
5348 max_group_size = MAX (rld[j].nregs, max_group_size);
5350 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5353 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5357 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5359 /* If -O, try first with inheritance, then turning it off.
5360 If not -O, don't do inheritance.
5361 Using inheritance when not optimizing leads to paradoxes
5362 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5363 because one side of the comparison might be inherited. */
5365 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5367 choose_reload_regs_init (chain, save_reload_reg_rtx);
5369 /* Process the reloads in order of preference just found.
5370 Beyond this point, subregs can be found in reload_reg_rtx.
5372 This used to look for an existing reloaded home for all of the
5373 reloads, and only then perform any new reloads. But that could lose
5374 if the reloads were done out of reg-class order because a later
5375 reload with a looser constraint might have an old home in a register
5376 needed by an earlier reload with a tighter constraint.
5378 To solve this, we make two passes over the reloads, in the order
5379 described above. In the first pass we try to inherit a reload
5380 from a previous insn. If there is a later reload that needs a
5381 class that is a proper subset of the class being processed, we must
5382 also allocate a spill register during the first pass.
5384 Then make a second pass over the reloads to allocate any reloads
5385 that haven't been given registers yet. */
5387 for (j = 0; j < n_reloads; j++)
5389 int r = reload_order[j];
5390 rtx search_equiv = NULL_RTX;
5392 /* Ignore reloads that got marked inoperative. */
5393 if (rld[r].out == 0 && rld[r].in == 0
5394 && ! rld[r].secondary_p)
5397 /* If find_reloads chose to use reload_in or reload_out as a reload
5398 register, we don't need to chose one. Otherwise, try even if it
5399 found one since we might save an insn if we find the value lying
5401 Try also when reload_in is a pseudo without a hard reg. */
5402 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5403 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5404 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5405 && GET_CODE (rld[r].in) != MEM
5406 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5409 #if 0 /* No longer needed for correct operation.
5410 It might give better code, or might not; worth an experiment? */
5411 /* If this is an optional reload, we can't inherit from earlier insns
5412 until we are sure that any non-optional reloads have been allocated.
5413 The following code takes advantage of the fact that optional reloads
5414 are at the end of reload_order. */
5415 if (rld[r].optional != 0)
5416 for (i = 0; i < j; i++)
5417 if ((rld[reload_order[i]].out != 0
5418 || rld[reload_order[i]].in != 0
5419 || rld[reload_order[i]].secondary_p)
5420 && ! rld[reload_order[i]].optional
5421 && rld[reload_order[i]].reg_rtx == 0)
5422 allocate_reload_reg (chain, reload_order[i], 0);
5425 /* First see if this pseudo is already available as reloaded
5426 for a previous insn. We cannot try to inherit for reloads
5427 that are smaller than the maximum number of registers needed
5428 for groups unless the register we would allocate cannot be used
5431 We could check here to see if this is a secondary reload for
5432 an object that is already in a register of the desired class.
5433 This would avoid the need for the secondary reload register.
5434 But this is complex because we can't easily determine what
5435 objects might want to be loaded via this reload. So let a
5436 register be allocated here. In `emit_reload_insns' we suppress
5437 one of the loads in the case described above. */
5443 enum machine_mode mode = VOIDmode;
5447 else if (GET_CODE (rld[r].in) == REG)
5449 regno = REGNO (rld[r].in);
5450 mode = GET_MODE (rld[r].in);
5452 else if (GET_CODE (rld[r].in_reg) == REG)
5454 regno = REGNO (rld[r].in_reg);
5455 mode = GET_MODE (rld[r].in_reg);
5457 else if (GET_CODE (rld[r].in_reg) == SUBREG
5458 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5460 byte = SUBREG_BYTE (rld[r].in_reg);
5461 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5462 if (regno < FIRST_PSEUDO_REGISTER)
5463 regno = subreg_regno (rld[r].in_reg);
5464 mode = GET_MODE (rld[r].in_reg);
5467 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5468 || GET_CODE (rld[r].in_reg) == PRE_DEC
5469 || GET_CODE (rld[r].in_reg) == POST_INC
5470 || GET_CODE (rld[r].in_reg) == POST_DEC)
5471 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5473 regno = REGNO (XEXP (rld[r].in_reg, 0));
5474 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5475 rld[r].out = rld[r].in;
5479 /* This won't work, since REGNO can be a pseudo reg number.
5480 Also, it takes much more hair to keep track of all the things
5481 that can invalidate an inherited reload of part of a pseudoreg. */
5482 else if (GET_CODE (rld[r].in) == SUBREG
5483 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5484 regno = subreg_regno (rld[r].in);
5487 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5489 enum reg_class class = rld[r].class, last_class;
5490 rtx last_reg = reg_last_reload_reg[regno];
5491 enum machine_mode need_mode;
5493 i = REGNO (last_reg);
5494 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5495 last_class = REGNO_REG_CLASS (i);
5501 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5502 GET_MODE_CLASS (mode));
5505 #ifdef CANNOT_CHANGE_MODE_CLASS
5506 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5510 (GET_MODE_SIZE (GET_MODE (last_reg))
5511 >= GET_MODE_SIZE (need_mode))
5512 #ifdef CANNOT_CHANGE_MODE_CLASS
5515 && reg_reloaded_contents[i] == regno
5516 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5517 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5518 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5519 /* Even if we can't use this register as a reload
5520 register, we might use it for reload_override_in,
5521 if copying it to the desired class is cheap
5523 || ((REGISTER_MOVE_COST (mode, last_class, class)
5524 < MEMORY_MOVE_COST (mode, class, 1))
5525 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5526 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5530 #ifdef SECONDARY_MEMORY_NEEDED
5531 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5536 && (rld[r].nregs == max_group_size
5537 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5539 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5540 rld[r].when_needed, rld[r].in,
5543 /* If a group is needed, verify that all the subsequent
5544 registers still have their values intact. */
5545 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5548 for (k = 1; k < nr; k++)
5549 if (reg_reloaded_contents[i + k] != regno
5550 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5558 last_reg = (GET_MODE (last_reg) == mode
5559 ? last_reg : gen_rtx_REG (mode, i));
5562 for (k = 0; k < nr; k++)
5563 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5566 /* We found a register that contains the
5567 value we need. If this register is the
5568 same as an `earlyclobber' operand of the
5569 current insn, just mark it as a place to
5570 reload from since we can't use it as the
5571 reload register itself. */
5573 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5574 if (reg_overlap_mentioned_for_reload_p
5575 (reg_last_reload_reg[regno],
5576 reload_earlyclobbers[i1]))
5579 if (i1 != n_earlyclobbers
5580 || ! (free_for_value_p (i, rld[r].mode,
5582 rld[r].when_needed, rld[r].in,
5584 /* Don't use it if we'd clobber a pseudo reg. */
5585 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5587 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5588 /* Don't clobber the frame pointer. */
5589 || (i == HARD_FRAME_POINTER_REGNUM
5590 && frame_pointer_needed
5592 /* Don't really use the inherited spill reg
5593 if we need it wider than we've got it. */
5594 || (GET_MODE_SIZE (rld[r].mode)
5595 > GET_MODE_SIZE (mode))
5598 /* If find_reloads chose reload_out as reload
5599 register, stay with it - that leaves the
5600 inherited register for subsequent reloads. */
5601 || (rld[r].out && rld[r].reg_rtx
5602 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5604 if (! rld[r].optional)
5606 reload_override_in[r] = last_reg;
5607 reload_inheritance_insn[r]
5608 = reg_reloaded_insn[i];
5614 /* We can use this as a reload reg. */
5615 /* Mark the register as in use for this part of
5617 mark_reload_reg_in_use (i,
5621 rld[r].reg_rtx = last_reg;
5622 reload_inherited[r] = 1;
5623 reload_inheritance_insn[r]
5624 = reg_reloaded_insn[i];
5625 reload_spill_index[r] = i;
5626 for (k = 0; k < nr; k++)
5627 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5635 /* Here's another way to see if the value is already lying around. */
5638 && ! reload_inherited[r]
5640 && (CONSTANT_P (rld[r].in)
5641 || GET_CODE (rld[r].in) == PLUS
5642 || GET_CODE (rld[r].in) == REG
5643 || GET_CODE (rld[r].in) == MEM)
5644 && (rld[r].nregs == max_group_size
5645 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5646 search_equiv = rld[r].in;
5647 /* If this is an output reload from a simple move insn, look
5648 if an equivalence for the input is available. */
5649 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5651 rtx set = single_set (insn);
5654 && rtx_equal_p (rld[r].out, SET_DEST (set))
5655 && CONSTANT_P (SET_SRC (set)))
5656 search_equiv = SET_SRC (set);
5662 = find_equiv_reg (search_equiv, insn, rld[r].class,
5663 -1, NULL, 0, rld[r].mode);
5668 if (GET_CODE (equiv) == REG)
5669 regno = REGNO (equiv);
5670 else if (GET_CODE (equiv) == SUBREG)
5672 /* This must be a SUBREG of a hard register.
5673 Make a new REG since this might be used in an
5674 address and not all machines support SUBREGs
5676 regno = subreg_regno (equiv);
5677 equiv = gen_rtx_REG (rld[r].mode, regno);
5683 /* If we found a spill reg, reject it unless it is free
5684 and of the desired class. */
5688 int bad_for_class = 0;
5689 int max_regno = regno + rld[r].nregs;
5691 for (i = regno; i < max_regno; i++)
5693 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5695 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5700 && ! free_for_value_p (regno, rld[r].mode,
5701 rld[r].opnum, rld[r].when_needed,
5702 rld[r].in, rld[r].out, r, 1))
5707 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5710 /* We found a register that contains the value we need.
5711 If this register is the same as an `earlyclobber' operand
5712 of the current insn, just mark it as a place to reload from
5713 since we can't use it as the reload register itself. */
5716 for (i = 0; i < n_earlyclobbers; i++)
5717 if (reg_overlap_mentioned_for_reload_p (equiv,
5718 reload_earlyclobbers[i]))
5720 if (! rld[r].optional)
5721 reload_override_in[r] = equiv;
5726 /* If the equiv register we have found is explicitly clobbered
5727 in the current insn, it depends on the reload type if we
5728 can use it, use it for reload_override_in, or not at all.
5729 In particular, we then can't use EQUIV for a
5730 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5734 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5735 switch (rld[r].when_needed)
5737 case RELOAD_FOR_OTHER_ADDRESS:
5738 case RELOAD_FOR_INPADDR_ADDRESS:
5739 case RELOAD_FOR_INPUT_ADDRESS:
5740 case RELOAD_FOR_OPADDR_ADDR:
5743 case RELOAD_FOR_INPUT:
5744 case RELOAD_FOR_OPERAND_ADDRESS:
5745 if (! rld[r].optional)
5746 reload_override_in[r] = equiv;
5752 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5753 switch (rld[r].when_needed)
5755 case RELOAD_FOR_OTHER_ADDRESS:
5756 case RELOAD_FOR_INPADDR_ADDRESS:
5757 case RELOAD_FOR_INPUT_ADDRESS:
5758 case RELOAD_FOR_OPADDR_ADDR:
5759 case RELOAD_FOR_OPERAND_ADDRESS:
5760 case RELOAD_FOR_INPUT:
5763 if (! rld[r].optional)
5764 reload_override_in[r] = equiv;
5772 /* If we found an equivalent reg, say no code need be generated
5773 to load it, and use it as our reload reg. */
5775 && (regno != HARD_FRAME_POINTER_REGNUM
5776 || !frame_pointer_needed))
5778 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5780 rld[r].reg_rtx = equiv;
5781 reload_inherited[r] = 1;
5783 /* If reg_reloaded_valid is not set for this register,
5784 there might be a stale spill_reg_store lying around.
5785 We must clear it, since otherwise emit_reload_insns
5786 might delete the store. */
5787 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5788 spill_reg_store[regno] = NULL_RTX;
5789 /* If any of the hard registers in EQUIV are spill
5790 registers, mark them as in use for this insn. */
5791 for (k = 0; k < nr; k++)
5793 i = spill_reg_order[regno + k];
5796 mark_reload_reg_in_use (regno, rld[r].opnum,
5799 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5806 /* If we found a register to use already, or if this is an optional
5807 reload, we are done. */
5808 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5812 /* No longer needed for correct operation. Might or might
5813 not give better code on the average. Want to experiment? */
5815 /* See if there is a later reload that has a class different from our
5816 class that intersects our class or that requires less register
5817 than our reload. If so, we must allocate a register to this
5818 reload now, since that reload might inherit a previous reload
5819 and take the only available register in our class. Don't do this
5820 for optional reloads since they will force all previous reloads
5821 to be allocated. Also don't do this for reloads that have been
5824 for (i = j + 1; i < n_reloads; i++)
5826 int s = reload_order[i];
5828 if ((rld[s].in == 0 && rld[s].out == 0
5829 && ! rld[s].secondary_p)
5833 if ((rld[s].class != rld[r].class
5834 && reg_classes_intersect_p (rld[r].class,
5836 || rld[s].nregs < rld[r].nregs)
5843 allocate_reload_reg (chain, r, j == n_reloads - 1);
5847 /* Now allocate reload registers for anything non-optional that
5848 didn't get one yet. */
5849 for (j = 0; j < n_reloads; j++)
5851 int r = reload_order[j];
5853 /* Ignore reloads that got marked inoperative. */
5854 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5857 /* Skip reloads that already have a register allocated or are
5859 if (rld[r].reg_rtx != 0 || rld[r].optional)
5862 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5866 /* If that loop got all the way, we have won. */
5873 /* Loop around and try without any inheritance. */
5878 /* First undo everything done by the failed attempt
5879 to allocate with inheritance. */
5880 choose_reload_regs_init (chain, save_reload_reg_rtx);
5882 /* Some sanity tests to verify that the reloads found in the first
5883 pass are identical to the ones we have now. */
5884 if (chain->n_reloads != n_reloads)
5887 for (i = 0; i < n_reloads; i++)
5889 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5891 if (chain->rld[i].when_needed != rld[i].when_needed)
5893 for (j = 0; j < n_spills; j++)
5894 if (spill_regs[j] == chain->rld[i].regno)
5895 if (! set_reload_reg (j, i))
5896 failed_reload (chain->insn, i);
5900 /* If we thought we could inherit a reload, because it seemed that
5901 nothing else wanted the same reload register earlier in the insn,
5902 verify that assumption, now that all reloads have been assigned.
5903 Likewise for reloads where reload_override_in has been set. */
5905 /* If doing expensive optimizations, do one preliminary pass that doesn't
5906 cancel any inheritance, but removes reloads that have been needed only
5907 for reloads that we know can be inherited. */
5908 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5910 for (j = 0; j < n_reloads; j++)
5912 int r = reload_order[j];
5914 if (reload_inherited[r] && rld[r].reg_rtx)
5915 check_reg = rld[r].reg_rtx;
5916 else if (reload_override_in[r]
5917 && (GET_CODE (reload_override_in[r]) == REG
5918 || GET_CODE (reload_override_in[r]) == SUBREG))
5919 check_reg = reload_override_in[r];
5922 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5923 rld[r].opnum, rld[r].when_needed, rld[r].in,
5924 (reload_inherited[r]
5925 ? rld[r].out : const0_rtx),
5930 reload_inherited[r] = 0;
5931 reload_override_in[r] = 0;
5933 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5934 reload_override_in, then we do not need its related
5935 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5936 likewise for other reload types.
5937 We handle this by removing a reload when its only replacement
5938 is mentioned in reload_in of the reload we are going to inherit.
5939 A special case are auto_inc expressions; even if the input is
5940 inherited, we still need the address for the output. We can
5941 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5942 If we succeeded removing some reload and we are doing a preliminary
5943 pass just to remove such reloads, make another pass, since the
5944 removal of one reload might allow us to inherit another one. */
5946 && rld[r].out != rld[r].in
5947 && remove_address_replacements (rld[r].in) && pass)
5952 /* Now that reload_override_in is known valid,
5953 actually override reload_in. */
5954 for (j = 0; j < n_reloads; j++)
5955 if (reload_override_in[j])
5956 rld[j].in = reload_override_in[j];
5958 /* If this reload won't be done because it has been canceled or is
5959 optional and not inherited, clear reload_reg_rtx so other
5960 routines (such as subst_reloads) don't get confused. */
5961 for (j = 0; j < n_reloads; j++)
5962 if (rld[j].reg_rtx != 0
5963 && ((rld[j].optional && ! reload_inherited[j])
5964 || (rld[j].in == 0 && rld[j].out == 0
5965 && ! rld[j].secondary_p)))
5967 int regno = true_regnum (rld[j].reg_rtx);
5969 if (spill_reg_order[regno] >= 0)
5970 clear_reload_reg_in_use (regno, rld[j].opnum,
5971 rld[j].when_needed, rld[j].mode);
5973 reload_spill_index[j] = -1;
5976 /* Record which pseudos and which spill regs have output reloads. */
5977 for (j = 0; j < n_reloads; j++)
5979 int r = reload_order[j];
5981 i = reload_spill_index[r];
5983 /* I is nonneg if this reload uses a register.
5984 If rld[r].reg_rtx is 0, this is an optional reload
5985 that we opted to ignore. */
5986 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5987 && rld[r].reg_rtx != 0)
5989 int nregno = REGNO (rld[r].out_reg);
5992 if (nregno < FIRST_PSEUDO_REGISTER)
5993 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5996 reg_has_output_reload[nregno + nr] = 1;
6000 nr = HARD_REGNO_NREGS (i, rld[r].mode);
6002 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6005 if (rld[r].when_needed != RELOAD_OTHER
6006 && rld[r].when_needed != RELOAD_FOR_OUTPUT
6007 && rld[r].when_needed != RELOAD_FOR_INSN)
6013 /* Deallocate the reload register for reload R. This is called from
6014 remove_address_replacements. */
6017 deallocate_reload_reg (r)
6022 if (! rld[r].reg_rtx)
6024 regno = true_regnum (rld[r].reg_rtx);
6026 if (spill_reg_order[regno] >= 0)
6027 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6029 reload_spill_index[r] = -1;
6032 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6033 reloads of the same item for fear that we might not have enough reload
6034 registers. However, normally they will get the same reload register
6035 and hence actually need not be loaded twice.
6037 Here we check for the most common case of this phenomenon: when we have
6038 a number of reloads for the same object, each of which were allocated
6039 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6040 reload, and is not modified in the insn itself. If we find such,
6041 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6042 This will not increase the number of spill registers needed and will
6043 prevent redundant code. */
6046 merge_assigned_reloads (insn)
6051 /* Scan all the reloads looking for ones that only load values and
6052 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6053 assigned and not modified by INSN. */
6055 for (i = 0; i < n_reloads; i++)
6057 int conflicting_input = 0;
6058 int max_input_address_opnum = -1;
6059 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6061 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6062 || rld[i].out != 0 || rld[i].reg_rtx == 0
6063 || reg_set_p (rld[i].reg_rtx, insn))
6066 /* Look at all other reloads. Ensure that the only use of this
6067 reload_reg_rtx is in a reload that just loads the same value
6068 as we do. Note that any secondary reloads must be of the identical
6069 class since the values, modes, and result registers are the
6070 same, so we need not do anything with any secondary reloads. */
6072 for (j = 0; j < n_reloads; j++)
6074 if (i == j || rld[j].reg_rtx == 0
6075 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6079 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6080 && rld[j].opnum > max_input_address_opnum)
6081 max_input_address_opnum = rld[j].opnum;
6083 /* If the reload regs aren't exactly the same (e.g, different modes)
6084 or if the values are different, we can't merge this reload.
6085 But if it is an input reload, we might still merge
6086 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6088 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6089 || rld[j].out != 0 || rld[j].in == 0
6090 || ! rtx_equal_p (rld[i].in, rld[j].in))
6092 if (rld[j].when_needed != RELOAD_FOR_INPUT
6093 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6094 || rld[i].opnum > rld[j].opnum)
6095 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6097 conflicting_input = 1;
6098 if (min_conflicting_input_opnum > rld[j].opnum)
6099 min_conflicting_input_opnum = rld[j].opnum;
6103 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6104 we, in fact, found any matching reloads. */
6107 && max_input_address_opnum <= min_conflicting_input_opnum)
6109 for (j = 0; j < n_reloads; j++)
6110 if (i != j && rld[j].reg_rtx != 0
6111 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6112 && (! conflicting_input
6113 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6114 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6116 rld[i].when_needed = RELOAD_OTHER;
6118 reload_spill_index[j] = -1;
6119 transfer_replacements (i, j);
6122 /* If this is now RELOAD_OTHER, look for any reloads that load
6123 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6124 if they were for inputs, RELOAD_OTHER for outputs. Note that
6125 this test is equivalent to looking for reloads for this operand
6127 /* We must take special care when there are two or more reloads to
6128 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6129 same value or a part of it; we must not change its type if there
6130 is a conflicting input. */
6132 if (rld[i].when_needed == RELOAD_OTHER)
6133 for (j = 0; j < n_reloads; j++)
6135 && rld[j].when_needed != RELOAD_OTHER
6136 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6137 && (! conflicting_input
6138 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6139 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6140 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6146 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6147 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6148 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6150 /* Check to see if we accidentally converted two reloads
6151 that use the same reload register with different inputs
6152 to the same type. If so, the resulting code won't work,
6155 for (k = 0; k < j; k++)
6156 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6157 && rld[k].when_needed == rld[j].when_needed
6158 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6159 && ! rtx_equal_p (rld[k].in, rld[j].in))
6166 /* These arrays are filled by emit_reload_insns and its subroutines. */
6167 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6168 static rtx other_input_address_reload_insns = 0;
6169 static rtx other_input_reload_insns = 0;
6170 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6171 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6172 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6173 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6174 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6175 static rtx operand_reload_insns = 0;
6176 static rtx other_operand_reload_insns = 0;
6177 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6179 /* Values to be put in spill_reg_store are put here first. */
6180 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6181 static HARD_REG_SET reg_reloaded_died;
6183 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6184 has the number J. OLD contains the value to be used as input. */
6187 emit_input_reload_insns (chain, rl, old, j)
6188 struct insn_chain *chain;
6193 rtx insn = chain->insn;
6194 rtx reloadreg = rl->reg_rtx;
6195 rtx oldequiv_reg = 0;
6198 enum machine_mode mode;
6201 /* Determine the mode to reload in.
6202 This is very tricky because we have three to choose from.
6203 There is the mode the insn operand wants (rl->inmode).
6204 There is the mode of the reload register RELOADREG.
6205 There is the intrinsic mode of the operand, which we could find
6206 by stripping some SUBREGs.
6207 It turns out that RELOADREG's mode is irrelevant:
6208 we can change that arbitrarily.
6210 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6211 then the reload reg may not support QImode moves, so use SImode.
6212 If foo is in memory due to spilling a pseudo reg, this is safe,
6213 because the QImode value is in the least significant part of a
6214 slot big enough for a SImode. If foo is some other sort of
6215 memory reference, then it is impossible to reload this case,
6216 so previous passes had better make sure this never happens.
6218 Then consider a one-word union which has SImode and one of its
6219 members is a float, being fetched as (SUBREG:SF union:SI).
6220 We must fetch that as SFmode because we could be loading into
6221 a float-only register. In this case OLD's mode is correct.
6223 Consider an immediate integer: it has VOIDmode. Here we need
6224 to get a mode from something else.
6226 In some cases, there is a fourth mode, the operand's
6227 containing mode. If the insn specifies a containing mode for
6228 this operand, it overrides all others.
6230 I am not sure whether the algorithm here is always right,
6231 but it does the right things in those cases. */
6233 mode = GET_MODE (old);
6234 if (mode == VOIDmode)
6237 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6238 /* If we need a secondary register for this operation, see if
6239 the value is already in a register in that class. Don't
6240 do this if the secondary register will be used as a scratch
6243 if (rl->secondary_in_reload >= 0
6244 && rl->secondary_in_icode == CODE_FOR_nothing
6247 = find_equiv_reg (old, insn,
6248 rld[rl->secondary_in_reload].class,
6252 /* If reloading from memory, see if there is a register
6253 that already holds the same value. If so, reload from there.
6254 We can pass 0 as the reload_reg_p argument because
6255 any other reload has either already been emitted,
6256 in which case find_equiv_reg will see the reload-insn,
6257 or has yet to be emitted, in which case it doesn't matter
6258 because we will use this equiv reg right away. */
6260 if (oldequiv == 0 && optimize
6261 && (GET_CODE (old) == MEM
6262 || (GET_CODE (old) == REG
6263 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6264 && reg_renumber[REGNO (old)] < 0)))
6265 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6269 unsigned int regno = true_regnum (oldequiv);
6271 /* Don't use OLDEQUIV if any other reload changes it at an
6272 earlier stage of this insn or at this stage. */
6273 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6274 rl->in, const0_rtx, j, 0))
6277 /* If it is no cheaper to copy from OLDEQUIV into the
6278 reload register than it would be to move from memory,
6279 don't use it. Likewise, if we need a secondary register
6283 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6284 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6286 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6287 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6288 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6292 #ifdef SECONDARY_MEMORY_NEEDED
6293 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6301 /* delete_output_reload is only invoked properly if old contains
6302 the original pseudo register. Since this is replaced with a
6303 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6304 find the pseudo in RELOAD_IN_REG. */
6306 && reload_override_in[j]
6307 && GET_CODE (rl->in_reg) == REG)
6314 else if (GET_CODE (oldequiv) == REG)
6315 oldequiv_reg = oldequiv;
6316 else if (GET_CODE (oldequiv) == SUBREG)
6317 oldequiv_reg = SUBREG_REG (oldequiv);
6319 /* If we are reloading from a register that was recently stored in
6320 with an output-reload, see if we can prove there was
6321 actually no need to store the old value in it. */
6323 if (optimize && GET_CODE (oldequiv) == REG
6324 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6325 && spill_reg_store[REGNO (oldequiv)]
6326 && GET_CODE (old) == REG
6327 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6328 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6330 delete_output_reload (insn, j, REGNO (oldequiv));
6332 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6333 then load RELOADREG from OLDEQUIV. Note that we cannot use
6334 gen_lowpart_common since it can do the wrong thing when
6335 RELOADREG has a multi-word mode. Note that RELOADREG
6336 must always be a REG here. */
6338 if (GET_MODE (reloadreg) != mode)
6339 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6340 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6341 oldequiv = SUBREG_REG (oldequiv);
6342 if (GET_MODE (oldequiv) != VOIDmode
6343 && mode != GET_MODE (oldequiv))
6344 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6346 /* Switch to the right place to emit the reload insns. */
6347 switch (rl->when_needed)
6350 where = &other_input_reload_insns;
6352 case RELOAD_FOR_INPUT:
6353 where = &input_reload_insns[rl->opnum];
6355 case RELOAD_FOR_INPUT_ADDRESS:
6356 where = &input_address_reload_insns[rl->opnum];
6358 case RELOAD_FOR_INPADDR_ADDRESS:
6359 where = &inpaddr_address_reload_insns[rl->opnum];
6361 case RELOAD_FOR_OUTPUT_ADDRESS:
6362 where = &output_address_reload_insns[rl->opnum];
6364 case RELOAD_FOR_OUTADDR_ADDRESS:
6365 where = &outaddr_address_reload_insns[rl->opnum];
6367 case RELOAD_FOR_OPERAND_ADDRESS:
6368 where = &operand_reload_insns;
6370 case RELOAD_FOR_OPADDR_ADDR:
6371 where = &other_operand_reload_insns;
6373 case RELOAD_FOR_OTHER_ADDRESS:
6374 where = &other_input_address_reload_insns;
6380 push_to_sequence (*where);
6382 /* Auto-increment addresses must be reloaded in a special way. */
6383 if (rl->out && ! rl->out_reg)
6385 /* We are not going to bother supporting the case where a
6386 incremented register can't be copied directly from
6387 OLDEQUIV since this seems highly unlikely. */
6388 if (rl->secondary_in_reload >= 0)
6391 if (reload_inherited[j])
6392 oldequiv = reloadreg;
6394 old = XEXP (rl->in_reg, 0);
6396 if (optimize && GET_CODE (oldequiv) == REG
6397 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6398 && spill_reg_store[REGNO (oldequiv)]
6399 && GET_CODE (old) == REG
6400 && (dead_or_set_p (insn,
6401 spill_reg_stored_to[REGNO (oldequiv)])
6402 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6404 delete_output_reload (insn, j, REGNO (oldequiv));
6406 /* Prevent normal processing of this reload. */
6408 /* Output a special code sequence for this case. */
6409 new_spill_reg_store[REGNO (reloadreg)]
6410 = inc_for_reload (reloadreg, oldequiv, rl->out,
6414 /* If we are reloading a pseudo-register that was set by the previous
6415 insn, see if we can get rid of that pseudo-register entirely
6416 by redirecting the previous insn into our reload register. */
6418 else if (optimize && GET_CODE (old) == REG
6419 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6420 && dead_or_set_p (insn, old)
6421 /* This is unsafe if some other reload
6422 uses the same reg first. */
6423 && ! conflicts_with_override (reloadreg)
6424 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6425 rl->when_needed, old, rl->out, j, 0))
6427 rtx temp = PREV_INSN (insn);
6428 while (temp && GET_CODE (temp) == NOTE)
6429 temp = PREV_INSN (temp);
6431 && GET_CODE (temp) == INSN
6432 && GET_CODE (PATTERN (temp)) == SET
6433 && SET_DEST (PATTERN (temp)) == old
6434 /* Make sure we can access insn_operand_constraint. */
6435 && asm_noperands (PATTERN (temp)) < 0
6436 /* This is unsafe if operand occurs more than once in current
6437 insn. Perhaps some occurrences aren't reloaded. */
6438 && count_occurrences (PATTERN (insn), old, 0) == 1)
6440 rtx old = SET_DEST (PATTERN (temp));
6441 /* Store into the reload register instead of the pseudo. */
6442 SET_DEST (PATTERN (temp)) = reloadreg;
6444 /* Verify that resulting insn is valid. */
6445 extract_insn (temp);
6446 if (constrain_operands (1))
6448 /* If the previous insn is an output reload, the source is
6449 a reload register, and its spill_reg_store entry will
6450 contain the previous destination. This is now
6452 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6453 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6455 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6456 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6459 /* If these are the only uses of the pseudo reg,
6460 pretend for GDB it lives in the reload reg we used. */
6461 if (REG_N_DEATHS (REGNO (old)) == 1
6462 && REG_N_SETS (REGNO (old)) == 1)
6464 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6465 alter_reg (REGNO (old), -1);
6471 SET_DEST (PATTERN (temp)) = old;
6476 /* We can't do that, so output an insn to load RELOADREG. */
6478 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6479 /* If we have a secondary reload, pick up the secondary register
6480 and icode, if any. If OLDEQUIV and OLD are different or
6481 if this is an in-out reload, recompute whether or not we
6482 still need a secondary register and what the icode should
6483 be. If we still need a secondary register and the class or
6484 icode is different, go back to reloading from OLD if using
6485 OLDEQUIV means that we got the wrong type of register. We
6486 cannot have different class or icode due to an in-out reload
6487 because we don't make such reloads when both the input and
6488 output need secondary reload registers. */
6490 if (! special && rl->secondary_in_reload >= 0)
6492 rtx second_reload_reg = 0;
6493 int secondary_reload = rl->secondary_in_reload;
6494 rtx real_oldequiv = oldequiv;
6497 enum insn_code icode;
6499 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6500 and similarly for OLD.
6501 See comments in get_secondary_reload in reload.c. */
6502 /* If it is a pseudo that cannot be replaced with its
6503 equivalent MEM, we must fall back to reload_in, which
6504 will have all the necessary substitutions registered.
6505 Likewise for a pseudo that can't be replaced with its
6506 equivalent constant.
6508 Take extra care for subregs of such pseudos. Note that
6509 we cannot use reg_equiv_mem in this case because it is
6510 not in the right mode. */
6513 if (GET_CODE (tmp) == SUBREG)
6514 tmp = SUBREG_REG (tmp);
6515 if (GET_CODE (tmp) == REG
6516 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6517 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6518 || reg_equiv_constant[REGNO (tmp)] != 0))
6520 if (! reg_equiv_mem[REGNO (tmp)]
6521 || num_not_at_initial_offset
6522 || GET_CODE (oldequiv) == SUBREG)
6523 real_oldequiv = rl->in;
6525 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6529 if (GET_CODE (tmp) == SUBREG)
6530 tmp = SUBREG_REG (tmp);
6531 if (GET_CODE (tmp) == REG
6532 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6533 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6534 || reg_equiv_constant[REGNO (tmp)] != 0))
6536 if (! reg_equiv_mem[REGNO (tmp)]
6537 || num_not_at_initial_offset
6538 || GET_CODE (old) == SUBREG)
6541 real_old = reg_equiv_mem[REGNO (tmp)];
6544 second_reload_reg = rld[secondary_reload].reg_rtx;
6545 icode = rl->secondary_in_icode;
6547 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6548 || (rl->in != 0 && rl->out != 0))
6550 enum reg_class new_class
6551 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6552 mode, real_oldequiv);
6554 if (new_class == NO_REGS)
6555 second_reload_reg = 0;
6558 enum insn_code new_icode;
6559 enum machine_mode new_mode;
6561 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6562 REGNO (second_reload_reg)))
6563 oldequiv = old, real_oldequiv = real_old;
6566 new_icode = reload_in_optab[(int) mode];
6567 if (new_icode != CODE_FOR_nothing
6568 && ((insn_data[(int) new_icode].operand[0].predicate
6569 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6571 || (insn_data[(int) new_icode].operand[1].predicate
6572 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6573 (real_oldequiv, mode)))))
6574 new_icode = CODE_FOR_nothing;
6576 if (new_icode == CODE_FOR_nothing)
6579 new_mode = insn_data[(int) new_icode].operand[2].mode;
6581 if (GET_MODE (second_reload_reg) != new_mode)
6583 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6585 oldequiv = old, real_oldequiv = real_old;
6588 = reload_adjust_reg_for_mode (second_reload_reg,
6595 /* If we still need a secondary reload register, check
6596 to see if it is being used as a scratch or intermediate
6597 register and generate code appropriately. If we need
6598 a scratch register, use REAL_OLDEQUIV since the form of
6599 the insn may depend on the actual address if it is
6602 if (second_reload_reg)
6604 if (icode != CODE_FOR_nothing)
6606 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6607 second_reload_reg));
6612 /* See if we need a scratch register to load the
6613 intermediate register (a tertiary reload). */
6614 enum insn_code tertiary_icode
6615 = rld[secondary_reload].secondary_in_icode;
6617 if (tertiary_icode != CODE_FOR_nothing)
6619 rtx third_reload_reg
6620 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6622 emit_insn ((GEN_FCN (tertiary_icode)
6623 (second_reload_reg, real_oldequiv,
6624 third_reload_reg)));
6627 gen_reload (second_reload_reg, real_oldequiv,
6631 oldequiv = second_reload_reg;
6637 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6639 rtx real_oldequiv = oldequiv;
6641 if ((GET_CODE (oldequiv) == REG
6642 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6643 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6644 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6645 || (GET_CODE (oldequiv) == SUBREG
6646 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6647 && (REGNO (SUBREG_REG (oldequiv))
6648 >= FIRST_PSEUDO_REGISTER)
6649 && ((reg_equiv_memory_loc
6650 [REGNO (SUBREG_REG (oldequiv))] != 0)
6651 || (reg_equiv_constant
6652 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6653 || (CONSTANT_P (oldequiv)
6654 && (PREFERRED_RELOAD_CLASS (oldequiv,
6655 REGNO_REG_CLASS (REGNO (reloadreg)))
6657 real_oldequiv = rl->in;
6658 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6662 if (flag_non_call_exceptions)
6663 copy_eh_notes (insn, get_insns ());
6665 /* End this sequence. */
6666 *where = get_insns ();
6669 /* Update reload_override_in so that delete_address_reloads_1
6670 can see the actual register usage. */
6672 reload_override_in[j] = oldequiv;
6675 /* Generate insns to for the output reload RL, which is for the insn described
6676 by CHAIN and has the number J. */
6678 emit_output_reload_insns (chain, rl, j)
6679 struct insn_chain *chain;
6683 rtx reloadreg = rl->reg_rtx;
6684 rtx insn = chain->insn;
6687 enum machine_mode mode = GET_MODE (old);
6690 if (rl->when_needed == RELOAD_OTHER)
6693 push_to_sequence (output_reload_insns[rl->opnum]);
6695 /* Determine the mode to reload in.
6696 See comments above (for input reloading). */
6698 if (mode == VOIDmode)
6700 /* VOIDmode should never happen for an output. */
6701 if (asm_noperands (PATTERN (insn)) < 0)
6702 /* It's the compiler's fault. */
6703 fatal_insn ("VOIDmode on an output", insn);
6704 error_for_asm (insn, "output operand is constant in `asm'");
6705 /* Prevent crash--use something we know is valid. */
6707 old = gen_rtx_REG (mode, REGNO (reloadreg));
6710 if (GET_MODE (reloadreg) != mode)
6711 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6713 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6715 /* If we need two reload regs, set RELOADREG to the intermediate
6716 one, since it will be stored into OLD. We might need a secondary
6717 register only for an input reload, so check again here. */
6719 if (rl->secondary_out_reload >= 0)
6723 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6724 && reg_equiv_mem[REGNO (old)] != 0)
6725 real_old = reg_equiv_mem[REGNO (old)];
6727 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6731 rtx second_reloadreg = reloadreg;
6732 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6734 /* See if RELOADREG is to be used as a scratch register
6735 or as an intermediate register. */
6736 if (rl->secondary_out_icode != CODE_FOR_nothing)
6738 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6739 (real_old, second_reloadreg, reloadreg)));
6744 /* See if we need both a scratch and intermediate reload
6747 int secondary_reload = rl->secondary_out_reload;
6748 enum insn_code tertiary_icode
6749 = rld[secondary_reload].secondary_out_icode;
6751 if (GET_MODE (reloadreg) != mode)
6752 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6754 if (tertiary_icode != CODE_FOR_nothing)
6757 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6760 /* Copy primary reload reg to secondary reload reg.
6761 (Note that these have been swapped above, then
6762 secondary reload reg to OLD using our insn.) */
6764 /* If REAL_OLD is a paradoxical SUBREG, remove it
6765 and try to put the opposite SUBREG on
6767 if (GET_CODE (real_old) == SUBREG
6768 && (GET_MODE_SIZE (GET_MODE (real_old))
6769 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6770 && 0 != (tem = gen_lowpart_common
6771 (GET_MODE (SUBREG_REG (real_old)),
6773 real_old = SUBREG_REG (real_old), reloadreg = tem;
6775 gen_reload (reloadreg, second_reloadreg,
6776 rl->opnum, rl->when_needed);
6777 emit_insn ((GEN_FCN (tertiary_icode)
6778 (real_old, reloadreg, third_reloadreg)));
6783 /* Copy between the reload regs here and then to
6786 gen_reload (reloadreg, second_reloadreg,
6787 rl->opnum, rl->when_needed);
6793 /* Output the last reload insn. */
6798 /* Don't output the last reload if OLD is not the dest of
6799 INSN and is in the src and is clobbered by INSN. */
6800 if (! flag_expensive_optimizations
6801 || GET_CODE (old) != REG
6802 || !(set = single_set (insn))
6803 || rtx_equal_p (old, SET_DEST (set))
6804 || !reg_mentioned_p (old, SET_SRC (set))
6805 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6806 gen_reload (old, reloadreg, rl->opnum,
6810 /* Look at all insns we emitted, just to be safe. */
6811 for (p = get_insns (); p; p = NEXT_INSN (p))
6814 rtx pat = PATTERN (p);
6816 /* If this output reload doesn't come from a spill reg,
6817 clear any memory of reloaded copies of the pseudo reg.
6818 If this output reload comes from a spill reg,
6819 reg_has_output_reload will make this do nothing. */
6820 note_stores (pat, forget_old_reloads_1, NULL);
6822 if (reg_mentioned_p (rl->reg_rtx, pat))
6824 rtx set = single_set (insn);
6825 if (reload_spill_index[j] < 0
6827 && SET_SRC (set) == rl->reg_rtx)
6829 int src = REGNO (SET_SRC (set));
6831 reload_spill_index[j] = src;
6832 SET_HARD_REG_BIT (reg_is_output_reload, src);
6833 if (find_regno_note (insn, REG_DEAD, src))
6834 SET_HARD_REG_BIT (reg_reloaded_died, src);
6836 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6838 int s = rl->secondary_out_reload;
6839 set = single_set (p);
6840 /* If this reload copies only to the secondary reload
6841 register, the secondary reload does the actual
6843 if (s >= 0 && set == NULL_RTX)
6844 /* We can't tell what function the secondary reload
6845 has and where the actual store to the pseudo is
6846 made; leave new_spill_reg_store alone. */
6849 && SET_SRC (set) == rl->reg_rtx
6850 && SET_DEST (set) == rld[s].reg_rtx)
6852 /* Usually the next instruction will be the
6853 secondary reload insn; if we can confirm
6854 that it is, setting new_spill_reg_store to
6855 that insn will allow an extra optimization. */
6856 rtx s_reg = rld[s].reg_rtx;
6857 rtx next = NEXT_INSN (p);
6858 rld[s].out = rl->out;
6859 rld[s].out_reg = rl->out_reg;
6860 set = single_set (next);
6861 if (set && SET_SRC (set) == s_reg
6862 && ! new_spill_reg_store[REGNO (s_reg)])
6864 SET_HARD_REG_BIT (reg_is_output_reload,
6866 new_spill_reg_store[REGNO (s_reg)] = next;
6870 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6875 if (rl->when_needed == RELOAD_OTHER)
6877 emit_insn (other_output_reload_insns[rl->opnum]);
6878 other_output_reload_insns[rl->opnum] = get_insns ();
6881 output_reload_insns[rl->opnum] = get_insns ();
6883 if (flag_non_call_exceptions)
6884 copy_eh_notes (insn, get_insns ());
6889 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6890 and has the number J. */
6892 do_input_reload (chain, rl, j)
6893 struct insn_chain *chain;
6897 rtx insn = chain->insn;
6898 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6899 ? rl->in_reg : rl->in);
6902 /* AUTO_INC reloads need to be handled even if inherited. We got an
6903 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6904 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6905 && ! rtx_equal_p (rl->reg_rtx, old)
6906 && rl->reg_rtx != 0)
6907 emit_input_reload_insns (chain, rld + j, old, j);
6909 /* When inheriting a wider reload, we have a MEM in rl->in,
6910 e.g. inheriting a SImode output reload for
6911 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6912 if (optimize && reload_inherited[j] && rl->in
6913 && GET_CODE (rl->in) == MEM
6914 && GET_CODE (rl->in_reg) == MEM
6915 && reload_spill_index[j] >= 0
6916 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6917 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6919 /* If we are reloading a register that was recently stored in with an
6920 output-reload, see if we can prove there was
6921 actually no need to store the old value in it. */
6924 && (reload_inherited[j] || reload_override_in[j])
6926 && GET_CODE (rl->reg_rtx) == REG
6927 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6929 /* There doesn't seem to be any reason to restrict this to pseudos
6930 and doing so loses in the case where we are copying from a
6931 register of the wrong class. */
6932 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6933 >= FIRST_PSEUDO_REGISTER)
6935 /* The insn might have already some references to stackslots
6936 replaced by MEMs, while reload_out_reg still names the
6938 && (dead_or_set_p (insn,
6939 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6940 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6942 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6945 /* Do output reloading for reload RL, which is for the insn described by
6946 CHAIN and has the number J.
6947 ??? At some point we need to support handling output reloads of
6948 JUMP_INSNs or insns that set cc0. */
6950 do_output_reload (chain, rl, j)
6951 struct insn_chain *chain;
6956 rtx insn = chain->insn;
6957 /* If this is an output reload that stores something that is
6958 not loaded in this same reload, see if we can eliminate a previous
6960 rtx pseudo = rl->out_reg;
6964 && GET_CODE (pseudo) == REG
6965 && ! rtx_equal_p (rl->in_reg, pseudo)
6966 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6967 && reg_last_reload_reg[REGNO (pseudo)])
6969 int pseudo_no = REGNO (pseudo);
6970 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6972 /* We don't need to test full validity of last_regno for
6973 inherit here; we only want to know if the store actually
6974 matches the pseudo. */
6975 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6976 && reg_reloaded_contents[last_regno] == pseudo_no
6977 && spill_reg_store[last_regno]
6978 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6979 delete_output_reload (insn, j, last_regno);
6984 || rl->reg_rtx == old
6985 || rl->reg_rtx == 0)
6988 /* An output operand that dies right away does need a reload,
6989 but need not be copied from it. Show the new location in the
6991 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6992 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6994 XEXP (note, 0) = rl->reg_rtx;
6997 /* Likewise for a SUBREG of an operand that dies. */
6998 else if (GET_CODE (old) == SUBREG
6999 && GET_CODE (SUBREG_REG (old)) == REG
7000 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7003 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7007 else if (GET_CODE (old) == SCRATCH)
7008 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7009 but we don't want to make an output reload. */
7012 /* If is a JUMP_INSN, we can't support output reloads yet. */
7013 if (GET_CODE (insn) == JUMP_INSN)
7016 emit_output_reload_insns (chain, rld + j, j);
7019 /* Output insns to reload values in and out of the chosen reload regs. */
7022 emit_reload_insns (chain)
7023 struct insn_chain *chain;
7025 rtx insn = chain->insn;
7029 CLEAR_HARD_REG_SET (reg_reloaded_died);
7031 for (j = 0; j < reload_n_operands; j++)
7032 input_reload_insns[j] = input_address_reload_insns[j]
7033 = inpaddr_address_reload_insns[j]
7034 = output_reload_insns[j] = output_address_reload_insns[j]
7035 = outaddr_address_reload_insns[j]
7036 = other_output_reload_insns[j] = 0;
7037 other_input_address_reload_insns = 0;
7038 other_input_reload_insns = 0;
7039 operand_reload_insns = 0;
7040 other_operand_reload_insns = 0;
7042 /* Dump reloads into the dump file. */
7045 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7046 debug_reload_to_stream (rtl_dump_file);
7049 /* Now output the instructions to copy the data into and out of the
7050 reload registers. Do these in the order that the reloads were reported,
7051 since reloads of base and index registers precede reloads of operands
7052 and the operands may need the base and index registers reloaded. */
7054 for (j = 0; j < n_reloads; j++)
7057 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7058 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7060 do_input_reload (chain, rld + j, j);
7061 do_output_reload (chain, rld + j, j);
7064 /* Now write all the insns we made for reloads in the order expected by
7065 the allocation functions. Prior to the insn being reloaded, we write
7066 the following reloads:
7068 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7070 RELOAD_OTHER reloads.
7072 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7073 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7074 RELOAD_FOR_INPUT reload for the operand.
7076 RELOAD_FOR_OPADDR_ADDRS reloads.
7078 RELOAD_FOR_OPERAND_ADDRESS reloads.
7080 After the insn being reloaded, we write the following:
7082 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7083 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7084 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7085 reloads for the operand. The RELOAD_OTHER output reloads are
7086 output in descending order by reload number. */
7088 emit_insn_before (other_input_address_reload_insns, insn);
7089 emit_insn_before (other_input_reload_insns, insn);
7091 for (j = 0; j < reload_n_operands; j++)
7093 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7094 emit_insn_before (input_address_reload_insns[j], insn);
7095 emit_insn_before (input_reload_insns[j], insn);
7098 emit_insn_before (other_operand_reload_insns, insn);
7099 emit_insn_before (operand_reload_insns, insn);
7101 for (j = 0; j < reload_n_operands; j++)
7103 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7104 x = emit_insn_after (output_address_reload_insns[j], x);
7105 x = emit_insn_after (output_reload_insns[j], x);
7106 emit_insn_after (other_output_reload_insns[j], x);
7109 /* For all the spill regs newly reloaded in this instruction,
7110 record what they were reloaded from, so subsequent instructions
7111 can inherit the reloads.
7113 Update spill_reg_store for the reloads of this insn.
7114 Copy the elements that were updated in the loop above. */
7116 for (j = 0; j < n_reloads; j++)
7118 int r = reload_order[j];
7119 int i = reload_spill_index[r];
7121 /* If this is a non-inherited input reload from a pseudo, we must
7122 clear any memory of a previous store to the same pseudo. Only do
7123 something if there will not be an output reload for the pseudo
7125 if (rld[r].in_reg != 0
7126 && ! (reload_inherited[r] || reload_override_in[r]))
7128 rtx reg = rld[r].in_reg;
7130 if (GET_CODE (reg) == SUBREG)
7131 reg = SUBREG_REG (reg);
7133 if (GET_CODE (reg) == REG
7134 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7135 && ! reg_has_output_reload[REGNO (reg)])
7137 int nregno = REGNO (reg);
7139 if (reg_last_reload_reg[nregno])
7141 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7143 if (reg_reloaded_contents[last_regno] == nregno)
7144 spill_reg_store[last_regno] = 0;
7149 /* I is nonneg if this reload used a register.
7150 If rld[r].reg_rtx is 0, this is an optional reload
7151 that we opted to ignore. */
7153 if (i >= 0 && rld[r].reg_rtx != 0)
7155 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7157 int part_reaches_end = 0;
7158 int all_reaches_end = 1;
7160 /* For a multi register reload, we need to check if all or part
7161 of the value lives to the end. */
7162 for (k = 0; k < nr; k++)
7164 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7165 rld[r].when_needed))
7166 part_reaches_end = 1;
7168 all_reaches_end = 0;
7171 /* Ignore reloads that don't reach the end of the insn in
7173 if (all_reaches_end)
7175 /* First, clear out memory of what used to be in this spill reg.
7176 If consecutive registers are used, clear them all. */
7178 for (k = 0; k < nr; k++)
7179 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7181 /* Maybe the spill reg contains a copy of reload_out. */
7183 && (GET_CODE (rld[r].out) == REG
7187 || GET_CODE (rld[r].out_reg) == REG))
7189 rtx out = (GET_CODE (rld[r].out) == REG
7193 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7194 int nregno = REGNO (out);
7195 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7196 : HARD_REGNO_NREGS (nregno,
7197 GET_MODE (rld[r].reg_rtx)));
7199 spill_reg_store[i] = new_spill_reg_store[i];
7200 spill_reg_stored_to[i] = out;
7201 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7203 /* If NREGNO is a hard register, it may occupy more than
7204 one register. If it does, say what is in the
7205 rest of the registers assuming that both registers
7206 agree on how many words the object takes. If not,
7207 invalidate the subsequent registers. */
7209 if (nregno < FIRST_PSEUDO_REGISTER)
7210 for (k = 1; k < nnr; k++)
7211 reg_last_reload_reg[nregno + k]
7213 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7216 /* Now do the inverse operation. */
7217 for (k = 0; k < nr; k++)
7219 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7220 reg_reloaded_contents[i + k]
7221 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7224 reg_reloaded_insn[i + k] = insn;
7225 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7229 /* Maybe the spill reg contains a copy of reload_in. Only do
7230 something if there will not be an output reload for
7231 the register being reloaded. */
7232 else if (rld[r].out_reg == 0
7234 && ((GET_CODE (rld[r].in) == REG
7235 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7236 && ! reg_has_output_reload[REGNO (rld[r].in)])
7237 || (GET_CODE (rld[r].in_reg) == REG
7238 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7239 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7244 if (GET_CODE (rld[r].in) == REG
7245 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7246 nregno = REGNO (rld[r].in);
7247 else if (GET_CODE (rld[r].in_reg) == REG)
7248 nregno = REGNO (rld[r].in_reg);
7250 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7252 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7253 : HARD_REGNO_NREGS (nregno,
7254 GET_MODE (rld[r].reg_rtx)));
7256 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7258 if (nregno < FIRST_PSEUDO_REGISTER)
7259 for (k = 1; k < nnr; k++)
7260 reg_last_reload_reg[nregno + k]
7262 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7265 /* Unless we inherited this reload, show we haven't
7266 recently done a store.
7267 Previous stores of inherited auto_inc expressions
7268 also have to be discarded. */
7269 if (! reload_inherited[r]
7270 || (rld[r].out && ! rld[r].out_reg))
7271 spill_reg_store[i] = 0;
7273 for (k = 0; k < nr; k++)
7275 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7276 reg_reloaded_contents[i + k]
7277 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7280 reg_reloaded_insn[i + k] = insn;
7281 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7286 /* However, if part of the reload reaches the end, then we must
7287 invalidate the old info for the part that survives to the end. */
7288 else if (part_reaches_end)
7290 for (k = 0; k < nr; k++)
7291 if (reload_reg_reaches_end_p (i + k,
7293 rld[r].when_needed))
7294 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7298 /* The following if-statement was #if 0'd in 1.34 (or before...).
7299 It's reenabled in 1.35 because supposedly nothing else
7300 deals with this problem. */
7302 /* If a register gets output-reloaded from a non-spill register,
7303 that invalidates any previous reloaded copy of it.
7304 But forget_old_reloads_1 won't get to see it, because
7305 it thinks only about the original insn. So invalidate it here. */
7306 if (i < 0 && rld[r].out != 0
7307 && (GET_CODE (rld[r].out) == REG
7308 || (GET_CODE (rld[r].out) == MEM
7309 && GET_CODE (rld[r].out_reg) == REG)))
7311 rtx out = (GET_CODE (rld[r].out) == REG
7312 ? rld[r].out : rld[r].out_reg);
7313 int nregno = REGNO (out);
7314 if (nregno >= FIRST_PSEUDO_REGISTER)
7316 rtx src_reg, store_insn = NULL_RTX;
7318 reg_last_reload_reg[nregno] = 0;
7320 /* If we can find a hard register that is stored, record
7321 the storing insn so that we may delete this insn with
7322 delete_output_reload. */
7323 src_reg = rld[r].reg_rtx;
7325 /* If this is an optional reload, try to find the source reg
7326 from an input reload. */
7329 rtx set = single_set (insn);
7330 if (set && SET_DEST (set) == rld[r].out)
7334 src_reg = SET_SRC (set);
7336 for (k = 0; k < n_reloads; k++)
7338 if (rld[k].in == src_reg)
7340 src_reg = rld[k].reg_rtx;
7347 store_insn = new_spill_reg_store[REGNO (src_reg)];
7348 if (src_reg && GET_CODE (src_reg) == REG
7349 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7351 int src_regno = REGNO (src_reg);
7352 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7353 /* The place where to find a death note varies with
7354 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7355 necessarily checked exactly in the code that moves
7356 notes, so just check both locations. */
7357 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7358 if (! note && store_insn)
7359 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7362 spill_reg_store[src_regno + nr] = store_insn;
7363 spill_reg_stored_to[src_regno + nr] = out;
7364 reg_reloaded_contents[src_regno + nr] = nregno;
7365 reg_reloaded_insn[src_regno + nr] = store_insn;
7366 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7367 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7368 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7370 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7372 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7374 reg_last_reload_reg[nregno] = src_reg;
7379 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7381 while (num_regs-- > 0)
7382 reg_last_reload_reg[nregno + num_regs] = 0;
7386 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7389 /* Emit code to perform a reload from IN (which may be a reload register) to
7390 OUT (which may also be a reload register). IN or OUT is from operand
7391 OPNUM with reload type TYPE.
7393 Returns first insn emitted. */
7396 gen_reload (out, in, opnum, type)
7400 enum reload_type type;
7402 rtx last = get_last_insn ();
7405 /* If IN is a paradoxical SUBREG, remove it and try to put the
7406 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7407 if (GET_CODE (in) == SUBREG
7408 && (GET_MODE_SIZE (GET_MODE (in))
7409 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7410 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7411 in = SUBREG_REG (in), out = tem;
7412 else if (GET_CODE (out) == SUBREG
7413 && (GET_MODE_SIZE (GET_MODE (out))
7414 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7415 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7416 out = SUBREG_REG (out), in = tem;
7418 /* How to do this reload can get quite tricky. Normally, we are being
7419 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7420 register that didn't get a hard register. In that case we can just
7421 call emit_move_insn.
7423 We can also be asked to reload a PLUS that adds a register or a MEM to
7424 another register, constant or MEM. This can occur during frame pointer
7425 elimination and while reloading addresses. This case is handled by
7426 trying to emit a single insn to perform the add. If it is not valid,
7427 we use a two insn sequence.
7429 Finally, we could be called to handle an 'o' constraint by putting
7430 an address into a register. In that case, we first try to do this
7431 with a named pattern of "reload_load_address". If no such pattern
7432 exists, we just emit a SET insn and hope for the best (it will normally
7433 be valid on machines that use 'o').
7435 This entire process is made complex because reload will never
7436 process the insns we generate here and so we must ensure that
7437 they will fit their constraints and also by the fact that parts of
7438 IN might be being reloaded separately and replaced with spill registers.
7439 Because of this, we are, in some sense, just guessing the right approach
7440 here. The one listed above seems to work.
7442 ??? At some point, this whole thing needs to be rethought. */
7444 if (GET_CODE (in) == PLUS
7445 && (GET_CODE (XEXP (in, 0)) == REG
7446 || GET_CODE (XEXP (in, 0)) == SUBREG
7447 || GET_CODE (XEXP (in, 0)) == MEM)
7448 && (GET_CODE (XEXP (in, 1)) == REG
7449 || GET_CODE (XEXP (in, 1)) == SUBREG
7450 || CONSTANT_P (XEXP (in, 1))
7451 || GET_CODE (XEXP (in, 1)) == MEM))
7453 /* We need to compute the sum of a register or a MEM and another
7454 register, constant, or MEM, and put it into the reload
7455 register. The best possible way of doing this is if the machine
7456 has a three-operand ADD insn that accepts the required operands.
7458 The simplest approach is to try to generate such an insn and see if it
7459 is recognized and matches its constraints. If so, it can be used.
7461 It might be better not to actually emit the insn unless it is valid,
7462 but we need to pass the insn as an operand to `recog' and
7463 `extract_insn' and it is simpler to emit and then delete the insn if
7464 not valid than to dummy things up. */
7466 rtx op0, op1, tem, insn;
7469 op0 = find_replacement (&XEXP (in, 0));
7470 op1 = find_replacement (&XEXP (in, 1));
7472 /* Since constraint checking is strict, commutativity won't be
7473 checked, so we need to do that here to avoid spurious failure
7474 if the add instruction is two-address and the second operand
7475 of the add is the same as the reload reg, which is frequently
7476 the case. If the insn would be A = B + A, rearrange it so
7477 it will be A = A + B as constrain_operands expects. */
7479 if (GET_CODE (XEXP (in, 1)) == REG
7480 && REGNO (out) == REGNO (XEXP (in, 1)))
7481 tem = op0, op0 = op1, op1 = tem;
7483 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7484 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7486 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7487 code = recog_memoized (insn);
7491 extract_insn (insn);
7492 /* We want constrain operands to treat this insn strictly in
7493 its validity determination, i.e., the way it would after reload
7495 if (constrain_operands (1))
7499 delete_insns_since (last);
7501 /* If that failed, we must use a conservative two-insn sequence.
7503 Use a move to copy one operand into the reload register. Prefer
7504 to reload a constant, MEM or pseudo since the move patterns can
7505 handle an arbitrary operand. If OP1 is not a constant, MEM or
7506 pseudo and OP1 is not a valid operand for an add instruction, then
7509 After reloading one of the operands into the reload register, add
7510 the reload register to the output register.
7512 If there is another way to do this for a specific machine, a
7513 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7516 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7518 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7519 || (GET_CODE (op1) == REG
7520 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7521 || (code != CODE_FOR_nothing
7522 && ! ((*insn_data[code].operand[2].predicate)
7523 (op1, insn_data[code].operand[2].mode))))
7524 tem = op0, op0 = op1, op1 = tem;
7526 gen_reload (out, op0, opnum, type);
7528 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7529 This fixes a problem on the 32K where the stack pointer cannot
7530 be used as an operand of an add insn. */
7532 if (rtx_equal_p (op0, op1))
7535 insn = emit_insn (gen_add2_insn (out, op1));
7537 /* If that failed, copy the address register to the reload register.
7538 Then add the constant to the reload register. */
7540 code = recog_memoized (insn);
7544 extract_insn (insn);
7545 /* We want constrain operands to treat this insn strictly in
7546 its validity determination, i.e., the way it would after reload
7548 if (constrain_operands (1))
7550 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7552 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7557 delete_insns_since (last);
7559 gen_reload (out, op1, opnum, type);
7560 insn = emit_insn (gen_add2_insn (out, op0));
7561 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7564 #ifdef SECONDARY_MEMORY_NEEDED
7565 /* If we need a memory location to do the move, do it that way. */
7566 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7567 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7568 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7569 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7570 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7571 REGNO_REG_CLASS (reg_or_subregno (out)),
7574 /* Get the memory to use and rewrite both registers to its mode. */
7575 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7577 if (GET_MODE (loc) != GET_MODE (out))
7578 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7580 if (GET_MODE (loc) != GET_MODE (in))
7581 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7583 gen_reload (loc, in, opnum, type);
7584 gen_reload (out, loc, opnum, type);
7588 /* If IN is a simple operand, use gen_move_insn. */
7589 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7590 emit_insn (gen_move_insn (out, in));
7592 #ifdef HAVE_reload_load_address
7593 else if (HAVE_reload_load_address)
7594 emit_insn (gen_reload_load_address (out, in));
7597 /* Otherwise, just write (set OUT IN) and hope for the best. */
7599 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7601 /* Return the first insn emitted.
7602 We can not just return get_last_insn, because there may have
7603 been multiple instructions emitted. Also note that gen_move_insn may
7604 emit more than one insn itself, so we can not assume that there is one
7605 insn emitted per emit_insn_before call. */
7607 return last ? NEXT_INSN (last) : get_insns ();
7610 /* Delete a previously made output-reload whose result we now believe
7611 is not needed. First we double-check.
7613 INSN is the insn now being processed.
7614 LAST_RELOAD_REG is the hard register number for which we want to delete
7615 the last output reload.
7616 J is the reload-number that originally used REG. The caller has made
7617 certain that reload J doesn't use REG any longer for input. */
7620 delete_output_reload (insn, j, last_reload_reg)
7623 int last_reload_reg;
7625 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7626 rtx reg = spill_reg_stored_to[last_reload_reg];
7629 int n_inherited = 0;
7633 /* It is possible that this reload has been only used to set another reload
7634 we eliminated earlier and thus deleted this instruction too. */
7635 if (INSN_DELETED_P (output_reload_insn))
7638 /* Get the raw pseudo-register referred to. */
7640 while (GET_CODE (reg) == SUBREG)
7641 reg = SUBREG_REG (reg);
7642 substed = reg_equiv_memory_loc[REGNO (reg)];
7644 /* This is unsafe if the operand occurs more often in the current
7645 insn than it is inherited. */
7646 for (k = n_reloads - 1; k >= 0; k--)
7648 rtx reg2 = rld[k].in;
7651 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7652 reg2 = rld[k].in_reg;
7654 if (rld[k].out && ! rld[k].out_reg)
7655 reg2 = XEXP (rld[k].in_reg, 0);
7657 while (GET_CODE (reg2) == SUBREG)
7658 reg2 = SUBREG_REG (reg2);
7659 if (rtx_equal_p (reg2, reg))
7661 if (reload_inherited[k] || reload_override_in[k] || k == j)
7664 reg2 = rld[k].out_reg;
7667 while (GET_CODE (reg2) == SUBREG)
7668 reg2 = XEXP (reg2, 0);
7669 if (rtx_equal_p (reg2, reg))
7676 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7678 n_occurrences += count_occurrences (PATTERN (insn),
7679 eliminate_regs (substed, 0,
7681 if (n_occurrences > n_inherited)
7684 /* If the pseudo-reg we are reloading is no longer referenced
7685 anywhere between the store into it and here,
7686 and no jumps or labels intervene, then the value can get
7687 here through the reload reg alone.
7688 Otherwise, give up--return. */
7689 for (i1 = NEXT_INSN (output_reload_insn);
7690 i1 != insn; i1 = NEXT_INSN (i1))
7692 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7694 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7695 && reg_mentioned_p (reg, PATTERN (i1)))
7697 /* If this is USE in front of INSN, we only have to check that
7698 there are no more references than accounted for by inheritance. */
7699 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7701 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7702 i1 = NEXT_INSN (i1);
7704 if (n_occurrences <= n_inherited && i1 == insn)
7710 /* We will be deleting the insn. Remove the spill reg information. */
7711 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7713 spill_reg_store[last_reload_reg + k] = 0;
7714 spill_reg_stored_to[last_reload_reg + k] = 0;
7717 /* The caller has already checked that REG dies or is set in INSN.
7718 It has also checked that we are optimizing, and thus some
7719 inaccuracies in the debugging information are acceptable.
7720 So we could just delete output_reload_insn. But in some cases
7721 we can improve the debugging information without sacrificing
7722 optimization - maybe even improving the code: See if the pseudo
7723 reg has been completely replaced with reload regs. If so, delete
7724 the store insn and forget we had a stack slot for the pseudo. */
7725 if (rld[j].out != rld[j].in
7726 && REG_N_DEATHS (REGNO (reg)) == 1
7727 && REG_N_SETS (REGNO (reg)) == 1
7728 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7729 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7733 /* We know that it was used only between here and the beginning of
7734 the current basic block. (We also know that the last use before
7735 INSN was the output reload we are thinking of deleting, but never
7736 mind that.) Search that range; see if any ref remains. */
7737 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7739 rtx set = single_set (i2);
7741 /* Uses which just store in the pseudo don't count,
7742 since if they are the only uses, they are dead. */
7743 if (set != 0 && SET_DEST (set) == reg)
7745 if (GET_CODE (i2) == CODE_LABEL
7746 || GET_CODE (i2) == JUMP_INSN)
7748 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7749 && reg_mentioned_p (reg, PATTERN (i2)))
7751 /* Some other ref remains; just delete the output reload we
7753 delete_address_reloads (output_reload_insn, insn);
7754 delete_insn (output_reload_insn);
7759 /* Delete the now-dead stores into this pseudo. Note that this
7760 loop also takes care of deleting output_reload_insn. */
7761 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7763 rtx set = single_set (i2);
7765 if (set != 0 && SET_DEST (set) == reg)
7767 delete_address_reloads (i2, insn);
7770 if (GET_CODE (i2) == CODE_LABEL
7771 || GET_CODE (i2) == JUMP_INSN)
7775 /* For the debugging info, say the pseudo lives in this reload reg. */
7776 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7777 alter_reg (REGNO (reg), -1);
7781 delete_address_reloads (output_reload_insn, insn);
7782 delete_insn (output_reload_insn);
7786 /* We are going to delete DEAD_INSN. Recursively delete loads of
7787 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7788 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7790 delete_address_reloads (dead_insn, current_insn)
7791 rtx dead_insn, current_insn;
7793 rtx set = single_set (dead_insn);
7794 rtx set2, dst, prev, next;
7797 rtx dst = SET_DEST (set);
7798 if (GET_CODE (dst) == MEM)
7799 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7801 /* If we deleted the store from a reloaded post_{in,de}c expression,
7802 we can delete the matching adds. */
7803 prev = PREV_INSN (dead_insn);
7804 next = NEXT_INSN (dead_insn);
7805 if (! prev || ! next)
7807 set = single_set (next);
7808 set2 = single_set (prev);
7810 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7811 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7812 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7814 dst = SET_DEST (set);
7815 if (! rtx_equal_p (dst, SET_DEST (set2))
7816 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7817 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7818 || (INTVAL (XEXP (SET_SRC (set), 1))
7819 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7821 delete_related_insns (prev);
7822 delete_related_insns (next);
7825 /* Subfunction of delete_address_reloads: process registers found in X. */
7827 delete_address_reloads_1 (dead_insn, x, current_insn)
7828 rtx dead_insn, x, current_insn;
7830 rtx prev, set, dst, i2;
7832 enum rtx_code code = GET_CODE (x);
7836 const char *fmt = GET_RTX_FORMAT (code);
7837 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7840 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7841 else if (fmt[i] == 'E')
7843 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7844 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7851 if (spill_reg_order[REGNO (x)] < 0)
7854 /* Scan backwards for the insn that sets x. This might be a way back due
7856 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7858 code = GET_CODE (prev);
7859 if (code == CODE_LABEL || code == JUMP_INSN)
7861 if (GET_RTX_CLASS (code) != 'i')
7863 if (reg_set_p (x, PATTERN (prev)))
7865 if (reg_referenced_p (x, PATTERN (prev)))
7868 if (! prev || INSN_UID (prev) < reload_first_uid)
7870 /* Check that PREV only sets the reload register. */
7871 set = single_set (prev);
7874 dst = SET_DEST (set);
7875 if (GET_CODE (dst) != REG
7876 || ! rtx_equal_p (dst, x))
7878 if (! reg_set_p (dst, PATTERN (dead_insn)))
7880 /* Check if DST was used in a later insn -
7881 it might have been inherited. */
7882 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7884 if (GET_CODE (i2) == CODE_LABEL)
7888 if (reg_referenced_p (dst, PATTERN (i2)))
7890 /* If there is a reference to the register in the current insn,
7891 it might be loaded in a non-inherited reload. If no other
7892 reload uses it, that means the register is set before
7894 if (i2 == current_insn)
7896 for (j = n_reloads - 1; j >= 0; j--)
7897 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7898 || reload_override_in[j] == dst)
7900 for (j = n_reloads - 1; j >= 0; j--)
7901 if (rld[j].in && rld[j].reg_rtx == dst)
7908 if (GET_CODE (i2) == JUMP_INSN)
7910 /* If DST is still live at CURRENT_INSN, check if it is used for
7911 any reload. Note that even if CURRENT_INSN sets DST, we still
7912 have to check the reloads. */
7913 if (i2 == current_insn)
7915 for (j = n_reloads - 1; j >= 0; j--)
7916 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7917 || reload_override_in[j] == dst)
7919 /* ??? We can't finish the loop here, because dst might be
7920 allocated to a pseudo in this block if no reload in this
7921 block needs any of the classes containing DST - see
7922 spill_hard_reg. There is no easy way to tell this, so we
7923 have to scan till the end of the basic block. */
7925 if (reg_set_p (dst, PATTERN (i2)))
7929 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7930 reg_reloaded_contents[REGNO (dst)] = -1;
7934 /* Output reload-insns to reload VALUE into RELOADREG.
7935 VALUE is an autoincrement or autodecrement RTX whose operand
7936 is a register or memory location;
7937 so reloading involves incrementing that location.
7938 IN is either identical to VALUE, or some cheaper place to reload from.
7940 INC_AMOUNT is the number to increment or decrement by (always positive).
7941 This cannot be deduced from VALUE.
7943 Return the instruction that stores into RELOADREG. */
7946 inc_for_reload (reloadreg, in, value, inc_amount)
7951 /* REG or MEM to be copied and incremented. */
7952 rtx incloc = XEXP (value, 0);
7953 /* Nonzero if increment after copying. */
7954 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7960 rtx real_in = in == value ? XEXP (in, 0) : in;
7962 /* No hard register is equivalent to this register after
7963 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7964 we could inc/dec that register as well (maybe even using it for
7965 the source), but I'm not sure it's worth worrying about. */
7966 if (GET_CODE (incloc) == REG)
7967 reg_last_reload_reg[REGNO (incloc)] = 0;
7969 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7970 inc_amount = -inc_amount;
7972 inc = GEN_INT (inc_amount);
7974 /* If this is post-increment, first copy the location to the reload reg. */
7975 if (post && real_in != reloadreg)
7976 emit_insn (gen_move_insn (reloadreg, real_in));
7980 /* See if we can directly increment INCLOC. Use a method similar to
7981 that in gen_reload. */
7983 last = get_last_insn ();
7984 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7985 gen_rtx_PLUS (GET_MODE (incloc),
7988 code = recog_memoized (add_insn);
7991 extract_insn (add_insn);
7992 if (constrain_operands (1))
7994 /* If this is a pre-increment and we have incremented the value
7995 where it lives, copy the incremented value to RELOADREG to
7996 be used as an address. */
7999 emit_insn (gen_move_insn (reloadreg, incloc));
8004 delete_insns_since (last);
8007 /* If couldn't do the increment directly, must increment in RELOADREG.
8008 The way we do this depends on whether this is pre- or post-increment.
8009 For pre-increment, copy INCLOC to the reload register, increment it
8010 there, then save back. */
8014 if (in != reloadreg)
8015 emit_insn (gen_move_insn (reloadreg, real_in));
8016 emit_insn (gen_add2_insn (reloadreg, inc));
8017 store = emit_insn (gen_move_insn (incloc, reloadreg));
8022 Because this might be a jump insn or a compare, and because RELOADREG
8023 may not be available after the insn in an input reload, we must do
8024 the incrementation before the insn being reloaded for.
8026 We have already copied IN to RELOADREG. Increment the copy in
8027 RELOADREG, save that back, then decrement RELOADREG so it has
8028 the original value. */
8030 emit_insn (gen_add2_insn (reloadreg, inc));
8031 store = emit_insn (gen_move_insn (incloc, reloadreg));
8032 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8039 /* See whether a single set SET is a noop. */
8041 reload_cse_noop_set_p (set)
8044 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
8047 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8050 /* Try to simplify INSN. */
8052 reload_cse_simplify (insn, testreg)
8056 rtx body = PATTERN (insn);
8058 if (GET_CODE (body) == SET)
8062 /* Simplify even if we may think it is a no-op.
8063 We may think a memory load of a value smaller than WORD_SIZE
8064 is redundant because we haven't taken into account possible
8065 implicit extension. reload_cse_simplify_set() will bring
8066 this out, so it's safer to simplify before we delete. */
8067 count += reload_cse_simplify_set (body, insn);
8069 if (!count && reload_cse_noop_set_p (body))
8071 rtx value = SET_DEST (body);
8073 && ! REG_FUNCTION_VALUE_P (value))
8075 delete_insn_and_edges (insn);
8080 apply_change_group ();
8082 reload_cse_simplify_operands (insn, testreg);
8084 else if (GET_CODE (body) == PARALLEL)
8088 rtx value = NULL_RTX;
8090 /* If every action in a PARALLEL is a noop, we can delete
8091 the entire PARALLEL. */
8092 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8094 rtx part = XVECEXP (body, 0, i);
8095 if (GET_CODE (part) == SET)
8097 if (! reload_cse_noop_set_p (part))
8099 if (REG_P (SET_DEST (part))
8100 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
8104 value = SET_DEST (part);
8107 else if (GET_CODE (part) != CLOBBER)
8113 delete_insn_and_edges (insn);
8114 /* We're done with this insn. */
8118 /* It's not a no-op, but we can try to simplify it. */
8119 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8120 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8121 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8124 apply_change_group ();
8126 reload_cse_simplify_operands (insn, testreg);
8130 /* Do a very simple CSE pass over the hard registers.
8132 This function detects no-op moves where we happened to assign two
8133 different pseudo-registers to the same hard register, and then
8134 copied one to the other. Reload will generate a useless
8135 instruction copying a register to itself.
8137 This function also detects cases where we load a value from memory
8138 into two different registers, and (if memory is more expensive than
8139 registers) changes it to simply copy the first register into the
8142 Another optimization is performed that scans the operands of each
8143 instruction to see whether the value is already available in a
8144 hard register. It then replaces the operand with the hard register
8145 if possible, much like an optional reload would. */
8148 reload_cse_regs_1 (first)
8152 rtx testreg = gen_rtx_REG (VOIDmode, -1);
8155 init_alias_analysis ();
8157 for (insn = first; insn; insn = NEXT_INSN (insn))
8160 reload_cse_simplify (insn, testreg);
8162 cselib_process_insn (insn);
8166 end_alias_analysis ();
8170 /* Call cse / combine like post-reload optimization phases.
8171 FIRST is the first instruction. */
8173 reload_cse_regs (first)
8176 reload_cse_regs_1 (first);
8178 reload_cse_move2add (first);
8179 if (flag_expensive_optimizations)
8180 reload_cse_regs_1 (first);
8183 /* Try to simplify a single SET instruction. SET is the set pattern.
8184 INSN is the instruction it came from.
8185 This function only handles one case: if we set a register to a value
8186 which is not a register, we try to find that value in some other register
8187 and change the set into a register copy. */
8190 reload_cse_simplify_set (set, insn)
8197 enum reg_class dclass;
8200 struct elt_loc_list *l;
8201 #ifdef LOAD_EXTEND_OP
8202 enum rtx_code extend_op = NIL;
8205 dreg = true_regnum (SET_DEST (set));
8209 src = SET_SRC (set);
8210 if (side_effects_p (src) || true_regnum (src) >= 0)
8213 dclass = REGNO_REG_CLASS (dreg);
8215 #ifdef LOAD_EXTEND_OP
8216 /* When replacing a memory with a register, we need to honor assumptions
8217 that combine made wrt the contents of sign bits. We'll do this by
8218 generating an extend instruction instead of a reg->reg copy. Thus
8219 the destination must be a register that we can widen. */
8220 if (GET_CODE (src) == MEM
8221 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8222 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8223 && GET_CODE (SET_DEST (set)) != REG)
8227 /* If memory loads are cheaper than register copies, don't change them. */
8228 if (GET_CODE (src) == MEM)
8229 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8230 else if (CONSTANT_P (src))
8231 old_cost = rtx_cost (src, SET);
8232 else if (GET_CODE (src) == REG)
8233 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8234 REGNO_REG_CLASS (REGNO (src)), dclass);
8237 old_cost = rtx_cost (src, SET);
8239 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8242 for (l = val->locs; l; l = l->next)
8244 rtx this_rtx = l->loc;
8247 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8249 #ifdef LOAD_EXTEND_OP
8250 if (extend_op != NIL)
8252 HOST_WIDE_INT this_val;
8254 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8255 constants, such as SYMBOL_REF, cannot be extended. */
8256 if (GET_CODE (this_rtx) != CONST_INT)
8259 this_val = INTVAL (this_rtx);
8263 this_val &= GET_MODE_MASK (GET_MODE (src));
8266 /* ??? In theory we're already extended. */
8267 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8272 this_rtx = GEN_INT (this_val);
8275 this_cost = rtx_cost (this_rtx, SET);
8277 else if (GET_CODE (this_rtx) == REG)
8279 #ifdef LOAD_EXTEND_OP
8280 if (extend_op != NIL)
8282 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8283 this_cost = rtx_cost (this_rtx, SET);
8287 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8288 REGNO_REG_CLASS (REGNO (this_rtx)),
8294 /* If equal costs, prefer registers over anything else. That
8295 tends to lead to smaller instructions on some machines. */
8296 if (this_cost < old_cost
8297 || (this_cost == old_cost
8298 && GET_CODE (this_rtx) == REG
8299 && GET_CODE (SET_SRC (set)) != REG))
8301 #ifdef LOAD_EXTEND_OP
8302 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8304 #ifdef CANNOT_CHANGE_MODE_CLASS
8305 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
8307 REGNO_REG_CLASS (REGNO (SET_DEST (set))))
8311 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8312 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8313 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8317 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8318 old_cost = this_cost, did_change = 1;
8325 /* Try to replace operands in INSN with equivalent values that are already
8326 in registers. This can be viewed as optional reloading.
8328 For each non-register operand in the insn, see if any hard regs are
8329 known to be equivalent to that operand. Record the alternatives which
8330 can accept these hard registers. Among all alternatives, select the
8331 ones which are better or equal to the one currently matching, where
8332 "better" is in terms of '?' and '!' constraints. Among the remaining
8333 alternatives, select the one which replaces most operands with
8337 reload_cse_simplify_operands (insn, testreg)
8343 /* For each operand, all registers that are equivalent to it. */
8344 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8346 const char *constraints[MAX_RECOG_OPERANDS];
8348 /* Vector recording how bad an alternative is. */
8349 int *alternative_reject;
8350 /* Vector recording how many registers can be introduced by choosing
8351 this alternative. */
8352 int *alternative_nregs;
8353 /* Array of vectors recording, for each operand and each alternative,
8354 which hard register to substitute, or -1 if the operand should be
8356 int *op_alt_regno[MAX_RECOG_OPERANDS];
8357 /* Array of alternatives, sorted in order of decreasing desirability. */
8358 int *alternative_order;
8360 extract_insn (insn);
8362 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8365 /* Figure out which alternative currently matches. */
8366 if (! constrain_operands (1))
8367 fatal_insn_not_found (insn);
8369 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8370 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8371 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8372 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8373 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8375 /* For each operand, find out which regs are equivalent. */
8376 for (i = 0; i < recog_data.n_operands; i++)
8379 struct elt_loc_list *l;
8381 CLEAR_HARD_REG_SET (equiv_regs[i]);
8383 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8384 right, so avoid the problem here. Likewise if we have a constant
8385 and the insn pattern doesn't tell us the mode we need. */
8386 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8387 || (CONSTANT_P (recog_data.operand[i])
8388 && recog_data.operand_mode[i] == VOIDmode))
8391 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8395 for (l = v->locs; l; l = l->next)
8396 if (GET_CODE (l->loc) == REG)
8397 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8400 for (i = 0; i < recog_data.n_operands; i++)
8402 enum machine_mode mode;
8406 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8407 for (j = 0; j < recog_data.n_alternatives; j++)
8408 op_alt_regno[i][j] = -1;
8410 p = constraints[i] = recog_data.constraints[i];
8411 mode = recog_data.operand_mode[i];
8413 /* Add the reject values for each alternative given by the constraints
8414 for this operand. */
8422 alternative_reject[j] += 3;
8424 alternative_reject[j] += 300;
8427 /* We won't change operands which are already registers. We
8428 also don't want to modify output operands. */
8429 regno = true_regnum (recog_data.operand[i]);
8431 || constraints[i][0] == '='
8432 || constraints[i][0] == '+')
8435 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8437 int class = (int) NO_REGS;
8439 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8442 REGNO (testreg) = regno;
8443 PUT_MODE (testreg, mode);
8445 /* We found a register equal to this operand. Now look for all
8446 alternatives that can accept this register and have not been
8447 assigned a register they can use yet. */
8456 case '=': case '+': case '?':
8457 case '#': case '&': case '!':
8459 case '0': case '1': case '2': case '3': case '4':
8460 case '5': case '6': case '7': case '8': case '9':
8461 case 'm': case '<': case '>': case 'V': case 'o':
8462 case 'E': case 'F': case 'G': case 'H':
8463 case 's': case 'i': case 'n':
8464 case 'I': case 'J': case 'K': case 'L':
8465 case 'M': case 'N': case 'O': case 'P':
8467 /* These don't say anything we care about. */
8471 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8476 = (reg_class_subunion
8478 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
8481 case ',': case '\0':
8482 /* See if REGNO fits this alternative, and set it up as the
8483 replacement register if we don't have one for this
8484 alternative yet and the operand being replaced is not
8485 a cheap CONST_INT. */
8486 if (op_alt_regno[i][j] == -1
8487 && reg_fits_class_p (testreg, class, 0, mode)
8488 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8489 || (rtx_cost (recog_data.operand[i], SET)
8490 > rtx_cost (testreg, SET))))
8492 alternative_nregs[j]++;
8493 op_alt_regno[i][j] = regno;
8498 p += CONSTRAINT_LEN (c, p);
8506 /* Record all alternatives which are better or equal to the currently
8507 matching one in the alternative_order array. */
8508 for (i = j = 0; i < recog_data.n_alternatives; i++)
8509 if (alternative_reject[i] <= alternative_reject[which_alternative])
8510 alternative_order[j++] = i;
8511 recog_data.n_alternatives = j;
8513 /* Sort it. Given a small number of alternatives, a dumb algorithm
8514 won't hurt too much. */
8515 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8518 int best_reject = alternative_reject[alternative_order[i]];
8519 int best_nregs = alternative_nregs[alternative_order[i]];
8522 for (j = i + 1; j < recog_data.n_alternatives; j++)
8524 int this_reject = alternative_reject[alternative_order[j]];
8525 int this_nregs = alternative_nregs[alternative_order[j]];
8527 if (this_reject < best_reject
8528 || (this_reject == best_reject && this_nregs < best_nregs))
8531 best_reject = this_reject;
8532 best_nregs = this_nregs;
8536 tmp = alternative_order[best];
8537 alternative_order[best] = alternative_order[i];
8538 alternative_order[i] = tmp;
8541 /* Substitute the operands as determined by op_alt_regno for the best
8543 j = alternative_order[0];
8545 for (i = 0; i < recog_data.n_operands; i++)
8547 enum machine_mode mode = recog_data.operand_mode[i];
8548 if (op_alt_regno[i][j] == -1)
8551 validate_change (insn, recog_data.operand_loc[i],
8552 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8555 for (i = recog_data.n_dups - 1; i >= 0; i--)
8557 int op = recog_data.dup_num[i];
8558 enum machine_mode mode = recog_data.operand_mode[op];
8560 if (op_alt_regno[op][j] == -1)
8563 validate_change (insn, recog_data.dup_loc[i],
8564 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8567 return apply_change_group ();
8570 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8572 This code might also be useful when reload gave up on reg+reg addressing
8573 because of clashes between the return register and INDEX_REG_CLASS. */
8575 /* The maximum number of uses of a register we can keep track of to
8576 replace them with reg+reg addressing. */
8577 #define RELOAD_COMBINE_MAX_USES 6
8579 /* INSN is the insn where a register has ben used, and USEP points to the
8580 location of the register within the rtl. */
8581 struct reg_use { rtx insn, *usep; };
8583 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8584 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8585 indicates where it becomes live again.
8586 Otherwise, USE_INDEX is the index of the last encountered use of the
8587 register (which is first among these we have seen since we scan backwards),
8588 OFFSET contains the constant offset that is added to the register in
8589 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8590 last, of these uses.
8591 STORE_RUID is always meaningful if we only want to use a value in a
8592 register in a different place: it denotes the next insn in the insn
8593 stream (i.e. the last encountered) that sets or clobbers the register. */
8596 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8601 } reg_state[FIRST_PSEUDO_REGISTER];
8603 /* Reverse linear uid. This is increased in reload_combine while scanning
8604 the instructions from last to first. It is used to set last_label_ruid
8605 and the store_ruid / use_ruid fields in reg_state. */
8606 static int reload_combine_ruid;
8608 #define LABEL_LIVE(LABEL) \
8609 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8615 int first_index_reg = -1;
8616 int last_index_reg = 0;
8620 int last_label_ruid;
8621 int min_labelno, n_labels;
8622 HARD_REG_SET ever_live_at_start, *label_live;
8624 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8625 reload has already used it where appropriate, so there is no use in
8626 trying to generate it now. */
8627 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8630 /* To avoid wasting too much time later searching for an index register,
8631 determine the minimum and maximum index register numbers. */
8632 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8633 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8635 if (first_index_reg == -1)
8636 first_index_reg = r;
8641 /* If no index register is available, we can quit now. */
8642 if (first_index_reg == -1)
8645 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8646 information is a bit fuzzy immediately after reload, but it's
8647 still good enough to determine which registers are live at a jump
8649 min_labelno = get_first_label_num ();
8650 n_labels = max_label_num () - min_labelno;
8651 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8652 CLEAR_HARD_REG_SET (ever_live_at_start);
8654 FOR_EACH_BB_REVERSE (bb)
8657 if (GET_CODE (insn) == CODE_LABEL)
8661 REG_SET_TO_HARD_REG_SET (live,
8662 bb->global_live_at_start);
8663 compute_use_by_pseudos (&live,
8664 bb->global_live_at_start);
8665 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8666 IOR_HARD_REG_SET (ever_live_at_start, live);
8670 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8671 last_label_ruid = reload_combine_ruid = 0;
8672 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8674 reg_state[r].store_ruid = reload_combine_ruid;
8676 reg_state[r].use_index = -1;
8678 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8681 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8685 /* We cannot do our optimization across labels. Invalidating all the use
8686 information we have would be costly, so we just note where the label
8687 is and then later disable any optimization that would cross it. */
8688 if (GET_CODE (insn) == CODE_LABEL)
8689 last_label_ruid = reload_combine_ruid;
8690 else if (GET_CODE (insn) == BARRIER)
8691 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8692 if (! fixed_regs[r])
8693 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8695 if (! INSN_P (insn))
8698 reload_combine_ruid++;
8700 /* Look for (set (REGX) (CONST_INT))
8701 (set (REGX) (PLUS (REGX) (REGY)))
8703 ... (MEM (REGX)) ...
8705 (set (REGZ) (CONST_INT))
8707 ... (MEM (PLUS (REGZ) (REGY)))... .
8709 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8710 and that we know all uses of REGX before it dies. */
8711 set = single_set (insn);
8713 && GET_CODE (SET_DEST (set)) == REG
8714 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8715 GET_MODE (SET_DEST (set)))
8717 && GET_CODE (SET_SRC (set)) == PLUS
8718 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8719 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8720 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8722 rtx reg = SET_DEST (set);
8723 rtx plus = SET_SRC (set);
8724 rtx base = XEXP (plus, 1);
8725 rtx prev = prev_nonnote_insn (insn);
8726 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8727 unsigned int regno = REGNO (reg);
8728 rtx const_reg = NULL_RTX;
8729 rtx reg_sum = NULL_RTX;
8731 /* Now, we need an index register.
8732 We'll set index_reg to this index register, const_reg to the
8733 register that is to be loaded with the constant
8734 (denoted as REGZ in the substitution illustration above),
8735 and reg_sum to the register-register that we want to use to
8736 substitute uses of REG (typically in MEMs) with.
8737 First check REG and BASE for being index registers;
8738 we can use them even if they are not dead. */
8739 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8740 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8748 /* Otherwise, look for a free index register. Since we have
8749 checked above that neiter REG nor BASE are index registers,
8750 if we find anything at all, it will be different from these
8752 for (i = first_index_reg; i <= last_index_reg; i++)
8754 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8756 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8757 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8758 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8760 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8762 const_reg = index_reg;
8763 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8769 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8770 (REGY), i.e. BASE, is not clobbered before the last use we'll
8773 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8774 && rtx_equal_p (SET_DEST (prev_set), reg)
8775 && reg_state[regno].use_index >= 0
8776 && (reg_state[REGNO (base)].store_ruid
8777 <= reg_state[regno].use_ruid)
8782 /* Change destination register and, if necessary, the
8783 constant value in PREV, the constant loading instruction. */
8784 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8785 if (reg_state[regno].offset != const0_rtx)
8786 validate_change (prev,
8787 &SET_SRC (prev_set),
8788 GEN_INT (INTVAL (SET_SRC (prev_set))
8789 + INTVAL (reg_state[regno].offset)),
8792 /* Now for every use of REG that we have recorded, replace REG
8794 for (i = reg_state[regno].use_index;
8795 i < RELOAD_COMBINE_MAX_USES; i++)
8796 validate_change (reg_state[regno].reg_use[i].insn,
8797 reg_state[regno].reg_use[i].usep,
8798 /* Each change must have its own
8800 copy_rtx (reg_sum), 1);
8802 if (apply_change_group ())
8806 /* Delete the reg-reg addition. */
8809 if (reg_state[regno].offset != const0_rtx)
8810 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8812 for (np = ®_NOTES (prev); *np;)
8814 if (REG_NOTE_KIND (*np) == REG_EQUAL
8815 || REG_NOTE_KIND (*np) == REG_EQUIV)
8816 *np = XEXP (*np, 1);
8818 np = &XEXP (*np, 1);
8821 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8822 reg_state[REGNO (const_reg)].store_ruid
8823 = reload_combine_ruid;
8829 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8831 if (GET_CODE (insn) == CALL_INSN)
8835 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8836 if (call_used_regs[r])
8838 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8839 reg_state[r].store_ruid = reload_combine_ruid;
8842 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8843 link = XEXP (link, 1))
8845 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8846 if (GET_CODE (usage_rtx) == REG)
8849 unsigned int start_reg = REGNO (usage_rtx);
8850 unsigned int num_regs =
8851 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8852 unsigned int end_reg = start_reg + num_regs - 1;
8853 for (i = start_reg; i <= end_reg; i++)
8854 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8856 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8857 reg_state[i].store_ruid = reload_combine_ruid;
8860 reg_state[i].use_index = -1;
8865 else if (GET_CODE (insn) == JUMP_INSN
8866 && GET_CODE (PATTERN (insn)) != RETURN)
8868 /* Non-spill registers might be used at the call destination in
8869 some unknown fashion, so we have to mark the unknown use. */
8872 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8873 && JUMP_LABEL (insn))
8874 live = &LABEL_LIVE (JUMP_LABEL (insn));
8876 live = &ever_live_at_start;
8878 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8879 if (TEST_HARD_REG_BIT (*live, i))
8880 reg_state[i].use_index = -1;
8883 reload_combine_note_use (&PATTERN (insn), insn);
8884 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8886 if (REG_NOTE_KIND (note) == REG_INC
8887 && GET_CODE (XEXP (note, 0)) == REG)
8889 int regno = REGNO (XEXP (note, 0));
8891 reg_state[regno].store_ruid = reload_combine_ruid;
8892 reg_state[regno].use_index = -1;
8900 /* Check if DST is a register or a subreg of a register; if it is,
8901 update reg_state[regno].store_ruid and reg_state[regno].use_index
8902 accordingly. Called via note_stores from reload_combine. */
8905 reload_combine_note_store (dst, set, data)
8907 void *data ATTRIBUTE_UNUSED;
8911 enum machine_mode mode = GET_MODE (dst);
8913 if (GET_CODE (dst) == SUBREG)
8915 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8916 GET_MODE (SUBREG_REG (dst)),
8919 dst = SUBREG_REG (dst);
8921 if (GET_CODE (dst) != REG)
8923 regno += REGNO (dst);
8925 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8926 careful with registers / register parts that are not full words.
8928 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8929 if (GET_CODE (set) != SET
8930 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8931 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8932 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8934 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8936 reg_state[i].use_index = -1;
8937 reg_state[i].store_ruid = reload_combine_ruid;
8942 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8944 reg_state[i].store_ruid = reload_combine_ruid;
8945 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8950 /* XP points to a piece of rtl that has to be checked for any uses of
8952 *XP is the pattern of INSN, or a part of it.
8953 Called from reload_combine, and recursively by itself. */
8955 reload_combine_note_use (xp, insn)
8959 enum rtx_code code = x->code;
8962 rtx offset = const0_rtx; /* For the REG case below. */
8967 if (GET_CODE (SET_DEST (x)) == REG)
8969 reload_combine_note_use (&SET_SRC (x), insn);
8975 /* If this is the USE of a return value, we can't change it. */
8976 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8978 /* Mark the return register as used in an unknown fashion. */
8979 rtx reg = XEXP (x, 0);
8980 int regno = REGNO (reg);
8981 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8983 while (--nregs >= 0)
8984 reg_state[regno + nregs].use_index = -1;
8990 if (GET_CODE (SET_DEST (x)) == REG)
8992 /* No spurious CLOBBERs of pseudo registers may remain. */
8993 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
9000 /* We are interested in (plus (reg) (const_int)) . */
9001 if (GET_CODE (XEXP (x, 0)) != REG
9002 || GET_CODE (XEXP (x, 1)) != CONST_INT)
9004 offset = XEXP (x, 1);
9009 int regno = REGNO (x);
9013 /* No spurious USEs of pseudo registers may remain. */
9014 if (regno >= FIRST_PSEUDO_REGISTER)
9017 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
9019 /* We can't substitute into multi-hard-reg uses. */
9022 while (--nregs >= 0)
9023 reg_state[regno + nregs].use_index = -1;
9027 /* If this register is already used in some unknown fashion, we
9029 If we decrement the index from zero to -1, we can't store more
9030 uses, so this register becomes used in an unknown fashion. */
9031 use_index = --reg_state[regno].use_index;
9035 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9037 /* We have found another use for a register that is already
9038 used later. Check if the offsets match; if not, mark the
9039 register as used in an unknown fashion. */
9040 if (! rtx_equal_p (offset, reg_state[regno].offset))
9042 reg_state[regno].use_index = -1;
9048 /* This is the first use of this register we have seen since we
9049 marked it as dead. */
9050 reg_state[regno].offset = offset;
9051 reg_state[regno].use_ruid = reload_combine_ruid;
9053 reg_state[regno].reg_use[use_index].insn = insn;
9054 reg_state[regno].reg_use[use_index].usep = xp;
9062 /* Recursively process the components of X. */
9063 fmt = GET_RTX_FORMAT (code);
9064 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9067 reload_combine_note_use (&XEXP (x, i), insn);
9068 else if (fmt[i] == 'E')
9070 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9071 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9076 /* See if we can reduce the cost of a constant by replacing a move
9077 with an add. We track situations in which a register is set to a
9078 constant or to a register plus a constant. */
9079 /* We cannot do our optimization across labels. Invalidating all the
9080 information about register contents we have would be costly, so we
9081 use move2add_last_label_luid to note where the label is and then
9082 later disable any optimization that would cross it.
9083 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9084 reg_set_luid[n] is greater than move2add_last_label_luid. */
9085 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9087 /* If reg_base_reg[n] is negative, register n has been set to
9088 reg_offset[n] in mode reg_mode[n] .
9089 If reg_base_reg[n] is non-negative, register n has been set to the
9090 sum of reg_offset[n] and the value of register reg_base_reg[n]
9091 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9092 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9093 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9094 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9096 /* move2add_luid is linearly increased while scanning the instructions
9097 from first to last. It is used to set reg_set_luid in
9098 reload_cse_move2add and move2add_note_store. */
9099 static int move2add_luid;
9101 /* move2add_last_label_luid is set whenever a label is found. Labels
9102 invalidate all previously collected reg_offset data. */
9103 static int move2add_last_label_luid;
9105 /* ??? We don't know how zero / sign extension is handled, hence we
9106 can't go from a narrower to a wider mode. */
9107 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9108 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9109 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9110 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9111 GET_MODE_BITSIZE (INMODE))))
9114 reload_cse_move2add (first)
9120 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9121 reg_set_luid[i] = 0;
9123 move2add_last_label_luid = 0;
9125 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9129 if (GET_CODE (insn) == CODE_LABEL)
9131 move2add_last_label_luid = move2add_luid;
9132 /* We're going to increment move2add_luid twice after a
9133 label, so that we can use move2add_last_label_luid + 1 as
9134 the luid for constants. */
9138 if (! INSN_P (insn))
9140 pat = PATTERN (insn);
9141 /* For simplicity, we only perform this optimization on
9142 straightforward SETs. */
9143 if (GET_CODE (pat) == SET
9144 && GET_CODE (SET_DEST (pat)) == REG)
9146 rtx reg = SET_DEST (pat);
9147 int regno = REGNO (reg);
9148 rtx src = SET_SRC (pat);
9150 /* Check if we have valid information on the contents of this
9151 register in the mode of REG. */
9152 if (reg_set_luid[regno] > move2add_last_label_luid
9153 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9155 /* Try to transform (set (REGX) (CONST_INT A))
9157 (set (REGX) (CONST_INT B))
9159 (set (REGX) (CONST_INT A))
9161 (set (REGX) (plus (REGX) (CONST_INT B-A)))
9163 (set (REGX) (CONST_INT A))
9165 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
9168 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9171 GEN_INT (trunc_int_for_mode (INTVAL (src)
9172 - reg_offset[regno],
9174 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9175 use (set (reg) (reg)) instead.
9176 We don't delete this insn, nor do we convert it into a
9177 note, to avoid losing register notes or the return
9178 value flag. jump2 already knows how to get rid of
9180 if (new_src == const0_rtx)
9182 /* If the constants are different, this is a
9183 truncation, that, if turned into (set (reg)
9184 (reg)), would be discarded. Maybe we should
9185 try a truncMN pattern? */
9186 if (INTVAL (src) == reg_offset [regno])
9187 validate_change (insn, &SET_SRC (pat), reg, 0);
9189 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9190 && have_add2_insn (reg, new_src))
9192 rtx newpat = gen_add2_insn (reg, new_src);
9193 if (INSN_P (newpat) && NEXT_INSN (newpat) == NULL_RTX)
9194 newpat = PATTERN (newpat);
9195 /* If it was the first insn of a sequence or
9196 some other emitted insn, validate_change will
9198 validate_change (insn, &PATTERN (insn),
9203 enum machine_mode narrow_mode;
9204 for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
9205 narrow_mode != GET_MODE (reg);
9206 narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
9208 if (have_insn_for (STRICT_LOW_PART, narrow_mode)
9209 && ((reg_offset[regno]
9210 & ~GET_MODE_MASK (narrow_mode))
9212 & ~GET_MODE_MASK (narrow_mode))))
9214 rtx narrow_reg = gen_rtx_REG (narrow_mode,
9217 GEN_INT (trunc_int_for_mode (INTVAL (src),
9220 gen_rtx_SET (VOIDmode,
9221 gen_rtx_STRICT_LOW_PART (VOIDmode,
9224 if (validate_change (insn, &PATTERN (insn),
9230 reg_set_luid[regno] = move2add_luid;
9231 reg_mode[regno] = GET_MODE (reg);
9232 reg_offset[regno] = INTVAL (src);
9236 /* Try to transform (set (REGX) (REGY))
9237 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9240 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9243 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9245 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9246 else if (GET_CODE (src) == REG
9247 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9248 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9249 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9250 reg_mode[REGNO (src)]))
9252 rtx next = next_nonnote_insn (insn);
9255 set = single_set (next);
9257 && SET_DEST (set) == reg
9258 && GET_CODE (SET_SRC (set)) == PLUS
9259 && XEXP (SET_SRC (set), 0) == reg
9260 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9262 rtx src3 = XEXP (SET_SRC (set), 1);
9263 HOST_WIDE_INT added_offset = INTVAL (src3);
9264 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9265 HOST_WIDE_INT regno_offset = reg_offset[regno];
9267 GEN_INT (trunc_int_for_mode (added_offset
9273 if (new_src == const0_rtx)
9274 /* See above why we create (set (reg) (reg)) here. */
9276 = validate_change (next, &SET_SRC (set), reg, 0);
9277 else if ((rtx_cost (new_src, PLUS)
9278 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9279 && have_add2_insn (reg, new_src))
9281 rtx newpat = gen_add2_insn (reg, new_src);
9283 && NEXT_INSN (newpat) == NULL_RTX)
9284 newpat = PATTERN (newpat);
9286 = validate_change (next, &PATTERN (next),
9292 reg_mode[regno] = GET_MODE (reg);
9294 trunc_int_for_mode (added_offset + base_offset,
9302 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9304 if (REG_NOTE_KIND (note) == REG_INC
9305 && GET_CODE (XEXP (note, 0)) == REG)
9307 /* Reset the information about this register. */
9308 int regno = REGNO (XEXP (note, 0));
9309 if (regno < FIRST_PSEUDO_REGISTER)
9310 reg_set_luid[regno] = 0;
9313 note_stores (PATTERN (insn), move2add_note_store, NULL);
9315 /* If INSN is a conditional branch, we try to extract an
9316 implicit set out of it. */
9317 if (any_condjump_p (insn) && onlyjump_p (insn))
9319 rtx cnd = fis_get_condition (insn);
9322 && GET_CODE (cnd) == NE
9323 && GET_CODE (XEXP (cnd, 0)) == REG
9324 /* The following two checks, which are also in
9325 move2add_note_store, are intended to reduce the
9326 number of calls to gen_rtx_SET to avoid memory
9327 allocation if possible. */
9328 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))
9329 && HARD_REGNO_NREGS (REGNO (XEXP (cnd, 0)), GET_MODE (XEXP (cnd, 0))) == 1
9330 && GET_CODE (XEXP (cnd, 1)) == CONST_INT)
9333 gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1));
9334 move2add_note_store (SET_DEST (implicit_set), implicit_set, 0);
9338 /* If this is a CALL_INSN, all call used registers are stored with
9340 if (GET_CODE (insn) == CALL_INSN)
9342 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9344 if (call_used_regs[i])
9345 /* Reset the information about this register. */
9346 reg_set_luid[i] = 0;
9352 /* SET is a SET or CLOBBER that sets DST.
9353 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9354 Called from reload_cse_move2add via note_stores. */
9357 move2add_note_store (dst, set, data)
9359 void *data ATTRIBUTE_UNUSED;
9361 unsigned int regno = 0;
9363 enum machine_mode mode = GET_MODE (dst);
9365 if (GET_CODE (dst) == SUBREG)
9367 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9368 GET_MODE (SUBREG_REG (dst)),
9371 dst = SUBREG_REG (dst);
9374 /* Some targets do argument pushes without adding REG_INC notes. */
9376 if (GET_CODE (dst) == MEM)
9378 dst = XEXP (dst, 0);
9379 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9380 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9381 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9384 if (GET_CODE (dst) != REG)
9387 regno += REGNO (dst);
9389 if (SCALAR_INT_MODE_P (mode)
9390 && HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9391 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9392 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9393 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9395 rtx src = SET_SRC (set);
9397 HOST_WIDE_INT offset;
9399 /* This may be different from mode, if SET_DEST (set) is a
9401 enum machine_mode dst_mode = GET_MODE (dst);
9403 switch (GET_CODE (src))
9406 if (GET_CODE (XEXP (src, 0)) == REG)
9408 base_reg = XEXP (src, 0);
9410 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9411 offset = INTVAL (XEXP (src, 1));
9412 else if (GET_CODE (XEXP (src, 1)) == REG
9413 && (reg_set_luid[REGNO (XEXP (src, 1))]
9414 > move2add_last_label_luid)
9415 && (MODES_OK_FOR_MOVE2ADD
9416 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9418 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9419 offset = reg_offset[REGNO (XEXP (src, 1))];
9420 /* Maybe the first register is known to be a
9422 else if (reg_set_luid[REGNO (base_reg)]
9423 > move2add_last_label_luid
9424 && (MODES_OK_FOR_MOVE2ADD
9425 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9426 && reg_base_reg[REGNO (base_reg)] < 0)
9428 offset = reg_offset[REGNO (base_reg)];
9429 base_reg = XEXP (src, 1);
9448 /* Start tracking the register as a constant. */
9449 reg_base_reg[regno] = -1;
9450 reg_offset[regno] = INTVAL (SET_SRC (set));
9451 /* We assign the same luid to all registers set to constants. */
9452 reg_set_luid[regno] = move2add_last_label_luid + 1;
9453 reg_mode[regno] = mode;
9458 /* Invalidate the contents of the register. */
9459 reg_set_luid[regno] = 0;
9463 base_regno = REGNO (base_reg);
9464 /* If information about the base register is not valid, set it
9465 up as a new base register, pretending its value is known
9466 starting from the current insn. */
9467 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9469 reg_base_reg[base_regno] = base_regno;
9470 reg_offset[base_regno] = 0;
9471 reg_set_luid[base_regno] = move2add_luid;
9472 reg_mode[base_regno] = mode;
9474 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9475 reg_mode[base_regno]))
9478 reg_mode[regno] = mode;
9480 /* Copy base information from our base register. */
9481 reg_set_luid[regno] = reg_set_luid[base_regno];
9482 reg_base_reg[regno] = reg_base_reg[base_regno];
9484 /* Compute the sum of the offsets or constants. */
9485 reg_offset[regno] = trunc_int_for_mode (offset
9486 + reg_offset[base_regno],
9491 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9493 for (i = regno; i < endregno; i++)
9494 /* Reset the information about this register. */
9495 reg_set_luid[i] = 0;
9501 add_auto_inc_notes (insn, x)
9505 enum rtx_code code = GET_CODE (x);
9509 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9512 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9516 /* Scan all the operand sub-expressions. */
9517 fmt = GET_RTX_FORMAT (code);
9518 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9521 add_auto_inc_notes (insn, XEXP (x, i));
9522 else if (fmt[i] == 'E')
9523 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9524 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9529 /* Copy EH notes from an insn to its reloads. */
9531 copy_eh_notes (insn, x)
9535 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9538 for (; x != 0; x = NEXT_INSN (x))
9540 if (may_trap_p (PATTERN (x)))
9542 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9548 /* This is used by reload pass, that does emit some instructions after
9549 abnormal calls moving basic block end, but in fact it wants to emit
9550 them on the edge. Looks for abnormal call edges, find backward the
9551 proper call and fix the damage.
9553 Similar handle instructions throwing exceptions internally. */
9555 fixup_abnormal_edges ()
9557 bool inserted = false;
9564 /* Look for cases we are interested in - calls or instructions causing
9566 for (e = bb->succ; e; e = e->succ_next)
9568 if (e->flags & EDGE_ABNORMAL_CALL)
9570 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9571 == (EDGE_ABNORMAL | EDGE_EH))
9574 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9576 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9578 for (e = bb->succ; e; e = e->succ_next)
9579 if (e->flags & EDGE_FALLTHRU)
9581 /* Get past the new insns generated. Allow notes, as the insns may
9582 be already deleted. */
9583 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9584 && !can_throw_internal (insn)
9585 && insn != bb->head)
9586 insn = PREV_INSN (insn);
9587 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9591 insn = NEXT_INSN (insn);
9592 while (insn && insn != stop)
9594 next = NEXT_INSN (insn);
9599 /* Sometimes there's still the return value USE.
9600 If it's placed after a trapping call (i.e. that
9601 call is the last insn anyway), we have no fallthru
9602 edge. Simply delete this use and don't try to insert
9603 on the non-existent edge. */
9604 if (GET_CODE (PATTERN (insn)) != USE)
9606 /* We're not deleting it, we're moving it. */
9607 INSN_DELETED_P (insn) = 0;
9608 PREV_INSN (insn) = NULL_RTX;
9609 NEXT_INSN (insn) = NULL_RTX;
9611 insert_insn_on_edge (insn, e);
9618 /* We've possibly turned single trapping insn into multiple ones. */
9619 if (flag_non_call_exceptions)
9622 blocks = sbitmap_alloc (last_basic_block);
9623 sbitmap_ones (blocks);
9624 find_many_sub_basic_blocks (blocks);
9627 commit_edge_insertions ();
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