1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
82 #define LOCAL_REGNO(REGNO) 0
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static char *reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is a memory location to which pseudo reg N is equivalent,
104 prior to any register elimination (such as frame pointer to stack
105 pointer). Depending on whether or not it is a valid address, this value
106 is transferred to either reg_equiv_address or reg_equiv_mem. */
107 rtx *reg_equiv_memory_loc;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Number of spill-regs so far; number of valid elements of spill_regs. */
148 /* In parallel with spill_regs, contains REG rtx's for those regs.
149 Holds the last rtx used for any given reg, or 0 if it has never
150 been used for spilling yet. This rtx is reused, provided it has
152 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
154 /* In parallel with spill_regs, contains nonzero for a spill reg
155 that was stored after the last time it was used.
156 The precise value is the insn generated to do the store. */
157 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
159 /* This is the register that was stored with spill_reg_store. This is a
160 copy of reload_out / reload_out_reg when the value was stored; if
161 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
162 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
164 /* This table is the inverse mapping of spill_regs:
165 indexed by hard reg number,
166 it contains the position of that reg in spill_regs,
167 or -1 for something that is not in spill_regs.
169 ?!? This is no longer accurate. */
170 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
172 /* This reg set indicates registers that can't be used as spill registers for
173 the currently processed insn. These are the hard registers which are live
174 during the insn, but not allocated to pseudos, as well as fixed
176 static HARD_REG_SET bad_spill_regs;
178 /* These are the hard registers that can't be used as spill register for any
179 insn. This includes registers used for user variables and registers that
180 we can't eliminate. A register that appears in this set also can't be used
181 to retry register allocation. */
182 static HARD_REG_SET bad_spill_regs_global;
184 /* Describes order of use of registers for reloading
185 of spilled pseudo-registers. `n_spills' is the number of
186 elements that are actually valid; new ones are added at the end.
188 Both spill_regs and spill_reg_order are used on two occasions:
189 once during find_reload_regs, where they keep track of the spill registers
190 for a single insn, but also during reload_as_needed where they show all
191 the registers ever used by reload. For the latter case, the information
192 is calculated during finish_spills. */
193 static short spill_regs[FIRST_PSEUDO_REGISTER];
195 /* This vector of reg sets indicates, for each pseudo, which hard registers
196 may not be used for retrying global allocation because the register was
197 formerly spilled from one of them. If we allowed reallocating a pseudo to
198 a register that it was already allocated to, reload might not
200 static HARD_REG_SET *pseudo_previous_regs;
202 /* This vector of reg sets indicates, for each pseudo, which hard
203 registers may not be used for retrying global allocation because they
204 are used as spill registers during one of the insns in which the
206 static HARD_REG_SET *pseudo_forbidden_regs;
208 /* All hard regs that have been used as spill registers for any insn are
209 marked in this set. */
210 static HARD_REG_SET used_spill_regs;
212 /* Index of last register assigned as a spill register. We allocate in
213 a round-robin fashion. */
214 static int last_spill_reg;
216 /* Nonzero if indirect addressing is supported on the machine; this means
217 that spilling (REG n) does not require reloading it into a register in
218 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
219 value indicates the level of indirect addressing supported, e.g., two
220 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
222 static char spill_indirect_levels;
224 /* Nonzero if indirect addressing is supported when the innermost MEM is
225 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
226 which these are valid is the same as spill_indirect_levels, above. */
227 char indirect_symref_ok;
229 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
230 char double_reg_address_ok;
232 /* Record the stack slot for each spilled hard register. */
233 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
235 /* Width allocated so far for that stack slot. */
236 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
238 /* Record which pseudos needed to be spilled. */
239 static regset_head spilled_pseudos;
241 /* Used for communication between order_regs_for_reload and count_pseudo.
242 Used to avoid counting one pseudo twice. */
243 static regset_head pseudos_counted;
245 /* First uid used by insns created by reload in this function.
246 Used in find_equiv_reg. */
247 int reload_first_uid;
249 /* Flag set by local-alloc or global-alloc if anything is live in
250 a call-clobbered reg across calls. */
251 int caller_save_needed;
253 /* Set to 1 while reload_as_needed is operating.
254 Required by some machines to handle any generated moves differently. */
255 int reload_in_progress = 0;
257 /* These arrays record the insn_code of insns that may be needed to
258 perform input and output reloads of special objects. They provide a
259 place to pass a scratch register. */
260 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
261 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
263 /* This obstack is used for allocation of rtl during register elimination.
264 The allocated storage can be freed once find_reloads has processed the
266 struct obstack reload_obstack;
268 /* Points to the beginning of the reload_obstack. All insn_chain structures
269 are allocated first. */
270 char *reload_startobj;
272 /* The point after all insn_chain structures. Used to quickly deallocate
273 memory allocated in copy_reloads during calculate_needs_all_insns. */
274 char *reload_firstobj;
276 /* This points before all local rtl generated by register elimination.
277 Used to quickly free all memory after processing one insn. */
278 static char *reload_insn_firstobj;
280 /* List of insn_chain instructions, one for every insn that reload needs to
282 struct insn_chain *reload_insn_chain;
284 /* List of all insns needing reloads. */
285 static struct insn_chain *insns_need_reload;
287 /* This structure is used to record information about register eliminations.
288 Each array entry describes one possible way of eliminating a register
289 in favor of another. If there is more than one way of eliminating a
290 particular register, the most preferred should be specified first. */
294 int from; /* Register number to be eliminated. */
295 int to; /* Register number used as replacement. */
296 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
297 int can_eliminate; /* Nonzero if this elimination can be done. */
298 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
299 insns made by reload. */
300 HOST_WIDE_INT offset; /* Current offset between the two regs. */
301 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
302 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
303 rtx from_rtx; /* REG rtx for the register to be eliminated.
304 We cannot simply compare the number since
305 we might then spuriously replace a hard
306 register corresponding to a pseudo
307 assigned to the reg to be eliminated. */
308 rtx to_rtx; /* REG rtx for the replacement. */
311 static struct elim_table *reg_eliminate = 0;
313 /* This is an intermediate structure to initialize the table. It has
314 exactly the members provided by ELIMINABLE_REGS. */
315 static const struct elim_table_1
319 } reg_eliminate_1[] =
321 /* If a set of eliminable registers was specified, define the table from it.
322 Otherwise, default to the normal case of the frame pointer being
323 replaced by the stack pointer. */
325 #ifdef ELIMINABLE_REGS
328 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
331 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
333 /* Record the number of pending eliminations that have an offset not equal
334 to their initial offset. If nonzero, we use a new copy of each
335 replacement result in any insns encountered. */
336 int num_not_at_initial_offset;
338 /* Count the number of registers that we may be able to eliminate. */
339 static int num_eliminable;
340 /* And the number of registers that are equivalent to a constant that
341 can be eliminated to frame_pointer / arg_pointer + constant. */
342 static int num_eliminable_invariants;
344 /* For each label, we record the offset of each elimination. If we reach
345 a label by more than one path and an offset differs, we cannot do the
346 elimination. This information is indexed by the difference of the
347 number of the label and the first label number. We can't offset the
348 pointer itself as this can cause problems on machines with segmented
349 memory. The first table is an array of flags that records whether we
350 have yet encountered a label and the second table is an array of arrays,
351 one entry in the latter array for each elimination. */
353 static int first_label_num;
354 static char *offsets_known_at;
355 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
357 /* Number of labels in the current function. */
359 static int num_labels;
361 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
362 static void maybe_fix_stack_asms (void);
363 static void copy_reloads (struct insn_chain *);
364 static void calculate_needs_all_insns (int);
365 static int find_reg (struct insn_chain *, int);
366 static void find_reload_regs (struct insn_chain *);
367 static void select_reload_regs (void);
368 static void delete_caller_save_insns (void);
370 static void spill_failure (rtx, enum reg_class);
371 static void count_spilled_pseudo (int, int, int);
372 static void delete_dead_insn (rtx);
373 static void alter_reg (int, int);
374 static void set_label_offsets (rtx, rtx, int);
375 static void check_eliminable_occurrences (rtx);
376 static void elimination_effects (rtx, enum machine_mode);
377 static int eliminate_regs_in_insn (rtx, int);
378 static void update_eliminable_offsets (void);
379 static void mark_not_eliminable (rtx, rtx, void *);
380 static void set_initial_elim_offsets (void);
381 static void verify_initial_elim_offsets (void);
382 static void set_initial_label_offsets (void);
383 static void set_offsets_for_label (rtx);
384 static void init_elim_table (void);
385 static void update_eliminables (HARD_REG_SET *);
386 static void spill_hard_reg (unsigned int, int);
387 static int finish_spills (int);
388 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
389 static void scan_paradoxical_subregs (rtx);
390 static void count_pseudo (int);
391 static void order_regs_for_reload (struct insn_chain *);
392 static void reload_as_needed (int);
393 static void forget_old_reloads_1 (rtx, rtx, void *);
394 static int reload_reg_class_lower (const void *, const void *);
395 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
397 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
399 static int reload_reg_free_p (unsigned int, int, enum reload_type);
400 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
402 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
404 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
405 static int allocate_reload_reg (struct insn_chain *, int, int);
406 static int conflicts_with_override (rtx);
407 static void failed_reload (rtx, int);
408 static int set_reload_reg (int, int);
409 static void choose_reload_regs_init (struct insn_chain *, rtx *);
410 static void choose_reload_regs (struct insn_chain *);
411 static void merge_assigned_reloads (rtx);
412 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
414 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
416 static void do_input_reload (struct insn_chain *, struct reload *, int);
417 static void do_output_reload (struct insn_chain *, struct reload *, int);
418 static void emit_reload_insns (struct insn_chain *);
419 static void delete_output_reload (rtx, int, int);
420 static void delete_address_reloads (rtx, rtx);
421 static void delete_address_reloads_1 (rtx, rtx, rtx);
422 static rtx inc_for_reload (rtx, rtx, rtx, int);
424 static void add_auto_inc_notes (rtx, rtx);
426 static void copy_eh_notes (rtx, rtx);
428 /* Initialize the reload pass once per compilation. */
435 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
436 Set spill_indirect_levels to the number of levels such addressing is
437 permitted, zero if it is not permitted at all. */
440 = gen_rtx_MEM (Pmode,
443 LAST_VIRTUAL_REGISTER + 1),
445 spill_indirect_levels = 0;
447 while (memory_address_p (QImode, tem))
449 spill_indirect_levels++;
450 tem = gen_rtx_MEM (Pmode, tem);
453 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
455 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
456 indirect_symref_ok = memory_address_p (QImode, tem);
458 /* See if reg+reg is a valid (and offsettable) address. */
460 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
462 tem = gen_rtx_PLUS (Pmode,
463 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
464 gen_rtx_REG (Pmode, i));
466 /* This way, we make sure that reg+reg is an offsettable address. */
467 tem = plus_constant (tem, 4);
469 if (memory_address_p (QImode, tem))
471 double_reg_address_ok = 1;
476 /* Initialize obstack for our rtl allocation. */
477 gcc_obstack_init (&reload_obstack);
478 reload_startobj = obstack_alloc (&reload_obstack, 0);
480 INIT_REG_SET (&spilled_pseudos);
481 INIT_REG_SET (&pseudos_counted);
484 /* List of insn chains that are currently unused. */
485 static struct insn_chain *unused_insn_chains = 0;
487 /* Allocate an empty insn_chain structure. */
489 new_insn_chain (void)
491 struct insn_chain *c;
493 if (unused_insn_chains == 0)
495 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
496 INIT_REG_SET (&c->live_throughout);
497 INIT_REG_SET (&c->dead_or_set);
501 c = unused_insn_chains;
502 unused_insn_chains = c->next;
504 c->is_caller_save_insn = 0;
505 c->need_operand_change = 0;
511 /* Small utility function to set all regs in hard reg set TO which are
512 allocated to pseudos in regset FROM. */
515 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
519 EXECUTE_IF_SET_IN_REG_SET
520 (from, FIRST_PSEUDO_REGISTER, regno,
522 int r = reg_renumber[regno];
527 /* reload_combine uses the information from
528 BASIC_BLOCK->global_live_at_start, which might still
529 contain registers that have not actually been allocated
530 since they have an equivalence. */
531 if (! reload_completed)
536 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
538 SET_HARD_REG_BIT (*to, r + nregs);
543 /* Replace all pseudos found in LOC with their corresponding
547 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
560 unsigned int regno = REGNO (x);
562 if (regno < FIRST_PSEUDO_REGISTER)
565 x = eliminate_regs (x, mem_mode, usage);
569 replace_pseudos_in (loc, mem_mode, usage);
573 if (reg_equiv_constant[regno])
574 *loc = reg_equiv_constant[regno];
575 else if (reg_equiv_mem[regno])
576 *loc = reg_equiv_mem[regno];
577 else if (reg_equiv_address[regno])
578 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
579 else if (GET_CODE (regno_reg_rtx[regno]) != REG
580 || REGNO (regno_reg_rtx[regno]) != regno)
581 *loc = regno_reg_rtx[regno];
587 else if (code == MEM)
589 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
593 /* Process each of our operands recursively. */
594 fmt = GET_RTX_FORMAT (code);
595 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
597 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
598 else if (*fmt == 'E')
599 for (j = 0; j < XVECLEN (x, i); j++)
600 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
604 /* Global variables used by reload and its subroutines. */
606 /* Set during calculate_needs if an insn needs register elimination. */
607 static int something_needs_elimination;
608 /* Set during calculate_needs if an insn needs an operand changed. */
609 int something_needs_operands_changed;
611 /* Nonzero means we couldn't get enough spill regs. */
614 /* Main entry point for the reload pass.
616 FIRST is the first insn of the function being compiled.
618 GLOBAL nonzero means we were called from global_alloc
619 and should attempt to reallocate any pseudoregs that we
620 displace from hard regs we will use for reloads.
621 If GLOBAL is zero, we do not have enough information to do that,
622 so any pseudo reg that is spilled must go to the stack.
624 Return value is nonzero if reload failed
625 and we must not do any more for this function. */
628 reload (rtx first, int global)
632 struct elim_table *ep;
635 /* Make sure even insns with volatile mem refs are recognizable. */
640 reload_firstobj = obstack_alloc (&reload_obstack, 0);
642 /* Make sure that the last insn in the chain
643 is not something that needs reloading. */
644 emit_note (NOTE_INSN_DELETED);
646 /* Enable find_equiv_reg to distinguish insns made by reload. */
647 reload_first_uid = get_max_uid ();
649 #ifdef SECONDARY_MEMORY_NEEDED
650 /* Initialize the secondary memory table. */
651 clear_secondary_mem ();
654 /* We don't have a stack slot for any spill reg yet. */
655 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
656 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
658 /* Initialize the save area information for caller-save, in case some
662 /* Compute which hard registers are now in use
663 as homes for pseudo registers.
664 This is done here rather than (eg) in global_alloc
665 because this point is reached even if not optimizing. */
666 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
669 /* A function that receives a nonlocal goto must save all call-saved
671 if (current_function_has_nonlocal_label)
672 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
673 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
674 regs_ever_live[i] = 1;
676 /* Find all the pseudo registers that didn't get hard regs
677 but do have known equivalent constants or memory slots.
678 These include parameters (known equivalent to parameter slots)
679 and cse'd or loop-moved constant memory addresses.
681 Record constant equivalents in reg_equiv_constant
682 so they will be substituted by find_reloads.
683 Record memory equivalents in reg_mem_equiv so they can
684 be substituted eventually by altering the REG-rtx's. */
686 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
687 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
688 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
689 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
690 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
691 reg_old_renumber = xcalloc (max_regno, sizeof (short));
692 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
693 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
694 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
696 CLEAR_HARD_REG_SET (bad_spill_regs_global);
698 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
699 Also find all paradoxical subregs and find largest such for each pseudo.
700 On machines with small register classes, record hard registers that
701 are used for user variables. These can never be used for spills. */
703 num_eliminable_invariants = 0;
704 for (insn = first; insn; insn = NEXT_INSN (insn))
706 rtx set = single_set (insn);
708 /* We may introduce USEs that we want to remove at the end, so
709 we'll mark them with QImode. Make sure there are no
710 previously-marked insns left by say regmove. */
711 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
712 && GET_MODE (insn) != VOIDmode)
713 PUT_MODE (insn, VOIDmode);
715 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
717 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
719 #ifdef LEGITIMATE_PIC_OPERAND_P
720 && (! function_invariant_p (XEXP (note, 0))
722 /* A function invariant is often CONSTANT_P but may
723 include a register. We promise to only pass
724 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
725 || (CONSTANT_P (XEXP (note, 0))
726 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
730 rtx x = XEXP (note, 0);
731 i = REGNO (SET_DEST (set));
732 if (i > LAST_VIRTUAL_REGISTER)
734 /* It can happen that a REG_EQUIV note contains a MEM
735 that is not a legitimate memory operand. As later
736 stages of reload assume that all addresses found
737 in the reg_equiv_* arrays were originally legitimate,
738 we ignore such REG_EQUIV notes. */
739 if (memory_operand (x, VOIDmode))
741 /* Always unshare the equivalence, so we can
742 substitute into this insn without touching the
744 reg_equiv_memory_loc[i] = copy_rtx (x);
746 else if (function_invariant_p (x))
748 if (GET_CODE (x) == PLUS)
750 /* This is PLUS of frame pointer and a constant,
751 and might be shared. Unshare it. */
752 reg_equiv_constant[i] = copy_rtx (x);
753 num_eliminable_invariants++;
755 else if (x == frame_pointer_rtx
756 || x == arg_pointer_rtx)
758 reg_equiv_constant[i] = x;
759 num_eliminable_invariants++;
761 else if (LEGITIMATE_CONSTANT_P (x))
762 reg_equiv_constant[i] = x;
765 reg_equiv_memory_loc[i]
766 = force_const_mem (GET_MODE (SET_DEST (set)), x);
767 if (!reg_equiv_memory_loc[i])
774 /* If this register is being made equivalent to a MEM
775 and the MEM is not SET_SRC, the equivalencing insn
776 is one with the MEM as a SET_DEST and it occurs later.
777 So don't mark this insn now. */
778 if (GET_CODE (x) != MEM
779 || rtx_equal_p (SET_SRC (set), x))
781 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
786 /* If this insn is setting a MEM from a register equivalent to it,
787 this is the equivalencing insn. */
788 else if (set && GET_CODE (SET_DEST (set)) == MEM
789 && GET_CODE (SET_SRC (set)) == REG
790 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
791 && rtx_equal_p (SET_DEST (set),
792 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
793 reg_equiv_init[REGNO (SET_SRC (set))]
794 = gen_rtx_INSN_LIST (VOIDmode, insn,
795 reg_equiv_init[REGNO (SET_SRC (set))]);
798 scan_paradoxical_subregs (PATTERN (insn));
803 first_label_num = get_first_label_num ();
804 num_labels = max_label_num () - first_label_num;
806 /* Allocate the tables used to store offset information at labels. */
807 /* We used to use alloca here, but the size of what it would try to
808 allocate would occasionally cause it to exceed the stack limit and
809 cause a core dump. */
810 offsets_known_at = xmalloc (num_labels);
811 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
813 /* Alter each pseudo-reg rtx to contain its hard reg number.
814 Assign stack slots to the pseudos that lack hard regs or equivalents.
815 Do not touch virtual registers. */
817 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
820 /* If we have some registers we think can be eliminated, scan all insns to
821 see if there is an insn that sets one of these registers to something
822 other than itself plus a constant. If so, the register cannot be
823 eliminated. Doing this scan here eliminates an extra pass through the
824 main reload loop in the most common case where register elimination
826 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
827 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
828 || GET_CODE (insn) == CALL_INSN)
829 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
831 maybe_fix_stack_asms ();
833 insns_need_reload = 0;
834 something_needs_elimination = 0;
836 /* Initialize to -1, which means take the first spill register. */
839 /* Spill any hard regs that we know we can't eliminate. */
840 CLEAR_HARD_REG_SET (used_spill_regs);
841 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
842 if (! ep->can_eliminate)
843 spill_hard_reg (ep->from, 1);
845 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
846 if (frame_pointer_needed)
847 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
849 finish_spills (global);
851 /* From now on, we may need to generate moves differently. We may also
852 allow modifications of insns which cause them to not be recognized.
853 Any such modifications will be cleaned up during reload itself. */
854 reload_in_progress = 1;
856 /* This loop scans the entire function each go-round
857 and repeats until one repetition spills no additional hard regs. */
860 int something_changed;
863 HOST_WIDE_INT starting_frame_size;
865 /* Round size of stack frame to stack_alignment_needed. This must be done
866 here because the stack size may be a part of the offset computation
867 for register elimination, and there might have been new stack slots
868 created in the last iteration of this loop. */
869 if (cfun->stack_alignment_needed)
870 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
872 starting_frame_size = get_frame_size ();
874 set_initial_elim_offsets ();
875 set_initial_label_offsets ();
877 /* For each pseudo register that has an equivalent location defined,
878 try to eliminate any eliminable registers (such as the frame pointer)
879 assuming initial offsets for the replacement register, which
882 If the resulting location is directly addressable, substitute
883 the MEM we just got directly for the old REG.
885 If it is not addressable but is a constant or the sum of a hard reg
886 and constant, it is probably not addressable because the constant is
887 out of range, in that case record the address; we will generate
888 hairy code to compute the address in a register each time it is
889 needed. Similarly if it is a hard register, but one that is not
890 valid as an address register.
892 If the location is not addressable, but does not have one of the
893 above forms, assign a stack slot. We have to do this to avoid the
894 potential of producing lots of reloads if, e.g., a location involves
895 a pseudo that didn't get a hard register and has an equivalent memory
896 location that also involves a pseudo that didn't get a hard register.
898 Perhaps at some point we will improve reload_when_needed handling
899 so this problem goes away. But that's very hairy. */
901 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
902 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
904 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
906 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
908 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
909 else if (CONSTANT_P (XEXP (x, 0))
910 || (GET_CODE (XEXP (x, 0)) == REG
911 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
912 || (GET_CODE (XEXP (x, 0)) == PLUS
913 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
914 && (REGNO (XEXP (XEXP (x, 0), 0))
915 < FIRST_PSEUDO_REGISTER)
916 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
917 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
920 /* Make a new stack slot. Then indicate that something
921 changed so we go back and recompute offsets for
922 eliminable registers because the allocation of memory
923 below might change some offset. reg_equiv_{mem,address}
924 will be set up for this pseudo on the next pass around
926 reg_equiv_memory_loc[i] = 0;
927 reg_equiv_init[i] = 0;
932 if (caller_save_needed)
935 /* If we allocated another stack slot, redo elimination bookkeeping. */
936 if (starting_frame_size != get_frame_size ())
939 if (caller_save_needed)
941 save_call_clobbered_regs ();
942 /* That might have allocated new insn_chain structures. */
943 reload_firstobj = obstack_alloc (&reload_obstack, 0);
946 calculate_needs_all_insns (global);
948 CLEAR_REG_SET (&spilled_pseudos);
951 something_changed = 0;
953 /* If we allocated any new memory locations, make another pass
954 since it might have changed elimination offsets. */
955 if (starting_frame_size != get_frame_size ())
956 something_changed = 1;
959 HARD_REG_SET to_spill;
960 CLEAR_HARD_REG_SET (to_spill);
961 update_eliminables (&to_spill);
962 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
963 if (TEST_HARD_REG_BIT (to_spill, i))
965 spill_hard_reg (i, 1);
968 /* Regardless of the state of spills, if we previously had
969 a register that we thought we could eliminate, but now can
970 not eliminate, we must run another pass.
972 Consider pseudos which have an entry in reg_equiv_* which
973 reference an eliminable register. We must make another pass
974 to update reg_equiv_* so that we do not substitute in the
975 old value from when we thought the elimination could be
977 something_changed = 1;
981 select_reload_regs ();
985 if (insns_need_reload != 0 || did_spill)
986 something_changed |= finish_spills (global);
988 if (! something_changed)
991 if (caller_save_needed)
992 delete_caller_save_insns ();
994 obstack_free (&reload_obstack, reload_firstobj);
997 /* If global-alloc was run, notify it of any register eliminations we have
1000 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1001 if (ep->can_eliminate)
1002 mark_elimination (ep->from, ep->to);
1004 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1005 If that insn didn't set the register (i.e., it copied the register to
1006 memory), just delete that insn instead of the equivalencing insn plus
1007 anything now dead. If we call delete_dead_insn on that insn, we may
1008 delete the insn that actually sets the register if the register dies
1009 there and that is incorrect. */
1011 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1013 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1016 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1018 rtx equiv_insn = XEXP (list, 0);
1020 /* If we already deleted the insn or if it may trap, we can't
1021 delete it. The latter case shouldn't happen, but can
1022 if an insn has a variable address, gets a REG_EH_REGION
1023 note added to it, and then gets converted into an load
1024 from a constant address. */
1025 if (GET_CODE (equiv_insn) == NOTE
1026 || can_throw_internal (equiv_insn))
1028 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1029 delete_dead_insn (equiv_insn);
1032 PUT_CODE (equiv_insn, NOTE);
1033 NOTE_SOURCE_FILE (equiv_insn) = 0;
1034 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1040 /* Use the reload registers where necessary
1041 by generating move instructions to move the must-be-register
1042 values into or out of the reload registers. */
1044 if (insns_need_reload != 0 || something_needs_elimination
1045 || something_needs_operands_changed)
1047 HOST_WIDE_INT old_frame_size = get_frame_size ();
1049 reload_as_needed (global);
1051 if (old_frame_size != get_frame_size ())
1055 verify_initial_elim_offsets ();
1058 /* If we were able to eliminate the frame pointer, show that it is no
1059 longer live at the start of any basic block. If it ls live by
1060 virtue of being in a pseudo, that pseudo will be marked live
1061 and hence the frame pointer will be known to be live via that
1064 if (! frame_pointer_needed)
1066 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1067 HARD_FRAME_POINTER_REGNUM);
1069 /* Come here (with failure set nonzero) if we can't get enough spill regs
1070 and we decide not to abort about it. */
1073 CLEAR_REG_SET (&spilled_pseudos);
1074 reload_in_progress = 0;
1076 /* Now eliminate all pseudo regs by modifying them into
1077 their equivalent memory references.
1078 The REG-rtx's for the pseudos are modified in place,
1079 so all insns that used to refer to them now refer to memory.
1081 For a reg that has a reg_equiv_address, all those insns
1082 were changed by reloading so that no insns refer to it any longer;
1083 but the DECL_RTL of a variable decl may refer to it,
1084 and if so this causes the debugging info to mention the variable. */
1086 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1090 if (reg_equiv_mem[i])
1091 addr = XEXP (reg_equiv_mem[i], 0);
1093 if (reg_equiv_address[i])
1094 addr = reg_equiv_address[i];
1098 if (reg_renumber[i] < 0)
1100 rtx reg = regno_reg_rtx[i];
1102 REG_USERVAR_P (reg) = 0;
1103 PUT_CODE (reg, MEM);
1104 XEXP (reg, 0) = addr;
1105 if (reg_equiv_memory_loc[i])
1106 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1109 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1110 = MEM_SCALAR_P (reg) = 0;
1111 MEM_ATTRS (reg) = 0;
1114 else if (reg_equiv_mem[i])
1115 XEXP (reg_equiv_mem[i], 0) = addr;
1119 /* We must set reload_completed now since the cleanup_subreg_operands call
1120 below will re-recognize each insn and reload may have generated insns
1121 which are only valid during and after reload. */
1122 reload_completed = 1;
1124 /* Make a pass over all the insns and delete all USEs which we inserted
1125 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1126 notes. Delete all CLOBBER insns, except those that refer to the return
1127 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1128 from misarranging variable-array code, and simplify (subreg (reg))
1129 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1130 are no longer useful or accurate. Strip and regenerate REG_INC notes
1131 that may have been moved around. */
1133 for (insn = first; insn; insn = NEXT_INSN (insn))
1138 if (GET_CODE (insn) == CALL_INSN)
1139 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1140 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1142 if ((GET_CODE (PATTERN (insn)) == USE
1143 /* We mark with QImode USEs introduced by reload itself. */
1144 && (GET_MODE (insn) == QImode
1145 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1146 || (GET_CODE (PATTERN (insn)) == CLOBBER
1147 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1148 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1149 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1150 && XEXP (XEXP (PATTERN (insn), 0), 0)
1151 != stack_pointer_rtx))
1152 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1153 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1159 /* Some CLOBBERs may survive until here and still reference unassigned
1160 pseudos with const equivalent, which may in turn cause ICE in later
1161 passes if the reference remains in place. */
1162 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1163 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1164 VOIDmode, PATTERN (insn));
1166 pnote = ®_NOTES (insn);
1169 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1170 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1171 || REG_NOTE_KIND (*pnote) == REG_INC
1172 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1173 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1174 *pnote = XEXP (*pnote, 1);
1176 pnote = &XEXP (*pnote, 1);
1180 add_auto_inc_notes (insn, PATTERN (insn));
1183 /* And simplify (subreg (reg)) if it appears as an operand. */
1184 cleanup_subreg_operands (insn);
1187 /* If we are doing stack checking, give a warning if this function's
1188 frame size is larger than we expect. */
1189 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1191 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1192 static int verbose_warned = 0;
1194 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1195 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1196 size += UNITS_PER_WORD;
1198 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1200 warning ("frame size too large for reliable stack checking");
1201 if (! verbose_warned)
1203 warning ("try reducing the number of local variables");
1209 /* Indicate that we no longer have known memory locations or constants. */
1210 if (reg_equiv_constant)
1211 free (reg_equiv_constant);
1212 reg_equiv_constant = 0;
1213 if (reg_equiv_memory_loc)
1214 free (reg_equiv_memory_loc);
1215 reg_equiv_memory_loc = 0;
1217 if (offsets_known_at)
1218 free (offsets_known_at);
1222 free (reg_equiv_mem);
1223 free (reg_equiv_init);
1224 free (reg_equiv_address);
1225 free (reg_max_ref_width);
1226 free (reg_old_renumber);
1227 free (pseudo_previous_regs);
1228 free (pseudo_forbidden_regs);
1230 CLEAR_HARD_REG_SET (used_spill_regs);
1231 for (i = 0; i < n_spills; i++)
1232 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1234 /* Free all the insn_chain structures at once. */
1235 obstack_free (&reload_obstack, reload_startobj);
1236 unused_insn_chains = 0;
1237 fixup_abnormal_edges ();
1239 /* Replacing pseudos with their memory equivalents might have
1240 created shared rtx. Subsequent passes would get confused
1241 by this, so unshare everything here. */
1242 unshare_all_rtl_again (first);
1247 /* Yet another special case. Unfortunately, reg-stack forces people to
1248 write incorrect clobbers in asm statements. These clobbers must not
1249 cause the register to appear in bad_spill_regs, otherwise we'll call
1250 fatal_insn later. We clear the corresponding regnos in the live
1251 register sets to avoid this.
1252 The whole thing is rather sick, I'm afraid. */
1255 maybe_fix_stack_asms (void)
1258 const char *constraints[MAX_RECOG_OPERANDS];
1259 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1260 struct insn_chain *chain;
1262 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1265 HARD_REG_SET clobbered, allowed;
1268 if (! INSN_P (chain->insn)
1269 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1271 pat = PATTERN (chain->insn);
1272 if (GET_CODE (pat) != PARALLEL)
1275 CLEAR_HARD_REG_SET (clobbered);
1276 CLEAR_HARD_REG_SET (allowed);
1278 /* First, make a mask of all stack regs that are clobbered. */
1279 for (i = 0; i < XVECLEN (pat, 0); i++)
1281 rtx t = XVECEXP (pat, 0, i);
1282 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1283 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1286 /* Get the operand values and constraints out of the insn. */
1287 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1288 constraints, operand_mode);
1290 /* For every operand, see what registers are allowed. */
1291 for (i = 0; i < noperands; i++)
1293 const char *p = constraints[i];
1294 /* For every alternative, we compute the class of registers allowed
1295 for reloading in CLS, and merge its contents into the reg set
1297 int cls = (int) NO_REGS;
1303 if (c == '\0' || c == ',' || c == '#')
1305 /* End of one alternative - mark the regs in the current
1306 class, and reset the class. */
1307 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1313 } while (c != '\0' && c != ',');
1321 case '=': case '+': case '*': case '%': case '?': case '!':
1322 case '0': case '1': case '2': case '3': case '4': case 'm':
1323 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1324 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1325 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1330 cls = (int) reg_class_subunion[cls]
1331 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1336 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1340 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1341 cls = (int) reg_class_subunion[cls]
1342 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1344 cls = (int) reg_class_subunion[cls]
1345 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1347 p += CONSTRAINT_LEN (c, p);
1350 /* Those of the registers which are clobbered, but allowed by the
1351 constraints, must be usable as reload registers. So clear them
1352 out of the life information. */
1353 AND_HARD_REG_SET (allowed, clobbered);
1354 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1355 if (TEST_HARD_REG_BIT (allowed, i))
1357 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1358 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1365 /* Copy the global variables n_reloads and rld into the corresponding elts
1368 copy_reloads (struct insn_chain *chain)
1370 chain->n_reloads = n_reloads;
1371 chain->rld = obstack_alloc (&reload_obstack,
1372 n_reloads * sizeof (struct reload));
1373 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1374 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1377 /* Walk the chain of insns, and determine for each whether it needs reloads
1378 and/or eliminations. Build the corresponding insns_need_reload list, and
1379 set something_needs_elimination as appropriate. */
1381 calculate_needs_all_insns (int global)
1383 struct insn_chain **pprev_reload = &insns_need_reload;
1384 struct insn_chain *chain, *next = 0;
1386 something_needs_elimination = 0;
1388 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1389 for (chain = reload_insn_chain; chain != 0; chain = next)
1391 rtx insn = chain->insn;
1395 /* Clear out the shortcuts. */
1396 chain->n_reloads = 0;
1397 chain->need_elim = 0;
1398 chain->need_reload = 0;
1399 chain->need_operand_change = 0;
1401 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1402 include REG_LABEL), we need to see what effects this has on the
1403 known offsets at labels. */
1405 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1406 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1407 set_label_offsets (insn, insn, 0);
1411 rtx old_body = PATTERN (insn);
1412 int old_code = INSN_CODE (insn);
1413 rtx old_notes = REG_NOTES (insn);
1414 int did_elimination = 0;
1415 int operands_changed = 0;
1416 rtx set = single_set (insn);
1418 /* Skip insns that only set an equivalence. */
1419 if (set && GET_CODE (SET_DEST (set)) == REG
1420 && reg_renumber[REGNO (SET_DEST (set))] < 0
1421 && reg_equiv_constant[REGNO (SET_DEST (set))])
1424 /* If needed, eliminate any eliminable registers. */
1425 if (num_eliminable || num_eliminable_invariants)
1426 did_elimination = eliminate_regs_in_insn (insn, 0);
1428 /* Analyze the instruction. */
1429 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1430 global, spill_reg_order);
1432 /* If a no-op set needs more than one reload, this is likely
1433 to be something that needs input address reloads. We
1434 can't get rid of this cleanly later, and it is of no use
1435 anyway, so discard it now.
1436 We only do this when expensive_optimizations is enabled,
1437 since this complements reload inheritance / output
1438 reload deletion, and it can make debugging harder. */
1439 if (flag_expensive_optimizations && n_reloads > 1)
1441 rtx set = single_set (insn);
1443 && SET_SRC (set) == SET_DEST (set)
1444 && GET_CODE (SET_SRC (set)) == REG
1445 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1448 /* Delete it from the reload chain. */
1450 chain->prev->next = next;
1452 reload_insn_chain = next;
1454 next->prev = chain->prev;
1455 chain->next = unused_insn_chains;
1456 unused_insn_chains = chain;
1461 update_eliminable_offsets ();
1463 /* Remember for later shortcuts which insns had any reloads or
1464 register eliminations. */
1465 chain->need_elim = did_elimination;
1466 chain->need_reload = n_reloads > 0;
1467 chain->need_operand_change = operands_changed;
1469 /* Discard any register replacements done. */
1470 if (did_elimination)
1472 obstack_free (&reload_obstack, reload_insn_firstobj);
1473 PATTERN (insn) = old_body;
1474 INSN_CODE (insn) = old_code;
1475 REG_NOTES (insn) = old_notes;
1476 something_needs_elimination = 1;
1479 something_needs_operands_changed |= operands_changed;
1483 copy_reloads (chain);
1484 *pprev_reload = chain;
1485 pprev_reload = &chain->next_need_reload;
1492 /* Comparison function for qsort to decide which of two reloads
1493 should be handled first. *P1 and *P2 are the reload numbers. */
1496 reload_reg_class_lower (const void *r1p, const void *r2p)
1498 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1501 /* Consider required reloads before optional ones. */
1502 t = rld[r1].optional - rld[r2].optional;
1506 /* Count all solitary classes before non-solitary ones. */
1507 t = ((reg_class_size[(int) rld[r2].class] == 1)
1508 - (reg_class_size[(int) rld[r1].class] == 1));
1512 /* Aside from solitaires, consider all multi-reg groups first. */
1513 t = rld[r2].nregs - rld[r1].nregs;
1517 /* Consider reloads in order of increasing reg-class number. */
1518 t = (int) rld[r1].class - (int) rld[r2].class;
1522 /* If reloads are equally urgent, sort by reload number,
1523 so that the results of qsort leave nothing to chance. */
1527 /* The cost of spilling each hard reg. */
1528 static int spill_cost[FIRST_PSEUDO_REGISTER];
1530 /* When spilling multiple hard registers, we use SPILL_COST for the first
1531 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1532 only the first hard reg for a multi-reg pseudo. */
1533 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1535 /* Update the spill cost arrays, considering that pseudo REG is live. */
1538 count_pseudo (int reg)
1540 int freq = REG_FREQ (reg);
1541 int r = reg_renumber[reg];
1544 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1545 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1548 SET_REGNO_REG_SET (&pseudos_counted, reg);
1553 spill_add_cost[r] += freq;
1555 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1557 spill_cost[r + nregs] += freq;
1560 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1561 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1564 order_regs_for_reload (struct insn_chain *chain)
1567 HARD_REG_SET used_by_pseudos;
1568 HARD_REG_SET used_by_pseudos2;
1570 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1572 memset (spill_cost, 0, sizeof spill_cost);
1573 memset (spill_add_cost, 0, sizeof spill_add_cost);
1575 /* Count number of uses of each hard reg by pseudo regs allocated to it
1576 and then order them by decreasing use. First exclude hard registers
1577 that are live in or across this insn. */
1579 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1580 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1581 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1582 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1584 /* Now find out which pseudos are allocated to it, and update
1586 CLEAR_REG_SET (&pseudos_counted);
1588 EXECUTE_IF_SET_IN_REG_SET
1589 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1593 EXECUTE_IF_SET_IN_REG_SET
1594 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1598 CLEAR_REG_SET (&pseudos_counted);
1601 /* Vector of reload-numbers showing the order in which the reloads should
1603 static short reload_order[MAX_RELOADS];
1605 /* This is used to keep track of the spill regs used in one insn. */
1606 static HARD_REG_SET used_spill_regs_local;
1608 /* We decided to spill hard register SPILLED, which has a size of
1609 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1610 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1611 update SPILL_COST/SPILL_ADD_COST. */
1614 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1616 int r = reg_renumber[reg];
1617 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1619 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1620 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1623 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1625 spill_add_cost[r] -= REG_FREQ (reg);
1627 spill_cost[r + nregs] -= REG_FREQ (reg);
1630 /* Find reload register to use for reload number ORDER. */
1633 find_reg (struct insn_chain *chain, int order)
1635 int rnum = reload_order[order];
1636 struct reload *rl = rld + rnum;
1637 int best_cost = INT_MAX;
1641 HARD_REG_SET not_usable;
1642 HARD_REG_SET used_by_other_reload;
1644 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1645 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1646 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1648 CLEAR_HARD_REG_SET (used_by_other_reload);
1649 for (k = 0; k < order; k++)
1651 int other = reload_order[k];
1653 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1654 for (j = 0; j < rld[other].nregs; j++)
1655 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1658 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1660 unsigned int regno = i;
1662 if (! TEST_HARD_REG_BIT (not_usable, regno)
1663 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1664 && HARD_REGNO_MODE_OK (regno, rl->mode))
1666 int this_cost = spill_cost[regno];
1668 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1670 for (j = 1; j < this_nregs; j++)
1672 this_cost += spill_add_cost[regno + j];
1673 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1674 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1679 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1681 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1683 if (this_cost < best_cost
1684 /* Among registers with equal cost, prefer caller-saved ones, or
1685 use REG_ALLOC_ORDER if it is defined. */
1686 || (this_cost == best_cost
1687 #ifdef REG_ALLOC_ORDER
1688 && (inv_reg_alloc_order[regno]
1689 < inv_reg_alloc_order[best_reg])
1691 && call_used_regs[regno]
1692 && ! call_used_regs[best_reg]
1697 best_cost = this_cost;
1705 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1707 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1708 rl->regno = best_reg;
1710 EXECUTE_IF_SET_IN_REG_SET
1711 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1713 count_spilled_pseudo (best_reg, rl->nregs, j);
1716 EXECUTE_IF_SET_IN_REG_SET
1717 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1719 count_spilled_pseudo (best_reg, rl->nregs, j);
1722 for (i = 0; i < rl->nregs; i++)
1724 if (spill_cost[best_reg + i] != 0
1725 || spill_add_cost[best_reg + i] != 0)
1727 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1732 /* Find more reload regs to satisfy the remaining need of an insn, which
1734 Do it by ascending class number, since otherwise a reg
1735 might be spilled for a big class and might fail to count
1736 for a smaller class even though it belongs to that class. */
1739 find_reload_regs (struct insn_chain *chain)
1743 /* In order to be certain of getting the registers we need,
1744 we must sort the reloads into order of increasing register class.
1745 Then our grabbing of reload registers will parallel the process
1746 that provided the reload registers. */
1747 for (i = 0; i < chain->n_reloads; i++)
1749 /* Show whether this reload already has a hard reg. */
1750 if (chain->rld[i].reg_rtx)
1752 int regno = REGNO (chain->rld[i].reg_rtx);
1753 chain->rld[i].regno = regno;
1755 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1758 chain->rld[i].regno = -1;
1759 reload_order[i] = i;
1762 n_reloads = chain->n_reloads;
1763 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1765 CLEAR_HARD_REG_SET (used_spill_regs_local);
1768 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1770 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1772 /* Compute the order of preference for hard registers to spill. */
1774 order_regs_for_reload (chain);
1776 for (i = 0; i < n_reloads; i++)
1778 int r = reload_order[i];
1780 /* Ignore reloads that got marked inoperative. */
1781 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1782 && ! rld[r].optional
1783 && rld[r].regno == -1)
1784 if (! find_reg (chain, i))
1786 spill_failure (chain->insn, rld[r].class);
1792 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1793 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1795 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1799 select_reload_regs (void)
1801 struct insn_chain *chain;
1803 /* Try to satisfy the needs for each insn. */
1804 for (chain = insns_need_reload; chain != 0;
1805 chain = chain->next_need_reload)
1806 find_reload_regs (chain);
1809 /* Delete all insns that were inserted by emit_caller_save_insns during
1812 delete_caller_save_insns (void)
1814 struct insn_chain *c = reload_insn_chain;
1818 while (c != 0 && c->is_caller_save_insn)
1820 struct insn_chain *next = c->next;
1823 if (c == reload_insn_chain)
1824 reload_insn_chain = next;
1828 next->prev = c->prev;
1830 c->prev->next = next;
1831 c->next = unused_insn_chains;
1832 unused_insn_chains = c;
1840 /* Handle the failure to find a register to spill.
1841 INSN should be one of the insns which needed this particular spill reg. */
1844 spill_failure (rtx insn, enum reg_class class)
1846 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1847 if (asm_noperands (PATTERN (insn)) >= 0)
1848 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1849 reg_class_names[class]);
1852 error ("unable to find a register to spill in class `%s'",
1853 reg_class_names[class]);
1854 fatal_insn ("this is the insn:", insn);
1858 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1859 data that is dead in INSN. */
1862 delete_dead_insn (rtx insn)
1864 rtx prev = prev_real_insn (insn);
1867 /* If the previous insn sets a register that dies in our insn, delete it
1869 if (prev && GET_CODE (PATTERN (prev)) == SET
1870 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1871 && reg_mentioned_p (prev_dest, PATTERN (insn))
1872 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1873 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1874 delete_dead_insn (prev);
1876 PUT_CODE (insn, NOTE);
1877 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1878 NOTE_SOURCE_FILE (insn) = 0;
1881 /* Modify the home of pseudo-reg I.
1882 The new home is present in reg_renumber[I].
1884 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1885 or it may be -1, meaning there is none or it is not relevant.
1886 This is used so that all pseudos spilled from a given hard reg
1887 can share one stack slot. */
1890 alter_reg (int i, int from_reg)
1892 /* When outputting an inline function, this can happen
1893 for a reg that isn't actually used. */
1894 if (regno_reg_rtx[i] == 0)
1897 /* If the reg got changed to a MEM at rtl-generation time,
1899 if (GET_CODE (regno_reg_rtx[i]) != REG)
1902 /* Modify the reg-rtx to contain the new hard reg
1903 number or else to contain its pseudo reg number. */
1904 REGNO (regno_reg_rtx[i])
1905 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1907 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1908 allocate a stack slot for it. */
1910 if (reg_renumber[i] < 0
1911 && REG_N_REFS (i) > 0
1912 && reg_equiv_constant[i] == 0
1913 && reg_equiv_memory_loc[i] == 0)
1916 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1917 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1920 /* Each pseudo reg has an inherent size which comes from its own mode,
1921 and a total size which provides room for paradoxical subregs
1922 which refer to the pseudo reg in wider modes.
1924 We can use a slot already allocated if it provides both
1925 enough inherent space and enough total space.
1926 Otherwise, we allocate a new slot, making sure that it has no less
1927 inherent space, and no less total space, then the previous slot. */
1930 /* No known place to spill from => no slot to reuse. */
1931 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1932 inherent_size == total_size ? 0 : -1);
1933 if (BYTES_BIG_ENDIAN)
1934 /* Cancel the big-endian correction done in assign_stack_local.
1935 Get the address of the beginning of the slot.
1936 This is so we can do a big-endian correction unconditionally
1938 adjust = inherent_size - total_size;
1940 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1942 /* Nothing can alias this slot except this pseudo. */
1943 set_mem_alias_set (x, new_alias_set ());
1946 /* Reuse a stack slot if possible. */
1947 else if (spill_stack_slot[from_reg] != 0
1948 && spill_stack_slot_width[from_reg] >= total_size
1949 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1951 x = spill_stack_slot[from_reg];
1953 /* Allocate a bigger slot. */
1956 /* Compute maximum size needed, both for inherent size
1957 and for total size. */
1958 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1961 if (spill_stack_slot[from_reg])
1963 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1965 mode = GET_MODE (spill_stack_slot[from_reg]);
1966 if (spill_stack_slot_width[from_reg] > total_size)
1967 total_size = spill_stack_slot_width[from_reg];
1970 /* Make a slot with that size. */
1971 x = assign_stack_local (mode, total_size,
1972 inherent_size == total_size ? 0 : -1);
1975 /* All pseudos mapped to this slot can alias each other. */
1976 if (spill_stack_slot[from_reg])
1977 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
1979 set_mem_alias_set (x, new_alias_set ());
1981 if (BYTES_BIG_ENDIAN)
1983 /* Cancel the big-endian correction done in assign_stack_local.
1984 Get the address of the beginning of the slot.
1985 This is so we can do a big-endian correction unconditionally
1987 adjust = GET_MODE_SIZE (mode) - total_size;
1990 = adjust_address_nv (x, mode_for_size (total_size
1996 spill_stack_slot[from_reg] = stack_slot;
1997 spill_stack_slot_width[from_reg] = total_size;
2000 /* On a big endian machine, the "address" of the slot
2001 is the address of the low part that fits its inherent mode. */
2002 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2003 adjust += (total_size - inherent_size);
2005 /* If we have any adjustment to make, or if the stack slot is the
2006 wrong mode, make a new stack slot. */
2007 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2009 /* If we have a decl for the original register, set it for the
2010 memory. If this is a shared MEM, make a copy. */
2011 if (REG_EXPR (regno_reg_rtx[i])
2012 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2014 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2016 /* We can do this only for the DECLs home pseudo, not for
2017 any copies of it, since otherwise when the stack slot
2018 is reused, nonoverlapping_memrefs_p might think they
2020 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2022 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2025 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2029 /* Save the stack slot for later. */
2030 reg_equiv_memory_loc[i] = x;
2034 /* Mark the slots in regs_ever_live for the hard regs
2035 used by pseudo-reg number REGNO. */
2038 mark_home_live (int regno)
2042 i = reg_renumber[regno];
2045 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2047 regs_ever_live[i++] = 1;
2050 /* This function handles the tracking of elimination offsets around branches.
2052 X is a piece of RTL being scanned.
2054 INSN is the insn that it came from, if any.
2056 INITIAL_P is nonzero if we are to set the offset to be the initial
2057 offset and zero if we are setting the offset of the label to be the
2061 set_label_offsets (rtx x, rtx insn, int initial_p)
2063 enum rtx_code code = GET_CODE (x);
2066 struct elim_table *p;
2071 if (LABEL_REF_NONLOCAL_P (x))
2076 /* ... fall through ... */
2079 /* If we know nothing about this label, set the desired offsets. Note
2080 that this sets the offset at a label to be the offset before a label
2081 if we don't know anything about the label. This is not correct for
2082 the label after a BARRIER, but is the best guess we can make. If
2083 we guessed wrong, we will suppress an elimination that might have
2084 been possible had we been able to guess correctly. */
2086 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2088 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2089 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2090 = (initial_p ? reg_eliminate[i].initial_offset
2091 : reg_eliminate[i].offset);
2092 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2095 /* Otherwise, if this is the definition of a label and it is
2096 preceded by a BARRIER, set our offsets to the known offset of
2100 && (tem = prev_nonnote_insn (insn)) != 0
2101 && GET_CODE (tem) == BARRIER)
2102 set_offsets_for_label (insn);
2104 /* If neither of the above cases is true, compare each offset
2105 with those previously recorded and suppress any eliminations
2106 where the offsets disagree. */
2108 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2109 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2110 != (initial_p ? reg_eliminate[i].initial_offset
2111 : reg_eliminate[i].offset))
2112 reg_eliminate[i].can_eliminate = 0;
2117 set_label_offsets (PATTERN (insn), insn, initial_p);
2119 /* ... fall through ... */
2123 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2124 and hence must have all eliminations at their initial offsets. */
2125 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2126 if (REG_NOTE_KIND (tem) == REG_LABEL)
2127 set_label_offsets (XEXP (tem, 0), insn, 1);
2133 /* Each of the labels in the parallel or address vector must be
2134 at their initial offsets. We want the first field for PARALLEL
2135 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2137 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2138 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2143 /* We only care about setting PC. If the source is not RETURN,
2144 IF_THEN_ELSE, or a label, disable any eliminations not at
2145 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2146 isn't one of those possibilities. For branches to a label,
2147 call ourselves recursively.
2149 Note that this can disable elimination unnecessarily when we have
2150 a non-local goto since it will look like a non-constant jump to
2151 someplace in the current function. This isn't a significant
2152 problem since such jumps will normally be when all elimination
2153 pairs are back to their initial offsets. */
2155 if (SET_DEST (x) != pc_rtx)
2158 switch (GET_CODE (SET_SRC (x)))
2165 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2169 tem = XEXP (SET_SRC (x), 1);
2170 if (GET_CODE (tem) == LABEL_REF)
2171 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2172 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2175 tem = XEXP (SET_SRC (x), 2);
2176 if (GET_CODE (tem) == LABEL_REF)
2177 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2178 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2186 /* If we reach here, all eliminations must be at their initial
2187 offset because we are doing a jump to a variable address. */
2188 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2189 if (p->offset != p->initial_offset)
2190 p->can_eliminate = 0;
2198 /* Scan X and replace any eliminable registers (such as fp) with a
2199 replacement (such as sp), plus an offset.
2201 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2202 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2203 MEM, we are allowed to replace a sum of a register and the constant zero
2204 with the register, which we cannot do outside a MEM. In addition, we need
2205 to record the fact that a register is referenced outside a MEM.
2207 If INSN is an insn, it is the insn containing X. If we replace a REG
2208 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2209 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2210 the REG is being modified.
2212 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2213 That's used when we eliminate in expressions stored in notes.
2214 This means, do not set ref_outside_mem even if the reference
2217 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2218 replacements done assuming all offsets are at their initial values. If
2219 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2220 encounter, return the actual location so that find_reloads will do
2221 the proper thing. */
2224 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2226 enum rtx_code code = GET_CODE (x);
2227 struct elim_table *ep;
2234 if (! current_function_decl)
2254 /* This is only for the benefit of the debugging backends, which call
2255 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2256 removed after CSE. */
2257 new = eliminate_regs (XEXP (x, 0), 0, insn);
2258 if (GET_CODE (new) == MEM)
2259 return XEXP (new, 0);
2265 /* First handle the case where we encounter a bare register that
2266 is eliminable. Replace it with a PLUS. */
2267 if (regno < FIRST_PSEUDO_REGISTER)
2269 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2271 if (ep->from_rtx == x && ep->can_eliminate)
2272 return plus_constant (ep->to_rtx, ep->previous_offset);
2275 else if (reg_renumber && reg_renumber[regno] < 0
2276 && reg_equiv_constant && reg_equiv_constant[regno]
2277 && ! CONSTANT_P (reg_equiv_constant[regno]))
2278 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2282 /* You might think handling MINUS in a manner similar to PLUS is a
2283 good idea. It is not. It has been tried multiple times and every
2284 time the change has had to have been reverted.
2286 Other parts of reload know a PLUS is special (gen_reload for example)
2287 and require special code to handle code a reloaded PLUS operand.
2289 Also consider backends where the flags register is clobbered by a
2290 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2291 lea instruction comes to mind). If we try to reload a MINUS, we
2292 may kill the flags register that was holding a useful value.
2294 So, please before trying to handle MINUS, consider reload as a
2295 whole instead of this little section as well as the backend issues. */
2297 /* If this is the sum of an eliminable register and a constant, rework
2299 if (GET_CODE (XEXP (x, 0)) == REG
2300 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2301 && CONSTANT_P (XEXP (x, 1)))
2303 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2305 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2307 /* The only time we want to replace a PLUS with a REG (this
2308 occurs when the constant operand of the PLUS is the negative
2309 of the offset) is when we are inside a MEM. We won't want
2310 to do so at other times because that would change the
2311 structure of the insn in a way that reload can't handle.
2312 We special-case the commonest situation in
2313 eliminate_regs_in_insn, so just replace a PLUS with a
2314 PLUS here, unless inside a MEM. */
2315 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2316 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2319 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2320 plus_constant (XEXP (x, 1),
2321 ep->previous_offset));
2324 /* If the register is not eliminable, we are done since the other
2325 operand is a constant. */
2329 /* If this is part of an address, we want to bring any constant to the
2330 outermost PLUS. We will do this by doing register replacement in
2331 our operands and seeing if a constant shows up in one of them.
2333 Note that there is no risk of modifying the structure of the insn,
2334 since we only get called for its operands, thus we are either
2335 modifying the address inside a MEM, or something like an address
2336 operand of a load-address insn. */
2339 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2340 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2342 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2344 /* If one side is a PLUS and the other side is a pseudo that
2345 didn't get a hard register but has a reg_equiv_constant,
2346 we must replace the constant here since it may no longer
2347 be in the position of any operand. */
2348 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2349 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2350 && reg_renumber[REGNO (new1)] < 0
2351 && reg_equiv_constant != 0
2352 && reg_equiv_constant[REGNO (new1)] != 0)
2353 new1 = reg_equiv_constant[REGNO (new1)];
2354 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2355 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2356 && reg_renumber[REGNO (new0)] < 0
2357 && reg_equiv_constant[REGNO (new0)] != 0)
2358 new0 = reg_equiv_constant[REGNO (new0)];
2360 new = form_sum (new0, new1);
2362 /* As above, if we are not inside a MEM we do not want to
2363 turn a PLUS into something else. We might try to do so here
2364 for an addition of 0 if we aren't optimizing. */
2365 if (! mem_mode && GET_CODE (new) != PLUS)
2366 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2374 /* If this is the product of an eliminable register and a
2375 constant, apply the distribute law and move the constant out
2376 so that we have (plus (mult ..) ..). This is needed in order
2377 to keep load-address insns valid. This case is pathological.
2378 We ignore the possibility of overflow here. */
2379 if (GET_CODE (XEXP (x, 0)) == REG
2380 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2381 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2382 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2384 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2387 /* Refs inside notes don't count for this purpose. */
2388 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2389 || GET_CODE (insn) == INSN_LIST)))
2390 ep->ref_outside_mem = 1;
2393 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2394 ep->previous_offset * INTVAL (XEXP (x, 1)));
2397 /* ... fall through ... */
2401 /* See comments before PLUS about handling MINUS. */
2403 case DIV: case UDIV:
2404 case MOD: case UMOD:
2405 case AND: case IOR: case XOR:
2406 case ROTATERT: case ROTATE:
2407 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2409 case GE: case GT: case GEU: case GTU:
2410 case LE: case LT: case LEU: case LTU:
2412 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2414 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2416 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2417 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2422 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2425 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2426 if (new != XEXP (x, 0))
2428 /* If this is a REG_DEAD note, it is not valid anymore.
2429 Using the eliminated version could result in creating a
2430 REG_DEAD note for the stack or frame pointer. */
2431 if (GET_MODE (x) == REG_DEAD)
2433 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2436 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2440 /* ... fall through ... */
2443 /* Now do eliminations in the rest of the chain. If this was
2444 an EXPR_LIST, this might result in allocating more memory than is
2445 strictly needed, but it simplifies the code. */
2448 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2449 if (new != XEXP (x, 1))
2451 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2459 case STRICT_LOW_PART:
2461 case SIGN_EXTEND: case ZERO_EXTEND:
2462 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2463 case FLOAT: case FIX:
2464 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2472 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2473 if (new != XEXP (x, 0))
2474 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2478 /* Similar to above processing, but preserve SUBREG_BYTE.
2479 Convert (subreg (mem)) to (mem) if not paradoxical.
2480 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2481 pseudo didn't get a hard reg, we must replace this with the
2482 eliminated version of the memory location because push_reload
2483 may do the replacement in certain circumstances. */
2484 if (GET_CODE (SUBREG_REG (x)) == REG
2485 && (GET_MODE_SIZE (GET_MODE (x))
2486 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2487 && reg_equiv_memory_loc != 0
2488 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2490 new = SUBREG_REG (x);
2493 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2495 if (new != SUBREG_REG (x))
2497 int x_size = GET_MODE_SIZE (GET_MODE (x));
2498 int new_size = GET_MODE_SIZE (GET_MODE (new));
2500 if (GET_CODE (new) == MEM
2501 && ((x_size < new_size
2502 #ifdef WORD_REGISTER_OPERATIONS
2503 /* On these machines, combine can create rtl of the form
2504 (set (subreg:m1 (reg:m2 R) 0) ...)
2505 where m1 < m2, and expects something interesting to
2506 happen to the entire word. Moreover, it will use the
2507 (reg:m2 R) later, expecting all bits to be preserved.
2508 So if the number of words is the same, preserve the
2509 subreg so that push_reload can see it. */
2510 && ! ((x_size - 1) / UNITS_PER_WORD
2511 == (new_size -1 ) / UNITS_PER_WORD)
2514 || x_size == new_size)
2516 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2518 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2524 /* This is only for the benefit of the debugging backends, which call
2525 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2526 removed after CSE. */
2527 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2528 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2530 /* Our only special processing is to pass the mode of the MEM to our
2531 recursive call and copy the flags. While we are here, handle this
2532 case more efficiently. */
2534 replace_equiv_address_nv (x,
2535 eliminate_regs (XEXP (x, 0),
2536 GET_MODE (x), insn));
2539 /* Handle insn_list USE that a call to a pure function may generate. */
2540 new = eliminate_regs (XEXP (x, 0), 0, insn);
2541 if (new != XEXP (x, 0))
2542 return gen_rtx_USE (GET_MODE (x), new);
2554 /* Process each of our operands recursively. If any have changed, make a
2556 fmt = GET_RTX_FORMAT (code);
2557 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2561 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2562 if (new != XEXP (x, i) && ! copied)
2564 rtx new_x = rtx_alloc (code);
2565 memcpy (new_x, x, RTX_SIZE (code));
2571 else if (*fmt == 'E')
2574 for (j = 0; j < XVECLEN (x, i); j++)
2576 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2577 if (new != XVECEXP (x, i, j) && ! copied_vec)
2579 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2583 rtx new_x = rtx_alloc (code);
2584 memcpy (new_x, x, RTX_SIZE (code));
2588 XVEC (x, i) = new_v;
2591 XVECEXP (x, i, j) = new;
2599 /* Scan rtx X for modifications of elimination target registers. Update
2600 the table of eliminables to reflect the changed state. MEM_MODE is
2601 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2604 elimination_effects (rtx x, enum machine_mode mem_mode)
2606 enum rtx_code code = GET_CODE (x);
2607 struct elim_table *ep;
2634 /* First handle the case where we encounter a bare register that
2635 is eliminable. Replace it with a PLUS. */
2636 if (regno < FIRST_PSEUDO_REGISTER)
2638 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2640 if (ep->from_rtx == x && ep->can_eliminate)
2643 ep->ref_outside_mem = 1;
2648 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2649 && reg_equiv_constant[regno]
2650 && ! function_invariant_p (reg_equiv_constant[regno]))
2651 elimination_effects (reg_equiv_constant[regno], mem_mode);
2660 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2661 if (ep->to_rtx == XEXP (x, 0))
2663 int size = GET_MODE_SIZE (mem_mode);
2665 /* If more bytes than MEM_MODE are pushed, account for them. */
2666 #ifdef PUSH_ROUNDING
2667 if (ep->to_rtx == stack_pointer_rtx)
2668 size = PUSH_ROUNDING (size);
2670 if (code == PRE_DEC || code == POST_DEC)
2672 else if (code == PRE_INC || code == POST_INC)
2674 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2675 && GET_CODE (XEXP (x, 1)) == PLUS
2676 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2677 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2678 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2681 /* These two aren't unary operators. */
2682 if (code == POST_MODIFY || code == PRE_MODIFY)
2685 /* Fall through to generic unary operation case. */
2686 case STRICT_LOW_PART:
2688 case SIGN_EXTEND: case ZERO_EXTEND:
2689 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2690 case FLOAT: case FIX:
2691 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2699 elimination_effects (XEXP (x, 0), mem_mode);
2703 if (GET_CODE (SUBREG_REG (x)) == REG
2704 && (GET_MODE_SIZE (GET_MODE (x))
2705 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2706 && reg_equiv_memory_loc != 0
2707 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2710 elimination_effects (SUBREG_REG (x), mem_mode);
2714 /* If using a register that is the source of an eliminate we still
2715 think can be performed, note it cannot be performed since we don't
2716 know how this register is used. */
2717 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2718 if (ep->from_rtx == XEXP (x, 0))
2719 ep->can_eliminate = 0;
2721 elimination_effects (XEXP (x, 0), mem_mode);
2725 /* If clobbering a register that is the replacement register for an
2726 elimination we still think can be performed, note that it cannot
2727 be performed. Otherwise, we need not be concerned about it. */
2728 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2729 if (ep->to_rtx == XEXP (x, 0))
2730 ep->can_eliminate = 0;
2732 elimination_effects (XEXP (x, 0), mem_mode);
2736 /* Check for setting a register that we know about. */
2737 if (GET_CODE (SET_DEST (x)) == REG)
2739 /* See if this is setting the replacement register for an
2742 If DEST is the hard frame pointer, we do nothing because we
2743 assume that all assignments to the frame pointer are for
2744 non-local gotos and are being done at a time when they are valid
2745 and do not disturb anything else. Some machines want to
2746 eliminate a fake argument pointer (or even a fake frame pointer)
2747 with either the real frame or the stack pointer. Assignments to
2748 the hard frame pointer must not prevent this elimination. */
2750 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2752 if (ep->to_rtx == SET_DEST (x)
2753 && SET_DEST (x) != hard_frame_pointer_rtx)
2755 /* If it is being incremented, adjust the offset. Otherwise,
2756 this elimination can't be done. */
2757 rtx src = SET_SRC (x);
2759 if (GET_CODE (src) == PLUS
2760 && XEXP (src, 0) == SET_DEST (x)
2761 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2762 ep->offset -= INTVAL (XEXP (src, 1));
2764 ep->can_eliminate = 0;
2768 elimination_effects (SET_DEST (x), 0);
2769 elimination_effects (SET_SRC (x), 0);
2773 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2776 /* Our only special processing is to pass the mode of the MEM to our
2778 elimination_effects (XEXP (x, 0), GET_MODE (x));
2785 fmt = GET_RTX_FORMAT (code);
2786 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2789 elimination_effects (XEXP (x, i), mem_mode);
2790 else if (*fmt == 'E')
2791 for (j = 0; j < XVECLEN (x, i); j++)
2792 elimination_effects (XVECEXP (x, i, j), mem_mode);
2796 /* Descend through rtx X and verify that no references to eliminable registers
2797 remain. If any do remain, mark the involved register as not
2801 check_eliminable_occurrences (rtx x)
2810 code = GET_CODE (x);
2812 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2814 struct elim_table *ep;
2816 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2817 if (ep->from_rtx == x && ep->can_eliminate)
2818 ep->can_eliminate = 0;
2822 fmt = GET_RTX_FORMAT (code);
2823 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2826 check_eliminable_occurrences (XEXP (x, i));
2827 else if (*fmt == 'E')
2830 for (j = 0; j < XVECLEN (x, i); j++)
2831 check_eliminable_occurrences (XVECEXP (x, i, j));
2836 /* Scan INSN and eliminate all eliminable registers in it.
2838 If REPLACE is nonzero, do the replacement destructively. Also
2839 delete the insn as dead it if it is setting an eliminable register.
2841 If REPLACE is zero, do all our allocations in reload_obstack.
2843 If no eliminations were done and this insn doesn't require any elimination
2844 processing (these are not identical conditions: it might be updating sp,
2845 but not referencing fp; this needs to be seen during reload_as_needed so
2846 that the offset between fp and sp can be taken into consideration), zero
2847 is returned. Otherwise, 1 is returned. */
2850 eliminate_regs_in_insn (rtx insn, int replace)
2852 int icode = recog_memoized (insn);
2853 rtx old_body = PATTERN (insn);
2854 int insn_is_asm = asm_noperands (old_body) >= 0;
2855 rtx old_set = single_set (insn);
2859 rtx substed_operand[MAX_RECOG_OPERANDS];
2860 rtx orig_operand[MAX_RECOG_OPERANDS];
2861 struct elim_table *ep;
2863 if (! insn_is_asm && icode < 0)
2865 if (GET_CODE (PATTERN (insn)) == USE
2866 || GET_CODE (PATTERN (insn)) == CLOBBER
2867 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2868 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2869 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2874 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2875 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2877 /* Check for setting an eliminable register. */
2878 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2879 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2881 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2882 /* If this is setting the frame pointer register to the
2883 hardware frame pointer register and this is an elimination
2884 that will be done (tested above), this insn is really
2885 adjusting the frame pointer downward to compensate for
2886 the adjustment done before a nonlocal goto. */
2887 if (ep->from == FRAME_POINTER_REGNUM
2888 && ep->to == HARD_FRAME_POINTER_REGNUM)
2890 rtx base = SET_SRC (old_set);
2891 rtx base_insn = insn;
2892 HOST_WIDE_INT offset = 0;
2894 while (base != ep->to_rtx)
2896 rtx prev_insn, prev_set;
2898 if (GET_CODE (base) == PLUS
2899 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2901 offset += INTVAL (XEXP (base, 1));
2902 base = XEXP (base, 0);
2904 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2905 && (prev_set = single_set (prev_insn)) != 0
2906 && rtx_equal_p (SET_DEST (prev_set), base))
2908 base = SET_SRC (prev_set);
2909 base_insn = prev_insn;
2915 if (base == ep->to_rtx)
2918 = plus_constant (ep->to_rtx, offset - ep->offset);
2920 new_body = old_body;
2923 new_body = copy_insn (old_body);
2924 if (REG_NOTES (insn))
2925 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2927 PATTERN (insn) = new_body;
2928 old_set = single_set (insn);
2930 /* First see if this insn remains valid when we
2931 make the change. If not, keep the INSN_CODE
2932 the same and let reload fit it up. */
2933 validate_change (insn, &SET_SRC (old_set), src, 1);
2934 validate_change (insn, &SET_DEST (old_set),
2936 if (! apply_change_group ())
2938 SET_SRC (old_set) = src;
2939 SET_DEST (old_set) = ep->to_rtx;
2948 /* In this case this insn isn't serving a useful purpose. We
2949 will delete it in reload_as_needed once we know that this
2950 elimination is, in fact, being done.
2952 If REPLACE isn't set, we can't delete this insn, but needn't
2953 process it since it won't be used unless something changes. */
2956 delete_dead_insn (insn);
2964 /* We allow one special case which happens to work on all machines we
2965 currently support: a single set with the source being a PLUS of an
2966 eliminable register and a constant. */
2968 && GET_CODE (SET_DEST (old_set)) == REG
2969 && GET_CODE (SET_SRC (old_set)) == PLUS
2970 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2971 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2972 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2974 rtx reg = XEXP (SET_SRC (old_set), 0);
2975 HOST_WIDE_INT offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2977 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2978 if (ep->from_rtx == reg && ep->can_eliminate)
2980 offset += ep->offset;
2985 /* We assume here that if we need a PARALLEL with
2986 CLOBBERs for this assignment, we can do with the
2987 MATCH_SCRATCHes that add_clobbers allocates.
2988 There's not much we can do if that doesn't work. */
2989 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2993 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
2996 rtvec vec = rtvec_alloc (num_clobbers + 1);
2998 vec->elem[0] = PATTERN (insn);
2999 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3000 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3002 if (INSN_CODE (insn) < 0)
3007 new_body = old_body;
3010 new_body = copy_insn (old_body);
3011 if (REG_NOTES (insn))
3012 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3014 PATTERN (insn) = new_body;
3015 old_set = single_set (insn);
3017 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3018 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3021 /* This can't have an effect on elimination offsets, so skip right
3027 /* Determine the effects of this insn on elimination offsets. */
3028 elimination_effects (old_body, 0);
3030 /* Eliminate all eliminable registers occurring in operands that
3031 can be handled by reload. */
3032 extract_insn (insn);
3033 for (i = 0; i < recog_data.n_operands; i++)
3035 orig_operand[i] = recog_data.operand[i];
3036 substed_operand[i] = recog_data.operand[i];
3038 /* For an asm statement, every operand is eliminable. */
3039 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3041 /* Check for setting a register that we know about. */
3042 if (recog_data.operand_type[i] != OP_IN
3043 && GET_CODE (orig_operand[i]) == REG)
3045 /* If we are assigning to a register that can be eliminated, it
3046 must be as part of a PARALLEL, since the code above handles
3047 single SETs. We must indicate that we can no longer
3048 eliminate this reg. */
3049 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3051 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3052 ep->can_eliminate = 0;
3055 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3056 replace ? insn : NULL_RTX);
3057 if (substed_operand[i] != orig_operand[i])
3059 /* Terminate the search in check_eliminable_occurrences at
3061 *recog_data.operand_loc[i] = 0;
3063 /* If an output operand changed from a REG to a MEM and INSN is an
3064 insn, write a CLOBBER insn. */
3065 if (recog_data.operand_type[i] != OP_IN
3066 && GET_CODE (orig_operand[i]) == REG
3067 && GET_CODE (substed_operand[i]) == MEM
3069 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3074 for (i = 0; i < recog_data.n_dups; i++)
3075 *recog_data.dup_loc[i]
3076 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3078 /* If any eliminable remain, they aren't eliminable anymore. */
3079 check_eliminable_occurrences (old_body);
3081 /* Substitute the operands; the new values are in the substed_operand
3083 for (i = 0; i < recog_data.n_operands; i++)
3084 *recog_data.operand_loc[i] = substed_operand[i];
3085 for (i = 0; i < recog_data.n_dups; i++)
3086 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3088 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3089 re-recognize the insn. We do this in case we had a simple addition
3090 but now can do this as a load-address. This saves an insn in this
3092 If re-recognition fails, the old insn code number will still be used,
3093 and some register operands may have changed into PLUS expressions.
3094 These will be handled by find_reloads by loading them into a register
3099 /* If we aren't replacing things permanently and we changed something,
3100 make another copy to ensure that all the RTL is new. Otherwise
3101 things can go wrong if find_reload swaps commutative operands
3102 and one is inside RTL that has been copied while the other is not. */
3103 new_body = old_body;
3106 new_body = copy_insn (old_body);
3107 if (REG_NOTES (insn))
3108 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3110 PATTERN (insn) = new_body;
3112 /* If we had a move insn but now we don't, rerecognize it. This will
3113 cause spurious re-recognition if the old move had a PARALLEL since
3114 the new one still will, but we can't call single_set without
3115 having put NEW_BODY into the insn and the re-recognition won't
3116 hurt in this rare case. */
3117 /* ??? Why this huge if statement - why don't we just rerecognize the
3121 && ((GET_CODE (SET_SRC (old_set)) == REG
3122 && (GET_CODE (new_body) != SET
3123 || GET_CODE (SET_SRC (new_body)) != REG))
3124 /* If this was a load from or store to memory, compare
3125 the MEM in recog_data.operand to the one in the insn.
3126 If they are not equal, then rerecognize the insn. */
3128 && ((GET_CODE (SET_SRC (old_set)) == MEM
3129 && SET_SRC (old_set) != recog_data.operand[1])
3130 || (GET_CODE (SET_DEST (old_set)) == MEM
3131 && SET_DEST (old_set) != recog_data.operand[0])))
3132 /* If this was an add insn before, rerecognize. */
3133 || GET_CODE (SET_SRC (old_set)) == PLUS))
3135 int new_icode = recog (PATTERN (insn), insn, 0);
3137 INSN_CODE (insn) = icode;
3141 /* Restore the old body. If there were any changes to it, we made a copy
3142 of it while the changes were still in place, so we'll correctly return
3143 a modified insn below. */
3146 /* Restore the old body. */
3147 for (i = 0; i < recog_data.n_operands; i++)
3148 *recog_data.operand_loc[i] = orig_operand[i];
3149 for (i = 0; i < recog_data.n_dups; i++)
3150 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3153 /* Update all elimination pairs to reflect the status after the current
3154 insn. The changes we make were determined by the earlier call to
3155 elimination_effects.
3157 We also detect cases where register elimination cannot be done,
3158 namely, if a register would be both changed and referenced outside a MEM
3159 in the resulting insn since such an insn is often undefined and, even if
3160 not, we cannot know what meaning will be given to it. Note that it is
3161 valid to have a register used in an address in an insn that changes it
3162 (presumably with a pre- or post-increment or decrement).
3164 If anything changes, return nonzero. */
3166 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3168 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3169 ep->can_eliminate = 0;
3171 ep->ref_outside_mem = 0;
3173 if (ep->previous_offset != ep->offset)
3178 /* If we changed something, perform elimination in REG_NOTES. This is
3179 needed even when REPLACE is zero because a REG_DEAD note might refer
3180 to a register that we eliminate and could cause a different number
3181 of spill registers to be needed in the final reload pass than in
3183 if (val && REG_NOTES (insn) != 0)
3184 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3189 /* Loop through all elimination pairs.
3190 Recalculate the number not at initial offset.
3192 Compute the maximum offset (minimum offset if the stack does not
3193 grow downward) for each elimination pair. */
3196 update_eliminable_offsets (void)
3198 struct elim_table *ep;
3200 num_not_at_initial_offset = 0;
3201 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3203 ep->previous_offset = ep->offset;
3204 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3205 num_not_at_initial_offset++;
3209 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3210 replacement we currently believe is valid, mark it as not eliminable if X
3211 modifies DEST in any way other than by adding a constant integer to it.
3213 If DEST is the frame pointer, we do nothing because we assume that
3214 all assignments to the hard frame pointer are nonlocal gotos and are being
3215 done at a time when they are valid and do not disturb anything else.
3216 Some machines want to eliminate a fake argument pointer with either the
3217 frame or stack pointer. Assignments to the hard frame pointer must not
3218 prevent this elimination.
3220 Called via note_stores from reload before starting its passes to scan
3221 the insns of the function. */
3224 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3228 /* A SUBREG of a hard register here is just changing its mode. We should
3229 not see a SUBREG of an eliminable hard register, but check just in
3231 if (GET_CODE (dest) == SUBREG)
3232 dest = SUBREG_REG (dest);
3234 if (dest == hard_frame_pointer_rtx)
3237 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3238 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3239 && (GET_CODE (x) != SET
3240 || GET_CODE (SET_SRC (x)) != PLUS
3241 || XEXP (SET_SRC (x), 0) != dest
3242 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3244 reg_eliminate[i].can_eliminate_previous
3245 = reg_eliminate[i].can_eliminate = 0;
3250 /* Verify that the initial elimination offsets did not change since the
3251 last call to set_initial_elim_offsets. This is used to catch cases
3252 where something illegal happened during reload_as_needed that could
3253 cause incorrect code to be generated if we did not check for it. */
3256 verify_initial_elim_offsets (void)
3260 #ifdef ELIMINABLE_REGS
3261 struct elim_table *ep;
3263 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3265 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3266 if (t != ep->initial_offset)
3270 INITIAL_FRAME_POINTER_OFFSET (t);
3271 if (t != reg_eliminate[0].initial_offset)
3276 /* Reset all offsets on eliminable registers to their initial values. */
3279 set_initial_elim_offsets (void)
3281 struct elim_table *ep = reg_eliminate;
3283 #ifdef ELIMINABLE_REGS
3284 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3286 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3287 ep->previous_offset = ep->offset = ep->initial_offset;
3290 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3291 ep->previous_offset = ep->offset = ep->initial_offset;
3294 num_not_at_initial_offset = 0;
3297 /* Initialize the known label offsets.
3298 Set a known offset for each forced label to be at the initial offset
3299 of each elimination. We do this because we assume that all
3300 computed jumps occur from a location where each elimination is
3301 at its initial offset.
3302 For all other labels, show that we don't know the offsets. */
3305 set_initial_label_offsets (void)
3308 memset (offsets_known_at, 0, num_labels);
3310 for (x = forced_labels; x; x = XEXP (x, 1))
3312 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3315 /* Set all elimination offsets to the known values for the code label given
3319 set_offsets_for_label (rtx insn)
3322 int label_nr = CODE_LABEL_NUMBER (insn);
3323 struct elim_table *ep;
3325 num_not_at_initial_offset = 0;
3326 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3328 ep->offset = ep->previous_offset
3329 = offsets_at[label_nr - first_label_num][i];
3330 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3331 num_not_at_initial_offset++;
3335 /* See if anything that happened changes which eliminations are valid.
3336 For example, on the SPARC, whether or not the frame pointer can
3337 be eliminated can depend on what registers have been used. We need
3338 not check some conditions again (such as flag_omit_frame_pointer)
3339 since they can't have changed. */
3342 update_eliminables (HARD_REG_SET *pset)
3344 int previous_frame_pointer_needed = frame_pointer_needed;
3345 struct elim_table *ep;
3347 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3348 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3349 #ifdef ELIMINABLE_REGS
3350 || ! CAN_ELIMINATE (ep->from, ep->to)
3353 ep->can_eliminate = 0;
3355 /* Look for the case where we have discovered that we can't replace
3356 register A with register B and that means that we will now be
3357 trying to replace register A with register C. This means we can
3358 no longer replace register C with register B and we need to disable
3359 such an elimination, if it exists. This occurs often with A == ap,
3360 B == sp, and C == fp. */
3362 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3364 struct elim_table *op;
3367 if (! ep->can_eliminate && ep->can_eliminate_previous)
3369 /* Find the current elimination for ep->from, if there is a
3371 for (op = reg_eliminate;
3372 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3373 if (op->from == ep->from && op->can_eliminate)
3379 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3381 for (op = reg_eliminate;
3382 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3383 if (op->from == new_to && op->to == ep->to)
3384 op->can_eliminate = 0;
3388 /* See if any registers that we thought we could eliminate the previous
3389 time are no longer eliminable. If so, something has changed and we
3390 must spill the register. Also, recompute the number of eliminable
3391 registers and see if the frame pointer is needed; it is if there is
3392 no elimination of the frame pointer that we can perform. */
3394 frame_pointer_needed = 1;
3395 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3397 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3398 && ep->to != HARD_FRAME_POINTER_REGNUM)
3399 frame_pointer_needed = 0;
3401 if (! ep->can_eliminate && ep->can_eliminate_previous)
3403 ep->can_eliminate_previous = 0;
3404 SET_HARD_REG_BIT (*pset, ep->from);
3409 /* If we didn't need a frame pointer last time, but we do now, spill
3410 the hard frame pointer. */
3411 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3412 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3415 /* Initialize the table of registers to eliminate. */
3418 init_elim_table (void)
3420 struct elim_table *ep;
3421 #ifdef ELIMINABLE_REGS
3422 const struct elim_table_1 *ep1;
3426 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3428 /* Does this function require a frame pointer? */
3430 frame_pointer_needed = (! flag_omit_frame_pointer
3431 #ifdef EXIT_IGNORE_STACK
3432 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3433 and restore sp for alloca. So we can't eliminate
3434 the frame pointer in that case. At some point,
3435 we should improve this by emitting the
3436 sp-adjusting insns for this case. */
3437 || (current_function_calls_alloca
3438 && EXIT_IGNORE_STACK)
3440 || FRAME_POINTER_REQUIRED);
3444 #ifdef ELIMINABLE_REGS
3445 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3446 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3448 ep->from = ep1->from;
3450 ep->can_eliminate = ep->can_eliminate_previous
3451 = (CAN_ELIMINATE (ep->from, ep->to)
3452 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3455 reg_eliminate[0].from = reg_eliminate_1[0].from;
3456 reg_eliminate[0].to = reg_eliminate_1[0].to;
3457 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3458 = ! frame_pointer_needed;
3461 /* Count the number of eliminable registers and build the FROM and TO
3462 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3463 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3464 We depend on this. */
3465 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3467 num_eliminable += ep->can_eliminate;
3468 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3469 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3473 /* Kick all pseudos out of hard register REGNO.
3475 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3476 because we found we can't eliminate some register. In the case, no pseudos
3477 are allowed to be in the register, even if they are only in a block that
3478 doesn't require spill registers, unlike the case when we are spilling this
3479 hard reg to produce another spill register.
3481 Return nonzero if any pseudos needed to be kicked out. */
3484 spill_hard_reg (unsigned int regno, int cant_eliminate)
3490 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3491 regs_ever_live[regno] = 1;
3494 /* Spill every pseudo reg that was allocated to this reg
3495 or to something that overlaps this reg. */
3497 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3498 if (reg_renumber[i] >= 0
3499 && (unsigned int) reg_renumber[i] <= regno
3500 && ((unsigned int) reg_renumber[i]
3501 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3502 PSEUDO_REGNO_MODE (i))
3504 SET_REGNO_REG_SET (&spilled_pseudos, i);
3507 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3508 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3511 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3513 IOR_HARD_REG_SET (*set1, *set2);
3516 /* After find_reload_regs has been run for all insn that need reloads,
3517 and/or spill_hard_regs was called, this function is used to actually
3518 spill pseudo registers and try to reallocate them. It also sets up the
3519 spill_regs array for use by choose_reload_regs. */
3522 finish_spills (int global)
3524 struct insn_chain *chain;
3525 int something_changed = 0;
3528 /* Build the spill_regs array for the function. */
3529 /* If there are some registers still to eliminate and one of the spill regs
3530 wasn't ever used before, additional stack space may have to be
3531 allocated to store this register. Thus, we may have changed the offset
3532 between the stack and frame pointers, so mark that something has changed.
3534 One might think that we need only set VAL to 1 if this is a call-used
3535 register. However, the set of registers that must be saved by the
3536 prologue is not identical to the call-used set. For example, the
3537 register used by the call insn for the return PC is a call-used register,
3538 but must be saved by the prologue. */
3541 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3542 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3544 spill_reg_order[i] = n_spills;
3545 spill_regs[n_spills++] = i;
3546 if (num_eliminable && ! regs_ever_live[i])
3547 something_changed = 1;
3548 regs_ever_live[i] = 1;
3551 spill_reg_order[i] = -1;
3553 EXECUTE_IF_SET_IN_REG_SET
3554 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3556 /* Record the current hard register the pseudo is allocated to in
3557 pseudo_previous_regs so we avoid reallocating it to the same
3558 hard reg in a later pass. */
3559 if (reg_renumber[i] < 0)
3562 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3563 /* Mark it as no longer having a hard register home. */
3564 reg_renumber[i] = -1;
3565 /* We will need to scan everything again. */
3566 something_changed = 1;
3569 /* Retry global register allocation if possible. */
3572 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3573 /* For every insn that needs reloads, set the registers used as spill
3574 regs in pseudo_forbidden_regs for every pseudo live across the
3576 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3578 EXECUTE_IF_SET_IN_REG_SET
3579 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3581 ior_hard_reg_set (pseudo_forbidden_regs + i,
3582 &chain->used_spill_regs);
3584 EXECUTE_IF_SET_IN_REG_SET
3585 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3587 ior_hard_reg_set (pseudo_forbidden_regs + i,
3588 &chain->used_spill_regs);
3592 /* Retry allocating the spilled pseudos. For each reg, merge the
3593 various reg sets that indicate which hard regs can't be used,
3594 and call retry_global_alloc.
3595 We change spill_pseudos here to only contain pseudos that did not
3596 get a new hard register. */
3597 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3598 if (reg_old_renumber[i] != reg_renumber[i])
3600 HARD_REG_SET forbidden;
3601 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3602 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3603 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3604 retry_global_alloc (i, forbidden);
3605 if (reg_renumber[i] >= 0)
3606 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3610 /* Fix up the register information in the insn chain.
3611 This involves deleting those of the spilled pseudos which did not get
3612 a new hard register home from the live_{before,after} sets. */
3613 for (chain = reload_insn_chain; chain; chain = chain->next)
3615 HARD_REG_SET used_by_pseudos;
3616 HARD_REG_SET used_by_pseudos2;
3618 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3619 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3621 /* Mark any unallocated hard regs as available for spills. That
3622 makes inheritance work somewhat better. */
3623 if (chain->need_reload)
3625 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3626 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3627 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3629 /* Save the old value for the sanity test below. */
3630 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3632 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3633 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3634 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3635 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3637 /* Make sure we only enlarge the set. */
3638 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3644 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3645 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3647 int regno = reg_renumber[i];
3648 if (reg_old_renumber[i] == regno)
3651 alter_reg (i, reg_old_renumber[i]);
3652 reg_old_renumber[i] = regno;
3656 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3658 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3659 i, reg_renumber[i]);
3663 return something_changed;
3666 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3667 Also mark any hard registers used to store user variables as
3668 forbidden from being used for spill registers. */
3671 scan_paradoxical_subregs (rtx x)
3675 enum rtx_code code = GET_CODE (x);
3681 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3682 && REG_USERVAR_P (x))
3683 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3692 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3700 if (GET_CODE (SUBREG_REG (x)) == REG
3701 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3702 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3703 = GET_MODE_SIZE (GET_MODE (x));
3710 fmt = GET_RTX_FORMAT (code);
3711 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3714 scan_paradoxical_subregs (XEXP (x, i));
3715 else if (fmt[i] == 'E')
3718 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3719 scan_paradoxical_subregs (XVECEXP (x, i, j));
3724 /* Reload pseudo-registers into hard regs around each insn as needed.
3725 Additional register load insns are output before the insn that needs it
3726 and perhaps store insns after insns that modify the reloaded pseudo reg.
3728 reg_last_reload_reg and reg_reloaded_contents keep track of
3729 which registers are already available in reload registers.
3730 We update these for the reloads that we perform,
3731 as the insns are scanned. */
3734 reload_as_needed (int live_known)
3736 struct insn_chain *chain;
3737 #if defined (AUTO_INC_DEC)
3742 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3743 memset (spill_reg_store, 0, sizeof spill_reg_store);
3744 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3745 reg_has_output_reload = xmalloc (max_regno);
3746 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3748 set_initial_elim_offsets ();
3750 for (chain = reload_insn_chain; chain; chain = chain->next)
3753 rtx insn = chain->insn;
3754 rtx old_next = NEXT_INSN (insn);
3756 /* If we pass a label, copy the offsets from the label information
3757 into the current offsets of each elimination. */
3758 if (GET_CODE (insn) == CODE_LABEL)
3759 set_offsets_for_label (insn);
3761 else if (INSN_P (insn))
3763 rtx oldpat = copy_rtx (PATTERN (insn));
3765 /* If this is a USE and CLOBBER of a MEM, ensure that any
3766 references to eliminable registers have been removed. */
3768 if ((GET_CODE (PATTERN (insn)) == USE
3769 || GET_CODE (PATTERN (insn)) == CLOBBER)
3770 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3771 XEXP (XEXP (PATTERN (insn), 0), 0)
3772 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3773 GET_MODE (XEXP (PATTERN (insn), 0)),
3776 /* If we need to do register elimination processing, do so.
3777 This might delete the insn, in which case we are done. */
3778 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3780 eliminate_regs_in_insn (insn, 1);
3781 if (GET_CODE (insn) == NOTE)
3783 update_eliminable_offsets ();
3788 /* If need_elim is nonzero but need_reload is zero, one might think
3789 that we could simply set n_reloads to 0. However, find_reloads
3790 could have done some manipulation of the insn (such as swapping
3791 commutative operands), and these manipulations are lost during
3792 the first pass for every insn that needs register elimination.
3793 So the actions of find_reloads must be redone here. */
3795 if (! chain->need_elim && ! chain->need_reload
3796 && ! chain->need_operand_change)
3798 /* First find the pseudo regs that must be reloaded for this insn.
3799 This info is returned in the tables reload_... (see reload.h).
3800 Also modify the body of INSN by substituting RELOAD
3801 rtx's for those pseudo regs. */
3804 memset (reg_has_output_reload, 0, max_regno);
3805 CLEAR_HARD_REG_SET (reg_is_output_reload);
3807 find_reloads (insn, 1, spill_indirect_levels, live_known,
3813 rtx next = NEXT_INSN (insn);
3816 prev = PREV_INSN (insn);
3818 /* Now compute which reload regs to reload them into. Perhaps
3819 reusing reload regs from previous insns, or else output
3820 load insns to reload them. Maybe output store insns too.
3821 Record the choices of reload reg in reload_reg_rtx. */
3822 choose_reload_regs (chain);
3824 /* Merge any reloads that we didn't combine for fear of
3825 increasing the number of spill registers needed but now
3826 discover can be safely merged. */
3827 if (SMALL_REGISTER_CLASSES)
3828 merge_assigned_reloads (insn);
3830 /* Generate the insns to reload operands into or out of
3831 their reload regs. */
3832 emit_reload_insns (chain);
3834 /* Substitute the chosen reload regs from reload_reg_rtx
3835 into the insn's body (or perhaps into the bodies of other
3836 load and store insn that we just made for reloading
3837 and that we moved the structure into). */
3838 subst_reloads (insn);
3840 /* If this was an ASM, make sure that all the reload insns
3841 we have generated are valid. If not, give an error
3844 if (asm_noperands (PATTERN (insn)) >= 0)
3845 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3846 if (p != insn && INSN_P (p)
3847 && GET_CODE (PATTERN (p)) != USE
3848 && (recog_memoized (p) < 0
3849 || (extract_insn (p), ! constrain_operands (1))))
3851 error_for_asm (insn,
3852 "`asm' operand requires impossible reload");
3857 if (num_eliminable && chain->need_elim)
3858 update_eliminable_offsets ();
3860 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3861 is no longer validly lying around to save a future reload.
3862 Note that this does not detect pseudos that were reloaded
3863 for this insn in order to be stored in
3864 (obeying register constraints). That is correct; such reload
3865 registers ARE still valid. */
3866 note_stores (oldpat, forget_old_reloads_1, NULL);
3868 /* There may have been CLOBBER insns placed after INSN. So scan
3869 between INSN and NEXT and use them to forget old reloads. */
3870 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3871 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3872 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3875 /* Likewise for regs altered by auto-increment in this insn.
3876 REG_INC notes have been changed by reloading:
3877 find_reloads_address_1 records substitutions for them,
3878 which have been performed by subst_reloads above. */
3879 for (i = n_reloads - 1; i >= 0; i--)
3881 rtx in_reg = rld[i].in_reg;
3884 enum rtx_code code = GET_CODE (in_reg);
3885 /* PRE_INC / PRE_DEC will have the reload register ending up
3886 with the same value as the stack slot, but that doesn't
3887 hold true for POST_INC / POST_DEC. Either we have to
3888 convert the memory access to a true POST_INC / POST_DEC,
3889 or we can't use the reload register for inheritance. */
3890 if ((code == POST_INC || code == POST_DEC)
3891 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3892 REGNO (rld[i].reg_rtx))
3893 /* Make sure it is the inc/dec pseudo, and not
3894 some other (e.g. output operand) pseudo. */
3895 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3896 == REGNO (XEXP (in_reg, 0))))
3899 rtx reload_reg = rld[i].reg_rtx;
3900 enum machine_mode mode = GET_MODE (reload_reg);
3904 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3906 /* We really want to ignore REG_INC notes here, so
3907 use PATTERN (p) as argument to reg_set_p . */
3908 if (reg_set_p (reload_reg, PATTERN (p)))
3910 n = count_occurrences (PATTERN (p), reload_reg, 0);
3915 n = validate_replace_rtx (reload_reg,
3916 gen_rtx (code, mode,
3920 /* We must also verify that the constraints
3921 are met after the replacement. */
3924 n = constrain_operands (1);
3928 /* If the constraints were not met, then
3929 undo the replacement. */
3932 validate_replace_rtx (gen_rtx (code, mode,
3944 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3946 /* Mark this as having an output reload so that the
3947 REG_INC processing code below won't invalidate
3948 the reload for inheritance. */
3949 SET_HARD_REG_BIT (reg_is_output_reload,
3950 REGNO (reload_reg));
3951 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3954 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3957 else if ((code == PRE_INC || code == PRE_DEC)
3958 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3959 REGNO (rld[i].reg_rtx))
3960 /* Make sure it is the inc/dec pseudo, and not
3961 some other (e.g. output operand) pseudo. */
3962 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3963 == REGNO (XEXP (in_reg, 0))))
3965 SET_HARD_REG_BIT (reg_is_output_reload,
3966 REGNO (rld[i].reg_rtx));
3967 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3971 /* If a pseudo that got a hard register is auto-incremented,
3972 we must purge records of copying it into pseudos without
3974 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3975 if (REG_NOTE_KIND (x) == REG_INC)
3977 /* See if this pseudo reg was reloaded in this insn.
3978 If so, its last-reload info is still valid
3979 because it is based on this insn's reload. */
3980 for (i = 0; i < n_reloads; i++)
3981 if (rld[i].out == XEXP (x, 0))
3985 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3989 /* A reload reg's contents are unknown after a label. */
3990 if (GET_CODE (insn) == CODE_LABEL)
3991 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3993 /* Don't assume a reload reg is still good after a call insn
3994 if it is a call-used reg. */
3995 else if (GET_CODE (insn) == CALL_INSN)
3996 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4000 free (reg_last_reload_reg);
4001 free (reg_has_output_reload);
4004 /* Discard all record of any value reloaded from X,
4005 or reloaded in X from someplace else;
4006 unless X is an output reload reg of the current insn.
4008 X may be a hard reg (the reload reg)
4009 or it may be a pseudo reg that was reloaded from. */
4012 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4013 void *data ATTRIBUTE_UNUSED)
4018 /* note_stores does give us subregs of hard regs,
4019 subreg_regno_offset will abort if it is not a hard reg. */
4020 while (GET_CODE (x) == SUBREG)
4022 /* We ignore the subreg offset when calculating the regno,
4023 because we are using the entire underlying hard register
4028 if (GET_CODE (x) != REG)
4033 if (regno >= FIRST_PSEUDO_REGISTER)
4039 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4040 /* Storing into a spilled-reg invalidates its contents.
4041 This can happen if a block-local pseudo is allocated to that reg
4042 and it wasn't spilled because this block's total need is 0.
4043 Then some insn might have an optional reload and use this reg. */
4044 for (i = 0; i < nr; i++)
4045 /* But don't do this if the reg actually serves as an output
4046 reload reg in the current instruction. */
4048 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4050 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4051 spill_reg_store[regno + i] = 0;
4055 /* Since value of X has changed,
4056 forget any value previously copied from it. */
4059 /* But don't forget a copy if this is the output reload
4060 that establishes the copy's validity. */
4061 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4062 reg_last_reload_reg[regno + nr] = 0;
4065 /* The following HARD_REG_SETs indicate when each hard register is
4066 used for a reload of various parts of the current insn. */
4068 /* If reg is unavailable for all reloads. */
4069 static HARD_REG_SET reload_reg_unavailable;
4070 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4071 static HARD_REG_SET reload_reg_used;
4072 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4073 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4074 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4075 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4076 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4077 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4078 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4079 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4080 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4081 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4082 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4083 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4084 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4085 static HARD_REG_SET reload_reg_used_in_op_addr;
4086 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4087 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4088 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4089 static HARD_REG_SET reload_reg_used_in_insn;
4090 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4091 static HARD_REG_SET reload_reg_used_in_other_addr;
4093 /* If reg is in use as a reload reg for any sort of reload. */
4094 static HARD_REG_SET reload_reg_used_at_all;
4096 /* If reg is use as an inherited reload. We just mark the first register
4098 static HARD_REG_SET reload_reg_used_for_inherit;
4100 /* Records which hard regs are used in any way, either as explicit use or
4101 by being allocated to a pseudo during any point of the current insn. */
4102 static HARD_REG_SET reg_used_in_insn;
4104 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4105 TYPE. MODE is used to indicate how many consecutive regs are
4109 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4110 enum machine_mode mode)
4112 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4115 for (i = regno; i < nregs + regno; i++)
4120 SET_HARD_REG_BIT (reload_reg_used, i);
4123 case RELOAD_FOR_INPUT_ADDRESS:
4124 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4127 case RELOAD_FOR_INPADDR_ADDRESS:
4128 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4131 case RELOAD_FOR_OUTPUT_ADDRESS:
4132 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4135 case RELOAD_FOR_OUTADDR_ADDRESS:
4136 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4139 case RELOAD_FOR_OPERAND_ADDRESS:
4140 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4143 case RELOAD_FOR_OPADDR_ADDR:
4144 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4147 case RELOAD_FOR_OTHER_ADDRESS:
4148 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4151 case RELOAD_FOR_INPUT:
4152 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4155 case RELOAD_FOR_OUTPUT:
4156 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4159 case RELOAD_FOR_INSN:
4160 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4164 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4168 /* Similarly, but show REGNO is no longer in use for a reload. */
4171 clear_reload_reg_in_use (unsigned int regno, int opnum,
4172 enum reload_type type, enum machine_mode mode)
4174 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4175 unsigned int start_regno, end_regno, r;
4177 /* A complication is that for some reload types, inheritance might
4178 allow multiple reloads of the same types to share a reload register.
4179 We set check_opnum if we have to check only reloads with the same
4180 operand number, and check_any if we have to check all reloads. */
4181 int check_opnum = 0;
4183 HARD_REG_SET *used_in_set;
4188 used_in_set = &reload_reg_used;
4191 case RELOAD_FOR_INPUT_ADDRESS:
4192 used_in_set = &reload_reg_used_in_input_addr[opnum];
4195 case RELOAD_FOR_INPADDR_ADDRESS:
4197 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4200 case RELOAD_FOR_OUTPUT_ADDRESS:
4201 used_in_set = &reload_reg_used_in_output_addr[opnum];
4204 case RELOAD_FOR_OUTADDR_ADDRESS:
4206 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4209 case RELOAD_FOR_OPERAND_ADDRESS:
4210 used_in_set = &reload_reg_used_in_op_addr;
4213 case RELOAD_FOR_OPADDR_ADDR:
4215 used_in_set = &reload_reg_used_in_op_addr_reload;
4218 case RELOAD_FOR_OTHER_ADDRESS:
4219 used_in_set = &reload_reg_used_in_other_addr;
4223 case RELOAD_FOR_INPUT:
4224 used_in_set = &reload_reg_used_in_input[opnum];
4227 case RELOAD_FOR_OUTPUT:
4228 used_in_set = &reload_reg_used_in_output[opnum];
4231 case RELOAD_FOR_INSN:
4232 used_in_set = &reload_reg_used_in_insn;
4237 /* We resolve conflicts with remaining reloads of the same type by
4238 excluding the intervals of reload registers by them from the
4239 interval of freed reload registers. Since we only keep track of
4240 one set of interval bounds, we might have to exclude somewhat
4241 more than what would be necessary if we used a HARD_REG_SET here.
4242 But this should only happen very infrequently, so there should
4243 be no reason to worry about it. */
4245 start_regno = regno;
4246 end_regno = regno + nregs;
4247 if (check_opnum || check_any)
4249 for (i = n_reloads - 1; i >= 0; i--)
4251 if (rld[i].when_needed == type
4252 && (check_any || rld[i].opnum == opnum)
4255 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4256 unsigned int conflict_end
4258 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4260 /* If there is an overlap with the first to-be-freed register,
4261 adjust the interval start. */
4262 if (conflict_start <= start_regno && conflict_end > start_regno)
4263 start_regno = conflict_end;
4264 /* Otherwise, if there is a conflict with one of the other
4265 to-be-freed registers, adjust the interval end. */
4266 if (conflict_start > start_regno && conflict_start < end_regno)
4267 end_regno = conflict_start;
4272 for (r = start_regno; r < end_regno; r++)
4273 CLEAR_HARD_REG_BIT (*used_in_set, r);
4276 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4277 specified by OPNUM and TYPE. */
4280 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4284 /* In use for a RELOAD_OTHER means it's not available for anything. */
4285 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4286 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4292 /* In use for anything means we can't use it for RELOAD_OTHER. */
4293 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4294 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4295 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4298 for (i = 0; i < reload_n_operands; i++)
4299 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4300 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4301 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4302 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4303 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4304 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4309 case RELOAD_FOR_INPUT:
4310 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4311 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4314 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4317 /* If it is used for some other input, can't use it. */
4318 for (i = 0; i < reload_n_operands; i++)
4319 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4322 /* If it is used in a later operand's address, can't use it. */
4323 for (i = opnum + 1; i < reload_n_operands; i++)
4324 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4325 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4330 case RELOAD_FOR_INPUT_ADDRESS:
4331 /* Can't use a register if it is used for an input address for this
4332 operand or used as an input in an earlier one. */
4333 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4334 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4337 for (i = 0; i < opnum; i++)
4338 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4343 case RELOAD_FOR_INPADDR_ADDRESS:
4344 /* Can't use a register if it is used for an input address
4345 for this operand or used as an input in an earlier
4347 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4350 for (i = 0; i < opnum; i++)
4351 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4356 case RELOAD_FOR_OUTPUT_ADDRESS:
4357 /* Can't use a register if it is used for an output address for this
4358 operand or used as an output in this or a later operand. Note
4359 that multiple output operands are emitted in reverse order, so
4360 the conflicting ones are those with lower indices. */
4361 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4364 for (i = 0; i <= opnum; i++)
4365 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4370 case RELOAD_FOR_OUTADDR_ADDRESS:
4371 /* Can't use a register if it is used for an output address
4372 for this operand or used as an output in this or a
4373 later operand. Note that multiple output operands are
4374 emitted in reverse order, so the conflicting ones are
4375 those with lower indices. */
4376 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4379 for (i = 0; i <= opnum; i++)
4380 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4385 case RELOAD_FOR_OPERAND_ADDRESS:
4386 for (i = 0; i < reload_n_operands; i++)
4387 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4390 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4391 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4393 case RELOAD_FOR_OPADDR_ADDR:
4394 for (i = 0; i < reload_n_operands; i++)
4395 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4398 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4400 case RELOAD_FOR_OUTPUT:
4401 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4402 outputs, or an operand address for this or an earlier output.
4403 Note that multiple output operands are emitted in reverse order,
4404 so the conflicting ones are those with higher indices. */
4405 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4408 for (i = 0; i < reload_n_operands; i++)
4409 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4412 for (i = opnum; i < reload_n_operands; i++)
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4414 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4419 case RELOAD_FOR_INSN:
4420 for (i = 0; i < reload_n_operands; i++)
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4422 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4425 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4426 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4428 case RELOAD_FOR_OTHER_ADDRESS:
4429 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4434 /* Return 1 if the value in reload reg REGNO, as used by a reload
4435 needed for the part of the insn specified by OPNUM and TYPE,
4436 is still available in REGNO at the end of the insn.
4438 We can assume that the reload reg was already tested for availability
4439 at the time it is needed, and we should not check this again,
4440 in case the reg has already been marked in use. */
4443 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4450 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4451 its value must reach the end. */
4454 /* If this use is for part of the insn,
4455 its value reaches if no subsequent part uses the same register.
4456 Just like the above function, don't try to do this with lots
4459 case RELOAD_FOR_OTHER_ADDRESS:
4460 /* Here we check for everything else, since these don't conflict
4461 with anything else and everything comes later. */
4463 for (i = 0; i < reload_n_operands; i++)
4464 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4465 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4466 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4467 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4468 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4469 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4472 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4473 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4474 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4476 case RELOAD_FOR_INPUT_ADDRESS:
4477 case RELOAD_FOR_INPADDR_ADDRESS:
4478 /* Similar, except that we check only for this and subsequent inputs
4479 and the address of only subsequent inputs and we do not need
4480 to check for RELOAD_OTHER objects since they are known not to
4483 for (i = opnum; i < reload_n_operands; i++)
4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4487 for (i = opnum + 1; i < reload_n_operands; i++)
4488 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4489 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4492 for (i = 0; i < reload_n_operands; i++)
4493 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4494 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4501 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4502 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4503 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4505 case RELOAD_FOR_INPUT:
4506 /* Similar to input address, except we start at the next operand for
4507 both input and input address and we do not check for
4508 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4511 for (i = opnum + 1; i < reload_n_operands; i++)
4512 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4513 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4517 /* ... fall through ... */
4519 case RELOAD_FOR_OPERAND_ADDRESS:
4520 /* Check outputs and their addresses. */
4522 for (i = 0; i < reload_n_operands; i++)
4523 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4524 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4528 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4530 case RELOAD_FOR_OPADDR_ADDR:
4531 for (i = 0; i < reload_n_operands; i++)
4532 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4534 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4537 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4538 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4539 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4541 case RELOAD_FOR_INSN:
4542 /* These conflict with other outputs with RELOAD_OTHER. So
4543 we need only check for output addresses. */
4545 opnum = reload_n_operands;
4547 /* ... fall through ... */
4549 case RELOAD_FOR_OUTPUT:
4550 case RELOAD_FOR_OUTPUT_ADDRESS:
4551 case RELOAD_FOR_OUTADDR_ADDRESS:
4552 /* We already know these can't conflict with a later output. So the
4553 only thing to check are later output addresses.
4554 Note that multiple output operands are emitted in reverse order,
4555 so the conflicting ones are those with lower indices. */
4556 for (i = 0; i < opnum; i++)
4557 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4558 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4567 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4570 This function uses the same algorithm as reload_reg_free_p above. */
4573 reloads_conflict (int r1, int r2)
4575 enum reload_type r1_type = rld[r1].when_needed;
4576 enum reload_type r2_type = rld[r2].when_needed;
4577 int r1_opnum = rld[r1].opnum;
4578 int r2_opnum = rld[r2].opnum;
4580 /* RELOAD_OTHER conflicts with everything. */
4581 if (r2_type == RELOAD_OTHER)
4584 /* Otherwise, check conflicts differently for each type. */
4588 case RELOAD_FOR_INPUT:
4589 return (r2_type == RELOAD_FOR_INSN
4590 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4591 || r2_type == RELOAD_FOR_OPADDR_ADDR
4592 || r2_type == RELOAD_FOR_INPUT
4593 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4594 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4595 && r2_opnum > r1_opnum));
4597 case RELOAD_FOR_INPUT_ADDRESS:
4598 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4599 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4601 case RELOAD_FOR_INPADDR_ADDRESS:
4602 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4603 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4605 case RELOAD_FOR_OUTPUT_ADDRESS:
4606 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4607 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4609 case RELOAD_FOR_OUTADDR_ADDRESS:
4610 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4611 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4613 case RELOAD_FOR_OPERAND_ADDRESS:
4614 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4615 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4617 case RELOAD_FOR_OPADDR_ADDR:
4618 return (r2_type == RELOAD_FOR_INPUT
4619 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4621 case RELOAD_FOR_OUTPUT:
4622 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4623 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4624 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4625 && r2_opnum >= r1_opnum));
4627 case RELOAD_FOR_INSN:
4628 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4629 || r2_type == RELOAD_FOR_INSN
4630 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4632 case RELOAD_FOR_OTHER_ADDRESS:
4633 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4643 /* Indexed by reload number, 1 if incoming value
4644 inherited from previous insns. */
4645 char reload_inherited[MAX_RELOADS];
4647 /* For an inherited reload, this is the insn the reload was inherited from,
4648 if we know it. Otherwise, this is 0. */
4649 rtx reload_inheritance_insn[MAX_RELOADS];
4651 /* If nonzero, this is a place to get the value of the reload,
4652 rather than using reload_in. */
4653 rtx reload_override_in[MAX_RELOADS];
4655 /* For each reload, the hard register number of the register used,
4656 or -1 if we did not need a register for this reload. */
4657 int reload_spill_index[MAX_RELOADS];
4659 /* Subroutine of free_for_value_p, used to check a single register.
4660 START_REGNO is the starting regno of the full reload register
4661 (possibly comprising multiple hard registers) that we are considering. */
4664 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4665 enum reload_type type, rtx value, rtx out,
4666 int reloadnum, int ignore_address_reloads)
4669 /* Set if we see an input reload that must not share its reload register
4670 with any new earlyclobber, but might otherwise share the reload
4671 register with an output or input-output reload. */
4672 int check_earlyclobber = 0;
4676 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4679 if (out == const0_rtx)
4685 /* We use some pseudo 'time' value to check if the lifetimes of the
4686 new register use would overlap with the one of a previous reload
4687 that is not read-only or uses a different value.
4688 The 'time' used doesn't have to be linear in any shape or form, just
4690 Some reload types use different 'buckets' for each operand.
4691 So there are MAX_RECOG_OPERANDS different time values for each
4693 We compute TIME1 as the time when the register for the prospective
4694 new reload ceases to be live, and TIME2 for each existing
4695 reload as the time when that the reload register of that reload
4697 Where there is little to be gained by exact lifetime calculations,
4698 we just make conservative assumptions, i.e. a longer lifetime;
4699 this is done in the 'default:' cases. */
4702 case RELOAD_FOR_OTHER_ADDRESS:
4703 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4704 time1 = copy ? 0 : 1;
4707 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4709 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4710 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4711 respectively, to the time values for these, we get distinct time
4712 values. To get distinct time values for each operand, we have to
4713 multiply opnum by at least three. We round that up to four because
4714 multiply by four is often cheaper. */
4715 case RELOAD_FOR_INPADDR_ADDRESS:
4716 time1 = opnum * 4 + 2;
4718 case RELOAD_FOR_INPUT_ADDRESS:
4719 time1 = opnum * 4 + 3;
4721 case RELOAD_FOR_INPUT:
4722 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4723 executes (inclusive). */
4724 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4726 case RELOAD_FOR_OPADDR_ADDR:
4728 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4729 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4731 case RELOAD_FOR_OPERAND_ADDRESS:
4732 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4734 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4736 case RELOAD_FOR_OUTADDR_ADDRESS:
4737 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4739 case RELOAD_FOR_OUTPUT_ADDRESS:
4740 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4743 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4746 for (i = 0; i < n_reloads; i++)
4748 rtx reg = rld[i].reg_rtx;
4749 if (reg && GET_CODE (reg) == REG
4750 && ((unsigned) regno - true_regnum (reg)
4751 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4754 rtx other_input = rld[i].in;
4756 /* If the other reload loads the same input value, that
4757 will not cause a conflict only if it's loading it into
4758 the same register. */
4759 if (true_regnum (reg) != start_regno)
4760 other_input = NULL_RTX;
4761 if (! other_input || ! rtx_equal_p (other_input, value)
4762 || rld[i].out || out)
4765 switch (rld[i].when_needed)
4767 case RELOAD_FOR_OTHER_ADDRESS:
4770 case RELOAD_FOR_INPADDR_ADDRESS:
4771 /* find_reloads makes sure that a
4772 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4773 by at most one - the first -
4774 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4775 address reload is inherited, the address address reload
4776 goes away, so we can ignore this conflict. */
4777 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4778 && ignore_address_reloads
4779 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4780 Then the address address is still needed to store
4781 back the new address. */
4782 && ! rld[reloadnum].out)
4784 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4785 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4787 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4788 && ignore_address_reloads
4789 /* Unless we are reloading an auto_inc expression. */
4790 && ! rld[reloadnum].out)
4792 time2 = rld[i].opnum * 4 + 2;
4794 case RELOAD_FOR_INPUT_ADDRESS:
4795 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4796 && ignore_address_reloads
4797 && ! rld[reloadnum].out)
4799 time2 = rld[i].opnum * 4 + 3;
4801 case RELOAD_FOR_INPUT:
4802 time2 = rld[i].opnum * 4 + 4;
4803 check_earlyclobber = 1;
4805 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4806 == MAX_RECOG_OPERAND * 4 */
4807 case RELOAD_FOR_OPADDR_ADDR:
4808 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4809 && ignore_address_reloads
4810 && ! rld[reloadnum].out)
4812 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4814 case RELOAD_FOR_OPERAND_ADDRESS:
4815 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4816 check_earlyclobber = 1;
4818 case RELOAD_FOR_INSN:
4819 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4821 case RELOAD_FOR_OUTPUT:
4822 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4823 instruction is executed. */
4824 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4826 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4827 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4829 case RELOAD_FOR_OUTADDR_ADDRESS:
4830 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4831 && ignore_address_reloads
4832 && ! rld[reloadnum].out)
4834 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4836 case RELOAD_FOR_OUTPUT_ADDRESS:
4837 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4840 /* If there is no conflict in the input part, handle this
4841 like an output reload. */
4842 if (! rld[i].in || rtx_equal_p (other_input, value))
4844 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4845 /* Earlyclobbered outputs must conflict with inputs. */
4846 if (earlyclobber_operand_p (rld[i].out))
4847 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4852 /* RELOAD_OTHER might be live beyond instruction execution,
4853 but this is not obvious when we set time2 = 1. So check
4854 here if there might be a problem with the new reload
4855 clobbering the register used by the RELOAD_OTHER. */
4863 && (! rld[i].in || rld[i].out
4864 || ! rtx_equal_p (other_input, value)))
4865 || (out && rld[reloadnum].out_reg
4866 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4872 /* Earlyclobbered outputs must conflict with inputs. */
4873 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4879 /* Return 1 if the value in reload reg REGNO, as used by a reload
4880 needed for the part of the insn specified by OPNUM and TYPE,
4881 may be used to load VALUE into it.
4883 MODE is the mode in which the register is used, this is needed to
4884 determine how many hard regs to test.
4886 Other read-only reloads with the same value do not conflict
4887 unless OUT is nonzero and these other reloads have to live while
4888 output reloads live.
4889 If OUT is CONST0_RTX, this is a special case: it means that the
4890 test should not be for using register REGNO as reload register, but
4891 for copying from register REGNO into the reload register.
4893 RELOADNUM is the number of the reload we want to load this value for;
4894 a reload does not conflict with itself.
4896 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4897 reloads that load an address for the very reload we are considering.
4899 The caller has to make sure that there is no conflict with the return
4903 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4904 enum reload_type type, rtx value, rtx out, int reloadnum,
4905 int ignore_address_reloads)
4907 int nregs = HARD_REGNO_NREGS (regno, mode);
4909 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4910 value, out, reloadnum,
4911 ignore_address_reloads))
4916 /* Determine whether the reload reg X overlaps any rtx'es used for
4917 overriding inheritance. Return nonzero if so. */
4920 conflicts_with_override (rtx x)
4923 for (i = 0; i < n_reloads; i++)
4924 if (reload_override_in[i]
4925 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4930 /* Give an error message saying we failed to find a reload for INSN,
4931 and clear out reload R. */
4933 failed_reload (rtx insn, int r)
4935 if (asm_noperands (PATTERN (insn)) < 0)
4936 /* It's the compiler's fault. */
4937 fatal_insn ("could not find a spill register", insn);
4939 /* It's the user's fault; the operand's mode and constraint
4940 don't match. Disable this reload so we don't crash in final. */
4941 error_for_asm (insn,
4942 "`asm' operand constraint incompatible with operand size");
4946 rld[r].optional = 1;
4947 rld[r].secondary_p = 1;
4950 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4951 for reload R. If it's valid, get an rtx for it. Return nonzero if
4954 set_reload_reg (int i, int r)
4957 rtx reg = spill_reg_rtx[i];
4959 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4960 spill_reg_rtx[i] = reg
4961 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4963 regno = true_regnum (reg);
4965 /* Detect when the reload reg can't hold the reload mode.
4966 This used to be one `if', but Sequent compiler can't handle that. */
4967 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4969 enum machine_mode test_mode = VOIDmode;
4971 test_mode = GET_MODE (rld[r].in);
4972 /* If rld[r].in has VOIDmode, it means we will load it
4973 in whatever mode the reload reg has: to wit, rld[r].mode.
4974 We have already tested that for validity. */
4975 /* Aside from that, we need to test that the expressions
4976 to reload from or into have modes which are valid for this
4977 reload register. Otherwise the reload insns would be invalid. */
4978 if (! (rld[r].in != 0 && test_mode != VOIDmode
4979 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4980 if (! (rld[r].out != 0
4981 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4983 /* The reg is OK. */
4986 /* Mark as in use for this insn the reload regs we use
4988 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4989 rld[r].when_needed, rld[r].mode);
4991 rld[r].reg_rtx = reg;
4992 reload_spill_index[r] = spill_regs[i];
4999 /* Find a spill register to use as a reload register for reload R.
5000 LAST_RELOAD is nonzero if this is the last reload for the insn being
5003 Set rld[R].reg_rtx to the register allocated.
5005 We return 1 if successful, or 0 if we couldn't find a spill reg and
5006 we didn't change anything. */
5009 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5014 /* If we put this reload ahead, thinking it is a group,
5015 then insist on finding a group. Otherwise we can grab a
5016 reg that some other reload needs.
5017 (That can happen when we have a 68000 DATA_OR_FP_REG
5018 which is a group of data regs or one fp reg.)
5019 We need not be so restrictive if there are no more reloads
5022 ??? Really it would be nicer to have smarter handling
5023 for that kind of reg class, where a problem like this is normal.
5024 Perhaps those classes should be avoided for reloading
5025 by use of more alternatives. */
5027 int force_group = rld[r].nregs > 1 && ! last_reload;
5029 /* If we want a single register and haven't yet found one,
5030 take any reg in the right class and not in use.
5031 If we want a consecutive group, here is where we look for it.
5033 We use two passes so we can first look for reload regs to
5034 reuse, which are already in use for other reloads in this insn,
5035 and only then use additional registers.
5036 I think that maximizing reuse is needed to make sure we don't
5037 run out of reload regs. Suppose we have three reloads, and
5038 reloads A and B can share regs. These need two regs.
5039 Suppose A and B are given different regs.
5040 That leaves none for C. */
5041 for (pass = 0; pass < 2; pass++)
5043 /* I is the index in spill_regs.
5044 We advance it round-robin between insns to use all spill regs
5045 equally, so that inherited reloads have a chance
5046 of leapfrogging each other. */
5050 for (count = 0; count < n_spills; count++)
5052 int class = (int) rld[r].class;
5058 regnum = spill_regs[i];
5060 if ((reload_reg_free_p (regnum, rld[r].opnum,
5063 /* We check reload_reg_used to make sure we
5064 don't clobber the return register. */
5065 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5066 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5067 rld[r].when_needed, rld[r].in,
5069 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5070 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5071 /* Look first for regs to share, then for unshared. But
5072 don't share regs used for inherited reloads; they are
5073 the ones we want to preserve. */
5075 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5077 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5080 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5081 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5082 (on 68000) got us two FP regs. If NR is 1,
5083 we would reject both of them. */
5086 /* If we need only one reg, we have already won. */
5089 /* But reject a single reg if we demand a group. */
5094 /* Otherwise check that as many consecutive regs as we need
5095 are available here. */
5098 int regno = regnum + nr - 1;
5099 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5100 && spill_reg_order[regno] >= 0
5101 && reload_reg_free_p (regno, rld[r].opnum,
5102 rld[r].when_needed)))
5111 /* If we found something on pass 1, omit pass 2. */
5112 if (count < n_spills)
5116 /* We should have found a spill register by now. */
5117 if (count >= n_spills)
5120 /* I is the index in SPILL_REG_RTX of the reload register we are to
5121 allocate. Get an rtx for it and find its register number. */
5123 return set_reload_reg (i, r);
5126 /* Initialize all the tables needed to allocate reload registers.
5127 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5128 is the array we use to restore the reg_rtx field for every reload. */
5131 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5135 for (i = 0; i < n_reloads; i++)
5136 rld[i].reg_rtx = save_reload_reg_rtx[i];
5138 memset (reload_inherited, 0, MAX_RELOADS);
5139 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5140 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5142 CLEAR_HARD_REG_SET (reload_reg_used);
5143 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5144 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5145 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5146 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5147 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5149 CLEAR_HARD_REG_SET (reg_used_in_insn);
5152 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5153 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5154 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5155 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5156 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5157 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5160 for (i = 0; i < reload_n_operands; i++)
5162 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5163 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5164 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5165 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5166 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5167 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5170 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5172 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5174 for (i = 0; i < n_reloads; i++)
5175 /* If we have already decided to use a certain register,
5176 don't use it in another way. */
5178 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5179 rld[i].when_needed, rld[i].mode);
5182 /* Assign hard reg targets for the pseudo-registers we must reload
5183 into hard regs for this insn.
5184 Also output the instructions to copy them in and out of the hard regs.
5186 For machines with register classes, we are responsible for
5187 finding a reload reg in the proper class. */
5190 choose_reload_regs (struct insn_chain *chain)
5192 rtx insn = chain->insn;
5194 unsigned int max_group_size = 1;
5195 enum reg_class group_class = NO_REGS;
5196 int pass, win, inheritance;
5198 rtx save_reload_reg_rtx[MAX_RELOADS];
5200 /* In order to be certain of getting the registers we need,
5201 we must sort the reloads into order of increasing register class.
5202 Then our grabbing of reload registers will parallel the process
5203 that provided the reload registers.
5205 Also note whether any of the reloads wants a consecutive group of regs.
5206 If so, record the maximum size of the group desired and what
5207 register class contains all the groups needed by this insn. */
5209 for (j = 0; j < n_reloads; j++)
5211 reload_order[j] = j;
5212 reload_spill_index[j] = -1;
5214 if (rld[j].nregs > 1)
5216 max_group_size = MAX (rld[j].nregs, max_group_size);
5218 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5221 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5225 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5227 /* If -O, try first with inheritance, then turning it off.
5228 If not -O, don't do inheritance.
5229 Using inheritance when not optimizing leads to paradoxes
5230 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5231 because one side of the comparison might be inherited. */
5233 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5235 choose_reload_regs_init (chain, save_reload_reg_rtx);
5237 /* Process the reloads in order of preference just found.
5238 Beyond this point, subregs can be found in reload_reg_rtx.
5240 This used to look for an existing reloaded home for all of the
5241 reloads, and only then perform any new reloads. But that could lose
5242 if the reloads were done out of reg-class order because a later
5243 reload with a looser constraint might have an old home in a register
5244 needed by an earlier reload with a tighter constraint.
5246 To solve this, we make two passes over the reloads, in the order
5247 described above. In the first pass we try to inherit a reload
5248 from a previous insn. If there is a later reload that needs a
5249 class that is a proper subset of the class being processed, we must
5250 also allocate a spill register during the first pass.
5252 Then make a second pass over the reloads to allocate any reloads
5253 that haven't been given registers yet. */
5255 for (j = 0; j < n_reloads; j++)
5257 int r = reload_order[j];
5258 rtx search_equiv = NULL_RTX;
5260 /* Ignore reloads that got marked inoperative. */
5261 if (rld[r].out == 0 && rld[r].in == 0
5262 && ! rld[r].secondary_p)
5265 /* If find_reloads chose to use reload_in or reload_out as a reload
5266 register, we don't need to chose one. Otherwise, try even if it
5267 found one since we might save an insn if we find the value lying
5269 Try also when reload_in is a pseudo without a hard reg. */
5270 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5271 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5272 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5273 && GET_CODE (rld[r].in) != MEM
5274 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5277 #if 0 /* No longer needed for correct operation.
5278 It might give better code, or might not; worth an experiment? */
5279 /* If this is an optional reload, we can't inherit from earlier insns
5280 until we are sure that any non-optional reloads have been allocated.
5281 The following code takes advantage of the fact that optional reloads
5282 are at the end of reload_order. */
5283 if (rld[r].optional != 0)
5284 for (i = 0; i < j; i++)
5285 if ((rld[reload_order[i]].out != 0
5286 || rld[reload_order[i]].in != 0
5287 || rld[reload_order[i]].secondary_p)
5288 && ! rld[reload_order[i]].optional
5289 && rld[reload_order[i]].reg_rtx == 0)
5290 allocate_reload_reg (chain, reload_order[i], 0);
5293 /* First see if this pseudo is already available as reloaded
5294 for a previous insn. We cannot try to inherit for reloads
5295 that are smaller than the maximum number of registers needed
5296 for groups unless the register we would allocate cannot be used
5299 We could check here to see if this is a secondary reload for
5300 an object that is already in a register of the desired class.
5301 This would avoid the need for the secondary reload register.
5302 But this is complex because we can't easily determine what
5303 objects might want to be loaded via this reload. So let a
5304 register be allocated here. In `emit_reload_insns' we suppress
5305 one of the loads in the case described above. */
5311 enum machine_mode mode = VOIDmode;
5315 else if (GET_CODE (rld[r].in) == REG)
5317 regno = REGNO (rld[r].in);
5318 mode = GET_MODE (rld[r].in);
5320 else if (GET_CODE (rld[r].in_reg) == REG)
5322 regno = REGNO (rld[r].in_reg);
5323 mode = GET_MODE (rld[r].in_reg);
5325 else if (GET_CODE (rld[r].in_reg) == SUBREG
5326 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5328 byte = SUBREG_BYTE (rld[r].in_reg);
5329 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5330 if (regno < FIRST_PSEUDO_REGISTER)
5331 regno = subreg_regno (rld[r].in_reg);
5332 mode = GET_MODE (rld[r].in_reg);
5335 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5336 || GET_CODE (rld[r].in_reg) == PRE_DEC
5337 || GET_CODE (rld[r].in_reg) == POST_INC
5338 || GET_CODE (rld[r].in_reg) == POST_DEC)
5339 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5341 regno = REGNO (XEXP (rld[r].in_reg, 0));
5342 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5343 rld[r].out = rld[r].in;
5347 /* This won't work, since REGNO can be a pseudo reg number.
5348 Also, it takes much more hair to keep track of all the things
5349 that can invalidate an inherited reload of part of a pseudoreg. */
5350 else if (GET_CODE (rld[r].in) == SUBREG
5351 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5352 regno = subreg_regno (rld[r].in);
5355 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5357 enum reg_class class = rld[r].class, last_class;
5358 rtx last_reg = reg_last_reload_reg[regno];
5359 enum machine_mode need_mode;
5361 i = REGNO (last_reg);
5362 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5363 last_class = REGNO_REG_CLASS (i);
5369 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5370 GET_MODE_CLASS (mode));
5373 #ifdef CANNOT_CHANGE_MODE_CLASS
5374 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5378 (GET_MODE_SIZE (GET_MODE (last_reg))
5379 >= GET_MODE_SIZE (need_mode))
5380 #ifdef CANNOT_CHANGE_MODE_CLASS
5383 && reg_reloaded_contents[i] == regno
5384 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5385 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5386 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5387 /* Even if we can't use this register as a reload
5388 register, we might use it for reload_override_in,
5389 if copying it to the desired class is cheap
5391 || ((REGISTER_MOVE_COST (mode, last_class, class)
5392 < MEMORY_MOVE_COST (mode, class, 1))
5393 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5394 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5398 #ifdef SECONDARY_MEMORY_NEEDED
5399 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5404 && (rld[r].nregs == max_group_size
5405 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5407 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5408 rld[r].when_needed, rld[r].in,
5411 /* If a group is needed, verify that all the subsequent
5412 registers still have their values intact. */
5413 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5416 for (k = 1; k < nr; k++)
5417 if (reg_reloaded_contents[i + k] != regno
5418 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5426 last_reg = (GET_MODE (last_reg) == mode
5427 ? last_reg : gen_rtx_REG (mode, i));
5430 for (k = 0; k < nr; k++)
5431 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5434 /* We found a register that contains the
5435 value we need. If this register is the
5436 same as an `earlyclobber' operand of the
5437 current insn, just mark it as a place to
5438 reload from since we can't use it as the
5439 reload register itself. */
5441 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5442 if (reg_overlap_mentioned_for_reload_p
5443 (reg_last_reload_reg[regno],
5444 reload_earlyclobbers[i1]))
5447 if (i1 != n_earlyclobbers
5448 || ! (free_for_value_p (i, rld[r].mode,
5450 rld[r].when_needed, rld[r].in,
5452 /* Don't use it if we'd clobber a pseudo reg. */
5453 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5455 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5456 /* Don't clobber the frame pointer. */
5457 || (i == HARD_FRAME_POINTER_REGNUM
5458 && frame_pointer_needed
5460 /* Don't really use the inherited spill reg
5461 if we need it wider than we've got it. */
5462 || (GET_MODE_SIZE (rld[r].mode)
5463 > GET_MODE_SIZE (mode))
5466 /* If find_reloads chose reload_out as reload
5467 register, stay with it - that leaves the
5468 inherited register for subsequent reloads. */
5469 || (rld[r].out && rld[r].reg_rtx
5470 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5472 if (! rld[r].optional)
5474 reload_override_in[r] = last_reg;
5475 reload_inheritance_insn[r]
5476 = reg_reloaded_insn[i];
5482 /* We can use this as a reload reg. */
5483 /* Mark the register as in use for this part of
5485 mark_reload_reg_in_use (i,
5489 rld[r].reg_rtx = last_reg;
5490 reload_inherited[r] = 1;
5491 reload_inheritance_insn[r]
5492 = reg_reloaded_insn[i];
5493 reload_spill_index[r] = i;
5494 for (k = 0; k < nr; k++)
5495 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5503 /* Here's another way to see if the value is already lying around. */
5506 && ! reload_inherited[r]
5508 && (CONSTANT_P (rld[r].in)
5509 || GET_CODE (rld[r].in) == PLUS
5510 || GET_CODE (rld[r].in) == REG
5511 || GET_CODE (rld[r].in) == MEM)
5512 && (rld[r].nregs == max_group_size
5513 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5514 search_equiv = rld[r].in;
5515 /* If this is an output reload from a simple move insn, look
5516 if an equivalence for the input is available. */
5517 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5519 rtx set = single_set (insn);
5522 && rtx_equal_p (rld[r].out, SET_DEST (set))
5523 && CONSTANT_P (SET_SRC (set)))
5524 search_equiv = SET_SRC (set);
5530 = find_equiv_reg (search_equiv, insn, rld[r].class,
5531 -1, NULL, 0, rld[r].mode);
5536 if (GET_CODE (equiv) == REG)
5537 regno = REGNO (equiv);
5538 else if (GET_CODE (equiv) == SUBREG)
5540 /* This must be a SUBREG of a hard register.
5541 Make a new REG since this might be used in an
5542 address and not all machines support SUBREGs
5544 regno = subreg_regno (equiv);
5545 equiv = gen_rtx_REG (rld[r].mode, regno);
5551 /* If we found a spill reg, reject it unless it is free
5552 and of the desired class. */
5556 int bad_for_class = 0;
5557 int max_regno = regno + rld[r].nregs;
5559 for (i = regno; i < max_regno; i++)
5561 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5563 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5568 && ! free_for_value_p (regno, rld[r].mode,
5569 rld[r].opnum, rld[r].when_needed,
5570 rld[r].in, rld[r].out, r, 1))
5575 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5578 /* We found a register that contains the value we need.
5579 If this register is the same as an `earlyclobber' operand
5580 of the current insn, just mark it as a place to reload from
5581 since we can't use it as the reload register itself. */
5584 for (i = 0; i < n_earlyclobbers; i++)
5585 if (reg_overlap_mentioned_for_reload_p (equiv,
5586 reload_earlyclobbers[i]))
5588 if (! rld[r].optional)
5589 reload_override_in[r] = equiv;
5594 /* If the equiv register we have found is explicitly clobbered
5595 in the current insn, it depends on the reload type if we
5596 can use it, use it for reload_override_in, or not at all.
5597 In particular, we then can't use EQUIV for a
5598 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5602 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5603 switch (rld[r].when_needed)
5605 case RELOAD_FOR_OTHER_ADDRESS:
5606 case RELOAD_FOR_INPADDR_ADDRESS:
5607 case RELOAD_FOR_INPUT_ADDRESS:
5608 case RELOAD_FOR_OPADDR_ADDR:
5611 case RELOAD_FOR_INPUT:
5612 case RELOAD_FOR_OPERAND_ADDRESS:
5613 if (! rld[r].optional)
5614 reload_override_in[r] = equiv;
5620 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5621 switch (rld[r].when_needed)
5623 case RELOAD_FOR_OTHER_ADDRESS:
5624 case RELOAD_FOR_INPADDR_ADDRESS:
5625 case RELOAD_FOR_INPUT_ADDRESS:
5626 case RELOAD_FOR_OPADDR_ADDR:
5627 case RELOAD_FOR_OPERAND_ADDRESS:
5628 case RELOAD_FOR_INPUT:
5631 if (! rld[r].optional)
5632 reload_override_in[r] = equiv;
5640 /* If we found an equivalent reg, say no code need be generated
5641 to load it, and use it as our reload reg. */
5643 && (regno != HARD_FRAME_POINTER_REGNUM
5644 || !frame_pointer_needed))
5646 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5648 rld[r].reg_rtx = equiv;
5649 reload_inherited[r] = 1;
5651 /* If reg_reloaded_valid is not set for this register,
5652 there might be a stale spill_reg_store lying around.
5653 We must clear it, since otherwise emit_reload_insns
5654 might delete the store. */
5655 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5656 spill_reg_store[regno] = NULL_RTX;
5657 /* If any of the hard registers in EQUIV are spill
5658 registers, mark them as in use for this insn. */
5659 for (k = 0; k < nr; k++)
5661 i = spill_reg_order[regno + k];
5664 mark_reload_reg_in_use (regno, rld[r].opnum,
5667 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5674 /* If we found a register to use already, or if this is an optional
5675 reload, we are done. */
5676 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5680 /* No longer needed for correct operation. Might or might
5681 not give better code on the average. Want to experiment? */
5683 /* See if there is a later reload that has a class different from our
5684 class that intersects our class or that requires less register
5685 than our reload. If so, we must allocate a register to this
5686 reload now, since that reload might inherit a previous reload
5687 and take the only available register in our class. Don't do this
5688 for optional reloads since they will force all previous reloads
5689 to be allocated. Also don't do this for reloads that have been
5692 for (i = j + 1; i < n_reloads; i++)
5694 int s = reload_order[i];
5696 if ((rld[s].in == 0 && rld[s].out == 0
5697 && ! rld[s].secondary_p)
5701 if ((rld[s].class != rld[r].class
5702 && reg_classes_intersect_p (rld[r].class,
5704 || rld[s].nregs < rld[r].nregs)
5711 allocate_reload_reg (chain, r, j == n_reloads - 1);
5715 /* Now allocate reload registers for anything non-optional that
5716 didn't get one yet. */
5717 for (j = 0; j < n_reloads; j++)
5719 int r = reload_order[j];
5721 /* Ignore reloads that got marked inoperative. */
5722 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5725 /* Skip reloads that already have a register allocated or are
5727 if (rld[r].reg_rtx != 0 || rld[r].optional)
5730 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5734 /* If that loop got all the way, we have won. */
5741 /* Loop around and try without any inheritance. */
5746 /* First undo everything done by the failed attempt
5747 to allocate with inheritance. */
5748 choose_reload_regs_init (chain, save_reload_reg_rtx);
5750 /* Some sanity tests to verify that the reloads found in the first
5751 pass are identical to the ones we have now. */
5752 if (chain->n_reloads != n_reloads)
5755 for (i = 0; i < n_reloads; i++)
5757 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5759 if (chain->rld[i].when_needed != rld[i].when_needed)
5761 for (j = 0; j < n_spills; j++)
5762 if (spill_regs[j] == chain->rld[i].regno)
5763 if (! set_reload_reg (j, i))
5764 failed_reload (chain->insn, i);
5768 /* If we thought we could inherit a reload, because it seemed that
5769 nothing else wanted the same reload register earlier in the insn,
5770 verify that assumption, now that all reloads have been assigned.
5771 Likewise for reloads where reload_override_in has been set. */
5773 /* If doing expensive optimizations, do one preliminary pass that doesn't
5774 cancel any inheritance, but removes reloads that have been needed only
5775 for reloads that we know can be inherited. */
5776 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5778 for (j = 0; j < n_reloads; j++)
5780 int r = reload_order[j];
5782 if (reload_inherited[r] && rld[r].reg_rtx)
5783 check_reg = rld[r].reg_rtx;
5784 else if (reload_override_in[r]
5785 && (GET_CODE (reload_override_in[r]) == REG
5786 || GET_CODE (reload_override_in[r]) == SUBREG))
5787 check_reg = reload_override_in[r];
5790 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5791 rld[r].opnum, rld[r].when_needed, rld[r].in,
5792 (reload_inherited[r]
5793 ? rld[r].out : const0_rtx),
5798 reload_inherited[r] = 0;
5799 reload_override_in[r] = 0;
5801 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5802 reload_override_in, then we do not need its related
5803 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5804 likewise for other reload types.
5805 We handle this by removing a reload when its only replacement
5806 is mentioned in reload_in of the reload we are going to inherit.
5807 A special case are auto_inc expressions; even if the input is
5808 inherited, we still need the address for the output. We can
5809 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5810 If we succeeded removing some reload and we are doing a preliminary
5811 pass just to remove such reloads, make another pass, since the
5812 removal of one reload might allow us to inherit another one. */
5814 && rld[r].out != rld[r].in
5815 && remove_address_replacements (rld[r].in) && pass)
5820 /* Now that reload_override_in is known valid,
5821 actually override reload_in. */
5822 for (j = 0; j < n_reloads; j++)
5823 if (reload_override_in[j])
5824 rld[j].in = reload_override_in[j];
5826 /* If this reload won't be done because it has been canceled or is
5827 optional and not inherited, clear reload_reg_rtx so other
5828 routines (such as subst_reloads) don't get confused. */
5829 for (j = 0; j < n_reloads; j++)
5830 if (rld[j].reg_rtx != 0
5831 && ((rld[j].optional && ! reload_inherited[j])
5832 || (rld[j].in == 0 && rld[j].out == 0
5833 && ! rld[j].secondary_p)))
5835 int regno = true_regnum (rld[j].reg_rtx);
5837 if (spill_reg_order[regno] >= 0)
5838 clear_reload_reg_in_use (regno, rld[j].opnum,
5839 rld[j].when_needed, rld[j].mode);
5841 reload_spill_index[j] = -1;
5844 /* Record which pseudos and which spill regs have output reloads. */
5845 for (j = 0; j < n_reloads; j++)
5847 int r = reload_order[j];
5849 i = reload_spill_index[r];
5851 /* I is nonneg if this reload uses a register.
5852 If rld[r].reg_rtx is 0, this is an optional reload
5853 that we opted to ignore. */
5854 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5855 && rld[r].reg_rtx != 0)
5857 int nregno = REGNO (rld[r].out_reg);
5860 if (nregno < FIRST_PSEUDO_REGISTER)
5861 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5864 reg_has_output_reload[nregno + nr] = 1;
5868 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5870 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5873 if (rld[r].when_needed != RELOAD_OTHER
5874 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5875 && rld[r].when_needed != RELOAD_FOR_INSN)
5881 /* Deallocate the reload register for reload R. This is called from
5882 remove_address_replacements. */
5885 deallocate_reload_reg (int r)
5889 if (! rld[r].reg_rtx)
5891 regno = true_regnum (rld[r].reg_rtx);
5893 if (spill_reg_order[regno] >= 0)
5894 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5896 reload_spill_index[r] = -1;
5899 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5900 reloads of the same item for fear that we might not have enough reload
5901 registers. However, normally they will get the same reload register
5902 and hence actually need not be loaded twice.
5904 Here we check for the most common case of this phenomenon: when we have
5905 a number of reloads for the same object, each of which were allocated
5906 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5907 reload, and is not modified in the insn itself. If we find such,
5908 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5909 This will not increase the number of spill registers needed and will
5910 prevent redundant code. */
5913 merge_assigned_reloads (rtx insn)
5917 /* Scan all the reloads looking for ones that only load values and
5918 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5919 assigned and not modified by INSN. */
5921 for (i = 0; i < n_reloads; i++)
5923 int conflicting_input = 0;
5924 int max_input_address_opnum = -1;
5925 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5927 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5928 || rld[i].out != 0 || rld[i].reg_rtx == 0
5929 || reg_set_p (rld[i].reg_rtx, insn))
5932 /* Look at all other reloads. Ensure that the only use of this
5933 reload_reg_rtx is in a reload that just loads the same value
5934 as we do. Note that any secondary reloads must be of the identical
5935 class since the values, modes, and result registers are the
5936 same, so we need not do anything with any secondary reloads. */
5938 for (j = 0; j < n_reloads; j++)
5940 if (i == j || rld[j].reg_rtx == 0
5941 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5945 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5946 && rld[j].opnum > max_input_address_opnum)
5947 max_input_address_opnum = rld[j].opnum;
5949 /* If the reload regs aren't exactly the same (e.g, different modes)
5950 or if the values are different, we can't merge this reload.
5951 But if it is an input reload, we might still merge
5952 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5954 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5955 || rld[j].out != 0 || rld[j].in == 0
5956 || ! rtx_equal_p (rld[i].in, rld[j].in))
5958 if (rld[j].when_needed != RELOAD_FOR_INPUT
5959 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5960 || rld[i].opnum > rld[j].opnum)
5961 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5963 conflicting_input = 1;
5964 if (min_conflicting_input_opnum > rld[j].opnum)
5965 min_conflicting_input_opnum = rld[j].opnum;
5969 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5970 we, in fact, found any matching reloads. */
5973 && max_input_address_opnum <= min_conflicting_input_opnum)
5975 for (j = 0; j < n_reloads; j++)
5976 if (i != j && rld[j].reg_rtx != 0
5977 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5978 && (! conflicting_input
5979 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5980 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5982 rld[i].when_needed = RELOAD_OTHER;
5984 reload_spill_index[j] = -1;
5985 transfer_replacements (i, j);
5988 /* If this is now RELOAD_OTHER, look for any reloads that load
5989 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5990 if they were for inputs, RELOAD_OTHER for outputs. Note that
5991 this test is equivalent to looking for reloads for this operand
5993 /* We must take special care when there are two or more reloads to
5994 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
5995 same value or a part of it; we must not change its type if there
5996 is a conflicting input. */
5998 if (rld[i].when_needed == RELOAD_OTHER)
5999 for (j = 0; j < n_reloads; j++)
6001 && rld[j].when_needed != RELOAD_OTHER
6002 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6003 && (! conflicting_input
6004 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6005 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6006 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6012 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6013 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6014 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6016 /* Check to see if we accidentally converted two reloads
6017 that use the same reload register with different inputs
6018 to the same type. If so, the resulting code won't work,
6021 for (k = 0; k < j; k++)
6022 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6023 && rld[k].when_needed == rld[j].when_needed
6024 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6025 && ! rtx_equal_p (rld[k].in, rld[j].in))
6032 /* These arrays are filled by emit_reload_insns and its subroutines. */
6033 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6034 static rtx other_input_address_reload_insns = 0;
6035 static rtx other_input_reload_insns = 0;
6036 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6037 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6038 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6039 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6040 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6041 static rtx operand_reload_insns = 0;
6042 static rtx other_operand_reload_insns = 0;
6043 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6045 /* Values to be put in spill_reg_store are put here first. */
6046 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6047 static HARD_REG_SET reg_reloaded_died;
6049 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6050 has the number J. OLD contains the value to be used as input. */
6053 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6056 rtx insn = chain->insn;
6057 rtx reloadreg = rl->reg_rtx;
6058 rtx oldequiv_reg = 0;
6061 enum machine_mode mode;
6064 /* Determine the mode to reload in.
6065 This is very tricky because we have three to choose from.
6066 There is the mode the insn operand wants (rl->inmode).
6067 There is the mode of the reload register RELOADREG.
6068 There is the intrinsic mode of the operand, which we could find
6069 by stripping some SUBREGs.
6070 It turns out that RELOADREG's mode is irrelevant:
6071 we can change that arbitrarily.
6073 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6074 then the reload reg may not support QImode moves, so use SImode.
6075 If foo is in memory due to spilling a pseudo reg, this is safe,
6076 because the QImode value is in the least significant part of a
6077 slot big enough for a SImode. If foo is some other sort of
6078 memory reference, then it is impossible to reload this case,
6079 so previous passes had better make sure this never happens.
6081 Then consider a one-word union which has SImode and one of its
6082 members is a float, being fetched as (SUBREG:SF union:SI).
6083 We must fetch that as SFmode because we could be loading into
6084 a float-only register. In this case OLD's mode is correct.
6086 Consider an immediate integer: it has VOIDmode. Here we need
6087 to get a mode from something else.
6089 In some cases, there is a fourth mode, the operand's
6090 containing mode. If the insn specifies a containing mode for
6091 this operand, it overrides all others.
6093 I am not sure whether the algorithm here is always right,
6094 but it does the right things in those cases. */
6096 mode = GET_MODE (old);
6097 if (mode == VOIDmode)
6100 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6101 /* If we need a secondary register for this operation, see if
6102 the value is already in a register in that class. Don't
6103 do this if the secondary register will be used as a scratch
6106 if (rl->secondary_in_reload >= 0
6107 && rl->secondary_in_icode == CODE_FOR_nothing
6110 = find_equiv_reg (old, insn,
6111 rld[rl->secondary_in_reload].class,
6115 /* If reloading from memory, see if there is a register
6116 that already holds the same value. If so, reload from there.
6117 We can pass 0 as the reload_reg_p argument because
6118 any other reload has either already been emitted,
6119 in which case find_equiv_reg will see the reload-insn,
6120 or has yet to be emitted, in which case it doesn't matter
6121 because we will use this equiv reg right away. */
6123 if (oldequiv == 0 && optimize
6124 && (GET_CODE (old) == MEM
6125 || (GET_CODE (old) == REG
6126 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6127 && reg_renumber[REGNO (old)] < 0)))
6128 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6132 unsigned int regno = true_regnum (oldequiv);
6134 /* Don't use OLDEQUIV if any other reload changes it at an
6135 earlier stage of this insn or at this stage. */
6136 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6137 rl->in, const0_rtx, j, 0))
6140 /* If it is no cheaper to copy from OLDEQUIV into the
6141 reload register than it would be to move from memory,
6142 don't use it. Likewise, if we need a secondary register
6146 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6147 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6149 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6150 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6151 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6155 #ifdef SECONDARY_MEMORY_NEEDED
6156 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6164 /* delete_output_reload is only invoked properly if old contains
6165 the original pseudo register. Since this is replaced with a
6166 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6167 find the pseudo in RELOAD_IN_REG. */
6169 && reload_override_in[j]
6170 && GET_CODE (rl->in_reg) == REG)
6177 else if (GET_CODE (oldequiv) == REG)
6178 oldequiv_reg = oldequiv;
6179 else if (GET_CODE (oldequiv) == SUBREG)
6180 oldequiv_reg = SUBREG_REG (oldequiv);
6182 /* If we are reloading from a register that was recently stored in
6183 with an output-reload, see if we can prove there was
6184 actually no need to store the old value in it. */
6186 if (optimize && GET_CODE (oldequiv) == REG
6187 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6188 && spill_reg_store[REGNO (oldequiv)]
6189 && GET_CODE (old) == REG
6190 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6191 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6193 delete_output_reload (insn, j, REGNO (oldequiv));
6195 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6196 then load RELOADREG from OLDEQUIV. Note that we cannot use
6197 gen_lowpart_common since it can do the wrong thing when
6198 RELOADREG has a multi-word mode. Note that RELOADREG
6199 must always be a REG here. */
6201 if (GET_MODE (reloadreg) != mode)
6202 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6203 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6204 oldequiv = SUBREG_REG (oldequiv);
6205 if (GET_MODE (oldequiv) != VOIDmode
6206 && mode != GET_MODE (oldequiv))
6207 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6209 /* Switch to the right place to emit the reload insns. */
6210 switch (rl->when_needed)
6213 where = &other_input_reload_insns;
6215 case RELOAD_FOR_INPUT:
6216 where = &input_reload_insns[rl->opnum];
6218 case RELOAD_FOR_INPUT_ADDRESS:
6219 where = &input_address_reload_insns[rl->opnum];
6221 case RELOAD_FOR_INPADDR_ADDRESS:
6222 where = &inpaddr_address_reload_insns[rl->opnum];
6224 case RELOAD_FOR_OUTPUT_ADDRESS:
6225 where = &output_address_reload_insns[rl->opnum];
6227 case RELOAD_FOR_OUTADDR_ADDRESS:
6228 where = &outaddr_address_reload_insns[rl->opnum];
6230 case RELOAD_FOR_OPERAND_ADDRESS:
6231 where = &operand_reload_insns;
6233 case RELOAD_FOR_OPADDR_ADDR:
6234 where = &other_operand_reload_insns;
6236 case RELOAD_FOR_OTHER_ADDRESS:
6237 where = &other_input_address_reload_insns;
6243 push_to_sequence (*where);
6245 /* Auto-increment addresses must be reloaded in a special way. */
6246 if (rl->out && ! rl->out_reg)
6248 /* We are not going to bother supporting the case where a
6249 incremented register can't be copied directly from
6250 OLDEQUIV since this seems highly unlikely. */
6251 if (rl->secondary_in_reload >= 0)
6254 if (reload_inherited[j])
6255 oldequiv = reloadreg;
6257 old = XEXP (rl->in_reg, 0);
6259 if (optimize && GET_CODE (oldequiv) == REG
6260 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6261 && spill_reg_store[REGNO (oldequiv)]
6262 && GET_CODE (old) == REG
6263 && (dead_or_set_p (insn,
6264 spill_reg_stored_to[REGNO (oldequiv)])
6265 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6267 delete_output_reload (insn, j, REGNO (oldequiv));
6269 /* Prevent normal processing of this reload. */
6271 /* Output a special code sequence for this case. */
6272 new_spill_reg_store[REGNO (reloadreg)]
6273 = inc_for_reload (reloadreg, oldequiv, rl->out,
6277 /* If we are reloading a pseudo-register that was set by the previous
6278 insn, see if we can get rid of that pseudo-register entirely
6279 by redirecting the previous insn into our reload register. */
6281 else if (optimize && GET_CODE (old) == REG
6282 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6283 && dead_or_set_p (insn, old)
6284 /* This is unsafe if some other reload
6285 uses the same reg first. */
6286 && ! conflicts_with_override (reloadreg)
6287 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6288 rl->when_needed, old, rl->out, j, 0))
6290 rtx temp = PREV_INSN (insn);
6291 while (temp && GET_CODE (temp) == NOTE)
6292 temp = PREV_INSN (temp);
6294 && GET_CODE (temp) == INSN
6295 && GET_CODE (PATTERN (temp)) == SET
6296 && SET_DEST (PATTERN (temp)) == old
6297 /* Make sure we can access insn_operand_constraint. */
6298 && asm_noperands (PATTERN (temp)) < 0
6299 /* This is unsafe if operand occurs more than once in current
6300 insn. Perhaps some occurrences aren't reloaded. */
6301 && count_occurrences (PATTERN (insn), old, 0) == 1)
6303 rtx old = SET_DEST (PATTERN (temp));
6304 /* Store into the reload register instead of the pseudo. */
6305 SET_DEST (PATTERN (temp)) = reloadreg;
6307 /* Verify that resulting insn is valid. */
6308 extract_insn (temp);
6309 if (constrain_operands (1))
6311 /* If the previous insn is an output reload, the source is
6312 a reload register, and its spill_reg_store entry will
6313 contain the previous destination. This is now
6315 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6316 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6318 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6319 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6322 /* If these are the only uses of the pseudo reg,
6323 pretend for GDB it lives in the reload reg we used. */
6324 if (REG_N_DEATHS (REGNO (old)) == 1
6325 && REG_N_SETS (REGNO (old)) == 1)
6327 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6328 alter_reg (REGNO (old), -1);
6334 SET_DEST (PATTERN (temp)) = old;
6339 /* We can't do that, so output an insn to load RELOADREG. */
6341 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6342 /* If we have a secondary reload, pick up the secondary register
6343 and icode, if any. If OLDEQUIV and OLD are different or
6344 if this is an in-out reload, recompute whether or not we
6345 still need a secondary register and what the icode should
6346 be. If we still need a secondary register and the class or
6347 icode is different, go back to reloading from OLD if using
6348 OLDEQUIV means that we got the wrong type of register. We
6349 cannot have different class or icode due to an in-out reload
6350 because we don't make such reloads when both the input and
6351 output need secondary reload registers. */
6353 if (! special && rl->secondary_in_reload >= 0)
6355 rtx second_reload_reg = 0;
6356 int secondary_reload = rl->secondary_in_reload;
6357 rtx real_oldequiv = oldequiv;
6360 enum insn_code icode;
6362 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6363 and similarly for OLD.
6364 See comments in get_secondary_reload in reload.c. */
6365 /* If it is a pseudo that cannot be replaced with its
6366 equivalent MEM, we must fall back to reload_in, which
6367 will have all the necessary substitutions registered.
6368 Likewise for a pseudo that can't be replaced with its
6369 equivalent constant.
6371 Take extra care for subregs of such pseudos. Note that
6372 we cannot use reg_equiv_mem in this case because it is
6373 not in the right mode. */
6376 if (GET_CODE (tmp) == SUBREG)
6377 tmp = SUBREG_REG (tmp);
6378 if (GET_CODE (tmp) == REG
6379 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6380 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6381 || reg_equiv_constant[REGNO (tmp)] != 0))
6383 if (! reg_equiv_mem[REGNO (tmp)]
6384 || num_not_at_initial_offset
6385 || GET_CODE (oldequiv) == SUBREG)
6386 real_oldequiv = rl->in;
6388 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6392 if (GET_CODE (tmp) == SUBREG)
6393 tmp = SUBREG_REG (tmp);
6394 if (GET_CODE (tmp) == REG
6395 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6396 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6397 || reg_equiv_constant[REGNO (tmp)] != 0))
6399 if (! reg_equiv_mem[REGNO (tmp)]
6400 || num_not_at_initial_offset
6401 || GET_CODE (old) == SUBREG)
6404 real_old = reg_equiv_mem[REGNO (tmp)];
6407 second_reload_reg = rld[secondary_reload].reg_rtx;
6408 icode = rl->secondary_in_icode;
6410 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6411 || (rl->in != 0 && rl->out != 0))
6413 enum reg_class new_class
6414 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6415 mode, real_oldequiv);
6417 if (new_class == NO_REGS)
6418 second_reload_reg = 0;
6421 enum insn_code new_icode;
6422 enum machine_mode new_mode;
6424 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6425 REGNO (second_reload_reg)))
6426 oldequiv = old, real_oldequiv = real_old;
6429 new_icode = reload_in_optab[(int) mode];
6430 if (new_icode != CODE_FOR_nothing
6431 && ((insn_data[(int) new_icode].operand[0].predicate
6432 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6434 || (insn_data[(int) new_icode].operand[1].predicate
6435 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6436 (real_oldequiv, mode)))))
6437 new_icode = CODE_FOR_nothing;
6439 if (new_icode == CODE_FOR_nothing)
6442 new_mode = insn_data[(int) new_icode].operand[2].mode;
6444 if (GET_MODE (second_reload_reg) != new_mode)
6446 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6448 oldequiv = old, real_oldequiv = real_old;
6451 = reload_adjust_reg_for_mode (second_reload_reg,
6458 /* If we still need a secondary reload register, check
6459 to see if it is being used as a scratch or intermediate
6460 register and generate code appropriately. If we need
6461 a scratch register, use REAL_OLDEQUIV since the form of
6462 the insn may depend on the actual address if it is
6465 if (second_reload_reg)
6467 if (icode != CODE_FOR_nothing)
6469 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6470 second_reload_reg));
6475 /* See if we need a scratch register to load the
6476 intermediate register (a tertiary reload). */
6477 enum insn_code tertiary_icode
6478 = rld[secondary_reload].secondary_in_icode;
6480 if (tertiary_icode != CODE_FOR_nothing)
6482 rtx third_reload_reg
6483 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6485 emit_insn ((GEN_FCN (tertiary_icode)
6486 (second_reload_reg, real_oldequiv,
6487 third_reload_reg)));
6490 gen_reload (second_reload_reg, real_oldequiv,
6494 oldequiv = second_reload_reg;
6500 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6502 rtx real_oldequiv = oldequiv;
6504 if ((GET_CODE (oldequiv) == REG
6505 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6506 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6507 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6508 || (GET_CODE (oldequiv) == SUBREG
6509 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6510 && (REGNO (SUBREG_REG (oldequiv))
6511 >= FIRST_PSEUDO_REGISTER)
6512 && ((reg_equiv_memory_loc
6513 [REGNO (SUBREG_REG (oldequiv))] != 0)
6514 || (reg_equiv_constant
6515 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6516 || (CONSTANT_P (oldequiv)
6517 && (PREFERRED_RELOAD_CLASS (oldequiv,
6518 REGNO_REG_CLASS (REGNO (reloadreg)))
6520 real_oldequiv = rl->in;
6521 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6525 if (flag_non_call_exceptions)
6526 copy_eh_notes (insn, get_insns ());
6528 /* End this sequence. */
6529 *where = get_insns ();
6532 /* Update reload_override_in so that delete_address_reloads_1
6533 can see the actual register usage. */
6535 reload_override_in[j] = oldequiv;
6538 /* Generate insns to for the output reload RL, which is for the insn described
6539 by CHAIN and has the number J. */
6541 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6544 rtx reloadreg = rl->reg_rtx;
6545 rtx insn = chain->insn;
6548 enum machine_mode mode = GET_MODE (old);
6551 if (rl->when_needed == RELOAD_OTHER)
6554 push_to_sequence (output_reload_insns[rl->opnum]);
6556 /* Determine the mode to reload in.
6557 See comments above (for input reloading). */
6559 if (mode == VOIDmode)
6561 /* VOIDmode should never happen for an output. */
6562 if (asm_noperands (PATTERN (insn)) < 0)
6563 /* It's the compiler's fault. */
6564 fatal_insn ("VOIDmode on an output", insn);
6565 error_for_asm (insn, "output operand is constant in `asm'");
6566 /* Prevent crash--use something we know is valid. */
6568 old = gen_rtx_REG (mode, REGNO (reloadreg));
6571 if (GET_MODE (reloadreg) != mode)
6572 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6574 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6576 /* If we need two reload regs, set RELOADREG to the intermediate
6577 one, since it will be stored into OLD. We might need a secondary
6578 register only for an input reload, so check again here. */
6580 if (rl->secondary_out_reload >= 0)
6584 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6585 && reg_equiv_mem[REGNO (old)] != 0)
6586 real_old = reg_equiv_mem[REGNO (old)];
6588 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6592 rtx second_reloadreg = reloadreg;
6593 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6595 /* See if RELOADREG is to be used as a scratch register
6596 or as an intermediate register. */
6597 if (rl->secondary_out_icode != CODE_FOR_nothing)
6599 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6600 (real_old, second_reloadreg, reloadreg)));
6605 /* See if we need both a scratch and intermediate reload
6608 int secondary_reload = rl->secondary_out_reload;
6609 enum insn_code tertiary_icode
6610 = rld[secondary_reload].secondary_out_icode;
6612 if (GET_MODE (reloadreg) != mode)
6613 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6615 if (tertiary_icode != CODE_FOR_nothing)
6618 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6621 /* Copy primary reload reg to secondary reload reg.
6622 (Note that these have been swapped above, then
6623 secondary reload reg to OLD using our insn.) */
6625 /* If REAL_OLD is a paradoxical SUBREG, remove it
6626 and try to put the opposite SUBREG on
6628 if (GET_CODE (real_old) == SUBREG
6629 && (GET_MODE_SIZE (GET_MODE (real_old))
6630 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6631 && 0 != (tem = gen_lowpart_common
6632 (GET_MODE (SUBREG_REG (real_old)),
6634 real_old = SUBREG_REG (real_old), reloadreg = tem;
6636 gen_reload (reloadreg, second_reloadreg,
6637 rl->opnum, rl->when_needed);
6638 emit_insn ((GEN_FCN (tertiary_icode)
6639 (real_old, reloadreg, third_reloadreg)));
6644 /* Copy between the reload regs here and then to
6647 gen_reload (reloadreg, second_reloadreg,
6648 rl->opnum, rl->when_needed);
6654 /* Output the last reload insn. */
6659 /* Don't output the last reload if OLD is not the dest of
6660 INSN and is in the src and is clobbered by INSN. */
6661 if (! flag_expensive_optimizations
6662 || GET_CODE (old) != REG
6663 || !(set = single_set (insn))
6664 || rtx_equal_p (old, SET_DEST (set))
6665 || !reg_mentioned_p (old, SET_SRC (set))
6666 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6667 gen_reload (old, reloadreg, rl->opnum,
6671 /* Look at all insns we emitted, just to be safe. */
6672 for (p = get_insns (); p; p = NEXT_INSN (p))
6675 rtx pat = PATTERN (p);
6677 /* If this output reload doesn't come from a spill reg,
6678 clear any memory of reloaded copies of the pseudo reg.
6679 If this output reload comes from a spill reg,
6680 reg_has_output_reload will make this do nothing. */
6681 note_stores (pat, forget_old_reloads_1, NULL);
6683 if (reg_mentioned_p (rl->reg_rtx, pat))
6685 rtx set = single_set (insn);
6686 if (reload_spill_index[j] < 0
6688 && SET_SRC (set) == rl->reg_rtx)
6690 int src = REGNO (SET_SRC (set));
6692 reload_spill_index[j] = src;
6693 SET_HARD_REG_BIT (reg_is_output_reload, src);
6694 if (find_regno_note (insn, REG_DEAD, src))
6695 SET_HARD_REG_BIT (reg_reloaded_died, src);
6697 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6699 int s = rl->secondary_out_reload;
6700 set = single_set (p);
6701 /* If this reload copies only to the secondary reload
6702 register, the secondary reload does the actual
6704 if (s >= 0 && set == NULL_RTX)
6705 /* We can't tell what function the secondary reload
6706 has and where the actual store to the pseudo is
6707 made; leave new_spill_reg_store alone. */
6710 && SET_SRC (set) == rl->reg_rtx
6711 && SET_DEST (set) == rld[s].reg_rtx)
6713 /* Usually the next instruction will be the
6714 secondary reload insn; if we can confirm
6715 that it is, setting new_spill_reg_store to
6716 that insn will allow an extra optimization. */
6717 rtx s_reg = rld[s].reg_rtx;
6718 rtx next = NEXT_INSN (p);
6719 rld[s].out = rl->out;
6720 rld[s].out_reg = rl->out_reg;
6721 set = single_set (next);
6722 if (set && SET_SRC (set) == s_reg
6723 && ! new_spill_reg_store[REGNO (s_reg)])
6725 SET_HARD_REG_BIT (reg_is_output_reload,
6727 new_spill_reg_store[REGNO (s_reg)] = next;
6731 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6736 if (rl->when_needed == RELOAD_OTHER)
6738 emit_insn (other_output_reload_insns[rl->opnum]);
6739 other_output_reload_insns[rl->opnum] = get_insns ();
6742 output_reload_insns[rl->opnum] = get_insns ();
6744 if (flag_non_call_exceptions)
6745 copy_eh_notes (insn, get_insns ());
6750 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6751 and has the number J. */
6753 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6755 rtx insn = chain->insn;
6756 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6757 ? rl->in_reg : rl->in);
6760 /* AUTO_INC reloads need to be handled even if inherited. We got an
6761 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6762 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6763 && ! rtx_equal_p (rl->reg_rtx, old)
6764 && rl->reg_rtx != 0)
6765 emit_input_reload_insns (chain, rld + j, old, j);
6767 /* When inheriting a wider reload, we have a MEM in rl->in,
6768 e.g. inheriting a SImode output reload for
6769 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6770 if (optimize && reload_inherited[j] && rl->in
6771 && GET_CODE (rl->in) == MEM
6772 && GET_CODE (rl->in_reg) == MEM
6773 && reload_spill_index[j] >= 0
6774 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6775 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6777 /* If we are reloading a register that was recently stored in with an
6778 output-reload, see if we can prove there was
6779 actually no need to store the old value in it. */
6782 && (reload_inherited[j] || reload_override_in[j])
6784 && GET_CODE (rl->reg_rtx) == REG
6785 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6787 /* There doesn't seem to be any reason to restrict this to pseudos
6788 and doing so loses in the case where we are copying from a
6789 register of the wrong class. */
6790 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6791 >= FIRST_PSEUDO_REGISTER)
6793 /* The insn might have already some references to stackslots
6794 replaced by MEMs, while reload_out_reg still names the
6796 && (dead_or_set_p (insn,
6797 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6798 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6800 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6803 /* Do output reloading for reload RL, which is for the insn described by
6804 CHAIN and has the number J.
6805 ??? At some point we need to support handling output reloads of
6806 JUMP_INSNs or insns that set cc0. */
6808 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6811 rtx insn = chain->insn;
6812 /* If this is an output reload that stores something that is
6813 not loaded in this same reload, see if we can eliminate a previous
6815 rtx pseudo = rl->out_reg;
6819 && GET_CODE (pseudo) == REG
6820 && ! rtx_equal_p (rl->in_reg, pseudo)
6821 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6822 && reg_last_reload_reg[REGNO (pseudo)])
6824 int pseudo_no = REGNO (pseudo);
6825 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6827 /* We don't need to test full validity of last_regno for
6828 inherit here; we only want to know if the store actually
6829 matches the pseudo. */
6830 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6831 && reg_reloaded_contents[last_regno] == pseudo_no
6832 && spill_reg_store[last_regno]
6833 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6834 delete_output_reload (insn, j, last_regno);
6839 || rl->reg_rtx == old
6840 || rl->reg_rtx == 0)
6843 /* An output operand that dies right away does need a reload,
6844 but need not be copied from it. Show the new location in the
6846 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6847 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6849 XEXP (note, 0) = rl->reg_rtx;
6852 /* Likewise for a SUBREG of an operand that dies. */
6853 else if (GET_CODE (old) == SUBREG
6854 && GET_CODE (SUBREG_REG (old)) == REG
6855 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6858 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6862 else if (GET_CODE (old) == SCRATCH)
6863 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6864 but we don't want to make an output reload. */
6867 /* If is a JUMP_INSN, we can't support output reloads yet. */
6868 if (GET_CODE (insn) == JUMP_INSN)
6871 emit_output_reload_insns (chain, rld + j, j);
6874 /* Output insns to reload values in and out of the chosen reload regs. */
6877 emit_reload_insns (struct insn_chain *chain)
6879 rtx insn = chain->insn;
6883 CLEAR_HARD_REG_SET (reg_reloaded_died);
6885 for (j = 0; j < reload_n_operands; j++)
6886 input_reload_insns[j] = input_address_reload_insns[j]
6887 = inpaddr_address_reload_insns[j]
6888 = output_reload_insns[j] = output_address_reload_insns[j]
6889 = outaddr_address_reload_insns[j]
6890 = other_output_reload_insns[j] = 0;
6891 other_input_address_reload_insns = 0;
6892 other_input_reload_insns = 0;
6893 operand_reload_insns = 0;
6894 other_operand_reload_insns = 0;
6896 /* Dump reloads into the dump file. */
6899 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6900 debug_reload_to_stream (rtl_dump_file);
6903 /* Now output the instructions to copy the data into and out of the
6904 reload registers. Do these in the order that the reloads were reported,
6905 since reloads of base and index registers precede reloads of operands
6906 and the operands may need the base and index registers reloaded. */
6908 for (j = 0; j < n_reloads; j++)
6911 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6912 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6914 do_input_reload (chain, rld + j, j);
6915 do_output_reload (chain, rld + j, j);
6918 /* Now write all the insns we made for reloads in the order expected by
6919 the allocation functions. Prior to the insn being reloaded, we write
6920 the following reloads:
6922 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6924 RELOAD_OTHER reloads.
6926 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6927 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6928 RELOAD_FOR_INPUT reload for the operand.
6930 RELOAD_FOR_OPADDR_ADDRS reloads.
6932 RELOAD_FOR_OPERAND_ADDRESS reloads.
6934 After the insn being reloaded, we write the following:
6936 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6937 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6938 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6939 reloads for the operand. The RELOAD_OTHER output reloads are
6940 output in descending order by reload number. */
6942 emit_insn_before (other_input_address_reload_insns, insn);
6943 emit_insn_before (other_input_reload_insns, insn);
6945 for (j = 0; j < reload_n_operands; j++)
6947 emit_insn_before (inpaddr_address_reload_insns[j], insn);
6948 emit_insn_before (input_address_reload_insns[j], insn);
6949 emit_insn_before (input_reload_insns[j], insn);
6952 emit_insn_before (other_operand_reload_insns, insn);
6953 emit_insn_before (operand_reload_insns, insn);
6955 for (j = 0; j < reload_n_operands; j++)
6957 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
6958 x = emit_insn_after (output_address_reload_insns[j], x);
6959 x = emit_insn_after (output_reload_insns[j], x);
6960 emit_insn_after (other_output_reload_insns[j], x);
6963 /* For all the spill regs newly reloaded in this instruction,
6964 record what they were reloaded from, so subsequent instructions
6965 can inherit the reloads.
6967 Update spill_reg_store for the reloads of this insn.
6968 Copy the elements that were updated in the loop above. */
6970 for (j = 0; j < n_reloads; j++)
6972 int r = reload_order[j];
6973 int i = reload_spill_index[r];
6975 /* If this is a non-inherited input reload from a pseudo, we must
6976 clear any memory of a previous store to the same pseudo. Only do
6977 something if there will not be an output reload for the pseudo
6979 if (rld[r].in_reg != 0
6980 && ! (reload_inherited[r] || reload_override_in[r]))
6982 rtx reg = rld[r].in_reg;
6984 if (GET_CODE (reg) == SUBREG)
6985 reg = SUBREG_REG (reg);
6987 if (GET_CODE (reg) == REG
6988 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6989 && ! reg_has_output_reload[REGNO (reg)])
6991 int nregno = REGNO (reg);
6993 if (reg_last_reload_reg[nregno])
6995 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6997 if (reg_reloaded_contents[last_regno] == nregno)
6998 spill_reg_store[last_regno] = 0;
7003 /* I is nonneg if this reload used a register.
7004 If rld[r].reg_rtx is 0, this is an optional reload
7005 that we opted to ignore. */
7007 if (i >= 0 && rld[r].reg_rtx != 0)
7009 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7011 int part_reaches_end = 0;
7012 int all_reaches_end = 1;
7014 /* For a multi register reload, we need to check if all or part
7015 of the value lives to the end. */
7016 for (k = 0; k < nr; k++)
7018 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7019 rld[r].when_needed))
7020 part_reaches_end = 1;
7022 all_reaches_end = 0;
7025 /* Ignore reloads that don't reach the end of the insn in
7027 if (all_reaches_end)
7029 /* First, clear out memory of what used to be in this spill reg.
7030 If consecutive registers are used, clear them all. */
7032 for (k = 0; k < nr; k++)
7033 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7035 /* Maybe the spill reg contains a copy of reload_out. */
7037 && (GET_CODE (rld[r].out) == REG
7041 || GET_CODE (rld[r].out_reg) == REG))
7043 rtx out = (GET_CODE (rld[r].out) == REG
7047 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7048 int nregno = REGNO (out);
7049 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7050 : HARD_REGNO_NREGS (nregno,
7051 GET_MODE (rld[r].reg_rtx)));
7053 spill_reg_store[i] = new_spill_reg_store[i];
7054 spill_reg_stored_to[i] = out;
7055 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7057 /* If NREGNO is a hard register, it may occupy more than
7058 one register. If it does, say what is in the
7059 rest of the registers assuming that both registers
7060 agree on how many words the object takes. If not,
7061 invalidate the subsequent registers. */
7063 if (nregno < FIRST_PSEUDO_REGISTER)
7064 for (k = 1; k < nnr; k++)
7065 reg_last_reload_reg[nregno + k]
7067 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7070 /* Now do the inverse operation. */
7071 for (k = 0; k < nr; k++)
7073 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7074 reg_reloaded_contents[i + k]
7075 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7078 reg_reloaded_insn[i + k] = insn;
7079 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7083 /* Maybe the spill reg contains a copy of reload_in. Only do
7084 something if there will not be an output reload for
7085 the register being reloaded. */
7086 else if (rld[r].out_reg == 0
7088 && ((GET_CODE (rld[r].in) == REG
7089 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7090 && ! reg_has_output_reload[REGNO (rld[r].in)])
7091 || (GET_CODE (rld[r].in_reg) == REG
7092 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7093 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7098 if (GET_CODE (rld[r].in) == REG
7099 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7100 nregno = REGNO (rld[r].in);
7101 else if (GET_CODE (rld[r].in_reg) == REG)
7102 nregno = REGNO (rld[r].in_reg);
7104 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7106 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7107 : HARD_REGNO_NREGS (nregno,
7108 GET_MODE (rld[r].reg_rtx)));
7110 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7112 if (nregno < FIRST_PSEUDO_REGISTER)
7113 for (k = 1; k < nnr; k++)
7114 reg_last_reload_reg[nregno + k]
7116 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7119 /* Unless we inherited this reload, show we haven't
7120 recently done a store.
7121 Previous stores of inherited auto_inc expressions
7122 also have to be discarded. */
7123 if (! reload_inherited[r]
7124 || (rld[r].out && ! rld[r].out_reg))
7125 spill_reg_store[i] = 0;
7127 for (k = 0; k < nr; k++)
7129 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7130 reg_reloaded_contents[i + k]
7131 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7134 reg_reloaded_insn[i + k] = insn;
7135 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7140 /* However, if part of the reload reaches the end, then we must
7141 invalidate the old info for the part that survives to the end. */
7142 else if (part_reaches_end)
7144 for (k = 0; k < nr; k++)
7145 if (reload_reg_reaches_end_p (i + k,
7147 rld[r].when_needed))
7148 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7152 /* The following if-statement was #if 0'd in 1.34 (or before...).
7153 It's reenabled in 1.35 because supposedly nothing else
7154 deals with this problem. */
7156 /* If a register gets output-reloaded from a non-spill register,
7157 that invalidates any previous reloaded copy of it.
7158 But forget_old_reloads_1 won't get to see it, because
7159 it thinks only about the original insn. So invalidate it here. */
7160 if (i < 0 && rld[r].out != 0
7161 && (GET_CODE (rld[r].out) == REG
7162 || (GET_CODE (rld[r].out) == MEM
7163 && GET_CODE (rld[r].out_reg) == REG)))
7165 rtx out = (GET_CODE (rld[r].out) == REG
7166 ? rld[r].out : rld[r].out_reg);
7167 int nregno = REGNO (out);
7168 if (nregno >= FIRST_PSEUDO_REGISTER)
7170 rtx src_reg, store_insn = NULL_RTX;
7172 reg_last_reload_reg[nregno] = 0;
7174 /* If we can find a hard register that is stored, record
7175 the storing insn so that we may delete this insn with
7176 delete_output_reload. */
7177 src_reg = rld[r].reg_rtx;
7179 /* If this is an optional reload, try to find the source reg
7180 from an input reload. */
7183 rtx set = single_set (insn);
7184 if (set && SET_DEST (set) == rld[r].out)
7188 src_reg = SET_SRC (set);
7190 for (k = 0; k < n_reloads; k++)
7192 if (rld[k].in == src_reg)
7194 src_reg = rld[k].reg_rtx;
7201 store_insn = new_spill_reg_store[REGNO (src_reg)];
7202 if (src_reg && GET_CODE (src_reg) == REG
7203 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7205 int src_regno = REGNO (src_reg);
7206 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7207 /* The place where to find a death note varies with
7208 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7209 necessarily checked exactly in the code that moves
7210 notes, so just check both locations. */
7211 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7212 if (! note && store_insn)
7213 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7216 spill_reg_store[src_regno + nr] = store_insn;
7217 spill_reg_stored_to[src_regno + nr] = out;
7218 reg_reloaded_contents[src_regno + nr] = nregno;
7219 reg_reloaded_insn[src_regno + nr] = store_insn;
7220 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7221 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7222 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7224 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7226 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7228 reg_last_reload_reg[nregno] = src_reg;
7233 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7235 while (num_regs-- > 0)
7236 reg_last_reload_reg[nregno + num_regs] = 0;
7240 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7243 /* Emit code to perform a reload from IN (which may be a reload register) to
7244 OUT (which may also be a reload register). IN or OUT is from operand
7245 OPNUM with reload type TYPE.
7247 Returns first insn emitted. */
7250 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7252 rtx last = get_last_insn ();
7255 /* If IN is a paradoxical SUBREG, remove it and try to put the
7256 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7257 if (GET_CODE (in) == SUBREG
7258 && (GET_MODE_SIZE (GET_MODE (in))
7259 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7260 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7261 in = SUBREG_REG (in), out = tem;
7262 else if (GET_CODE (out) == SUBREG
7263 && (GET_MODE_SIZE (GET_MODE (out))
7264 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7265 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7266 out = SUBREG_REG (out), in = tem;
7268 /* How to do this reload can get quite tricky. Normally, we are being
7269 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7270 register that didn't get a hard register. In that case we can just
7271 call emit_move_insn.
7273 We can also be asked to reload a PLUS that adds a register or a MEM to
7274 another register, constant or MEM. This can occur during frame pointer
7275 elimination and while reloading addresses. This case is handled by
7276 trying to emit a single insn to perform the add. If it is not valid,
7277 we use a two insn sequence.
7279 Finally, we could be called to handle an 'o' constraint by putting
7280 an address into a register. In that case, we first try to do this
7281 with a named pattern of "reload_load_address". If no such pattern
7282 exists, we just emit a SET insn and hope for the best (it will normally
7283 be valid on machines that use 'o').
7285 This entire process is made complex because reload will never
7286 process the insns we generate here and so we must ensure that
7287 they will fit their constraints and also by the fact that parts of
7288 IN might be being reloaded separately and replaced with spill registers.
7289 Because of this, we are, in some sense, just guessing the right approach
7290 here. The one listed above seems to work.
7292 ??? At some point, this whole thing needs to be rethought. */
7294 if (GET_CODE (in) == PLUS
7295 && (GET_CODE (XEXP (in, 0)) == REG
7296 || GET_CODE (XEXP (in, 0)) == SUBREG
7297 || GET_CODE (XEXP (in, 0)) == MEM)
7298 && (GET_CODE (XEXP (in, 1)) == REG
7299 || GET_CODE (XEXP (in, 1)) == SUBREG
7300 || CONSTANT_P (XEXP (in, 1))
7301 || GET_CODE (XEXP (in, 1)) == MEM))
7303 /* We need to compute the sum of a register or a MEM and another
7304 register, constant, or MEM, and put it into the reload
7305 register. The best possible way of doing this is if the machine
7306 has a three-operand ADD insn that accepts the required operands.
7308 The simplest approach is to try to generate such an insn and see if it
7309 is recognized and matches its constraints. If so, it can be used.
7311 It might be better not to actually emit the insn unless it is valid,
7312 but we need to pass the insn as an operand to `recog' and
7313 `extract_insn' and it is simpler to emit and then delete the insn if
7314 not valid than to dummy things up. */
7316 rtx op0, op1, tem, insn;
7319 op0 = find_replacement (&XEXP (in, 0));
7320 op1 = find_replacement (&XEXP (in, 1));
7322 /* Since constraint checking is strict, commutativity won't be
7323 checked, so we need to do that here to avoid spurious failure
7324 if the add instruction is two-address and the second operand
7325 of the add is the same as the reload reg, which is frequently
7326 the case. If the insn would be A = B + A, rearrange it so
7327 it will be A = A + B as constrain_operands expects. */
7329 if (GET_CODE (XEXP (in, 1)) == REG
7330 && REGNO (out) == REGNO (XEXP (in, 1)))
7331 tem = op0, op0 = op1, op1 = tem;
7333 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7334 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7336 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7337 code = recog_memoized (insn);
7341 extract_insn (insn);
7342 /* We want constrain operands to treat this insn strictly in
7343 its validity determination, i.e., the way it would after reload
7345 if (constrain_operands (1))
7349 delete_insns_since (last);
7351 /* If that failed, we must use a conservative two-insn sequence.
7353 Use a move to copy one operand into the reload register. Prefer
7354 to reload a constant, MEM or pseudo since the move patterns can
7355 handle an arbitrary operand. If OP1 is not a constant, MEM or
7356 pseudo and OP1 is not a valid operand for an add instruction, then
7359 After reloading one of the operands into the reload register, add
7360 the reload register to the output register.
7362 If there is another way to do this for a specific machine, a
7363 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7366 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7368 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7369 || (GET_CODE (op1) == REG
7370 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7371 || (code != CODE_FOR_nothing
7372 && ! ((*insn_data[code].operand[2].predicate)
7373 (op1, insn_data[code].operand[2].mode))))
7374 tem = op0, op0 = op1, op1 = tem;
7376 gen_reload (out, op0, opnum, type);
7378 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7379 This fixes a problem on the 32K where the stack pointer cannot
7380 be used as an operand of an add insn. */
7382 if (rtx_equal_p (op0, op1))
7385 insn = emit_insn (gen_add2_insn (out, op1));
7387 /* If that failed, copy the address register to the reload register.
7388 Then add the constant to the reload register. */
7390 code = recog_memoized (insn);
7394 extract_insn (insn);
7395 /* We want constrain operands to treat this insn strictly in
7396 its validity determination, i.e., the way it would after reload
7398 if (constrain_operands (1))
7400 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7402 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7407 delete_insns_since (last);
7409 gen_reload (out, op1, opnum, type);
7410 insn = emit_insn (gen_add2_insn (out, op0));
7411 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7414 #ifdef SECONDARY_MEMORY_NEEDED
7415 /* If we need a memory location to do the move, do it that way. */
7416 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7417 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7418 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7419 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7420 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7421 REGNO_REG_CLASS (reg_or_subregno (out)),
7424 /* Get the memory to use and rewrite both registers to its mode. */
7425 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7427 if (GET_MODE (loc) != GET_MODE (out))
7428 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7430 if (GET_MODE (loc) != GET_MODE (in))
7431 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7433 gen_reload (loc, in, opnum, type);
7434 gen_reload (out, loc, opnum, type);
7438 /* If IN is a simple operand, use gen_move_insn. */
7439 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7440 emit_insn (gen_move_insn (out, in));
7442 #ifdef HAVE_reload_load_address
7443 else if (HAVE_reload_load_address)
7444 emit_insn (gen_reload_load_address (out, in));
7447 /* Otherwise, just write (set OUT IN) and hope for the best. */
7449 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7451 /* Return the first insn emitted.
7452 We can not just return get_last_insn, because there may have
7453 been multiple instructions emitted. Also note that gen_move_insn may
7454 emit more than one insn itself, so we can not assume that there is one
7455 insn emitted per emit_insn_before call. */
7457 return last ? NEXT_INSN (last) : get_insns ();
7460 /* Delete a previously made output-reload whose result we now believe
7461 is not needed. First we double-check.
7463 INSN is the insn now being processed.
7464 LAST_RELOAD_REG is the hard register number for which we want to delete
7465 the last output reload.
7466 J is the reload-number that originally used REG. The caller has made
7467 certain that reload J doesn't use REG any longer for input. */
7470 delete_output_reload (rtx insn, int j, int last_reload_reg)
7472 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7473 rtx reg = spill_reg_stored_to[last_reload_reg];
7476 int n_inherited = 0;
7480 /* It is possible that this reload has been only used to set another reload
7481 we eliminated earlier and thus deleted this instruction too. */
7482 if (INSN_DELETED_P (output_reload_insn))
7485 /* Get the raw pseudo-register referred to. */
7487 while (GET_CODE (reg) == SUBREG)
7488 reg = SUBREG_REG (reg);
7489 substed = reg_equiv_memory_loc[REGNO (reg)];
7491 /* This is unsafe if the operand occurs more often in the current
7492 insn than it is inherited. */
7493 for (k = n_reloads - 1; k >= 0; k--)
7495 rtx reg2 = rld[k].in;
7498 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7499 reg2 = rld[k].in_reg;
7501 if (rld[k].out && ! rld[k].out_reg)
7502 reg2 = XEXP (rld[k].in_reg, 0);
7504 while (GET_CODE (reg2) == SUBREG)
7505 reg2 = SUBREG_REG (reg2);
7506 if (rtx_equal_p (reg2, reg))
7508 if (reload_inherited[k] || reload_override_in[k] || k == j)
7511 reg2 = rld[k].out_reg;
7514 while (GET_CODE (reg2) == SUBREG)
7515 reg2 = XEXP (reg2, 0);
7516 if (rtx_equal_p (reg2, reg))
7523 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7525 n_occurrences += count_occurrences (PATTERN (insn),
7526 eliminate_regs (substed, 0,
7528 if (n_occurrences > n_inherited)
7531 /* If the pseudo-reg we are reloading is no longer referenced
7532 anywhere between the store into it and here,
7533 and no jumps or labels intervene, then the value can get
7534 here through the reload reg alone.
7535 Otherwise, give up--return. */
7536 for (i1 = NEXT_INSN (output_reload_insn);
7537 i1 != insn; i1 = NEXT_INSN (i1))
7539 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7541 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7542 && reg_mentioned_p (reg, PATTERN (i1)))
7544 /* If this is USE in front of INSN, we only have to check that
7545 there are no more references than accounted for by inheritance. */
7546 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7548 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7549 i1 = NEXT_INSN (i1);
7551 if (n_occurrences <= n_inherited && i1 == insn)
7557 /* We will be deleting the insn. Remove the spill reg information. */
7558 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7560 spill_reg_store[last_reload_reg + k] = 0;
7561 spill_reg_stored_to[last_reload_reg + k] = 0;
7564 /* The caller has already checked that REG dies or is set in INSN.
7565 It has also checked that we are optimizing, and thus some
7566 inaccuracies in the debugging information are acceptable.
7567 So we could just delete output_reload_insn. But in some cases
7568 we can improve the debugging information without sacrificing
7569 optimization - maybe even improving the code: See if the pseudo
7570 reg has been completely replaced with reload regs. If so, delete
7571 the store insn and forget we had a stack slot for the pseudo. */
7572 if (rld[j].out != rld[j].in
7573 && REG_N_DEATHS (REGNO (reg)) == 1
7574 && REG_N_SETS (REGNO (reg)) == 1
7575 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7576 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7580 /* We know that it was used only between here and the beginning of
7581 the current basic block. (We also know that the last use before
7582 INSN was the output reload we are thinking of deleting, but never
7583 mind that.) Search that range; see if any ref remains. */
7584 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7586 rtx set = single_set (i2);
7588 /* Uses which just store in the pseudo don't count,
7589 since if they are the only uses, they are dead. */
7590 if (set != 0 && SET_DEST (set) == reg)
7592 if (GET_CODE (i2) == CODE_LABEL
7593 || GET_CODE (i2) == JUMP_INSN)
7595 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7596 && reg_mentioned_p (reg, PATTERN (i2)))
7598 /* Some other ref remains; just delete the output reload we
7600 delete_address_reloads (output_reload_insn, insn);
7601 delete_insn (output_reload_insn);
7606 /* Delete the now-dead stores into this pseudo. Note that this
7607 loop also takes care of deleting output_reload_insn. */
7608 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7610 rtx set = single_set (i2);
7612 if (set != 0 && SET_DEST (set) == reg)
7614 delete_address_reloads (i2, insn);
7617 if (GET_CODE (i2) == CODE_LABEL
7618 || GET_CODE (i2) == JUMP_INSN)
7622 /* For the debugging info, say the pseudo lives in this reload reg. */
7623 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7624 alter_reg (REGNO (reg), -1);
7628 delete_address_reloads (output_reload_insn, insn);
7629 delete_insn (output_reload_insn);
7633 /* We are going to delete DEAD_INSN. Recursively delete loads of
7634 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7635 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7637 delete_address_reloads (rtx dead_insn, rtx current_insn)
7639 rtx set = single_set (dead_insn);
7640 rtx set2, dst, prev, next;
7643 rtx dst = SET_DEST (set);
7644 if (GET_CODE (dst) == MEM)
7645 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7647 /* If we deleted the store from a reloaded post_{in,de}c expression,
7648 we can delete the matching adds. */
7649 prev = PREV_INSN (dead_insn);
7650 next = NEXT_INSN (dead_insn);
7651 if (! prev || ! next)
7653 set = single_set (next);
7654 set2 = single_set (prev);
7656 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7657 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7658 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7660 dst = SET_DEST (set);
7661 if (! rtx_equal_p (dst, SET_DEST (set2))
7662 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7663 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7664 || (INTVAL (XEXP (SET_SRC (set), 1))
7665 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7667 delete_related_insns (prev);
7668 delete_related_insns (next);
7671 /* Subfunction of delete_address_reloads: process registers found in X. */
7673 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7675 rtx prev, set, dst, i2;
7677 enum rtx_code code = GET_CODE (x);
7681 const char *fmt = GET_RTX_FORMAT (code);
7682 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7685 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7686 else if (fmt[i] == 'E')
7688 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7689 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7696 if (spill_reg_order[REGNO (x)] < 0)
7699 /* Scan backwards for the insn that sets x. This might be a way back due
7701 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7703 code = GET_CODE (prev);
7704 if (code == CODE_LABEL || code == JUMP_INSN)
7706 if (GET_RTX_CLASS (code) != 'i')
7708 if (reg_set_p (x, PATTERN (prev)))
7710 if (reg_referenced_p (x, PATTERN (prev)))
7713 if (! prev || INSN_UID (prev) < reload_first_uid)
7715 /* Check that PREV only sets the reload register. */
7716 set = single_set (prev);
7719 dst = SET_DEST (set);
7720 if (GET_CODE (dst) != REG
7721 || ! rtx_equal_p (dst, x))
7723 if (! reg_set_p (dst, PATTERN (dead_insn)))
7725 /* Check if DST was used in a later insn -
7726 it might have been inherited. */
7727 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7729 if (GET_CODE (i2) == CODE_LABEL)
7733 if (reg_referenced_p (dst, PATTERN (i2)))
7735 /* If there is a reference to the register in the current insn,
7736 it might be loaded in a non-inherited reload. If no other
7737 reload uses it, that means the register is set before
7739 if (i2 == current_insn)
7741 for (j = n_reloads - 1; j >= 0; j--)
7742 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7743 || reload_override_in[j] == dst)
7745 for (j = n_reloads - 1; j >= 0; j--)
7746 if (rld[j].in && rld[j].reg_rtx == dst)
7753 if (GET_CODE (i2) == JUMP_INSN)
7755 /* If DST is still live at CURRENT_INSN, check if it is used for
7756 any reload. Note that even if CURRENT_INSN sets DST, we still
7757 have to check the reloads. */
7758 if (i2 == current_insn)
7760 for (j = n_reloads - 1; j >= 0; j--)
7761 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7762 || reload_override_in[j] == dst)
7764 /* ??? We can't finish the loop here, because dst might be
7765 allocated to a pseudo in this block if no reload in this
7766 block needs any of the classes containing DST - see
7767 spill_hard_reg. There is no easy way to tell this, so we
7768 have to scan till the end of the basic block. */
7770 if (reg_set_p (dst, PATTERN (i2)))
7774 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7775 reg_reloaded_contents[REGNO (dst)] = -1;
7779 /* Output reload-insns to reload VALUE into RELOADREG.
7780 VALUE is an autoincrement or autodecrement RTX whose operand
7781 is a register or memory location;
7782 so reloading involves incrementing that location.
7783 IN is either identical to VALUE, or some cheaper place to reload from.
7785 INC_AMOUNT is the number to increment or decrement by (always positive).
7786 This cannot be deduced from VALUE.
7788 Return the instruction that stores into RELOADREG. */
7791 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7793 /* REG or MEM to be copied and incremented. */
7794 rtx incloc = XEXP (value, 0);
7795 /* Nonzero if increment after copying. */
7796 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7802 rtx real_in = in == value ? XEXP (in, 0) : in;
7804 /* No hard register is equivalent to this register after
7805 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7806 we could inc/dec that register as well (maybe even using it for
7807 the source), but I'm not sure it's worth worrying about. */
7808 if (GET_CODE (incloc) == REG)
7809 reg_last_reload_reg[REGNO (incloc)] = 0;
7811 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7812 inc_amount = -inc_amount;
7814 inc = GEN_INT (inc_amount);
7816 /* If this is post-increment, first copy the location to the reload reg. */
7817 if (post && real_in != reloadreg)
7818 emit_insn (gen_move_insn (reloadreg, real_in));
7822 /* See if we can directly increment INCLOC. Use a method similar to
7823 that in gen_reload. */
7825 last = get_last_insn ();
7826 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7827 gen_rtx_PLUS (GET_MODE (incloc),
7830 code = recog_memoized (add_insn);
7833 extract_insn (add_insn);
7834 if (constrain_operands (1))
7836 /* If this is a pre-increment and we have incremented the value
7837 where it lives, copy the incremented value to RELOADREG to
7838 be used as an address. */
7841 emit_insn (gen_move_insn (reloadreg, incloc));
7846 delete_insns_since (last);
7849 /* If couldn't do the increment directly, must increment in RELOADREG.
7850 The way we do this depends on whether this is pre- or post-increment.
7851 For pre-increment, copy INCLOC to the reload register, increment it
7852 there, then save back. */
7856 if (in != reloadreg)
7857 emit_insn (gen_move_insn (reloadreg, real_in));
7858 emit_insn (gen_add2_insn (reloadreg, inc));
7859 store = emit_insn (gen_move_insn (incloc, reloadreg));
7864 Because this might be a jump insn or a compare, and because RELOADREG
7865 may not be available after the insn in an input reload, we must do
7866 the incrementation before the insn being reloaded for.
7868 We have already copied IN to RELOADREG. Increment the copy in
7869 RELOADREG, save that back, then decrement RELOADREG so it has
7870 the original value. */
7872 emit_insn (gen_add2_insn (reloadreg, inc));
7873 store = emit_insn (gen_move_insn (incloc, reloadreg));
7874 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7882 add_auto_inc_notes (rtx insn, rtx x)
7884 enum rtx_code code = GET_CODE (x);
7888 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7891 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7895 /* Scan all the operand sub-expressions. */
7896 fmt = GET_RTX_FORMAT (code);
7897 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7900 add_auto_inc_notes (insn, XEXP (x, i));
7901 else if (fmt[i] == 'E')
7902 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7903 add_auto_inc_notes (insn, XVECEXP (x, i, j));
7908 /* Copy EH notes from an insn to its reloads. */
7910 copy_eh_notes (rtx insn, rtx x)
7912 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7915 for (; x != 0; x = NEXT_INSN (x))
7917 if (may_trap_p (PATTERN (x)))
7919 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
7925 /* This is used by reload pass, that does emit some instructions after
7926 abnormal calls moving basic block end, but in fact it wants to emit
7927 them on the edge. Looks for abnormal call edges, find backward the
7928 proper call and fix the damage.
7930 Similar handle instructions throwing exceptions internally. */
7932 fixup_abnormal_edges (void)
7934 bool inserted = false;
7941 /* Look for cases we are interested in - calls or instructions causing
7943 for (e = bb->succ; e; e = e->succ_next)
7945 if (e->flags & EDGE_ABNORMAL_CALL)
7947 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
7948 == (EDGE_ABNORMAL | EDGE_EH))
7951 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
7953 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
7955 for (e = bb->succ; e; e = e->succ_next)
7956 if (e->flags & EDGE_FALLTHRU)
7958 /* Get past the new insns generated. Allow notes, as the insns may
7959 be already deleted. */
7960 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
7961 && !can_throw_internal (insn)
7962 && insn != bb->head)
7963 insn = PREV_INSN (insn);
7964 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
7968 insn = NEXT_INSN (insn);
7969 while (insn && insn != stop)
7971 next = NEXT_INSN (insn);
7976 /* Sometimes there's still the return value USE.
7977 If it's placed after a trapping call (i.e. that
7978 call is the last insn anyway), we have no fallthru
7979 edge. Simply delete this use and don't try to insert
7980 on the non-existent edge. */
7981 if (GET_CODE (PATTERN (insn)) != USE)
7983 /* We're not deleting it, we're moving it. */
7984 INSN_DELETED_P (insn) = 0;
7985 PREV_INSN (insn) = NULL_RTX;
7986 NEXT_INSN (insn) = NULL_RTX;
7988 insert_insn_on_edge (insn, e);
7995 /* We've possibly turned single trapping insn into multiple ones. */
7996 if (flag_non_call_exceptions)
7999 blocks = sbitmap_alloc (last_basic_block);
8000 sbitmap_ones (blocks);
8001 find_many_sub_basic_blocks (blocks);
8004 commit_edge_insertions ();
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