1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "insn-config.h"
26 #include "insn-flags.h"
27 #include "insn-codes.h"
31 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 /* This file contains the reload pass of the compiler, which is
38 run after register allocation has been done. It checks that
39 each insn is valid (operands required to be in registers really
40 are in registers of the proper class) and fixes up invalid ones
41 by copying values temporarily into registers for the insns
44 The results of register allocation are described by the vector
45 reg_renumber; the insns still contain pseudo regs, but reg_renumber
46 can be used to find which hard reg, if any, a pseudo reg is in.
48 The technique we always use is to free up a few hard regs that are
49 called ``reload regs'', and for each place where a pseudo reg
50 must be in a hard reg, copy it temporarily into one of the reload regs.
52 All the pseudos that were formerly allocated to the hard regs that
53 are now in use as reload regs must be ``spilled''. This means
54 that they go to other hard regs, or to stack slots if no other
55 available hard regs can be found. Spilling can invalidate more
56 insns, requiring additional need for reloads, so we must keep checking
57 until the process stabilizes.
59 For machines with different classes of registers, we must keep track
60 of the register class needed for each reload, and make sure that
61 we allocate enough reload registers of each class.
63 The file reload.c contains the code that checks one insn for
64 validity and reports the reloads that it needs. This file
65 is in charge of scanning the entire rtl code, accumulating the
66 reload needs, spilling, assigning reload registers to use for
67 fixing up each insn, and generating the new insns to copy values
68 into the reload registers. */
71 #ifndef REGISTER_MOVE_COST
72 #define REGISTER_MOVE_COST(x, y) 2
75 #ifndef MEMORY_MOVE_COST
76 #define MEMORY_MOVE_COST(x) 4
79 /* During reload_as_needed, element N contains a REG rtx for the hard reg
80 into which reg N has been reloaded (perhaps for a previous insn). */
81 static rtx *reg_last_reload_reg;
83 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
84 for an output reload that stores into reg N. */
85 static char *reg_has_output_reload;
87 /* Indicates which hard regs are reload-registers for an output reload
88 in the current insn. */
89 static HARD_REG_SET reg_is_output_reload;
91 /* Element N is the constant value to which pseudo reg N is equivalent,
92 or zero if pseudo reg N is not equivalent to a constant.
93 find_reloads looks at this in order to replace pseudo reg N
94 with the constant it stands for. */
95 rtx *reg_equiv_constant;
97 /* Element N is a memory location to which pseudo reg N is equivalent,
98 prior to any register elimination (such as frame pointer to stack
99 pointer). Depending on whether or not it is a valid address, this value
100 is transferred to either reg_equiv_address or reg_equiv_mem. */
101 rtx *reg_equiv_memory_loc;
103 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
104 This is used when the address is not valid as a memory address
105 (because its displacement is too big for the machine.) */
106 rtx *reg_equiv_address;
108 /* Element N is the memory slot to which pseudo reg N is equivalent,
109 or zero if pseudo reg N is not equivalent to a memory slot. */
112 /* Widest width in which each pseudo reg is referred to (via subreg). */
113 static int *reg_max_ref_width;
115 /* Element N is the insn that initialized reg N from its equivalent
116 constant or memory slot. */
117 static rtx *reg_equiv_init;
119 /* During reload_as_needed, element N contains the last pseudo regno
120 reloaded into the Nth reload register. This vector is in parallel
121 with spill_regs. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
126 /* During reload_as_needed, element N contains the insn for which
127 the Nth reload register was last used. This vector is in parallel
128 with spill_regs, and its contents are significant only when
129 reg_reloaded_contents is significant. */
130 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
132 /* Number of spill-regs so far; number of valid elements of spill_regs. */
135 /* In parallel with spill_regs, contains REG rtx's for those regs.
136 Holds the last rtx used for any given reg, or 0 if it has never
137 been used for spilling yet. This rtx is reused, provided it has
139 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
141 /* In parallel with spill_regs, contains nonzero for a spill reg
142 that was stored after the last time it was used.
143 The precise value is the insn generated to do the store. */
144 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
146 /* This table is the inverse mapping of spill_regs:
147 indexed by hard reg number,
148 it contains the position of that reg in spill_regs,
149 or -1 for something that is not in spill_regs. */
150 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
152 /* This reg set indicates registers that may not be used for retrying global
153 allocation. The registers that may not be used include all spill registers
154 and the frame pointer (if we are using one). */
155 HARD_REG_SET forbidden_regs;
157 /* This reg set indicates registers that are not good for spill registers.
158 They will not be used to complete groups of spill registers. This includes
159 all fixed registers, registers that may be eliminated, and, if
160 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
162 (spill_reg_order prevents these registers from being used to start a
164 static HARD_REG_SET bad_spill_regs;
166 /* Describes order of use of registers for reloading
167 of spilled pseudo-registers. `spills' is the number of
168 elements that are actually valid; new ones are added at the end. */
169 static short spill_regs[FIRST_PSEUDO_REGISTER];
171 /* Describes order of preference for putting regs into spill_regs.
172 Contains the numbers of all the hard regs, in order most preferred first.
173 This order is different for each function.
174 It is set up by order_regs_for_reload.
175 Empty elements at the end contain -1. */
176 static short potential_reload_regs[FIRST_PSEUDO_REGISTER];
178 /* 1 for a hard register that appears explicitly in the rtl
179 (for example, function value registers, special registers
180 used by insns, structure value pointer registers). */
181 static char regs_explicitly_used[FIRST_PSEUDO_REGISTER];
183 /* Indicates if a register was counted against the need for
184 groups. 0 means it can count against max_nongroup instead. */
185 static HARD_REG_SET counted_for_groups;
187 /* Indicates if a register was counted against the need for
188 non-groups. 0 means it can become part of a new group.
189 During choose_reload_regs, 1 here means don't use this reg
190 as part of a group, even if it seems to be otherwise ok. */
191 static HARD_REG_SET counted_for_nongroups;
193 /* Nonzero if indirect addressing is supported on the machine; this means
194 that spilling (REG n) does not require reloading it into a register in
195 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
196 value indicates the level of indirect addressing supported, e.g., two
197 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
200 static char spill_indirect_levels;
202 /* Nonzero if indirect addressing is supported when the innermost MEM is
203 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
204 which these are valid is the same as spill_indirect_levels, above. */
206 char indirect_symref_ok;
208 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
210 char double_reg_address_ok;
212 /* Record the stack slot for each spilled hard register. */
214 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
216 /* Width allocated so far for that stack slot. */
218 static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
220 /* Indexed by register class and basic block number, nonzero if there is
221 any need for a spill register of that class in that basic block.
222 The pointer is 0 if we did stupid allocation and don't know
223 the structure of basic blocks. */
225 char *basic_block_needs[N_REG_CLASSES];
227 /* First uid used by insns created by reload in this function.
228 Used in find_equiv_reg. */
229 int reload_first_uid;
231 /* Flag set by local-alloc or global-alloc if anything is live in
232 a call-clobbered reg across calls. */
234 int caller_save_needed;
236 /* Set to 1 while reload_as_needed is operating.
237 Required by some machines to handle any generated moves differently. */
239 int reload_in_progress = 0;
241 /* These arrays record the insn_code of insns that may be needed to
242 perform input and output reloads of special objects. They provide a
243 place to pass a scratch register. */
245 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
246 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
248 /* This obstack is used for allocation of rtl during register elimination.
249 The allocated storage can be freed once find_reloads has processed the
252 struct obstack reload_obstack;
253 char *reload_firstobj;
255 #define obstack_chunk_alloc xmalloc
256 #define obstack_chunk_free free
258 /* List of labels that must never be deleted. */
259 extern rtx forced_labels;
261 /* This structure is used to record information about register eliminations.
262 Each array entry describes one possible way of eliminating a register
263 in favor of another. If there is more than one way of eliminating a
264 particular register, the most preferred should be specified first. */
266 static struct elim_table
268 int from; /* Register number to be eliminated. */
269 int to; /* Register number used as replacement. */
270 int initial_offset; /* Initial difference between values. */
271 int can_eliminate; /* Non-zero if this elimination can be done. */
272 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
273 insns made by reload. */
274 int offset; /* Current offset between the two regs. */
275 int max_offset; /* Maximum offset between the two regs. */
276 int previous_offset; /* Offset at end of previous insn. */
277 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
278 rtx from_rtx; /* REG rtx for the register to be eliminated.
279 We cannot simply compare the number since
280 we might then spuriously replace a hard
281 register corresponding to a pseudo
282 assigned to the reg to be eliminated. */
283 rtx to_rtx; /* REG rtx for the replacement. */
286 /* If a set of eliminable registers was specified, define the table from it.
287 Otherwise, default to the normal case of the frame pointer being
288 replaced by the stack pointer. */
290 #ifdef ELIMINABLE_REGS
293 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
296 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
298 /* Record the number of pending eliminations that have an offset not equal
299 to their initial offset. If non-zero, we use a new copy of each
300 replacement result in any insns encountered. */
301 static int num_not_at_initial_offset;
303 /* Count the number of registers that we may be able to eliminate. */
304 static int num_eliminable;
306 /* For each label, we record the offset of each elimination. If we reach
307 a label by more than one path and an offset differs, we cannot do the
308 elimination. This information is indexed by the number of the label.
309 The first table is an array of flags that records whether we have yet
310 encountered a label and the second table is an array of arrays, one
311 entry in the latter array for each elimination. */
313 static char *offsets_known_at;
314 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
316 /* Number of labels in the current function. */
318 static int num_labels;
320 struct hard_reg_n_uses { int regno; int uses; };
322 static int possible_group_p PROTO((int, int *));
323 static void count_possible_groups PROTO((int *, enum machine_mode *,
325 static int modes_equiv_for_class_p PROTO((enum machine_mode,
328 static void spill_failure PROTO((rtx));
329 static int new_spill_reg PROTO((int, int, int *, int *, int,
331 static void delete_dead_insn PROTO((rtx));
332 static void alter_reg PROTO((int, int));
333 static void set_label_offsets PROTO((rtx, rtx, int));
334 static int eliminate_regs_in_insn PROTO((rtx, int));
335 static void mark_not_eliminable PROTO((rtx, rtx));
336 static int spill_hard_reg PROTO((int, int, FILE *, int));
337 static void scan_paradoxical_subregs PROTO((rtx));
338 static int hard_reg_use_compare PROTO((struct hard_reg_n_uses *,
339 struct hard_reg_n_uses *));
340 static void order_regs_for_reload PROTO((void));
341 static void reload_as_needed PROTO((rtx, int));
342 static void forget_old_reloads_1 PROTO((rtx));
343 static int reload_reg_class_lower PROTO((short *, short *));
344 static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
346 static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
348 static int reload_reg_free_p PROTO((int, int, enum reload_type));
349 static int reload_reg_free_before_p PROTO((int, int, enum reload_type));
350 static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
351 static int allocate_reload_reg PROTO((int, rtx, int, int));
352 static void choose_reload_regs PROTO((rtx, rtx));
353 static void merge_assigned_reloads PROTO((rtx));
354 static void emit_reload_insns PROTO((rtx));
355 static void delete_output_reload PROTO((rtx, int, rtx));
356 static void inc_for_reload PROTO((rtx, rtx, int));
357 static int constraint_accepts_reg_p PROTO((char *, rtx));
358 static int count_occurrences PROTO((rtx, rtx));
360 /* Initialize the reload pass once per compilation. */
367 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
368 Set spill_indirect_levels to the number of levels such addressing is
369 permitted, zero if it is not permitted at all. */
372 = gen_rtx (MEM, Pmode,
373 gen_rtx (PLUS, Pmode,
374 gen_rtx (REG, Pmode, LAST_VIRTUAL_REGISTER + 1),
376 spill_indirect_levels = 0;
378 while (memory_address_p (QImode, tem))
380 spill_indirect_levels++;
381 tem = gen_rtx (MEM, Pmode, tem);
384 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
386 tem = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, Pmode, "foo"));
387 indirect_symref_ok = memory_address_p (QImode, tem);
389 /* See if reg+reg is a valid (and offsettable) address. */
391 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
393 tem = gen_rtx (PLUS, Pmode,
394 gen_rtx (REG, Pmode, FRAME_POINTER_REGNUM),
395 gen_rtx (REG, Pmode, i));
396 /* This way, we make sure that reg+reg is an offsettable address. */
397 tem = plus_constant (tem, 4);
399 if (memory_address_p (QImode, tem))
401 double_reg_address_ok = 1;
406 /* Initialize obstack for our rtl allocation. */
407 gcc_obstack_init (&reload_obstack);
408 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
411 /* Main entry point for the reload pass.
413 FIRST is the first insn of the function being compiled.
415 GLOBAL nonzero means we were called from global_alloc
416 and should attempt to reallocate any pseudoregs that we
417 displace from hard regs we will use for reloads.
418 If GLOBAL is zero, we do not have enough information to do that,
419 so any pseudo reg that is spilled must go to the stack.
421 DUMPFILE is the global-reg debugging dump file stream, or 0.
422 If it is nonzero, messages are written to it to describe
423 which registers are seized as reload regs, which pseudo regs
424 are spilled from them, and where the pseudo regs are reallocated to.
426 Return value is nonzero if reload failed
427 and we must not do any more for this function. */
430 reload (first, global, dumpfile)
438 register struct elim_table *ep;
440 int something_changed;
441 int something_needs_reloads;
442 int something_needs_elimination;
443 int new_basic_block_needs;
444 enum reg_class caller_save_spill_class = NO_REGS;
445 int caller_save_group_size = 1;
447 /* Nonzero means we couldn't get enough spill regs. */
450 /* The basic block number currently being processed for INSN. */
453 /* Make sure even insns with volatile mem refs are recognizable. */
456 /* Enable find_equiv_reg to distinguish insns made by reload. */
457 reload_first_uid = get_max_uid ();
459 for (i = 0; i < N_REG_CLASSES; i++)
460 basic_block_needs[i] = 0;
462 #ifdef SECONDARY_MEMORY_NEEDED
463 /* Initialize the secondary memory table. */
464 clear_secondary_mem ();
467 /* Remember which hard regs appear explicitly
468 before we merge into `regs_ever_live' the ones in which
469 pseudo regs have been allocated. */
470 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live);
472 /* We don't have a stack slot for any spill reg yet. */
473 bzero (spill_stack_slot, sizeof spill_stack_slot);
474 bzero (spill_stack_slot_width, sizeof spill_stack_slot_width);
476 /* Initialize the save area information for caller-save, in case some
480 /* Compute which hard registers are now in use
481 as homes for pseudo registers.
482 This is done here rather than (eg) in global_alloc
483 because this point is reached even if not optimizing. */
485 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
488 /* Make sure that the last insn in the chain
489 is not something that needs reloading. */
490 emit_note (NULL_PTR, NOTE_INSN_DELETED);
492 /* Find all the pseudo registers that didn't get hard regs
493 but do have known equivalent constants or memory slots.
494 These include parameters (known equivalent to parameter slots)
495 and cse'd or loop-moved constant memory addresses.
497 Record constant equivalents in reg_equiv_constant
498 so they will be substituted by find_reloads.
499 Record memory equivalents in reg_mem_equiv so they can
500 be substituted eventually by altering the REG-rtx's. */
502 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx));
503 bzero (reg_equiv_constant, max_regno * sizeof (rtx));
504 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx));
505 bzero (reg_equiv_memory_loc, max_regno * sizeof (rtx));
506 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx));
507 bzero (reg_equiv_mem, max_regno * sizeof (rtx));
508 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx));
509 bzero (reg_equiv_init, max_regno * sizeof (rtx));
510 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx));
511 bzero (reg_equiv_address, max_regno * sizeof (rtx));
512 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int));
513 bzero (reg_max_ref_width, max_regno * sizeof (int));
515 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
516 Also find all paradoxical subregs
517 and find largest such for each pseudo. */
519 for (insn = first; insn; insn = NEXT_INSN (insn))
521 rtx set = single_set (insn);
523 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
525 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
527 #ifdef LEGITIMATE_PIC_OPERAND_P
528 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic
529 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
533 rtx x = XEXP (note, 0);
534 i = REGNO (SET_DEST (set));
535 if (i > LAST_VIRTUAL_REGISTER)
537 if (GET_CODE (x) == MEM)
538 reg_equiv_memory_loc[i] = x;
539 else if (CONSTANT_P (x))
541 if (LEGITIMATE_CONSTANT_P (x))
542 reg_equiv_constant[i] = x;
544 reg_equiv_memory_loc[i]
545 = force_const_mem (GET_MODE (SET_DEST (set)), x);
550 /* If this register is being made equivalent to a MEM
551 and the MEM is not SET_SRC, the equivalencing insn
552 is one with the MEM as a SET_DEST and it occurs later.
553 So don't mark this insn now. */
554 if (GET_CODE (x) != MEM
555 || rtx_equal_p (SET_SRC (set), x))
556 reg_equiv_init[i] = insn;
561 /* If this insn is setting a MEM from a register equivalent to it,
562 this is the equivalencing insn. */
563 else if (set && GET_CODE (SET_DEST (set)) == MEM
564 && GET_CODE (SET_SRC (set)) == REG
565 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
566 && rtx_equal_p (SET_DEST (set),
567 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
568 reg_equiv_init[REGNO (SET_SRC (set))] = insn;
570 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
571 scan_paradoxical_subregs (PATTERN (insn));
574 /* Does this function require a frame pointer? */
576 frame_pointer_needed = (! flag_omit_frame_pointer
577 #ifdef EXIT_IGNORE_STACK
578 /* ?? If EXIT_IGNORE_STACK is set, we will not save
579 and restore sp for alloca. So we can't eliminate
580 the frame pointer in that case. At some point,
581 we should improve this by emitting the
582 sp-adjusting insns for this case. */
583 || (current_function_calls_alloca
584 && EXIT_IGNORE_STACK)
586 || FRAME_POINTER_REQUIRED);
590 /* Initialize the table of registers to eliminate. The way we do this
591 depends on how the eliminable registers were defined. */
592 #ifdef ELIMINABLE_REGS
593 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
595 ep->can_eliminate = ep->can_eliminate_previous
596 = (CAN_ELIMINATE (ep->from, ep->to)
597 && (ep->from != FRAME_POINTER_REGNUM || ! frame_pointer_needed));
600 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
601 = ! frame_pointer_needed;
604 /* Count the number of eliminable registers and build the FROM and TO
605 REG rtx's. Note that code in gen_rtx will cause, e.g.,
606 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
607 We depend on this. */
608 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
610 num_eliminable += ep->can_eliminate;
611 ep->from_rtx = gen_rtx (REG, Pmode, ep->from);
612 ep->to_rtx = gen_rtx (REG, Pmode, ep->to);
615 num_labels = max_label_num () - get_first_label_num ();
617 /* Allocate the tables used to store offset information at labels. */
618 offsets_known_at = (char *) alloca (num_labels);
620 = (int (*)[NUM_ELIMINABLE_REGS])
621 alloca (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
623 offsets_known_at -= get_first_label_num ();
624 offsets_at -= get_first_label_num ();
626 /* Alter each pseudo-reg rtx to contain its hard reg number.
627 Assign stack slots to the pseudos that lack hard regs or equivalents.
628 Do not touch virtual registers. */
630 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
633 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
634 because the stack size may be a part of the offset computation for
635 register elimination. */
636 assign_stack_local (BLKmode, 0, 0);
638 /* If we have some registers we think can be eliminated, scan all insns to
639 see if there is an insn that sets one of these registers to something
640 other than itself plus a constant. If so, the register cannot be
641 eliminated. Doing this scan here eliminates an extra pass through the
642 main reload loop in the most common case where register elimination
644 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
645 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
646 || GET_CODE (insn) == CALL_INSN)
647 note_stores (PATTERN (insn), mark_not_eliminable);
649 #ifndef REGISTER_CONSTRAINTS
650 /* If all the pseudo regs have hard regs,
651 except for those that are never referenced,
652 we know that no reloads are needed. */
653 /* But that is not true if there are register constraints, since
654 in that case some pseudos might be in the wrong kind of hard reg. */
656 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
657 if (reg_renumber[i] == -1 && reg_n_refs[i] != 0)
660 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
664 /* Compute the order of preference for hard registers to spill.
665 Store them by decreasing preference in potential_reload_regs. */
667 order_regs_for_reload ();
669 /* So far, no hard regs have been spilled. */
671 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
672 spill_reg_order[i] = -1;
674 /* On most machines, we can't use any register explicitly used in the
675 rtl as a spill register. But on some, we have to. Those will have
676 taken care to keep the life of hard regs as short as possible. */
678 #ifdef SMALL_REGISTER_CLASSES
679 CLEAR_HARD_REG_SET (forbidden_regs);
681 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs);
684 /* Spill any hard regs that we know we can't eliminate. */
685 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
686 if (! ep->can_eliminate)
688 spill_hard_reg (ep->from, global, dumpfile, 1);
689 regs_ever_live[ep->from] = 1;
693 for (i = 0; i < N_REG_CLASSES; i++)
695 basic_block_needs[i] = (char *)alloca (n_basic_blocks);
696 bzero (basic_block_needs[i], n_basic_blocks);
699 /* From now on, we need to emit any moves without making new pseudos. */
700 reload_in_progress = 1;
702 /* This loop scans the entire function each go-round
703 and repeats until one repetition spills no additional hard regs. */
705 /* This flag is set when a pseudo reg is spilled,
706 to require another pass. Note that getting an additional reload
707 reg does not necessarily imply any pseudo reg was spilled;
708 sometimes we find a reload reg that no pseudo reg was allocated in. */
709 something_changed = 1;
710 /* This flag is set if there are any insns that require reloading. */
711 something_needs_reloads = 0;
712 /* This flag is set if there are any insns that require register
714 something_needs_elimination = 0;
715 while (something_changed)
719 /* For each class, number of reload regs needed in that class.
720 This is the maximum over all insns of the needs in that class
721 of the individual insn. */
722 int max_needs[N_REG_CLASSES];
723 /* For each class, size of group of consecutive regs
724 that is needed for the reloads of this class. */
725 int group_size[N_REG_CLASSES];
726 /* For each class, max number of consecutive groups needed.
727 (Each group contains group_size[CLASS] consecutive registers.) */
728 int max_groups[N_REG_CLASSES];
729 /* For each class, max number needed of regs that don't belong
730 to any of the groups. */
731 int max_nongroups[N_REG_CLASSES];
732 /* For each class, the machine mode which requires consecutive
733 groups of regs of that class.
734 If two different modes ever require groups of one class,
735 they must be the same size and equally restrictive for that class,
736 otherwise we can't handle the complexity. */
737 enum machine_mode group_mode[N_REG_CLASSES];
738 /* Record the insn where each maximum need is first found. */
739 rtx max_needs_insn[N_REG_CLASSES];
740 rtx max_groups_insn[N_REG_CLASSES];
741 rtx max_nongroups_insn[N_REG_CLASSES];
743 int starting_frame_size = get_frame_size ();
744 static char *reg_class_names[] = REG_CLASS_NAMES;
746 something_changed = 0;
747 bzero (max_needs, sizeof max_needs);
748 bzero (max_groups, sizeof max_groups);
749 bzero (max_nongroups, sizeof max_nongroups);
750 bzero (max_needs_insn, sizeof max_needs_insn);
751 bzero (max_groups_insn, sizeof max_groups_insn);
752 bzero (max_nongroups_insn, sizeof max_nongroups_insn);
753 bzero (group_size, sizeof group_size);
754 for (i = 0; i < N_REG_CLASSES; i++)
755 group_mode[i] = VOIDmode;
757 /* Keep track of which basic blocks are needing the reloads. */
760 /* Remember whether any element of basic_block_needs
761 changes from 0 to 1 in this pass. */
762 new_basic_block_needs = 0;
764 /* Reset all offsets on eliminable registers to their initial values. */
765 #ifdef ELIMINABLE_REGS
766 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
768 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
769 ep->previous_offset = ep->offset
770 = ep->max_offset = ep->initial_offset;
773 #ifdef INITIAL_FRAME_POINTER_OFFSET
774 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
776 if (!FRAME_POINTER_REQUIRED)
778 reg_eliminate[0].initial_offset = 0;
780 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset
781 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
784 num_not_at_initial_offset = 0;
786 bzero (&offsets_known_at[get_first_label_num ()], num_labels);
788 /* Set a known offset for each forced label to be at the initial offset
789 of each elimination. We do this because we assume that all
790 computed jumps occur from a location where each elimination is
791 at its initial offset. */
793 for (x = forced_labels; x; x = XEXP (x, 1))
795 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
797 /* For each pseudo register that has an equivalent location defined,
798 try to eliminate any eliminable registers (such as the frame pointer)
799 assuming initial offsets for the replacement register, which
802 If the resulting location is directly addressable, substitute
803 the MEM we just got directly for the old REG.
805 If it is not addressable but is a constant or the sum of a hard reg
806 and constant, it is probably not addressable because the constant is
807 out of range, in that case record the address; we will generate
808 hairy code to compute the address in a register each time it is
811 If the location is not addressable, but does not have one of the
812 above forms, assign a stack slot. We have to do this to avoid the
813 potential of producing lots of reloads if, e.g., a location involves
814 a pseudo that didn't get a hard register and has an equivalent memory
815 location that also involves a pseudo that didn't get a hard register.
817 Perhaps at some point we will improve reload_when_needed handling
818 so this problem goes away. But that's very hairy. */
820 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
821 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
823 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
825 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
827 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
828 else if (CONSTANT_P (XEXP (x, 0))
829 || (GET_CODE (XEXP (x, 0)) == PLUS
830 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
831 && (REGNO (XEXP (XEXP (x, 0), 0))
832 < FIRST_PSEUDO_REGISTER)
833 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
834 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
837 /* Make a new stack slot. Then indicate that something
838 changed so we go back and recompute offsets for
839 eliminable registers because the allocation of memory
840 below might change some offset. reg_equiv_{mem,address}
841 will be set up for this pseudo on the next pass around
843 reg_equiv_memory_loc[i] = 0;
844 reg_equiv_init[i] = 0;
846 something_changed = 1;
850 /* If we allocated another pseudo to the stack, redo elimination
852 if (something_changed)
855 /* If caller-saves needs a group, initialize the group to include
856 the size and mode required for caller-saves. */
858 if (caller_save_group_size > 1)
860 group_mode[(int) caller_save_spill_class] = Pmode;
861 group_size[(int) caller_save_spill_class] = caller_save_group_size;
864 /* Compute the most additional registers needed by any instruction.
865 Collect information separately for each class of regs. */
867 for (insn = first; insn; insn = NEXT_INSN (insn))
869 if (global && this_block + 1 < n_basic_blocks
870 && insn == basic_block_head[this_block+1])
873 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
874 might include REG_LABEL), we need to see what effects this
875 has on the known offsets at labels. */
877 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
878 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
879 && REG_NOTES (insn) != 0))
880 set_label_offsets (insn, insn, 0);
882 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
884 /* Nonzero means don't use a reload reg that overlaps
885 the place where a function value can be returned. */
886 rtx avoid_return_reg = 0;
888 rtx old_body = PATTERN (insn);
889 int old_code = INSN_CODE (insn);
890 rtx old_notes = REG_NOTES (insn);
891 int did_elimination = 0;
892 int max_total_input_groups = 0, max_total_output_groups = 0;
894 /* To compute the number of reload registers of each class
895 needed for an insn, we must similate what choose_reload_regs
896 can do. We do this by splitting an insn into an "input" and
897 an "output" part. RELOAD_OTHER reloads are used in both.
898 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
899 which must be live over the entire input section of reloads,
900 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
901 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
904 The registers needed for output are RELOAD_OTHER and
905 RELOAD_FOR_OUTPUT, which are live for the entire output
906 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
907 reloads for each operand.
909 The total number of registers needed is the maximum of the
910 inputs and outputs. */
912 /* These just count RELOAD_OTHER. */
913 int insn_needs[N_REG_CLASSES];
914 int insn_groups[N_REG_CLASSES];
915 int insn_total_groups = 0;
917 /* Count RELOAD_FOR_INPUT reloads. */
918 int insn_needs_for_inputs[N_REG_CLASSES];
919 int insn_groups_for_inputs[N_REG_CLASSES];
920 int insn_total_groups_for_inputs = 0;
922 /* Count RELOAD_FOR_OUTPUT reloads. */
923 int insn_needs_for_outputs[N_REG_CLASSES];
924 int insn_groups_for_outputs[N_REG_CLASSES];
925 int insn_total_groups_for_outputs = 0;
927 /* Count RELOAD_FOR_INSN reloads. */
928 int insn_needs_for_insn[N_REG_CLASSES];
929 int insn_groups_for_insn[N_REG_CLASSES];
930 int insn_total_groups_for_insn = 0;
932 /* Count RELOAD_FOR_OTHER_ADDRESS reloads. */
933 int insn_needs_for_other_addr[N_REG_CLASSES];
934 int insn_groups_for_other_addr[N_REG_CLASSES];
935 int insn_total_groups_for_other_addr = 0;
937 /* Count RELOAD_FOR_INPUT_ADDRESS reloads. */
938 int insn_needs_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
939 int insn_groups_for_in_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
940 int insn_total_groups_for_in_addr[MAX_RECOG_OPERANDS];
942 /* Count RELOAD_FOR_OUTPUT_ADDRESS reloads. */
943 int insn_needs_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
944 int insn_groups_for_out_addr[MAX_RECOG_OPERANDS][N_REG_CLASSES];
945 int insn_total_groups_for_out_addr[MAX_RECOG_OPERANDS];
947 /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
948 int insn_needs_for_op_addr[N_REG_CLASSES];
949 int insn_groups_for_op_addr[N_REG_CLASSES];
950 int insn_total_groups_for_op_addr = 0;
952 #if 0 /* This wouldn't work nowadays, since optimize_bit_field
953 looks for non-strict memory addresses. */
954 /* Optimization: a bit-field instruction whose field
955 happens to be a byte or halfword in memory
956 can be changed to a move instruction. */
958 if (GET_CODE (PATTERN (insn)) == SET)
960 rtx dest = SET_DEST (PATTERN (insn));
961 rtx src = SET_SRC (PATTERN (insn));
963 if (GET_CODE (dest) == ZERO_EXTRACT
964 || GET_CODE (dest) == SIGN_EXTRACT)
965 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
966 if (GET_CODE (src) == ZERO_EXTRACT
967 || GET_CODE (src) == SIGN_EXTRACT)
968 optimize_bit_field (PATTERN (insn), insn, reg_equiv_mem);
972 /* If needed, eliminate any eliminable registers. */
974 did_elimination = eliminate_regs_in_insn (insn, 0);
976 #ifdef SMALL_REGISTER_CLASSES
977 /* Set avoid_return_reg if this is an insn
978 that might use the value of a function call. */
979 if (GET_CODE (insn) == CALL_INSN)
981 if (GET_CODE (PATTERN (insn)) == SET)
982 after_call = SET_DEST (PATTERN (insn));
983 else if (GET_CODE (PATTERN (insn)) == PARALLEL
984 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
985 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
989 else if (after_call != 0
990 && !(GET_CODE (PATTERN (insn)) == SET
991 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
993 if (reg_mentioned_p (after_call, PATTERN (insn)))
994 avoid_return_reg = after_call;
997 #endif /* SMALL_REGISTER_CLASSES */
999 /* Analyze the instruction. */
1000 find_reloads (insn, 0, spill_indirect_levels, global,
1003 /* Remember for later shortcuts which insns had any reloads or
1004 register eliminations.
1006 One might think that it would be worthwhile to mark insns
1007 that need register replacements but not reloads, but this is
1008 not safe because find_reloads may do some manipulation of
1009 the insn (such as swapping commutative operands), which would
1010 be lost when we restore the old pattern after register
1011 replacement. So the actions of find_reloads must be redone in
1012 subsequent passes or in reload_as_needed.
1014 However, it is safe to mark insns that need reloads
1015 but not register replacement. */
1017 PUT_MODE (insn, (did_elimination ? QImode
1018 : n_reloads ? HImode
1019 : GET_MODE (insn) == DImode ? DImode
1022 /* Discard any register replacements done. */
1023 if (did_elimination)
1025 obstack_free (&reload_obstack, reload_firstobj);
1026 PATTERN (insn) = old_body;
1027 INSN_CODE (insn) = old_code;
1028 REG_NOTES (insn) = old_notes;
1029 something_needs_elimination = 1;
1032 /* If this insn has no reloads, we need not do anything except
1033 in the case of a CALL_INSN when we have caller-saves and
1034 caller-save needs reloads. */
1037 && ! (GET_CODE (insn) == CALL_INSN
1038 && caller_save_spill_class != NO_REGS))
1041 something_needs_reloads = 1;
1043 for (i = 0; i < N_REG_CLASSES; i++)
1045 insn_needs[i] = 0, insn_groups[i] = 0;
1046 insn_needs_for_inputs[i] = 0, insn_groups_for_inputs[i] = 0;
1047 insn_needs_for_outputs[i] = 0, insn_groups_for_outputs[i] = 0;
1048 insn_needs_for_insn[i] = 0, insn_groups_for_insn[i] = 0;
1049 insn_needs_for_op_addr[i] = 0, insn_groups_for_op_addr[i] = 0;
1050 insn_needs_for_other_addr[i] = 0;
1051 insn_groups_for_other_addr[i] = 0;
1054 for (i = 0; i < reload_n_operands; i++)
1056 insn_total_groups_for_in_addr[i] = 0;
1057 insn_total_groups_for_out_addr[i] = 0;
1059 for (j = 0; j < N_REG_CLASSES; j++)
1061 insn_needs_for_in_addr[i][j] = 0;
1062 insn_needs_for_out_addr[i][j] = 0;
1063 insn_groups_for_in_addr[i][j] = 0;
1064 insn_groups_for_out_addr[i][j] = 0;
1068 /* Count each reload once in every class
1069 containing the reload's own class. */
1071 for (i = 0; i < n_reloads; i++)
1073 register enum reg_class *p;
1074 enum reg_class class = reload_reg_class[i];
1076 enum machine_mode mode;
1079 int *this_total_groups;
1081 /* Don't count the dummy reloads, for which one of the
1082 regs mentioned in the insn can be used for reloading.
1083 Don't count optional reloads.
1084 Don't count reloads that got combined with others. */
1085 if (reload_reg_rtx[i] != 0
1086 || reload_optional[i] != 0
1087 || (reload_out[i] == 0 && reload_in[i] == 0
1088 && ! reload_secondary_p[i]))
1091 /* Show that a reload register of this class is needed
1092 in this basic block. We do not use insn_needs and
1093 insn_groups because they are overly conservative for
1095 if (global && ! basic_block_needs[(int) class][this_block])
1097 basic_block_needs[(int) class][this_block] = 1;
1098 new_basic_block_needs = 1;
1101 /* Decide which time-of-use to count this reload for. */
1102 switch (reload_when_needed[i])
1105 this_needs = insn_needs;
1106 this_groups = insn_groups;
1107 this_total_groups = &insn_total_groups;
1110 case RELOAD_FOR_INPUT:
1111 this_needs = insn_needs_for_inputs;
1112 this_groups = insn_groups_for_inputs;
1113 this_total_groups = &insn_total_groups_for_inputs;
1116 case RELOAD_FOR_OUTPUT:
1117 this_needs = insn_needs_for_outputs;
1118 this_groups = insn_groups_for_outputs;
1119 this_total_groups = &insn_total_groups_for_outputs;
1122 case RELOAD_FOR_INSN:
1123 this_needs = insn_needs_for_insn;
1124 this_groups = insn_groups_for_outputs;
1125 this_total_groups = &insn_total_groups_for_insn;
1128 case RELOAD_FOR_OTHER_ADDRESS:
1129 this_needs = insn_needs_for_other_addr;
1130 this_groups = insn_groups_for_other_addr;
1131 this_total_groups = &insn_total_groups_for_other_addr;
1134 case RELOAD_FOR_INPUT_ADDRESS:
1135 this_needs = insn_needs_for_in_addr[reload_opnum[i]];
1136 this_groups = insn_groups_for_in_addr[reload_opnum[i]];
1138 = &insn_total_groups_for_in_addr[reload_opnum[i]];
1141 case RELOAD_FOR_OUTPUT_ADDRESS:
1142 this_needs = insn_needs_for_out_addr[reload_opnum[i]];
1143 this_groups = insn_groups_for_out_addr[reload_opnum[i]];
1145 = &insn_total_groups_for_out_addr[reload_opnum[i]];
1148 case RELOAD_FOR_OPERAND_ADDRESS:
1149 this_needs = insn_needs_for_op_addr;
1150 this_groups = insn_groups_for_op_addr;
1151 this_total_groups = &insn_total_groups_for_op_addr;
1155 mode = reload_inmode[i];
1156 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
1157 mode = reload_outmode[i];
1158 size = CLASS_MAX_NREGS (class, mode);
1161 enum machine_mode other_mode, allocate_mode;
1163 /* Count number of groups needed separately from
1164 number of individual regs needed. */
1165 this_groups[(int) class]++;
1166 p = reg_class_superclasses[(int) class];
1167 while (*p != LIM_REG_CLASSES)
1168 this_groups[(int) *p++]++;
1169 (*this_total_groups)++;
1171 /* Record size and mode of a group of this class. */
1172 /* If more than one size group is needed,
1173 make all groups the largest needed size. */
1174 if (group_size[(int) class] < size)
1176 other_mode = group_mode[(int) class];
1177 allocate_mode = mode;
1179 group_size[(int) class] = size;
1180 group_mode[(int) class] = mode;
1185 allocate_mode = group_mode[(int) class];
1188 /* Crash if two dissimilar machine modes both need
1189 groups of consecutive regs of the same class. */
1191 if (other_mode != VOIDmode
1192 && other_mode != allocate_mode
1193 && ! modes_equiv_for_class_p (allocate_mode,
1200 this_needs[(int) class] += 1;
1201 p = reg_class_superclasses[(int) class];
1202 while (*p != LIM_REG_CLASSES)
1203 this_needs[(int) *p++] += 1;
1209 /* All reloads have been counted for this insn;
1210 now merge the various times of use.
1211 This sets insn_needs, etc., to the maximum total number
1212 of registers needed at any point in this insn. */
1214 for (i = 0; i < N_REG_CLASSES; i++)
1216 int in_max, out_max;
1218 for (in_max = 0, out_max = 0, j = 0;
1219 j < reload_n_operands; j++)
1221 in_max = MAX (in_max, insn_needs_for_in_addr[j][i]);
1222 out_max = MAX (out_max, insn_needs_for_out_addr[j][i]);
1225 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1226 and operand addresses but not things used to reload them.
1227 Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads don't
1228 conflict with things needed to reload inputs or
1231 in_max = MAX (in_max, insn_needs_for_op_addr[i]);
1232 out_max = MAX (out_max, insn_needs_for_insn[i]);
1234 insn_needs_for_inputs[i]
1235 = MAX (insn_needs_for_inputs[i]
1236 + insn_needs_for_op_addr[i]
1237 + insn_needs_for_insn[i],
1238 in_max + insn_needs_for_inputs[i]);
1240 insn_needs_for_outputs[i] += out_max;
1241 insn_needs[i] += MAX (MAX (insn_needs_for_inputs[i],
1242 insn_needs_for_outputs[i]),
1243 insn_needs_for_other_addr[i]);
1245 for (in_max = 0, out_max = 0, j = 0;
1246 j < reload_n_operands; j++)
1248 in_max = MAX (in_max, insn_groups_for_in_addr[j][i]);
1249 out_max = MAX (out_max, insn_groups_for_out_addr[j][i]);
1252 in_max = MAX (in_max, insn_groups_for_op_addr[i]);
1253 out_max = MAX (out_max, insn_groups_for_insn[i]);
1255 insn_groups_for_inputs[i]
1256 = MAX (insn_groups_for_inputs[i]
1257 + insn_groups_for_op_addr[i]
1258 + insn_groups_for_insn[i],
1259 in_max + insn_groups_for_inputs[i]);
1261 insn_groups_for_outputs[i] += out_max;
1262 insn_groups[i] += MAX (MAX (insn_groups_for_inputs[i],
1263 insn_groups_for_outputs[i]),
1264 insn_groups_for_other_addr[i]);
1267 for (i = 0; i < reload_n_operands; i++)
1269 max_total_input_groups
1270 = MAX (max_total_input_groups,
1271 insn_total_groups_for_in_addr[i]);
1272 max_total_output_groups
1273 = MAX (max_total_output_groups,
1274 insn_total_groups_for_out_addr[i]);
1277 max_total_input_groups = MAX (max_total_input_groups,
1278 insn_total_groups_for_op_addr);
1279 max_total_output_groups = MAX (max_total_output_groups,
1280 insn_total_groups_for_insn);
1282 insn_total_groups_for_inputs
1283 = MAX (max_total_input_groups + insn_total_groups_for_op_addr
1284 + insn_total_groups_for_insn,
1285 max_total_input_groups + insn_total_groups_for_inputs);
1287 insn_total_groups_for_outputs += max_total_output_groups;
1289 insn_total_groups += MAX (MAX (insn_total_groups_for_outputs,
1290 insn_total_groups_for_inputs),
1291 insn_total_groups_for_other_addr);
1293 /* If this is a CALL_INSN and caller-saves will need
1294 a spill register, act as if the spill register is
1295 needed for this insn. However, the spill register
1296 can be used by any reload of this insn, so we only
1297 need do something if no need for that class has
1300 The assumption that every CALL_INSN will trigger a
1301 caller-save is highly conservative, however, the number
1302 of cases where caller-saves will need a spill register but
1303 a block containing a CALL_INSN won't need a spill register
1304 of that class should be quite rare.
1306 If a group is needed, the size and mode of the group will
1307 have been set up at the beginning of this loop. */
1309 if (GET_CODE (insn) == CALL_INSN
1310 && caller_save_spill_class != NO_REGS)
1312 int *caller_save_needs
1313 = (caller_save_group_size > 1 ? insn_groups : insn_needs);
1315 if (caller_save_needs[(int) caller_save_spill_class] == 0)
1317 register enum reg_class *p
1318 = reg_class_superclasses[(int) caller_save_spill_class];
1320 caller_save_needs[(int) caller_save_spill_class]++;
1322 while (*p != LIM_REG_CLASSES)
1323 caller_save_needs[(int) *p++] += 1;
1326 if (caller_save_group_size > 1)
1327 insn_total_groups = MAX (insn_total_groups, 1);
1330 /* Show that this basic block will need a register of
1334 && ! (basic_block_needs[(int) caller_save_spill_class]
1337 basic_block_needs[(int) caller_save_spill_class]
1339 new_basic_block_needs = 1;
1343 #ifdef SMALL_REGISTER_CLASSES
1344 /* If this insn stores the value of a function call,
1345 and that value is in a register that has been spilled,
1346 and if the insn needs a reload in a class
1347 that might use that register as the reload register,
1348 then add add an extra need in that class.
1349 This makes sure we have a register available that does
1350 not overlap the return value. */
1351 if (avoid_return_reg)
1353 int regno = REGNO (avoid_return_reg);
1355 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
1357 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES];
1359 /* First compute the "basic needs", which counts a
1360 need only in the smallest class in which it
1363 bcopy (insn_needs, basic_needs, sizeof basic_needs);
1364 bcopy (insn_groups, basic_groups, sizeof basic_groups);
1366 for (i = 0; i < N_REG_CLASSES; i++)
1370 if (basic_needs[i] >= 0)
1371 for (p = reg_class_superclasses[i];
1372 *p != LIM_REG_CLASSES; p++)
1373 basic_needs[(int) *p] -= basic_needs[i];
1375 if (basic_groups[i] >= 0)
1376 for (p = reg_class_superclasses[i];
1377 *p != LIM_REG_CLASSES; p++)
1378 basic_groups[(int) *p] -= basic_groups[i];
1381 /* Now count extra regs if there might be a conflict with
1382 the return value register.
1384 ??? This is not quite correct because we don't properly
1385 handle the case of groups, but if we end up doing
1386 something wrong, it either will end up not mattering or
1387 we will abort elsewhere. */
1389 for (r = regno; r < regno + nregs; r++)
1390 if (spill_reg_order[r] >= 0)
1391 for (i = 0; i < N_REG_CLASSES; i++)
1392 if (TEST_HARD_REG_BIT (reg_class_contents[i], r))
1394 if (basic_needs[i] > 0 || basic_groups[i] > 0)
1399 p = reg_class_superclasses[i];
1400 while (*p != LIM_REG_CLASSES)
1401 insn_needs[(int) *p++]++;
1405 #endif /* SMALL_REGISTER_CLASSES */
1407 /* For each class, collect maximum need of any insn. */
1409 for (i = 0; i < N_REG_CLASSES; i++)
1411 if (max_needs[i] < insn_needs[i])
1413 max_needs[i] = insn_needs[i];
1414 max_needs_insn[i] = insn;
1416 if (max_groups[i] < insn_groups[i])
1418 max_groups[i] = insn_groups[i];
1419 max_groups_insn[i] = insn;
1421 if (insn_total_groups > 0)
1422 if (max_nongroups[i] < insn_needs[i])
1424 max_nongroups[i] = insn_needs[i];
1425 max_nongroups_insn[i] = insn;
1429 /* Note that there is a continue statement above. */
1432 /* If we allocated any new memory locations, make another pass
1433 since it might have changed elimination offsets. */
1434 if (starting_frame_size != get_frame_size ())
1435 something_changed = 1;
1438 for (i = 0; i < N_REG_CLASSES; i++)
1440 if (max_needs[i] > 0)
1442 ";; Need %d reg%s of class %s (for insn %d).\n",
1443 max_needs[i], max_needs[i] == 1 ? "" : "s",
1444 reg_class_names[i], INSN_UID (max_needs_insn[i]));
1445 if (max_nongroups[i] > 0)
1447 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1448 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s",
1449 reg_class_names[i], INSN_UID (max_nongroups_insn[i]));
1450 if (max_groups[i] > 0)
1452 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1453 max_groups[i], max_groups[i] == 1 ? "" : "s",
1454 mode_name[(int) group_mode[i]],
1455 reg_class_names[i], INSN_UID (max_groups_insn[i]));
1458 /* If we have caller-saves, set up the save areas and see if caller-save
1459 will need a spill register. */
1461 if (caller_save_needed
1462 && ! setup_save_areas (&something_changed)
1463 && caller_save_spill_class == NO_REGS)
1465 /* The class we will need depends on whether the machine
1466 supports the sum of two registers for an address; see
1467 find_address_reloads for details. */
1469 caller_save_spill_class
1470 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS;
1471 caller_save_group_size
1472 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode);
1473 something_changed = 1;
1476 /* See if anything that happened changes which eliminations are valid.
1477 For example, on the Sparc, whether or not the frame pointer can
1478 be eliminated can depend on what registers have been used. We need
1479 not check some conditions again (such as flag_omit_frame_pointer)
1480 since they can't have changed. */
1482 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1483 if ((ep->from == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
1484 #ifdef ELIMINABLE_REGS
1485 || ! CAN_ELIMINATE (ep->from, ep->to)
1488 ep->can_eliminate = 0;
1490 /* Look for the case where we have discovered that we can't replace
1491 register A with register B and that means that we will now be
1492 trying to replace register A with register C. This means we can
1493 no longer replace register C with register B and we need to disable
1494 such an elimination, if it exists. This occurs often with A == ap,
1495 B == sp, and C == fp. */
1497 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1499 struct elim_table *op;
1500 register int new_to = -1;
1502 if (! ep->can_eliminate && ep->can_eliminate_previous)
1504 /* Find the current elimination for ep->from, if there is a
1506 for (op = reg_eliminate;
1507 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1508 if (op->from == ep->from && op->can_eliminate)
1514 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1516 for (op = reg_eliminate;
1517 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
1518 if (op->from == new_to && op->to == ep->to)
1519 op->can_eliminate = 0;
1523 /* See if any registers that we thought we could eliminate the previous
1524 time are no longer eliminable. If so, something has changed and we
1525 must spill the register. Also, recompute the number of eliminable
1526 registers and see if the frame pointer is needed; it is if there is
1527 no elimination of the frame pointer that we can perform. */
1529 frame_pointer_needed = 1;
1530 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1532 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM)
1533 frame_pointer_needed = 0;
1535 if (! ep->can_eliminate && ep->can_eliminate_previous)
1537 ep->can_eliminate_previous = 0;
1538 spill_hard_reg (ep->from, global, dumpfile, 1);
1539 regs_ever_live[ep->from] = 1;
1540 something_changed = 1;
1545 /* If all needs are met, we win. */
1547 for (i = 0; i < N_REG_CLASSES; i++)
1548 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0)
1550 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed)
1553 /* Not all needs are met; must spill some hard regs. */
1555 /* Put all registers spilled so far back in potential_reload_regs, but
1556 put them at the front, since we've already spilled most of the
1557 psuedos in them (we might have left some pseudos unspilled if they
1558 were in a block that didn't need any spill registers of a conflicting
1559 class. We used to try to mark off the need for those registers,
1560 but doing so properly is very complex and reallocating them is the
1561 simpler approach. First, "pack" potential_reload_regs by pushing
1562 any nonnegative entries towards the end. That will leave room
1563 for the registers we already spilled.
1565 Also, undo the marking of the spill registers from the last time
1566 around in FORBIDDEN_REGS since we will be probably be allocating
1569 ??? It is theoretically possible that we might end up not using one
1570 of our previously-spilled registers in this allocation, even though
1571 they are at the head of the list. It's not clear what to do about
1572 this, but it was no better before, when we marked off the needs met
1573 by the previously-spilled registers. With the current code, globals
1574 can be allocated into these registers, but locals cannot. */
1578 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
1579 if (potential_reload_regs[i] != -1)
1580 potential_reload_regs[j--] = potential_reload_regs[i];
1582 for (i = 0; i < n_spills; i++)
1584 potential_reload_regs[i] = spill_regs[i];
1585 spill_reg_order[spill_regs[i]] = -1;
1586 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]);
1592 /* Now find more reload regs to satisfy the remaining need
1593 Do it by ascending class number, since otherwise a reg
1594 might be spilled for a big class and might fail to count
1595 for a smaller class even though it belongs to that class.
1597 Count spilled regs in `spills', and add entries to
1598 `spill_regs' and `spill_reg_order'.
1600 ??? Note there is a problem here.
1601 When there is a need for a group in a high-numbered class,
1602 and also need for non-group regs that come from a lower class,
1603 the non-group regs are chosen first. If there aren't many regs,
1604 they might leave no room for a group.
1606 This was happening on the 386. To fix it, we added the code
1607 that calls possible_group_p, so that the lower class won't
1608 break up the last possible group.
1610 Really fixing the problem would require changes above
1611 in counting the regs already spilled, and in choose_reload_regs.
1612 It might be hard to avoid introducing bugs there. */
1614 CLEAR_HARD_REG_SET (counted_for_groups);
1615 CLEAR_HARD_REG_SET (counted_for_nongroups);
1617 for (class = 0; class < N_REG_CLASSES; class++)
1619 /* First get the groups of registers.
1620 If we got single registers first, we might fragment
1622 while (max_groups[class] > 0)
1624 /* If any single spilled regs happen to form groups,
1625 count them now. Maybe we don't really need
1626 to spill another group. */
1627 count_possible_groups (group_size, group_mode, max_groups);
1629 if (max_groups[class] <= 0)
1632 /* Groups of size 2 (the only groups used on most machines)
1633 are treated specially. */
1634 if (group_size[class] == 2)
1636 /* First, look for a register that will complete a group. */
1637 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1641 j = potential_reload_regs[i];
1642 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j)
1644 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0)
1645 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1646 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1647 && HARD_REGNO_MODE_OK (other, group_mode[class])
1648 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1650 /* We don't want one part of another group.
1651 We could get "two groups" that overlap! */
1652 && ! TEST_HARD_REG_BIT (counted_for_groups, other))
1654 (j < FIRST_PSEUDO_REGISTER - 1
1655 && (other = j + 1, spill_reg_order[other] >= 0)
1656 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1657 && TEST_HARD_REG_BIT (reg_class_contents[class], other)
1658 && HARD_REGNO_MODE_OK (j, group_mode[class])
1659 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1661 && ! TEST_HARD_REG_BIT (counted_for_groups,
1664 register enum reg_class *p;
1666 /* We have found one that will complete a group,
1667 so count off one group as provided. */
1668 max_groups[class]--;
1669 p = reg_class_superclasses[class];
1670 while (*p != LIM_REG_CLASSES)
1671 max_groups[(int) *p++]--;
1673 /* Indicate both these regs are part of a group. */
1674 SET_HARD_REG_BIT (counted_for_groups, j);
1675 SET_HARD_REG_BIT (counted_for_groups, other);
1679 /* We can't complete a group, so start one. */
1680 if (i == FIRST_PSEUDO_REGISTER)
1681 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1683 j = potential_reload_regs[i];
1684 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER
1685 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0
1686 && TEST_HARD_REG_BIT (reg_class_contents[class], j)
1687 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1)
1688 && HARD_REGNO_MODE_OK (j, group_mode[class])
1689 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
1694 /* I should be the index in potential_reload_regs
1695 of the new reload reg we have found. */
1697 if (i >= FIRST_PSEUDO_REGISTER)
1699 /* There are no groups left to spill. */
1700 spill_failure (max_groups_insn[class]);
1706 |= new_spill_reg (i, class, max_needs, NULL_PTR,
1711 /* For groups of more than 2 registers,
1712 look for a sufficient sequence of unspilled registers,
1713 and spill them all at once. */
1714 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1718 j = potential_reload_regs[i];
1720 && j + group_size[class] <= FIRST_PSEUDO_REGISTER
1721 && HARD_REGNO_MODE_OK (j, group_mode[class]))
1723 /* Check each reg in the sequence. */
1724 for (k = 0; k < group_size[class]; k++)
1725 if (! (spill_reg_order[j + k] < 0
1726 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k)
1727 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k)))
1729 /* We got a full sequence, so spill them all. */
1730 if (k == group_size[class])
1732 register enum reg_class *p;
1733 for (k = 0; k < group_size[class]; k++)
1736 SET_HARD_REG_BIT (counted_for_groups, j + k);
1737 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++)
1738 if (potential_reload_regs[idx] == j + k)
1741 |= new_spill_reg (idx, class,
1742 max_needs, NULL_PTR,
1746 /* We have found one that will complete a group,
1747 so count off one group as provided. */
1748 max_groups[class]--;
1749 p = reg_class_superclasses[class];
1750 while (*p != LIM_REG_CLASSES)
1751 max_groups[(int) *p++]--;
1757 /* We couldn't find any registers for this reload.
1758 Avoid going into an infinite loop. */
1759 if (i >= FIRST_PSEUDO_REGISTER)
1761 /* There are no groups left. */
1762 spill_failure (max_groups_insn[class]);
1769 /* Now similarly satisfy all need for single registers. */
1771 while (max_needs[class] > 0 || max_nongroups[class] > 0)
1773 /* Consider the potential reload regs that aren't
1774 yet in use as reload regs, in order of preference.
1775 Find the most preferred one that's in this class. */
1777 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1778 if (potential_reload_regs[i] >= 0
1779 && TEST_HARD_REG_BIT (reg_class_contents[class],
1780 potential_reload_regs[i])
1781 /* If this reg will not be available for groups,
1782 pick one that does not foreclose possible groups.
1783 This is a kludge, and not very general,
1784 but it should be sufficient to make the 386 work,
1785 and the problem should not occur on machines with
1787 && (max_nongroups[class] == 0
1788 || possible_group_p (potential_reload_regs[i], max_groups)))
1791 /* If we couldn't get a register, try to get one even if we
1792 might foreclose possible groups. This may cause problems
1793 later, but that's better than aborting now, since it is
1794 possible that we will, in fact, be able to form the needed
1795 group even with this allocation. */
1797 if (i >= FIRST_PSEUDO_REGISTER
1798 && (asm_noperands (max_needs[class] > 0
1799 ? max_needs_insn[class]
1800 : max_nongroups_insn[class])
1802 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1803 if (potential_reload_regs[i] >= 0
1804 && TEST_HARD_REG_BIT (reg_class_contents[class],
1805 potential_reload_regs[i]))
1808 /* I should be the index in potential_reload_regs
1809 of the new reload reg we have found. */
1811 if (i >= FIRST_PSEUDO_REGISTER)
1813 /* There are no possible registers left to spill. */
1814 spill_failure (max_needs[class] > 0 ? max_needs_insn[class]
1815 : max_nongroups_insn[class]);
1821 |= new_spill_reg (i, class, max_needs, max_nongroups,
1827 /* If global-alloc was run, notify it of any register eliminations we have
1830 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1831 if (ep->can_eliminate)
1832 mark_elimination (ep->from, ep->to);
1834 /* Insert code to save and restore call-clobbered hard regs
1835 around calls. Tell if what mode to use so that we will process
1836 those insns in reload_as_needed if we have to. */
1838 if (caller_save_needed)
1839 save_call_clobbered_regs (num_eliminable ? QImode
1840 : caller_save_spill_class != NO_REGS ? HImode
1843 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1844 If that insn didn't set the register (i.e., it copied the register to
1845 memory), just delete that insn instead of the equivalencing insn plus
1846 anything now dead. If we call delete_dead_insn on that insn, we may
1847 delete the insn that actually sets the register if the register die
1848 there and that is incorrect. */
1850 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1851 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0
1852 && GET_CODE (reg_equiv_init[i]) != NOTE)
1854 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i])))
1855 delete_dead_insn (reg_equiv_init[i]);
1858 PUT_CODE (reg_equiv_init[i], NOTE);
1859 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0;
1860 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED;
1864 /* Use the reload registers where necessary
1865 by generating move instructions to move the must-be-register
1866 values into or out of the reload registers. */
1868 if (something_needs_reloads || something_needs_elimination
1869 || (caller_save_needed && num_eliminable)
1870 || caller_save_spill_class != NO_REGS)
1871 reload_as_needed (first, global);
1873 /* If we were able to eliminate the frame pointer, show that it is no
1874 longer live at the start of any basic block. If it ls live by
1875 virtue of being in a pseudo, that pseudo will be marked live
1876 and hence the frame pointer will be known to be live via that
1879 if (! frame_pointer_needed)
1880 for (i = 0; i < n_basic_blocks; i++)
1881 basic_block_live_at_start[i][FRAME_POINTER_REGNUM / REGSET_ELT_BITS]
1882 &= ~ ((REGSET_ELT_TYPE) 1 << (FRAME_POINTER_REGNUM % REGSET_ELT_BITS));
1884 /* Come here (with failure set nonzero) if we can't get enough spill regs
1885 and we decide not to abort about it. */
1888 reload_in_progress = 0;
1890 /* Now eliminate all pseudo regs by modifying them into
1891 their equivalent memory references.
1892 The REG-rtx's for the pseudos are modified in place,
1893 so all insns that used to refer to them now refer to memory.
1895 For a reg that has a reg_equiv_address, all those insns
1896 were changed by reloading so that no insns refer to it any longer;
1897 but the DECL_RTL of a variable decl may refer to it,
1898 and if so this causes the debugging info to mention the variable. */
1900 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1904 if (reg_equiv_mem[i])
1906 addr = XEXP (reg_equiv_mem[i], 0);
1907 in_struct = MEM_IN_STRUCT_P (reg_equiv_mem[i]);
1909 if (reg_equiv_address[i])
1910 addr = reg_equiv_address[i];
1913 if (reg_renumber[i] < 0)
1915 rtx reg = regno_reg_rtx[i];
1916 XEXP (reg, 0) = addr;
1917 REG_USERVAR_P (reg) = 0;
1918 MEM_IN_STRUCT_P (reg) = in_struct;
1919 PUT_CODE (reg, MEM);
1921 else if (reg_equiv_mem[i])
1922 XEXP (reg_equiv_mem[i], 0) = addr;
1926 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1927 /* Make a pass over all the insns and remove death notes for things that
1928 are no longer registers or no longer die in the insn (e.g., an input
1929 and output pseudo being tied). */
1931 for (insn = first; insn; insn = NEXT_INSN (insn))
1932 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1936 for (note = REG_NOTES (insn); note; note = next)
1938 next = XEXP (note, 1);
1939 if (REG_NOTE_KIND (note) == REG_DEAD
1940 && (GET_CODE (XEXP (note, 0)) != REG
1941 || reg_set_p (XEXP (note, 0), PATTERN (insn))))
1942 remove_note (insn, note);
1947 /* Indicate that we no longer have known memory locations or constants. */
1948 reg_equiv_constant = 0;
1949 reg_equiv_memory_loc = 0;
1954 /* Nonzero if, after spilling reg REGNO for non-groups,
1955 it will still be possible to find a group if we still need one. */
1958 possible_group_p (regno, max_groups)
1963 int class = (int) NO_REGS;
1965 for (i = 0; i < (int) N_REG_CLASSES; i++)
1966 if (max_groups[i] > 0)
1972 if (class == (int) NO_REGS)
1975 /* Consider each pair of consecutive registers. */
1976 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++)
1978 /* Ignore pairs that include reg REGNO. */
1979 if (i == regno || i + 1 == regno)
1982 /* Ignore pairs that are outside the class that needs the group.
1983 ??? Here we fail to handle the case where two different classes
1984 independently need groups. But this never happens with our
1985 current machine descriptions. */
1986 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i)
1987 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1)))
1990 /* A pair of consecutive regs we can still spill does the trick. */
1991 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0
1992 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
1993 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1))
1996 /* A pair of one already spilled and one we can spill does it
1997 provided the one already spilled is not otherwise reserved. */
1998 if (spill_reg_order[i] < 0
1999 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)
2000 && spill_reg_order[i + 1] >= 0
2001 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1)
2002 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1))
2004 if (spill_reg_order[i + 1] < 0
2005 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)
2006 && spill_reg_order[i] >= 0
2007 && ! TEST_HARD_REG_BIT (counted_for_groups, i)
2008 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i))
2015 /* Count any groups that can be formed from the registers recently spilled.
2016 This is done class by class, in order of ascending class number. */
2019 count_possible_groups (group_size, group_mode, max_groups)
2021 enum machine_mode *group_mode;
2025 /* Now find all consecutive groups of spilled registers
2026 and mark each group off against the need for such groups.
2027 But don't count them against ordinary need, yet. */
2029 for (i = 0; i < N_REG_CLASSES; i++)
2030 if (group_size[i] > 1)
2035 CLEAR_HARD_REG_SET (new);
2037 /* Make a mask of all the regs that are spill regs in class I. */
2038 for (j = 0; j < n_spills; j++)
2039 if (TEST_HARD_REG_BIT (reg_class_contents[i], spill_regs[j])
2040 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[j])
2041 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
2043 SET_HARD_REG_BIT (new, spill_regs[j]);
2045 /* Find each consecutive group of them. */
2046 for (j = 0; j < FIRST_PSEUDO_REGISTER && max_groups[i] > 0; j++)
2047 if (TEST_HARD_REG_BIT (new, j)
2048 && j + group_size[i] <= FIRST_PSEUDO_REGISTER
2049 /* Next line in case group-mode for this class
2050 demands an even-odd pair. */
2051 && HARD_REGNO_MODE_OK (j, group_mode[i]))
2054 for (k = 1; k < group_size[i]; k++)
2055 if (! TEST_HARD_REG_BIT (new, j + k))
2057 if (k == group_size[i])
2059 /* We found a group. Mark it off against this class's
2060 need for groups, and against each superclass too. */
2061 register enum reg_class *p;
2063 p = reg_class_superclasses[i];
2064 while (*p != LIM_REG_CLASSES)
2065 max_groups[(int) *p++]--;
2066 /* Don't count these registers again. */
2067 for (k = 0; k < group_size[i]; k++)
2068 SET_HARD_REG_BIT (counted_for_groups, j + k);
2070 /* Skip to the last reg in this group. When j is incremented
2071 above, it will then point to the first reg of the next
2079 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2080 another mode that needs to be reloaded for the same register class CLASS.
2081 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2082 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2084 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2085 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2086 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2087 causes unnecessary failures on machines requiring alignment of register
2088 groups when the two modes are different sizes, because the larger mode has
2089 more strict alignment rules than the smaller mode. */
2092 modes_equiv_for_class_p (allocate_mode, other_mode, class)
2093 enum machine_mode allocate_mode, other_mode;
2094 enum reg_class class;
2097 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2099 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)
2100 && HARD_REGNO_MODE_OK (regno, allocate_mode)
2101 && ! HARD_REGNO_MODE_OK (regno, other_mode))
2107 /* Handle the failure to find a register to spill.
2108 INSN should be one of the insns which needed this particular spill reg. */
2111 spill_failure (insn)
2114 if (asm_noperands (PATTERN (insn)) >= 0)
2115 error_for_asm (insn, "`asm' needs too many reloads");
2120 /* Add a new register to the tables of available spill-registers
2121 (as well as spilling all pseudos allocated to the register).
2122 I is the index of this register in potential_reload_regs.
2123 CLASS is the regclass whose need is being satisfied.
2124 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2125 so that this register can count off against them.
2126 MAX_NONGROUPS is 0 if this register is part of a group.
2127 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2130 new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile)
2138 register enum reg_class *p;
2140 int regno = potential_reload_regs[i];
2142 if (i >= FIRST_PSEUDO_REGISTER)
2143 abort (); /* Caller failed to find any register. */
2145 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno))
2146 fatal ("fixed or forbidden register was spilled.\n\
2147 This may be due to a compiler bug or to impossible asm statements.");
2149 /* Make reg REGNO an additional reload reg. */
2151 potential_reload_regs[i] = -1;
2152 spill_regs[n_spills] = regno;
2153 spill_reg_order[regno] = n_spills;
2155 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]);
2157 /* Clear off the needs we just satisfied. */
2160 p = reg_class_superclasses[class];
2161 while (*p != LIM_REG_CLASSES)
2162 max_needs[(int) *p++]--;
2164 if (max_nongroups && max_nongroups[class] > 0)
2166 SET_HARD_REG_BIT (counted_for_nongroups, regno);
2167 max_nongroups[class]--;
2168 p = reg_class_superclasses[class];
2169 while (*p != LIM_REG_CLASSES)
2170 max_nongroups[(int) *p++]--;
2173 /* Spill every pseudo reg that was allocated to this reg
2174 or to something that overlaps this reg. */
2176 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0);
2178 /* If there are some registers still to eliminate and this register
2179 wasn't ever used before, additional stack space may have to be
2180 allocated to store this register. Thus, we may have changed the offset
2181 between the stack and frame pointers, so mark that something has changed.
2182 (If new pseudos were spilled, thus requiring more space, VAL would have
2183 been set non-zero by the call to spill_hard_reg above since additional
2184 reloads may be needed in that case.
2186 One might think that we need only set VAL to 1 if this is a call-used
2187 register. However, the set of registers that must be saved by the
2188 prologue is not identical to the call-used set. For example, the
2189 register used by the call insn for the return PC is a call-used register,
2190 but must be saved by the prologue. */
2191 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]])
2194 regs_ever_live[spill_regs[n_spills]] = 1;
2200 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2201 data that is dead in INSN. */
2204 delete_dead_insn (insn)
2207 rtx prev = prev_real_insn (insn);
2210 /* If the previous insn sets a register that dies in our insn, delete it
2212 if (prev && GET_CODE (PATTERN (prev)) == SET
2213 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
2214 && reg_mentioned_p (prev_dest, PATTERN (insn))
2215 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)))
2216 delete_dead_insn (prev);
2218 PUT_CODE (insn, NOTE);
2219 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2220 NOTE_SOURCE_FILE (insn) = 0;
2223 /* Modify the home of pseudo-reg I.
2224 The new home is present in reg_renumber[I].
2226 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2227 or it may be -1, meaning there is none or it is not relevant.
2228 This is used so that all pseudos spilled from a given hard reg
2229 can share one stack slot. */
2232 alter_reg (i, from_reg)
2236 /* When outputting an inline function, this can happen
2237 for a reg that isn't actually used. */
2238 if (regno_reg_rtx[i] == 0)
2241 /* If the reg got changed to a MEM at rtl-generation time,
2243 if (GET_CODE (regno_reg_rtx[i]) != REG)
2246 /* Modify the reg-rtx to contain the new hard reg
2247 number or else to contain its pseudo reg number. */
2248 REGNO (regno_reg_rtx[i])
2249 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
2251 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2252 allocate a stack slot for it. */
2254 if (reg_renumber[i] < 0
2255 && reg_n_refs[i] > 0
2256 && reg_equiv_constant[i] == 0
2257 && reg_equiv_memory_loc[i] == 0)
2260 int inherent_size = PSEUDO_REGNO_BYTES (i);
2261 int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2264 /* Each pseudo reg has an inherent size which comes from its own mode,
2265 and a total size which provides room for paradoxical subregs
2266 which refer to the pseudo reg in wider modes.
2268 We can use a slot already allocated if it provides both
2269 enough inherent space and enough total space.
2270 Otherwise, we allocate a new slot, making sure that it has no less
2271 inherent space, and no less total space, then the previous slot. */
2274 /* No known place to spill from => no slot to reuse. */
2275 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, -1);
2276 #if BYTES_BIG_ENDIAN
2277 /* Cancel the big-endian correction done in assign_stack_local.
2278 Get the address of the beginning of the slot.
2279 This is so we can do a big-endian correction unconditionally
2281 adjust = inherent_size - total_size;
2284 /* Reuse a stack slot if possible. */
2285 else if (spill_stack_slot[from_reg] != 0
2286 && spill_stack_slot_width[from_reg] >= total_size
2287 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2289 x = spill_stack_slot[from_reg];
2290 /* Allocate a bigger slot. */
2293 /* Compute maximum size needed, both for inherent size
2294 and for total size. */
2295 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2296 if (spill_stack_slot[from_reg])
2298 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2300 mode = GET_MODE (spill_stack_slot[from_reg]);
2301 if (spill_stack_slot_width[from_reg] > total_size)
2302 total_size = spill_stack_slot_width[from_reg];
2304 /* Make a slot with that size. */
2305 x = assign_stack_local (mode, total_size, -1);
2306 #if BYTES_BIG_ENDIAN
2307 /* Cancel the big-endian correction done in assign_stack_local.
2308 Get the address of the beginning of the slot.
2309 This is so we can do a big-endian correction unconditionally
2311 adjust = GET_MODE_SIZE (mode) - total_size;
2313 spill_stack_slot[from_reg] = x;
2314 spill_stack_slot_width[from_reg] = total_size;
2317 #if BYTES_BIG_ENDIAN
2318 /* On a big endian machine, the "address" of the slot
2319 is the address of the low part that fits its inherent mode. */
2320 if (inherent_size < total_size)
2321 adjust += (total_size - inherent_size);
2322 #endif /* BYTES_BIG_ENDIAN */
2324 /* If we have any adjustment to make, or if the stack slot is the
2325 wrong mode, make a new stack slot. */
2326 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2328 x = gen_rtx (MEM, GET_MODE (regno_reg_rtx[i]),
2329 plus_constant (XEXP (x, 0), adjust));
2330 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2333 /* Save the stack slot for later. */
2334 reg_equiv_memory_loc[i] = x;
2338 /* Mark the slots in regs_ever_live for the hard regs
2339 used by pseudo-reg number REGNO. */
2342 mark_home_live (regno)
2345 register int i, lim;
2346 i = reg_renumber[regno];
2349 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2351 regs_ever_live[i++] = 1;
2354 /* This function handles the tracking of elimination offsets around branches.
2356 X is a piece of RTL being scanned.
2358 INSN is the insn that it came from, if any.
2360 INITIAL_P is non-zero if we are to set the offset to be the initial
2361 offset and zero if we are setting the offset of the label to be the
2365 set_label_offsets (x, insn, initial_p)
2370 enum rtx_code code = GET_CODE (x);
2373 struct elim_table *p;
2378 if (LABEL_REF_NONLOCAL_P (x))
2383 /* ... fall through ... */
2386 /* If we know nothing about this label, set the desired offsets. Note
2387 that this sets the offset at a label to be the offset before a label
2388 if we don't know anything about the label. This is not correct for
2389 the label after a BARRIER, but is the best guess we can make. If
2390 we guessed wrong, we will suppress an elimination that might have
2391 been possible had we been able to guess correctly. */
2393 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2395 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2396 offsets_at[CODE_LABEL_NUMBER (x)][i]
2397 = (initial_p ? reg_eliminate[i].initial_offset
2398 : reg_eliminate[i].offset);
2399 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2402 /* Otherwise, if this is the definition of a label and it is
2403 preceded by a BARRIER, set our offsets to the known offset of
2407 && (tem = prev_nonnote_insn (insn)) != 0
2408 && GET_CODE (tem) == BARRIER)
2410 num_not_at_initial_offset = 0;
2411 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2413 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
2414 = offsets_at[CODE_LABEL_NUMBER (x)][i];
2415 if (reg_eliminate[i].can_eliminate
2416 && (reg_eliminate[i].offset
2417 != reg_eliminate[i].initial_offset))
2418 num_not_at_initial_offset++;
2423 /* If neither of the above cases is true, compare each offset
2424 with those previously recorded and suppress any eliminations
2425 where the offsets disagree. */
2427 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2428 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2429 != (initial_p ? reg_eliminate[i].initial_offset
2430 : reg_eliminate[i].offset))
2431 reg_eliminate[i].can_eliminate = 0;
2436 set_label_offsets (PATTERN (insn), insn, initial_p);
2438 /* ... fall through ... */
2442 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2443 and hence must have all eliminations at their initial offsets. */
2444 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2445 if (REG_NOTE_KIND (tem) == REG_LABEL)
2446 set_label_offsets (XEXP (tem, 0), insn, 1);
2451 /* Each of the labels in the address vector must be at their initial
2452 offsets. We want the first first for ADDR_VEC and the second
2453 field for ADDR_DIFF_VEC. */
2455 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2456 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2461 /* We only care about setting PC. If the source is not RETURN,
2462 IF_THEN_ELSE, or a label, disable any eliminations not at
2463 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2464 isn't one of those possibilities. For branches to a label,
2465 call ourselves recursively.
2467 Note that this can disable elimination unnecessarily when we have
2468 a non-local goto since it will look like a non-constant jump to
2469 someplace in the current function. This isn't a significant
2470 problem since such jumps will normally be when all elimination
2471 pairs are back to their initial offsets. */
2473 if (SET_DEST (x) != pc_rtx)
2476 switch (GET_CODE (SET_SRC (x)))
2483 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2487 tem = XEXP (SET_SRC (x), 1);
2488 if (GET_CODE (tem) == LABEL_REF)
2489 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2490 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2493 tem = XEXP (SET_SRC (x), 2);
2494 if (GET_CODE (tem) == LABEL_REF)
2495 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2496 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2501 /* If we reach here, all eliminations must be at their initial
2502 offset because we are doing a jump to a variable address. */
2503 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2504 if (p->offset != p->initial_offset)
2505 p->can_eliminate = 0;
2509 /* Used for communication between the next two function to properly share
2510 the vector for an ASM_OPERANDS. */
2512 static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
2514 /* Scan X and replace any eliminable registers (such as fp) with a
2515 replacement (such as sp), plus an offset.
2517 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2518 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2519 MEM, we are allowed to replace a sum of a register and the constant zero
2520 with the register, which we cannot do outside a MEM. In addition, we need
2521 to record the fact that a register is referenced outside a MEM.
2523 If INSN is nonzero, it is the insn containing X. If we replace a REG
2524 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2525 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2526 that the REG is being modified.
2528 If we see a modification to a register we know about, take the
2529 appropriate action (see case SET, below).
2531 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2532 replacements done assuming all offsets are at their initial values. If
2533 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2534 encounter, return the actual location so that find_reloads will do
2535 the proper thing. */
2538 eliminate_regs (x, mem_mode, insn)
2540 enum machine_mode mem_mode;
2543 enum rtx_code code = GET_CODE (x);
2544 struct elim_table *ep;
2569 /* First handle the case where we encounter a bare register that
2570 is eliminable. Replace it with a PLUS. */
2571 if (regno < FIRST_PSEUDO_REGISTER)
2573 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2575 if (ep->from_rtx == x && ep->can_eliminate)
2578 ep->ref_outside_mem = 1;
2579 return plus_constant (ep->to_rtx, ep->previous_offset);
2583 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno]
2584 && (reg_equiv_address[regno] || num_not_at_initial_offset))
2586 /* In this case, find_reloads would attempt to either use an
2587 incorrect address (if something is not at its initial offset)
2588 or substitute an replaced address into an insn (which loses
2589 if the offset is changed by some later action). So we simply
2590 return the replaced stack slot (assuming it is changed by
2591 elimination) and ignore the fact that this is actually a
2592 reference to the pseudo. Ensure we make a copy of the
2593 address in case it is shared. */
2594 new = eliminate_regs (reg_equiv_memory_loc[regno],
2595 mem_mode, NULL_RTX);
2596 if (new != reg_equiv_memory_loc[regno])
2597 return copy_rtx (new);
2602 /* If this is the sum of an eliminable register and a constant, rework
2604 if (GET_CODE (XEXP (x, 0)) == REG
2605 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2606 && CONSTANT_P (XEXP (x, 1)))
2608 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2610 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2613 ep->ref_outside_mem = 1;
2615 /* The only time we want to replace a PLUS with a REG (this
2616 occurs when the constant operand of the PLUS is the negative
2617 of the offset) is when we are inside a MEM. We won't want
2618 to do so at other times because that would change the
2619 structure of the insn in a way that reload can't handle.
2620 We special-case the commonest situation in
2621 eliminate_regs_in_insn, so just replace a PLUS with a
2622 PLUS here, unless inside a MEM. */
2623 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2624 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2627 return gen_rtx (PLUS, Pmode, ep->to_rtx,
2628 plus_constant (XEXP (x, 1),
2629 ep->previous_offset));
2632 /* If the register is not eliminable, we are done since the other
2633 operand is a constant. */
2637 /* If this is part of an address, we want to bring any constant to the
2638 outermost PLUS. We will do this by doing register replacement in
2639 our operands and seeing if a constant shows up in one of them.
2641 We assume here this is part of an address (or a "load address" insn)
2642 since an eliminable register is not likely to appear in any other
2645 If we have (plus (eliminable) (reg)), we want to produce
2646 (plus (plus (replacement) (reg) (const))). If this was part of a
2647 normal add insn, (plus (replacement) (reg)) will be pushed as a
2648 reload. This is the desired action. */
2651 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2652 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2654 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2656 /* If one side is a PLUS and the other side is a pseudo that
2657 didn't get a hard register but has a reg_equiv_constant,
2658 we must replace the constant here since it may no longer
2659 be in the position of any operand. */
2660 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2661 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2662 && reg_renumber[REGNO (new1)] < 0
2663 && reg_equiv_constant != 0
2664 && reg_equiv_constant[REGNO (new1)] != 0)
2665 new1 = reg_equiv_constant[REGNO (new1)];
2666 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2667 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2668 && reg_renumber[REGNO (new0)] < 0
2669 && reg_equiv_constant[REGNO (new0)] != 0)
2670 new0 = reg_equiv_constant[REGNO (new0)];
2672 new = form_sum (new0, new1);
2674 /* As above, if we are not inside a MEM we do not want to
2675 turn a PLUS into something else. We might try to do so here
2676 for an addition of 0 if we aren't optimizing. */
2677 if (! mem_mode && GET_CODE (new) != PLUS)
2678 return gen_rtx (PLUS, GET_MODE (x), new, const0_rtx);
2686 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2689 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2690 if (new != XEXP (x, 0))
2691 x = gen_rtx (EXPR_LIST, REG_NOTE_KIND (x), new, XEXP (x, 1));
2694 /* ... fall through ... */
2697 /* Now do eliminations in the rest of the chain. If this was
2698 an EXPR_LIST, this might result in allocating more memory than is
2699 strictly needed, but it simplifies the code. */
2702 new = eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX);
2703 if (new != XEXP (x, 1))
2704 return gen_rtx (INSN_LIST, GET_MODE (x), XEXP (x, 0), new);
2712 case DIV: case UDIV:
2713 case MOD: case UMOD:
2714 case AND: case IOR: case XOR:
2715 case LSHIFT: case ASHIFT: case ROTATE:
2716 case ASHIFTRT: case LSHIFTRT: case ROTATERT:
2718 case GE: case GT: case GEU: case GTU:
2719 case LE: case LT: case LEU: case LTU:
2721 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2723 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, NULL_RTX) : 0;
2725 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2726 return gen_rtx (code, GET_MODE (x), new0, new1);
2734 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2735 if (ep->to_rtx == XEXP (x, 0))
2737 if (code == PRE_DEC || code == POST_DEC)
2738 ep->offset += GET_MODE_SIZE (mem_mode);
2740 ep->offset -= GET_MODE_SIZE (mem_mode);
2743 /* Fall through to generic unary operation case. */
2745 case STRICT_LOW_PART:
2747 case SIGN_EXTEND: case ZERO_EXTEND:
2748 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2749 case FLOAT: case FIX:
2750 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2754 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2755 if (new != XEXP (x, 0))
2756 return gen_rtx (code, GET_MODE (x), new);
2760 /* Similar to above processing, but preserve SUBREG_WORD.
2761 Convert (subreg (mem)) to (mem) if not paradoxical.
2762 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2763 pseudo didn't get a hard reg, we must replace this with the
2764 eliminated version of the memory location because push_reloads
2765 may do the replacement in certain circumstances. */
2766 if (GET_CODE (SUBREG_REG (x)) == REG
2767 && (GET_MODE_SIZE (GET_MODE (x))
2768 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2769 && reg_equiv_memory_loc != 0
2770 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2772 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
2773 mem_mode, NULL_RTX);
2775 /* If we didn't change anything, we must retain the pseudo. */
2776 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
2779 /* Otherwise, ensure NEW isn't shared in case we have to reload
2781 new = copy_rtx (new);
2784 new = eliminate_regs (SUBREG_REG (x), mem_mode, NULL_RTX);
2786 if (new != XEXP (x, 0))
2788 if (GET_CODE (new) == MEM
2789 && (GET_MODE_SIZE (GET_MODE (x))
2790 <= GET_MODE_SIZE (GET_MODE (new))))
2792 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2793 enum machine_mode mode = GET_MODE (x);
2795 #if BYTES_BIG_ENDIAN
2796 offset += (MIN (UNITS_PER_WORD,
2797 GET_MODE_SIZE (GET_MODE (new)))
2798 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2801 PUT_MODE (new, mode);
2802 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2806 return gen_rtx (SUBREG, GET_MODE (x), new, SUBREG_WORD (x));
2812 /* If clobbering a register that is the replacement register for an
2813 elimination we still think can be performed, note that it cannot
2814 be performed. Otherwise, we need not be concerned about it. */
2815 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2816 if (ep->to_rtx == XEXP (x, 0))
2817 ep->can_eliminate = 0;
2819 new = eliminate_regs (XEXP (x, 0), mem_mode, NULL_RTX);
2820 if (new != XEXP (x, 0))
2821 return gen_rtx (code, GET_MODE (x), new);
2827 /* Properly handle sharing input and constraint vectors. */
2828 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
2830 /* When we come to a new vector not seen before,
2831 scan all its elements; keep the old vector if none
2832 of them changes; otherwise, make a copy. */
2833 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
2834 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
2835 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2836 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
2837 mem_mode, NULL_RTX);
2839 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
2840 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
2843 if (i == ASM_OPERANDS_INPUT_LENGTH (x))
2844 new_asm_operands_vec = old_asm_operands_vec;
2846 new_asm_operands_vec
2847 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
2850 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2851 if (new_asm_operands_vec == old_asm_operands_vec)
2854 new = gen_rtx (ASM_OPERANDS, VOIDmode, ASM_OPERANDS_TEMPLATE (x),
2855 ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
2856 ASM_OPERANDS_OUTPUT_IDX (x), new_asm_operands_vec,
2857 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
2858 ASM_OPERANDS_SOURCE_FILE (x),
2859 ASM_OPERANDS_SOURCE_LINE (x));
2860 new->volatil = x->volatil;
2865 /* Check for setting a register that we know about. */
2866 if (GET_CODE (SET_DEST (x)) == REG)
2868 /* See if this is setting the replacement register for an
2871 If DEST is the frame pointer, we do nothing because we assume that
2872 all assignments to the frame pointer are for non-local gotos and
2873 are being done at a time when they are valid and do not disturb
2874 anything else. Some machines want to eliminate a fake argument
2875 pointer with either the frame or stack pointer. Assignments to
2876 the frame pointer must not prevent this elimination. */
2878 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2880 if (ep->to_rtx == SET_DEST (x)
2881 && SET_DEST (x) != frame_pointer_rtx)
2883 /* If it is being incremented, adjust the offset. Otherwise,
2884 this elimination can't be done. */
2885 rtx src = SET_SRC (x);
2887 if (GET_CODE (src) == PLUS
2888 && XEXP (src, 0) == SET_DEST (x)
2889 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2890 ep->offset -= INTVAL (XEXP (src, 1));
2892 ep->can_eliminate = 0;
2895 /* Now check to see we are assigning to a register that can be
2896 eliminated. If so, it must be as part of a PARALLEL, since we
2897 will not have been called if this is a single SET. So indicate
2898 that we can no longer eliminate this reg. */
2899 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2901 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
2902 ep->can_eliminate = 0;
2905 /* Now avoid the loop below in this common case. */
2907 rtx new0 = eliminate_regs (SET_DEST (x), 0, NULL_RTX);
2908 rtx new1 = eliminate_regs (SET_SRC (x), 0, NULL_RTX);
2910 /* If SET_DEST changed from a REG to a MEM and INSN is non-zero,
2911 write a CLOBBER insn. */
2912 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
2914 emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn);
2916 if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
2917 return gen_rtx (SET, VOIDmode, new0, new1);
2923 /* Our only special processing is to pass the mode of the MEM to our
2924 recursive call and copy the flags. While we are here, handle this
2925 case more efficiently. */
2926 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), NULL_RTX);
2927 if (new != XEXP (x, 0))
2929 new = gen_rtx (MEM, GET_MODE (x), new);
2930 new->volatil = x->volatil;
2931 new->unchanging = x->unchanging;
2932 new->in_struct = x->in_struct;
2939 /* Process each of our operands recursively. If any have changed, make a
2941 fmt = GET_RTX_FORMAT (code);
2942 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2946 new = eliminate_regs (XEXP (x, i), mem_mode, NULL_RTX);
2947 if (new != XEXP (x, i) && ! copied)
2949 rtx new_x = rtx_alloc (code);
2950 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2951 + (sizeof (new_x->fld[0])
2952 * GET_RTX_LENGTH (code))));
2958 else if (*fmt == 'E')
2961 for (j = 0; j < XVECLEN (x, i); j++)
2963 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2964 if (new != XVECEXP (x, i, j) && ! copied_vec)
2966 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2967 &XVECEXP (x, i, 0));
2970 rtx new_x = rtx_alloc (code);
2971 bcopy (x, new_x, (sizeof (*new_x) - sizeof (new_x->fld)
2972 + (sizeof (new_x->fld[0])
2973 * GET_RTX_LENGTH (code))));
2977 XVEC (x, i) = new_v;
2980 XVECEXP (x, i, j) = new;
2988 /* Scan INSN and eliminate all eliminable registers in it.
2990 If REPLACE is nonzero, do the replacement destructively. Also
2991 delete the insn as dead it if it is setting an eliminable register.
2993 If REPLACE is zero, do all our allocations in reload_obstack.
2995 If no eliminations were done and this insn doesn't require any elimination
2996 processing (these are not identical conditions: it might be updating sp,
2997 but not referencing fp; this needs to be seen during reload_as_needed so
2998 that the offset between fp and sp can be taken into consideration), zero
2999 is returned. Otherwise, 1 is returned. */
3002 eliminate_regs_in_insn (insn, replace)
3006 rtx old_body = PATTERN (insn);
3009 struct elim_table *ep;
3012 push_obstacks (&reload_obstack, &reload_obstack);
3014 if (GET_CODE (old_body) == SET && GET_CODE (SET_DEST (old_body)) == REG
3015 && REGNO (SET_DEST (old_body)) < FIRST_PSEUDO_REGISTER)
3017 /* Check for setting an eliminable register. */
3018 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3019 if (ep->from_rtx == SET_DEST (old_body) && ep->can_eliminate)
3021 /* In this case this insn isn't serving a useful purpose. We
3022 will delete it in reload_as_needed once we know that this
3023 elimination is, in fact, being done.
3025 If REPLACE isn't set, we can't delete this insn, but neededn't
3026 process it since it won't be used unless something changes. */
3028 delete_dead_insn (insn);
3033 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3034 in the insn is the negative of the offset in FROM. Substitute
3035 (set (reg) (reg to)) for the insn and change its code.
3037 We have to do this here, rather than in eliminate_regs, do that we can
3038 change the insn code. */
3040 if (GET_CODE (SET_SRC (old_body)) == PLUS
3041 && GET_CODE (XEXP (SET_SRC (old_body), 0)) == REG
3042 && GET_CODE (XEXP (SET_SRC (old_body), 1)) == CONST_INT)
3043 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3045 if (ep->from_rtx == XEXP (SET_SRC (old_body), 0)
3046 && ep->can_eliminate
3047 && ep->offset == - INTVAL (XEXP (SET_SRC (old_body), 1)))
3049 PATTERN (insn) = gen_rtx (SET, VOIDmode,
3050 SET_DEST (old_body), ep->to_rtx);
3051 INSN_CODE (insn) = -1;
3057 old_asm_operands_vec = 0;
3059 /* Replace the body of this insn with a substituted form. If we changed
3060 something, return non-zero. If this is the final call for this
3061 insn (REPLACE is non-zero), do the elimination in REG_NOTES as well.
3063 If we are replacing a body that was a (set X (plus Y Z)), try to
3064 re-recognize the insn. We do this in case we had a simple addition
3065 but now can do this as a load-address. This saves an insn in this
3068 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
3069 if (new_body != old_body)
3071 /* If we aren't replacing things permanently and we changed something,
3072 make another copy to ensure that all the RTL is new. Otherwise
3073 things can go wrong if find_reload swaps commutative operands
3074 and one is inside RTL that has been copied while the other is not. */
3076 /* Don't copy an asm_operands because (1) there's no need and (2)
3077 copy_rtx can't do it properly when there are multiple outputs. */
3078 if (! replace && asm_noperands (old_body) < 0)
3079 new_body = copy_rtx (new_body);
3081 /* If we had a move insn but now we don't, rerecognize it. */
3082 if ((GET_CODE (old_body) == SET && GET_CODE (SET_SRC (old_body)) == REG
3083 && (GET_CODE (new_body) != SET
3084 || GET_CODE (SET_SRC (new_body)) != REG))
3085 /* If this was an add insn before, rerecognize. */
3087 (GET_CODE (old_body) == SET
3088 && GET_CODE (SET_SRC (old_body)) == PLUS))
3090 if (! validate_change (insn, &PATTERN (insn), new_body, 0))
3091 /* If recognition fails, store the new body anyway.
3092 It's normal to have recognition failures here
3093 due to bizarre memory addresses; reloading will fix them. */
3094 PATTERN (insn) = new_body;
3097 PATTERN (insn) = new_body;
3099 if (replace && REG_NOTES (insn))
3100 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, NULL_RTX);
3104 /* Loop through all elimination pairs. See if any have changed and
3105 recalculate the number not at initial offset.
3107 Compute the maximum offset (minimum offset if the stack does not
3108 grow downward) for each elimination pair.
3110 We also detect a cases where register elimination cannot be done,
3111 namely, if a register would be both changed and referenced outside a MEM
3112 in the resulting insn since such an insn is often undefined and, even if
3113 not, we cannot know what meaning will be given to it. Note that it is
3114 valid to have a register used in an address in an insn that changes it
3115 (presumably with a pre- or post-increment or decrement).
3117 If anything changes, return nonzero. */
3119 num_not_at_initial_offset = 0;
3120 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3122 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3123 ep->can_eliminate = 0;
3125 ep->ref_outside_mem = 0;
3127 if (ep->previous_offset != ep->offset)
3130 ep->previous_offset = ep->offset;
3131 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3132 num_not_at_initial_offset++;
3134 #ifdef STACK_GROWS_DOWNWARD
3135 ep->max_offset = MAX (ep->max_offset, ep->offset);
3137 ep->max_offset = MIN (ep->max_offset, ep->offset);
3148 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3149 replacement we currently believe is valid, mark it as not eliminable if X
3150 modifies DEST in any way other than by adding a constant integer to it.
3152 If DEST is the frame pointer, we do nothing because we assume that
3153 all assignments to the frame pointer are nonlocal gotos and are being done
3154 at a time when they are valid and do not disturb anything else.
3155 Some machines want to eliminate a fake argument pointer with either the
3156 frame or stack pointer. Assignments to the frame pointer must not prevent
3159 Called via note_stores from reload before starting its passes to scan
3160 the insns of the function. */
3163 mark_not_eliminable (dest, x)
3169 /* A SUBREG of a hard register here is just changing its mode. We should
3170 not see a SUBREG of an eliminable hard register, but check just in
3172 if (GET_CODE (dest) == SUBREG)
3173 dest = SUBREG_REG (dest);
3175 if (dest == frame_pointer_rtx)
3178 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3179 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3180 && (GET_CODE (x) != SET
3181 || GET_CODE (SET_SRC (x)) != PLUS
3182 || XEXP (SET_SRC (x), 0) != dest
3183 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3185 reg_eliminate[i].can_eliminate_previous
3186 = reg_eliminate[i].can_eliminate = 0;
3191 /* Kick all pseudos out of hard register REGNO.
3192 If GLOBAL is nonzero, try to find someplace else to put them.
3193 If DUMPFILE is nonzero, log actions taken on that file.
3195 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3196 because we found we can't eliminate some register. In the case, no pseudos
3197 are allowed to be in the register, even if they are only in a block that
3198 doesn't require spill registers, unlike the case when we are spilling this
3199 hard reg to produce another spill register.
3201 Return nonzero if any pseudos needed to be kicked out. */
3204 spill_hard_reg (regno, global, dumpfile, cant_eliminate)
3210 int something_changed = 0;
3213 SET_HARD_REG_BIT (forbidden_regs, regno);
3215 /* Spill every pseudo reg that was allocated to this reg
3216 or to something that overlaps this reg. */
3218 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3219 if (reg_renumber[i] >= 0
3220 && reg_renumber[i] <= regno
3222 + HARD_REGNO_NREGS (reg_renumber[i],
3223 PSEUDO_REGNO_MODE (i))
3226 enum reg_class class = REGNO_REG_CLASS (regno);
3228 /* If this register belongs solely to a basic block which needed no
3229 spilling of any class that this register is contained in,
3230 leave it be, unless we are spilling this register because
3231 it was a hard register that can't be eliminated. */
3233 if (! cant_eliminate
3234 && basic_block_needs[0]
3235 && reg_basic_block[i] >= 0
3236 && basic_block_needs[(int) class][reg_basic_block[i]] == 0)
3240 for (p = reg_class_superclasses[(int) class];
3241 *p != LIM_REG_CLASSES; p++)
3242 if (basic_block_needs[(int) *p][reg_basic_block[i]] > 0)
3245 if (*p == LIM_REG_CLASSES)
3249 /* Mark it as no longer having a hard register home. */
3250 reg_renumber[i] = -1;
3251 /* We will need to scan everything again. */
3252 something_changed = 1;
3254 retry_global_alloc (i, forbidden_regs);
3256 alter_reg (i, regno);
3259 if (reg_renumber[i] == -1)
3260 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3262 fprintf (dumpfile, " Register %d now in %d.\n\n",
3263 i, reg_renumber[i]);
3267 return something_changed;
3270 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3273 scan_paradoxical_subregs (x)
3278 register enum rtx_code code = GET_CODE (x);
3295 if (GET_CODE (SUBREG_REG (x)) == REG
3296 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3297 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3298 = GET_MODE_SIZE (GET_MODE (x));
3302 fmt = GET_RTX_FORMAT (code);
3303 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3306 scan_paradoxical_subregs (XEXP (x, i));
3307 else if (fmt[i] == 'E')
3310 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3311 scan_paradoxical_subregs (XVECEXP (x, i, j));
3317 hard_reg_use_compare (p1, p2)
3318 struct hard_reg_n_uses *p1, *p2;
3320 int tem = p1->uses - p2->uses;
3321 if (tem != 0) return tem;
3322 /* If regs are equally good, sort by regno,
3323 so that the results of qsort leave nothing to chance. */
3324 return p1->regno - p2->regno;
3327 /* Choose the order to consider regs for use as reload registers
3328 based on how much trouble would be caused by spilling one.
3329 Store them in order of decreasing preference in potential_reload_regs. */
3332 order_regs_for_reload ()
3338 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER];
3340 CLEAR_HARD_REG_SET (bad_spill_regs);
3342 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3343 potential_reload_regs[i] = -1;
3345 /* Count number of uses of each hard reg by pseudo regs allocated to it
3346 and then order them by decreasing use. */
3348 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3350 hard_reg_n_uses[i].uses = 0;
3351 hard_reg_n_uses[i].regno = i;
3354 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3356 int regno = reg_renumber[i];
3359 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i));
3361 hard_reg_n_uses[regno++].uses += reg_n_refs[i];
3363 large += reg_n_refs[i];
3366 /* Now fixed registers (which cannot safely be used for reloading)
3367 get a very high use count so they will be considered least desirable.
3368 Registers used explicitly in the rtl code are almost as bad. */
3370 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3374 hard_reg_n_uses[i].uses += 2 * large + 2;
3375 SET_HARD_REG_BIT (bad_spill_regs, i);
3377 else if (regs_explicitly_used[i])
3379 hard_reg_n_uses[i].uses += large + 1;
3380 #ifndef SMALL_REGISTER_CLASSES
3381 /* ??? We are doing this here because of the potential that
3382 bad code may be generated if a register explicitly used in
3383 an insn was used as a spill register for that insn. But
3384 not using these are spill registers may lose on some machine.
3385 We'll have to see how this works out. */
3386 SET_HARD_REG_BIT (bad_spill_regs, i);
3390 hard_reg_n_uses[FRAME_POINTER_REGNUM].uses += 2 * large + 2;
3391 SET_HARD_REG_BIT (bad_spill_regs, FRAME_POINTER_REGNUM);
3393 #ifdef ELIMINABLE_REGS
3394 /* If registers other than the frame pointer are eliminable, mark them as
3396 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3398 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2;
3399 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from);
3403 /* Prefer registers not so far used, for use in temporary loading.
3404 Among them, if REG_ALLOC_ORDER is defined, use that order.
3405 Otherwise, prefer registers not preserved by calls. */
3407 #ifdef REG_ALLOC_ORDER
3408 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3410 int regno = reg_alloc_order[i];
3412 if (hard_reg_n_uses[regno].uses == 0)
3413 potential_reload_regs[o++] = regno;
3416 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3418 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i])
3419 potential_reload_regs[o++] = i;
3421 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3423 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i])
3424 potential_reload_regs[o++] = i;
3428 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER,
3429 sizeof hard_reg_n_uses[0], hard_reg_use_compare);
3431 /* Now add the regs that are already used,
3432 preferring those used less often. The fixed and otherwise forbidden
3433 registers will be at the end of this list. */
3435 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3436 if (hard_reg_n_uses[i].uses != 0)
3437 potential_reload_regs[o++] = hard_reg_n_uses[i].regno;
3440 /* Reload pseudo-registers into hard regs around each insn as needed.
3441 Additional register load insns are output before the insn that needs it
3442 and perhaps store insns after insns that modify the reloaded pseudo reg.
3444 reg_last_reload_reg and reg_reloaded_contents keep track of
3445 which registers are already available in reload registers.
3446 We update these for the reloads that we perform,
3447 as the insns are scanned. */
3450 reload_as_needed (first, live_known)
3460 bzero (spill_reg_rtx, sizeof spill_reg_rtx);
3461 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
3462 bzero (reg_last_reload_reg, max_regno * sizeof (rtx));
3463 reg_has_output_reload = (char *) alloca (max_regno);
3464 for (i = 0; i < n_spills; i++)
3466 reg_reloaded_contents[i] = -1;
3467 reg_reloaded_insn[i] = 0;
3470 /* Reset all offsets on eliminable registers to their initial values. */
3471 #ifdef ELIMINABLE_REGS
3472 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3474 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to,
3475 reg_eliminate[i].initial_offset);
3476 reg_eliminate[i].previous_offset
3477 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset;
3480 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset);
3481 reg_eliminate[0].previous_offset
3482 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset;
3485 num_not_at_initial_offset = 0;
3487 for (insn = first; insn;)
3489 register rtx next = NEXT_INSN (insn);
3491 /* Notice when we move to a new basic block. */
3492 if (live_known && this_block + 1 < n_basic_blocks
3493 && insn == basic_block_head[this_block+1])
3496 /* If we pass a label, copy the offsets from the label information
3497 into the current offsets of each elimination. */
3498 if (GET_CODE (insn) == CODE_LABEL)
3500 num_not_at_initial_offset = 0;
3501 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3503 reg_eliminate[i].offset = reg_eliminate[i].previous_offset
3504 = offsets_at[CODE_LABEL_NUMBER (insn)][i];
3505 if (reg_eliminate[i].can_eliminate
3506 && (reg_eliminate[i].offset
3507 != reg_eliminate[i].initial_offset))
3508 num_not_at_initial_offset++;
3512 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3514 rtx avoid_return_reg = 0;
3516 #ifdef SMALL_REGISTER_CLASSES
3517 /* Set avoid_return_reg if this is an insn
3518 that might use the value of a function call. */
3519 if (GET_CODE (insn) == CALL_INSN)
3521 if (GET_CODE (PATTERN (insn)) == SET)
3522 after_call = SET_DEST (PATTERN (insn));
3523 else if (GET_CODE (PATTERN (insn)) == PARALLEL
3524 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
3525 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0));
3529 else if (after_call != 0
3530 && !(GET_CODE (PATTERN (insn)) == SET
3531 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx))
3533 if (reg_mentioned_p (after_call, PATTERN (insn)))
3534 avoid_return_reg = after_call;
3537 #endif /* SMALL_REGISTER_CLASSES */
3539 /* If this is a USE and CLOBBER of a MEM, ensure that any
3540 references to eliminable registers have been removed. */
3542 if ((GET_CODE (PATTERN (insn)) == USE
3543 || GET_CODE (PATTERN (insn)) == CLOBBER)
3544 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3545 XEXP (XEXP (PATTERN (insn), 0), 0)
3546 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3547 GET_MODE (XEXP (PATTERN (insn), 0)), NULL_RTX);
3549 /* If we need to do register elimination processing, do so.
3550 This might delete the insn, in which case we are done. */
3551 if (num_eliminable && GET_MODE (insn) == QImode)
3553 eliminate_regs_in_insn (insn, 1);
3554 if (GET_CODE (insn) == NOTE)
3561 if (GET_MODE (insn) == VOIDmode)
3563 /* First find the pseudo regs that must be reloaded for this insn.
3564 This info is returned in the tables reload_... (see reload.h).
3565 Also modify the body of INSN by substituting RELOAD
3566 rtx's for those pseudo regs. */
3569 bzero (reg_has_output_reload, max_regno);
3570 CLEAR_HARD_REG_SET (reg_is_output_reload);
3572 find_reloads (insn, 1, spill_indirect_levels, live_known,
3578 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn);
3582 /* If this block has not had spilling done for a
3583 particular clas and we have any non-optionals that need a
3584 spill reg in that class, abort. */
3586 for (class = 0; class < N_REG_CLASSES; class++)
3587 if (basic_block_needs[class] != 0
3588 && basic_block_needs[class][this_block] == 0)
3589 for (i = 0; i < n_reloads; i++)
3590 if (class == (int) reload_reg_class[i]
3591 && reload_reg_rtx[i] == 0
3592 && ! reload_optional[i]
3593 && (reload_in[i] != 0 || reload_out[i] != 0
3594 || reload_secondary_p[i] != 0))
3597 /* Now compute which reload regs to reload them into. Perhaps
3598 reusing reload regs from previous insns, or else output
3599 load insns to reload them. Maybe output store insns too.
3600 Record the choices of reload reg in reload_reg_rtx. */
3601 choose_reload_regs (insn, avoid_return_reg);
3603 #ifdef SMALL_REGISTER_CLASSES
3604 /* Merge any reloads that we didn't combine for fear of
3605 increasing the number of spill registers needed but now
3606 discover can be safely merged. */
3607 merge_assigned_reloads (insn);
3610 /* Generate the insns to reload operands into or out of
3611 their reload regs. */
3612 emit_reload_insns (insn);
3614 /* Substitute the chosen reload regs from reload_reg_rtx
3615 into the insn's body (or perhaps into the bodies of other
3616 load and store insn that we just made for reloading
3617 and that we moved the structure into). */
3620 /* If this was an ASM, make sure that all the reload insns
3621 we have generated are valid. If not, give an error
3624 if (asm_noperands (PATTERN (insn)) >= 0)
3625 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3626 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i'
3627 && (recog_memoized (p) < 0
3628 || (insn_extract (p),
3629 ! constrain_operands (INSN_CODE (p), 1))))
3631 error_for_asm (insn,
3632 "`asm' operand requires impossible reload");
3634 NOTE_SOURCE_FILE (p) = 0;
3635 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3638 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3639 is no longer validly lying around to save a future reload.
3640 Note that this does not detect pseudos that were reloaded
3641 for this insn in order to be stored in
3642 (obeying register constraints). That is correct; such reload
3643 registers ARE still valid. */
3644 note_stores (PATTERN (insn), forget_old_reloads_1);
3646 /* There may have been CLOBBER insns placed after INSN. So scan
3647 between INSN and NEXT and use them to forget old reloads. */
3648 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x))
3649 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3650 note_stores (PATTERN (x), forget_old_reloads_1);
3653 /* Likewise for regs altered by auto-increment in this insn.
3654 But note that the reg-notes are not changed by reloading:
3655 they still contain the pseudo-regs, not the spill regs. */
3656 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3657 if (REG_NOTE_KIND (x) == REG_INC)
3659 /* See if this pseudo reg was reloaded in this insn.
3660 If so, its last-reload info is still valid
3661 because it is based on this insn's reload. */
3662 for (i = 0; i < n_reloads; i++)
3663 if (reload_out[i] == XEXP (x, 0))
3667 forget_old_reloads_1 (XEXP (x, 0));
3671 /* A reload reg's contents are unknown after a label. */
3672 if (GET_CODE (insn) == CODE_LABEL)
3673 for (i = 0; i < n_spills; i++)
3675 reg_reloaded_contents[i] = -1;
3676 reg_reloaded_insn[i] = 0;
3679 /* Don't assume a reload reg is still good after a call insn
3680 if it is a call-used reg. */
3681 else if (GET_CODE (insn) == CALL_INSN)
3682 for (i = 0; i < n_spills; i++)
3683 if (call_used_regs[spill_regs[i]])
3685 reg_reloaded_contents[i] = -1;
3686 reg_reloaded_insn[i] = 0;
3689 /* In case registers overlap, allow certain insns to invalidate
3690 particular hard registers. */
3692 #ifdef INSN_CLOBBERS_REGNO_P
3693 for (i = 0 ; i < n_spills ; i++)
3694 if (INSN_CLOBBERS_REGNO_P (insn, spill_regs[i]))
3696 reg_reloaded_contents[i] = -1;
3697 reg_reloaded_insn[i] = 0;
3709 /* Discard all record of any value reloaded from X,
3710 or reloaded in X from someplace else;
3711 unless X is an output reload reg of the current insn.
3713 X may be a hard reg (the reload reg)
3714 or it may be a pseudo reg that was reloaded from. */
3717 forget_old_reloads_1 (x)
3724 /* note_stores does give us subregs of hard regs. */
3725 while (GET_CODE (x) == SUBREG)
3727 offset += SUBREG_WORD (x);
3731 if (GET_CODE (x) != REG)
3734 regno = REGNO (x) + offset;
3736 if (regno >= FIRST_PSEUDO_REGISTER)
3741 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
3742 /* Storing into a spilled-reg invalidates its contents.
3743 This can happen if a block-local pseudo is allocated to that reg
3744 and it wasn't spilled because this block's total need is 0.
3745 Then some insn might have an optional reload and use this reg. */
3746 for (i = 0; i < nr; i++)
3747 if (spill_reg_order[regno + i] >= 0
3748 /* But don't do this if the reg actually serves as an output
3749 reload reg in the current instruction. */
3751 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)))
3753 reg_reloaded_contents[spill_reg_order[regno + i]] = -1;
3754 reg_reloaded_insn[spill_reg_order[regno + i]] = 0;
3758 /* Since value of X has changed,
3759 forget any value previously copied from it. */
3762 /* But don't forget a copy if this is the output reload
3763 that establishes the copy's validity. */
3764 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
3765 reg_last_reload_reg[regno + nr] = 0;
3768 /* For each reload, the mode of the reload register. */
3769 static enum machine_mode reload_mode[MAX_RELOADS];
3771 /* For each reload, the largest number of registers it will require. */
3772 static int reload_nregs[MAX_RELOADS];
3774 /* Comparison function for qsort to decide which of two reloads
3775 should be handled first. *P1 and *P2 are the reload numbers. */
3778 reload_reg_class_lower (p1, p2)
3781 register int r1 = *p1, r2 = *p2;
3784 /* Consider required reloads before optional ones. */
3785 t = reload_optional[r1] - reload_optional[r2];
3789 /* Count all solitary classes before non-solitary ones. */
3790 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
3791 - (reg_class_size[(int) reload_reg_class[r1]] == 1));
3795 /* Aside from solitaires, consider all multi-reg groups first. */
3796 t = reload_nregs[r2] - reload_nregs[r1];
3800 /* Consider reloads in order of increasing reg-class number. */
3801 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
3805 /* If reloads are equally urgent, sort by reload number,
3806 so that the results of qsort leave nothing to chance. */
3810 /* The following HARD_REG_SETs indicate when each hard register is
3811 used for a reload of various parts of the current insn. */
3813 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3814 static HARD_REG_SET reload_reg_used;
3815 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
3816 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
3817 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
3818 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
3819 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
3820 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
3821 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
3822 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
3823 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3824 static HARD_REG_SET reload_reg_used_in_op_addr;
3825 /* If reg is in use for a RELOAD_FOR_INSN reload. */
3826 static HARD_REG_SET reload_reg_used_in_insn;
3827 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
3828 static HARD_REG_SET reload_reg_used_in_other_addr;
3830 /* If reg is in use as a reload reg for any sort of reload. */
3831 static HARD_REG_SET reload_reg_used_at_all;
3833 /* If reg is use as an inherited reload. We just mark the first register
3835 static HARD_REG_SET reload_reg_used_for_inherit;
3837 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
3838 TYPE. MODE is used to indicate how many consecutive regs are
3842 mark_reload_reg_in_use (regno, opnum, type, mode)
3845 enum reload_type type;
3846 enum machine_mode mode;
3848 int nregs = HARD_REGNO_NREGS (regno, mode);
3851 for (i = regno; i < nregs + regno; i++)
3856 SET_HARD_REG_BIT (reload_reg_used, i);
3859 case RELOAD_FOR_INPUT_ADDRESS:
3860 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
3863 case RELOAD_FOR_OUTPUT_ADDRESS:
3864 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
3867 case RELOAD_FOR_OPERAND_ADDRESS:
3868 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3871 case RELOAD_FOR_OTHER_ADDRESS:
3872 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
3875 case RELOAD_FOR_INPUT:
3876 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
3879 case RELOAD_FOR_OUTPUT:
3880 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
3883 case RELOAD_FOR_INSN:
3884 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
3888 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
3892 /* Similarly, but show REGNO is no longer in use for a reload. */
3895 clear_reload_reg_in_use (regno, opnum, type, mode)
3898 enum reload_type type;
3899 enum machine_mode mode;
3901 int nregs = HARD_REGNO_NREGS (regno, mode);
3904 for (i = regno; i < nregs + regno; i++)
3909 CLEAR_HARD_REG_BIT (reload_reg_used, i);
3912 case RELOAD_FOR_INPUT_ADDRESS:
3913 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
3916 case RELOAD_FOR_OUTPUT_ADDRESS:
3917 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
3920 case RELOAD_FOR_OPERAND_ADDRESS:
3921 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
3924 case RELOAD_FOR_OTHER_ADDRESS:
3925 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
3928 case RELOAD_FOR_INPUT:
3929 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
3932 case RELOAD_FOR_OUTPUT:
3933 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
3936 case RELOAD_FOR_INSN:
3937 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i);
3943 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
3944 specified by OPNUM and TYPE. */
3947 reload_reg_free_p (regno, opnum, type)
3950 enum reload_type type;
3954 /* In use for a RELOAD_OTHER means it's not available for anything except
3955 RELOAD_FOR_OTHER_ADDRESS. Recall that RELOAD_FOR_OTHER_ADDRESS is known
3956 to be used only for inputs. */
3958 if (type != RELOAD_FOR_OTHER_ADDRESS
3959 && TEST_HARD_REG_BIT (reload_reg_used, regno))
3965 /* In use for anything means not available for a RELOAD_OTHER. */
3966 return ! TEST_HARD_REG_BIT (reload_reg_used_at_all, regno);
3968 /* The other kinds of use can sometimes share a register. */
3969 case RELOAD_FOR_INPUT:
3970 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
3971 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
3974 /* If it is used for some other input, can't use it. */
3975 for (i = 0; i < reload_n_operands; i++)
3976 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
3979 /* If it is used in a later operand's address, can't use it. */
3980 for (i = opnum + 1; i < reload_n_operands; i++)
3981 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
3986 case RELOAD_FOR_INPUT_ADDRESS:
3987 /* Can't use a register if it is used for an input address for this
3988 operand or used as an input in an earlier one. */
3989 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
3992 for (i = 0; i < opnum; i++)
3993 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
3998 case RELOAD_FOR_OUTPUT_ADDRESS:
3999 /* Can't use a register if it is used for an output address for this
4000 operand or used as an output in this or a later operand. */
4001 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4004 for (i = opnum; i < reload_n_operands; i++)
4005 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4010 case RELOAD_FOR_OPERAND_ADDRESS:
4011 for (i = 0; i < reload_n_operands; i++)
4012 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4015 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4016 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4018 case RELOAD_FOR_OUTPUT:
4019 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4020 outputs, or an operand address for this or an earlier output. */
4021 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4024 for (i = 0; i < reload_n_operands; i++)
4025 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4028 for (i = 0; i <= opnum; i++)
4029 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4034 case RELOAD_FOR_INSN:
4035 for (i = 0; i < reload_n_operands; i++)
4036 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4037 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4040 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4041 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4043 case RELOAD_FOR_OTHER_ADDRESS:
4044 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4049 /* Return 1 if the value in reload reg REGNO, as used by a reload
4050 needed for the part of the insn specified by OPNUM and TYPE,
4051 is not in use for a reload in any prior part of the insn.
4053 We can assume that the reload reg was already tested for availability
4054 at the time it is needed, and we should not check this again,
4055 in case the reg has already been marked in use. */
4058 reload_reg_free_before_p (regno, opnum, type)
4061 enum reload_type type;
4067 case RELOAD_FOR_OTHER_ADDRESS:
4068 /* These always come first. */
4072 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4074 /* If this use is for part of the insn,
4075 check the reg is not in use for any prior part. It is tempting
4076 to try to do this by falling through from objecs that occur
4077 later in the insn to ones that occur earlier, but that will not
4078 correctly take into account the fact that here we MUST ignore
4079 things that would prevent the register from being allocated in
4080 the first place, since we know that it was allocated. */
4082 case RELOAD_FOR_OUTPUT_ADDRESS:
4083 /* Earlier reloads are for earlier outputs or their addresses,
4084 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4085 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4087 for (i = 0; i < opnum; i++)
4088 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4089 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4092 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4095 for (i = 0; i < reload_n_operands; i++)
4096 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4097 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4100 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4101 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4102 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4104 case RELOAD_FOR_OUTPUT:
4105 /* This can't be used in the output address for this operand and
4106 anything that can't be used for it, except that we've already
4107 tested for RELOAD_FOR_INSN objects. */
4109 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4112 for (i = 0; i < opnum; i++)
4113 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4114 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4117 for (i = 0; i < reload_n_operands; i++)
4118 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4119 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4120 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4123 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4125 case RELOAD_FOR_OPERAND_ADDRESS:
4126 case RELOAD_FOR_INSN:
4127 /* These can't conflict with inputs, or each other, so all we have to
4128 test is input addresses and the addresses of OTHER items. */
4130 for (i = 0; i < reload_n_operands; i++)
4131 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4134 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4136 case RELOAD_FOR_INPUT:
4137 /* The only things earlier are the address for this and
4138 earlier inputs, other inputs (which we know we don't conflict
4139 with), and addresses of RELOAD_OTHER objects. */
4141 for (i = 0; i <= opnum; i++)
4142 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4145 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4147 case RELOAD_FOR_INPUT_ADDRESS:
4148 /* Similarly, all we have to check is for use in earlier inputs'
4150 for (i = 0; i < opnum; i++)
4151 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4154 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4159 /* Return 1 if the value in reload reg REGNO, as used by a reload
4160 needed for the part of the insn specified by OPNUM and TYPE,
4161 is still available in REGNO at the end of the insn.
4163 We can assume that the reload reg was already tested for availability
4164 at the time it is needed, and we should not check this again,
4165 in case the reg has already been marked in use. */
4168 reload_reg_reaches_end_p (regno, opnum, type)
4171 enum reload_type type;
4178 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4179 its value must reach the end. */
4182 /* If this use is for part of the insn,
4183 its value reaches if no subsequent part uses the same register.
4184 Just like the above function, don't try to do this with lots
4187 case RELOAD_FOR_OTHER_ADDRESS:
4188 /* Here we check for everything else, since these don't conflict
4189 with anything else and everything comes later. */
4191 for (i = 0; i < reload_n_operands; i++)
4192 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4193 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4194 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4195 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4198 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4199 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4200 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4202 case RELOAD_FOR_INPUT_ADDRESS:
4203 /* Similar, except that we check only for this and subsequent inputs
4204 and the address of only subsequent inputs and we do not need
4205 to check for RELOAD_OTHER objects since they are known not to
4208 for (i = opnum; i < reload_n_operands; i++)
4209 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4212 for (i = opnum + 1; i < reload_n_operands; i++)
4213 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno))
4216 for (i = 0; i < reload_n_operands; i++)
4217 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4218 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4221 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4222 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4224 case RELOAD_FOR_INPUT:
4225 /* Similar to input address, except we start at the next operand for
4226 both input and input address and we do not check for
4227 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4230 for (i = opnum + 1; i < reload_n_operands; i++)
4231 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4232 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4235 /* ... fall through ... */
4237 case RELOAD_FOR_OPERAND_ADDRESS:
4238 /* Check outputs and their addresses. */
4240 for (i = 0; i < reload_n_operands; i++)
4241 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4242 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4247 case RELOAD_FOR_INSN:
4248 /* These conflict with other outputs with with RELOAD_OTHER. So
4249 we need only check for output addresses. */
4253 /* ... fall through ... */
4255 case RELOAD_FOR_OUTPUT:
4256 case RELOAD_FOR_OUTPUT_ADDRESS:
4257 /* We already know these can't conflict with a later output. So the
4258 only thing to check are later output addresses. */
4259 for (i = opnum + 1; i < reload_n_operands; i++)
4260 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno))
4269 /* Vector of reload-numbers showing the order in which the reloads should
4271 short reload_order[MAX_RELOADS];
4273 /* Indexed by reload number, 1 if incoming value
4274 inherited from previous insns. */
4275 char reload_inherited[MAX_RELOADS];
4277 /* For an inherited reload, this is the insn the reload was inherited from,
4278 if we know it. Otherwise, this is 0. */
4279 rtx reload_inheritance_insn[MAX_RELOADS];
4281 /* If non-zero, this is a place to get the value of the reload,
4282 rather than using reload_in. */
4283 rtx reload_override_in[MAX_RELOADS];
4285 /* For each reload, the index in spill_regs of the spill register used,
4286 or -1 if we did not need one of the spill registers for this reload. */
4287 int reload_spill_index[MAX_RELOADS];
4289 /* Index of last register assigned as a spill register. We allocate in
4290 a round-robin fashio. */
4292 static last_spill_reg = 0;
4294 /* Find a spill register to use as a reload register for reload R.
4295 LAST_RELOAD is non-zero if this is the last reload for the insn being
4298 Set reload_reg_rtx[R] to the register allocated.
4300 If NOERROR is nonzero, we return 1 if successful,
4301 or 0 if we couldn't find a spill reg and we didn't change anything. */
4304 allocate_reload_reg (r, insn, last_reload, noerror)
4316 /* If we put this reload ahead, thinking it is a group,
4317 then insist on finding a group. Otherwise we can grab a
4318 reg that some other reload needs.
4319 (That can happen when we have a 68000 DATA_OR_FP_REG
4320 which is a group of data regs or one fp reg.)
4321 We need not be so restrictive if there are no more reloads
4324 ??? Really it would be nicer to have smarter handling
4325 for that kind of reg class, where a problem like this is normal.
4326 Perhaps those classes should be avoided for reloading
4327 by use of more alternatives. */
4329 int force_group = reload_nregs[r] > 1 && ! last_reload;
4331 /* If we want a single register and haven't yet found one,
4332 take any reg in the right class and not in use.
4333 If we want a consecutive group, here is where we look for it.
4335 We use two passes so we can first look for reload regs to
4336 reuse, which are already in use for other reloads in this insn,
4337 and only then use additional registers.
4338 I think that maximizing reuse is needed to make sure we don't
4339 run out of reload regs. Suppose we have three reloads, and
4340 reloads A and B can share regs. These need two regs.
4341 Suppose A and B are given different regs.
4342 That leaves none for C. */
4343 for (pass = 0; pass < 2; pass++)
4345 /* I is the index in spill_regs.
4346 We advance it round-robin between insns to use all spill regs
4347 equally, so that inherited reloads have a chance
4348 of leapfrogging each other. */
4350 for (count = 0, i = last_spill_reg; count < n_spills; count++)
4352 int class = (int) reload_reg_class[r];
4354 i = (i + 1) % n_spills;
4356 if (reload_reg_free_p (spill_regs[i], reload_opnum[r],
4357 reload_when_needed[r])
4358 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i])
4359 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4360 /* Look first for regs to share, then for unshared. But
4361 don't share regs used for inherited reloads; they are
4362 the ones we want to preserve. */
4364 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
4366 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
4369 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4370 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4371 (on 68000) got us two FP regs. If NR is 1,
4372 we would reject both of them. */
4374 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
4375 /* If we need only one reg, we have already won. */
4378 /* But reject a single reg if we demand a group. */
4383 /* Otherwise check that as many consecutive regs as we need
4385 Also, don't use for a group registers that are
4386 needed for nongroups. */
4387 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]))
4390 regno = spill_regs[i] + nr - 1;
4391 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
4392 && spill_reg_order[regno] >= 0
4393 && reload_reg_free_p (regno, reload_opnum[r],
4394 reload_when_needed[r])
4395 && ! TEST_HARD_REG_BIT (counted_for_nongroups,
4405 /* If we found something on pass 1, omit pass 2. */
4406 if (count < n_spills)
4410 /* We should have found a spill register by now. */
4411 if (count == n_spills)
4418 /* I is the index in SPILL_REG_RTX of the reload register we are to
4419 allocate. Get an rtx for it and find its register number. */
4421 new = spill_reg_rtx[i];
4423 if (new == 0 || GET_MODE (new) != reload_mode[r])
4424 spill_reg_rtx[i] = new
4425 = gen_rtx (REG, reload_mode[r], spill_regs[i]);
4427 regno = true_regnum (new);
4429 /* Detect when the reload reg can't hold the reload mode.
4430 This used to be one `if', but Sequent compiler can't handle that. */
4431 if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4433 enum machine_mode test_mode = VOIDmode;
4435 test_mode = GET_MODE (reload_in[r]);
4436 /* If reload_in[r] has VOIDmode, it means we will load it
4437 in whatever mode the reload reg has: to wit, reload_mode[r].
4438 We have already tested that for validity. */
4439 /* Aside from that, we need to test that the expressions
4440 to reload from or into have modes which are valid for this
4441 reload register. Otherwise the reload insns would be invalid. */
4442 if (! (reload_in[r] != 0 && test_mode != VOIDmode
4443 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4444 if (! (reload_out[r] != 0
4445 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
4447 /* The reg is OK. */
4450 /* Mark as in use for this insn the reload regs we use
4452 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
4453 reload_when_needed[r], reload_mode[r]);
4455 reload_reg_rtx[r] = new;
4456 reload_spill_index[r] = i;
4461 /* The reg is not OK. */
4466 if (asm_noperands (PATTERN (insn)) < 0)
4467 /* It's the compiler's fault. */
4470 /* It's the user's fault; the operand's mode and constraint
4471 don't match. Disable this reload so we don't crash in final. */
4472 error_for_asm (insn,
4473 "`asm' operand constraint incompatible with operand size");
4476 reload_reg_rtx[r] = 0;
4477 reload_optional[r] = 1;
4478 reload_secondary_p[r] = 1;
4483 /* Assign hard reg targets for the pseudo-registers we must reload
4484 into hard regs for this insn.
4485 Also output the instructions to copy them in and out of the hard regs.
4487 For machines with register classes, we are responsible for
4488 finding a reload reg in the proper class. */
4491 choose_reload_regs (insn, avoid_return_reg)
4493 rtx avoid_return_reg;
4496 int max_group_size = 1;
4497 enum reg_class group_class = NO_REGS;
4500 rtx save_reload_reg_rtx[MAX_RELOADS];
4501 char save_reload_inherited[MAX_RELOADS];
4502 rtx save_reload_inheritance_insn[MAX_RELOADS];
4503 rtx save_reload_override_in[MAX_RELOADS];
4504 int save_reload_spill_index[MAX_RELOADS];
4505 HARD_REG_SET save_reload_reg_used;
4506 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4507 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4508 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4509 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4510 HARD_REG_SET save_reload_reg_used_in_op_addr;
4511 HARD_REG_SET save_reload_reg_used_in_insn;
4512 HARD_REG_SET save_reload_reg_used_in_other_addr;
4513 HARD_REG_SET save_reload_reg_used_at_all;
4515 bzero (reload_inherited, MAX_RELOADS);
4516 bzero (reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
4517 bzero (reload_override_in, MAX_RELOADS * sizeof (rtx));
4519 CLEAR_HARD_REG_SET (reload_reg_used);
4520 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
4521 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
4522 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
4523 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
4525 for (i = 0; i < reload_n_operands; i++)
4527 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
4528 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
4529 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
4530 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
4533 #ifdef SMALL_REGISTER_CLASSES
4534 /* Don't bother with avoiding the return reg
4535 if we have no mandatory reload that could use it. */
4536 if (avoid_return_reg)
4539 int regno = REGNO (avoid_return_reg);
4541 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4544 for (r = regno; r < regno + nregs; r++)
4545 if (spill_reg_order[r] >= 0)
4546 for (j = 0; j < n_reloads; j++)
4547 if (!reload_optional[j] && reload_reg_rtx[j] == 0
4548 && (reload_in[j] != 0 || reload_out[j] != 0
4549 || reload_secondary_p[j])
4551 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r))
4554 avoid_return_reg = 0;
4556 #endif /* SMALL_REGISTER_CLASSES */
4558 #if 0 /* Not needed, now that we can always retry without inheritance. */
4559 /* See if we have more mandatory reloads than spill regs.
4560 If so, then we cannot risk optimizations that could prevent
4561 reloads from sharing one spill register.
4563 Since we will try finding a better register than reload_reg_rtx
4564 unless it is equal to reload_in or reload_out, count such reloads. */
4568 #ifdef SMALL_REGISTER_CLASSES
4569 int tem = (avoid_return_reg != 0);
4571 for (j = 0; j < n_reloads; j++)
4572 if (! reload_optional[j]
4573 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
4574 && (reload_reg_rtx[j] == 0
4575 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
4576 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
4583 #ifdef SMALL_REGISTER_CLASSES
4584 /* Don't use the subroutine call return reg for a reload
4585 if we are supposed to avoid it. */
4586 if (avoid_return_reg)
4588 int regno = REGNO (avoid_return_reg);
4590 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg));
4593 for (r = regno; r < regno + nregs; r++)
4594 if (spill_reg_order[r] >= 0)
4595 SET_HARD_REG_BIT (reload_reg_used, r);
4597 #endif /* SMALL_REGISTER_CLASSES */
4599 /* In order to be certain of getting the registers we need,
4600 we must sort the reloads into order of increasing register class.
4601 Then our grabbing of reload registers will parallel the process
4602 that provided the reload registers.
4604 Also note whether any of the reloads wants a consecutive group of regs.
4605 If so, record the maximum size of the group desired and what
4606 register class contains all the groups needed by this insn. */
4608 for (j = 0; j < n_reloads; j++)
4610 reload_order[j] = j;
4611 reload_spill_index[j] = -1;
4614 = (reload_inmode[j] == VOIDmode
4615 || (GET_MODE_SIZE (reload_outmode[j])
4616 > GET_MODE_SIZE (reload_inmode[j])))
4617 ? reload_outmode[j] : reload_inmode[j];
4619 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
4621 if (reload_nregs[j] > 1)
4623 max_group_size = MAX (reload_nregs[j], max_group_size);
4624 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
4627 /* If we have already decided to use a certain register,
4628 don't use it in another way. */
4629 if (reload_reg_rtx[j])
4630 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
4631 reload_when_needed[j], reload_mode[j]);
4635 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
4637 bcopy (reload_reg_rtx, save_reload_reg_rtx, sizeof reload_reg_rtx);
4638 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
4639 bcopy (reload_inheritance_insn, save_reload_inheritance_insn,
4640 sizeof reload_inheritance_insn);
4641 bcopy (reload_override_in, save_reload_override_in,
4642 sizeof reload_override_in);
4643 bcopy (reload_spill_index, save_reload_spill_index,
4644 sizeof reload_spill_index);
4645 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
4646 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
4647 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
4648 reload_reg_used_in_op_addr);
4649 COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
4650 reload_reg_used_in_insn);
4651 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
4652 reload_reg_used_in_other_addr);
4654 for (i = 0; i < reload_n_operands; i++)
4656 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
4657 reload_reg_used_in_output[i]);
4658 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
4659 reload_reg_used_in_input[i]);
4660 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
4661 reload_reg_used_in_input_addr[i]);
4662 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
4663 reload_reg_used_in_output_addr[i]);
4666 /* If -O, try first with inheritance, then turning it off.
4667 If not -O, don't do inheritance.
4668 Using inheritance when not optimizing leads to paradoxes
4669 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
4670 because one side of the comparison might be inherited. */
4672 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
4674 /* Process the reloads in order of preference just found.
4675 Beyond this point, subregs can be found in reload_reg_rtx.
4677 This used to look for an existing reloaded home for all
4678 of the reloads, and only then perform any new reloads.
4679 But that could lose if the reloads were done out of reg-class order
4680 because a later reload with a looser constraint might have an old
4681 home in a register needed by an earlier reload with a tighter constraint.
4683 To solve this, we make two passes over the reloads, in the order
4684 described above. In the first pass we try to inherit a reload
4685 from a previous insn. If there is a later reload that needs a
4686 class that is a proper subset of the class being processed, we must
4687 also allocate a spill register during the first pass.
4689 Then make a second pass over the reloads to allocate any reloads
4690 that haven't been given registers yet. */
4692 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
4694 for (j = 0; j < n_reloads; j++)
4696 register int r = reload_order[j];
4698 /* Ignore reloads that got marked inoperative. */
4699 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4702 /* If find_reloads chose a to use reload_in or reload_out as a reload
4703 register, we don't need to chose one. Otherwise, try even if it found
4704 one since we might save an insn if we find the value lying around. */
4705 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
4706 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
4707 || rtx_equal_p (reload_out[r], reload_reg_rtx[r])))
4710 #if 0 /* No longer needed for correct operation.
4711 It might give better code, or might not; worth an experiment? */
4712 /* If this is an optional reload, we can't inherit from earlier insns
4713 until we are sure that any non-optional reloads have been allocated.
4714 The following code takes advantage of the fact that optional reloads
4715 are at the end of reload_order. */
4716 if (reload_optional[r] != 0)
4717 for (i = 0; i < j; i++)
4718 if ((reload_out[reload_order[i]] != 0
4719 || reload_in[reload_order[i]] != 0
4720 || reload_secondary_p[reload_order[i]])
4721 && ! reload_optional[reload_order[i]]
4722 && reload_reg_rtx[reload_order[i]] == 0)
4723 allocate_reload_reg (reload_order[i], insn, 0, inheritance);
4726 /* First see if this pseudo is already available as reloaded
4727 for a previous insn. We cannot try to inherit for reloads
4728 that are smaller than the maximum number of registers needed
4729 for groups unless the register we would allocate cannot be used
4732 We could check here to see if this is a secondary reload for
4733 an object that is already in a register of the desired class.
4734 This would avoid the need for the secondary reload register.
4735 But this is complex because we can't easily determine what
4736 objects might want to be loaded via this reload. So let a register
4737 be allocated here. In `emit_reload_insns' we suppress one of the
4738 loads in the case described above. */
4742 register int regno = -1;
4743 enum machine_mode mode;
4745 if (reload_in[r] == 0)
4747 else if (GET_CODE (reload_in[r]) == REG)
4749 regno = REGNO (reload_in[r]);
4750 mode = GET_MODE (reload_in[r]);
4752 else if (GET_CODE (reload_in_reg[r]) == REG)
4754 regno = REGNO (reload_in_reg[r]);
4755 mode = GET_MODE (reload_in_reg[r]);
4758 /* This won't work, since REGNO can be a pseudo reg number.
4759 Also, it takes much more hair to keep track of all the things
4760 that can invalidate an inherited reload of part of a pseudoreg. */
4761 else if (GET_CODE (reload_in[r]) == SUBREG
4762 && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
4763 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
4766 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
4768 i = spill_reg_order[REGNO (reg_last_reload_reg[regno])];
4770 if (reg_reloaded_contents[i] == regno
4771 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
4772 >= GET_MODE_SIZE (mode))
4773 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r])
4774 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4776 && (reload_nregs[r] == max_group_size
4777 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
4779 && reload_reg_free_p (spill_regs[i], reload_opnum[r],
4780 reload_when_needed[r])
4781 && reload_reg_free_before_p (spill_regs[i],
4783 reload_when_needed[r]))
4785 /* If a group is needed, verify that all the subsequent
4786 registers still have their values intact. */
4788 = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
4791 for (k = 1; k < nr; k++)
4792 if (reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
4798 /* Mark the register as in use for this part of
4800 mark_reload_reg_in_use (spill_regs[i],
4802 reload_when_needed[r],
4804 reload_reg_rtx[r] = reg_last_reload_reg[regno];
4805 reload_inherited[r] = 1;
4806 reload_inheritance_insn[r] = reg_reloaded_insn[i];
4807 reload_spill_index[r] = i;
4808 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
4815 /* Here's another way to see if the value is already lying around. */
4817 && reload_in[r] != 0
4818 && ! reload_inherited[r]
4819 && reload_out[r] == 0
4820 && (CONSTANT_P (reload_in[r])
4821 || GET_CODE (reload_in[r]) == PLUS
4822 || GET_CODE (reload_in[r]) == REG
4823 || GET_CODE (reload_in[r]) == MEM)
4824 && (reload_nregs[r] == max_group_size
4825 || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
4828 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
4829 -1, NULL_PTR, 0, reload_mode[r]);
4834 if (GET_CODE (equiv) == REG)
4835 regno = REGNO (equiv);
4836 else if (GET_CODE (equiv) == SUBREG)
4838 regno = REGNO (SUBREG_REG (equiv));
4839 if (regno < FIRST_PSEUDO_REGISTER)
4840 regno += SUBREG_WORD (equiv);
4846 /* If we found a spill reg, reject it unless it is free
4847 and of the desired class. */
4849 && ((spill_reg_order[regno] >= 0
4850 && ! reload_reg_free_before_p (regno, reload_opnum[r],
4851 reload_when_needed[r]))
4852 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
4856 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno))
4859 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
4862 /* We found a register that contains the value we need.
4863 If this register is the same as an `earlyclobber' operand
4864 of the current insn, just mark it as a place to reload from
4865 since we can't use it as the reload register itself. */
4868 for (i = 0; i < n_earlyclobbers; i++)
4869 if (reg_overlap_mentioned_for_reload_p (equiv,
4870 reload_earlyclobbers[i]))
4872 reload_override_in[r] = equiv;
4877 /* JRV: If the equiv register we have found is explicitly
4878 clobbered in the current insn, mark but don't use, as above. */
4880 if (equiv != 0 && regno_clobbered_p (regno, insn))
4882 reload_override_in[r] = equiv;
4886 /* If we found an equivalent reg, say no code need be generated
4887 to load it, and use it as our reload reg. */
4888 if (equiv != 0 && regno != FRAME_POINTER_REGNUM)
4890 reload_reg_rtx[r] = equiv;
4891 reload_inherited[r] = 1;
4892 /* If it is a spill reg,
4893 mark the spill reg as in use for this insn. */
4894 i = spill_reg_order[regno];
4897 mark_reload_reg_in_use (regno, reload_opnum[r],
4898 reload_when_needed[r],
4900 SET_HARD_REG_BIT (reload_reg_used_for_inherit, regno);
4905 /* If we found a register to use already, or if this is an optional
4906 reload, we are done. */
4907 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
4910 #if 0 /* No longer needed for correct operation. Might or might not
4911 give better code on the average. Want to experiment? */
4913 /* See if there is a later reload that has a class different from our
4914 class that intersects our class or that requires less register
4915 than our reload. If so, we must allocate a register to this
4916 reload now, since that reload might inherit a previous reload
4917 and take the only available register in our class. Don't do this
4918 for optional reloads since they will force all previous reloads
4919 to be allocated. Also don't do this for reloads that have been
4922 for (i = j + 1; i < n_reloads; i++)
4924 int s = reload_order[i];
4926 if ((reload_in[s] == 0 && reload_out[s] == 0
4927 && ! reload_secondary_p[s])
4928 || reload_optional[s])
4931 if ((reload_reg_class[s] != reload_reg_class[r]
4932 && reg_classes_intersect_p (reload_reg_class[r],
4933 reload_reg_class[s]))
4934 || reload_nregs[s] < reload_nregs[r])
4941 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance);
4945 /* Now allocate reload registers for anything non-optional that
4946 didn't get one yet. */
4947 for (j = 0; j < n_reloads; j++)
4949 register int r = reload_order[j];
4951 /* Ignore reloads that got marked inoperative. */
4952 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
4955 /* Skip reloads that already have a register allocated or are
4957 if (reload_reg_rtx[r] != 0 || reload_optional[r])
4960 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance))
4964 /* If that loop got all the way, we have won. */
4969 /* Loop around and try without any inheritance. */
4970 /* First undo everything done by the failed attempt
4971 to allocate with inheritance. */
4972 bcopy (save_reload_reg_rtx, reload_reg_rtx, sizeof reload_reg_rtx);
4973 bcopy (save_reload_inherited, reload_inherited, sizeof reload_inherited);
4974 bcopy (save_reload_inheritance_insn, reload_inheritance_insn,
4975 sizeof reload_inheritance_insn);
4976 bcopy (save_reload_override_in, reload_override_in,
4977 sizeof reload_override_in);
4978 bcopy (save_reload_spill_index, reload_spill_index,
4979 sizeof reload_spill_index);
4980 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
4981 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
4982 COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
4983 save_reload_reg_used_in_op_addr);
4984 COPY_HARD_REG_SET (reload_reg_used_in_insn,
4985 save_reload_reg_used_in_insn);
4986 COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
4987 save_reload_reg_used_in_other_addr);
4989 for (i = 0; i < reload_n_operands; i++)
4991 COPY_HARD_REG_SET (reload_reg_used_in_input[i],
4992 save_reload_reg_used_in_input[i]);
4993 COPY_HARD_REG_SET (reload_reg_used_in_output[i],
4994 save_reload_reg_used_in_output[i]);
4995 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
4996 save_reload_reg_used_in_input_addr[i]);
4997 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
4998 save_reload_reg_used_in_output_addr[i]);
5002 /* If we thought we could inherit a reload, because it seemed that
5003 nothing else wanted the same reload register earlier in the insn,
5004 verify that assumption, now that all reloads have been assigned. */
5006 for (j = 0; j < n_reloads; j++)
5008 register int r = reload_order[j];
5010 if (reload_inherited[r] && reload_reg_rtx[r] != 0
5011 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]),
5013 reload_when_needed[r]))
5014 reload_inherited[r] = 0;
5016 /* If we found a better place to reload from,
5017 validate it in the same fashion, if it is a reload reg. */
5018 if (reload_override_in[r]
5019 && (GET_CODE (reload_override_in[r]) == REG
5020 || GET_CODE (reload_override_in[r]) == SUBREG))
5022 int regno = true_regnum (reload_override_in[r]);
5023 if (spill_reg_order[regno] >= 0
5024 && ! reload_reg_free_before_p (regno, reload_opnum[r],
5025 reload_when_needed[r]))
5026 reload_override_in[r] = 0;
5030 /* Now that reload_override_in is known valid,
5031 actually override reload_in. */
5032 for (j = 0; j < n_reloads; j++)
5033 if (reload_override_in[j])
5034 reload_in[j] = reload_override_in[j];
5036 /* If this reload won't be done because it has been cancelled or is
5037 optional and not inherited, clear reload_reg_rtx so other
5038 routines (such as subst_reloads) don't get confused. */
5039 for (j = 0; j < n_reloads; j++)
5040 if (reload_reg_rtx[j] != 0
5041 && ((reload_optional[j] && ! reload_inherited[j])
5042 || (reload_in[j] == 0 && reload_out[j] == 0
5043 && ! reload_secondary_p[j])))
5045 int regno = true_regnum (reload_reg_rtx[j]);
5047 if (spill_reg_order[regno] >= 0)
5048 clear_reload_reg_in_use (regno, reload_opnum[j],
5049 reload_when_needed[j], reload_mode[j]);
5050 reload_reg_rtx[j] = 0;
5053 /* Record which pseudos and which spill regs have output reloads. */
5054 for (j = 0; j < n_reloads; j++)
5056 register int r = reload_order[j];
5058 i = reload_spill_index[r];
5060 /* I is nonneg if this reload used one of the spill regs.
5061 If reload_reg_rtx[r] is 0, this is an optional reload
5062 that we opted to ignore. */
5063 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG
5064 && reload_reg_rtx[r] != 0)
5066 register int nregno = REGNO (reload_out[r]);
5069 if (nregno < FIRST_PSEUDO_REGISTER)
5070 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
5073 reg_has_output_reload[nregno + nr] = 1;
5077 nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]);
5079 SET_HARD_REG_BIT (reg_is_output_reload, spill_regs[i] + nr);
5082 if (reload_when_needed[r] != RELOAD_OTHER
5083 && reload_when_needed[r] != RELOAD_FOR_OUTPUT
5084 && reload_when_needed[r] != RELOAD_FOR_INSN)
5090 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5091 reloads of the same item for fear that we might not have enough reload
5092 registers. However, normally they will get the same reload register
5093 and hence actually need not be loaded twice.
5095 Here we check for the most common case of this phenomenon: when we have
5096 a number of reloads for the same object, each of which were allocated
5097 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5098 reload, and is not modified in the insn itself. If we find such,
5099 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5100 This will not increase the number of spill registers needed and will
5101 prevent redundant code. */
5103 #ifdef SMALL_REGISTER_CLASSES
5106 merge_assigned_reloads (insn)
5111 /* Scan all the reloads looking for ones that only load values and
5112 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5113 assigned and not modified by INSN. */
5115 for (i = 0; i < n_reloads; i++)
5117 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
5118 || reload_out[i] != 0 || reload_reg_rtx[i] == 0
5119 || reg_set_p (reload_reg_rtx[i], insn))
5122 /* Look at all other reloads. Ensure that the only use of this
5123 reload_reg_rtx is in a reload that just loads the same value
5124 as we do. Note that any secondary reloads must be of the identical
5125 class since the values, modes, and result registers are the
5126 same, so we need not do anything with any secondary reloads. */
5128 for (j = 0; j < n_reloads; j++)
5130 if (i == j || reload_reg_rtx[j] == 0
5131 || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
5135 /* If the reload regs aren't exactly the same (e.g, different modes)
5136 or if the values are different, we can't merge anything with this
5139 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
5140 || reload_out[j] != 0 || reload_in[j] == 0
5141 || ! rtx_equal_p (reload_in[i], reload_in[j]))
5145 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5146 we, in fact, found any matching reloads. */
5150 for (j = 0; j < n_reloads; j++)
5151 if (i != j && reload_reg_rtx[j] != 0
5152 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]))
5154 reload_when_needed[i] = RELOAD_OTHER;
5156 transfer_replacements (i, j);
5159 /* If this is now RELOAD_OTHER, look for any reloads that load
5160 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5161 if they were for inputs, RELOAD_OTHER for outputs. Note that
5162 this test is equivalent to looking for reloads for this operand
5165 if (reload_when_needed[i] == RELOAD_OTHER)
5166 for (j = 0; j < n_reloads; j++)
5167 if (reload_in[j] != 0
5168 && reload_when_needed[i] != RELOAD_OTHER
5169 && reg_overlap_mentioned_for_reload_p (reload_in[j],
5171 reload_when_needed[j]
5172 = reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
5173 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER;
5177 #endif /* SMALL_RELOAD_CLASSES */
5179 /* Output insns to reload values in and out of the chosen reload regs. */
5182 emit_reload_insns (insn)
5186 rtx input_reload_insns[MAX_RECOG_OPERANDS];
5187 rtx other_input_address_reload_insns = 0;
5188 rtx other_input_reload_insns = 0;
5189 rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5190 rtx output_reload_insns[MAX_RECOG_OPERANDS];
5191 rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5192 rtx operand_reload_insns = 0;
5193 rtx following_insn = NEXT_INSN (insn);
5194 rtx before_insn = insn;
5196 /* Values to be put in spill_reg_store are put here first. */
5197 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5199 for (j = 0; j < reload_n_operands; j++)
5200 input_reload_insns[j] = input_address_reload_insns[j]
5201 = output_reload_insns[j] = output_address_reload_insns[j] = 0;
5203 /* If this is a CALL_INSN preceded by USE insns, any reload insns
5204 must go in front of the first USE insn, not in front of INSN. */
5206 if (GET_CODE (insn) == CALL_INSN && GET_CODE (PREV_INSN (insn)) == INSN
5207 && GET_CODE (PATTERN (PREV_INSN (insn))) == USE)
5208 while (GET_CODE (PREV_INSN (before_insn)) == INSN
5209 && GET_CODE (PATTERN (PREV_INSN (before_insn))) == USE)
5210 before_insn = PREV_INSN (before_insn);
5212 /* If this insn is followed by any CLOBBER insns made by find_reloads,
5213 put our reloads after them since they may otherwise be
5216 while (NEXT_INSN (following_insn) != 0
5217 && GET_CODE (NEXT_INSN (following_insn)) == INSN
5218 && GET_MODE (NEXT_INSN (following_insn)) == DImode
5219 && GET_CODE (PATTERN (NEXT_INSN (following_insn))) == CLOBBER)
5220 following_insn = NEXT_INSN (following_insn);
5222 /* Now output the instructions to copy the data into and out of the
5223 reload registers. Do these in the order that the reloads were reported,
5224 since reloads of base and index registers precede reloads of operands
5225 and the operands may need the base and index registers reloaded. */
5227 for (j = 0; j < n_reloads; j++)
5230 rtx oldequiv_reg = 0;
5234 if (old != 0 && ! reload_inherited[j]
5235 && ! rtx_equal_p (reload_reg_rtx[j], old)
5236 && reload_reg_rtx[j] != 0)
5238 register rtx reloadreg = reload_reg_rtx[j];
5240 enum machine_mode mode;
5243 /* Determine the mode to reload in.
5244 This is very tricky because we have three to choose from.
5245 There is the mode the insn operand wants (reload_inmode[J]).
5246 There is the mode of the reload register RELOADREG.
5247 There is the intrinsic mode of the operand, which we could find
5248 by stripping some SUBREGs.
5249 It turns out that RELOADREG's mode is irrelevant:
5250 we can change that arbitrarily.
5252 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5253 then the reload reg may not support QImode moves, so use SImode.
5254 If foo is in memory due to spilling a pseudo reg, this is safe,
5255 because the QImode value is in the least significant part of a
5256 slot big enough for a SImode. If foo is some other sort of
5257 memory reference, then it is impossible to reload this case,
5258 so previous passes had better make sure this never happens.
5260 Then consider a one-word union which has SImode and one of its
5261 members is a float, being fetched as (SUBREG:SF union:SI).
5262 We must fetch that as SFmode because we could be loading into
5263 a float-only register. In this case OLD's mode is correct.
5265 Consider an immediate integer: it has VOIDmode. Here we need
5266 to get a mode from something else.
5268 In some cases, there is a fourth mode, the operand's
5269 containing mode. If the insn specifies a containing mode for
5270 this operand, it overrides all others.
5272 I am not sure whether the algorithm here is always right,
5273 but it does the right things in those cases. */
5275 mode = GET_MODE (old);
5276 if (mode == VOIDmode)
5277 mode = reload_inmode[j];
5279 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5280 /* If we need a secondary register for this operation, see if
5281 the value is already in a register in that class. Don't
5282 do this if the secondary register will be used as a scratch
5285 if (reload_secondary_reload[j] >= 0
5286 && reload_secondary_icode[j] == CODE_FOR_nothing
5289 = find_equiv_reg (old, insn,
5290 reload_reg_class[reload_secondary_reload[j]],
5291 -1, NULL_PTR, 0, mode);
5294 /* If reloading from memory, see if there is a register
5295 that already holds the same value. If so, reload from there.
5296 We can pass 0 as the reload_reg_p argument because
5297 any other reload has either already been emitted,
5298 in which case find_equiv_reg will see the reload-insn,
5299 or has yet to be emitted, in which case it doesn't matter
5300 because we will use this equiv reg right away. */
5302 if (oldequiv == 0 && optimize
5303 && (GET_CODE (old) == MEM
5304 || (GET_CODE (old) == REG
5305 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5306 && reg_renumber[REGNO (old)] < 0)))
5307 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
5308 -1, NULL_PTR, 0, mode);
5312 int regno = true_regnum (oldequiv);
5314 /* If OLDEQUIV is a spill register, don't use it for this
5315 if any other reload needs it at an earlier stage of this insn
5316 or at this stage. */
5317 if (spill_reg_order[regno] >= 0
5318 && (! reload_reg_free_p (regno, reload_opnum[j],
5319 reload_when_needed[j])
5320 || ! reload_reg_free_before_p (regno, reload_opnum[j],
5321 reload_when_needed[j])))
5324 /* If OLDEQUIV is not a spill register,
5325 don't use it if any other reload wants it. */
5326 if (spill_reg_order[regno] < 0)
5329 for (k = 0; k < n_reloads; k++)
5330 if (reload_reg_rtx[k] != 0 && k != j
5331 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k],
5339 /* If it is no cheaper to copy from OLDEQUIV into the
5340 reload register than it would be to move from memory,
5341 don't use it. Likewise, if we need a secondary register
5345 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
5346 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
5347 reload_reg_class[j])
5348 >= MEMORY_MOVE_COST (mode)))
5349 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5350 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5354 #ifdef SECONDARY_MEMORY_NEEDED
5355 || SECONDARY_MEMORY_NEEDED (reload_reg_class[j],
5356 REGNO_REG_CLASS (regno),
5365 else if (GET_CODE (oldequiv) == REG)
5366 oldequiv_reg = oldequiv;
5367 else if (GET_CODE (oldequiv) == SUBREG)
5368 oldequiv_reg = SUBREG_REG (oldequiv);
5370 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
5371 then load RELOADREG from OLDEQUIV. */
5373 if (GET_MODE (reloadreg) != mode)
5374 reloadreg = gen_lowpart_common (mode, reloadreg);
5375 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
5376 oldequiv = SUBREG_REG (oldequiv);
5377 if (GET_MODE (oldequiv) != VOIDmode
5378 && mode != GET_MODE (oldequiv))
5379 oldequiv = gen_rtx (SUBREG, mode, oldequiv, 0);
5381 /* Switch to the right place to emit the reload insns. */
5382 switch (reload_when_needed[j])
5385 where = &other_input_reload_insns;
5387 case RELOAD_FOR_INPUT:
5388 where = &input_reload_insns[reload_opnum[j]];
5390 case RELOAD_FOR_INPUT_ADDRESS:
5391 where = &input_address_reload_insns[reload_opnum[j]];
5393 case RELOAD_FOR_OUTPUT_ADDRESS:
5394 where = &output_address_reload_insns[reload_opnum[j]];
5396 case RELOAD_FOR_OPERAND_ADDRESS:
5397 where = &operand_reload_insns;
5399 case RELOAD_FOR_OTHER_ADDRESS:
5400 where = &other_input_address_reload_insns;
5406 push_to_sequence (*where);
5409 /* Auto-increment addresses must be reloaded in a special way. */
5410 if (GET_CODE (oldequiv) == POST_INC
5411 || GET_CODE (oldequiv) == POST_DEC
5412 || GET_CODE (oldequiv) == PRE_INC
5413 || GET_CODE (oldequiv) == PRE_DEC)
5415 /* We are not going to bother supporting the case where a
5416 incremented register can't be copied directly from
5417 OLDEQUIV since this seems highly unlikely. */
5418 if (reload_secondary_reload[j] >= 0)
5420 /* Prevent normal processing of this reload. */
5422 /* Output a special code sequence for this case. */
5423 inc_for_reload (reloadreg, oldequiv, reload_inc[j]);
5426 /* If we are reloading a pseudo-register that was set by the previous
5427 insn, see if we can get rid of that pseudo-register entirely
5428 by redirecting the previous insn into our reload register. */
5430 else if (optimize && GET_CODE (old) == REG
5431 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5432 && dead_or_set_p (insn, old)
5433 /* This is unsafe if some other reload
5434 uses the same reg first. */
5435 && reload_reg_free_before_p (REGNO (reloadreg),
5437 reload_when_needed[j]))
5439 rtx temp = PREV_INSN (insn);
5440 while (temp && GET_CODE (temp) == NOTE)
5441 temp = PREV_INSN (temp);
5443 && GET_CODE (temp) == INSN
5444 && GET_CODE (PATTERN (temp)) == SET
5445 && SET_DEST (PATTERN (temp)) == old
5446 /* Make sure we can access insn_operand_constraint. */
5447 && asm_noperands (PATTERN (temp)) < 0
5448 /* This is unsafe if prev insn rejects our reload reg. */
5449 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
5451 /* This is unsafe if operand occurs more than once in current
5452 insn. Perhaps some occurrences aren't reloaded. */
5453 && count_occurrences (PATTERN (insn), old) == 1
5454 /* Don't risk splitting a matching pair of operands. */
5455 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
5457 /* Store into the reload register instead of the pseudo. */
5458 SET_DEST (PATTERN (temp)) = reloadreg;
5459 /* If these are the only uses of the pseudo reg,
5460 pretend for GDB it lives in the reload reg we used. */
5461 if (reg_n_deaths[REGNO (old)] == 1
5462 && reg_n_sets[REGNO (old)] == 1)
5464 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
5465 alter_reg (REGNO (old), -1);
5471 /* We can't do that, so output an insn to load RELOADREG. */
5475 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5476 rtx second_reload_reg = 0;
5477 enum insn_code icode;
5479 /* If we have a secondary reload, pick up the secondary register
5480 and icode, if any. If OLDEQUIV and OLD are different or
5481 if this is an in-out reload, recompute whether or not we
5482 still need a secondary register and what the icode should
5483 be. If we still need a secondary register and the class or
5484 icode is different, go back to reloading from OLD if using
5485 OLDEQUIV means that we got the wrong type of register. We
5486 cannot have different class or icode due to an in-out reload
5487 because we don't make such reloads when both the input and
5488 output need secondary reload registers. */
5490 if (reload_secondary_reload[j] >= 0)
5492 int secondary_reload = reload_secondary_reload[j];
5493 rtx real_oldequiv = oldequiv;
5496 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
5497 and similarly for OLD.
5498 See comments in find_secondary_reload in reload.c. */
5499 if (GET_CODE (oldequiv) == REG
5500 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
5501 && reg_equiv_mem[REGNO (oldequiv)] != 0)
5502 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
5504 if (GET_CODE (old) == REG
5505 && REGNO (old) >= FIRST_PSEUDO_REGISTER
5506 && reg_equiv_mem[REGNO (old)] != 0)
5507 real_old = reg_equiv_mem[REGNO (old)];
5509 second_reload_reg = reload_reg_rtx[secondary_reload];
5510 icode = reload_secondary_icode[j];
5512 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
5513 || (reload_in[j] != 0 && reload_out[j] != 0))
5515 enum reg_class new_class
5516 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
5517 mode, real_oldequiv);
5519 if (new_class == NO_REGS)
5520 second_reload_reg = 0;
5523 enum insn_code new_icode;
5524 enum machine_mode new_mode;
5526 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
5527 REGNO (second_reload_reg)))
5528 oldequiv = old, real_oldequiv = real_old;
5531 new_icode = reload_in_optab[(int) mode];
5532 if (new_icode != CODE_FOR_nothing
5533 && ((insn_operand_predicate[(int) new_icode][0]
5534 && ! ((*insn_operand_predicate[(int) new_icode][0])
5536 || (insn_operand_predicate[(int) new_icode][1]
5537 && ! ((*insn_operand_predicate[(int) new_icode][1])
5538 (real_oldequiv, mode)))))
5539 new_icode = CODE_FOR_nothing;
5541 if (new_icode == CODE_FOR_nothing)
5544 new_mode = insn_operand_mode[(int) new_icode][2];
5546 if (GET_MODE (second_reload_reg) != new_mode)
5548 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
5550 oldequiv = old, real_oldequiv = real_old;
5553 = gen_rtx (REG, new_mode,
5554 REGNO (second_reload_reg));
5560 /* If we still need a secondary reload register, check
5561 to see if it is being used as a scratch or intermediate
5562 register and generate code appropriately. If we need
5563 a scratch register, use REAL_OLDEQUIV since the form of
5564 the insn may depend on the actual address if it is
5567 if (second_reload_reg)
5569 if (icode != CODE_FOR_nothing)
5571 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
5572 second_reload_reg));
5577 /* See if we need a scratch register to load the
5578 intermediate register (a tertiary reload). */
5579 enum insn_code tertiary_icode
5580 = reload_secondary_icode[secondary_reload];
5582 if (tertiary_icode != CODE_FOR_nothing)
5584 rtx third_reload_reg
5585 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5587 emit_insn ((GEN_FCN (tertiary_icode)
5588 (second_reload_reg, real_oldequiv,
5589 third_reload_reg)));
5592 gen_input_reload (second_reload_reg, oldequiv,
5594 reload_when_needed[j]);
5596 oldequiv = second_reload_reg;
5603 gen_input_reload (reloadreg, oldequiv, reload_opnum[j],
5604 reload_when_needed[j]);
5606 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
5607 /* We may have to make a REG_DEAD note for the secondary reload
5608 register in the insns we just made. Find the last insn that
5609 mentioned the register. */
5610 if (! special && second_reload_reg
5611 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg)))
5615 for (prev = get_last_insn (); prev;
5616 prev = PREV_INSN (prev))
5617 if (GET_RTX_CLASS (GET_CODE (prev) == 'i')
5618 && reg_overlap_mentioned_for_reload_p (second_reload_reg,
5621 REG_NOTES (prev) = gen_rtx (EXPR_LIST, REG_DEAD,
5630 /* End this sequence. */
5631 *where = get_insns ();
5635 /* Add a note saying the input reload reg
5636 dies in this insn, if anyone cares. */
5637 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5639 && reload_reg_rtx[j] != old
5640 && reload_reg_rtx[j] != 0
5641 && reload_out[j] == 0
5642 && ! reload_inherited[j]
5643 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])))
5645 register rtx reloadreg = reload_reg_rtx[j];
5648 /* We can't abort here because we need to support this for sched.c.
5649 It's not terrible to miss a REG_DEAD note, but we should try
5650 to figure out how to do this correctly. */
5651 /* The code below is incorrect for address-only reloads. */
5652 if (reload_when_needed[j] != RELOAD_OTHER
5653 && reload_when_needed[j] != RELOAD_FOR_INPUT)
5657 /* Add a death note to this insn, for an input reload. */
5659 if ((reload_when_needed[j] == RELOAD_OTHER
5660 || reload_when_needed[j] == RELOAD_FOR_INPUT)
5661 && ! dead_or_set_p (insn, reloadreg))
5663 = gen_rtx (EXPR_LIST, REG_DEAD,
5664 reloadreg, REG_NOTES (insn));
5667 /* When we inherit a reload, the last marked death of the reload reg
5668 may no longer really be a death. */
5669 if (reload_reg_rtx[j] != 0
5670 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))
5671 && reload_inherited[j])
5673 /* Handle inheriting an output reload.
5674 Remove the death note from the output reload insn. */
5675 if (reload_spill_index[j] >= 0
5676 && GET_CODE (reload_in[j]) == REG
5677 && spill_reg_store[reload_spill_index[j]] != 0
5678 && find_regno_note (spill_reg_store[reload_spill_index[j]],
5679 REG_DEAD, REGNO (reload_reg_rtx[j])))
5680 remove_death (REGNO (reload_reg_rtx[j]),
5681 spill_reg_store[reload_spill_index[j]]);
5682 /* Likewise for input reloads that were inherited. */
5683 else if (reload_spill_index[j] >= 0
5684 && GET_CODE (reload_in[j]) == REG
5685 && spill_reg_store[reload_spill_index[j]] == 0
5686 && reload_inheritance_insn[j] != 0
5687 && find_regno_note (reload_inheritance_insn[j], REG_DEAD,
5688 REGNO (reload_reg_rtx[j])))
5689 remove_death (REGNO (reload_reg_rtx[j]),
5690 reload_inheritance_insn[j]);
5695 /* We got this register from find_equiv_reg.
5696 Search back for its last death note and get rid of it.
5697 But don't search back too far.
5698 Don't go past a place where this reg is set,
5699 since a death note before that remains valid. */
5700 for (prev = PREV_INSN (insn);
5701 prev && GET_CODE (prev) != CODE_LABEL;
5702 prev = PREV_INSN (prev))
5703 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5704 && dead_or_set_p (prev, reload_reg_rtx[j]))
5706 if (find_regno_note (prev, REG_DEAD,
5707 REGNO (reload_reg_rtx[j])))
5708 remove_death (REGNO (reload_reg_rtx[j]), prev);
5714 /* We might have used find_equiv_reg above to choose an alternate
5715 place from which to reload. If so, and it died, we need to remove
5716 that death and move it to one of the insns we just made. */
5718 if (oldequiv_reg != 0
5719 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg)))
5723 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL;
5724 prev = PREV_INSN (prev))
5725 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i'
5726 && dead_or_set_p (prev, oldequiv_reg))
5728 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg)))
5730 for (prev1 = this_reload_insn;
5731 prev1; prev1 = PREV_INSN (prev1))
5732 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i')
5733 && reg_overlap_mentioned_for_reload_p (oldequiv_reg,
5736 REG_NOTES (prev1) = gen_rtx (EXPR_LIST, REG_DEAD,
5741 remove_death (REGNO (oldequiv_reg), prev);
5748 /* If we are reloading a register that was recently stored in with an
5749 output-reload, see if we can prove there was
5750 actually no need to store the old value in it. */
5752 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0
5753 && reload_in[j] != 0
5754 && GET_CODE (reload_in[j]) == REG
5756 /* There doesn't seem to be any reason to restrict this to pseudos
5757 and doing so loses in the case where we are copying from a
5758 register of the wrong class. */
5759 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER
5761 && spill_reg_store[reload_spill_index[j]] != 0
5762 /* This is unsafe if some other reload uses the same reg first. */
5763 && reload_reg_free_before_p (spill_regs[reload_spill_index[j]],
5764 reload_opnum[j], reload_when_needed[j])
5765 && dead_or_set_p (insn, reload_in[j])
5766 /* This is unsafe if operand occurs more than once in current
5767 insn. Perhaps some occurrences weren't reloaded. */
5768 && count_occurrences (PATTERN (insn), reload_in[j]) == 1)
5769 delete_output_reload (insn, j,
5770 spill_reg_store[reload_spill_index[j]]);
5772 /* Input-reloading is done. Now do output-reloading,
5773 storing the value from the reload-register after the main insn
5774 if reload_out[j] is nonzero.
5776 ??? At some point we need to support handling output reloads of
5777 JUMP_INSNs or insns that set cc0. */
5778 old = reload_out[j];
5780 && reload_reg_rtx[j] != old
5781 && reload_reg_rtx[j] != 0)
5783 register rtx reloadreg = reload_reg_rtx[j];
5784 register rtx second_reloadreg = 0;
5786 enum machine_mode mode;
5789 /* An output operand that dies right away does need a reload,
5790 but need not be copied from it. Show the new location in the
5792 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
5793 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
5795 XEXP (note, 0) = reload_reg_rtx[j];
5798 else if (GET_CODE (old) == SCRATCH)
5799 /* If we aren't optimizing, there won't be a REG_UNUSED note,
5800 but we don't want to make an output reload. */
5804 /* Strip off of OLD any size-increasing SUBREGs such as
5805 (SUBREG:SI foo:QI 0). */
5807 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0
5808 && (GET_MODE_SIZE (GET_MODE (old))
5809 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old)))))
5810 old = SUBREG_REG (old);
5813 /* If is a JUMP_INSN, we can't support output reloads yet. */
5814 if (GET_CODE (insn) == JUMP_INSN)
5817 push_to_sequence (output_reload_insns[reload_opnum[j]]);
5819 /* Determine the mode to reload in.
5820 See comments above (for input reloading). */
5822 mode = GET_MODE (old);
5823 if (mode == VOIDmode)
5825 /* VOIDmode should never happen for an output. */
5826 if (asm_noperands (PATTERN (insn)) < 0)
5827 /* It's the compiler's fault. */
5829 error_for_asm (insn, "output operand is constant in `asm'");
5830 /* Prevent crash--use something we know is valid. */
5832 old = gen_rtx (REG, mode, REGNO (reloadreg));
5835 if (GET_MODE (reloadreg) != mode)
5836 reloadreg = gen_lowpart_common (mode, reloadreg);
5838 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5840 /* If we need two reload regs, set RELOADREG to the intermediate
5841 one, since it will be stored into OUT. We might need a secondary
5842 register only for an input reload, so check again here. */
5844 if (reload_secondary_reload[j] >= 0)
5848 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
5849 && reg_equiv_mem[REGNO (old)] != 0)
5850 real_old = reg_equiv_mem[REGNO (old)];
5852 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
5856 second_reloadreg = reloadreg;
5857 reloadreg = reload_reg_rtx[reload_secondary_reload[j]];
5859 /* See if RELOADREG is to be used as a scratch register
5860 or as an intermediate register. */
5861 if (reload_secondary_icode[j] != CODE_FOR_nothing)
5863 emit_insn ((GEN_FCN (reload_secondary_icode[j])
5864 (real_old, second_reloadreg, reloadreg)));
5869 /* See if we need both a scratch and intermediate reload
5871 int secondary_reload = reload_secondary_reload[j];
5872 enum insn_code tertiary_icode
5873 = reload_secondary_icode[secondary_reload];
5876 if (GET_MODE (reloadreg) != mode)
5877 reloadreg = gen_rtx (REG, mode, REGNO (reloadreg));
5879 if (tertiary_icode != CODE_FOR_nothing)
5882 = reload_reg_rtx[reload_secondary_reload[secondary_reload]];
5883 pat = (GEN_FCN (tertiary_icode)
5884 (reloadreg, second_reloadreg, third_reloadreg));
5886 #ifdef SECONDARY_MEMORY_NEEDED
5887 /* If we need a memory location to do the move, do it that way. */
5888 else if (GET_CODE (reloadreg) == REG
5889 && REGNO (reloadreg) < FIRST_PSEUDO_REGISTER
5890 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg)),
5891 REGNO_REG_CLASS (REGNO (second_reloadreg)),
5892 GET_MODE (second_reloadreg)))
5894 /* Get the memory to use and rewrite both registers
5897 = get_secondary_mem (reloadreg,
5898 GET_MODE (second_reloadreg),
5900 reload_when_needed[j]);
5903 if (GET_MODE (loc) != GET_MODE (second_reloadreg))
5904 second_reloadreg = gen_rtx (REG, GET_MODE (loc),
5905 REGNO (second_reloadreg));
5907 if (GET_MODE (loc) != GET_MODE (reloadreg))
5908 tmp_reloadreg = gen_rtx (REG, GET_MODE (loc),
5911 tmp_reloadreg = reloadreg;
5913 emit_move_insn (loc, second_reloadreg);
5914 pat = gen_move_insn (tmp_reloadreg, loc);
5918 pat = gen_move_insn (reloadreg, second_reloadreg);
5926 /* Output the last reload insn. */
5929 #ifdef SECONDARY_MEMORY_NEEDED
5930 /* If we need a memory location to do the move, do it that way. */
5931 if (GET_CODE (old) == REG && REGNO (old) < FIRST_PSEUDO_REGISTER
5932 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old)),
5933 REGNO_REG_CLASS (REGNO (reloadreg)),
5934 GET_MODE (reloadreg)))
5936 /* Get the memory to use and rewrite both registers to
5938 rtx loc = get_secondary_mem (old, GET_MODE (reloadreg),
5940 reload_when_needed[j]);
5942 if (GET_MODE (loc) != GET_MODE (reloadreg))
5943 reloadreg = gen_rtx (REG, GET_MODE (loc),
5946 if (GET_MODE (loc) != GET_MODE (old))
5947 old = gen_rtx (REG, GET_MODE (loc), REGNO (old));
5949 emit_insn (gen_move_insn (loc, reloadreg));
5950 emit_insn (gen_move_insn (old, loc));
5954 emit_insn (gen_move_insn (old, reloadreg));
5957 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5958 /* If final will look at death notes for this reg,
5959 put one on the last output-reload insn to use it. Similarly
5960 for any secondary register. */
5961 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg)))
5962 for (p = get_last_insn (); p; p = PREV_INSN (p))
5963 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5964 && reg_overlap_mentioned_for_reload_p (reloadreg,
5966 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5967 reloadreg, REG_NOTES (p));
5969 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
5971 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg)))
5972 for (p = get_last_insn (); p; p = PREV_INSN (p))
5973 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
5974 && reg_overlap_mentioned_for_reload_p (second_reloadreg,
5976 REG_NOTES (p) = gen_rtx (EXPR_LIST, REG_DEAD,
5977 second_reloadreg, REG_NOTES (p));
5980 /* Look at all insns we emitted, just to be safe. */
5981 for (p = get_insns (); p; p = NEXT_INSN (p))
5982 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
5984 /* If this output reload doesn't come from a spill reg,
5985 clear any memory of reloaded copies of the pseudo reg.
5986 If this output reload comes from a spill reg,
5987 reg_has_output_reload will make this do nothing. */
5988 note_stores (PATTERN (p), forget_old_reloads_1);
5990 if (reg_mentioned_p (reload_reg_rtx[j], PATTERN (p)))
5994 output_reload_insns[reload_opnum[j]] = get_insns ();
5999 if (reload_spill_index[j] >= 0)
6000 new_spill_reg_store[reload_spill_index[j]] = store_insn;
6003 /* Now write all the insns we made for reloads in the order expected by
6004 the allocation functions. Prior to the insn being reloaded, we write
6005 the following reloads:
6007 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6009 RELOAD_OTHER reloads.
6011 For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by
6012 the RELOAD_FOR_INPUT reload for the operand.
6014 RELOAD_FOR_OPERAND_ADDRESS reloads.
6016 After the insn being reloaded, we write the following:
6018 For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by
6019 the RELOAD_FOR_OUTPUT reload for that operand. */
6021 emit_insns_before (other_input_address_reload_insns, before_insn);
6022 emit_insns_before (other_input_reload_insns, before_insn);
6024 for (j = 0; j < reload_n_operands; j++)
6026 emit_insns_before (input_address_reload_insns[j], before_insn);
6027 emit_insns_before (input_reload_insns[j], before_insn);
6030 emit_insns_before (operand_reload_insns, before_insn);
6032 for (j = 0; j < reload_n_operands; j++)
6034 emit_insns_before (output_address_reload_insns[j], following_insn);
6035 emit_insns_before (output_reload_insns[j], following_insn);
6038 /* Move death notes from INSN
6039 to output-operand-address and output reload insns. */
6040 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6043 /* Loop over those insns, last ones first. */
6044 for (insn1 = PREV_INSN (following_insn); insn1 != insn;
6045 insn1 = PREV_INSN (insn1))
6046 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET)
6048 rtx source = SET_SRC (PATTERN (insn1));
6049 rtx dest = SET_DEST (PATTERN (insn1));
6051 /* The note we will examine next. */
6052 rtx reg_notes = REG_NOTES (insn);
6053 /* The place that pointed to this note. */
6054 rtx *prev_reg_note = ®_NOTES (insn);
6056 /* If the note is for something used in the source of this
6057 reload insn, or in the output address, move the note. */
6060 rtx next_reg_notes = XEXP (reg_notes, 1);
6061 if (REG_NOTE_KIND (reg_notes) == REG_DEAD
6062 && GET_CODE (XEXP (reg_notes, 0)) == REG
6063 && ((GET_CODE (dest) != REG
6064 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6066 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0),
6069 *prev_reg_note = next_reg_notes;
6070 XEXP (reg_notes, 1) = REG_NOTES (insn1);
6071 REG_NOTES (insn1) = reg_notes;
6074 prev_reg_note = &XEXP (reg_notes, 1);
6076 reg_notes = next_reg_notes;
6082 /* For all the spill regs newly reloaded in this instruction,
6083 record what they were reloaded from, so subsequent instructions
6084 can inherit the reloads.
6086 Update spill_reg_store for the reloads of this insn.
6087 Copy the elements that were updated in the loop above. */
6089 for (j = 0; j < n_reloads; j++)
6091 register int r = reload_order[j];
6092 register int i = reload_spill_index[r];
6094 /* I is nonneg if this reload used one of the spill regs.
6095 If reload_reg_rtx[r] is 0, this is an optional reload
6096 that we opted to ignore.
6098 Also ignore reloads that don't reach the end of the insn,
6099 since we will eventually see the one that does. */
6101 if (i >= 0 && reload_reg_rtx[r] != 0
6102 && reload_reg_reaches_end_p (spill_regs[i], reload_opnum[r],
6103 reload_when_needed[r]))
6105 /* First, clear out memory of what used to be in this spill reg.
6106 If consecutive registers are used, clear them all. */
6108 = HARD_REGNO_NREGS (spill_regs[i], GET_MODE (reload_reg_rtx[r]));
6111 for (k = 0; k < nr; k++)
6113 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]] = -1;
6114 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = 0;
6117 /* Maybe the spill reg contains a copy of reload_out. */
6118 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6120 register int nregno = REGNO (reload_out[r]);
6121 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6122 : HARD_REGNO_NREGS (nregno,
6123 GET_MODE (reload_reg_rtx[r])));
6125 spill_reg_store[i] = new_spill_reg_store[i];
6126 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6128 /* If NREGNO is a hard register, it may occupy more than
6129 one register. If it does, say what is in the
6130 rest of the registers assuming that both registers
6131 agree on how many words the object takes. If not,
6132 invalidate the subsequent registers. */
6134 if (nregno < FIRST_PSEUDO_REGISTER)
6135 for (k = 1; k < nnr; k++)
6136 reg_last_reload_reg[nregno + k]
6137 = (nr == nnr ? gen_rtx (REG, word_mode,
6138 REGNO (reload_reg_rtx[r]) + k)
6141 /* Now do the inverse operation. */
6142 for (k = 0; k < nr; k++)
6144 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6145 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6147 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]] = insn;
6151 /* Maybe the spill reg contains a copy of reload_in. Only do
6152 something if there will not be an output reload for
6153 the register being reloaded. */
6154 else if (reload_out[r] == 0
6155 && reload_in[r] != 0
6156 && ((GET_CODE (reload_in[r]) == REG
6157 && ! reg_has_output_reload[REGNO (reload_in[r])]
6158 || (GET_CODE (reload_in_reg[r]) == REG
6159 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))))
6161 register int nregno;
6164 if (GET_CODE (reload_in[r]) == REG)
6165 nregno = REGNO (reload_in[r]);
6167 nregno = REGNO (reload_in_reg[r]);
6169 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6170 : HARD_REGNO_NREGS (nregno,
6171 GET_MODE (reload_reg_rtx[r])));
6173 reg_last_reload_reg[nregno] = reload_reg_rtx[r];
6175 if (nregno < FIRST_PSEUDO_REGISTER)
6176 for (k = 1; k < nnr; k++)
6177 reg_last_reload_reg[nregno + k]
6178 = (nr == nnr ? gen_rtx (REG, word_mode,
6179 REGNO (reload_reg_rtx[r]) + k)
6182 /* Unless we inherited this reload, show we haven't
6183 recently done a store. */
6184 if (! reload_inherited[r])
6185 spill_reg_store[i] = 0;
6187 for (k = 0; k < nr; k++)
6189 reg_reloaded_contents[spill_reg_order[spill_regs[i] + k]]
6190 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr ? nregno
6192 reg_reloaded_insn[spill_reg_order[spill_regs[i] + k]]
6198 /* The following if-statement was #if 0'd in 1.34 (or before...).
6199 It's reenabled in 1.35 because supposedly nothing else
6200 deals with this problem. */
6202 /* If a register gets output-reloaded from a non-spill register,
6203 that invalidates any previous reloaded copy of it.
6204 But forget_old_reloads_1 won't get to see it, because
6205 it thinks only about the original insn. So invalidate it here. */
6206 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG)
6208 register int nregno = REGNO (reload_out[r]);
6209 reg_last_reload_reg[nregno] = 0;
6214 /* Emit code to perform an input reload of IN to RELOADREG. IN is from
6215 operand OPNUM with reload type TYPE.
6217 Returns first insn emitted. */
6220 gen_input_reload (reloadreg, in, opnum, type)
6224 enum reload_type type;
6226 rtx last = get_last_insn ();
6228 /* How to do this reload can get quite tricky. Normally, we are being
6229 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
6230 register that didn't get a hard register. In that case we can just
6231 call emit_move_insn.
6233 We can also be asked to reload a PLUS that adds either two registers, or
6234 a register and a constant or MEM, or a MEM and a constant. This can
6235 occur during frame pointer elimination and while reloading addresses.
6236 This case is handled by trying to emit a single insn
6237 to perform the add. If it is not valid, we use a two insn sequence.
6239 Finally, we could be called to handle an 'o' constraint by putting
6240 an address into a register. In that case, we first try to do this
6241 with a named pattern of "reload_load_address". If no such pattern
6242 exists, we just emit a SET insn and hope for the best (it will normally
6243 be valid on machines that use 'o').
6245 This entire process is made complex because reload will never
6246 process the insns we generate here and so we must ensure that
6247 they will fit their constraints and also by the fact that parts of
6248 IN might be being reloaded separately and replaced with spill registers.
6249 Because of this, we are, in some sense, just guessing the right approach
6250 here. The one listed above seems to work.
6252 ??? At some point, this whole thing needs to be rethought. */
6254 if (GET_CODE (in) == PLUS
6255 && ((GET_CODE (XEXP (in, 0)) == REG
6256 && (GET_CODE (XEXP (in, 1)) == REG
6257 || CONSTANT_P (XEXP (in, 1))
6258 || GET_CODE (XEXP (in, 1)) == MEM))
6259 || (GET_CODE (XEXP (in, 0)) == MEM
6260 && CONSTANT_P (XEXP (in, 1)))))
6262 /* We need to compute the sum of what is either a register and a
6263 constant, a register and memory, a hard register and a pseudo
6264 register, or memory and a constant and put it into the reload
6265 register. The best possible way of doing this is if the machine
6266 has a three-operand ADD insn that accepts the required operands.
6268 The simplest approach is to try to generate such an insn and see if it
6269 is recognized and matches its constraints. If so, it can be used.
6271 It might be better not to actually emit the insn unless it is valid,
6272 but we need to pass the insn as an operand to `recog' and
6273 `insn_extract' and it is simpler to emit and then delete the insn if
6274 not valid than to dummy things up. */
6276 rtx op0, op1, tem, insn;
6279 op0 = find_replacement (&XEXP (in, 0));
6280 op1 = find_replacement (&XEXP (in, 1));
6282 /* Since constraint checking is strict, commutativity won't be
6283 checked, so we need to do that here to avoid spurious failure
6284 if the add instruction is two-address and the second operand
6285 of the add is the same as the reload reg, which is frequently
6286 the case. If the insn would be A = B + A, rearrange it so
6287 it will be A = A + B as constrain_operands expects. */
6289 if (GET_CODE (XEXP (in, 1)) == REG
6290 && REGNO (reloadreg) == REGNO (XEXP (in, 1)))
6291 tem = op0, op0 = op1, op1 = tem;
6293 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
6294 in = gen_rtx (PLUS, GET_MODE (in), op0, op1);
6296 insn = emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6297 code = recog_memoized (insn);
6301 insn_extract (insn);
6302 /* We want constrain operands to treat this insn strictly in
6303 its validity determination, i.e., the way it would after reload
6305 if (constrain_operands (code, 1))
6309 delete_insns_since (last);
6311 /* If that failed, we must use a conservative two-insn sequence.
6312 use move to copy constant, MEM, or pseudo register to the reload
6313 register since "move" will be able to handle an arbitrary operand,
6314 unlike add which can't, in general. Then add the registers.
6316 If there is another way to do this for a specific machine, a
6317 DEFINE_PEEPHOLE should be specified that recognizes the sequence
6320 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM
6321 || (GET_CODE (op1) == REG
6322 && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
6323 tem = op0, op0 = op1, op1 = tem;
6325 emit_insn (gen_move_insn (reloadreg, op0));
6327 /* If OP0 and OP1 are the same, we can use RELOADREG for OP1.
6328 This fixes a problem on the 32K where the stack pointer cannot
6329 be used as an operand of an add insn. */
6331 if (rtx_equal_p (op0, op1))
6334 emit_insn (gen_add2_insn (reloadreg, op1));
6337 #ifdef SECONDARY_MEMORY_NEEDED
6338 /* If we need a memory location to do the move, do it that way. */
6339 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
6340 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
6341 REGNO_REG_CLASS (REGNO (reloadreg)),
6342 GET_MODE (reloadreg)))
6344 /* Get the memory to use and rewrite both registers to its mode. */
6345 rtx loc = get_secondary_mem (in, GET_MODE (reloadreg), opnum, type);
6347 if (GET_MODE (loc) != GET_MODE (reloadreg))
6348 reloadreg = gen_rtx (REG, GET_MODE (loc), REGNO (reloadreg));
6350 if (GET_MODE (loc) != GET_MODE (in))
6351 in = gen_rtx (REG, GET_MODE (loc), REGNO (in));
6353 emit_insn (gen_move_insn (loc, in));
6354 emit_insn (gen_move_insn (reloadreg, loc));
6358 /* If IN is a simple operand, use gen_move_insn. */
6359 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
6360 emit_insn (gen_move_insn (reloadreg, in));
6362 #ifdef HAVE_reload_load_address
6363 else if (HAVE_reload_load_address)
6364 emit_insn (gen_reload_load_address (reloadreg, in));
6367 /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
6369 emit_insn (gen_rtx (SET, VOIDmode, reloadreg, in));
6371 /* Return the first insn emitted.
6372 We can not just return get_last_insn, because there may have
6373 been multiple instructions emitted. Also note that gen_move_insn may
6374 emit more than one insn itself, so we can not assume that there is one
6375 insn emitted per emit_insn_before call. */
6377 return last ? NEXT_INSN (last) : get_insns ();
6380 /* Delete a previously made output-reload
6381 whose result we now believe is not needed.
6382 First we double-check.
6384 INSN is the insn now being processed.
6385 OUTPUT_RELOAD_INSN is the insn of the output reload.
6386 J is the reload-number for this insn. */
6389 delete_output_reload (insn, j, output_reload_insn)
6392 rtx output_reload_insn;
6396 /* Get the raw pseudo-register referred to. */
6398 rtx reg = reload_in[j];
6399 while (GET_CODE (reg) == SUBREG)
6400 reg = SUBREG_REG (reg);
6402 /* If the pseudo-reg we are reloading is no longer referenced
6403 anywhere between the store into it and here,
6404 and no jumps or labels intervene, then the value can get
6405 here through the reload reg alone.
6406 Otherwise, give up--return. */
6407 for (i1 = NEXT_INSN (output_reload_insn);
6408 i1 != insn; i1 = NEXT_INSN (i1))
6410 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
6412 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
6413 && reg_mentioned_p (reg, PATTERN (i1)))
6417 /* If this insn will store in the pseudo again,
6418 the previous store can be removed. */
6419 if (reload_out[j] == reload_in[j])
6420 delete_insn (output_reload_insn);
6422 /* See if the pseudo reg has been completely replaced
6423 with reload regs. If so, delete the store insn
6424 and forget we had a stack slot for the pseudo. */
6425 else if (reg_n_deaths[REGNO (reg)] == 1
6426 && reg_basic_block[REGNO (reg)] >= 0
6427 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
6431 /* We know that it was used only between here
6432 and the beginning of the current basic block.
6433 (We also know that the last use before INSN was
6434 the output reload we are thinking of deleting, but never mind that.)
6435 Search that range; see if any ref remains. */
6436 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6438 rtx set = single_set (i2);
6440 /* Uses which just store in the pseudo don't count,
6441 since if they are the only uses, they are dead. */
6442 if (set != 0 && SET_DEST (set) == reg)
6444 if (GET_CODE (i2) == CODE_LABEL
6445 || GET_CODE (i2) == JUMP_INSN)
6447 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
6448 && reg_mentioned_p (reg, PATTERN (i2)))
6449 /* Some other ref remains;
6450 we can't do anything. */
6454 /* Delete the now-dead stores into this pseudo. */
6455 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
6457 rtx set = single_set (i2);
6459 if (set != 0 && SET_DEST (set) == reg)
6461 if (GET_CODE (i2) == CODE_LABEL
6462 || GET_CODE (i2) == JUMP_INSN)
6466 /* For the debugging info,
6467 say the pseudo lives in this reload reg. */
6468 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
6469 alter_reg (REGNO (reg), -1);
6473 /* Output reload-insns to reload VALUE into RELOADREG.
6474 VALUE is an autoincrement or autodecrement RTX whose operand
6475 is a register or memory location;
6476 so reloading involves incrementing that location.
6478 INC_AMOUNT is the number to increment or decrement by (always positive).
6479 This cannot be deduced from VALUE. */
6482 inc_for_reload (reloadreg, value, inc_amount)
6487 /* REG or MEM to be copied and incremented. */
6488 rtx incloc = XEXP (value, 0);
6489 /* Nonzero if increment after copying. */
6490 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
6496 /* No hard register is equivalent to this register after
6497 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
6498 we could inc/dec that register as well (maybe even using it for
6499 the source), but I'm not sure it's worth worrying about. */
6500 if (GET_CODE (incloc) == REG)
6501 reg_last_reload_reg[REGNO (incloc)] = 0;
6503 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
6504 inc_amount = - inc_amount;
6506 inc = GEN_INT (inc_amount);
6508 /* If this is post-increment, first copy the location to the reload reg. */
6510 emit_insn (gen_move_insn (reloadreg, incloc));
6512 /* See if we can directly increment INCLOC. Use a method similar to that
6513 in gen_input_reload. */
6515 last = get_last_insn ();
6516 add_insn = emit_insn (gen_rtx (SET, VOIDmode, incloc,
6517 gen_rtx (PLUS, GET_MODE (incloc),
6520 code = recog_memoized (add_insn);
6523 insn_extract (add_insn);
6524 if (constrain_operands (code, 1))
6526 /* If this is a pre-increment and we have incremented the value
6527 where it lives, copy the incremented value to RELOADREG to
6528 be used as an address. */
6531 emit_insn (gen_move_insn (reloadreg, incloc));
6537 delete_insns_since (last);
6539 /* If couldn't do the increment directly, must increment in RELOADREG.
6540 The way we do this depends on whether this is pre- or post-increment.
6541 For pre-increment, copy INCLOC to the reload register, increment it
6542 there, then save back. */
6546 emit_insn (gen_move_insn (reloadreg, incloc));
6547 emit_insn (gen_add2_insn (reloadreg, inc));
6548 emit_insn (gen_move_insn (incloc, reloadreg));
6553 Because this might be a jump insn or a compare, and because RELOADREG
6554 may not be available after the insn in an input reload, we must do
6555 the incrementation before the insn being reloaded for.
6557 We have already copied INCLOC to RELOADREG. Increment the copy in
6558 RELOADREG, save that back, then decrement RELOADREG so it has
6559 the original value. */
6561 emit_insn (gen_add2_insn (reloadreg, inc));
6562 emit_insn (gen_move_insn (incloc, reloadreg));
6563 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
6569 /* Return 1 if we are certain that the constraint-string STRING allows
6570 the hard register REG. Return 0 if we can't be sure of this. */
6573 constraint_accepts_reg_p (string, reg)
6578 int regno = true_regnum (reg);
6581 /* Initialize for first alternative. */
6583 /* Check that each alternative contains `g' or `r'. */
6585 switch (c = *string++)
6588 /* If an alternative lacks `g' or `r', we lose. */
6591 /* If an alternative lacks `g' or `r', we lose. */
6594 /* Initialize for next alternative. */
6599 /* Any general reg wins for this alternative. */
6600 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
6604 /* Any reg in specified class wins for this alternative. */
6606 enum reg_class class = REG_CLASS_FROM_LETTER (c);
6608 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
6614 /* Return the number of places FIND appears within X, but don't count
6615 an occurrence if some SET_DEST is FIND. */
6618 count_occurrences (x, find)
6619 register rtx x, find;
6622 register enum rtx_code code;
6623 register char *format_ptr;
6631 code = GET_CODE (x);
6646 if (SET_DEST (x) == find)
6647 return count_occurrences (SET_SRC (x), find);
6651 format_ptr = GET_RTX_FORMAT (code);
6654 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6656 switch (*format_ptr++)
6659 count += count_occurrences (XEXP (x, i), find);
6663 if (XVEC (x, i) != NULL)
6665 for (j = 0; j < XVECLEN (x, i); j++)
6666 count += count_occurrences (XVECEXP (x, i, j), find);
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