1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 #ifndef REGISTER_MOVE_COST
83 #define REGISTER_MOVE_COST(m, x, y) 2
87 #define LOCAL_REGNO(REGNO) 0
90 /* During reload_as_needed, element N contains a REG rtx for the hard reg
91 into which reg N has been reloaded (perhaps for a previous insn). */
92 static rtx *reg_last_reload_reg;
94 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
95 for an output reload that stores into reg N. */
96 static char *reg_has_output_reload;
98 /* Indicates which hard regs are reload-registers for an output reload
99 in the current insn. */
100 static HARD_REG_SET reg_is_output_reload;
102 /* Element N is the constant value to which pseudo reg N is equivalent,
103 or zero if pseudo reg N is not equivalent to a constant.
104 find_reloads looks at this in order to replace pseudo reg N
105 with the constant it stands for. */
106 rtx *reg_equiv_constant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx *reg_equiv_address;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
128 static rtx *reg_equiv_init;
130 /* Vector to remember old contents of reg_renumber before spilling. */
131 static short *reg_old_renumber;
133 /* During reload_as_needed, element N contains the last pseudo regno reloaded
134 into hard register N. If that pseudo reg occupied more than one register,
135 reg_reloaded_contents points to that pseudo for each spill register in
136 use; all of these must remain set for an inheritance to occur. */
137 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
139 /* During reload_as_needed, element N contains the insn for which
140 hard register N was last used. Its contents are significant only
141 when reg_reloaded_valid is set for this register. */
142 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
144 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
145 static HARD_REG_SET reg_reloaded_valid;
146 /* Indicate if the register was dead at the end of the reload.
147 This is only valid if reg_reloaded_contents is set and valid. */
148 static HARD_REG_SET reg_reloaded_dead;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Nonzero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If nonzero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the difference of the
358 number of the label and the first label number. We can't offset the
359 pointer itself as this can cause problems on machines with segmented
360 memory. The first table is an array of flags that records whether we
361 have yet encountered a label and the second table is an array of arrays,
362 one entry in the latter array for each elimination. */
364 static int first_label_num;
365 static char *offsets_known_at;
366 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
368 /* Number of labels in the current function. */
370 static int num_labels;
372 static void replace_pseudos_in PARAMS ((rtx *, enum machine_mode, rtx));
373 static void maybe_fix_stack_asms PARAMS ((void));
374 static void copy_reloads PARAMS ((struct insn_chain *));
375 static void calculate_needs_all_insns PARAMS ((int));
376 static int find_reg PARAMS ((struct insn_chain *, int));
377 static void find_reload_regs PARAMS ((struct insn_chain *));
378 static void select_reload_regs PARAMS ((void));
379 static void delete_caller_save_insns PARAMS ((void));
381 static void spill_failure PARAMS ((rtx, enum reg_class));
382 static void count_spilled_pseudo PARAMS ((int, int, int));
383 static void delete_dead_insn PARAMS ((rtx));
384 static void alter_reg PARAMS ((int, int));
385 static void set_label_offsets PARAMS ((rtx, rtx, int));
386 static void check_eliminable_occurrences PARAMS ((rtx));
387 static void elimination_effects PARAMS ((rtx, enum machine_mode));
388 static int eliminate_regs_in_insn PARAMS ((rtx, int));
389 static void update_eliminable_offsets PARAMS ((void));
390 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
391 static void set_initial_elim_offsets PARAMS ((void));
392 static void verify_initial_elim_offsets PARAMS ((void));
393 static void set_initial_label_offsets PARAMS ((void));
394 static void set_offsets_for_label PARAMS ((rtx));
395 static void init_elim_table PARAMS ((void));
396 static void update_eliminables PARAMS ((HARD_REG_SET *));
397 static void spill_hard_reg PARAMS ((unsigned int, int));
398 static int finish_spills PARAMS ((int));
399 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
400 static void scan_paradoxical_subregs PARAMS ((rtx));
401 static void count_pseudo PARAMS ((int));
402 static void order_regs_for_reload PARAMS ((struct insn_chain *));
403 static void reload_as_needed PARAMS ((int));
404 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
405 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
406 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
409 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
412 static int reload_reg_free_p PARAMS ((unsigned int, int,
414 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
416 rtx, rtx, int, int));
417 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
418 enum reload_type, rtx, rtx,
420 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
422 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
424 static int conflicts_with_override PARAMS ((rtx));
425 static void failed_reload PARAMS ((rtx, int));
426 static int set_reload_reg PARAMS ((int, int));
427 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
428 static void choose_reload_regs PARAMS ((struct insn_chain *));
429 static void merge_assigned_reloads PARAMS ((rtx));
430 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
431 struct reload *, rtx, int));
432 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
433 struct reload *, int));
434 static void do_input_reload PARAMS ((struct insn_chain *,
435 struct reload *, int));
436 static void do_output_reload PARAMS ((struct insn_chain *,
437 struct reload *, int));
438 static void emit_reload_insns PARAMS ((struct insn_chain *));
439 static void delete_output_reload PARAMS ((rtx, int, int));
440 static void delete_address_reloads PARAMS ((rtx, rtx));
441 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
442 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
443 static void reload_cse_regs_1 PARAMS ((rtx));
444 static int reload_cse_noop_set_p PARAMS ((rtx));
445 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
446 static int reload_cse_simplify_operands PARAMS ((rtx, rtx));
447 static void reload_combine PARAMS ((void));
448 static void reload_combine_note_use PARAMS ((rtx *, rtx));
449 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
450 static void reload_cse_move2add PARAMS ((rtx));
451 static void move2add_note_store PARAMS ((rtx, rtx, void *));
453 static void add_auto_inc_notes PARAMS ((rtx, rtx));
455 static void copy_eh_notes PARAMS ((rtx, rtx));
456 static void failed_reload PARAMS ((rtx, int));
457 static int set_reload_reg PARAMS ((int, int));
458 static void reload_cse_simplify PARAMS ((rtx, rtx));
459 void fixup_abnormal_edges PARAMS ((void));
460 extern void dump_needs PARAMS ((struct insn_chain *));
462 /* Initialize the reload pass once per compilation. */
469 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
470 Set spill_indirect_levels to the number of levels such addressing is
471 permitted, zero if it is not permitted at all. */
474 = gen_rtx_MEM (Pmode,
477 LAST_VIRTUAL_REGISTER + 1),
479 spill_indirect_levels = 0;
481 while (memory_address_p (QImode, tem))
483 spill_indirect_levels++;
484 tem = gen_rtx_MEM (Pmode, tem);
487 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
489 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
490 indirect_symref_ok = memory_address_p (QImode, tem);
492 /* See if reg+reg is a valid (and offsettable) address. */
494 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
496 tem = gen_rtx_PLUS (Pmode,
497 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
498 gen_rtx_REG (Pmode, i));
500 /* This way, we make sure that reg+reg is an offsettable address. */
501 tem = plus_constant (tem, 4);
503 if (memory_address_p (QImode, tem))
505 double_reg_address_ok = 1;
510 /* Initialize obstack for our rtl allocation. */
511 gcc_obstack_init (&reload_obstack);
512 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
514 INIT_REG_SET (&spilled_pseudos);
515 INIT_REG_SET (&pseudos_counted);
518 /* List of insn chains that are currently unused. */
519 static struct insn_chain *unused_insn_chains = 0;
521 /* Allocate an empty insn_chain structure. */
525 struct insn_chain *c;
527 if (unused_insn_chains == 0)
529 c = (struct insn_chain *)
530 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
531 INIT_REG_SET (&c->live_throughout);
532 INIT_REG_SET (&c->dead_or_set);
536 c = unused_insn_chains;
537 unused_insn_chains = c->next;
539 c->is_caller_save_insn = 0;
540 c->need_operand_change = 0;
546 /* Small utility function to set all regs in hard reg set TO which are
547 allocated to pseudos in regset FROM. */
550 compute_use_by_pseudos (to, from)
556 EXECUTE_IF_SET_IN_REG_SET
557 (from, FIRST_PSEUDO_REGISTER, regno,
559 int r = reg_renumber[regno];
564 /* reload_combine uses the information from
565 BASIC_BLOCK->global_live_at_start, which might still
566 contain registers that have not actually been allocated
567 since they have an equivalence. */
568 if (! reload_completed)
573 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
575 SET_HARD_REG_BIT (*to, r + nregs);
580 /* Replace all pseudos found in LOC with their corresponding
584 replace_pseudos_in (loc, mem_mode, usage)
586 enum machine_mode mem_mode;
600 unsigned int regno = REGNO (x);
602 if (regno < FIRST_PSEUDO_REGISTER)
605 x = eliminate_regs (x, mem_mode, usage);
609 replace_pseudos_in (loc, mem_mode, usage);
613 if (reg_equiv_constant[regno])
614 *loc = reg_equiv_constant[regno];
615 else if (reg_equiv_mem[regno])
616 *loc = reg_equiv_mem[regno];
617 else if (reg_equiv_address[regno])
618 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
619 else if (GET_CODE (regno_reg_rtx[regno]) != REG
620 || REGNO (regno_reg_rtx[regno]) != regno)
621 *loc = regno_reg_rtx[regno];
627 else if (code == MEM)
629 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
633 /* Process each of our operands recursively. */
634 fmt = GET_RTX_FORMAT (code);
635 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
637 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
638 else if (*fmt == 'E')
639 for (j = 0; j < XVECLEN (x, i); j++)
640 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
644 /* Global variables used by reload and its subroutines. */
646 /* Set during calculate_needs if an insn needs register elimination. */
647 static int something_needs_elimination;
648 /* Set during calculate_needs if an insn needs an operand changed. */
649 int something_needs_operands_changed;
651 /* Nonzero means we couldn't get enough spill regs. */
654 /* Main entry point for the reload pass.
656 FIRST is the first insn of the function being compiled.
658 GLOBAL nonzero means we were called from global_alloc
659 and should attempt to reallocate any pseudoregs that we
660 displace from hard regs we will use for reloads.
661 If GLOBAL is zero, we do not have enough information to do that,
662 so any pseudo reg that is spilled must go to the stack.
664 Return value is nonzero if reload failed
665 and we must not do any more for this function. */
668 reload (first, global)
674 struct elim_table *ep;
677 /* Make sure even insns with volatile mem refs are recognizable. */
682 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
684 /* Make sure that the last insn in the chain
685 is not something that needs reloading. */
686 emit_note (NULL, NOTE_INSN_DELETED);
688 /* Enable find_equiv_reg to distinguish insns made by reload. */
689 reload_first_uid = get_max_uid ();
691 #ifdef SECONDARY_MEMORY_NEEDED
692 /* Initialize the secondary memory table. */
693 clear_secondary_mem ();
696 /* We don't have a stack slot for any spill reg yet. */
697 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
698 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
700 /* Initialize the save area information for caller-save, in case some
704 /* Compute which hard registers are now in use
705 as homes for pseudo registers.
706 This is done here rather than (eg) in global_alloc
707 because this point is reached even if not optimizing. */
708 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
711 /* A function that receives a nonlocal goto must save all call-saved
713 if (current_function_has_nonlocal_label)
714 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
715 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
716 regs_ever_live[i] = 1;
718 /* Find all the pseudo registers that didn't get hard regs
719 but do have known equivalent constants or memory slots.
720 These include parameters (known equivalent to parameter slots)
721 and cse'd or loop-moved constant memory addresses.
723 Record constant equivalents in reg_equiv_constant
724 so they will be substituted by find_reloads.
725 Record memory equivalents in reg_mem_equiv so they can
726 be substituted eventually by altering the REG-rtx's. */
728 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
729 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
730 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
731 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
732 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
733 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
734 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
735 pseudo_forbidden_regs
736 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
738 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
740 CLEAR_HARD_REG_SET (bad_spill_regs_global);
742 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
743 Also find all paradoxical subregs and find largest such for each pseudo.
744 On machines with small register classes, record hard registers that
745 are used for user variables. These can never be used for spills.
746 Also look for a "constant" REG_SETJMP. This means that all
747 caller-saved registers must be marked live. */
749 num_eliminable_invariants = 0;
750 for (insn = first; insn; insn = NEXT_INSN (insn))
752 rtx set = single_set (insn);
754 /* We may introduce USEs that we want to remove at the end, so
755 we'll mark them with QImode. Make sure there are no
756 previously-marked insns left by say regmove. */
757 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
758 && GET_MODE (insn) != VOIDmode)
759 PUT_MODE (insn, VOIDmode);
761 if (GET_CODE (insn) == CALL_INSN
762 && find_reg_note (insn, REG_SETJMP, NULL))
763 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
764 if (! call_used_regs[i])
765 regs_ever_live[i] = 1;
767 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
769 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
771 #ifdef LEGITIMATE_PIC_OPERAND_P
772 && (! function_invariant_p (XEXP (note, 0))
774 /* A function invariant is often CONSTANT_P but may
775 include a register. We promise to only pass
776 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
777 || (CONSTANT_P (XEXP (note, 0))
778 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
782 rtx x = XEXP (note, 0);
783 i = REGNO (SET_DEST (set));
784 if (i > LAST_VIRTUAL_REGISTER)
786 /* It can happen that a REG_EQUIV note contains a MEM
787 that is not a legitimate memory operand. As later
788 stages of reload assume that all addresses found
789 in the reg_equiv_* arrays were originally legitimate,
790 we ignore such REG_EQUIV notes. */
791 if (memory_operand (x, VOIDmode))
793 /* Always unshare the equivalence, so we can
794 substitute into this insn without touching the
796 reg_equiv_memory_loc[i] = copy_rtx (x);
798 else if (function_invariant_p (x))
800 if (GET_CODE (x) == PLUS)
802 /* This is PLUS of frame pointer and a constant,
803 and might be shared. Unshare it. */
804 reg_equiv_constant[i] = copy_rtx (x);
805 num_eliminable_invariants++;
807 else if (x == frame_pointer_rtx
808 || x == arg_pointer_rtx)
810 reg_equiv_constant[i] = x;
811 num_eliminable_invariants++;
813 else if (LEGITIMATE_CONSTANT_P (x))
814 reg_equiv_constant[i] = x;
817 reg_equiv_memory_loc[i]
818 = force_const_mem (GET_MODE (SET_DEST (set)), x);
819 if (!reg_equiv_memory_loc[i])
826 /* If this register is being made equivalent to a MEM
827 and the MEM is not SET_SRC, the equivalencing insn
828 is one with the MEM as a SET_DEST and it occurs later.
829 So don't mark this insn now. */
830 if (GET_CODE (x) != MEM
831 || rtx_equal_p (SET_SRC (set), x))
833 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
838 /* If this insn is setting a MEM from a register equivalent to it,
839 this is the equivalencing insn. */
840 else if (set && GET_CODE (SET_DEST (set)) == MEM
841 && GET_CODE (SET_SRC (set)) == REG
842 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
843 && rtx_equal_p (SET_DEST (set),
844 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
845 reg_equiv_init[REGNO (SET_SRC (set))]
846 = gen_rtx_INSN_LIST (VOIDmode, insn,
847 reg_equiv_init[REGNO (SET_SRC (set))]);
850 scan_paradoxical_subregs (PATTERN (insn));
855 first_label_num = get_first_label_num ();
856 num_labels = max_label_num () - first_label_num;
858 /* Allocate the tables used to store offset information at labels. */
859 /* We used to use alloca here, but the size of what it would try to
860 allocate would occasionally cause it to exceed the stack limit and
861 cause a core dump. */
862 offsets_known_at = xmalloc (num_labels);
864 = (int (*)[NUM_ELIMINABLE_REGS])
865 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
867 /* Alter each pseudo-reg rtx to contain its hard reg number.
868 Assign stack slots to the pseudos that lack hard regs or equivalents.
869 Do not touch virtual registers. */
871 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
874 /* If we have some registers we think can be eliminated, scan all insns to
875 see if there is an insn that sets one of these registers to something
876 other than itself plus a constant. If so, the register cannot be
877 eliminated. Doing this scan here eliminates an extra pass through the
878 main reload loop in the most common case where register elimination
880 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
881 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
882 || GET_CODE (insn) == CALL_INSN)
883 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
885 maybe_fix_stack_asms ();
887 insns_need_reload = 0;
888 something_needs_elimination = 0;
890 /* Initialize to -1, which means take the first spill register. */
893 /* Spill any hard regs that we know we can't eliminate. */
894 CLEAR_HARD_REG_SET (used_spill_regs);
895 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
896 if (! ep->can_eliminate)
897 spill_hard_reg (ep->from, 1);
899 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
900 if (frame_pointer_needed)
901 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
903 finish_spills (global);
905 /* From now on, we may need to generate moves differently. We may also
906 allow modifications of insns which cause them to not be recognized.
907 Any such modifications will be cleaned up during reload itself. */
908 reload_in_progress = 1;
910 /* This loop scans the entire function each go-round
911 and repeats until one repetition spills no additional hard regs. */
914 int something_changed;
917 HOST_WIDE_INT starting_frame_size;
919 /* Round size of stack frame to stack_alignment_needed. This must be done
920 here because the stack size may be a part of the offset computation
921 for register elimination, and there might have been new stack slots
922 created in the last iteration of this loop. */
923 if (cfun->stack_alignment_needed)
924 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
926 starting_frame_size = get_frame_size ();
928 set_initial_elim_offsets ();
929 set_initial_label_offsets ();
931 /* For each pseudo register that has an equivalent location defined,
932 try to eliminate any eliminable registers (such as the frame pointer)
933 assuming initial offsets for the replacement register, which
936 If the resulting location is directly addressable, substitute
937 the MEM we just got directly for the old REG.
939 If it is not addressable but is a constant or the sum of a hard reg
940 and constant, it is probably not addressable because the constant is
941 out of range, in that case record the address; we will generate
942 hairy code to compute the address in a register each time it is
943 needed. Similarly if it is a hard register, but one that is not
944 valid as an address register.
946 If the location is not addressable, but does not have one of the
947 above forms, assign a stack slot. We have to do this to avoid the
948 potential of producing lots of reloads if, e.g., a location involves
949 a pseudo that didn't get a hard register and has an equivalent memory
950 location that also involves a pseudo that didn't get a hard register.
952 Perhaps at some point we will improve reload_when_needed handling
953 so this problem goes away. But that's very hairy. */
955 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
956 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
958 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
960 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
962 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
963 else if (CONSTANT_P (XEXP (x, 0))
964 || (GET_CODE (XEXP (x, 0)) == REG
965 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
966 || (GET_CODE (XEXP (x, 0)) == PLUS
967 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
968 && (REGNO (XEXP (XEXP (x, 0), 0))
969 < FIRST_PSEUDO_REGISTER)
970 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
971 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
974 /* Make a new stack slot. Then indicate that something
975 changed so we go back and recompute offsets for
976 eliminable registers because the allocation of memory
977 below might change some offset. reg_equiv_{mem,address}
978 will be set up for this pseudo on the next pass around
980 reg_equiv_memory_loc[i] = 0;
981 reg_equiv_init[i] = 0;
986 if (caller_save_needed)
989 /* If we allocated another stack slot, redo elimination bookkeeping. */
990 if (starting_frame_size != get_frame_size ())
993 if (caller_save_needed)
995 save_call_clobbered_regs ();
996 /* That might have allocated new insn_chain structures. */
997 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1000 calculate_needs_all_insns (global);
1002 CLEAR_REG_SET (&spilled_pseudos);
1005 something_changed = 0;
1007 /* If we allocated any new memory locations, make another pass
1008 since it might have changed elimination offsets. */
1009 if (starting_frame_size != get_frame_size ())
1010 something_changed = 1;
1013 HARD_REG_SET to_spill;
1014 CLEAR_HARD_REG_SET (to_spill);
1015 update_eliminables (&to_spill);
1016 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1017 if (TEST_HARD_REG_BIT (to_spill, i))
1019 spill_hard_reg (i, 1);
1022 /* Regardless of the state of spills, if we previously had
1023 a register that we thought we could eliminate, but now can
1024 not eliminate, we must run another pass.
1026 Consider pseudos which have an entry in reg_equiv_* which
1027 reference an eliminable register. We must make another pass
1028 to update reg_equiv_* so that we do not substitute in the
1029 old value from when we thought the elimination could be
1031 something_changed = 1;
1035 select_reload_regs ();
1039 if (insns_need_reload != 0 || did_spill)
1040 something_changed |= finish_spills (global);
1042 if (! something_changed)
1045 if (caller_save_needed)
1046 delete_caller_save_insns ();
1048 obstack_free (&reload_obstack, reload_firstobj);
1051 /* If global-alloc was run, notify it of any register eliminations we have
1054 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1055 if (ep->can_eliminate)
1056 mark_elimination (ep->from, ep->to);
1058 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1059 If that insn didn't set the register (i.e., it copied the register to
1060 memory), just delete that insn instead of the equivalencing insn plus
1061 anything now dead. If we call delete_dead_insn on that insn, we may
1062 delete the insn that actually sets the register if the register dies
1063 there and that is incorrect. */
1065 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1067 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1070 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1072 rtx equiv_insn = XEXP (list, 0);
1074 /* If we already deleted the insn or if it may trap, we can't
1075 delete it. The latter case shouldn't happen, but can
1076 if an insn has a variable address, gets a REG_EH_REGION
1077 note added to it, and then gets converted into an load
1078 from a constant address. */
1079 if (GET_CODE (equiv_insn) == NOTE
1080 || can_throw_internal (equiv_insn))
1082 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1083 delete_dead_insn (equiv_insn);
1086 PUT_CODE (equiv_insn, NOTE);
1087 NOTE_SOURCE_FILE (equiv_insn) = 0;
1088 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1094 /* Use the reload registers where necessary
1095 by generating move instructions to move the must-be-register
1096 values into or out of the reload registers. */
1098 if (insns_need_reload != 0 || something_needs_elimination
1099 || something_needs_operands_changed)
1101 HOST_WIDE_INT old_frame_size = get_frame_size ();
1103 reload_as_needed (global);
1105 if (old_frame_size != get_frame_size ())
1109 verify_initial_elim_offsets ();
1112 /* If we were able to eliminate the frame pointer, show that it is no
1113 longer live at the start of any basic block. If it ls live by
1114 virtue of being in a pseudo, that pseudo will be marked live
1115 and hence the frame pointer will be known to be live via that
1118 if (! frame_pointer_needed)
1120 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1121 HARD_FRAME_POINTER_REGNUM);
1123 /* Come here (with failure set nonzero) if we can't get enough spill regs
1124 and we decide not to abort about it. */
1127 CLEAR_REG_SET (&spilled_pseudos);
1128 reload_in_progress = 0;
1130 /* Now eliminate all pseudo regs by modifying them into
1131 their equivalent memory references.
1132 The REG-rtx's for the pseudos are modified in place,
1133 so all insns that used to refer to them now refer to memory.
1135 For a reg that has a reg_equiv_address, all those insns
1136 were changed by reloading so that no insns refer to it any longer;
1137 but the DECL_RTL of a variable decl may refer to it,
1138 and if so this causes the debugging info to mention the variable. */
1140 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1144 if (reg_equiv_mem[i])
1145 addr = XEXP (reg_equiv_mem[i], 0);
1147 if (reg_equiv_address[i])
1148 addr = reg_equiv_address[i];
1152 if (reg_renumber[i] < 0)
1154 rtx reg = regno_reg_rtx[i];
1156 REG_USERVAR_P (reg) = 0;
1157 PUT_CODE (reg, MEM);
1158 XEXP (reg, 0) = addr;
1159 if (reg_equiv_memory_loc[i])
1160 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1163 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1164 = MEM_SCALAR_P (reg) = 0;
1165 MEM_ATTRS (reg) = 0;
1168 else if (reg_equiv_mem[i])
1169 XEXP (reg_equiv_mem[i], 0) = addr;
1173 /* We must set reload_completed now since the cleanup_subreg_operands call
1174 below will re-recognize each insn and reload may have generated insns
1175 which are only valid during and after reload. */
1176 reload_completed = 1;
1178 /* Make a pass over all the insns and delete all USEs which we inserted
1179 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1180 notes. Delete all CLOBBER insns, except those that refer to the return
1181 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1182 from misarranging variable-array code, and simplify (subreg (reg))
1183 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1184 are no longer useful or accurate. Strip and regenerate REG_INC notes
1185 that may have been moved around. */
1187 for (insn = first; insn; insn = NEXT_INSN (insn))
1192 if (GET_CODE (insn) == CALL_INSN)
1193 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1194 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1196 if ((GET_CODE (PATTERN (insn)) == USE
1197 /* We mark with QImode USEs introduced by reload itself. */
1198 && (GET_MODE (insn) == QImode
1199 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1200 || (GET_CODE (PATTERN (insn)) == CLOBBER
1201 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1202 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1203 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1204 && XEXP (XEXP (PATTERN (insn), 0), 0)
1205 != stack_pointer_rtx))
1206 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1207 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1213 /* Some CLOBBERs may survive until here and still reference unassigned
1214 pseudos with const equivalent, which may in turn cause ICE in later
1215 passes if the reference remains in place. */
1216 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1217 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1218 VOIDmode, PATTERN (insn));
1220 pnote = ®_NOTES (insn);
1223 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1224 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1225 || REG_NOTE_KIND (*pnote) == REG_INC
1226 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1227 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1228 *pnote = XEXP (*pnote, 1);
1230 pnote = &XEXP (*pnote, 1);
1234 add_auto_inc_notes (insn, PATTERN (insn));
1237 /* And simplify (subreg (reg)) if it appears as an operand. */
1238 cleanup_subreg_operands (insn);
1241 /* If we are doing stack checking, give a warning if this function's
1242 frame size is larger than we expect. */
1243 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1245 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1246 static int verbose_warned = 0;
1248 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1249 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1250 size += UNITS_PER_WORD;
1252 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1254 warning ("frame size too large for reliable stack checking");
1255 if (! verbose_warned)
1257 warning ("try reducing the number of local variables");
1263 /* Indicate that we no longer have known memory locations or constants. */
1264 if (reg_equiv_constant)
1265 free (reg_equiv_constant);
1266 reg_equiv_constant = 0;
1267 if (reg_equiv_memory_loc)
1268 free (reg_equiv_memory_loc);
1269 reg_equiv_memory_loc = 0;
1271 if (offsets_known_at)
1272 free (offsets_known_at);
1276 free (reg_equiv_mem);
1277 free (reg_equiv_init);
1278 free (reg_equiv_address);
1279 free (reg_max_ref_width);
1280 free (reg_old_renumber);
1281 free (pseudo_previous_regs);
1282 free (pseudo_forbidden_regs);
1284 CLEAR_HARD_REG_SET (used_spill_regs);
1285 for (i = 0; i < n_spills; i++)
1286 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1288 /* Free all the insn_chain structures at once. */
1289 obstack_free (&reload_obstack, reload_startobj);
1290 unused_insn_chains = 0;
1291 fixup_abnormal_edges ();
1293 /* Replacing pseudos with their memory equivalents might have
1294 created shared rtx. Subsequent passes would get confused
1295 by this, so unshare everything here. */
1296 unshare_all_rtl_again (first);
1301 /* Yet another special case. Unfortunately, reg-stack forces people to
1302 write incorrect clobbers in asm statements. These clobbers must not
1303 cause the register to appear in bad_spill_regs, otherwise we'll call
1304 fatal_insn later. We clear the corresponding regnos in the live
1305 register sets to avoid this.
1306 The whole thing is rather sick, I'm afraid. */
1309 maybe_fix_stack_asms ()
1312 const char *constraints[MAX_RECOG_OPERANDS];
1313 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1314 struct insn_chain *chain;
1316 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1319 HARD_REG_SET clobbered, allowed;
1322 if (! INSN_P (chain->insn)
1323 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1325 pat = PATTERN (chain->insn);
1326 if (GET_CODE (pat) != PARALLEL)
1329 CLEAR_HARD_REG_SET (clobbered);
1330 CLEAR_HARD_REG_SET (allowed);
1332 /* First, make a mask of all stack regs that are clobbered. */
1333 for (i = 0; i < XVECLEN (pat, 0); i++)
1335 rtx t = XVECEXP (pat, 0, i);
1336 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1337 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1340 /* Get the operand values and constraints out of the insn. */
1341 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1342 constraints, operand_mode);
1344 /* For every operand, see what registers are allowed. */
1345 for (i = 0; i < noperands; i++)
1347 const char *p = constraints[i];
1348 /* For every alternative, we compute the class of registers allowed
1349 for reloading in CLS, and merge its contents into the reg set
1351 int cls = (int) NO_REGS;
1357 if (c == '\0' || c == ',' || c == '#')
1359 /* End of one alternative - mark the regs in the current
1360 class, and reset the class. */
1361 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1367 } while (c != '\0' && c != ',');
1375 case '=': case '+': case '*': case '%': case '?': case '!':
1376 case '0': case '1': case '2': case '3': case '4': case 'm':
1377 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1378 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1379 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1384 cls = (int) reg_class_subunion[cls]
1385 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1390 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1394 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1395 cls = (int) reg_class_subunion[cls]
1396 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1398 cls = (int) reg_class_subunion[cls]
1399 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1401 p += CONSTRAINT_LEN (c, p);
1404 /* Those of the registers which are clobbered, but allowed by the
1405 constraints, must be usable as reload registers. So clear them
1406 out of the life information. */
1407 AND_HARD_REG_SET (allowed, clobbered);
1408 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1409 if (TEST_HARD_REG_BIT (allowed, i))
1411 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1412 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1419 /* Copy the global variables n_reloads and rld into the corresponding elts
1422 copy_reloads (chain)
1423 struct insn_chain *chain;
1425 chain->n_reloads = n_reloads;
1427 = (struct reload *) obstack_alloc (&reload_obstack,
1428 n_reloads * sizeof (struct reload));
1429 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1430 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1433 /* Walk the chain of insns, and determine for each whether it needs reloads
1434 and/or eliminations. Build the corresponding insns_need_reload list, and
1435 set something_needs_elimination as appropriate. */
1437 calculate_needs_all_insns (global)
1440 struct insn_chain **pprev_reload = &insns_need_reload;
1441 struct insn_chain *chain, *next = 0;
1443 something_needs_elimination = 0;
1445 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1446 for (chain = reload_insn_chain; chain != 0; chain = next)
1448 rtx insn = chain->insn;
1452 /* Clear out the shortcuts. */
1453 chain->n_reloads = 0;
1454 chain->need_elim = 0;
1455 chain->need_reload = 0;
1456 chain->need_operand_change = 0;
1458 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1459 include REG_LABEL), we need to see what effects this has on the
1460 known offsets at labels. */
1462 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1463 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1464 set_label_offsets (insn, insn, 0);
1468 rtx old_body = PATTERN (insn);
1469 int old_code = INSN_CODE (insn);
1470 rtx old_notes = REG_NOTES (insn);
1471 int did_elimination = 0;
1472 int operands_changed = 0;
1473 rtx set = single_set (insn);
1475 /* Skip insns that only set an equivalence. */
1476 if (set && GET_CODE (SET_DEST (set)) == REG
1477 && reg_renumber[REGNO (SET_DEST (set))] < 0
1478 && reg_equiv_constant[REGNO (SET_DEST (set))])
1481 /* If needed, eliminate any eliminable registers. */
1482 if (num_eliminable || num_eliminable_invariants)
1483 did_elimination = eliminate_regs_in_insn (insn, 0);
1485 /* Analyze the instruction. */
1486 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1487 global, spill_reg_order);
1489 /* If a no-op set needs more than one reload, this is likely
1490 to be something that needs input address reloads. We
1491 can't get rid of this cleanly later, and it is of no use
1492 anyway, so discard it now.
1493 We only do this when expensive_optimizations is enabled,
1494 since this complements reload inheritance / output
1495 reload deletion, and it can make debugging harder. */
1496 if (flag_expensive_optimizations && n_reloads > 1)
1498 rtx set = single_set (insn);
1500 && SET_SRC (set) == SET_DEST (set)
1501 && GET_CODE (SET_SRC (set)) == REG
1502 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1505 /* Delete it from the reload chain. */
1507 chain->prev->next = next;
1509 reload_insn_chain = next;
1511 next->prev = chain->prev;
1512 chain->next = unused_insn_chains;
1513 unused_insn_chains = chain;
1518 update_eliminable_offsets ();
1520 /* Remember for later shortcuts which insns had any reloads or
1521 register eliminations. */
1522 chain->need_elim = did_elimination;
1523 chain->need_reload = n_reloads > 0;
1524 chain->need_operand_change = operands_changed;
1526 /* Discard any register replacements done. */
1527 if (did_elimination)
1529 obstack_free (&reload_obstack, reload_insn_firstobj);
1530 PATTERN (insn) = old_body;
1531 INSN_CODE (insn) = old_code;
1532 REG_NOTES (insn) = old_notes;
1533 something_needs_elimination = 1;
1536 something_needs_operands_changed |= operands_changed;
1540 copy_reloads (chain);
1541 *pprev_reload = chain;
1542 pprev_reload = &chain->next_need_reload;
1549 /* Comparison function for qsort to decide which of two reloads
1550 should be handled first. *P1 and *P2 are the reload numbers. */
1553 reload_reg_class_lower (r1p, r2p)
1557 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1560 /* Consider required reloads before optional ones. */
1561 t = rld[r1].optional - rld[r2].optional;
1565 /* Count all solitary classes before non-solitary ones. */
1566 t = ((reg_class_size[(int) rld[r2].class] == 1)
1567 - (reg_class_size[(int) rld[r1].class] == 1));
1571 /* Aside from solitaires, consider all multi-reg groups first. */
1572 t = rld[r2].nregs - rld[r1].nregs;
1576 /* Consider reloads in order of increasing reg-class number. */
1577 t = (int) rld[r1].class - (int) rld[r2].class;
1581 /* If reloads are equally urgent, sort by reload number,
1582 so that the results of qsort leave nothing to chance. */
1586 /* The cost of spilling each hard reg. */
1587 static int spill_cost[FIRST_PSEUDO_REGISTER];
1589 /* When spilling multiple hard registers, we use SPILL_COST for the first
1590 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1591 only the first hard reg for a multi-reg pseudo. */
1592 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1594 /* Update the spill cost arrays, considering that pseudo REG is live. */
1600 int freq = REG_FREQ (reg);
1601 int r = reg_renumber[reg];
1604 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1605 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1608 SET_REGNO_REG_SET (&pseudos_counted, reg);
1613 spill_add_cost[r] += freq;
1615 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1617 spill_cost[r + nregs] += freq;
1620 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1621 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1624 order_regs_for_reload (chain)
1625 struct insn_chain *chain;
1628 HARD_REG_SET used_by_pseudos;
1629 HARD_REG_SET used_by_pseudos2;
1631 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1633 memset (spill_cost, 0, sizeof spill_cost);
1634 memset (spill_add_cost, 0, sizeof spill_add_cost);
1636 /* Count number of uses of each hard reg by pseudo regs allocated to it
1637 and then order them by decreasing use. First exclude hard registers
1638 that are live in or across this insn. */
1640 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1641 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1642 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1643 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1645 /* Now find out which pseudos are allocated to it, and update
1647 CLEAR_REG_SET (&pseudos_counted);
1649 EXECUTE_IF_SET_IN_REG_SET
1650 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1654 EXECUTE_IF_SET_IN_REG_SET
1655 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1659 CLEAR_REG_SET (&pseudos_counted);
1662 /* Vector of reload-numbers showing the order in which the reloads should
1664 static short reload_order[MAX_RELOADS];
1666 /* This is used to keep track of the spill regs used in one insn. */
1667 static HARD_REG_SET used_spill_regs_local;
1669 /* We decided to spill hard register SPILLED, which has a size of
1670 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1671 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1672 update SPILL_COST/SPILL_ADD_COST. */
1675 count_spilled_pseudo (spilled, spilled_nregs, reg)
1676 int spilled, spilled_nregs, reg;
1678 int r = reg_renumber[reg];
1679 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1681 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1682 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1685 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1687 spill_add_cost[r] -= REG_FREQ (reg);
1689 spill_cost[r + nregs] -= REG_FREQ (reg);
1692 /* Find reload register to use for reload number ORDER. */
1695 find_reg (chain, order)
1696 struct insn_chain *chain;
1699 int rnum = reload_order[order];
1700 struct reload *rl = rld + rnum;
1701 int best_cost = INT_MAX;
1705 HARD_REG_SET not_usable;
1706 HARD_REG_SET used_by_other_reload;
1708 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1709 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1710 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1712 CLEAR_HARD_REG_SET (used_by_other_reload);
1713 for (k = 0; k < order; k++)
1715 int other = reload_order[k];
1717 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1718 for (j = 0; j < rld[other].nregs; j++)
1719 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1722 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1724 unsigned int regno = i;
1726 if (! TEST_HARD_REG_BIT (not_usable, regno)
1727 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1728 && HARD_REGNO_MODE_OK (regno, rl->mode))
1730 int this_cost = spill_cost[regno];
1732 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1734 for (j = 1; j < this_nregs; j++)
1736 this_cost += spill_add_cost[regno + j];
1737 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1738 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1743 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1745 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1747 if (this_cost < best_cost
1748 /* Among registers with equal cost, prefer caller-saved ones, or
1749 use REG_ALLOC_ORDER if it is defined. */
1750 || (this_cost == best_cost
1751 #ifdef REG_ALLOC_ORDER
1752 && (inv_reg_alloc_order[regno]
1753 < inv_reg_alloc_order[best_reg])
1755 && call_used_regs[regno]
1756 && ! call_used_regs[best_reg]
1761 best_cost = this_cost;
1769 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1771 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1772 rl->regno = best_reg;
1774 EXECUTE_IF_SET_IN_REG_SET
1775 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1777 count_spilled_pseudo (best_reg, rl->nregs, j);
1780 EXECUTE_IF_SET_IN_REG_SET
1781 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1783 count_spilled_pseudo (best_reg, rl->nregs, j);
1786 for (i = 0; i < rl->nregs; i++)
1788 if (spill_cost[best_reg + i] != 0
1789 || spill_add_cost[best_reg + i] != 0)
1791 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1796 /* Find more reload regs to satisfy the remaining need of an insn, which
1798 Do it by ascending class number, since otherwise a reg
1799 might be spilled for a big class and might fail to count
1800 for a smaller class even though it belongs to that class. */
1803 find_reload_regs (chain)
1804 struct insn_chain *chain;
1808 /* In order to be certain of getting the registers we need,
1809 we must sort the reloads into order of increasing register class.
1810 Then our grabbing of reload registers will parallel the process
1811 that provided the reload registers. */
1812 for (i = 0; i < chain->n_reloads; i++)
1814 /* Show whether this reload already has a hard reg. */
1815 if (chain->rld[i].reg_rtx)
1817 int regno = REGNO (chain->rld[i].reg_rtx);
1818 chain->rld[i].regno = regno;
1820 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1823 chain->rld[i].regno = -1;
1824 reload_order[i] = i;
1827 n_reloads = chain->n_reloads;
1828 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1830 CLEAR_HARD_REG_SET (used_spill_regs_local);
1833 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1835 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1837 /* Compute the order of preference for hard registers to spill. */
1839 order_regs_for_reload (chain);
1841 for (i = 0; i < n_reloads; i++)
1843 int r = reload_order[i];
1845 /* Ignore reloads that got marked inoperative. */
1846 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1847 && ! rld[r].optional
1848 && rld[r].regno == -1)
1849 if (! find_reg (chain, i))
1851 spill_failure (chain->insn, rld[r].class);
1857 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1858 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1860 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1864 select_reload_regs ()
1866 struct insn_chain *chain;
1868 /* Try to satisfy the needs for each insn. */
1869 for (chain = insns_need_reload; chain != 0;
1870 chain = chain->next_need_reload)
1871 find_reload_regs (chain);
1874 /* Delete all insns that were inserted by emit_caller_save_insns during
1877 delete_caller_save_insns ()
1879 struct insn_chain *c = reload_insn_chain;
1883 while (c != 0 && c->is_caller_save_insn)
1885 struct insn_chain *next = c->next;
1888 if (c == reload_insn_chain)
1889 reload_insn_chain = next;
1893 next->prev = c->prev;
1895 c->prev->next = next;
1896 c->next = unused_insn_chains;
1897 unused_insn_chains = c;
1905 /* Handle the failure to find a register to spill.
1906 INSN should be one of the insns which needed this particular spill reg. */
1909 spill_failure (insn, class)
1911 enum reg_class class;
1913 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1914 if (asm_noperands (PATTERN (insn)) >= 0)
1915 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1916 reg_class_names[class]);
1919 error ("unable to find a register to spill in class `%s'",
1920 reg_class_names[class]);
1921 fatal_insn ("this is the insn:", insn);
1925 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1926 data that is dead in INSN. */
1929 delete_dead_insn (insn)
1932 rtx prev = prev_real_insn (insn);
1935 /* If the previous insn sets a register that dies in our insn, delete it
1937 if (prev && GET_CODE (PATTERN (prev)) == SET
1938 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1939 && reg_mentioned_p (prev_dest, PATTERN (insn))
1940 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1941 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1942 delete_dead_insn (prev);
1944 PUT_CODE (insn, NOTE);
1945 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1946 NOTE_SOURCE_FILE (insn) = 0;
1949 /* Modify the home of pseudo-reg I.
1950 The new home is present in reg_renumber[I].
1952 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1953 or it may be -1, meaning there is none or it is not relevant.
1954 This is used so that all pseudos spilled from a given hard reg
1955 can share one stack slot. */
1958 alter_reg (i, from_reg)
1962 /* When outputting an inline function, this can happen
1963 for a reg that isn't actually used. */
1964 if (regno_reg_rtx[i] == 0)
1967 /* If the reg got changed to a MEM at rtl-generation time,
1969 if (GET_CODE (regno_reg_rtx[i]) != REG)
1972 /* Modify the reg-rtx to contain the new hard reg
1973 number or else to contain its pseudo reg number. */
1974 REGNO (regno_reg_rtx[i])
1975 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1977 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1978 allocate a stack slot for it. */
1980 if (reg_renumber[i] < 0
1981 && REG_N_REFS (i) > 0
1982 && reg_equiv_constant[i] == 0
1983 && reg_equiv_memory_loc[i] == 0)
1986 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1987 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1990 /* Each pseudo reg has an inherent size which comes from its own mode,
1991 and a total size which provides room for paradoxical subregs
1992 which refer to the pseudo reg in wider modes.
1994 We can use a slot already allocated if it provides both
1995 enough inherent space and enough total space.
1996 Otherwise, we allocate a new slot, making sure that it has no less
1997 inherent space, and no less total space, then the previous slot. */
2000 /* No known place to spill from => no slot to reuse. */
2001 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
2002 inherent_size == total_size ? 0 : -1);
2003 if (BYTES_BIG_ENDIAN)
2004 /* Cancel the big-endian correction done in assign_stack_local.
2005 Get the address of the beginning of the slot.
2006 This is so we can do a big-endian correction unconditionally
2008 adjust = inherent_size - total_size;
2010 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
2012 /* Nothing can alias this slot except this pseudo. */
2013 set_mem_alias_set (x, new_alias_set ());
2016 /* Reuse a stack slot if possible. */
2017 else if (spill_stack_slot[from_reg] != 0
2018 && spill_stack_slot_width[from_reg] >= total_size
2019 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2021 x = spill_stack_slot[from_reg];
2023 /* Allocate a bigger slot. */
2026 /* Compute maximum size needed, both for inherent size
2027 and for total size. */
2028 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2031 if (spill_stack_slot[from_reg])
2033 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2035 mode = GET_MODE (spill_stack_slot[from_reg]);
2036 if (spill_stack_slot_width[from_reg] > total_size)
2037 total_size = spill_stack_slot_width[from_reg];
2040 /* Make a slot with that size. */
2041 x = assign_stack_local (mode, total_size,
2042 inherent_size == total_size ? 0 : -1);
2045 /* All pseudos mapped to this slot can alias each other. */
2046 if (spill_stack_slot[from_reg])
2047 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2049 set_mem_alias_set (x, new_alias_set ());
2051 if (BYTES_BIG_ENDIAN)
2053 /* Cancel the big-endian correction done in assign_stack_local.
2054 Get the address of the beginning of the slot.
2055 This is so we can do a big-endian correction unconditionally
2057 adjust = GET_MODE_SIZE (mode) - total_size;
2060 = adjust_address_nv (x, mode_for_size (total_size
2066 spill_stack_slot[from_reg] = stack_slot;
2067 spill_stack_slot_width[from_reg] = total_size;
2070 /* On a big endian machine, the "address" of the slot
2071 is the address of the low part that fits its inherent mode. */
2072 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2073 adjust += (total_size - inherent_size);
2075 /* If we have any adjustment to make, or if the stack slot is the
2076 wrong mode, make a new stack slot. */
2077 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2079 /* If we have a decl for the original register, set it for the
2080 memory. If this is a shared MEM, make a copy. */
2081 if (REG_EXPR (regno_reg_rtx[i])
2082 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2084 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2086 /* We can do this only for the DECLs home pseudo, not for
2087 any copies of it, since otherwise when the stack slot
2088 is reused, nonoverlapping_memrefs_p might think they
2090 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2092 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2095 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2099 /* Save the stack slot for later. */
2100 reg_equiv_memory_loc[i] = x;
2104 /* Mark the slots in regs_ever_live for the hard regs
2105 used by pseudo-reg number REGNO. */
2108 mark_home_live (regno)
2113 i = reg_renumber[regno];
2116 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2118 regs_ever_live[i++] = 1;
2121 /* This function handles the tracking of elimination offsets around branches.
2123 X is a piece of RTL being scanned.
2125 INSN is the insn that it came from, if any.
2127 INITIAL_P is nonzero if we are to set the offset to be the initial
2128 offset and zero if we are setting the offset of the label to be the
2132 set_label_offsets (x, insn, initial_p)
2137 enum rtx_code code = GET_CODE (x);
2140 struct elim_table *p;
2145 if (LABEL_REF_NONLOCAL_P (x))
2150 /* ... fall through ... */
2153 /* If we know nothing about this label, set the desired offsets. Note
2154 that this sets the offset at a label to be the offset before a label
2155 if we don't know anything about the label. This is not correct for
2156 the label after a BARRIER, but is the best guess we can make. If
2157 we guessed wrong, we will suppress an elimination that might have
2158 been possible had we been able to guess correctly. */
2160 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2162 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2163 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2164 = (initial_p ? reg_eliminate[i].initial_offset
2165 : reg_eliminate[i].offset);
2166 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2169 /* Otherwise, if this is the definition of a label and it is
2170 preceded by a BARRIER, set our offsets to the known offset of
2174 && (tem = prev_nonnote_insn (insn)) != 0
2175 && GET_CODE (tem) == BARRIER)
2176 set_offsets_for_label (insn);
2178 /* If neither of the above cases is true, compare each offset
2179 with those previously recorded and suppress any eliminations
2180 where the offsets disagree. */
2182 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2183 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2184 != (initial_p ? reg_eliminate[i].initial_offset
2185 : reg_eliminate[i].offset))
2186 reg_eliminate[i].can_eliminate = 0;
2191 set_label_offsets (PATTERN (insn), insn, initial_p);
2193 /* ... fall through ... */
2197 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2198 and hence must have all eliminations at their initial offsets. */
2199 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2200 if (REG_NOTE_KIND (tem) == REG_LABEL)
2201 set_label_offsets (XEXP (tem, 0), insn, 1);
2207 /* Each of the labels in the parallel or address vector must be
2208 at their initial offsets. We want the first field for PARALLEL
2209 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2211 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2212 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2217 /* We only care about setting PC. If the source is not RETURN,
2218 IF_THEN_ELSE, or a label, disable any eliminations not at
2219 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2220 isn't one of those possibilities. For branches to a label,
2221 call ourselves recursively.
2223 Note that this can disable elimination unnecessarily when we have
2224 a non-local goto since it will look like a non-constant jump to
2225 someplace in the current function. This isn't a significant
2226 problem since such jumps will normally be when all elimination
2227 pairs are back to their initial offsets. */
2229 if (SET_DEST (x) != pc_rtx)
2232 switch (GET_CODE (SET_SRC (x)))
2239 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2243 tem = XEXP (SET_SRC (x), 1);
2244 if (GET_CODE (tem) == LABEL_REF)
2245 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2246 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2249 tem = XEXP (SET_SRC (x), 2);
2250 if (GET_CODE (tem) == LABEL_REF)
2251 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2252 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2260 /* If we reach here, all eliminations must be at their initial
2261 offset because we are doing a jump to a variable address. */
2262 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2263 if (p->offset != p->initial_offset)
2264 p->can_eliminate = 0;
2272 /* Scan X and replace any eliminable registers (such as fp) with a
2273 replacement (such as sp), plus an offset.
2275 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2276 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2277 MEM, we are allowed to replace a sum of a register and the constant zero
2278 with the register, which we cannot do outside a MEM. In addition, we need
2279 to record the fact that a register is referenced outside a MEM.
2281 If INSN is an insn, it is the insn containing X. If we replace a REG
2282 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2283 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2284 the REG is being modified.
2286 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2287 That's used when we eliminate in expressions stored in notes.
2288 This means, do not set ref_outside_mem even if the reference
2291 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2292 replacements done assuming all offsets are at their initial values. If
2293 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2294 encounter, return the actual location so that find_reloads will do
2295 the proper thing. */
2298 eliminate_regs (x, mem_mode, insn)
2300 enum machine_mode mem_mode;
2303 enum rtx_code code = GET_CODE (x);
2304 struct elim_table *ep;
2311 if (! current_function_decl)
2331 /* This is only for the benefit of the debugging backends, which call
2332 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2333 removed after CSE. */
2334 new = eliminate_regs (XEXP (x, 0), 0, insn);
2335 if (GET_CODE (new) == MEM)
2336 return XEXP (new, 0);
2342 /* First handle the case where we encounter a bare register that
2343 is eliminable. Replace it with a PLUS. */
2344 if (regno < FIRST_PSEUDO_REGISTER)
2346 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2348 if (ep->from_rtx == x && ep->can_eliminate)
2349 return plus_constant (ep->to_rtx, ep->previous_offset);
2352 else if (reg_renumber && reg_renumber[regno] < 0
2353 && reg_equiv_constant && reg_equiv_constant[regno]
2354 && ! CONSTANT_P (reg_equiv_constant[regno]))
2355 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2359 /* You might think handling MINUS in a manner similar to PLUS is a
2360 good idea. It is not. It has been tried multiple times and every
2361 time the change has had to have been reverted.
2363 Other parts of reload know a PLUS is special (gen_reload for example)
2364 and require special code to handle code a reloaded PLUS operand.
2366 Also consider backends where the flags register is clobbered by a
2367 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2368 lea instruction comes to mind). If we try to reload a MINUS, we
2369 may kill the flags register that was holding a useful value.
2371 So, please before trying to handle MINUS, consider reload as a
2372 whole instead of this little section as well as the backend issues. */
2374 /* If this is the sum of an eliminable register and a constant, rework
2376 if (GET_CODE (XEXP (x, 0)) == REG
2377 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2378 && CONSTANT_P (XEXP (x, 1)))
2380 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2382 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2384 /* The only time we want to replace a PLUS with a REG (this
2385 occurs when the constant operand of the PLUS is the negative
2386 of the offset) is when we are inside a MEM. We won't want
2387 to do so at other times because that would change the
2388 structure of the insn in a way that reload can't handle.
2389 We special-case the commonest situation in
2390 eliminate_regs_in_insn, so just replace a PLUS with a
2391 PLUS here, unless inside a MEM. */
2392 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2393 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2396 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2397 plus_constant (XEXP (x, 1),
2398 ep->previous_offset));
2401 /* If the register is not eliminable, we are done since the other
2402 operand is a constant. */
2406 /* If this is part of an address, we want to bring any constant to the
2407 outermost PLUS. We will do this by doing register replacement in
2408 our operands and seeing if a constant shows up in one of them.
2410 Note that there is no risk of modifying the structure of the insn,
2411 since we only get called for its operands, thus we are either
2412 modifying the address inside a MEM, or something like an address
2413 operand of a load-address insn. */
2416 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2417 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2419 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2421 /* If one side is a PLUS and the other side is a pseudo that
2422 didn't get a hard register but has a reg_equiv_constant,
2423 we must replace the constant here since it may no longer
2424 be in the position of any operand. */
2425 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2426 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2427 && reg_renumber[REGNO (new1)] < 0
2428 && reg_equiv_constant != 0
2429 && reg_equiv_constant[REGNO (new1)] != 0)
2430 new1 = reg_equiv_constant[REGNO (new1)];
2431 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2432 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2433 && reg_renumber[REGNO (new0)] < 0
2434 && reg_equiv_constant[REGNO (new0)] != 0)
2435 new0 = reg_equiv_constant[REGNO (new0)];
2437 new = form_sum (new0, new1);
2439 /* As above, if we are not inside a MEM we do not want to
2440 turn a PLUS into something else. We might try to do so here
2441 for an addition of 0 if we aren't optimizing. */
2442 if (! mem_mode && GET_CODE (new) != PLUS)
2443 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2451 /* If this is the product of an eliminable register and a
2452 constant, apply the distribute law and move the constant out
2453 so that we have (plus (mult ..) ..). This is needed in order
2454 to keep load-address insns valid. This case is pathological.
2455 We ignore the possibility of overflow here. */
2456 if (GET_CODE (XEXP (x, 0)) == REG
2457 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2458 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2459 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2461 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2464 /* Refs inside notes don't count for this purpose. */
2465 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2466 || GET_CODE (insn) == INSN_LIST)))
2467 ep->ref_outside_mem = 1;
2470 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2471 ep->previous_offset * INTVAL (XEXP (x, 1)));
2474 /* ... fall through ... */
2478 /* See comments before PLUS about handling MINUS. */
2480 case DIV: case UDIV:
2481 case MOD: case UMOD:
2482 case AND: case IOR: case XOR:
2483 case ROTATERT: case ROTATE:
2484 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2486 case GE: case GT: case GEU: case GTU:
2487 case LE: case LT: case LEU: case LTU:
2489 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2491 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2493 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2494 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2499 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2502 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2503 if (new != XEXP (x, 0))
2505 /* If this is a REG_DEAD note, it is not valid anymore.
2506 Using the eliminated version could result in creating a
2507 REG_DEAD note for the stack or frame pointer. */
2508 if (GET_MODE (x) == REG_DEAD)
2510 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2513 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2517 /* ... fall through ... */
2520 /* Now do eliminations in the rest of the chain. If this was
2521 an EXPR_LIST, this might result in allocating more memory than is
2522 strictly needed, but it simplifies the code. */
2525 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2526 if (new != XEXP (x, 1))
2528 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2536 case STRICT_LOW_PART:
2538 case SIGN_EXTEND: case ZERO_EXTEND:
2539 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2540 case FLOAT: case FIX:
2541 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2549 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2550 if (new != XEXP (x, 0))
2551 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2555 /* Similar to above processing, but preserve SUBREG_BYTE.
2556 Convert (subreg (mem)) to (mem) if not paradoxical.
2557 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2558 pseudo didn't get a hard reg, we must replace this with the
2559 eliminated version of the memory location because push_reloads
2560 may do the replacement in certain circumstances. */
2561 if (GET_CODE (SUBREG_REG (x)) == REG
2562 && (GET_MODE_SIZE (GET_MODE (x))
2563 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2564 && reg_equiv_memory_loc != 0
2565 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2567 new = SUBREG_REG (x);
2570 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2572 if (new != SUBREG_REG (x))
2574 int x_size = GET_MODE_SIZE (GET_MODE (x));
2575 int new_size = GET_MODE_SIZE (GET_MODE (new));
2577 if (GET_CODE (new) == MEM
2578 && ((x_size < new_size
2579 #ifdef WORD_REGISTER_OPERATIONS
2580 /* On these machines, combine can create rtl of the form
2581 (set (subreg:m1 (reg:m2 R) 0) ...)
2582 where m1 < m2, and expects something interesting to
2583 happen to the entire word. Moreover, it will use the
2584 (reg:m2 R) later, expecting all bits to be preserved.
2585 So if the number of words is the same, preserve the
2586 subreg so that push_reloads can see it. */
2587 && ! ((x_size - 1) / UNITS_PER_WORD
2588 == (new_size -1 ) / UNITS_PER_WORD)
2591 || x_size == new_size)
2593 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2595 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2601 /* This is only for the benefit of the debugging backends, which call
2602 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2603 removed after CSE. */
2604 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2605 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2607 /* Our only special processing is to pass the mode of the MEM to our
2608 recursive call and copy the flags. While we are here, handle this
2609 case more efficiently. */
2611 replace_equiv_address_nv (x,
2612 eliminate_regs (XEXP (x, 0),
2613 GET_MODE (x), insn));
2616 /* Handle insn_list USE that a call to a pure function may generate. */
2617 new = eliminate_regs (XEXP (x, 0), 0, insn);
2618 if (new != XEXP (x, 0))
2619 return gen_rtx_USE (GET_MODE (x), new);
2631 /* Process each of our operands recursively. If any have changed, make a
2633 fmt = GET_RTX_FORMAT (code);
2634 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2638 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2639 if (new != XEXP (x, i) && ! copied)
2641 rtx new_x = rtx_alloc (code);
2643 (sizeof (*new_x) - sizeof (new_x->fld)
2644 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2650 else if (*fmt == 'E')
2653 for (j = 0; j < XVECLEN (x, i); j++)
2655 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2656 if (new != XVECEXP (x, i, j) && ! copied_vec)
2658 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2662 rtx new_x = rtx_alloc (code);
2664 (sizeof (*new_x) - sizeof (new_x->fld)
2665 + (sizeof (new_x->fld[0])
2666 * GET_RTX_LENGTH (code))));
2670 XVEC (x, i) = new_v;
2673 XVECEXP (x, i, j) = new;
2681 /* Scan rtx X for modifications of elimination target registers. Update
2682 the table of eliminables to reflect the changed state. MEM_MODE is
2683 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2686 elimination_effects (x, mem_mode)
2688 enum machine_mode mem_mode;
2691 enum rtx_code code = GET_CODE (x);
2692 struct elim_table *ep;
2719 /* First handle the case where we encounter a bare register that
2720 is eliminable. Replace it with a PLUS. */
2721 if (regno < FIRST_PSEUDO_REGISTER)
2723 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2725 if (ep->from_rtx == x && ep->can_eliminate)
2728 ep->ref_outside_mem = 1;
2733 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2734 && reg_equiv_constant[regno]
2735 && ! function_invariant_p (reg_equiv_constant[regno]))
2736 elimination_effects (reg_equiv_constant[regno], mem_mode);
2745 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2746 if (ep->to_rtx == XEXP (x, 0))
2748 int size = GET_MODE_SIZE (mem_mode);
2750 /* If more bytes than MEM_MODE are pushed, account for them. */
2751 #ifdef PUSH_ROUNDING
2752 if (ep->to_rtx == stack_pointer_rtx)
2753 size = PUSH_ROUNDING (size);
2755 if (code == PRE_DEC || code == POST_DEC)
2757 else if (code == PRE_INC || code == POST_INC)
2759 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2760 && GET_CODE (XEXP (x, 1)) == PLUS
2761 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2762 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2763 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2766 /* These two aren't unary operators. */
2767 if (code == POST_MODIFY || code == PRE_MODIFY)
2770 /* Fall through to generic unary operation case. */
2771 case STRICT_LOW_PART:
2773 case SIGN_EXTEND: case ZERO_EXTEND:
2774 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2775 case FLOAT: case FIX:
2776 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2784 elimination_effects (XEXP (x, 0), mem_mode);
2788 if (GET_CODE (SUBREG_REG (x)) == REG
2789 && (GET_MODE_SIZE (GET_MODE (x))
2790 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2791 && reg_equiv_memory_loc != 0
2792 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2795 elimination_effects (SUBREG_REG (x), mem_mode);
2799 /* If using a register that is the source of an eliminate we still
2800 think can be performed, note it cannot be performed since we don't
2801 know how this register is used. */
2802 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2803 if (ep->from_rtx == XEXP (x, 0))
2804 ep->can_eliminate = 0;
2806 elimination_effects (XEXP (x, 0), mem_mode);
2810 /* If clobbering a register that is the replacement register for an
2811 elimination we still think can be performed, note that it cannot
2812 be performed. Otherwise, we need not be concerned about it. */
2813 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2814 if (ep->to_rtx == XEXP (x, 0))
2815 ep->can_eliminate = 0;
2817 elimination_effects (XEXP (x, 0), mem_mode);
2821 /* Check for setting a register that we know about. */
2822 if (GET_CODE (SET_DEST (x)) == REG)
2824 /* See if this is setting the replacement register for an
2827 If DEST is the hard frame pointer, we do nothing because we
2828 assume that all assignments to the frame pointer are for
2829 non-local gotos and are being done at a time when they are valid
2830 and do not disturb anything else. Some machines want to
2831 eliminate a fake argument pointer (or even a fake frame pointer)
2832 with either the real frame or the stack pointer. Assignments to
2833 the hard frame pointer must not prevent this elimination. */
2835 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2837 if (ep->to_rtx == SET_DEST (x)
2838 && SET_DEST (x) != hard_frame_pointer_rtx)
2840 /* If it is being incremented, adjust the offset. Otherwise,
2841 this elimination can't be done. */
2842 rtx src = SET_SRC (x);
2844 if (GET_CODE (src) == PLUS
2845 && XEXP (src, 0) == SET_DEST (x)
2846 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2847 ep->offset -= INTVAL (XEXP (src, 1));
2849 ep->can_eliminate = 0;
2853 elimination_effects (SET_DEST (x), 0);
2854 elimination_effects (SET_SRC (x), 0);
2858 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2861 /* Our only special processing is to pass the mode of the MEM to our
2863 elimination_effects (XEXP (x, 0), GET_MODE (x));
2870 fmt = GET_RTX_FORMAT (code);
2871 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2874 elimination_effects (XEXP (x, i), mem_mode);
2875 else if (*fmt == 'E')
2876 for (j = 0; j < XVECLEN (x, i); j++)
2877 elimination_effects (XVECEXP (x, i, j), mem_mode);
2881 /* Descend through rtx X and verify that no references to eliminable registers
2882 remain. If any do remain, mark the involved register as not
2886 check_eliminable_occurrences (x)
2896 code = GET_CODE (x);
2898 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2900 struct elim_table *ep;
2902 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2903 if (ep->from_rtx == x && ep->can_eliminate)
2904 ep->can_eliminate = 0;
2908 fmt = GET_RTX_FORMAT (code);
2909 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2912 check_eliminable_occurrences (XEXP (x, i));
2913 else if (*fmt == 'E')
2916 for (j = 0; j < XVECLEN (x, i); j++)
2917 check_eliminable_occurrences (XVECEXP (x, i, j));
2922 /* Scan INSN and eliminate all eliminable registers in it.
2924 If REPLACE is nonzero, do the replacement destructively. Also
2925 delete the insn as dead it if it is setting an eliminable register.
2927 If REPLACE is zero, do all our allocations in reload_obstack.
2929 If no eliminations were done and this insn doesn't require any elimination
2930 processing (these are not identical conditions: it might be updating sp,
2931 but not referencing fp; this needs to be seen during reload_as_needed so
2932 that the offset between fp and sp can be taken into consideration), zero
2933 is returned. Otherwise, 1 is returned. */
2936 eliminate_regs_in_insn (insn, replace)
2940 int icode = recog_memoized (insn);
2941 rtx old_body = PATTERN (insn);
2942 int insn_is_asm = asm_noperands (old_body) >= 0;
2943 rtx old_set = single_set (insn);
2947 rtx substed_operand[MAX_RECOG_OPERANDS];
2948 rtx orig_operand[MAX_RECOG_OPERANDS];
2949 struct elim_table *ep;
2951 if (! insn_is_asm && icode < 0)
2953 if (GET_CODE (PATTERN (insn)) == USE
2954 || GET_CODE (PATTERN (insn)) == CLOBBER
2955 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2956 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2957 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2962 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2963 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2965 /* Check for setting an eliminable register. */
2966 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2967 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2969 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2970 /* If this is setting the frame pointer register to the
2971 hardware frame pointer register and this is an elimination
2972 that will be done (tested above), this insn is really
2973 adjusting the frame pointer downward to compensate for
2974 the adjustment done before a nonlocal goto. */
2975 if (ep->from == FRAME_POINTER_REGNUM
2976 && ep->to == HARD_FRAME_POINTER_REGNUM)
2978 rtx base = SET_SRC (old_set);
2979 rtx base_insn = insn;
2982 while (base != ep->to_rtx)
2984 rtx prev_insn, prev_set;
2986 if (GET_CODE (base) == PLUS
2987 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2989 offset += INTVAL (XEXP (base, 1));
2990 base = XEXP (base, 0);
2992 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2993 && (prev_set = single_set (prev_insn)) != 0
2994 && rtx_equal_p (SET_DEST (prev_set), base))
2996 base = SET_SRC (prev_set);
2997 base_insn = prev_insn;
3003 if (base == ep->to_rtx)
3006 = plus_constant (ep->to_rtx, offset - ep->offset);
3008 new_body = old_body;
3011 new_body = copy_insn (old_body);
3012 if (REG_NOTES (insn))
3013 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3015 PATTERN (insn) = new_body;
3016 old_set = single_set (insn);
3018 /* First see if this insn remains valid when we
3019 make the change. If not, keep the INSN_CODE
3020 the same and let reload fit it up. */
3021 validate_change (insn, &SET_SRC (old_set), src, 1);
3022 validate_change (insn, &SET_DEST (old_set),
3024 if (! apply_change_group ())
3026 SET_SRC (old_set) = src;
3027 SET_DEST (old_set) = ep->to_rtx;
3036 /* In this case this insn isn't serving a useful purpose. We
3037 will delete it in reload_as_needed once we know that this
3038 elimination is, in fact, being done.
3040 If REPLACE isn't set, we can't delete this insn, but needn't
3041 process it since it won't be used unless something changes. */
3044 delete_dead_insn (insn);
3052 /* We allow one special case which happens to work on all machines we
3053 currently support: a single set with the source being a PLUS of an
3054 eliminable register and a constant. */
3056 && GET_CODE (SET_DEST (old_set)) == REG
3057 && GET_CODE (SET_SRC (old_set)) == PLUS
3058 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3059 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3060 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3062 rtx reg = XEXP (SET_SRC (old_set), 0);
3063 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3065 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3066 if (ep->from_rtx == reg && ep->can_eliminate)
3068 offset += ep->offset;
3073 /* We assume here that if we need a PARALLEL with
3074 CLOBBERs for this assignment, we can do with the
3075 MATCH_SCRATCHes that add_clobbers allocates.
3076 There's not much we can do if that doesn't work. */
3077 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3081 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3084 rtvec vec = rtvec_alloc (num_clobbers + 1);
3086 vec->elem[0] = PATTERN (insn);
3087 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3088 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3090 if (INSN_CODE (insn) < 0)
3095 new_body = old_body;
3098 new_body = copy_insn (old_body);
3099 if (REG_NOTES (insn))
3100 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3102 PATTERN (insn) = new_body;
3103 old_set = single_set (insn);
3105 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3106 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3109 /* This can't have an effect on elimination offsets, so skip right
3115 /* Determine the effects of this insn on elimination offsets. */
3116 elimination_effects (old_body, 0);
3118 /* Eliminate all eliminable registers occurring in operands that
3119 can be handled by reload. */
3120 extract_insn (insn);
3121 for (i = 0; i < recog_data.n_operands; i++)
3123 orig_operand[i] = recog_data.operand[i];
3124 substed_operand[i] = recog_data.operand[i];
3126 /* For an asm statement, every operand is eliminable. */
3127 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3129 /* Check for setting a register that we know about. */
3130 if (recog_data.operand_type[i] != OP_IN
3131 && GET_CODE (orig_operand[i]) == REG)
3133 /* If we are assigning to a register that can be eliminated, it
3134 must be as part of a PARALLEL, since the code above handles
3135 single SETs. We must indicate that we can no longer
3136 eliminate this reg. */
3137 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3139 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3140 ep->can_eliminate = 0;
3143 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3144 replace ? insn : NULL_RTX);
3145 if (substed_operand[i] != orig_operand[i])
3147 /* Terminate the search in check_eliminable_occurrences at
3149 *recog_data.operand_loc[i] = 0;
3151 /* If an output operand changed from a REG to a MEM and INSN is an
3152 insn, write a CLOBBER insn. */
3153 if (recog_data.operand_type[i] != OP_IN
3154 && GET_CODE (orig_operand[i]) == REG
3155 && GET_CODE (substed_operand[i]) == MEM
3157 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3162 for (i = 0; i < recog_data.n_dups; i++)
3163 *recog_data.dup_loc[i]
3164 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3166 /* If any eliminable remain, they aren't eliminable anymore. */
3167 check_eliminable_occurrences (old_body);
3169 /* Substitute the operands; the new values are in the substed_operand
3171 for (i = 0; i < recog_data.n_operands; i++)
3172 *recog_data.operand_loc[i] = substed_operand[i];
3173 for (i = 0; i < recog_data.n_dups; i++)
3174 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3176 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3177 re-recognize the insn. We do this in case we had a simple addition
3178 but now can do this as a load-address. This saves an insn in this
3180 If re-recognition fails, the old insn code number will still be used,
3181 and some register operands may have changed into PLUS expressions.
3182 These will be handled by find_reloads by loading them into a register
3187 /* If we aren't replacing things permanently and we changed something,
3188 make another copy to ensure that all the RTL is new. Otherwise
3189 things can go wrong if find_reload swaps commutative operands
3190 and one is inside RTL that has been copied while the other is not. */
3191 new_body = old_body;
3194 new_body = copy_insn (old_body);
3195 if (REG_NOTES (insn))
3196 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3198 PATTERN (insn) = new_body;
3200 /* If we had a move insn but now we don't, rerecognize it. This will
3201 cause spurious re-recognition if the old move had a PARALLEL since
3202 the new one still will, but we can't call single_set without
3203 having put NEW_BODY into the insn and the re-recognition won't
3204 hurt in this rare case. */
3205 /* ??? Why this huge if statement - why don't we just rerecognize the
3209 && ((GET_CODE (SET_SRC (old_set)) == REG
3210 && (GET_CODE (new_body) != SET
3211 || GET_CODE (SET_SRC (new_body)) != REG))
3212 /* If this was a load from or store to memory, compare
3213 the MEM in recog_data.operand to the one in the insn.
3214 If they are not equal, then rerecognize the insn. */
3216 && ((GET_CODE (SET_SRC (old_set)) == MEM
3217 && SET_SRC (old_set) != recog_data.operand[1])
3218 || (GET_CODE (SET_DEST (old_set)) == MEM
3219 && SET_DEST (old_set) != recog_data.operand[0])))
3220 /* If this was an add insn before, rerecognize. */
3221 || GET_CODE (SET_SRC (old_set)) == PLUS))
3223 int new_icode = recog (PATTERN (insn), insn, 0);
3225 INSN_CODE (insn) = icode;
3229 /* Restore the old body. If there were any changes to it, we made a copy
3230 of it while the changes were still in place, so we'll correctly return
3231 a modified insn below. */
3234 /* Restore the old body. */
3235 for (i = 0; i < recog_data.n_operands; i++)
3236 *recog_data.operand_loc[i] = orig_operand[i];
3237 for (i = 0; i < recog_data.n_dups; i++)
3238 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3241 /* Update all elimination pairs to reflect the status after the current
3242 insn. The changes we make were determined by the earlier call to
3243 elimination_effects.
3245 We also detect cases where register elimination cannot be done,
3246 namely, if a register would be both changed and referenced outside a MEM
3247 in the resulting insn since such an insn is often undefined and, even if
3248 not, we cannot know what meaning will be given to it. Note that it is
3249 valid to have a register used in an address in an insn that changes it
3250 (presumably with a pre- or post-increment or decrement).
3252 If anything changes, return nonzero. */
3254 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3256 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3257 ep->can_eliminate = 0;
3259 ep->ref_outside_mem = 0;
3261 if (ep->previous_offset != ep->offset)
3266 /* If we changed something, perform elimination in REG_NOTES. This is
3267 needed even when REPLACE is zero because a REG_DEAD note might refer
3268 to a register that we eliminate and could cause a different number
3269 of spill registers to be needed in the final reload pass than in
3271 if (val && REG_NOTES (insn) != 0)
3272 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3277 /* Loop through all elimination pairs.
3278 Recalculate the number not at initial offset.
3280 Compute the maximum offset (minimum offset if the stack does not
3281 grow downward) for each elimination pair. */
3284 update_eliminable_offsets ()
3286 struct elim_table *ep;
3288 num_not_at_initial_offset = 0;
3289 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3291 ep->previous_offset = ep->offset;
3292 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3293 num_not_at_initial_offset++;
3297 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3298 replacement we currently believe is valid, mark it as not eliminable if X
3299 modifies DEST in any way other than by adding a constant integer to it.
3301 If DEST is the frame pointer, we do nothing because we assume that
3302 all assignments to the hard frame pointer are nonlocal gotos and are being
3303 done at a time when they are valid and do not disturb anything else.
3304 Some machines want to eliminate a fake argument pointer with either the
3305 frame or stack pointer. Assignments to the hard frame pointer must not
3306 prevent this elimination.
3308 Called via note_stores from reload before starting its passes to scan
3309 the insns of the function. */
3312 mark_not_eliminable (dest, x, data)
3315 void *data ATTRIBUTE_UNUSED;
3319 /* A SUBREG of a hard register here is just changing its mode. We should
3320 not see a SUBREG of an eliminable hard register, but check just in
3322 if (GET_CODE (dest) == SUBREG)
3323 dest = SUBREG_REG (dest);
3325 if (dest == hard_frame_pointer_rtx)
3328 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3329 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3330 && (GET_CODE (x) != SET
3331 || GET_CODE (SET_SRC (x)) != PLUS
3332 || XEXP (SET_SRC (x), 0) != dest
3333 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3335 reg_eliminate[i].can_eliminate_previous
3336 = reg_eliminate[i].can_eliminate = 0;
3341 /* Verify that the initial elimination offsets did not change since the
3342 last call to set_initial_elim_offsets. This is used to catch cases
3343 where something illegal happened during reload_as_needed that could
3344 cause incorrect code to be generated if we did not check for it. */
3347 verify_initial_elim_offsets ()
3351 #ifdef ELIMINABLE_REGS
3352 struct elim_table *ep;
3354 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3356 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3357 if (t != ep->initial_offset)
3361 INITIAL_FRAME_POINTER_OFFSET (t);
3362 if (t != reg_eliminate[0].initial_offset)
3367 /* Reset all offsets on eliminable registers to their initial values. */
3370 set_initial_elim_offsets ()
3372 struct elim_table *ep = reg_eliminate;
3374 #ifdef ELIMINABLE_REGS
3375 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3377 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3378 ep->previous_offset = ep->offset = ep->initial_offset;
3381 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3382 ep->previous_offset = ep->offset = ep->initial_offset;
3385 num_not_at_initial_offset = 0;
3388 /* Initialize the known label offsets.
3389 Set a known offset for each forced label to be at the initial offset
3390 of each elimination. We do this because we assume that all
3391 computed jumps occur from a location where each elimination is
3392 at its initial offset.
3393 For all other labels, show that we don't know the offsets. */
3396 set_initial_label_offsets ()
3399 memset (offsets_known_at, 0, num_labels);
3401 for (x = forced_labels; x; x = XEXP (x, 1))
3403 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3406 /* Set all elimination offsets to the known values for the code label given
3410 set_offsets_for_label (insn)
3414 int label_nr = CODE_LABEL_NUMBER (insn);
3415 struct elim_table *ep;
3417 num_not_at_initial_offset = 0;
3418 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3420 ep->offset = ep->previous_offset
3421 = offsets_at[label_nr - first_label_num][i];
3422 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3423 num_not_at_initial_offset++;
3427 /* See if anything that happened changes which eliminations are valid.
3428 For example, on the SPARC, whether or not the frame pointer can
3429 be eliminated can depend on what registers have been used. We need
3430 not check some conditions again (such as flag_omit_frame_pointer)
3431 since they can't have changed. */
3434 update_eliminables (pset)
3437 int previous_frame_pointer_needed = frame_pointer_needed;
3438 struct elim_table *ep;
3440 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3441 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3442 #ifdef ELIMINABLE_REGS
3443 || ! CAN_ELIMINATE (ep->from, ep->to)
3446 ep->can_eliminate = 0;
3448 /* Look for the case where we have discovered that we can't replace
3449 register A with register B and that means that we will now be
3450 trying to replace register A with register C. This means we can
3451 no longer replace register C with register B and we need to disable
3452 such an elimination, if it exists. This occurs often with A == ap,
3453 B == sp, and C == fp. */
3455 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3457 struct elim_table *op;
3460 if (! ep->can_eliminate && ep->can_eliminate_previous)
3462 /* Find the current elimination for ep->from, if there is a
3464 for (op = reg_eliminate;
3465 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3466 if (op->from == ep->from && op->can_eliminate)
3472 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3474 for (op = reg_eliminate;
3475 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3476 if (op->from == new_to && op->to == ep->to)
3477 op->can_eliminate = 0;
3481 /* See if any registers that we thought we could eliminate the previous
3482 time are no longer eliminable. If so, something has changed and we
3483 must spill the register. Also, recompute the number of eliminable
3484 registers and see if the frame pointer is needed; it is if there is
3485 no elimination of the frame pointer that we can perform. */
3487 frame_pointer_needed = 1;
3488 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3490 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3491 && ep->to != HARD_FRAME_POINTER_REGNUM)
3492 frame_pointer_needed = 0;
3494 if (! ep->can_eliminate && ep->can_eliminate_previous)
3496 ep->can_eliminate_previous = 0;
3497 SET_HARD_REG_BIT (*pset, ep->from);
3502 /* If we didn't need a frame pointer last time, but we do now, spill
3503 the hard frame pointer. */
3504 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3505 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3508 /* Initialize the table of registers to eliminate. */
3513 struct elim_table *ep;
3514 #ifdef ELIMINABLE_REGS
3515 const struct elim_table_1 *ep1;
3519 reg_eliminate = (struct elim_table *)
3520 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3522 /* Does this function require a frame pointer? */
3524 frame_pointer_needed = (! flag_omit_frame_pointer
3525 #ifdef EXIT_IGNORE_STACK
3526 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3527 and restore sp for alloca. So we can't eliminate
3528 the frame pointer in that case. At some point,
3529 we should improve this by emitting the
3530 sp-adjusting insns for this case. */
3531 || (current_function_calls_alloca
3532 && EXIT_IGNORE_STACK)
3534 || FRAME_POINTER_REQUIRED);
3538 #ifdef ELIMINABLE_REGS
3539 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3540 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3542 ep->from = ep1->from;
3544 ep->can_eliminate = ep->can_eliminate_previous
3545 = (CAN_ELIMINATE (ep->from, ep->to)
3546 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3549 reg_eliminate[0].from = reg_eliminate_1[0].from;
3550 reg_eliminate[0].to = reg_eliminate_1[0].to;
3551 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3552 = ! frame_pointer_needed;
3555 /* Count the number of eliminable registers and build the FROM and TO
3556 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3557 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3558 We depend on this. */
3559 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3561 num_eliminable += ep->can_eliminate;
3562 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3563 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3567 /* Kick all pseudos out of hard register REGNO.
3569 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3570 because we found we can't eliminate some register. In the case, no pseudos
3571 are allowed to be in the register, even if they are only in a block that
3572 doesn't require spill registers, unlike the case when we are spilling this
3573 hard reg to produce another spill register.
3575 Return nonzero if any pseudos needed to be kicked out. */
3578 spill_hard_reg (regno, cant_eliminate)
3586 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3587 regs_ever_live[regno] = 1;
3590 /* Spill every pseudo reg that was allocated to this reg
3591 or to something that overlaps this reg. */
3593 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3594 if (reg_renumber[i] >= 0
3595 && (unsigned int) reg_renumber[i] <= regno
3596 && ((unsigned int) reg_renumber[i]
3597 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3598 PSEUDO_REGNO_MODE (i))
3600 SET_REGNO_REG_SET (&spilled_pseudos, i);
3603 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3604 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3607 ior_hard_reg_set (set1, set2)
3608 HARD_REG_SET *set1, *set2;
3610 IOR_HARD_REG_SET (*set1, *set2);
3613 /* After find_reload_regs has been run for all insn that need reloads,
3614 and/or spill_hard_regs was called, this function is used to actually
3615 spill pseudo registers and try to reallocate them. It also sets up the
3616 spill_regs array for use by choose_reload_regs. */
3619 finish_spills (global)
3622 struct insn_chain *chain;
3623 int something_changed = 0;
3626 /* Build the spill_regs array for the function. */
3627 /* If there are some registers still to eliminate and one of the spill regs
3628 wasn't ever used before, additional stack space may have to be
3629 allocated to store this register. Thus, we may have changed the offset
3630 between the stack and frame pointers, so mark that something has changed.
3632 One might think that we need only set VAL to 1 if this is a call-used
3633 register. However, the set of registers that must be saved by the
3634 prologue is not identical to the call-used set. For example, the
3635 register used by the call insn for the return PC is a call-used register,
3636 but must be saved by the prologue. */
3639 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3640 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3642 spill_reg_order[i] = n_spills;
3643 spill_regs[n_spills++] = i;
3644 if (num_eliminable && ! regs_ever_live[i])
3645 something_changed = 1;
3646 regs_ever_live[i] = 1;
3649 spill_reg_order[i] = -1;
3651 EXECUTE_IF_SET_IN_REG_SET
3652 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3654 /* Record the current hard register the pseudo is allocated to in
3655 pseudo_previous_regs so we avoid reallocating it to the same
3656 hard reg in a later pass. */
3657 if (reg_renumber[i] < 0)
3660 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3661 /* Mark it as no longer having a hard register home. */
3662 reg_renumber[i] = -1;
3663 /* We will need to scan everything again. */
3664 something_changed = 1;
3667 /* Retry global register allocation if possible. */
3670 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3671 /* For every insn that needs reloads, set the registers used as spill
3672 regs in pseudo_forbidden_regs for every pseudo live across the
3674 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3676 EXECUTE_IF_SET_IN_REG_SET
3677 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3679 ior_hard_reg_set (pseudo_forbidden_regs + i,
3680 &chain->used_spill_regs);
3682 EXECUTE_IF_SET_IN_REG_SET
3683 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3685 ior_hard_reg_set (pseudo_forbidden_regs + i,
3686 &chain->used_spill_regs);
3690 /* Retry allocating the spilled pseudos. For each reg, merge the
3691 various reg sets that indicate which hard regs can't be used,
3692 and call retry_global_alloc.
3693 We change spill_pseudos here to only contain pseudos that did not
3694 get a new hard register. */
3695 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3696 if (reg_old_renumber[i] != reg_renumber[i])
3698 HARD_REG_SET forbidden;
3699 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3700 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3701 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3702 retry_global_alloc (i, forbidden);
3703 if (reg_renumber[i] >= 0)
3704 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3708 /* Fix up the register information in the insn chain.
3709 This involves deleting those of the spilled pseudos which did not get
3710 a new hard register home from the live_{before,after} sets. */
3711 for (chain = reload_insn_chain; chain; chain = chain->next)
3713 HARD_REG_SET used_by_pseudos;
3714 HARD_REG_SET used_by_pseudos2;
3716 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3717 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3719 /* Mark any unallocated hard regs as available for spills. That
3720 makes inheritance work somewhat better. */
3721 if (chain->need_reload)
3723 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3724 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3725 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3727 /* Save the old value for the sanity test below. */
3728 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3730 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3731 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3732 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3733 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3735 /* Make sure we only enlarge the set. */
3736 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3742 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3743 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3745 int regno = reg_renumber[i];
3746 if (reg_old_renumber[i] == regno)
3749 alter_reg (i, reg_old_renumber[i]);
3750 reg_old_renumber[i] = regno;
3754 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3756 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3757 i, reg_renumber[i]);
3761 return something_changed;
3764 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3765 Also mark any hard registers used to store user variables as
3766 forbidden from being used for spill registers. */
3769 scan_paradoxical_subregs (x)
3774 enum rtx_code code = GET_CODE (x);
3780 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3781 && REG_USERVAR_P (x))
3782 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3791 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3799 if (GET_CODE (SUBREG_REG (x)) == REG
3800 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3801 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3802 = GET_MODE_SIZE (GET_MODE (x));
3809 fmt = GET_RTX_FORMAT (code);
3810 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3813 scan_paradoxical_subregs (XEXP (x, i));
3814 else if (fmt[i] == 'E')
3817 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3818 scan_paradoxical_subregs (XVECEXP (x, i, j));
3823 /* Reload pseudo-registers into hard regs around each insn as needed.
3824 Additional register load insns are output before the insn that needs it
3825 and perhaps store insns after insns that modify the reloaded pseudo reg.
3827 reg_last_reload_reg and reg_reloaded_contents keep track of
3828 which registers are already available in reload registers.
3829 We update these for the reloads that we perform,
3830 as the insns are scanned. */
3833 reload_as_needed (live_known)
3836 struct insn_chain *chain;
3837 #if defined (AUTO_INC_DEC)
3842 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3843 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3844 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3845 reg_has_output_reload = (char *) xmalloc (max_regno);
3846 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3848 set_initial_elim_offsets ();
3850 for (chain = reload_insn_chain; chain; chain = chain->next)
3853 rtx insn = chain->insn;
3854 rtx old_next = NEXT_INSN (insn);
3856 /* If we pass a label, copy the offsets from the label information
3857 into the current offsets of each elimination. */
3858 if (GET_CODE (insn) == CODE_LABEL)
3859 set_offsets_for_label (insn);
3861 else if (INSN_P (insn))
3863 rtx oldpat = copy_rtx (PATTERN (insn));
3865 /* If this is a USE and CLOBBER of a MEM, ensure that any
3866 references to eliminable registers have been removed. */
3868 if ((GET_CODE (PATTERN (insn)) == USE
3869 || GET_CODE (PATTERN (insn)) == CLOBBER)
3870 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3871 XEXP (XEXP (PATTERN (insn), 0), 0)
3872 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3873 GET_MODE (XEXP (PATTERN (insn), 0)),
3876 /* If we need to do register elimination processing, do so.
3877 This might delete the insn, in which case we are done. */
3878 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3880 eliminate_regs_in_insn (insn, 1);
3881 if (GET_CODE (insn) == NOTE)
3883 update_eliminable_offsets ();
3888 /* If need_elim is nonzero but need_reload is zero, one might think
3889 that we could simply set n_reloads to 0. However, find_reloads
3890 could have done some manipulation of the insn (such as swapping
3891 commutative operands), and these manipulations are lost during
3892 the first pass for every insn that needs register elimination.
3893 So the actions of find_reloads must be redone here. */
3895 if (! chain->need_elim && ! chain->need_reload
3896 && ! chain->need_operand_change)
3898 /* First find the pseudo regs that must be reloaded for this insn.
3899 This info is returned in the tables reload_... (see reload.h).
3900 Also modify the body of INSN by substituting RELOAD
3901 rtx's for those pseudo regs. */
3904 memset (reg_has_output_reload, 0, max_regno);
3905 CLEAR_HARD_REG_SET (reg_is_output_reload);
3907 find_reloads (insn, 1, spill_indirect_levels, live_known,
3913 rtx next = NEXT_INSN (insn);
3916 prev = PREV_INSN (insn);
3918 /* Now compute which reload regs to reload them into. Perhaps
3919 reusing reload regs from previous insns, or else output
3920 load insns to reload them. Maybe output store insns too.
3921 Record the choices of reload reg in reload_reg_rtx. */
3922 choose_reload_regs (chain);
3924 /* Merge any reloads that we didn't combine for fear of
3925 increasing the number of spill registers needed but now
3926 discover can be safely merged. */
3927 if (SMALL_REGISTER_CLASSES)
3928 merge_assigned_reloads (insn);
3930 /* Generate the insns to reload operands into or out of
3931 their reload regs. */
3932 emit_reload_insns (chain);
3934 /* Substitute the chosen reload regs from reload_reg_rtx
3935 into the insn's body (or perhaps into the bodies of other
3936 load and store insn that we just made for reloading
3937 and that we moved the structure into). */
3938 subst_reloads (insn);
3940 /* If this was an ASM, make sure that all the reload insns
3941 we have generated are valid. If not, give an error
3944 if (asm_noperands (PATTERN (insn)) >= 0)
3945 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3946 if (p != insn && INSN_P (p)
3947 && GET_CODE (PATTERN (p)) != USE
3948 && (recog_memoized (p) < 0
3949 || (extract_insn (p), ! constrain_operands (1))))
3951 error_for_asm (insn,
3952 "`asm' operand requires impossible reload");
3957 if (num_eliminable && chain->need_elim)
3958 update_eliminable_offsets ();
3960 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3961 is no longer validly lying around to save a future reload.
3962 Note that this does not detect pseudos that were reloaded
3963 for this insn in order to be stored in
3964 (obeying register constraints). That is correct; such reload
3965 registers ARE still valid. */
3966 note_stores (oldpat, forget_old_reloads_1, NULL);
3968 /* There may have been CLOBBER insns placed after INSN. So scan
3969 between INSN and NEXT and use them to forget old reloads. */
3970 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3971 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3972 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3975 /* Likewise for regs altered by auto-increment in this insn.
3976 REG_INC notes have been changed by reloading:
3977 find_reloads_address_1 records substitutions for them,
3978 which have been performed by subst_reloads above. */
3979 for (i = n_reloads - 1; i >= 0; i--)
3981 rtx in_reg = rld[i].in_reg;
3984 enum rtx_code code = GET_CODE (in_reg);
3985 /* PRE_INC / PRE_DEC will have the reload register ending up
3986 with the same value as the stack slot, but that doesn't
3987 hold true for POST_INC / POST_DEC. Either we have to
3988 convert the memory access to a true POST_INC / POST_DEC,
3989 or we can't use the reload register for inheritance. */
3990 if ((code == POST_INC || code == POST_DEC)
3991 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3992 REGNO (rld[i].reg_rtx))
3993 /* Make sure it is the inc/dec pseudo, and not
3994 some other (e.g. output operand) pseudo. */
3995 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3996 == REGNO (XEXP (in_reg, 0))))
3999 rtx reload_reg = rld[i].reg_rtx;
4000 enum machine_mode mode = GET_MODE (reload_reg);
4004 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4006 /* We really want to ignore REG_INC notes here, so
4007 use PATTERN (p) as argument to reg_set_p . */
4008 if (reg_set_p (reload_reg, PATTERN (p)))
4010 n = count_occurrences (PATTERN (p), reload_reg, 0);
4015 n = validate_replace_rtx (reload_reg,
4016 gen_rtx (code, mode,
4020 /* We must also verify that the constraints
4021 are met after the replacement. */
4024 n = constrain_operands (1);
4028 /* If the constraints were not met, then
4029 undo the replacement. */
4032 validate_replace_rtx (gen_rtx (code, mode,
4044 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4046 /* Mark this as having an output reload so that the
4047 REG_INC processing code below won't invalidate
4048 the reload for inheritance. */
4049 SET_HARD_REG_BIT (reg_is_output_reload,
4050 REGNO (reload_reg));
4051 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4054 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4057 else if ((code == PRE_INC || code == PRE_DEC)
4058 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4059 REGNO (rld[i].reg_rtx))
4060 /* Make sure it is the inc/dec pseudo, and not
4061 some other (e.g. output operand) pseudo. */
4062 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4063 == REGNO (XEXP (in_reg, 0))))
4065 SET_HARD_REG_BIT (reg_is_output_reload,
4066 REGNO (rld[i].reg_rtx));
4067 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4071 /* If a pseudo that got a hard register is auto-incremented,
4072 we must purge records of copying it into pseudos without
4074 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4075 if (REG_NOTE_KIND (x) == REG_INC)
4077 /* See if this pseudo reg was reloaded in this insn.
4078 If so, its last-reload info is still valid
4079 because it is based on this insn's reload. */
4080 for (i = 0; i < n_reloads; i++)
4081 if (rld[i].out == XEXP (x, 0))
4085 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4089 /* A reload reg's contents are unknown after a label. */
4090 if (GET_CODE (insn) == CODE_LABEL)
4091 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4093 /* Don't assume a reload reg is still good after a call insn
4094 if it is a call-used reg. */
4095 else if (GET_CODE (insn) == CALL_INSN)
4096 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4100 free (reg_last_reload_reg);
4101 free (reg_has_output_reload);
4104 /* Discard all record of any value reloaded from X,
4105 or reloaded in X from someplace else;
4106 unless X is an output reload reg of the current insn.
4108 X may be a hard reg (the reload reg)
4109 or it may be a pseudo reg that was reloaded from. */
4112 forget_old_reloads_1 (x, ignored, data)
4114 rtx ignored ATTRIBUTE_UNUSED;
4115 void *data ATTRIBUTE_UNUSED;
4120 /* note_stores does give us subregs of hard regs,
4121 subreg_regno_offset will abort if it is not a hard reg. */
4122 while (GET_CODE (x) == SUBREG)
4124 /* We ignore the subreg offset when calculating the regno,
4125 because we are using the entire underlying hard register
4130 if (GET_CODE (x) != REG)
4135 if (regno >= FIRST_PSEUDO_REGISTER)
4141 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4142 /* Storing into a spilled-reg invalidates its contents.
4143 This can happen if a block-local pseudo is allocated to that reg
4144 and it wasn't spilled because this block's total need is 0.
4145 Then some insn might have an optional reload and use this reg. */
4146 for (i = 0; i < nr; i++)
4147 /* But don't do this if the reg actually serves as an output
4148 reload reg in the current instruction. */
4150 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4152 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4153 spill_reg_store[regno + i] = 0;
4157 /* Since value of X has changed,
4158 forget any value previously copied from it. */
4161 /* But don't forget a copy if this is the output reload
4162 that establishes the copy's validity. */
4163 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4164 reg_last_reload_reg[regno + nr] = 0;
4167 /* The following HARD_REG_SETs indicate when each hard register is
4168 used for a reload of various parts of the current insn. */
4170 /* If reg is unavailable for all reloads. */
4171 static HARD_REG_SET reload_reg_unavailable;
4172 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4173 static HARD_REG_SET reload_reg_used;
4174 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4175 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4176 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4177 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4178 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4179 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4180 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4181 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4182 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4183 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4184 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4185 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4186 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4187 static HARD_REG_SET reload_reg_used_in_op_addr;
4188 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4189 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4190 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4191 static HARD_REG_SET reload_reg_used_in_insn;
4192 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4193 static HARD_REG_SET reload_reg_used_in_other_addr;
4195 /* If reg is in use as a reload reg for any sort of reload. */
4196 static HARD_REG_SET reload_reg_used_at_all;
4198 /* If reg is use as an inherited reload. We just mark the first register
4200 static HARD_REG_SET reload_reg_used_for_inherit;
4202 /* Records which hard regs are used in any way, either as explicit use or
4203 by being allocated to a pseudo during any point of the current insn. */
4204 static HARD_REG_SET reg_used_in_insn;
4206 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4207 TYPE. MODE is used to indicate how many consecutive regs are
4211 mark_reload_reg_in_use (regno, opnum, type, mode)
4214 enum reload_type type;
4215 enum machine_mode mode;
4217 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4220 for (i = regno; i < nregs + regno; i++)
4225 SET_HARD_REG_BIT (reload_reg_used, i);
4228 case RELOAD_FOR_INPUT_ADDRESS:
4229 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4232 case RELOAD_FOR_INPADDR_ADDRESS:
4233 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4236 case RELOAD_FOR_OUTPUT_ADDRESS:
4237 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4240 case RELOAD_FOR_OUTADDR_ADDRESS:
4241 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4244 case RELOAD_FOR_OPERAND_ADDRESS:
4245 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4248 case RELOAD_FOR_OPADDR_ADDR:
4249 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4252 case RELOAD_FOR_OTHER_ADDRESS:
4253 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4256 case RELOAD_FOR_INPUT:
4257 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4260 case RELOAD_FOR_OUTPUT:
4261 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4264 case RELOAD_FOR_INSN:
4265 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4269 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4273 /* Similarly, but show REGNO is no longer in use for a reload. */
4276 clear_reload_reg_in_use (regno, opnum, type, mode)
4279 enum reload_type type;
4280 enum machine_mode mode;
4282 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4283 unsigned int start_regno, end_regno, r;
4285 /* A complication is that for some reload types, inheritance might
4286 allow multiple reloads of the same types to share a reload register.
4287 We set check_opnum if we have to check only reloads with the same
4288 operand number, and check_any if we have to check all reloads. */
4289 int check_opnum = 0;
4291 HARD_REG_SET *used_in_set;
4296 used_in_set = &reload_reg_used;
4299 case RELOAD_FOR_INPUT_ADDRESS:
4300 used_in_set = &reload_reg_used_in_input_addr[opnum];
4303 case RELOAD_FOR_INPADDR_ADDRESS:
4305 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4308 case RELOAD_FOR_OUTPUT_ADDRESS:
4309 used_in_set = &reload_reg_used_in_output_addr[opnum];
4312 case RELOAD_FOR_OUTADDR_ADDRESS:
4314 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4317 case RELOAD_FOR_OPERAND_ADDRESS:
4318 used_in_set = &reload_reg_used_in_op_addr;
4321 case RELOAD_FOR_OPADDR_ADDR:
4323 used_in_set = &reload_reg_used_in_op_addr_reload;
4326 case RELOAD_FOR_OTHER_ADDRESS:
4327 used_in_set = &reload_reg_used_in_other_addr;
4331 case RELOAD_FOR_INPUT:
4332 used_in_set = &reload_reg_used_in_input[opnum];
4335 case RELOAD_FOR_OUTPUT:
4336 used_in_set = &reload_reg_used_in_output[opnum];
4339 case RELOAD_FOR_INSN:
4340 used_in_set = &reload_reg_used_in_insn;
4345 /* We resolve conflicts with remaining reloads of the same type by
4346 excluding the intervals of reload registers by them from the
4347 interval of freed reload registers. Since we only keep track of
4348 one set of interval bounds, we might have to exclude somewhat
4349 more than what would be necessary if we used a HARD_REG_SET here.
4350 But this should only happen very infrequently, so there should
4351 be no reason to worry about it. */
4353 start_regno = regno;
4354 end_regno = regno + nregs;
4355 if (check_opnum || check_any)
4357 for (i = n_reloads - 1; i >= 0; i--)
4359 if (rld[i].when_needed == type
4360 && (check_any || rld[i].opnum == opnum)
4363 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4364 unsigned int conflict_end
4366 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4368 /* If there is an overlap with the first to-be-freed register,
4369 adjust the interval start. */
4370 if (conflict_start <= start_regno && conflict_end > start_regno)
4371 start_regno = conflict_end;
4372 /* Otherwise, if there is a conflict with one of the other
4373 to-be-freed registers, adjust the interval end. */
4374 if (conflict_start > start_regno && conflict_start < end_regno)
4375 end_regno = conflict_start;
4380 for (r = start_regno; r < end_regno; r++)
4381 CLEAR_HARD_REG_BIT (*used_in_set, r);
4384 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4385 specified by OPNUM and TYPE. */
4388 reload_reg_free_p (regno, opnum, type)
4391 enum reload_type type;
4395 /* In use for a RELOAD_OTHER means it's not available for anything. */
4396 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4397 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4403 /* In use for anything means we can't use it for RELOAD_OTHER. */
4404 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4405 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4406 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4409 for (i = 0; i < reload_n_operands; i++)
4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4411 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4412 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4413 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4414 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4415 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4420 case RELOAD_FOR_INPUT:
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4422 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4428 /* If it is used for some other input, can't use it. */
4429 for (i = 0; i < reload_n_operands; i++)
4430 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4433 /* If it is used in a later operand's address, can't use it. */
4434 for (i = opnum + 1; i < reload_n_operands; i++)
4435 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4436 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4441 case RELOAD_FOR_INPUT_ADDRESS:
4442 /* Can't use a register if it is used for an input address for this
4443 operand or used as an input in an earlier one. */
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4445 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4448 for (i = 0; i < opnum; i++)
4449 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4454 case RELOAD_FOR_INPADDR_ADDRESS:
4455 /* Can't use a register if it is used for an input address
4456 for this operand or used as an input in an earlier
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4461 for (i = 0; i < opnum; i++)
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4467 case RELOAD_FOR_OUTPUT_ADDRESS:
4468 /* Can't use a register if it is used for an output address for this
4469 operand or used as an output in this or a later operand. Note
4470 that multiple output operands are emitted in reverse order, so
4471 the conflicting ones are those with lower indices. */
4472 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4475 for (i = 0; i <= opnum; i++)
4476 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4481 case RELOAD_FOR_OUTADDR_ADDRESS:
4482 /* Can't use a register if it is used for an output address
4483 for this operand or used as an output in this or a
4484 later operand. Note that multiple output operands are
4485 emitted in reverse order, so the conflicting ones are
4486 those with lower indices. */
4487 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4490 for (i = 0; i <= opnum; i++)
4491 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4496 case RELOAD_FOR_OPERAND_ADDRESS:
4497 for (i = 0; i < reload_n_operands; i++)
4498 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4501 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4502 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4504 case RELOAD_FOR_OPADDR_ADDR:
4505 for (i = 0; i < reload_n_operands; i++)
4506 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4509 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4511 case RELOAD_FOR_OUTPUT:
4512 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4513 outputs, or an operand address for this or an earlier output.
4514 Note that multiple output operands are emitted in reverse order,
4515 so the conflicting ones are those with higher indices. */
4516 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4519 for (i = 0; i < reload_n_operands; i++)
4520 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4523 for (i = opnum; i < reload_n_operands; i++)
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4530 case RELOAD_FOR_INSN:
4531 for (i = 0; i < reload_n_operands; i++)
4532 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4536 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4537 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4539 case RELOAD_FOR_OTHER_ADDRESS:
4540 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4545 /* Return 1 if the value in reload reg REGNO, as used by a reload
4546 needed for the part of the insn specified by OPNUM and TYPE,
4547 is still available in REGNO at the end of the insn.
4549 We can assume that the reload reg was already tested for availability
4550 at the time it is needed, and we should not check this again,
4551 in case the reg has already been marked in use. */
4554 reload_reg_reaches_end_p (regno, opnum, type)
4557 enum reload_type type;
4564 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4565 its value must reach the end. */
4568 /* If this use is for part of the insn,
4569 its value reaches if no subsequent part uses the same register.
4570 Just like the above function, don't try to do this with lots
4573 case RELOAD_FOR_OTHER_ADDRESS:
4574 /* Here we check for everything else, since these don't conflict
4575 with anything else and everything comes later. */
4577 for (i = 0; i < reload_n_operands; i++)
4578 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4579 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4580 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4581 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4582 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4583 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4586 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4587 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4588 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4590 case RELOAD_FOR_INPUT_ADDRESS:
4591 case RELOAD_FOR_INPADDR_ADDRESS:
4592 /* Similar, except that we check only for this and subsequent inputs
4593 and the address of only subsequent inputs and we do not need
4594 to check for RELOAD_OTHER objects since they are known not to
4597 for (i = opnum; i < reload_n_operands; i++)
4598 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4601 for (i = opnum + 1; i < reload_n_operands; i++)
4602 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4603 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4606 for (i = 0; i < reload_n_operands; i++)
4607 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4608 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4612 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4615 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4616 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4617 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4619 case RELOAD_FOR_INPUT:
4620 /* Similar to input address, except we start at the next operand for
4621 both input and input address and we do not check for
4622 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4625 for (i = opnum + 1; i < reload_n_operands; i++)
4626 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4627 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4628 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4631 /* ... fall through ... */
4633 case RELOAD_FOR_OPERAND_ADDRESS:
4634 /* Check outputs and their addresses. */
4636 for (i = 0; i < reload_n_operands; i++)
4637 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4638 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4639 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4642 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4644 case RELOAD_FOR_OPADDR_ADDR:
4645 for (i = 0; i < reload_n_operands; i++)
4646 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4647 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4648 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4651 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4652 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4653 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4655 case RELOAD_FOR_INSN:
4656 /* These conflict with other outputs with RELOAD_OTHER. So
4657 we need only check for output addresses. */
4659 opnum = reload_n_operands;
4661 /* ... fall through ... */
4663 case RELOAD_FOR_OUTPUT:
4664 case RELOAD_FOR_OUTPUT_ADDRESS:
4665 case RELOAD_FOR_OUTADDR_ADDRESS:
4666 /* We already know these can't conflict with a later output. So the
4667 only thing to check are later output addresses.
4668 Note that multiple output operands are emitted in reverse order,
4669 so the conflicting ones are those with lower indices. */
4670 for (i = 0; i < opnum; i++)
4671 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4672 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4681 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4684 This function uses the same algorithm as reload_reg_free_p above. */
4687 reloads_conflict (r1, r2)
4690 enum reload_type r1_type = rld[r1].when_needed;
4691 enum reload_type r2_type = rld[r2].when_needed;
4692 int r1_opnum = rld[r1].opnum;
4693 int r2_opnum = rld[r2].opnum;
4695 /* RELOAD_OTHER conflicts with everything. */
4696 if (r2_type == RELOAD_OTHER)
4699 /* Otherwise, check conflicts differently for each type. */
4703 case RELOAD_FOR_INPUT:
4704 return (r2_type == RELOAD_FOR_INSN
4705 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4706 || r2_type == RELOAD_FOR_OPADDR_ADDR
4707 || r2_type == RELOAD_FOR_INPUT
4708 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4709 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4710 && r2_opnum > r1_opnum));
4712 case RELOAD_FOR_INPUT_ADDRESS:
4713 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4714 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4716 case RELOAD_FOR_INPADDR_ADDRESS:
4717 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4718 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4720 case RELOAD_FOR_OUTPUT_ADDRESS:
4721 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4722 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4724 case RELOAD_FOR_OUTADDR_ADDRESS:
4725 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4726 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4728 case RELOAD_FOR_OPERAND_ADDRESS:
4729 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4730 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4732 case RELOAD_FOR_OPADDR_ADDR:
4733 return (r2_type == RELOAD_FOR_INPUT
4734 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4736 case RELOAD_FOR_OUTPUT:
4737 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4738 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4739 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4740 && r2_opnum >= r1_opnum));
4742 case RELOAD_FOR_INSN:
4743 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4744 || r2_type == RELOAD_FOR_INSN
4745 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4747 case RELOAD_FOR_OTHER_ADDRESS:
4748 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4758 /* Indexed by reload number, 1 if incoming value
4759 inherited from previous insns. */
4760 char reload_inherited[MAX_RELOADS];
4762 /* For an inherited reload, this is the insn the reload was inherited from,
4763 if we know it. Otherwise, this is 0. */
4764 rtx reload_inheritance_insn[MAX_RELOADS];
4766 /* If nonzero, this is a place to get the value of the reload,
4767 rather than using reload_in. */
4768 rtx reload_override_in[MAX_RELOADS];
4770 /* For each reload, the hard register number of the register used,
4771 or -1 if we did not need a register for this reload. */
4772 int reload_spill_index[MAX_RELOADS];
4774 /* Subroutine of free_for_value_p, used to check a single register.
4775 START_REGNO is the starting regno of the full reload register
4776 (possibly comprising multiple hard registers) that we are considering. */
4779 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4780 reloadnum, ignore_address_reloads)
4781 int start_regno, regno;
4783 enum reload_type type;
4786 int ignore_address_reloads;
4789 /* Set if we see an input reload that must not share its reload register
4790 with any new earlyclobber, but might otherwise share the reload
4791 register with an output or input-output reload. */
4792 int check_earlyclobber = 0;
4796 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4799 if (out == const0_rtx)
4805 /* We use some pseudo 'time' value to check if the lifetimes of the
4806 new register use would overlap with the one of a previous reload
4807 that is not read-only or uses a different value.
4808 The 'time' used doesn't have to be linear in any shape or form, just
4810 Some reload types use different 'buckets' for each operand.
4811 So there are MAX_RECOG_OPERANDS different time values for each
4813 We compute TIME1 as the time when the register for the prospective
4814 new reload ceases to be live, and TIME2 for each existing
4815 reload as the time when that the reload register of that reload
4817 Where there is little to be gained by exact lifetime calculations,
4818 we just make conservative assumptions, i.e. a longer lifetime;
4819 this is done in the 'default:' cases. */
4822 case RELOAD_FOR_OTHER_ADDRESS:
4823 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4824 time1 = copy ? 0 : 1;
4827 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4829 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4830 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4831 respectively, to the time values for these, we get distinct time
4832 values. To get distinct time values for each operand, we have to
4833 multiply opnum by at least three. We round that up to four because
4834 multiply by four is often cheaper. */
4835 case RELOAD_FOR_INPADDR_ADDRESS:
4836 time1 = opnum * 4 + 2;
4838 case RELOAD_FOR_INPUT_ADDRESS:
4839 time1 = opnum * 4 + 3;
4841 case RELOAD_FOR_INPUT:
4842 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4843 executes (inclusive). */
4844 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4846 case RELOAD_FOR_OPADDR_ADDR:
4848 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4849 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4851 case RELOAD_FOR_OPERAND_ADDRESS:
4852 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4854 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4856 case RELOAD_FOR_OUTADDR_ADDRESS:
4857 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4859 case RELOAD_FOR_OUTPUT_ADDRESS:
4860 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4863 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4866 for (i = 0; i < n_reloads; i++)
4868 rtx reg = rld[i].reg_rtx;
4869 if (reg && GET_CODE (reg) == REG
4870 && ((unsigned) regno - true_regnum (reg)
4871 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4874 rtx other_input = rld[i].in;
4876 /* If the other reload loads the same input value, that
4877 will not cause a conflict only if it's loading it into
4878 the same register. */
4879 if (true_regnum (reg) != start_regno)
4880 other_input = NULL_RTX;
4881 if (! other_input || ! rtx_equal_p (other_input, value)
4882 || rld[i].out || out)
4885 switch (rld[i].when_needed)
4887 case RELOAD_FOR_OTHER_ADDRESS:
4890 case RELOAD_FOR_INPADDR_ADDRESS:
4891 /* find_reloads makes sure that a
4892 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4893 by at most one - the first -
4894 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4895 address reload is inherited, the address address reload
4896 goes away, so we can ignore this conflict. */
4897 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4898 && ignore_address_reloads
4899 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4900 Then the address address is still needed to store
4901 back the new address. */
4902 && ! rld[reloadnum].out)
4904 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4905 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4907 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4908 && ignore_address_reloads
4909 /* Unless we are reloading an auto_inc expression. */
4910 && ! rld[reloadnum].out)
4912 time2 = rld[i].opnum * 4 + 2;
4914 case RELOAD_FOR_INPUT_ADDRESS:
4915 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4916 && ignore_address_reloads
4917 && ! rld[reloadnum].out)
4919 time2 = rld[i].opnum * 4 + 3;
4921 case RELOAD_FOR_INPUT:
4922 time2 = rld[i].opnum * 4 + 4;
4923 check_earlyclobber = 1;
4925 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4926 == MAX_RECOG_OPERAND * 4 */
4927 case RELOAD_FOR_OPADDR_ADDR:
4928 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4929 && ignore_address_reloads
4930 && ! rld[reloadnum].out)
4932 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4934 case RELOAD_FOR_OPERAND_ADDRESS:
4935 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4936 check_earlyclobber = 1;
4938 case RELOAD_FOR_INSN:
4939 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4941 case RELOAD_FOR_OUTPUT:
4942 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4943 instruction is executed. */
4944 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4946 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4947 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4949 case RELOAD_FOR_OUTADDR_ADDRESS:
4950 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4951 && ignore_address_reloads
4952 && ! rld[reloadnum].out)
4954 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4956 case RELOAD_FOR_OUTPUT_ADDRESS:
4957 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4960 /* If there is no conflict in the input part, handle this
4961 like an output reload. */
4962 if (! rld[i].in || rtx_equal_p (other_input, value))
4964 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4965 /* Earlyclobbered outputs must conflict with inputs. */
4966 if (earlyclobber_operand_p (rld[i].out))
4967 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4972 /* RELOAD_OTHER might be live beyond instruction execution,
4973 but this is not obvious when we set time2 = 1. So check
4974 here if there might be a problem with the new reload
4975 clobbering the register used by the RELOAD_OTHER. */
4983 && (! rld[i].in || rld[i].out
4984 || ! rtx_equal_p (other_input, value)))
4985 || (out && rld[reloadnum].out_reg
4986 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4992 /* Earlyclobbered outputs must conflict with inputs. */
4993 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4999 /* Return 1 if the value in reload reg REGNO, as used by a reload
5000 needed for the part of the insn specified by OPNUM and TYPE,
5001 may be used to load VALUE into it.
5003 MODE is the mode in which the register is used, this is needed to
5004 determine how many hard regs to test.
5006 Other read-only reloads with the same value do not conflict
5007 unless OUT is nonzero and these other reloads have to live while
5008 output reloads live.
5009 If OUT is CONST0_RTX, this is a special case: it means that the
5010 test should not be for using register REGNO as reload register, but
5011 for copying from register REGNO into the reload register.
5013 RELOADNUM is the number of the reload we want to load this value for;
5014 a reload does not conflict with itself.
5016 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5017 reloads that load an address for the very reload we are considering.
5019 The caller has to make sure that there is no conflict with the return
5023 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
5024 ignore_address_reloads)
5026 enum machine_mode mode;
5028 enum reload_type type;
5031 int ignore_address_reloads;
5033 int nregs = HARD_REGNO_NREGS (regno, mode);
5035 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5036 value, out, reloadnum,
5037 ignore_address_reloads))
5042 /* Determine whether the reload reg X overlaps any rtx'es used for
5043 overriding inheritance. Return nonzero if so. */
5046 conflicts_with_override (x)
5050 for (i = 0; i < n_reloads; i++)
5051 if (reload_override_in[i]
5052 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5057 /* Give an error message saying we failed to find a reload for INSN,
5058 and clear out reload R. */
5060 failed_reload (insn, r)
5064 if (asm_noperands (PATTERN (insn)) < 0)
5065 /* It's the compiler's fault. */
5066 fatal_insn ("could not find a spill register", insn);
5068 /* It's the user's fault; the operand's mode and constraint
5069 don't match. Disable this reload so we don't crash in final. */
5070 error_for_asm (insn,
5071 "`asm' operand constraint incompatible with operand size");
5075 rld[r].optional = 1;
5076 rld[r].secondary_p = 1;
5079 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5080 for reload R. If it's valid, get an rtx for it. Return nonzero if
5083 set_reload_reg (i, r)
5087 rtx reg = spill_reg_rtx[i];
5089 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5090 spill_reg_rtx[i] = reg
5091 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5093 regno = true_regnum (reg);
5095 /* Detect when the reload reg can't hold the reload mode.
5096 This used to be one `if', but Sequent compiler can't handle that. */
5097 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5099 enum machine_mode test_mode = VOIDmode;
5101 test_mode = GET_MODE (rld[r].in);
5102 /* If rld[r].in has VOIDmode, it means we will load it
5103 in whatever mode the reload reg has: to wit, rld[r].mode.
5104 We have already tested that for validity. */
5105 /* Aside from that, we need to test that the expressions
5106 to reload from or into have modes which are valid for this
5107 reload register. Otherwise the reload insns would be invalid. */
5108 if (! (rld[r].in != 0 && test_mode != VOIDmode
5109 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5110 if (! (rld[r].out != 0
5111 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5113 /* The reg is OK. */
5116 /* Mark as in use for this insn the reload regs we use
5118 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5119 rld[r].when_needed, rld[r].mode);
5121 rld[r].reg_rtx = reg;
5122 reload_spill_index[r] = spill_regs[i];
5129 /* Find a spill register to use as a reload register for reload R.
5130 LAST_RELOAD is nonzero if this is the last reload for the insn being
5133 Set rld[R].reg_rtx to the register allocated.
5135 We return 1 if successful, or 0 if we couldn't find a spill reg and
5136 we didn't change anything. */
5139 allocate_reload_reg (chain, r, last_reload)
5140 struct insn_chain *chain ATTRIBUTE_UNUSED;
5146 /* If we put this reload ahead, thinking it is a group,
5147 then insist on finding a group. Otherwise we can grab a
5148 reg that some other reload needs.
5149 (That can happen when we have a 68000 DATA_OR_FP_REG
5150 which is a group of data regs or one fp reg.)
5151 We need not be so restrictive if there are no more reloads
5154 ??? Really it would be nicer to have smarter handling
5155 for that kind of reg class, where a problem like this is normal.
5156 Perhaps those classes should be avoided for reloading
5157 by use of more alternatives. */
5159 int force_group = rld[r].nregs > 1 && ! last_reload;
5161 /* If we want a single register and haven't yet found one,
5162 take any reg in the right class and not in use.
5163 If we want a consecutive group, here is where we look for it.
5165 We use two passes so we can first look for reload regs to
5166 reuse, which are already in use for other reloads in this insn,
5167 and only then use additional registers.
5168 I think that maximizing reuse is needed to make sure we don't
5169 run out of reload regs. Suppose we have three reloads, and
5170 reloads A and B can share regs. These need two regs.
5171 Suppose A and B are given different regs.
5172 That leaves none for C. */
5173 for (pass = 0; pass < 2; pass++)
5175 /* I is the index in spill_regs.
5176 We advance it round-robin between insns to use all spill regs
5177 equally, so that inherited reloads have a chance
5178 of leapfrogging each other. */
5182 for (count = 0; count < n_spills; count++)
5184 int class = (int) rld[r].class;
5190 regnum = spill_regs[i];
5192 if ((reload_reg_free_p (regnum, rld[r].opnum,
5195 /* We check reload_reg_used to make sure we
5196 don't clobber the return register. */
5197 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5198 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5199 rld[r].when_needed, rld[r].in,
5201 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5202 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5203 /* Look first for regs to share, then for unshared. But
5204 don't share regs used for inherited reloads; they are
5205 the ones we want to preserve. */
5207 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5209 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5212 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5213 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5214 (on 68000) got us two FP regs. If NR is 1,
5215 we would reject both of them. */
5218 /* If we need only one reg, we have already won. */
5221 /* But reject a single reg if we demand a group. */
5226 /* Otherwise check that as many consecutive regs as we need
5227 are available here. */
5230 int regno = regnum + nr - 1;
5231 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5232 && spill_reg_order[regno] >= 0
5233 && reload_reg_free_p (regno, rld[r].opnum,
5234 rld[r].when_needed)))
5243 /* If we found something on pass 1, omit pass 2. */
5244 if (count < n_spills)
5248 /* We should have found a spill register by now. */
5249 if (count >= n_spills)
5252 /* I is the index in SPILL_REG_RTX of the reload register we are to
5253 allocate. Get an rtx for it and find its register number. */
5255 return set_reload_reg (i, r);
5258 /* Initialize all the tables needed to allocate reload registers.
5259 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5260 is the array we use to restore the reg_rtx field for every reload. */
5263 choose_reload_regs_init (chain, save_reload_reg_rtx)
5264 struct insn_chain *chain;
5265 rtx *save_reload_reg_rtx;
5269 for (i = 0; i < n_reloads; i++)
5270 rld[i].reg_rtx = save_reload_reg_rtx[i];
5272 memset (reload_inherited, 0, MAX_RELOADS);
5273 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5274 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5276 CLEAR_HARD_REG_SET (reload_reg_used);
5277 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5278 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5279 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5280 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5281 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5283 CLEAR_HARD_REG_SET (reg_used_in_insn);
5286 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5287 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5288 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5289 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5290 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5291 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5294 for (i = 0; i < reload_n_operands; i++)
5296 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5297 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5298 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5299 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5300 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5301 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5304 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5306 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5308 for (i = 0; i < n_reloads; i++)
5309 /* If we have already decided to use a certain register,
5310 don't use it in another way. */
5312 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5313 rld[i].when_needed, rld[i].mode);
5316 /* Assign hard reg targets for the pseudo-registers we must reload
5317 into hard regs for this insn.
5318 Also output the instructions to copy them in and out of the hard regs.
5320 For machines with register classes, we are responsible for
5321 finding a reload reg in the proper class. */
5324 choose_reload_regs (chain)
5325 struct insn_chain *chain;
5327 rtx insn = chain->insn;
5329 unsigned int max_group_size = 1;
5330 enum reg_class group_class = NO_REGS;
5331 int pass, win, inheritance;
5333 rtx save_reload_reg_rtx[MAX_RELOADS];
5335 /* In order to be certain of getting the registers we need,
5336 we must sort the reloads into order of increasing register class.
5337 Then our grabbing of reload registers will parallel the process
5338 that provided the reload registers.
5340 Also note whether any of the reloads wants a consecutive group of regs.
5341 If so, record the maximum size of the group desired and what
5342 register class contains all the groups needed by this insn. */
5344 for (j = 0; j < n_reloads; j++)
5346 reload_order[j] = j;
5347 reload_spill_index[j] = -1;
5349 if (rld[j].nregs > 1)
5351 max_group_size = MAX (rld[j].nregs, max_group_size);
5353 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5356 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5360 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5362 /* If -O, try first with inheritance, then turning it off.
5363 If not -O, don't do inheritance.
5364 Using inheritance when not optimizing leads to paradoxes
5365 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5366 because one side of the comparison might be inherited. */
5368 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5370 choose_reload_regs_init (chain, save_reload_reg_rtx);
5372 /* Process the reloads in order of preference just found.
5373 Beyond this point, subregs can be found in reload_reg_rtx.
5375 This used to look for an existing reloaded home for all of the
5376 reloads, and only then perform any new reloads. But that could lose
5377 if the reloads were done out of reg-class order because a later
5378 reload with a looser constraint might have an old home in a register
5379 needed by an earlier reload with a tighter constraint.
5381 To solve this, we make two passes over the reloads, in the order
5382 described above. In the first pass we try to inherit a reload
5383 from a previous insn. If there is a later reload that needs a
5384 class that is a proper subset of the class being processed, we must
5385 also allocate a spill register during the first pass.
5387 Then make a second pass over the reloads to allocate any reloads
5388 that haven't been given registers yet. */
5390 for (j = 0; j < n_reloads; j++)
5392 int r = reload_order[j];
5393 rtx search_equiv = NULL_RTX;
5395 /* Ignore reloads that got marked inoperative. */
5396 if (rld[r].out == 0 && rld[r].in == 0
5397 && ! rld[r].secondary_p)
5400 /* If find_reloads chose to use reload_in or reload_out as a reload
5401 register, we don't need to chose one. Otherwise, try even if it
5402 found one since we might save an insn if we find the value lying
5404 Try also when reload_in is a pseudo without a hard reg. */
5405 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5406 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5407 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5408 && GET_CODE (rld[r].in) != MEM
5409 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5412 #if 0 /* No longer needed for correct operation.
5413 It might give better code, or might not; worth an experiment? */
5414 /* If this is an optional reload, we can't inherit from earlier insns
5415 until we are sure that any non-optional reloads have been allocated.
5416 The following code takes advantage of the fact that optional reloads
5417 are at the end of reload_order. */
5418 if (rld[r].optional != 0)
5419 for (i = 0; i < j; i++)
5420 if ((rld[reload_order[i]].out != 0
5421 || rld[reload_order[i]].in != 0
5422 || rld[reload_order[i]].secondary_p)
5423 && ! rld[reload_order[i]].optional
5424 && rld[reload_order[i]].reg_rtx == 0)
5425 allocate_reload_reg (chain, reload_order[i], 0);
5428 /* First see if this pseudo is already available as reloaded
5429 for a previous insn. We cannot try to inherit for reloads
5430 that are smaller than the maximum number of registers needed
5431 for groups unless the register we would allocate cannot be used
5434 We could check here to see if this is a secondary reload for
5435 an object that is already in a register of the desired class.
5436 This would avoid the need for the secondary reload register.
5437 But this is complex because we can't easily determine what
5438 objects might want to be loaded via this reload. So let a
5439 register be allocated here. In `emit_reload_insns' we suppress
5440 one of the loads in the case described above. */
5446 enum machine_mode mode = VOIDmode;
5450 else if (GET_CODE (rld[r].in) == REG)
5452 regno = REGNO (rld[r].in);
5453 mode = GET_MODE (rld[r].in);
5455 else if (GET_CODE (rld[r].in_reg) == REG)
5457 regno = REGNO (rld[r].in_reg);
5458 mode = GET_MODE (rld[r].in_reg);
5460 else if (GET_CODE (rld[r].in_reg) == SUBREG
5461 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5463 byte = SUBREG_BYTE (rld[r].in_reg);
5464 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5465 if (regno < FIRST_PSEUDO_REGISTER)
5466 regno = subreg_regno (rld[r].in_reg);
5467 mode = GET_MODE (rld[r].in_reg);
5470 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5471 || GET_CODE (rld[r].in_reg) == PRE_DEC
5472 || GET_CODE (rld[r].in_reg) == POST_INC
5473 || GET_CODE (rld[r].in_reg) == POST_DEC)
5474 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5476 regno = REGNO (XEXP (rld[r].in_reg, 0));
5477 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5478 rld[r].out = rld[r].in;
5482 /* This won't work, since REGNO can be a pseudo reg number.
5483 Also, it takes much more hair to keep track of all the things
5484 that can invalidate an inherited reload of part of a pseudoreg. */
5485 else if (GET_CODE (rld[r].in) == SUBREG
5486 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5487 regno = subreg_regno (rld[r].in);
5490 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5492 enum reg_class class = rld[r].class, last_class;
5493 rtx last_reg = reg_last_reload_reg[regno];
5494 enum machine_mode need_mode;
5496 i = REGNO (last_reg);
5497 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5498 last_class = REGNO_REG_CLASS (i);
5504 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5505 GET_MODE_CLASS (mode));
5508 #ifdef CANNOT_CHANGE_MODE_CLASS
5509 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5513 (GET_MODE_SIZE (GET_MODE (last_reg))
5514 >= GET_MODE_SIZE (need_mode))
5515 #ifdef CANNOT_CHANGE_MODE_CLASS
5518 && reg_reloaded_contents[i] == regno
5519 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5520 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5521 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5522 /* Even if we can't use this register as a reload
5523 register, we might use it for reload_override_in,
5524 if copying it to the desired class is cheap
5526 || ((REGISTER_MOVE_COST (mode, last_class, class)
5527 < MEMORY_MOVE_COST (mode, class, 1))
5528 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5529 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5533 #ifdef SECONDARY_MEMORY_NEEDED
5534 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5539 && (rld[r].nregs == max_group_size
5540 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5542 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5543 rld[r].when_needed, rld[r].in,
5546 /* If a group is needed, verify that all the subsequent
5547 registers still have their values intact. */
5548 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5551 for (k = 1; k < nr; k++)
5552 if (reg_reloaded_contents[i + k] != regno
5553 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5561 last_reg = (GET_MODE (last_reg) == mode
5562 ? last_reg : gen_rtx_REG (mode, i));
5565 for (k = 0; k < nr; k++)
5566 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5569 /* We found a register that contains the
5570 value we need. If this register is the
5571 same as an `earlyclobber' operand of the
5572 current insn, just mark it as a place to
5573 reload from since we can't use it as the
5574 reload register itself. */
5576 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5577 if (reg_overlap_mentioned_for_reload_p
5578 (reg_last_reload_reg[regno],
5579 reload_earlyclobbers[i1]))
5582 if (i1 != n_earlyclobbers
5583 || ! (free_for_value_p (i, rld[r].mode,
5585 rld[r].when_needed, rld[r].in,
5587 /* Don't use it if we'd clobber a pseudo reg. */
5588 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5590 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5591 /* Don't clobber the frame pointer. */
5592 || (i == HARD_FRAME_POINTER_REGNUM
5593 && frame_pointer_needed
5595 /* Don't really use the inherited spill reg
5596 if we need it wider than we've got it. */
5597 || (GET_MODE_SIZE (rld[r].mode)
5598 > GET_MODE_SIZE (mode))
5601 /* If find_reloads chose reload_out as reload
5602 register, stay with it - that leaves the
5603 inherited register for subsequent reloads. */
5604 || (rld[r].out && rld[r].reg_rtx
5605 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5607 if (! rld[r].optional)
5609 reload_override_in[r] = last_reg;
5610 reload_inheritance_insn[r]
5611 = reg_reloaded_insn[i];
5617 /* We can use this as a reload reg. */
5618 /* Mark the register as in use for this part of
5620 mark_reload_reg_in_use (i,
5624 rld[r].reg_rtx = last_reg;
5625 reload_inherited[r] = 1;
5626 reload_inheritance_insn[r]
5627 = reg_reloaded_insn[i];
5628 reload_spill_index[r] = i;
5629 for (k = 0; k < nr; k++)
5630 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5638 /* Here's another way to see if the value is already lying around. */
5641 && ! reload_inherited[r]
5643 && (CONSTANT_P (rld[r].in)
5644 || GET_CODE (rld[r].in) == PLUS
5645 || GET_CODE (rld[r].in) == REG
5646 || GET_CODE (rld[r].in) == MEM)
5647 && (rld[r].nregs == max_group_size
5648 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5649 search_equiv = rld[r].in;
5650 /* If this is an output reload from a simple move insn, look
5651 if an equivalence for the input is available. */
5652 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5654 rtx set = single_set (insn);
5657 && rtx_equal_p (rld[r].out, SET_DEST (set))
5658 && CONSTANT_P (SET_SRC (set)))
5659 search_equiv = SET_SRC (set);
5665 = find_equiv_reg (search_equiv, insn, rld[r].class,
5666 -1, NULL, 0, rld[r].mode);
5671 if (GET_CODE (equiv) == REG)
5672 regno = REGNO (equiv);
5673 else if (GET_CODE (equiv) == SUBREG)
5675 /* This must be a SUBREG of a hard register.
5676 Make a new REG since this might be used in an
5677 address and not all machines support SUBREGs
5679 regno = subreg_regno (equiv);
5680 equiv = gen_rtx_REG (rld[r].mode, regno);
5686 /* If we found a spill reg, reject it unless it is free
5687 and of the desired class. */
5691 int bad_for_class = 0;
5692 int max_regno = regno + rld[r].nregs;
5694 for (i = regno; i < max_regno; i++)
5696 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5698 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5703 && ! free_for_value_p (regno, rld[r].mode,
5704 rld[r].opnum, rld[r].when_needed,
5705 rld[r].in, rld[r].out, r, 1))
5710 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5713 /* We found a register that contains the value we need.
5714 If this register is the same as an `earlyclobber' operand
5715 of the current insn, just mark it as a place to reload from
5716 since we can't use it as the reload register itself. */
5719 for (i = 0; i < n_earlyclobbers; i++)
5720 if (reg_overlap_mentioned_for_reload_p (equiv,
5721 reload_earlyclobbers[i]))
5723 if (! rld[r].optional)
5724 reload_override_in[r] = equiv;
5729 /* If the equiv register we have found is explicitly clobbered
5730 in the current insn, it depends on the reload type if we
5731 can use it, use it for reload_override_in, or not at all.
5732 In particular, we then can't use EQUIV for a
5733 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5737 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5738 switch (rld[r].when_needed)
5740 case RELOAD_FOR_OTHER_ADDRESS:
5741 case RELOAD_FOR_INPADDR_ADDRESS:
5742 case RELOAD_FOR_INPUT_ADDRESS:
5743 case RELOAD_FOR_OPADDR_ADDR:
5746 case RELOAD_FOR_INPUT:
5747 case RELOAD_FOR_OPERAND_ADDRESS:
5748 if (! rld[r].optional)
5749 reload_override_in[r] = equiv;
5755 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5756 switch (rld[r].when_needed)
5758 case RELOAD_FOR_OTHER_ADDRESS:
5759 case RELOAD_FOR_INPADDR_ADDRESS:
5760 case RELOAD_FOR_INPUT_ADDRESS:
5761 case RELOAD_FOR_OPADDR_ADDR:
5762 case RELOAD_FOR_OPERAND_ADDRESS:
5763 case RELOAD_FOR_INPUT:
5766 if (! rld[r].optional)
5767 reload_override_in[r] = equiv;
5775 /* If we found an equivalent reg, say no code need be generated
5776 to load it, and use it as our reload reg. */
5778 && (regno != HARD_FRAME_POINTER_REGNUM
5779 || !frame_pointer_needed))
5781 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5783 rld[r].reg_rtx = equiv;
5784 reload_inherited[r] = 1;
5786 /* If reg_reloaded_valid is not set for this register,
5787 there might be a stale spill_reg_store lying around.
5788 We must clear it, since otherwise emit_reload_insns
5789 might delete the store. */
5790 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5791 spill_reg_store[regno] = NULL_RTX;
5792 /* If any of the hard registers in EQUIV are spill
5793 registers, mark them as in use for this insn. */
5794 for (k = 0; k < nr; k++)
5796 i = spill_reg_order[regno + k];
5799 mark_reload_reg_in_use (regno, rld[r].opnum,
5802 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5809 /* If we found a register to use already, or if this is an optional
5810 reload, we are done. */
5811 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5815 /* No longer needed for correct operation. Might or might
5816 not give better code on the average. Want to experiment? */
5818 /* See if there is a later reload that has a class different from our
5819 class that intersects our class or that requires less register
5820 than our reload. If so, we must allocate a register to this
5821 reload now, since that reload might inherit a previous reload
5822 and take the only available register in our class. Don't do this
5823 for optional reloads since they will force all previous reloads
5824 to be allocated. Also don't do this for reloads that have been
5827 for (i = j + 1; i < n_reloads; i++)
5829 int s = reload_order[i];
5831 if ((rld[s].in == 0 && rld[s].out == 0
5832 && ! rld[s].secondary_p)
5836 if ((rld[s].class != rld[r].class
5837 && reg_classes_intersect_p (rld[r].class,
5839 || rld[s].nregs < rld[r].nregs)
5846 allocate_reload_reg (chain, r, j == n_reloads - 1);
5850 /* Now allocate reload registers for anything non-optional that
5851 didn't get one yet. */
5852 for (j = 0; j < n_reloads; j++)
5854 int r = reload_order[j];
5856 /* Ignore reloads that got marked inoperative. */
5857 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5860 /* Skip reloads that already have a register allocated or are
5862 if (rld[r].reg_rtx != 0 || rld[r].optional)
5865 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5869 /* If that loop got all the way, we have won. */
5876 /* Loop around and try without any inheritance. */
5881 /* First undo everything done by the failed attempt
5882 to allocate with inheritance. */
5883 choose_reload_regs_init (chain, save_reload_reg_rtx);
5885 /* Some sanity tests to verify that the reloads found in the first
5886 pass are identical to the ones we have now. */
5887 if (chain->n_reloads != n_reloads)
5890 for (i = 0; i < n_reloads; i++)
5892 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5894 if (chain->rld[i].when_needed != rld[i].when_needed)
5896 for (j = 0; j < n_spills; j++)
5897 if (spill_regs[j] == chain->rld[i].regno)
5898 if (! set_reload_reg (j, i))
5899 failed_reload (chain->insn, i);
5903 /* If we thought we could inherit a reload, because it seemed that
5904 nothing else wanted the same reload register earlier in the insn,
5905 verify that assumption, now that all reloads have been assigned.
5906 Likewise for reloads where reload_override_in has been set. */
5908 /* If doing expensive optimizations, do one preliminary pass that doesn't
5909 cancel any inheritance, but removes reloads that have been needed only
5910 for reloads that we know can be inherited. */
5911 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5913 for (j = 0; j < n_reloads; j++)
5915 int r = reload_order[j];
5917 if (reload_inherited[r] && rld[r].reg_rtx)
5918 check_reg = rld[r].reg_rtx;
5919 else if (reload_override_in[r]
5920 && (GET_CODE (reload_override_in[r]) == REG
5921 || GET_CODE (reload_override_in[r]) == SUBREG))
5922 check_reg = reload_override_in[r];
5925 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5926 rld[r].opnum, rld[r].when_needed, rld[r].in,
5927 (reload_inherited[r]
5928 ? rld[r].out : const0_rtx),
5933 reload_inherited[r] = 0;
5934 reload_override_in[r] = 0;
5936 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5937 reload_override_in, then we do not need its related
5938 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5939 likewise for other reload types.
5940 We handle this by removing a reload when its only replacement
5941 is mentioned in reload_in of the reload we are going to inherit.
5942 A special case are auto_inc expressions; even if the input is
5943 inherited, we still need the address for the output. We can
5944 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5945 If we succeeded removing some reload and we are doing a preliminary
5946 pass just to remove such reloads, make another pass, since the
5947 removal of one reload might allow us to inherit another one. */
5949 && rld[r].out != rld[r].in
5950 && remove_address_replacements (rld[r].in) && pass)
5955 /* Now that reload_override_in is known valid,
5956 actually override reload_in. */
5957 for (j = 0; j < n_reloads; j++)
5958 if (reload_override_in[j])
5959 rld[j].in = reload_override_in[j];
5961 /* If this reload won't be done because it has been canceled or is
5962 optional and not inherited, clear reload_reg_rtx so other
5963 routines (such as subst_reloads) don't get confused. */
5964 for (j = 0; j < n_reloads; j++)
5965 if (rld[j].reg_rtx != 0
5966 && ((rld[j].optional && ! reload_inherited[j])
5967 || (rld[j].in == 0 && rld[j].out == 0
5968 && ! rld[j].secondary_p)))
5970 int regno = true_regnum (rld[j].reg_rtx);
5972 if (spill_reg_order[regno] >= 0)
5973 clear_reload_reg_in_use (regno, rld[j].opnum,
5974 rld[j].when_needed, rld[j].mode);
5976 reload_spill_index[j] = -1;
5979 /* Record which pseudos and which spill regs have output reloads. */
5980 for (j = 0; j < n_reloads; j++)
5982 int r = reload_order[j];
5984 i = reload_spill_index[r];
5986 /* I is nonneg if this reload uses a register.
5987 If rld[r].reg_rtx is 0, this is an optional reload
5988 that we opted to ignore. */
5989 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5990 && rld[r].reg_rtx != 0)
5992 int nregno = REGNO (rld[r].out_reg);
5995 if (nregno < FIRST_PSEUDO_REGISTER)
5996 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5999 reg_has_output_reload[nregno + nr] = 1;
6003 nr = HARD_REGNO_NREGS (i, rld[r].mode);
6005 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6008 if (rld[r].when_needed != RELOAD_OTHER
6009 && rld[r].when_needed != RELOAD_FOR_OUTPUT
6010 && rld[r].when_needed != RELOAD_FOR_INSN)
6016 /* Deallocate the reload register for reload R. This is called from
6017 remove_address_replacements. */
6020 deallocate_reload_reg (r)
6025 if (! rld[r].reg_rtx)
6027 regno = true_regnum (rld[r].reg_rtx);
6029 if (spill_reg_order[regno] >= 0)
6030 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6032 reload_spill_index[r] = -1;
6035 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6036 reloads of the same item for fear that we might not have enough reload
6037 registers. However, normally they will get the same reload register
6038 and hence actually need not be loaded twice.
6040 Here we check for the most common case of this phenomenon: when we have
6041 a number of reloads for the same object, each of which were allocated
6042 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6043 reload, and is not modified in the insn itself. If we find such,
6044 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6045 This will not increase the number of spill registers needed and will
6046 prevent redundant code. */
6049 merge_assigned_reloads (insn)
6054 /* Scan all the reloads looking for ones that only load values and
6055 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6056 assigned and not modified by INSN. */
6058 for (i = 0; i < n_reloads; i++)
6060 int conflicting_input = 0;
6061 int max_input_address_opnum = -1;
6062 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6064 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6065 || rld[i].out != 0 || rld[i].reg_rtx == 0
6066 || reg_set_p (rld[i].reg_rtx, insn))
6069 /* Look at all other reloads. Ensure that the only use of this
6070 reload_reg_rtx is in a reload that just loads the same value
6071 as we do. Note that any secondary reloads must be of the identical
6072 class since the values, modes, and result registers are the
6073 same, so we need not do anything with any secondary reloads. */
6075 for (j = 0; j < n_reloads; j++)
6077 if (i == j || rld[j].reg_rtx == 0
6078 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6082 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6083 && rld[j].opnum > max_input_address_opnum)
6084 max_input_address_opnum = rld[j].opnum;
6086 /* If the reload regs aren't exactly the same (e.g, different modes)
6087 or if the values are different, we can't merge this reload.
6088 But if it is an input reload, we might still merge
6089 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6091 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6092 || rld[j].out != 0 || rld[j].in == 0
6093 || ! rtx_equal_p (rld[i].in, rld[j].in))
6095 if (rld[j].when_needed != RELOAD_FOR_INPUT
6096 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6097 || rld[i].opnum > rld[j].opnum)
6098 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6100 conflicting_input = 1;
6101 if (min_conflicting_input_opnum > rld[j].opnum)
6102 min_conflicting_input_opnum = rld[j].opnum;
6106 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6107 we, in fact, found any matching reloads. */
6110 && max_input_address_opnum <= min_conflicting_input_opnum)
6112 for (j = 0; j < n_reloads; j++)
6113 if (i != j && rld[j].reg_rtx != 0
6114 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6115 && (! conflicting_input
6116 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6117 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6119 rld[i].when_needed = RELOAD_OTHER;
6121 reload_spill_index[j] = -1;
6122 transfer_replacements (i, j);
6125 /* If this is now RELOAD_OTHER, look for any reloads that load
6126 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6127 if they were for inputs, RELOAD_OTHER for outputs. Note that
6128 this test is equivalent to looking for reloads for this operand
6130 /* We must take special care when there are two or more reloads to
6131 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6132 same value or a part of it; we must not change its type if there
6133 is a conflicting input. */
6135 if (rld[i].when_needed == RELOAD_OTHER)
6136 for (j = 0; j < n_reloads; j++)
6138 && rld[j].when_needed != RELOAD_OTHER
6139 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6140 && (! conflicting_input
6141 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6142 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6143 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6149 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6150 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6151 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6153 /* Check to see if we accidentally converted two reloads
6154 that use the same reload register with different inputs
6155 to the same type. If so, the resulting code won't work,
6158 for (k = 0; k < j; k++)
6159 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6160 && rld[k].when_needed == rld[j].when_needed
6161 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6162 && ! rtx_equal_p (rld[k].in, rld[j].in))
6169 /* These arrays are filled by emit_reload_insns and its subroutines. */
6170 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6171 static rtx other_input_address_reload_insns = 0;
6172 static rtx other_input_reload_insns = 0;
6173 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6174 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6175 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6176 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6177 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6178 static rtx operand_reload_insns = 0;
6179 static rtx other_operand_reload_insns = 0;
6180 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6182 /* Values to be put in spill_reg_store are put here first. */
6183 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6184 static HARD_REG_SET reg_reloaded_died;
6186 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6187 has the number J. OLD contains the value to be used as input. */
6190 emit_input_reload_insns (chain, rl, old, j)
6191 struct insn_chain *chain;
6196 rtx insn = chain->insn;
6197 rtx reloadreg = rl->reg_rtx;
6198 rtx oldequiv_reg = 0;
6201 enum machine_mode mode;
6204 /* Determine the mode to reload in.
6205 This is very tricky because we have three to choose from.
6206 There is the mode the insn operand wants (rl->inmode).
6207 There is the mode of the reload register RELOADREG.
6208 There is the intrinsic mode of the operand, which we could find
6209 by stripping some SUBREGs.
6210 It turns out that RELOADREG's mode is irrelevant:
6211 we can change that arbitrarily.
6213 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6214 then the reload reg may not support QImode moves, so use SImode.
6215 If foo is in memory due to spilling a pseudo reg, this is safe,
6216 because the QImode value is in the least significant part of a
6217 slot big enough for a SImode. If foo is some other sort of
6218 memory reference, then it is impossible to reload this case,
6219 so previous passes had better make sure this never happens.
6221 Then consider a one-word union which has SImode and one of its
6222 members is a float, being fetched as (SUBREG:SF union:SI).
6223 We must fetch that as SFmode because we could be loading into
6224 a float-only register. In this case OLD's mode is correct.
6226 Consider an immediate integer: it has VOIDmode. Here we need
6227 to get a mode from something else.
6229 In some cases, there is a fourth mode, the operand's
6230 containing mode. If the insn specifies a containing mode for
6231 this operand, it overrides all others.
6233 I am not sure whether the algorithm here is always right,
6234 but it does the right things in those cases. */
6236 mode = GET_MODE (old);
6237 if (mode == VOIDmode)
6240 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6241 /* If we need a secondary register for this operation, see if
6242 the value is already in a register in that class. Don't
6243 do this if the secondary register will be used as a scratch
6246 if (rl->secondary_in_reload >= 0
6247 && rl->secondary_in_icode == CODE_FOR_nothing
6250 = find_equiv_reg (old, insn,
6251 rld[rl->secondary_in_reload].class,
6255 /* If reloading from memory, see if there is a register
6256 that already holds the same value. If so, reload from there.
6257 We can pass 0 as the reload_reg_p argument because
6258 any other reload has either already been emitted,
6259 in which case find_equiv_reg will see the reload-insn,
6260 or has yet to be emitted, in which case it doesn't matter
6261 because we will use this equiv reg right away. */
6263 if (oldequiv == 0 && optimize
6264 && (GET_CODE (old) == MEM
6265 || (GET_CODE (old) == REG
6266 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6267 && reg_renumber[REGNO (old)] < 0)))
6268 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6272 unsigned int regno = true_regnum (oldequiv);
6274 /* Don't use OLDEQUIV if any other reload changes it at an
6275 earlier stage of this insn or at this stage. */
6276 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6277 rl->in, const0_rtx, j, 0))
6280 /* If it is no cheaper to copy from OLDEQUIV into the
6281 reload register than it would be to move from memory,
6282 don't use it. Likewise, if we need a secondary register
6286 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6287 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6289 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6290 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6291 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6295 #ifdef SECONDARY_MEMORY_NEEDED
6296 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6304 /* delete_output_reload is only invoked properly if old contains
6305 the original pseudo register. Since this is replaced with a
6306 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6307 find the pseudo in RELOAD_IN_REG. */
6309 && reload_override_in[j]
6310 && GET_CODE (rl->in_reg) == REG)
6317 else if (GET_CODE (oldequiv) == REG)
6318 oldequiv_reg = oldequiv;
6319 else if (GET_CODE (oldequiv) == SUBREG)
6320 oldequiv_reg = SUBREG_REG (oldequiv);
6322 /* If we are reloading from a register that was recently stored in
6323 with an output-reload, see if we can prove there was
6324 actually no need to store the old value in it. */
6326 if (optimize && GET_CODE (oldequiv) == REG
6327 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6328 && spill_reg_store[REGNO (oldequiv)]
6329 && GET_CODE (old) == REG
6330 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6331 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6333 delete_output_reload (insn, j, REGNO (oldequiv));
6335 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6336 then load RELOADREG from OLDEQUIV. Note that we cannot use
6337 gen_lowpart_common since it can do the wrong thing when
6338 RELOADREG has a multi-word mode. Note that RELOADREG
6339 must always be a REG here. */
6341 if (GET_MODE (reloadreg) != mode)
6342 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6343 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6344 oldequiv = SUBREG_REG (oldequiv);
6345 if (GET_MODE (oldequiv) != VOIDmode
6346 && mode != GET_MODE (oldequiv))
6347 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6349 /* Switch to the right place to emit the reload insns. */
6350 switch (rl->when_needed)
6353 where = &other_input_reload_insns;
6355 case RELOAD_FOR_INPUT:
6356 where = &input_reload_insns[rl->opnum];
6358 case RELOAD_FOR_INPUT_ADDRESS:
6359 where = &input_address_reload_insns[rl->opnum];
6361 case RELOAD_FOR_INPADDR_ADDRESS:
6362 where = &inpaddr_address_reload_insns[rl->opnum];
6364 case RELOAD_FOR_OUTPUT_ADDRESS:
6365 where = &output_address_reload_insns[rl->opnum];
6367 case RELOAD_FOR_OUTADDR_ADDRESS:
6368 where = &outaddr_address_reload_insns[rl->opnum];
6370 case RELOAD_FOR_OPERAND_ADDRESS:
6371 where = &operand_reload_insns;
6373 case RELOAD_FOR_OPADDR_ADDR:
6374 where = &other_operand_reload_insns;
6376 case RELOAD_FOR_OTHER_ADDRESS:
6377 where = &other_input_address_reload_insns;
6383 push_to_sequence (*where);
6385 /* Auto-increment addresses must be reloaded in a special way. */
6386 if (rl->out && ! rl->out_reg)
6388 /* We are not going to bother supporting the case where a
6389 incremented register can't be copied directly from
6390 OLDEQUIV since this seems highly unlikely. */
6391 if (rl->secondary_in_reload >= 0)
6394 if (reload_inherited[j])
6395 oldequiv = reloadreg;
6397 old = XEXP (rl->in_reg, 0);
6399 if (optimize && GET_CODE (oldequiv) == REG
6400 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6401 && spill_reg_store[REGNO (oldequiv)]
6402 && GET_CODE (old) == REG
6403 && (dead_or_set_p (insn,
6404 spill_reg_stored_to[REGNO (oldequiv)])
6405 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6407 delete_output_reload (insn, j, REGNO (oldequiv));
6409 /* Prevent normal processing of this reload. */
6411 /* Output a special code sequence for this case. */
6412 new_spill_reg_store[REGNO (reloadreg)]
6413 = inc_for_reload (reloadreg, oldequiv, rl->out,
6417 /* If we are reloading a pseudo-register that was set by the previous
6418 insn, see if we can get rid of that pseudo-register entirely
6419 by redirecting the previous insn into our reload register. */
6421 else if (optimize && GET_CODE (old) == REG
6422 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6423 && dead_or_set_p (insn, old)
6424 /* This is unsafe if some other reload
6425 uses the same reg first. */
6426 && ! conflicts_with_override (reloadreg)
6427 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6428 rl->when_needed, old, rl->out, j, 0))
6430 rtx temp = PREV_INSN (insn);
6431 while (temp && GET_CODE (temp) == NOTE)
6432 temp = PREV_INSN (temp);
6434 && GET_CODE (temp) == INSN
6435 && GET_CODE (PATTERN (temp)) == SET
6436 && SET_DEST (PATTERN (temp)) == old
6437 /* Make sure we can access insn_operand_constraint. */
6438 && asm_noperands (PATTERN (temp)) < 0
6439 /* This is unsafe if operand occurs more than once in current
6440 insn. Perhaps some occurrences aren't reloaded. */
6441 && count_occurrences (PATTERN (insn), old, 0) == 1)
6443 rtx old = SET_DEST (PATTERN (temp));
6444 /* Store into the reload register instead of the pseudo. */
6445 SET_DEST (PATTERN (temp)) = reloadreg;
6447 /* Verify that resulting insn is valid. */
6448 extract_insn (temp);
6449 if (constrain_operands (1))
6451 /* If the previous insn is an output reload, the source is
6452 a reload register, and its spill_reg_store entry will
6453 contain the previous destination. This is now
6455 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6456 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6458 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6459 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6462 /* If these are the only uses of the pseudo reg,
6463 pretend for GDB it lives in the reload reg we used. */
6464 if (REG_N_DEATHS (REGNO (old)) == 1
6465 && REG_N_SETS (REGNO (old)) == 1)
6467 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6468 alter_reg (REGNO (old), -1);
6474 SET_DEST (PATTERN (temp)) = old;
6479 /* We can't do that, so output an insn to load RELOADREG. */
6481 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6482 /* If we have a secondary reload, pick up the secondary register
6483 and icode, if any. If OLDEQUIV and OLD are different or
6484 if this is an in-out reload, recompute whether or not we
6485 still need a secondary register and what the icode should
6486 be. If we still need a secondary register and the class or
6487 icode is different, go back to reloading from OLD if using
6488 OLDEQUIV means that we got the wrong type of register. We
6489 cannot have different class or icode due to an in-out reload
6490 because we don't make such reloads when both the input and
6491 output need secondary reload registers. */
6493 if (! special && rl->secondary_in_reload >= 0)
6495 rtx second_reload_reg = 0;
6496 int secondary_reload = rl->secondary_in_reload;
6497 rtx real_oldequiv = oldequiv;
6500 enum insn_code icode;
6502 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6503 and similarly for OLD.
6504 See comments in get_secondary_reload in reload.c. */
6505 /* If it is a pseudo that cannot be replaced with its
6506 equivalent MEM, we must fall back to reload_in, which
6507 will have all the necessary substitutions registered.
6508 Likewise for a pseudo that can't be replaced with its
6509 equivalent constant.
6511 Take extra care for subregs of such pseudos. Note that
6512 we cannot use reg_equiv_mem in this case because it is
6513 not in the right mode. */
6516 if (GET_CODE (tmp) == SUBREG)
6517 tmp = SUBREG_REG (tmp);
6518 if (GET_CODE (tmp) == REG
6519 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6520 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6521 || reg_equiv_constant[REGNO (tmp)] != 0))
6523 if (! reg_equiv_mem[REGNO (tmp)]
6524 || num_not_at_initial_offset
6525 || GET_CODE (oldequiv) == SUBREG)
6526 real_oldequiv = rl->in;
6528 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6532 if (GET_CODE (tmp) == SUBREG)
6533 tmp = SUBREG_REG (tmp);
6534 if (GET_CODE (tmp) == REG
6535 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6536 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6537 || reg_equiv_constant[REGNO (tmp)] != 0))
6539 if (! reg_equiv_mem[REGNO (tmp)]
6540 || num_not_at_initial_offset
6541 || GET_CODE (old) == SUBREG)
6544 real_old = reg_equiv_mem[REGNO (tmp)];
6547 second_reload_reg = rld[secondary_reload].reg_rtx;
6548 icode = rl->secondary_in_icode;
6550 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6551 || (rl->in != 0 && rl->out != 0))
6553 enum reg_class new_class
6554 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6555 mode, real_oldequiv);
6557 if (new_class == NO_REGS)
6558 second_reload_reg = 0;
6561 enum insn_code new_icode;
6562 enum machine_mode new_mode;
6564 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6565 REGNO (second_reload_reg)))
6566 oldequiv = old, real_oldequiv = real_old;
6569 new_icode = reload_in_optab[(int) mode];
6570 if (new_icode != CODE_FOR_nothing
6571 && ((insn_data[(int) new_icode].operand[0].predicate
6572 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6574 || (insn_data[(int) new_icode].operand[1].predicate
6575 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6576 (real_oldequiv, mode)))))
6577 new_icode = CODE_FOR_nothing;
6579 if (new_icode == CODE_FOR_nothing)
6582 new_mode = insn_data[(int) new_icode].operand[2].mode;
6584 if (GET_MODE (second_reload_reg) != new_mode)
6586 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6588 oldequiv = old, real_oldequiv = real_old;
6591 = reload_adjust_reg_for_mode (second_reload_reg,
6598 /* If we still need a secondary reload register, check
6599 to see if it is being used as a scratch or intermediate
6600 register and generate code appropriately. If we need
6601 a scratch register, use REAL_OLDEQUIV since the form of
6602 the insn may depend on the actual address if it is
6605 if (second_reload_reg)
6607 if (icode != CODE_FOR_nothing)
6609 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6610 second_reload_reg));
6615 /* See if we need a scratch register to load the
6616 intermediate register (a tertiary reload). */
6617 enum insn_code tertiary_icode
6618 = rld[secondary_reload].secondary_in_icode;
6620 if (tertiary_icode != CODE_FOR_nothing)
6622 rtx third_reload_reg
6623 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6625 emit_insn ((GEN_FCN (tertiary_icode)
6626 (second_reload_reg, real_oldequiv,
6627 third_reload_reg)));
6630 gen_reload (second_reload_reg, real_oldequiv,
6634 oldequiv = second_reload_reg;
6640 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6642 rtx real_oldequiv = oldequiv;
6644 if ((GET_CODE (oldequiv) == REG
6645 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6646 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6647 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6648 || (GET_CODE (oldequiv) == SUBREG
6649 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6650 && (REGNO (SUBREG_REG (oldequiv))
6651 >= FIRST_PSEUDO_REGISTER)
6652 && ((reg_equiv_memory_loc
6653 [REGNO (SUBREG_REG (oldequiv))] != 0)
6654 || (reg_equiv_constant
6655 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6656 || (CONSTANT_P (oldequiv)
6657 && (PREFERRED_RELOAD_CLASS (oldequiv,
6658 REGNO_REG_CLASS (REGNO (reloadreg)))
6660 real_oldequiv = rl->in;
6661 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6665 if (flag_non_call_exceptions)
6666 copy_eh_notes (insn, get_insns ());
6668 /* End this sequence. */
6669 *where = get_insns ();
6672 /* Update reload_override_in so that delete_address_reloads_1
6673 can see the actual register usage. */
6675 reload_override_in[j] = oldequiv;
6678 /* Generate insns to for the output reload RL, which is for the insn described
6679 by CHAIN and has the number J. */
6681 emit_output_reload_insns (chain, rl, j)
6682 struct insn_chain *chain;
6686 rtx reloadreg = rl->reg_rtx;
6687 rtx insn = chain->insn;
6690 enum machine_mode mode = GET_MODE (old);
6693 if (rl->when_needed == RELOAD_OTHER)
6696 push_to_sequence (output_reload_insns[rl->opnum]);
6698 /* Determine the mode to reload in.
6699 See comments above (for input reloading). */
6701 if (mode == VOIDmode)
6703 /* VOIDmode should never happen for an output. */
6704 if (asm_noperands (PATTERN (insn)) < 0)
6705 /* It's the compiler's fault. */
6706 fatal_insn ("VOIDmode on an output", insn);
6707 error_for_asm (insn, "output operand is constant in `asm'");
6708 /* Prevent crash--use something we know is valid. */
6710 old = gen_rtx_REG (mode, REGNO (reloadreg));
6713 if (GET_MODE (reloadreg) != mode)
6714 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6716 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6718 /* If we need two reload regs, set RELOADREG to the intermediate
6719 one, since it will be stored into OLD. We might need a secondary
6720 register only for an input reload, so check again here. */
6722 if (rl->secondary_out_reload >= 0)
6726 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6727 && reg_equiv_mem[REGNO (old)] != 0)
6728 real_old = reg_equiv_mem[REGNO (old)];
6730 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6734 rtx second_reloadreg = reloadreg;
6735 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6737 /* See if RELOADREG is to be used as a scratch register
6738 or as an intermediate register. */
6739 if (rl->secondary_out_icode != CODE_FOR_nothing)
6741 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6742 (real_old, second_reloadreg, reloadreg)));
6747 /* See if we need both a scratch and intermediate reload
6750 int secondary_reload = rl->secondary_out_reload;
6751 enum insn_code tertiary_icode
6752 = rld[secondary_reload].secondary_out_icode;
6754 if (GET_MODE (reloadreg) != mode)
6755 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6757 if (tertiary_icode != CODE_FOR_nothing)
6760 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6763 /* Copy primary reload reg to secondary reload reg.
6764 (Note that these have been swapped above, then
6765 secondary reload reg to OLD using our insn.) */
6767 /* If REAL_OLD is a paradoxical SUBREG, remove it
6768 and try to put the opposite SUBREG on
6770 if (GET_CODE (real_old) == SUBREG
6771 && (GET_MODE_SIZE (GET_MODE (real_old))
6772 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6773 && 0 != (tem = gen_lowpart_common
6774 (GET_MODE (SUBREG_REG (real_old)),
6776 real_old = SUBREG_REG (real_old), reloadreg = tem;
6778 gen_reload (reloadreg, second_reloadreg,
6779 rl->opnum, rl->when_needed);
6780 emit_insn ((GEN_FCN (tertiary_icode)
6781 (real_old, reloadreg, third_reloadreg)));
6786 /* Copy between the reload regs here and then to
6789 gen_reload (reloadreg, second_reloadreg,
6790 rl->opnum, rl->when_needed);
6796 /* Output the last reload insn. */
6801 /* Don't output the last reload if OLD is not the dest of
6802 INSN and is in the src and is clobbered by INSN. */
6803 if (! flag_expensive_optimizations
6804 || GET_CODE (old) != REG
6805 || !(set = single_set (insn))
6806 || rtx_equal_p (old, SET_DEST (set))
6807 || !reg_mentioned_p (old, SET_SRC (set))
6808 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6809 gen_reload (old, reloadreg, rl->opnum,
6813 /* Look at all insns we emitted, just to be safe. */
6814 for (p = get_insns (); p; p = NEXT_INSN (p))
6817 rtx pat = PATTERN (p);
6819 /* If this output reload doesn't come from a spill reg,
6820 clear any memory of reloaded copies of the pseudo reg.
6821 If this output reload comes from a spill reg,
6822 reg_has_output_reload will make this do nothing. */
6823 note_stores (pat, forget_old_reloads_1, NULL);
6825 if (reg_mentioned_p (rl->reg_rtx, pat))
6827 rtx set = single_set (insn);
6828 if (reload_spill_index[j] < 0
6830 && SET_SRC (set) == rl->reg_rtx)
6832 int src = REGNO (SET_SRC (set));
6834 reload_spill_index[j] = src;
6835 SET_HARD_REG_BIT (reg_is_output_reload, src);
6836 if (find_regno_note (insn, REG_DEAD, src))
6837 SET_HARD_REG_BIT (reg_reloaded_died, src);
6839 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6841 int s = rl->secondary_out_reload;
6842 set = single_set (p);
6843 /* If this reload copies only to the secondary reload
6844 register, the secondary reload does the actual
6846 if (s >= 0 && set == NULL_RTX)
6847 /* We can't tell what function the secondary reload
6848 has and where the actual store to the pseudo is
6849 made; leave new_spill_reg_store alone. */
6852 && SET_SRC (set) == rl->reg_rtx
6853 && SET_DEST (set) == rld[s].reg_rtx)
6855 /* Usually the next instruction will be the
6856 secondary reload insn; if we can confirm
6857 that it is, setting new_spill_reg_store to
6858 that insn will allow an extra optimization. */
6859 rtx s_reg = rld[s].reg_rtx;
6860 rtx next = NEXT_INSN (p);
6861 rld[s].out = rl->out;
6862 rld[s].out_reg = rl->out_reg;
6863 set = single_set (next);
6864 if (set && SET_SRC (set) == s_reg
6865 && ! new_spill_reg_store[REGNO (s_reg)])
6867 SET_HARD_REG_BIT (reg_is_output_reload,
6869 new_spill_reg_store[REGNO (s_reg)] = next;
6873 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6878 if (rl->when_needed == RELOAD_OTHER)
6880 emit_insn (other_output_reload_insns[rl->opnum]);
6881 other_output_reload_insns[rl->opnum] = get_insns ();
6884 output_reload_insns[rl->opnum] = get_insns ();
6886 if (flag_non_call_exceptions)
6887 copy_eh_notes (insn, get_insns ());
6892 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6893 and has the number J. */
6895 do_input_reload (chain, rl, j)
6896 struct insn_chain *chain;
6900 rtx insn = chain->insn;
6901 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6902 ? rl->in_reg : rl->in);
6905 /* AUTO_INC reloads need to be handled even if inherited. We got an
6906 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6907 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6908 && ! rtx_equal_p (rl->reg_rtx, old)
6909 && rl->reg_rtx != 0)
6910 emit_input_reload_insns (chain, rld + j, old, j);
6912 /* When inheriting a wider reload, we have a MEM in rl->in,
6913 e.g. inheriting a SImode output reload for
6914 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6915 if (optimize && reload_inherited[j] && rl->in
6916 && GET_CODE (rl->in) == MEM
6917 && GET_CODE (rl->in_reg) == MEM
6918 && reload_spill_index[j] >= 0
6919 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6920 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6922 /* If we are reloading a register that was recently stored in with an
6923 output-reload, see if we can prove there was
6924 actually no need to store the old value in it. */
6927 && (reload_inherited[j] || reload_override_in[j])
6929 && GET_CODE (rl->reg_rtx) == REG
6930 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6932 /* There doesn't seem to be any reason to restrict this to pseudos
6933 and doing so loses in the case where we are copying from a
6934 register of the wrong class. */
6935 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6936 >= FIRST_PSEUDO_REGISTER)
6938 /* The insn might have already some references to stackslots
6939 replaced by MEMs, while reload_out_reg still names the
6941 && (dead_or_set_p (insn,
6942 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6943 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6945 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6948 /* Do output reloading for reload RL, which is for the insn described by
6949 CHAIN and has the number J.
6950 ??? At some point we need to support handling output reloads of
6951 JUMP_INSNs or insns that set cc0. */
6953 do_output_reload (chain, rl, j)
6954 struct insn_chain *chain;
6959 rtx insn = chain->insn;
6960 /* If this is an output reload that stores something that is
6961 not loaded in this same reload, see if we can eliminate a previous
6963 rtx pseudo = rl->out_reg;
6967 && GET_CODE (pseudo) == REG
6968 && ! rtx_equal_p (rl->in_reg, pseudo)
6969 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6970 && reg_last_reload_reg[REGNO (pseudo)])
6972 int pseudo_no = REGNO (pseudo);
6973 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6975 /* We don't need to test full validity of last_regno for
6976 inherit here; we only want to know if the store actually
6977 matches the pseudo. */
6978 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6979 && reg_reloaded_contents[last_regno] == pseudo_no
6980 && spill_reg_store[last_regno]
6981 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6982 delete_output_reload (insn, j, last_regno);
6987 || rl->reg_rtx == old
6988 || rl->reg_rtx == 0)
6991 /* An output operand that dies right away does need a reload,
6992 but need not be copied from it. Show the new location in the
6994 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6995 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6997 XEXP (note, 0) = rl->reg_rtx;
7000 /* Likewise for a SUBREG of an operand that dies. */
7001 else if (GET_CODE (old) == SUBREG
7002 && GET_CODE (SUBREG_REG (old)) == REG
7003 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7006 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7010 else if (GET_CODE (old) == SCRATCH)
7011 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7012 but we don't want to make an output reload. */
7015 /* If is a JUMP_INSN, we can't support output reloads yet. */
7016 if (GET_CODE (insn) == JUMP_INSN)
7019 emit_output_reload_insns (chain, rld + j, j);
7022 /* Output insns to reload values in and out of the chosen reload regs. */
7025 emit_reload_insns (chain)
7026 struct insn_chain *chain;
7028 rtx insn = chain->insn;
7032 CLEAR_HARD_REG_SET (reg_reloaded_died);
7034 for (j = 0; j < reload_n_operands; j++)
7035 input_reload_insns[j] = input_address_reload_insns[j]
7036 = inpaddr_address_reload_insns[j]
7037 = output_reload_insns[j] = output_address_reload_insns[j]
7038 = outaddr_address_reload_insns[j]
7039 = other_output_reload_insns[j] = 0;
7040 other_input_address_reload_insns = 0;
7041 other_input_reload_insns = 0;
7042 operand_reload_insns = 0;
7043 other_operand_reload_insns = 0;
7045 /* Dump reloads into the dump file. */
7048 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7049 debug_reload_to_stream (rtl_dump_file);
7052 /* Now output the instructions to copy the data into and out of the
7053 reload registers. Do these in the order that the reloads were reported,
7054 since reloads of base and index registers precede reloads of operands
7055 and the operands may need the base and index registers reloaded. */
7057 for (j = 0; j < n_reloads; j++)
7060 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7061 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7063 do_input_reload (chain, rld + j, j);
7064 do_output_reload (chain, rld + j, j);
7067 /* Now write all the insns we made for reloads in the order expected by
7068 the allocation functions. Prior to the insn being reloaded, we write
7069 the following reloads:
7071 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7073 RELOAD_OTHER reloads.
7075 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7076 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7077 RELOAD_FOR_INPUT reload for the operand.
7079 RELOAD_FOR_OPADDR_ADDRS reloads.
7081 RELOAD_FOR_OPERAND_ADDRESS reloads.
7083 After the insn being reloaded, we write the following:
7085 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7086 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7087 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7088 reloads for the operand. The RELOAD_OTHER output reloads are
7089 output in descending order by reload number. */
7091 emit_insn_before (other_input_address_reload_insns, insn);
7092 emit_insn_before (other_input_reload_insns, insn);
7094 for (j = 0; j < reload_n_operands; j++)
7096 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7097 emit_insn_before (input_address_reload_insns[j], insn);
7098 emit_insn_before (input_reload_insns[j], insn);
7101 emit_insn_before (other_operand_reload_insns, insn);
7102 emit_insn_before (operand_reload_insns, insn);
7104 for (j = 0; j < reload_n_operands; j++)
7106 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7107 x = emit_insn_after (output_address_reload_insns[j], x);
7108 x = emit_insn_after (output_reload_insns[j], x);
7109 emit_insn_after (other_output_reload_insns[j], x);
7112 /* For all the spill regs newly reloaded in this instruction,
7113 record what they were reloaded from, so subsequent instructions
7114 can inherit the reloads.
7116 Update spill_reg_store for the reloads of this insn.
7117 Copy the elements that were updated in the loop above. */
7119 for (j = 0; j < n_reloads; j++)
7121 int r = reload_order[j];
7122 int i = reload_spill_index[r];
7124 /* If this is a non-inherited input reload from a pseudo, we must
7125 clear any memory of a previous store to the same pseudo. Only do
7126 something if there will not be an output reload for the pseudo
7128 if (rld[r].in_reg != 0
7129 && ! (reload_inherited[r] || reload_override_in[r]))
7131 rtx reg = rld[r].in_reg;
7133 if (GET_CODE (reg) == SUBREG)
7134 reg = SUBREG_REG (reg);
7136 if (GET_CODE (reg) == REG
7137 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7138 && ! reg_has_output_reload[REGNO (reg)])
7140 int nregno = REGNO (reg);
7142 if (reg_last_reload_reg[nregno])
7144 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7146 if (reg_reloaded_contents[last_regno] == nregno)
7147 spill_reg_store[last_regno] = 0;
7152 /* I is nonneg if this reload used a register.
7153 If rld[r].reg_rtx is 0, this is an optional reload
7154 that we opted to ignore. */
7156 if (i >= 0 && rld[r].reg_rtx != 0)
7158 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7160 int part_reaches_end = 0;
7161 int all_reaches_end = 1;
7163 /* For a multi register reload, we need to check if all or part
7164 of the value lives to the end. */
7165 for (k = 0; k < nr; k++)
7167 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7168 rld[r].when_needed))
7169 part_reaches_end = 1;
7171 all_reaches_end = 0;
7174 /* Ignore reloads that don't reach the end of the insn in
7176 if (all_reaches_end)
7178 /* First, clear out memory of what used to be in this spill reg.
7179 If consecutive registers are used, clear them all. */
7181 for (k = 0; k < nr; k++)
7182 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7184 /* Maybe the spill reg contains a copy of reload_out. */
7186 && (GET_CODE (rld[r].out) == REG
7190 || GET_CODE (rld[r].out_reg) == REG))
7192 rtx out = (GET_CODE (rld[r].out) == REG
7196 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7197 int nregno = REGNO (out);
7198 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7199 : HARD_REGNO_NREGS (nregno,
7200 GET_MODE (rld[r].reg_rtx)));
7202 spill_reg_store[i] = new_spill_reg_store[i];
7203 spill_reg_stored_to[i] = out;
7204 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7206 /* If NREGNO is a hard register, it may occupy more than
7207 one register. If it does, say what is in the
7208 rest of the registers assuming that both registers
7209 agree on how many words the object takes. If not,
7210 invalidate the subsequent registers. */
7212 if (nregno < FIRST_PSEUDO_REGISTER)
7213 for (k = 1; k < nnr; k++)
7214 reg_last_reload_reg[nregno + k]
7216 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7219 /* Now do the inverse operation. */
7220 for (k = 0; k < nr; k++)
7222 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7223 reg_reloaded_contents[i + k]
7224 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7227 reg_reloaded_insn[i + k] = insn;
7228 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7232 /* Maybe the spill reg contains a copy of reload_in. Only do
7233 something if there will not be an output reload for
7234 the register being reloaded. */
7235 else if (rld[r].out_reg == 0
7237 && ((GET_CODE (rld[r].in) == REG
7238 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7239 && ! reg_has_output_reload[REGNO (rld[r].in)])
7240 || (GET_CODE (rld[r].in_reg) == REG
7241 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7242 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7247 if (GET_CODE (rld[r].in) == REG
7248 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7249 nregno = REGNO (rld[r].in);
7250 else if (GET_CODE (rld[r].in_reg) == REG)
7251 nregno = REGNO (rld[r].in_reg);
7253 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7255 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7256 : HARD_REGNO_NREGS (nregno,
7257 GET_MODE (rld[r].reg_rtx)));
7259 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7261 if (nregno < FIRST_PSEUDO_REGISTER)
7262 for (k = 1; k < nnr; k++)
7263 reg_last_reload_reg[nregno + k]
7265 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7268 /* Unless we inherited this reload, show we haven't
7269 recently done a store.
7270 Previous stores of inherited auto_inc expressions
7271 also have to be discarded. */
7272 if (! reload_inherited[r]
7273 || (rld[r].out && ! rld[r].out_reg))
7274 spill_reg_store[i] = 0;
7276 for (k = 0; k < nr; k++)
7278 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7279 reg_reloaded_contents[i + k]
7280 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7283 reg_reloaded_insn[i + k] = insn;
7284 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7289 /* However, if part of the reload reaches the end, then we must
7290 invalidate the old info for the part that survives to the end. */
7291 else if (part_reaches_end)
7293 for (k = 0; k < nr; k++)
7294 if (reload_reg_reaches_end_p (i + k,
7296 rld[r].when_needed))
7297 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7301 /* The following if-statement was #if 0'd in 1.34 (or before...).
7302 It's reenabled in 1.35 because supposedly nothing else
7303 deals with this problem. */
7305 /* If a register gets output-reloaded from a non-spill register,
7306 that invalidates any previous reloaded copy of it.
7307 But forget_old_reloads_1 won't get to see it, because
7308 it thinks only about the original insn. So invalidate it here. */
7309 if (i < 0 && rld[r].out != 0
7310 && (GET_CODE (rld[r].out) == REG
7311 || (GET_CODE (rld[r].out) == MEM
7312 && GET_CODE (rld[r].out_reg) == REG)))
7314 rtx out = (GET_CODE (rld[r].out) == REG
7315 ? rld[r].out : rld[r].out_reg);
7316 int nregno = REGNO (out);
7317 if (nregno >= FIRST_PSEUDO_REGISTER)
7319 rtx src_reg, store_insn = NULL_RTX;
7321 reg_last_reload_reg[nregno] = 0;
7323 /* If we can find a hard register that is stored, record
7324 the storing insn so that we may delete this insn with
7325 delete_output_reload. */
7326 src_reg = rld[r].reg_rtx;
7328 /* If this is an optional reload, try to find the source reg
7329 from an input reload. */
7332 rtx set = single_set (insn);
7333 if (set && SET_DEST (set) == rld[r].out)
7337 src_reg = SET_SRC (set);
7339 for (k = 0; k < n_reloads; k++)
7341 if (rld[k].in == src_reg)
7343 src_reg = rld[k].reg_rtx;
7350 store_insn = new_spill_reg_store[REGNO (src_reg)];
7351 if (src_reg && GET_CODE (src_reg) == REG
7352 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7354 int src_regno = REGNO (src_reg);
7355 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7356 /* The place where to find a death note varies with
7357 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7358 necessarily checked exactly in the code that moves
7359 notes, so just check both locations. */
7360 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7361 if (! note && store_insn)
7362 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7365 spill_reg_store[src_regno + nr] = store_insn;
7366 spill_reg_stored_to[src_regno + nr] = out;
7367 reg_reloaded_contents[src_regno + nr] = nregno;
7368 reg_reloaded_insn[src_regno + nr] = store_insn;
7369 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7370 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7371 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7373 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7375 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7377 reg_last_reload_reg[nregno] = src_reg;
7382 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7384 while (num_regs-- > 0)
7385 reg_last_reload_reg[nregno + num_regs] = 0;
7389 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7392 /* Emit code to perform a reload from IN (which may be a reload register) to
7393 OUT (which may also be a reload register). IN or OUT is from operand
7394 OPNUM with reload type TYPE.
7396 Returns first insn emitted. */
7399 gen_reload (out, in, opnum, type)
7403 enum reload_type type;
7405 rtx last = get_last_insn ();
7408 /* If IN is a paradoxical SUBREG, remove it and try to put the
7409 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7410 if (GET_CODE (in) == SUBREG
7411 && (GET_MODE_SIZE (GET_MODE (in))
7412 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7413 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7414 in = SUBREG_REG (in), out = tem;
7415 else if (GET_CODE (out) == SUBREG
7416 && (GET_MODE_SIZE (GET_MODE (out))
7417 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7418 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7419 out = SUBREG_REG (out), in = tem;
7421 /* How to do this reload can get quite tricky. Normally, we are being
7422 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7423 register that didn't get a hard register. In that case we can just
7424 call emit_move_insn.
7426 We can also be asked to reload a PLUS that adds a register or a MEM to
7427 another register, constant or MEM. This can occur during frame pointer
7428 elimination and while reloading addresses. This case is handled by
7429 trying to emit a single insn to perform the add. If it is not valid,
7430 we use a two insn sequence.
7432 Finally, we could be called to handle an 'o' constraint by putting
7433 an address into a register. In that case, we first try to do this
7434 with a named pattern of "reload_load_address". If no such pattern
7435 exists, we just emit a SET insn and hope for the best (it will normally
7436 be valid on machines that use 'o').
7438 This entire process is made complex because reload will never
7439 process the insns we generate here and so we must ensure that
7440 they will fit their constraints and also by the fact that parts of
7441 IN might be being reloaded separately and replaced with spill registers.
7442 Because of this, we are, in some sense, just guessing the right approach
7443 here. The one listed above seems to work.
7445 ??? At some point, this whole thing needs to be rethought. */
7447 if (GET_CODE (in) == PLUS
7448 && (GET_CODE (XEXP (in, 0)) == REG
7449 || GET_CODE (XEXP (in, 0)) == SUBREG
7450 || GET_CODE (XEXP (in, 0)) == MEM)
7451 && (GET_CODE (XEXP (in, 1)) == REG
7452 || GET_CODE (XEXP (in, 1)) == SUBREG
7453 || CONSTANT_P (XEXP (in, 1))
7454 || GET_CODE (XEXP (in, 1)) == MEM))
7456 /* We need to compute the sum of a register or a MEM and another
7457 register, constant, or MEM, and put it into the reload
7458 register. The best possible way of doing this is if the machine
7459 has a three-operand ADD insn that accepts the required operands.
7461 The simplest approach is to try to generate such an insn and see if it
7462 is recognized and matches its constraints. If so, it can be used.
7464 It might be better not to actually emit the insn unless it is valid,
7465 but we need to pass the insn as an operand to `recog' and
7466 `extract_insn' and it is simpler to emit and then delete the insn if
7467 not valid than to dummy things up. */
7469 rtx op0, op1, tem, insn;
7472 op0 = find_replacement (&XEXP (in, 0));
7473 op1 = find_replacement (&XEXP (in, 1));
7475 /* Since constraint checking is strict, commutativity won't be
7476 checked, so we need to do that here to avoid spurious failure
7477 if the add instruction is two-address and the second operand
7478 of the add is the same as the reload reg, which is frequently
7479 the case. If the insn would be A = B + A, rearrange it so
7480 it will be A = A + B as constrain_operands expects. */
7482 if (GET_CODE (XEXP (in, 1)) == REG
7483 && REGNO (out) == REGNO (XEXP (in, 1)))
7484 tem = op0, op0 = op1, op1 = tem;
7486 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7487 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7489 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7490 code = recog_memoized (insn);
7494 extract_insn (insn);
7495 /* We want constrain operands to treat this insn strictly in
7496 its validity determination, i.e., the way it would after reload
7498 if (constrain_operands (1))
7502 delete_insns_since (last);
7504 /* If that failed, we must use a conservative two-insn sequence.
7506 Use a move to copy one operand into the reload register. Prefer
7507 to reload a constant, MEM or pseudo since the move patterns can
7508 handle an arbitrary operand. If OP1 is not a constant, MEM or
7509 pseudo and OP1 is not a valid operand for an add instruction, then
7512 After reloading one of the operands into the reload register, add
7513 the reload register to the output register.
7515 If there is another way to do this for a specific machine, a
7516 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7519 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7521 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7522 || (GET_CODE (op1) == REG
7523 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7524 || (code != CODE_FOR_nothing
7525 && ! ((*insn_data[code].operand[2].predicate)
7526 (op1, insn_data[code].operand[2].mode))))
7527 tem = op0, op0 = op1, op1 = tem;
7529 gen_reload (out, op0, opnum, type);
7531 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7532 This fixes a problem on the 32K where the stack pointer cannot
7533 be used as an operand of an add insn. */
7535 if (rtx_equal_p (op0, op1))
7538 insn = emit_insn (gen_add2_insn (out, op1));
7540 /* If that failed, copy the address register to the reload register.
7541 Then add the constant to the reload register. */
7543 code = recog_memoized (insn);
7547 extract_insn (insn);
7548 /* We want constrain operands to treat this insn strictly in
7549 its validity determination, i.e., the way it would after reload
7551 if (constrain_operands (1))
7553 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7555 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7560 delete_insns_since (last);
7562 gen_reload (out, op1, opnum, type);
7563 insn = emit_insn (gen_add2_insn (out, op0));
7564 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7567 #ifdef SECONDARY_MEMORY_NEEDED
7568 /* If we need a memory location to do the move, do it that way. */
7569 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7570 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7571 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7572 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7573 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7574 REGNO_REG_CLASS (reg_or_subregno (out)),
7577 /* Get the memory to use and rewrite both registers to its mode. */
7578 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7580 if (GET_MODE (loc) != GET_MODE (out))
7581 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7583 if (GET_MODE (loc) != GET_MODE (in))
7584 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7586 gen_reload (loc, in, opnum, type);
7587 gen_reload (out, loc, opnum, type);
7591 /* If IN is a simple operand, use gen_move_insn. */
7592 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7593 emit_insn (gen_move_insn (out, in));
7595 #ifdef HAVE_reload_load_address
7596 else if (HAVE_reload_load_address)
7597 emit_insn (gen_reload_load_address (out, in));
7600 /* Otherwise, just write (set OUT IN) and hope for the best. */
7602 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7604 /* Return the first insn emitted.
7605 We can not just return get_last_insn, because there may have
7606 been multiple instructions emitted. Also note that gen_move_insn may
7607 emit more than one insn itself, so we can not assume that there is one
7608 insn emitted per emit_insn_before call. */
7610 return last ? NEXT_INSN (last) : get_insns ();
7613 /* Delete a previously made output-reload whose result we now believe
7614 is not needed. First we double-check.
7616 INSN is the insn now being processed.
7617 LAST_RELOAD_REG is the hard register number for which we want to delete
7618 the last output reload.
7619 J is the reload-number that originally used REG. The caller has made
7620 certain that reload J doesn't use REG any longer for input. */
7623 delete_output_reload (insn, j, last_reload_reg)
7626 int last_reload_reg;
7628 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7629 rtx reg = spill_reg_stored_to[last_reload_reg];
7632 int n_inherited = 0;
7636 /* It is possible that this reload has been only used to set another reload
7637 we eliminated earlier and thus deleted this instruction too. */
7638 if (INSN_DELETED_P (output_reload_insn))
7641 /* Get the raw pseudo-register referred to. */
7643 while (GET_CODE (reg) == SUBREG)
7644 reg = SUBREG_REG (reg);
7645 substed = reg_equiv_memory_loc[REGNO (reg)];
7647 /* This is unsafe if the operand occurs more often in the current
7648 insn than it is inherited. */
7649 for (k = n_reloads - 1; k >= 0; k--)
7651 rtx reg2 = rld[k].in;
7654 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7655 reg2 = rld[k].in_reg;
7657 if (rld[k].out && ! rld[k].out_reg)
7658 reg2 = XEXP (rld[k].in_reg, 0);
7660 while (GET_CODE (reg2) == SUBREG)
7661 reg2 = SUBREG_REG (reg2);
7662 if (rtx_equal_p (reg2, reg))
7664 if (reload_inherited[k] || reload_override_in[k] || k == j)
7667 reg2 = rld[k].out_reg;
7670 while (GET_CODE (reg2) == SUBREG)
7671 reg2 = XEXP (reg2, 0);
7672 if (rtx_equal_p (reg2, reg))
7679 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7681 n_occurrences += count_occurrences (PATTERN (insn),
7682 eliminate_regs (substed, 0,
7684 if (n_occurrences > n_inherited)
7687 /* If the pseudo-reg we are reloading is no longer referenced
7688 anywhere between the store into it and here,
7689 and no jumps or labels intervene, then the value can get
7690 here through the reload reg alone.
7691 Otherwise, give up--return. */
7692 for (i1 = NEXT_INSN (output_reload_insn);
7693 i1 != insn; i1 = NEXT_INSN (i1))
7695 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7697 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7698 && reg_mentioned_p (reg, PATTERN (i1)))
7700 /* If this is USE in front of INSN, we only have to check that
7701 there are no more references than accounted for by inheritance. */
7702 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7704 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7705 i1 = NEXT_INSN (i1);
7707 if (n_occurrences <= n_inherited && i1 == insn)
7713 /* We will be deleting the insn. Remove the spill reg information. */
7714 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7716 spill_reg_store[last_reload_reg + k] = 0;
7717 spill_reg_stored_to[last_reload_reg + k] = 0;
7720 /* The caller has already checked that REG dies or is set in INSN.
7721 It has also checked that we are optimizing, and thus some
7722 inaccuracies in the debugging information are acceptable.
7723 So we could just delete output_reload_insn. But in some cases
7724 we can improve the debugging information without sacrificing
7725 optimization - maybe even improving the code: See if the pseudo
7726 reg has been completely replaced with reload regs. If so, delete
7727 the store insn and forget we had a stack slot for the pseudo. */
7728 if (rld[j].out != rld[j].in
7729 && REG_N_DEATHS (REGNO (reg)) == 1
7730 && REG_N_SETS (REGNO (reg)) == 1
7731 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7732 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7736 /* We know that it was used only between here and the beginning of
7737 the current basic block. (We also know that the last use before
7738 INSN was the output reload we are thinking of deleting, but never
7739 mind that.) Search that range; see if any ref remains. */
7740 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7742 rtx set = single_set (i2);
7744 /* Uses which just store in the pseudo don't count,
7745 since if they are the only uses, they are dead. */
7746 if (set != 0 && SET_DEST (set) == reg)
7748 if (GET_CODE (i2) == CODE_LABEL
7749 || GET_CODE (i2) == JUMP_INSN)
7751 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7752 && reg_mentioned_p (reg, PATTERN (i2)))
7754 /* Some other ref remains; just delete the output reload we
7756 delete_address_reloads (output_reload_insn, insn);
7757 delete_insn (output_reload_insn);
7762 /* Delete the now-dead stores into this pseudo. Note that this
7763 loop also takes care of deleting output_reload_insn. */
7764 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7766 rtx set = single_set (i2);
7768 if (set != 0 && SET_DEST (set) == reg)
7770 delete_address_reloads (i2, insn);
7773 if (GET_CODE (i2) == CODE_LABEL
7774 || GET_CODE (i2) == JUMP_INSN)
7778 /* For the debugging info, say the pseudo lives in this reload reg. */
7779 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7780 alter_reg (REGNO (reg), -1);
7784 delete_address_reloads (output_reload_insn, insn);
7785 delete_insn (output_reload_insn);
7789 /* We are going to delete DEAD_INSN. Recursively delete loads of
7790 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7791 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7793 delete_address_reloads (dead_insn, current_insn)
7794 rtx dead_insn, current_insn;
7796 rtx set = single_set (dead_insn);
7797 rtx set2, dst, prev, next;
7800 rtx dst = SET_DEST (set);
7801 if (GET_CODE (dst) == MEM)
7802 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7804 /* If we deleted the store from a reloaded post_{in,de}c expression,
7805 we can delete the matching adds. */
7806 prev = PREV_INSN (dead_insn);
7807 next = NEXT_INSN (dead_insn);
7808 if (! prev || ! next)
7810 set = single_set (next);
7811 set2 = single_set (prev);
7813 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7814 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7815 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7817 dst = SET_DEST (set);
7818 if (! rtx_equal_p (dst, SET_DEST (set2))
7819 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7820 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7821 || (INTVAL (XEXP (SET_SRC (set), 1))
7822 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7824 delete_related_insns (prev);
7825 delete_related_insns (next);
7828 /* Subfunction of delete_address_reloads: process registers found in X. */
7830 delete_address_reloads_1 (dead_insn, x, current_insn)
7831 rtx dead_insn, x, current_insn;
7833 rtx prev, set, dst, i2;
7835 enum rtx_code code = GET_CODE (x);
7839 const char *fmt = GET_RTX_FORMAT (code);
7840 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7843 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7844 else if (fmt[i] == 'E')
7846 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7847 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7854 if (spill_reg_order[REGNO (x)] < 0)
7857 /* Scan backwards for the insn that sets x. This might be a way back due
7859 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7861 code = GET_CODE (prev);
7862 if (code == CODE_LABEL || code == JUMP_INSN)
7864 if (GET_RTX_CLASS (code) != 'i')
7866 if (reg_set_p (x, PATTERN (prev)))
7868 if (reg_referenced_p (x, PATTERN (prev)))
7871 if (! prev || INSN_UID (prev) < reload_first_uid)
7873 /* Check that PREV only sets the reload register. */
7874 set = single_set (prev);
7877 dst = SET_DEST (set);
7878 if (GET_CODE (dst) != REG
7879 || ! rtx_equal_p (dst, x))
7881 if (! reg_set_p (dst, PATTERN (dead_insn)))
7883 /* Check if DST was used in a later insn -
7884 it might have been inherited. */
7885 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7887 if (GET_CODE (i2) == CODE_LABEL)
7891 if (reg_referenced_p (dst, PATTERN (i2)))
7893 /* If there is a reference to the register in the current insn,
7894 it might be loaded in a non-inherited reload. If no other
7895 reload uses it, that means the register is set before
7897 if (i2 == current_insn)
7899 for (j = n_reloads - 1; j >= 0; j--)
7900 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7901 || reload_override_in[j] == dst)
7903 for (j = n_reloads - 1; j >= 0; j--)
7904 if (rld[j].in && rld[j].reg_rtx == dst)
7911 if (GET_CODE (i2) == JUMP_INSN)
7913 /* If DST is still live at CURRENT_INSN, check if it is used for
7914 any reload. Note that even if CURRENT_INSN sets DST, we still
7915 have to check the reloads. */
7916 if (i2 == current_insn)
7918 for (j = n_reloads - 1; j >= 0; j--)
7919 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7920 || reload_override_in[j] == dst)
7922 /* ??? We can't finish the loop here, because dst might be
7923 allocated to a pseudo in this block if no reload in this
7924 block needs any of the classes containing DST - see
7925 spill_hard_reg. There is no easy way to tell this, so we
7926 have to scan till the end of the basic block. */
7928 if (reg_set_p (dst, PATTERN (i2)))
7932 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7933 reg_reloaded_contents[REGNO (dst)] = -1;
7937 /* Output reload-insns to reload VALUE into RELOADREG.
7938 VALUE is an autoincrement or autodecrement RTX whose operand
7939 is a register or memory location;
7940 so reloading involves incrementing that location.
7941 IN is either identical to VALUE, or some cheaper place to reload from.
7943 INC_AMOUNT is the number to increment or decrement by (always positive).
7944 This cannot be deduced from VALUE.
7946 Return the instruction that stores into RELOADREG. */
7949 inc_for_reload (reloadreg, in, value, inc_amount)
7954 /* REG or MEM to be copied and incremented. */
7955 rtx incloc = XEXP (value, 0);
7956 /* Nonzero if increment after copying. */
7957 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7963 rtx real_in = in == value ? XEXP (in, 0) : in;
7965 /* No hard register is equivalent to this register after
7966 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7967 we could inc/dec that register as well (maybe even using it for
7968 the source), but I'm not sure it's worth worrying about. */
7969 if (GET_CODE (incloc) == REG)
7970 reg_last_reload_reg[REGNO (incloc)] = 0;
7972 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7973 inc_amount = -inc_amount;
7975 inc = GEN_INT (inc_amount);
7977 /* If this is post-increment, first copy the location to the reload reg. */
7978 if (post && real_in != reloadreg)
7979 emit_insn (gen_move_insn (reloadreg, real_in));
7983 /* See if we can directly increment INCLOC. Use a method similar to
7984 that in gen_reload. */
7986 last = get_last_insn ();
7987 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7988 gen_rtx_PLUS (GET_MODE (incloc),
7991 code = recog_memoized (add_insn);
7994 extract_insn (add_insn);
7995 if (constrain_operands (1))
7997 /* If this is a pre-increment and we have incremented the value
7998 where it lives, copy the incremented value to RELOADREG to
7999 be used as an address. */
8002 emit_insn (gen_move_insn (reloadreg, incloc));
8007 delete_insns_since (last);
8010 /* If couldn't do the increment directly, must increment in RELOADREG.
8011 The way we do this depends on whether this is pre- or post-increment.
8012 For pre-increment, copy INCLOC to the reload register, increment it
8013 there, then save back. */
8017 if (in != reloadreg)
8018 emit_insn (gen_move_insn (reloadreg, real_in));
8019 emit_insn (gen_add2_insn (reloadreg, inc));
8020 store = emit_insn (gen_move_insn (incloc, reloadreg));
8025 Because this might be a jump insn or a compare, and because RELOADREG
8026 may not be available after the insn in an input reload, we must do
8027 the incrementation before the insn being reloaded for.
8029 We have already copied IN to RELOADREG. Increment the copy in
8030 RELOADREG, save that back, then decrement RELOADREG so it has
8031 the original value. */
8033 emit_insn (gen_add2_insn (reloadreg, inc));
8034 store = emit_insn (gen_move_insn (incloc, reloadreg));
8035 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8042 /* See whether a single set SET is a noop. */
8044 reload_cse_noop_set_p (set)
8047 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set)))
8050 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8053 /* Try to simplify INSN. */
8055 reload_cse_simplify (insn, testreg)
8059 rtx body = PATTERN (insn);
8061 if (GET_CODE (body) == SET)
8065 /* Simplify even if we may think it is a no-op.
8066 We may think a memory load of a value smaller than WORD_SIZE
8067 is redundant because we haven't taken into account possible
8068 implicit extension. reload_cse_simplify_set() will bring
8069 this out, so it's safer to simplify before we delete. */
8070 count += reload_cse_simplify_set (body, insn);
8072 if (!count && reload_cse_noop_set_p (body))
8074 rtx value = SET_DEST (body);
8076 && ! REG_FUNCTION_VALUE_P (value))
8078 delete_insn_and_edges (insn);
8083 apply_change_group ();
8085 reload_cse_simplify_operands (insn, testreg);
8087 else if (GET_CODE (body) == PARALLEL)
8091 rtx value = NULL_RTX;
8093 /* If every action in a PARALLEL is a noop, we can delete
8094 the entire PARALLEL. */
8095 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8097 rtx part = XVECEXP (body, 0, i);
8098 if (GET_CODE (part) == SET)
8100 if (! reload_cse_noop_set_p (part))
8102 if (REG_P (SET_DEST (part))
8103 && REG_FUNCTION_VALUE_P (SET_DEST (part)))
8107 value = SET_DEST (part);
8110 else if (GET_CODE (part) != CLOBBER)
8116 delete_insn_and_edges (insn);
8117 /* We're done with this insn. */
8121 /* It's not a no-op, but we can try to simplify it. */
8122 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8123 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8124 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8127 apply_change_group ();
8129 reload_cse_simplify_operands (insn, testreg);
8133 /* Do a very simple CSE pass over the hard registers.
8135 This function detects no-op moves where we happened to assign two
8136 different pseudo-registers to the same hard register, and then
8137 copied one to the other. Reload will generate a useless
8138 instruction copying a register to itself.
8140 This function also detects cases where we load a value from memory
8141 into two different registers, and (if memory is more expensive than
8142 registers) changes it to simply copy the first register into the
8145 Another optimization is performed that scans the operands of each
8146 instruction to see whether the value is already available in a
8147 hard register. It then replaces the operand with the hard register
8148 if possible, much like an optional reload would. */
8151 reload_cse_regs_1 (first)
8155 rtx testreg = gen_rtx_REG (VOIDmode, -1);
8158 init_alias_analysis ();
8160 for (insn = first; insn; insn = NEXT_INSN (insn))
8163 reload_cse_simplify (insn, testreg);
8165 cselib_process_insn (insn);
8169 end_alias_analysis ();
8173 /* Call cse / combine like post-reload optimization phases.
8174 FIRST is the first instruction. */
8176 reload_cse_regs (first)
8179 reload_cse_regs_1 (first);
8181 reload_cse_move2add (first);
8182 if (flag_expensive_optimizations)
8183 reload_cse_regs_1 (first);
8186 /* Try to simplify a single SET instruction. SET is the set pattern.
8187 INSN is the instruction it came from.
8188 This function only handles one case: if we set a register to a value
8189 which is not a register, we try to find that value in some other register
8190 and change the set into a register copy. */
8193 reload_cse_simplify_set (set, insn)
8200 enum reg_class dclass;
8203 struct elt_loc_list *l;
8204 #ifdef LOAD_EXTEND_OP
8205 enum rtx_code extend_op = NIL;
8208 dreg = true_regnum (SET_DEST (set));
8212 src = SET_SRC (set);
8213 if (side_effects_p (src) || true_regnum (src) >= 0)
8216 dclass = REGNO_REG_CLASS (dreg);
8218 #ifdef LOAD_EXTEND_OP
8219 /* When replacing a memory with a register, we need to honor assumptions
8220 that combine made wrt the contents of sign bits. We'll do this by
8221 generating an extend instruction instead of a reg->reg copy. Thus
8222 the destination must be a register that we can widen. */
8223 if (GET_CODE (src) == MEM
8224 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8225 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8226 && GET_CODE (SET_DEST (set)) != REG)
8230 /* If memory loads are cheaper than register copies, don't change them. */
8231 if (GET_CODE (src) == MEM)
8232 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8233 else if (CONSTANT_P (src))
8234 old_cost = rtx_cost (src, SET);
8235 else if (GET_CODE (src) == REG)
8236 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8237 REGNO_REG_CLASS (REGNO (src)), dclass);
8240 old_cost = rtx_cost (src, SET);
8242 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8245 for (l = val->locs; l; l = l->next)
8247 rtx this_rtx = l->loc;
8250 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8252 #ifdef LOAD_EXTEND_OP
8253 if (extend_op != NIL)
8255 HOST_WIDE_INT this_val;
8257 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8258 constants, such as SYMBOL_REF, cannot be extended. */
8259 if (GET_CODE (this_rtx) != CONST_INT)
8262 this_val = INTVAL (this_rtx);
8266 this_val &= GET_MODE_MASK (GET_MODE (src));
8269 /* ??? In theory we're already extended. */
8270 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8275 this_rtx = GEN_INT (this_val);
8278 this_cost = rtx_cost (this_rtx, SET);
8280 else if (GET_CODE (this_rtx) == REG)
8282 #ifdef LOAD_EXTEND_OP
8283 if (extend_op != NIL)
8285 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8286 this_cost = rtx_cost (this_rtx, SET);
8290 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8291 REGNO_REG_CLASS (REGNO (this_rtx)),
8297 /* If equal costs, prefer registers over anything else. That
8298 tends to lead to smaller instructions on some machines. */
8299 if (this_cost < old_cost
8300 || (this_cost == old_cost
8301 && GET_CODE (this_rtx) == REG
8302 && GET_CODE (SET_SRC (set)) != REG))
8304 #ifdef LOAD_EXTEND_OP
8305 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8307 #ifdef CANNOT_CHANGE_MODE_CLASS
8308 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
8310 REGNO_REG_CLASS (REGNO (SET_DEST (set))))
8314 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8315 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8316 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8320 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8321 old_cost = this_cost, did_change = 1;
8328 /* Try to replace operands in INSN with equivalent values that are already
8329 in registers. This can be viewed as optional reloading.
8331 For each non-register operand in the insn, see if any hard regs are
8332 known to be equivalent to that operand. Record the alternatives which
8333 can accept these hard registers. Among all alternatives, select the
8334 ones which are better or equal to the one currently matching, where
8335 "better" is in terms of '?' and '!' constraints. Among the remaining
8336 alternatives, select the one which replaces most operands with
8340 reload_cse_simplify_operands (insn, testreg)
8346 /* For each operand, all registers that are equivalent to it. */
8347 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8349 const char *constraints[MAX_RECOG_OPERANDS];
8351 /* Vector recording how bad an alternative is. */
8352 int *alternative_reject;
8353 /* Vector recording how many registers can be introduced by choosing
8354 this alternative. */
8355 int *alternative_nregs;
8356 /* Array of vectors recording, for each operand and each alternative,
8357 which hard register to substitute, or -1 if the operand should be
8359 int *op_alt_regno[MAX_RECOG_OPERANDS];
8360 /* Array of alternatives, sorted in order of decreasing desirability. */
8361 int *alternative_order;
8363 extract_insn (insn);
8365 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8368 /* Figure out which alternative currently matches. */
8369 if (! constrain_operands (1))
8370 fatal_insn_not_found (insn);
8372 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8373 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8374 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8375 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8376 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8378 /* For each operand, find out which regs are equivalent. */
8379 for (i = 0; i < recog_data.n_operands; i++)
8382 struct elt_loc_list *l;
8384 CLEAR_HARD_REG_SET (equiv_regs[i]);
8386 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8387 right, so avoid the problem here. Likewise if we have a constant
8388 and the insn pattern doesn't tell us the mode we need. */
8389 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8390 || (CONSTANT_P (recog_data.operand[i])
8391 && recog_data.operand_mode[i] == VOIDmode))
8394 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8398 for (l = v->locs; l; l = l->next)
8399 if (GET_CODE (l->loc) == REG)
8400 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8403 for (i = 0; i < recog_data.n_operands; i++)
8405 enum machine_mode mode;
8409 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8410 for (j = 0; j < recog_data.n_alternatives; j++)
8411 op_alt_regno[i][j] = -1;
8413 p = constraints[i] = recog_data.constraints[i];
8414 mode = recog_data.operand_mode[i];
8416 /* Add the reject values for each alternative given by the constraints
8417 for this operand. */
8425 alternative_reject[j] += 3;
8427 alternative_reject[j] += 300;
8430 /* We won't change operands which are already registers. We
8431 also don't want to modify output operands. */
8432 regno = true_regnum (recog_data.operand[i]);
8434 || constraints[i][0] == '='
8435 || constraints[i][0] == '+')
8438 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8440 int class = (int) NO_REGS;
8442 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8445 REGNO (testreg) = regno;
8446 PUT_MODE (testreg, mode);
8448 /* We found a register equal to this operand. Now look for all
8449 alternatives that can accept this register and have not been
8450 assigned a register they can use yet. */
8459 case '=': case '+': case '?':
8460 case '#': case '&': case '!':
8462 case '0': case '1': case '2': case '3': case '4':
8463 case '5': case '6': case '7': case '8': case '9':
8464 case 'm': case '<': case '>': case 'V': case 'o':
8465 case 'E': case 'F': case 'G': case 'H':
8466 case 's': case 'i': case 'n':
8467 case 'I': case 'J': case 'K': case 'L':
8468 case 'M': case 'N': case 'O': case 'P':
8470 /* These don't say anything we care about. */
8474 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8479 = (reg_class_subunion
8481 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c, p)]);
8484 case ',': case '\0':
8485 /* See if REGNO fits this alternative, and set it up as the
8486 replacement register if we don't have one for this
8487 alternative yet and the operand being replaced is not
8488 a cheap CONST_INT. */
8489 if (op_alt_regno[i][j] == -1
8490 && reg_fits_class_p (testreg, class, 0, mode)
8491 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8492 || (rtx_cost (recog_data.operand[i], SET)
8493 > rtx_cost (testreg, SET))))
8495 alternative_nregs[j]++;
8496 op_alt_regno[i][j] = regno;
8501 p += CONSTRAINT_LEN (c, p);
8509 /* Record all alternatives which are better or equal to the currently
8510 matching one in the alternative_order array. */
8511 for (i = j = 0; i < recog_data.n_alternatives; i++)
8512 if (alternative_reject[i] <= alternative_reject[which_alternative])
8513 alternative_order[j++] = i;
8514 recog_data.n_alternatives = j;
8516 /* Sort it. Given a small number of alternatives, a dumb algorithm
8517 won't hurt too much. */
8518 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8521 int best_reject = alternative_reject[alternative_order[i]];
8522 int best_nregs = alternative_nregs[alternative_order[i]];
8525 for (j = i + 1; j < recog_data.n_alternatives; j++)
8527 int this_reject = alternative_reject[alternative_order[j]];
8528 int this_nregs = alternative_nregs[alternative_order[j]];
8530 if (this_reject < best_reject
8531 || (this_reject == best_reject && this_nregs < best_nregs))
8534 best_reject = this_reject;
8535 best_nregs = this_nregs;
8539 tmp = alternative_order[best];
8540 alternative_order[best] = alternative_order[i];
8541 alternative_order[i] = tmp;
8544 /* Substitute the operands as determined by op_alt_regno for the best
8546 j = alternative_order[0];
8548 for (i = 0; i < recog_data.n_operands; i++)
8550 enum machine_mode mode = recog_data.operand_mode[i];
8551 if (op_alt_regno[i][j] == -1)
8554 validate_change (insn, recog_data.operand_loc[i],
8555 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8558 for (i = recog_data.n_dups - 1; i >= 0; i--)
8560 int op = recog_data.dup_num[i];
8561 enum machine_mode mode = recog_data.operand_mode[op];
8563 if (op_alt_regno[op][j] == -1)
8566 validate_change (insn, recog_data.dup_loc[i],
8567 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8570 return apply_change_group ();
8573 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8575 This code might also be useful when reload gave up on reg+reg addressing
8576 because of clashes between the return register and INDEX_REG_CLASS. */
8578 /* The maximum number of uses of a register we can keep track of to
8579 replace them with reg+reg addressing. */
8580 #define RELOAD_COMBINE_MAX_USES 6
8582 /* INSN is the insn where a register has ben used, and USEP points to the
8583 location of the register within the rtl. */
8584 struct reg_use { rtx insn, *usep; };
8586 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8587 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8588 indicates where it becomes live again.
8589 Otherwise, USE_INDEX is the index of the last encountered use of the
8590 register (which is first among these we have seen since we scan backwards),
8591 OFFSET contains the constant offset that is added to the register in
8592 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8593 last, of these uses.
8594 STORE_RUID is always meaningful if we only want to use a value in a
8595 register in a different place: it denotes the next insn in the insn
8596 stream (i.e. the last encountered) that sets or clobbers the register. */
8599 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8604 } reg_state[FIRST_PSEUDO_REGISTER];
8606 /* Reverse linear uid. This is increased in reload_combine while scanning
8607 the instructions from last to first. It is used to set last_label_ruid
8608 and the store_ruid / use_ruid fields in reg_state. */
8609 static int reload_combine_ruid;
8611 #define LABEL_LIVE(LABEL) \
8612 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8618 int first_index_reg = -1;
8619 int last_index_reg = 0;
8623 int last_label_ruid;
8624 int min_labelno, n_labels;
8625 HARD_REG_SET ever_live_at_start, *label_live;
8627 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8628 reload has already used it where appropriate, so there is no use in
8629 trying to generate it now. */
8630 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8633 /* To avoid wasting too much time later searching for an index register,
8634 determine the minimum and maximum index register numbers. */
8635 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8636 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8638 if (first_index_reg == -1)
8639 first_index_reg = r;
8644 /* If no index register is available, we can quit now. */
8645 if (first_index_reg == -1)
8648 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8649 information is a bit fuzzy immediately after reload, but it's
8650 still good enough to determine which registers are live at a jump
8652 min_labelno = get_first_label_num ();
8653 n_labels = max_label_num () - min_labelno;
8654 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8655 CLEAR_HARD_REG_SET (ever_live_at_start);
8657 FOR_EACH_BB_REVERSE (bb)
8660 if (GET_CODE (insn) == CODE_LABEL)
8664 REG_SET_TO_HARD_REG_SET (live,
8665 bb->global_live_at_start);
8666 compute_use_by_pseudos (&live,
8667 bb->global_live_at_start);
8668 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8669 IOR_HARD_REG_SET (ever_live_at_start, live);
8673 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8674 last_label_ruid = reload_combine_ruid = 0;
8675 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8677 reg_state[r].store_ruid = reload_combine_ruid;
8679 reg_state[r].use_index = -1;
8681 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8684 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8688 /* We cannot do our optimization across labels. Invalidating all the use
8689 information we have would be costly, so we just note where the label
8690 is and then later disable any optimization that would cross it. */
8691 if (GET_CODE (insn) == CODE_LABEL)
8692 last_label_ruid = reload_combine_ruid;
8693 else if (GET_CODE (insn) == BARRIER)
8694 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8695 if (! fixed_regs[r])
8696 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8698 if (! INSN_P (insn))
8701 reload_combine_ruid++;
8703 /* Look for (set (REGX) (CONST_INT))
8704 (set (REGX) (PLUS (REGX) (REGY)))
8706 ... (MEM (REGX)) ...
8708 (set (REGZ) (CONST_INT))
8710 ... (MEM (PLUS (REGZ) (REGY)))... .
8712 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8713 and that we know all uses of REGX before it dies. */
8714 set = single_set (insn);
8716 && GET_CODE (SET_DEST (set)) == REG
8717 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8718 GET_MODE (SET_DEST (set)))
8720 && GET_CODE (SET_SRC (set)) == PLUS
8721 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8722 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8723 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8725 rtx reg = SET_DEST (set);
8726 rtx plus = SET_SRC (set);
8727 rtx base = XEXP (plus, 1);
8728 rtx prev = prev_nonnote_insn (insn);
8729 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8730 unsigned int regno = REGNO (reg);
8731 rtx const_reg = NULL_RTX;
8732 rtx reg_sum = NULL_RTX;
8734 /* Now, we need an index register.
8735 We'll set index_reg to this index register, const_reg to the
8736 register that is to be loaded with the constant
8737 (denoted as REGZ in the substitution illustration above),
8738 and reg_sum to the register-register that we want to use to
8739 substitute uses of REG (typically in MEMs) with.
8740 First check REG and BASE for being index registers;
8741 we can use them even if they are not dead. */
8742 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8743 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8751 /* Otherwise, look for a free index register. Since we have
8752 checked above that neiter REG nor BASE are index registers,
8753 if we find anything at all, it will be different from these
8755 for (i = first_index_reg; i <= last_index_reg; i++)
8757 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8759 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8760 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8761 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8763 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8765 const_reg = index_reg;
8766 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8772 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8773 (REGY), i.e. BASE, is not clobbered before the last use we'll
8776 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8777 && rtx_equal_p (SET_DEST (prev_set), reg)
8778 && reg_state[regno].use_index >= 0
8779 && (reg_state[REGNO (base)].store_ruid
8780 <= reg_state[regno].use_ruid)
8785 /* Change destination register and, if necessary, the
8786 constant value in PREV, the constant loading instruction. */
8787 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8788 if (reg_state[regno].offset != const0_rtx)
8789 validate_change (prev,
8790 &SET_SRC (prev_set),
8791 GEN_INT (INTVAL (SET_SRC (prev_set))
8792 + INTVAL (reg_state[regno].offset)),
8795 /* Now for every use of REG that we have recorded, replace REG
8797 for (i = reg_state[regno].use_index;
8798 i < RELOAD_COMBINE_MAX_USES; i++)
8799 validate_change (reg_state[regno].reg_use[i].insn,
8800 reg_state[regno].reg_use[i].usep,
8801 /* Each change must have its own
8803 copy_rtx (reg_sum), 1);
8805 if (apply_change_group ())
8809 /* Delete the reg-reg addition. */
8812 if (reg_state[regno].offset != const0_rtx)
8813 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8815 for (np = ®_NOTES (prev); *np;)
8817 if (REG_NOTE_KIND (*np) == REG_EQUAL
8818 || REG_NOTE_KIND (*np) == REG_EQUIV)
8819 *np = XEXP (*np, 1);
8821 np = &XEXP (*np, 1);
8824 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8825 reg_state[REGNO (const_reg)].store_ruid
8826 = reload_combine_ruid;
8832 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8834 if (GET_CODE (insn) == CALL_INSN)
8838 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8839 if (call_used_regs[r])
8841 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8842 reg_state[r].store_ruid = reload_combine_ruid;
8845 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8846 link = XEXP (link, 1))
8848 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8849 if (GET_CODE (usage_rtx) == REG)
8852 unsigned int start_reg = REGNO (usage_rtx);
8853 unsigned int num_regs =
8854 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8855 unsigned int end_reg = start_reg + num_regs - 1;
8856 for (i = start_reg; i <= end_reg; i++)
8857 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8859 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8860 reg_state[i].store_ruid = reload_combine_ruid;
8863 reg_state[i].use_index = -1;
8868 else if (GET_CODE (insn) == JUMP_INSN
8869 && GET_CODE (PATTERN (insn)) != RETURN)
8871 /* Non-spill registers might be used at the call destination in
8872 some unknown fashion, so we have to mark the unknown use. */
8875 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8876 && JUMP_LABEL (insn))
8877 live = &LABEL_LIVE (JUMP_LABEL (insn));
8879 live = &ever_live_at_start;
8881 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8882 if (TEST_HARD_REG_BIT (*live, i))
8883 reg_state[i].use_index = -1;
8886 reload_combine_note_use (&PATTERN (insn), insn);
8887 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8889 if (REG_NOTE_KIND (note) == REG_INC
8890 && GET_CODE (XEXP (note, 0)) == REG)
8892 int regno = REGNO (XEXP (note, 0));
8894 reg_state[regno].store_ruid = reload_combine_ruid;
8895 reg_state[regno].use_index = -1;
8903 /* Check if DST is a register or a subreg of a register; if it is,
8904 update reg_state[regno].store_ruid and reg_state[regno].use_index
8905 accordingly. Called via note_stores from reload_combine. */
8908 reload_combine_note_store (dst, set, data)
8910 void *data ATTRIBUTE_UNUSED;
8914 enum machine_mode mode = GET_MODE (dst);
8916 if (GET_CODE (dst) == SUBREG)
8918 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8919 GET_MODE (SUBREG_REG (dst)),
8922 dst = SUBREG_REG (dst);
8924 if (GET_CODE (dst) != REG)
8926 regno += REGNO (dst);
8928 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8929 careful with registers / register parts that are not full words.
8931 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8932 if (GET_CODE (set) != SET
8933 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8934 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8935 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8937 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8939 reg_state[i].use_index = -1;
8940 reg_state[i].store_ruid = reload_combine_ruid;
8945 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8947 reg_state[i].store_ruid = reload_combine_ruid;
8948 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8953 /* XP points to a piece of rtl that has to be checked for any uses of
8955 *XP is the pattern of INSN, or a part of it.
8956 Called from reload_combine, and recursively by itself. */
8958 reload_combine_note_use (xp, insn)
8962 enum rtx_code code = x->code;
8965 rtx offset = const0_rtx; /* For the REG case below. */
8970 if (GET_CODE (SET_DEST (x)) == REG)
8972 reload_combine_note_use (&SET_SRC (x), insn);
8978 /* If this is the USE of a return value, we can't change it. */
8979 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8981 /* Mark the return register as used in an unknown fashion. */
8982 rtx reg = XEXP (x, 0);
8983 int regno = REGNO (reg);
8984 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8986 while (--nregs >= 0)
8987 reg_state[regno + nregs].use_index = -1;
8993 if (GET_CODE (SET_DEST (x)) == REG)
8995 /* No spurious CLOBBERs of pseudo registers may remain. */
8996 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER)
9003 /* We are interested in (plus (reg) (const_int)) . */
9004 if (GET_CODE (XEXP (x, 0)) != REG
9005 || GET_CODE (XEXP (x, 1)) != CONST_INT)
9007 offset = XEXP (x, 1);
9012 int regno = REGNO (x);
9016 /* No spurious USEs of pseudo registers may remain. */
9017 if (regno >= FIRST_PSEUDO_REGISTER)
9020 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
9022 /* We can't substitute into multi-hard-reg uses. */
9025 while (--nregs >= 0)
9026 reg_state[regno + nregs].use_index = -1;
9030 /* If this register is already used in some unknown fashion, we
9032 If we decrement the index from zero to -1, we can't store more
9033 uses, so this register becomes used in an unknown fashion. */
9034 use_index = --reg_state[regno].use_index;
9038 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9040 /* We have found another use for a register that is already
9041 used later. Check if the offsets match; if not, mark the
9042 register as used in an unknown fashion. */
9043 if (! rtx_equal_p (offset, reg_state[regno].offset))
9045 reg_state[regno].use_index = -1;
9051 /* This is the first use of this register we have seen since we
9052 marked it as dead. */
9053 reg_state[regno].offset = offset;
9054 reg_state[regno].use_ruid = reload_combine_ruid;
9056 reg_state[regno].reg_use[use_index].insn = insn;
9057 reg_state[regno].reg_use[use_index].usep = xp;
9065 /* Recursively process the components of X. */
9066 fmt = GET_RTX_FORMAT (code);
9067 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9070 reload_combine_note_use (&XEXP (x, i), insn);
9071 else if (fmt[i] == 'E')
9073 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9074 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9079 /* See if we can reduce the cost of a constant by replacing a move
9080 with an add. We track situations in which a register is set to a
9081 constant or to a register plus a constant. */
9082 /* We cannot do our optimization across labels. Invalidating all the
9083 information about register contents we have would be costly, so we
9084 use move2add_last_label_luid to note where the label is and then
9085 later disable any optimization that would cross it.
9086 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9087 reg_set_luid[n] is greater than move2add_last_label_luid. */
9088 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9090 /* If reg_base_reg[n] is negative, register n has been set to
9091 reg_offset[n] in mode reg_mode[n] .
9092 If reg_base_reg[n] is non-negative, register n has been set to the
9093 sum of reg_offset[n] and the value of register reg_base_reg[n]
9094 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9095 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9096 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9097 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9099 /* move2add_luid is linearly increased while scanning the instructions
9100 from first to last. It is used to set reg_set_luid in
9101 reload_cse_move2add and move2add_note_store. */
9102 static int move2add_luid;
9104 /* move2add_last_label_luid is set whenever a label is found. Labels
9105 invalidate all previously collected reg_offset data. */
9106 static int move2add_last_label_luid;
9108 /* ??? We don't know how zero / sign extension is handled, hence we
9109 can't go from a narrower to a wider mode. */
9110 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9111 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9112 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9113 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9114 GET_MODE_BITSIZE (INMODE))))
9117 reload_cse_move2add (first)
9123 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9124 reg_set_luid[i] = 0;
9126 move2add_last_label_luid = 0;
9128 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9132 if (GET_CODE (insn) == CODE_LABEL)
9134 move2add_last_label_luid = move2add_luid;
9135 /* We're going to increment move2add_luid twice after a
9136 label, so that we can use move2add_last_label_luid + 1 as
9137 the luid for constants. */
9141 if (! INSN_P (insn))
9143 pat = PATTERN (insn);
9144 /* For simplicity, we only perform this optimization on
9145 straightforward SETs. */
9146 if (GET_CODE (pat) == SET
9147 && GET_CODE (SET_DEST (pat)) == REG)
9149 rtx reg = SET_DEST (pat);
9150 int regno = REGNO (reg);
9151 rtx src = SET_SRC (pat);
9153 /* Check if we have valid information on the contents of this
9154 register in the mode of REG. */
9155 if (reg_set_luid[regno] > move2add_last_label_luid
9156 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9158 /* Try to transform (set (REGX) (CONST_INT A))
9160 (set (REGX) (CONST_INT B))
9162 (set (REGX) (CONST_INT A))
9164 (set (REGX) (plus (REGX) (CONST_INT B-A)))
9166 (set (REGX) (CONST_INT A))
9168 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
9171 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9174 GEN_INT (trunc_int_for_mode (INTVAL (src)
9175 - reg_offset[regno],
9177 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9178 use (set (reg) (reg)) instead.
9179 We don't delete this insn, nor do we convert it into a
9180 note, to avoid losing register notes or the return
9181 value flag. jump2 already knows how to get rid of
9183 if (new_src == const0_rtx)
9185 /* If the constants are different, this is a
9186 truncation, that, if turned into (set (reg)
9187 (reg)), would be discarded. Maybe we should
9188 try a truncMN pattern? */
9189 if (INTVAL (src) == reg_offset [regno])
9190 validate_change (insn, &SET_SRC (pat), reg, 0);
9192 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9193 && have_add2_insn (reg, new_src))
9195 rtx newpat = gen_add2_insn (reg, new_src);
9196 if (INSN_P (newpat) && NEXT_INSN (newpat) == NULL_RTX)
9197 newpat = PATTERN (newpat);
9198 /* If it was the first insn of a sequence or
9199 some other emitted insn, validate_change will
9201 validate_change (insn, &PATTERN (insn),
9206 enum machine_mode narrow_mode;
9207 for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
9208 narrow_mode != GET_MODE (reg);
9209 narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
9211 if (have_insn_for (STRICT_LOW_PART, narrow_mode)
9212 && ((reg_offset[regno]
9213 & ~GET_MODE_MASK (narrow_mode))
9215 & ~GET_MODE_MASK (narrow_mode))))
9217 rtx narrow_reg = gen_rtx_REG (narrow_mode,
9220 GEN_INT (trunc_int_for_mode (INTVAL (src),
9223 gen_rtx_SET (VOIDmode,
9224 gen_rtx_STRICT_LOW_PART (VOIDmode,
9227 if (validate_change (insn, &PATTERN (insn),
9233 reg_set_luid[regno] = move2add_luid;
9234 reg_mode[regno] = GET_MODE (reg);
9235 reg_offset[regno] = INTVAL (src);
9239 /* Try to transform (set (REGX) (REGY))
9240 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9243 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9246 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9248 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9249 else if (GET_CODE (src) == REG
9250 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9251 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9252 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9253 reg_mode[REGNO (src)]))
9255 rtx next = next_nonnote_insn (insn);
9258 set = single_set (next);
9260 && SET_DEST (set) == reg
9261 && GET_CODE (SET_SRC (set)) == PLUS
9262 && XEXP (SET_SRC (set), 0) == reg
9263 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9265 rtx src3 = XEXP (SET_SRC (set), 1);
9266 HOST_WIDE_INT added_offset = INTVAL (src3);
9267 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9268 HOST_WIDE_INT regno_offset = reg_offset[regno];
9270 GEN_INT (trunc_int_for_mode (added_offset
9276 if (new_src == const0_rtx)
9277 /* See above why we create (set (reg) (reg)) here. */
9279 = validate_change (next, &SET_SRC (set), reg, 0);
9280 else if ((rtx_cost (new_src, PLUS)
9281 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9282 && have_add2_insn (reg, new_src))
9284 rtx newpat = gen_add2_insn (reg, new_src);
9286 && NEXT_INSN (newpat) == NULL_RTX)
9287 newpat = PATTERN (newpat);
9289 = validate_change (next, &PATTERN (next),
9295 reg_mode[regno] = GET_MODE (reg);
9297 trunc_int_for_mode (added_offset + base_offset,
9305 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9307 if (REG_NOTE_KIND (note) == REG_INC
9308 && GET_CODE (XEXP (note, 0)) == REG)
9310 /* Reset the information about this register. */
9311 int regno = REGNO (XEXP (note, 0));
9312 if (regno < FIRST_PSEUDO_REGISTER)
9313 reg_set_luid[regno] = 0;
9316 note_stores (PATTERN (insn), move2add_note_store, NULL);
9318 /* If INSN is a conditional branch, we try to extract an
9319 implicit set out of it. */
9320 if (any_condjump_p (insn) && onlyjump_p (insn))
9322 rtx cnd = fis_get_condition (insn);
9325 && GET_CODE (cnd) == NE
9326 && GET_CODE (XEXP (cnd, 0)) == REG
9327 /* The following two checks, which are also in
9328 move2add_note_store, are intended to reduce the
9329 number of calls to gen_rtx_SET to avoid memory
9330 allocation if possible. */
9331 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0)))
9332 && HARD_REGNO_NREGS (REGNO (XEXP (cnd, 0)), GET_MODE (XEXP (cnd, 0))) == 1
9333 && GET_CODE (XEXP (cnd, 1)) == CONST_INT)
9336 gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1));
9337 move2add_note_store (SET_DEST (implicit_set), implicit_set, 0);
9341 /* If this is a CALL_INSN, all call used registers are stored with
9343 if (GET_CODE (insn) == CALL_INSN)
9345 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9347 if (call_used_regs[i])
9348 /* Reset the information about this register. */
9349 reg_set_luid[i] = 0;
9355 /* SET is a SET or CLOBBER that sets DST.
9356 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9357 Called from reload_cse_move2add via note_stores. */
9360 move2add_note_store (dst, set, data)
9362 void *data ATTRIBUTE_UNUSED;
9364 unsigned int regno = 0;
9366 enum machine_mode mode = GET_MODE (dst);
9368 if (GET_CODE (dst) == SUBREG)
9370 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9371 GET_MODE (SUBREG_REG (dst)),
9374 dst = SUBREG_REG (dst);
9377 /* Some targets do argument pushes without adding REG_INC notes. */
9379 if (GET_CODE (dst) == MEM)
9381 dst = XEXP (dst, 0);
9382 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9383 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9384 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9387 if (GET_CODE (dst) != REG)
9390 regno += REGNO (dst);
9392 if (SCALAR_INT_MODE_P (mode)
9393 && HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9394 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9395 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9396 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9398 rtx src = SET_SRC (set);
9400 HOST_WIDE_INT offset;
9402 /* This may be different from mode, if SET_DEST (set) is a
9404 enum machine_mode dst_mode = GET_MODE (dst);
9406 switch (GET_CODE (src))
9409 if (GET_CODE (XEXP (src, 0)) == REG)
9411 base_reg = XEXP (src, 0);
9413 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9414 offset = INTVAL (XEXP (src, 1));
9415 else if (GET_CODE (XEXP (src, 1)) == REG
9416 && (reg_set_luid[REGNO (XEXP (src, 1))]
9417 > move2add_last_label_luid)
9418 && (MODES_OK_FOR_MOVE2ADD
9419 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9421 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9422 offset = reg_offset[REGNO (XEXP (src, 1))];
9423 /* Maybe the first register is known to be a
9425 else if (reg_set_luid[REGNO (base_reg)]
9426 > move2add_last_label_luid
9427 && (MODES_OK_FOR_MOVE2ADD
9428 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9429 && reg_base_reg[REGNO (base_reg)] < 0)
9431 offset = reg_offset[REGNO (base_reg)];
9432 base_reg = XEXP (src, 1);
9451 /* Start tracking the register as a constant. */
9452 reg_base_reg[regno] = -1;
9453 reg_offset[regno] = INTVAL (SET_SRC (set));
9454 /* We assign the same luid to all registers set to constants. */
9455 reg_set_luid[regno] = move2add_last_label_luid + 1;
9456 reg_mode[regno] = mode;
9461 /* Invalidate the contents of the register. */
9462 reg_set_luid[regno] = 0;
9466 base_regno = REGNO (base_reg);
9467 /* If information about the base register is not valid, set it
9468 up as a new base register, pretending its value is known
9469 starting from the current insn. */
9470 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9472 reg_base_reg[base_regno] = base_regno;
9473 reg_offset[base_regno] = 0;
9474 reg_set_luid[base_regno] = move2add_luid;
9475 reg_mode[base_regno] = mode;
9477 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9478 reg_mode[base_regno]))
9481 reg_mode[regno] = mode;
9483 /* Copy base information from our base register. */
9484 reg_set_luid[regno] = reg_set_luid[base_regno];
9485 reg_base_reg[regno] = reg_base_reg[base_regno];
9487 /* Compute the sum of the offsets or constants. */
9488 reg_offset[regno] = trunc_int_for_mode (offset
9489 + reg_offset[base_regno],
9494 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9496 for (i = regno; i < endregno; i++)
9497 /* Reset the information about this register. */
9498 reg_set_luid[i] = 0;
9504 add_auto_inc_notes (insn, x)
9508 enum rtx_code code = GET_CODE (x);
9512 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9515 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9519 /* Scan all the operand sub-expressions. */
9520 fmt = GET_RTX_FORMAT (code);
9521 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9524 add_auto_inc_notes (insn, XEXP (x, i));
9525 else if (fmt[i] == 'E')
9526 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9527 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9532 /* Copy EH notes from an insn to its reloads. */
9534 copy_eh_notes (insn, x)
9538 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9541 for (; x != 0; x = NEXT_INSN (x))
9543 if (may_trap_p (PATTERN (x)))
9545 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9551 /* This is used by reload pass, that does emit some instructions after
9552 abnormal calls moving basic block end, but in fact it wants to emit
9553 them on the edge. Looks for abnormal call edges, find backward the
9554 proper call and fix the damage.
9556 Similar handle instructions throwing exceptions internally. */
9558 fixup_abnormal_edges ()
9560 bool inserted = false;
9567 /* Look for cases we are interested in - calls or instructions causing
9569 for (e = bb->succ; e; e = e->succ_next)
9571 if (e->flags & EDGE_ABNORMAL_CALL)
9573 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9574 == (EDGE_ABNORMAL | EDGE_EH))
9577 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9579 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9581 for (e = bb->succ; e; e = e->succ_next)
9582 if (e->flags & EDGE_FALLTHRU)
9584 /* Get past the new insns generated. Allow notes, as the insns may
9585 be already deleted. */
9586 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9587 && !can_throw_internal (insn)
9588 && insn != bb->head)
9589 insn = PREV_INSN (insn);
9590 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9594 insn = NEXT_INSN (insn);
9595 while (insn && insn != stop)
9597 next = NEXT_INSN (insn);
9602 /* Sometimes there's still the return value USE.
9603 If it's placed after a trapping call (i.e. that
9604 call is the last insn anyway), we have no fallthru
9605 edge. Simply delete this use and don't try to insert
9606 on the non-existent edge. */
9607 if (GET_CODE (PATTERN (insn)) != USE)
9609 /* We're not deleting it, we're moving it. */
9610 INSN_DELETED_P (insn) = 0;
9611 PREV_INSN (insn) = NULL_RTX;
9612 NEXT_INSN (insn) = NULL_RTX;
9614 insert_insn_on_edge (insn, e);
9621 /* We've possibly turned single trapping insn into multiple ones. */
9622 if (flag_non_call_exceptions)
9625 blocks = sbitmap_alloc (last_basic_block);
9626 sbitmap_ones (blocks);
9627 find_many_sub_basic_blocks (blocks);
9630 commit_edge_insertions ();
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