1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 static struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 static char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 static char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static bool verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void scan_paradoxical_subregs (rtx);
394 static void count_pseudo (int);
395 static void order_regs_for_reload (struct insn_chain *);
396 static void reload_as_needed (int);
397 static void forget_old_reloads_1 (rtx, rtx, void *);
398 static int reload_reg_class_lower (const void *, const void *);
399 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
401 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
403 static int reload_reg_free_p (unsigned int, int, enum reload_type);
404 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
406 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
408 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
409 static int allocate_reload_reg (struct insn_chain *, int, int);
410 static int conflicts_with_override (rtx);
411 static void failed_reload (rtx, int);
412 static int set_reload_reg (int, int);
413 static void choose_reload_regs_init (struct insn_chain *, rtx *);
414 static void choose_reload_regs (struct insn_chain *);
415 static void merge_assigned_reloads (rtx);
416 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
418 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
420 static void do_input_reload (struct insn_chain *, struct reload *, int);
421 static void do_output_reload (struct insn_chain *, struct reload *, int);
422 static bool inherit_piecemeal_p (int, int);
423 static void emit_reload_insns (struct insn_chain *);
424 static void delete_output_reload (rtx, int, int);
425 static void delete_address_reloads (rtx, rtx);
426 static void delete_address_reloads_1 (rtx, rtx, rtx);
427 static rtx inc_for_reload (rtx, rtx, rtx, int);
429 static void add_auto_inc_notes (rtx, rtx);
431 static void copy_eh_notes (rtx, rtx);
432 static int reloads_conflict (int, int);
433 static rtx gen_reload (rtx, rtx, int, enum reload_type);
435 /* Initialize the reload pass once per compilation. */
442 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
443 Set spill_indirect_levels to the number of levels such addressing is
444 permitted, zero if it is not permitted at all. */
447 = gen_rtx_MEM (Pmode,
450 LAST_VIRTUAL_REGISTER + 1),
452 spill_indirect_levels = 0;
454 while (memory_address_p (QImode, tem))
456 spill_indirect_levels++;
457 tem = gen_rtx_MEM (Pmode, tem);
460 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
462 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
463 indirect_symref_ok = memory_address_p (QImode, tem);
465 /* See if reg+reg is a valid (and offsettable) address. */
467 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
469 tem = gen_rtx_PLUS (Pmode,
470 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
471 gen_rtx_REG (Pmode, i));
473 /* This way, we make sure that reg+reg is an offsettable address. */
474 tem = plus_constant (tem, 4);
476 if (memory_address_p (QImode, tem))
478 double_reg_address_ok = 1;
483 /* Initialize obstack for our rtl allocation. */
484 gcc_obstack_init (&reload_obstack);
485 reload_startobj = obstack_alloc (&reload_obstack, 0);
487 INIT_REG_SET (&spilled_pseudos);
488 INIT_REG_SET (&pseudos_counted);
489 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
492 /* List of insn chains that are currently unused. */
493 static struct insn_chain *unused_insn_chains = 0;
495 /* Allocate an empty insn_chain structure. */
497 new_insn_chain (void)
499 struct insn_chain *c;
501 if (unused_insn_chains == 0)
503 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
504 INIT_REG_SET (&c->live_throughout);
505 INIT_REG_SET (&c->dead_or_set);
509 c = unused_insn_chains;
510 unused_insn_chains = c->next;
512 c->is_caller_save_insn = 0;
513 c->need_operand_change = 0;
519 /* Small utility function to set all regs in hard reg set TO which are
520 allocated to pseudos in regset FROM. */
523 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
526 reg_set_iterator rsi;
528 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
530 int r = reg_renumber[regno];
535 /* reload_combine uses the information from
536 BASIC_BLOCK->global_live_at_start, which might still
537 contain registers that have not actually been allocated
538 since they have an equivalence. */
539 gcc_assert (reload_completed);
543 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
545 SET_HARD_REG_BIT (*to, r + nregs);
550 /* Replace all pseudos found in LOC with their corresponding
554 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
567 unsigned int regno = REGNO (x);
569 if (regno < FIRST_PSEUDO_REGISTER)
572 x = eliminate_regs (x, mem_mode, usage);
576 replace_pseudos_in (loc, mem_mode, usage);
580 if (reg_equiv_constant[regno])
581 *loc = reg_equiv_constant[regno];
582 else if (reg_equiv_mem[regno])
583 *loc = reg_equiv_mem[regno];
584 else if (reg_equiv_address[regno])
585 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
588 gcc_assert (!REG_P (regno_reg_rtx[regno])
589 || REGNO (regno_reg_rtx[regno]) != regno);
590 *loc = regno_reg_rtx[regno];
595 else if (code == MEM)
597 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
601 /* Process each of our operands recursively. */
602 fmt = GET_RTX_FORMAT (code);
603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
605 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
606 else if (*fmt == 'E')
607 for (j = 0; j < XVECLEN (x, i); j++)
608 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
612 /* Global variables used by reload and its subroutines. */
614 /* Set during calculate_needs if an insn needs register elimination. */
615 static int something_needs_elimination;
616 /* Set during calculate_needs if an insn needs an operand changed. */
617 static int something_needs_operands_changed;
619 /* Nonzero means we couldn't get enough spill regs. */
622 /* Main entry point for the reload pass.
624 FIRST is the first insn of the function being compiled.
626 GLOBAL nonzero means we were called from global_alloc
627 and should attempt to reallocate any pseudoregs that we
628 displace from hard regs we will use for reloads.
629 If GLOBAL is zero, we do not have enough information to do that,
630 so any pseudo reg that is spilled must go to the stack.
632 Return value is nonzero if reload failed
633 and we must not do any more for this function. */
636 reload (rtx first, int global)
640 struct elim_table *ep;
643 /* Make sure even insns with volatile mem refs are recognizable. */
648 reload_firstobj = obstack_alloc (&reload_obstack, 0);
650 /* Make sure that the last insn in the chain
651 is not something that needs reloading. */
652 emit_note (NOTE_INSN_DELETED);
654 /* Enable find_equiv_reg to distinguish insns made by reload. */
655 reload_first_uid = get_max_uid ();
657 #ifdef SECONDARY_MEMORY_NEEDED
658 /* Initialize the secondary memory table. */
659 clear_secondary_mem ();
662 /* We don't have a stack slot for any spill reg yet. */
663 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
664 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
666 /* Initialize the save area information for caller-save, in case some
670 /* Compute which hard registers are now in use
671 as homes for pseudo registers.
672 This is done here rather than (eg) in global_alloc
673 because this point is reached even if not optimizing. */
674 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
677 /* A function that receives a nonlocal goto must save all call-saved
679 if (current_function_has_nonlocal_label)
680 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
681 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
682 regs_ever_live[i] = 1;
684 /* Find all the pseudo registers that didn't get hard regs
685 but do have known equivalent constants or memory slots.
686 These include parameters (known equivalent to parameter slots)
687 and cse'd or loop-moved constant memory addresses.
689 Record constant equivalents in reg_equiv_constant
690 so they will be substituted by find_reloads.
691 Record memory equivalents in reg_mem_equiv so they can
692 be substituted eventually by altering the REG-rtx's. */
694 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
695 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
696 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
697 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
698 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
699 reg_old_renumber = xcalloc (max_regno, sizeof (short));
700 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
701 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
702 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
704 CLEAR_HARD_REG_SET (bad_spill_regs_global);
706 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
707 to. Also find all paradoxical subregs and find largest such for
710 num_eliminable_invariants = 0;
711 for (insn = first; insn; insn = NEXT_INSN (insn))
713 rtx set = single_set (insn);
715 /* We may introduce USEs that we want to remove at the end, so
716 we'll mark them with QImode. Make sure there are no
717 previously-marked insns left by say regmove. */
718 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
719 && GET_MODE (insn) != VOIDmode)
720 PUT_MODE (insn, VOIDmode);
722 if (set != 0 && REG_P (SET_DEST (set)))
724 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
726 && (! function_invariant_p (XEXP (note, 0))
728 /* A function invariant is often CONSTANT_P but may
729 include a register. We promise to only pass
730 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
731 || (CONSTANT_P (XEXP (note, 0))
732 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))))
734 rtx x = XEXP (note, 0);
735 i = REGNO (SET_DEST (set));
736 if (i > LAST_VIRTUAL_REGISTER)
738 /* It can happen that a REG_EQUIV note contains a MEM
739 that is not a legitimate memory operand. As later
740 stages of reload assume that all addresses found
741 in the reg_equiv_* arrays were originally legitimate,
743 It can also happen that a REG_EQUIV note contains a
744 readonly memory location. If the destination pseudo
745 is set from some other value (typically a different
746 pseudo), and the destination pseudo does not get a
747 hard reg, then reload will replace the destination
748 pseudo with its equivalent memory location. This
749 is horribly bad as it creates a store to a readonly
750 memory location and a runtime segfault. To avoid
751 this problem we reject readonly memory locations
752 for equivalences. This is overly conservative as
753 we could find all sets of the destination pseudo
754 and remove them as they should be redundant. */
755 if (memory_operand (x, VOIDmode) && ! MEM_READONLY_P (x))
757 /* Always unshare the equivalence, so we can
758 substitute into this insn without touching the
760 reg_equiv_memory_loc[i] = copy_rtx (x);
762 else if (function_invariant_p (x))
764 if (GET_CODE (x) == PLUS)
766 /* This is PLUS of frame pointer and a constant,
767 and might be shared. Unshare it. */
768 reg_equiv_constant[i] = copy_rtx (x);
769 num_eliminable_invariants++;
771 else if (x == frame_pointer_rtx
772 || x == arg_pointer_rtx)
774 reg_equiv_constant[i] = x;
775 num_eliminable_invariants++;
777 else if (LEGITIMATE_CONSTANT_P (x))
778 reg_equiv_constant[i] = x;
781 reg_equiv_memory_loc[i]
782 = force_const_mem (GET_MODE (SET_DEST (set)), x);
783 if (!reg_equiv_memory_loc[i])
790 /* If this register is being made equivalent to a MEM
791 and the MEM is not SET_SRC, the equivalencing insn
792 is one with the MEM as a SET_DEST and it occurs later.
793 So don't mark this insn now. */
795 || rtx_equal_p (SET_SRC (set), x))
797 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
802 /* If this insn is setting a MEM from a register equivalent to it,
803 this is the equivalencing insn. */
804 else if (set && MEM_P (SET_DEST (set))
805 && REG_P (SET_SRC (set))
806 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
807 && rtx_equal_p (SET_DEST (set),
808 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
809 reg_equiv_init[REGNO (SET_SRC (set))]
810 = gen_rtx_INSN_LIST (VOIDmode, insn,
811 reg_equiv_init[REGNO (SET_SRC (set))]);
814 scan_paradoxical_subregs (PATTERN (insn));
819 first_label_num = get_first_label_num ();
820 num_labels = max_label_num () - first_label_num;
822 /* Allocate the tables used to store offset information at labels. */
823 /* We used to use alloca here, but the size of what it would try to
824 allocate would occasionally cause it to exceed the stack limit and
825 cause a core dump. */
826 offsets_known_at = xmalloc (num_labels);
827 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
829 /* Alter each pseudo-reg rtx to contain its hard reg number.
830 Assign stack slots to the pseudos that lack hard regs or equivalents.
831 Do not touch virtual registers. */
833 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
836 /* If we have some registers we think can be eliminated, scan all insns to
837 see if there is an insn that sets one of these registers to something
838 other than itself plus a constant. If so, the register cannot be
839 eliminated. Doing this scan here eliminates an extra pass through the
840 main reload loop in the most common case where register elimination
842 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
844 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
846 maybe_fix_stack_asms ();
848 insns_need_reload = 0;
849 something_needs_elimination = 0;
851 /* Initialize to -1, which means take the first spill register. */
854 /* Spill any hard regs that we know we can't eliminate. */
855 CLEAR_HARD_REG_SET (used_spill_regs);
856 /* There can be multiple ways to eliminate a register;
857 they should be listed adjacently.
858 Elimination for any register fails only if all possible ways fail. */
859 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
862 int can_eliminate = 0;
865 can_eliminate |= ep->can_eliminate;
868 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
870 spill_hard_reg (from, 1);
873 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
874 if (frame_pointer_needed)
875 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
877 finish_spills (global);
879 /* From now on, we may need to generate moves differently. We may also
880 allow modifications of insns which cause them to not be recognized.
881 Any such modifications will be cleaned up during reload itself. */
882 reload_in_progress = 1;
884 /* This loop scans the entire function each go-round
885 and repeats until one repetition spills no additional hard regs. */
888 int something_changed;
891 HOST_WIDE_INT starting_frame_size;
893 /* Round size of stack frame to stack_alignment_needed. This must be done
894 here because the stack size may be a part of the offset computation
895 for register elimination, and there might have been new stack slots
896 created in the last iteration of this loop. */
897 if (cfun->stack_alignment_needed)
898 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
900 starting_frame_size = get_frame_size ();
902 set_initial_elim_offsets ();
903 set_initial_label_offsets ();
905 /* For each pseudo register that has an equivalent location defined,
906 try to eliminate any eliminable registers (such as the frame pointer)
907 assuming initial offsets for the replacement register, which
910 If the resulting location is directly addressable, substitute
911 the MEM we just got directly for the old REG.
913 If it is not addressable but is a constant or the sum of a hard reg
914 and constant, it is probably not addressable because the constant is
915 out of range, in that case record the address; we will generate
916 hairy code to compute the address in a register each time it is
917 needed. Similarly if it is a hard register, but one that is not
918 valid as an address register.
920 If the location is not addressable, but does not have one of the
921 above forms, assign a stack slot. We have to do this to avoid the
922 potential of producing lots of reloads if, e.g., a location involves
923 a pseudo that didn't get a hard register and has an equivalent memory
924 location that also involves a pseudo that didn't get a hard register.
926 Perhaps at some point we will improve reload_when_needed handling
927 so this problem goes away. But that's very hairy. */
929 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
930 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
932 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
934 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
936 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
937 else if (CONSTANT_P (XEXP (x, 0))
938 || (REG_P (XEXP (x, 0))
939 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
940 || (GET_CODE (XEXP (x, 0)) == PLUS
941 && REG_P (XEXP (XEXP (x, 0), 0))
942 && (REGNO (XEXP (XEXP (x, 0), 0))
943 < FIRST_PSEUDO_REGISTER)
944 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
945 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
948 /* Make a new stack slot. Then indicate that something
949 changed so we go back and recompute offsets for
950 eliminable registers because the allocation of memory
951 below might change some offset. reg_equiv_{mem,address}
952 will be set up for this pseudo on the next pass around
954 reg_equiv_memory_loc[i] = 0;
955 reg_equiv_init[i] = 0;
960 if (caller_save_needed)
963 /* If we allocated another stack slot, redo elimination bookkeeping. */
964 if (starting_frame_size != get_frame_size ())
967 if (caller_save_needed)
969 save_call_clobbered_regs ();
970 /* That might have allocated new insn_chain structures. */
971 reload_firstobj = obstack_alloc (&reload_obstack, 0);
974 calculate_needs_all_insns (global);
976 CLEAR_REG_SET (&spilled_pseudos);
979 something_changed = 0;
981 /* If we allocated any new memory locations, make another pass
982 since it might have changed elimination offsets. */
983 if (starting_frame_size != get_frame_size ())
984 something_changed = 1;
986 /* Even if the frame size remained the same, we might still have
987 changed elimination offsets, e.g. if find_reloads called
988 force_const_mem requiring the back end to allocate a constant
989 pool base register that needs to be saved on the stack. */
990 else if (!verify_initial_elim_offsets ())
991 something_changed = 1;
994 HARD_REG_SET to_spill;
995 CLEAR_HARD_REG_SET (to_spill);
996 update_eliminables (&to_spill);
997 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
998 if (TEST_HARD_REG_BIT (to_spill, i))
1000 spill_hard_reg (i, 1);
1003 /* Regardless of the state of spills, if we previously had
1004 a register that we thought we could eliminate, but now can
1005 not eliminate, we must run another pass.
1007 Consider pseudos which have an entry in reg_equiv_* which
1008 reference an eliminable register. We must make another pass
1009 to update reg_equiv_* so that we do not substitute in the
1010 old value from when we thought the elimination could be
1012 something_changed = 1;
1016 select_reload_regs ();
1020 if (insns_need_reload != 0 || did_spill)
1021 something_changed |= finish_spills (global);
1023 if (! something_changed)
1026 if (caller_save_needed)
1027 delete_caller_save_insns ();
1029 obstack_free (&reload_obstack, reload_firstobj);
1032 /* If global-alloc was run, notify it of any register eliminations we have
1035 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1036 if (ep->can_eliminate)
1037 mark_elimination (ep->from, ep->to);
1039 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1040 If that insn didn't set the register (i.e., it copied the register to
1041 memory), just delete that insn instead of the equivalencing insn plus
1042 anything now dead. If we call delete_dead_insn on that insn, we may
1043 delete the insn that actually sets the register if the register dies
1044 there and that is incorrect. */
1046 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1048 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1051 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1053 rtx equiv_insn = XEXP (list, 0);
1055 /* If we already deleted the insn or if it may trap, we can't
1056 delete it. The latter case shouldn't happen, but can
1057 if an insn has a variable address, gets a REG_EH_REGION
1058 note added to it, and then gets converted into an load
1059 from a constant address. */
1060 if (NOTE_P (equiv_insn)
1061 || can_throw_internal (equiv_insn))
1063 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1064 delete_dead_insn (equiv_insn);
1066 SET_INSN_DELETED (equiv_insn);
1071 /* Use the reload registers where necessary
1072 by generating move instructions to move the must-be-register
1073 values into or out of the reload registers. */
1075 if (insns_need_reload != 0 || something_needs_elimination
1076 || something_needs_operands_changed)
1078 HOST_WIDE_INT old_frame_size = get_frame_size ();
1080 reload_as_needed (global);
1082 gcc_assert (old_frame_size == get_frame_size ());
1084 gcc_assert (verify_initial_elim_offsets ());
1087 /* If we were able to eliminate the frame pointer, show that it is no
1088 longer live at the start of any basic block. If it ls live by
1089 virtue of being in a pseudo, that pseudo will be marked live
1090 and hence the frame pointer will be known to be live via that
1093 if (! frame_pointer_needed)
1095 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1096 HARD_FRAME_POINTER_REGNUM);
1098 /* Come here (with failure set nonzero) if we can't get enough spill
1102 CLEAR_REG_SET (&spilled_pseudos);
1103 reload_in_progress = 0;
1105 /* Now eliminate all pseudo regs by modifying them into
1106 their equivalent memory references.
1107 The REG-rtx's for the pseudos are modified in place,
1108 so all insns that used to refer to them now refer to memory.
1110 For a reg that has a reg_equiv_address, all those insns
1111 were changed by reloading so that no insns refer to it any longer;
1112 but the DECL_RTL of a variable decl may refer to it,
1113 and if so this causes the debugging info to mention the variable. */
1115 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1119 if (reg_equiv_mem[i])
1120 addr = XEXP (reg_equiv_mem[i], 0);
1122 if (reg_equiv_address[i])
1123 addr = reg_equiv_address[i];
1127 if (reg_renumber[i] < 0)
1129 rtx reg = regno_reg_rtx[i];
1131 REG_USERVAR_P (reg) = 0;
1132 PUT_CODE (reg, MEM);
1133 XEXP (reg, 0) = addr;
1134 if (reg_equiv_memory_loc[i])
1135 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1138 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1139 MEM_ATTRS (reg) = 0;
1142 else if (reg_equiv_mem[i])
1143 XEXP (reg_equiv_mem[i], 0) = addr;
1147 /* We must set reload_completed now since the cleanup_subreg_operands call
1148 below will re-recognize each insn and reload may have generated insns
1149 which are only valid during and after reload. */
1150 reload_completed = 1;
1152 /* Make a pass over all the insns and delete all USEs which we inserted
1153 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1154 notes. Delete all CLOBBER insns, except those that refer to the return
1155 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1156 from misarranging variable-array code, and simplify (subreg (reg))
1157 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1158 are no longer useful or accurate. Strip and regenerate REG_INC notes
1159 that may have been moved around. */
1161 for (insn = first; insn; insn = NEXT_INSN (insn))
1167 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1168 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1170 if ((GET_CODE (PATTERN (insn)) == USE
1171 /* We mark with QImode USEs introduced by reload itself. */
1172 && (GET_MODE (insn) == QImode
1173 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1174 || (GET_CODE (PATTERN (insn)) == CLOBBER
1175 && (!MEM_P (XEXP (PATTERN (insn), 0))
1176 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1177 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1178 && XEXP (XEXP (PATTERN (insn), 0), 0)
1179 != stack_pointer_rtx))
1180 && (!REG_P (XEXP (PATTERN (insn), 0))
1181 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1187 /* Some CLOBBERs may survive until here and still reference unassigned
1188 pseudos with const equivalent, which may in turn cause ICE in later
1189 passes if the reference remains in place. */
1190 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1191 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1192 VOIDmode, PATTERN (insn));
1194 /* Discard obvious no-ops, even without -O. This optimization
1195 is fast and doesn't interfere with debugging. */
1196 if (NONJUMP_INSN_P (insn)
1197 && GET_CODE (PATTERN (insn)) == SET
1198 && REG_P (SET_SRC (PATTERN (insn)))
1199 && REG_P (SET_DEST (PATTERN (insn)))
1200 && (REGNO (SET_SRC (PATTERN (insn)))
1201 == REGNO (SET_DEST (PATTERN (insn)))))
1207 pnote = ®_NOTES (insn);
1210 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1211 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1212 || REG_NOTE_KIND (*pnote) == REG_INC
1213 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1214 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1215 *pnote = XEXP (*pnote, 1);
1217 pnote = &XEXP (*pnote, 1);
1221 add_auto_inc_notes (insn, PATTERN (insn));
1224 /* And simplify (subreg (reg)) if it appears as an operand. */
1225 cleanup_subreg_operands (insn);
1228 /* If we are doing stack checking, give a warning if this function's
1229 frame size is larger than we expect. */
1230 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1232 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1233 static int verbose_warned = 0;
1235 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1236 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1237 size += UNITS_PER_WORD;
1239 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1241 warning (0, "frame size too large for reliable stack checking");
1242 if (! verbose_warned)
1244 warning (0, "try reducing the number of local variables");
1250 /* Indicate that we no longer have known memory locations or constants. */
1251 if (reg_equiv_constant)
1252 free (reg_equiv_constant);
1253 reg_equiv_constant = 0;
1254 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1255 reg_equiv_memory_loc = 0;
1257 if (offsets_known_at)
1258 free (offsets_known_at);
1262 free (reg_equiv_mem);
1263 free (reg_equiv_init);
1264 free (reg_equiv_address);
1265 free (reg_max_ref_width);
1266 free (reg_old_renumber);
1267 free (pseudo_previous_regs);
1268 free (pseudo_forbidden_regs);
1270 CLEAR_HARD_REG_SET (used_spill_regs);
1271 for (i = 0; i < n_spills; i++)
1272 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1274 /* Free all the insn_chain structures at once. */
1275 obstack_free (&reload_obstack, reload_startobj);
1276 unused_insn_chains = 0;
1277 fixup_abnormal_edges ();
1279 /* Replacing pseudos with their memory equivalents might have
1280 created shared rtx. Subsequent passes would get confused
1281 by this, so unshare everything here. */
1282 unshare_all_rtl_again (first);
1284 #ifdef STACK_BOUNDARY
1285 /* init_emit has set the alignment of the hard frame pointer
1286 to STACK_BOUNDARY. It is very likely no longer valid if
1287 the hard frame pointer was used for register allocation. */
1288 if (!frame_pointer_needed)
1289 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1295 /* Yet another special case. Unfortunately, reg-stack forces people to
1296 write incorrect clobbers in asm statements. These clobbers must not
1297 cause the register to appear in bad_spill_regs, otherwise we'll call
1298 fatal_insn later. We clear the corresponding regnos in the live
1299 register sets to avoid this.
1300 The whole thing is rather sick, I'm afraid. */
1303 maybe_fix_stack_asms (void)
1306 const char *constraints[MAX_RECOG_OPERANDS];
1307 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1308 struct insn_chain *chain;
1310 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1313 HARD_REG_SET clobbered, allowed;
1316 if (! INSN_P (chain->insn)
1317 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1319 pat = PATTERN (chain->insn);
1320 if (GET_CODE (pat) != PARALLEL)
1323 CLEAR_HARD_REG_SET (clobbered);
1324 CLEAR_HARD_REG_SET (allowed);
1326 /* First, make a mask of all stack regs that are clobbered. */
1327 for (i = 0; i < XVECLEN (pat, 0); i++)
1329 rtx t = XVECEXP (pat, 0, i);
1330 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1331 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1334 /* Get the operand values and constraints out of the insn. */
1335 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1336 constraints, operand_mode);
1338 /* For every operand, see what registers are allowed. */
1339 for (i = 0; i < noperands; i++)
1341 const char *p = constraints[i];
1342 /* For every alternative, we compute the class of registers allowed
1343 for reloading in CLS, and merge its contents into the reg set
1345 int cls = (int) NO_REGS;
1351 if (c == '\0' || c == ',' || c == '#')
1353 /* End of one alternative - mark the regs in the current
1354 class, and reset the class. */
1355 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1361 } while (c != '\0' && c != ',');
1369 case '=': case '+': case '*': case '%': case '?': case '!':
1370 case '0': case '1': case '2': case '3': case '4': case 'm':
1371 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1372 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1373 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1378 cls = (int) reg_class_subunion[cls]
1379 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1384 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1388 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1389 cls = (int) reg_class_subunion[cls]
1390 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1392 cls = (int) reg_class_subunion[cls]
1393 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1395 p += CONSTRAINT_LEN (c, p);
1398 /* Those of the registers which are clobbered, but allowed by the
1399 constraints, must be usable as reload registers. So clear them
1400 out of the life information. */
1401 AND_HARD_REG_SET (allowed, clobbered);
1402 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1403 if (TEST_HARD_REG_BIT (allowed, i))
1405 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1406 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1413 /* Copy the global variables n_reloads and rld into the corresponding elts
1416 copy_reloads (struct insn_chain *chain)
1418 chain->n_reloads = n_reloads;
1419 chain->rld = obstack_alloc (&reload_obstack,
1420 n_reloads * sizeof (struct reload));
1421 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1422 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1425 /* Walk the chain of insns, and determine for each whether it needs reloads
1426 and/or eliminations. Build the corresponding insns_need_reload list, and
1427 set something_needs_elimination as appropriate. */
1429 calculate_needs_all_insns (int global)
1431 struct insn_chain **pprev_reload = &insns_need_reload;
1432 struct insn_chain *chain, *next = 0;
1434 something_needs_elimination = 0;
1436 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1437 for (chain = reload_insn_chain; chain != 0; chain = next)
1439 rtx insn = chain->insn;
1443 /* Clear out the shortcuts. */
1444 chain->n_reloads = 0;
1445 chain->need_elim = 0;
1446 chain->need_reload = 0;
1447 chain->need_operand_change = 0;
1449 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1450 include REG_LABEL), we need to see what effects this has on the
1451 known offsets at labels. */
1453 if (LABEL_P (insn) || JUMP_P (insn)
1454 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1455 set_label_offsets (insn, insn, 0);
1459 rtx old_body = PATTERN (insn);
1460 int old_code = INSN_CODE (insn);
1461 rtx old_notes = REG_NOTES (insn);
1462 int did_elimination = 0;
1463 int operands_changed = 0;
1464 rtx set = single_set (insn);
1466 /* Skip insns that only set an equivalence. */
1467 if (set && REG_P (SET_DEST (set))
1468 && reg_renumber[REGNO (SET_DEST (set))] < 0
1469 && reg_equiv_constant[REGNO (SET_DEST (set))])
1472 /* If needed, eliminate any eliminable registers. */
1473 if (num_eliminable || num_eliminable_invariants)
1474 did_elimination = eliminate_regs_in_insn (insn, 0);
1476 /* Analyze the instruction. */
1477 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1478 global, spill_reg_order);
1480 /* If a no-op set needs more than one reload, this is likely
1481 to be something that needs input address reloads. We
1482 can't get rid of this cleanly later, and it is of no use
1483 anyway, so discard it now.
1484 We only do this when expensive_optimizations is enabled,
1485 since this complements reload inheritance / output
1486 reload deletion, and it can make debugging harder. */
1487 if (flag_expensive_optimizations && n_reloads > 1)
1489 rtx set = single_set (insn);
1491 && SET_SRC (set) == SET_DEST (set)
1492 && REG_P (SET_SRC (set))
1493 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1496 /* Delete it from the reload chain. */
1498 chain->prev->next = next;
1500 reload_insn_chain = next;
1502 next->prev = chain->prev;
1503 chain->next = unused_insn_chains;
1504 unused_insn_chains = chain;
1509 update_eliminable_offsets ();
1511 /* Remember for later shortcuts which insns had any reloads or
1512 register eliminations. */
1513 chain->need_elim = did_elimination;
1514 chain->need_reload = n_reloads > 0;
1515 chain->need_operand_change = operands_changed;
1517 /* Discard any register replacements done. */
1518 if (did_elimination)
1520 obstack_free (&reload_obstack, reload_insn_firstobj);
1521 PATTERN (insn) = old_body;
1522 INSN_CODE (insn) = old_code;
1523 REG_NOTES (insn) = old_notes;
1524 something_needs_elimination = 1;
1527 something_needs_operands_changed |= operands_changed;
1531 copy_reloads (chain);
1532 *pprev_reload = chain;
1533 pprev_reload = &chain->next_need_reload;
1540 /* Comparison function for qsort to decide which of two reloads
1541 should be handled first. *P1 and *P2 are the reload numbers. */
1544 reload_reg_class_lower (const void *r1p, const void *r2p)
1546 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1549 /* Consider required reloads before optional ones. */
1550 t = rld[r1].optional - rld[r2].optional;
1554 /* Count all solitary classes before non-solitary ones. */
1555 t = ((reg_class_size[(int) rld[r2].class] == 1)
1556 - (reg_class_size[(int) rld[r1].class] == 1));
1560 /* Aside from solitaires, consider all multi-reg groups first. */
1561 t = rld[r2].nregs - rld[r1].nregs;
1565 /* Consider reloads in order of increasing reg-class number. */
1566 t = (int) rld[r1].class - (int) rld[r2].class;
1570 /* If reloads are equally urgent, sort by reload number,
1571 so that the results of qsort leave nothing to chance. */
1575 /* The cost of spilling each hard reg. */
1576 static int spill_cost[FIRST_PSEUDO_REGISTER];
1578 /* When spilling multiple hard registers, we use SPILL_COST for the first
1579 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1580 only the first hard reg for a multi-reg pseudo. */
1581 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1583 /* Update the spill cost arrays, considering that pseudo REG is live. */
1586 count_pseudo (int reg)
1588 int freq = REG_FREQ (reg);
1589 int r = reg_renumber[reg];
1592 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1593 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1596 SET_REGNO_REG_SET (&pseudos_counted, reg);
1598 gcc_assert (r >= 0);
1600 spill_add_cost[r] += freq;
1602 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1604 spill_cost[r + nregs] += freq;
1607 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1608 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1611 order_regs_for_reload (struct insn_chain *chain)
1614 HARD_REG_SET used_by_pseudos;
1615 HARD_REG_SET used_by_pseudos2;
1616 reg_set_iterator rsi;
1618 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1620 memset (spill_cost, 0, sizeof spill_cost);
1621 memset (spill_add_cost, 0, sizeof spill_add_cost);
1623 /* Count number of uses of each hard reg by pseudo regs allocated to it
1624 and then order them by decreasing use. First exclude hard registers
1625 that are live in or across this insn. */
1627 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1628 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1629 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1630 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1632 /* Now find out which pseudos are allocated to it, and update
1634 CLEAR_REG_SET (&pseudos_counted);
1636 EXECUTE_IF_SET_IN_REG_SET
1637 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1641 EXECUTE_IF_SET_IN_REG_SET
1642 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1646 CLEAR_REG_SET (&pseudos_counted);
1649 /* Vector of reload-numbers showing the order in which the reloads should
1651 static short reload_order[MAX_RELOADS];
1653 /* This is used to keep track of the spill regs used in one insn. */
1654 static HARD_REG_SET used_spill_regs_local;
1656 /* We decided to spill hard register SPILLED, which has a size of
1657 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1658 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1659 update SPILL_COST/SPILL_ADD_COST. */
1662 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1664 int r = reg_renumber[reg];
1665 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1667 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1668 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1671 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1673 spill_add_cost[r] -= REG_FREQ (reg);
1675 spill_cost[r + nregs] -= REG_FREQ (reg);
1678 /* Find reload register to use for reload number ORDER. */
1681 find_reg (struct insn_chain *chain, int order)
1683 int rnum = reload_order[order];
1684 struct reload *rl = rld + rnum;
1685 int best_cost = INT_MAX;
1689 HARD_REG_SET not_usable;
1690 HARD_REG_SET used_by_other_reload;
1691 reg_set_iterator rsi;
1693 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1694 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1695 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1697 CLEAR_HARD_REG_SET (used_by_other_reload);
1698 for (k = 0; k < order; k++)
1700 int other = reload_order[k];
1702 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1703 for (j = 0; j < rld[other].nregs; j++)
1704 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1707 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1709 unsigned int regno = i;
1711 if (! TEST_HARD_REG_BIT (not_usable, regno)
1712 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1713 && HARD_REGNO_MODE_OK (regno, rl->mode))
1715 int this_cost = spill_cost[regno];
1717 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1719 for (j = 1; j < this_nregs; j++)
1721 this_cost += spill_add_cost[regno + j];
1722 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1723 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1728 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1730 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1732 if (this_cost < best_cost
1733 /* Among registers with equal cost, prefer caller-saved ones, or
1734 use REG_ALLOC_ORDER if it is defined. */
1735 || (this_cost == best_cost
1736 #ifdef REG_ALLOC_ORDER
1737 && (inv_reg_alloc_order[regno]
1738 < inv_reg_alloc_order[best_reg])
1740 && call_used_regs[regno]
1741 && ! call_used_regs[best_reg]
1746 best_cost = this_cost;
1754 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1756 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1757 rl->regno = best_reg;
1759 EXECUTE_IF_SET_IN_REG_SET
1760 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1762 count_spilled_pseudo (best_reg, rl->nregs, j);
1765 EXECUTE_IF_SET_IN_REG_SET
1766 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1768 count_spilled_pseudo (best_reg, rl->nregs, j);
1771 for (i = 0; i < rl->nregs; i++)
1773 gcc_assert (spill_cost[best_reg + i] == 0);
1774 gcc_assert (spill_add_cost[best_reg + i] == 0);
1775 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1780 /* Find more reload regs to satisfy the remaining need of an insn, which
1782 Do it by ascending class number, since otherwise a reg
1783 might be spilled for a big class and might fail to count
1784 for a smaller class even though it belongs to that class. */
1787 find_reload_regs (struct insn_chain *chain)
1791 /* In order to be certain of getting the registers we need,
1792 we must sort the reloads into order of increasing register class.
1793 Then our grabbing of reload registers will parallel the process
1794 that provided the reload registers. */
1795 for (i = 0; i < chain->n_reloads; i++)
1797 /* Show whether this reload already has a hard reg. */
1798 if (chain->rld[i].reg_rtx)
1800 int regno = REGNO (chain->rld[i].reg_rtx);
1801 chain->rld[i].regno = regno;
1803 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1806 chain->rld[i].regno = -1;
1807 reload_order[i] = i;
1810 n_reloads = chain->n_reloads;
1811 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1813 CLEAR_HARD_REG_SET (used_spill_regs_local);
1816 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1818 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1820 /* Compute the order of preference for hard registers to spill. */
1822 order_regs_for_reload (chain);
1824 for (i = 0; i < n_reloads; i++)
1826 int r = reload_order[i];
1828 /* Ignore reloads that got marked inoperative. */
1829 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1830 && ! rld[r].optional
1831 && rld[r].regno == -1)
1832 if (! find_reg (chain, i))
1834 spill_failure (chain->insn, rld[r].class);
1840 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1841 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1843 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1847 select_reload_regs (void)
1849 struct insn_chain *chain;
1851 /* Try to satisfy the needs for each insn. */
1852 for (chain = insns_need_reload; chain != 0;
1853 chain = chain->next_need_reload)
1854 find_reload_regs (chain);
1857 /* Delete all insns that were inserted by emit_caller_save_insns during
1860 delete_caller_save_insns (void)
1862 struct insn_chain *c = reload_insn_chain;
1866 while (c != 0 && c->is_caller_save_insn)
1868 struct insn_chain *next = c->next;
1871 if (c == reload_insn_chain)
1872 reload_insn_chain = next;
1876 next->prev = c->prev;
1878 c->prev->next = next;
1879 c->next = unused_insn_chains;
1880 unused_insn_chains = c;
1888 /* Handle the failure to find a register to spill.
1889 INSN should be one of the insns which needed this particular spill reg. */
1892 spill_failure (rtx insn, enum reg_class class)
1894 if (asm_noperands (PATTERN (insn)) >= 0)
1895 error_for_asm (insn, "can't find a register in class %qs while "
1896 "reloading %<asm%>",
1897 reg_class_names[class]);
1900 error ("unable to find a register to spill in class %qs",
1901 reg_class_names[class]);
1902 fatal_insn ("this is the insn:", insn);
1906 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1907 data that is dead in INSN. */
1910 delete_dead_insn (rtx insn)
1912 rtx prev = prev_real_insn (insn);
1915 /* If the previous insn sets a register that dies in our insn, delete it
1917 if (prev && GET_CODE (PATTERN (prev)) == SET
1918 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1919 && reg_mentioned_p (prev_dest, PATTERN (insn))
1920 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1921 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1922 delete_dead_insn (prev);
1924 SET_INSN_DELETED (insn);
1927 /* Modify the home of pseudo-reg I.
1928 The new home is present in reg_renumber[I].
1930 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1931 or it may be -1, meaning there is none or it is not relevant.
1932 This is used so that all pseudos spilled from a given hard reg
1933 can share one stack slot. */
1936 alter_reg (int i, int from_reg)
1938 /* When outputting an inline function, this can happen
1939 for a reg that isn't actually used. */
1940 if (regno_reg_rtx[i] == 0)
1943 /* If the reg got changed to a MEM at rtl-generation time,
1945 if (!REG_P (regno_reg_rtx[i]))
1948 /* Modify the reg-rtx to contain the new hard reg
1949 number or else to contain its pseudo reg number. */
1950 REGNO (regno_reg_rtx[i])
1951 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1953 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1954 allocate a stack slot for it. */
1956 if (reg_renumber[i] < 0
1957 && REG_N_REFS (i) > 0
1958 && reg_equiv_constant[i] == 0
1959 && reg_equiv_memory_loc[i] == 0)
1962 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1963 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1966 /* Each pseudo reg has an inherent size which comes from its own mode,
1967 and a total size which provides room for paradoxical subregs
1968 which refer to the pseudo reg in wider modes.
1970 We can use a slot already allocated if it provides both
1971 enough inherent space and enough total space.
1972 Otherwise, we allocate a new slot, making sure that it has no less
1973 inherent space, and no less total space, then the previous slot. */
1976 /* No known place to spill from => no slot to reuse. */
1977 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1978 inherent_size == total_size ? 0 : -1);
1979 if (BYTES_BIG_ENDIAN)
1980 /* Cancel the big-endian correction done in assign_stack_local.
1981 Get the address of the beginning of the slot.
1982 This is so we can do a big-endian correction unconditionally
1984 adjust = inherent_size - total_size;
1986 /* Nothing can alias this slot except this pseudo. */
1987 set_mem_alias_set (x, new_alias_set ());
1990 /* Reuse a stack slot if possible. */
1991 else if (spill_stack_slot[from_reg] != 0
1992 && spill_stack_slot_width[from_reg] >= total_size
1993 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1995 x = spill_stack_slot[from_reg];
1997 /* Allocate a bigger slot. */
2000 /* Compute maximum size needed, both for inherent size
2001 and for total size. */
2002 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2005 if (spill_stack_slot[from_reg])
2007 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2009 mode = GET_MODE (spill_stack_slot[from_reg]);
2010 if (spill_stack_slot_width[from_reg] > total_size)
2011 total_size = spill_stack_slot_width[from_reg];
2014 /* Make a slot with that size. */
2015 x = assign_stack_local (mode, total_size,
2016 inherent_size == total_size ? 0 : -1);
2019 /* All pseudos mapped to this slot can alias each other. */
2020 if (spill_stack_slot[from_reg])
2021 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2023 set_mem_alias_set (x, new_alias_set ());
2025 if (BYTES_BIG_ENDIAN)
2027 /* Cancel the big-endian correction done in assign_stack_local.
2028 Get the address of the beginning of the slot.
2029 This is so we can do a big-endian correction unconditionally
2031 adjust = GET_MODE_SIZE (mode) - total_size;
2034 = adjust_address_nv (x, mode_for_size (total_size
2040 spill_stack_slot[from_reg] = stack_slot;
2041 spill_stack_slot_width[from_reg] = total_size;
2044 /* On a big endian machine, the "address" of the slot
2045 is the address of the low part that fits its inherent mode. */
2046 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2047 adjust += (total_size - inherent_size);
2049 /* If we have any adjustment to make, or if the stack slot is the
2050 wrong mode, make a new stack slot. */
2051 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2053 /* If we have a decl for the original register, set it for the
2054 memory. If this is a shared MEM, make a copy. */
2055 if (REG_EXPR (regno_reg_rtx[i])
2056 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2058 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2060 /* We can do this only for the DECLs home pseudo, not for
2061 any copies of it, since otherwise when the stack slot
2062 is reused, nonoverlapping_memrefs_p might think they
2064 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2066 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2069 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2073 /* Save the stack slot for later. */
2074 reg_equiv_memory_loc[i] = x;
2078 /* Mark the slots in regs_ever_live for the hard regs
2079 used by pseudo-reg number REGNO. */
2082 mark_home_live (int regno)
2086 i = reg_renumber[regno];
2089 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2091 regs_ever_live[i++] = 1;
2094 /* This function handles the tracking of elimination offsets around branches.
2096 X is a piece of RTL being scanned.
2098 INSN is the insn that it came from, if any.
2100 INITIAL_P is nonzero if we are to set the offset to be the initial
2101 offset and zero if we are setting the offset of the label to be the
2105 set_label_offsets (rtx x, rtx insn, int initial_p)
2107 enum rtx_code code = GET_CODE (x);
2110 struct elim_table *p;
2115 if (LABEL_REF_NONLOCAL_P (x))
2120 /* ... fall through ... */
2123 /* If we know nothing about this label, set the desired offsets. Note
2124 that this sets the offset at a label to be the offset before a label
2125 if we don't know anything about the label. This is not correct for
2126 the label after a BARRIER, but is the best guess we can make. If
2127 we guessed wrong, we will suppress an elimination that might have
2128 been possible had we been able to guess correctly. */
2130 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2132 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2133 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2134 = (initial_p ? reg_eliminate[i].initial_offset
2135 : reg_eliminate[i].offset);
2136 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2139 /* Otherwise, if this is the definition of a label and it is
2140 preceded by a BARRIER, set our offsets to the known offset of
2144 && (tem = prev_nonnote_insn (insn)) != 0
2146 set_offsets_for_label (insn);
2148 /* If neither of the above cases is true, compare each offset
2149 with those previously recorded and suppress any eliminations
2150 where the offsets disagree. */
2152 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2153 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2154 != (initial_p ? reg_eliminate[i].initial_offset
2155 : reg_eliminate[i].offset))
2156 reg_eliminate[i].can_eliminate = 0;
2161 set_label_offsets (PATTERN (insn), insn, initial_p);
2163 /* ... fall through ... */
2167 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2168 and hence must have all eliminations at their initial offsets. */
2169 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2170 if (REG_NOTE_KIND (tem) == REG_LABEL)
2171 set_label_offsets (XEXP (tem, 0), insn, 1);
2177 /* Each of the labels in the parallel or address vector must be
2178 at their initial offsets. We want the first field for PARALLEL
2179 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2181 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2182 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2187 /* We only care about setting PC. If the source is not RETURN,
2188 IF_THEN_ELSE, or a label, disable any eliminations not at
2189 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2190 isn't one of those possibilities. For branches to a label,
2191 call ourselves recursively.
2193 Note that this can disable elimination unnecessarily when we have
2194 a non-local goto since it will look like a non-constant jump to
2195 someplace in the current function. This isn't a significant
2196 problem since such jumps will normally be when all elimination
2197 pairs are back to their initial offsets. */
2199 if (SET_DEST (x) != pc_rtx)
2202 switch (GET_CODE (SET_SRC (x)))
2209 set_label_offsets (SET_SRC (x), insn, initial_p);
2213 tem = XEXP (SET_SRC (x), 1);
2214 if (GET_CODE (tem) == LABEL_REF)
2215 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2216 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2219 tem = XEXP (SET_SRC (x), 2);
2220 if (GET_CODE (tem) == LABEL_REF)
2221 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2222 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2230 /* If we reach here, all eliminations must be at their initial
2231 offset because we are doing a jump to a variable address. */
2232 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2233 if (p->offset != p->initial_offset)
2234 p->can_eliminate = 0;
2242 /* Scan X and replace any eliminable registers (such as fp) with a
2243 replacement (such as sp), plus an offset.
2245 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2246 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2247 MEM, we are allowed to replace a sum of a register and the constant zero
2248 with the register, which we cannot do outside a MEM. In addition, we need
2249 to record the fact that a register is referenced outside a MEM.
2251 If INSN is an insn, it is the insn containing X. If we replace a REG
2252 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2253 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2254 the REG is being modified.
2256 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2257 That's used when we eliminate in expressions stored in notes.
2258 This means, do not set ref_outside_mem even if the reference
2261 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2262 replacements done assuming all offsets are at their initial values. If
2263 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2264 encounter, return the actual location so that find_reloads will do
2265 the proper thing. */
2268 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2270 enum rtx_code code = GET_CODE (x);
2271 struct elim_table *ep;
2278 if (! current_function_decl)
2300 /* First handle the case where we encounter a bare register that
2301 is eliminable. Replace it with a PLUS. */
2302 if (regno < FIRST_PSEUDO_REGISTER)
2304 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2306 if (ep->from_rtx == x && ep->can_eliminate)
2307 return plus_constant (ep->to_rtx, ep->previous_offset);
2310 else if (reg_renumber && reg_renumber[regno] < 0
2311 && reg_equiv_constant && reg_equiv_constant[regno]
2312 && ! CONSTANT_P (reg_equiv_constant[regno]))
2313 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2317 /* You might think handling MINUS in a manner similar to PLUS is a
2318 good idea. It is not. It has been tried multiple times and every
2319 time the change has had to have been reverted.
2321 Other parts of reload know a PLUS is special (gen_reload for example)
2322 and require special code to handle code a reloaded PLUS operand.
2324 Also consider backends where the flags register is clobbered by a
2325 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2326 lea instruction comes to mind). If we try to reload a MINUS, we
2327 may kill the flags register that was holding a useful value.
2329 So, please before trying to handle MINUS, consider reload as a
2330 whole instead of this little section as well as the backend issues. */
2332 /* If this is the sum of an eliminable register and a constant, rework
2334 if (REG_P (XEXP (x, 0))
2335 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2336 && CONSTANT_P (XEXP (x, 1)))
2338 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2340 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2342 /* The only time we want to replace a PLUS with a REG (this
2343 occurs when the constant operand of the PLUS is the negative
2344 of the offset) is when we are inside a MEM. We won't want
2345 to do so at other times because that would change the
2346 structure of the insn in a way that reload can't handle.
2347 We special-case the commonest situation in
2348 eliminate_regs_in_insn, so just replace a PLUS with a
2349 PLUS here, unless inside a MEM. */
2350 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2351 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2354 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2355 plus_constant (XEXP (x, 1),
2356 ep->previous_offset));
2359 /* If the register is not eliminable, we are done since the other
2360 operand is a constant. */
2364 /* If this is part of an address, we want to bring any constant to the
2365 outermost PLUS. We will do this by doing register replacement in
2366 our operands and seeing if a constant shows up in one of them.
2368 Note that there is no risk of modifying the structure of the insn,
2369 since we only get called for its operands, thus we are either
2370 modifying the address inside a MEM, or something like an address
2371 operand of a load-address insn. */
2374 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2375 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2377 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2379 /* If one side is a PLUS and the other side is a pseudo that
2380 didn't get a hard register but has a reg_equiv_constant,
2381 we must replace the constant here since it may no longer
2382 be in the position of any operand. */
2383 if (GET_CODE (new0) == PLUS && REG_P (new1)
2384 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2385 && reg_renumber[REGNO (new1)] < 0
2386 && reg_equiv_constant != 0
2387 && reg_equiv_constant[REGNO (new1)] != 0)
2388 new1 = reg_equiv_constant[REGNO (new1)];
2389 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2390 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2391 && reg_renumber[REGNO (new0)] < 0
2392 && reg_equiv_constant[REGNO (new0)] != 0)
2393 new0 = reg_equiv_constant[REGNO (new0)];
2395 new = form_sum (new0, new1);
2397 /* As above, if we are not inside a MEM we do not want to
2398 turn a PLUS into something else. We might try to do so here
2399 for an addition of 0 if we aren't optimizing. */
2400 if (! mem_mode && GET_CODE (new) != PLUS)
2401 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2409 /* If this is the product of an eliminable register and a
2410 constant, apply the distribute law and move the constant out
2411 so that we have (plus (mult ..) ..). This is needed in order
2412 to keep load-address insns valid. This case is pathological.
2413 We ignore the possibility of overflow here. */
2414 if (REG_P (XEXP (x, 0))
2415 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2416 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2417 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2419 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2422 /* Refs inside notes don't count for this purpose. */
2423 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2424 || GET_CODE (insn) == INSN_LIST)))
2425 ep->ref_outside_mem = 1;
2428 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2429 ep->previous_offset * INTVAL (XEXP (x, 1)));
2432 /* ... fall through ... */
2436 /* See comments before PLUS about handling MINUS. */
2438 case DIV: case UDIV:
2439 case MOD: case UMOD:
2440 case AND: case IOR: case XOR:
2441 case ROTATERT: case ROTATE:
2442 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2444 case GE: case GT: case GEU: case GTU:
2445 case LE: case LT: case LEU: case LTU:
2447 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2449 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2451 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2452 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2457 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2460 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2461 if (new != XEXP (x, 0))
2463 /* If this is a REG_DEAD note, it is not valid anymore.
2464 Using the eliminated version could result in creating a
2465 REG_DEAD note for the stack or frame pointer. */
2466 if (GET_MODE (x) == REG_DEAD)
2468 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2471 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2475 /* ... fall through ... */
2478 /* Now do eliminations in the rest of the chain. If this was
2479 an EXPR_LIST, this might result in allocating more memory than is
2480 strictly needed, but it simplifies the code. */
2483 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2484 if (new != XEXP (x, 1))
2486 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2494 case STRICT_LOW_PART:
2496 case SIGN_EXTEND: case ZERO_EXTEND:
2497 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2498 case FLOAT: case FIX:
2499 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2507 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2508 if (new != XEXP (x, 0))
2509 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2513 /* Similar to above processing, but preserve SUBREG_BYTE.
2514 Convert (subreg (mem)) to (mem) if not paradoxical.
2515 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2516 pseudo didn't get a hard reg, we must replace this with the
2517 eliminated version of the memory location because push_reload
2518 may do the replacement in certain circumstances. */
2519 if (REG_P (SUBREG_REG (x))
2520 && (GET_MODE_SIZE (GET_MODE (x))
2521 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2522 && reg_equiv_memory_loc != 0
2523 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2525 new = SUBREG_REG (x);
2528 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2530 if (new != SUBREG_REG (x))
2532 int x_size = GET_MODE_SIZE (GET_MODE (x));
2533 int new_size = GET_MODE_SIZE (GET_MODE (new));
2536 && ((x_size < new_size
2537 #ifdef WORD_REGISTER_OPERATIONS
2538 /* On these machines, combine can create rtl of the form
2539 (set (subreg:m1 (reg:m2 R) 0) ...)
2540 where m1 < m2, and expects something interesting to
2541 happen to the entire word. Moreover, it will use the
2542 (reg:m2 R) later, expecting all bits to be preserved.
2543 So if the number of words is the same, preserve the
2544 subreg so that push_reload can see it. */
2545 && ! ((x_size - 1) / UNITS_PER_WORD
2546 == (new_size -1 ) / UNITS_PER_WORD)
2549 || x_size == new_size)
2551 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2553 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2559 /* Our only special processing is to pass the mode of the MEM to our
2560 recursive call and copy the flags. While we are here, handle this
2561 case more efficiently. */
2563 replace_equiv_address_nv (x,
2564 eliminate_regs (XEXP (x, 0),
2565 GET_MODE (x), insn));
2568 /* Handle insn_list USE that a call to a pure function may generate. */
2569 new = eliminate_regs (XEXP (x, 0), 0, insn);
2570 if (new != XEXP (x, 0))
2571 return gen_rtx_USE (GET_MODE (x), new);
2583 /* Process each of our operands recursively. If any have changed, make a
2585 fmt = GET_RTX_FORMAT (code);
2586 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2590 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2591 if (new != XEXP (x, i) && ! copied)
2593 rtx new_x = rtx_alloc (code);
2594 memcpy (new_x, x, RTX_SIZE (code));
2600 else if (*fmt == 'E')
2603 for (j = 0; j < XVECLEN (x, i); j++)
2605 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2606 if (new != XVECEXP (x, i, j) && ! copied_vec)
2608 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2612 rtx new_x = rtx_alloc (code);
2613 memcpy (new_x, x, RTX_SIZE (code));
2617 XVEC (x, i) = new_v;
2620 XVECEXP (x, i, j) = new;
2628 /* Scan rtx X for modifications of elimination target registers. Update
2629 the table of eliminables to reflect the changed state. MEM_MODE is
2630 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2633 elimination_effects (rtx x, enum machine_mode mem_mode)
2635 enum rtx_code code = GET_CODE (x);
2636 struct elim_table *ep;
2660 /* First handle the case where we encounter a bare register that
2661 is eliminable. Replace it with a PLUS. */
2662 if (regno < FIRST_PSEUDO_REGISTER)
2664 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2666 if (ep->from_rtx == x && ep->can_eliminate)
2669 ep->ref_outside_mem = 1;
2674 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2675 && reg_equiv_constant[regno]
2676 && ! function_invariant_p (reg_equiv_constant[regno]))
2677 elimination_effects (reg_equiv_constant[regno], mem_mode);
2686 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2687 if (ep->to_rtx == XEXP (x, 0))
2689 int size = GET_MODE_SIZE (mem_mode);
2691 /* If more bytes than MEM_MODE are pushed, account for them. */
2692 #ifdef PUSH_ROUNDING
2693 if (ep->to_rtx == stack_pointer_rtx)
2694 size = PUSH_ROUNDING (size);
2696 if (code == PRE_DEC || code == POST_DEC)
2698 else if (code == PRE_INC || code == POST_INC)
2700 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2701 && GET_CODE (XEXP (x, 1)) == PLUS
2702 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2703 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2704 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2707 /* These two aren't unary operators. */
2708 if (code == POST_MODIFY || code == PRE_MODIFY)
2711 /* Fall through to generic unary operation case. */
2712 case STRICT_LOW_PART:
2714 case SIGN_EXTEND: case ZERO_EXTEND:
2715 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2716 case FLOAT: case FIX:
2717 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2725 elimination_effects (XEXP (x, 0), mem_mode);
2729 if (REG_P (SUBREG_REG (x))
2730 && (GET_MODE_SIZE (GET_MODE (x))
2731 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2732 && reg_equiv_memory_loc != 0
2733 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2736 elimination_effects (SUBREG_REG (x), mem_mode);
2740 /* If using a register that is the source of an eliminate we still
2741 think can be performed, note it cannot be performed since we don't
2742 know how this register is used. */
2743 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2744 if (ep->from_rtx == XEXP (x, 0))
2745 ep->can_eliminate = 0;
2747 elimination_effects (XEXP (x, 0), mem_mode);
2751 /* If clobbering a register that is the replacement register for an
2752 elimination we still think can be performed, note that it cannot
2753 be performed. Otherwise, we need not be concerned about it. */
2754 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2755 if (ep->to_rtx == XEXP (x, 0))
2756 ep->can_eliminate = 0;
2758 elimination_effects (XEXP (x, 0), mem_mode);
2762 /* Check for setting a register that we know about. */
2763 if (REG_P (SET_DEST (x)))
2765 /* See if this is setting the replacement register for an
2768 If DEST is the hard frame pointer, we do nothing because we
2769 assume that all assignments to the frame pointer are for
2770 non-local gotos and are being done at a time when they are valid
2771 and do not disturb anything else. Some machines want to
2772 eliminate a fake argument pointer (or even a fake frame pointer)
2773 with either the real frame or the stack pointer. Assignments to
2774 the hard frame pointer must not prevent this elimination. */
2776 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2778 if (ep->to_rtx == SET_DEST (x)
2779 && SET_DEST (x) != hard_frame_pointer_rtx)
2781 /* If it is being incremented, adjust the offset. Otherwise,
2782 this elimination can't be done. */
2783 rtx src = SET_SRC (x);
2785 if (GET_CODE (src) == PLUS
2786 && XEXP (src, 0) == SET_DEST (x)
2787 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2788 ep->offset -= INTVAL (XEXP (src, 1));
2790 ep->can_eliminate = 0;
2794 elimination_effects (SET_DEST (x), 0);
2795 elimination_effects (SET_SRC (x), 0);
2799 /* Our only special processing is to pass the mode of the MEM to our
2801 elimination_effects (XEXP (x, 0), GET_MODE (x));
2808 fmt = GET_RTX_FORMAT (code);
2809 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2812 elimination_effects (XEXP (x, i), mem_mode);
2813 else if (*fmt == 'E')
2814 for (j = 0; j < XVECLEN (x, i); j++)
2815 elimination_effects (XVECEXP (x, i, j), mem_mode);
2819 /* Descend through rtx X and verify that no references to eliminable registers
2820 remain. If any do remain, mark the involved register as not
2824 check_eliminable_occurrences (rtx x)
2833 code = GET_CODE (x);
2835 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2837 struct elim_table *ep;
2839 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2840 if (ep->from_rtx == x)
2841 ep->can_eliminate = 0;
2845 fmt = GET_RTX_FORMAT (code);
2846 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2849 check_eliminable_occurrences (XEXP (x, i));
2850 else if (*fmt == 'E')
2853 for (j = 0; j < XVECLEN (x, i); j++)
2854 check_eliminable_occurrences (XVECEXP (x, i, j));
2859 /* Scan INSN and eliminate all eliminable registers in it.
2861 If REPLACE is nonzero, do the replacement destructively. Also
2862 delete the insn as dead it if it is setting an eliminable register.
2864 If REPLACE is zero, do all our allocations in reload_obstack.
2866 If no eliminations were done and this insn doesn't require any elimination
2867 processing (these are not identical conditions: it might be updating sp,
2868 but not referencing fp; this needs to be seen during reload_as_needed so
2869 that the offset between fp and sp can be taken into consideration), zero
2870 is returned. Otherwise, 1 is returned. */
2873 eliminate_regs_in_insn (rtx insn, int replace)
2875 int icode = recog_memoized (insn);
2876 rtx old_body = PATTERN (insn);
2877 int insn_is_asm = asm_noperands (old_body) >= 0;
2878 rtx old_set = single_set (insn);
2882 rtx substed_operand[MAX_RECOG_OPERANDS];
2883 rtx orig_operand[MAX_RECOG_OPERANDS];
2884 struct elim_table *ep;
2887 if (! insn_is_asm && icode < 0)
2889 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2890 || GET_CODE (PATTERN (insn)) == CLOBBER
2891 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2892 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2893 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2897 if (old_set != 0 && REG_P (SET_DEST (old_set))
2898 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2900 /* Check for setting an eliminable register. */
2901 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2902 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2904 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2905 /* If this is setting the frame pointer register to the
2906 hardware frame pointer register and this is an elimination
2907 that will be done (tested above), this insn is really
2908 adjusting the frame pointer downward to compensate for
2909 the adjustment done before a nonlocal goto. */
2910 if (ep->from == FRAME_POINTER_REGNUM
2911 && ep->to == HARD_FRAME_POINTER_REGNUM)
2913 rtx base = SET_SRC (old_set);
2914 rtx base_insn = insn;
2915 HOST_WIDE_INT offset = 0;
2917 while (base != ep->to_rtx)
2919 rtx prev_insn, prev_set;
2921 if (GET_CODE (base) == PLUS
2922 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2924 offset += INTVAL (XEXP (base, 1));
2925 base = XEXP (base, 0);
2927 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2928 && (prev_set = single_set (prev_insn)) != 0
2929 && rtx_equal_p (SET_DEST (prev_set), base))
2931 base = SET_SRC (prev_set);
2932 base_insn = prev_insn;
2938 if (base == ep->to_rtx)
2941 = plus_constant (ep->to_rtx, offset - ep->offset);
2943 new_body = old_body;
2946 new_body = copy_insn (old_body);
2947 if (REG_NOTES (insn))
2948 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2950 PATTERN (insn) = new_body;
2951 old_set = single_set (insn);
2953 /* First see if this insn remains valid when we
2954 make the change. If not, keep the INSN_CODE
2955 the same and let reload fit it up. */
2956 validate_change (insn, &SET_SRC (old_set), src, 1);
2957 validate_change (insn, &SET_DEST (old_set),
2959 if (! apply_change_group ())
2961 SET_SRC (old_set) = src;
2962 SET_DEST (old_set) = ep->to_rtx;
2971 /* In this case this insn isn't serving a useful purpose. We
2972 will delete it in reload_as_needed once we know that this
2973 elimination is, in fact, being done.
2975 If REPLACE isn't set, we can't delete this insn, but needn't
2976 process it since it won't be used unless something changes. */
2979 delete_dead_insn (insn);
2987 /* We allow one special case which happens to work on all machines we
2988 currently support: a single set with the source or a REG_EQUAL
2989 note being a PLUS of an eliminable register and a constant. */
2991 if (old_set && REG_P (SET_DEST (old_set)))
2993 /* First see if the source is of the form (plus (reg) CST). */
2994 if (GET_CODE (SET_SRC (old_set)) == PLUS
2995 && REG_P (XEXP (SET_SRC (old_set), 0))
2996 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2997 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2998 plus_src = SET_SRC (old_set);
2999 else if (REG_P (SET_SRC (old_set)))
3001 /* Otherwise, see if we have a REG_EQUAL note of the form
3002 (plus (reg) CST). */
3004 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3006 if (REG_NOTE_KIND (links) == REG_EQUAL
3007 && GET_CODE (XEXP (links, 0)) == PLUS
3008 && REG_P (XEXP (XEXP (links, 0), 0))
3009 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
3010 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
3012 plus_src = XEXP (links, 0);
3020 rtx reg = XEXP (plus_src, 0);
3021 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3023 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3024 if (ep->from_rtx == reg && ep->can_eliminate)
3026 offset += ep->offset;
3031 /* We assume here that if we need a PARALLEL with
3032 CLOBBERs for this assignment, we can do with the
3033 MATCH_SCRATCHes that add_clobbers allocates.
3034 There's not much we can do if that doesn't work. */
3035 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3039 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3042 rtvec vec = rtvec_alloc (num_clobbers + 1);
3044 vec->elem[0] = PATTERN (insn);
3045 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3046 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3048 gcc_assert (INSN_CODE (insn) >= 0);
3050 /* If we have a nonzero offset, and the source is already
3051 a simple REG, the following transformation would
3052 increase the cost of the insn by replacing a simple REG
3053 with (plus (reg sp) CST). So try only when plus_src
3054 comes from old_set proper, not REG_NOTES. */
3055 else if (SET_SRC (old_set) == plus_src)
3057 new_body = old_body;
3060 new_body = copy_insn (old_body);
3061 if (REG_NOTES (insn))
3062 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3064 PATTERN (insn) = new_body;
3065 old_set = single_set (insn);
3067 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3068 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3074 /* This can't have an effect on elimination offsets, so skip right
3080 /* Determine the effects of this insn on elimination offsets. */
3081 elimination_effects (old_body, 0);
3083 /* Eliminate all eliminable registers occurring in operands that
3084 can be handled by reload. */
3085 extract_insn (insn);
3086 for (i = 0; i < recog_data.n_operands; i++)
3088 orig_operand[i] = recog_data.operand[i];
3089 substed_operand[i] = recog_data.operand[i];
3091 /* For an asm statement, every operand is eliminable. */
3092 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3094 /* Check for setting a register that we know about. */
3095 if (recog_data.operand_type[i] != OP_IN
3096 && REG_P (orig_operand[i]))
3098 /* If we are assigning to a register that can be eliminated, it
3099 must be as part of a PARALLEL, since the code above handles
3100 single SETs. We must indicate that we can no longer
3101 eliminate this reg. */
3102 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3104 if (ep->from_rtx == orig_operand[i])
3105 ep->can_eliminate = 0;
3108 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3109 replace ? insn : NULL_RTX);
3110 if (substed_operand[i] != orig_operand[i])
3112 /* Terminate the search in check_eliminable_occurrences at
3114 *recog_data.operand_loc[i] = 0;
3116 /* If an output operand changed from a REG to a MEM and INSN is an
3117 insn, write a CLOBBER insn. */
3118 if (recog_data.operand_type[i] != OP_IN
3119 && REG_P (orig_operand[i])
3120 && MEM_P (substed_operand[i])
3122 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3127 for (i = 0; i < recog_data.n_dups; i++)
3128 *recog_data.dup_loc[i]
3129 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3131 /* If any eliminable remain, they aren't eliminable anymore. */
3132 check_eliminable_occurrences (old_body);
3134 /* Substitute the operands; the new values are in the substed_operand
3136 for (i = 0; i < recog_data.n_operands; i++)
3137 *recog_data.operand_loc[i] = substed_operand[i];
3138 for (i = 0; i < recog_data.n_dups; i++)
3139 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3141 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3142 re-recognize the insn. We do this in case we had a simple addition
3143 but now can do this as a load-address. This saves an insn in this
3145 If re-recognition fails, the old insn code number will still be used,
3146 and some register operands may have changed into PLUS expressions.
3147 These will be handled by find_reloads by loading them into a register
3152 /* If we aren't replacing things permanently and we changed something,
3153 make another copy to ensure that all the RTL is new. Otherwise
3154 things can go wrong if find_reload swaps commutative operands
3155 and one is inside RTL that has been copied while the other is not. */
3156 new_body = old_body;
3159 new_body = copy_insn (old_body);
3160 if (REG_NOTES (insn))
3161 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3163 PATTERN (insn) = new_body;
3165 /* If we had a move insn but now we don't, rerecognize it. This will
3166 cause spurious re-recognition if the old move had a PARALLEL since
3167 the new one still will, but we can't call single_set without
3168 having put NEW_BODY into the insn and the re-recognition won't
3169 hurt in this rare case. */
3170 /* ??? Why this huge if statement - why don't we just rerecognize the
3174 && ((REG_P (SET_SRC (old_set))
3175 && (GET_CODE (new_body) != SET
3176 || !REG_P (SET_SRC (new_body))))
3177 /* If this was a load from or store to memory, compare
3178 the MEM in recog_data.operand to the one in the insn.
3179 If they are not equal, then rerecognize the insn. */
3181 && ((MEM_P (SET_SRC (old_set))
3182 && SET_SRC (old_set) != recog_data.operand[1])
3183 || (MEM_P (SET_DEST (old_set))
3184 && SET_DEST (old_set) != recog_data.operand[0])))
3185 /* If this was an add insn before, rerecognize. */
3186 || GET_CODE (SET_SRC (old_set)) == PLUS))
3188 int new_icode = recog (PATTERN (insn), insn, 0);
3190 INSN_CODE (insn) = icode;
3194 /* Restore the old body. If there were any changes to it, we made a copy
3195 of it while the changes were still in place, so we'll correctly return
3196 a modified insn below. */
3199 /* Restore the old body. */
3200 for (i = 0; i < recog_data.n_operands; i++)
3201 *recog_data.operand_loc[i] = orig_operand[i];
3202 for (i = 0; i < recog_data.n_dups; i++)
3203 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3206 /* Update all elimination pairs to reflect the status after the current
3207 insn. The changes we make were determined by the earlier call to
3208 elimination_effects.
3210 We also detect cases where register elimination cannot be done,
3211 namely, if a register would be both changed and referenced outside a MEM
3212 in the resulting insn since such an insn is often undefined and, even if
3213 not, we cannot know what meaning will be given to it. Note that it is
3214 valid to have a register used in an address in an insn that changes it
3215 (presumably with a pre- or post-increment or decrement).
3217 If anything changes, return nonzero. */
3219 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3221 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3222 ep->can_eliminate = 0;
3224 ep->ref_outside_mem = 0;
3226 if (ep->previous_offset != ep->offset)
3231 /* If we changed something, perform elimination in REG_NOTES. This is
3232 needed even when REPLACE is zero because a REG_DEAD note might refer
3233 to a register that we eliminate and could cause a different number
3234 of spill registers to be needed in the final reload pass than in
3236 if (val && REG_NOTES (insn) != 0)
3237 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3242 /* Loop through all elimination pairs.
3243 Recalculate the number not at initial offset.
3245 Compute the maximum offset (minimum offset if the stack does not
3246 grow downward) for each elimination pair. */
3249 update_eliminable_offsets (void)
3251 struct elim_table *ep;
3253 num_not_at_initial_offset = 0;
3254 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3256 ep->previous_offset = ep->offset;
3257 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3258 num_not_at_initial_offset++;
3262 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3263 replacement we currently believe is valid, mark it as not eliminable if X
3264 modifies DEST in any way other than by adding a constant integer to it.
3266 If DEST is the frame pointer, we do nothing because we assume that
3267 all assignments to the hard frame pointer are nonlocal gotos and are being
3268 done at a time when they are valid and do not disturb anything else.
3269 Some machines want to eliminate a fake argument pointer with either the
3270 frame or stack pointer. Assignments to the hard frame pointer must not
3271 prevent this elimination.
3273 Called via note_stores from reload before starting its passes to scan
3274 the insns of the function. */
3277 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3281 /* A SUBREG of a hard register here is just changing its mode. We should
3282 not see a SUBREG of an eliminable hard register, but check just in
3284 if (GET_CODE (dest) == SUBREG)
3285 dest = SUBREG_REG (dest);
3287 if (dest == hard_frame_pointer_rtx)
3290 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3291 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3292 && (GET_CODE (x) != SET
3293 || GET_CODE (SET_SRC (x)) != PLUS
3294 || XEXP (SET_SRC (x), 0) != dest
3295 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3297 reg_eliminate[i].can_eliminate_previous
3298 = reg_eliminate[i].can_eliminate = 0;
3303 /* Verify that the initial elimination offsets did not change since the
3304 last call to set_initial_elim_offsets. This is used to catch cases
3305 where something illegal happened during reload_as_needed that could
3306 cause incorrect code to be generated if we did not check for it. */
3309 verify_initial_elim_offsets (void)
3313 if (!num_eliminable)
3316 #ifdef ELIMINABLE_REGS
3318 struct elim_table *ep;
3320 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3322 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3323 if (t != ep->initial_offset)
3328 INITIAL_FRAME_POINTER_OFFSET (t);
3329 if (t != reg_eliminate[0].initial_offset)
3336 /* Reset all offsets on eliminable registers to their initial values. */
3339 set_initial_elim_offsets (void)
3341 struct elim_table *ep = reg_eliminate;
3343 #ifdef ELIMINABLE_REGS
3344 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3346 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3347 ep->previous_offset = ep->offset = ep->initial_offset;
3350 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3351 ep->previous_offset = ep->offset = ep->initial_offset;
3354 num_not_at_initial_offset = 0;
3357 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3360 set_initial_eh_label_offset (rtx label)
3362 set_label_offsets (label, NULL_RTX, 1);
3365 /* Initialize the known label offsets.
3366 Set a known offset for each forced label to be at the initial offset
3367 of each elimination. We do this because we assume that all
3368 computed jumps occur from a location where each elimination is
3369 at its initial offset.
3370 For all other labels, show that we don't know the offsets. */
3373 set_initial_label_offsets (void)
3376 memset (offsets_known_at, 0, num_labels);
3378 for (x = forced_labels; x; x = XEXP (x, 1))
3380 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3382 for_each_eh_label (set_initial_eh_label_offset);
3385 /* Set all elimination offsets to the known values for the code label given
3389 set_offsets_for_label (rtx insn)
3392 int label_nr = CODE_LABEL_NUMBER (insn);
3393 struct elim_table *ep;
3395 num_not_at_initial_offset = 0;
3396 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3398 ep->offset = ep->previous_offset
3399 = offsets_at[label_nr - first_label_num][i];
3400 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3401 num_not_at_initial_offset++;
3405 /* See if anything that happened changes which eliminations are valid.
3406 For example, on the SPARC, whether or not the frame pointer can
3407 be eliminated can depend on what registers have been used. We need
3408 not check some conditions again (such as flag_omit_frame_pointer)
3409 since they can't have changed. */
3412 update_eliminables (HARD_REG_SET *pset)
3414 int previous_frame_pointer_needed = frame_pointer_needed;
3415 struct elim_table *ep;
3417 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3418 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3419 #ifdef ELIMINABLE_REGS
3420 || ! CAN_ELIMINATE (ep->from, ep->to)
3423 ep->can_eliminate = 0;
3425 /* Look for the case where we have discovered that we can't replace
3426 register A with register B and that means that we will now be
3427 trying to replace register A with register C. This means we can
3428 no longer replace register C with register B and we need to disable
3429 such an elimination, if it exists. This occurs often with A == ap,
3430 B == sp, and C == fp. */
3432 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3434 struct elim_table *op;
3437 if (! ep->can_eliminate && ep->can_eliminate_previous)
3439 /* Find the current elimination for ep->from, if there is a
3441 for (op = reg_eliminate;
3442 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3443 if (op->from == ep->from && op->can_eliminate)
3449 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3451 for (op = reg_eliminate;
3452 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3453 if (op->from == new_to && op->to == ep->to)
3454 op->can_eliminate = 0;
3458 /* See if any registers that we thought we could eliminate the previous
3459 time are no longer eliminable. If so, something has changed and we
3460 must spill the register. Also, recompute the number of eliminable
3461 registers and see if the frame pointer is needed; it is if there is
3462 no elimination of the frame pointer that we can perform. */
3464 frame_pointer_needed = 1;
3465 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3467 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3468 && ep->to != HARD_FRAME_POINTER_REGNUM)
3469 frame_pointer_needed = 0;
3471 if (! ep->can_eliminate && ep->can_eliminate_previous)
3473 ep->can_eliminate_previous = 0;
3474 SET_HARD_REG_BIT (*pset, ep->from);
3479 /* If we didn't need a frame pointer last time, but we do now, spill
3480 the hard frame pointer. */
3481 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3482 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3485 /* Initialize the table of registers to eliminate. */
3488 init_elim_table (void)
3490 struct elim_table *ep;
3491 #ifdef ELIMINABLE_REGS
3492 const struct elim_table_1 *ep1;
3496 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3498 /* Does this function require a frame pointer? */
3500 frame_pointer_needed = (! flag_omit_frame_pointer
3501 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3502 and restore sp for alloca. So we can't eliminate
3503 the frame pointer in that case. At some point,
3504 we should improve this by emitting the
3505 sp-adjusting insns for this case. */
3506 || (current_function_calls_alloca
3507 && EXIT_IGNORE_STACK)
3508 || FRAME_POINTER_REQUIRED);
3512 #ifdef ELIMINABLE_REGS
3513 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3514 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3516 ep->from = ep1->from;
3518 ep->can_eliminate = ep->can_eliminate_previous
3519 = (CAN_ELIMINATE (ep->from, ep->to)
3520 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3523 reg_eliminate[0].from = reg_eliminate_1[0].from;
3524 reg_eliminate[0].to = reg_eliminate_1[0].to;
3525 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3526 = ! frame_pointer_needed;
3529 /* Count the number of eliminable registers and build the FROM and TO
3530 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3531 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3532 We depend on this. */
3533 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3535 num_eliminable += ep->can_eliminate;
3536 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3537 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3541 /* Kick all pseudos out of hard register REGNO.
3543 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3544 because we found we can't eliminate some register. In the case, no pseudos
3545 are allowed to be in the register, even if they are only in a block that
3546 doesn't require spill registers, unlike the case when we are spilling this
3547 hard reg to produce another spill register.
3549 Return nonzero if any pseudos needed to be kicked out. */
3552 spill_hard_reg (unsigned int regno, int cant_eliminate)
3558 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3559 regs_ever_live[regno] = 1;
3562 /* Spill every pseudo reg that was allocated to this reg
3563 or to something that overlaps this reg. */
3565 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3566 if (reg_renumber[i] >= 0
3567 && (unsigned int) reg_renumber[i] <= regno
3568 && ((unsigned int) reg_renumber[i]
3569 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3570 [PSEUDO_REGNO_MODE (i)]
3572 SET_REGNO_REG_SET (&spilled_pseudos, i);
3575 /* After find_reload_regs has been run for all insn that need reloads,
3576 and/or spill_hard_regs was called, this function is used to actually
3577 spill pseudo registers and try to reallocate them. It also sets up the
3578 spill_regs array for use by choose_reload_regs. */
3581 finish_spills (int global)
3583 struct insn_chain *chain;
3584 int something_changed = 0;
3586 reg_set_iterator rsi;
3588 /* Build the spill_regs array for the function. */
3589 /* If there are some registers still to eliminate and one of the spill regs
3590 wasn't ever used before, additional stack space may have to be
3591 allocated to store this register. Thus, we may have changed the offset
3592 between the stack and frame pointers, so mark that something has changed.
3594 One might think that we need only set VAL to 1 if this is a call-used
3595 register. However, the set of registers that must be saved by the
3596 prologue is not identical to the call-used set. For example, the
3597 register used by the call insn for the return PC is a call-used register,
3598 but must be saved by the prologue. */
3601 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3602 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3604 spill_reg_order[i] = n_spills;
3605 spill_regs[n_spills++] = i;
3606 if (num_eliminable && ! regs_ever_live[i])
3607 something_changed = 1;
3608 regs_ever_live[i] = 1;
3611 spill_reg_order[i] = -1;
3613 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3615 /* Record the current hard register the pseudo is allocated to in
3616 pseudo_previous_regs so we avoid reallocating it to the same
3617 hard reg in a later pass. */
3618 gcc_assert (reg_renumber[i] >= 0);
3620 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3621 /* Mark it as no longer having a hard register home. */
3622 reg_renumber[i] = -1;
3623 /* We will need to scan everything again. */
3624 something_changed = 1;
3627 /* Retry global register allocation if possible. */
3630 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3631 /* For every insn that needs reloads, set the registers used as spill
3632 regs in pseudo_forbidden_regs for every pseudo live across the
3634 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3636 EXECUTE_IF_SET_IN_REG_SET
3637 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3639 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3640 chain->used_spill_regs);
3642 EXECUTE_IF_SET_IN_REG_SET
3643 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3645 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3646 chain->used_spill_regs);
3650 /* Retry allocating the spilled pseudos. For each reg, merge the
3651 various reg sets that indicate which hard regs can't be used,
3652 and call retry_global_alloc.
3653 We change spill_pseudos here to only contain pseudos that did not
3654 get a new hard register. */
3655 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3656 if (reg_old_renumber[i] != reg_renumber[i])
3658 HARD_REG_SET forbidden;
3659 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3660 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3661 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3662 retry_global_alloc (i, forbidden);
3663 if (reg_renumber[i] >= 0)
3664 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3668 /* Fix up the register information in the insn chain.
3669 This involves deleting those of the spilled pseudos which did not get
3670 a new hard register home from the live_{before,after} sets. */
3671 for (chain = reload_insn_chain; chain; chain = chain->next)
3673 HARD_REG_SET used_by_pseudos;
3674 HARD_REG_SET used_by_pseudos2;
3676 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3677 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3679 /* Mark any unallocated hard regs as available for spills. That
3680 makes inheritance work somewhat better. */
3681 if (chain->need_reload)
3683 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3684 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3685 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3687 /* Save the old value for the sanity test below. */
3688 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3690 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3691 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3692 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3693 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3695 /* Make sure we only enlarge the set. */
3696 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3702 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3703 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3705 int regno = reg_renumber[i];
3706 if (reg_old_renumber[i] == regno)
3709 alter_reg (i, reg_old_renumber[i]);
3710 reg_old_renumber[i] = regno;
3714 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3716 fprintf (dump_file, " Register %d now in %d.\n\n",
3717 i, reg_renumber[i]);
3721 return something_changed;
3724 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3727 scan_paradoxical_subregs (rtx x)
3731 enum rtx_code code = GET_CODE (x);
3741 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3749 if (REG_P (SUBREG_REG (x))
3750 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3751 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3752 = GET_MODE_SIZE (GET_MODE (x));
3759 fmt = GET_RTX_FORMAT (code);
3760 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3763 scan_paradoxical_subregs (XEXP (x, i));
3764 else if (fmt[i] == 'E')
3767 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3768 scan_paradoxical_subregs (XVECEXP (x, i, j));
3773 /* Reload pseudo-registers into hard regs around each insn as needed.
3774 Additional register load insns are output before the insn that needs it
3775 and perhaps store insns after insns that modify the reloaded pseudo reg.
3777 reg_last_reload_reg and reg_reloaded_contents keep track of
3778 which registers are already available in reload registers.
3779 We update these for the reloads that we perform,
3780 as the insns are scanned. */
3783 reload_as_needed (int live_known)
3785 struct insn_chain *chain;
3786 #if defined (AUTO_INC_DEC)
3791 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3792 memset (spill_reg_store, 0, sizeof spill_reg_store);
3793 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3794 reg_has_output_reload = xmalloc (max_regno);
3795 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3796 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3798 set_initial_elim_offsets ();
3800 for (chain = reload_insn_chain; chain; chain = chain->next)
3803 rtx insn = chain->insn;
3804 rtx old_next = NEXT_INSN (insn);
3806 /* If we pass a label, copy the offsets from the label information
3807 into the current offsets of each elimination. */
3809 set_offsets_for_label (insn);
3811 else if (INSN_P (insn))
3813 rtx oldpat = copy_rtx (PATTERN (insn));
3815 /* If this is a USE and CLOBBER of a MEM, ensure that any
3816 references to eliminable registers have been removed. */
3818 if ((GET_CODE (PATTERN (insn)) == USE
3819 || GET_CODE (PATTERN (insn)) == CLOBBER)
3820 && MEM_P (XEXP (PATTERN (insn), 0)))
3821 XEXP (XEXP (PATTERN (insn), 0), 0)
3822 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3823 GET_MODE (XEXP (PATTERN (insn), 0)),
3826 /* If we need to do register elimination processing, do so.
3827 This might delete the insn, in which case we are done. */
3828 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3830 eliminate_regs_in_insn (insn, 1);
3833 update_eliminable_offsets ();
3838 /* If need_elim is nonzero but need_reload is zero, one might think
3839 that we could simply set n_reloads to 0. However, find_reloads
3840 could have done some manipulation of the insn (such as swapping
3841 commutative operands), and these manipulations are lost during
3842 the first pass for every insn that needs register elimination.
3843 So the actions of find_reloads must be redone here. */
3845 if (! chain->need_elim && ! chain->need_reload
3846 && ! chain->need_operand_change)
3848 /* First find the pseudo regs that must be reloaded for this insn.
3849 This info is returned in the tables reload_... (see reload.h).
3850 Also modify the body of INSN by substituting RELOAD
3851 rtx's for those pseudo regs. */
3854 memset (reg_has_output_reload, 0, max_regno);
3855 CLEAR_HARD_REG_SET (reg_is_output_reload);
3857 find_reloads (insn, 1, spill_indirect_levels, live_known,
3863 rtx next = NEXT_INSN (insn);
3866 prev = PREV_INSN (insn);
3868 /* Now compute which reload regs to reload them into. Perhaps
3869 reusing reload regs from previous insns, or else output
3870 load insns to reload them. Maybe output store insns too.
3871 Record the choices of reload reg in reload_reg_rtx. */
3872 choose_reload_regs (chain);
3874 /* Merge any reloads that we didn't combine for fear of
3875 increasing the number of spill registers needed but now
3876 discover can be safely merged. */
3877 if (SMALL_REGISTER_CLASSES)
3878 merge_assigned_reloads (insn);
3880 /* Generate the insns to reload operands into or out of
3881 their reload regs. */
3882 emit_reload_insns (chain);
3884 /* Substitute the chosen reload regs from reload_reg_rtx
3885 into the insn's body (or perhaps into the bodies of other
3886 load and store insn that we just made for reloading
3887 and that we moved the structure into). */
3888 subst_reloads (insn);
3890 /* If this was an ASM, make sure that all the reload insns
3891 we have generated are valid. If not, give an error
3894 if (asm_noperands (PATTERN (insn)) >= 0)
3895 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3896 if (p != insn && INSN_P (p)
3897 && GET_CODE (PATTERN (p)) != USE
3898 && (recog_memoized (p) < 0
3899 || (extract_insn (p), ! constrain_operands (1))))
3901 error_for_asm (insn,
3902 "%<asm%> operand requires "
3903 "impossible reload");
3908 if (num_eliminable && chain->need_elim)
3909 update_eliminable_offsets ();
3911 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3912 is no longer validly lying around to save a future reload.
3913 Note that this does not detect pseudos that were reloaded
3914 for this insn in order to be stored in
3915 (obeying register constraints). That is correct; such reload
3916 registers ARE still valid. */
3917 note_stores (oldpat, forget_old_reloads_1, NULL);
3919 /* There may have been CLOBBER insns placed after INSN. So scan
3920 between INSN and NEXT and use them to forget old reloads. */
3921 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3922 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3923 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3926 /* Likewise for regs altered by auto-increment in this insn.
3927 REG_INC notes have been changed by reloading:
3928 find_reloads_address_1 records substitutions for them,
3929 which have been performed by subst_reloads above. */
3930 for (i = n_reloads - 1; i >= 0; i--)
3932 rtx in_reg = rld[i].in_reg;
3935 enum rtx_code code = GET_CODE (in_reg);
3936 /* PRE_INC / PRE_DEC will have the reload register ending up
3937 with the same value as the stack slot, but that doesn't
3938 hold true for POST_INC / POST_DEC. Either we have to
3939 convert the memory access to a true POST_INC / POST_DEC,
3940 or we can't use the reload register for inheritance. */
3941 if ((code == POST_INC || code == POST_DEC)
3942 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3943 REGNO (rld[i].reg_rtx))
3944 /* Make sure it is the inc/dec pseudo, and not
3945 some other (e.g. output operand) pseudo. */
3946 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3947 == REGNO (XEXP (in_reg, 0))))
3950 rtx reload_reg = rld[i].reg_rtx;
3951 enum machine_mode mode = GET_MODE (reload_reg);
3955 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3957 /* We really want to ignore REG_INC notes here, so
3958 use PATTERN (p) as argument to reg_set_p . */
3959 if (reg_set_p (reload_reg, PATTERN (p)))
3961 n = count_occurrences (PATTERN (p), reload_reg, 0);
3966 n = validate_replace_rtx (reload_reg,
3967 gen_rtx_fmt_e (code,
3972 /* We must also verify that the constraints
3973 are met after the replacement. */
3976 n = constrain_operands (1);
3980 /* If the constraints were not met, then
3981 undo the replacement. */
3984 validate_replace_rtx (gen_rtx_fmt_e (code,
3997 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3999 /* Mark this as having an output reload so that the
4000 REG_INC processing code below won't invalidate
4001 the reload for inheritance. */
4002 SET_HARD_REG_BIT (reg_is_output_reload,
4003 REGNO (reload_reg));
4004 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4007 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4010 else if ((code == PRE_INC || code == PRE_DEC)
4011 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4012 REGNO (rld[i].reg_rtx))
4013 /* Make sure it is the inc/dec pseudo, and not
4014 some other (e.g. output operand) pseudo. */
4015 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4016 == REGNO (XEXP (in_reg, 0))))
4018 SET_HARD_REG_BIT (reg_is_output_reload,
4019 REGNO (rld[i].reg_rtx));
4020 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4024 /* If a pseudo that got a hard register is auto-incremented,
4025 we must purge records of copying it into pseudos without
4027 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4028 if (REG_NOTE_KIND (x) == REG_INC)
4030 /* See if this pseudo reg was reloaded in this insn.
4031 If so, its last-reload info is still valid
4032 because it is based on this insn's reload. */
4033 for (i = 0; i < n_reloads; i++)
4034 if (rld[i].out == XEXP (x, 0))
4038 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4042 /* A reload reg's contents are unknown after a label. */
4044 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4046 /* Don't assume a reload reg is still good after a call insn
4047 if it is a call-used reg, or if it contains a value that will
4048 be partially clobbered by the call. */
4049 else if (CALL_P (insn))
4051 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4052 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4057 free (reg_last_reload_reg);
4058 free (reg_has_output_reload);
4061 /* Discard all record of any value reloaded from X,
4062 or reloaded in X from someplace else;
4063 unless X is an output reload reg of the current insn.
4065 X may be a hard reg (the reload reg)
4066 or it may be a pseudo reg that was reloaded from. */
4069 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4070 void *data ATTRIBUTE_UNUSED)
4075 /* note_stores does give us subregs of hard regs,
4076 subreg_regno_offset requires a hard reg. */
4077 while (GET_CODE (x) == SUBREG)
4079 /* We ignore the subreg offset when calculating the regno,
4080 because we are using the entire underlying hard register
4090 if (regno >= FIRST_PSEUDO_REGISTER)
4096 nr = hard_regno_nregs[regno][GET_MODE (x)];
4097 /* Storing into a spilled-reg invalidates its contents.
4098 This can happen if a block-local pseudo is allocated to that reg
4099 and it wasn't spilled because this block's total need is 0.
4100 Then some insn might have an optional reload and use this reg. */
4101 for (i = 0; i < nr; i++)
4102 /* But don't do this if the reg actually serves as an output
4103 reload reg in the current instruction. */
4105 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4107 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4108 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4109 spill_reg_store[regno + i] = 0;
4113 /* Since value of X has changed,
4114 forget any value previously copied from it. */
4117 /* But don't forget a copy if this is the output reload
4118 that establishes the copy's validity. */
4119 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4120 reg_last_reload_reg[regno + nr] = 0;
4123 /* The following HARD_REG_SETs indicate when each hard register is
4124 used for a reload of various parts of the current insn. */
4126 /* If reg is unavailable for all reloads. */
4127 static HARD_REG_SET reload_reg_unavailable;
4128 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4129 static HARD_REG_SET reload_reg_used;
4130 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4131 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4132 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4133 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4134 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4135 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4136 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4137 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4138 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4139 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4140 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4141 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4142 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4143 static HARD_REG_SET reload_reg_used_in_op_addr;
4144 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4145 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4146 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4147 static HARD_REG_SET reload_reg_used_in_insn;
4148 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4149 static HARD_REG_SET reload_reg_used_in_other_addr;
4151 /* If reg is in use as a reload reg for any sort of reload. */
4152 static HARD_REG_SET reload_reg_used_at_all;
4154 /* If reg is use as an inherited reload. We just mark the first register
4156 static HARD_REG_SET reload_reg_used_for_inherit;
4158 /* Records which hard regs are used in any way, either as explicit use or
4159 by being allocated to a pseudo during any point of the current insn. */
4160 static HARD_REG_SET reg_used_in_insn;
4162 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4163 TYPE. MODE is used to indicate how many consecutive regs are
4167 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4168 enum machine_mode mode)
4170 unsigned int nregs = hard_regno_nregs[regno][mode];
4173 for (i = regno; i < nregs + regno; i++)
4178 SET_HARD_REG_BIT (reload_reg_used, i);
4181 case RELOAD_FOR_INPUT_ADDRESS:
4182 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4185 case RELOAD_FOR_INPADDR_ADDRESS:
4186 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4189 case RELOAD_FOR_OUTPUT_ADDRESS:
4190 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4193 case RELOAD_FOR_OUTADDR_ADDRESS:
4194 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4197 case RELOAD_FOR_OPERAND_ADDRESS:
4198 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4201 case RELOAD_FOR_OPADDR_ADDR:
4202 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4205 case RELOAD_FOR_OTHER_ADDRESS:
4206 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4209 case RELOAD_FOR_INPUT:
4210 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4213 case RELOAD_FOR_OUTPUT:
4214 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4217 case RELOAD_FOR_INSN:
4218 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4222 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4226 /* Similarly, but show REGNO is no longer in use for a reload. */
4229 clear_reload_reg_in_use (unsigned int regno, int opnum,
4230 enum reload_type type, enum machine_mode mode)
4232 unsigned int nregs = hard_regno_nregs[regno][mode];
4233 unsigned int start_regno, end_regno, r;
4235 /* A complication is that for some reload types, inheritance might
4236 allow multiple reloads of the same types to share a reload register.
4237 We set check_opnum if we have to check only reloads with the same
4238 operand number, and check_any if we have to check all reloads. */
4239 int check_opnum = 0;
4241 HARD_REG_SET *used_in_set;
4246 used_in_set = &reload_reg_used;
4249 case RELOAD_FOR_INPUT_ADDRESS:
4250 used_in_set = &reload_reg_used_in_input_addr[opnum];
4253 case RELOAD_FOR_INPADDR_ADDRESS:
4255 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4258 case RELOAD_FOR_OUTPUT_ADDRESS:
4259 used_in_set = &reload_reg_used_in_output_addr[opnum];
4262 case RELOAD_FOR_OUTADDR_ADDRESS:
4264 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4267 case RELOAD_FOR_OPERAND_ADDRESS:
4268 used_in_set = &reload_reg_used_in_op_addr;
4271 case RELOAD_FOR_OPADDR_ADDR:
4273 used_in_set = &reload_reg_used_in_op_addr_reload;
4276 case RELOAD_FOR_OTHER_ADDRESS:
4277 used_in_set = &reload_reg_used_in_other_addr;
4281 case RELOAD_FOR_INPUT:
4282 used_in_set = &reload_reg_used_in_input[opnum];
4285 case RELOAD_FOR_OUTPUT:
4286 used_in_set = &reload_reg_used_in_output[opnum];
4289 case RELOAD_FOR_INSN:
4290 used_in_set = &reload_reg_used_in_insn;
4295 /* We resolve conflicts with remaining reloads of the same type by
4296 excluding the intervals of reload registers by them from the
4297 interval of freed reload registers. Since we only keep track of
4298 one set of interval bounds, we might have to exclude somewhat
4299 more than what would be necessary if we used a HARD_REG_SET here.
4300 But this should only happen very infrequently, so there should
4301 be no reason to worry about it. */
4303 start_regno = regno;
4304 end_regno = regno + nregs;
4305 if (check_opnum || check_any)
4307 for (i = n_reloads - 1; i >= 0; i--)
4309 if (rld[i].when_needed == type
4310 && (check_any || rld[i].opnum == opnum)
4313 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4314 unsigned int conflict_end
4316 + hard_regno_nregs[conflict_start][rld[i].mode]);
4318 /* If there is an overlap with the first to-be-freed register,
4319 adjust the interval start. */
4320 if (conflict_start <= start_regno && conflict_end > start_regno)
4321 start_regno = conflict_end;
4322 /* Otherwise, if there is a conflict with one of the other
4323 to-be-freed registers, adjust the interval end. */
4324 if (conflict_start > start_regno && conflict_start < end_regno)
4325 end_regno = conflict_start;
4330 for (r = start_regno; r < end_regno; r++)
4331 CLEAR_HARD_REG_BIT (*used_in_set, r);
4334 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4335 specified by OPNUM and TYPE. */
4338 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4342 /* In use for a RELOAD_OTHER means it's not available for anything. */
4343 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4344 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4350 /* In use for anything means we can't use it for RELOAD_OTHER. */
4351 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4352 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4353 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4354 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4357 for (i = 0; i < reload_n_operands; i++)
4358 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4359 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4360 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4361 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4362 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4363 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4368 case RELOAD_FOR_INPUT:
4369 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4370 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4373 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4376 /* If it is used for some other input, can't use it. */
4377 for (i = 0; i < reload_n_operands; i++)
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4381 /* If it is used in a later operand's address, can't use it. */
4382 for (i = opnum + 1; i < reload_n_operands; i++)
4383 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4384 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4389 case RELOAD_FOR_INPUT_ADDRESS:
4390 /* Can't use a register if it is used for an input address for this
4391 operand or used as an input in an earlier one. */
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4393 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4396 for (i = 0; i < opnum; i++)
4397 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4402 case RELOAD_FOR_INPADDR_ADDRESS:
4403 /* Can't use a register if it is used for an input address
4404 for this operand or used as an input in an earlier
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4409 for (i = 0; i < opnum; i++)
4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4415 case RELOAD_FOR_OUTPUT_ADDRESS:
4416 /* Can't use a register if it is used for an output address for this
4417 operand or used as an output in this or a later operand. Note
4418 that multiple output operands are emitted in reverse order, so
4419 the conflicting ones are those with lower indices. */
4420 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4423 for (i = 0; i <= opnum; i++)
4424 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4429 case RELOAD_FOR_OUTADDR_ADDRESS:
4430 /* Can't use a register if it is used for an output address
4431 for this operand or used as an output in this or a
4432 later operand. Note that multiple output operands are
4433 emitted in reverse order, so the conflicting ones are
4434 those with lower indices. */
4435 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4438 for (i = 0; i <= opnum; i++)
4439 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4444 case RELOAD_FOR_OPERAND_ADDRESS:
4445 for (i = 0; i < reload_n_operands; i++)
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4449 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4450 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4452 case RELOAD_FOR_OPADDR_ADDR:
4453 for (i = 0; i < reload_n_operands; i++)
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4457 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4459 case RELOAD_FOR_OUTPUT:
4460 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4461 outputs, or an operand address for this or an earlier output.
4462 Note that multiple output operands are emitted in reverse order,
4463 so the conflicting ones are those with higher indices. */
4464 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4467 for (i = 0; i < reload_n_operands; i++)
4468 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4471 for (i = opnum; i < reload_n_operands; i++)
4472 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4473 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4478 case RELOAD_FOR_INSN:
4479 for (i = 0; i < reload_n_operands; i++)
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4481 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4484 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4485 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4487 case RELOAD_FOR_OTHER_ADDRESS:
4488 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4495 /* Return 1 if the value in reload reg REGNO, as used by a reload
4496 needed for the part of the insn specified by OPNUM and TYPE,
4497 is still available in REGNO at the end of the insn.
4499 We can assume that the reload reg was already tested for availability
4500 at the time it is needed, and we should not check this again,
4501 in case the reg has already been marked in use. */
4504 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4511 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4512 its value must reach the end. */
4515 /* If this use is for part of the insn,
4516 its value reaches if no subsequent part uses the same register.
4517 Just like the above function, don't try to do this with lots
4520 case RELOAD_FOR_OTHER_ADDRESS:
4521 /* Here we check for everything else, since these don't conflict
4522 with anything else and everything comes later. */
4524 for (i = 0; i < reload_n_operands; i++)
4525 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4529 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4533 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4534 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4535 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4536 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4538 case RELOAD_FOR_INPUT_ADDRESS:
4539 case RELOAD_FOR_INPADDR_ADDRESS:
4540 /* Similar, except that we check only for this and subsequent inputs
4541 and the address of only subsequent inputs and we do not need
4542 to check for RELOAD_OTHER objects since they are known not to
4545 for (i = opnum; i < reload_n_operands; i++)
4546 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4549 for (i = opnum + 1; i < reload_n_operands; i++)
4550 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4551 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4554 for (i = 0; i < reload_n_operands; i++)
4555 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4556 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4563 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4564 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4565 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4567 case RELOAD_FOR_INPUT:
4568 /* Similar to input address, except we start at the next operand for
4569 both input and input address and we do not check for
4570 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4573 for (i = opnum + 1; i < reload_n_operands; i++)
4574 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4575 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4579 /* ... fall through ... */
4581 case RELOAD_FOR_OPERAND_ADDRESS:
4582 /* Check outputs and their addresses. */
4584 for (i = 0; i < reload_n_operands; i++)
4585 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4586 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4587 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4590 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4592 case RELOAD_FOR_OPADDR_ADDR:
4593 for (i = 0; i < reload_n_operands; i++)
4594 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4595 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4599 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4600 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4601 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4603 case RELOAD_FOR_INSN:
4604 /* These conflict with other outputs with RELOAD_OTHER. So
4605 we need only check for output addresses. */
4607 opnum = reload_n_operands;
4609 /* ... fall through ... */
4611 case RELOAD_FOR_OUTPUT:
4612 case RELOAD_FOR_OUTPUT_ADDRESS:
4613 case RELOAD_FOR_OUTADDR_ADDRESS:
4614 /* We already know these can't conflict with a later output. So the
4615 only thing to check are later output addresses.
4616 Note that multiple output operands are emitted in reverse order,
4617 so the conflicting ones are those with lower indices. */
4618 for (i = 0; i < opnum; i++)
4619 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4620 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4630 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4633 This function uses the same algorithm as reload_reg_free_p above. */
4636 reloads_conflict (int r1, int r2)
4638 enum reload_type r1_type = rld[r1].when_needed;
4639 enum reload_type r2_type = rld[r2].when_needed;
4640 int r1_opnum = rld[r1].opnum;
4641 int r2_opnum = rld[r2].opnum;
4643 /* RELOAD_OTHER conflicts with everything. */
4644 if (r2_type == RELOAD_OTHER)
4647 /* Otherwise, check conflicts differently for each type. */
4651 case RELOAD_FOR_INPUT:
4652 return (r2_type == RELOAD_FOR_INSN
4653 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4654 || r2_type == RELOAD_FOR_OPADDR_ADDR
4655 || r2_type == RELOAD_FOR_INPUT
4656 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4657 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4658 && r2_opnum > r1_opnum));
4660 case RELOAD_FOR_INPUT_ADDRESS:
4661 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4662 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4664 case RELOAD_FOR_INPADDR_ADDRESS:
4665 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4666 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4668 case RELOAD_FOR_OUTPUT_ADDRESS:
4669 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4670 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4672 case RELOAD_FOR_OUTADDR_ADDRESS:
4673 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4674 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4676 case RELOAD_FOR_OPERAND_ADDRESS:
4677 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4678 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4680 case RELOAD_FOR_OPADDR_ADDR:
4681 return (r2_type == RELOAD_FOR_INPUT
4682 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4684 case RELOAD_FOR_OUTPUT:
4685 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4686 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4687 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4688 && r2_opnum >= r1_opnum));
4690 case RELOAD_FOR_INSN:
4691 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4692 || r2_type == RELOAD_FOR_INSN
4693 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4695 case RELOAD_FOR_OTHER_ADDRESS:
4696 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4706 /* Indexed by reload number, 1 if incoming value
4707 inherited from previous insns. */
4708 static char reload_inherited[MAX_RELOADS];
4710 /* For an inherited reload, this is the insn the reload was inherited from,
4711 if we know it. Otherwise, this is 0. */
4712 static rtx reload_inheritance_insn[MAX_RELOADS];
4714 /* If nonzero, this is a place to get the value of the reload,
4715 rather than using reload_in. */
4716 static rtx reload_override_in[MAX_RELOADS];
4718 /* For each reload, the hard register number of the register used,
4719 or -1 if we did not need a register for this reload. */
4720 static int reload_spill_index[MAX_RELOADS];
4722 /* Subroutine of free_for_value_p, used to check a single register.
4723 START_REGNO is the starting regno of the full reload register
4724 (possibly comprising multiple hard registers) that we are considering. */
4727 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4728 enum reload_type type, rtx value, rtx out,
4729 int reloadnum, int ignore_address_reloads)
4732 /* Set if we see an input reload that must not share its reload register
4733 with any new earlyclobber, but might otherwise share the reload
4734 register with an output or input-output reload. */
4735 int check_earlyclobber = 0;
4739 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4742 if (out == const0_rtx)
4748 /* We use some pseudo 'time' value to check if the lifetimes of the
4749 new register use would overlap with the one of a previous reload
4750 that is not read-only or uses a different value.
4751 The 'time' used doesn't have to be linear in any shape or form, just
4753 Some reload types use different 'buckets' for each operand.
4754 So there are MAX_RECOG_OPERANDS different time values for each
4756 We compute TIME1 as the time when the register for the prospective
4757 new reload ceases to be live, and TIME2 for each existing
4758 reload as the time when that the reload register of that reload
4760 Where there is little to be gained by exact lifetime calculations,
4761 we just make conservative assumptions, i.e. a longer lifetime;
4762 this is done in the 'default:' cases. */
4765 case RELOAD_FOR_OTHER_ADDRESS:
4766 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4767 time1 = copy ? 0 : 1;
4770 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4772 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4773 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4774 respectively, to the time values for these, we get distinct time
4775 values. To get distinct time values for each operand, we have to
4776 multiply opnum by at least three. We round that up to four because
4777 multiply by four is often cheaper. */
4778 case RELOAD_FOR_INPADDR_ADDRESS:
4779 time1 = opnum * 4 + 2;
4781 case RELOAD_FOR_INPUT_ADDRESS:
4782 time1 = opnum * 4 + 3;
4784 case RELOAD_FOR_INPUT:
4785 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4786 executes (inclusive). */
4787 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4789 case RELOAD_FOR_OPADDR_ADDR:
4791 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4792 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4794 case RELOAD_FOR_OPERAND_ADDRESS:
4795 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4797 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4799 case RELOAD_FOR_OUTADDR_ADDRESS:
4800 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4802 case RELOAD_FOR_OUTPUT_ADDRESS:
4803 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4806 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4809 for (i = 0; i < n_reloads; i++)
4811 rtx reg = rld[i].reg_rtx;
4812 if (reg && REG_P (reg)
4813 && ((unsigned) regno - true_regnum (reg)
4814 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4817 rtx other_input = rld[i].in;
4819 /* If the other reload loads the same input value, that
4820 will not cause a conflict only if it's loading it into
4821 the same register. */
4822 if (true_regnum (reg) != start_regno)
4823 other_input = NULL_RTX;
4824 if (! other_input || ! rtx_equal_p (other_input, value)
4825 || rld[i].out || out)
4828 switch (rld[i].when_needed)
4830 case RELOAD_FOR_OTHER_ADDRESS:
4833 case RELOAD_FOR_INPADDR_ADDRESS:
4834 /* find_reloads makes sure that a
4835 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4836 by at most one - the first -
4837 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4838 address reload is inherited, the address address reload
4839 goes away, so we can ignore this conflict. */
4840 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4841 && ignore_address_reloads
4842 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4843 Then the address address is still needed to store
4844 back the new address. */
4845 && ! rld[reloadnum].out)
4847 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4848 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4850 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4851 && ignore_address_reloads
4852 /* Unless we are reloading an auto_inc expression. */
4853 && ! rld[reloadnum].out)
4855 time2 = rld[i].opnum * 4 + 2;
4857 case RELOAD_FOR_INPUT_ADDRESS:
4858 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4859 && ignore_address_reloads
4860 && ! rld[reloadnum].out)
4862 time2 = rld[i].opnum * 4 + 3;
4864 case RELOAD_FOR_INPUT:
4865 time2 = rld[i].opnum * 4 + 4;
4866 check_earlyclobber = 1;
4868 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4869 == MAX_RECOG_OPERAND * 4 */
4870 case RELOAD_FOR_OPADDR_ADDR:
4871 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4872 && ignore_address_reloads
4873 && ! rld[reloadnum].out)
4875 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4877 case RELOAD_FOR_OPERAND_ADDRESS:
4878 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4879 check_earlyclobber = 1;
4881 case RELOAD_FOR_INSN:
4882 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4884 case RELOAD_FOR_OUTPUT:
4885 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4886 instruction is executed. */
4887 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4889 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4890 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4892 case RELOAD_FOR_OUTADDR_ADDRESS:
4893 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4894 && ignore_address_reloads
4895 && ! rld[reloadnum].out)
4897 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4899 case RELOAD_FOR_OUTPUT_ADDRESS:
4900 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4903 /* If there is no conflict in the input part, handle this
4904 like an output reload. */
4905 if (! rld[i].in || rtx_equal_p (other_input, value))
4907 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4908 /* Earlyclobbered outputs must conflict with inputs. */
4909 if (earlyclobber_operand_p (rld[i].out))
4910 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4915 /* RELOAD_OTHER might be live beyond instruction execution,
4916 but this is not obvious when we set time2 = 1. So check
4917 here if there might be a problem with the new reload
4918 clobbering the register used by the RELOAD_OTHER. */
4926 && (! rld[i].in || rld[i].out
4927 || ! rtx_equal_p (other_input, value)))
4928 || (out && rld[reloadnum].out_reg
4929 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4935 /* Earlyclobbered outputs must conflict with inputs. */
4936 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4942 /* Return 1 if the value in reload reg REGNO, as used by a reload
4943 needed for the part of the insn specified by OPNUM and TYPE,
4944 may be used to load VALUE into it.
4946 MODE is the mode in which the register is used, this is needed to
4947 determine how many hard regs to test.
4949 Other read-only reloads with the same value do not conflict
4950 unless OUT is nonzero and these other reloads have to live while
4951 output reloads live.
4952 If OUT is CONST0_RTX, this is a special case: it means that the
4953 test should not be for using register REGNO as reload register, but
4954 for copying from register REGNO into the reload register.
4956 RELOADNUM is the number of the reload we want to load this value for;
4957 a reload does not conflict with itself.
4959 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4960 reloads that load an address for the very reload we are considering.
4962 The caller has to make sure that there is no conflict with the return
4966 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4967 enum reload_type type, rtx value, rtx out, int reloadnum,
4968 int ignore_address_reloads)
4970 int nregs = hard_regno_nregs[regno][mode];
4972 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4973 value, out, reloadnum,
4974 ignore_address_reloads))
4979 /* Return nonzero if the rtx X is invariant over the current function. */
4980 /* ??? Actually, the places where we use this expect exactly what is
4981 tested here, and not everything that is function invariant. In
4982 particular, the frame pointer and arg pointer are special cased;
4983 pic_offset_table_rtx is not, and we must not spill these things to
4987 function_invariant_p (rtx x)
4991 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4993 if (GET_CODE (x) == PLUS
4994 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4995 && CONSTANT_P (XEXP (x, 1)))
5000 /* Determine whether the reload reg X overlaps any rtx'es used for
5001 overriding inheritance. Return nonzero if so. */
5004 conflicts_with_override (rtx x)
5007 for (i = 0; i < n_reloads; i++)
5008 if (reload_override_in[i]
5009 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5014 /* Give an error message saying we failed to find a reload for INSN,
5015 and clear out reload R. */
5017 failed_reload (rtx insn, int r)
5019 if (asm_noperands (PATTERN (insn)) < 0)
5020 /* It's the compiler's fault. */
5021 fatal_insn ("could not find a spill register", insn);
5023 /* It's the user's fault; the operand's mode and constraint
5024 don't match. Disable this reload so we don't crash in final. */
5025 error_for_asm (insn,
5026 "%<asm%> operand constraint incompatible with operand size");
5030 rld[r].optional = 1;
5031 rld[r].secondary_p = 1;
5034 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5035 for reload R. If it's valid, get an rtx for it. Return nonzero if
5038 set_reload_reg (int i, int r)
5041 rtx reg = spill_reg_rtx[i];
5043 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5044 spill_reg_rtx[i] = reg
5045 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5047 regno = true_regnum (reg);
5049 /* Detect when the reload reg can't hold the reload mode.
5050 This used to be one `if', but Sequent compiler can't handle that. */
5051 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5053 enum machine_mode test_mode = VOIDmode;
5055 test_mode = GET_MODE (rld[r].in);
5056 /* If rld[r].in has VOIDmode, it means we will load it
5057 in whatever mode the reload reg has: to wit, rld[r].mode.
5058 We have already tested that for validity. */
5059 /* Aside from that, we need to test that the expressions
5060 to reload from or into have modes which are valid for this
5061 reload register. Otherwise the reload insns would be invalid. */
5062 if (! (rld[r].in != 0 && test_mode != VOIDmode
5063 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5064 if (! (rld[r].out != 0
5065 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5067 /* The reg is OK. */
5070 /* Mark as in use for this insn the reload regs we use
5072 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5073 rld[r].when_needed, rld[r].mode);
5075 rld[r].reg_rtx = reg;
5076 reload_spill_index[r] = spill_regs[i];
5083 /* Find a spill register to use as a reload register for reload R.
5084 LAST_RELOAD is nonzero if this is the last reload for the insn being
5087 Set rld[R].reg_rtx to the register allocated.
5089 We return 1 if successful, or 0 if we couldn't find a spill reg and
5090 we didn't change anything. */
5093 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5098 /* If we put this reload ahead, thinking it is a group,
5099 then insist on finding a group. Otherwise we can grab a
5100 reg that some other reload needs.
5101 (That can happen when we have a 68000 DATA_OR_FP_REG
5102 which is a group of data regs or one fp reg.)
5103 We need not be so restrictive if there are no more reloads
5106 ??? Really it would be nicer to have smarter handling
5107 for that kind of reg class, where a problem like this is normal.
5108 Perhaps those classes should be avoided for reloading
5109 by use of more alternatives. */
5111 int force_group = rld[r].nregs > 1 && ! last_reload;
5113 /* If we want a single register and haven't yet found one,
5114 take any reg in the right class and not in use.
5115 If we want a consecutive group, here is where we look for it.
5117 We use two passes so we can first look for reload regs to
5118 reuse, which are already in use for other reloads in this insn,
5119 and only then use additional registers.
5120 I think that maximizing reuse is needed to make sure we don't
5121 run out of reload regs. Suppose we have three reloads, and
5122 reloads A and B can share regs. These need two regs.
5123 Suppose A and B are given different regs.
5124 That leaves none for C. */
5125 for (pass = 0; pass < 2; pass++)
5127 /* I is the index in spill_regs.
5128 We advance it round-robin between insns to use all spill regs
5129 equally, so that inherited reloads have a chance
5130 of leapfrogging each other. */
5134 for (count = 0; count < n_spills; count++)
5136 int class = (int) rld[r].class;
5142 regnum = spill_regs[i];
5144 if ((reload_reg_free_p (regnum, rld[r].opnum,
5147 /* We check reload_reg_used to make sure we
5148 don't clobber the return register. */
5149 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5150 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5151 rld[r].when_needed, rld[r].in,
5153 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5154 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5155 /* Look first for regs to share, then for unshared. But
5156 don't share regs used for inherited reloads; they are
5157 the ones we want to preserve. */
5159 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5161 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5164 int nr = hard_regno_nregs[regnum][rld[r].mode];
5165 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5166 (on 68000) got us two FP regs. If NR is 1,
5167 we would reject both of them. */
5170 /* If we need only one reg, we have already won. */
5173 /* But reject a single reg if we demand a group. */
5178 /* Otherwise check that as many consecutive regs as we need
5179 are available here. */
5182 int regno = regnum + nr - 1;
5183 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5184 && spill_reg_order[regno] >= 0
5185 && reload_reg_free_p (regno, rld[r].opnum,
5186 rld[r].when_needed)))
5195 /* If we found something on pass 1, omit pass 2. */
5196 if (count < n_spills)
5200 /* We should have found a spill register by now. */
5201 if (count >= n_spills)
5204 /* I is the index in SPILL_REG_RTX of the reload register we are to
5205 allocate. Get an rtx for it and find its register number. */
5207 return set_reload_reg (i, r);
5210 /* Initialize all the tables needed to allocate reload registers.
5211 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5212 is the array we use to restore the reg_rtx field for every reload. */
5215 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5219 for (i = 0; i < n_reloads; i++)
5220 rld[i].reg_rtx = save_reload_reg_rtx[i];
5222 memset (reload_inherited, 0, MAX_RELOADS);
5223 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5224 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5226 CLEAR_HARD_REG_SET (reload_reg_used);
5227 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5228 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5229 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5230 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5231 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5233 CLEAR_HARD_REG_SET (reg_used_in_insn);
5236 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5237 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5238 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5239 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5240 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5241 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5244 for (i = 0; i < reload_n_operands; i++)
5246 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5247 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5248 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5249 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5250 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5251 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5254 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5256 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5258 for (i = 0; i < n_reloads; i++)
5259 /* If we have already decided to use a certain register,
5260 don't use it in another way. */
5262 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5263 rld[i].when_needed, rld[i].mode);
5266 /* Assign hard reg targets for the pseudo-registers we must reload
5267 into hard regs for this insn.
5268 Also output the instructions to copy them in and out of the hard regs.
5270 For machines with register classes, we are responsible for
5271 finding a reload reg in the proper class. */
5274 choose_reload_regs (struct insn_chain *chain)
5276 rtx insn = chain->insn;
5278 unsigned int max_group_size = 1;
5279 enum reg_class group_class = NO_REGS;
5280 int pass, win, inheritance;
5282 rtx save_reload_reg_rtx[MAX_RELOADS];
5284 /* In order to be certain of getting the registers we need,
5285 we must sort the reloads into order of increasing register class.
5286 Then our grabbing of reload registers will parallel the process
5287 that provided the reload registers.
5289 Also note whether any of the reloads wants a consecutive group of regs.
5290 If so, record the maximum size of the group desired and what
5291 register class contains all the groups needed by this insn. */
5293 for (j = 0; j < n_reloads; j++)
5295 reload_order[j] = j;
5296 reload_spill_index[j] = -1;
5298 if (rld[j].nregs > 1)
5300 max_group_size = MAX (rld[j].nregs, max_group_size);
5302 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5305 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5309 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5311 /* If -O, try first with inheritance, then turning it off.
5312 If not -O, don't do inheritance.
5313 Using inheritance when not optimizing leads to paradoxes
5314 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5315 because one side of the comparison might be inherited. */
5317 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5319 choose_reload_regs_init (chain, save_reload_reg_rtx);
5321 /* Process the reloads in order of preference just found.
5322 Beyond this point, subregs can be found in reload_reg_rtx.
5324 This used to look for an existing reloaded home for all of the
5325 reloads, and only then perform any new reloads. But that could lose
5326 if the reloads were done out of reg-class order because a later
5327 reload with a looser constraint might have an old home in a register
5328 needed by an earlier reload with a tighter constraint.
5330 To solve this, we make two passes over the reloads, in the order
5331 described above. In the first pass we try to inherit a reload
5332 from a previous insn. If there is a later reload that needs a
5333 class that is a proper subset of the class being processed, we must
5334 also allocate a spill register during the first pass.
5336 Then make a second pass over the reloads to allocate any reloads
5337 that haven't been given registers yet. */
5339 for (j = 0; j < n_reloads; j++)
5341 int r = reload_order[j];
5342 rtx search_equiv = NULL_RTX;
5344 /* Ignore reloads that got marked inoperative. */
5345 if (rld[r].out == 0 && rld[r].in == 0
5346 && ! rld[r].secondary_p)
5349 /* If find_reloads chose to use reload_in or reload_out as a reload
5350 register, we don't need to chose one. Otherwise, try even if it
5351 found one since we might save an insn if we find the value lying
5353 Try also when reload_in is a pseudo without a hard reg. */
5354 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5355 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5356 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5357 && !MEM_P (rld[r].in)
5358 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5361 #if 0 /* No longer needed for correct operation.
5362 It might give better code, or might not; worth an experiment? */
5363 /* If this is an optional reload, we can't inherit from earlier insns
5364 until we are sure that any non-optional reloads have been allocated.
5365 The following code takes advantage of the fact that optional reloads
5366 are at the end of reload_order. */
5367 if (rld[r].optional != 0)
5368 for (i = 0; i < j; i++)
5369 if ((rld[reload_order[i]].out != 0
5370 || rld[reload_order[i]].in != 0
5371 || rld[reload_order[i]].secondary_p)
5372 && ! rld[reload_order[i]].optional
5373 && rld[reload_order[i]].reg_rtx == 0)
5374 allocate_reload_reg (chain, reload_order[i], 0);
5377 /* First see if this pseudo is already available as reloaded
5378 for a previous insn. We cannot try to inherit for reloads
5379 that are smaller than the maximum number of registers needed
5380 for groups unless the register we would allocate cannot be used
5383 We could check here to see if this is a secondary reload for
5384 an object that is already in a register of the desired class.
5385 This would avoid the need for the secondary reload register.
5386 But this is complex because we can't easily determine what
5387 objects might want to be loaded via this reload. So let a
5388 register be allocated here. In `emit_reload_insns' we suppress
5389 one of the loads in the case described above. */
5395 enum machine_mode mode = VOIDmode;
5399 else if (REG_P (rld[r].in))
5401 regno = REGNO (rld[r].in);
5402 mode = GET_MODE (rld[r].in);
5404 else if (REG_P (rld[r].in_reg))
5406 regno = REGNO (rld[r].in_reg);
5407 mode = GET_MODE (rld[r].in_reg);
5409 else if (GET_CODE (rld[r].in_reg) == SUBREG
5410 && REG_P (SUBREG_REG (rld[r].in_reg)))
5412 byte = SUBREG_BYTE (rld[r].in_reg);
5413 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5414 if (regno < FIRST_PSEUDO_REGISTER)
5415 regno = subreg_regno (rld[r].in_reg);
5416 mode = GET_MODE (rld[r].in_reg);
5419 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5420 || GET_CODE (rld[r].in_reg) == PRE_DEC
5421 || GET_CODE (rld[r].in_reg) == POST_INC
5422 || GET_CODE (rld[r].in_reg) == POST_DEC)
5423 && REG_P (XEXP (rld[r].in_reg, 0)))
5425 regno = REGNO (XEXP (rld[r].in_reg, 0));
5426 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5427 rld[r].out = rld[r].in;
5431 /* This won't work, since REGNO can be a pseudo reg number.
5432 Also, it takes much more hair to keep track of all the things
5433 that can invalidate an inherited reload of part of a pseudoreg. */
5434 else if (GET_CODE (rld[r].in) == SUBREG
5435 && REG_P (SUBREG_REG (rld[r].in)))
5436 regno = subreg_regno (rld[r].in);
5439 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5441 enum reg_class class = rld[r].class, last_class;
5442 rtx last_reg = reg_last_reload_reg[regno];
5443 enum machine_mode need_mode;
5445 i = REGNO (last_reg);
5446 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5447 last_class = REGNO_REG_CLASS (i);
5453 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5454 + byte * BITS_PER_UNIT,
5455 GET_MODE_CLASS (mode));
5457 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5458 >= GET_MODE_SIZE (need_mode))
5459 #ifdef CANNOT_CHANGE_MODE_CLASS
5460 /* Verify that the register in "i" can be obtained
5462 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5463 GET_MODE (last_reg),
5466 && reg_reloaded_contents[i] == regno
5467 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5468 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5469 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5470 /* Even if we can't use this register as a reload
5471 register, we might use it for reload_override_in,
5472 if copying it to the desired class is cheap
5474 || ((REGISTER_MOVE_COST (mode, last_class, class)
5475 < MEMORY_MOVE_COST (mode, class, 1))
5476 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5477 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5481 #ifdef SECONDARY_MEMORY_NEEDED
5482 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5487 && (rld[r].nregs == max_group_size
5488 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5490 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5491 rld[r].when_needed, rld[r].in,
5494 /* If a group is needed, verify that all the subsequent
5495 registers still have their values intact. */
5496 int nr = hard_regno_nregs[i][rld[r].mode];
5499 for (k = 1; k < nr; k++)
5500 if (reg_reloaded_contents[i + k] != regno
5501 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5509 last_reg = (GET_MODE (last_reg) == mode
5510 ? last_reg : gen_rtx_REG (mode, i));
5513 for (k = 0; k < nr; k++)
5514 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5517 /* We found a register that contains the
5518 value we need. If this register is the
5519 same as an `earlyclobber' operand of the
5520 current insn, just mark it as a place to
5521 reload from since we can't use it as the
5522 reload register itself. */
5524 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5525 if (reg_overlap_mentioned_for_reload_p
5526 (reg_last_reload_reg[regno],
5527 reload_earlyclobbers[i1]))
5530 if (i1 != n_earlyclobbers
5531 || ! (free_for_value_p (i, rld[r].mode,
5533 rld[r].when_needed, rld[r].in,
5535 /* Don't use it if we'd clobber a pseudo reg. */
5536 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5538 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5539 /* Don't clobber the frame pointer. */
5540 || (i == HARD_FRAME_POINTER_REGNUM
5541 && frame_pointer_needed
5543 /* Don't really use the inherited spill reg
5544 if we need it wider than we've got it. */
5545 || (GET_MODE_SIZE (rld[r].mode)
5546 > GET_MODE_SIZE (mode))
5549 /* If find_reloads chose reload_out as reload
5550 register, stay with it - that leaves the
5551 inherited register for subsequent reloads. */
5552 || (rld[r].out && rld[r].reg_rtx
5553 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5555 if (! rld[r].optional)
5557 reload_override_in[r] = last_reg;
5558 reload_inheritance_insn[r]
5559 = reg_reloaded_insn[i];
5565 /* We can use this as a reload reg. */
5566 /* Mark the register as in use for this part of
5568 mark_reload_reg_in_use (i,
5572 rld[r].reg_rtx = last_reg;
5573 reload_inherited[r] = 1;
5574 reload_inheritance_insn[r]
5575 = reg_reloaded_insn[i];
5576 reload_spill_index[r] = i;
5577 for (k = 0; k < nr; k++)
5578 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5586 /* Here's another way to see if the value is already lying around. */
5589 && ! reload_inherited[r]
5591 && (CONSTANT_P (rld[r].in)
5592 || GET_CODE (rld[r].in) == PLUS
5593 || REG_P (rld[r].in)
5594 || MEM_P (rld[r].in))
5595 && (rld[r].nregs == max_group_size
5596 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5597 search_equiv = rld[r].in;
5598 /* If this is an output reload from a simple move insn, look
5599 if an equivalence for the input is available. */
5600 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5602 rtx set = single_set (insn);
5605 && rtx_equal_p (rld[r].out, SET_DEST (set))
5606 && CONSTANT_P (SET_SRC (set)))
5607 search_equiv = SET_SRC (set);
5613 = find_equiv_reg (search_equiv, insn, rld[r].class,
5614 -1, NULL, 0, rld[r].mode);
5620 regno = REGNO (equiv);
5623 /* This must be a SUBREG of a hard register.
5624 Make a new REG since this might be used in an
5625 address and not all machines support SUBREGs
5627 gcc_assert (GET_CODE (equiv) == SUBREG);
5628 regno = subreg_regno (equiv);
5629 equiv = gen_rtx_REG (rld[r].mode, regno);
5630 /* If we choose EQUIV as the reload register, but the
5631 loop below decides to cancel the inheritance, we'll
5632 end up reloading EQUIV in rld[r].mode, not the mode
5633 it had originally. That isn't safe when EQUIV isn't
5634 available as a spill register since its value might
5635 still be live at this point. */
5636 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5637 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5642 /* If we found a spill reg, reject it unless it is free
5643 and of the desired class. */
5647 int bad_for_class = 0;
5648 int max_regno = regno + rld[r].nregs;
5650 for (i = regno; i < max_regno; i++)
5652 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5654 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5659 && ! free_for_value_p (regno, rld[r].mode,
5660 rld[r].opnum, rld[r].when_needed,
5661 rld[r].in, rld[r].out, r, 1))
5666 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5669 /* We found a register that contains the value we need.
5670 If this register is the same as an `earlyclobber' operand
5671 of the current insn, just mark it as a place to reload from
5672 since we can't use it as the reload register itself. */
5675 for (i = 0; i < n_earlyclobbers; i++)
5676 if (reg_overlap_mentioned_for_reload_p (equiv,
5677 reload_earlyclobbers[i]))
5679 if (! rld[r].optional)
5680 reload_override_in[r] = equiv;
5685 /* If the equiv register we have found is explicitly clobbered
5686 in the current insn, it depends on the reload type if we
5687 can use it, use it for reload_override_in, or not at all.
5688 In particular, we then can't use EQUIV for a
5689 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5693 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5694 switch (rld[r].when_needed)
5696 case RELOAD_FOR_OTHER_ADDRESS:
5697 case RELOAD_FOR_INPADDR_ADDRESS:
5698 case RELOAD_FOR_INPUT_ADDRESS:
5699 case RELOAD_FOR_OPADDR_ADDR:
5702 case RELOAD_FOR_INPUT:
5703 case RELOAD_FOR_OPERAND_ADDRESS:
5704 if (! rld[r].optional)
5705 reload_override_in[r] = equiv;
5711 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5712 switch (rld[r].when_needed)
5714 case RELOAD_FOR_OTHER_ADDRESS:
5715 case RELOAD_FOR_INPADDR_ADDRESS:
5716 case RELOAD_FOR_INPUT_ADDRESS:
5717 case RELOAD_FOR_OPADDR_ADDR:
5718 case RELOAD_FOR_OPERAND_ADDRESS:
5719 case RELOAD_FOR_INPUT:
5722 if (! rld[r].optional)
5723 reload_override_in[r] = equiv;
5731 /* If we found an equivalent reg, say no code need be generated
5732 to load it, and use it as our reload reg. */
5734 && (regno != HARD_FRAME_POINTER_REGNUM
5735 || !frame_pointer_needed))
5737 int nr = hard_regno_nregs[regno][rld[r].mode];
5739 rld[r].reg_rtx = equiv;
5740 reload_inherited[r] = 1;
5742 /* If reg_reloaded_valid is not set for this register,
5743 there might be a stale spill_reg_store lying around.
5744 We must clear it, since otherwise emit_reload_insns
5745 might delete the store. */
5746 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5747 spill_reg_store[regno] = NULL_RTX;
5748 /* If any of the hard registers in EQUIV are spill
5749 registers, mark them as in use for this insn. */
5750 for (k = 0; k < nr; k++)
5752 i = spill_reg_order[regno + k];
5755 mark_reload_reg_in_use (regno, rld[r].opnum,
5758 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5765 /* If we found a register to use already, or if this is an optional
5766 reload, we are done. */
5767 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5771 /* No longer needed for correct operation. Might or might
5772 not give better code on the average. Want to experiment? */
5774 /* See if there is a later reload that has a class different from our
5775 class that intersects our class or that requires less register
5776 than our reload. If so, we must allocate a register to this
5777 reload now, since that reload might inherit a previous reload
5778 and take the only available register in our class. Don't do this
5779 for optional reloads since they will force all previous reloads
5780 to be allocated. Also don't do this for reloads that have been
5783 for (i = j + 1; i < n_reloads; i++)
5785 int s = reload_order[i];
5787 if ((rld[s].in == 0 && rld[s].out == 0
5788 && ! rld[s].secondary_p)
5792 if ((rld[s].class != rld[r].class
5793 && reg_classes_intersect_p (rld[r].class,
5795 || rld[s].nregs < rld[r].nregs)
5802 allocate_reload_reg (chain, r, j == n_reloads - 1);
5806 /* Now allocate reload registers for anything non-optional that
5807 didn't get one yet. */
5808 for (j = 0; j < n_reloads; j++)
5810 int r = reload_order[j];
5812 /* Ignore reloads that got marked inoperative. */
5813 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5816 /* Skip reloads that already have a register allocated or are
5818 if (rld[r].reg_rtx != 0 || rld[r].optional)
5821 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5825 /* If that loop got all the way, we have won. */
5832 /* Loop around and try without any inheritance. */
5837 /* First undo everything done by the failed attempt
5838 to allocate with inheritance. */
5839 choose_reload_regs_init (chain, save_reload_reg_rtx);
5841 /* Some sanity tests to verify that the reloads found in the first
5842 pass are identical to the ones we have now. */
5843 gcc_assert (chain->n_reloads == n_reloads);
5845 for (i = 0; i < n_reloads; i++)
5847 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5849 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5850 for (j = 0; j < n_spills; j++)
5851 if (spill_regs[j] == chain->rld[i].regno)
5852 if (! set_reload_reg (j, i))
5853 failed_reload (chain->insn, i);
5857 /* If we thought we could inherit a reload, because it seemed that
5858 nothing else wanted the same reload register earlier in the insn,
5859 verify that assumption, now that all reloads have been assigned.
5860 Likewise for reloads where reload_override_in has been set. */
5862 /* If doing expensive optimizations, do one preliminary pass that doesn't
5863 cancel any inheritance, but removes reloads that have been needed only
5864 for reloads that we know can be inherited. */
5865 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5867 for (j = 0; j < n_reloads; j++)
5869 int r = reload_order[j];
5871 if (reload_inherited[r] && rld[r].reg_rtx)
5872 check_reg = rld[r].reg_rtx;
5873 else if (reload_override_in[r]
5874 && (REG_P (reload_override_in[r])
5875 || GET_CODE (reload_override_in[r]) == SUBREG))
5876 check_reg = reload_override_in[r];
5879 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5880 rld[r].opnum, rld[r].when_needed, rld[r].in,
5881 (reload_inherited[r]
5882 ? rld[r].out : const0_rtx),
5887 reload_inherited[r] = 0;
5888 reload_override_in[r] = 0;
5890 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5891 reload_override_in, then we do not need its related
5892 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5893 likewise for other reload types.
5894 We handle this by removing a reload when its only replacement
5895 is mentioned in reload_in of the reload we are going to inherit.
5896 A special case are auto_inc expressions; even if the input is
5897 inherited, we still need the address for the output. We can
5898 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5899 If we succeeded removing some reload and we are doing a preliminary
5900 pass just to remove such reloads, make another pass, since the
5901 removal of one reload might allow us to inherit another one. */
5903 && rld[r].out != rld[r].in
5904 && remove_address_replacements (rld[r].in) && pass)
5909 /* Now that reload_override_in is known valid,
5910 actually override reload_in. */
5911 for (j = 0; j < n_reloads; j++)
5912 if (reload_override_in[j])
5913 rld[j].in = reload_override_in[j];
5915 /* If this reload won't be done because it has been canceled or is
5916 optional and not inherited, clear reload_reg_rtx so other
5917 routines (such as subst_reloads) don't get confused. */
5918 for (j = 0; j < n_reloads; j++)
5919 if (rld[j].reg_rtx != 0
5920 && ((rld[j].optional && ! reload_inherited[j])
5921 || (rld[j].in == 0 && rld[j].out == 0
5922 && ! rld[j].secondary_p)))
5924 int regno = true_regnum (rld[j].reg_rtx);
5926 if (spill_reg_order[regno] >= 0)
5927 clear_reload_reg_in_use (regno, rld[j].opnum,
5928 rld[j].when_needed, rld[j].mode);
5930 reload_spill_index[j] = -1;
5933 /* Record which pseudos and which spill regs have output reloads. */
5934 for (j = 0; j < n_reloads; j++)
5936 int r = reload_order[j];
5938 i = reload_spill_index[r];
5940 /* I is nonneg if this reload uses a register.
5941 If rld[r].reg_rtx is 0, this is an optional reload
5942 that we opted to ignore. */
5943 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5944 && rld[r].reg_rtx != 0)
5946 int nregno = REGNO (rld[r].out_reg);
5949 if (nregno < FIRST_PSEUDO_REGISTER)
5950 nr = hard_regno_nregs[nregno][rld[r].mode];
5953 reg_has_output_reload[nregno + nr] = 1;
5957 nr = hard_regno_nregs[i][rld[r].mode];
5959 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5962 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5963 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5964 || rld[r].when_needed == RELOAD_FOR_INSN);
5969 /* Deallocate the reload register for reload R. This is called from
5970 remove_address_replacements. */
5973 deallocate_reload_reg (int r)
5977 if (! rld[r].reg_rtx)
5979 regno = true_regnum (rld[r].reg_rtx);
5981 if (spill_reg_order[regno] >= 0)
5982 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5984 reload_spill_index[r] = -1;
5987 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5988 reloads of the same item for fear that we might not have enough reload
5989 registers. However, normally they will get the same reload register
5990 and hence actually need not be loaded twice.
5992 Here we check for the most common case of this phenomenon: when we have
5993 a number of reloads for the same object, each of which were allocated
5994 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5995 reload, and is not modified in the insn itself. If we find such,
5996 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5997 This will not increase the number of spill registers needed and will
5998 prevent redundant code. */
6001 merge_assigned_reloads (rtx insn)
6005 /* Scan all the reloads looking for ones that only load values and
6006 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6007 assigned and not modified by INSN. */
6009 for (i = 0; i < n_reloads; i++)
6011 int conflicting_input = 0;
6012 int max_input_address_opnum = -1;
6013 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6015 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6016 || rld[i].out != 0 || rld[i].reg_rtx == 0
6017 || reg_set_p (rld[i].reg_rtx, insn))
6020 /* Look at all other reloads. Ensure that the only use of this
6021 reload_reg_rtx is in a reload that just loads the same value
6022 as we do. Note that any secondary reloads must be of the identical
6023 class since the values, modes, and result registers are the
6024 same, so we need not do anything with any secondary reloads. */
6026 for (j = 0; j < n_reloads; j++)
6028 if (i == j || rld[j].reg_rtx == 0
6029 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6033 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6034 && rld[j].opnum > max_input_address_opnum)
6035 max_input_address_opnum = rld[j].opnum;
6037 /* If the reload regs aren't exactly the same (e.g, different modes)
6038 or if the values are different, we can't merge this reload.
6039 But if it is an input reload, we might still merge
6040 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6042 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6043 || rld[j].out != 0 || rld[j].in == 0
6044 || ! rtx_equal_p (rld[i].in, rld[j].in))
6046 if (rld[j].when_needed != RELOAD_FOR_INPUT
6047 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6048 || rld[i].opnum > rld[j].opnum)
6049 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6051 conflicting_input = 1;
6052 if (min_conflicting_input_opnum > rld[j].opnum)
6053 min_conflicting_input_opnum = rld[j].opnum;
6057 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6058 we, in fact, found any matching reloads. */
6061 && max_input_address_opnum <= min_conflicting_input_opnum)
6063 for (j = 0; j < n_reloads; j++)
6064 if (i != j && rld[j].reg_rtx != 0
6065 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6066 && (! conflicting_input
6067 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6068 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6070 rld[i].when_needed = RELOAD_OTHER;
6072 reload_spill_index[j] = -1;
6073 transfer_replacements (i, j);
6076 /* If this is now RELOAD_OTHER, look for any reloads that load
6077 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6078 if they were for inputs, RELOAD_OTHER for outputs. Note that
6079 this test is equivalent to looking for reloads for this operand
6081 /* We must take special care when there are two or more reloads to
6082 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6083 same value or a part of it; we must not change its type if there
6084 is a conflicting input. */
6086 if (rld[i].when_needed == RELOAD_OTHER)
6087 for (j = 0; j < n_reloads; j++)
6089 && rld[j].when_needed != RELOAD_OTHER
6090 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6091 && (! conflicting_input
6092 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6093 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6094 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6100 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6101 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6102 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6104 /* Check to see if we accidentally converted two
6105 reloads that use the same reload register with
6106 different inputs to the same type. If so, the
6107 resulting code won't work. */
6109 for (k = 0; k < j; k++)
6110 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6111 || rld[k].when_needed != rld[j].when_needed
6112 || !rtx_equal_p (rld[k].reg_rtx,
6114 || rtx_equal_p (rld[k].in,
6121 /* These arrays are filled by emit_reload_insns and its subroutines. */
6122 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6123 static rtx other_input_address_reload_insns = 0;
6124 static rtx other_input_reload_insns = 0;
6125 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6126 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6127 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6128 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6129 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6130 static rtx operand_reload_insns = 0;
6131 static rtx other_operand_reload_insns = 0;
6132 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6134 /* Values to be put in spill_reg_store are put here first. */
6135 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6136 static HARD_REG_SET reg_reloaded_died;
6138 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6139 has the number J. OLD contains the value to be used as input. */
6142 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6145 rtx insn = chain->insn;
6146 rtx reloadreg = rl->reg_rtx;
6147 rtx oldequiv_reg = 0;
6150 enum machine_mode mode;
6153 /* Determine the mode to reload in.
6154 This is very tricky because we have three to choose from.
6155 There is the mode the insn operand wants (rl->inmode).
6156 There is the mode of the reload register RELOADREG.
6157 There is the intrinsic mode of the operand, which we could find
6158 by stripping some SUBREGs.
6159 It turns out that RELOADREG's mode is irrelevant:
6160 we can change that arbitrarily.
6162 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6163 then the reload reg may not support QImode moves, so use SImode.
6164 If foo is in memory due to spilling a pseudo reg, this is safe,
6165 because the QImode value is in the least significant part of a
6166 slot big enough for a SImode. If foo is some other sort of
6167 memory reference, then it is impossible to reload this case,
6168 so previous passes had better make sure this never happens.
6170 Then consider a one-word union which has SImode and one of its
6171 members is a float, being fetched as (SUBREG:SF union:SI).
6172 We must fetch that as SFmode because we could be loading into
6173 a float-only register. In this case OLD's mode is correct.
6175 Consider an immediate integer: it has VOIDmode. Here we need
6176 to get a mode from something else.
6178 In some cases, there is a fourth mode, the operand's
6179 containing mode. If the insn specifies a containing mode for
6180 this operand, it overrides all others.
6182 I am not sure whether the algorithm here is always right,
6183 but it does the right things in those cases. */
6185 mode = GET_MODE (old);
6186 if (mode == VOIDmode)
6189 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6190 /* If we need a secondary register for this operation, see if
6191 the value is already in a register in that class. Don't
6192 do this if the secondary register will be used as a scratch
6195 if (rl->secondary_in_reload >= 0
6196 && rl->secondary_in_icode == CODE_FOR_nothing
6199 = find_equiv_reg (old, insn,
6200 rld[rl->secondary_in_reload].class,
6204 /* If reloading from memory, see if there is a register
6205 that already holds the same value. If so, reload from there.
6206 We can pass 0 as the reload_reg_p argument because
6207 any other reload has either already been emitted,
6208 in which case find_equiv_reg will see the reload-insn,
6209 or has yet to be emitted, in which case it doesn't matter
6210 because we will use this equiv reg right away. */
6212 if (oldequiv == 0 && optimize
6215 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6216 && reg_renumber[REGNO (old)] < 0)))
6217 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6221 unsigned int regno = true_regnum (oldequiv);
6223 /* Don't use OLDEQUIV if any other reload changes it at an
6224 earlier stage of this insn or at this stage. */
6225 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6226 rl->in, const0_rtx, j, 0))
6229 /* If it is no cheaper to copy from OLDEQUIV into the
6230 reload register than it would be to move from memory,
6231 don't use it. Likewise, if we need a secondary register
6235 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6236 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6238 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6239 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6240 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6244 #ifdef SECONDARY_MEMORY_NEEDED
6245 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6253 /* delete_output_reload is only invoked properly if old contains
6254 the original pseudo register. Since this is replaced with a
6255 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6256 find the pseudo in RELOAD_IN_REG. */
6258 && reload_override_in[j]
6259 && REG_P (rl->in_reg))
6266 else if (REG_P (oldequiv))
6267 oldequiv_reg = oldequiv;
6268 else if (GET_CODE (oldequiv) == SUBREG)
6269 oldequiv_reg = SUBREG_REG (oldequiv);
6271 /* If we are reloading from a register that was recently stored in
6272 with an output-reload, see if we can prove there was
6273 actually no need to store the old value in it. */
6275 if (optimize && REG_P (oldequiv)
6276 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6277 && spill_reg_store[REGNO (oldequiv)]
6279 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6280 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6282 delete_output_reload (insn, j, REGNO (oldequiv));
6284 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6285 then load RELOADREG from OLDEQUIV. Note that we cannot use
6286 gen_lowpart_common since it can do the wrong thing when
6287 RELOADREG has a multi-word mode. Note that RELOADREG
6288 must always be a REG here. */
6290 if (GET_MODE (reloadreg) != mode)
6291 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6292 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6293 oldequiv = SUBREG_REG (oldequiv);
6294 if (GET_MODE (oldequiv) != VOIDmode
6295 && mode != GET_MODE (oldequiv))
6296 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6298 /* Switch to the right place to emit the reload insns. */
6299 switch (rl->when_needed)
6302 where = &other_input_reload_insns;
6304 case RELOAD_FOR_INPUT:
6305 where = &input_reload_insns[rl->opnum];
6307 case RELOAD_FOR_INPUT_ADDRESS:
6308 where = &input_address_reload_insns[rl->opnum];
6310 case RELOAD_FOR_INPADDR_ADDRESS:
6311 where = &inpaddr_address_reload_insns[rl->opnum];
6313 case RELOAD_FOR_OUTPUT_ADDRESS:
6314 where = &output_address_reload_insns[rl->opnum];
6316 case RELOAD_FOR_OUTADDR_ADDRESS:
6317 where = &outaddr_address_reload_insns[rl->opnum];
6319 case RELOAD_FOR_OPERAND_ADDRESS:
6320 where = &operand_reload_insns;
6322 case RELOAD_FOR_OPADDR_ADDR:
6323 where = &other_operand_reload_insns;
6325 case RELOAD_FOR_OTHER_ADDRESS:
6326 where = &other_input_address_reload_insns;
6332 push_to_sequence (*where);
6334 /* Auto-increment addresses must be reloaded in a special way. */
6335 if (rl->out && ! rl->out_reg)
6337 /* We are not going to bother supporting the case where a
6338 incremented register can't be copied directly from
6339 OLDEQUIV since this seems highly unlikely. */
6340 gcc_assert (rl->secondary_in_reload < 0);
6342 if (reload_inherited[j])
6343 oldequiv = reloadreg;
6345 old = XEXP (rl->in_reg, 0);
6347 if (optimize && REG_P (oldequiv)
6348 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6349 && spill_reg_store[REGNO (oldequiv)]
6351 && (dead_or_set_p (insn,
6352 spill_reg_stored_to[REGNO (oldequiv)])
6353 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6355 delete_output_reload (insn, j, REGNO (oldequiv));
6357 /* Prevent normal processing of this reload. */
6359 /* Output a special code sequence for this case. */
6360 new_spill_reg_store[REGNO (reloadreg)]
6361 = inc_for_reload (reloadreg, oldequiv, rl->out,
6365 /* If we are reloading a pseudo-register that was set by the previous
6366 insn, see if we can get rid of that pseudo-register entirely
6367 by redirecting the previous insn into our reload register. */
6369 else if (optimize && REG_P (old)
6370 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6371 && dead_or_set_p (insn, old)
6372 /* This is unsafe if some other reload
6373 uses the same reg first. */
6374 && ! conflicts_with_override (reloadreg)
6375 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6376 rl->when_needed, old, rl->out, j, 0))
6378 rtx temp = PREV_INSN (insn);
6379 while (temp && NOTE_P (temp))
6380 temp = PREV_INSN (temp);
6382 && NONJUMP_INSN_P (temp)
6383 && GET_CODE (PATTERN (temp)) == SET
6384 && SET_DEST (PATTERN (temp)) == old
6385 /* Make sure we can access insn_operand_constraint. */
6386 && asm_noperands (PATTERN (temp)) < 0
6387 /* This is unsafe if operand occurs more than once in current
6388 insn. Perhaps some occurrences aren't reloaded. */
6389 && count_occurrences (PATTERN (insn), old, 0) == 1)
6391 rtx old = SET_DEST (PATTERN (temp));
6392 /* Store into the reload register instead of the pseudo. */
6393 SET_DEST (PATTERN (temp)) = reloadreg;
6395 /* Verify that resulting insn is valid. */
6396 extract_insn (temp);
6397 if (constrain_operands (1))
6399 /* If the previous insn is an output reload, the source is
6400 a reload register, and its spill_reg_store entry will
6401 contain the previous destination. This is now
6403 if (REG_P (SET_SRC (PATTERN (temp)))
6404 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6406 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6407 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6410 /* If these are the only uses of the pseudo reg,
6411 pretend for GDB it lives in the reload reg we used. */
6412 if (REG_N_DEATHS (REGNO (old)) == 1
6413 && REG_N_SETS (REGNO (old)) == 1)
6415 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6416 alter_reg (REGNO (old), -1);
6422 SET_DEST (PATTERN (temp)) = old;
6427 /* We can't do that, so output an insn to load RELOADREG. */
6429 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6430 /* If we have a secondary reload, pick up the secondary register
6431 and icode, if any. If OLDEQUIV and OLD are different or
6432 if this is an in-out reload, recompute whether or not we
6433 still need a secondary register and what the icode should
6434 be. If we still need a secondary register and the class or
6435 icode is different, go back to reloading from OLD if using
6436 OLDEQUIV means that we got the wrong type of register. We
6437 cannot have different class or icode due to an in-out reload
6438 because we don't make such reloads when both the input and
6439 output need secondary reload registers. */
6441 if (! special && rl->secondary_in_reload >= 0)
6443 rtx second_reload_reg = 0;
6444 int secondary_reload = rl->secondary_in_reload;
6445 rtx real_oldequiv = oldequiv;
6448 enum insn_code icode;
6450 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6451 and similarly for OLD.
6452 See comments in get_secondary_reload in reload.c. */
6453 /* If it is a pseudo that cannot be replaced with its
6454 equivalent MEM, we must fall back to reload_in, which
6455 will have all the necessary substitutions registered.
6456 Likewise for a pseudo that can't be replaced with its
6457 equivalent constant.
6459 Take extra care for subregs of such pseudos. Note that
6460 we cannot use reg_equiv_mem in this case because it is
6461 not in the right mode. */
6464 if (GET_CODE (tmp) == SUBREG)
6465 tmp = SUBREG_REG (tmp);
6467 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6468 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6469 || reg_equiv_constant[REGNO (tmp)] != 0))
6471 if (! reg_equiv_mem[REGNO (tmp)]
6472 || num_not_at_initial_offset
6473 || GET_CODE (oldequiv) == SUBREG)
6474 real_oldequiv = rl->in;
6476 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6480 if (GET_CODE (tmp) == SUBREG)
6481 tmp = SUBREG_REG (tmp);
6483 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6484 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6485 || reg_equiv_constant[REGNO (tmp)] != 0))
6487 if (! reg_equiv_mem[REGNO (tmp)]
6488 || num_not_at_initial_offset
6489 || GET_CODE (old) == SUBREG)
6492 real_old = reg_equiv_mem[REGNO (tmp)];
6495 second_reload_reg = rld[secondary_reload].reg_rtx;
6496 icode = rl->secondary_in_icode;
6498 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6499 || (rl->in != 0 && rl->out != 0))
6501 enum reg_class new_class
6502 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6503 mode, real_oldequiv);
6505 if (new_class == NO_REGS)
6506 second_reload_reg = 0;
6509 enum insn_code new_icode;
6510 enum machine_mode new_mode;
6512 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6513 REGNO (second_reload_reg)))
6514 oldequiv = old, real_oldequiv = real_old;
6517 new_icode = reload_in_optab[(int) mode];
6518 if (new_icode != CODE_FOR_nothing
6519 && ((insn_data[(int) new_icode].operand[0].predicate
6520 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6522 || (insn_data[(int) new_icode].operand[1].predicate
6523 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6524 (real_oldequiv, mode)))))
6525 new_icode = CODE_FOR_nothing;
6527 if (new_icode == CODE_FOR_nothing)
6530 new_mode = insn_data[(int) new_icode].operand[2].mode;
6532 if (GET_MODE (second_reload_reg) != new_mode)
6534 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6536 oldequiv = old, real_oldequiv = real_old;
6539 = reload_adjust_reg_for_mode (second_reload_reg,
6546 /* If we still need a secondary reload register, check
6547 to see if it is being used as a scratch or intermediate
6548 register and generate code appropriately. If we need
6549 a scratch register, use REAL_OLDEQUIV since the form of
6550 the insn may depend on the actual address if it is
6553 if (second_reload_reg)
6555 if (icode != CODE_FOR_nothing)
6557 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6558 second_reload_reg));
6563 /* See if we need a scratch register to load the
6564 intermediate register (a tertiary reload). */
6565 enum insn_code tertiary_icode
6566 = rld[secondary_reload].secondary_in_icode;
6568 if (tertiary_icode != CODE_FOR_nothing)
6570 rtx third_reload_reg
6571 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6573 emit_insn ((GEN_FCN (tertiary_icode)
6574 (second_reload_reg, real_oldequiv,
6575 third_reload_reg)));
6578 gen_reload (second_reload_reg, real_oldequiv,
6582 oldequiv = second_reload_reg;
6588 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6590 rtx real_oldequiv = oldequiv;
6592 if ((REG_P (oldequiv)
6593 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6594 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6595 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6596 || (GET_CODE (oldequiv) == SUBREG
6597 && REG_P (SUBREG_REG (oldequiv))
6598 && (REGNO (SUBREG_REG (oldequiv))
6599 >= FIRST_PSEUDO_REGISTER)
6600 && ((reg_equiv_memory_loc
6601 [REGNO (SUBREG_REG (oldequiv))] != 0)
6602 || (reg_equiv_constant
6603 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6604 || (CONSTANT_P (oldequiv)
6605 && (PREFERRED_RELOAD_CLASS (oldequiv,
6606 REGNO_REG_CLASS (REGNO (reloadreg)))
6608 real_oldequiv = rl->in;
6609 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6613 if (flag_non_call_exceptions)
6614 copy_eh_notes (insn, get_insns ());
6616 /* End this sequence. */
6617 *where = get_insns ();
6620 /* Update reload_override_in so that delete_address_reloads_1
6621 can see the actual register usage. */
6623 reload_override_in[j] = oldequiv;
6626 /* Generate insns to for the output reload RL, which is for the insn described
6627 by CHAIN and has the number J. */
6629 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6632 rtx reloadreg = rl->reg_rtx;
6633 rtx insn = chain->insn;
6636 enum machine_mode mode = GET_MODE (old);
6639 if (rl->when_needed == RELOAD_OTHER)
6642 push_to_sequence (output_reload_insns[rl->opnum]);
6644 /* Determine the mode to reload in.
6645 See comments above (for input reloading). */
6647 if (mode == VOIDmode)
6649 /* VOIDmode should never happen for an output. */
6650 if (asm_noperands (PATTERN (insn)) < 0)
6651 /* It's the compiler's fault. */
6652 fatal_insn ("VOIDmode on an output", insn);
6653 error_for_asm (insn, "output operand is constant in %<asm%>");
6654 /* Prevent crash--use something we know is valid. */
6656 old = gen_rtx_REG (mode, REGNO (reloadreg));
6659 if (GET_MODE (reloadreg) != mode)
6660 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6662 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6664 /* If we need two reload regs, set RELOADREG to the intermediate
6665 one, since it will be stored into OLD. We might need a secondary
6666 register only for an input reload, so check again here. */
6668 if (rl->secondary_out_reload >= 0)
6672 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6673 && reg_equiv_mem[REGNO (old)] != 0)
6674 real_old = reg_equiv_mem[REGNO (old)];
6676 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6680 rtx second_reloadreg = reloadreg;
6681 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6683 /* See if RELOADREG is to be used as a scratch register
6684 or as an intermediate register. */
6685 if (rl->secondary_out_icode != CODE_FOR_nothing)
6687 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6688 (real_old, second_reloadreg, reloadreg)));
6693 /* See if we need both a scratch and intermediate reload
6696 int secondary_reload = rl->secondary_out_reload;
6697 enum insn_code tertiary_icode
6698 = rld[secondary_reload].secondary_out_icode;
6700 if (GET_MODE (reloadreg) != mode)
6701 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6703 if (tertiary_icode != CODE_FOR_nothing)
6706 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6709 /* Copy primary reload reg to secondary reload reg.
6710 (Note that these have been swapped above, then
6711 secondary reload reg to OLD using our insn.) */
6713 /* If REAL_OLD is a paradoxical SUBREG, remove it
6714 and try to put the opposite SUBREG on
6716 if (GET_CODE (real_old) == SUBREG
6717 && (GET_MODE_SIZE (GET_MODE (real_old))
6718 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6719 && 0 != (tem = gen_lowpart_common
6720 (GET_MODE (SUBREG_REG (real_old)),
6722 real_old = SUBREG_REG (real_old), reloadreg = tem;
6724 gen_reload (reloadreg, second_reloadreg,
6725 rl->opnum, rl->when_needed);
6726 emit_insn ((GEN_FCN (tertiary_icode)
6727 (real_old, reloadreg, third_reloadreg)));
6732 /* Copy between the reload regs here and then to
6735 gen_reload (reloadreg, second_reloadreg,
6736 rl->opnum, rl->when_needed);
6742 /* Output the last reload insn. */
6747 /* Don't output the last reload if OLD is not the dest of
6748 INSN and is in the src and is clobbered by INSN. */
6749 if (! flag_expensive_optimizations
6751 || !(set = single_set (insn))
6752 || rtx_equal_p (old, SET_DEST (set))
6753 || !reg_mentioned_p (old, SET_SRC (set))
6754 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6755 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6756 gen_reload (old, reloadreg, rl->opnum,
6760 /* Look at all insns we emitted, just to be safe. */
6761 for (p = get_insns (); p; p = NEXT_INSN (p))
6764 rtx pat = PATTERN (p);
6766 /* If this output reload doesn't come from a spill reg,
6767 clear any memory of reloaded copies of the pseudo reg.
6768 If this output reload comes from a spill reg,
6769 reg_has_output_reload will make this do nothing. */
6770 note_stores (pat, forget_old_reloads_1, NULL);
6772 if (reg_mentioned_p (rl->reg_rtx, pat))
6774 rtx set = single_set (insn);
6775 if (reload_spill_index[j] < 0
6777 && SET_SRC (set) == rl->reg_rtx)
6779 int src = REGNO (SET_SRC (set));
6781 reload_spill_index[j] = src;
6782 SET_HARD_REG_BIT (reg_is_output_reload, src);
6783 if (find_regno_note (insn, REG_DEAD, src))
6784 SET_HARD_REG_BIT (reg_reloaded_died, src);
6786 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6788 int s = rl->secondary_out_reload;
6789 set = single_set (p);
6790 /* If this reload copies only to the secondary reload
6791 register, the secondary reload does the actual
6793 if (s >= 0 && set == NULL_RTX)
6794 /* We can't tell what function the secondary reload
6795 has and where the actual store to the pseudo is
6796 made; leave new_spill_reg_store alone. */
6799 && SET_SRC (set) == rl->reg_rtx
6800 && SET_DEST (set) == rld[s].reg_rtx)
6802 /* Usually the next instruction will be the
6803 secondary reload insn; if we can confirm
6804 that it is, setting new_spill_reg_store to
6805 that insn will allow an extra optimization. */
6806 rtx s_reg = rld[s].reg_rtx;
6807 rtx next = NEXT_INSN (p);
6808 rld[s].out = rl->out;
6809 rld[s].out_reg = rl->out_reg;
6810 set = single_set (next);
6811 if (set && SET_SRC (set) == s_reg
6812 && ! new_spill_reg_store[REGNO (s_reg)])
6814 SET_HARD_REG_BIT (reg_is_output_reload,
6816 new_spill_reg_store[REGNO (s_reg)] = next;
6820 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6825 if (rl->when_needed == RELOAD_OTHER)
6827 emit_insn (other_output_reload_insns[rl->opnum]);
6828 other_output_reload_insns[rl->opnum] = get_insns ();
6831 output_reload_insns[rl->opnum] = get_insns ();
6833 if (flag_non_call_exceptions)
6834 copy_eh_notes (insn, get_insns ());
6839 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6840 and has the number J. */
6842 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6844 rtx insn = chain->insn;
6845 rtx old = (rl->in && MEM_P (rl->in)
6846 ? rl->in_reg : rl->in);
6849 /* AUTO_INC reloads need to be handled even if inherited. We got an
6850 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6851 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6852 && ! rtx_equal_p (rl->reg_rtx, old)
6853 && rl->reg_rtx != 0)
6854 emit_input_reload_insns (chain, rld + j, old, j);
6856 /* When inheriting a wider reload, we have a MEM in rl->in,
6857 e.g. inheriting a SImode output reload for
6858 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6859 if (optimize && reload_inherited[j] && rl->in
6861 && MEM_P (rl->in_reg)
6862 && reload_spill_index[j] >= 0
6863 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6864 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6866 /* If we are reloading a register that was recently stored in with an
6867 output-reload, see if we can prove there was
6868 actually no need to store the old value in it. */
6871 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6872 that there may be multiple uses of the previous output reload.
6873 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6874 && rl->when_needed == RELOAD_FOR_INPUT
6875 && (reload_inherited[j] || reload_override_in[j])
6877 && REG_P (rl->reg_rtx)
6878 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6880 /* There doesn't seem to be any reason to restrict this to pseudos
6881 and doing so loses in the case where we are copying from a
6882 register of the wrong class. */
6883 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6884 >= FIRST_PSEUDO_REGISTER)
6886 /* The insn might have already some references to stackslots
6887 replaced by MEMs, while reload_out_reg still names the
6889 && (dead_or_set_p (insn,
6890 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6891 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6893 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6896 /* Do output reloading for reload RL, which is for the insn described by
6897 CHAIN and has the number J.
6898 ??? At some point we need to support handling output reloads of
6899 JUMP_INSNs or insns that set cc0. */
6901 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6904 rtx insn = chain->insn;
6905 /* If this is an output reload that stores something that is
6906 not loaded in this same reload, see if we can eliminate a previous
6908 rtx pseudo = rl->out_reg;
6913 && ! rtx_equal_p (rl->in_reg, pseudo)
6914 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6915 && reg_last_reload_reg[REGNO (pseudo)])
6917 int pseudo_no = REGNO (pseudo);
6918 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6920 /* We don't need to test full validity of last_regno for
6921 inherit here; we only want to know if the store actually
6922 matches the pseudo. */
6923 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6924 && reg_reloaded_contents[last_regno] == pseudo_no
6925 && spill_reg_store[last_regno]
6926 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6927 delete_output_reload (insn, j, last_regno);
6932 || rl->reg_rtx == old
6933 || rl->reg_rtx == 0)
6936 /* An output operand that dies right away does need a reload,
6937 but need not be copied from it. Show the new location in the
6939 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6940 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6942 XEXP (note, 0) = rl->reg_rtx;
6945 /* Likewise for a SUBREG of an operand that dies. */
6946 else if (GET_CODE (old) == SUBREG
6947 && REG_P (SUBREG_REG (old))
6948 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6951 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6955 else if (GET_CODE (old) == SCRATCH)
6956 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6957 but we don't want to make an output reload. */
6960 /* If is a JUMP_INSN, we can't support output reloads yet. */
6961 gcc_assert (!JUMP_P (insn));
6963 emit_output_reload_insns (chain, rld + j, j);
6966 /* Reload number R reloads from or to a group of hard registers starting at
6967 register REGNO. Return true if it can be treated for inheritance purposes
6968 like a group of reloads, each one reloading a single hard register.
6969 The caller has already checked that the spill register and REGNO use
6970 the same number of registers to store the reload value. */
6973 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6975 #ifdef CANNOT_CHANGE_MODE_CLASS
6976 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6977 GET_MODE (rld[r].reg_rtx),
6978 reg_raw_mode[reload_spill_index[r]])
6979 && !REG_CANNOT_CHANGE_MODE_P (regno,
6980 GET_MODE (rld[r].reg_rtx),
6981 reg_raw_mode[regno]));
6987 /* Output insns to reload values in and out of the chosen reload regs. */
6990 emit_reload_insns (struct insn_chain *chain)
6992 rtx insn = chain->insn;
6996 CLEAR_HARD_REG_SET (reg_reloaded_died);
6998 for (j = 0; j < reload_n_operands; j++)
6999 input_reload_insns[j] = input_address_reload_insns[j]
7000 = inpaddr_address_reload_insns[j]
7001 = output_reload_insns[j] = output_address_reload_insns[j]
7002 = outaddr_address_reload_insns[j]
7003 = other_output_reload_insns[j] = 0;
7004 other_input_address_reload_insns = 0;
7005 other_input_reload_insns = 0;
7006 operand_reload_insns = 0;
7007 other_operand_reload_insns = 0;
7009 /* Dump reloads into the dump file. */
7012 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7013 debug_reload_to_stream (dump_file);
7016 /* Now output the instructions to copy the data into and out of the
7017 reload registers. Do these in the order that the reloads were reported,
7018 since reloads of base and index registers precede reloads of operands
7019 and the operands may need the base and index registers reloaded. */
7021 for (j = 0; j < n_reloads; j++)
7024 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7025 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7027 do_input_reload (chain, rld + j, j);
7028 do_output_reload (chain, rld + j, j);
7031 /* Now write all the insns we made for reloads in the order expected by
7032 the allocation functions. Prior to the insn being reloaded, we write
7033 the following reloads:
7035 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7037 RELOAD_OTHER reloads.
7039 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7040 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7041 RELOAD_FOR_INPUT reload for the operand.
7043 RELOAD_FOR_OPADDR_ADDRS reloads.
7045 RELOAD_FOR_OPERAND_ADDRESS reloads.
7047 After the insn being reloaded, we write the following:
7049 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7050 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7051 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7052 reloads for the operand. The RELOAD_OTHER output reloads are
7053 output in descending order by reload number. */
7055 emit_insn_before (other_input_address_reload_insns, insn);
7056 emit_insn_before (other_input_reload_insns, insn);
7058 for (j = 0; j < reload_n_operands; j++)
7060 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7061 emit_insn_before (input_address_reload_insns[j], insn);
7062 emit_insn_before (input_reload_insns[j], insn);
7065 emit_insn_before (other_operand_reload_insns, insn);
7066 emit_insn_before (operand_reload_insns, insn);
7068 for (j = 0; j < reload_n_operands; j++)
7070 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7071 x = emit_insn_after (output_address_reload_insns[j], x);
7072 x = emit_insn_after (output_reload_insns[j], x);
7073 emit_insn_after (other_output_reload_insns[j], x);
7076 /* For all the spill regs newly reloaded in this instruction,
7077 record what they were reloaded from, so subsequent instructions
7078 can inherit the reloads.
7080 Update spill_reg_store for the reloads of this insn.
7081 Copy the elements that were updated in the loop above. */
7083 for (j = 0; j < n_reloads; j++)
7085 int r = reload_order[j];
7086 int i = reload_spill_index[r];
7088 /* If this is a non-inherited input reload from a pseudo, we must
7089 clear any memory of a previous store to the same pseudo. Only do
7090 something if there will not be an output reload for the pseudo
7092 if (rld[r].in_reg != 0
7093 && ! (reload_inherited[r] || reload_override_in[r]))
7095 rtx reg = rld[r].in_reg;
7097 if (GET_CODE (reg) == SUBREG)
7098 reg = SUBREG_REG (reg);
7101 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7102 && ! reg_has_output_reload[REGNO (reg)])
7104 int nregno = REGNO (reg);
7106 if (reg_last_reload_reg[nregno])
7108 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7110 if (reg_reloaded_contents[last_regno] == nregno)
7111 spill_reg_store[last_regno] = 0;
7116 /* I is nonneg if this reload used a register.
7117 If rld[r].reg_rtx is 0, this is an optional reload
7118 that we opted to ignore. */
7120 if (i >= 0 && rld[r].reg_rtx != 0)
7122 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7124 int part_reaches_end = 0;
7125 int all_reaches_end = 1;
7127 /* For a multi register reload, we need to check if all or part
7128 of the value lives to the end. */
7129 for (k = 0; k < nr; k++)
7131 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7132 rld[r].when_needed))
7133 part_reaches_end = 1;
7135 all_reaches_end = 0;
7138 /* Ignore reloads that don't reach the end of the insn in
7140 if (all_reaches_end)
7142 /* First, clear out memory of what used to be in this spill reg.
7143 If consecutive registers are used, clear them all. */
7145 for (k = 0; k < nr; k++)
7147 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7148 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7151 /* Maybe the spill reg contains a copy of reload_out. */
7153 && (REG_P (rld[r].out)
7157 || REG_P (rld[r].out_reg)))
7159 rtx out = (REG_P (rld[r].out)
7163 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7164 int nregno = REGNO (out);
7165 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7166 : hard_regno_nregs[nregno]
7167 [GET_MODE (rld[r].reg_rtx)]);
7170 spill_reg_store[i] = new_spill_reg_store[i];
7171 spill_reg_stored_to[i] = out;
7172 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7174 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7176 && inherit_piecemeal_p (r, nregno));
7178 /* If NREGNO is a hard register, it may occupy more than
7179 one register. If it does, say what is in the
7180 rest of the registers assuming that both registers
7181 agree on how many words the object takes. If not,
7182 invalidate the subsequent registers. */
7184 if (nregno < FIRST_PSEUDO_REGISTER)
7185 for (k = 1; k < nnr; k++)
7186 reg_last_reload_reg[nregno + k]
7188 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7191 /* Now do the inverse operation. */
7192 for (k = 0; k < nr; k++)
7194 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7195 reg_reloaded_contents[i + k]
7196 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7199 reg_reloaded_insn[i + k] = insn;
7200 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7201 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7202 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7206 /* Maybe the spill reg contains a copy of reload_in. Only do
7207 something if there will not be an output reload for
7208 the register being reloaded. */
7209 else if (rld[r].out_reg == 0
7211 && ((REG_P (rld[r].in)
7212 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7213 && ! reg_has_output_reload[REGNO (rld[r].in)])
7214 || (REG_P (rld[r].in_reg)
7215 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7216 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7223 if (REG_P (rld[r].in)
7224 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7226 else if (REG_P (rld[r].in_reg))
7229 in = XEXP (rld[r].in_reg, 0);
7230 nregno = REGNO (in);
7232 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7233 : hard_regno_nregs[nregno]
7234 [GET_MODE (rld[r].reg_rtx)]);
7236 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7238 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7240 && inherit_piecemeal_p (r, nregno));
7242 if (nregno < FIRST_PSEUDO_REGISTER)
7243 for (k = 1; k < nnr; k++)
7244 reg_last_reload_reg[nregno + k]
7246 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7249 /* Unless we inherited this reload, show we haven't
7250 recently done a store.
7251 Previous stores of inherited auto_inc expressions
7252 also have to be discarded. */
7253 if (! reload_inherited[r]
7254 || (rld[r].out && ! rld[r].out_reg))
7255 spill_reg_store[i] = 0;
7257 for (k = 0; k < nr; k++)
7259 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7260 reg_reloaded_contents[i + k]
7261 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7264 reg_reloaded_insn[i + k] = insn;
7265 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7266 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7267 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7272 /* However, if part of the reload reaches the end, then we must
7273 invalidate the old info for the part that survives to the end. */
7274 else if (part_reaches_end)
7276 for (k = 0; k < nr; k++)
7277 if (reload_reg_reaches_end_p (i + k,
7279 rld[r].when_needed))
7280 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7284 /* The following if-statement was #if 0'd in 1.34 (or before...).
7285 It's reenabled in 1.35 because supposedly nothing else
7286 deals with this problem. */
7288 /* If a register gets output-reloaded from a non-spill register,
7289 that invalidates any previous reloaded copy of it.
7290 But forget_old_reloads_1 won't get to see it, because
7291 it thinks only about the original insn. So invalidate it here. */
7292 if (i < 0 && rld[r].out != 0
7293 && (REG_P (rld[r].out)
7294 || (MEM_P (rld[r].out)
7295 && REG_P (rld[r].out_reg))))
7297 rtx out = (REG_P (rld[r].out)
7298 ? rld[r].out : rld[r].out_reg);
7299 int nregno = REGNO (out);
7300 if (nregno >= FIRST_PSEUDO_REGISTER)
7302 rtx src_reg, store_insn = NULL_RTX;
7304 reg_last_reload_reg[nregno] = 0;
7306 /* If we can find a hard register that is stored, record
7307 the storing insn so that we may delete this insn with
7308 delete_output_reload. */
7309 src_reg = rld[r].reg_rtx;
7311 /* If this is an optional reload, try to find the source reg
7312 from an input reload. */
7315 rtx set = single_set (insn);
7316 if (set && SET_DEST (set) == rld[r].out)
7320 src_reg = SET_SRC (set);
7322 for (k = 0; k < n_reloads; k++)
7324 if (rld[k].in == src_reg)
7326 src_reg = rld[k].reg_rtx;
7333 store_insn = new_spill_reg_store[REGNO (src_reg)];
7334 if (src_reg && REG_P (src_reg)
7335 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7337 int src_regno = REGNO (src_reg);
7338 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7339 /* The place where to find a death note varies with
7340 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7341 necessarily checked exactly in the code that moves
7342 notes, so just check both locations. */
7343 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7344 if (! note && store_insn)
7345 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7348 spill_reg_store[src_regno + nr] = store_insn;
7349 spill_reg_stored_to[src_regno + nr] = out;
7350 reg_reloaded_contents[src_regno + nr] = nregno;
7351 reg_reloaded_insn[src_regno + nr] = store_insn;
7352 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7353 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7354 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7355 GET_MODE (src_reg)))
7356 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7358 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7360 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7362 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7364 reg_last_reload_reg[nregno] = src_reg;
7365 /* We have to set reg_has_output_reload here, or else
7366 forget_old_reloads_1 will clear reg_last_reload_reg
7368 reg_has_output_reload[nregno] = 1;
7373 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7375 while (num_regs-- > 0)
7376 reg_last_reload_reg[nregno + num_regs] = 0;
7380 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7383 /* Emit code to perform a reload from IN (which may be a reload register) to
7384 OUT (which may also be a reload register). IN or OUT is from operand
7385 OPNUM with reload type TYPE.
7387 Returns first insn emitted. */
7390 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7392 rtx last = get_last_insn ();
7395 /* If IN is a paradoxical SUBREG, remove it and try to put the
7396 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7397 if (GET_CODE (in) == SUBREG
7398 && (GET_MODE_SIZE (GET_MODE (in))
7399 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7400 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7401 in = SUBREG_REG (in), out = tem;
7402 else if (GET_CODE (out) == SUBREG
7403 && (GET_MODE_SIZE (GET_MODE (out))
7404 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7405 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7406 out = SUBREG_REG (out), in = tem;
7408 /* How to do this reload can get quite tricky. Normally, we are being
7409 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7410 register that didn't get a hard register. In that case we can just
7411 call emit_move_insn.
7413 We can also be asked to reload a PLUS that adds a register or a MEM to
7414 another register, constant or MEM. This can occur during frame pointer
7415 elimination and while reloading addresses. This case is handled by
7416 trying to emit a single insn to perform the add. If it is not valid,
7417 we use a two insn sequence.
7419 Finally, we could be called to handle an 'o' constraint by putting
7420 an address into a register. In that case, we first try to do this
7421 with a named pattern of "reload_load_address". If no such pattern
7422 exists, we just emit a SET insn and hope for the best (it will normally
7423 be valid on machines that use 'o').
7425 This entire process is made complex because reload will never
7426 process the insns we generate here and so we must ensure that
7427 they will fit their constraints and also by the fact that parts of
7428 IN might be being reloaded separately and replaced with spill registers.
7429 Because of this, we are, in some sense, just guessing the right approach
7430 here. The one listed above seems to work.
7432 ??? At some point, this whole thing needs to be rethought. */
7434 if (GET_CODE (in) == PLUS
7435 && (REG_P (XEXP (in, 0))
7436 || GET_CODE (XEXP (in, 0)) == SUBREG
7437 || MEM_P (XEXP (in, 0)))
7438 && (REG_P (XEXP (in, 1))
7439 || GET_CODE (XEXP (in, 1)) == SUBREG
7440 || CONSTANT_P (XEXP (in, 1))
7441 || MEM_P (XEXP (in, 1))))
7443 /* We need to compute the sum of a register or a MEM and another
7444 register, constant, or MEM, and put it into the reload
7445 register. The best possible way of doing this is if the machine
7446 has a three-operand ADD insn that accepts the required operands.
7448 The simplest approach is to try to generate such an insn and see if it
7449 is recognized and matches its constraints. If so, it can be used.
7451 It might be better not to actually emit the insn unless it is valid,
7452 but we need to pass the insn as an operand to `recog' and
7453 `extract_insn' and it is simpler to emit and then delete the insn if
7454 not valid than to dummy things up. */
7456 rtx op0, op1, tem, insn;
7459 op0 = find_replacement (&XEXP (in, 0));
7460 op1 = find_replacement (&XEXP (in, 1));
7462 /* Since constraint checking is strict, commutativity won't be
7463 checked, so we need to do that here to avoid spurious failure
7464 if the add instruction is two-address and the second operand
7465 of the add is the same as the reload reg, which is frequently
7466 the case. If the insn would be A = B + A, rearrange it so
7467 it will be A = A + B as constrain_operands expects. */
7469 if (REG_P (XEXP (in, 1))
7470 && REGNO (out) == REGNO (XEXP (in, 1)))
7471 tem = op0, op0 = op1, op1 = tem;
7473 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7474 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7476 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7477 code = recog_memoized (insn);
7481 extract_insn (insn);
7482 /* We want constrain operands to treat this insn strictly in
7483 its validity determination, i.e., the way it would after reload
7485 if (constrain_operands (1))
7489 delete_insns_since (last);
7491 /* If that failed, we must use a conservative two-insn sequence.
7493 Use a move to copy one operand into the reload register. Prefer
7494 to reload a constant, MEM or pseudo since the move patterns can
7495 handle an arbitrary operand. If OP1 is not a constant, MEM or
7496 pseudo and OP1 is not a valid operand for an add instruction, then
7499 After reloading one of the operands into the reload register, add
7500 the reload register to the output register.
7502 If there is another way to do this for a specific machine, a
7503 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7506 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7508 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7510 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7511 || (code != CODE_FOR_nothing
7512 && ! ((*insn_data[code].operand[2].predicate)
7513 (op1, insn_data[code].operand[2].mode))))
7514 tem = op0, op0 = op1, op1 = tem;
7516 gen_reload (out, op0, opnum, type);
7518 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7519 This fixes a problem on the 32K where the stack pointer cannot
7520 be used as an operand of an add insn. */
7522 if (rtx_equal_p (op0, op1))
7525 insn = emit_insn (gen_add2_insn (out, op1));
7527 /* If that failed, copy the address register to the reload register.
7528 Then add the constant to the reload register. */
7530 code = recog_memoized (insn);
7534 extract_insn (insn);
7535 /* We want constrain operands to treat this insn strictly in
7536 its validity determination, i.e., the way it would after reload
7538 if (constrain_operands (1))
7540 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7542 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7547 delete_insns_since (last);
7549 gen_reload (out, op1, opnum, type);
7550 insn = emit_insn (gen_add2_insn (out, op0));
7551 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7554 #ifdef SECONDARY_MEMORY_NEEDED
7555 /* If we need a memory location to do the move, do it that way. */
7556 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7557 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7558 && (REG_P (out) || GET_CODE (out) == SUBREG)
7559 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7560 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7561 REGNO_REG_CLASS (reg_or_subregno (out)),
7564 /* Get the memory to use and rewrite both registers to its mode. */
7565 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7567 if (GET_MODE (loc) != GET_MODE (out))
7568 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7570 if (GET_MODE (loc) != GET_MODE (in))
7571 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7573 gen_reload (loc, in, opnum, type);
7574 gen_reload (out, loc, opnum, type);
7578 /* If IN is a simple operand, use gen_move_insn. */
7579 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7580 emit_insn (gen_move_insn (out, in));
7582 #ifdef HAVE_reload_load_address
7583 else if (HAVE_reload_load_address)
7584 emit_insn (gen_reload_load_address (out, in));
7587 /* Otherwise, just write (set OUT IN) and hope for the best. */
7589 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7591 /* Return the first insn emitted.
7592 We can not just return get_last_insn, because there may have
7593 been multiple instructions emitted. Also note that gen_move_insn may
7594 emit more than one insn itself, so we can not assume that there is one
7595 insn emitted per emit_insn_before call. */
7597 return last ? NEXT_INSN (last) : get_insns ();
7600 /* Delete a previously made output-reload whose result we now believe
7601 is not needed. First we double-check.
7603 INSN is the insn now being processed.
7604 LAST_RELOAD_REG is the hard register number for which we want to delete
7605 the last output reload.
7606 J is the reload-number that originally used REG. The caller has made
7607 certain that reload J doesn't use REG any longer for input. */
7610 delete_output_reload (rtx insn, int j, int last_reload_reg)
7612 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7613 rtx reg = spill_reg_stored_to[last_reload_reg];
7616 int n_inherited = 0;
7620 /* It is possible that this reload has been only used to set another reload
7621 we eliminated earlier and thus deleted this instruction too. */
7622 if (INSN_DELETED_P (output_reload_insn))
7625 /* Get the raw pseudo-register referred to. */
7627 while (GET_CODE (reg) == SUBREG)
7628 reg = SUBREG_REG (reg);
7629 substed = reg_equiv_memory_loc[REGNO (reg)];
7631 /* This is unsafe if the operand occurs more often in the current
7632 insn than it is inherited. */
7633 for (k = n_reloads - 1; k >= 0; k--)
7635 rtx reg2 = rld[k].in;
7638 if (MEM_P (reg2) || reload_override_in[k])
7639 reg2 = rld[k].in_reg;
7641 if (rld[k].out && ! rld[k].out_reg)
7642 reg2 = XEXP (rld[k].in_reg, 0);
7644 while (GET_CODE (reg2) == SUBREG)
7645 reg2 = SUBREG_REG (reg2);
7646 if (rtx_equal_p (reg2, reg))
7648 if (reload_inherited[k] || reload_override_in[k] || k == j)
7651 reg2 = rld[k].out_reg;
7654 while (GET_CODE (reg2) == SUBREG)
7655 reg2 = XEXP (reg2, 0);
7656 if (rtx_equal_p (reg2, reg))
7663 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7665 n_occurrences += count_occurrences (PATTERN (insn),
7666 eliminate_regs (substed, 0,
7668 if (n_occurrences > n_inherited)
7671 /* If the pseudo-reg we are reloading is no longer referenced
7672 anywhere between the store into it and here,
7673 and we're within the same basic block, then the value can only
7674 pass through the reload reg and end up here.
7675 Otherwise, give up--return. */
7676 for (i1 = NEXT_INSN (output_reload_insn);
7677 i1 != insn; i1 = NEXT_INSN (i1))
7679 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7681 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7682 && reg_mentioned_p (reg, PATTERN (i1)))
7684 /* If this is USE in front of INSN, we only have to check that
7685 there are no more references than accounted for by inheritance. */
7686 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7688 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7689 i1 = NEXT_INSN (i1);
7691 if (n_occurrences <= n_inherited && i1 == insn)
7697 /* We will be deleting the insn. Remove the spill reg information. */
7698 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7700 spill_reg_store[last_reload_reg + k] = 0;
7701 spill_reg_stored_to[last_reload_reg + k] = 0;
7704 /* The caller has already checked that REG dies or is set in INSN.
7705 It has also checked that we are optimizing, and thus some
7706 inaccuracies in the debugging information are acceptable.
7707 So we could just delete output_reload_insn. But in some cases
7708 we can improve the debugging information without sacrificing
7709 optimization - maybe even improving the code: See if the pseudo
7710 reg has been completely replaced with reload regs. If so, delete
7711 the store insn and forget we had a stack slot for the pseudo. */
7712 if (rld[j].out != rld[j].in
7713 && REG_N_DEATHS (REGNO (reg)) == 1
7714 && REG_N_SETS (REGNO (reg)) == 1
7715 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7716 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7720 /* We know that it was used only between here and the beginning of
7721 the current basic block. (We also know that the last use before
7722 INSN was the output reload we are thinking of deleting, but never
7723 mind that.) Search that range; see if any ref remains. */
7724 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7726 rtx set = single_set (i2);
7728 /* Uses which just store in the pseudo don't count,
7729 since if they are the only uses, they are dead. */
7730 if (set != 0 && SET_DEST (set) == reg)
7735 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7736 && reg_mentioned_p (reg, PATTERN (i2)))
7738 /* Some other ref remains; just delete the output reload we
7740 delete_address_reloads (output_reload_insn, insn);
7741 delete_insn (output_reload_insn);
7746 /* Delete the now-dead stores into this pseudo. Note that this
7747 loop also takes care of deleting output_reload_insn. */
7748 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7750 rtx set = single_set (i2);
7752 if (set != 0 && SET_DEST (set) == reg)
7754 delete_address_reloads (i2, insn);
7762 /* For the debugging info, say the pseudo lives in this reload reg. */
7763 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7764 alter_reg (REGNO (reg), -1);
7768 delete_address_reloads (output_reload_insn, insn);
7769 delete_insn (output_reload_insn);
7773 /* We are going to delete DEAD_INSN. Recursively delete loads of
7774 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7775 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7777 delete_address_reloads (rtx dead_insn, rtx current_insn)
7779 rtx set = single_set (dead_insn);
7780 rtx set2, dst, prev, next;
7783 rtx dst = SET_DEST (set);
7785 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7787 /* If we deleted the store from a reloaded post_{in,de}c expression,
7788 we can delete the matching adds. */
7789 prev = PREV_INSN (dead_insn);
7790 next = NEXT_INSN (dead_insn);
7791 if (! prev || ! next)
7793 set = single_set (next);
7794 set2 = single_set (prev);
7796 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7797 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7798 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7800 dst = SET_DEST (set);
7801 if (! rtx_equal_p (dst, SET_DEST (set2))
7802 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7803 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7804 || (INTVAL (XEXP (SET_SRC (set), 1))
7805 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7807 delete_related_insns (prev);
7808 delete_related_insns (next);
7811 /* Subfunction of delete_address_reloads: process registers found in X. */
7813 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7815 rtx prev, set, dst, i2;
7817 enum rtx_code code = GET_CODE (x);
7821 const char *fmt = GET_RTX_FORMAT (code);
7822 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7825 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7826 else if (fmt[i] == 'E')
7828 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7829 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7836 if (spill_reg_order[REGNO (x)] < 0)
7839 /* Scan backwards for the insn that sets x. This might be a way back due
7841 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7843 code = GET_CODE (prev);
7844 if (code == CODE_LABEL || code == JUMP_INSN)
7848 if (reg_set_p (x, PATTERN (prev)))
7850 if (reg_referenced_p (x, PATTERN (prev)))
7853 if (! prev || INSN_UID (prev) < reload_first_uid)
7855 /* Check that PREV only sets the reload register. */
7856 set = single_set (prev);
7859 dst = SET_DEST (set);
7861 || ! rtx_equal_p (dst, x))
7863 if (! reg_set_p (dst, PATTERN (dead_insn)))
7865 /* Check if DST was used in a later insn -
7866 it might have been inherited. */
7867 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7873 if (reg_referenced_p (dst, PATTERN (i2)))
7875 /* If there is a reference to the register in the current insn,
7876 it might be loaded in a non-inherited reload. If no other
7877 reload uses it, that means the register is set before
7879 if (i2 == current_insn)
7881 for (j = n_reloads - 1; j >= 0; j--)
7882 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7883 || reload_override_in[j] == dst)
7885 for (j = n_reloads - 1; j >= 0; j--)
7886 if (rld[j].in && rld[j].reg_rtx == dst)
7895 /* If DST is still live at CURRENT_INSN, check if it is used for
7896 any reload. Note that even if CURRENT_INSN sets DST, we still
7897 have to check the reloads. */
7898 if (i2 == current_insn)
7900 for (j = n_reloads - 1; j >= 0; j--)
7901 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7902 || reload_override_in[j] == dst)
7904 /* ??? We can't finish the loop here, because dst might be
7905 allocated to a pseudo in this block if no reload in this
7906 block needs any of the classes containing DST - see
7907 spill_hard_reg. There is no easy way to tell this, so we
7908 have to scan till the end of the basic block. */
7910 if (reg_set_p (dst, PATTERN (i2)))
7914 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7915 reg_reloaded_contents[REGNO (dst)] = -1;
7919 /* Output reload-insns to reload VALUE into RELOADREG.
7920 VALUE is an autoincrement or autodecrement RTX whose operand
7921 is a register or memory location;
7922 so reloading involves incrementing that location.
7923 IN is either identical to VALUE, or some cheaper place to reload from.
7925 INC_AMOUNT is the number to increment or decrement by (always positive).
7926 This cannot be deduced from VALUE.
7928 Return the instruction that stores into RELOADREG. */
7931 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7933 /* REG or MEM to be copied and incremented. */
7934 rtx incloc = XEXP (value, 0);
7935 /* Nonzero if increment after copying. */
7936 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7942 rtx real_in = in == value ? XEXP (in, 0) : in;
7944 /* No hard register is equivalent to this register after
7945 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7946 we could inc/dec that register as well (maybe even using it for
7947 the source), but I'm not sure it's worth worrying about. */
7949 reg_last_reload_reg[REGNO (incloc)] = 0;
7951 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7952 inc_amount = -inc_amount;
7954 inc = GEN_INT (inc_amount);
7956 /* If this is post-increment, first copy the location to the reload reg. */
7957 if (post && real_in != reloadreg)
7958 emit_insn (gen_move_insn (reloadreg, real_in));
7962 /* See if we can directly increment INCLOC. Use a method similar to
7963 that in gen_reload. */
7965 last = get_last_insn ();
7966 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7967 gen_rtx_PLUS (GET_MODE (incloc),
7970 code = recog_memoized (add_insn);
7973 extract_insn (add_insn);
7974 if (constrain_operands (1))
7976 /* If this is a pre-increment and we have incremented the value
7977 where it lives, copy the incremented value to RELOADREG to
7978 be used as an address. */
7981 emit_insn (gen_move_insn (reloadreg, incloc));
7986 delete_insns_since (last);
7989 /* If couldn't do the increment directly, must increment in RELOADREG.
7990 The way we do this depends on whether this is pre- or post-increment.
7991 For pre-increment, copy INCLOC to the reload register, increment it
7992 there, then save back. */
7996 if (in != reloadreg)
7997 emit_insn (gen_move_insn (reloadreg, real_in));
7998 emit_insn (gen_add2_insn (reloadreg, inc));
7999 store = emit_insn (gen_move_insn (incloc, reloadreg));
8004 Because this might be a jump insn or a compare, and because RELOADREG
8005 may not be available after the insn in an input reload, we must do
8006 the incrementation before the insn being reloaded for.
8008 We have already copied IN to RELOADREG. Increment the copy in
8009 RELOADREG, save that back, then decrement RELOADREG so it has
8010 the original value. */
8012 emit_insn (gen_add2_insn (reloadreg, inc));
8013 store = emit_insn (gen_move_insn (incloc, reloadreg));
8014 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8022 add_auto_inc_notes (rtx insn, rtx x)
8024 enum rtx_code code = GET_CODE (x);
8028 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8031 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8035 /* Scan all the operand sub-expressions. */
8036 fmt = GET_RTX_FORMAT (code);
8037 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8040 add_auto_inc_notes (insn, XEXP (x, i));
8041 else if (fmt[i] == 'E')
8042 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8043 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8048 /* Copy EH notes from an insn to its reloads. */
8050 copy_eh_notes (rtx insn, rtx x)
8052 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8055 for (; x != 0; x = NEXT_INSN (x))
8057 if (may_trap_p (PATTERN (x)))
8059 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8065 /* This is used by reload pass, that does emit some instructions after
8066 abnormal calls moving basic block end, but in fact it wants to emit
8067 them on the edge. Looks for abnormal call edges, find backward the
8068 proper call and fix the damage.
8070 Similar handle instructions throwing exceptions internally. */
8072 fixup_abnormal_edges (void)
8074 bool inserted = false;
8082 /* Look for cases we are interested in - calls or instructions causing
8084 FOR_EACH_EDGE (e, ei, bb->succs)
8086 if (e->flags & EDGE_ABNORMAL_CALL)
8088 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8089 == (EDGE_ABNORMAL | EDGE_EH))
8092 if (e && !CALL_P (BB_END (bb))
8093 && !can_throw_internal (BB_END (bb)))
8095 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8097 FOR_EACH_EDGE (e, ei, bb->succs)
8098 if (e->flags & EDGE_FALLTHRU)
8100 /* Get past the new insns generated. Allow notes, as the insns may
8101 be already deleted. */
8102 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8103 && !can_throw_internal (insn)
8104 && insn != BB_HEAD (bb))
8105 insn = PREV_INSN (insn);
8106 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8109 insn = NEXT_INSN (insn);
8110 while (insn && insn != stop)
8112 next = NEXT_INSN (insn);
8117 /* Sometimes there's still the return value USE.
8118 If it's placed after a trapping call (i.e. that
8119 call is the last insn anyway), we have no fallthru
8120 edge. Simply delete this use and don't try to insert
8121 on the non-existent edge. */
8122 if (GET_CODE (PATTERN (insn)) != USE)
8124 /* We're not deleting it, we're moving it. */
8125 INSN_DELETED_P (insn) = 0;
8126 PREV_INSN (insn) = NULL_RTX;
8127 NEXT_INSN (insn) = NULL_RTX;
8129 insert_insn_on_edge (insn, e);
8136 /* We've possibly turned single trapping insn into multiple ones. */
8137 if (flag_non_call_exceptions)
8140 blocks = sbitmap_alloc (last_basic_block);
8141 sbitmap_ones (blocks);
8142 find_many_sub_basic_blocks (blocks);
8145 commit_edge_insertions ();
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