1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 static struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 static char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 static char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static void verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void scan_paradoxical_subregs (rtx);
394 static void count_pseudo (int);
395 static void order_regs_for_reload (struct insn_chain *);
396 static void reload_as_needed (int);
397 static void forget_old_reloads_1 (rtx, rtx, void *);
398 static int reload_reg_class_lower (const void *, const void *);
399 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
401 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
403 static int reload_reg_free_p (unsigned int, int, enum reload_type);
404 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
406 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
408 static int function_invariant_p (rtx);
409 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
410 static int allocate_reload_reg (struct insn_chain *, int, int);
411 static int conflicts_with_override (rtx);
412 static void failed_reload (rtx, int);
413 static int set_reload_reg (int, int);
414 static void choose_reload_regs_init (struct insn_chain *, rtx *);
415 static void choose_reload_regs (struct insn_chain *);
416 static void merge_assigned_reloads (rtx);
417 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
419 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
421 static void do_input_reload (struct insn_chain *, struct reload *, int);
422 static void do_output_reload (struct insn_chain *, struct reload *, int);
423 static bool inherit_piecemeal_p (int, int);
424 static void emit_reload_insns (struct insn_chain *);
425 static void delete_output_reload (rtx, int, int);
426 static void delete_address_reloads (rtx, rtx);
427 static void delete_address_reloads_1 (rtx, rtx, rtx);
428 static rtx inc_for_reload (rtx, rtx, rtx, int);
430 static void add_auto_inc_notes (rtx, rtx);
432 static void copy_eh_notes (rtx, rtx);
433 static int reloads_conflict (int, int);
434 static rtx gen_reload (rtx, rtx, int, enum reload_type);
436 /* Initialize the reload pass once per compilation. */
443 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
444 Set spill_indirect_levels to the number of levels such addressing is
445 permitted, zero if it is not permitted at all. */
448 = gen_rtx_MEM (Pmode,
451 LAST_VIRTUAL_REGISTER + 1),
453 spill_indirect_levels = 0;
455 while (memory_address_p (QImode, tem))
457 spill_indirect_levels++;
458 tem = gen_rtx_MEM (Pmode, tem);
461 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
463 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
464 indirect_symref_ok = memory_address_p (QImode, tem);
466 /* See if reg+reg is a valid (and offsettable) address. */
468 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
470 tem = gen_rtx_PLUS (Pmode,
471 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
472 gen_rtx_REG (Pmode, i));
474 /* This way, we make sure that reg+reg is an offsettable address. */
475 tem = plus_constant (tem, 4);
477 if (memory_address_p (QImode, tem))
479 double_reg_address_ok = 1;
484 /* Initialize obstack for our rtl allocation. */
485 gcc_obstack_init (&reload_obstack);
486 reload_startobj = obstack_alloc (&reload_obstack, 0);
488 INIT_REG_SET (&spilled_pseudos);
489 INIT_REG_SET (&pseudos_counted);
490 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
493 /* List of insn chains that are currently unused. */
494 static struct insn_chain *unused_insn_chains = 0;
496 /* Allocate an empty insn_chain structure. */
498 new_insn_chain (void)
500 struct insn_chain *c;
502 if (unused_insn_chains == 0)
504 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
505 INIT_REG_SET (&c->live_throughout);
506 INIT_REG_SET (&c->dead_or_set);
510 c = unused_insn_chains;
511 unused_insn_chains = c->next;
513 c->is_caller_save_insn = 0;
514 c->need_operand_change = 0;
520 /* Small utility function to set all regs in hard reg set TO which are
521 allocated to pseudos in regset FROM. */
524 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 reg_set_iterator rsi;
529 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
531 int r = reg_renumber[regno];
536 /* reload_combine uses the information from
537 BASIC_BLOCK->global_live_at_start, which might still
538 contain registers that have not actually been allocated
539 since they have an equivalence. */
540 gcc_assert (reload_completed);
544 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
546 SET_HARD_REG_BIT (*to, r + nregs);
551 /* Replace all pseudos found in LOC with their corresponding
555 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
568 unsigned int regno = REGNO (x);
570 if (regno < FIRST_PSEUDO_REGISTER)
573 x = eliminate_regs (x, mem_mode, usage);
577 replace_pseudos_in (loc, mem_mode, usage);
581 if (reg_equiv_constant[regno])
582 *loc = reg_equiv_constant[regno];
583 else if (reg_equiv_mem[regno])
584 *loc = reg_equiv_mem[regno];
585 else if (reg_equiv_address[regno])
586 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
589 gcc_assert (!REG_P (regno_reg_rtx[regno])
590 || REGNO (regno_reg_rtx[regno]) != regno);
591 *loc = regno_reg_rtx[regno];
596 else if (code == MEM)
598 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
602 /* Process each of our operands recursively. */
603 fmt = GET_RTX_FORMAT (code);
604 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
606 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
607 else if (*fmt == 'E')
608 for (j = 0; j < XVECLEN (x, i); j++)
609 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
613 /* Global variables used by reload and its subroutines. */
615 /* Set during calculate_needs if an insn needs register elimination. */
616 static int something_needs_elimination;
617 /* Set during calculate_needs if an insn needs an operand changed. */
618 static int something_needs_operands_changed;
620 /* Nonzero means we couldn't get enough spill regs. */
623 /* Main entry point for the reload pass.
625 FIRST is the first insn of the function being compiled.
627 GLOBAL nonzero means we were called from global_alloc
628 and should attempt to reallocate any pseudoregs that we
629 displace from hard regs we will use for reloads.
630 If GLOBAL is zero, we do not have enough information to do that,
631 so any pseudo reg that is spilled must go to the stack.
633 Return value is nonzero if reload failed
634 and we must not do any more for this function. */
637 reload (rtx first, int global)
641 struct elim_table *ep;
644 /* Make sure even insns with volatile mem refs are recognizable. */
649 reload_firstobj = obstack_alloc (&reload_obstack, 0);
651 /* Make sure that the last insn in the chain
652 is not something that needs reloading. */
653 emit_note (NOTE_INSN_DELETED);
655 /* Enable find_equiv_reg to distinguish insns made by reload. */
656 reload_first_uid = get_max_uid ();
658 #ifdef SECONDARY_MEMORY_NEEDED
659 /* Initialize the secondary memory table. */
660 clear_secondary_mem ();
663 /* We don't have a stack slot for any spill reg yet. */
664 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
665 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
667 /* Initialize the save area information for caller-save, in case some
671 /* Compute which hard registers are now in use
672 as homes for pseudo registers.
673 This is done here rather than (eg) in global_alloc
674 because this point is reached even if not optimizing. */
675 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
678 /* A function that receives a nonlocal goto must save all call-saved
680 if (current_function_has_nonlocal_label)
681 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
682 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
683 regs_ever_live[i] = 1;
685 /* Find all the pseudo registers that didn't get hard regs
686 but do have known equivalent constants or memory slots.
687 These include parameters (known equivalent to parameter slots)
688 and cse'd or loop-moved constant memory addresses.
690 Record constant equivalents in reg_equiv_constant
691 so they will be substituted by find_reloads.
692 Record memory equivalents in reg_mem_equiv so they can
693 be substituted eventually by altering the REG-rtx's. */
695 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
696 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
697 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
698 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
699 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
700 reg_old_renumber = xcalloc (max_regno, sizeof (short));
701 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
702 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
703 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
705 CLEAR_HARD_REG_SET (bad_spill_regs_global);
707 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
708 to. Also find all paradoxical subregs and find largest such for
711 num_eliminable_invariants = 0;
712 for (insn = first; insn; insn = NEXT_INSN (insn))
714 rtx set = single_set (insn);
716 /* We may introduce USEs that we want to remove at the end, so
717 we'll mark them with QImode. Make sure there are no
718 previously-marked insns left by say regmove. */
719 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
720 && GET_MODE (insn) != VOIDmode)
721 PUT_MODE (insn, VOIDmode);
723 if (set != 0 && REG_P (SET_DEST (set)))
725 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
727 && (! function_invariant_p (XEXP (note, 0))
729 /* A function invariant is often CONSTANT_P but may
730 include a register. We promise to only pass
731 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
732 || (CONSTANT_P (XEXP (note, 0))
733 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))))
735 rtx x = XEXP (note, 0);
736 i = REGNO (SET_DEST (set));
737 if (i > LAST_VIRTUAL_REGISTER)
739 /* It can happen that a REG_EQUIV note contains a MEM
740 that is not a legitimate memory operand. As later
741 stages of reload assume that all addresses found
742 in the reg_equiv_* arrays were originally legitimate,
744 It can also happen that a REG_EQUIV note contains a
745 readonly memory location. If the destination pseudo
746 is set from some other value (typically a different
747 pseudo), and the destination pseudo does not get a
748 hard reg, then reload will replace the destination
749 pseudo with its equivalent memory location. This
750 is horribly bad as it creates a store to a readonly
751 memory location and a runtime segfault. To avoid
752 this problem we reject readonly memory locations
753 for equivalences. This is overly conservative as
754 we could find all sets of the destination pseudo
755 and remove them as they should be redundant. */
756 if (memory_operand (x, VOIDmode) && ! MEM_READONLY_P (x))
758 /* Always unshare the equivalence, so we can
759 substitute into this insn without touching the
761 reg_equiv_memory_loc[i] = copy_rtx (x);
763 else if (function_invariant_p (x))
765 if (GET_CODE (x) == PLUS)
767 /* This is PLUS of frame pointer and a constant,
768 and might be shared. Unshare it. */
769 reg_equiv_constant[i] = copy_rtx (x);
770 num_eliminable_invariants++;
772 else if (x == frame_pointer_rtx
773 || x == arg_pointer_rtx)
775 reg_equiv_constant[i] = x;
776 num_eliminable_invariants++;
778 else if (LEGITIMATE_CONSTANT_P (x))
779 reg_equiv_constant[i] = x;
782 reg_equiv_memory_loc[i]
783 = force_const_mem (GET_MODE (SET_DEST (set)), x);
784 if (!reg_equiv_memory_loc[i])
791 /* If this register is being made equivalent to a MEM
792 and the MEM is not SET_SRC, the equivalencing insn
793 is one with the MEM as a SET_DEST and it occurs later.
794 So don't mark this insn now. */
796 || rtx_equal_p (SET_SRC (set), x))
798 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
803 /* If this insn is setting a MEM from a register equivalent to it,
804 this is the equivalencing insn. */
805 else if (set && MEM_P (SET_DEST (set))
806 && REG_P (SET_SRC (set))
807 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
808 && rtx_equal_p (SET_DEST (set),
809 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
810 reg_equiv_init[REGNO (SET_SRC (set))]
811 = gen_rtx_INSN_LIST (VOIDmode, insn,
812 reg_equiv_init[REGNO (SET_SRC (set))]);
815 scan_paradoxical_subregs (PATTERN (insn));
820 first_label_num = get_first_label_num ();
821 num_labels = max_label_num () - first_label_num;
823 /* Allocate the tables used to store offset information at labels. */
824 /* We used to use alloca here, but the size of what it would try to
825 allocate would occasionally cause it to exceed the stack limit and
826 cause a core dump. */
827 offsets_known_at = xmalloc (num_labels);
828 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
830 /* Alter each pseudo-reg rtx to contain its hard reg number.
831 Assign stack slots to the pseudos that lack hard regs or equivalents.
832 Do not touch virtual registers. */
834 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
837 /* If we have some registers we think can be eliminated, scan all insns to
838 see if there is an insn that sets one of these registers to something
839 other than itself plus a constant. If so, the register cannot be
840 eliminated. Doing this scan here eliminates an extra pass through the
841 main reload loop in the most common case where register elimination
843 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
845 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
847 maybe_fix_stack_asms ();
849 insns_need_reload = 0;
850 something_needs_elimination = 0;
852 /* Initialize to -1, which means take the first spill register. */
855 /* Spill any hard regs that we know we can't eliminate. */
856 CLEAR_HARD_REG_SET (used_spill_regs);
857 /* There can be multiple ways to eliminate a register;
858 they should be listed adjacently.
859 Elimination for any register fails only if all possible ways fail. */
860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
863 int can_eliminate = 0;
866 can_eliminate |= ep->can_eliminate;
869 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
871 spill_hard_reg (from, 1);
874 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
875 if (frame_pointer_needed)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
878 finish_spills (global);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress = 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed;
892 HOST_WIDE_INT starting_frame_size;
894 /* Round size of stack frame to stack_alignment_needed. This must be done
895 here because the stack size may be a part of the offset computation
896 for register elimination, and there might have been new stack slots
897 created in the last iteration of this loop. */
898 if (cfun->stack_alignment_needed)
899 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
901 starting_frame_size = get_frame_size ();
903 set_initial_elim_offsets ();
904 set_initial_label_offsets ();
906 /* For each pseudo register that has an equivalent location defined,
907 try to eliminate any eliminable registers (such as the frame pointer)
908 assuming initial offsets for the replacement register, which
911 If the resulting location is directly addressable, substitute
912 the MEM we just got directly for the old REG.
914 If it is not addressable but is a constant or the sum of a hard reg
915 and constant, it is probably not addressable because the constant is
916 out of range, in that case record the address; we will generate
917 hairy code to compute the address in a register each time it is
918 needed. Similarly if it is a hard register, but one that is not
919 valid as an address register.
921 If the location is not addressable, but does not have one of the
922 above forms, assign a stack slot. We have to do this to avoid the
923 potential of producing lots of reloads if, e.g., a location involves
924 a pseudo that didn't get a hard register and has an equivalent memory
925 location that also involves a pseudo that didn't get a hard register.
927 Perhaps at some point we will improve reload_when_needed handling
928 so this problem goes away. But that's very hairy. */
930 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
931 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
933 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
935 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
937 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
938 else if (CONSTANT_P (XEXP (x, 0))
939 || (REG_P (XEXP (x, 0))
940 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
941 || (GET_CODE (XEXP (x, 0)) == PLUS
942 && REG_P (XEXP (XEXP (x, 0), 0))
943 && (REGNO (XEXP (XEXP (x, 0), 0))
944 < FIRST_PSEUDO_REGISTER)
945 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
946 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
949 /* Make a new stack slot. Then indicate that something
950 changed so we go back and recompute offsets for
951 eliminable registers because the allocation of memory
952 below might change some offset. reg_equiv_{mem,address}
953 will be set up for this pseudo on the next pass around
955 reg_equiv_memory_loc[i] = 0;
956 reg_equiv_init[i] = 0;
961 if (caller_save_needed)
964 /* If we allocated another stack slot, redo elimination bookkeeping. */
965 if (starting_frame_size != get_frame_size ())
968 if (caller_save_needed)
970 save_call_clobbered_regs ();
971 /* That might have allocated new insn_chain structures. */
972 reload_firstobj = obstack_alloc (&reload_obstack, 0);
975 calculate_needs_all_insns (global);
977 CLEAR_REG_SET (&spilled_pseudos);
980 something_changed = 0;
982 /* If we allocated any new memory locations, make another pass
983 since it might have changed elimination offsets. */
984 if (starting_frame_size != get_frame_size ())
985 something_changed = 1;
988 HARD_REG_SET to_spill;
989 CLEAR_HARD_REG_SET (to_spill);
990 update_eliminables (&to_spill);
991 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
992 if (TEST_HARD_REG_BIT (to_spill, i))
994 spill_hard_reg (i, 1);
997 /* Regardless of the state of spills, if we previously had
998 a register that we thought we could eliminate, but now can
999 not eliminate, we must run another pass.
1001 Consider pseudos which have an entry in reg_equiv_* which
1002 reference an eliminable register. We must make another pass
1003 to update reg_equiv_* so that we do not substitute in the
1004 old value from when we thought the elimination could be
1006 something_changed = 1;
1010 select_reload_regs ();
1014 if (insns_need_reload != 0 || did_spill)
1015 something_changed |= finish_spills (global);
1017 if (! something_changed)
1020 if (caller_save_needed)
1021 delete_caller_save_insns ();
1023 obstack_free (&reload_obstack, reload_firstobj);
1026 /* If global-alloc was run, notify it of any register eliminations we have
1029 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1030 if (ep->can_eliminate)
1031 mark_elimination (ep->from, ep->to);
1033 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1034 If that insn didn't set the register (i.e., it copied the register to
1035 memory), just delete that insn instead of the equivalencing insn plus
1036 anything now dead. If we call delete_dead_insn on that insn, we may
1037 delete the insn that actually sets the register if the register dies
1038 there and that is incorrect. */
1040 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1042 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1045 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1047 rtx equiv_insn = XEXP (list, 0);
1049 /* If we already deleted the insn or if it may trap, we can't
1050 delete it. The latter case shouldn't happen, but can
1051 if an insn has a variable address, gets a REG_EH_REGION
1052 note added to it, and then gets converted into an load
1053 from a constant address. */
1054 if (NOTE_P (equiv_insn)
1055 || can_throw_internal (equiv_insn))
1057 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1058 delete_dead_insn (equiv_insn);
1060 SET_INSN_DELETED (equiv_insn);
1065 /* Use the reload registers where necessary
1066 by generating move instructions to move the must-be-register
1067 values into or out of the reload registers. */
1069 if (insns_need_reload != 0 || something_needs_elimination
1070 || something_needs_operands_changed)
1072 HOST_WIDE_INT old_frame_size = get_frame_size ();
1074 reload_as_needed (global);
1076 gcc_assert (old_frame_size == get_frame_size ());
1079 verify_initial_elim_offsets ();
1082 /* If we were able to eliminate the frame pointer, show that it is no
1083 longer live at the start of any basic block. If it ls live by
1084 virtue of being in a pseudo, that pseudo will be marked live
1085 and hence the frame pointer will be known to be live via that
1088 if (! frame_pointer_needed)
1090 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1091 HARD_FRAME_POINTER_REGNUM);
1093 /* Come here (with failure set nonzero) if we can't get enough spill
1097 CLEAR_REG_SET (&spilled_pseudos);
1098 reload_in_progress = 0;
1100 /* Now eliminate all pseudo regs by modifying them into
1101 their equivalent memory references.
1102 The REG-rtx's for the pseudos are modified in place,
1103 so all insns that used to refer to them now refer to memory.
1105 For a reg that has a reg_equiv_address, all those insns
1106 were changed by reloading so that no insns refer to it any longer;
1107 but the DECL_RTL of a variable decl may refer to it,
1108 and if so this causes the debugging info to mention the variable. */
1110 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1114 if (reg_equiv_mem[i])
1115 addr = XEXP (reg_equiv_mem[i], 0);
1117 if (reg_equiv_address[i])
1118 addr = reg_equiv_address[i];
1122 if (reg_renumber[i] < 0)
1124 rtx reg = regno_reg_rtx[i];
1126 REG_USERVAR_P (reg) = 0;
1127 PUT_CODE (reg, MEM);
1128 XEXP (reg, 0) = addr;
1129 if (reg_equiv_memory_loc[i])
1130 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1133 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1134 MEM_ATTRS (reg) = 0;
1137 else if (reg_equiv_mem[i])
1138 XEXP (reg_equiv_mem[i], 0) = addr;
1142 /* We must set reload_completed now since the cleanup_subreg_operands call
1143 below will re-recognize each insn and reload may have generated insns
1144 which are only valid during and after reload. */
1145 reload_completed = 1;
1147 /* Make a pass over all the insns and delete all USEs which we inserted
1148 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1149 notes. Delete all CLOBBER insns, except those that refer to the return
1150 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1151 from misarranging variable-array code, and simplify (subreg (reg))
1152 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1153 are no longer useful or accurate. Strip and regenerate REG_INC notes
1154 that may have been moved around. */
1156 for (insn = first; insn; insn = NEXT_INSN (insn))
1162 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1163 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1165 if ((GET_CODE (PATTERN (insn)) == USE
1166 /* We mark with QImode USEs introduced by reload itself. */
1167 && (GET_MODE (insn) == QImode
1168 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1169 || (GET_CODE (PATTERN (insn)) == CLOBBER
1170 && (!MEM_P (XEXP (PATTERN (insn), 0))
1171 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1172 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1173 && XEXP (XEXP (PATTERN (insn), 0), 0)
1174 != stack_pointer_rtx))
1175 && (!REG_P (XEXP (PATTERN (insn), 0))
1176 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1182 /* Some CLOBBERs may survive until here and still reference unassigned
1183 pseudos with const equivalent, which may in turn cause ICE in later
1184 passes if the reference remains in place. */
1185 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1186 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1187 VOIDmode, PATTERN (insn));
1189 /* Discard obvious no-ops, even without -O. This optimization
1190 is fast and doesn't interfere with debugging. */
1191 if (NONJUMP_INSN_P (insn)
1192 && GET_CODE (PATTERN (insn)) == SET
1193 && REG_P (SET_SRC (PATTERN (insn)))
1194 && REG_P (SET_DEST (PATTERN (insn)))
1195 && (REGNO (SET_SRC (PATTERN (insn)))
1196 == REGNO (SET_DEST (PATTERN (insn)))))
1202 pnote = ®_NOTES (insn);
1205 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1206 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1207 || REG_NOTE_KIND (*pnote) == REG_INC
1208 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1209 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1210 *pnote = XEXP (*pnote, 1);
1212 pnote = &XEXP (*pnote, 1);
1216 add_auto_inc_notes (insn, PATTERN (insn));
1219 /* And simplify (subreg (reg)) if it appears as an operand. */
1220 cleanup_subreg_operands (insn);
1223 /* If we are doing stack checking, give a warning if this function's
1224 frame size is larger than we expect. */
1225 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1227 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1228 static int verbose_warned = 0;
1230 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1231 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1232 size += UNITS_PER_WORD;
1234 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1236 warning (0, "frame size too large for reliable stack checking");
1237 if (! verbose_warned)
1239 warning (0, "try reducing the number of local variables");
1245 /* Indicate that we no longer have known memory locations or constants. */
1246 if (reg_equiv_constant)
1247 free (reg_equiv_constant);
1248 reg_equiv_constant = 0;
1249 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1250 reg_equiv_memory_loc = 0;
1252 if (offsets_known_at)
1253 free (offsets_known_at);
1257 free (reg_equiv_mem);
1258 free (reg_equiv_init);
1259 free (reg_equiv_address);
1260 free (reg_max_ref_width);
1261 free (reg_old_renumber);
1262 free (pseudo_previous_regs);
1263 free (pseudo_forbidden_regs);
1265 CLEAR_HARD_REG_SET (used_spill_regs);
1266 for (i = 0; i < n_spills; i++)
1267 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1269 /* Free all the insn_chain structures at once. */
1270 obstack_free (&reload_obstack, reload_startobj);
1271 unused_insn_chains = 0;
1272 fixup_abnormal_edges ();
1274 /* Replacing pseudos with their memory equivalents might have
1275 created shared rtx. Subsequent passes would get confused
1276 by this, so unshare everything here. */
1277 unshare_all_rtl_again (first);
1279 #ifdef STACK_BOUNDARY
1280 /* init_emit has set the alignment of the hard frame pointer
1281 to STACK_BOUNDARY. It is very likely no longer valid if
1282 the hard frame pointer was used for register allocation. */
1283 if (!frame_pointer_needed)
1284 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1290 /* Yet another special case. Unfortunately, reg-stack forces people to
1291 write incorrect clobbers in asm statements. These clobbers must not
1292 cause the register to appear in bad_spill_regs, otherwise we'll call
1293 fatal_insn later. We clear the corresponding regnos in the live
1294 register sets to avoid this.
1295 The whole thing is rather sick, I'm afraid. */
1298 maybe_fix_stack_asms (void)
1301 const char *constraints[MAX_RECOG_OPERANDS];
1302 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1303 struct insn_chain *chain;
1305 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1308 HARD_REG_SET clobbered, allowed;
1311 if (! INSN_P (chain->insn)
1312 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1314 pat = PATTERN (chain->insn);
1315 if (GET_CODE (pat) != PARALLEL)
1318 CLEAR_HARD_REG_SET (clobbered);
1319 CLEAR_HARD_REG_SET (allowed);
1321 /* First, make a mask of all stack regs that are clobbered. */
1322 for (i = 0; i < XVECLEN (pat, 0); i++)
1324 rtx t = XVECEXP (pat, 0, i);
1325 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1326 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1329 /* Get the operand values and constraints out of the insn. */
1330 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1331 constraints, operand_mode);
1333 /* For every operand, see what registers are allowed. */
1334 for (i = 0; i < noperands; i++)
1336 const char *p = constraints[i];
1337 /* For every alternative, we compute the class of registers allowed
1338 for reloading in CLS, and merge its contents into the reg set
1340 int cls = (int) NO_REGS;
1346 if (c == '\0' || c == ',' || c == '#')
1348 /* End of one alternative - mark the regs in the current
1349 class, and reset the class. */
1350 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1356 } while (c != '\0' && c != ',');
1364 case '=': case '+': case '*': case '%': case '?': case '!':
1365 case '0': case '1': case '2': case '3': case '4': case 'm':
1366 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1367 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1368 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1373 cls = (int) reg_class_subunion[cls]
1374 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1379 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1383 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1384 cls = (int) reg_class_subunion[cls]
1385 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1387 cls = (int) reg_class_subunion[cls]
1388 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1390 p += CONSTRAINT_LEN (c, p);
1393 /* Those of the registers which are clobbered, but allowed by the
1394 constraints, must be usable as reload registers. So clear them
1395 out of the life information. */
1396 AND_HARD_REG_SET (allowed, clobbered);
1397 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1398 if (TEST_HARD_REG_BIT (allowed, i))
1400 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1401 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1408 /* Copy the global variables n_reloads and rld into the corresponding elts
1411 copy_reloads (struct insn_chain *chain)
1413 chain->n_reloads = n_reloads;
1414 chain->rld = obstack_alloc (&reload_obstack,
1415 n_reloads * sizeof (struct reload));
1416 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1417 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1420 /* Walk the chain of insns, and determine for each whether it needs reloads
1421 and/or eliminations. Build the corresponding insns_need_reload list, and
1422 set something_needs_elimination as appropriate. */
1424 calculate_needs_all_insns (int global)
1426 struct insn_chain **pprev_reload = &insns_need_reload;
1427 struct insn_chain *chain, *next = 0;
1429 something_needs_elimination = 0;
1431 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1432 for (chain = reload_insn_chain; chain != 0; chain = next)
1434 rtx insn = chain->insn;
1438 /* Clear out the shortcuts. */
1439 chain->n_reloads = 0;
1440 chain->need_elim = 0;
1441 chain->need_reload = 0;
1442 chain->need_operand_change = 0;
1444 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1445 include REG_LABEL), we need to see what effects this has on the
1446 known offsets at labels. */
1448 if (LABEL_P (insn) || JUMP_P (insn)
1449 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1450 set_label_offsets (insn, insn, 0);
1454 rtx old_body = PATTERN (insn);
1455 int old_code = INSN_CODE (insn);
1456 rtx old_notes = REG_NOTES (insn);
1457 int did_elimination = 0;
1458 int operands_changed = 0;
1459 rtx set = single_set (insn);
1461 /* Skip insns that only set an equivalence. */
1462 if (set && REG_P (SET_DEST (set))
1463 && reg_renumber[REGNO (SET_DEST (set))] < 0
1464 && reg_equiv_constant[REGNO (SET_DEST (set))])
1467 /* If needed, eliminate any eliminable registers. */
1468 if (num_eliminable || num_eliminable_invariants)
1469 did_elimination = eliminate_regs_in_insn (insn, 0);
1471 /* Analyze the instruction. */
1472 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1473 global, spill_reg_order);
1475 /* If a no-op set needs more than one reload, this is likely
1476 to be something that needs input address reloads. We
1477 can't get rid of this cleanly later, and it is of no use
1478 anyway, so discard it now.
1479 We only do this when expensive_optimizations is enabled,
1480 since this complements reload inheritance / output
1481 reload deletion, and it can make debugging harder. */
1482 if (flag_expensive_optimizations && n_reloads > 1)
1484 rtx set = single_set (insn);
1486 && SET_SRC (set) == SET_DEST (set)
1487 && REG_P (SET_SRC (set))
1488 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1491 /* Delete it from the reload chain. */
1493 chain->prev->next = next;
1495 reload_insn_chain = next;
1497 next->prev = chain->prev;
1498 chain->next = unused_insn_chains;
1499 unused_insn_chains = chain;
1504 update_eliminable_offsets ();
1506 /* Remember for later shortcuts which insns had any reloads or
1507 register eliminations. */
1508 chain->need_elim = did_elimination;
1509 chain->need_reload = n_reloads > 0;
1510 chain->need_operand_change = operands_changed;
1512 /* Discard any register replacements done. */
1513 if (did_elimination)
1515 obstack_free (&reload_obstack, reload_insn_firstobj);
1516 PATTERN (insn) = old_body;
1517 INSN_CODE (insn) = old_code;
1518 REG_NOTES (insn) = old_notes;
1519 something_needs_elimination = 1;
1522 something_needs_operands_changed |= operands_changed;
1526 copy_reloads (chain);
1527 *pprev_reload = chain;
1528 pprev_reload = &chain->next_need_reload;
1535 /* Comparison function for qsort to decide which of two reloads
1536 should be handled first. *P1 and *P2 are the reload numbers. */
1539 reload_reg_class_lower (const void *r1p, const void *r2p)
1541 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1544 /* Consider required reloads before optional ones. */
1545 t = rld[r1].optional - rld[r2].optional;
1549 /* Count all solitary classes before non-solitary ones. */
1550 t = ((reg_class_size[(int) rld[r2].class] == 1)
1551 - (reg_class_size[(int) rld[r1].class] == 1));
1555 /* Aside from solitaires, consider all multi-reg groups first. */
1556 t = rld[r2].nregs - rld[r1].nregs;
1560 /* Consider reloads in order of increasing reg-class number. */
1561 t = (int) rld[r1].class - (int) rld[r2].class;
1565 /* If reloads are equally urgent, sort by reload number,
1566 so that the results of qsort leave nothing to chance. */
1570 /* The cost of spilling each hard reg. */
1571 static int spill_cost[FIRST_PSEUDO_REGISTER];
1573 /* When spilling multiple hard registers, we use SPILL_COST for the first
1574 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1575 only the first hard reg for a multi-reg pseudo. */
1576 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1578 /* Update the spill cost arrays, considering that pseudo REG is live. */
1581 count_pseudo (int reg)
1583 int freq = REG_FREQ (reg);
1584 int r = reg_renumber[reg];
1587 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1588 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1591 SET_REGNO_REG_SET (&pseudos_counted, reg);
1593 gcc_assert (r >= 0);
1595 spill_add_cost[r] += freq;
1597 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1599 spill_cost[r + nregs] += freq;
1602 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1603 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1606 order_regs_for_reload (struct insn_chain *chain)
1609 HARD_REG_SET used_by_pseudos;
1610 HARD_REG_SET used_by_pseudos2;
1611 reg_set_iterator rsi;
1613 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1615 memset (spill_cost, 0, sizeof spill_cost);
1616 memset (spill_add_cost, 0, sizeof spill_add_cost);
1618 /* Count number of uses of each hard reg by pseudo regs allocated to it
1619 and then order them by decreasing use. First exclude hard registers
1620 that are live in or across this insn. */
1622 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1623 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1624 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1625 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1627 /* Now find out which pseudos are allocated to it, and update
1629 CLEAR_REG_SET (&pseudos_counted);
1631 EXECUTE_IF_SET_IN_REG_SET
1632 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1636 EXECUTE_IF_SET_IN_REG_SET
1637 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1641 CLEAR_REG_SET (&pseudos_counted);
1644 /* Vector of reload-numbers showing the order in which the reloads should
1646 static short reload_order[MAX_RELOADS];
1648 /* This is used to keep track of the spill regs used in one insn. */
1649 static HARD_REG_SET used_spill_regs_local;
1651 /* We decided to spill hard register SPILLED, which has a size of
1652 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1653 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1654 update SPILL_COST/SPILL_ADD_COST. */
1657 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1659 int r = reg_renumber[reg];
1660 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1662 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1663 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1666 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1668 spill_add_cost[r] -= REG_FREQ (reg);
1670 spill_cost[r + nregs] -= REG_FREQ (reg);
1673 /* Find reload register to use for reload number ORDER. */
1676 find_reg (struct insn_chain *chain, int order)
1678 int rnum = reload_order[order];
1679 struct reload *rl = rld + rnum;
1680 int best_cost = INT_MAX;
1684 HARD_REG_SET not_usable;
1685 HARD_REG_SET used_by_other_reload;
1686 reg_set_iterator rsi;
1688 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1689 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1690 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1692 CLEAR_HARD_REG_SET (used_by_other_reload);
1693 for (k = 0; k < order; k++)
1695 int other = reload_order[k];
1697 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1698 for (j = 0; j < rld[other].nregs; j++)
1699 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1702 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1704 unsigned int regno = i;
1706 if (! TEST_HARD_REG_BIT (not_usable, regno)
1707 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1708 && HARD_REGNO_MODE_OK (regno, rl->mode))
1710 int this_cost = spill_cost[regno];
1712 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1714 for (j = 1; j < this_nregs; j++)
1716 this_cost += spill_add_cost[regno + j];
1717 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1718 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1723 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1725 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1727 if (this_cost < best_cost
1728 /* Among registers with equal cost, prefer caller-saved ones, or
1729 use REG_ALLOC_ORDER if it is defined. */
1730 || (this_cost == best_cost
1731 #ifdef REG_ALLOC_ORDER
1732 && (inv_reg_alloc_order[regno]
1733 < inv_reg_alloc_order[best_reg])
1735 && call_used_regs[regno]
1736 && ! call_used_regs[best_reg]
1741 best_cost = this_cost;
1749 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1751 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1752 rl->regno = best_reg;
1754 EXECUTE_IF_SET_IN_REG_SET
1755 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1757 count_spilled_pseudo (best_reg, rl->nregs, j);
1760 EXECUTE_IF_SET_IN_REG_SET
1761 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1763 count_spilled_pseudo (best_reg, rl->nregs, j);
1766 for (i = 0; i < rl->nregs; i++)
1768 gcc_assert (spill_cost[best_reg + i] == 0);
1769 gcc_assert (spill_add_cost[best_reg + i] == 0);
1770 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1775 /* Find more reload regs to satisfy the remaining need of an insn, which
1777 Do it by ascending class number, since otherwise a reg
1778 might be spilled for a big class and might fail to count
1779 for a smaller class even though it belongs to that class. */
1782 find_reload_regs (struct insn_chain *chain)
1786 /* In order to be certain of getting the registers we need,
1787 we must sort the reloads into order of increasing register class.
1788 Then our grabbing of reload registers will parallel the process
1789 that provided the reload registers. */
1790 for (i = 0; i < chain->n_reloads; i++)
1792 /* Show whether this reload already has a hard reg. */
1793 if (chain->rld[i].reg_rtx)
1795 int regno = REGNO (chain->rld[i].reg_rtx);
1796 chain->rld[i].regno = regno;
1798 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1801 chain->rld[i].regno = -1;
1802 reload_order[i] = i;
1805 n_reloads = chain->n_reloads;
1806 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1808 CLEAR_HARD_REG_SET (used_spill_regs_local);
1811 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1813 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1815 /* Compute the order of preference for hard registers to spill. */
1817 order_regs_for_reload (chain);
1819 for (i = 0; i < n_reloads; i++)
1821 int r = reload_order[i];
1823 /* Ignore reloads that got marked inoperative. */
1824 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1825 && ! rld[r].optional
1826 && rld[r].regno == -1)
1827 if (! find_reg (chain, i))
1829 spill_failure (chain->insn, rld[r].class);
1835 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1836 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1838 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1842 select_reload_regs (void)
1844 struct insn_chain *chain;
1846 /* Try to satisfy the needs for each insn. */
1847 for (chain = insns_need_reload; chain != 0;
1848 chain = chain->next_need_reload)
1849 find_reload_regs (chain);
1852 /* Delete all insns that were inserted by emit_caller_save_insns during
1855 delete_caller_save_insns (void)
1857 struct insn_chain *c = reload_insn_chain;
1861 while (c != 0 && c->is_caller_save_insn)
1863 struct insn_chain *next = c->next;
1866 if (c == reload_insn_chain)
1867 reload_insn_chain = next;
1871 next->prev = c->prev;
1873 c->prev->next = next;
1874 c->next = unused_insn_chains;
1875 unused_insn_chains = c;
1883 /* Handle the failure to find a register to spill.
1884 INSN should be one of the insns which needed this particular spill reg. */
1887 spill_failure (rtx insn, enum reg_class class)
1889 if (asm_noperands (PATTERN (insn)) >= 0)
1890 error_for_asm (insn, "can't find a register in class %qs while "
1891 "reloading %<asm%>",
1892 reg_class_names[class]);
1895 error ("unable to find a register to spill in class %qs",
1896 reg_class_names[class]);
1897 fatal_insn ("this is the insn:", insn);
1901 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1902 data that is dead in INSN. */
1905 delete_dead_insn (rtx insn)
1907 rtx prev = prev_real_insn (insn);
1910 /* If the previous insn sets a register that dies in our insn, delete it
1912 if (prev && GET_CODE (PATTERN (prev)) == SET
1913 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1914 && reg_mentioned_p (prev_dest, PATTERN (insn))
1915 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1916 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1917 delete_dead_insn (prev);
1919 SET_INSN_DELETED (insn);
1922 /* Modify the home of pseudo-reg I.
1923 The new home is present in reg_renumber[I].
1925 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1926 or it may be -1, meaning there is none or it is not relevant.
1927 This is used so that all pseudos spilled from a given hard reg
1928 can share one stack slot. */
1931 alter_reg (int i, int from_reg)
1933 /* When outputting an inline function, this can happen
1934 for a reg that isn't actually used. */
1935 if (regno_reg_rtx[i] == 0)
1938 /* If the reg got changed to a MEM at rtl-generation time,
1940 if (!REG_P (regno_reg_rtx[i]))
1943 /* Modify the reg-rtx to contain the new hard reg
1944 number or else to contain its pseudo reg number. */
1945 REGNO (regno_reg_rtx[i])
1946 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1948 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1949 allocate a stack slot for it. */
1951 if (reg_renumber[i] < 0
1952 && REG_N_REFS (i) > 0
1953 && reg_equiv_constant[i] == 0
1954 && reg_equiv_memory_loc[i] == 0)
1957 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1958 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1961 /* Each pseudo reg has an inherent size which comes from its own mode,
1962 and a total size which provides room for paradoxical subregs
1963 which refer to the pseudo reg in wider modes.
1965 We can use a slot already allocated if it provides both
1966 enough inherent space and enough total space.
1967 Otherwise, we allocate a new slot, making sure that it has no less
1968 inherent space, and no less total space, then the previous slot. */
1971 /* No known place to spill from => no slot to reuse. */
1972 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1973 inherent_size == total_size ? 0 : -1);
1974 if (BYTES_BIG_ENDIAN)
1975 /* Cancel the big-endian correction done in assign_stack_local.
1976 Get the address of the beginning of the slot.
1977 This is so we can do a big-endian correction unconditionally
1979 adjust = inherent_size - total_size;
1981 /* Nothing can alias this slot except this pseudo. */
1982 set_mem_alias_set (x, new_alias_set ());
1985 /* Reuse a stack slot if possible. */
1986 else if (spill_stack_slot[from_reg] != 0
1987 && spill_stack_slot_width[from_reg] >= total_size
1988 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1990 x = spill_stack_slot[from_reg];
1992 /* Allocate a bigger slot. */
1995 /* Compute maximum size needed, both for inherent size
1996 and for total size. */
1997 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2000 if (spill_stack_slot[from_reg])
2002 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2004 mode = GET_MODE (spill_stack_slot[from_reg]);
2005 if (spill_stack_slot_width[from_reg] > total_size)
2006 total_size = spill_stack_slot_width[from_reg];
2009 /* Make a slot with that size. */
2010 x = assign_stack_local (mode, total_size,
2011 inherent_size == total_size ? 0 : -1);
2014 /* All pseudos mapped to this slot can alias each other. */
2015 if (spill_stack_slot[from_reg])
2016 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2018 set_mem_alias_set (x, new_alias_set ());
2020 if (BYTES_BIG_ENDIAN)
2022 /* Cancel the big-endian correction done in assign_stack_local.
2023 Get the address of the beginning of the slot.
2024 This is so we can do a big-endian correction unconditionally
2026 adjust = GET_MODE_SIZE (mode) - total_size;
2029 = adjust_address_nv (x, mode_for_size (total_size
2035 spill_stack_slot[from_reg] = stack_slot;
2036 spill_stack_slot_width[from_reg] = total_size;
2039 /* On a big endian machine, the "address" of the slot
2040 is the address of the low part that fits its inherent mode. */
2041 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2042 adjust += (total_size - inherent_size);
2044 /* If we have any adjustment to make, or if the stack slot is the
2045 wrong mode, make a new stack slot. */
2046 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2048 /* If we have a decl for the original register, set it for the
2049 memory. If this is a shared MEM, make a copy. */
2050 if (REG_EXPR (regno_reg_rtx[i])
2051 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2053 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2055 /* We can do this only for the DECLs home pseudo, not for
2056 any copies of it, since otherwise when the stack slot
2057 is reused, nonoverlapping_memrefs_p might think they
2059 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2061 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2064 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2068 /* Save the stack slot for later. */
2069 reg_equiv_memory_loc[i] = x;
2073 /* Mark the slots in regs_ever_live for the hard regs
2074 used by pseudo-reg number REGNO. */
2077 mark_home_live (int regno)
2081 i = reg_renumber[regno];
2084 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2086 regs_ever_live[i++] = 1;
2089 /* This function handles the tracking of elimination offsets around branches.
2091 X is a piece of RTL being scanned.
2093 INSN is the insn that it came from, if any.
2095 INITIAL_P is nonzero if we are to set the offset to be the initial
2096 offset and zero if we are setting the offset of the label to be the
2100 set_label_offsets (rtx x, rtx insn, int initial_p)
2102 enum rtx_code code = GET_CODE (x);
2105 struct elim_table *p;
2110 if (LABEL_REF_NONLOCAL_P (x))
2115 /* ... fall through ... */
2118 /* If we know nothing about this label, set the desired offsets. Note
2119 that this sets the offset at a label to be the offset before a label
2120 if we don't know anything about the label. This is not correct for
2121 the label after a BARRIER, but is the best guess we can make. If
2122 we guessed wrong, we will suppress an elimination that might have
2123 been possible had we been able to guess correctly. */
2125 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2127 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2128 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2129 = (initial_p ? reg_eliminate[i].initial_offset
2130 : reg_eliminate[i].offset);
2131 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2134 /* Otherwise, if this is the definition of a label and it is
2135 preceded by a BARRIER, set our offsets to the known offset of
2139 && (tem = prev_nonnote_insn (insn)) != 0
2141 set_offsets_for_label (insn);
2143 /* If neither of the above cases is true, compare each offset
2144 with those previously recorded and suppress any eliminations
2145 where the offsets disagree. */
2147 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2148 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2149 != (initial_p ? reg_eliminate[i].initial_offset
2150 : reg_eliminate[i].offset))
2151 reg_eliminate[i].can_eliminate = 0;
2156 set_label_offsets (PATTERN (insn), insn, initial_p);
2158 /* ... fall through ... */
2162 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2163 and hence must have all eliminations at their initial offsets. */
2164 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2165 if (REG_NOTE_KIND (tem) == REG_LABEL)
2166 set_label_offsets (XEXP (tem, 0), insn, 1);
2172 /* Each of the labels in the parallel or address vector must be
2173 at their initial offsets. We want the first field for PARALLEL
2174 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2176 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2177 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2182 /* We only care about setting PC. If the source is not RETURN,
2183 IF_THEN_ELSE, or a label, disable any eliminations not at
2184 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2185 isn't one of those possibilities. For branches to a label,
2186 call ourselves recursively.
2188 Note that this can disable elimination unnecessarily when we have
2189 a non-local goto since it will look like a non-constant jump to
2190 someplace in the current function. This isn't a significant
2191 problem since such jumps will normally be when all elimination
2192 pairs are back to their initial offsets. */
2194 if (SET_DEST (x) != pc_rtx)
2197 switch (GET_CODE (SET_SRC (x)))
2204 set_label_offsets (SET_SRC (x), insn, initial_p);
2208 tem = XEXP (SET_SRC (x), 1);
2209 if (GET_CODE (tem) == LABEL_REF)
2210 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2211 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2214 tem = XEXP (SET_SRC (x), 2);
2215 if (GET_CODE (tem) == LABEL_REF)
2216 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2217 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2225 /* If we reach here, all eliminations must be at their initial
2226 offset because we are doing a jump to a variable address. */
2227 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2228 if (p->offset != p->initial_offset)
2229 p->can_eliminate = 0;
2237 /* Scan X and replace any eliminable registers (such as fp) with a
2238 replacement (such as sp), plus an offset.
2240 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2241 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2242 MEM, we are allowed to replace a sum of a register and the constant zero
2243 with the register, which we cannot do outside a MEM. In addition, we need
2244 to record the fact that a register is referenced outside a MEM.
2246 If INSN is an insn, it is the insn containing X. If we replace a REG
2247 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2248 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2249 the REG is being modified.
2251 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2252 That's used when we eliminate in expressions stored in notes.
2253 This means, do not set ref_outside_mem even if the reference
2256 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2257 replacements done assuming all offsets are at their initial values. If
2258 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2259 encounter, return the actual location so that find_reloads will do
2260 the proper thing. */
2263 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2265 enum rtx_code code = GET_CODE (x);
2266 struct elim_table *ep;
2273 if (! current_function_decl)
2295 /* First handle the case where we encounter a bare register that
2296 is eliminable. Replace it with a PLUS. */
2297 if (regno < FIRST_PSEUDO_REGISTER)
2299 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2301 if (ep->from_rtx == x && ep->can_eliminate)
2302 return plus_constant (ep->to_rtx, ep->previous_offset);
2305 else if (reg_renumber && reg_renumber[regno] < 0
2306 && reg_equiv_constant && reg_equiv_constant[regno]
2307 && ! CONSTANT_P (reg_equiv_constant[regno]))
2308 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2312 /* You might think handling MINUS in a manner similar to PLUS is a
2313 good idea. It is not. It has been tried multiple times and every
2314 time the change has had to have been reverted.
2316 Other parts of reload know a PLUS is special (gen_reload for example)
2317 and require special code to handle code a reloaded PLUS operand.
2319 Also consider backends where the flags register is clobbered by a
2320 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2321 lea instruction comes to mind). If we try to reload a MINUS, we
2322 may kill the flags register that was holding a useful value.
2324 So, please before trying to handle MINUS, consider reload as a
2325 whole instead of this little section as well as the backend issues. */
2327 /* If this is the sum of an eliminable register and a constant, rework
2329 if (REG_P (XEXP (x, 0))
2330 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2331 && CONSTANT_P (XEXP (x, 1)))
2333 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2335 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2337 /* The only time we want to replace a PLUS with a REG (this
2338 occurs when the constant operand of the PLUS is the negative
2339 of the offset) is when we are inside a MEM. We won't want
2340 to do so at other times because that would change the
2341 structure of the insn in a way that reload can't handle.
2342 We special-case the commonest situation in
2343 eliminate_regs_in_insn, so just replace a PLUS with a
2344 PLUS here, unless inside a MEM. */
2345 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2346 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2349 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2350 plus_constant (XEXP (x, 1),
2351 ep->previous_offset));
2354 /* If the register is not eliminable, we are done since the other
2355 operand is a constant. */
2359 /* If this is part of an address, we want to bring any constant to the
2360 outermost PLUS. We will do this by doing register replacement in
2361 our operands and seeing if a constant shows up in one of them.
2363 Note that there is no risk of modifying the structure of the insn,
2364 since we only get called for its operands, thus we are either
2365 modifying the address inside a MEM, or something like an address
2366 operand of a load-address insn. */
2369 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2370 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2372 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2374 /* If one side is a PLUS and the other side is a pseudo that
2375 didn't get a hard register but has a reg_equiv_constant,
2376 we must replace the constant here since it may no longer
2377 be in the position of any operand. */
2378 if (GET_CODE (new0) == PLUS && REG_P (new1)
2379 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2380 && reg_renumber[REGNO (new1)] < 0
2381 && reg_equiv_constant != 0
2382 && reg_equiv_constant[REGNO (new1)] != 0)
2383 new1 = reg_equiv_constant[REGNO (new1)];
2384 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2385 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2386 && reg_renumber[REGNO (new0)] < 0
2387 && reg_equiv_constant[REGNO (new0)] != 0)
2388 new0 = reg_equiv_constant[REGNO (new0)];
2390 new = form_sum (new0, new1);
2392 /* As above, if we are not inside a MEM we do not want to
2393 turn a PLUS into something else. We might try to do so here
2394 for an addition of 0 if we aren't optimizing. */
2395 if (! mem_mode && GET_CODE (new) != PLUS)
2396 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2404 /* If this is the product of an eliminable register and a
2405 constant, apply the distribute law and move the constant out
2406 so that we have (plus (mult ..) ..). This is needed in order
2407 to keep load-address insns valid. This case is pathological.
2408 We ignore the possibility of overflow here. */
2409 if (REG_P (XEXP (x, 0))
2410 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2411 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2412 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2414 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2417 /* Refs inside notes don't count for this purpose. */
2418 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2419 || GET_CODE (insn) == INSN_LIST)))
2420 ep->ref_outside_mem = 1;
2423 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2424 ep->previous_offset * INTVAL (XEXP (x, 1)));
2427 /* ... fall through ... */
2431 /* See comments before PLUS about handling MINUS. */
2433 case DIV: case UDIV:
2434 case MOD: case UMOD:
2435 case AND: case IOR: case XOR:
2436 case ROTATERT: case ROTATE:
2437 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2439 case GE: case GT: case GEU: case GTU:
2440 case LE: case LT: case LEU: case LTU:
2442 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2444 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2446 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2447 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2452 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2455 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2456 if (new != XEXP (x, 0))
2458 /* If this is a REG_DEAD note, it is not valid anymore.
2459 Using the eliminated version could result in creating a
2460 REG_DEAD note for the stack or frame pointer. */
2461 if (GET_MODE (x) == REG_DEAD)
2463 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2466 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2470 /* ... fall through ... */
2473 /* Now do eliminations in the rest of the chain. If this was
2474 an EXPR_LIST, this might result in allocating more memory than is
2475 strictly needed, but it simplifies the code. */
2478 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2479 if (new != XEXP (x, 1))
2481 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2489 case STRICT_LOW_PART:
2491 case SIGN_EXTEND: case ZERO_EXTEND:
2492 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2493 case FLOAT: case FIX:
2494 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2502 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2503 if (new != XEXP (x, 0))
2504 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2508 /* Similar to above processing, but preserve SUBREG_BYTE.
2509 Convert (subreg (mem)) to (mem) if not paradoxical.
2510 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2511 pseudo didn't get a hard reg, we must replace this with the
2512 eliminated version of the memory location because push_reload
2513 may do the replacement in certain circumstances. */
2514 if (REG_P (SUBREG_REG (x))
2515 && (GET_MODE_SIZE (GET_MODE (x))
2516 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2517 && reg_equiv_memory_loc != 0
2518 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2520 new = SUBREG_REG (x);
2523 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2525 if (new != SUBREG_REG (x))
2527 int x_size = GET_MODE_SIZE (GET_MODE (x));
2528 int new_size = GET_MODE_SIZE (GET_MODE (new));
2531 && ((x_size < new_size
2532 #ifdef WORD_REGISTER_OPERATIONS
2533 /* On these machines, combine can create rtl of the form
2534 (set (subreg:m1 (reg:m2 R) 0) ...)
2535 where m1 < m2, and expects something interesting to
2536 happen to the entire word. Moreover, it will use the
2537 (reg:m2 R) later, expecting all bits to be preserved.
2538 So if the number of words is the same, preserve the
2539 subreg so that push_reload can see it. */
2540 && ! ((x_size - 1) / UNITS_PER_WORD
2541 == (new_size -1 ) / UNITS_PER_WORD)
2544 || x_size == new_size)
2546 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2548 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2554 /* Our only special processing is to pass the mode of the MEM to our
2555 recursive call and copy the flags. While we are here, handle this
2556 case more efficiently. */
2558 replace_equiv_address_nv (x,
2559 eliminate_regs (XEXP (x, 0),
2560 GET_MODE (x), insn));
2563 /* Handle insn_list USE that a call to a pure function may generate. */
2564 new = eliminate_regs (XEXP (x, 0), 0, insn);
2565 if (new != XEXP (x, 0))
2566 return gen_rtx_USE (GET_MODE (x), new);
2578 /* Process each of our operands recursively. If any have changed, make a
2580 fmt = GET_RTX_FORMAT (code);
2581 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2585 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2586 if (new != XEXP (x, i) && ! copied)
2588 rtx new_x = rtx_alloc (code);
2589 memcpy (new_x, x, RTX_SIZE (code));
2595 else if (*fmt == 'E')
2598 for (j = 0; j < XVECLEN (x, i); j++)
2600 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2601 if (new != XVECEXP (x, i, j) && ! copied_vec)
2603 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2607 rtx new_x = rtx_alloc (code);
2608 memcpy (new_x, x, RTX_SIZE (code));
2612 XVEC (x, i) = new_v;
2615 XVECEXP (x, i, j) = new;
2623 /* Scan rtx X for modifications of elimination target registers. Update
2624 the table of eliminables to reflect the changed state. MEM_MODE is
2625 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2628 elimination_effects (rtx x, enum machine_mode mem_mode)
2630 enum rtx_code code = GET_CODE (x);
2631 struct elim_table *ep;
2655 /* First handle the case where we encounter a bare register that
2656 is eliminable. Replace it with a PLUS. */
2657 if (regno < FIRST_PSEUDO_REGISTER)
2659 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2661 if (ep->from_rtx == x && ep->can_eliminate)
2664 ep->ref_outside_mem = 1;
2669 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2670 && reg_equiv_constant[regno]
2671 && ! function_invariant_p (reg_equiv_constant[regno]))
2672 elimination_effects (reg_equiv_constant[regno], mem_mode);
2681 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2682 if (ep->to_rtx == XEXP (x, 0))
2684 int size = GET_MODE_SIZE (mem_mode);
2686 /* If more bytes than MEM_MODE are pushed, account for them. */
2687 #ifdef PUSH_ROUNDING
2688 if (ep->to_rtx == stack_pointer_rtx)
2689 size = PUSH_ROUNDING (size);
2691 if (code == PRE_DEC || code == POST_DEC)
2693 else if (code == PRE_INC || code == POST_INC)
2695 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2696 && GET_CODE (XEXP (x, 1)) == PLUS
2697 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2698 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2699 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2702 /* These two aren't unary operators. */
2703 if (code == POST_MODIFY || code == PRE_MODIFY)
2706 /* Fall through to generic unary operation case. */
2707 case STRICT_LOW_PART:
2709 case SIGN_EXTEND: case ZERO_EXTEND:
2710 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2711 case FLOAT: case FIX:
2712 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2720 elimination_effects (XEXP (x, 0), mem_mode);
2724 if (REG_P (SUBREG_REG (x))
2725 && (GET_MODE_SIZE (GET_MODE (x))
2726 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2727 && reg_equiv_memory_loc != 0
2728 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2731 elimination_effects (SUBREG_REG (x), mem_mode);
2735 /* If using a register that is the source of an eliminate we still
2736 think can be performed, note it cannot be performed since we don't
2737 know how this register is used. */
2738 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2739 if (ep->from_rtx == XEXP (x, 0))
2740 ep->can_eliminate = 0;
2742 elimination_effects (XEXP (x, 0), mem_mode);
2746 /* If clobbering a register that is the replacement register for an
2747 elimination we still think can be performed, note that it cannot
2748 be performed. Otherwise, we need not be concerned about it. */
2749 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2750 if (ep->to_rtx == XEXP (x, 0))
2751 ep->can_eliminate = 0;
2753 elimination_effects (XEXP (x, 0), mem_mode);
2757 /* Check for setting a register that we know about. */
2758 if (REG_P (SET_DEST (x)))
2760 /* See if this is setting the replacement register for an
2763 If DEST is the hard frame pointer, we do nothing because we
2764 assume that all assignments to the frame pointer are for
2765 non-local gotos and are being done at a time when they are valid
2766 and do not disturb anything else. Some machines want to
2767 eliminate a fake argument pointer (or even a fake frame pointer)
2768 with either the real frame or the stack pointer. Assignments to
2769 the hard frame pointer must not prevent this elimination. */
2771 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2773 if (ep->to_rtx == SET_DEST (x)
2774 && SET_DEST (x) != hard_frame_pointer_rtx)
2776 /* If it is being incremented, adjust the offset. Otherwise,
2777 this elimination can't be done. */
2778 rtx src = SET_SRC (x);
2780 if (GET_CODE (src) == PLUS
2781 && XEXP (src, 0) == SET_DEST (x)
2782 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2783 ep->offset -= INTVAL (XEXP (src, 1));
2785 ep->can_eliminate = 0;
2789 elimination_effects (SET_DEST (x), 0);
2790 elimination_effects (SET_SRC (x), 0);
2794 /* Our only special processing is to pass the mode of the MEM to our
2796 elimination_effects (XEXP (x, 0), GET_MODE (x));
2803 fmt = GET_RTX_FORMAT (code);
2804 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2807 elimination_effects (XEXP (x, i), mem_mode);
2808 else if (*fmt == 'E')
2809 for (j = 0; j < XVECLEN (x, i); j++)
2810 elimination_effects (XVECEXP (x, i, j), mem_mode);
2814 /* Descend through rtx X and verify that no references to eliminable registers
2815 remain. If any do remain, mark the involved register as not
2819 check_eliminable_occurrences (rtx x)
2828 code = GET_CODE (x);
2830 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2832 struct elim_table *ep;
2834 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2835 if (ep->from_rtx == x)
2836 ep->can_eliminate = 0;
2840 fmt = GET_RTX_FORMAT (code);
2841 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2844 check_eliminable_occurrences (XEXP (x, i));
2845 else if (*fmt == 'E')
2848 for (j = 0; j < XVECLEN (x, i); j++)
2849 check_eliminable_occurrences (XVECEXP (x, i, j));
2854 /* Scan INSN and eliminate all eliminable registers in it.
2856 If REPLACE is nonzero, do the replacement destructively. Also
2857 delete the insn as dead it if it is setting an eliminable register.
2859 If REPLACE is zero, do all our allocations in reload_obstack.
2861 If no eliminations were done and this insn doesn't require any elimination
2862 processing (these are not identical conditions: it might be updating sp,
2863 but not referencing fp; this needs to be seen during reload_as_needed so
2864 that the offset between fp and sp can be taken into consideration), zero
2865 is returned. Otherwise, 1 is returned. */
2868 eliminate_regs_in_insn (rtx insn, int replace)
2870 int icode = recog_memoized (insn);
2871 rtx old_body = PATTERN (insn);
2872 int insn_is_asm = asm_noperands (old_body) >= 0;
2873 rtx old_set = single_set (insn);
2877 rtx substed_operand[MAX_RECOG_OPERANDS];
2878 rtx orig_operand[MAX_RECOG_OPERANDS];
2879 struct elim_table *ep;
2882 if (! insn_is_asm && icode < 0)
2884 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2885 || GET_CODE (PATTERN (insn)) == CLOBBER
2886 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2887 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2888 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2892 if (old_set != 0 && REG_P (SET_DEST (old_set))
2893 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2895 /* Check for setting an eliminable register. */
2896 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2897 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2899 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2900 /* If this is setting the frame pointer register to the
2901 hardware frame pointer register and this is an elimination
2902 that will be done (tested above), this insn is really
2903 adjusting the frame pointer downward to compensate for
2904 the adjustment done before a nonlocal goto. */
2905 if (ep->from == FRAME_POINTER_REGNUM
2906 && ep->to == HARD_FRAME_POINTER_REGNUM)
2908 rtx base = SET_SRC (old_set);
2909 rtx base_insn = insn;
2910 HOST_WIDE_INT offset = 0;
2912 while (base != ep->to_rtx)
2914 rtx prev_insn, prev_set;
2916 if (GET_CODE (base) == PLUS
2917 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2919 offset += INTVAL (XEXP (base, 1));
2920 base = XEXP (base, 0);
2922 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2923 && (prev_set = single_set (prev_insn)) != 0
2924 && rtx_equal_p (SET_DEST (prev_set), base))
2926 base = SET_SRC (prev_set);
2927 base_insn = prev_insn;
2933 if (base == ep->to_rtx)
2936 = plus_constant (ep->to_rtx, offset - ep->offset);
2938 new_body = old_body;
2941 new_body = copy_insn (old_body);
2942 if (REG_NOTES (insn))
2943 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2945 PATTERN (insn) = new_body;
2946 old_set = single_set (insn);
2948 /* First see if this insn remains valid when we
2949 make the change. If not, keep the INSN_CODE
2950 the same and let reload fit it up. */
2951 validate_change (insn, &SET_SRC (old_set), src, 1);
2952 validate_change (insn, &SET_DEST (old_set),
2954 if (! apply_change_group ())
2956 SET_SRC (old_set) = src;
2957 SET_DEST (old_set) = ep->to_rtx;
2966 /* In this case this insn isn't serving a useful purpose. We
2967 will delete it in reload_as_needed once we know that this
2968 elimination is, in fact, being done.
2970 If REPLACE isn't set, we can't delete this insn, but needn't
2971 process it since it won't be used unless something changes. */
2974 delete_dead_insn (insn);
2982 /* We allow one special case which happens to work on all machines we
2983 currently support: a single set with the source or a REG_EQUAL
2984 note being a PLUS of an eliminable register and a constant. */
2986 if (old_set && REG_P (SET_DEST (old_set)))
2988 /* First see if the source is of the form (plus (reg) CST). */
2989 if (GET_CODE (SET_SRC (old_set)) == PLUS
2990 && REG_P (XEXP (SET_SRC (old_set), 0))
2991 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2992 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2993 plus_src = SET_SRC (old_set);
2994 else if (REG_P (SET_SRC (old_set)))
2996 /* Otherwise, see if we have a REG_EQUAL note of the form
2997 (plus (reg) CST). */
2999 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3001 if (REG_NOTE_KIND (links) == REG_EQUAL
3002 && GET_CODE (XEXP (links, 0)) == PLUS
3003 && REG_P (XEXP (XEXP (links, 0), 0))
3004 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
3005 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
3007 plus_src = XEXP (links, 0);
3015 rtx reg = XEXP (plus_src, 0);
3016 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3018 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3019 if (ep->from_rtx == reg && ep->can_eliminate)
3021 offset += ep->offset;
3026 /* We assume here that if we need a PARALLEL with
3027 CLOBBERs for this assignment, we can do with the
3028 MATCH_SCRATCHes that add_clobbers allocates.
3029 There's not much we can do if that doesn't work. */
3030 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3034 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3037 rtvec vec = rtvec_alloc (num_clobbers + 1);
3039 vec->elem[0] = PATTERN (insn);
3040 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3041 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3043 gcc_assert (INSN_CODE (insn) >= 0);
3045 /* If we have a nonzero offset, and the source is already
3046 a simple REG, the following transformation would
3047 increase the cost of the insn by replacing a simple REG
3048 with (plus (reg sp) CST). So try only when plus_src
3049 comes from old_set proper, not REG_NOTES. */
3050 else if (SET_SRC (old_set) == plus_src)
3052 new_body = old_body;
3055 new_body = copy_insn (old_body);
3056 if (REG_NOTES (insn))
3057 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3059 PATTERN (insn) = new_body;
3060 old_set = single_set (insn);
3062 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3063 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3069 /* This can't have an effect on elimination offsets, so skip right
3075 /* Determine the effects of this insn on elimination offsets. */
3076 elimination_effects (old_body, 0);
3078 /* Eliminate all eliminable registers occurring in operands that
3079 can be handled by reload. */
3080 extract_insn (insn);
3081 for (i = 0; i < recog_data.n_operands; i++)
3083 orig_operand[i] = recog_data.operand[i];
3084 substed_operand[i] = recog_data.operand[i];
3086 /* For an asm statement, every operand is eliminable. */
3087 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3089 /* Check for setting a register that we know about. */
3090 if (recog_data.operand_type[i] != OP_IN
3091 && REG_P (orig_operand[i]))
3093 /* If we are assigning to a register that can be eliminated, it
3094 must be as part of a PARALLEL, since the code above handles
3095 single SETs. We must indicate that we can no longer
3096 eliminate this reg. */
3097 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3099 if (ep->from_rtx == orig_operand[i])
3100 ep->can_eliminate = 0;
3103 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3104 replace ? insn : NULL_RTX);
3105 if (substed_operand[i] != orig_operand[i])
3107 /* Terminate the search in check_eliminable_occurrences at
3109 *recog_data.operand_loc[i] = 0;
3111 /* If an output operand changed from a REG to a MEM and INSN is an
3112 insn, write a CLOBBER insn. */
3113 if (recog_data.operand_type[i] != OP_IN
3114 && REG_P (orig_operand[i])
3115 && MEM_P (substed_operand[i])
3117 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3122 for (i = 0; i < recog_data.n_dups; i++)
3123 *recog_data.dup_loc[i]
3124 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3126 /* If any eliminable remain, they aren't eliminable anymore. */
3127 check_eliminable_occurrences (old_body);
3129 /* Substitute the operands; the new values are in the substed_operand
3131 for (i = 0; i < recog_data.n_operands; i++)
3132 *recog_data.operand_loc[i] = substed_operand[i];
3133 for (i = 0; i < recog_data.n_dups; i++)
3134 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3136 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3137 re-recognize the insn. We do this in case we had a simple addition
3138 but now can do this as a load-address. This saves an insn in this
3140 If re-recognition fails, the old insn code number will still be used,
3141 and some register operands may have changed into PLUS expressions.
3142 These will be handled by find_reloads by loading them into a register
3147 /* If we aren't replacing things permanently and we changed something,
3148 make another copy to ensure that all the RTL is new. Otherwise
3149 things can go wrong if find_reload swaps commutative operands
3150 and one is inside RTL that has been copied while the other is not. */
3151 new_body = old_body;
3154 new_body = copy_insn (old_body);
3155 if (REG_NOTES (insn))
3156 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3158 PATTERN (insn) = new_body;
3160 /* If we had a move insn but now we don't, rerecognize it. This will
3161 cause spurious re-recognition if the old move had a PARALLEL since
3162 the new one still will, but we can't call single_set without
3163 having put NEW_BODY into the insn and the re-recognition won't
3164 hurt in this rare case. */
3165 /* ??? Why this huge if statement - why don't we just rerecognize the
3169 && ((REG_P (SET_SRC (old_set))
3170 && (GET_CODE (new_body) != SET
3171 || !REG_P (SET_SRC (new_body))))
3172 /* If this was a load from or store to memory, compare
3173 the MEM in recog_data.operand to the one in the insn.
3174 If they are not equal, then rerecognize the insn. */
3176 && ((MEM_P (SET_SRC (old_set))
3177 && SET_SRC (old_set) != recog_data.operand[1])
3178 || (MEM_P (SET_DEST (old_set))
3179 && SET_DEST (old_set) != recog_data.operand[0])))
3180 /* If this was an add insn before, rerecognize. */
3181 || GET_CODE (SET_SRC (old_set)) == PLUS))
3183 int new_icode = recog (PATTERN (insn), insn, 0);
3185 INSN_CODE (insn) = icode;
3189 /* Restore the old body. If there were any changes to it, we made a copy
3190 of it while the changes were still in place, so we'll correctly return
3191 a modified insn below. */
3194 /* Restore the old body. */
3195 for (i = 0; i < recog_data.n_operands; i++)
3196 *recog_data.operand_loc[i] = orig_operand[i];
3197 for (i = 0; i < recog_data.n_dups; i++)
3198 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3201 /* Update all elimination pairs to reflect the status after the current
3202 insn. The changes we make were determined by the earlier call to
3203 elimination_effects.
3205 We also detect cases where register elimination cannot be done,
3206 namely, if a register would be both changed and referenced outside a MEM
3207 in the resulting insn since such an insn is often undefined and, even if
3208 not, we cannot know what meaning will be given to it. Note that it is
3209 valid to have a register used in an address in an insn that changes it
3210 (presumably with a pre- or post-increment or decrement).
3212 If anything changes, return nonzero. */
3214 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3216 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3217 ep->can_eliminate = 0;
3219 ep->ref_outside_mem = 0;
3221 if (ep->previous_offset != ep->offset)
3226 /* If we changed something, perform elimination in REG_NOTES. This is
3227 needed even when REPLACE is zero because a REG_DEAD note might refer
3228 to a register that we eliminate and could cause a different number
3229 of spill registers to be needed in the final reload pass than in
3231 if (val && REG_NOTES (insn) != 0)
3232 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3237 /* Loop through all elimination pairs.
3238 Recalculate the number not at initial offset.
3240 Compute the maximum offset (minimum offset if the stack does not
3241 grow downward) for each elimination pair. */
3244 update_eliminable_offsets (void)
3246 struct elim_table *ep;
3248 num_not_at_initial_offset = 0;
3249 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3251 ep->previous_offset = ep->offset;
3252 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3253 num_not_at_initial_offset++;
3257 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3258 replacement we currently believe is valid, mark it as not eliminable if X
3259 modifies DEST in any way other than by adding a constant integer to it.
3261 If DEST is the frame pointer, we do nothing because we assume that
3262 all assignments to the hard frame pointer are nonlocal gotos and are being
3263 done at a time when they are valid and do not disturb anything else.
3264 Some machines want to eliminate a fake argument pointer with either the
3265 frame or stack pointer. Assignments to the hard frame pointer must not
3266 prevent this elimination.
3268 Called via note_stores from reload before starting its passes to scan
3269 the insns of the function. */
3272 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3276 /* A SUBREG of a hard register here is just changing its mode. We should
3277 not see a SUBREG of an eliminable hard register, but check just in
3279 if (GET_CODE (dest) == SUBREG)
3280 dest = SUBREG_REG (dest);
3282 if (dest == hard_frame_pointer_rtx)
3285 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3286 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3287 && (GET_CODE (x) != SET
3288 || GET_CODE (SET_SRC (x)) != PLUS
3289 || XEXP (SET_SRC (x), 0) != dest
3290 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3292 reg_eliminate[i].can_eliminate_previous
3293 = reg_eliminate[i].can_eliminate = 0;
3298 /* Verify that the initial elimination offsets did not change since the
3299 last call to set_initial_elim_offsets. This is used to catch cases
3300 where something illegal happened during reload_as_needed that could
3301 cause incorrect code to be generated if we did not check for it. */
3304 verify_initial_elim_offsets (void)
3308 #ifdef ELIMINABLE_REGS
3309 struct elim_table *ep;
3311 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3313 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3314 gcc_assert (t == ep->initial_offset);
3317 INITIAL_FRAME_POINTER_OFFSET (t);
3318 gcc_assert (t == reg_eliminate[0].initial_offset);
3322 /* Reset all offsets on eliminable registers to their initial values. */
3325 set_initial_elim_offsets (void)
3327 struct elim_table *ep = reg_eliminate;
3329 #ifdef ELIMINABLE_REGS
3330 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3332 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3333 ep->previous_offset = ep->offset = ep->initial_offset;
3336 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3337 ep->previous_offset = ep->offset = ep->initial_offset;
3340 num_not_at_initial_offset = 0;
3343 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3346 set_initial_eh_label_offset (rtx label)
3348 set_label_offsets (label, NULL_RTX, 1);
3351 /* Initialize the known label offsets.
3352 Set a known offset for each forced label to be at the initial offset
3353 of each elimination. We do this because we assume that all
3354 computed jumps occur from a location where each elimination is
3355 at its initial offset.
3356 For all other labels, show that we don't know the offsets. */
3359 set_initial_label_offsets (void)
3362 memset (offsets_known_at, 0, num_labels);
3364 for (x = forced_labels; x; x = XEXP (x, 1))
3366 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3368 for_each_eh_label (set_initial_eh_label_offset);
3371 /* Set all elimination offsets to the known values for the code label given
3375 set_offsets_for_label (rtx insn)
3378 int label_nr = CODE_LABEL_NUMBER (insn);
3379 struct elim_table *ep;
3381 num_not_at_initial_offset = 0;
3382 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3384 ep->offset = ep->previous_offset
3385 = offsets_at[label_nr - first_label_num][i];
3386 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3387 num_not_at_initial_offset++;
3391 /* See if anything that happened changes which eliminations are valid.
3392 For example, on the SPARC, whether or not the frame pointer can
3393 be eliminated can depend on what registers have been used. We need
3394 not check some conditions again (such as flag_omit_frame_pointer)
3395 since they can't have changed. */
3398 update_eliminables (HARD_REG_SET *pset)
3400 int previous_frame_pointer_needed = frame_pointer_needed;
3401 struct elim_table *ep;
3403 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3404 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3405 #ifdef ELIMINABLE_REGS
3406 || ! CAN_ELIMINATE (ep->from, ep->to)
3409 ep->can_eliminate = 0;
3411 /* Look for the case where we have discovered that we can't replace
3412 register A with register B and that means that we will now be
3413 trying to replace register A with register C. This means we can
3414 no longer replace register C with register B and we need to disable
3415 such an elimination, if it exists. This occurs often with A == ap,
3416 B == sp, and C == fp. */
3418 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3420 struct elim_table *op;
3423 if (! ep->can_eliminate && ep->can_eliminate_previous)
3425 /* Find the current elimination for ep->from, if there is a
3427 for (op = reg_eliminate;
3428 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3429 if (op->from == ep->from && op->can_eliminate)
3435 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3437 for (op = reg_eliminate;
3438 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3439 if (op->from == new_to && op->to == ep->to)
3440 op->can_eliminate = 0;
3444 /* See if any registers that we thought we could eliminate the previous
3445 time are no longer eliminable. If so, something has changed and we
3446 must spill the register. Also, recompute the number of eliminable
3447 registers and see if the frame pointer is needed; it is if there is
3448 no elimination of the frame pointer that we can perform. */
3450 frame_pointer_needed = 1;
3451 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3453 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3454 && ep->to != HARD_FRAME_POINTER_REGNUM)
3455 frame_pointer_needed = 0;
3457 if (! ep->can_eliminate && ep->can_eliminate_previous)
3459 ep->can_eliminate_previous = 0;
3460 SET_HARD_REG_BIT (*pset, ep->from);
3465 /* If we didn't need a frame pointer last time, but we do now, spill
3466 the hard frame pointer. */
3467 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3468 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3471 /* Initialize the table of registers to eliminate. */
3474 init_elim_table (void)
3476 struct elim_table *ep;
3477 #ifdef ELIMINABLE_REGS
3478 const struct elim_table_1 *ep1;
3482 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3484 /* Does this function require a frame pointer? */
3486 frame_pointer_needed = (! flag_omit_frame_pointer
3487 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3488 and restore sp for alloca. So we can't eliminate
3489 the frame pointer in that case. At some point,
3490 we should improve this by emitting the
3491 sp-adjusting insns for this case. */
3492 || (current_function_calls_alloca
3493 && EXIT_IGNORE_STACK)
3494 || FRAME_POINTER_REQUIRED);
3498 #ifdef ELIMINABLE_REGS
3499 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3500 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3502 ep->from = ep1->from;
3504 ep->can_eliminate = ep->can_eliminate_previous
3505 = (CAN_ELIMINATE (ep->from, ep->to)
3506 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3509 reg_eliminate[0].from = reg_eliminate_1[0].from;
3510 reg_eliminate[0].to = reg_eliminate_1[0].to;
3511 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3512 = ! frame_pointer_needed;
3515 /* Count the number of eliminable registers and build the FROM and TO
3516 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3517 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3518 We depend on this. */
3519 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3521 num_eliminable += ep->can_eliminate;
3522 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3523 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3527 /* Kick all pseudos out of hard register REGNO.
3529 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3530 because we found we can't eliminate some register. In the case, no pseudos
3531 are allowed to be in the register, even if they are only in a block that
3532 doesn't require spill registers, unlike the case when we are spilling this
3533 hard reg to produce another spill register.
3535 Return nonzero if any pseudos needed to be kicked out. */
3538 spill_hard_reg (unsigned int regno, int cant_eliminate)
3544 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3545 regs_ever_live[regno] = 1;
3548 /* Spill every pseudo reg that was allocated to this reg
3549 or to something that overlaps this reg. */
3551 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3552 if (reg_renumber[i] >= 0
3553 && (unsigned int) reg_renumber[i] <= regno
3554 && ((unsigned int) reg_renumber[i]
3555 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3556 [PSEUDO_REGNO_MODE (i)]
3558 SET_REGNO_REG_SET (&spilled_pseudos, i);
3561 /* After find_reload_regs has been run for all insn that need reloads,
3562 and/or spill_hard_regs was called, this function is used to actually
3563 spill pseudo registers and try to reallocate them. It also sets up the
3564 spill_regs array for use by choose_reload_regs. */
3567 finish_spills (int global)
3569 struct insn_chain *chain;
3570 int something_changed = 0;
3572 reg_set_iterator rsi;
3574 /* Build the spill_regs array for the function. */
3575 /* If there are some registers still to eliminate and one of the spill regs
3576 wasn't ever used before, additional stack space may have to be
3577 allocated to store this register. Thus, we may have changed the offset
3578 between the stack and frame pointers, so mark that something has changed.
3580 One might think that we need only set VAL to 1 if this is a call-used
3581 register. However, the set of registers that must be saved by the
3582 prologue is not identical to the call-used set. For example, the
3583 register used by the call insn for the return PC is a call-used register,
3584 but must be saved by the prologue. */
3587 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3588 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3590 spill_reg_order[i] = n_spills;
3591 spill_regs[n_spills++] = i;
3592 if (num_eliminable && ! regs_ever_live[i])
3593 something_changed = 1;
3594 regs_ever_live[i] = 1;
3597 spill_reg_order[i] = -1;
3599 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3601 /* Record the current hard register the pseudo is allocated to in
3602 pseudo_previous_regs so we avoid reallocating it to the same
3603 hard reg in a later pass. */
3604 gcc_assert (reg_renumber[i] >= 0);
3606 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3607 /* Mark it as no longer having a hard register home. */
3608 reg_renumber[i] = -1;
3609 /* We will need to scan everything again. */
3610 something_changed = 1;
3613 /* Retry global register allocation if possible. */
3616 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3617 /* For every insn that needs reloads, set the registers used as spill
3618 regs in pseudo_forbidden_regs for every pseudo live across the
3620 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3622 EXECUTE_IF_SET_IN_REG_SET
3623 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3625 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3626 chain->used_spill_regs);
3628 EXECUTE_IF_SET_IN_REG_SET
3629 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3631 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3632 chain->used_spill_regs);
3636 /* Retry allocating the spilled pseudos. For each reg, merge the
3637 various reg sets that indicate which hard regs can't be used,
3638 and call retry_global_alloc.
3639 We change spill_pseudos here to only contain pseudos that did not
3640 get a new hard register. */
3641 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3642 if (reg_old_renumber[i] != reg_renumber[i])
3644 HARD_REG_SET forbidden;
3645 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3646 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3647 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3648 retry_global_alloc (i, forbidden);
3649 if (reg_renumber[i] >= 0)
3650 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3654 /* Fix up the register information in the insn chain.
3655 This involves deleting those of the spilled pseudos which did not get
3656 a new hard register home from the live_{before,after} sets. */
3657 for (chain = reload_insn_chain; chain; chain = chain->next)
3659 HARD_REG_SET used_by_pseudos;
3660 HARD_REG_SET used_by_pseudos2;
3662 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3663 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3665 /* Mark any unallocated hard regs as available for spills. That
3666 makes inheritance work somewhat better. */
3667 if (chain->need_reload)
3669 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3670 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3671 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3673 /* Save the old value for the sanity test below. */
3674 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3676 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3677 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3678 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3679 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3681 /* Make sure we only enlarge the set. */
3682 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3688 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3689 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3691 int regno = reg_renumber[i];
3692 if (reg_old_renumber[i] == regno)
3695 alter_reg (i, reg_old_renumber[i]);
3696 reg_old_renumber[i] = regno;
3700 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3702 fprintf (dump_file, " Register %d now in %d.\n\n",
3703 i, reg_renumber[i]);
3707 return something_changed;
3710 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3713 scan_paradoxical_subregs (rtx x)
3717 enum rtx_code code = GET_CODE (x);
3727 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3735 if (REG_P (SUBREG_REG (x))
3736 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3737 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3738 = GET_MODE_SIZE (GET_MODE (x));
3745 fmt = GET_RTX_FORMAT (code);
3746 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3749 scan_paradoxical_subregs (XEXP (x, i));
3750 else if (fmt[i] == 'E')
3753 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3754 scan_paradoxical_subregs (XVECEXP (x, i, j));
3759 /* Reload pseudo-registers into hard regs around each insn as needed.
3760 Additional register load insns are output before the insn that needs it
3761 and perhaps store insns after insns that modify the reloaded pseudo reg.
3763 reg_last_reload_reg and reg_reloaded_contents keep track of
3764 which registers are already available in reload registers.
3765 We update these for the reloads that we perform,
3766 as the insns are scanned. */
3769 reload_as_needed (int live_known)
3771 struct insn_chain *chain;
3772 #if defined (AUTO_INC_DEC)
3777 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3778 memset (spill_reg_store, 0, sizeof spill_reg_store);
3779 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3780 reg_has_output_reload = xmalloc (max_regno);
3781 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3782 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3784 set_initial_elim_offsets ();
3786 for (chain = reload_insn_chain; chain; chain = chain->next)
3789 rtx insn = chain->insn;
3790 rtx old_next = NEXT_INSN (insn);
3792 /* If we pass a label, copy the offsets from the label information
3793 into the current offsets of each elimination. */
3795 set_offsets_for_label (insn);
3797 else if (INSN_P (insn))
3799 rtx oldpat = copy_rtx (PATTERN (insn));
3801 /* If this is a USE and CLOBBER of a MEM, ensure that any
3802 references to eliminable registers have been removed. */
3804 if ((GET_CODE (PATTERN (insn)) == USE
3805 || GET_CODE (PATTERN (insn)) == CLOBBER)
3806 && MEM_P (XEXP (PATTERN (insn), 0)))
3807 XEXP (XEXP (PATTERN (insn), 0), 0)
3808 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3809 GET_MODE (XEXP (PATTERN (insn), 0)),
3812 /* If we need to do register elimination processing, do so.
3813 This might delete the insn, in which case we are done. */
3814 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3816 eliminate_regs_in_insn (insn, 1);
3819 update_eliminable_offsets ();
3824 /* If need_elim is nonzero but need_reload is zero, one might think
3825 that we could simply set n_reloads to 0. However, find_reloads
3826 could have done some manipulation of the insn (such as swapping
3827 commutative operands), and these manipulations are lost during
3828 the first pass for every insn that needs register elimination.
3829 So the actions of find_reloads must be redone here. */
3831 if (! chain->need_elim && ! chain->need_reload
3832 && ! chain->need_operand_change)
3834 /* First find the pseudo regs that must be reloaded for this insn.
3835 This info is returned in the tables reload_... (see reload.h).
3836 Also modify the body of INSN by substituting RELOAD
3837 rtx's for those pseudo regs. */
3840 memset (reg_has_output_reload, 0, max_regno);
3841 CLEAR_HARD_REG_SET (reg_is_output_reload);
3843 find_reloads (insn, 1, spill_indirect_levels, live_known,
3849 rtx next = NEXT_INSN (insn);
3852 prev = PREV_INSN (insn);
3854 /* Now compute which reload regs to reload them into. Perhaps
3855 reusing reload regs from previous insns, or else output
3856 load insns to reload them. Maybe output store insns too.
3857 Record the choices of reload reg in reload_reg_rtx. */
3858 choose_reload_regs (chain);
3860 /* Merge any reloads that we didn't combine for fear of
3861 increasing the number of spill registers needed but now
3862 discover can be safely merged. */
3863 if (SMALL_REGISTER_CLASSES)
3864 merge_assigned_reloads (insn);
3866 /* Generate the insns to reload operands into or out of
3867 their reload regs. */
3868 emit_reload_insns (chain);
3870 /* Substitute the chosen reload regs from reload_reg_rtx
3871 into the insn's body (or perhaps into the bodies of other
3872 load and store insn that we just made for reloading
3873 and that we moved the structure into). */
3874 subst_reloads (insn);
3876 /* If this was an ASM, make sure that all the reload insns
3877 we have generated are valid. If not, give an error
3880 if (asm_noperands (PATTERN (insn)) >= 0)
3881 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3882 if (p != insn && INSN_P (p)
3883 && GET_CODE (PATTERN (p)) != USE
3884 && (recog_memoized (p) < 0
3885 || (extract_insn (p), ! constrain_operands (1))))
3887 error_for_asm (insn,
3888 "%<asm%> operand requires "
3889 "impossible reload");
3894 if (num_eliminable && chain->need_elim)
3895 update_eliminable_offsets ();
3897 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3898 is no longer validly lying around to save a future reload.
3899 Note that this does not detect pseudos that were reloaded
3900 for this insn in order to be stored in
3901 (obeying register constraints). That is correct; such reload
3902 registers ARE still valid. */
3903 note_stores (oldpat, forget_old_reloads_1, NULL);
3905 /* There may have been CLOBBER insns placed after INSN. So scan
3906 between INSN and NEXT and use them to forget old reloads. */
3907 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3908 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3909 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3912 /* Likewise for regs altered by auto-increment in this insn.
3913 REG_INC notes have been changed by reloading:
3914 find_reloads_address_1 records substitutions for them,
3915 which have been performed by subst_reloads above. */
3916 for (i = n_reloads - 1; i >= 0; i--)
3918 rtx in_reg = rld[i].in_reg;
3921 enum rtx_code code = GET_CODE (in_reg);
3922 /* PRE_INC / PRE_DEC will have the reload register ending up
3923 with the same value as the stack slot, but that doesn't
3924 hold true for POST_INC / POST_DEC. Either we have to
3925 convert the memory access to a true POST_INC / POST_DEC,
3926 or we can't use the reload register for inheritance. */
3927 if ((code == POST_INC || code == POST_DEC)
3928 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3929 REGNO (rld[i].reg_rtx))
3930 /* Make sure it is the inc/dec pseudo, and not
3931 some other (e.g. output operand) pseudo. */
3932 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3933 == REGNO (XEXP (in_reg, 0))))
3936 rtx reload_reg = rld[i].reg_rtx;
3937 enum machine_mode mode = GET_MODE (reload_reg);
3941 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3943 /* We really want to ignore REG_INC notes here, so
3944 use PATTERN (p) as argument to reg_set_p . */
3945 if (reg_set_p (reload_reg, PATTERN (p)))
3947 n = count_occurrences (PATTERN (p), reload_reg, 0);
3952 n = validate_replace_rtx (reload_reg,
3953 gen_rtx_fmt_e (code,
3958 /* We must also verify that the constraints
3959 are met after the replacement. */
3962 n = constrain_operands (1);
3966 /* If the constraints were not met, then
3967 undo the replacement. */
3970 validate_replace_rtx (gen_rtx_fmt_e (code,
3983 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3985 /* Mark this as having an output reload so that the
3986 REG_INC processing code below won't invalidate
3987 the reload for inheritance. */
3988 SET_HARD_REG_BIT (reg_is_output_reload,
3989 REGNO (reload_reg));
3990 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3993 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3996 else if ((code == PRE_INC || code == PRE_DEC)
3997 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3998 REGNO (rld[i].reg_rtx))
3999 /* Make sure it is the inc/dec pseudo, and not
4000 some other (e.g. output operand) pseudo. */
4001 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4002 == REGNO (XEXP (in_reg, 0))))
4004 SET_HARD_REG_BIT (reg_is_output_reload,
4005 REGNO (rld[i].reg_rtx));
4006 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4010 /* If a pseudo that got a hard register is auto-incremented,
4011 we must purge records of copying it into pseudos without
4013 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4014 if (REG_NOTE_KIND (x) == REG_INC)
4016 /* See if this pseudo reg was reloaded in this insn.
4017 If so, its last-reload info is still valid
4018 because it is based on this insn's reload. */
4019 for (i = 0; i < n_reloads; i++)
4020 if (rld[i].out == XEXP (x, 0))
4024 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4028 /* A reload reg's contents are unknown after a label. */
4030 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4032 /* Don't assume a reload reg is still good after a call insn
4033 if it is a call-used reg, or if it contains a value that will
4034 be partially clobbered by the call. */
4035 else if (CALL_P (insn))
4037 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4038 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4043 free (reg_last_reload_reg);
4044 free (reg_has_output_reload);
4047 /* Discard all record of any value reloaded from X,
4048 or reloaded in X from someplace else;
4049 unless X is an output reload reg of the current insn.
4051 X may be a hard reg (the reload reg)
4052 or it may be a pseudo reg that was reloaded from. */
4055 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4056 void *data ATTRIBUTE_UNUSED)
4061 /* note_stores does give us subregs of hard regs,
4062 subreg_regno_offset requires a hard reg. */
4063 while (GET_CODE (x) == SUBREG)
4065 /* We ignore the subreg offset when calculating the regno,
4066 because we are using the entire underlying hard register
4076 if (regno >= FIRST_PSEUDO_REGISTER)
4082 nr = hard_regno_nregs[regno][GET_MODE (x)];
4083 /* Storing into a spilled-reg invalidates its contents.
4084 This can happen if a block-local pseudo is allocated to that reg
4085 and it wasn't spilled because this block's total need is 0.
4086 Then some insn might have an optional reload and use this reg. */
4087 for (i = 0; i < nr; i++)
4088 /* But don't do this if the reg actually serves as an output
4089 reload reg in the current instruction. */
4091 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4093 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4094 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4095 spill_reg_store[regno + i] = 0;
4099 /* Since value of X has changed,
4100 forget any value previously copied from it. */
4103 /* But don't forget a copy if this is the output reload
4104 that establishes the copy's validity. */
4105 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4106 reg_last_reload_reg[regno + nr] = 0;
4109 /* The following HARD_REG_SETs indicate when each hard register is
4110 used for a reload of various parts of the current insn. */
4112 /* If reg is unavailable for all reloads. */
4113 static HARD_REG_SET reload_reg_unavailable;
4114 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4115 static HARD_REG_SET reload_reg_used;
4116 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4117 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4118 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4119 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4120 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4121 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4122 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4123 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4124 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4125 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4126 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4127 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4128 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4129 static HARD_REG_SET reload_reg_used_in_op_addr;
4130 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4131 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4132 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4133 static HARD_REG_SET reload_reg_used_in_insn;
4134 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4135 static HARD_REG_SET reload_reg_used_in_other_addr;
4137 /* If reg is in use as a reload reg for any sort of reload. */
4138 static HARD_REG_SET reload_reg_used_at_all;
4140 /* If reg is use as an inherited reload. We just mark the first register
4142 static HARD_REG_SET reload_reg_used_for_inherit;
4144 /* Records which hard regs are used in any way, either as explicit use or
4145 by being allocated to a pseudo during any point of the current insn. */
4146 static HARD_REG_SET reg_used_in_insn;
4148 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4149 TYPE. MODE is used to indicate how many consecutive regs are
4153 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4154 enum machine_mode mode)
4156 unsigned int nregs = hard_regno_nregs[regno][mode];
4159 for (i = regno; i < nregs + regno; i++)
4164 SET_HARD_REG_BIT (reload_reg_used, i);
4167 case RELOAD_FOR_INPUT_ADDRESS:
4168 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4171 case RELOAD_FOR_INPADDR_ADDRESS:
4172 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4175 case RELOAD_FOR_OUTPUT_ADDRESS:
4176 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4179 case RELOAD_FOR_OUTADDR_ADDRESS:
4180 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4183 case RELOAD_FOR_OPERAND_ADDRESS:
4184 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4187 case RELOAD_FOR_OPADDR_ADDR:
4188 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4191 case RELOAD_FOR_OTHER_ADDRESS:
4192 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4195 case RELOAD_FOR_INPUT:
4196 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4199 case RELOAD_FOR_OUTPUT:
4200 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4203 case RELOAD_FOR_INSN:
4204 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4208 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4212 /* Similarly, but show REGNO is no longer in use for a reload. */
4215 clear_reload_reg_in_use (unsigned int regno, int opnum,
4216 enum reload_type type, enum machine_mode mode)
4218 unsigned int nregs = hard_regno_nregs[regno][mode];
4219 unsigned int start_regno, end_regno, r;
4221 /* A complication is that for some reload types, inheritance might
4222 allow multiple reloads of the same types to share a reload register.
4223 We set check_opnum if we have to check only reloads with the same
4224 operand number, and check_any if we have to check all reloads. */
4225 int check_opnum = 0;
4227 HARD_REG_SET *used_in_set;
4232 used_in_set = &reload_reg_used;
4235 case RELOAD_FOR_INPUT_ADDRESS:
4236 used_in_set = &reload_reg_used_in_input_addr[opnum];
4239 case RELOAD_FOR_INPADDR_ADDRESS:
4241 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4244 case RELOAD_FOR_OUTPUT_ADDRESS:
4245 used_in_set = &reload_reg_used_in_output_addr[opnum];
4248 case RELOAD_FOR_OUTADDR_ADDRESS:
4250 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4253 case RELOAD_FOR_OPERAND_ADDRESS:
4254 used_in_set = &reload_reg_used_in_op_addr;
4257 case RELOAD_FOR_OPADDR_ADDR:
4259 used_in_set = &reload_reg_used_in_op_addr_reload;
4262 case RELOAD_FOR_OTHER_ADDRESS:
4263 used_in_set = &reload_reg_used_in_other_addr;
4267 case RELOAD_FOR_INPUT:
4268 used_in_set = &reload_reg_used_in_input[opnum];
4271 case RELOAD_FOR_OUTPUT:
4272 used_in_set = &reload_reg_used_in_output[opnum];
4275 case RELOAD_FOR_INSN:
4276 used_in_set = &reload_reg_used_in_insn;
4281 /* We resolve conflicts with remaining reloads of the same type by
4282 excluding the intervals of reload registers by them from the
4283 interval of freed reload registers. Since we only keep track of
4284 one set of interval bounds, we might have to exclude somewhat
4285 more than what would be necessary if we used a HARD_REG_SET here.
4286 But this should only happen very infrequently, so there should
4287 be no reason to worry about it. */
4289 start_regno = regno;
4290 end_regno = regno + nregs;
4291 if (check_opnum || check_any)
4293 for (i = n_reloads - 1; i >= 0; i--)
4295 if (rld[i].when_needed == type
4296 && (check_any || rld[i].opnum == opnum)
4299 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4300 unsigned int conflict_end
4302 + hard_regno_nregs[conflict_start][rld[i].mode]);
4304 /* If there is an overlap with the first to-be-freed register,
4305 adjust the interval start. */
4306 if (conflict_start <= start_regno && conflict_end > start_regno)
4307 start_regno = conflict_end;
4308 /* Otherwise, if there is a conflict with one of the other
4309 to-be-freed registers, adjust the interval end. */
4310 if (conflict_start > start_regno && conflict_start < end_regno)
4311 end_regno = conflict_start;
4316 for (r = start_regno; r < end_regno; r++)
4317 CLEAR_HARD_REG_BIT (*used_in_set, r);
4320 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4321 specified by OPNUM and TYPE. */
4324 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4328 /* In use for a RELOAD_OTHER means it's not available for anything. */
4329 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4330 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4336 /* In use for anything means we can't use it for RELOAD_OTHER. */
4337 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4338 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4339 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4340 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4343 for (i = 0; i < reload_n_operands; i++)
4344 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4345 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4346 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4347 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4348 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4349 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4354 case RELOAD_FOR_INPUT:
4355 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4356 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4362 /* If it is used for some other input, can't use it. */
4363 for (i = 0; i < reload_n_operands; i++)
4364 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4367 /* If it is used in a later operand's address, can't use it. */
4368 for (i = opnum + 1; i < reload_n_operands; i++)
4369 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4370 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4375 case RELOAD_FOR_INPUT_ADDRESS:
4376 /* Can't use a register if it is used for an input address for this
4377 operand or used as an input in an earlier one. */
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4382 for (i = 0; i < opnum; i++)
4383 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4388 case RELOAD_FOR_INPADDR_ADDRESS:
4389 /* Can't use a register if it is used for an input address
4390 for this operand or used as an input in an earlier
4392 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4395 for (i = 0; i < opnum; i++)
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4401 case RELOAD_FOR_OUTPUT_ADDRESS:
4402 /* Can't use a register if it is used for an output address for this
4403 operand or used as an output in this or a later operand. Note
4404 that multiple output operands are emitted in reverse order, so
4405 the conflicting ones are those with lower indices. */
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4409 for (i = 0; i <= opnum; i++)
4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4415 case RELOAD_FOR_OUTADDR_ADDRESS:
4416 /* Can't use a register if it is used for an output address
4417 for this operand or used as an output in this or a
4418 later operand. Note that multiple output operands are
4419 emitted in reverse order, so the conflicting ones are
4420 those with lower indices. */
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4424 for (i = 0; i <= opnum; i++)
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4430 case RELOAD_FOR_OPERAND_ADDRESS:
4431 for (i = 0; i < reload_n_operands; i++)
4432 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4435 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4436 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4438 case RELOAD_FOR_OPADDR_ADDR:
4439 for (i = 0; i < reload_n_operands; i++)
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4443 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4445 case RELOAD_FOR_OUTPUT:
4446 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4447 outputs, or an operand address for this or an earlier output.
4448 Note that multiple output operands are emitted in reverse order,
4449 so the conflicting ones are those with higher indices. */
4450 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4453 for (i = 0; i < reload_n_operands; i++)
4454 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4457 for (i = opnum; i < reload_n_operands; i++)
4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4459 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4464 case RELOAD_FOR_INSN:
4465 for (i = 0; i < reload_n_operands; i++)
4466 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4467 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4470 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4471 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4473 case RELOAD_FOR_OTHER_ADDRESS:
4474 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4481 /* Return 1 if the value in reload reg REGNO, as used by a reload
4482 needed for the part of the insn specified by OPNUM and TYPE,
4483 is still available in REGNO at the end of the insn.
4485 We can assume that the reload reg was already tested for availability
4486 at the time it is needed, and we should not check this again,
4487 in case the reg has already been marked in use. */
4490 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4497 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4498 its value must reach the end. */
4501 /* If this use is for part of the insn,
4502 its value reaches if no subsequent part uses the same register.
4503 Just like the above function, don't try to do this with lots
4506 case RELOAD_FOR_OTHER_ADDRESS:
4507 /* Here we check for everything else, since these don't conflict
4508 with anything else and everything comes later. */
4510 for (i = 0; i < reload_n_operands; i++)
4511 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4512 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4513 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4514 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4516 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4519 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4520 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4521 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4522 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4524 case RELOAD_FOR_INPUT_ADDRESS:
4525 case RELOAD_FOR_INPADDR_ADDRESS:
4526 /* Similar, except that we check only for this and subsequent inputs
4527 and the address of only subsequent inputs and we do not need
4528 to check for RELOAD_OTHER objects since they are known not to
4531 for (i = opnum; i < reload_n_operands; i++)
4532 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4535 for (i = opnum + 1; i < reload_n_operands; i++)
4536 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4537 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4540 for (i = 0; i < reload_n_operands; i++)
4541 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4542 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4546 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4549 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4550 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4551 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4553 case RELOAD_FOR_INPUT:
4554 /* Similar to input address, except we start at the next operand for
4555 both input and input address and we do not check for
4556 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4559 for (i = opnum + 1; i < reload_n_operands; i++)
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4561 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4562 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4565 /* ... fall through ... */
4567 case RELOAD_FOR_OPERAND_ADDRESS:
4568 /* Check outputs and their addresses. */
4570 for (i = 0; i < reload_n_operands; i++)
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4573 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4576 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4578 case RELOAD_FOR_OPADDR_ADDR:
4579 for (i = 0; i < reload_n_operands; i++)
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4581 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4582 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4585 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4586 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4587 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4589 case RELOAD_FOR_INSN:
4590 /* These conflict with other outputs with RELOAD_OTHER. So
4591 we need only check for output addresses. */
4593 opnum = reload_n_operands;
4595 /* ... fall through ... */
4597 case RELOAD_FOR_OUTPUT:
4598 case RELOAD_FOR_OUTPUT_ADDRESS:
4599 case RELOAD_FOR_OUTADDR_ADDRESS:
4600 /* We already know these can't conflict with a later output. So the
4601 only thing to check are later output addresses.
4602 Note that multiple output operands are emitted in reverse order,
4603 so the conflicting ones are those with lower indices. */
4604 for (i = 0; i < opnum; i++)
4605 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4606 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4616 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4619 This function uses the same algorithm as reload_reg_free_p above. */
4622 reloads_conflict (int r1, int r2)
4624 enum reload_type r1_type = rld[r1].when_needed;
4625 enum reload_type r2_type = rld[r2].when_needed;
4626 int r1_opnum = rld[r1].opnum;
4627 int r2_opnum = rld[r2].opnum;
4629 /* RELOAD_OTHER conflicts with everything. */
4630 if (r2_type == RELOAD_OTHER)
4633 /* Otherwise, check conflicts differently for each type. */
4637 case RELOAD_FOR_INPUT:
4638 return (r2_type == RELOAD_FOR_INSN
4639 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4640 || r2_type == RELOAD_FOR_OPADDR_ADDR
4641 || r2_type == RELOAD_FOR_INPUT
4642 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4643 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4644 && r2_opnum > r1_opnum));
4646 case RELOAD_FOR_INPUT_ADDRESS:
4647 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4648 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4650 case RELOAD_FOR_INPADDR_ADDRESS:
4651 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4652 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4654 case RELOAD_FOR_OUTPUT_ADDRESS:
4655 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4656 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4658 case RELOAD_FOR_OUTADDR_ADDRESS:
4659 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4660 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4662 case RELOAD_FOR_OPERAND_ADDRESS:
4663 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4664 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4666 case RELOAD_FOR_OPADDR_ADDR:
4667 return (r2_type == RELOAD_FOR_INPUT
4668 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4670 case RELOAD_FOR_OUTPUT:
4671 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4672 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4673 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4674 && r2_opnum >= r1_opnum));
4676 case RELOAD_FOR_INSN:
4677 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4678 || r2_type == RELOAD_FOR_INSN
4679 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4681 case RELOAD_FOR_OTHER_ADDRESS:
4682 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4692 /* Indexed by reload number, 1 if incoming value
4693 inherited from previous insns. */
4694 static char reload_inherited[MAX_RELOADS];
4696 /* For an inherited reload, this is the insn the reload was inherited from,
4697 if we know it. Otherwise, this is 0. */
4698 static rtx reload_inheritance_insn[MAX_RELOADS];
4700 /* If nonzero, this is a place to get the value of the reload,
4701 rather than using reload_in. */
4702 static rtx reload_override_in[MAX_RELOADS];
4704 /* For each reload, the hard register number of the register used,
4705 or -1 if we did not need a register for this reload. */
4706 static int reload_spill_index[MAX_RELOADS];
4708 /* Subroutine of free_for_value_p, used to check a single register.
4709 START_REGNO is the starting regno of the full reload register
4710 (possibly comprising multiple hard registers) that we are considering. */
4713 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4714 enum reload_type type, rtx value, rtx out,
4715 int reloadnum, int ignore_address_reloads)
4718 /* Set if we see an input reload that must not share its reload register
4719 with any new earlyclobber, but might otherwise share the reload
4720 register with an output or input-output reload. */
4721 int check_earlyclobber = 0;
4725 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4728 if (out == const0_rtx)
4734 /* We use some pseudo 'time' value to check if the lifetimes of the
4735 new register use would overlap with the one of a previous reload
4736 that is not read-only or uses a different value.
4737 The 'time' used doesn't have to be linear in any shape or form, just
4739 Some reload types use different 'buckets' for each operand.
4740 So there are MAX_RECOG_OPERANDS different time values for each
4742 We compute TIME1 as the time when the register for the prospective
4743 new reload ceases to be live, and TIME2 for each existing
4744 reload as the time when that the reload register of that reload
4746 Where there is little to be gained by exact lifetime calculations,
4747 we just make conservative assumptions, i.e. a longer lifetime;
4748 this is done in the 'default:' cases. */
4751 case RELOAD_FOR_OTHER_ADDRESS:
4752 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4753 time1 = copy ? 0 : 1;
4756 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4758 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4759 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4760 respectively, to the time values for these, we get distinct time
4761 values. To get distinct time values for each operand, we have to
4762 multiply opnum by at least three. We round that up to four because
4763 multiply by four is often cheaper. */
4764 case RELOAD_FOR_INPADDR_ADDRESS:
4765 time1 = opnum * 4 + 2;
4767 case RELOAD_FOR_INPUT_ADDRESS:
4768 time1 = opnum * 4 + 3;
4770 case RELOAD_FOR_INPUT:
4771 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4772 executes (inclusive). */
4773 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4775 case RELOAD_FOR_OPADDR_ADDR:
4777 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4778 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4780 case RELOAD_FOR_OPERAND_ADDRESS:
4781 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4783 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4785 case RELOAD_FOR_OUTADDR_ADDRESS:
4786 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4788 case RELOAD_FOR_OUTPUT_ADDRESS:
4789 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4792 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4795 for (i = 0; i < n_reloads; i++)
4797 rtx reg = rld[i].reg_rtx;
4798 if (reg && REG_P (reg)
4799 && ((unsigned) regno - true_regnum (reg)
4800 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4803 rtx other_input = rld[i].in;
4805 /* If the other reload loads the same input value, that
4806 will not cause a conflict only if it's loading it into
4807 the same register. */
4808 if (true_regnum (reg) != start_regno)
4809 other_input = NULL_RTX;
4810 if (! other_input || ! rtx_equal_p (other_input, value)
4811 || rld[i].out || out)
4814 switch (rld[i].when_needed)
4816 case RELOAD_FOR_OTHER_ADDRESS:
4819 case RELOAD_FOR_INPADDR_ADDRESS:
4820 /* find_reloads makes sure that a
4821 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4822 by at most one - the first -
4823 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4824 address reload is inherited, the address address reload
4825 goes away, so we can ignore this conflict. */
4826 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4827 && ignore_address_reloads
4828 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4829 Then the address address is still needed to store
4830 back the new address. */
4831 && ! rld[reloadnum].out)
4833 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4834 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4836 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4837 && ignore_address_reloads
4838 /* Unless we are reloading an auto_inc expression. */
4839 && ! rld[reloadnum].out)
4841 time2 = rld[i].opnum * 4 + 2;
4843 case RELOAD_FOR_INPUT_ADDRESS:
4844 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4845 && ignore_address_reloads
4846 && ! rld[reloadnum].out)
4848 time2 = rld[i].opnum * 4 + 3;
4850 case RELOAD_FOR_INPUT:
4851 time2 = rld[i].opnum * 4 + 4;
4852 check_earlyclobber = 1;
4854 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4855 == MAX_RECOG_OPERAND * 4 */
4856 case RELOAD_FOR_OPADDR_ADDR:
4857 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4858 && ignore_address_reloads
4859 && ! rld[reloadnum].out)
4861 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4863 case RELOAD_FOR_OPERAND_ADDRESS:
4864 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4865 check_earlyclobber = 1;
4867 case RELOAD_FOR_INSN:
4868 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4870 case RELOAD_FOR_OUTPUT:
4871 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4872 instruction is executed. */
4873 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4875 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4876 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4878 case RELOAD_FOR_OUTADDR_ADDRESS:
4879 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4880 && ignore_address_reloads
4881 && ! rld[reloadnum].out)
4883 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4885 case RELOAD_FOR_OUTPUT_ADDRESS:
4886 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4889 /* If there is no conflict in the input part, handle this
4890 like an output reload. */
4891 if (! rld[i].in || rtx_equal_p (other_input, value))
4893 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4894 /* Earlyclobbered outputs must conflict with inputs. */
4895 if (earlyclobber_operand_p (rld[i].out))
4896 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4901 /* RELOAD_OTHER might be live beyond instruction execution,
4902 but this is not obvious when we set time2 = 1. So check
4903 here if there might be a problem with the new reload
4904 clobbering the register used by the RELOAD_OTHER. */
4912 && (! rld[i].in || rld[i].out
4913 || ! rtx_equal_p (other_input, value)))
4914 || (out && rld[reloadnum].out_reg
4915 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4921 /* Earlyclobbered outputs must conflict with inputs. */
4922 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4928 /* Return 1 if the value in reload reg REGNO, as used by a reload
4929 needed for the part of the insn specified by OPNUM and TYPE,
4930 may be used to load VALUE into it.
4932 MODE is the mode in which the register is used, this is needed to
4933 determine how many hard regs to test.
4935 Other read-only reloads with the same value do not conflict
4936 unless OUT is nonzero and these other reloads have to live while
4937 output reloads live.
4938 If OUT is CONST0_RTX, this is a special case: it means that the
4939 test should not be for using register REGNO as reload register, but
4940 for copying from register REGNO into the reload register.
4942 RELOADNUM is the number of the reload we want to load this value for;
4943 a reload does not conflict with itself.
4945 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4946 reloads that load an address for the very reload we are considering.
4948 The caller has to make sure that there is no conflict with the return
4952 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4953 enum reload_type type, rtx value, rtx out, int reloadnum,
4954 int ignore_address_reloads)
4956 int nregs = hard_regno_nregs[regno][mode];
4958 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4959 value, out, reloadnum,
4960 ignore_address_reloads))
4965 /* Return nonzero if the rtx X is invariant over the current function. */
4966 /* ??? Actually, the places where we use this expect exactly what is
4967 tested here, and not everything that is function invariant. In
4968 particular, the frame pointer and arg pointer are special cased;
4969 pic_offset_table_rtx is not, and we must not spill these things to
4973 function_invariant_p (rtx x)
4977 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4979 if (GET_CODE (x) == PLUS
4980 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4981 && CONSTANT_P (XEXP (x, 1)))
4986 /* Determine whether the reload reg X overlaps any rtx'es used for
4987 overriding inheritance. Return nonzero if so. */
4990 conflicts_with_override (rtx x)
4993 for (i = 0; i < n_reloads; i++)
4994 if (reload_override_in[i]
4995 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5000 /* Give an error message saying we failed to find a reload for INSN,
5001 and clear out reload R. */
5003 failed_reload (rtx insn, int r)
5005 if (asm_noperands (PATTERN (insn)) < 0)
5006 /* It's the compiler's fault. */
5007 fatal_insn ("could not find a spill register", insn);
5009 /* It's the user's fault; the operand's mode and constraint
5010 don't match. Disable this reload so we don't crash in final. */
5011 error_for_asm (insn,
5012 "%<asm%> operand constraint incompatible with operand size");
5016 rld[r].optional = 1;
5017 rld[r].secondary_p = 1;
5020 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5021 for reload R. If it's valid, get an rtx for it. Return nonzero if
5024 set_reload_reg (int i, int r)
5027 rtx reg = spill_reg_rtx[i];
5029 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5030 spill_reg_rtx[i] = reg
5031 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5033 regno = true_regnum (reg);
5035 /* Detect when the reload reg can't hold the reload mode.
5036 This used to be one `if', but Sequent compiler can't handle that. */
5037 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5039 enum machine_mode test_mode = VOIDmode;
5041 test_mode = GET_MODE (rld[r].in);
5042 /* If rld[r].in has VOIDmode, it means we will load it
5043 in whatever mode the reload reg has: to wit, rld[r].mode.
5044 We have already tested that for validity. */
5045 /* Aside from that, we need to test that the expressions
5046 to reload from or into have modes which are valid for this
5047 reload register. Otherwise the reload insns would be invalid. */
5048 if (! (rld[r].in != 0 && test_mode != VOIDmode
5049 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5050 if (! (rld[r].out != 0
5051 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5053 /* The reg is OK. */
5056 /* Mark as in use for this insn the reload regs we use
5058 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5059 rld[r].when_needed, rld[r].mode);
5061 rld[r].reg_rtx = reg;
5062 reload_spill_index[r] = spill_regs[i];
5069 /* Find a spill register to use as a reload register for reload R.
5070 LAST_RELOAD is nonzero if this is the last reload for the insn being
5073 Set rld[R].reg_rtx to the register allocated.
5075 We return 1 if successful, or 0 if we couldn't find a spill reg and
5076 we didn't change anything. */
5079 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5084 /* If we put this reload ahead, thinking it is a group,
5085 then insist on finding a group. Otherwise we can grab a
5086 reg that some other reload needs.
5087 (That can happen when we have a 68000 DATA_OR_FP_REG
5088 which is a group of data regs or one fp reg.)
5089 We need not be so restrictive if there are no more reloads
5092 ??? Really it would be nicer to have smarter handling
5093 for that kind of reg class, where a problem like this is normal.
5094 Perhaps those classes should be avoided for reloading
5095 by use of more alternatives. */
5097 int force_group = rld[r].nregs > 1 && ! last_reload;
5099 /* If we want a single register and haven't yet found one,
5100 take any reg in the right class and not in use.
5101 If we want a consecutive group, here is where we look for it.
5103 We use two passes so we can first look for reload regs to
5104 reuse, which are already in use for other reloads in this insn,
5105 and only then use additional registers.
5106 I think that maximizing reuse is needed to make sure we don't
5107 run out of reload regs. Suppose we have three reloads, and
5108 reloads A and B can share regs. These need two regs.
5109 Suppose A and B are given different regs.
5110 That leaves none for C. */
5111 for (pass = 0; pass < 2; pass++)
5113 /* I is the index in spill_regs.
5114 We advance it round-robin between insns to use all spill regs
5115 equally, so that inherited reloads have a chance
5116 of leapfrogging each other. */
5120 for (count = 0; count < n_spills; count++)
5122 int class = (int) rld[r].class;
5128 regnum = spill_regs[i];
5130 if ((reload_reg_free_p (regnum, rld[r].opnum,
5133 /* We check reload_reg_used to make sure we
5134 don't clobber the return register. */
5135 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5136 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5137 rld[r].when_needed, rld[r].in,
5139 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5140 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5141 /* Look first for regs to share, then for unshared. But
5142 don't share regs used for inherited reloads; they are
5143 the ones we want to preserve. */
5145 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5147 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5150 int nr = hard_regno_nregs[regnum][rld[r].mode];
5151 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5152 (on 68000) got us two FP regs. If NR is 1,
5153 we would reject both of them. */
5156 /* If we need only one reg, we have already won. */
5159 /* But reject a single reg if we demand a group. */
5164 /* Otherwise check that as many consecutive regs as we need
5165 are available here. */
5168 int regno = regnum + nr - 1;
5169 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5170 && spill_reg_order[regno] >= 0
5171 && reload_reg_free_p (regno, rld[r].opnum,
5172 rld[r].when_needed)))
5181 /* If we found something on pass 1, omit pass 2. */
5182 if (count < n_spills)
5186 /* We should have found a spill register by now. */
5187 if (count >= n_spills)
5190 /* I is the index in SPILL_REG_RTX of the reload register we are to
5191 allocate. Get an rtx for it and find its register number. */
5193 return set_reload_reg (i, r);
5196 /* Initialize all the tables needed to allocate reload registers.
5197 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5198 is the array we use to restore the reg_rtx field for every reload. */
5201 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5205 for (i = 0; i < n_reloads; i++)
5206 rld[i].reg_rtx = save_reload_reg_rtx[i];
5208 memset (reload_inherited, 0, MAX_RELOADS);
5209 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5210 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5212 CLEAR_HARD_REG_SET (reload_reg_used);
5213 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5214 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5215 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5216 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5217 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5219 CLEAR_HARD_REG_SET (reg_used_in_insn);
5222 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5223 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5224 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5225 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5226 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5227 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5230 for (i = 0; i < reload_n_operands; i++)
5232 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5233 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5234 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5235 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5236 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5237 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5240 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5242 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5244 for (i = 0; i < n_reloads; i++)
5245 /* If we have already decided to use a certain register,
5246 don't use it in another way. */
5248 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5249 rld[i].when_needed, rld[i].mode);
5252 /* Assign hard reg targets for the pseudo-registers we must reload
5253 into hard regs for this insn.
5254 Also output the instructions to copy them in and out of the hard regs.
5256 For machines with register classes, we are responsible for
5257 finding a reload reg in the proper class. */
5260 choose_reload_regs (struct insn_chain *chain)
5262 rtx insn = chain->insn;
5264 unsigned int max_group_size = 1;
5265 enum reg_class group_class = NO_REGS;
5266 int pass, win, inheritance;
5268 rtx save_reload_reg_rtx[MAX_RELOADS];
5270 /* In order to be certain of getting the registers we need,
5271 we must sort the reloads into order of increasing register class.
5272 Then our grabbing of reload registers will parallel the process
5273 that provided the reload registers.
5275 Also note whether any of the reloads wants a consecutive group of regs.
5276 If so, record the maximum size of the group desired and what
5277 register class contains all the groups needed by this insn. */
5279 for (j = 0; j < n_reloads; j++)
5281 reload_order[j] = j;
5282 reload_spill_index[j] = -1;
5284 if (rld[j].nregs > 1)
5286 max_group_size = MAX (rld[j].nregs, max_group_size);
5288 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5291 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5295 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5297 /* If -O, try first with inheritance, then turning it off.
5298 If not -O, don't do inheritance.
5299 Using inheritance when not optimizing leads to paradoxes
5300 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5301 because one side of the comparison might be inherited. */
5303 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5305 choose_reload_regs_init (chain, save_reload_reg_rtx);
5307 /* Process the reloads in order of preference just found.
5308 Beyond this point, subregs can be found in reload_reg_rtx.
5310 This used to look for an existing reloaded home for all of the
5311 reloads, and only then perform any new reloads. But that could lose
5312 if the reloads were done out of reg-class order because a later
5313 reload with a looser constraint might have an old home in a register
5314 needed by an earlier reload with a tighter constraint.
5316 To solve this, we make two passes over the reloads, in the order
5317 described above. In the first pass we try to inherit a reload
5318 from a previous insn. If there is a later reload that needs a
5319 class that is a proper subset of the class being processed, we must
5320 also allocate a spill register during the first pass.
5322 Then make a second pass over the reloads to allocate any reloads
5323 that haven't been given registers yet. */
5325 for (j = 0; j < n_reloads; j++)
5327 int r = reload_order[j];
5328 rtx search_equiv = NULL_RTX;
5330 /* Ignore reloads that got marked inoperative. */
5331 if (rld[r].out == 0 && rld[r].in == 0
5332 && ! rld[r].secondary_p)
5335 /* If find_reloads chose to use reload_in or reload_out as a reload
5336 register, we don't need to chose one. Otherwise, try even if it
5337 found one since we might save an insn if we find the value lying
5339 Try also when reload_in is a pseudo without a hard reg. */
5340 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5341 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5342 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5343 && !MEM_P (rld[r].in)
5344 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5347 #if 0 /* No longer needed for correct operation.
5348 It might give better code, or might not; worth an experiment? */
5349 /* If this is an optional reload, we can't inherit from earlier insns
5350 until we are sure that any non-optional reloads have been allocated.
5351 The following code takes advantage of the fact that optional reloads
5352 are at the end of reload_order. */
5353 if (rld[r].optional != 0)
5354 for (i = 0; i < j; i++)
5355 if ((rld[reload_order[i]].out != 0
5356 || rld[reload_order[i]].in != 0
5357 || rld[reload_order[i]].secondary_p)
5358 && ! rld[reload_order[i]].optional
5359 && rld[reload_order[i]].reg_rtx == 0)
5360 allocate_reload_reg (chain, reload_order[i], 0);
5363 /* First see if this pseudo is already available as reloaded
5364 for a previous insn. We cannot try to inherit for reloads
5365 that are smaller than the maximum number of registers needed
5366 for groups unless the register we would allocate cannot be used
5369 We could check here to see if this is a secondary reload for
5370 an object that is already in a register of the desired class.
5371 This would avoid the need for the secondary reload register.
5372 But this is complex because we can't easily determine what
5373 objects might want to be loaded via this reload. So let a
5374 register be allocated here. In `emit_reload_insns' we suppress
5375 one of the loads in the case described above. */
5381 enum machine_mode mode = VOIDmode;
5385 else if (REG_P (rld[r].in))
5387 regno = REGNO (rld[r].in);
5388 mode = GET_MODE (rld[r].in);
5390 else if (REG_P (rld[r].in_reg))
5392 regno = REGNO (rld[r].in_reg);
5393 mode = GET_MODE (rld[r].in_reg);
5395 else if (GET_CODE (rld[r].in_reg) == SUBREG
5396 && REG_P (SUBREG_REG (rld[r].in_reg)))
5398 byte = SUBREG_BYTE (rld[r].in_reg);
5399 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5400 if (regno < FIRST_PSEUDO_REGISTER)
5401 regno = subreg_regno (rld[r].in_reg);
5402 mode = GET_MODE (rld[r].in_reg);
5405 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5406 || GET_CODE (rld[r].in_reg) == PRE_DEC
5407 || GET_CODE (rld[r].in_reg) == POST_INC
5408 || GET_CODE (rld[r].in_reg) == POST_DEC)
5409 && REG_P (XEXP (rld[r].in_reg, 0)))
5411 regno = REGNO (XEXP (rld[r].in_reg, 0));
5412 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5413 rld[r].out = rld[r].in;
5417 /* This won't work, since REGNO can be a pseudo reg number.
5418 Also, it takes much more hair to keep track of all the things
5419 that can invalidate an inherited reload of part of a pseudoreg. */
5420 else if (GET_CODE (rld[r].in) == SUBREG
5421 && REG_P (SUBREG_REG (rld[r].in)))
5422 regno = subreg_regno (rld[r].in);
5425 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5427 enum reg_class class = rld[r].class, last_class;
5428 rtx last_reg = reg_last_reload_reg[regno];
5429 enum machine_mode need_mode;
5431 i = REGNO (last_reg);
5432 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5433 last_class = REGNO_REG_CLASS (i);
5439 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5440 + byte * BITS_PER_UNIT,
5441 GET_MODE_CLASS (mode));
5443 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5444 >= GET_MODE_SIZE (need_mode))
5445 #ifdef CANNOT_CHANGE_MODE_CLASS
5446 /* Verify that the register in "i" can be obtained
5448 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5449 GET_MODE (last_reg),
5452 && reg_reloaded_contents[i] == regno
5453 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5454 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5455 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5456 /* Even if we can't use this register as a reload
5457 register, we might use it for reload_override_in,
5458 if copying it to the desired class is cheap
5460 || ((REGISTER_MOVE_COST (mode, last_class, class)
5461 < MEMORY_MOVE_COST (mode, class, 1))
5462 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5463 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5467 #ifdef SECONDARY_MEMORY_NEEDED
5468 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5473 && (rld[r].nregs == max_group_size
5474 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5476 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5477 rld[r].when_needed, rld[r].in,
5480 /* If a group is needed, verify that all the subsequent
5481 registers still have their values intact. */
5482 int nr = hard_regno_nregs[i][rld[r].mode];
5485 for (k = 1; k < nr; k++)
5486 if (reg_reloaded_contents[i + k] != regno
5487 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5495 last_reg = (GET_MODE (last_reg) == mode
5496 ? last_reg : gen_rtx_REG (mode, i));
5499 for (k = 0; k < nr; k++)
5500 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5503 /* We found a register that contains the
5504 value we need. If this register is the
5505 same as an `earlyclobber' operand of the
5506 current insn, just mark it as a place to
5507 reload from since we can't use it as the
5508 reload register itself. */
5510 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5511 if (reg_overlap_mentioned_for_reload_p
5512 (reg_last_reload_reg[regno],
5513 reload_earlyclobbers[i1]))
5516 if (i1 != n_earlyclobbers
5517 || ! (free_for_value_p (i, rld[r].mode,
5519 rld[r].when_needed, rld[r].in,
5521 /* Don't use it if we'd clobber a pseudo reg. */
5522 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5524 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5525 /* Don't clobber the frame pointer. */
5526 || (i == HARD_FRAME_POINTER_REGNUM
5527 && frame_pointer_needed
5529 /* Don't really use the inherited spill reg
5530 if we need it wider than we've got it. */
5531 || (GET_MODE_SIZE (rld[r].mode)
5532 > GET_MODE_SIZE (mode))
5535 /* If find_reloads chose reload_out as reload
5536 register, stay with it - that leaves the
5537 inherited register for subsequent reloads. */
5538 || (rld[r].out && rld[r].reg_rtx
5539 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5541 if (! rld[r].optional)
5543 reload_override_in[r] = last_reg;
5544 reload_inheritance_insn[r]
5545 = reg_reloaded_insn[i];
5551 /* We can use this as a reload reg. */
5552 /* Mark the register as in use for this part of
5554 mark_reload_reg_in_use (i,
5558 rld[r].reg_rtx = last_reg;
5559 reload_inherited[r] = 1;
5560 reload_inheritance_insn[r]
5561 = reg_reloaded_insn[i];
5562 reload_spill_index[r] = i;
5563 for (k = 0; k < nr; k++)
5564 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5572 /* Here's another way to see if the value is already lying around. */
5575 && ! reload_inherited[r]
5577 && (CONSTANT_P (rld[r].in)
5578 || GET_CODE (rld[r].in) == PLUS
5579 || REG_P (rld[r].in)
5580 || MEM_P (rld[r].in))
5581 && (rld[r].nregs == max_group_size
5582 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5583 search_equiv = rld[r].in;
5584 /* If this is an output reload from a simple move insn, look
5585 if an equivalence for the input is available. */
5586 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5588 rtx set = single_set (insn);
5591 && rtx_equal_p (rld[r].out, SET_DEST (set))
5592 && CONSTANT_P (SET_SRC (set)))
5593 search_equiv = SET_SRC (set);
5599 = find_equiv_reg (search_equiv, insn, rld[r].class,
5600 -1, NULL, 0, rld[r].mode);
5606 regno = REGNO (equiv);
5609 /* This must be a SUBREG of a hard register.
5610 Make a new REG since this might be used in an
5611 address and not all machines support SUBREGs
5613 gcc_assert (GET_CODE (equiv) == SUBREG);
5614 regno = subreg_regno (equiv);
5615 equiv = gen_rtx_REG (rld[r].mode, regno);
5616 /* If we choose EQUIV as the reload register, but the
5617 loop below decides to cancel the inheritance, we'll
5618 end up reloading EQUIV in rld[r].mode, not the mode
5619 it had originally. That isn't safe when EQUIV isn't
5620 available as a spill register since its value might
5621 still be live at this point. */
5622 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5623 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5628 /* If we found a spill reg, reject it unless it is free
5629 and of the desired class. */
5633 int bad_for_class = 0;
5634 int max_regno = regno + rld[r].nregs;
5636 for (i = regno; i < max_regno; i++)
5638 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5640 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5645 && ! free_for_value_p (regno, rld[r].mode,
5646 rld[r].opnum, rld[r].when_needed,
5647 rld[r].in, rld[r].out, r, 1))
5652 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5655 /* We found a register that contains the value we need.
5656 If this register is the same as an `earlyclobber' operand
5657 of the current insn, just mark it as a place to reload from
5658 since we can't use it as the reload register itself. */
5661 for (i = 0; i < n_earlyclobbers; i++)
5662 if (reg_overlap_mentioned_for_reload_p (equiv,
5663 reload_earlyclobbers[i]))
5665 if (! rld[r].optional)
5666 reload_override_in[r] = equiv;
5671 /* If the equiv register we have found is explicitly clobbered
5672 in the current insn, it depends on the reload type if we
5673 can use it, use it for reload_override_in, or not at all.
5674 In particular, we then can't use EQUIV for a
5675 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5679 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5680 switch (rld[r].when_needed)
5682 case RELOAD_FOR_OTHER_ADDRESS:
5683 case RELOAD_FOR_INPADDR_ADDRESS:
5684 case RELOAD_FOR_INPUT_ADDRESS:
5685 case RELOAD_FOR_OPADDR_ADDR:
5688 case RELOAD_FOR_INPUT:
5689 case RELOAD_FOR_OPERAND_ADDRESS:
5690 if (! rld[r].optional)
5691 reload_override_in[r] = equiv;
5697 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5698 switch (rld[r].when_needed)
5700 case RELOAD_FOR_OTHER_ADDRESS:
5701 case RELOAD_FOR_INPADDR_ADDRESS:
5702 case RELOAD_FOR_INPUT_ADDRESS:
5703 case RELOAD_FOR_OPADDR_ADDR:
5704 case RELOAD_FOR_OPERAND_ADDRESS:
5705 case RELOAD_FOR_INPUT:
5708 if (! rld[r].optional)
5709 reload_override_in[r] = equiv;
5717 /* If we found an equivalent reg, say no code need be generated
5718 to load it, and use it as our reload reg. */
5720 && (regno != HARD_FRAME_POINTER_REGNUM
5721 || !frame_pointer_needed))
5723 int nr = hard_regno_nregs[regno][rld[r].mode];
5725 rld[r].reg_rtx = equiv;
5726 reload_inherited[r] = 1;
5728 /* If reg_reloaded_valid is not set for this register,
5729 there might be a stale spill_reg_store lying around.
5730 We must clear it, since otherwise emit_reload_insns
5731 might delete the store. */
5732 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5733 spill_reg_store[regno] = NULL_RTX;
5734 /* If any of the hard registers in EQUIV are spill
5735 registers, mark them as in use for this insn. */
5736 for (k = 0; k < nr; k++)
5738 i = spill_reg_order[regno + k];
5741 mark_reload_reg_in_use (regno, rld[r].opnum,
5744 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5751 /* If we found a register to use already, or if this is an optional
5752 reload, we are done. */
5753 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5757 /* No longer needed for correct operation. Might or might
5758 not give better code on the average. Want to experiment? */
5760 /* See if there is a later reload that has a class different from our
5761 class that intersects our class or that requires less register
5762 than our reload. If so, we must allocate a register to this
5763 reload now, since that reload might inherit a previous reload
5764 and take the only available register in our class. Don't do this
5765 for optional reloads since they will force all previous reloads
5766 to be allocated. Also don't do this for reloads that have been
5769 for (i = j + 1; i < n_reloads; i++)
5771 int s = reload_order[i];
5773 if ((rld[s].in == 0 && rld[s].out == 0
5774 && ! rld[s].secondary_p)
5778 if ((rld[s].class != rld[r].class
5779 && reg_classes_intersect_p (rld[r].class,
5781 || rld[s].nregs < rld[r].nregs)
5788 allocate_reload_reg (chain, r, j == n_reloads - 1);
5792 /* Now allocate reload registers for anything non-optional that
5793 didn't get one yet. */
5794 for (j = 0; j < n_reloads; j++)
5796 int r = reload_order[j];
5798 /* Ignore reloads that got marked inoperative. */
5799 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5802 /* Skip reloads that already have a register allocated or are
5804 if (rld[r].reg_rtx != 0 || rld[r].optional)
5807 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5811 /* If that loop got all the way, we have won. */
5818 /* Loop around and try without any inheritance. */
5823 /* First undo everything done by the failed attempt
5824 to allocate with inheritance. */
5825 choose_reload_regs_init (chain, save_reload_reg_rtx);
5827 /* Some sanity tests to verify that the reloads found in the first
5828 pass are identical to the ones we have now. */
5829 gcc_assert (chain->n_reloads == n_reloads);
5831 for (i = 0; i < n_reloads; i++)
5833 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5835 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5836 for (j = 0; j < n_spills; j++)
5837 if (spill_regs[j] == chain->rld[i].regno)
5838 if (! set_reload_reg (j, i))
5839 failed_reload (chain->insn, i);
5843 /* If we thought we could inherit a reload, because it seemed that
5844 nothing else wanted the same reload register earlier in the insn,
5845 verify that assumption, now that all reloads have been assigned.
5846 Likewise for reloads where reload_override_in has been set. */
5848 /* If doing expensive optimizations, do one preliminary pass that doesn't
5849 cancel any inheritance, but removes reloads that have been needed only
5850 for reloads that we know can be inherited. */
5851 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5853 for (j = 0; j < n_reloads; j++)
5855 int r = reload_order[j];
5857 if (reload_inherited[r] && rld[r].reg_rtx)
5858 check_reg = rld[r].reg_rtx;
5859 else if (reload_override_in[r]
5860 && (REG_P (reload_override_in[r])
5861 || GET_CODE (reload_override_in[r]) == SUBREG))
5862 check_reg = reload_override_in[r];
5865 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5866 rld[r].opnum, rld[r].when_needed, rld[r].in,
5867 (reload_inherited[r]
5868 ? rld[r].out : const0_rtx),
5873 reload_inherited[r] = 0;
5874 reload_override_in[r] = 0;
5876 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5877 reload_override_in, then we do not need its related
5878 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5879 likewise for other reload types.
5880 We handle this by removing a reload when its only replacement
5881 is mentioned in reload_in of the reload we are going to inherit.
5882 A special case are auto_inc expressions; even if the input is
5883 inherited, we still need the address for the output. We can
5884 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5885 If we succeeded removing some reload and we are doing a preliminary
5886 pass just to remove such reloads, make another pass, since the
5887 removal of one reload might allow us to inherit another one. */
5889 && rld[r].out != rld[r].in
5890 && remove_address_replacements (rld[r].in) && pass)
5895 /* Now that reload_override_in is known valid,
5896 actually override reload_in. */
5897 for (j = 0; j < n_reloads; j++)
5898 if (reload_override_in[j])
5899 rld[j].in = reload_override_in[j];
5901 /* If this reload won't be done because it has been canceled or is
5902 optional and not inherited, clear reload_reg_rtx so other
5903 routines (such as subst_reloads) don't get confused. */
5904 for (j = 0; j < n_reloads; j++)
5905 if (rld[j].reg_rtx != 0
5906 && ((rld[j].optional && ! reload_inherited[j])
5907 || (rld[j].in == 0 && rld[j].out == 0
5908 && ! rld[j].secondary_p)))
5910 int regno = true_regnum (rld[j].reg_rtx);
5912 if (spill_reg_order[regno] >= 0)
5913 clear_reload_reg_in_use (regno, rld[j].opnum,
5914 rld[j].when_needed, rld[j].mode);
5916 reload_spill_index[j] = -1;
5919 /* Record which pseudos and which spill regs have output reloads. */
5920 for (j = 0; j < n_reloads; j++)
5922 int r = reload_order[j];
5924 i = reload_spill_index[r];
5926 /* I is nonneg if this reload uses a register.
5927 If rld[r].reg_rtx is 0, this is an optional reload
5928 that we opted to ignore. */
5929 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5930 && rld[r].reg_rtx != 0)
5932 int nregno = REGNO (rld[r].out_reg);
5935 if (nregno < FIRST_PSEUDO_REGISTER)
5936 nr = hard_regno_nregs[nregno][rld[r].mode];
5939 reg_has_output_reload[nregno + nr] = 1;
5943 nr = hard_regno_nregs[i][rld[r].mode];
5945 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5948 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5949 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5950 || rld[r].when_needed == RELOAD_FOR_INSN);
5955 /* Deallocate the reload register for reload R. This is called from
5956 remove_address_replacements. */
5959 deallocate_reload_reg (int r)
5963 if (! rld[r].reg_rtx)
5965 regno = true_regnum (rld[r].reg_rtx);
5967 if (spill_reg_order[regno] >= 0)
5968 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5970 reload_spill_index[r] = -1;
5973 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5974 reloads of the same item for fear that we might not have enough reload
5975 registers. However, normally they will get the same reload register
5976 and hence actually need not be loaded twice.
5978 Here we check for the most common case of this phenomenon: when we have
5979 a number of reloads for the same object, each of which were allocated
5980 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5981 reload, and is not modified in the insn itself. If we find such,
5982 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5983 This will not increase the number of spill registers needed and will
5984 prevent redundant code. */
5987 merge_assigned_reloads (rtx insn)
5991 /* Scan all the reloads looking for ones that only load values and
5992 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5993 assigned and not modified by INSN. */
5995 for (i = 0; i < n_reloads; i++)
5997 int conflicting_input = 0;
5998 int max_input_address_opnum = -1;
5999 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6001 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6002 || rld[i].out != 0 || rld[i].reg_rtx == 0
6003 || reg_set_p (rld[i].reg_rtx, insn))
6006 /* Look at all other reloads. Ensure that the only use of this
6007 reload_reg_rtx is in a reload that just loads the same value
6008 as we do. Note that any secondary reloads must be of the identical
6009 class since the values, modes, and result registers are the
6010 same, so we need not do anything with any secondary reloads. */
6012 for (j = 0; j < n_reloads; j++)
6014 if (i == j || rld[j].reg_rtx == 0
6015 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6019 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6020 && rld[j].opnum > max_input_address_opnum)
6021 max_input_address_opnum = rld[j].opnum;
6023 /* If the reload regs aren't exactly the same (e.g, different modes)
6024 or if the values are different, we can't merge this reload.
6025 But if it is an input reload, we might still merge
6026 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6028 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6029 || rld[j].out != 0 || rld[j].in == 0
6030 || ! rtx_equal_p (rld[i].in, rld[j].in))
6032 if (rld[j].when_needed != RELOAD_FOR_INPUT
6033 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6034 || rld[i].opnum > rld[j].opnum)
6035 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6037 conflicting_input = 1;
6038 if (min_conflicting_input_opnum > rld[j].opnum)
6039 min_conflicting_input_opnum = rld[j].opnum;
6043 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6044 we, in fact, found any matching reloads. */
6047 && max_input_address_opnum <= min_conflicting_input_opnum)
6049 for (j = 0; j < n_reloads; j++)
6050 if (i != j && rld[j].reg_rtx != 0
6051 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6052 && (! conflicting_input
6053 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6054 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6056 rld[i].when_needed = RELOAD_OTHER;
6058 reload_spill_index[j] = -1;
6059 transfer_replacements (i, j);
6062 /* If this is now RELOAD_OTHER, look for any reloads that load
6063 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6064 if they were for inputs, RELOAD_OTHER for outputs. Note that
6065 this test is equivalent to looking for reloads for this operand
6067 /* We must take special care when there are two or more reloads to
6068 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6069 same value or a part of it; we must not change its type if there
6070 is a conflicting input. */
6072 if (rld[i].when_needed == RELOAD_OTHER)
6073 for (j = 0; j < n_reloads; j++)
6075 && rld[j].when_needed != RELOAD_OTHER
6076 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6077 && (! conflicting_input
6078 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6079 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6080 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6086 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6087 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6088 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6090 /* Check to see if we accidentally converted two
6091 reloads that use the same reload register with
6092 different inputs to the same type. If so, the
6093 resulting code won't work. */
6095 for (k = 0; k < j; k++)
6096 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6097 || rld[k].when_needed != rld[j].when_needed
6098 || !rtx_equal_p (rld[k].reg_rtx,
6100 || rtx_equal_p (rld[k].in,
6107 /* These arrays are filled by emit_reload_insns and its subroutines. */
6108 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6109 static rtx other_input_address_reload_insns = 0;
6110 static rtx other_input_reload_insns = 0;
6111 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6112 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6113 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6114 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6115 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6116 static rtx operand_reload_insns = 0;
6117 static rtx other_operand_reload_insns = 0;
6118 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6120 /* Values to be put in spill_reg_store are put here first. */
6121 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6122 static HARD_REG_SET reg_reloaded_died;
6124 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6125 has the number J. OLD contains the value to be used as input. */
6128 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6131 rtx insn = chain->insn;
6132 rtx reloadreg = rl->reg_rtx;
6133 rtx oldequiv_reg = 0;
6136 enum machine_mode mode;
6139 /* Determine the mode to reload in.
6140 This is very tricky because we have three to choose from.
6141 There is the mode the insn operand wants (rl->inmode).
6142 There is the mode of the reload register RELOADREG.
6143 There is the intrinsic mode of the operand, which we could find
6144 by stripping some SUBREGs.
6145 It turns out that RELOADREG's mode is irrelevant:
6146 we can change that arbitrarily.
6148 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6149 then the reload reg may not support QImode moves, so use SImode.
6150 If foo is in memory due to spilling a pseudo reg, this is safe,
6151 because the QImode value is in the least significant part of a
6152 slot big enough for a SImode. If foo is some other sort of
6153 memory reference, then it is impossible to reload this case,
6154 so previous passes had better make sure this never happens.
6156 Then consider a one-word union which has SImode and one of its
6157 members is a float, being fetched as (SUBREG:SF union:SI).
6158 We must fetch that as SFmode because we could be loading into
6159 a float-only register. In this case OLD's mode is correct.
6161 Consider an immediate integer: it has VOIDmode. Here we need
6162 to get a mode from something else.
6164 In some cases, there is a fourth mode, the operand's
6165 containing mode. If the insn specifies a containing mode for
6166 this operand, it overrides all others.
6168 I am not sure whether the algorithm here is always right,
6169 but it does the right things in those cases. */
6171 mode = GET_MODE (old);
6172 if (mode == VOIDmode)
6175 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6176 /* If we need a secondary register for this operation, see if
6177 the value is already in a register in that class. Don't
6178 do this if the secondary register will be used as a scratch
6181 if (rl->secondary_in_reload >= 0
6182 && rl->secondary_in_icode == CODE_FOR_nothing
6185 = find_equiv_reg (old, insn,
6186 rld[rl->secondary_in_reload].class,
6190 /* If reloading from memory, see if there is a register
6191 that already holds the same value. If so, reload from there.
6192 We can pass 0 as the reload_reg_p argument because
6193 any other reload has either already been emitted,
6194 in which case find_equiv_reg will see the reload-insn,
6195 or has yet to be emitted, in which case it doesn't matter
6196 because we will use this equiv reg right away. */
6198 if (oldequiv == 0 && optimize
6201 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6202 && reg_renumber[REGNO (old)] < 0)))
6203 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6207 unsigned int regno = true_regnum (oldequiv);
6209 /* Don't use OLDEQUIV if any other reload changes it at an
6210 earlier stage of this insn or at this stage. */
6211 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6212 rl->in, const0_rtx, j, 0))
6215 /* If it is no cheaper to copy from OLDEQUIV into the
6216 reload register than it would be to move from memory,
6217 don't use it. Likewise, if we need a secondary register
6221 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6222 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6224 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6225 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6226 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6230 #ifdef SECONDARY_MEMORY_NEEDED
6231 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6239 /* delete_output_reload is only invoked properly if old contains
6240 the original pseudo register. Since this is replaced with a
6241 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6242 find the pseudo in RELOAD_IN_REG. */
6244 && reload_override_in[j]
6245 && REG_P (rl->in_reg))
6252 else if (REG_P (oldequiv))
6253 oldequiv_reg = oldequiv;
6254 else if (GET_CODE (oldequiv) == SUBREG)
6255 oldequiv_reg = SUBREG_REG (oldequiv);
6257 /* If we are reloading from a register that was recently stored in
6258 with an output-reload, see if we can prove there was
6259 actually no need to store the old value in it. */
6261 if (optimize && REG_P (oldequiv)
6262 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6263 && spill_reg_store[REGNO (oldequiv)]
6265 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6266 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6268 delete_output_reload (insn, j, REGNO (oldequiv));
6270 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6271 then load RELOADREG from OLDEQUIV. Note that we cannot use
6272 gen_lowpart_common since it can do the wrong thing when
6273 RELOADREG has a multi-word mode. Note that RELOADREG
6274 must always be a REG here. */
6276 if (GET_MODE (reloadreg) != mode)
6277 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6278 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6279 oldequiv = SUBREG_REG (oldequiv);
6280 if (GET_MODE (oldequiv) != VOIDmode
6281 && mode != GET_MODE (oldequiv))
6282 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6284 /* Switch to the right place to emit the reload insns. */
6285 switch (rl->when_needed)
6288 where = &other_input_reload_insns;
6290 case RELOAD_FOR_INPUT:
6291 where = &input_reload_insns[rl->opnum];
6293 case RELOAD_FOR_INPUT_ADDRESS:
6294 where = &input_address_reload_insns[rl->opnum];
6296 case RELOAD_FOR_INPADDR_ADDRESS:
6297 where = &inpaddr_address_reload_insns[rl->opnum];
6299 case RELOAD_FOR_OUTPUT_ADDRESS:
6300 where = &output_address_reload_insns[rl->opnum];
6302 case RELOAD_FOR_OUTADDR_ADDRESS:
6303 where = &outaddr_address_reload_insns[rl->opnum];
6305 case RELOAD_FOR_OPERAND_ADDRESS:
6306 where = &operand_reload_insns;
6308 case RELOAD_FOR_OPADDR_ADDR:
6309 where = &other_operand_reload_insns;
6311 case RELOAD_FOR_OTHER_ADDRESS:
6312 where = &other_input_address_reload_insns;
6318 push_to_sequence (*where);
6320 /* Auto-increment addresses must be reloaded in a special way. */
6321 if (rl->out && ! rl->out_reg)
6323 /* We are not going to bother supporting the case where a
6324 incremented register can't be copied directly from
6325 OLDEQUIV since this seems highly unlikely. */
6326 gcc_assert (rl->secondary_in_reload < 0);
6328 if (reload_inherited[j])
6329 oldequiv = reloadreg;
6331 old = XEXP (rl->in_reg, 0);
6333 if (optimize && REG_P (oldequiv)
6334 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6335 && spill_reg_store[REGNO (oldequiv)]
6337 && (dead_or_set_p (insn,
6338 spill_reg_stored_to[REGNO (oldequiv)])
6339 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6341 delete_output_reload (insn, j, REGNO (oldequiv));
6343 /* Prevent normal processing of this reload. */
6345 /* Output a special code sequence for this case. */
6346 new_spill_reg_store[REGNO (reloadreg)]
6347 = inc_for_reload (reloadreg, oldequiv, rl->out,
6351 /* If we are reloading a pseudo-register that was set by the previous
6352 insn, see if we can get rid of that pseudo-register entirely
6353 by redirecting the previous insn into our reload register. */
6355 else if (optimize && REG_P (old)
6356 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6357 && dead_or_set_p (insn, old)
6358 /* This is unsafe if some other reload
6359 uses the same reg first. */
6360 && ! conflicts_with_override (reloadreg)
6361 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6362 rl->when_needed, old, rl->out, j, 0))
6364 rtx temp = PREV_INSN (insn);
6365 while (temp && NOTE_P (temp))
6366 temp = PREV_INSN (temp);
6368 && NONJUMP_INSN_P (temp)
6369 && GET_CODE (PATTERN (temp)) == SET
6370 && SET_DEST (PATTERN (temp)) == old
6371 /* Make sure we can access insn_operand_constraint. */
6372 && asm_noperands (PATTERN (temp)) < 0
6373 /* This is unsafe if operand occurs more than once in current
6374 insn. Perhaps some occurrences aren't reloaded. */
6375 && count_occurrences (PATTERN (insn), old, 0) == 1)
6377 rtx old = SET_DEST (PATTERN (temp));
6378 /* Store into the reload register instead of the pseudo. */
6379 SET_DEST (PATTERN (temp)) = reloadreg;
6381 /* Verify that resulting insn is valid. */
6382 extract_insn (temp);
6383 if (constrain_operands (1))
6385 /* If the previous insn is an output reload, the source is
6386 a reload register, and its spill_reg_store entry will
6387 contain the previous destination. This is now
6389 if (REG_P (SET_SRC (PATTERN (temp)))
6390 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6392 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6393 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6396 /* If these are the only uses of the pseudo reg,
6397 pretend for GDB it lives in the reload reg we used. */
6398 if (REG_N_DEATHS (REGNO (old)) == 1
6399 && REG_N_SETS (REGNO (old)) == 1)
6401 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6402 alter_reg (REGNO (old), -1);
6408 SET_DEST (PATTERN (temp)) = old;
6413 /* We can't do that, so output an insn to load RELOADREG. */
6415 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6416 /* If we have a secondary reload, pick up the secondary register
6417 and icode, if any. If OLDEQUIV and OLD are different or
6418 if this is an in-out reload, recompute whether or not we
6419 still need a secondary register and what the icode should
6420 be. If we still need a secondary register and the class or
6421 icode is different, go back to reloading from OLD if using
6422 OLDEQUIV means that we got the wrong type of register. We
6423 cannot have different class or icode due to an in-out reload
6424 because we don't make such reloads when both the input and
6425 output need secondary reload registers. */
6427 if (! special && rl->secondary_in_reload >= 0)
6429 rtx second_reload_reg = 0;
6430 int secondary_reload = rl->secondary_in_reload;
6431 rtx real_oldequiv = oldequiv;
6434 enum insn_code icode;
6436 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6437 and similarly for OLD.
6438 See comments in get_secondary_reload in reload.c. */
6439 /* If it is a pseudo that cannot be replaced with its
6440 equivalent MEM, we must fall back to reload_in, which
6441 will have all the necessary substitutions registered.
6442 Likewise for a pseudo that can't be replaced with its
6443 equivalent constant.
6445 Take extra care for subregs of such pseudos. Note that
6446 we cannot use reg_equiv_mem in this case because it is
6447 not in the right mode. */
6450 if (GET_CODE (tmp) == SUBREG)
6451 tmp = SUBREG_REG (tmp);
6453 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6454 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6455 || reg_equiv_constant[REGNO (tmp)] != 0))
6457 if (! reg_equiv_mem[REGNO (tmp)]
6458 || num_not_at_initial_offset
6459 || GET_CODE (oldequiv) == SUBREG)
6460 real_oldequiv = rl->in;
6462 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6466 if (GET_CODE (tmp) == SUBREG)
6467 tmp = SUBREG_REG (tmp);
6469 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6470 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6471 || reg_equiv_constant[REGNO (tmp)] != 0))
6473 if (! reg_equiv_mem[REGNO (tmp)]
6474 || num_not_at_initial_offset
6475 || GET_CODE (old) == SUBREG)
6478 real_old = reg_equiv_mem[REGNO (tmp)];
6481 second_reload_reg = rld[secondary_reload].reg_rtx;
6482 icode = rl->secondary_in_icode;
6484 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6485 || (rl->in != 0 && rl->out != 0))
6487 enum reg_class new_class
6488 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6489 mode, real_oldequiv);
6491 if (new_class == NO_REGS)
6492 second_reload_reg = 0;
6495 enum insn_code new_icode;
6496 enum machine_mode new_mode;
6498 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6499 REGNO (second_reload_reg)))
6500 oldequiv = old, real_oldequiv = real_old;
6503 new_icode = reload_in_optab[(int) mode];
6504 if (new_icode != CODE_FOR_nothing
6505 && ((insn_data[(int) new_icode].operand[0].predicate
6506 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6508 || (insn_data[(int) new_icode].operand[1].predicate
6509 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6510 (real_oldequiv, mode)))))
6511 new_icode = CODE_FOR_nothing;
6513 if (new_icode == CODE_FOR_nothing)
6516 new_mode = insn_data[(int) new_icode].operand[2].mode;
6518 if (GET_MODE (second_reload_reg) != new_mode)
6520 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6522 oldequiv = old, real_oldequiv = real_old;
6525 = reload_adjust_reg_for_mode (second_reload_reg,
6532 /* If we still need a secondary reload register, check
6533 to see if it is being used as a scratch or intermediate
6534 register and generate code appropriately. If we need
6535 a scratch register, use REAL_OLDEQUIV since the form of
6536 the insn may depend on the actual address if it is
6539 if (second_reload_reg)
6541 if (icode != CODE_FOR_nothing)
6543 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6544 second_reload_reg));
6549 /* See if we need a scratch register to load the
6550 intermediate register (a tertiary reload). */
6551 enum insn_code tertiary_icode
6552 = rld[secondary_reload].secondary_in_icode;
6554 if (tertiary_icode != CODE_FOR_nothing)
6556 rtx third_reload_reg
6557 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6559 emit_insn ((GEN_FCN (tertiary_icode)
6560 (second_reload_reg, real_oldequiv,
6561 third_reload_reg)));
6564 gen_reload (second_reload_reg, real_oldequiv,
6568 oldequiv = second_reload_reg;
6574 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6576 rtx real_oldequiv = oldequiv;
6578 if ((REG_P (oldequiv)
6579 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6580 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6581 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6582 || (GET_CODE (oldequiv) == SUBREG
6583 && REG_P (SUBREG_REG (oldequiv))
6584 && (REGNO (SUBREG_REG (oldequiv))
6585 >= FIRST_PSEUDO_REGISTER)
6586 && ((reg_equiv_memory_loc
6587 [REGNO (SUBREG_REG (oldequiv))] != 0)
6588 || (reg_equiv_constant
6589 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6590 || (CONSTANT_P (oldequiv)
6591 && (PREFERRED_RELOAD_CLASS (oldequiv,
6592 REGNO_REG_CLASS (REGNO (reloadreg)))
6594 real_oldequiv = rl->in;
6595 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6599 if (flag_non_call_exceptions)
6600 copy_eh_notes (insn, get_insns ());
6602 /* End this sequence. */
6603 *where = get_insns ();
6606 /* Update reload_override_in so that delete_address_reloads_1
6607 can see the actual register usage. */
6609 reload_override_in[j] = oldequiv;
6612 /* Generate insns to for the output reload RL, which is for the insn described
6613 by CHAIN and has the number J. */
6615 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6618 rtx reloadreg = rl->reg_rtx;
6619 rtx insn = chain->insn;
6622 enum machine_mode mode = GET_MODE (old);
6625 if (rl->when_needed == RELOAD_OTHER)
6628 push_to_sequence (output_reload_insns[rl->opnum]);
6630 /* Determine the mode to reload in.
6631 See comments above (for input reloading). */
6633 if (mode == VOIDmode)
6635 /* VOIDmode should never happen for an output. */
6636 if (asm_noperands (PATTERN (insn)) < 0)
6637 /* It's the compiler's fault. */
6638 fatal_insn ("VOIDmode on an output", insn);
6639 error_for_asm (insn, "output operand is constant in %<asm%>");
6640 /* Prevent crash--use something we know is valid. */
6642 old = gen_rtx_REG (mode, REGNO (reloadreg));
6645 if (GET_MODE (reloadreg) != mode)
6646 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6648 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6650 /* If we need two reload regs, set RELOADREG to the intermediate
6651 one, since it will be stored into OLD. We might need a secondary
6652 register only for an input reload, so check again here. */
6654 if (rl->secondary_out_reload >= 0)
6658 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6659 && reg_equiv_mem[REGNO (old)] != 0)
6660 real_old = reg_equiv_mem[REGNO (old)];
6662 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6666 rtx second_reloadreg = reloadreg;
6667 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6669 /* See if RELOADREG is to be used as a scratch register
6670 or as an intermediate register. */
6671 if (rl->secondary_out_icode != CODE_FOR_nothing)
6673 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6674 (real_old, second_reloadreg, reloadreg)));
6679 /* See if we need both a scratch and intermediate reload
6682 int secondary_reload = rl->secondary_out_reload;
6683 enum insn_code tertiary_icode
6684 = rld[secondary_reload].secondary_out_icode;
6686 if (GET_MODE (reloadreg) != mode)
6687 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6689 if (tertiary_icode != CODE_FOR_nothing)
6692 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6695 /* Copy primary reload reg to secondary reload reg.
6696 (Note that these have been swapped above, then
6697 secondary reload reg to OLD using our insn.) */
6699 /* If REAL_OLD is a paradoxical SUBREG, remove it
6700 and try to put the opposite SUBREG on
6702 if (GET_CODE (real_old) == SUBREG
6703 && (GET_MODE_SIZE (GET_MODE (real_old))
6704 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6705 && 0 != (tem = gen_lowpart_common
6706 (GET_MODE (SUBREG_REG (real_old)),
6708 real_old = SUBREG_REG (real_old), reloadreg = tem;
6710 gen_reload (reloadreg, second_reloadreg,
6711 rl->opnum, rl->when_needed);
6712 emit_insn ((GEN_FCN (tertiary_icode)
6713 (real_old, reloadreg, third_reloadreg)));
6718 /* Copy between the reload regs here and then to
6721 gen_reload (reloadreg, second_reloadreg,
6722 rl->opnum, rl->when_needed);
6728 /* Output the last reload insn. */
6733 /* Don't output the last reload if OLD is not the dest of
6734 INSN and is in the src and is clobbered by INSN. */
6735 if (! flag_expensive_optimizations
6737 || !(set = single_set (insn))
6738 || rtx_equal_p (old, SET_DEST (set))
6739 || !reg_mentioned_p (old, SET_SRC (set))
6740 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6741 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6742 gen_reload (old, reloadreg, rl->opnum,
6746 /* Look at all insns we emitted, just to be safe. */
6747 for (p = get_insns (); p; p = NEXT_INSN (p))
6750 rtx pat = PATTERN (p);
6752 /* If this output reload doesn't come from a spill reg,
6753 clear any memory of reloaded copies of the pseudo reg.
6754 If this output reload comes from a spill reg,
6755 reg_has_output_reload will make this do nothing. */
6756 note_stores (pat, forget_old_reloads_1, NULL);
6758 if (reg_mentioned_p (rl->reg_rtx, pat))
6760 rtx set = single_set (insn);
6761 if (reload_spill_index[j] < 0
6763 && SET_SRC (set) == rl->reg_rtx)
6765 int src = REGNO (SET_SRC (set));
6767 reload_spill_index[j] = src;
6768 SET_HARD_REG_BIT (reg_is_output_reload, src);
6769 if (find_regno_note (insn, REG_DEAD, src))
6770 SET_HARD_REG_BIT (reg_reloaded_died, src);
6772 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6774 int s = rl->secondary_out_reload;
6775 set = single_set (p);
6776 /* If this reload copies only to the secondary reload
6777 register, the secondary reload does the actual
6779 if (s >= 0 && set == NULL_RTX)
6780 /* We can't tell what function the secondary reload
6781 has and where the actual store to the pseudo is
6782 made; leave new_spill_reg_store alone. */
6785 && SET_SRC (set) == rl->reg_rtx
6786 && SET_DEST (set) == rld[s].reg_rtx)
6788 /* Usually the next instruction will be the
6789 secondary reload insn; if we can confirm
6790 that it is, setting new_spill_reg_store to
6791 that insn will allow an extra optimization. */
6792 rtx s_reg = rld[s].reg_rtx;
6793 rtx next = NEXT_INSN (p);
6794 rld[s].out = rl->out;
6795 rld[s].out_reg = rl->out_reg;
6796 set = single_set (next);
6797 if (set && SET_SRC (set) == s_reg
6798 && ! new_spill_reg_store[REGNO (s_reg)])
6800 SET_HARD_REG_BIT (reg_is_output_reload,
6802 new_spill_reg_store[REGNO (s_reg)] = next;
6806 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6811 if (rl->when_needed == RELOAD_OTHER)
6813 emit_insn (other_output_reload_insns[rl->opnum]);
6814 other_output_reload_insns[rl->opnum] = get_insns ();
6817 output_reload_insns[rl->opnum] = get_insns ();
6819 if (flag_non_call_exceptions)
6820 copy_eh_notes (insn, get_insns ());
6825 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6826 and has the number J. */
6828 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6830 rtx insn = chain->insn;
6831 rtx old = (rl->in && MEM_P (rl->in)
6832 ? rl->in_reg : rl->in);
6835 /* AUTO_INC reloads need to be handled even if inherited. We got an
6836 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6837 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6838 && ! rtx_equal_p (rl->reg_rtx, old)
6839 && rl->reg_rtx != 0)
6840 emit_input_reload_insns (chain, rld + j, old, j);
6842 /* When inheriting a wider reload, we have a MEM in rl->in,
6843 e.g. inheriting a SImode output reload for
6844 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6845 if (optimize && reload_inherited[j] && rl->in
6847 && MEM_P (rl->in_reg)
6848 && reload_spill_index[j] >= 0
6849 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6850 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6852 /* If we are reloading a register that was recently stored in with an
6853 output-reload, see if we can prove there was
6854 actually no need to store the old value in it. */
6857 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6858 that there may be multiple uses of the previous output reload.
6859 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
6860 && rl->when_needed == RELOAD_FOR_INPUT
6861 && (reload_inherited[j] || reload_override_in[j])
6863 && REG_P (rl->reg_rtx)
6864 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6866 /* There doesn't seem to be any reason to restrict this to pseudos
6867 and doing so loses in the case where we are copying from a
6868 register of the wrong class. */
6869 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6870 >= FIRST_PSEUDO_REGISTER)
6872 /* The insn might have already some references to stackslots
6873 replaced by MEMs, while reload_out_reg still names the
6875 && (dead_or_set_p (insn,
6876 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6877 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6879 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6882 /* Do output reloading for reload RL, which is for the insn described by
6883 CHAIN and has the number J.
6884 ??? At some point we need to support handling output reloads of
6885 JUMP_INSNs or insns that set cc0. */
6887 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6890 rtx insn = chain->insn;
6891 /* If this is an output reload that stores something that is
6892 not loaded in this same reload, see if we can eliminate a previous
6894 rtx pseudo = rl->out_reg;
6899 && ! rtx_equal_p (rl->in_reg, pseudo)
6900 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6901 && reg_last_reload_reg[REGNO (pseudo)])
6903 int pseudo_no = REGNO (pseudo);
6904 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6906 /* We don't need to test full validity of last_regno for
6907 inherit here; we only want to know if the store actually
6908 matches the pseudo. */
6909 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6910 && reg_reloaded_contents[last_regno] == pseudo_no
6911 && spill_reg_store[last_regno]
6912 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6913 delete_output_reload (insn, j, last_regno);
6918 || rl->reg_rtx == old
6919 || rl->reg_rtx == 0)
6922 /* An output operand that dies right away does need a reload,
6923 but need not be copied from it. Show the new location in the
6925 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6926 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6928 XEXP (note, 0) = rl->reg_rtx;
6931 /* Likewise for a SUBREG of an operand that dies. */
6932 else if (GET_CODE (old) == SUBREG
6933 && REG_P (SUBREG_REG (old))
6934 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6937 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6941 else if (GET_CODE (old) == SCRATCH)
6942 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6943 but we don't want to make an output reload. */
6946 /* If is a JUMP_INSN, we can't support output reloads yet. */
6947 gcc_assert (!JUMP_P (insn));
6949 emit_output_reload_insns (chain, rld + j, j);
6952 /* Reload number R reloads from or to a group of hard registers starting at
6953 register REGNO. Return true if it can be treated for inheritance purposes
6954 like a group of reloads, each one reloading a single hard register.
6955 The caller has already checked that the spill register and REGNO use
6956 the same number of registers to store the reload value. */
6959 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6961 #ifdef CANNOT_CHANGE_MODE_CLASS
6962 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6963 GET_MODE (rld[r].reg_rtx),
6964 reg_raw_mode[reload_spill_index[r]])
6965 && !REG_CANNOT_CHANGE_MODE_P (regno,
6966 GET_MODE (rld[r].reg_rtx),
6967 reg_raw_mode[regno]));
6973 /* Output insns to reload values in and out of the chosen reload regs. */
6976 emit_reload_insns (struct insn_chain *chain)
6978 rtx insn = chain->insn;
6982 CLEAR_HARD_REG_SET (reg_reloaded_died);
6984 for (j = 0; j < reload_n_operands; j++)
6985 input_reload_insns[j] = input_address_reload_insns[j]
6986 = inpaddr_address_reload_insns[j]
6987 = output_reload_insns[j] = output_address_reload_insns[j]
6988 = outaddr_address_reload_insns[j]
6989 = other_output_reload_insns[j] = 0;
6990 other_input_address_reload_insns = 0;
6991 other_input_reload_insns = 0;
6992 operand_reload_insns = 0;
6993 other_operand_reload_insns = 0;
6995 /* Dump reloads into the dump file. */
6998 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6999 debug_reload_to_stream (dump_file);
7002 /* Now output the instructions to copy the data into and out of the
7003 reload registers. Do these in the order that the reloads were reported,
7004 since reloads of base and index registers precede reloads of operands
7005 and the operands may need the base and index registers reloaded. */
7007 for (j = 0; j < n_reloads; j++)
7010 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7011 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7013 do_input_reload (chain, rld + j, j);
7014 do_output_reload (chain, rld + j, j);
7017 /* Now write all the insns we made for reloads in the order expected by
7018 the allocation functions. Prior to the insn being reloaded, we write
7019 the following reloads:
7021 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7023 RELOAD_OTHER reloads.
7025 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7026 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7027 RELOAD_FOR_INPUT reload for the operand.
7029 RELOAD_FOR_OPADDR_ADDRS reloads.
7031 RELOAD_FOR_OPERAND_ADDRESS reloads.
7033 After the insn being reloaded, we write the following:
7035 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7036 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7037 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7038 reloads for the operand. The RELOAD_OTHER output reloads are
7039 output in descending order by reload number. */
7041 emit_insn_before (other_input_address_reload_insns, insn);
7042 emit_insn_before (other_input_reload_insns, insn);
7044 for (j = 0; j < reload_n_operands; j++)
7046 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7047 emit_insn_before (input_address_reload_insns[j], insn);
7048 emit_insn_before (input_reload_insns[j], insn);
7051 emit_insn_before (other_operand_reload_insns, insn);
7052 emit_insn_before (operand_reload_insns, insn);
7054 for (j = 0; j < reload_n_operands; j++)
7056 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7057 x = emit_insn_after (output_address_reload_insns[j], x);
7058 x = emit_insn_after (output_reload_insns[j], x);
7059 emit_insn_after (other_output_reload_insns[j], x);
7062 /* For all the spill regs newly reloaded in this instruction,
7063 record what they were reloaded from, so subsequent instructions
7064 can inherit the reloads.
7066 Update spill_reg_store for the reloads of this insn.
7067 Copy the elements that were updated in the loop above. */
7069 for (j = 0; j < n_reloads; j++)
7071 int r = reload_order[j];
7072 int i = reload_spill_index[r];
7074 /* If this is a non-inherited input reload from a pseudo, we must
7075 clear any memory of a previous store to the same pseudo. Only do
7076 something if there will not be an output reload for the pseudo
7078 if (rld[r].in_reg != 0
7079 && ! (reload_inherited[r] || reload_override_in[r]))
7081 rtx reg = rld[r].in_reg;
7083 if (GET_CODE (reg) == SUBREG)
7084 reg = SUBREG_REG (reg);
7087 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7088 && ! reg_has_output_reload[REGNO (reg)])
7090 int nregno = REGNO (reg);
7092 if (reg_last_reload_reg[nregno])
7094 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7096 if (reg_reloaded_contents[last_regno] == nregno)
7097 spill_reg_store[last_regno] = 0;
7102 /* I is nonneg if this reload used a register.
7103 If rld[r].reg_rtx is 0, this is an optional reload
7104 that we opted to ignore. */
7106 if (i >= 0 && rld[r].reg_rtx != 0)
7108 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7110 int part_reaches_end = 0;
7111 int all_reaches_end = 1;
7113 /* For a multi register reload, we need to check if all or part
7114 of the value lives to the end. */
7115 for (k = 0; k < nr; k++)
7117 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7118 rld[r].when_needed))
7119 part_reaches_end = 1;
7121 all_reaches_end = 0;
7124 /* Ignore reloads that don't reach the end of the insn in
7126 if (all_reaches_end)
7128 /* First, clear out memory of what used to be in this spill reg.
7129 If consecutive registers are used, clear them all. */
7131 for (k = 0; k < nr; k++)
7133 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7134 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7137 /* Maybe the spill reg contains a copy of reload_out. */
7139 && (REG_P (rld[r].out)
7143 || REG_P (rld[r].out_reg)))
7145 rtx out = (REG_P (rld[r].out)
7149 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7150 int nregno = REGNO (out);
7151 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7152 : hard_regno_nregs[nregno]
7153 [GET_MODE (rld[r].reg_rtx)]);
7156 spill_reg_store[i] = new_spill_reg_store[i];
7157 spill_reg_stored_to[i] = out;
7158 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7160 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7162 && inherit_piecemeal_p (r, nregno));
7164 /* If NREGNO is a hard register, it may occupy more than
7165 one register. If it does, say what is in the
7166 rest of the registers assuming that both registers
7167 agree on how many words the object takes. If not,
7168 invalidate the subsequent registers. */
7170 if (nregno < FIRST_PSEUDO_REGISTER)
7171 for (k = 1; k < nnr; k++)
7172 reg_last_reload_reg[nregno + k]
7174 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7177 /* Now do the inverse operation. */
7178 for (k = 0; k < nr; k++)
7180 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7181 reg_reloaded_contents[i + k]
7182 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7185 reg_reloaded_insn[i + k] = insn;
7186 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7187 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7188 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7192 /* Maybe the spill reg contains a copy of reload_in. Only do
7193 something if there will not be an output reload for
7194 the register being reloaded. */
7195 else if (rld[r].out_reg == 0
7197 && ((REG_P (rld[r].in)
7198 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7199 && ! reg_has_output_reload[REGNO (rld[r].in)])
7200 || (REG_P (rld[r].in_reg)
7201 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7202 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7209 if (REG_P (rld[r].in)
7210 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7212 else if (REG_P (rld[r].in_reg))
7215 in = XEXP (rld[r].in_reg, 0);
7216 nregno = REGNO (in);
7218 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7219 : hard_regno_nregs[nregno]
7220 [GET_MODE (rld[r].reg_rtx)]);
7222 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7224 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7226 && inherit_piecemeal_p (r, nregno));
7228 if (nregno < FIRST_PSEUDO_REGISTER)
7229 for (k = 1; k < nnr; k++)
7230 reg_last_reload_reg[nregno + k]
7232 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7235 /* Unless we inherited this reload, show we haven't
7236 recently done a store.
7237 Previous stores of inherited auto_inc expressions
7238 also have to be discarded. */
7239 if (! reload_inherited[r]
7240 || (rld[r].out && ! rld[r].out_reg))
7241 spill_reg_store[i] = 0;
7243 for (k = 0; k < nr; k++)
7245 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7246 reg_reloaded_contents[i + k]
7247 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7250 reg_reloaded_insn[i + k] = insn;
7251 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7252 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7253 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7258 /* However, if part of the reload reaches the end, then we must
7259 invalidate the old info for the part that survives to the end. */
7260 else if (part_reaches_end)
7262 for (k = 0; k < nr; k++)
7263 if (reload_reg_reaches_end_p (i + k,
7265 rld[r].when_needed))
7266 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7270 /* The following if-statement was #if 0'd in 1.34 (or before...).
7271 It's reenabled in 1.35 because supposedly nothing else
7272 deals with this problem. */
7274 /* If a register gets output-reloaded from a non-spill register,
7275 that invalidates any previous reloaded copy of it.
7276 But forget_old_reloads_1 won't get to see it, because
7277 it thinks only about the original insn. So invalidate it here. */
7278 if (i < 0 && rld[r].out != 0
7279 && (REG_P (rld[r].out)
7280 || (MEM_P (rld[r].out)
7281 && REG_P (rld[r].out_reg))))
7283 rtx out = (REG_P (rld[r].out)
7284 ? rld[r].out : rld[r].out_reg);
7285 int nregno = REGNO (out);
7286 if (nregno >= FIRST_PSEUDO_REGISTER)
7288 rtx src_reg, store_insn = NULL_RTX;
7290 reg_last_reload_reg[nregno] = 0;
7292 /* If we can find a hard register that is stored, record
7293 the storing insn so that we may delete this insn with
7294 delete_output_reload. */
7295 src_reg = rld[r].reg_rtx;
7297 /* If this is an optional reload, try to find the source reg
7298 from an input reload. */
7301 rtx set = single_set (insn);
7302 if (set && SET_DEST (set) == rld[r].out)
7306 src_reg = SET_SRC (set);
7308 for (k = 0; k < n_reloads; k++)
7310 if (rld[k].in == src_reg)
7312 src_reg = rld[k].reg_rtx;
7319 store_insn = new_spill_reg_store[REGNO (src_reg)];
7320 if (src_reg && REG_P (src_reg)
7321 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7323 int src_regno = REGNO (src_reg);
7324 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7325 /* The place where to find a death note varies with
7326 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7327 necessarily checked exactly in the code that moves
7328 notes, so just check both locations. */
7329 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7330 if (! note && store_insn)
7331 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7334 spill_reg_store[src_regno + nr] = store_insn;
7335 spill_reg_stored_to[src_regno + nr] = out;
7336 reg_reloaded_contents[src_regno + nr] = nregno;
7337 reg_reloaded_insn[src_regno + nr] = store_insn;
7338 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7339 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7340 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7341 GET_MODE (src_reg)))
7342 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7344 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7346 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7348 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7350 reg_last_reload_reg[nregno] = src_reg;
7351 /* We have to set reg_has_output_reload here, or else
7352 forget_old_reloads_1 will clear reg_last_reload_reg
7354 reg_has_output_reload[nregno] = 1;
7359 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7361 while (num_regs-- > 0)
7362 reg_last_reload_reg[nregno + num_regs] = 0;
7366 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7369 /* Emit code to perform a reload from IN (which may be a reload register) to
7370 OUT (which may also be a reload register). IN or OUT is from operand
7371 OPNUM with reload type TYPE.
7373 Returns first insn emitted. */
7376 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7378 rtx last = get_last_insn ();
7381 /* If IN is a paradoxical SUBREG, remove it and try to put the
7382 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7383 if (GET_CODE (in) == SUBREG
7384 && (GET_MODE_SIZE (GET_MODE (in))
7385 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7386 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7387 in = SUBREG_REG (in), out = tem;
7388 else if (GET_CODE (out) == SUBREG
7389 && (GET_MODE_SIZE (GET_MODE (out))
7390 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7391 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7392 out = SUBREG_REG (out), in = tem;
7394 /* How to do this reload can get quite tricky. Normally, we are being
7395 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7396 register that didn't get a hard register. In that case we can just
7397 call emit_move_insn.
7399 We can also be asked to reload a PLUS that adds a register or a MEM to
7400 another register, constant or MEM. This can occur during frame pointer
7401 elimination and while reloading addresses. This case is handled by
7402 trying to emit a single insn to perform the add. If it is not valid,
7403 we use a two insn sequence.
7405 Finally, we could be called to handle an 'o' constraint by putting
7406 an address into a register. In that case, we first try to do this
7407 with a named pattern of "reload_load_address". If no such pattern
7408 exists, we just emit a SET insn and hope for the best (it will normally
7409 be valid on machines that use 'o').
7411 This entire process is made complex because reload will never
7412 process the insns we generate here and so we must ensure that
7413 they will fit their constraints and also by the fact that parts of
7414 IN might be being reloaded separately and replaced with spill registers.
7415 Because of this, we are, in some sense, just guessing the right approach
7416 here. The one listed above seems to work.
7418 ??? At some point, this whole thing needs to be rethought. */
7420 if (GET_CODE (in) == PLUS
7421 && (REG_P (XEXP (in, 0))
7422 || GET_CODE (XEXP (in, 0)) == SUBREG
7423 || MEM_P (XEXP (in, 0)))
7424 && (REG_P (XEXP (in, 1))
7425 || GET_CODE (XEXP (in, 1)) == SUBREG
7426 || CONSTANT_P (XEXP (in, 1))
7427 || MEM_P (XEXP (in, 1))))
7429 /* We need to compute the sum of a register or a MEM and another
7430 register, constant, or MEM, and put it into the reload
7431 register. The best possible way of doing this is if the machine
7432 has a three-operand ADD insn that accepts the required operands.
7434 The simplest approach is to try to generate such an insn and see if it
7435 is recognized and matches its constraints. If so, it can be used.
7437 It might be better not to actually emit the insn unless it is valid,
7438 but we need to pass the insn as an operand to `recog' and
7439 `extract_insn' and it is simpler to emit and then delete the insn if
7440 not valid than to dummy things up. */
7442 rtx op0, op1, tem, insn;
7445 op0 = find_replacement (&XEXP (in, 0));
7446 op1 = find_replacement (&XEXP (in, 1));
7448 /* Since constraint checking is strict, commutativity won't be
7449 checked, so we need to do that here to avoid spurious failure
7450 if the add instruction is two-address and the second operand
7451 of the add is the same as the reload reg, which is frequently
7452 the case. If the insn would be A = B + A, rearrange it so
7453 it will be A = A + B as constrain_operands expects. */
7455 if (REG_P (XEXP (in, 1))
7456 && REGNO (out) == REGNO (XEXP (in, 1)))
7457 tem = op0, op0 = op1, op1 = tem;
7459 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7460 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7462 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7463 code = recog_memoized (insn);
7467 extract_insn (insn);
7468 /* We want constrain operands to treat this insn strictly in
7469 its validity determination, i.e., the way it would after reload
7471 if (constrain_operands (1))
7475 delete_insns_since (last);
7477 /* If that failed, we must use a conservative two-insn sequence.
7479 Use a move to copy one operand into the reload register. Prefer
7480 to reload a constant, MEM or pseudo since the move patterns can
7481 handle an arbitrary operand. If OP1 is not a constant, MEM or
7482 pseudo and OP1 is not a valid operand for an add instruction, then
7485 After reloading one of the operands into the reload register, add
7486 the reload register to the output register.
7488 If there is another way to do this for a specific machine, a
7489 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7492 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7494 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7496 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7497 || (code != CODE_FOR_nothing
7498 && ! ((*insn_data[code].operand[2].predicate)
7499 (op1, insn_data[code].operand[2].mode))))
7500 tem = op0, op0 = op1, op1 = tem;
7502 gen_reload (out, op0, opnum, type);
7504 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7505 This fixes a problem on the 32K where the stack pointer cannot
7506 be used as an operand of an add insn. */
7508 if (rtx_equal_p (op0, op1))
7511 insn = emit_insn (gen_add2_insn (out, op1));
7513 /* If that failed, copy the address register to the reload register.
7514 Then add the constant to the reload register. */
7516 code = recog_memoized (insn);
7520 extract_insn (insn);
7521 /* We want constrain operands to treat this insn strictly in
7522 its validity determination, i.e., the way it would after reload
7524 if (constrain_operands (1))
7526 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7528 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7533 delete_insns_since (last);
7535 gen_reload (out, op1, opnum, type);
7536 insn = emit_insn (gen_add2_insn (out, op0));
7537 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7540 #ifdef SECONDARY_MEMORY_NEEDED
7541 /* If we need a memory location to do the move, do it that way. */
7542 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7543 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7544 && (REG_P (out) || GET_CODE (out) == SUBREG)
7545 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7546 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7547 REGNO_REG_CLASS (reg_or_subregno (out)),
7550 /* Get the memory to use and rewrite both registers to its mode. */
7551 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7553 if (GET_MODE (loc) != GET_MODE (out))
7554 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7556 if (GET_MODE (loc) != GET_MODE (in))
7557 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7559 gen_reload (loc, in, opnum, type);
7560 gen_reload (out, loc, opnum, type);
7564 /* If IN is a simple operand, use gen_move_insn. */
7565 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7566 emit_insn (gen_move_insn (out, in));
7568 #ifdef HAVE_reload_load_address
7569 else if (HAVE_reload_load_address)
7570 emit_insn (gen_reload_load_address (out, in));
7573 /* Otherwise, just write (set OUT IN) and hope for the best. */
7575 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7577 /* Return the first insn emitted.
7578 We can not just return get_last_insn, because there may have
7579 been multiple instructions emitted. Also note that gen_move_insn may
7580 emit more than one insn itself, so we can not assume that there is one
7581 insn emitted per emit_insn_before call. */
7583 return last ? NEXT_INSN (last) : get_insns ();
7586 /* Delete a previously made output-reload whose result we now believe
7587 is not needed. First we double-check.
7589 INSN is the insn now being processed.
7590 LAST_RELOAD_REG is the hard register number for which we want to delete
7591 the last output reload.
7592 J is the reload-number that originally used REG. The caller has made
7593 certain that reload J doesn't use REG any longer for input. */
7596 delete_output_reload (rtx insn, int j, int last_reload_reg)
7598 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7599 rtx reg = spill_reg_stored_to[last_reload_reg];
7602 int n_inherited = 0;
7606 /* It is possible that this reload has been only used to set another reload
7607 we eliminated earlier and thus deleted this instruction too. */
7608 if (INSN_DELETED_P (output_reload_insn))
7611 /* Get the raw pseudo-register referred to. */
7613 while (GET_CODE (reg) == SUBREG)
7614 reg = SUBREG_REG (reg);
7615 substed = reg_equiv_memory_loc[REGNO (reg)];
7617 /* This is unsafe if the operand occurs more often in the current
7618 insn than it is inherited. */
7619 for (k = n_reloads - 1; k >= 0; k--)
7621 rtx reg2 = rld[k].in;
7624 if (MEM_P (reg2) || reload_override_in[k])
7625 reg2 = rld[k].in_reg;
7627 if (rld[k].out && ! rld[k].out_reg)
7628 reg2 = XEXP (rld[k].in_reg, 0);
7630 while (GET_CODE (reg2) == SUBREG)
7631 reg2 = SUBREG_REG (reg2);
7632 if (rtx_equal_p (reg2, reg))
7634 if (reload_inherited[k] || reload_override_in[k] || k == j)
7637 reg2 = rld[k].out_reg;
7640 while (GET_CODE (reg2) == SUBREG)
7641 reg2 = XEXP (reg2, 0);
7642 if (rtx_equal_p (reg2, reg))
7649 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7651 n_occurrences += count_occurrences (PATTERN (insn),
7652 eliminate_regs (substed, 0,
7654 if (n_occurrences > n_inherited)
7657 /* If the pseudo-reg we are reloading is no longer referenced
7658 anywhere between the store into it and here,
7659 and we're within the same basic block, then the value can only
7660 pass through the reload reg and end up here.
7661 Otherwise, give up--return. */
7662 for (i1 = NEXT_INSN (output_reload_insn);
7663 i1 != insn; i1 = NEXT_INSN (i1))
7665 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7667 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7668 && reg_mentioned_p (reg, PATTERN (i1)))
7670 /* If this is USE in front of INSN, we only have to check that
7671 there are no more references than accounted for by inheritance. */
7672 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7674 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7675 i1 = NEXT_INSN (i1);
7677 if (n_occurrences <= n_inherited && i1 == insn)
7683 /* We will be deleting the insn. Remove the spill reg information. */
7684 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7686 spill_reg_store[last_reload_reg + k] = 0;
7687 spill_reg_stored_to[last_reload_reg + k] = 0;
7690 /* The caller has already checked that REG dies or is set in INSN.
7691 It has also checked that we are optimizing, and thus some
7692 inaccuracies in the debugging information are acceptable.
7693 So we could just delete output_reload_insn. But in some cases
7694 we can improve the debugging information without sacrificing
7695 optimization - maybe even improving the code: See if the pseudo
7696 reg has been completely replaced with reload regs. If so, delete
7697 the store insn and forget we had a stack slot for the pseudo. */
7698 if (rld[j].out != rld[j].in
7699 && REG_N_DEATHS (REGNO (reg)) == 1
7700 && REG_N_SETS (REGNO (reg)) == 1
7701 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7702 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7706 /* We know that it was used only between here and the beginning of
7707 the current basic block. (We also know that the last use before
7708 INSN was the output reload we are thinking of deleting, but never
7709 mind that.) Search that range; see if any ref remains. */
7710 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7712 rtx set = single_set (i2);
7714 /* Uses which just store in the pseudo don't count,
7715 since if they are the only uses, they are dead. */
7716 if (set != 0 && SET_DEST (set) == reg)
7721 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7722 && reg_mentioned_p (reg, PATTERN (i2)))
7724 /* Some other ref remains; just delete the output reload we
7726 delete_address_reloads (output_reload_insn, insn);
7727 delete_insn (output_reload_insn);
7732 /* Delete the now-dead stores into this pseudo. Note that this
7733 loop also takes care of deleting output_reload_insn. */
7734 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7736 rtx set = single_set (i2);
7738 if (set != 0 && SET_DEST (set) == reg)
7740 delete_address_reloads (i2, insn);
7748 /* For the debugging info, say the pseudo lives in this reload reg. */
7749 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7750 alter_reg (REGNO (reg), -1);
7754 delete_address_reloads (output_reload_insn, insn);
7755 delete_insn (output_reload_insn);
7759 /* We are going to delete DEAD_INSN. Recursively delete loads of
7760 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7761 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7763 delete_address_reloads (rtx dead_insn, rtx current_insn)
7765 rtx set = single_set (dead_insn);
7766 rtx set2, dst, prev, next;
7769 rtx dst = SET_DEST (set);
7771 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7773 /* If we deleted the store from a reloaded post_{in,de}c expression,
7774 we can delete the matching adds. */
7775 prev = PREV_INSN (dead_insn);
7776 next = NEXT_INSN (dead_insn);
7777 if (! prev || ! next)
7779 set = single_set (next);
7780 set2 = single_set (prev);
7782 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7783 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7784 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7786 dst = SET_DEST (set);
7787 if (! rtx_equal_p (dst, SET_DEST (set2))
7788 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7789 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7790 || (INTVAL (XEXP (SET_SRC (set), 1))
7791 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7793 delete_related_insns (prev);
7794 delete_related_insns (next);
7797 /* Subfunction of delete_address_reloads: process registers found in X. */
7799 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7801 rtx prev, set, dst, i2;
7803 enum rtx_code code = GET_CODE (x);
7807 const char *fmt = GET_RTX_FORMAT (code);
7808 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7811 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7812 else if (fmt[i] == 'E')
7814 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7815 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7822 if (spill_reg_order[REGNO (x)] < 0)
7825 /* Scan backwards for the insn that sets x. This might be a way back due
7827 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7829 code = GET_CODE (prev);
7830 if (code == CODE_LABEL || code == JUMP_INSN)
7834 if (reg_set_p (x, PATTERN (prev)))
7836 if (reg_referenced_p (x, PATTERN (prev)))
7839 if (! prev || INSN_UID (prev) < reload_first_uid)
7841 /* Check that PREV only sets the reload register. */
7842 set = single_set (prev);
7845 dst = SET_DEST (set);
7847 || ! rtx_equal_p (dst, x))
7849 if (! reg_set_p (dst, PATTERN (dead_insn)))
7851 /* Check if DST was used in a later insn -
7852 it might have been inherited. */
7853 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7859 if (reg_referenced_p (dst, PATTERN (i2)))
7861 /* If there is a reference to the register in the current insn,
7862 it might be loaded in a non-inherited reload. If no other
7863 reload uses it, that means the register is set before
7865 if (i2 == current_insn)
7867 for (j = n_reloads - 1; j >= 0; j--)
7868 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7869 || reload_override_in[j] == dst)
7871 for (j = n_reloads - 1; j >= 0; j--)
7872 if (rld[j].in && rld[j].reg_rtx == dst)
7881 /* If DST is still live at CURRENT_INSN, check if it is used for
7882 any reload. Note that even if CURRENT_INSN sets DST, we still
7883 have to check the reloads. */
7884 if (i2 == current_insn)
7886 for (j = n_reloads - 1; j >= 0; j--)
7887 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7888 || reload_override_in[j] == dst)
7890 /* ??? We can't finish the loop here, because dst might be
7891 allocated to a pseudo in this block if no reload in this
7892 block needs any of the classes containing DST - see
7893 spill_hard_reg. There is no easy way to tell this, so we
7894 have to scan till the end of the basic block. */
7896 if (reg_set_p (dst, PATTERN (i2)))
7900 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7901 reg_reloaded_contents[REGNO (dst)] = -1;
7905 /* Output reload-insns to reload VALUE into RELOADREG.
7906 VALUE is an autoincrement or autodecrement RTX whose operand
7907 is a register or memory location;
7908 so reloading involves incrementing that location.
7909 IN is either identical to VALUE, or some cheaper place to reload from.
7911 INC_AMOUNT is the number to increment or decrement by (always positive).
7912 This cannot be deduced from VALUE.
7914 Return the instruction that stores into RELOADREG. */
7917 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7919 /* REG or MEM to be copied and incremented. */
7920 rtx incloc = XEXP (value, 0);
7921 /* Nonzero if increment after copying. */
7922 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7928 rtx real_in = in == value ? XEXP (in, 0) : in;
7930 /* No hard register is equivalent to this register after
7931 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7932 we could inc/dec that register as well (maybe even using it for
7933 the source), but I'm not sure it's worth worrying about. */
7935 reg_last_reload_reg[REGNO (incloc)] = 0;
7937 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7938 inc_amount = -inc_amount;
7940 inc = GEN_INT (inc_amount);
7942 /* If this is post-increment, first copy the location to the reload reg. */
7943 if (post && real_in != reloadreg)
7944 emit_insn (gen_move_insn (reloadreg, real_in));
7948 /* See if we can directly increment INCLOC. Use a method similar to
7949 that in gen_reload. */
7951 last = get_last_insn ();
7952 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7953 gen_rtx_PLUS (GET_MODE (incloc),
7956 code = recog_memoized (add_insn);
7959 extract_insn (add_insn);
7960 if (constrain_operands (1))
7962 /* If this is a pre-increment and we have incremented the value
7963 where it lives, copy the incremented value to RELOADREG to
7964 be used as an address. */
7967 emit_insn (gen_move_insn (reloadreg, incloc));
7972 delete_insns_since (last);
7975 /* If couldn't do the increment directly, must increment in RELOADREG.
7976 The way we do this depends on whether this is pre- or post-increment.
7977 For pre-increment, copy INCLOC to the reload register, increment it
7978 there, then save back. */
7982 if (in != reloadreg)
7983 emit_insn (gen_move_insn (reloadreg, real_in));
7984 emit_insn (gen_add2_insn (reloadreg, inc));
7985 store = emit_insn (gen_move_insn (incloc, reloadreg));
7990 Because this might be a jump insn or a compare, and because RELOADREG
7991 may not be available after the insn in an input reload, we must do
7992 the incrementation before the insn being reloaded for.
7994 We have already copied IN to RELOADREG. Increment the copy in
7995 RELOADREG, save that back, then decrement RELOADREG so it has
7996 the original value. */
7998 emit_insn (gen_add2_insn (reloadreg, inc));
7999 store = emit_insn (gen_move_insn (incloc, reloadreg));
8000 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
8008 add_auto_inc_notes (rtx insn, rtx x)
8010 enum rtx_code code = GET_CODE (x);
8014 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8017 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8021 /* Scan all the operand sub-expressions. */
8022 fmt = GET_RTX_FORMAT (code);
8023 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8026 add_auto_inc_notes (insn, XEXP (x, i));
8027 else if (fmt[i] == 'E')
8028 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8029 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8034 /* Copy EH notes from an insn to its reloads. */
8036 copy_eh_notes (rtx insn, rtx x)
8038 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8041 for (; x != 0; x = NEXT_INSN (x))
8043 if (may_trap_p (PATTERN (x)))
8045 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8051 /* This is used by reload pass, that does emit some instructions after
8052 abnormal calls moving basic block end, but in fact it wants to emit
8053 them on the edge. Looks for abnormal call edges, find backward the
8054 proper call and fix the damage.
8056 Similar handle instructions throwing exceptions internally. */
8058 fixup_abnormal_edges (void)
8060 bool inserted = false;
8068 /* Look for cases we are interested in - calls or instructions causing
8070 FOR_EACH_EDGE (e, ei, bb->succs)
8072 if (e->flags & EDGE_ABNORMAL_CALL)
8074 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8075 == (EDGE_ABNORMAL | EDGE_EH))
8078 if (e && !CALL_P (BB_END (bb))
8079 && !can_throw_internal (BB_END (bb)))
8081 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8083 FOR_EACH_EDGE (e, ei, bb->succs)
8084 if (e->flags & EDGE_FALLTHRU)
8086 /* Get past the new insns generated. Allow notes, as the insns may
8087 be already deleted. */
8088 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8089 && !can_throw_internal (insn)
8090 && insn != BB_HEAD (bb))
8091 insn = PREV_INSN (insn);
8092 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8095 insn = NEXT_INSN (insn);
8096 while (insn && insn != stop)
8098 next = NEXT_INSN (insn);
8103 /* Sometimes there's still the return value USE.
8104 If it's placed after a trapping call (i.e. that
8105 call is the last insn anyway), we have no fallthru
8106 edge. Simply delete this use and don't try to insert
8107 on the non-existent edge. */
8108 if (GET_CODE (PATTERN (insn)) != USE)
8110 /* We're not deleting it, we're moving it. */
8111 INSN_DELETED_P (insn) = 0;
8112 PREV_INSN (insn) = NULL_RTX;
8113 NEXT_INSN (insn) = NULL_RTX;
8115 insert_insn_on_edge (insn, e);
8122 /* We've possibly turned single trapping insn into multiple ones. */
8123 if (flag_non_call_exceptions)
8126 blocks = sbitmap_alloc (last_basic_block);
8127 sbitmap_ones (blocks);
8128 find_many_sub_basic_blocks (blocks);
8131 commit_edge_insertions ();
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