1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91, 92, 93, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This file contains two passes of the compiler: reg_scan and reg_class.
22 It also defines some tables of information about the hardware registers
23 and a function init_reg_sets to initialize the tables. */
27 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
37 #ifndef REGISTER_MOVE_COST
38 #define REGISTER_MOVE_COST(x, y) 2
41 #ifndef MEMORY_MOVE_COST
42 #define MEMORY_MOVE_COST(x) 4
45 /* If we have auto-increment or auto-decrement and we can have secondary
46 reloads, we are not allowed to use classes requiring secondary
47 reloads for psuedos auto-incremented since reload can't handle it. */
50 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
51 #define FORBIDDEN_INC_DEC_CLASSES
55 /* Register tables used by many passes. */
57 /* Indexed by hard register number, contains 1 for registers
58 that are fixed use (stack pointer, pc, frame pointer, etc.).
59 These are the registers that cannot be used to allocate
60 a pseudo reg whose life does not cross calls. */
62 char fixed_regs[FIRST_PSEUDO_REGISTER];
64 /* Same info as a HARD_REG_SET. */
66 HARD_REG_SET fixed_reg_set;
68 /* Data for initializing the above. */
70 static char initial_fixed_regs[] = FIXED_REGISTERS;
72 /* Indexed by hard register number, contains 1 for registers
73 that are fixed use or are clobbered by function calls.
74 These are the registers that cannot be used to allocate
75 a pseudo reg whose life crosses calls. */
77 char call_used_regs[FIRST_PSEUDO_REGISTER];
79 /* Same info as a HARD_REG_SET. */
81 HARD_REG_SET call_used_reg_set;
83 /* Data for initializing the above. */
85 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
87 /* Indexed by hard register number, contains 1 for registers that are
88 fixed use -- i.e. in fixed_regs -- or a function value return register
89 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
90 registers that cannot hold quantities across calls even if we are
91 willing to save and restore them. */
93 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
95 /* The same info as a HARD_REG_SET. */
97 HARD_REG_SET call_fixed_reg_set;
99 /* Number of non-fixed registers. */
101 int n_non_fixed_regs;
103 /* Indexed by hard register number, contains 1 for registers
104 that are being used for global register decls.
105 These must be exempt from ordinary flow analysis
106 and are also considered fixed. */
108 char global_regs[FIRST_PSEUDO_REGISTER];
110 /* Table of register numbers in the order in which to try to use them. */
111 #ifdef REG_ALLOC_ORDER
112 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
115 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
117 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
119 /* The same information, but as an array of unsigned ints. We copy from
120 these unsigned ints to the table above. We do this so the tm.h files
121 do not have to be aware of the wordsize for machines with <= 64 regs. */
124 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
126 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
127 = REG_CLASS_CONTENTS;
129 /* For each reg class, number of regs it contains. */
131 int reg_class_size[N_REG_CLASSES];
133 /* For each reg class, table listing all the containing classes. */
135 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
137 /* For each reg class, table listing all the classes contained in it. */
139 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
141 /* For each pair of reg classes,
142 a largest reg class contained in their union. */
144 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
146 /* For each pair of reg classes,
147 the smallest reg class containing their union. */
149 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
151 /* Array containing all of the register names */
153 char *reg_names[] = REGISTER_NAMES;
155 /* For each hard register, the widest mode object that it can contain.
156 This will be a MODE_INT mode if the register can hold integers. Otherwise
157 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
160 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
162 /* Indexed by n, gives number of times (REG n) is set or clobbered.
163 This information remains valid for the rest of the compilation
164 of the current function; it is used to control register allocation.
166 This information applies to both hard registers and pseudo registers,
167 unlike much of the information above. */
171 /* Maximum cost of moving from a register in one class to a register in
172 another class. Based on REGISTER_MOVE_COST. */
174 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
176 /* Similar, but here we don't have to move if the first index is a subset
177 of the second so in that case the cost is zero. */
179 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
181 #ifdef FORBIDDEN_INC_DEC_CLASSES
183 /* These are the classes that regs which are auto-incremented or decremented
186 static int forbidden_inc_dec_class[N_REG_CLASSES];
188 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
191 static char *in_inc_dec;
193 #endif /* FORBIDDEN_INC_DEC_CLASSES */
195 /* Function called only once to initialize the above data on reg usage.
196 Once this is done, various switches may override. */
203 /* First copy the register information from the initial int form into
206 for (i = 0; i < N_REG_CLASSES; i++)
208 CLEAR_HARD_REG_SET (reg_class_contents[i]);
210 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
211 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
212 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
213 SET_HARD_REG_BIT (reg_class_contents[i], j);
216 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
217 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
218 bzero (global_regs, sizeof global_regs);
220 /* Compute number of hard regs in each class. */
222 bzero (reg_class_size, sizeof reg_class_size);
223 for (i = 0; i < N_REG_CLASSES; i++)
224 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
225 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
228 /* Initialize the table of subunions.
229 reg_class_subunion[I][J] gets the largest-numbered reg-class
230 that is contained in the union of classes I and J. */
232 for (i = 0; i < N_REG_CLASSES; i++)
234 for (j = 0; j < N_REG_CLASSES; j++)
237 register /* Declare it register if it's a scalar. */
242 COPY_HARD_REG_SET (c, reg_class_contents[i]);
243 IOR_HARD_REG_SET (c, reg_class_contents[j]);
244 for (k = 0; k < N_REG_CLASSES; k++)
246 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
251 /* keep the largest subclass */ /* SPEE 900308 */
252 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
253 reg_class_contents[(int) reg_class_subunion[i][j]],
255 reg_class_subunion[i][j] = (enum reg_class) k;
262 /* Initialize the table of superunions.
263 reg_class_superunion[I][J] gets the smallest-numbered reg-class
264 containing the union of classes I and J. */
266 for (i = 0; i < N_REG_CLASSES; i++)
268 for (j = 0; j < N_REG_CLASSES; j++)
271 register /* Declare it register if it's a scalar. */
276 COPY_HARD_REG_SET (c, reg_class_contents[i]);
277 IOR_HARD_REG_SET (c, reg_class_contents[j]);
278 for (k = 0; k < N_REG_CLASSES; k++)
279 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
282 reg_class_superunion[i][j] = (enum reg_class) k;
286 /* Initialize the tables of subclasses and superclasses of each reg class.
287 First clear the whole table, then add the elements as they are found. */
289 for (i = 0; i < N_REG_CLASSES; i++)
291 for (j = 0; j < N_REG_CLASSES; j++)
293 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
294 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
298 for (i = 0; i < N_REG_CLASSES; i++)
300 if (i == (int) NO_REGS)
303 for (j = i + 1; j < N_REG_CLASSES; j++)
307 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
311 /* Reg class I is a subclass of J.
312 Add J to the table of superclasses of I. */
313 p = ®_class_superclasses[i][0];
314 while (*p != LIM_REG_CLASSES) p++;
315 *p = (enum reg_class) j;
316 /* Add I to the table of superclasses of J. */
317 p = ®_class_subclasses[j][0];
318 while (*p != LIM_REG_CLASSES) p++;
319 *p = (enum reg_class) i;
323 /* Initialize the move cost table. Find every subset of each class
324 and take the maximum cost of moving any subset to any other. */
326 for (i = 0; i < N_REG_CLASSES; i++)
327 for (j = 0; j < N_REG_CLASSES; j++)
329 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
330 enum reg_class *p1, *p2;
332 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
334 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
336 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
339 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
341 for (p2 = ®_class_subclasses[j][0];
342 *p2 != LIM_REG_CLASSES; p2++)
344 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
347 move_cost[i][j] = cost;
349 if (reg_class_subset_p (i, j))
352 may_move_cost[i][j] = cost;
356 /* After switches have been processed, which perhaps alter
357 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
364 /* This macro allows the fixed or call-used registers
365 to depend on target flags. */
367 #ifdef CONDITIONAL_REGISTER_USAGE
368 CONDITIONAL_REGISTER_USAGE;
371 /* Initialize "constant" tables. */
373 CLEAR_HARD_REG_SET (fixed_reg_set);
374 CLEAR_HARD_REG_SET (call_used_reg_set);
375 CLEAR_HARD_REG_SET (call_fixed_reg_set);
377 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
378 #ifdef STRUCT_VALUE_REGNUM
379 call_fixed_regs[STRUCT_VALUE_REGNUM] = 1;
381 #ifdef STATIC_CHAIN_REGNUM
382 call_fixed_regs[STATIC_CHAIN_REGNUM] = 1;
385 n_non_fixed_regs = 0;
387 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
389 if (FUNCTION_VALUE_REGNO_P (i))
390 call_fixed_regs[i] = 1;
392 SET_HARD_REG_BIT (fixed_reg_set, i);
396 if (call_used_regs[i])
397 SET_HARD_REG_BIT (call_used_reg_set, i);
398 if (call_fixed_regs[i])
399 SET_HARD_REG_BIT (call_fixed_reg_set, i);
403 /* Compute the table of register modes.
404 These values are used to record death information for individual registers
405 (as opposed to a multi-register mode). */
412 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
413 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
416 /* Finish initializing the register sets and
417 initialize the register modes. */
422 /* This finishes what was started by init_reg_sets, but couldn't be done
423 until after register usage was specified. */
424 if (!output_bytecode)
430 /* Return a machine mode that is legitimate for hard reg REGNO and large
431 enough to save nregs. If we can't find one, return VOIDmode. */
434 choose_hard_reg_mode (regno, nregs)
438 enum machine_mode found_mode = VOIDmode, mode;
440 /* We first look for the largest integer mode that can be validly
441 held in REGNO. If none, we look for the largest floating-point mode.
442 If we still didn't find a valid mode, try CCmode. */
444 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
446 mode = GET_MODE_WIDER_MODE (mode))
447 if (HARD_REGNO_NREGS (regno, mode) == nregs
448 && HARD_REGNO_MODE_OK (regno, mode))
451 if (found_mode != VOIDmode)
454 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
456 mode = GET_MODE_WIDER_MODE (mode))
457 if (HARD_REGNO_NREGS (regno, mode) == nregs
458 && HARD_REGNO_MODE_OK (regno, mode))
461 if (found_mode != VOIDmode)
464 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
465 && HARD_REGNO_MODE_OK (regno, CCmode))
468 /* We can't find a mode valid for this register. */
472 /* Specify the usage characteristics of the register named NAME.
473 It should be a fixed register if FIXED and a
474 call-used register if CALL_USED. */
477 fix_register (name, fixed, call_used)
479 int fixed, call_used;
485 warning ("request to mark `%s' as %s ignored by bytecode compiler",
486 name, call_used ? "call-used" : "fixed");
490 /* Decode the name and update the primary form of
491 the register info. */
493 if ((i = decode_reg_name (name)) >= 0)
495 fixed_regs[i] = fixed;
496 call_used_regs[i] = call_used;
500 warning ("unknown register name: %s", name);
504 /* Mark register number I as global. */
512 warning ("register used for two global register variables");
516 if (call_used_regs[i] && ! fixed_regs[i])
517 warning ("call-clobbered register used for global register variable");
521 /* If already fixed, nothing else to do. */
525 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
528 SET_HARD_REG_BIT (fixed_reg_set, i);
529 SET_HARD_REG_BIT (call_used_reg_set, i);
530 SET_HARD_REG_BIT (call_fixed_reg_set, i);
533 /* Now the data and code for the `regclass' pass, which happens
534 just before local-alloc. */
536 /* The `costs' struct records the cost of using a hard register of each class
537 and of using memory for each pseudo. We use this data to set up
538 register class preferences. */
542 int cost[N_REG_CLASSES];
546 /* Record the cost of each class for each pseudo. */
548 static struct costs *costs;
550 /* Record the same data by operand number, accumulated for each alternative
551 in an insn. The contribution to a pseudo is that of the minimum-cost
554 static struct costs op_costs[MAX_RECOG_OPERANDS];
556 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
557 This is available after `regclass' is run. */
559 static char *prefclass;
561 /* altclass[R] is a register class that we should use for allocating
562 pseudo number R if no register in the preferred class is available.
563 If no register in this class is available, memory is preferred.
565 It might appear to be more general to have a bitmask of classes here,
566 but since it is recommended that there be a class corresponding to the
567 union of most major pair of classes, that generality is not required.
569 This is available after `regclass' is run. */
571 static char *altclass;
573 /* Record the depth of loops that we are in. */
575 static int loop_depth;
577 /* Account for the fact that insns within a loop are executed very commonly,
578 but don't keep doing this as loops go too deep. */
580 static int loop_cost;
582 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
584 static int copy_cost PROTO((rtx, enum machine_mode,
585 enum reg_class, int));
586 static void record_address_regs PROTO((rtx, enum reg_class, int));
587 static auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
588 static void reg_scan_mark_refs PROTO((rtx, rtx, int));
590 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
591 This function is sometimes called before the info has been computed.
592 When that happens, just return GENERAL_REGS, which is innocuous. */
595 reg_preferred_class (regno)
600 return (enum reg_class) prefclass[regno];
604 reg_alternate_class (regno)
609 return (enum reg_class) altclass[regno];
612 /* This prevents dump_flow_info from losing if called
613 before regclass is run. */
621 /* This is a pass of the compiler that scans all instructions
622 and calculates the preferred class for each pseudo-register.
623 This information can be accessed later by calling `reg_preferred_class'.
624 This pass comes just before local register allocation. */
631 #ifdef REGISTER_CONSTRAINTS
634 struct costs init_cost;
640 costs = (struct costs *) alloca (nregs * sizeof (struct costs));
642 #ifdef FORBIDDEN_INC_DEC_CLASSES
644 in_inc_dec = (char *) alloca (nregs);
646 /* Initialize information about which register classes can be used for
647 pseudos that are auto-incremented or auto-decremented. It would
648 seem better to put this in init_reg_sets, but we need to be able
649 to allocate rtx, which we can't do that early. */
651 for (i = 0; i < N_REG_CLASSES; i++)
653 rtx r = gen_rtx (REG, VOIDmode, 0);
656 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
657 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
661 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
662 m = (enum machine_mode) ((int) m + 1))
663 if (HARD_REGNO_MODE_OK (j, m))
667 /* If a register is not directly suitable for an
668 auto-increment or decrement addressing mode and
669 requires secondary reloads, disallow its class from
670 being used in such addresses. */
673 #ifdef SECONDARY_INPUT_RELOAD_CLASS
674 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
677 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
678 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
682 && ! auto_inc_dec_reg_p (r, m))
683 forbidden_inc_dec_class[i] = 1;
687 #endif /* FORBIDDEN_INC_DEC_CLASSES */
689 init_cost.mem_cost = 10000;
690 for (i = 0; i < N_REG_CLASSES; i++)
691 init_cost.cost[i] = 10000;
693 /* Normally we scan the insns once and determine the best class to use for
694 each register. However, if -fexpensive_optimizations are on, we do so
695 twice, the second time using the tentative best classes to guide the
698 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
700 /* Zero out our accumulation of the cost of each class for each reg. */
702 bzero (costs, nregs * sizeof (struct costs));
704 #ifdef FORBIDDEN_INC_DEC_CLASSES
705 bzero (in_inc_dec, nregs);
708 loop_depth = 0, loop_cost = 1;
710 /* Scan the instructions and record each time it would
711 save code to put a certain register in a certain class. */
713 for (insn = f; insn; insn = NEXT_INSN (insn))
715 char *constraints[MAX_RECOG_OPERANDS];
716 enum machine_mode modes[MAX_RECOG_OPERANDS];
720 /* Show that an insn inside a loop is likely to be executed three
721 times more than insns outside a loop. This is much more aggressive
722 than the assumptions made elsewhere and is being tried as an
725 if (GET_CODE (insn) == NOTE
726 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
727 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
728 else if (GET_CODE (insn) == NOTE
729 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
730 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
732 else if ((GET_CODE (insn) == INSN
733 && GET_CODE (PATTERN (insn)) != USE
734 && GET_CODE (PATTERN (insn)) != CLOBBER
735 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
736 || (GET_CODE (insn) == JUMP_INSN
737 && GET_CODE (PATTERN (insn)) != ADDR_VEC
738 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
739 || GET_CODE (insn) == CALL_INSN)
741 if (GET_CODE (insn) == INSN
742 && (noperands = asm_noperands (PATTERN (insn))) >= 0)
744 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR,
746 nalternatives = (noperands == 0 ? 0
747 : n_occurrences (',', constraints[0]) + 1);
751 int insn_code_number = recog_memoized (insn);
754 set = single_set (insn);
757 nalternatives = insn_n_alternatives[insn_code_number];
758 noperands = insn_n_operands[insn_code_number];
760 /* If this insn loads a parameter from its stack slot, then
761 it represents a savings, rather than a cost, if the
762 parameter is stored in memory. Record this fact. */
764 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
765 && GET_CODE (SET_SRC (set)) == MEM
766 && (note = find_reg_note (insn, REG_EQUIV,
768 && GET_CODE (XEXP (note, 0)) == MEM)
770 costs[REGNO (SET_DEST (set))].mem_cost
771 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)))
773 record_address_regs (XEXP (SET_SRC (set), 0),
774 BASE_REG_CLASS, loop_cost * 2);
778 /* Improve handling of two-address insns such as
779 (set X (ashift CONST Y)) where CONST must be made to
780 match X. Change it into two insns: (set X CONST)
781 (set X (ashift X Y)). If we left this for reloading, it
782 would probably get three insns because X and Y might go
783 in the same place. This prevents X and Y from receiving
786 We can only do this if the modes of operands 0 and 1
787 (which might not be the same) are tieable and we only need
788 do this during our first pass. */
790 if (pass == 0 && optimize
792 && insn_operand_constraint[insn_code_number][1][0] == '0'
793 && insn_operand_constraint[insn_code_number][1][1] == 0
794 && CONSTANT_P (recog_operand[1])
795 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
796 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
797 && GET_CODE (recog_operand[0]) == REG
798 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
799 insn_operand_mode[insn_code_number][1]))
801 rtx previnsn = prev_real_insn (insn);
803 = gen_lowpart (insn_operand_mode[insn_code_number][1],
806 = emit_insn_before (gen_move_insn (dest,
810 /* If this insn was the start of a basic block,
811 include the new insn in that block.
812 We need not check for code_label here;
813 while a basic block can start with a code_label,
814 INSN could not be at the beginning of that block. */
815 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
818 for (b = 0; b < n_basic_blocks; b++)
819 if (insn == basic_block_head[b])
820 basic_block_head[b] = newinsn;
823 /* This makes one more setting of new insns's dest. */
824 reg_n_sets[REGNO (recog_operand[0])]++;
826 *recog_operand_loc[1] = recog_operand[0];
827 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
828 if (recog_dup_num[i] == 1)
829 *recog_dup_loc[i] = recog_operand[0];
831 insn = PREV_INSN (newinsn);
835 for (i = 0; i < noperands; i++)
838 = insn_operand_constraint[insn_code_number][i];
839 modes[i] = insn_operand_mode[insn_code_number][i];
843 /* If we get here, we are set up to record the costs of all the
844 operands for this insn. Start by initializing the costs.
845 Then handle any address registers. Finally record the desired
846 classes for any pseudos, doing it twice if some pair of
847 operands are commutative. */
849 for (i = 0; i < noperands; i++)
851 op_costs[i] = init_cost;
853 if (GET_CODE (recog_operand[i]) == SUBREG)
854 recog_operand[i] = SUBREG_REG (recog_operand[i]);
856 if (GET_CODE (recog_operand[i]) == MEM)
857 record_address_regs (XEXP (recog_operand[i], 0),
858 BASE_REG_CLASS, loop_cost * 2);
859 else if (constraints[i][0] == 'p')
860 record_address_regs (recog_operand[i],
861 BASE_REG_CLASS, loop_cost * 2);
864 /* Check for commutative in a separate loop so everything will
865 have been initialized. We must do this even if one operand
866 is a constant--see addsi3 in m68k.md. */
868 for (i = 0; i < noperands - 1; i++)
869 if (constraints[i][0] == '%')
871 char *xconstraints[MAX_RECOG_OPERANDS];
874 /* Handle commutative operands by swapping the constraints.
875 We assume the modes are the same. */
877 for (j = 0; j < noperands; j++)
878 xconstraints[j] = constraints[j];
880 xconstraints[i] = constraints[i+1];
881 xconstraints[i+1] = constraints[i];
882 record_reg_classes (nalternatives, noperands,
883 recog_operand, modes, xconstraints,
887 record_reg_classes (nalternatives, noperands, recog_operand,
888 modes, constraints, insn);
890 /* Now add the cost for each operand to the total costs for
893 for (i = 0; i < noperands; i++)
894 if (GET_CODE (recog_operand[i]) == REG
895 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
897 int regno = REGNO (recog_operand[i]);
898 struct costs *p = &costs[regno], *q = &op_costs[i];
900 p->mem_cost += q->mem_cost * loop_cost;
901 for (j = 0; j < N_REG_CLASSES; j++)
902 p->cost[j] += q->cost[j] * loop_cost;
907 /* Now for each register look at how desirable each class is
908 and find which class is preferred. Store that in
909 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
910 class any of whose registers is better than memory. */
914 prefclass = (char *) oballoc (nregs);
915 altclass = (char *) oballoc (nregs);
918 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
920 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
921 enum reg_class best = ALL_REGS, alt = NO_REGS;
922 /* This is an enum reg_class, but we call it an int
923 to save lots of casts. */
925 register struct costs *p = &costs[i];
927 for (class = (int) ALL_REGS - 1; class > 0; class--)
929 /* Ignore classes that are too small for this operand or
930 invalid for a operand that was auto-incremented. */
931 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
932 > reg_class_size[class]
933 #ifdef FORBIDDEN_INC_DEC_CLASSES
934 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
938 else if (p->cost[class] < best_cost)
940 best_cost = p->cost[class];
941 best = (enum reg_class) class;
943 else if (p->cost[class] == best_cost)
944 best = reg_class_subunion[(int)best][class];
947 /* Record the alternate register class; i.e., a class for which
948 every register in it is better than using memory. If adding a
949 class would make a smaller class (i.e., no union of just those
950 classes exists), skip that class. The major unions of classes
951 should be provided as a register class. Don't do this if we
952 will be doing it again later. */
954 if (pass == 1 || ! flag_expensive_optimizations)
955 for (class = 0; class < N_REG_CLASSES; class++)
956 if (p->cost[class] < p->mem_cost
957 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
958 > reg_class_size[(int) alt])
959 #ifdef FORBIDDEN_INC_DEC_CLASSES
960 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
963 alt = reg_class_subunion[(int) alt][class];
965 /* If we don't add any classes, nothing to try. */
969 /* We cast to (int) because (char) hits bugs in some compilers. */
970 prefclass[i] = (int) best;
971 altclass[i] = (int) alt;
974 #endif /* REGISTER_CONSTRAINTS */
977 #ifdef REGISTER_CONSTRAINTS
979 /* Record the cost of using memory or registers of various classes for
980 the operands in INSN.
982 N_ALTS is the number of alternatives.
984 N_OPS is the number of operands.
986 OPS is an array of the operands.
988 MODES are the modes of the operands, in case any are VOIDmode.
990 CONSTRAINTS are the constraints to use for the operands. This array
991 is modified by this procedure.
993 This procedure works alternative by alternative. For each alternative
994 we assume that we will be able to allocate all pseudos to their ideal
995 register class and calculate the cost of using that alternative. Then
996 we compute for each operand that is a pseudo-register, the cost of
997 having the pseudo allocated to each register class and using it in that
998 alternative. To this cost is added the cost of the alternative.
1000 The cost of each class for this insn is its lowest cost among all the
1004 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
1008 enum machine_mode *modes;
1013 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS];
1016 /* By default, each operand is an input operand. */
1018 for (i = 0; i < n_ops; i++)
1019 op_types[i] = OP_READ;
1021 /* Process each alternative, each time minimizing an operand's cost with
1022 the cost for each operand in that alternative. */
1024 for (alt = 0; alt < n_alts; alt++)
1026 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1029 enum reg_class classes[MAX_RECOG_OPERANDS];
1032 for (i = 0; i < n_ops; i++)
1034 char *p = constraints[i];
1036 enum machine_mode mode = modes[i];
1041 /* If this operand has no constraints at all, we can conclude
1042 nothing about it since anything is valid. */
1046 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1047 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1055 /* If this alternative is only relevant when this operand
1056 matches a previous operand, we do different things depending
1057 on whether this operand is a pseudo-reg or not. */
1059 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1062 classes[i] = classes[j];
1064 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1066 /* If this matches the other operand, we have no added
1068 if (rtx_equal_p (ops[j], op))
1071 /* If we can put the other operand into a register, add to
1072 the cost of this alternative the cost to copy this
1073 operand to the register used for the other operand. */
1075 else if (classes[j] != NO_REGS)
1076 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1078 else if (GET_CODE (ops[j]) != REG
1079 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1081 /* This op is a pseudo but the one it matches is not. */
1083 /* If we can't put the other operand into a register, this
1084 alternative can't be used. */
1086 if (classes[j] == NO_REGS)
1089 /* Otherwise, add to the cost of this alternative the cost
1090 to copy the other operand to the register used for this
1094 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1098 /* The costs of this operand are the same as that of the
1099 other operand. However, if we cannot tie them, this
1100 alternative needs to do a copy, which is one
1103 this_op_costs[i] = this_op_costs[j];
1104 if (REGNO (ops[i]) != REGNO (ops[j])
1105 && ! find_reg_note (insn, REG_DEAD, op))
1108 /* This is in place of ordinary cost computation
1109 for this operand, so skip to the end of the
1110 alternative (should be just one character). */
1111 while (*p && *p++ != ',')
1119 /* Scan all the constraint letters. See if the operand matches
1120 any of the constraints. Collect the valid register classes
1121 and see if this operand accepts memory. */
1123 classes[i] = NO_REGS;
1124 while (*p && (c = *p++) != ',')
1128 op_types[i] = OP_WRITE;
1132 op_types[i] = OP_READ_WRITE;
1136 /* Ignore the next letter for this pass. */
1141 case '?': case '!': case '#':
1143 case '0': case '1': case '2': case '3': case '4':
1147 case 'm': case 'o': case 'V':
1148 /* It doesn't seem worth distinguishing between offsettable
1149 and non-offsettable addresses here. */
1151 if (GET_CODE (op) == MEM)
1156 if (GET_CODE (op) == MEM
1157 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1158 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1163 if (GET_CODE (op) == MEM
1164 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1165 || GET_CODE (XEXP (op, 0)) == POST_INC))
1170 /* Match any floating double constant, but only if
1171 we can examine the bits of it reliably. */
1172 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1173 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1174 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1176 if (GET_CODE (op) == CONST_DOUBLE)
1181 if (GET_CODE (op) == CONST_DOUBLE)
1187 if (GET_CODE (op) == CONST_DOUBLE
1188 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1193 if (GET_CODE (op) == CONST_INT
1194 || (GET_CODE (op) == CONST_DOUBLE
1195 && GET_MODE (op) == VOIDmode))
1199 #ifdef LEGITIMATE_PIC_OPERAND_P
1200 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1207 if (GET_CODE (op) == CONST_INT
1208 || (GET_CODE (op) == CONST_DOUBLE
1209 && GET_MODE (op) == VOIDmode))
1221 if (GET_CODE (op) == CONST_INT
1222 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1230 #ifdef EXTRA_CONSTRAINT
1236 if (EXTRA_CONSTRAINT (op, c))
1242 if (GET_CODE (op) == MEM
1244 #ifdef LEGITIMATE_PIC_OPERAND_P
1245 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1252 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1257 = reg_class_subunion[(int) classes[i]]
1258 [(int) REG_CLASS_FROM_LETTER (c)];
1263 /* How we account for this operand now depends on whether it is a
1264 pseudo register or not. If it is, we first check if any
1265 register classes are valid. If not, we ignore this alternative,
1266 since we want to assume that all pseudos get allocated for
1267 register preferencing. If some register class is valid, compute
1268 the costs of moving the pseudo into that class. */
1270 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1272 if (classes[i] == NO_REGS)
1276 struct costs *pp = &this_op_costs[i];
1278 for (class = 0; class < N_REG_CLASSES; class++)
1279 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1281 /* If the alternative actually allows memory, make things
1282 a bit cheaper since we won't need an extra insn to
1285 pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem;
1287 /* If we have assigned a class to this register in our
1288 first pass, add a cost to this alternative corresponding
1289 to what we would add if this register were not in the
1290 appropriate class. */
1294 += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]];
1298 /* Otherwise, if this alternative wins, either because we
1299 have already determined that or if we have a hard register of
1300 the proper class, there is no cost for this alternative. */
1303 || (GET_CODE (op) == REG
1304 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1307 /* If registers are valid, the cost of this alternative includes
1308 copying the object to and/or from a register. */
1310 else if (classes[i] != NO_REGS)
1312 if (op_types[i] != OP_WRITE)
1313 alt_cost += copy_cost (op, mode, classes[i], 1);
1315 if (op_types[i] != OP_READ)
1316 alt_cost += copy_cost (op, mode, classes[i], 0);
1319 /* The only other way this alternative can be used is if this is a
1320 constant that could be placed into memory. */
1322 else if (CONSTANT_P (op) && allows_mem)
1323 alt_cost += MEMORY_MOVE_COST (mode);
1331 /* Finally, update the costs with the information we've calculated
1332 about this alternative. */
1334 for (i = 0; i < n_ops; i++)
1335 if (GET_CODE (ops[i]) == REG
1336 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1338 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1339 int scale = 1 + (op_types[i] == OP_READ_WRITE);
1341 pp->mem_cost = MIN (pp->mem_cost,
1342 (qq->mem_cost + alt_cost) * scale);
1344 for (class = 0; class < N_REG_CLASSES; class++)
1345 pp->cost[class] = MIN (pp->cost[class],
1346 (qq->cost[class] + alt_cost) * scale);
1351 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1352 TO_P is zero) a register of class CLASS in mode MODE.
1354 X must not be a pseudo. */
1357 copy_cost (x, mode, class, to_p)
1359 enum machine_mode mode;
1360 enum reg_class class;
1363 enum reg_class secondary_class = NO_REGS;
1365 /* If X is a SCRATCH, there is actually nothing to move since we are
1366 assuming optimal allocation. */
1368 if (GET_CODE (x) == SCRATCH)
1371 /* Get the class we will actually use for a reload. */
1372 class = PREFERRED_RELOAD_CLASS (x, class);
1374 #ifdef HAVE_SECONDARY_RELOADS
1375 /* If we need a secondary reload (we assume here that we are using
1376 the secondary reload as an intermediate, not a scratch register), the
1377 cost is that to load the input into the intermediate register, then
1378 to copy them. We use a special value of TO_P to avoid recursion. */
1380 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1382 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1385 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1387 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1390 if (secondary_class != NO_REGS)
1391 return (move_cost[(int) secondary_class][(int) class]
1392 + copy_cost (x, mode, secondary_class, 2));
1393 #endif /* HAVE_SECONDARY_RELOADS */
1395 /* For memory, use the memory move cost, for (hard) registers, use the
1396 cost to move between the register classes, and use 2 for everything
1397 else (constants). */
1399 if (GET_CODE (x) == MEM || class == NO_REGS)
1400 return MEMORY_MOVE_COST (mode);
1402 else if (GET_CODE (x) == REG)
1403 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1406 /* If this is a constant, we may eventually want to call rtx_cost here. */
1410 /* Record the pseudo registers we must reload into hard registers
1411 in a subexpression of a memory address, X.
1413 CLASS is the class that the register needs to be in and is either
1414 BASE_REG_CLASS or INDEX_REG_CLASS.
1416 SCALE is twice the amount to multiply the cost by (it is twice so we
1417 can represent half-cost adjustments). */
1420 record_address_regs (x, class, scale)
1422 enum reg_class class;
1425 register enum rtx_code code = GET_CODE (x);
1438 /* When we have an address that is a sum,
1439 we must determine whether registers are "base" or "index" regs.
1440 If there is a sum of two registers, we must choose one to be
1441 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1442 to make a good choice most of the time. We only need to do this
1443 on machines that can have two registers in an address and where
1444 the base and index register classes are different.
1446 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1447 that seems bogus since it should only be set when we are sure
1448 the register is being used as a pointer. */
1451 rtx arg0 = XEXP (x, 0);
1452 rtx arg1 = XEXP (x, 1);
1453 register enum rtx_code code0 = GET_CODE (arg0);
1454 register enum rtx_code code1 = GET_CODE (arg1);
1456 /* Look inside subregs. */
1457 if (code0 == SUBREG)
1458 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1459 if (code1 == SUBREG)
1460 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1462 /* If this machine only allows one register per address, it must
1463 be in the first operand. */
1465 if (MAX_REGS_PER_ADDRESS == 1)
1466 record_address_regs (arg0, class, scale);
1468 /* If index and base registers are the same on this machine, just
1469 record registers in any non-constant operands. We assume here,
1470 as well as in the tests below, that all addresses are in
1473 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1475 record_address_regs (arg0, class, scale);
1476 if (! CONSTANT_P (arg1))
1477 record_address_regs (arg1, class, scale);
1480 /* If the second operand is a constant integer, it doesn't change
1481 what class the first operand must be. */
1483 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1484 record_address_regs (arg0, class, scale);
1486 /* If the second operand is a symbolic constant, the first operand
1487 must be an index register. */
1489 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1490 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1492 /* If this the sum of two registers where the first is known to be a
1493 pointer, it must be a base register with the second an index. */
1495 else if (code0 == REG && code1 == REG
1496 && REGNO_POINTER_FLAG (REGNO (arg0)))
1498 record_address_regs (arg0, BASE_REG_CLASS, scale);
1499 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1502 /* If this is the sum of two registers and neither is known to
1503 be a pointer, count equal chances that each might be a base
1504 or index register. This case should be rare. */
1506 else if (code0 == REG && code1 == REG
1507 && ! REGNO_POINTER_FLAG (REGNO (arg0))
1508 && ! REGNO_POINTER_FLAG (REGNO (arg1)))
1510 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1511 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1512 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1513 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1516 /* In all other cases, the first operand is an index and the
1517 second is the base. */
1521 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1522 record_address_regs (arg1, BASE_REG_CLASS, scale);
1531 /* Double the importance of a pseudo register that is incremented
1532 or decremented, since it would take two extra insns
1533 if it ends up in the wrong place. If the operand is a pseudo,
1534 show it is being used in an INC_DEC context. */
1536 #ifdef FORBIDDEN_INC_DEC_CLASSES
1537 if (GET_CODE (XEXP (x, 0)) == REG
1538 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1539 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1542 record_address_regs (XEXP (x, 0), class, 2 * scale);
1547 register struct costs *pp = &costs[REGNO (x)];
1550 pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2;
1552 for (i = 0; i < N_REG_CLASSES; i++)
1553 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1559 register char *fmt = GET_RTX_FORMAT (code);
1561 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1563 record_address_regs (XEXP (x, i), class, scale);
1568 #ifdef FORBIDDEN_INC_DEC_CLASSES
1570 /* Return 1 if REG is valid as an auto-increment memory reference
1571 to an object of MODE. */
1574 auto_inc_dec_reg_p (reg, mode)
1576 enum machine_mode mode;
1578 #ifdef HAVE_POST_INCREMENT
1579 if (memory_address_p (mode, gen_rtx (POST_INC, Pmode, reg)))
1583 #ifdef HAVE_POST_DECREMENT
1584 if (memory_address_p (mode, gen_rtx (POST_DEC, Pmode, reg)))
1588 #ifdef HAVE_PRE_INCREMENT
1589 if (memory_address_p (mode, gen_rtx (PRE_INC, Pmode, reg)))
1593 #ifdef HAVE_PRE_DECREMENT
1594 if (memory_address_p (mode, gen_rtx (PRE_DEC, Pmode, reg)))
1602 #endif /* REGISTER_CONSTRAINTS */
1604 /* This is the `regscan' pass of the compiler, run just before cse
1605 and again just before loop.
1607 It finds the first and last use of each pseudo-register
1608 and records them in the vectors regno_first_uid, regno_last_uid
1609 and counts the number of sets in the vector reg_n_sets.
1611 REPEAT is nonzero the second time this is called. */
1613 /* Indexed by pseudo register number, gives uid of first insn using the reg
1614 (as of the time reg_scan is called). */
1616 int *regno_first_uid;
1618 /* Indexed by pseudo register number, gives uid of last insn using the reg
1619 (as of the time reg_scan is called). */
1621 int *regno_last_uid;
1623 /* Indexed by pseudo register number, gives uid of last insn using the reg
1624 or mentioning it in a note (as of the time reg_scan is called). */
1626 int *regno_last_note_uid;
1628 /* Record the number of registers we used when we allocated the above two
1629 tables. If we are called again with more than this, we must re-allocate
1632 static int highest_regno_in_uid_map;
1634 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1635 Always at least 3, since the combiner could put that many togetherm
1636 and we want this to remain correct for all the remaining passes. */
1641 reg_scan (f, nregs, repeat)
1648 if (!repeat || nregs > highest_regno_in_uid_map)
1650 /* Leave some spare space in case more regs are allocated. */
1651 highest_regno_in_uid_map = nregs + nregs / 20;
1653 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1655 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1657 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1659 = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1662 bzero (regno_first_uid, highest_regno_in_uid_map * sizeof (int));
1663 bzero (regno_last_uid, highest_regno_in_uid_map * sizeof (int));
1664 bzero (regno_last_note_uid, highest_regno_in_uid_map * sizeof (int));
1665 bzero (reg_n_sets, highest_regno_in_uid_map * sizeof (short));
1669 for (insn = f; insn; insn = NEXT_INSN (insn))
1670 if (GET_CODE (insn) == INSN
1671 || GET_CODE (insn) == CALL_INSN
1672 || GET_CODE (insn) == JUMP_INSN)
1674 if (GET_CODE (PATTERN (insn)) == PARALLEL
1675 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1676 max_parallel = XVECLEN (PATTERN (insn), 0);
1677 reg_scan_mark_refs (PATTERN (insn), insn, 0);
1679 if (REG_NOTES (insn))
1680 reg_scan_mark_refs (REG_NOTES (insn), insn, 1);
1684 /* X is the expression to scan. INSN is the insn it appears in.
1685 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */
1688 reg_scan_mark_refs (x, insn, note_flag)
1693 register enum rtx_code code = GET_CODE (x);
1712 register int regno = REGNO (x);
1714 regno_last_note_uid[regno] = INSN_UID (insn);
1716 regno_last_uid[regno] = INSN_UID (insn);
1717 if (regno_first_uid[regno] == 0)
1718 regno_first_uid[regno] = INSN_UID (insn);
1724 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag);
1726 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1731 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1735 /* Count a set of the destination if it is a register. */
1736 for (dest = SET_DEST (x);
1737 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
1738 || GET_CODE (dest) == ZERO_EXTEND;
1739 dest = XEXP (dest, 0))
1742 if (GET_CODE (dest) == REG)
1743 reg_n_sets[REGNO (dest)]++;
1745 /* If this is setting a pseudo from another pseudo or the sum of a
1746 pseudo and a constant integer and the other pseudo is known to be
1747 a pointer, set the destination to be a pointer as well.
1749 Likewise if it is setting the destination from an address or from a
1750 value equivalent to an address or to the sum of an address and
1753 But don't do any of this if the pseudo corresponds to a user
1754 variable since it should have already been set as a pointer based
1757 if (GET_CODE (SET_DEST (x)) == REG
1758 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
1759 && ! REG_USERVAR_P (SET_DEST (x))
1760 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
1761 && ((GET_CODE (SET_SRC (x)) == REG
1762 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
1763 || ((GET_CODE (SET_SRC (x)) == PLUS
1764 || GET_CODE (SET_SRC (x)) == LO_SUM)
1765 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
1766 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
1767 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
1768 || GET_CODE (SET_SRC (x)) == CONST
1769 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
1770 || GET_CODE (SET_SRC (x)) == LABEL_REF
1771 || (GET_CODE (SET_SRC (x)) == HIGH
1772 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
1773 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
1774 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
1775 || ((GET_CODE (SET_SRC (x)) == PLUS
1776 || GET_CODE (SET_SRC (x)) == LO_SUM)
1777 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
1778 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
1779 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
1780 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
1781 && (GET_CODE (XEXP (note, 0)) == CONST
1782 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
1783 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
1784 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
1786 /* ... fall through ... */
1790 register char *fmt = GET_RTX_FORMAT (code);
1792 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1795 reg_scan_mark_refs (XEXP (x, i), insn, note_flag);
1796 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
1799 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1800 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag);
1807 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1811 reg_class_subset_p (c1, c2)
1812 register enum reg_class c1;
1813 register enum reg_class c2;
1815 if (c1 == c2) return 1;
1820 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
1821 reg_class_contents[(int)c2],
1826 /* Return nonzero if there is a register that is in both C1 and C2. */
1829 reg_classes_intersect_p (c1, c2)
1830 register enum reg_class c1;
1831 register enum reg_class c2;
1838 if (c1 == c2) return 1;
1840 if (c1 == ALL_REGS || c2 == ALL_REGS)
1843 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1844 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1846 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);