1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
29 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "insn-config.h"
40 #ifndef REGISTER_MOVE_COST
41 #define REGISTER_MOVE_COST(x, y) 2
44 /* If we have auto-increment or auto-decrement and we can have secondary
45 reloads, we are not allowed to use classes requiring secondary
46 reloads for pseudos auto-incremented since reload can't handle it. */
49 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
50 #define FORBIDDEN_INC_DEC_CLASSES
54 /* Register tables used by many passes. */
56 /* Indexed by hard register number, contains 1 for registers
57 that are fixed use (stack pointer, pc, frame pointer, etc.).
58 These are the registers that cannot be used to allocate
59 a pseudo reg whose life does not cross calls. */
61 char fixed_regs[FIRST_PSEUDO_REGISTER];
63 /* Same info as a HARD_REG_SET. */
65 HARD_REG_SET fixed_reg_set;
67 /* Data for initializing the above. */
69 static char initial_fixed_regs[] = FIXED_REGISTERS;
71 /* Indexed by hard register number, contains 1 for registers
72 that are fixed use or are clobbered by function calls.
73 These are the registers that cannot be used to allocate
74 a pseudo reg whose life crosses calls. */
76 char call_used_regs[FIRST_PSEUDO_REGISTER];
78 /* Same info as a HARD_REG_SET. */
80 HARD_REG_SET call_used_reg_set;
82 /* HARD_REG_SET of registers we want to avoid caller saving. */
83 HARD_REG_SET losing_caller_save_reg_set;
85 /* Data for initializing the above. */
87 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
89 /* Indexed by hard register number, contains 1 for registers that are
90 fixed use -- i.e. in fixed_regs -- or a function value return register
91 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
92 registers that cannot hold quantities across calls even if we are
93 willing to save and restore them. */
95 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
97 /* The same info as a HARD_REG_SET. */
99 HARD_REG_SET call_fixed_reg_set;
101 /* Number of non-fixed registers. */
103 int n_non_fixed_regs;
105 /* Indexed by hard register number, contains 1 for registers
106 that are being used for global register decls.
107 These must be exempt from ordinary flow analysis
108 and are also considered fixed. */
110 char global_regs[FIRST_PSEUDO_REGISTER];
112 /* Table of register numbers in the order in which to try to use them. */
113 #ifdef REG_ALLOC_ORDER
114 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
117 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
119 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
121 /* The same information, but as an array of unsigned ints. We copy from
122 these unsigned ints to the table above. We do this so the tm.h files
123 do not have to be aware of the wordsize for machines with <= 64 regs. */
126 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
128 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
129 = REG_CLASS_CONTENTS;
131 /* For each reg class, number of regs it contains. */
133 int reg_class_size[N_REG_CLASSES];
135 /* For each reg class, table listing all the containing classes. */
137 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
139 /* For each reg class, table listing all the classes contained in it. */
141 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
143 /* For each pair of reg classes,
144 a largest reg class contained in their union. */
146 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
148 /* For each pair of reg classes,
149 the smallest reg class containing their union. */
151 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
153 /* Array containing all of the register names */
155 char *reg_names[] = REGISTER_NAMES;
157 /* For each hard register, the widest mode object that it can contain.
158 This will be a MODE_INT mode if the register can hold integers. Otherwise
159 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
162 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
164 /* Maximum cost of moving from a register in one class to a register in
165 another class. Based on REGISTER_MOVE_COST. */
167 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
169 /* Similar, but here we don't have to move if the first index is a subset
170 of the second so in that case the cost is zero. */
172 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
174 #ifdef FORBIDDEN_INC_DEC_CLASSES
176 /* These are the classes that regs which are auto-incremented or decremented
179 static int forbidden_inc_dec_class[N_REG_CLASSES];
181 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
184 static char *in_inc_dec;
186 #endif /* FORBIDDEN_INC_DEC_CLASSES */
188 #ifdef HAVE_SECONDARY_RELOADS
190 /* Sample MEM values for use by memory_move_secondary_cost. */
192 static rtx top_of_stack[MAX_MACHINE_MODE];
194 #endif /* HAVE_SECONDARY_RELOADS */
196 /* Linked list of reg_info structures allocated for reg_n_info array.
197 Grouping all of the allocated structures together in one lump
198 means only one call to bzero to clear them, rather than n smaller
200 struct reg_info_data {
201 struct reg_info_data *next; /* next set of reg_info structures */
202 size_t min_index; /* minimum index # */
203 size_t max_index; /* maximum index # */
204 char used_p; /* non-zero if this has been used previously */
205 reg_info data[1]; /* beginning of the reg_info data */
208 static struct reg_info_data *reg_info_head;
211 /* Function called only once to initialize the above data on reg usage.
212 Once this is done, various switches may override. */
219 /* First copy the register information from the initial int form into
222 for (i = 0; i < N_REG_CLASSES; i++)
224 CLEAR_HARD_REG_SET (reg_class_contents[i]);
226 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
227 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
228 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
229 SET_HARD_REG_BIT (reg_class_contents[i], j);
232 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
233 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
234 bzero (global_regs, sizeof global_regs);
236 /* Compute number of hard regs in each class. */
238 bzero ((char *) reg_class_size, sizeof reg_class_size);
239 for (i = 0; i < N_REG_CLASSES; i++)
240 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
241 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
244 /* Initialize the table of subunions.
245 reg_class_subunion[I][J] gets the largest-numbered reg-class
246 that is contained in the union of classes I and J. */
248 for (i = 0; i < N_REG_CLASSES; i++)
250 for (j = 0; j < N_REG_CLASSES; j++)
253 register /* Declare it register if it's a scalar. */
258 COPY_HARD_REG_SET (c, reg_class_contents[i]);
259 IOR_HARD_REG_SET (c, reg_class_contents[j]);
260 for (k = 0; k < N_REG_CLASSES; k++)
262 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
267 /* keep the largest subclass */ /* SPEE 900308 */
268 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
269 reg_class_contents[(int) reg_class_subunion[i][j]],
271 reg_class_subunion[i][j] = (enum reg_class) k;
278 /* Initialize the table of superunions.
279 reg_class_superunion[I][J] gets the smallest-numbered reg-class
280 containing the union of classes I and J. */
282 for (i = 0; i < N_REG_CLASSES; i++)
284 for (j = 0; j < N_REG_CLASSES; j++)
287 register /* Declare it register if it's a scalar. */
292 COPY_HARD_REG_SET (c, reg_class_contents[i]);
293 IOR_HARD_REG_SET (c, reg_class_contents[j]);
294 for (k = 0; k < N_REG_CLASSES; k++)
295 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
298 reg_class_superunion[i][j] = (enum reg_class) k;
302 /* Initialize the tables of subclasses and superclasses of each reg class.
303 First clear the whole table, then add the elements as they are found. */
305 for (i = 0; i < N_REG_CLASSES; i++)
307 for (j = 0; j < N_REG_CLASSES; j++)
309 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
310 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
314 for (i = 0; i < N_REG_CLASSES; i++)
316 if (i == (int) NO_REGS)
319 for (j = i + 1; j < N_REG_CLASSES; j++)
323 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
327 /* Reg class I is a subclass of J.
328 Add J to the table of superclasses of I. */
329 p = ®_class_superclasses[i][0];
330 while (*p != LIM_REG_CLASSES) p++;
331 *p = (enum reg_class) j;
332 /* Add I to the table of superclasses of J. */
333 p = ®_class_subclasses[j][0];
334 while (*p != LIM_REG_CLASSES) p++;
335 *p = (enum reg_class) i;
339 /* Do any additional initialization regsets may need */
340 INIT_ONCE_REG_SET ();
343 /* After switches have been processed, which perhaps alter
344 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
349 register unsigned int i, j;
351 /* This macro allows the fixed or call-used registers
352 to depend on target flags. */
354 #ifdef CONDITIONAL_REGISTER_USAGE
355 CONDITIONAL_REGISTER_USAGE;
358 /* Initialize "constant" tables. */
360 CLEAR_HARD_REG_SET (fixed_reg_set);
361 CLEAR_HARD_REG_SET (call_used_reg_set);
362 CLEAR_HARD_REG_SET (call_fixed_reg_set);
364 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
366 n_non_fixed_regs = 0;
368 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
371 SET_HARD_REG_BIT (fixed_reg_set, i);
375 if (call_used_regs[i])
376 SET_HARD_REG_BIT (call_used_reg_set, i);
377 if (call_fixed_regs[i])
378 SET_HARD_REG_BIT (call_fixed_reg_set, i);
379 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
380 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
383 /* Initialize the move cost table. Find every subset of each class
384 and take the maximum cost of moving any subset to any other. */
386 for (i = 0; i < N_REG_CLASSES; i++)
387 for (j = 0; j < N_REG_CLASSES; j++)
389 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
390 enum reg_class *p1, *p2;
392 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
394 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
396 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
399 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
401 for (p2 = ®_class_subclasses[j][0];
402 *p2 != LIM_REG_CLASSES; p2++)
404 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
407 move_cost[i][j] = cost;
409 if (reg_class_subset_p (i, j))
412 may_move_cost[i][j] = cost;
416 /* Compute the table of register modes.
417 These values are used to record death information for individual registers
418 (as opposed to a multi-register mode). */
425 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
427 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
429 /* If we couldn't find a valid mode, just use the previous mode.
430 ??? One situation in which we need to do this is on the mips where
431 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
432 to use DF mode for the even registers and VOIDmode for the odd
433 (for the cpu models where the odd ones are inaccessible). */
434 if (reg_raw_mode[i] == VOIDmode)
435 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
439 /* Finish initializing the register sets and
440 initialize the register modes. */
445 /* This finishes what was started by init_reg_sets, but couldn't be done
446 until after register usage was specified. */
451 #ifdef HAVE_SECONDARY_RELOADS
453 /* Make some fake stack-frame MEM references for use in
454 memory_move_secondary_cost. */
456 for (i = 0; i < MAX_MACHINE_MODE; i++)
457 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
462 #ifdef HAVE_SECONDARY_RELOADS
464 /* Compute extra cost of moving registers to/from memory due to reloads.
465 Only needed if secondary reloads are required for memory moves. */
468 memory_move_secondary_cost (mode, class, in)
469 enum machine_mode mode;
470 enum reg_class class;
473 enum reg_class altclass;
474 int partial_cost = 0;
475 /* We need a memory reference to feed to SECONDARY... macros. */
476 rtx mem = top_of_stack[(int) mode];
480 #ifdef SECONDARY_INPUT_RELOAD_CLASS
481 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
488 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
489 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
495 if (altclass == NO_REGS)
499 partial_cost = REGISTER_MOVE_COST (altclass, class);
501 partial_cost = REGISTER_MOVE_COST (class, altclass);
503 if (class == altclass)
504 /* This isn't simply a copy-to-temporary situation. Can't guess
505 what it is, so MEMORY_MOVE_COST really ought not to be calling
508 I'm tempted to put in an abort here, but returning this will
509 probably only give poor estimates, which is what we would've
510 had before this code anyways. */
513 /* Check if the secondary reload register will also need a
515 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
519 /* Return a machine mode that is legitimate for hard reg REGNO and large
520 enough to save nregs. If we can't find one, return VOIDmode. */
523 choose_hard_reg_mode (regno, nregs)
527 enum machine_mode found_mode = VOIDmode, mode;
529 /* We first look for the largest integer mode that can be validly
530 held in REGNO. If none, we look for the largest floating-point mode.
531 If we still didn't find a valid mode, try CCmode. */
533 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
535 mode = GET_MODE_WIDER_MODE (mode))
536 if (HARD_REGNO_NREGS (regno, mode) == nregs
537 && HARD_REGNO_MODE_OK (regno, mode))
540 if (found_mode != VOIDmode)
543 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
545 mode = GET_MODE_WIDER_MODE (mode))
546 if (HARD_REGNO_NREGS (regno, mode) == nregs
547 && HARD_REGNO_MODE_OK (regno, mode))
550 if (found_mode != VOIDmode)
553 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
554 && HARD_REGNO_MODE_OK (regno, CCmode))
557 /* We can't find a mode valid for this register. */
561 /* Specify the usage characteristics of the register named NAME.
562 It should be a fixed register if FIXED and a
563 call-used register if CALL_USED. */
566 fix_register (name, fixed, call_used)
568 int fixed, call_used;
572 /* Decode the name and update the primary form of
573 the register info. */
575 if ((i = decode_reg_name (name)) >= 0)
577 fixed_regs[i] = fixed;
578 call_used_regs[i] = call_used;
582 warning ("unknown register name: %s", name);
586 /* Mark register number I as global. */
594 warning ("register used for two global register variables");
598 if (call_used_regs[i] && ! fixed_regs[i])
599 warning ("call-clobbered register used for global register variable");
603 /* If already fixed, nothing else to do. */
607 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
610 SET_HARD_REG_BIT (fixed_reg_set, i);
611 SET_HARD_REG_BIT (call_used_reg_set, i);
612 SET_HARD_REG_BIT (call_fixed_reg_set, i);
615 /* Now the data and code for the `regclass' pass, which happens
616 just before local-alloc. */
618 /* The `costs' struct records the cost of using a hard register of each class
619 and of using memory for each pseudo. We use this data to set up
620 register class preferences. */
624 int cost[N_REG_CLASSES];
628 /* Record the cost of each class for each pseudo. */
630 static struct costs *costs;
632 /* Record the same data by operand number, accumulated for each alternative
633 in an insn. The contribution to a pseudo is that of the minimum-cost
636 static struct costs op_costs[MAX_RECOG_OPERANDS];
638 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
639 This is available after `regclass' is run. */
641 static char *prefclass;
643 /* altclass[R] is a register class that we should use for allocating
644 pseudo number R if no register in the preferred class is available.
645 If no register in this class is available, memory is preferred.
647 It might appear to be more general to have a bitmask of classes here,
648 but since it is recommended that there be a class corresponding to the
649 union of most major pair of classes, that generality is not required.
651 This is available after `regclass' is run. */
653 static char *altclass;
655 /* Allocated buffers for prefclass and altclass. */
656 static char *prefclass_buffer;
657 static char *altclass_buffer;
659 /* Record the depth of loops that we are in. */
661 static int loop_depth;
663 /* Account for the fact that insns within a loop are executed very commonly,
664 but don't keep doing this as loops go too deep. */
666 static int loop_cost;
668 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
670 static int copy_cost PROTO((rtx, enum machine_mode,
671 enum reg_class, int));
672 static void record_address_regs PROTO((rtx, enum reg_class, int));
673 #ifdef FORBIDDEN_INC_DEC_CLASSES
674 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
676 static void reg_scan_mark_refs PROTO((rtx, rtx, int));
678 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
679 This function is sometimes called before the info has been computed.
680 When that happens, just return GENERAL_REGS, which is innocuous. */
683 reg_preferred_class (regno)
688 return (enum reg_class) prefclass[regno];
692 reg_alternate_class (regno)
698 return (enum reg_class) altclass[regno];
701 /* This prevents dump_flow_info from losing if called
702 before regclass is run. */
710 /* This is a pass of the compiler that scans all instructions
711 and calculates the preferred class for each pseudo-register.
712 This information can be accessed later by calling `reg_preferred_class'.
713 This pass comes just before local register allocation. */
720 #ifdef REGISTER_CONSTRAINTS
723 struct costs init_cost;
729 costs = (struct costs *) alloca (nregs * sizeof (struct costs));
731 #ifdef FORBIDDEN_INC_DEC_CLASSES
733 in_inc_dec = (char *) alloca (nregs);
735 /* Initialize information about which register classes can be used for
736 pseudos that are auto-incremented or auto-decremented. It would
737 seem better to put this in init_reg_sets, but we need to be able
738 to allocate rtx, which we can't do that early. */
740 for (i = 0; i < N_REG_CLASSES; i++)
742 rtx r = gen_rtx_REG (VOIDmode, 0);
745 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
746 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
750 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
751 m = (enum machine_mode) ((int) m + 1))
752 if (HARD_REGNO_MODE_OK (j, m))
756 /* If a register is not directly suitable for an
757 auto-increment or decrement addressing mode and
758 requires secondary reloads, disallow its class from
759 being used in such addresses. */
762 #ifdef SECONDARY_RELOAD_CLASS
763 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
766 #ifdef SECONDARY_INPUT_RELOAD_CLASS
767 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
770 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
771 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
776 && ! auto_inc_dec_reg_p (r, m))
777 forbidden_inc_dec_class[i] = 1;
781 #endif /* FORBIDDEN_INC_DEC_CLASSES */
783 init_cost.mem_cost = 10000;
784 for (i = 0; i < N_REG_CLASSES; i++)
785 init_cost.cost[i] = 10000;
787 /* Normally we scan the insns once and determine the best class to use for
788 each register. However, if -fexpensive_optimizations are on, we do so
789 twice, the second time using the tentative best classes to guide the
792 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
794 /* Zero out our accumulation of the cost of each class for each reg. */
796 bzero ((char *) costs, nregs * sizeof (struct costs));
798 #ifdef FORBIDDEN_INC_DEC_CLASSES
799 bzero (in_inc_dec, nregs);
802 loop_depth = 0, loop_cost = 1;
804 /* Scan the instructions and record each time it would
805 save code to put a certain register in a certain class. */
807 for (insn = f; insn; insn = NEXT_INSN (insn))
809 char *constraints[MAX_RECOG_OPERANDS];
810 enum machine_mode modes[MAX_RECOG_OPERANDS];
814 /* Show that an insn inside a loop is likely to be executed three
815 times more than insns outside a loop. This is much more aggressive
816 than the assumptions made elsewhere and is being tried as an
819 if (GET_CODE (insn) == NOTE
820 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
821 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
822 else if (GET_CODE (insn) == NOTE
823 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
824 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
826 else if ((GET_CODE (insn) == INSN
827 && GET_CODE (PATTERN (insn)) != USE
828 && GET_CODE (PATTERN (insn)) != CLOBBER
829 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
830 || (GET_CODE (insn) == JUMP_INSN
831 && GET_CODE (PATTERN (insn)) != ADDR_VEC
832 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
833 || GET_CODE (insn) == CALL_INSN)
835 if (GET_CODE (insn) == INSN
836 && (noperands = asm_noperands (PATTERN (insn))) >= 0)
838 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR,
840 nalternatives = (noperands == 0 ? 0
841 : n_occurrences (',', constraints[0]) + 1);
845 int insn_code_number = recog_memoized (insn);
848 set = single_set (insn);
851 nalternatives = insn_n_alternatives[insn_code_number];
852 noperands = insn_n_operands[insn_code_number];
854 /* If this insn loads a parameter from its stack slot, then
855 it represents a savings, rather than a cost, if the
856 parameter is stored in memory. Record this fact. */
858 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
859 && GET_CODE (SET_SRC (set)) == MEM
860 && (note = find_reg_note (insn, REG_EQUIV,
862 && GET_CODE (XEXP (note, 0)) == MEM)
864 costs[REGNO (SET_DEST (set))].mem_cost
865 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
868 record_address_regs (XEXP (SET_SRC (set), 0),
869 BASE_REG_CLASS, loop_cost * 2);
873 /* Improve handling of two-address insns such as
874 (set X (ashift CONST Y)) where CONST must be made to
875 match X. Change it into two insns: (set X CONST)
876 (set X (ashift X Y)). If we left this for reloading, it
877 would probably get three insns because X and Y might go
878 in the same place. This prevents X and Y from receiving
881 We can only do this if the modes of operands 0 and 1
882 (which might not be the same) are tieable and we only need
883 do this during our first pass. */
885 if (pass == 0 && optimize
887 && insn_operand_constraint[insn_code_number][1][0] == '0'
888 && insn_operand_constraint[insn_code_number][1][1] == 0
889 && CONSTANT_P (recog_operand[1])
890 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
891 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
892 && GET_CODE (recog_operand[0]) == REG
893 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
894 insn_operand_mode[insn_code_number][1]))
896 rtx previnsn = prev_real_insn (insn);
898 = gen_lowpart (insn_operand_mode[insn_code_number][1],
901 = emit_insn_before (gen_move_insn (dest,
905 /* If this insn was the start of a basic block,
906 include the new insn in that block.
907 We need not check for code_label here;
908 while a basic block can start with a code_label,
909 INSN could not be at the beginning of that block. */
910 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
913 for (b = 0; b < n_basic_blocks; b++)
914 if (insn == basic_block_head[b])
915 basic_block_head[b] = newinsn;
918 /* This makes one more setting of new insns's dest. */
919 REG_N_SETS (REGNO (recog_operand[0]))++;
921 *recog_operand_loc[1] = recog_operand[0];
922 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
923 if (recog_dup_num[i] == 1)
924 *recog_dup_loc[i] = recog_operand[0];
926 insn = PREV_INSN (newinsn);
930 for (i = 0; i < noperands; i++)
933 = insn_operand_constraint[insn_code_number][i];
934 modes[i] = insn_operand_mode[insn_code_number][i];
938 /* If we get here, we are set up to record the costs of all the
939 operands for this insn. Start by initializing the costs.
940 Then handle any address registers. Finally record the desired
941 classes for any pseudos, doing it twice if some pair of
942 operands are commutative. */
944 for (i = 0; i < noperands; i++)
946 op_costs[i] = init_cost;
948 if (GET_CODE (recog_operand[i]) == SUBREG)
949 recog_operand[i] = SUBREG_REG (recog_operand[i]);
951 if (GET_CODE (recog_operand[i]) == MEM)
952 record_address_regs (XEXP (recog_operand[i], 0),
953 BASE_REG_CLASS, loop_cost * 2);
954 else if (constraints[i][0] == 'p')
955 record_address_regs (recog_operand[i],
956 BASE_REG_CLASS, loop_cost * 2);
959 /* Check for commutative in a separate loop so everything will
960 have been initialized. We must do this even if one operand
961 is a constant--see addsi3 in m68k.md. */
963 for (i = 0; i < noperands - 1; i++)
964 if (constraints[i][0] == '%')
966 char *xconstraints[MAX_RECOG_OPERANDS];
969 /* Handle commutative operands by swapping the constraints.
970 We assume the modes are the same. */
972 for (j = 0; j < noperands; j++)
973 xconstraints[j] = constraints[j];
975 xconstraints[i] = constraints[i+1];
976 xconstraints[i+1] = constraints[i];
977 record_reg_classes (nalternatives, noperands,
978 recog_operand, modes, xconstraints,
982 record_reg_classes (nalternatives, noperands, recog_operand,
983 modes, constraints, insn);
985 /* Now add the cost for each operand to the total costs for
988 for (i = 0; i < noperands; i++)
989 if (GET_CODE (recog_operand[i]) == REG
990 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
992 int regno = REGNO (recog_operand[i]);
993 struct costs *p = &costs[regno], *q = &op_costs[i];
995 p->mem_cost += q->mem_cost * loop_cost;
996 for (j = 0; j < N_REG_CLASSES; j++)
997 p->cost[j] += q->cost[j] * loop_cost;
1002 /* Now for each register look at how desirable each class is
1003 and find which class is preferred. Store that in
1004 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
1005 class any of whose registers is better than memory. */
1009 prefclass = prefclass_buffer;
1010 altclass = altclass_buffer;
1013 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1015 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1016 enum reg_class best = ALL_REGS, alt = NO_REGS;
1017 /* This is an enum reg_class, but we call it an int
1018 to save lots of casts. */
1020 register struct costs *p = &costs[i];
1022 for (class = (int) ALL_REGS - 1; class > 0; class--)
1024 /* Ignore classes that are too small for this operand or
1025 invalid for a operand that was auto-incremented. */
1026 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1027 > reg_class_size[class]
1028 #ifdef FORBIDDEN_INC_DEC_CLASSES
1029 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1033 else if (p->cost[class] < best_cost)
1035 best_cost = p->cost[class];
1036 best = (enum reg_class) class;
1038 else if (p->cost[class] == best_cost)
1039 best = reg_class_subunion[(int)best][class];
1042 /* Record the alternate register class; i.e., a class for which
1043 every register in it is better than using memory. If adding a
1044 class would make a smaller class (i.e., no union of just those
1045 classes exists), skip that class. The major unions of classes
1046 should be provided as a register class. Don't do this if we
1047 will be doing it again later. */
1049 if (pass == 1 || ! flag_expensive_optimizations)
1050 for (class = 0; class < N_REG_CLASSES; class++)
1051 if (p->cost[class] < p->mem_cost
1052 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1053 > reg_class_size[(int) alt])
1054 #ifdef FORBIDDEN_INC_DEC_CLASSES
1055 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1058 alt = reg_class_subunion[(int) alt][class];
1060 /* If we don't add any classes, nothing to try. */
1064 /* We cast to (int) because (char) hits bugs in some compilers. */
1065 prefclass[i] = (int) best;
1066 altclass[i] = (int) alt;
1069 #endif /* REGISTER_CONSTRAINTS */
1072 #ifdef REGISTER_CONSTRAINTS
1074 /* Record the cost of using memory or registers of various classes for
1075 the operands in INSN.
1077 N_ALTS is the number of alternatives.
1079 N_OPS is the number of operands.
1081 OPS is an array of the operands.
1083 MODES are the modes of the operands, in case any are VOIDmode.
1085 CONSTRAINTS are the constraints to use for the operands. This array
1086 is modified by this procedure.
1088 This procedure works alternative by alternative. For each alternative
1089 we assume that we will be able to allocate all pseudos to their ideal
1090 register class and calculate the cost of using that alternative. Then
1091 we compute for each operand that is a pseudo-register, the cost of
1092 having the pseudo allocated to each register class and using it in that
1093 alternative. To this cost is added the cost of the alternative.
1095 The cost of each class for this insn is its lowest cost among all the
1099 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
1103 enum machine_mode *modes;
1108 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS];
1112 /* By default, each operand is an input operand. */
1114 for (i = 0; i < n_ops; i++)
1115 op_types[i] = OP_READ;
1117 /* Process each alternative, each time minimizing an operand's cost with
1118 the cost for each operand in that alternative. */
1120 for (alt = 0; alt < n_alts; alt++)
1122 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1125 enum reg_class classes[MAX_RECOG_OPERANDS];
1128 for (i = 0; i < n_ops; i++)
1130 char *p = constraints[i];
1132 enum machine_mode mode = modes[i];
1137 /* If this operand has no constraints at all, we can conclude
1138 nothing about it since anything is valid. */
1142 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1143 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1151 /* If this alternative is only relevant when this operand
1152 matches a previous operand, we do different things depending
1153 on whether this operand is a pseudo-reg or not. */
1155 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1158 classes[i] = classes[j];
1160 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1162 /* If this matches the other operand, we have no added
1164 if (rtx_equal_p (ops[j], op))
1167 /* If we can put the other operand into a register, add to
1168 the cost of this alternative the cost to copy this
1169 operand to the register used for the other operand. */
1171 else if (classes[j] != NO_REGS)
1172 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1174 else if (GET_CODE (ops[j]) != REG
1175 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1177 /* This op is a pseudo but the one it matches is not. */
1179 /* If we can't put the other operand into a register, this
1180 alternative can't be used. */
1182 if (classes[j] == NO_REGS)
1185 /* Otherwise, add to the cost of this alternative the cost
1186 to copy the other operand to the register used for this
1190 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1194 /* The costs of this operand are the same as that of the
1195 other operand. However, if we cannot tie them, this
1196 alternative needs to do a copy, which is one
1199 this_op_costs[i] = this_op_costs[j];
1200 if (REGNO (ops[i]) != REGNO (ops[j])
1201 && ! find_reg_note (insn, REG_DEAD, op))
1204 /* This is in place of ordinary cost computation
1205 for this operand, so skip to the end of the
1206 alternative (should be just one character). */
1207 while (*p && *p++ != ',')
1215 /* Scan all the constraint letters. See if the operand matches
1216 any of the constraints. Collect the valid register classes
1217 and see if this operand accepts memory. */
1219 classes[i] = NO_REGS;
1220 while (*p && (c = *p++) != ',')
1224 op_types[i] = OP_WRITE;
1228 op_types[i] = OP_READ_WRITE;
1232 /* Ignore the next letter for this pass. */
1241 case '0': case '1': case '2': case '3': case '4':
1245 case 'm': case 'o': case 'V':
1246 /* It doesn't seem worth distinguishing between offsettable
1247 and non-offsettable addresses here. */
1249 if (GET_CODE (op) == MEM)
1254 if (GET_CODE (op) == MEM
1255 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1256 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1261 if (GET_CODE (op) == MEM
1262 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1263 || GET_CODE (XEXP (op, 0)) == POST_INC))
1268 #ifndef REAL_ARITHMETIC
1269 /* Match any floating double constant, but only if
1270 we can examine the bits of it reliably. */
1271 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1272 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1273 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1276 if (GET_CODE (op) == CONST_DOUBLE)
1281 if (GET_CODE (op) == CONST_DOUBLE)
1287 if (GET_CODE (op) == CONST_DOUBLE
1288 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1293 if (GET_CODE (op) == CONST_INT
1294 || (GET_CODE (op) == CONST_DOUBLE
1295 && GET_MODE (op) == VOIDmode))
1299 #ifdef LEGITIMATE_PIC_OPERAND_P
1300 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1307 if (GET_CODE (op) == CONST_INT
1308 || (GET_CODE (op) == CONST_DOUBLE
1309 && GET_MODE (op) == VOIDmode))
1321 if (GET_CODE (op) == CONST_INT
1322 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1330 #ifdef EXTRA_CONSTRAINT
1336 if (EXTRA_CONSTRAINT (op, c))
1342 if (GET_CODE (op) == MEM
1344 #ifdef LEGITIMATE_PIC_OPERAND_P
1345 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1352 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1357 = reg_class_subunion[(int) classes[i]]
1358 [(int) REG_CLASS_FROM_LETTER (c)];
1363 /* How we account for this operand now depends on whether it is a
1364 pseudo register or not. If it is, we first check if any
1365 register classes are valid. If not, we ignore this alternative,
1366 since we want to assume that all pseudos get allocated for
1367 register preferencing. If some register class is valid, compute
1368 the costs of moving the pseudo into that class. */
1370 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1372 if (classes[i] == NO_REGS)
1376 struct costs *pp = &this_op_costs[i];
1378 for (class = 0; class < N_REG_CLASSES; class++)
1379 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1381 /* If the alternative actually allows memory, make things
1382 a bit cheaper since we won't need an extra insn to
1385 pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1)
1388 /* If we have assigned a class to this register in our
1389 first pass, add a cost to this alternative corresponding
1390 to what we would add if this register were not in the
1391 appropriate class. */
1395 += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]];
1399 /* Otherwise, if this alternative wins, either because we
1400 have already determined that or if we have a hard register of
1401 the proper class, there is no cost for this alternative. */
1404 || (GET_CODE (op) == REG
1405 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1408 /* If registers are valid, the cost of this alternative includes
1409 copying the object to and/or from a register. */
1411 else if (classes[i] != NO_REGS)
1413 if (op_types[i] != OP_WRITE)
1414 alt_cost += copy_cost (op, mode, classes[i], 1);
1416 if (op_types[i] != OP_READ)
1417 alt_cost += copy_cost (op, mode, classes[i], 0);
1420 /* The only other way this alternative can be used is if this is a
1421 constant that could be placed into memory. */
1423 else if (CONSTANT_P (op) && allows_mem)
1424 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1432 /* Finally, update the costs with the information we've calculated
1433 about this alternative. */
1435 for (i = 0; i < n_ops; i++)
1436 if (GET_CODE (ops[i]) == REG
1437 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1439 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1440 int scale = 1 + (op_types[i] == OP_READ_WRITE);
1442 pp->mem_cost = MIN (pp->mem_cost,
1443 (qq->mem_cost + alt_cost) * scale);
1445 for (class = 0; class < N_REG_CLASSES; class++)
1446 pp->cost[class] = MIN (pp->cost[class],
1447 (qq->cost[class] + alt_cost) * scale);
1451 /* If this insn is a single set copying operand 1 to operand 0
1452 and one is a pseudo with the other a hard reg that is in its
1453 own register class, set the cost of that register class to -1. */
1455 if ((set = single_set (insn)) != 0
1456 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1457 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1458 for (i = 0; i <= 1; i++)
1459 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1461 int regno = REGNO (ops[!i]);
1462 enum machine_mode mode = GET_MODE (ops[!i]);
1466 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1467 && (reg_class_size[prefclass[regno]]
1468 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1469 op_costs[i].cost[prefclass[regno]] = -1;
1470 else if (regno < FIRST_PSEUDO_REGISTER)
1471 for (class = 0; class < N_REG_CLASSES; class++)
1472 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1473 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1475 if (reg_class_size[class] == 1)
1476 op_costs[i].cost[class] = -1;
1479 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1481 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1485 if (nr == HARD_REGNO_NREGS(regno,mode))
1486 op_costs[i].cost[class] = -1;
1492 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1493 TO_P is zero) a register of class CLASS in mode MODE.
1495 X must not be a pseudo. */
1498 copy_cost (x, mode, class, to_p)
1500 enum machine_mode mode;
1501 enum reg_class class;
1504 #ifdef HAVE_SECONDARY_RELOADS
1505 enum reg_class secondary_class = NO_REGS;
1508 /* If X is a SCRATCH, there is actually nothing to move since we are
1509 assuming optimal allocation. */
1511 if (GET_CODE (x) == SCRATCH)
1514 /* Get the class we will actually use for a reload. */
1515 class = PREFERRED_RELOAD_CLASS (x, class);
1517 #ifdef HAVE_SECONDARY_RELOADS
1518 /* If we need a secondary reload (we assume here that we are using
1519 the secondary reload as an intermediate, not a scratch register), the
1520 cost is that to load the input into the intermediate register, then
1521 to copy them. We use a special value of TO_P to avoid recursion. */
1523 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1525 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1528 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1530 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1533 if (secondary_class != NO_REGS)
1534 return (move_cost[(int) secondary_class][(int) class]
1535 + copy_cost (x, mode, secondary_class, 2));
1536 #endif /* HAVE_SECONDARY_RELOADS */
1538 /* For memory, use the memory move cost, for (hard) registers, use the
1539 cost to move between the register classes, and use 2 for everything
1540 else (constants). */
1542 if (GET_CODE (x) == MEM || class == NO_REGS)
1543 return MEMORY_MOVE_COST (mode, class, to_p);
1545 else if (GET_CODE (x) == REG)
1546 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1549 /* If this is a constant, we may eventually want to call rtx_cost here. */
1553 /* Record the pseudo registers we must reload into hard registers
1554 in a subexpression of a memory address, X.
1556 CLASS is the class that the register needs to be in and is either
1557 BASE_REG_CLASS or INDEX_REG_CLASS.
1559 SCALE is twice the amount to multiply the cost by (it is twice so we
1560 can represent half-cost adjustments). */
1563 record_address_regs (x, class, scale)
1565 enum reg_class class;
1568 register enum rtx_code code = GET_CODE (x);
1581 /* When we have an address that is a sum,
1582 we must determine whether registers are "base" or "index" regs.
1583 If there is a sum of two registers, we must choose one to be
1584 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1585 to make a good choice most of the time. We only need to do this
1586 on machines that can have two registers in an address and where
1587 the base and index register classes are different.
1589 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1590 that seems bogus since it should only be set when we are sure
1591 the register is being used as a pointer. */
1594 rtx arg0 = XEXP (x, 0);
1595 rtx arg1 = XEXP (x, 1);
1596 register enum rtx_code code0 = GET_CODE (arg0);
1597 register enum rtx_code code1 = GET_CODE (arg1);
1599 /* Look inside subregs. */
1600 if (code0 == SUBREG)
1601 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1602 if (code1 == SUBREG)
1603 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1605 /* If this machine only allows one register per address, it must
1606 be in the first operand. */
1608 if (MAX_REGS_PER_ADDRESS == 1)
1609 record_address_regs (arg0, class, scale);
1611 /* If index and base registers are the same on this machine, just
1612 record registers in any non-constant operands. We assume here,
1613 as well as in the tests below, that all addresses are in
1616 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1618 record_address_regs (arg0, class, scale);
1619 if (! CONSTANT_P (arg1))
1620 record_address_regs (arg1, class, scale);
1623 /* If the second operand is a constant integer, it doesn't change
1624 what class the first operand must be. */
1626 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1627 record_address_regs (arg0, class, scale);
1629 /* If the second operand is a symbolic constant, the first operand
1630 must be an index register. */
1632 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1633 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1635 /* If both operands are registers but one is already a hard register
1636 of index or base class, give the other the class that the hard
1639 #ifdef REG_OK_FOR_BASE_P
1640 else if (code0 == REG && code1 == REG
1641 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1642 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1643 record_address_regs (arg1,
1644 REG_OK_FOR_BASE_P (arg0)
1645 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1647 else if (code0 == REG && code1 == REG
1648 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1649 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1650 record_address_regs (arg0,
1651 REG_OK_FOR_BASE_P (arg1)
1652 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1656 /* If one operand is known to be a pointer, it must be the base
1657 with the other operand the index. Likewise if the other operand
1660 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1663 record_address_regs (arg0, BASE_REG_CLASS, scale);
1664 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1666 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1669 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1670 record_address_regs (arg1, BASE_REG_CLASS, scale);
1673 /* Otherwise, count equal chances that each might be a base
1674 or index register. This case should be rare. */
1678 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1679 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1680 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1681 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1690 /* Double the importance of a pseudo register that is incremented
1691 or decremented, since it would take two extra insns
1692 if it ends up in the wrong place. If the operand is a pseudo,
1693 show it is being used in an INC_DEC context. */
1695 #ifdef FORBIDDEN_INC_DEC_CLASSES
1696 if (GET_CODE (XEXP (x, 0)) == REG
1697 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1698 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1701 record_address_regs (XEXP (x, 0), class, 2 * scale);
1706 register struct costs *pp = &costs[REGNO (x)];
1709 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1711 for (i = 0; i < N_REG_CLASSES; i++)
1712 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1718 register char *fmt = GET_RTX_FORMAT (code);
1720 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1722 record_address_regs (XEXP (x, i), class, scale);
1727 #ifdef FORBIDDEN_INC_DEC_CLASSES
1729 /* Return 1 if REG is valid as an auto-increment memory reference
1730 to an object of MODE. */
1733 auto_inc_dec_reg_p (reg, mode)
1735 enum machine_mode mode;
1737 #ifdef HAVE_POST_INCREMENT
1738 if (memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1742 #ifdef HAVE_POST_DECREMENT
1743 if (memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1747 #ifdef HAVE_PRE_INCREMENT
1748 if (memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1752 #ifdef HAVE_PRE_DECREMENT
1753 if (memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1761 #endif /* REGISTER_CONSTRAINTS */
1763 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1764 reg_scan and flow_analysis that are indexed by the register number. If
1765 NEW_P is non zero, initialize all of the registers, otherwise only
1766 initialize the new registers allocated. The same table is kept from
1767 function to function, only reallocating it when we need more room. If
1768 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1771 allocate_reg_info (num_regs, new_p, renumber_p)
1776 static size_t regno_allocated = 0;
1777 static short *renumber = (short *)0;
1780 size_t size_renumber;
1781 size_t min = (new_p) ? 0 : reg_n_max;
1782 struct reg_info_data *reg_data;
1783 struct reg_info_data *reg_next;
1785 /* Free up all storage allocated */
1790 VARRAY_FREE (reg_n_info);
1791 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1793 reg_next = reg_data->next;
1794 free ((char *)reg_data);
1797 free (prefclass_buffer);
1798 free (altclass_buffer);
1799 prefclass_buffer = (char *)0;
1800 altclass_buffer = (char *)0;
1801 reg_info_head = (struct reg_info_data *)0;
1802 renumber = (short *)0;
1804 regno_allocated = 0;
1809 if (num_regs > regno_allocated)
1811 size_t old_allocated = regno_allocated;
1813 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1814 size_renumber = regno_allocated * sizeof (short);
1818 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
1819 renumber = (short *) xmalloc (size_renumber);
1820 prefclass_buffer = (char *) xmalloc (regno_allocated);
1821 altclass_buffer = (char *) xmalloc (regno_allocated);
1826 VARRAY_GROW (reg_n_info, regno_allocated);
1828 if (new_p) /* if we're zapping everything, no need to realloc */
1830 free ((char *)renumber);
1831 free ((char *)prefclass_buffer);
1832 free ((char *)altclass_buffer);
1833 renumber = (short *) xmalloc (size_renumber);
1834 prefclass_buffer = (char *) xmalloc (regno_allocated);
1835 altclass_buffer = (char *) xmalloc (regno_allocated);
1840 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1841 prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer,
1844 altclass_buffer = (char *) xrealloc ((char *)altclass_buffer,
1849 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
1850 + sizeof (struct reg_info_data) - sizeof (reg_info);
1851 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
1852 reg_data->min_index = old_allocated;
1853 reg_data->max_index = regno_allocated - 1;
1854 reg_data->next = reg_info_head;
1855 reg_info_head = reg_data;
1858 reg_n_max = num_regs;
1861 /* Loop through each of the segments allocated for the actual
1862 reg_info pages, and set up the pointers, zero the pages, etc. */
1863 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1865 size_t min_index = reg_data->min_index;
1866 size_t max_index = reg_data->max_index;
1868 reg_next = reg_data->next;
1869 if (min_index <= num_regs)
1871 size_t max = (max_index > num_regs) ? num_regs : max_index;
1872 if (!reg_data->used_p) /* page just allocated with calloc */
1873 reg_data->used_p = 1; /* no need to zero */
1875 bzero ((char *) ®_data->data,
1876 sizeof (reg_info) * (max - min_index + 1));
1878 for (i = min_index; i <= max; i++)
1880 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
1881 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
1883 prefclass_buffer[i] = (char) NO_REGS;
1884 altclass_buffer[i] = (char) NO_REGS;
1890 /* If {pref,alt}class have already been allocated, update the pointers to
1891 the newly realloced ones. */
1894 prefclass = prefclass_buffer;
1895 altclass = altclass_buffer;
1899 reg_renumber = renumber;
1901 /* Tell the regset code about the new number of registers */
1902 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
1906 /* This is the `regscan' pass of the compiler, run just before cse
1907 and again just before loop.
1909 It finds the first and last use of each pseudo-register
1910 and records them in the vectors regno_first_uid, regno_last_uid
1911 and counts the number of sets in the vector reg_n_sets.
1913 REPEAT is nonzero the second time this is called. */
1915 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1916 Always at least 3, since the combiner could put that many together
1917 and we want this to remain correct for all the remaining passes. */
1922 reg_scan (f, nregs, repeat)
1929 allocate_reg_info (nregs, TRUE, FALSE);
1932 for (insn = f; insn; insn = NEXT_INSN (insn))
1933 if (GET_CODE (insn) == INSN
1934 || GET_CODE (insn) == CALL_INSN
1935 || GET_CODE (insn) == JUMP_INSN)
1937 if (GET_CODE (PATTERN (insn)) == PARALLEL
1938 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1939 max_parallel = XVECLEN (PATTERN (insn), 0);
1940 reg_scan_mark_refs (PATTERN (insn), insn, 0);
1942 if (REG_NOTES (insn))
1943 reg_scan_mark_refs (REG_NOTES (insn), insn, 1);
1947 /* X is the expression to scan. INSN is the insn it appears in.
1948 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */
1951 reg_scan_mark_refs (x, insn, note_flag)
1956 register enum rtx_code code = GET_CODE (x);
1975 register int regno = REGNO (x);
1977 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
1979 REGNO_LAST_UID (regno) = INSN_UID (insn);
1980 if (REGNO_FIRST_UID (regno) == 0)
1981 REGNO_FIRST_UID (regno) = INSN_UID (insn);
1987 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag);
1989 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1994 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1998 /* Count a set of the destination if it is a register. */
1999 for (dest = SET_DEST (x);
2000 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2001 || GET_CODE (dest) == ZERO_EXTEND;
2002 dest = XEXP (dest, 0))
2005 if (GET_CODE (dest) == REG)
2006 REG_N_SETS (REGNO (dest))++;
2008 /* If this is setting a pseudo from another pseudo or the sum of a
2009 pseudo and a constant integer and the other pseudo is known to be
2010 a pointer, set the destination to be a pointer as well.
2012 Likewise if it is setting the destination from an address or from a
2013 value equivalent to an address or to the sum of an address and
2016 But don't do any of this if the pseudo corresponds to a user
2017 variable since it should have already been set as a pointer based
2020 if (GET_CODE (SET_DEST (x)) == REG
2021 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2022 /* If the destination pseudo is set more than once, then other
2023 sets might not be to a pointer value (consider access to a
2024 union in two threads of control in the presense of global
2025 optimizations). So only set REGNO_POINTER_FLAG on the destination
2026 pseudo if this is the only set of that pseudo. */
2027 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2028 && ! REG_USERVAR_P (SET_DEST (x))
2029 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2030 && ((GET_CODE (SET_SRC (x)) == REG
2031 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2032 || ((GET_CODE (SET_SRC (x)) == PLUS
2033 || GET_CODE (SET_SRC (x)) == LO_SUM)
2034 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2035 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2036 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2037 || GET_CODE (SET_SRC (x)) == CONST
2038 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2039 || GET_CODE (SET_SRC (x)) == LABEL_REF
2040 || (GET_CODE (SET_SRC (x)) == HIGH
2041 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2042 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2043 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2044 || ((GET_CODE (SET_SRC (x)) == PLUS
2045 || GET_CODE (SET_SRC (x)) == LO_SUM)
2046 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2047 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2048 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2049 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2050 && (GET_CODE (XEXP (note, 0)) == CONST
2051 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2052 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2053 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2055 /* ... fall through ... */
2059 register char *fmt = GET_RTX_FORMAT (code);
2061 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2064 reg_scan_mark_refs (XEXP (x, i), insn, note_flag);
2065 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2068 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2069 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag);
2076 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2080 reg_class_subset_p (c1, c2)
2081 register enum reg_class c1;
2082 register enum reg_class c2;
2084 if (c1 == c2) return 1;
2089 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2090 reg_class_contents[(int)c2],
2095 /* Return nonzero if there is a register that is in both C1 and C2. */
2098 reg_classes_intersect_p (c1, c2)
2099 register enum reg_class c1;
2100 register enum reg_class c2;
2107 if (c1 == c2) return 1;
2109 if (c1 == ALL_REGS || c2 == ALL_REGS)
2112 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2113 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2115 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2122 /* Release any memory allocated by register sets. */
2125 regset_release_memory ()
2127 if (basic_block_live_at_start)
2129 free_regset_vector (basic_block_live_at_start, n_basic_blocks);
2130 basic_block_live_at_start = 0;
2133 FREE_REG_SET (regs_live_at_setjmp);
2134 bitmap_release_memory ();