1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
29 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "insn-config.h"
40 #ifndef REGISTER_MOVE_COST
41 #define REGISTER_MOVE_COST(x, y) 2
44 static void init_reg_sets_1 PROTO((void));
45 static void init_reg_modes PROTO((void));
47 /* If we have auto-increment or auto-decrement and we can have secondary
48 reloads, we are not allowed to use classes requiring secondary
49 reloads for pseudos auto-incremented since reload can't handle it. */
52 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
53 #define FORBIDDEN_INC_DEC_CLASSES
57 /* Register tables used by many passes. */
59 /* Indexed by hard register number, contains 1 for registers
60 that are fixed use (stack pointer, pc, frame pointer, etc.).
61 These are the registers that cannot be used to allocate
62 a pseudo reg for general use. */
64 char fixed_regs[FIRST_PSEUDO_REGISTER];
66 /* Same info as a HARD_REG_SET. */
68 HARD_REG_SET fixed_reg_set;
70 /* Data for initializing the above. */
72 static char initial_fixed_regs[] = FIXED_REGISTERS;
74 /* Indexed by hard register number, contains 1 for registers
75 that are fixed use or are clobbered by function calls.
76 These are the registers that cannot be used to allocate
77 a pseudo reg whose life crosses calls unless we are able
78 to save/restore them across the calls. */
80 char call_used_regs[FIRST_PSEUDO_REGISTER];
82 /* Same info as a HARD_REG_SET. */
84 HARD_REG_SET call_used_reg_set;
86 /* HARD_REG_SET of registers we want to avoid caller saving. */
87 HARD_REG_SET losing_caller_save_reg_set;
89 /* Data for initializing the above. */
91 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
93 /* Indexed by hard register number, contains 1 for registers that are
94 fixed use or call used registers that cannot hold quantities across
95 calls even if we are willing to save and restore them. call fixed
96 registers are a subset of call used registers. */
98 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
100 /* The same info as a HARD_REG_SET. */
102 HARD_REG_SET call_fixed_reg_set;
104 /* Number of non-fixed registers. */
106 int n_non_fixed_regs;
108 /* Indexed by hard register number, contains 1 for registers
109 that are being used for global register decls.
110 These must be exempt from ordinary flow analysis
111 and are also considered fixed. */
113 char global_regs[FIRST_PSEUDO_REGISTER];
115 /* Table of register numbers in the order in which to try to use them. */
116 #ifdef REG_ALLOC_ORDER
117 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
120 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
122 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
124 /* The same information, but as an array of unsigned ints. We copy from
125 these unsigned ints to the table above. We do this so the tm.h files
126 do not have to be aware of the wordsize for machines with <= 64 regs. */
129 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
131 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
132 = REG_CLASS_CONTENTS;
134 /* For each reg class, number of regs it contains. */
136 int reg_class_size[N_REG_CLASSES];
138 /* For each reg class, table listing all the containing classes. */
140 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
142 /* For each reg class, table listing all the classes contained in it. */
144 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
146 /* For each pair of reg classes,
147 a largest reg class contained in their union. */
149 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
151 /* For each pair of reg classes,
152 the smallest reg class containing their union. */
154 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
156 /* Array containing all of the register names */
158 char *reg_names[] = REGISTER_NAMES;
160 /* For each hard register, the widest mode object that it can contain.
161 This will be a MODE_INT mode if the register can hold integers. Otherwise
162 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
165 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
167 /* Maximum cost of moving from a register in one class to a register in
168 another class. Based on REGISTER_MOVE_COST. */
170 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
172 /* Similar, but here we don't have to move if the first index is a subset
173 of the second so in that case the cost is zero. */
175 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
177 #ifdef FORBIDDEN_INC_DEC_CLASSES
179 /* These are the classes that regs which are auto-incremented or decremented
182 static int forbidden_inc_dec_class[N_REG_CLASSES];
184 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
187 static char *in_inc_dec;
189 #endif /* FORBIDDEN_INC_DEC_CLASSES */
191 #ifdef HAVE_SECONDARY_RELOADS
193 /* Sample MEM values for use by memory_move_secondary_cost. */
195 static rtx top_of_stack[MAX_MACHINE_MODE];
197 #endif /* HAVE_SECONDARY_RELOADS */
199 /* Linked list of reg_info structures allocated for reg_n_info array.
200 Grouping all of the allocated structures together in one lump
201 means only one call to bzero to clear them, rather than n smaller
203 struct reg_info_data {
204 struct reg_info_data *next; /* next set of reg_info structures */
205 size_t min_index; /* minimum index # */
206 size_t max_index; /* maximum index # */
207 char used_p; /* non-zero if this has been used previously */
208 reg_info data[1]; /* beginning of the reg_info data */
211 static struct reg_info_data *reg_info_head;
214 /* Function called only once to initialize the above data on reg usage.
215 Once this is done, various switches may override. */
222 /* First copy the register information from the initial int form into
225 for (i = 0; i < N_REG_CLASSES; i++)
227 CLEAR_HARD_REG_SET (reg_class_contents[i]);
229 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
230 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
231 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
232 SET_HARD_REG_BIT (reg_class_contents[i], j);
235 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
236 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
237 bzero (global_regs, sizeof global_regs);
239 /* Do any additional initialization regsets may need */
240 INIT_ONCE_REG_SET ();
243 /* After switches have been processed, which perhaps alter
244 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
249 register unsigned int i, j;
251 /* This macro allows the fixed or call-used registers
252 and the register classes to depend on target flags. */
254 #ifdef CONDITIONAL_REGISTER_USAGE
255 CONDITIONAL_REGISTER_USAGE;
258 /* Compute number of hard regs in each class. */
260 bzero ((char *) reg_class_size, sizeof reg_class_size);
261 for (i = 0; i < N_REG_CLASSES; i++)
262 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
263 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
266 /* Initialize the table of subunions.
267 reg_class_subunion[I][J] gets the largest-numbered reg-class
268 that is contained in the union of classes I and J. */
270 for (i = 0; i < N_REG_CLASSES; i++)
272 for (j = 0; j < N_REG_CLASSES; j++)
275 register /* Declare it register if it's a scalar. */
280 COPY_HARD_REG_SET (c, reg_class_contents[i]);
281 IOR_HARD_REG_SET (c, reg_class_contents[j]);
282 for (k = 0; k < N_REG_CLASSES; k++)
284 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
289 /* keep the largest subclass */ /* SPEE 900308 */
290 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
291 reg_class_contents[(int) reg_class_subunion[i][j]],
293 reg_class_subunion[i][j] = (enum reg_class) k;
300 /* Initialize the table of superunions.
301 reg_class_superunion[I][J] gets the smallest-numbered reg-class
302 containing the union of classes I and J. */
304 for (i = 0; i < N_REG_CLASSES; i++)
306 for (j = 0; j < N_REG_CLASSES; j++)
309 register /* Declare it register if it's a scalar. */
314 COPY_HARD_REG_SET (c, reg_class_contents[i]);
315 IOR_HARD_REG_SET (c, reg_class_contents[j]);
316 for (k = 0; k < N_REG_CLASSES; k++)
317 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
320 reg_class_superunion[i][j] = (enum reg_class) k;
324 /* Initialize the tables of subclasses and superclasses of each reg class.
325 First clear the whole table, then add the elements as they are found. */
327 for (i = 0; i < N_REG_CLASSES; i++)
329 for (j = 0; j < N_REG_CLASSES; j++)
331 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
332 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
336 for (i = 0; i < N_REG_CLASSES; i++)
338 if (i == (int) NO_REGS)
341 for (j = i + 1; j < N_REG_CLASSES; j++)
345 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
349 /* Reg class I is a subclass of J.
350 Add J to the table of superclasses of I. */
351 p = ®_class_superclasses[i][0];
352 while (*p != LIM_REG_CLASSES) p++;
353 *p = (enum reg_class) j;
354 /* Add I to the table of superclasses of J. */
355 p = ®_class_subclasses[j][0];
356 while (*p != LIM_REG_CLASSES) p++;
357 *p = (enum reg_class) i;
361 /* Initialize "constant" tables. */
363 CLEAR_HARD_REG_SET (fixed_reg_set);
364 CLEAR_HARD_REG_SET (call_used_reg_set);
365 CLEAR_HARD_REG_SET (call_fixed_reg_set);
367 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
369 n_non_fixed_regs = 0;
371 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
374 SET_HARD_REG_BIT (fixed_reg_set, i);
378 if (call_used_regs[i])
379 SET_HARD_REG_BIT (call_used_reg_set, i);
380 if (call_fixed_regs[i])
381 SET_HARD_REG_BIT (call_fixed_reg_set, i);
382 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
383 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
386 /* Initialize the move cost table. Find every subset of each class
387 and take the maximum cost of moving any subset to any other. */
389 for (i = 0; i < N_REG_CLASSES; i++)
390 for (j = 0; j < N_REG_CLASSES; j++)
392 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
393 enum reg_class *p1, *p2;
395 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
397 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
399 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
402 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
404 for (p2 = ®_class_subclasses[j][0];
405 *p2 != LIM_REG_CLASSES; p2++)
407 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
410 move_cost[i][j] = cost;
412 if (reg_class_subset_p (i, j))
415 may_move_cost[i][j] = cost;
419 /* Compute the table of register modes.
420 These values are used to record death information for individual registers
421 (as opposed to a multi-register mode). */
428 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
430 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
432 /* If we couldn't find a valid mode, just use the previous mode.
433 ??? One situation in which we need to do this is on the mips where
434 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
435 to use DF mode for the even registers and VOIDmode for the odd
436 (for the cpu models where the odd ones are inaccessible). */
437 if (reg_raw_mode[i] == VOIDmode)
438 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
442 /* Finish initializing the register sets and
443 initialize the register modes. */
448 /* This finishes what was started by init_reg_sets, but couldn't be done
449 until after register usage was specified. */
454 #ifdef HAVE_SECONDARY_RELOADS
456 /* Make some fake stack-frame MEM references for use in
457 memory_move_secondary_cost. */
459 for (i = 0; i < MAX_MACHINE_MODE; i++)
460 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
465 #ifdef HAVE_SECONDARY_RELOADS
467 /* Compute extra cost of moving registers to/from memory due to reloads.
468 Only needed if secondary reloads are required for memory moves. */
471 memory_move_secondary_cost (mode, class, in)
472 enum machine_mode mode;
473 enum reg_class class;
476 enum reg_class altclass;
477 int partial_cost = 0;
478 /* We need a memory reference to feed to SECONDARY... macros. */
479 rtx mem = top_of_stack[(int) mode];
483 #ifdef SECONDARY_INPUT_RELOAD_CLASS
484 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
491 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
492 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
498 if (altclass == NO_REGS)
502 partial_cost = REGISTER_MOVE_COST (altclass, class);
504 partial_cost = REGISTER_MOVE_COST (class, altclass);
506 if (class == altclass)
507 /* This isn't simply a copy-to-temporary situation. Can't guess
508 what it is, so MEMORY_MOVE_COST really ought not to be calling
511 I'm tempted to put in an abort here, but returning this will
512 probably only give poor estimates, which is what we would've
513 had before this code anyways. */
516 /* Check if the secondary reload register will also need a
518 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
522 /* Return a machine mode that is legitimate for hard reg REGNO and large
523 enough to save nregs. If we can't find one, return VOIDmode. */
526 choose_hard_reg_mode (regno, nregs)
530 enum machine_mode found_mode = VOIDmode, mode;
532 /* We first look for the largest integer mode that can be validly
533 held in REGNO. If none, we look for the largest floating-point mode.
534 If we still didn't find a valid mode, try CCmode. */
536 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
538 mode = GET_MODE_WIDER_MODE (mode))
539 if (HARD_REGNO_NREGS (regno, mode) == nregs
540 && HARD_REGNO_MODE_OK (regno, mode))
543 if (found_mode != VOIDmode)
546 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
548 mode = GET_MODE_WIDER_MODE (mode))
549 if (HARD_REGNO_NREGS (regno, mode) == nregs
550 && HARD_REGNO_MODE_OK (regno, mode))
553 if (found_mode != VOIDmode)
556 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
557 && HARD_REGNO_MODE_OK (regno, CCmode))
560 /* We can't find a mode valid for this register. */
564 /* Specify the usage characteristics of the register named NAME.
565 It should be a fixed register if FIXED and a
566 call-used register if CALL_USED. */
569 fix_register (name, fixed, call_used)
571 int fixed, call_used;
575 /* Decode the name and update the primary form of
576 the register info. */
578 if ((i = decode_reg_name (name)) >= 0)
580 if ((i == STACK_POINTER_REGNUM
581 #ifdef HARD_FRAME_POINTER_REGNUM
582 || i == HARD_FRAME_POINTER_REGNUM
584 || i == FRAME_POINTER_REGNUM
587 && (fixed == 0 || call_used == 0))
589 static char* what_option[2][2] = {
590 { "call-saved", "call-used" },
591 { "no-such-option", "fixed" }};
593 error ("can't use '%s' as a %s register", name,
594 what_option[fixed][call_used]);
598 fixed_regs[i] = fixed;
599 call_used_regs[i] = call_used;
604 warning ("unknown register name: %s", name);
608 /* Mark register number I as global. */
616 warning ("register used for two global register variables");
620 if (call_used_regs[i] && ! fixed_regs[i])
621 warning ("call-clobbered register used for global register variable");
625 /* If already fixed, nothing else to do. */
629 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
632 SET_HARD_REG_BIT (fixed_reg_set, i);
633 SET_HARD_REG_BIT (call_used_reg_set, i);
634 SET_HARD_REG_BIT (call_fixed_reg_set, i);
637 /* Now the data and code for the `regclass' pass, which happens
638 just before local-alloc. */
640 /* The `costs' struct records the cost of using a hard register of each class
641 and of using memory for each pseudo. We use this data to set up
642 register class preferences. */
646 int cost[N_REG_CLASSES];
650 /* Record the cost of each class for each pseudo. */
652 static struct costs *costs;
654 /* Initialized once, and used to initialize cost values for each insn. */
656 static struct costs init_cost;
658 /* Record the same data by operand number, accumulated for each alternative
659 in an insn. The contribution to a pseudo is that of the minimum-cost
662 static struct costs op_costs[MAX_RECOG_OPERANDS];
664 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
665 This is available after `regclass' is run. */
667 static char *prefclass;
669 /* altclass[R] is a register class that we should use for allocating
670 pseudo number R if no register in the preferred class is available.
671 If no register in this class is available, memory is preferred.
673 It might appear to be more general to have a bitmask of classes here,
674 but since it is recommended that there be a class corresponding to the
675 union of most major pair of classes, that generality is not required.
677 This is available after `regclass' is run. */
679 static char *altclass;
681 /* Allocated buffers for prefclass and altclass. */
682 static char *prefclass_buffer;
683 static char *altclass_buffer;
685 /* Record the depth of loops that we are in. */
687 static int loop_depth;
689 /* Account for the fact that insns within a loop are executed very commonly,
690 but don't keep doing this as loops go too deep. */
692 static int loop_cost;
694 static int n_occurrences PROTO((int, char *));
695 static rtx scan_one_insn PROTO((rtx, int));
696 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
698 static int copy_cost PROTO((rtx, enum machine_mode,
699 enum reg_class, int));
700 static void record_address_regs PROTO((rtx, enum reg_class, int));
701 #ifdef FORBIDDEN_INC_DEC_CLASSES
702 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
704 static void reg_scan_mark_refs PROTO((rtx, rtx, int, int));
706 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
707 This function is sometimes called before the info has been computed.
708 When that happens, just return GENERAL_REGS, which is innocuous. */
711 reg_preferred_class (regno)
716 return (enum reg_class) prefclass[regno];
720 reg_alternate_class (regno)
726 return (enum reg_class) altclass[regno];
729 /* Initialize some global data for this pass. */
736 init_cost.mem_cost = 10000;
737 for (i = 0; i < N_REG_CLASSES; i++)
738 init_cost.cost[i] = 10000;
740 /* This prevents dump_flow_info from losing if called
741 before regclass is run. */
745 /* Return the number of times character C occurs in string S. */
757 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
758 time it would save code to put a certain register in a certain class.
759 PASS, when nonzero, inhibits some optimizations which need only be done
761 Return the last insn processed, so that the scan can be continued from
765 scan_one_insn (insn, pass)
769 enum rtx_code code = GET_CODE (insn);
770 enum rtx_code pat_code;
771 char *constraints[MAX_RECOG_OPERANDS];
772 enum machine_mode modes[MAX_RECOG_OPERANDS];
776 /* Show that an insn inside a loop is likely to be executed three
777 times more than insns outside a loop. This is much more aggressive
778 than the assumptions made elsewhere and is being tried as an
783 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
784 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
785 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
786 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
791 if (GET_RTX_CLASS (code) != 'i')
794 pat_code = GET_CODE (PATTERN (insn));
796 || pat_code == CLOBBER
797 || pat_code == ASM_INPUT
798 || pat_code == ADDR_VEC
799 || pat_code == ADDR_DIFF_VEC)
802 set = single_set (insn);
805 for (i = 0; i < recog_n_operands; i++)
807 constraints[i] = recog_constraints[i];
808 modes[i] = recog_operand_mode[i];
811 /* If this insn loads a parameter from its stack slot, then
812 it represents a savings, rather than a cost, if the
813 parameter is stored in memory. Record this fact. */
815 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
816 && GET_CODE (SET_SRC (set)) == MEM
817 && (note = find_reg_note (insn, REG_EQUIV,
819 && GET_CODE (XEXP (note, 0)) == MEM)
821 costs[REGNO (SET_DEST (set))].mem_cost
822 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
825 record_address_regs (XEXP (SET_SRC (set), 0),
826 BASE_REG_CLASS, loop_cost * 2);
830 /* Improve handling of two-address insns such as
831 (set X (ashift CONST Y)) where CONST must be made to
832 match X. Change it into two insns: (set X CONST)
833 (set X (ashift X Y)). If we left this for reloading, it
834 would probably get three insns because X and Y might go
835 in the same place. This prevents X and Y from receiving
838 We can only do this if the modes of operands 0 and 1
839 (which might not be the same) are tieable and we only need
840 do this during our first pass. */
842 if (pass == 0 && optimize
843 && recog_n_operands >= 3
844 && recog_constraints[1][0] == '0'
845 && recog_constraints[1][1] == 0
846 && CONSTANT_P (recog_operand[1])
847 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
848 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
849 && GET_CODE (recog_operand[0]) == REG
850 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
851 recog_operand_mode[1]))
853 rtx previnsn = prev_real_insn (insn);
855 = gen_lowpart (recog_operand_mode[1],
858 = emit_insn_before (gen_move_insn (dest,
862 /* If this insn was the start of a basic block,
863 include the new insn in that block.
864 We need not check for code_label here;
865 while a basic block can start with a code_label,
866 INSN could not be at the beginning of that block. */
867 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
870 for (b = 0; b < n_basic_blocks; b++)
871 if (insn == BLOCK_HEAD (b))
872 BLOCK_HEAD (b) = newinsn;
875 /* This makes one more setting of new insns's dest. */
876 REG_N_SETS (REGNO (recog_operand[0]))++;
878 *recog_operand_loc[1] = recog_operand[0];
879 for (i = recog_n_dups - 1; i >= 0; i--)
880 if (recog_dup_num[i] == 1)
881 *recog_dup_loc[i] = recog_operand[0];
883 return PREV_INSN (newinsn);
886 /* If we get here, we are set up to record the costs of all the
887 operands for this insn. Start by initializing the costs.
888 Then handle any address registers. Finally record the desired
889 classes for any pseudos, doing it twice if some pair of
890 operands are commutative. */
892 for (i = 0; i < recog_n_operands; i++)
894 op_costs[i] = init_cost;
896 if (GET_CODE (recog_operand[i]) == SUBREG)
897 recog_operand[i] = SUBREG_REG (recog_operand[i]);
899 if (GET_CODE (recog_operand[i]) == MEM)
900 record_address_regs (XEXP (recog_operand[i], 0),
901 BASE_REG_CLASS, loop_cost * 2);
902 else if (constraints[i][0] == 'p')
903 record_address_regs (recog_operand[i],
904 BASE_REG_CLASS, loop_cost * 2);
907 /* Check for commutative in a separate loop so everything will
908 have been initialized. We must do this even if one operand
909 is a constant--see addsi3 in m68k.md. */
911 for (i = 0; i < recog_n_operands - 1; i++)
912 if (constraints[i][0] == '%')
914 char *xconstraints[MAX_RECOG_OPERANDS];
917 /* Handle commutative operands by swapping the constraints.
918 We assume the modes are the same. */
920 for (j = 0; j < recog_n_operands; j++)
921 xconstraints[j] = constraints[j];
923 xconstraints[i] = constraints[i+1];
924 xconstraints[i+1] = constraints[i];
925 record_reg_classes (recog_n_alternatives, recog_n_operands,
926 recog_operand, modes, xconstraints,
930 record_reg_classes (recog_n_alternatives, recog_n_operands, recog_operand,
931 modes, constraints, insn);
933 /* Now add the cost for each operand to the total costs for
936 for (i = 0; i < recog_n_operands; i++)
937 if (GET_CODE (recog_operand[i]) == REG
938 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
940 int regno = REGNO (recog_operand[i]);
941 struct costs *p = &costs[regno], *q = &op_costs[i];
943 p->mem_cost += q->mem_cost * loop_cost;
944 for (j = 0; j < N_REG_CLASSES; j++)
945 p->cost[j] += q->cost[j] * loop_cost;
951 /* This is a pass of the compiler that scans all instructions
952 and calculates the preferred class for each pseudo-register.
953 This information can be accessed later by calling `reg_preferred_class'.
954 This pass comes just before local register allocation. */
961 #ifdef REGISTER_CONSTRAINTS
968 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
970 #ifdef FORBIDDEN_INC_DEC_CLASSES
972 in_inc_dec = (char *) alloca (nregs);
974 /* Initialize information about which register classes can be used for
975 pseudos that are auto-incremented or auto-decremented. It would
976 seem better to put this in init_reg_sets, but we need to be able
977 to allocate rtx, which we can't do that early. */
979 for (i = 0; i < N_REG_CLASSES; i++)
981 rtx r = gen_rtx_REG (VOIDmode, 0);
985 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
986 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
990 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
991 m = (enum machine_mode) ((int) m + 1))
992 if (HARD_REGNO_MODE_OK (j, m))
996 /* If a register is not directly suitable for an
997 auto-increment or decrement addressing mode and
998 requires secondary reloads, disallow its class from
999 being used in such addresses. */
1002 #ifdef SECONDARY_RELOAD_CLASS
1003 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1006 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1007 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1010 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1011 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1016 && ! auto_inc_dec_reg_p (r, m))
1017 forbidden_inc_dec_class[i] = 1;
1021 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1023 /* Normally we scan the insns once and determine the best class to use for
1024 each register. However, if -fexpensive_optimizations are on, we do so
1025 twice, the second time using the tentative best classes to guide the
1028 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1030 /* Zero out our accumulation of the cost of each class for each reg. */
1032 bzero ((char *) costs, nregs * sizeof (struct costs));
1034 #ifdef FORBIDDEN_INC_DEC_CLASSES
1035 bzero (in_inc_dec, nregs);
1038 loop_depth = 0, loop_cost = 1;
1040 /* Scan the instructions and record each time it would
1041 save code to put a certain register in a certain class. */
1043 for (insn = f; insn; insn = NEXT_INSN (insn))
1045 insn = scan_one_insn (insn, pass);
1048 /* Now for each register look at how desirable each class is
1049 and find which class is preferred. Store that in
1050 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
1051 class any of whose registers is better than memory. */
1055 prefclass = prefclass_buffer;
1056 altclass = altclass_buffer;
1059 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1061 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1062 enum reg_class best = ALL_REGS, alt = NO_REGS;
1063 /* This is an enum reg_class, but we call it an int
1064 to save lots of casts. */
1066 register struct costs *p = &costs[i];
1068 for (class = (int) ALL_REGS - 1; class > 0; class--)
1070 /* Ignore classes that are too small for this operand or
1071 invalid for a operand that was auto-incremented. */
1072 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1073 > reg_class_size[class]
1074 #ifdef FORBIDDEN_INC_DEC_CLASSES
1075 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1079 else if (p->cost[class] < best_cost)
1081 best_cost = p->cost[class];
1082 best = (enum reg_class) class;
1084 else if (p->cost[class] == best_cost)
1085 best = reg_class_subunion[(int)best][class];
1088 /* Record the alternate register class; i.e., a class for which
1089 every register in it is better than using memory. If adding a
1090 class would make a smaller class (i.e., no union of just those
1091 classes exists), skip that class. The major unions of classes
1092 should be provided as a register class. Don't do this if we
1093 will be doing it again later. */
1095 if (pass == 1 || ! flag_expensive_optimizations)
1096 for (class = 0; class < N_REG_CLASSES; class++)
1097 if (p->cost[class] < p->mem_cost
1098 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1099 > reg_class_size[(int) alt])
1100 #ifdef FORBIDDEN_INC_DEC_CLASSES
1101 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1104 alt = reg_class_subunion[(int) alt][class];
1106 /* If we don't add any classes, nothing to try. */
1110 /* We cast to (int) because (char) hits bugs in some compilers. */
1111 prefclass[i] = (int) best;
1112 altclass[i] = (int) alt;
1115 #endif /* REGISTER_CONSTRAINTS */
1120 #ifdef REGISTER_CONSTRAINTS
1122 /* Record the cost of using memory or registers of various classes for
1123 the operands in INSN.
1125 N_ALTS is the number of alternatives.
1127 N_OPS is the number of operands.
1129 OPS is an array of the operands.
1131 MODES are the modes of the operands, in case any are VOIDmode.
1133 CONSTRAINTS are the constraints to use for the operands. This array
1134 is modified by this procedure.
1136 This procedure works alternative by alternative. For each alternative
1137 we assume that we will be able to allocate all pseudos to their ideal
1138 register class and calculate the cost of using that alternative. Then
1139 we compute for each operand that is a pseudo-register, the cost of
1140 having the pseudo allocated to each register class and using it in that
1141 alternative. To this cost is added the cost of the alternative.
1143 The cost of each class for this insn is its lowest cost among all the
1147 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
1151 enum machine_mode *modes;
1159 /* Process each alternative, each time minimizing an operand's cost with
1160 the cost for each operand in that alternative. */
1162 for (alt = 0; alt < n_alts; alt++)
1164 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1167 enum reg_class classes[MAX_RECOG_OPERANDS];
1170 for (i = 0; i < n_ops; i++)
1172 char *p = constraints[i];
1174 enum machine_mode mode = modes[i];
1179 /* Initially show we know nothing about the register class. */
1180 classes[i] = NO_REGS;
1182 /* If this operand has no constraints at all, we can conclude
1183 nothing about it since anything is valid. */
1187 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1188 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1193 /* If this alternative is only relevant when this operand
1194 matches a previous operand, we do different things depending
1195 on whether this operand is a pseudo-reg or not. We must process
1196 any modifiers for the operand before we can make this test. */
1198 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1201 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1204 classes[i] = classes[j];
1206 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1208 /* If this matches the other operand, we have no added
1210 if (rtx_equal_p (ops[j], op))
1213 /* If we can put the other operand into a register, add to
1214 the cost of this alternative the cost to copy this
1215 operand to the register used for the other operand. */
1217 else if (classes[j] != NO_REGS)
1218 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1220 else if (GET_CODE (ops[j]) != REG
1221 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1223 /* This op is a pseudo but the one it matches is not. */
1225 /* If we can't put the other operand into a register, this
1226 alternative can't be used. */
1228 if (classes[j] == NO_REGS)
1231 /* Otherwise, add to the cost of this alternative the cost
1232 to copy the other operand to the register used for this
1236 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1240 /* The costs of this operand are the same as that of the
1241 other operand. However, if we cannot tie them, this
1242 alternative needs to do a copy, which is one
1245 this_op_costs[i] = this_op_costs[j];
1246 if (REGNO (ops[i]) != REGNO (ops[j])
1247 && ! find_reg_note (insn, REG_DEAD, op))
1250 /* This is in place of ordinary cost computation
1251 for this operand, so skip to the end of the
1252 alternative (should be just one character). */
1253 while (*p && *p++ != ',')
1261 /* Scan all the constraint letters. See if the operand matches
1262 any of the constraints. Collect the valid register classes
1263 and see if this operand accepts memory. */
1265 while (*p && (c = *p++) != ',')
1269 /* Ignore the next letter for this pass. */
1275 case '!': case '#': case '&':
1276 case '0': case '1': case '2': case '3': case '4':
1277 case '5': case '6': case '7': case '8': case '9':
1281 case 'm': case 'o': case 'V':
1282 /* It doesn't seem worth distinguishing between offsettable
1283 and non-offsettable addresses here. */
1285 if (GET_CODE (op) == MEM)
1290 if (GET_CODE (op) == MEM
1291 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1292 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1297 if (GET_CODE (op) == MEM
1298 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1299 || GET_CODE (XEXP (op, 0)) == POST_INC))
1304 #ifndef REAL_ARITHMETIC
1305 /* Match any floating double constant, but only if
1306 we can examine the bits of it reliably. */
1307 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1308 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1309 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1312 if (GET_CODE (op) == CONST_DOUBLE)
1317 if (GET_CODE (op) == CONST_DOUBLE)
1323 if (GET_CODE (op) == CONST_DOUBLE
1324 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1329 if (GET_CODE (op) == CONST_INT
1330 || (GET_CODE (op) == CONST_DOUBLE
1331 && GET_MODE (op) == VOIDmode))
1335 #ifdef LEGITIMATE_PIC_OPERAND_P
1336 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1343 if (GET_CODE (op) == CONST_INT
1344 || (GET_CODE (op) == CONST_DOUBLE
1345 && GET_MODE (op) == VOIDmode))
1357 if (GET_CODE (op) == CONST_INT
1358 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1366 #ifdef EXTRA_CONSTRAINT
1372 if (EXTRA_CONSTRAINT (op, c))
1378 if (GET_CODE (op) == MEM
1380 #ifdef LEGITIMATE_PIC_OPERAND_P
1381 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1388 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1393 = reg_class_subunion[(int) classes[i]]
1394 [(int) REG_CLASS_FROM_LETTER (c)];
1399 /* How we account for this operand now depends on whether it is a
1400 pseudo register or not. If it is, we first check if any
1401 register classes are valid. If not, we ignore this alternative,
1402 since we want to assume that all pseudos get allocated for
1403 register preferencing. If some register class is valid, compute
1404 the costs of moving the pseudo into that class. */
1406 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1408 if (classes[i] == NO_REGS)
1412 struct costs *pp = &this_op_costs[i];
1414 for (class = 0; class < N_REG_CLASSES; class++)
1415 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1417 /* If the alternative actually allows memory, make things
1418 a bit cheaper since we won't need an extra insn to
1421 pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1)
1424 /* If we have assigned a class to this register in our
1425 first pass, add a cost to this alternative corresponding
1426 to what we would add if this register were not in the
1427 appropriate class. */
1431 += may_move_cost[(unsigned char)prefclass[REGNO (op)]][(int) classes[i]];
1435 /* Otherwise, if this alternative wins, either because we
1436 have already determined that or if we have a hard register of
1437 the proper class, there is no cost for this alternative. */
1440 || (GET_CODE (op) == REG
1441 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1444 /* If registers are valid, the cost of this alternative includes
1445 copying the object to and/or from a register. */
1447 else if (classes[i] != NO_REGS)
1449 if (recog_op_type[i] != OP_OUT)
1450 alt_cost += copy_cost (op, mode, classes[i], 1);
1452 if (recog_op_type[i] != OP_IN)
1453 alt_cost += copy_cost (op, mode, classes[i], 0);
1456 /* The only other way this alternative can be used is if this is a
1457 constant that could be placed into memory. */
1459 else if (CONSTANT_P (op) && allows_mem)
1460 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1468 /* Finally, update the costs with the information we've calculated
1469 about this alternative. */
1471 for (i = 0; i < n_ops; i++)
1472 if (GET_CODE (ops[i]) == REG
1473 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1475 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1476 int scale = 1 + (recog_op_type[i] == OP_INOUT);
1478 pp->mem_cost = MIN (pp->mem_cost,
1479 (qq->mem_cost + alt_cost) * scale);
1481 for (class = 0; class < N_REG_CLASSES; class++)
1482 pp->cost[class] = MIN (pp->cost[class],
1483 (qq->cost[class] + alt_cost) * scale);
1487 /* If this insn is a single set copying operand 1 to operand 0
1488 and one is a pseudo with the other a hard reg that is in its
1489 own register class, set the cost of that register class to -1. */
1491 if ((set = single_set (insn)) != 0
1492 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1493 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1494 for (i = 0; i <= 1; i++)
1495 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1497 int regno = REGNO (ops[!i]);
1498 enum machine_mode mode = GET_MODE (ops[!i]);
1502 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1503 && (reg_class_size[(unsigned char)prefclass[regno]]
1504 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1505 op_costs[i].cost[(unsigned char)prefclass[regno]] = -1;
1506 else if (regno < FIRST_PSEUDO_REGISTER)
1507 for (class = 0; class < N_REG_CLASSES; class++)
1508 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1509 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1511 if (reg_class_size[class] == 1)
1512 op_costs[i].cost[class] = -1;
1515 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1517 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1521 if (nr == HARD_REGNO_NREGS(regno,mode))
1522 op_costs[i].cost[class] = -1;
1528 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1529 TO_P is zero) a register of class CLASS in mode MODE.
1531 X must not be a pseudo. */
1534 copy_cost (x, mode, class, to_p)
1536 enum machine_mode mode;
1537 enum reg_class class;
1540 #ifdef HAVE_SECONDARY_RELOADS
1541 enum reg_class secondary_class = NO_REGS;
1544 /* If X is a SCRATCH, there is actually nothing to move since we are
1545 assuming optimal allocation. */
1547 if (GET_CODE (x) == SCRATCH)
1550 /* Get the class we will actually use for a reload. */
1551 class = PREFERRED_RELOAD_CLASS (x, class);
1553 #ifdef HAVE_SECONDARY_RELOADS
1554 /* If we need a secondary reload (we assume here that we are using
1555 the secondary reload as an intermediate, not a scratch register), the
1556 cost is that to load the input into the intermediate register, then
1557 to copy them. We use a special value of TO_P to avoid recursion. */
1559 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1561 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1564 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1566 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1569 if (secondary_class != NO_REGS)
1570 return (move_cost[(int) secondary_class][(int) class]
1571 + copy_cost (x, mode, secondary_class, 2));
1572 #endif /* HAVE_SECONDARY_RELOADS */
1574 /* For memory, use the memory move cost, for (hard) registers, use the
1575 cost to move between the register classes, and use 2 for everything
1576 else (constants). */
1578 if (GET_CODE (x) == MEM || class == NO_REGS)
1579 return MEMORY_MOVE_COST (mode, class, to_p);
1581 else if (GET_CODE (x) == REG)
1582 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1585 /* If this is a constant, we may eventually want to call rtx_cost here. */
1589 /* Record the pseudo registers we must reload into hard registers
1590 in a subexpression of a memory address, X.
1592 CLASS is the class that the register needs to be in and is either
1593 BASE_REG_CLASS or INDEX_REG_CLASS.
1595 SCALE is twice the amount to multiply the cost by (it is twice so we
1596 can represent half-cost adjustments). */
1599 record_address_regs (x, class, scale)
1601 enum reg_class class;
1604 register enum rtx_code code = GET_CODE (x);
1617 /* When we have an address that is a sum,
1618 we must determine whether registers are "base" or "index" regs.
1619 If there is a sum of two registers, we must choose one to be
1620 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1621 to make a good choice most of the time. We only need to do this
1622 on machines that can have two registers in an address and where
1623 the base and index register classes are different.
1625 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1626 that seems bogus since it should only be set when we are sure
1627 the register is being used as a pointer. */
1630 rtx arg0 = XEXP (x, 0);
1631 rtx arg1 = XEXP (x, 1);
1632 register enum rtx_code code0 = GET_CODE (arg0);
1633 register enum rtx_code code1 = GET_CODE (arg1);
1635 /* Look inside subregs. */
1636 if (code0 == SUBREG)
1637 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1638 if (code1 == SUBREG)
1639 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1641 /* If this machine only allows one register per address, it must
1642 be in the first operand. */
1644 if (MAX_REGS_PER_ADDRESS == 1)
1645 record_address_regs (arg0, class, scale);
1647 /* If index and base registers are the same on this machine, just
1648 record registers in any non-constant operands. We assume here,
1649 as well as in the tests below, that all addresses are in
1652 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1654 record_address_regs (arg0, class, scale);
1655 if (! CONSTANT_P (arg1))
1656 record_address_regs (arg1, class, scale);
1659 /* If the second operand is a constant integer, it doesn't change
1660 what class the first operand must be. */
1662 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1663 record_address_regs (arg0, class, scale);
1665 /* If the second operand is a symbolic constant, the first operand
1666 must be an index register. */
1668 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1669 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1671 /* If both operands are registers but one is already a hard register
1672 of index or base class, give the other the class that the hard
1675 #ifdef REG_OK_FOR_BASE_P
1676 else if (code0 == REG && code1 == REG
1677 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1678 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1679 record_address_regs (arg1,
1680 REG_OK_FOR_BASE_P (arg0)
1681 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1683 else if (code0 == REG && code1 == REG
1684 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1685 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1686 record_address_regs (arg0,
1687 REG_OK_FOR_BASE_P (arg1)
1688 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1692 /* If one operand is known to be a pointer, it must be the base
1693 with the other operand the index. Likewise if the other operand
1696 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1699 record_address_regs (arg0, BASE_REG_CLASS, scale);
1700 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1702 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1705 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1706 record_address_regs (arg1, BASE_REG_CLASS, scale);
1709 /* Otherwise, count equal chances that each might be a base
1710 or index register. This case should be rare. */
1714 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1715 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1716 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1717 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1726 /* Double the importance of a pseudo register that is incremented
1727 or decremented, since it would take two extra insns
1728 if it ends up in the wrong place. If the operand is a pseudo,
1729 show it is being used in an INC_DEC context. */
1731 #ifdef FORBIDDEN_INC_DEC_CLASSES
1732 if (GET_CODE (XEXP (x, 0)) == REG
1733 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1734 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1737 record_address_regs (XEXP (x, 0), class, 2 * scale);
1742 register struct costs *pp = &costs[REGNO (x)];
1745 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1747 for (i = 0; i < N_REG_CLASSES; i++)
1748 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1754 register char *fmt = GET_RTX_FORMAT (code);
1756 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1758 record_address_regs (XEXP (x, i), class, scale);
1763 #ifdef FORBIDDEN_INC_DEC_CLASSES
1765 /* Return 1 if REG is valid as an auto-increment memory reference
1766 to an object of MODE. */
1769 auto_inc_dec_reg_p (reg, mode)
1771 enum machine_mode mode;
1773 if (HAVE_POST_INCREMENT
1774 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1777 if (HAVE_POST_DECREMENT
1778 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1781 if (HAVE_PRE_INCREMENT
1782 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1785 if (HAVE_PRE_DECREMENT
1786 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1793 #endif /* REGISTER_CONSTRAINTS */
1795 static short *renumber = (short *)0;
1796 static size_t regno_allocated = 0;
1798 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1799 reg_scan and flow_analysis that are indexed by the register number. If
1800 NEW_P is non zero, initialize all of the registers, otherwise only
1801 initialize the new registers allocated. The same table is kept from
1802 function to function, only reallocating it when we need more room. If
1803 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1806 allocate_reg_info (num_regs, new_p, renumber_p)
1812 size_t size_renumber;
1813 size_t min = (new_p) ? 0 : reg_n_max;
1814 struct reg_info_data *reg_data;
1815 struct reg_info_data *reg_next;
1817 if (num_regs > regno_allocated)
1819 size_t old_allocated = regno_allocated;
1821 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1822 size_renumber = regno_allocated * sizeof (short);
1826 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
1827 renumber = (short *) xmalloc (size_renumber);
1828 prefclass_buffer = (char *) xmalloc (regno_allocated);
1829 altclass_buffer = (char *) xmalloc (regno_allocated);
1834 VARRAY_GROW (reg_n_info, regno_allocated);
1836 if (new_p) /* if we're zapping everything, no need to realloc */
1838 free ((char *)renumber);
1839 free ((char *)prefclass_buffer);
1840 free ((char *)altclass_buffer);
1841 renumber = (short *) xmalloc (size_renumber);
1842 prefclass_buffer = (char *) xmalloc (regno_allocated);
1843 altclass_buffer = (char *) xmalloc (regno_allocated);
1848 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1849 prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer,
1852 altclass_buffer = (char *) xrealloc ((char *)altclass_buffer,
1857 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
1858 + sizeof (struct reg_info_data) - sizeof (reg_info);
1859 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
1860 reg_data->min_index = old_allocated;
1861 reg_data->max_index = regno_allocated - 1;
1862 reg_data->next = reg_info_head;
1863 reg_info_head = reg_data;
1866 reg_n_max = num_regs;
1869 /* Loop through each of the segments allocated for the actual
1870 reg_info pages, and set up the pointers, zero the pages, etc. */
1871 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1873 size_t min_index = reg_data->min_index;
1874 size_t max_index = reg_data->max_index;
1876 reg_next = reg_data->next;
1877 if (min <= max_index)
1879 size_t max = max_index;
1880 size_t local_min = min - min_index;
1883 if (min < min_index)
1885 if (!reg_data->used_p) /* page just allocated with calloc */
1886 reg_data->used_p = 1; /* no need to zero */
1888 bzero ((char *) ®_data->data[local_min],
1889 sizeof (reg_info) * (max - min_index - local_min + 1));
1891 for (i = min_index+local_min; i <= max; i++)
1893 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
1894 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
1896 prefclass_buffer[i] = (char) NO_REGS;
1897 altclass_buffer[i] = (char) NO_REGS;
1903 /* If {pref,alt}class have already been allocated, update the pointers to
1904 the newly realloced ones. */
1907 prefclass = prefclass_buffer;
1908 altclass = altclass_buffer;
1912 reg_renumber = renumber;
1914 /* Tell the regset code about the new number of registers */
1915 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
1918 /* Free up the space allocated by allocate_reg_info. */
1924 struct reg_info_data *reg_data;
1925 struct reg_info_data *reg_next;
1927 VARRAY_FREE (reg_n_info);
1928 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1930 reg_next = reg_data->next;
1931 free ((char *)reg_data);
1934 free (prefclass_buffer);
1935 free (altclass_buffer);
1936 prefclass_buffer = (char *)0;
1937 altclass_buffer = (char *)0;
1938 reg_info_head = (struct reg_info_data *)0;
1939 renumber = (short *)0;
1941 regno_allocated = 0;
1945 /* This is the `regscan' pass of the compiler, run just before cse
1946 and again just before loop.
1948 It finds the first and last use of each pseudo-register
1949 and records them in the vectors regno_first_uid, regno_last_uid
1950 and counts the number of sets in the vector reg_n_sets.
1952 REPEAT is nonzero the second time this is called. */
1954 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1955 Always at least 3, since the combiner could put that many together
1956 and we want this to remain correct for all the remaining passes. */
1961 reg_scan (f, nregs, repeat)
1968 allocate_reg_info (nregs, TRUE, FALSE);
1971 for (insn = f; insn; insn = NEXT_INSN (insn))
1972 if (GET_CODE (insn) == INSN
1973 || GET_CODE (insn) == CALL_INSN
1974 || GET_CODE (insn) == JUMP_INSN)
1976 if (GET_CODE (PATTERN (insn)) == PARALLEL
1977 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1978 max_parallel = XVECLEN (PATTERN (insn), 0);
1979 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
1981 if (REG_NOTES (insn))
1982 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
1986 /* Update 'regscan' information by looking at the insns
1987 from FIRST to LAST. Some new REGs have been created,
1988 and any REG with number greater than OLD_MAX_REGNO is
1989 such a REG. We only update information for those. */
1992 reg_scan_update(first, last, old_max_regno)
1999 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2001 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2002 if (GET_CODE (insn) == INSN
2003 || GET_CODE (insn) == CALL_INSN
2004 || GET_CODE (insn) == JUMP_INSN)
2006 if (GET_CODE (PATTERN (insn)) == PARALLEL
2007 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2008 max_parallel = XVECLEN (PATTERN (insn), 0);
2009 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2011 if (REG_NOTES (insn))
2012 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2016 /* X is the expression to scan. INSN is the insn it appears in.
2017 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2018 We should only record information for REGs with numbers
2019 greater than or equal to MIN_REGNO. */
2022 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2028 register enum rtx_code code;
2032 code = GET_CODE (x);
2036 if (GET_CODE (XEXP (x, 0)) == CONSTANT_P_RTX)
2037 reg_scan_mark_refs (XEXP (XEXP (x, 0), 0), insn, note_flag, min_regno);
2052 register int regno = REGNO (x);
2054 if (regno >= min_regno)
2056 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2058 REGNO_LAST_UID (regno) = INSN_UID (insn);
2059 if (REGNO_FIRST_UID (regno) == 0)
2060 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2067 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2069 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2074 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2078 /* Count a set of the destination if it is a register. */
2079 for (dest = SET_DEST (x);
2080 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2081 || GET_CODE (dest) == ZERO_EXTEND;
2082 dest = XEXP (dest, 0))
2085 if (GET_CODE (dest) == REG
2086 && REGNO (dest) >= min_regno)
2087 REG_N_SETS (REGNO (dest))++;
2089 /* If this is setting a pseudo from another pseudo or the sum of a
2090 pseudo and a constant integer and the other pseudo is known to be
2091 a pointer, set the destination to be a pointer as well.
2093 Likewise if it is setting the destination from an address or from a
2094 value equivalent to an address or to the sum of an address and
2097 But don't do any of this if the pseudo corresponds to a user
2098 variable since it should have already been set as a pointer based
2101 if (GET_CODE (SET_DEST (x)) == REG
2102 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2103 && REGNO (SET_DEST (x)) >= min_regno
2104 /* If the destination pseudo is set more than once, then other
2105 sets might not be to a pointer value (consider access to a
2106 union in two threads of control in the presense of global
2107 optimizations). So only set REGNO_POINTER_FLAG on the destination
2108 pseudo if this is the only set of that pseudo. */
2109 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2110 && ! REG_USERVAR_P (SET_DEST (x))
2111 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2112 && ((GET_CODE (SET_SRC (x)) == REG
2113 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2114 || ((GET_CODE (SET_SRC (x)) == PLUS
2115 || GET_CODE (SET_SRC (x)) == LO_SUM)
2116 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2117 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2118 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2119 || GET_CODE (SET_SRC (x)) == CONST
2120 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2121 || GET_CODE (SET_SRC (x)) == LABEL_REF
2122 || (GET_CODE (SET_SRC (x)) == HIGH
2123 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2124 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2125 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2126 || ((GET_CODE (SET_SRC (x)) == PLUS
2127 || GET_CODE (SET_SRC (x)) == LO_SUM)
2128 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2129 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2130 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2131 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2132 && (GET_CODE (XEXP (note, 0)) == CONST
2133 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2134 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2135 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2137 /* ... fall through ... */
2141 register char *fmt = GET_RTX_FORMAT (code);
2143 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2146 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2147 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2150 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2151 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2158 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2162 reg_class_subset_p (c1, c2)
2163 register enum reg_class c1;
2164 register enum reg_class c2;
2166 if (c1 == c2) return 1;
2171 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2172 reg_class_contents[(int)c2],
2177 /* Return nonzero if there is a register that is in both C1 and C2. */
2180 reg_classes_intersect_p (c1, c2)
2181 register enum reg_class c1;
2182 register enum reg_class c2;
2189 if (c1 == c2) return 1;
2191 if (c1 == ALL_REGS || c2 == ALL_REGS)
2194 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2195 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2197 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2204 /* Release any memory allocated by register sets. */
2207 regset_release_memory ()
2209 if (basic_block_live_at_start)
2211 free_regset_vector (basic_block_live_at_start, n_basic_blocks);
2212 basic_block_live_at_start = 0;
2215 FREE_REG_SET (regs_live_at_setjmp);
2216 bitmap_release_memory ();