1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
29 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "insn-config.h"
40 #ifndef REGISTER_MOVE_COST
41 #define REGISTER_MOVE_COST(x, y) 2
44 /* If we have auto-increment or auto-decrement and we can have secondary
45 reloads, we are not allowed to use classes requiring secondary
46 reloads for pseudos auto-incremented since reload can't handle it. */
49 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
50 #define FORBIDDEN_INC_DEC_CLASSES
54 /* Register tables used by many passes. */
56 /* Indexed by hard register number, contains 1 for registers
57 that are fixed use (stack pointer, pc, frame pointer, etc.).
58 These are the registers that cannot be used to allocate
59 a pseudo reg for general use. */
61 char fixed_regs[FIRST_PSEUDO_REGISTER];
63 /* Same info as a HARD_REG_SET. */
65 HARD_REG_SET fixed_reg_set;
67 /* Data for initializing the above. */
69 static char initial_fixed_regs[] = FIXED_REGISTERS;
71 /* Indexed by hard register number, contains 1 for registers
72 that are fixed use or are clobbered by function calls.
73 These are the registers that cannot be used to allocate
74 a pseudo reg whose life crosses calls unless we are able
75 to save/restore them across the calls. */
77 char call_used_regs[FIRST_PSEUDO_REGISTER];
79 /* Same info as a HARD_REG_SET. */
81 HARD_REG_SET call_used_reg_set;
83 /* HARD_REG_SET of registers we want to avoid caller saving. */
84 HARD_REG_SET losing_caller_save_reg_set;
86 /* Data for initializing the above. */
88 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
90 /* Indexed by hard register number, contains 1 for registers that are
91 fixed use or call used registers that cannot hold quantities across
92 calls even if we are willing to save and restore them. call fixed
93 registers are a subset of call used registers. */
95 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
97 /* The same info as a HARD_REG_SET. */
99 HARD_REG_SET call_fixed_reg_set;
101 /* Number of non-fixed registers. */
103 int n_non_fixed_regs;
105 /* Indexed by hard register number, contains 1 for registers
106 that are being used for global register decls.
107 These must be exempt from ordinary flow analysis
108 and are also considered fixed. */
110 char global_regs[FIRST_PSEUDO_REGISTER];
112 /* Table of register numbers in the order in which to try to use them. */
113 #ifdef REG_ALLOC_ORDER
114 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
117 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
119 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
121 /* The same information, but as an array of unsigned ints. We copy from
122 these unsigned ints to the table above. We do this so the tm.h files
123 do not have to be aware of the wordsize for machines with <= 64 regs. */
126 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
128 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
129 = REG_CLASS_CONTENTS;
131 /* For each reg class, number of regs it contains. */
133 int reg_class_size[N_REG_CLASSES];
135 /* For each reg class, table listing all the containing classes. */
137 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
139 /* For each reg class, table listing all the classes contained in it. */
141 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
143 /* For each pair of reg classes,
144 a largest reg class contained in their union. */
146 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
148 /* For each pair of reg classes,
149 the smallest reg class containing their union. */
151 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
153 /* Array containing all of the register names */
155 char *reg_names[] = REGISTER_NAMES;
157 /* For each hard register, the widest mode object that it can contain.
158 This will be a MODE_INT mode if the register can hold integers. Otherwise
159 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
162 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
164 /* Maximum cost of moving from a register in one class to a register in
165 another class. Based on REGISTER_MOVE_COST. */
167 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
169 /* Similar, but here we don't have to move if the first index is a subset
170 of the second so in that case the cost is zero. */
172 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
174 #ifdef FORBIDDEN_INC_DEC_CLASSES
176 /* These are the classes that regs which are auto-incremented or decremented
179 static int forbidden_inc_dec_class[N_REG_CLASSES];
181 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
184 static char *in_inc_dec;
186 #endif /* FORBIDDEN_INC_DEC_CLASSES */
188 #ifdef HAVE_SECONDARY_RELOADS
190 /* Sample MEM values for use by memory_move_secondary_cost. */
192 static rtx top_of_stack[MAX_MACHINE_MODE];
194 #endif /* HAVE_SECONDARY_RELOADS */
196 /* Linked list of reg_info structures allocated for reg_n_info array.
197 Grouping all of the allocated structures together in one lump
198 means only one call to bzero to clear them, rather than n smaller
200 struct reg_info_data {
201 struct reg_info_data *next; /* next set of reg_info structures */
202 size_t min_index; /* minimum index # */
203 size_t max_index; /* maximum index # */
204 char used_p; /* non-zero if this has been used previously */
205 reg_info data[1]; /* beginning of the reg_info data */
208 static struct reg_info_data *reg_info_head;
211 /* Function called only once to initialize the above data on reg usage.
212 Once this is done, various switches may override. */
219 /* First copy the register information from the initial int form into
222 for (i = 0; i < N_REG_CLASSES; i++)
224 CLEAR_HARD_REG_SET (reg_class_contents[i]);
226 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
227 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
228 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
229 SET_HARD_REG_BIT (reg_class_contents[i], j);
232 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
233 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
234 bzero (global_regs, sizeof global_regs);
236 /* Compute number of hard regs in each class. */
238 bzero ((char *) reg_class_size, sizeof reg_class_size);
239 for (i = 0; i < N_REG_CLASSES; i++)
240 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
241 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
244 /* Initialize the table of subunions.
245 reg_class_subunion[I][J] gets the largest-numbered reg-class
246 that is contained in the union of classes I and J. */
248 for (i = 0; i < N_REG_CLASSES; i++)
250 for (j = 0; j < N_REG_CLASSES; j++)
253 register /* Declare it register if it's a scalar. */
258 COPY_HARD_REG_SET (c, reg_class_contents[i]);
259 IOR_HARD_REG_SET (c, reg_class_contents[j]);
260 for (k = 0; k < N_REG_CLASSES; k++)
262 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
267 /* keep the largest subclass */ /* SPEE 900308 */
268 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
269 reg_class_contents[(int) reg_class_subunion[i][j]],
271 reg_class_subunion[i][j] = (enum reg_class) k;
278 /* Initialize the table of superunions.
279 reg_class_superunion[I][J] gets the smallest-numbered reg-class
280 containing the union of classes I and J. */
282 for (i = 0; i < N_REG_CLASSES; i++)
284 for (j = 0; j < N_REG_CLASSES; j++)
287 register /* Declare it register if it's a scalar. */
292 COPY_HARD_REG_SET (c, reg_class_contents[i]);
293 IOR_HARD_REG_SET (c, reg_class_contents[j]);
294 for (k = 0; k < N_REG_CLASSES; k++)
295 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
298 reg_class_superunion[i][j] = (enum reg_class) k;
302 /* Initialize the tables of subclasses and superclasses of each reg class.
303 First clear the whole table, then add the elements as they are found. */
305 for (i = 0; i < N_REG_CLASSES; i++)
307 for (j = 0; j < N_REG_CLASSES; j++)
309 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
310 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
314 for (i = 0; i < N_REG_CLASSES; i++)
316 if (i == (int) NO_REGS)
319 for (j = i + 1; j < N_REG_CLASSES; j++)
323 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
327 /* Reg class I is a subclass of J.
328 Add J to the table of superclasses of I. */
329 p = ®_class_superclasses[i][0];
330 while (*p != LIM_REG_CLASSES) p++;
331 *p = (enum reg_class) j;
332 /* Add I to the table of superclasses of J. */
333 p = ®_class_subclasses[j][0];
334 while (*p != LIM_REG_CLASSES) p++;
335 *p = (enum reg_class) i;
339 /* Do any additional initialization regsets may need */
340 INIT_ONCE_REG_SET ();
343 /* After switches have been processed, which perhaps alter
344 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
349 register unsigned int i, j;
351 /* This macro allows the fixed or call-used registers
352 to depend on target flags. */
354 #ifdef CONDITIONAL_REGISTER_USAGE
355 CONDITIONAL_REGISTER_USAGE;
358 /* Initialize "constant" tables. */
360 CLEAR_HARD_REG_SET (fixed_reg_set);
361 CLEAR_HARD_REG_SET (call_used_reg_set);
362 CLEAR_HARD_REG_SET (call_fixed_reg_set);
364 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
366 n_non_fixed_regs = 0;
368 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
371 SET_HARD_REG_BIT (fixed_reg_set, i);
375 if (call_used_regs[i])
376 SET_HARD_REG_BIT (call_used_reg_set, i);
377 if (call_fixed_regs[i])
378 SET_HARD_REG_BIT (call_fixed_reg_set, i);
379 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
380 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
383 /* Initialize the move cost table. Find every subset of each class
384 and take the maximum cost of moving any subset to any other. */
386 for (i = 0; i < N_REG_CLASSES; i++)
387 for (j = 0; j < N_REG_CLASSES; j++)
389 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
390 enum reg_class *p1, *p2;
392 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
394 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
396 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
399 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
401 for (p2 = ®_class_subclasses[j][0];
402 *p2 != LIM_REG_CLASSES; p2++)
404 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
407 move_cost[i][j] = cost;
409 if (reg_class_subset_p (i, j))
412 may_move_cost[i][j] = cost;
416 /* Compute the table of register modes.
417 These values are used to record death information for individual registers
418 (as opposed to a multi-register mode). */
425 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
427 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
429 /* If we couldn't find a valid mode, just use the previous mode.
430 ??? One situation in which we need to do this is on the mips where
431 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
432 to use DF mode for the even registers and VOIDmode for the odd
433 (for the cpu models where the odd ones are inaccessible). */
434 if (reg_raw_mode[i] == VOIDmode)
435 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
439 /* Finish initializing the register sets and
440 initialize the register modes. */
445 /* This finishes what was started by init_reg_sets, but couldn't be done
446 until after register usage was specified. */
451 #ifdef HAVE_SECONDARY_RELOADS
453 /* Make some fake stack-frame MEM references for use in
454 memory_move_secondary_cost. */
456 for (i = 0; i < MAX_MACHINE_MODE; i++)
457 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
462 #ifdef HAVE_SECONDARY_RELOADS
464 /* Compute extra cost of moving registers to/from memory due to reloads.
465 Only needed if secondary reloads are required for memory moves. */
468 memory_move_secondary_cost (mode, class, in)
469 enum machine_mode mode;
470 enum reg_class class;
473 enum reg_class altclass;
474 int partial_cost = 0;
475 /* We need a memory reference to feed to SECONDARY... macros. */
476 rtx mem = top_of_stack[(int) mode];
480 #ifdef SECONDARY_INPUT_RELOAD_CLASS
481 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
488 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
489 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
495 if (altclass == NO_REGS)
499 partial_cost = REGISTER_MOVE_COST (altclass, class);
501 partial_cost = REGISTER_MOVE_COST (class, altclass);
503 if (class == altclass)
504 /* This isn't simply a copy-to-temporary situation. Can't guess
505 what it is, so MEMORY_MOVE_COST really ought not to be calling
508 I'm tempted to put in an abort here, but returning this will
509 probably only give poor estimates, which is what we would've
510 had before this code anyways. */
513 /* Check if the secondary reload register will also need a
515 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
519 /* Return a machine mode that is legitimate for hard reg REGNO and large
520 enough to save nregs. If we can't find one, return VOIDmode. */
523 choose_hard_reg_mode (regno, nregs)
527 enum machine_mode found_mode = VOIDmode, mode;
529 /* We first look for the largest integer mode that can be validly
530 held in REGNO. If none, we look for the largest floating-point mode.
531 If we still didn't find a valid mode, try CCmode. */
533 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
535 mode = GET_MODE_WIDER_MODE (mode))
536 if (HARD_REGNO_NREGS (regno, mode) == nregs
537 && HARD_REGNO_MODE_OK (regno, mode))
540 if (found_mode != VOIDmode)
543 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
545 mode = GET_MODE_WIDER_MODE (mode))
546 if (HARD_REGNO_NREGS (regno, mode) == nregs
547 && HARD_REGNO_MODE_OK (regno, mode))
550 if (found_mode != VOIDmode)
553 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
554 && HARD_REGNO_MODE_OK (regno, CCmode))
557 /* We can't find a mode valid for this register. */
561 /* Specify the usage characteristics of the register named NAME.
562 It should be a fixed register if FIXED and a
563 call-used register if CALL_USED. */
566 fix_register (name, fixed, call_used)
568 int fixed, call_used;
572 /* Decode the name and update the primary form of
573 the register info. */
575 if ((i = decode_reg_name (name)) >= 0)
577 fixed_regs[i] = fixed;
578 call_used_regs[i] = call_used;
582 warning ("unknown register name: %s", name);
586 /* Mark register number I as global. */
594 warning ("register used for two global register variables");
598 if (call_used_regs[i] && ! fixed_regs[i])
599 warning ("call-clobbered register used for global register variable");
603 /* If already fixed, nothing else to do. */
607 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
610 SET_HARD_REG_BIT (fixed_reg_set, i);
611 SET_HARD_REG_BIT (call_used_reg_set, i);
612 SET_HARD_REG_BIT (call_fixed_reg_set, i);
615 /* Now the data and code for the `regclass' pass, which happens
616 just before local-alloc. */
618 /* The `costs' struct records the cost of using a hard register of each class
619 and of using memory for each pseudo. We use this data to set up
620 register class preferences. */
624 int cost[N_REG_CLASSES];
628 /* Record the cost of each class for each pseudo. */
630 static struct costs *costs;
632 /* Record the same data by operand number, accumulated for each alternative
633 in an insn. The contribution to a pseudo is that of the minimum-cost
636 static struct costs op_costs[MAX_RECOG_OPERANDS];
638 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
639 This is available after `regclass' is run. */
641 static char *prefclass;
643 /* altclass[R] is a register class that we should use for allocating
644 pseudo number R if no register in the preferred class is available.
645 If no register in this class is available, memory is preferred.
647 It might appear to be more general to have a bitmask of classes here,
648 but since it is recommended that there be a class corresponding to the
649 union of most major pair of classes, that generality is not required.
651 This is available after `regclass' is run. */
653 static char *altclass;
655 /* Allocated buffers for prefclass and altclass. */
656 static char *prefclass_buffer;
657 static char *altclass_buffer;
659 /* Record the depth of loops that we are in. */
661 static int loop_depth;
663 /* Account for the fact that insns within a loop are executed very commonly,
664 but don't keep doing this as loops go too deep. */
666 static int loop_cost;
668 static int n_occurrences PROTO((int, char *));
669 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
671 static int copy_cost PROTO((rtx, enum machine_mode,
672 enum reg_class, int));
673 static void record_address_regs PROTO((rtx, enum reg_class, int));
674 #ifdef FORBIDDEN_INC_DEC_CLASSES
675 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
677 static void reg_scan_mark_refs PROTO((rtx, rtx, int, int));
679 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
680 This function is sometimes called before the info has been computed.
681 When that happens, just return GENERAL_REGS, which is innocuous. */
684 reg_preferred_class (regno)
689 return (enum reg_class) prefclass[regno];
693 reg_alternate_class (regno)
699 return (enum reg_class) altclass[regno];
702 /* This prevents dump_flow_info from losing if called
703 before regclass is run. */
711 /* Return the number of times character C occurs in string S. */
723 /* This is a pass of the compiler that scans all instructions
724 and calculates the preferred class for each pseudo-register.
725 This information can be accessed later by calling `reg_preferred_class'.
726 This pass comes just before local register allocation. */
733 #ifdef REGISTER_CONSTRAINTS
736 struct costs init_cost;
742 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
744 #ifdef FORBIDDEN_INC_DEC_CLASSES
746 in_inc_dec = (char *) alloca (nregs);
748 /* Initialize information about which register classes can be used for
749 pseudos that are auto-incremented or auto-decremented. It would
750 seem better to put this in init_reg_sets, but we need to be able
751 to allocate rtx, which we can't do that early. */
753 for (i = 0; i < N_REG_CLASSES; i++)
755 rtx r = gen_rtx_REG (VOIDmode, 0);
758 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
759 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
763 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
764 m = (enum machine_mode) ((int) m + 1))
765 if (HARD_REGNO_MODE_OK (j, m))
769 /* If a register is not directly suitable for an
770 auto-increment or decrement addressing mode and
771 requires secondary reloads, disallow its class from
772 being used in such addresses. */
775 #ifdef SECONDARY_RELOAD_CLASS
776 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
779 #ifdef SECONDARY_INPUT_RELOAD_CLASS
780 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
783 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
784 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
789 && ! auto_inc_dec_reg_p (r, m))
790 forbidden_inc_dec_class[i] = 1;
794 #endif /* FORBIDDEN_INC_DEC_CLASSES */
796 init_cost.mem_cost = 10000;
797 for (i = 0; i < N_REG_CLASSES; i++)
798 init_cost.cost[i] = 10000;
800 /* Normally we scan the insns once and determine the best class to use for
801 each register. However, if -fexpensive_optimizations are on, we do so
802 twice, the second time using the tentative best classes to guide the
805 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
807 /* Zero out our accumulation of the cost of each class for each reg. */
809 bzero ((char *) costs, nregs * sizeof (struct costs));
811 #ifdef FORBIDDEN_INC_DEC_CLASSES
812 bzero (in_inc_dec, nregs);
815 loop_depth = 0, loop_cost = 1;
817 /* Scan the instructions and record each time it would
818 save code to put a certain register in a certain class. */
820 for (insn = f; insn; insn = NEXT_INSN (insn))
822 char *constraints[MAX_RECOG_OPERANDS];
823 enum machine_mode modes[MAX_RECOG_OPERANDS];
827 /* Show that an insn inside a loop is likely to be executed three
828 times more than insns outside a loop. This is much more aggressive
829 than the assumptions made elsewhere and is being tried as an
832 if (GET_CODE (insn) == NOTE
833 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
834 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
835 else if (GET_CODE (insn) == NOTE
836 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
837 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
839 else if ((GET_CODE (insn) == INSN
840 && GET_CODE (PATTERN (insn)) != USE
841 && GET_CODE (PATTERN (insn)) != CLOBBER
842 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
843 || (GET_CODE (insn) == JUMP_INSN
844 && GET_CODE (PATTERN (insn)) != ADDR_VEC
845 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
846 || GET_CODE (insn) == CALL_INSN)
848 if (GET_CODE (insn) == INSN
849 && (noperands = asm_noperands (PATTERN (insn))) >= 0)
851 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR,
853 nalternatives = (noperands == 0 ? 0
854 : n_occurrences (',', constraints[0]) + 1);
858 int insn_code_number = recog_memoized (insn);
861 set = single_set (insn);
864 nalternatives = insn_n_alternatives[insn_code_number];
865 noperands = insn_n_operands[insn_code_number];
867 /* If this insn loads a parameter from its stack slot, then
868 it represents a savings, rather than a cost, if the
869 parameter is stored in memory. Record this fact. */
871 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
872 && GET_CODE (SET_SRC (set)) == MEM
873 && (note = find_reg_note (insn, REG_EQUIV,
875 && GET_CODE (XEXP (note, 0)) == MEM)
877 costs[REGNO (SET_DEST (set))].mem_cost
878 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
881 record_address_regs (XEXP (SET_SRC (set), 0),
882 BASE_REG_CLASS, loop_cost * 2);
886 /* Improve handling of two-address insns such as
887 (set X (ashift CONST Y)) where CONST must be made to
888 match X. Change it into two insns: (set X CONST)
889 (set X (ashift X Y)). If we left this for reloading, it
890 would probably get three insns because X and Y might go
891 in the same place. This prevents X and Y from receiving
894 We can only do this if the modes of operands 0 and 1
895 (which might not be the same) are tieable and we only need
896 do this during our first pass. */
898 if (pass == 0 && optimize
900 && insn_operand_constraint[insn_code_number][1][0] == '0'
901 && insn_operand_constraint[insn_code_number][1][1] == 0
902 && CONSTANT_P (recog_operand[1])
903 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
904 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
905 && GET_CODE (recog_operand[0]) == REG
906 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
907 insn_operand_mode[insn_code_number][1]))
909 rtx previnsn = prev_real_insn (insn);
911 = gen_lowpart (insn_operand_mode[insn_code_number][1],
914 = emit_insn_before (gen_move_insn (dest,
918 /* If this insn was the start of a basic block,
919 include the new insn in that block.
920 We need not check for code_label here;
921 while a basic block can start with a code_label,
922 INSN could not be at the beginning of that block. */
923 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
926 for (b = 0; b < n_basic_blocks; b++)
927 if (insn == basic_block_head[b])
928 basic_block_head[b] = newinsn;
931 /* This makes one more setting of new insns's dest. */
932 REG_N_SETS (REGNO (recog_operand[0]))++;
934 *recog_operand_loc[1] = recog_operand[0];
935 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
936 if (recog_dup_num[i] == 1)
937 *recog_dup_loc[i] = recog_operand[0];
939 insn = PREV_INSN (newinsn);
943 for (i = 0; i < noperands; i++)
946 = insn_operand_constraint[insn_code_number][i];
947 modes[i] = insn_operand_mode[insn_code_number][i];
951 /* If we get here, we are set up to record the costs of all the
952 operands for this insn. Start by initializing the costs.
953 Then handle any address registers. Finally record the desired
954 classes for any pseudos, doing it twice if some pair of
955 operands are commutative. */
957 for (i = 0; i < noperands; i++)
959 op_costs[i] = init_cost;
961 if (GET_CODE (recog_operand[i]) == SUBREG)
962 recog_operand[i] = SUBREG_REG (recog_operand[i]);
964 if (GET_CODE (recog_operand[i]) == MEM)
965 record_address_regs (XEXP (recog_operand[i], 0),
966 BASE_REG_CLASS, loop_cost * 2);
967 else if (constraints[i][0] == 'p')
968 record_address_regs (recog_operand[i],
969 BASE_REG_CLASS, loop_cost * 2);
972 /* Check for commutative in a separate loop so everything will
973 have been initialized. We must do this even if one operand
974 is a constant--see addsi3 in m68k.md. */
976 for (i = 0; i < noperands - 1; i++)
977 if (constraints[i][0] == '%')
979 char *xconstraints[MAX_RECOG_OPERANDS];
982 /* Handle commutative operands by swapping the constraints.
983 We assume the modes are the same. */
985 for (j = 0; j < noperands; j++)
986 xconstraints[j] = constraints[j];
988 xconstraints[i] = constraints[i+1];
989 xconstraints[i+1] = constraints[i];
990 record_reg_classes (nalternatives, noperands,
991 recog_operand, modes, xconstraints,
995 record_reg_classes (nalternatives, noperands, recog_operand,
996 modes, constraints, insn);
998 /* Now add the cost for each operand to the total costs for
1001 for (i = 0; i < noperands; i++)
1002 if (GET_CODE (recog_operand[i]) == REG
1003 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
1005 int regno = REGNO (recog_operand[i]);
1006 struct costs *p = &costs[regno], *q = &op_costs[i];
1008 p->mem_cost += q->mem_cost * loop_cost;
1009 for (j = 0; j < N_REG_CLASSES; j++)
1010 p->cost[j] += q->cost[j] * loop_cost;
1015 /* Now for each register look at how desirable each class is
1016 and find which class is preferred. Store that in
1017 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
1018 class any of whose registers is better than memory. */
1022 prefclass = prefclass_buffer;
1023 altclass = altclass_buffer;
1026 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1028 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1029 enum reg_class best = ALL_REGS, alt = NO_REGS;
1030 /* This is an enum reg_class, but we call it an int
1031 to save lots of casts. */
1033 register struct costs *p = &costs[i];
1035 for (class = (int) ALL_REGS - 1; class > 0; class--)
1037 /* Ignore classes that are too small for this operand or
1038 invalid for a operand that was auto-incremented. */
1039 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1040 > reg_class_size[class]
1041 #ifdef FORBIDDEN_INC_DEC_CLASSES
1042 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1046 else if (p->cost[class] < best_cost)
1048 best_cost = p->cost[class];
1049 best = (enum reg_class) class;
1051 else if (p->cost[class] == best_cost)
1052 best = reg_class_subunion[(int)best][class];
1055 /* Record the alternate register class; i.e., a class for which
1056 every register in it is better than using memory. If adding a
1057 class would make a smaller class (i.e., no union of just those
1058 classes exists), skip that class. The major unions of classes
1059 should be provided as a register class. Don't do this if we
1060 will be doing it again later. */
1062 if (pass == 1 || ! flag_expensive_optimizations)
1063 for (class = 0; class < N_REG_CLASSES; class++)
1064 if (p->cost[class] < p->mem_cost
1065 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1066 > reg_class_size[(int) alt])
1067 #ifdef FORBIDDEN_INC_DEC_CLASSES
1068 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1071 alt = reg_class_subunion[(int) alt][class];
1073 /* If we don't add any classes, nothing to try. */
1077 /* We cast to (int) because (char) hits bugs in some compilers. */
1078 prefclass[i] = (int) best;
1079 altclass[i] = (int) alt;
1082 #endif /* REGISTER_CONSTRAINTS */
1087 #ifdef REGISTER_CONSTRAINTS
1089 /* Record the cost of using memory or registers of various classes for
1090 the operands in INSN.
1092 N_ALTS is the number of alternatives.
1094 N_OPS is the number of operands.
1096 OPS is an array of the operands.
1098 MODES are the modes of the operands, in case any are VOIDmode.
1100 CONSTRAINTS are the constraints to use for the operands. This array
1101 is modified by this procedure.
1103 This procedure works alternative by alternative. For each alternative
1104 we assume that we will be able to allocate all pseudos to their ideal
1105 register class and calculate the cost of using that alternative. Then
1106 we compute for each operand that is a pseudo-register, the cost of
1107 having the pseudo allocated to each register class and using it in that
1108 alternative. To this cost is added the cost of the alternative.
1110 The cost of each class for this insn is its lowest cost among all the
1114 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
1118 enum machine_mode *modes;
1123 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS];
1127 /* By default, each operand is an input operand. */
1129 for (i = 0; i < n_ops; i++)
1130 op_types[i] = OP_READ;
1132 /* Process each alternative, each time minimizing an operand's cost with
1133 the cost for each operand in that alternative. */
1135 for (alt = 0; alt < n_alts; alt++)
1137 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1140 enum reg_class classes[MAX_RECOG_OPERANDS];
1143 for (i = 0; i < n_ops; i++)
1145 char *p = constraints[i];
1147 enum machine_mode mode = modes[i];
1152 /* If this operand has no constraints at all, we can conclude
1153 nothing about it since anything is valid. */
1157 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1158 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1166 /* If this alternative is only relevant when this operand
1167 matches a previous operand, we do different things depending
1168 on whether this operand is a pseudo-reg or not. */
1170 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1173 classes[i] = classes[j];
1175 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1177 /* If this matches the other operand, we have no added
1179 if (rtx_equal_p (ops[j], op))
1182 /* If we can put the other operand into a register, add to
1183 the cost of this alternative the cost to copy this
1184 operand to the register used for the other operand. */
1186 else if (classes[j] != NO_REGS)
1187 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1189 else if (GET_CODE (ops[j]) != REG
1190 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1192 /* This op is a pseudo but the one it matches is not. */
1194 /* If we can't put the other operand into a register, this
1195 alternative can't be used. */
1197 if (classes[j] == NO_REGS)
1200 /* Otherwise, add to the cost of this alternative the cost
1201 to copy the other operand to the register used for this
1205 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1209 /* The costs of this operand are the same as that of the
1210 other operand. However, if we cannot tie them, this
1211 alternative needs to do a copy, which is one
1214 this_op_costs[i] = this_op_costs[j];
1215 if (REGNO (ops[i]) != REGNO (ops[j])
1216 && ! find_reg_note (insn, REG_DEAD, op))
1219 /* This is in place of ordinary cost computation
1220 for this operand, so skip to the end of the
1221 alternative (should be just one character). */
1222 while (*p && *p++ != ',')
1230 /* Scan all the constraint letters. See if the operand matches
1231 any of the constraints. Collect the valid register classes
1232 and see if this operand accepts memory. */
1234 classes[i] = NO_REGS;
1235 while (*p && (c = *p++) != ',')
1239 op_types[i] = OP_WRITE;
1243 op_types[i] = OP_READ_WRITE;
1247 /* Ignore the next letter for this pass. */
1256 case '0': case '1': case '2': case '3': case '4':
1260 case 'm': case 'o': case 'V':
1261 /* It doesn't seem worth distinguishing between offsettable
1262 and non-offsettable addresses here. */
1264 if (GET_CODE (op) == MEM)
1269 if (GET_CODE (op) == MEM
1270 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1271 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1276 if (GET_CODE (op) == MEM
1277 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1278 || GET_CODE (XEXP (op, 0)) == POST_INC))
1283 #ifndef REAL_ARITHMETIC
1284 /* Match any floating double constant, but only if
1285 we can examine the bits of it reliably. */
1286 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1287 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1288 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1291 if (GET_CODE (op) == CONST_DOUBLE)
1296 if (GET_CODE (op) == CONST_DOUBLE)
1302 if (GET_CODE (op) == CONST_DOUBLE
1303 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1308 if (GET_CODE (op) == CONST_INT
1309 || (GET_CODE (op) == CONST_DOUBLE
1310 && GET_MODE (op) == VOIDmode))
1314 #ifdef LEGITIMATE_PIC_OPERAND_P
1315 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1322 if (GET_CODE (op) == CONST_INT
1323 || (GET_CODE (op) == CONST_DOUBLE
1324 && GET_MODE (op) == VOIDmode))
1336 if (GET_CODE (op) == CONST_INT
1337 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1345 #ifdef EXTRA_CONSTRAINT
1351 if (EXTRA_CONSTRAINT (op, c))
1357 if (GET_CODE (op) == MEM
1359 #ifdef LEGITIMATE_PIC_OPERAND_P
1360 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1367 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1372 = reg_class_subunion[(int) classes[i]]
1373 [(int) REG_CLASS_FROM_LETTER (c)];
1378 /* How we account for this operand now depends on whether it is a
1379 pseudo register or not. If it is, we first check if any
1380 register classes are valid. If not, we ignore this alternative,
1381 since we want to assume that all pseudos get allocated for
1382 register preferencing. If some register class is valid, compute
1383 the costs of moving the pseudo into that class. */
1385 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1387 if (classes[i] == NO_REGS)
1391 struct costs *pp = &this_op_costs[i];
1393 for (class = 0; class < N_REG_CLASSES; class++)
1394 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1396 /* If the alternative actually allows memory, make things
1397 a bit cheaper since we won't need an extra insn to
1400 pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1)
1403 /* If we have assigned a class to this register in our
1404 first pass, add a cost to this alternative corresponding
1405 to what we would add if this register were not in the
1406 appropriate class. */
1410 += may_move_cost[(unsigned char)prefclass[REGNO (op)]][(int) classes[i]];
1414 /* Otherwise, if this alternative wins, either because we
1415 have already determined that or if we have a hard register of
1416 the proper class, there is no cost for this alternative. */
1419 || (GET_CODE (op) == REG
1420 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1423 /* If registers are valid, the cost of this alternative includes
1424 copying the object to and/or from a register. */
1426 else if (classes[i] != NO_REGS)
1428 if (op_types[i] != OP_WRITE)
1429 alt_cost += copy_cost (op, mode, classes[i], 1);
1431 if (op_types[i] != OP_READ)
1432 alt_cost += copy_cost (op, mode, classes[i], 0);
1435 /* The only other way this alternative can be used is if this is a
1436 constant that could be placed into memory. */
1438 else if (CONSTANT_P (op) && allows_mem)
1439 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1447 /* Finally, update the costs with the information we've calculated
1448 about this alternative. */
1450 for (i = 0; i < n_ops; i++)
1451 if (GET_CODE (ops[i]) == REG
1452 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1454 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1455 int scale = 1 + (op_types[i] == OP_READ_WRITE);
1457 pp->mem_cost = MIN (pp->mem_cost,
1458 (qq->mem_cost + alt_cost) * scale);
1460 for (class = 0; class < N_REG_CLASSES; class++)
1461 pp->cost[class] = MIN (pp->cost[class],
1462 (qq->cost[class] + alt_cost) * scale);
1466 /* If this insn is a single set copying operand 1 to operand 0
1467 and one is a pseudo with the other a hard reg that is in its
1468 own register class, set the cost of that register class to -1. */
1470 if ((set = single_set (insn)) != 0
1471 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1472 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1473 for (i = 0; i <= 1; i++)
1474 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1476 int regno = REGNO (ops[!i]);
1477 enum machine_mode mode = GET_MODE (ops[!i]);
1481 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1482 && (reg_class_size[(unsigned char)prefclass[regno]]
1483 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1484 op_costs[i].cost[(unsigned char)prefclass[regno]] = -1;
1485 else if (regno < FIRST_PSEUDO_REGISTER)
1486 for (class = 0; class < N_REG_CLASSES; class++)
1487 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1488 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1490 if (reg_class_size[class] == 1)
1491 op_costs[i].cost[class] = -1;
1494 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1496 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1500 if (nr == HARD_REGNO_NREGS(regno,mode))
1501 op_costs[i].cost[class] = -1;
1507 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1508 TO_P is zero) a register of class CLASS in mode MODE.
1510 X must not be a pseudo. */
1513 copy_cost (x, mode, class, to_p)
1515 enum machine_mode mode;
1516 enum reg_class class;
1519 #ifdef HAVE_SECONDARY_RELOADS
1520 enum reg_class secondary_class = NO_REGS;
1523 /* If X is a SCRATCH, there is actually nothing to move since we are
1524 assuming optimal allocation. */
1526 if (GET_CODE (x) == SCRATCH)
1529 /* Get the class we will actually use for a reload. */
1530 class = PREFERRED_RELOAD_CLASS (x, class);
1532 #ifdef HAVE_SECONDARY_RELOADS
1533 /* If we need a secondary reload (we assume here that we are using
1534 the secondary reload as an intermediate, not a scratch register), the
1535 cost is that to load the input into the intermediate register, then
1536 to copy them. We use a special value of TO_P to avoid recursion. */
1538 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1540 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1543 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1545 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1548 if (secondary_class != NO_REGS)
1549 return (move_cost[(int) secondary_class][(int) class]
1550 + copy_cost (x, mode, secondary_class, 2));
1551 #endif /* HAVE_SECONDARY_RELOADS */
1553 /* For memory, use the memory move cost, for (hard) registers, use the
1554 cost to move between the register classes, and use 2 for everything
1555 else (constants). */
1557 if (GET_CODE (x) == MEM || class == NO_REGS)
1558 return MEMORY_MOVE_COST (mode, class, to_p);
1560 else if (GET_CODE (x) == REG)
1561 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1564 /* If this is a constant, we may eventually want to call rtx_cost here. */
1568 /* Record the pseudo registers we must reload into hard registers
1569 in a subexpression of a memory address, X.
1571 CLASS is the class that the register needs to be in and is either
1572 BASE_REG_CLASS or INDEX_REG_CLASS.
1574 SCALE is twice the amount to multiply the cost by (it is twice so we
1575 can represent half-cost adjustments). */
1578 record_address_regs (x, class, scale)
1580 enum reg_class class;
1583 register enum rtx_code code = GET_CODE (x);
1596 /* When we have an address that is a sum,
1597 we must determine whether registers are "base" or "index" regs.
1598 If there is a sum of two registers, we must choose one to be
1599 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1600 to make a good choice most of the time. We only need to do this
1601 on machines that can have two registers in an address and where
1602 the base and index register classes are different.
1604 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1605 that seems bogus since it should only be set when we are sure
1606 the register is being used as a pointer. */
1609 rtx arg0 = XEXP (x, 0);
1610 rtx arg1 = XEXP (x, 1);
1611 register enum rtx_code code0 = GET_CODE (arg0);
1612 register enum rtx_code code1 = GET_CODE (arg1);
1614 /* Look inside subregs. */
1615 if (code0 == SUBREG)
1616 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1617 if (code1 == SUBREG)
1618 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1620 /* If this machine only allows one register per address, it must
1621 be in the first operand. */
1623 if (MAX_REGS_PER_ADDRESS == 1)
1624 record_address_regs (arg0, class, scale);
1626 /* If index and base registers are the same on this machine, just
1627 record registers in any non-constant operands. We assume here,
1628 as well as in the tests below, that all addresses are in
1631 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1633 record_address_regs (arg0, class, scale);
1634 if (! CONSTANT_P (arg1))
1635 record_address_regs (arg1, class, scale);
1638 /* If the second operand is a constant integer, it doesn't change
1639 what class the first operand must be. */
1641 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1642 record_address_regs (arg0, class, scale);
1644 /* If the second operand is a symbolic constant, the first operand
1645 must be an index register. */
1647 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1648 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1650 /* If both operands are registers but one is already a hard register
1651 of index or base class, give the other the class that the hard
1654 #ifdef REG_OK_FOR_BASE_P
1655 else if (code0 == REG && code1 == REG
1656 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1657 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1658 record_address_regs (arg1,
1659 REG_OK_FOR_BASE_P (arg0)
1660 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1662 else if (code0 == REG && code1 == REG
1663 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1664 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1665 record_address_regs (arg0,
1666 REG_OK_FOR_BASE_P (arg1)
1667 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1671 /* If one operand is known to be a pointer, it must be the base
1672 with the other operand the index. Likewise if the other operand
1675 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1678 record_address_regs (arg0, BASE_REG_CLASS, scale);
1679 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1681 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1684 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1685 record_address_regs (arg1, BASE_REG_CLASS, scale);
1688 /* Otherwise, count equal chances that each might be a base
1689 or index register. This case should be rare. */
1693 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1694 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1695 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1696 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1705 /* Double the importance of a pseudo register that is incremented
1706 or decremented, since it would take two extra insns
1707 if it ends up in the wrong place. If the operand is a pseudo,
1708 show it is being used in an INC_DEC context. */
1710 #ifdef FORBIDDEN_INC_DEC_CLASSES
1711 if (GET_CODE (XEXP (x, 0)) == REG
1712 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1713 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1716 record_address_regs (XEXP (x, 0), class, 2 * scale);
1721 register struct costs *pp = &costs[REGNO (x)];
1724 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1726 for (i = 0; i < N_REG_CLASSES; i++)
1727 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1733 register char *fmt = GET_RTX_FORMAT (code);
1735 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1737 record_address_regs (XEXP (x, i), class, scale);
1742 #ifdef FORBIDDEN_INC_DEC_CLASSES
1744 /* Return 1 if REG is valid as an auto-increment memory reference
1745 to an object of MODE. */
1748 auto_inc_dec_reg_p (reg, mode)
1750 enum machine_mode mode;
1752 #ifdef HAVE_POST_INCREMENT
1753 if (memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1757 #ifdef HAVE_POST_DECREMENT
1758 if (memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1762 #ifdef HAVE_PRE_INCREMENT
1763 if (memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1767 #ifdef HAVE_PRE_DECREMENT
1768 if (memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1776 #endif /* REGISTER_CONSTRAINTS */
1778 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1779 reg_scan and flow_analysis that are indexed by the register number. If
1780 NEW_P is non zero, initialize all of the registers, otherwise only
1781 initialize the new registers allocated. The same table is kept from
1782 function to function, only reallocating it when we need more room. If
1783 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1786 allocate_reg_info (num_regs, new_p, renumber_p)
1791 static size_t regno_allocated = 0;
1792 static short *renumber = (short *)0;
1795 size_t size_renumber;
1796 size_t min = (new_p) ? 0 : reg_n_max;
1797 struct reg_info_data *reg_data;
1798 struct reg_info_data *reg_next;
1800 /* Free up all storage allocated */
1805 VARRAY_FREE (reg_n_info);
1806 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1808 reg_next = reg_data->next;
1809 free ((char *)reg_data);
1812 free (prefclass_buffer);
1813 free (altclass_buffer);
1814 prefclass_buffer = (char *)0;
1815 altclass_buffer = (char *)0;
1816 reg_info_head = (struct reg_info_data *)0;
1817 renumber = (short *)0;
1819 regno_allocated = 0;
1824 if (num_regs > regno_allocated)
1826 size_t old_allocated = regno_allocated;
1828 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1829 size_renumber = regno_allocated * sizeof (short);
1833 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
1834 renumber = (short *) xmalloc (size_renumber);
1835 prefclass_buffer = (char *) xmalloc (regno_allocated);
1836 altclass_buffer = (char *) xmalloc (regno_allocated);
1841 VARRAY_GROW (reg_n_info, regno_allocated);
1843 if (new_p) /* if we're zapping everything, no need to realloc */
1845 free ((char *)renumber);
1846 free ((char *)prefclass_buffer);
1847 free ((char *)altclass_buffer);
1848 renumber = (short *) xmalloc (size_renumber);
1849 prefclass_buffer = (char *) xmalloc (regno_allocated);
1850 altclass_buffer = (char *) xmalloc (regno_allocated);
1855 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1856 prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer,
1859 altclass_buffer = (char *) xrealloc ((char *)altclass_buffer,
1864 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
1865 + sizeof (struct reg_info_data) - sizeof (reg_info);
1866 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
1867 reg_data->min_index = old_allocated;
1868 reg_data->max_index = regno_allocated - 1;
1869 reg_data->next = reg_info_head;
1870 reg_info_head = reg_data;
1873 reg_n_max = num_regs;
1876 /* Loop through each of the segments allocated for the actual
1877 reg_info pages, and set up the pointers, zero the pages, etc. */
1878 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1880 size_t min_index = reg_data->min_index;
1881 size_t max_index = reg_data->max_index;
1883 reg_next = reg_data->next;
1884 if (min <= max_index)
1886 size_t max = max_index;
1887 size_t local_min = min - min_index;
1888 if (min < min_index)
1890 if (!reg_data->used_p) /* page just allocated with calloc */
1891 reg_data->used_p = 1; /* no need to zero */
1893 bzero ((char *) ®_data->data[local_min],
1894 sizeof (reg_info) * (max - min_index - local_min + 1));
1896 for (i = min_index+local_min; i <= max; i++)
1898 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
1899 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
1901 prefclass_buffer[i] = (char) NO_REGS;
1902 altclass_buffer[i] = (char) NO_REGS;
1908 /* If {pref,alt}class have already been allocated, update the pointers to
1909 the newly realloced ones. */
1912 prefclass = prefclass_buffer;
1913 altclass = altclass_buffer;
1917 reg_renumber = renumber;
1919 /* Tell the regset code about the new number of registers */
1920 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
1924 /* This is the `regscan' pass of the compiler, run just before cse
1925 and again just before loop.
1927 It finds the first and last use of each pseudo-register
1928 and records them in the vectors regno_first_uid, regno_last_uid
1929 and counts the number of sets in the vector reg_n_sets.
1931 REPEAT is nonzero the second time this is called. */
1933 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1934 Always at least 3, since the combiner could put that many together
1935 and we want this to remain correct for all the remaining passes. */
1940 reg_scan (f, nregs, repeat)
1947 allocate_reg_info (nregs, TRUE, FALSE);
1950 for (insn = f; insn; insn = NEXT_INSN (insn))
1951 if (GET_CODE (insn) == INSN
1952 || GET_CODE (insn) == CALL_INSN
1953 || GET_CODE (insn) == JUMP_INSN)
1955 if (GET_CODE (PATTERN (insn)) == PARALLEL
1956 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1957 max_parallel = XVECLEN (PATTERN (insn), 0);
1958 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
1960 if (REG_NOTES (insn))
1961 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
1965 /* Update 'regscan' information by looking at the insns
1966 from FIRST to LAST. Some new REGs have been created,
1967 and any REG with number greater than OLD_MAX_REGNO is
1968 such a REG. We only update information for those. */
1971 reg_scan_update(first, last, old_max_regno)
1978 allocate_reg_info (max_reg_num (), FALSE, FALSE);
1980 for (insn = first; insn != last; insn = NEXT_INSN (insn))
1981 if (GET_CODE (insn) == INSN
1982 || GET_CODE (insn) == CALL_INSN
1983 || GET_CODE (insn) == JUMP_INSN)
1985 if (GET_CODE (PATTERN (insn)) == PARALLEL
1986 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1987 max_parallel = XVECLEN (PATTERN (insn), 0);
1988 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
1990 if (REG_NOTES (insn))
1991 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
1995 /* X is the expression to scan. INSN is the insn it appears in.
1996 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
1997 We should only record information for REGs with numbers
1998 greater than or equal to MIN_REGNO. */
2001 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2007 register enum rtx_code code;
2011 code = GET_CODE (x);
2027 register int regno = REGNO (x);
2029 if (regno >= min_regno)
2031 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2033 REGNO_LAST_UID (regno) = INSN_UID (insn);
2034 if (REGNO_FIRST_UID (regno) == 0)
2035 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2042 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2044 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2049 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2053 /* Count a set of the destination if it is a register. */
2054 for (dest = SET_DEST (x);
2055 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2056 || GET_CODE (dest) == ZERO_EXTEND;
2057 dest = XEXP (dest, 0))
2060 if (GET_CODE (dest) == REG
2061 && REGNO (dest) >= min_regno)
2062 REG_N_SETS (REGNO (dest))++;
2064 /* If this is setting a pseudo from another pseudo or the sum of a
2065 pseudo and a constant integer and the other pseudo is known to be
2066 a pointer, set the destination to be a pointer as well.
2068 Likewise if it is setting the destination from an address or from a
2069 value equivalent to an address or to the sum of an address and
2072 But don't do any of this if the pseudo corresponds to a user
2073 variable since it should have already been set as a pointer based
2076 if (GET_CODE (SET_DEST (x)) == REG
2077 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2078 && REGNO (SET_DEST (x)) >= min_regno
2079 /* If the destination pseudo is set more than once, then other
2080 sets might not be to a pointer value (consider access to a
2081 union in two threads of control in the presense of global
2082 optimizations). So only set REGNO_POINTER_FLAG on the destination
2083 pseudo if this is the only set of that pseudo. */
2084 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2085 && ! REG_USERVAR_P (SET_DEST (x))
2086 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2087 && ((GET_CODE (SET_SRC (x)) == REG
2088 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2089 || ((GET_CODE (SET_SRC (x)) == PLUS
2090 || GET_CODE (SET_SRC (x)) == LO_SUM)
2091 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2092 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2093 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2094 || GET_CODE (SET_SRC (x)) == CONST
2095 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2096 || GET_CODE (SET_SRC (x)) == LABEL_REF
2097 || (GET_CODE (SET_SRC (x)) == HIGH
2098 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2099 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2100 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2101 || ((GET_CODE (SET_SRC (x)) == PLUS
2102 || GET_CODE (SET_SRC (x)) == LO_SUM)
2103 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2104 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2105 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2106 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2107 && (GET_CODE (XEXP (note, 0)) == CONST
2108 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2109 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2110 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2112 /* ... fall through ... */
2116 register char *fmt = GET_RTX_FORMAT (code);
2118 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2121 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2122 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2125 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2126 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2133 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2137 reg_class_subset_p (c1, c2)
2138 register enum reg_class c1;
2139 register enum reg_class c2;
2141 if (c1 == c2) return 1;
2146 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2147 reg_class_contents[(int)c2],
2152 /* Return nonzero if there is a register that is in both C1 and C2. */
2155 reg_classes_intersect_p (c1, c2)
2156 register enum reg_class c1;
2157 register enum reg_class c2;
2164 if (c1 == c2) return 1;
2166 if (c1 == ALL_REGS || c2 == ALL_REGS)
2169 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2170 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2172 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2179 /* Release any memory allocated by register sets. */
2182 regset_release_memory ()
2184 if (basic_block_live_at_start)
2186 free_regset_vector (basic_block_live_at_start, n_basic_blocks);
2187 basic_block_live_at_start = 0;
2190 FREE_REG_SET (regs_live_at_setjmp);
2191 bitmap_release_memory ();