1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This file contains two passes of the compiler: reg_scan and reg_class.
22 It also defines some tables of information about the hardware registers
23 and a function init_reg_sets to initialize the tables. */
27 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
36 #ifndef REGISTER_MOVE_COST
37 #define REGISTER_MOVE_COST(x, y) 2
40 #ifndef MEMORY_MOVE_COST
41 #define MEMORY_MOVE_COST(x) 4
44 /* If we have auto-increment or auto-decrement and we can have secondary
45 reloads, we are not allowed to use classes requiring secondary
46 reloads for psuedos auto-incremented since reload can't handle it. */
49 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
50 #define FORBIDDEN_INC_DEC_CLASSES
54 /* Register tables used by many passes. */
56 /* Indexed by hard register number, contains 1 for registers
57 that are fixed use (stack pointer, pc, frame pointer, etc.).
58 These are the registers that cannot be used to allocate
59 a pseudo reg whose life does not cross calls. */
61 char fixed_regs[FIRST_PSEUDO_REGISTER];
63 /* Same info as a HARD_REG_SET. */
65 HARD_REG_SET fixed_reg_set;
67 /* Data for initializing the above. */
69 static char initial_fixed_regs[] = FIXED_REGISTERS;
71 /* Indexed by hard register number, contains 1 for registers
72 that are fixed use or are clobbered by function calls.
73 These are the registers that cannot be used to allocate
74 a pseudo reg whose life crosses calls. */
76 char call_used_regs[FIRST_PSEUDO_REGISTER];
78 /* Same info as a HARD_REG_SET. */
80 HARD_REG_SET call_used_reg_set;
82 /* Data for initializing the above. */
84 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
86 /* Indexed by hard register number, contains 1 for registers that are
87 fixed use -- i.e. in fixed_regs -- or a function value return register
88 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
89 registers that cannot hold quantities across calls even if we are
90 willing to save and restore them. */
92 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
94 /* The same info as a HARD_REG_SET. */
96 HARD_REG_SET call_fixed_reg_set;
98 /* Number of non-fixed registers. */
100 int n_non_fixed_regs;
102 /* Indexed by hard register number, contains 1 for registers
103 that are being used for global register decls.
104 These must be exempt from ordinary flow analysis
105 and are also considered fixed. */
107 char global_regs[FIRST_PSEUDO_REGISTER];
109 /* Table of register numbers in the order in which to try to use them. */
110 #ifdef REG_ALLOC_ORDER
111 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
114 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
116 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
118 /* The same information, but as an array of ints. We copy from these
119 ints to the table above. This is done so that the tm.h files do
120 not have to be aware of the wordsize for machines with <= 64 regs. */
123 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
125 static int int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
126 = REG_CLASS_CONTENTS;
128 /* For each reg class, number of regs it contains. */
130 int reg_class_size[N_REG_CLASSES];
132 /* For each reg class, table listing all the containing classes. */
134 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
136 /* For each reg class, table listing all the classes contained in it. */
138 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
140 /* For each pair of reg classes,
141 a largest reg class contained in their union. */
143 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
145 /* For each pair of reg classes,
146 the smallest reg class containing their union. */
148 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
150 /* Array containing all of the register names */
152 char *reg_names[] = REGISTER_NAMES;
154 /* Indexed by n, gives number of times (REG n) is set or clobbered.
155 This information remains valid for the rest of the compilation
156 of the current function; it is used to control register allocation.
158 This information applies to both hard registers and pseudo registers,
159 unlike much of the information above. */
163 /* Maximum cost of moving from a register in one class to a register in
164 another class. Based on REGISTER_MOVE_COST. */
166 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
168 /* Similar, but here we don't have to move if the first index is a subset
169 of the second so in that case the cost is zero. */
171 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
173 #ifdef FORBIDDEN_INC_DEC_CLASSES
175 /* These are the classes that regs which are auto-incremented or decremented
178 static int forbidden_inc_dec_class[N_REG_CLASSES];
180 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
183 static char *in_inc_dec;
185 #endif /* FORBIDDEN_INC_DEC_CLASSES */
187 /* Function called only once to initialize the above data on reg usage.
188 Once this is done, various switches may override. */
195 /* First copy the register information from the initial int form into
198 for (i = 0; i < N_REG_CLASSES; i++)
200 CLEAR_HARD_REG_SET (reg_class_contents[i]);
202 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
203 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
204 & (1 << (j % HOST_BITS_PER_INT)))
205 SET_HARD_REG_BIT (reg_class_contents[i], j);
208 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
209 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
210 bzero (global_regs, sizeof global_regs);
212 /* Compute number of hard regs in each class. */
214 bzero (reg_class_size, sizeof reg_class_size);
215 for (i = 0; i < N_REG_CLASSES; i++)
216 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
217 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
220 /* Initialize the table of subunions.
221 reg_class_subunion[I][J] gets the largest-numbered reg-class
222 that is contained in the union of classes I and J. */
224 for (i = 0; i < N_REG_CLASSES; i++)
226 for (j = 0; j < N_REG_CLASSES; j++)
229 register /* Declare it register if it's a scalar. */
234 COPY_HARD_REG_SET (c, reg_class_contents[i]);
235 IOR_HARD_REG_SET (c, reg_class_contents[j]);
236 for (k = 0; k < N_REG_CLASSES; k++)
238 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
243 /* keep the largest subclass */ /* SPEE 900308 */
244 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
245 reg_class_contents[(int) reg_class_subunion[i][j]],
247 reg_class_subunion[i][j] = (enum reg_class) k;
254 /* Initialize the table of superunions.
255 reg_class_superunion[I][J] gets the smallest-numbered reg-class
256 containing the union of classes I and J. */
258 for (i = 0; i < N_REG_CLASSES; i++)
260 for (j = 0; j < N_REG_CLASSES; j++)
263 register /* Declare it register if it's a scalar. */
268 COPY_HARD_REG_SET (c, reg_class_contents[i]);
269 IOR_HARD_REG_SET (c, reg_class_contents[j]);
270 for (k = 0; k < N_REG_CLASSES; k++)
271 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
274 reg_class_superunion[i][j] = (enum reg_class) k;
278 /* Initialize the tables of subclasses and superclasses of each reg class.
279 First clear the whole table, then add the elements as they are found. */
281 for (i = 0; i < N_REG_CLASSES; i++)
283 for (j = 0; j < N_REG_CLASSES; j++)
285 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
286 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
290 for (i = 0; i < N_REG_CLASSES; i++)
292 if (i == (int) NO_REGS)
295 for (j = i + 1; j < N_REG_CLASSES; j++)
299 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
303 /* Reg class I is a subclass of J.
304 Add J to the table of superclasses of I. */
305 p = ®_class_superclasses[i][0];
306 while (*p != LIM_REG_CLASSES) p++;
307 *p = (enum reg_class) j;
308 /* Add I to the table of superclasses of J. */
309 p = ®_class_subclasses[j][0];
310 while (*p != LIM_REG_CLASSES) p++;
311 *p = (enum reg_class) i;
315 /* Initialize the move cost table. Find every subset of each class
316 and take the maximum cost of moving any subset to any other. */
318 for (i = 0; i < N_REG_CLASSES; i++)
319 for (j = 0; j < N_REG_CLASSES; j++)
321 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
322 enum reg_class *p1, *p2;
324 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
326 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
328 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
331 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
333 for (p2 = ®_class_subclasses[j][0];
334 *p2 != LIM_REG_CLASSES; p2++)
336 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
339 move_cost[i][j] = cost;
341 if (reg_class_subset_p (i, j))
344 may_move_cost[i][j] = cost;
348 /* After switches have been processed, which perhaps alter
349 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
356 /* This macro allows the fixed or call-used registers
357 to depend on target flags. */
359 #ifdef CONDITIONAL_REGISTER_USAGE
360 CONDITIONAL_REGISTER_USAGE;
363 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
366 if (call_used_regs[i] && ! fixed_regs[i])
367 warning ("call-clobbered register used for global register variable");
369 /* Prevent saving/restoring of this reg. */
370 call_used_regs[i] = 1;
373 /* Initialize "constant" tables. */
375 CLEAR_HARD_REG_SET (fixed_reg_set);
376 CLEAR_HARD_REG_SET (call_used_reg_set);
377 CLEAR_HARD_REG_SET (call_fixed_reg_set);
379 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
380 #ifdef STRUCT_VALUE_REGNUM
381 call_fixed_regs[STRUCT_VALUE_REGNUM] = 1;
383 #ifdef STATIC_CHAIN_REGNUM
384 call_fixed_regs[STATIC_CHAIN_REGNUM] = 1;
387 n_non_fixed_regs = 0;
389 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
391 if (FUNCTION_VALUE_REGNO_P (i))
392 call_fixed_regs[i] = 1;
394 SET_HARD_REG_BIT (fixed_reg_set, i);
398 if (call_used_regs[i])
399 SET_HARD_REG_BIT (call_used_reg_set, i);
400 if (call_fixed_regs[i])
401 SET_HARD_REG_BIT (call_fixed_reg_set, i);
405 /* Specify the usage characteristics of the register named NAME.
406 It should be a fixed register if FIXED and a
407 call-used register if CALL_USED. */
410 fix_register (name, fixed, call_used)
412 int fixed, call_used;
416 /* Decode the name and update the primary form of
417 the register info. */
419 if ((i = decode_reg_name (name)) >= 0)
421 fixed_regs[i] = fixed;
422 call_used_regs[i] = call_used;
426 warning ("unknown register name: %s", name);
430 /* Now the data and code for the `regclass' pass, which happens
431 just before local-alloc. */
433 /* The `costs' struct records the cost of using a hard register of each class
434 and of using memory for each pseudo. We use this data to set up
435 register class preferences. */
439 int cost[N_REG_CLASSES];
443 /* Record the cost of each class for each pseudo. */
445 static struct costs *costs;
447 /* Record the same data by operand number, accumulated for each alternative
448 in an insn. The contribution to a pseudo is that of the minimum-cost
451 static struct costs op_costs[MAX_RECOG_OPERANDS];
453 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
454 This is available after `regclass' is run. */
456 static char *prefclass;
458 /* altclass[R] is a register class that we should use for allocating
459 pseudo number R if no register in the preferred class is available.
460 If no register in this class is available, memory is preferred.
462 It might appear to be more general to have a bitmask of classes here,
463 but since it is recommended that there be a class corresponding to the
464 union of most major pair of classes, that generality is not required.
466 This is available after `regclass' is run. */
468 static char *altclass;
470 /* Record the depth of loops that we are in. */
472 static int loop_depth;
474 /* Account for the fact that insns within a loop are executed very commonly,
475 but don't keep doing this as loops go too deep. */
477 static int loop_cost;
479 static int copy_cost ();
480 static void record_reg_classes ();
481 static void record_address_regs ();
484 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
485 This function is sometimes called before the info has been computed.
486 When that happens, just return GENERAL_REGS, which is innocuous. */
489 reg_preferred_class (regno)
494 return (enum reg_class) prefclass[regno];
498 reg_alternate_class (regno)
503 return (enum reg_class) altclass[regno];
506 /* This prevents dump_flow_info from losing if called
507 before regclass is run. */
515 /* This is a pass of the compiler that scans all instructions
516 and calculates the preferred class for each pseudo-register.
517 This information can be accessed later by calling `reg_preferred_class'.
518 This pass comes just before local register allocation. */
525 #ifdef REGISTER_CONSTRAINTS
528 struct costs init_cost;
534 costs = (struct costs *) alloca (nregs * sizeof (struct costs));
536 #ifdef FORBIDDEN_INC_DEC_CLASSES
538 in_inc_dec = (char *) alloca (nregs);
540 /* Initialize information about which register classes can be used for
541 pseudos that are auto-incremented or auto-decremented. It would
542 seem better to put this in init_reg_sets, but we need to be able
543 to allocate rtx, which we can't do that early. */
545 for (i = 0; i < N_REG_CLASSES; i++)
547 rtx r = gen_rtx (REG, VOIDmode, 0);
550 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
551 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
555 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
556 m = (enum machine_mode) ((int) m) + 1)
557 if (HARD_REGNO_MODE_OK (j, m))
561 #ifdef SECONDARY_INPUT_RELOAD_CLASS
562 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
565 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
566 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
570 forbidden_inc_dec_class[i] = 1;
574 #endif /* FORBIDDEN_INC_DEC_CLASSES */
576 init_cost.mem_cost = 10000;
577 for (i = 0; i < N_REG_CLASSES; i++)
578 init_cost.cost[i] = 10000;
580 /* Normally we scan the insns once and determine the best class to use for
581 each register. However, if -fexpensive_optimizations are on, we do so
582 twice, the second time using the tentative best classes to guide the
585 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
587 /* Zero out our accumulation of the cost of each class for each reg. */
589 bzero (costs, nregs * sizeof (struct costs));
591 #ifdef FORBIDDEN_INC_DEC_CLASSES
592 bzero (in_inc_dec, nregs);
595 loop_depth = 0, loop_cost = 1;
597 /* Scan the instructions and record each time it would
598 save code to put a certain register in a certain class. */
600 for (insn = f; insn; insn = NEXT_INSN (insn))
602 char *constraints[MAX_RECOG_OPERANDS];
603 enum machine_mode modes[MAX_RECOG_OPERANDS];
607 /* Show that an insn inside a loop is likely to be executed three
608 times more than insns outside a loop. This is much more aggressive
609 than the assumptions made elsewhere and is being tried as an
612 if (GET_CODE (insn) == NOTE
613 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
614 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
615 else if (GET_CODE (insn) == NOTE
616 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
617 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
619 else if ((GET_CODE (insn) == INSN
620 && GET_CODE (PATTERN (insn)) != USE
621 && GET_CODE (PATTERN (insn)) != CLOBBER
622 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
623 || (GET_CODE (insn) == JUMP_INSN
624 && GET_CODE (PATTERN (insn)) != ADDR_VEC
625 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
626 || GET_CODE (insn) == CALL_INSN)
628 if (GET_CODE (insn) == INSN
629 && (noperands = asm_noperands (PATTERN (insn))) >= 0)
631 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR,
633 nalternatives = (noperands == 0 ? 0
634 : n_occurrences (',', constraints[0]) + 1);
638 int insn_code_number = recog_memoized (insn);
641 set = single_set (insn);
644 nalternatives = insn_n_alternatives[insn_code_number];
645 noperands = insn_n_operands[insn_code_number];
647 /* If this insn loads a parameter from its stack slot, then
648 it represents a savings, rather than a cost, if the
649 parameter is stored in memory. Record this fact. */
651 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
652 && GET_CODE (SET_SRC (set)) == MEM
653 && (note = find_reg_note (insn, REG_EQUIV,
655 && GET_CODE (XEXP (note, 0)) == MEM)
657 costs[REGNO (SET_DEST (set))].mem_cost
658 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)))
660 record_address_regs (XEXP (SET_SRC (set), 0),
661 BASE_REG_CLASS, loop_cost * 2);
665 /* Improve handling of two-address insns such as
666 (set X (ashift CONST Y)) where CONST must be made to
667 match X. Change it into two insns: (set X CONST)
668 (set X (ashift X Y)). If we left this for reloading, it
669 would probably get three insns because X and Y might go
670 in the same place. This prevents X and Y from receiving
673 We can only do this if the modes of operands 0 and 1
674 (which might not be the same) are tieable and we only need
675 do this during our first pass. */
677 if (pass == 0 && optimize
679 && insn_operand_constraint[insn_code_number][1][0] == '0'
680 && insn_operand_constraint[insn_code_number][1][1] == 0
681 && CONSTANT_P (recog_operand[1])
682 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
683 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
684 && GET_CODE (recog_operand[0]) == REG
685 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
686 insn_operand_mode[insn_code_number][1]))
688 rtx previnsn = prev_real_insn (insn);
690 = gen_lowpart (insn_operand_mode[insn_code_number][1],
693 = emit_insn_before (gen_move_insn (dest,
697 /* If this insn was the start of a basic block,
698 include the new insn in that block.
699 We need not check for code_label here;
700 while a basic block can start with a code_label,
701 INSN could not be at the beginning of that block. */
702 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
705 for (b = 0; b < n_basic_blocks; b++)
706 if (insn == basic_block_head[b])
707 basic_block_head[b] = newinsn;
710 /* This makes one more setting of new insns's dest. */
711 reg_n_sets[REGNO (recog_operand[0])]++;
713 *recog_operand_loc[1] = recog_operand[0];
714 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
715 if (recog_dup_num[i] == 1)
716 *recog_dup_loc[i] = recog_operand[0];
718 insn = PREV_INSN (newinsn);
722 /* If this is setting a pseudo from another pseudo or the
723 sum of a pseudo and a constant integer and the other
724 pseudo is known to be a pointer, set the destination to
725 be a pointer as well.
727 Likewise if it is setting the destination from an address
728 or from a value equivalent to an address or to the sum of
729 an address and something else.
731 But don't do any of this if the pseudo corresponds to
732 a user variable since it should have already been set
733 as a pointer based on the type.
735 There is no point in doing this during our second
736 pass since not enough should have changed. */
738 if (pass == 0 && set != 0 && GET_CODE (SET_DEST (set)) == REG
739 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER
740 && ! REG_USERVAR_P (SET_DEST (set))
741 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (set)))
742 && ((GET_CODE (SET_SRC (set)) == REG
743 && REGNO_POINTER_FLAG (REGNO (SET_SRC (set))))
744 || ((GET_CODE (SET_SRC (set)) == PLUS
745 || GET_CODE (SET_SRC (set)) == LO_SUM)
746 && (GET_CODE (XEXP (SET_SRC (set), 1))
748 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
749 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (set), 0))))
750 || GET_CODE (SET_SRC (set)) == CONST
751 || GET_CODE (SET_SRC (set)) == SYMBOL_REF
752 || GET_CODE (SET_SRC (set)) == LABEL_REF
753 || (GET_CODE (SET_SRC (set)) == HIGH
754 && (GET_CODE (XEXP (SET_SRC (set), 0)) == CONST
755 || (GET_CODE (XEXP (SET_SRC (set), 0))
757 || (GET_CODE (XEXP (SET_SRC (set), 0))
759 || ((GET_CODE (SET_SRC (set)) == PLUS
760 || GET_CODE (SET_SRC (set)) == LO_SUM)
761 && (GET_CODE (XEXP (SET_SRC (set), 1)) == CONST
762 || (GET_CODE (XEXP (SET_SRC (set), 1))
764 || (GET_CODE (XEXP (SET_SRC (set), 1))
766 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
767 && (GET_CODE (XEXP (note, 0)) == CONST
768 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
769 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
770 REGNO_POINTER_FLAG (REGNO (SET_DEST (set))) = 1;
772 for (i = 0; i < noperands; i++)
775 = insn_operand_constraint[insn_code_number][i];
776 modes[i] = insn_operand_mode[insn_code_number][i];
780 /* If we get here, we are set up to record the costs of all the
781 operands for this insn. Start by initializing the costs.
782 Then handle any address registers. Finally record the desired
783 classes for any pseudos, doing it twice if some pair of
784 operands are commutative. */
786 for (i = 0; i < noperands; i++)
788 op_costs[i] = init_cost;
790 if (GET_CODE (recog_operand[i]) == SUBREG)
791 recog_operand[i] = SUBREG_REG (recog_operand[i]);
793 if (GET_CODE (recog_operand[i]) == MEM)
794 record_address_regs (XEXP (recog_operand[i], 0),
795 BASE_REG_CLASS, loop_cost * 2);
796 else if (constraints[i][0] == 'p')
797 record_address_regs (recog_operand[i],
798 BASE_REG_CLASS, loop_cost * 2);
801 /* Check for commutative in a separate loop so everything will
802 have been initialized. Don't bother doing anything if the
803 second operand is a constant since that is the case
804 for which the constraints should have been written. */
806 for (i = 0; i < noperands - 1; i++)
807 if (constraints[i][0] == '%'
808 && ! CONSTANT_P (recog_operand[i+1]))
810 char *xconstraints[MAX_RECOG_OPERANDS];
813 /* Handle commutative operands by swapping the constraints.
814 We assume the modes are the same. */
816 for (j = 0; j < noperands; j++)
817 xconstraints[j] = constraints[j];
819 xconstraints[i] = constraints[i+1];
820 xconstraints[i+1] = constraints[i];
821 record_reg_classes (nalternatives, noperands,
822 recog_operand, modes, xconstraints,
826 record_reg_classes (nalternatives, noperands, recog_operand,
827 modes, constraints, insn);
829 /* Now add the cost for each operand to the total costs for
832 for (i = 0; i < noperands; i++)
833 if (GET_CODE (recog_operand[i]) == REG
834 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
836 int regno = REGNO (recog_operand[i]);
837 struct costs *p = &costs[regno], *q = &op_costs[i];
839 p->mem_cost += q->mem_cost * loop_cost;
840 for (j = 0; j < N_REG_CLASSES; j++)
841 p->cost[j] += q->cost[j] * loop_cost;
846 /* Now for each register look at how desirable each class is
847 and find which class is preferred. Store that in
848 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
849 class any of whose registers is better than memory. */
853 prefclass = (char *) oballoc (nregs);
854 altclass = (char *) oballoc (nregs);
857 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
859 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
860 enum reg_class best = ALL_REGS, alt = NO_REGS;
861 /* This is an enum reg_class, but we call it an int
862 to save lots of casts. */
864 register struct costs *p = &costs[i];
866 for (class = (int) ALL_REGS - 1; class > 0; class--)
868 /* Ignore classes that are too small for this operand or
869 invalid for a operand that was auto-incremented. */
870 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
871 > reg_class_size[class]
872 #ifdef FORBIDDEN_INC_DEC_CLASSES
873 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
877 else if (p->cost[class] < best_cost)
879 best_cost = p->cost[class];
880 best = (enum reg_class) class;
882 else if (p->cost[class] == best_cost)
883 best = reg_class_subunion[(int)best][class];
886 /* Record the alternate register class; i.e., a class for which
887 every register in it is better than using memory. If adding a
888 class would make a smaller class (i.e., no union of just those
889 classes exists), skip that class. The major unions of classes
890 should be provided as a register class. Don't do this if we
891 will be doing it again later. */
893 if (pass == 1 || ! flag_expensive_optimizations)
894 for (class = 0; class < N_REG_CLASSES; class++)
895 if (p->cost[class] < p->mem_cost
896 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
897 > reg_class_size[(int) alt])
898 #ifdef FORBIDDEN_INC_DEC_CLASSES
899 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
902 alt = reg_class_subunion[(int) alt][class];
904 /* If we don't add any classes, nothing to try. */
908 /* We cast to (int) because (char) hits bugs in some compilers. */
909 prefclass[i] = (int) best;
910 altclass[i] = (int) alt;
913 #endif /* REGISTER_CONSTRAINTS */
916 #ifdef REGISTER_CONSTRAINTS
918 /* Record the cost of using memory or registers of various classes for
919 the operands in INSN.
921 N_ALTS is the number of alternatives.
923 N_OPS is the number of operands.
925 OPS is an array of the operands.
927 MODES are the modes of the operands, in case any are VOIDmode.
929 CONSTRAINTS are the constraints to use for the operands. This array
930 is modified by this procedure.
932 This procedure works alternative by alternative. For each alternative
933 we assume that we will be able to allocate all pseudos to their ideal
934 register class and calculate the cost of using that alternative. Then
935 we compute for each operand that is a pseudo-register, the cost of
936 having the pseudo allocated to each register class and using it in that
937 alternative. To this cost is added the cost of the alternative.
939 The cost of each class for this insn is its lowest cost among all the
943 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
947 enum machine_mode *modes;
952 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS];
955 /* By default, each operand is an input operand. */
957 for (i = 0; i < n_ops; i++)
958 op_types[i] = OP_READ;
960 /* Process each alternative, each time minimizing an operand's cost with
961 the cost for each operand in that alternative. */
963 for (alt = 0; alt < n_alts; alt++)
965 struct costs this_op_costs[MAX_RECOG_OPERANDS];
968 enum reg_class classes[MAX_RECOG_OPERANDS];
971 for (i = 0; i < n_ops; i++)
973 char *p = constraints[i];
975 enum machine_mode mode = modes[i];
980 /* If this operand has no constraints at all, we can conclude
981 nothing about it since anything is valid. */
985 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
986 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
994 /* If this alternative is only relevant when this operand
995 matches a previous operand, we do different things depending
996 on whether this operand is a pseudo-reg or not. */
998 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1001 classes[i] = classes[j];
1003 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1005 /* If this matches the other operand, we have no added
1007 if (rtx_equal_p (ops[j], op))
1010 /* If we can't put the other operand into a register, this
1011 alternative can't be used. */
1013 else if (classes[j] == NO_REGS)
1016 /* Otherwise, add to the cost of this alternative the cost
1017 to copy this operand to the register used for the other
1021 alt_cost += copy_cost (op, mode, classes[j], 1);
1023 else if (GET_CODE (ops[j]) != REG
1024 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1026 /* This op is a pseudo but the one it matches is not. */
1028 /* If we can't put the other operand into a register, this
1029 alternative can't be used. */
1031 if (classes[j] == NO_REGS)
1034 /* Otherwise, add to the cost of this alternative the cost
1035 to copy the other operand to the register used for this
1039 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1043 /* The costs of this operand are the same as that of the
1044 other operand. However, if we cannot tie them, this
1045 alternative needs to do a copy, which is one
1048 this_op_costs[i] = this_op_costs[j];
1049 if (! find_reg_note (insn, REG_DEAD, op))
1052 /* This is in place of ordinary cost computation
1053 for this operand. */
1058 /* Scan all the constraint letters. See if the operand matches
1059 any of the constraints. Collect the valid register classes
1060 and see if this operand accepts memory. */
1062 classes[i] = NO_REGS;
1063 while (*p && (c = *p++) != ',')
1067 op_types[i] = OP_WRITE;
1071 op_types[i] = OP_READ_WRITE;
1075 /* Ignore the next letter for this pass. */
1080 case '?': case '!': case '#':
1082 case '0': case '1': case '2': case '3': case '4':
1086 case 'm': case 'o': case 'V':
1087 /* It doesn't seem worth distinguishing between offsettable
1088 and non-offsettable addresses here. */
1090 if (GET_CODE (op) == MEM)
1095 if (GET_CODE (op) == MEM
1096 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1097 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1102 if (GET_CODE (op) == MEM
1103 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1104 || GET_CODE (XEXP (op, 0)) == POST_INC))
1109 /* Match any floating double constant, but only if
1110 we can examine the bits of it reliably. */
1111 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1112 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1113 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1115 if (GET_CODE (op) == CONST_DOUBLE)
1120 if (GET_CODE (op) == CONST_DOUBLE)
1126 if (GET_CODE (op) == CONST_DOUBLE
1127 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1132 if (GET_CODE (op) == CONST_INT
1133 || (GET_CODE (op) == CONST_DOUBLE
1134 && GET_MODE (op) == VOIDmode))
1138 #ifdef LEGITIMATE_PIC_OPERAND_P
1139 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1146 if (GET_CODE (op) == CONST_INT
1147 || (GET_CODE (op) == CONST_DOUBLE
1148 && GET_MODE (op) == VOIDmode))
1160 if (GET_CODE (op) == CONST_INT
1161 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1169 #ifdef EXTRA_CONSTRAINT
1175 if (EXTRA_CONSTRAINT (op, c))
1181 if (GET_CODE (op) == MEM
1183 #ifdef LEGITIMATE_PIC_OPERAND_P
1184 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1191 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1196 = reg_class_subunion[(int) classes[i]]
1197 [(int) REG_CLASS_FROM_LETTER (c)];
1202 /* How we account for this operand now depends on whether it is a
1203 pseudo register or not. If it is, we first check if any
1204 register classes are valid. If not, we ignore this alternative,
1205 since we want to assume that all pseudos get allocated for
1206 register preferencing. If some register class is valid, compute
1207 the costs of moving the pseudo into that class. */
1209 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1211 if (classes[i] == NO_REGS)
1215 struct costs *pp = &this_op_costs[i];
1217 for (class = 0; class < N_REG_CLASSES; class++)
1218 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1220 /* If the alternative actually allows memory, make things
1221 a bit cheaper since we won't need an extra insn to
1224 pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem;
1226 /* If we have assigned a class to this register in our
1227 first pass, add a cost to this alternative corresponding
1228 to what we would add if this register were not in the
1229 appropriate class. */
1233 += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]];
1237 /* Otherwise, if this alternative wins, either because we
1238 have already determined that or if we have a hard register of
1239 the proper class, there is no cost for this alternative. */
1242 || (GET_CODE (op) == REG
1243 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1246 /* If registers are valid, the cost of this alternative includes
1247 copying the object to and/or from a register. */
1249 else if (classes[i] != NO_REGS)
1251 if (op_types[i] != OP_WRITE)
1252 alt_cost += copy_cost (op, mode, classes[i], 1);
1254 if (op_types[i] != OP_READ)
1255 alt_cost += copy_cost (op, mode, classes[i], 0);
1258 /* The only other way this alternative can be used is if this is a
1259 constant that could be placed into memory. */
1261 else if (CONSTANT_P (op) && allows_mem)
1262 alt_cost += MEMORY_MOVE_COST (mode);
1270 /* Finally, update the costs with the information we've calculated
1271 about this alternative. */
1273 for (i = 0; i < n_ops; i++)
1274 if (GET_CODE (ops[i]) == REG
1275 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1277 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1278 int scale = 1 + (op_types[i] == OP_READ_WRITE);
1280 pp->mem_cost = MIN (pp->mem_cost,
1281 (qq->mem_cost + alt_cost) * scale);
1283 for (class = 0; class < N_REG_CLASSES; class++)
1284 pp->cost[class] = MIN (pp->cost[class],
1285 (qq->cost[class] + alt_cost) * scale);
1290 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1291 TO_P is zero) a register of class CLASS in mode MODE.
1293 X must not be a pseudo. */
1296 copy_cost (x, mode, class, to_p)
1298 enum machine_mode mode;
1299 enum reg_class class;
1302 enum reg_class secondary_class = NO_REGS;
1304 /* If X is a SCRATCH, there is actually nothing to move since we are
1305 assuming optimal allocation. */
1307 if (GET_CODE (x) == SCRATCH)
1310 /* Get the class we will actually use for a reload. */
1311 class = PREFERRED_RELOAD_CLASS (x, class);
1313 #ifdef HAVE_SECONDARY_RELOADS
1314 /* If we need a secondary reload (we assume here that we are using
1315 the secondary reload as an intermediate, not a scratch register), the
1316 cost is that to load the input into the intermediate register, then
1317 to copy them. We use a special value of TO_P to avoid recursion. */
1319 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1321 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1324 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1326 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1329 if (secondary_class != NO_REGS)
1330 return (move_cost[(int) secondary_class][(int) class]
1331 + copy_cost (x, mode, secondary_class, 2));
1332 #endif /* HAVE_SECONDARY_RELOADS */
1334 /* For memory, use the memory move cost, for (hard) registers, use the
1335 cost to move between the register classes, and use 2 for everything
1336 else (constants). */
1338 if (GET_CODE (x) == MEM || class == NO_REGS)
1339 return MEMORY_MOVE_COST (mode);
1341 else if (GET_CODE (x) == REG)
1342 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1345 /* If this is a constant, we may eventually want to call rtx_cost here. */
1349 /* Record the pseudo registers we must reload into hard registers
1350 in a subexpression of a memory address, X.
1352 CLASS is the class that the register needs to be in and is either
1353 BASE_REG_CLASS or INDEX_REG_CLASS.
1355 SCALE is twice the amount to multiply the cost by (it is twice so we
1356 can represent half-cost adjustments). */
1359 record_address_regs (x, class, scale)
1361 enum reg_class class;
1364 register enum rtx_code code = GET_CODE (x);
1377 /* When we have an address that is a sum,
1378 we must determine whether registers are "base" or "index" regs.
1379 If there is a sum of two registers, we must choose one to be
1380 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1381 to make a good choice most of the time. We only need to do this
1382 on machines that can have two registers in an address and where
1383 the base and index register classes are different.
1385 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1386 that seems bogus since it should only be set when we are sure
1387 the register is being used as a pointer. */
1390 rtx arg0 = XEXP (x, 0);
1391 rtx arg1 = XEXP (x, 1);
1392 register enum rtx_code code0 = GET_CODE (arg0);
1393 register enum rtx_code code1 = GET_CODE (arg1);
1395 /* Look inside subregs. */
1396 if (code0 == SUBREG)
1397 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1398 if (code1 == SUBREG)
1399 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1401 /* If this machine only allows one register per address, it must
1402 be in the first operand. */
1404 if (MAX_REGS_PER_ADDRESS == 1)
1405 record_address_regs (arg0, class, scale);
1407 /* If index and base registers are the same on this machine, just
1408 record registers in any non-constant operands. We assume here,
1409 as well as in the tests below, that all addresses are in
1412 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1414 record_address_regs (arg0, class, scale);
1415 if (! CONSTANT_P (arg1))
1416 record_address_regs (arg1, class, scale);
1419 /* If the second operand is a constant integer, it doesn't change
1420 what class the first operand must be. */
1422 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1423 record_address_regs (arg0, class, scale);
1425 /* If the second operand is a symbolic constant, the first operand
1426 must be an index register. */
1428 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1429 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1431 /* If this the sum of two registers where the first is known to be a
1432 pointer, it must be a base register with the second an index. */
1434 else if (code0 == REG && code1 == REG
1435 && REGNO_POINTER_FLAG (REGNO (arg0)))
1437 record_address_regs (arg0, BASE_REG_CLASS, scale);
1438 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1441 /* If this is the sum of two registers and neither is known to
1442 be a pointer, count equal chances that each might be a base
1443 or index register. This case should be rare. */
1445 else if (code0 == REG && code1 == REG
1446 && ! REGNO_POINTER_FLAG (REGNO (arg0))
1447 && ! REGNO_POINTER_FLAG (REGNO (arg1)))
1449 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1450 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1451 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1452 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1455 /* In all other cases, the first operand is an index and the
1456 second is the base. */
1460 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1461 record_address_regs (arg1, BASE_REG_CLASS, scale);
1470 /* Double the importance of a pseudo register that is incremented
1471 or decremented, since it would take two extra insns
1472 if it ends up in the wrong place. If the operand is a pseudo,
1473 show it is being used in an INC_DEC context. */
1475 #ifdef FORBIDDEN_INC_DEC_CLASSES
1476 if (GET_CODE (XEXP (x, 0)) == REG
1477 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1478 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1481 record_address_regs (XEXP (x, 0), class, 2 * scale);
1486 register struct costs *pp = &costs[REGNO (x)];
1489 pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2;
1491 for (i = 0; i < N_REG_CLASSES; i++)
1492 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1498 register char *fmt = GET_RTX_FORMAT (code);
1500 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1502 record_address_regs (XEXP (x, i), class, scale);
1506 #endif /* REGISTER_CONSTRAINTS */
1508 /* This is the `regscan' pass of the compiler, run just before cse
1509 and again just before loop.
1511 It finds the first and last use of each pseudo-register
1512 and records them in the vectors regno_first_uid, regno_last_uid
1513 and counts the number of sets in the vector reg_n_sets.
1515 REPEAT is nonzero the second time this is called. */
1517 /* Indexed by pseudo register number, gives uid of first insn using the reg
1518 (as of the time reg_scan is called). */
1520 int *regno_first_uid;
1522 /* Indexed by pseudo register number, gives uid of last insn using the reg
1523 (as of the time reg_scan is called). */
1525 int *regno_last_uid;
1527 /* Record the number of registers we used when we allocated the above two
1528 tables. If we are called again with more than this, we must re-allocate
1531 static int highest_regno_in_uid_map;
1533 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1534 Always at least 3, since the combiner could put that many togetherm
1535 and we want this to remain correct for all the remaining passes. */
1539 void reg_scan_mark_refs ();
1542 reg_scan (f, nregs, repeat)
1549 if (!repeat || nregs > highest_regno_in_uid_map)
1551 /* Leave some spare space in case more regs are allocated. */
1552 highest_regno_in_uid_map = nregs + nregs / 20;
1554 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1556 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1558 = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1561 bzero (regno_first_uid, highest_regno_in_uid_map * sizeof (int));
1562 bzero (regno_last_uid, highest_regno_in_uid_map * sizeof (int));
1563 bzero (reg_n_sets, highest_regno_in_uid_map * sizeof (short));
1567 for (insn = f; insn; insn = NEXT_INSN (insn))
1568 if (GET_CODE (insn) == INSN
1569 || GET_CODE (insn) == CALL_INSN
1570 || GET_CODE (insn) == JUMP_INSN)
1572 if (GET_CODE (PATTERN (insn)) == PARALLEL
1573 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1574 max_parallel = XVECLEN (PATTERN (insn), 0);
1575 reg_scan_mark_refs (PATTERN (insn), INSN_UID (insn));
1580 reg_scan_mark_refs (x, uid)
1584 register enum rtx_code code = GET_CODE (x);
1602 register int regno = REGNO (x);
1604 regno_last_uid[regno] = uid;
1605 if (regno_first_uid[regno] == 0)
1606 regno_first_uid[regno] = uid;
1611 /* Count a set of the destination if it is a register. */
1612 for (dest = SET_DEST (x);
1613 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
1614 || GET_CODE (dest) == ZERO_EXTEND;
1615 dest = XEXP (dest, 0))
1618 if (GET_CODE (dest) == REG)
1619 reg_n_sets[REGNO (dest)]++;
1621 /* ... fall through ... */
1625 register char *fmt = GET_RTX_FORMAT (code);
1627 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1630 reg_scan_mark_refs (XEXP (x, i), uid);
1631 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
1634 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1635 reg_scan_mark_refs (XVECEXP (x, i, j), uid);
1642 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1646 reg_class_subset_p (c1, c2)
1647 register enum reg_class c1;
1648 register enum reg_class c2;
1650 if (c1 == c2) return 1;
1655 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
1656 reg_class_contents[(int)c2],
1661 /* Return nonzero if there is a register that is in both C1 and C2. */
1664 reg_classes_intersect_p (c1, c2)
1665 register enum reg_class c1;
1666 register enum reg_class c2;
1673 if (c1 == c2) return 1;
1675 if (c1 == ALL_REGS || c2 == ALL_REGS)
1678 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1679 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1681 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);