1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91, 92, 93, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This file contains two passes of the compiler: reg_scan and reg_class.
22 It also defines some tables of information about the hardware registers
23 and a function init_reg_sets to initialize the tables. */
27 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
37 #ifndef REGISTER_MOVE_COST
38 #define REGISTER_MOVE_COST(x, y) 2
41 #ifndef MEMORY_MOVE_COST
42 #define MEMORY_MOVE_COST(x) 4
45 /* If we have auto-increment or auto-decrement and we can have secondary
46 reloads, we are not allowed to use classes requiring secondary
47 reloads for psuedos auto-incremented since reload can't handle it. */
50 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
51 #define FORBIDDEN_INC_DEC_CLASSES
55 /* Register tables used by many passes. */
57 /* Indexed by hard register number, contains 1 for registers
58 that are fixed use (stack pointer, pc, frame pointer, etc.).
59 These are the registers that cannot be used to allocate
60 a pseudo reg whose life does not cross calls. */
62 char fixed_regs[FIRST_PSEUDO_REGISTER];
64 /* Same info as a HARD_REG_SET. */
66 HARD_REG_SET fixed_reg_set;
68 /* Data for initializing the above. */
70 static char initial_fixed_regs[] = FIXED_REGISTERS;
72 /* Indexed by hard register number, contains 1 for registers
73 that are fixed use or are clobbered by function calls.
74 These are the registers that cannot be used to allocate
75 a pseudo reg whose life crosses calls. */
77 char call_used_regs[FIRST_PSEUDO_REGISTER];
79 /* Same info as a HARD_REG_SET. */
81 HARD_REG_SET call_used_reg_set;
83 /* Data for initializing the above. */
85 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
87 /* Indexed by hard register number, contains 1 for registers that are
88 fixed use -- i.e. in fixed_regs -- or a function value return register
89 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
90 registers that cannot hold quantities across calls even if we are
91 willing to save and restore them. */
93 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
95 /* The same info as a HARD_REG_SET. */
97 HARD_REG_SET call_fixed_reg_set;
99 /* Number of non-fixed registers. */
101 int n_non_fixed_regs;
103 /* Indexed by hard register number, contains 1 for registers
104 that are being used for global register decls.
105 These must be exempt from ordinary flow analysis
106 and are also considered fixed. */
108 char global_regs[FIRST_PSEUDO_REGISTER];
110 /* Table of register numbers in the order in which to try to use them. */
111 #ifdef REG_ALLOC_ORDER
112 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
115 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
117 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
119 /* The same information, but as an array of unsigned ints. We copy from
120 these unsigned ints to the table above. We do this so the tm.h files
121 do not have to be aware of the wordsize for machines with <= 64 regs. */
124 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
126 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
127 = REG_CLASS_CONTENTS;
129 /* For each reg class, number of regs it contains. */
131 int reg_class_size[N_REG_CLASSES];
133 /* For each reg class, table listing all the containing classes. */
135 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
137 /* For each reg class, table listing all the classes contained in it. */
139 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
141 /* For each pair of reg classes,
142 a largest reg class contained in their union. */
144 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
146 /* For each pair of reg classes,
147 the smallest reg class containing their union. */
149 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
151 /* Array containing all of the register names */
153 char *reg_names[] = REGISTER_NAMES;
155 /* Indexed by n, gives number of times (REG n) is set or clobbered.
156 This information remains valid for the rest of the compilation
157 of the current function; it is used to control register allocation.
159 This information applies to both hard registers and pseudo registers,
160 unlike much of the information above. */
164 /* Maximum cost of moving from a register in one class to a register in
165 another class. Based on REGISTER_MOVE_COST. */
167 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
169 /* Similar, but here we don't have to move if the first index is a subset
170 of the second so in that case the cost is zero. */
172 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
174 #ifdef FORBIDDEN_INC_DEC_CLASSES
176 /* These are the classes that regs which are auto-incremented or decremented
179 static int forbidden_inc_dec_class[N_REG_CLASSES];
181 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
184 static char *in_inc_dec;
186 #endif /* FORBIDDEN_INC_DEC_CLASSES */
188 /* Function called only once to initialize the above data on reg usage.
189 Once this is done, various switches may override. */
196 /* First copy the register information from the initial int form into
199 for (i = 0; i < N_REG_CLASSES; i++)
201 CLEAR_HARD_REG_SET (reg_class_contents[i]);
203 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
204 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
205 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
206 SET_HARD_REG_BIT (reg_class_contents[i], j);
209 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
210 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
211 bzero (global_regs, sizeof global_regs);
213 /* Compute number of hard regs in each class. */
215 bzero (reg_class_size, sizeof reg_class_size);
216 for (i = 0; i < N_REG_CLASSES; i++)
217 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
218 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
221 /* Initialize the table of subunions.
222 reg_class_subunion[I][J] gets the largest-numbered reg-class
223 that is contained in the union of classes I and J. */
225 for (i = 0; i < N_REG_CLASSES; i++)
227 for (j = 0; j < N_REG_CLASSES; j++)
230 register /* Declare it register if it's a scalar. */
235 COPY_HARD_REG_SET (c, reg_class_contents[i]);
236 IOR_HARD_REG_SET (c, reg_class_contents[j]);
237 for (k = 0; k < N_REG_CLASSES; k++)
239 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
244 /* keep the largest subclass */ /* SPEE 900308 */
245 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
246 reg_class_contents[(int) reg_class_subunion[i][j]],
248 reg_class_subunion[i][j] = (enum reg_class) k;
255 /* Initialize the table of superunions.
256 reg_class_superunion[I][J] gets the smallest-numbered reg-class
257 containing the union of classes I and J. */
259 for (i = 0; i < N_REG_CLASSES; i++)
261 for (j = 0; j < N_REG_CLASSES; j++)
264 register /* Declare it register if it's a scalar. */
269 COPY_HARD_REG_SET (c, reg_class_contents[i]);
270 IOR_HARD_REG_SET (c, reg_class_contents[j]);
271 for (k = 0; k < N_REG_CLASSES; k++)
272 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
275 reg_class_superunion[i][j] = (enum reg_class) k;
279 /* Initialize the tables of subclasses and superclasses of each reg class.
280 First clear the whole table, then add the elements as they are found. */
282 for (i = 0; i < N_REG_CLASSES; i++)
284 for (j = 0; j < N_REG_CLASSES; j++)
286 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
287 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
291 for (i = 0; i < N_REG_CLASSES; i++)
293 if (i == (int) NO_REGS)
296 for (j = i + 1; j < N_REG_CLASSES; j++)
300 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
304 /* Reg class I is a subclass of J.
305 Add J to the table of superclasses of I. */
306 p = ®_class_superclasses[i][0];
307 while (*p != LIM_REG_CLASSES) p++;
308 *p = (enum reg_class) j;
309 /* Add I to the table of superclasses of J. */
310 p = ®_class_subclasses[j][0];
311 while (*p != LIM_REG_CLASSES) p++;
312 *p = (enum reg_class) i;
316 /* Initialize the move cost table. Find every subset of each class
317 and take the maximum cost of moving any subset to any other. */
319 for (i = 0; i < N_REG_CLASSES; i++)
320 for (j = 0; j < N_REG_CLASSES; j++)
322 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
323 enum reg_class *p1, *p2;
325 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
327 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
329 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
332 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
334 for (p2 = ®_class_subclasses[j][0];
335 *p2 != LIM_REG_CLASSES; p2++)
337 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
340 move_cost[i][j] = cost;
342 if (reg_class_subset_p (i, j))
345 may_move_cost[i][j] = cost;
349 /* After switches have been processed, which perhaps alter
350 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
357 /* This macro allows the fixed or call-used registers
358 to depend on target flags. */
360 #ifdef CONDITIONAL_REGISTER_USAGE
361 CONDITIONAL_REGISTER_USAGE;
364 /* Initialize "constant" tables. */
366 CLEAR_HARD_REG_SET (fixed_reg_set);
367 CLEAR_HARD_REG_SET (call_used_reg_set);
368 CLEAR_HARD_REG_SET (call_fixed_reg_set);
370 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
371 #ifdef STRUCT_VALUE_REGNUM
372 call_fixed_regs[STRUCT_VALUE_REGNUM] = 1;
374 #ifdef STATIC_CHAIN_REGNUM
375 call_fixed_regs[STATIC_CHAIN_REGNUM] = 1;
378 n_non_fixed_regs = 0;
380 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
382 if (FUNCTION_VALUE_REGNO_P (i))
383 call_fixed_regs[i] = 1;
385 SET_HARD_REG_BIT (fixed_reg_set, i);
389 if (call_used_regs[i])
390 SET_HARD_REG_BIT (call_used_reg_set, i);
391 if (call_fixed_regs[i])
392 SET_HARD_REG_BIT (call_fixed_reg_set, i);
396 /* Specify the usage characteristics of the register named NAME.
397 It should be a fixed register if FIXED and a
398 call-used register if CALL_USED. */
401 fix_register (name, fixed, call_used)
403 int fixed, call_used;
409 warning ("request to mark `%s' as %s ignored by bytecode compiler",
410 name, call_used ? "call-used" : "fixed");
414 /* Decode the name and update the primary form of
415 the register info. */
417 if ((i = decode_reg_name (name)) >= 0)
419 fixed_regs[i] = fixed;
420 call_used_regs[i] = call_used;
424 warning ("unknown register name: %s", name);
428 /* Mark register number I as global. */
436 warning ("register used for two global register variables");
440 if (call_used_regs[i] && ! fixed_regs[i])
441 warning ("call-clobbered register used for global register variable");
445 /* If already fixed, nothing else to do. */
449 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
452 SET_HARD_REG_BIT (fixed_reg_set, i);
453 SET_HARD_REG_BIT (call_used_reg_set, i);
454 SET_HARD_REG_BIT (call_fixed_reg_set, i);
457 /* Now the data and code for the `regclass' pass, which happens
458 just before local-alloc. */
460 /* The `costs' struct records the cost of using a hard register of each class
461 and of using memory for each pseudo. We use this data to set up
462 register class preferences. */
466 int cost[N_REG_CLASSES];
470 /* Record the cost of each class for each pseudo. */
472 static struct costs *costs;
474 /* Record the same data by operand number, accumulated for each alternative
475 in an insn. The contribution to a pseudo is that of the minimum-cost
478 static struct costs op_costs[MAX_RECOG_OPERANDS];
480 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
481 This is available after `regclass' is run. */
483 static char *prefclass;
485 /* altclass[R] is a register class that we should use for allocating
486 pseudo number R if no register in the preferred class is available.
487 If no register in this class is available, memory is preferred.
489 It might appear to be more general to have a bitmask of classes here,
490 but since it is recommended that there be a class corresponding to the
491 union of most major pair of classes, that generality is not required.
493 This is available after `regclass' is run. */
495 static char *altclass;
497 /* Record the depth of loops that we are in. */
499 static int loop_depth;
501 /* Account for the fact that insns within a loop are executed very commonly,
502 but don't keep doing this as loops go too deep. */
504 static int loop_cost;
506 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
508 static int copy_cost PROTO((rtx, enum machine_mode,
509 enum reg_class, int));
510 static void record_address_regs PROTO((rtx, enum reg_class, int));
511 static auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
512 static void reg_scan_mark_refs PROTO((rtx, rtx, int));
514 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
515 This function is sometimes called before the info has been computed.
516 When that happens, just return GENERAL_REGS, which is innocuous. */
519 reg_preferred_class (regno)
524 return (enum reg_class) prefclass[regno];
528 reg_alternate_class (regno)
533 return (enum reg_class) altclass[regno];
536 /* This prevents dump_flow_info from losing if called
537 before regclass is run. */
545 /* This is a pass of the compiler that scans all instructions
546 and calculates the preferred class for each pseudo-register.
547 This information can be accessed later by calling `reg_preferred_class'.
548 This pass comes just before local register allocation. */
555 #ifdef REGISTER_CONSTRAINTS
558 struct costs init_cost;
564 costs = (struct costs *) alloca (nregs * sizeof (struct costs));
566 #ifdef FORBIDDEN_INC_DEC_CLASSES
568 in_inc_dec = (char *) alloca (nregs);
570 /* Initialize information about which register classes can be used for
571 pseudos that are auto-incremented or auto-decremented. It would
572 seem better to put this in init_reg_sets, but we need to be able
573 to allocate rtx, which we can't do that early. */
575 for (i = 0; i < N_REG_CLASSES; i++)
577 rtx r = gen_rtx (REG, VOIDmode, 0);
580 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
581 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
585 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
586 m = (enum machine_mode) ((int) m + 1))
587 if (HARD_REGNO_MODE_OK (j, m))
591 /* If a register is not directly suitable for an
592 auto-increment or decrement addressing mode and
593 requires secondary reloads, disallow its class from
594 being used in such addresses. */
597 #ifdef SECONDARY_INPUT_RELOAD_CLASS
598 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
601 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
602 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
606 && ! auto_inc_dec_reg_p (r, m))
607 forbidden_inc_dec_class[i] = 1;
611 #endif /* FORBIDDEN_INC_DEC_CLASSES */
613 init_cost.mem_cost = 10000;
614 for (i = 0; i < N_REG_CLASSES; i++)
615 init_cost.cost[i] = 10000;
617 /* Normally we scan the insns once and determine the best class to use for
618 each register. However, if -fexpensive_optimizations are on, we do so
619 twice, the second time using the tentative best classes to guide the
622 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
624 /* Zero out our accumulation of the cost of each class for each reg. */
626 bzero (costs, nregs * sizeof (struct costs));
628 #ifdef FORBIDDEN_INC_DEC_CLASSES
629 bzero (in_inc_dec, nregs);
632 loop_depth = 0, loop_cost = 1;
634 /* Scan the instructions and record each time it would
635 save code to put a certain register in a certain class. */
637 for (insn = f; insn; insn = NEXT_INSN (insn))
639 char *constraints[MAX_RECOG_OPERANDS];
640 enum machine_mode modes[MAX_RECOG_OPERANDS];
644 /* Show that an insn inside a loop is likely to be executed three
645 times more than insns outside a loop. This is much more aggressive
646 than the assumptions made elsewhere and is being tried as an
649 if (GET_CODE (insn) == NOTE
650 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
651 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
652 else if (GET_CODE (insn) == NOTE
653 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
654 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
656 else if ((GET_CODE (insn) == INSN
657 && GET_CODE (PATTERN (insn)) != USE
658 && GET_CODE (PATTERN (insn)) != CLOBBER
659 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
660 || (GET_CODE (insn) == JUMP_INSN
661 && GET_CODE (PATTERN (insn)) != ADDR_VEC
662 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
663 || GET_CODE (insn) == CALL_INSN)
665 if (GET_CODE (insn) == INSN
666 && (noperands = asm_noperands (PATTERN (insn))) >= 0)
668 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR,
670 nalternatives = (noperands == 0 ? 0
671 : n_occurrences (',', constraints[0]) + 1);
675 int insn_code_number = recog_memoized (insn);
678 set = single_set (insn);
681 nalternatives = insn_n_alternatives[insn_code_number];
682 noperands = insn_n_operands[insn_code_number];
684 /* If this insn loads a parameter from its stack slot, then
685 it represents a savings, rather than a cost, if the
686 parameter is stored in memory. Record this fact. */
688 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
689 && GET_CODE (SET_SRC (set)) == MEM
690 && (note = find_reg_note (insn, REG_EQUIV,
692 && GET_CODE (XEXP (note, 0)) == MEM)
694 costs[REGNO (SET_DEST (set))].mem_cost
695 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)))
697 record_address_regs (XEXP (SET_SRC (set), 0),
698 BASE_REG_CLASS, loop_cost * 2);
702 /* Improve handling of two-address insns such as
703 (set X (ashift CONST Y)) where CONST must be made to
704 match X. Change it into two insns: (set X CONST)
705 (set X (ashift X Y)). If we left this for reloading, it
706 would probably get three insns because X and Y might go
707 in the same place. This prevents X and Y from receiving
710 We can only do this if the modes of operands 0 and 1
711 (which might not be the same) are tieable and we only need
712 do this during our first pass. */
714 if (pass == 0 && optimize
716 && insn_operand_constraint[insn_code_number][1][0] == '0'
717 && insn_operand_constraint[insn_code_number][1][1] == 0
718 && CONSTANT_P (recog_operand[1])
719 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
720 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
721 && GET_CODE (recog_operand[0]) == REG
722 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
723 insn_operand_mode[insn_code_number][1]))
725 rtx previnsn = prev_real_insn (insn);
727 = gen_lowpart (insn_operand_mode[insn_code_number][1],
730 = emit_insn_before (gen_move_insn (dest,
734 /* If this insn was the start of a basic block,
735 include the new insn in that block.
736 We need not check for code_label here;
737 while a basic block can start with a code_label,
738 INSN could not be at the beginning of that block. */
739 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
742 for (b = 0; b < n_basic_blocks; b++)
743 if (insn == basic_block_head[b])
744 basic_block_head[b] = newinsn;
747 /* This makes one more setting of new insns's dest. */
748 reg_n_sets[REGNO (recog_operand[0])]++;
750 *recog_operand_loc[1] = recog_operand[0];
751 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
752 if (recog_dup_num[i] == 1)
753 *recog_dup_loc[i] = recog_operand[0];
755 insn = PREV_INSN (newinsn);
759 for (i = 0; i < noperands; i++)
762 = insn_operand_constraint[insn_code_number][i];
763 modes[i] = insn_operand_mode[insn_code_number][i];
767 /* If we get here, we are set up to record the costs of all the
768 operands for this insn. Start by initializing the costs.
769 Then handle any address registers. Finally record the desired
770 classes for any pseudos, doing it twice if some pair of
771 operands are commutative. */
773 for (i = 0; i < noperands; i++)
775 op_costs[i] = init_cost;
777 if (GET_CODE (recog_operand[i]) == SUBREG)
778 recog_operand[i] = SUBREG_REG (recog_operand[i]);
780 if (GET_CODE (recog_operand[i]) == MEM)
781 record_address_regs (XEXP (recog_operand[i], 0),
782 BASE_REG_CLASS, loop_cost * 2);
783 else if (constraints[i][0] == 'p')
784 record_address_regs (recog_operand[i],
785 BASE_REG_CLASS, loop_cost * 2);
788 /* Check for commutative in a separate loop so everything will
789 have been initialized. We must do this even if one operand
790 is a constant--see addsi3 in m68k.md. */
792 for (i = 0; i < noperands - 1; i++)
793 if (constraints[i][0] == '%')
795 char *xconstraints[MAX_RECOG_OPERANDS];
798 /* Handle commutative operands by swapping the constraints.
799 We assume the modes are the same. */
801 for (j = 0; j < noperands; j++)
802 xconstraints[j] = constraints[j];
804 xconstraints[i] = constraints[i+1];
805 xconstraints[i+1] = constraints[i];
806 record_reg_classes (nalternatives, noperands,
807 recog_operand, modes, xconstraints,
811 record_reg_classes (nalternatives, noperands, recog_operand,
812 modes, constraints, insn);
814 /* Now add the cost for each operand to the total costs for
817 for (i = 0; i < noperands; i++)
818 if (GET_CODE (recog_operand[i]) == REG
819 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
821 int regno = REGNO (recog_operand[i]);
822 struct costs *p = &costs[regno], *q = &op_costs[i];
824 p->mem_cost += q->mem_cost * loop_cost;
825 for (j = 0; j < N_REG_CLASSES; j++)
826 p->cost[j] += q->cost[j] * loop_cost;
831 /* Now for each register look at how desirable each class is
832 and find which class is preferred. Store that in
833 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
834 class any of whose registers is better than memory. */
838 prefclass = (char *) oballoc (nregs);
839 altclass = (char *) oballoc (nregs);
842 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
844 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
845 enum reg_class best = ALL_REGS, alt = NO_REGS;
846 /* This is an enum reg_class, but we call it an int
847 to save lots of casts. */
849 register struct costs *p = &costs[i];
851 for (class = (int) ALL_REGS - 1; class > 0; class--)
853 /* Ignore classes that are too small for this operand or
854 invalid for a operand that was auto-incremented. */
855 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
856 > reg_class_size[class]
857 #ifdef FORBIDDEN_INC_DEC_CLASSES
858 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
862 else if (p->cost[class] < best_cost)
864 best_cost = p->cost[class];
865 best = (enum reg_class) class;
867 else if (p->cost[class] == best_cost)
868 best = reg_class_subunion[(int)best][class];
871 /* Record the alternate register class; i.e., a class for which
872 every register in it is better than using memory. If adding a
873 class would make a smaller class (i.e., no union of just those
874 classes exists), skip that class. The major unions of classes
875 should be provided as a register class. Don't do this if we
876 will be doing it again later. */
878 if (pass == 1 || ! flag_expensive_optimizations)
879 for (class = 0; class < N_REG_CLASSES; class++)
880 if (p->cost[class] < p->mem_cost
881 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
882 > reg_class_size[(int) alt])
883 #ifdef FORBIDDEN_INC_DEC_CLASSES
884 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
887 alt = reg_class_subunion[(int) alt][class];
889 /* If we don't add any classes, nothing to try. */
893 /* We cast to (int) because (char) hits bugs in some compilers. */
894 prefclass[i] = (int) best;
895 altclass[i] = (int) alt;
898 #endif /* REGISTER_CONSTRAINTS */
901 #ifdef REGISTER_CONSTRAINTS
903 /* Record the cost of using memory or registers of various classes for
904 the operands in INSN.
906 N_ALTS is the number of alternatives.
908 N_OPS is the number of operands.
910 OPS is an array of the operands.
912 MODES are the modes of the operands, in case any are VOIDmode.
914 CONSTRAINTS are the constraints to use for the operands. This array
915 is modified by this procedure.
917 This procedure works alternative by alternative. For each alternative
918 we assume that we will be able to allocate all pseudos to their ideal
919 register class and calculate the cost of using that alternative. Then
920 we compute for each operand that is a pseudo-register, the cost of
921 having the pseudo allocated to each register class and using it in that
922 alternative. To this cost is added the cost of the alternative.
924 The cost of each class for this insn is its lowest cost among all the
928 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
932 enum machine_mode *modes;
937 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS];
940 /* By default, each operand is an input operand. */
942 for (i = 0; i < n_ops; i++)
943 op_types[i] = OP_READ;
945 /* Process each alternative, each time minimizing an operand's cost with
946 the cost for each operand in that alternative. */
948 for (alt = 0; alt < n_alts; alt++)
950 struct costs this_op_costs[MAX_RECOG_OPERANDS];
953 enum reg_class classes[MAX_RECOG_OPERANDS];
956 for (i = 0; i < n_ops; i++)
958 char *p = constraints[i];
960 enum machine_mode mode = modes[i];
965 /* If this operand has no constraints at all, we can conclude
966 nothing about it since anything is valid. */
970 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
971 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
979 /* If this alternative is only relevant when this operand
980 matches a previous operand, we do different things depending
981 on whether this operand is a pseudo-reg or not. */
983 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
986 classes[i] = classes[j];
988 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
990 /* If this matches the other operand, we have no added
992 if (rtx_equal_p (ops[j], op))
995 /* If we can put the other operand into a register, add to
996 the cost of this alternative the cost to copy this
997 operand to the register used for the other operand. */
999 if (classes[j] != NO_REGS)
1000 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1002 else if (GET_CODE (ops[j]) != REG
1003 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1005 /* This op is a pseudo but the one it matches is not. */
1007 /* If we can't put the other operand into a register, this
1008 alternative can't be used. */
1010 if (classes[j] == NO_REGS)
1013 /* Otherwise, add to the cost of this alternative the cost
1014 to copy the other operand to the register used for this
1018 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1022 /* The costs of this operand are the same as that of the
1023 other operand. However, if we cannot tie them, this
1024 alternative needs to do a copy, which is one
1027 this_op_costs[i] = this_op_costs[j];
1028 if (REGNO (ops[i]) != REGNO (ops[j])
1029 && ! find_reg_note (insn, REG_DEAD, op))
1032 /* This is in place of ordinary cost computation
1033 for this operand, so skip to the end of the
1034 alternative (should be just one character). */
1035 while (*p && *p++ != ',')
1043 /* Scan all the constraint letters. See if the operand matches
1044 any of the constraints. Collect the valid register classes
1045 and see if this operand accepts memory. */
1047 classes[i] = NO_REGS;
1048 while (*p && (c = *p++) != ',')
1052 op_types[i] = OP_WRITE;
1056 op_types[i] = OP_READ_WRITE;
1060 /* Ignore the next letter for this pass. */
1065 case '?': case '!': case '#':
1067 case '0': case '1': case '2': case '3': case '4':
1071 case 'm': case 'o': case 'V':
1072 /* It doesn't seem worth distinguishing between offsettable
1073 and non-offsettable addresses here. */
1075 if (GET_CODE (op) == MEM)
1080 if (GET_CODE (op) == MEM
1081 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1082 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1087 if (GET_CODE (op) == MEM
1088 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1089 || GET_CODE (XEXP (op, 0)) == POST_INC))
1094 /* Match any floating double constant, but only if
1095 we can examine the bits of it reliably. */
1096 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1097 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1098 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1100 if (GET_CODE (op) == CONST_DOUBLE)
1105 if (GET_CODE (op) == CONST_DOUBLE)
1111 if (GET_CODE (op) == CONST_DOUBLE
1112 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1117 if (GET_CODE (op) == CONST_INT
1118 || (GET_CODE (op) == CONST_DOUBLE
1119 && GET_MODE (op) == VOIDmode))
1123 #ifdef LEGITIMATE_PIC_OPERAND_P
1124 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1131 if (GET_CODE (op) == CONST_INT
1132 || (GET_CODE (op) == CONST_DOUBLE
1133 && GET_MODE (op) == VOIDmode))
1145 if (GET_CODE (op) == CONST_INT
1146 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1154 #ifdef EXTRA_CONSTRAINT
1160 if (EXTRA_CONSTRAINT (op, c))
1166 if (GET_CODE (op) == MEM
1168 #ifdef LEGITIMATE_PIC_OPERAND_P
1169 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1176 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1181 = reg_class_subunion[(int) classes[i]]
1182 [(int) REG_CLASS_FROM_LETTER (c)];
1187 /* How we account for this operand now depends on whether it is a
1188 pseudo register or not. If it is, we first check if any
1189 register classes are valid. If not, we ignore this alternative,
1190 since we want to assume that all pseudos get allocated for
1191 register preferencing. If some register class is valid, compute
1192 the costs of moving the pseudo into that class. */
1194 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1196 if (classes[i] == NO_REGS)
1200 struct costs *pp = &this_op_costs[i];
1202 for (class = 0; class < N_REG_CLASSES; class++)
1203 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1205 /* If the alternative actually allows memory, make things
1206 a bit cheaper since we won't need an extra insn to
1209 pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem;
1211 /* If we have assigned a class to this register in our
1212 first pass, add a cost to this alternative corresponding
1213 to what we would add if this register were not in the
1214 appropriate class. */
1218 += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]];
1222 /* Otherwise, if this alternative wins, either because we
1223 have already determined that or if we have a hard register of
1224 the proper class, there is no cost for this alternative. */
1227 || (GET_CODE (op) == REG
1228 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1231 /* If registers are valid, the cost of this alternative includes
1232 copying the object to and/or from a register. */
1234 else if (classes[i] != NO_REGS)
1236 if (op_types[i] != OP_WRITE)
1237 alt_cost += copy_cost (op, mode, classes[i], 1);
1239 if (op_types[i] != OP_READ)
1240 alt_cost += copy_cost (op, mode, classes[i], 0);
1243 /* The only other way this alternative can be used is if this is a
1244 constant that could be placed into memory. */
1246 else if (CONSTANT_P (op) && allows_mem)
1247 alt_cost += MEMORY_MOVE_COST (mode);
1255 /* Finally, update the costs with the information we've calculated
1256 about this alternative. */
1258 for (i = 0; i < n_ops; i++)
1259 if (GET_CODE (ops[i]) == REG
1260 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1262 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1263 int scale = 1 + (op_types[i] == OP_READ_WRITE);
1265 pp->mem_cost = MIN (pp->mem_cost,
1266 (qq->mem_cost + alt_cost) * scale);
1268 for (class = 0; class < N_REG_CLASSES; class++)
1269 pp->cost[class] = MIN (pp->cost[class],
1270 (qq->cost[class] + alt_cost) * scale);
1275 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1276 TO_P is zero) a register of class CLASS in mode MODE.
1278 X must not be a pseudo. */
1281 copy_cost (x, mode, class, to_p)
1283 enum machine_mode mode;
1284 enum reg_class class;
1287 enum reg_class secondary_class = NO_REGS;
1289 /* If X is a SCRATCH, there is actually nothing to move since we are
1290 assuming optimal allocation. */
1292 if (GET_CODE (x) == SCRATCH)
1295 /* Get the class we will actually use for a reload. */
1296 class = PREFERRED_RELOAD_CLASS (x, class);
1298 #ifdef HAVE_SECONDARY_RELOADS
1299 /* If we need a secondary reload (we assume here that we are using
1300 the secondary reload as an intermediate, not a scratch register), the
1301 cost is that to load the input into the intermediate register, then
1302 to copy them. We use a special value of TO_P to avoid recursion. */
1304 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1306 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1309 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1311 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1314 if (secondary_class != NO_REGS)
1315 return (move_cost[(int) secondary_class][(int) class]
1316 + copy_cost (x, mode, secondary_class, 2));
1317 #endif /* HAVE_SECONDARY_RELOADS */
1319 /* For memory, use the memory move cost, for (hard) registers, use the
1320 cost to move between the register classes, and use 2 for everything
1321 else (constants). */
1323 if (GET_CODE (x) == MEM || class == NO_REGS)
1324 return MEMORY_MOVE_COST (mode);
1326 else if (GET_CODE (x) == REG)
1327 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1330 /* If this is a constant, we may eventually want to call rtx_cost here. */
1334 /* Record the pseudo registers we must reload into hard registers
1335 in a subexpression of a memory address, X.
1337 CLASS is the class that the register needs to be in and is either
1338 BASE_REG_CLASS or INDEX_REG_CLASS.
1340 SCALE is twice the amount to multiply the cost by (it is twice so we
1341 can represent half-cost adjustments). */
1344 record_address_regs (x, class, scale)
1346 enum reg_class class;
1349 register enum rtx_code code = GET_CODE (x);
1362 /* When we have an address that is a sum,
1363 we must determine whether registers are "base" or "index" regs.
1364 If there is a sum of two registers, we must choose one to be
1365 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1366 to make a good choice most of the time. We only need to do this
1367 on machines that can have two registers in an address and where
1368 the base and index register classes are different.
1370 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1371 that seems bogus since it should only be set when we are sure
1372 the register is being used as a pointer. */
1375 rtx arg0 = XEXP (x, 0);
1376 rtx arg1 = XEXP (x, 1);
1377 register enum rtx_code code0 = GET_CODE (arg0);
1378 register enum rtx_code code1 = GET_CODE (arg1);
1380 /* Look inside subregs. */
1381 if (code0 == SUBREG)
1382 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1383 if (code1 == SUBREG)
1384 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1386 /* If this machine only allows one register per address, it must
1387 be in the first operand. */
1389 if (MAX_REGS_PER_ADDRESS == 1)
1390 record_address_regs (arg0, class, scale);
1392 /* If index and base registers are the same on this machine, just
1393 record registers in any non-constant operands. We assume here,
1394 as well as in the tests below, that all addresses are in
1397 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1399 record_address_regs (arg0, class, scale);
1400 if (! CONSTANT_P (arg1))
1401 record_address_regs (arg1, class, scale);
1404 /* If the second operand is a constant integer, it doesn't change
1405 what class the first operand must be. */
1407 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1408 record_address_regs (arg0, class, scale);
1410 /* If the second operand is a symbolic constant, the first operand
1411 must be an index register. */
1413 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1414 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1416 /* If this the sum of two registers where the first is known to be a
1417 pointer, it must be a base register with the second an index. */
1419 else if (code0 == REG && code1 == REG
1420 && REGNO_POINTER_FLAG (REGNO (arg0)))
1422 record_address_regs (arg0, BASE_REG_CLASS, scale);
1423 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1426 /* If this is the sum of two registers and neither is known to
1427 be a pointer, count equal chances that each might be a base
1428 or index register. This case should be rare. */
1430 else if (code0 == REG && code1 == REG
1431 && ! REGNO_POINTER_FLAG (REGNO (arg0))
1432 && ! REGNO_POINTER_FLAG (REGNO (arg1)))
1434 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1435 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1436 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1437 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1440 /* In all other cases, the first operand is an index and the
1441 second is the base. */
1445 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1446 record_address_regs (arg1, BASE_REG_CLASS, scale);
1455 /* Double the importance of a pseudo register that is incremented
1456 or decremented, since it would take two extra insns
1457 if it ends up in the wrong place. If the operand is a pseudo,
1458 show it is being used in an INC_DEC context. */
1460 #ifdef FORBIDDEN_INC_DEC_CLASSES
1461 if (GET_CODE (XEXP (x, 0)) == REG
1462 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1463 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1466 record_address_regs (XEXP (x, 0), class, 2 * scale);
1471 register struct costs *pp = &costs[REGNO (x)];
1474 pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2;
1476 for (i = 0; i < N_REG_CLASSES; i++)
1477 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1483 register char *fmt = GET_RTX_FORMAT (code);
1485 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1487 record_address_regs (XEXP (x, i), class, scale);
1492 #ifdef FORBIDDEN_INC_DEC_CLASSES
1494 /* Return 1 if REG is valid as an auto-increment memory reference
1495 to an object of MODE. */
1498 auto_inc_dec_reg_p (reg, mode)
1500 enum machine_mode mode;
1502 #ifdef HAVE_POST_INCREMENT
1503 if (memory_address_p (mode, gen_rtx (POST_INC, Pmode, reg)))
1507 #ifdef HAVE_POST_DECREMENT
1508 if (memory_address_p (mode, gen_rtx (POST_DEC, Pmode, reg)))
1512 #ifdef HAVE_PRE_INCREMENT
1513 if (memory_address_p (mode, gen_rtx (PRE_INC, Pmode, reg)))
1517 #ifdef HAVE_PRE_DECREMENT
1518 if (memory_address_p (mode, gen_rtx (PRE_DEC, Pmode, reg)))
1526 #endif /* REGISTER_CONSTRAINTS */
1528 /* This is the `regscan' pass of the compiler, run just before cse
1529 and again just before loop.
1531 It finds the first and last use of each pseudo-register
1532 and records them in the vectors regno_first_uid, regno_last_uid
1533 and counts the number of sets in the vector reg_n_sets.
1535 REPEAT is nonzero the second time this is called. */
1537 /* Indexed by pseudo register number, gives uid of first insn using the reg
1538 (as of the time reg_scan is called). */
1540 int *regno_first_uid;
1542 /* Indexed by pseudo register number, gives uid of last insn using the reg
1543 (as of the time reg_scan is called). */
1545 int *regno_last_uid;
1547 /* Indexed by pseudo register number, gives uid of last insn using the reg
1548 or mentioning it in a note (as of the time reg_scan is called). */
1550 int *regno_last_note_uid;
1552 /* Record the number of registers we used when we allocated the above two
1553 tables. If we are called again with more than this, we must re-allocate
1556 static int highest_regno_in_uid_map;
1558 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1559 Always at least 3, since the combiner could put that many togetherm
1560 and we want this to remain correct for all the remaining passes. */
1565 reg_scan (f, nregs, repeat)
1572 if (!repeat || nregs > highest_regno_in_uid_map)
1574 /* Leave some spare space in case more regs are allocated. */
1575 highest_regno_in_uid_map = nregs + nregs / 20;
1577 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1579 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1581 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1583 = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1586 bzero (regno_first_uid, highest_regno_in_uid_map * sizeof (int));
1587 bzero (regno_last_uid, highest_regno_in_uid_map * sizeof (int));
1588 bzero (regno_last_note_uid, highest_regno_in_uid_map * sizeof (int));
1589 bzero (reg_n_sets, highest_regno_in_uid_map * sizeof (short));
1593 for (insn = f; insn; insn = NEXT_INSN (insn))
1594 if (GET_CODE (insn) == INSN
1595 || GET_CODE (insn) == CALL_INSN
1596 || GET_CODE (insn) == JUMP_INSN)
1598 if (GET_CODE (PATTERN (insn)) == PARALLEL
1599 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1600 max_parallel = XVECLEN (PATTERN (insn), 0);
1601 reg_scan_mark_refs (PATTERN (insn), insn, 0);
1603 if (REG_NOTES (insn))
1604 reg_scan_mark_refs (REG_NOTES (insn), insn, 1);
1608 /* X is the expression to scan. INSN is the insn it appears in.
1609 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */
1612 reg_scan_mark_refs (x, insn, note_flag)
1617 register enum rtx_code code = GET_CODE (x);
1636 register int regno = REGNO (x);
1638 regno_last_note_uid[regno] = INSN_UID (insn);
1640 regno_last_uid[regno] = INSN_UID (insn);
1641 if (regno_first_uid[regno] == 0)
1642 regno_first_uid[regno] = INSN_UID (insn);
1648 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag);
1650 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1655 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1659 /* Count a set of the destination if it is a register. */
1660 for (dest = SET_DEST (x);
1661 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
1662 || GET_CODE (dest) == ZERO_EXTEND;
1663 dest = XEXP (dest, 0))
1666 if (GET_CODE (dest) == REG)
1667 reg_n_sets[REGNO (dest)]++;
1669 /* If this is setting a pseudo from another pseudo or the sum of a
1670 pseudo and a constant integer and the other pseudo is known to be
1671 a pointer, set the destination to be a pointer as well.
1673 Likewise if it is setting the destination from an address or from a
1674 value equivalent to an address or to the sum of an address and
1677 But don't do any of this if the pseudo corresponds to a user
1678 variable since it should have already been set as a pointer based
1681 if (GET_CODE (SET_DEST (x)) == REG
1682 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
1683 && ! REG_USERVAR_P (SET_DEST (x))
1684 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
1685 && ((GET_CODE (SET_SRC (x)) == REG
1686 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
1687 || ((GET_CODE (SET_SRC (x)) == PLUS
1688 || GET_CODE (SET_SRC (x)) == LO_SUM)
1689 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
1690 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
1691 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
1692 || GET_CODE (SET_SRC (x)) == CONST
1693 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
1694 || GET_CODE (SET_SRC (x)) == LABEL_REF
1695 || (GET_CODE (SET_SRC (x)) == HIGH
1696 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
1697 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
1698 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
1699 || ((GET_CODE (SET_SRC (x)) == PLUS
1700 || GET_CODE (SET_SRC (x)) == LO_SUM)
1701 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
1702 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
1703 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
1704 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
1705 && (GET_CODE (XEXP (note, 0)) == CONST
1706 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
1707 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
1708 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
1710 /* ... fall through ... */
1714 register char *fmt = GET_RTX_FORMAT (code);
1716 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1719 reg_scan_mark_refs (XEXP (x, i), insn, note_flag);
1720 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
1723 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1724 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag);
1731 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1735 reg_class_subset_p (c1, c2)
1736 register enum reg_class c1;
1737 register enum reg_class c2;
1739 if (c1 == c2) return 1;
1744 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
1745 reg_class_contents[(int)c2],
1750 /* Return nonzero if there is a register that is in both C1 and C2. */
1753 reg_classes_intersect_p (c1, c2)
1754 register enum reg_class c1;
1755 register enum reg_class c2;
1762 if (c1 == c2) return 1;
1764 if (c1 == ALL_REGS || c2 == ALL_REGS)
1767 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1768 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1770 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);