1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91, 92, 93, 94, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
28 #include "hard-reg-set.h"
30 #include "basic-block.h"
32 #include "insn-config.h"
38 #ifndef REGISTER_MOVE_COST
39 #define REGISTER_MOVE_COST(x, y) 2
42 #ifndef MEMORY_MOVE_COST
43 #define MEMORY_MOVE_COST(x) 4
46 /* If we have auto-increment or auto-decrement and we can have secondary
47 reloads, we are not allowed to use classes requiring secondary
48 reloads for pseudos auto-incremented since reload can't handle it. */
51 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
52 #define FORBIDDEN_INC_DEC_CLASSES
56 /* Register tables used by many passes. */
58 /* Indexed by hard register number, contains 1 for registers
59 that are fixed use (stack pointer, pc, frame pointer, etc.).
60 These are the registers that cannot be used to allocate
61 a pseudo reg whose life does not cross calls. */
63 char fixed_regs[FIRST_PSEUDO_REGISTER];
65 /* Same info as a HARD_REG_SET. */
67 HARD_REG_SET fixed_reg_set;
69 /* Data for initializing the above. */
71 static char initial_fixed_regs[] = FIXED_REGISTERS;
73 /* Indexed by hard register number, contains 1 for registers
74 that are fixed use or are clobbered by function calls.
75 These are the registers that cannot be used to allocate
76 a pseudo reg whose life crosses calls. */
78 char call_used_regs[FIRST_PSEUDO_REGISTER];
80 /* Same info as a HARD_REG_SET. */
82 HARD_REG_SET call_used_reg_set;
84 /* HARD_REG_SET of registers we want to avoid caller saving. */
85 HARD_REG_SET losing_caller_save_reg_set;
87 /* Data for initializing the above. */
89 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
91 /* Indexed by hard register number, contains 1 for registers that are
92 fixed use -- i.e. in fixed_regs -- or a function value return register
93 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
94 registers that cannot hold quantities across calls even if we are
95 willing to save and restore them. */
97 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
99 /* The same info as a HARD_REG_SET. */
101 HARD_REG_SET call_fixed_reg_set;
103 /* Number of non-fixed registers. */
105 int n_non_fixed_regs;
107 /* Indexed by hard register number, contains 1 for registers
108 that are being used for global register decls.
109 These must be exempt from ordinary flow analysis
110 and are also considered fixed. */
112 char global_regs[FIRST_PSEUDO_REGISTER];
114 /* Table of register numbers in the order in which to try to use them. */
115 #ifdef REG_ALLOC_ORDER
116 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
119 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
121 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
123 /* The same information, but as an array of unsigned ints. We copy from
124 these unsigned ints to the table above. We do this so the tm.h files
125 do not have to be aware of the wordsize for machines with <= 64 regs. */
128 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
130 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
131 = REG_CLASS_CONTENTS;
133 /* For each reg class, number of regs it contains. */
135 int reg_class_size[N_REG_CLASSES];
137 /* For each reg class, table listing all the containing classes. */
139 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
141 /* For each reg class, table listing all the classes contained in it. */
143 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
145 /* For each pair of reg classes,
146 a largest reg class contained in their union. */
148 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
150 /* For each pair of reg classes,
151 the smallest reg class containing their union. */
153 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
155 /* Array containing all of the register names */
157 char *reg_names[] = REGISTER_NAMES;
159 /* For each hard register, the widest mode object that it can contain.
160 This will be a MODE_INT mode if the register can hold integers. Otherwise
161 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
164 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
166 /* Indexed by n, gives number of times (REG n) is set or clobbered.
167 This information remains valid for the rest of the compilation
168 of the current function; it is used to control register allocation.
170 This information applies to both hard registers and pseudo registers,
171 unlike much of the information above. */
175 /* Maximum cost of moving from a register in one class to a register in
176 another class. Based on REGISTER_MOVE_COST. */
178 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
180 /* Similar, but here we don't have to move if the first index is a subset
181 of the second so in that case the cost is zero. */
183 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
185 #ifdef FORBIDDEN_INC_DEC_CLASSES
187 /* These are the classes that regs which are auto-incremented or decremented
190 static int forbidden_inc_dec_class[N_REG_CLASSES];
192 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
195 static char *in_inc_dec;
197 #endif /* FORBIDDEN_INC_DEC_CLASSES */
199 /* Function called only once to initialize the above data on reg usage.
200 Once this is done, various switches may override. */
207 /* First copy the register information from the initial int form into
210 for (i = 0; i < N_REG_CLASSES; i++)
212 CLEAR_HARD_REG_SET (reg_class_contents[i]);
214 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
215 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
216 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
217 SET_HARD_REG_BIT (reg_class_contents[i], j);
220 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
221 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
222 bzero (global_regs, sizeof global_regs);
224 /* Compute number of hard regs in each class. */
226 bzero ((char *) reg_class_size, sizeof reg_class_size);
227 for (i = 0; i < N_REG_CLASSES; i++)
228 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
229 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
232 /* Initialize the table of subunions.
233 reg_class_subunion[I][J] gets the largest-numbered reg-class
234 that is contained in the union of classes I and J. */
236 for (i = 0; i < N_REG_CLASSES; i++)
238 for (j = 0; j < N_REG_CLASSES; j++)
241 register /* Declare it register if it's a scalar. */
246 COPY_HARD_REG_SET (c, reg_class_contents[i]);
247 IOR_HARD_REG_SET (c, reg_class_contents[j]);
248 for (k = 0; k < N_REG_CLASSES; k++)
250 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
255 /* keep the largest subclass */ /* SPEE 900308 */
256 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
257 reg_class_contents[(int) reg_class_subunion[i][j]],
259 reg_class_subunion[i][j] = (enum reg_class) k;
266 /* Initialize the table of superunions.
267 reg_class_superunion[I][J] gets the smallest-numbered reg-class
268 containing the union of classes I and J. */
270 for (i = 0; i < N_REG_CLASSES; i++)
272 for (j = 0; j < N_REG_CLASSES; j++)
275 register /* Declare it register if it's a scalar. */
280 COPY_HARD_REG_SET (c, reg_class_contents[i]);
281 IOR_HARD_REG_SET (c, reg_class_contents[j]);
282 for (k = 0; k < N_REG_CLASSES; k++)
283 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
286 reg_class_superunion[i][j] = (enum reg_class) k;
290 /* Initialize the tables of subclasses and superclasses of each reg class.
291 First clear the whole table, then add the elements as they are found. */
293 for (i = 0; i < N_REG_CLASSES; i++)
295 for (j = 0; j < N_REG_CLASSES; j++)
297 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
298 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
302 for (i = 0; i < N_REG_CLASSES; i++)
304 if (i == (int) NO_REGS)
307 for (j = i + 1; j < N_REG_CLASSES; j++)
311 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
315 /* Reg class I is a subclass of J.
316 Add J to the table of superclasses of I. */
317 p = ®_class_superclasses[i][0];
318 while (*p != LIM_REG_CLASSES) p++;
319 *p = (enum reg_class) j;
320 /* Add I to the table of superclasses of J. */
321 p = ®_class_subclasses[j][0];
322 while (*p != LIM_REG_CLASSES) p++;
323 *p = (enum reg_class) i;
327 /* Initialize the move cost table. Find every subset of each class
328 and take the maximum cost of moving any subset to any other. */
330 for (i = 0; i < N_REG_CLASSES; i++)
331 for (j = 0; j < N_REG_CLASSES; j++)
333 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
334 enum reg_class *p1, *p2;
336 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
338 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
340 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
343 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
345 for (p2 = ®_class_subclasses[j][0];
346 *p2 != LIM_REG_CLASSES; p2++)
348 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
351 move_cost[i][j] = cost;
353 if (reg_class_subset_p (i, j))
356 may_move_cost[i][j] = cost;
360 /* After switches have been processed, which perhaps alter
361 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
368 /* This macro allows the fixed or call-used registers
369 to depend on target flags. */
371 #ifdef CONDITIONAL_REGISTER_USAGE
372 CONDITIONAL_REGISTER_USAGE;
375 /* Initialize "constant" tables. */
377 CLEAR_HARD_REG_SET (fixed_reg_set);
378 CLEAR_HARD_REG_SET (call_used_reg_set);
379 CLEAR_HARD_REG_SET (call_fixed_reg_set);
381 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
383 n_non_fixed_regs = 0;
385 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
388 SET_HARD_REG_BIT (fixed_reg_set, i);
392 if (call_used_regs[i])
393 SET_HARD_REG_BIT (call_used_reg_set, i);
394 if (call_fixed_regs[i])
395 SET_HARD_REG_BIT (call_fixed_reg_set, i);
396 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
397 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
401 /* Compute the table of register modes.
402 These values are used to record death information for individual registers
403 (as opposed to a multi-register mode). */
410 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
412 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
414 /* If we couldn't find a valid mode, fall back to `word_mode'.
415 ??? We assume `word_mode' has already been initialized.
416 ??? One situation in which we need to do this is on the mips where
417 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
418 to use DF mode for the even registers and VOIDmode for the odd
419 (for the cpu models where the odd ones are inaccessible). */
420 if (reg_raw_mode[i] == VOIDmode)
421 reg_raw_mode[i] = word_mode;
425 /* Finish initializing the register sets and
426 initialize the register modes. */
431 /* This finishes what was started by init_reg_sets, but couldn't be done
432 until after register usage was specified. */
433 if (!output_bytecode)
439 /* Return a machine mode that is legitimate for hard reg REGNO and large
440 enough to save nregs. If we can't find one, return VOIDmode. */
443 choose_hard_reg_mode (regno, nregs)
447 enum machine_mode found_mode = VOIDmode, mode;
449 /* We first look for the largest integer mode that can be validly
450 held in REGNO. If none, we look for the largest floating-point mode.
451 If we still didn't find a valid mode, try CCmode. */
453 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
455 mode = GET_MODE_WIDER_MODE (mode))
456 if (HARD_REGNO_NREGS (regno, mode) == nregs
457 && HARD_REGNO_MODE_OK (regno, mode))
460 if (found_mode != VOIDmode)
463 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
465 mode = GET_MODE_WIDER_MODE (mode))
466 if (HARD_REGNO_NREGS (regno, mode) == nregs
467 && HARD_REGNO_MODE_OK (regno, mode))
470 if (found_mode != VOIDmode)
473 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
474 && HARD_REGNO_MODE_OK (regno, CCmode))
477 /* We can't find a mode valid for this register. */
481 /* Specify the usage characteristics of the register named NAME.
482 It should be a fixed register if FIXED and a
483 call-used register if CALL_USED. */
486 fix_register (name, fixed, call_used)
488 int fixed, call_used;
494 warning ("request to mark `%s' as %s ignored by bytecode compiler",
495 name, call_used ? "call-used" : "fixed");
499 /* Decode the name and update the primary form of
500 the register info. */
502 if ((i = decode_reg_name (name)) >= 0)
504 fixed_regs[i] = fixed;
505 call_used_regs[i] = call_used;
509 warning ("unknown register name: %s", name);
513 /* Mark register number I as global. */
521 warning ("register used for two global register variables");
525 if (call_used_regs[i] && ! fixed_regs[i])
526 warning ("call-clobbered register used for global register variable");
530 /* If already fixed, nothing else to do. */
534 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
537 SET_HARD_REG_BIT (fixed_reg_set, i);
538 SET_HARD_REG_BIT (call_used_reg_set, i);
539 SET_HARD_REG_BIT (call_fixed_reg_set, i);
542 /* Now the data and code for the `regclass' pass, which happens
543 just before local-alloc. */
545 /* The `costs' struct records the cost of using a hard register of each class
546 and of using memory for each pseudo. We use this data to set up
547 register class preferences. */
551 int cost[N_REG_CLASSES];
555 /* Record the cost of each class for each pseudo. */
557 static struct costs *costs;
559 /* Record the same data by operand number, accumulated for each alternative
560 in an insn. The contribution to a pseudo is that of the minimum-cost
563 static struct costs op_costs[MAX_RECOG_OPERANDS];
565 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
566 This is available after `regclass' is run. */
568 static char *prefclass;
570 /* altclass[R] is a register class that we should use for allocating
571 pseudo number R if no register in the preferred class is available.
572 If no register in this class is available, memory is preferred.
574 It might appear to be more general to have a bitmask of classes here,
575 but since it is recommended that there be a class corresponding to the
576 union of most major pair of classes, that generality is not required.
578 This is available after `regclass' is run. */
580 static char *altclass;
582 /* Record the depth of loops that we are in. */
584 static int loop_depth;
586 /* Account for the fact that insns within a loop are executed very commonly,
587 but don't keep doing this as loops go too deep. */
589 static int loop_cost;
591 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
593 static int copy_cost PROTO((rtx, enum machine_mode,
594 enum reg_class, int));
595 static void record_address_regs PROTO((rtx, enum reg_class, int));
596 static auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
597 static void reg_scan_mark_refs PROTO((rtx, rtx, int));
599 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
600 This function is sometimes called before the info has been computed.
601 When that happens, just return GENERAL_REGS, which is innocuous. */
604 reg_preferred_class (regno)
609 return (enum reg_class) prefclass[regno];
613 reg_alternate_class (regno)
618 return (enum reg_class) altclass[regno];
621 /* This prevents dump_flow_info from losing if called
622 before regclass is run. */
630 /* This is a pass of the compiler that scans all instructions
631 and calculates the preferred class for each pseudo-register.
632 This information can be accessed later by calling `reg_preferred_class'.
633 This pass comes just before local register allocation. */
640 #ifdef REGISTER_CONSTRAINTS
643 struct costs init_cost;
649 costs = (struct costs *) alloca (nregs * sizeof (struct costs));
651 #ifdef FORBIDDEN_INC_DEC_CLASSES
653 in_inc_dec = (char *) alloca (nregs);
655 /* Initialize information about which register classes can be used for
656 pseudos that are auto-incremented or auto-decremented. It would
657 seem better to put this in init_reg_sets, but we need to be able
658 to allocate rtx, which we can't do that early. */
660 for (i = 0; i < N_REG_CLASSES; i++)
662 rtx r = gen_rtx (REG, VOIDmode, 0);
665 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
666 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
670 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
671 m = (enum machine_mode) ((int) m + 1))
672 if (HARD_REGNO_MODE_OK (j, m))
676 /* If a register is not directly suitable for an
677 auto-increment or decrement addressing mode and
678 requires secondary reloads, disallow its class from
679 being used in such addresses. */
682 #ifdef SECONDARY_RELOAD_CLASS
683 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
686 #ifdef SECONDARY_INPUT_RELOAD_CLASS
687 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
690 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
691 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
696 && ! auto_inc_dec_reg_p (r, m))
697 forbidden_inc_dec_class[i] = 1;
701 #endif /* FORBIDDEN_INC_DEC_CLASSES */
703 init_cost.mem_cost = 10000;
704 for (i = 0; i < N_REG_CLASSES; i++)
705 init_cost.cost[i] = 10000;
707 /* Normally we scan the insns once and determine the best class to use for
708 each register. However, if -fexpensive_optimizations are on, we do so
709 twice, the second time using the tentative best classes to guide the
712 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
714 /* Zero out our accumulation of the cost of each class for each reg. */
716 bzero ((char *) costs, nregs * sizeof (struct costs));
718 #ifdef FORBIDDEN_INC_DEC_CLASSES
719 bzero (in_inc_dec, nregs);
722 loop_depth = 0, loop_cost = 1;
724 /* Scan the instructions and record each time it would
725 save code to put a certain register in a certain class. */
727 for (insn = f; insn; insn = NEXT_INSN (insn))
729 char *constraints[MAX_RECOG_OPERANDS];
730 enum machine_mode modes[MAX_RECOG_OPERANDS];
734 /* Show that an insn inside a loop is likely to be executed three
735 times more than insns outside a loop. This is much more aggressive
736 than the assumptions made elsewhere and is being tried as an
739 if (GET_CODE (insn) == NOTE
740 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
741 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
742 else if (GET_CODE (insn) == NOTE
743 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
744 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
746 else if ((GET_CODE (insn) == INSN
747 && GET_CODE (PATTERN (insn)) != USE
748 && GET_CODE (PATTERN (insn)) != CLOBBER
749 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
750 || (GET_CODE (insn) == JUMP_INSN
751 && GET_CODE (PATTERN (insn)) != ADDR_VEC
752 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
753 || GET_CODE (insn) == CALL_INSN)
755 if (GET_CODE (insn) == INSN
756 && (noperands = asm_noperands (PATTERN (insn))) >= 0)
758 decode_asm_operands (PATTERN (insn), recog_operand, NULL_PTR,
760 nalternatives = (noperands == 0 ? 0
761 : n_occurrences (',', constraints[0]) + 1);
765 int insn_code_number = recog_memoized (insn);
768 set = single_set (insn);
771 nalternatives = insn_n_alternatives[insn_code_number];
772 noperands = insn_n_operands[insn_code_number];
774 /* If this insn loads a parameter from its stack slot, then
775 it represents a savings, rather than a cost, if the
776 parameter is stored in memory. Record this fact. */
778 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
779 && GET_CODE (SET_SRC (set)) == MEM
780 && (note = find_reg_note (insn, REG_EQUIV,
782 && GET_CODE (XEXP (note, 0)) == MEM)
784 costs[REGNO (SET_DEST (set))].mem_cost
785 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)))
787 record_address_regs (XEXP (SET_SRC (set), 0),
788 BASE_REG_CLASS, loop_cost * 2);
792 /* Improve handling of two-address insns such as
793 (set X (ashift CONST Y)) where CONST must be made to
794 match X. Change it into two insns: (set X CONST)
795 (set X (ashift X Y)). If we left this for reloading, it
796 would probably get three insns because X and Y might go
797 in the same place. This prevents X and Y from receiving
800 We can only do this if the modes of operands 0 and 1
801 (which might not be the same) are tieable and we only need
802 do this during our first pass. */
804 if (pass == 0 && optimize
806 && insn_operand_constraint[insn_code_number][1][0] == '0'
807 && insn_operand_constraint[insn_code_number][1][1] == 0
808 && CONSTANT_P (recog_operand[1])
809 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
810 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
811 && GET_CODE (recog_operand[0]) == REG
812 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
813 insn_operand_mode[insn_code_number][1]))
815 rtx previnsn = prev_real_insn (insn);
817 = gen_lowpart (insn_operand_mode[insn_code_number][1],
820 = emit_insn_before (gen_move_insn (dest,
824 /* If this insn was the start of a basic block,
825 include the new insn in that block.
826 We need not check for code_label here;
827 while a basic block can start with a code_label,
828 INSN could not be at the beginning of that block. */
829 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
832 for (b = 0; b < n_basic_blocks; b++)
833 if (insn == basic_block_head[b])
834 basic_block_head[b] = newinsn;
837 /* This makes one more setting of new insns's dest. */
838 reg_n_sets[REGNO (recog_operand[0])]++;
840 *recog_operand_loc[1] = recog_operand[0];
841 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
842 if (recog_dup_num[i] == 1)
843 *recog_dup_loc[i] = recog_operand[0];
845 insn = PREV_INSN (newinsn);
849 for (i = 0; i < noperands; i++)
852 = insn_operand_constraint[insn_code_number][i];
853 modes[i] = insn_operand_mode[insn_code_number][i];
857 /* If we get here, we are set up to record the costs of all the
858 operands for this insn. Start by initializing the costs.
859 Then handle any address registers. Finally record the desired
860 classes for any pseudos, doing it twice if some pair of
861 operands are commutative. */
863 for (i = 0; i < noperands; i++)
865 op_costs[i] = init_cost;
867 if (GET_CODE (recog_operand[i]) == SUBREG)
868 recog_operand[i] = SUBREG_REG (recog_operand[i]);
870 if (GET_CODE (recog_operand[i]) == MEM)
871 record_address_regs (XEXP (recog_operand[i], 0),
872 BASE_REG_CLASS, loop_cost * 2);
873 else if (constraints[i][0] == 'p')
874 record_address_regs (recog_operand[i],
875 BASE_REG_CLASS, loop_cost * 2);
878 /* Check for commutative in a separate loop so everything will
879 have been initialized. We must do this even if one operand
880 is a constant--see addsi3 in m68k.md. */
882 for (i = 0; i < noperands - 1; i++)
883 if (constraints[i][0] == '%')
885 char *xconstraints[MAX_RECOG_OPERANDS];
888 /* Handle commutative operands by swapping the constraints.
889 We assume the modes are the same. */
891 for (j = 0; j < noperands; j++)
892 xconstraints[j] = constraints[j];
894 xconstraints[i] = constraints[i+1];
895 xconstraints[i+1] = constraints[i];
896 record_reg_classes (nalternatives, noperands,
897 recog_operand, modes, xconstraints,
901 record_reg_classes (nalternatives, noperands, recog_operand,
902 modes, constraints, insn);
904 /* Now add the cost for each operand to the total costs for
907 for (i = 0; i < noperands; i++)
908 if (GET_CODE (recog_operand[i]) == REG
909 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
911 int regno = REGNO (recog_operand[i]);
912 struct costs *p = &costs[regno], *q = &op_costs[i];
914 p->mem_cost += q->mem_cost * loop_cost;
915 for (j = 0; j < N_REG_CLASSES; j++)
916 p->cost[j] += q->cost[j] * loop_cost;
921 /* Now for each register look at how desirable each class is
922 and find which class is preferred. Store that in
923 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
924 class any of whose registers is better than memory. */
928 prefclass = (char *) oballoc (nregs);
929 altclass = (char *) oballoc (nregs);
932 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
934 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
935 enum reg_class best = ALL_REGS, alt = NO_REGS;
936 /* This is an enum reg_class, but we call it an int
937 to save lots of casts. */
939 register struct costs *p = &costs[i];
941 for (class = (int) ALL_REGS - 1; class > 0; class--)
943 /* Ignore classes that are too small for this operand or
944 invalid for a operand that was auto-incremented. */
945 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
946 > reg_class_size[class]
947 #ifdef FORBIDDEN_INC_DEC_CLASSES
948 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
952 else if (p->cost[class] < best_cost)
954 best_cost = p->cost[class];
955 best = (enum reg_class) class;
957 else if (p->cost[class] == best_cost)
958 best = reg_class_subunion[(int)best][class];
961 /* Record the alternate register class; i.e., a class for which
962 every register in it is better than using memory. If adding a
963 class would make a smaller class (i.e., no union of just those
964 classes exists), skip that class. The major unions of classes
965 should be provided as a register class. Don't do this if we
966 will be doing it again later. */
968 if (pass == 1 || ! flag_expensive_optimizations)
969 for (class = 0; class < N_REG_CLASSES; class++)
970 if (p->cost[class] < p->mem_cost
971 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
972 > reg_class_size[(int) alt])
973 #ifdef FORBIDDEN_INC_DEC_CLASSES
974 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
977 alt = reg_class_subunion[(int) alt][class];
979 /* If we don't add any classes, nothing to try. */
983 /* We cast to (int) because (char) hits bugs in some compilers. */
984 prefclass[i] = (int) best;
985 altclass[i] = (int) alt;
988 #endif /* REGISTER_CONSTRAINTS */
991 #ifdef REGISTER_CONSTRAINTS
993 /* Record the cost of using memory or registers of various classes for
994 the operands in INSN.
996 N_ALTS is the number of alternatives.
998 N_OPS is the number of operands.
1000 OPS is an array of the operands.
1002 MODES are the modes of the operands, in case any are VOIDmode.
1004 CONSTRAINTS are the constraints to use for the operands. This array
1005 is modified by this procedure.
1007 This procedure works alternative by alternative. For each alternative
1008 we assume that we will be able to allocate all pseudos to their ideal
1009 register class and calculate the cost of using that alternative. Then
1010 we compute for each operand that is a pseudo-register, the cost of
1011 having the pseudo allocated to each register class and using it in that
1012 alternative. To this cost is added the cost of the alternative.
1014 The cost of each class for this insn is its lowest cost among all the
1018 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
1022 enum machine_mode *modes;
1027 enum op_type {OP_READ, OP_WRITE, OP_READ_WRITE} op_types[MAX_RECOG_OPERANDS];
1031 /* By default, each operand is an input operand. */
1033 for (i = 0; i < n_ops; i++)
1034 op_types[i] = OP_READ;
1036 /* Process each alternative, each time minimizing an operand's cost with
1037 the cost for each operand in that alternative. */
1039 for (alt = 0; alt < n_alts; alt++)
1041 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1044 enum reg_class classes[MAX_RECOG_OPERANDS];
1047 for (i = 0; i < n_ops; i++)
1049 char *p = constraints[i];
1051 enum machine_mode mode = modes[i];
1056 /* If this operand has no constraints at all, we can conclude
1057 nothing about it since anything is valid. */
1061 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1062 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1070 /* If this alternative is only relevant when this operand
1071 matches a previous operand, we do different things depending
1072 on whether this operand is a pseudo-reg or not. */
1074 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1077 classes[i] = classes[j];
1079 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1081 /* If this matches the other operand, we have no added
1083 if (rtx_equal_p (ops[j], op))
1086 /* If we can put the other operand into a register, add to
1087 the cost of this alternative the cost to copy this
1088 operand to the register used for the other operand. */
1090 else if (classes[j] != NO_REGS)
1091 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1093 else if (GET_CODE (ops[j]) != REG
1094 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1096 /* This op is a pseudo but the one it matches is not. */
1098 /* If we can't put the other operand into a register, this
1099 alternative can't be used. */
1101 if (classes[j] == NO_REGS)
1104 /* Otherwise, add to the cost of this alternative the cost
1105 to copy the other operand to the register used for this
1109 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1113 /* The costs of this operand are the same as that of the
1114 other operand. However, if we cannot tie them, this
1115 alternative needs to do a copy, which is one
1118 this_op_costs[i] = this_op_costs[j];
1119 if (REGNO (ops[i]) != REGNO (ops[j])
1120 && ! find_reg_note (insn, REG_DEAD, op))
1123 /* This is in place of ordinary cost computation
1124 for this operand, so skip to the end of the
1125 alternative (should be just one character). */
1126 while (*p && *p++ != ',')
1134 /* Scan all the constraint letters. See if the operand matches
1135 any of the constraints. Collect the valid register classes
1136 and see if this operand accepts memory. */
1138 classes[i] = NO_REGS;
1139 while (*p && (c = *p++) != ',')
1143 op_types[i] = OP_WRITE;
1147 op_types[i] = OP_READ_WRITE;
1151 /* Ignore the next letter for this pass. */
1156 case '?': case '!': case '#':
1158 case '0': case '1': case '2': case '3': case '4':
1162 case 'm': case 'o': case 'V':
1163 /* It doesn't seem worth distinguishing between offsettable
1164 and non-offsettable addresses here. */
1166 if (GET_CODE (op) == MEM)
1171 if (GET_CODE (op) == MEM
1172 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1173 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1178 if (GET_CODE (op) == MEM
1179 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1180 || GET_CODE (XEXP (op, 0)) == POST_INC))
1185 #ifndef REAL_ARITHMETIC
1186 /* Match any floating double constant, but only if
1187 we can examine the bits of it reliably. */
1188 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1189 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1190 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1193 if (GET_CODE (op) == CONST_DOUBLE)
1198 if (GET_CODE (op) == CONST_DOUBLE)
1204 if (GET_CODE (op) == CONST_DOUBLE
1205 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1210 if (GET_CODE (op) == CONST_INT
1211 || (GET_CODE (op) == CONST_DOUBLE
1212 && GET_MODE (op) == VOIDmode))
1216 #ifdef LEGITIMATE_PIC_OPERAND_P
1217 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1224 if (GET_CODE (op) == CONST_INT
1225 || (GET_CODE (op) == CONST_DOUBLE
1226 && GET_MODE (op) == VOIDmode))
1238 if (GET_CODE (op) == CONST_INT
1239 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1247 #ifdef EXTRA_CONSTRAINT
1253 if (EXTRA_CONSTRAINT (op, c))
1259 if (GET_CODE (op) == MEM
1261 #ifdef LEGITIMATE_PIC_OPERAND_P
1262 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1269 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1274 = reg_class_subunion[(int) classes[i]]
1275 [(int) REG_CLASS_FROM_LETTER (c)];
1280 /* How we account for this operand now depends on whether it is a
1281 pseudo register or not. If it is, we first check if any
1282 register classes are valid. If not, we ignore this alternative,
1283 since we want to assume that all pseudos get allocated for
1284 register preferencing. If some register class is valid, compute
1285 the costs of moving the pseudo into that class. */
1287 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1289 if (classes[i] == NO_REGS)
1293 struct costs *pp = &this_op_costs[i];
1295 for (class = 0; class < N_REG_CLASSES; class++)
1296 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1298 /* If the alternative actually allows memory, make things
1299 a bit cheaper since we won't need an extra insn to
1302 pp->mem_cost = MEMORY_MOVE_COST (mode) - allows_mem;
1304 /* If we have assigned a class to this register in our
1305 first pass, add a cost to this alternative corresponding
1306 to what we would add if this register were not in the
1307 appropriate class. */
1311 += may_move_cost[prefclass[REGNO (op)]][(int) classes[i]];
1315 /* Otherwise, if this alternative wins, either because we
1316 have already determined that or if we have a hard register of
1317 the proper class, there is no cost for this alternative. */
1320 || (GET_CODE (op) == REG
1321 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1324 /* If registers are valid, the cost of this alternative includes
1325 copying the object to and/or from a register. */
1327 else if (classes[i] != NO_REGS)
1329 if (op_types[i] != OP_WRITE)
1330 alt_cost += copy_cost (op, mode, classes[i], 1);
1332 if (op_types[i] != OP_READ)
1333 alt_cost += copy_cost (op, mode, classes[i], 0);
1336 /* The only other way this alternative can be used is if this is a
1337 constant that could be placed into memory. */
1339 else if (CONSTANT_P (op) && allows_mem)
1340 alt_cost += MEMORY_MOVE_COST (mode);
1348 /* Finally, update the costs with the information we've calculated
1349 about this alternative. */
1351 for (i = 0; i < n_ops; i++)
1352 if (GET_CODE (ops[i]) == REG
1353 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1355 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1356 int scale = 1 + (op_types[i] == OP_READ_WRITE);
1358 pp->mem_cost = MIN (pp->mem_cost,
1359 (qq->mem_cost + alt_cost) * scale);
1361 for (class = 0; class < N_REG_CLASSES; class++)
1362 pp->cost[class] = MIN (pp->cost[class],
1363 (qq->cost[class] + alt_cost) * scale);
1367 /* If this insn is a single set copying operand 1 to operand 0
1368 and one is a pseudo with the other a hard reg that is in its
1369 own register class, set the cost of that register class to -1. */
1371 if ((set = single_set (insn)) != 0
1372 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1373 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1374 for (i = 0; i <= 1; i++)
1375 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1377 int regno = REGNO (ops[!i]);
1378 enum machine_mode mode = GET_MODE (ops[!i]);
1382 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1383 && (reg_class_size[prefclass[regno]]
1384 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1385 op_costs[i].cost[prefclass[regno]] = -1;
1386 else if (regno < FIRST_PSEUDO_REGISTER)
1387 for (class = 0; class < N_REG_CLASSES; class++)
1388 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1389 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1391 if (reg_class_size[class] == 1)
1392 op_costs[i].cost[class] = -1;
1395 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1397 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1401 if (nr == HARD_REGNO_NREGS(regno,mode))
1402 op_costs[i].cost[class] = -1;
1408 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1409 TO_P is zero) a register of class CLASS in mode MODE.
1411 X must not be a pseudo. */
1414 copy_cost (x, mode, class, to_p)
1416 enum machine_mode mode;
1417 enum reg_class class;
1420 enum reg_class secondary_class = NO_REGS;
1422 /* If X is a SCRATCH, there is actually nothing to move since we are
1423 assuming optimal allocation. */
1425 if (GET_CODE (x) == SCRATCH)
1428 /* Get the class we will actually use for a reload. */
1429 class = PREFERRED_RELOAD_CLASS (x, class);
1431 #ifdef HAVE_SECONDARY_RELOADS
1432 /* If we need a secondary reload (we assume here that we are using
1433 the secondary reload as an intermediate, not a scratch register), the
1434 cost is that to load the input into the intermediate register, then
1435 to copy them. We use a special value of TO_P to avoid recursion. */
1437 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1439 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1442 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1444 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1447 if (secondary_class != NO_REGS)
1448 return (move_cost[(int) secondary_class][(int) class]
1449 + copy_cost (x, mode, secondary_class, 2));
1450 #endif /* HAVE_SECONDARY_RELOADS */
1452 /* For memory, use the memory move cost, for (hard) registers, use the
1453 cost to move between the register classes, and use 2 for everything
1454 else (constants). */
1456 if (GET_CODE (x) == MEM || class == NO_REGS)
1457 return MEMORY_MOVE_COST (mode);
1459 else if (GET_CODE (x) == REG)
1460 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1463 /* If this is a constant, we may eventually want to call rtx_cost here. */
1467 /* Record the pseudo registers we must reload into hard registers
1468 in a subexpression of a memory address, X.
1470 CLASS is the class that the register needs to be in and is either
1471 BASE_REG_CLASS or INDEX_REG_CLASS.
1473 SCALE is twice the amount to multiply the cost by (it is twice so we
1474 can represent half-cost adjustments). */
1477 record_address_regs (x, class, scale)
1479 enum reg_class class;
1482 register enum rtx_code code = GET_CODE (x);
1495 /* When we have an address that is a sum,
1496 we must determine whether registers are "base" or "index" regs.
1497 If there is a sum of two registers, we must choose one to be
1498 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1499 to make a good choice most of the time. We only need to do this
1500 on machines that can have two registers in an address and where
1501 the base and index register classes are different.
1503 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1504 that seems bogus since it should only be set when we are sure
1505 the register is being used as a pointer. */
1508 rtx arg0 = XEXP (x, 0);
1509 rtx arg1 = XEXP (x, 1);
1510 register enum rtx_code code0 = GET_CODE (arg0);
1511 register enum rtx_code code1 = GET_CODE (arg1);
1513 /* Look inside subregs. */
1514 if (code0 == SUBREG)
1515 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1516 if (code1 == SUBREG)
1517 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1519 /* If this machine only allows one register per address, it must
1520 be in the first operand. */
1522 if (MAX_REGS_PER_ADDRESS == 1)
1523 record_address_regs (arg0, class, scale);
1525 /* If index and base registers are the same on this machine, just
1526 record registers in any non-constant operands. We assume here,
1527 as well as in the tests below, that all addresses are in
1530 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1532 record_address_regs (arg0, class, scale);
1533 if (! CONSTANT_P (arg1))
1534 record_address_regs (arg1, class, scale);
1537 /* If the second operand is a constant integer, it doesn't change
1538 what class the first operand must be. */
1540 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1541 record_address_regs (arg0, class, scale);
1543 /* If the second operand is a symbolic constant, the first operand
1544 must be an index register. */
1546 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1547 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1549 /* If this the sum of two registers where the first is known to be a
1550 pointer, it must be a base register with the second an index. */
1552 else if (code0 == REG && code1 == REG
1553 && REGNO_POINTER_FLAG (REGNO (arg0)))
1555 record_address_regs (arg0, BASE_REG_CLASS, scale);
1556 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1559 /* If this is the sum of two registers and neither is known to
1560 be a pointer, count equal chances that each might be a base
1561 or index register. This case should be rare. */
1563 else if (code0 == REG && code1 == REG
1564 && ! REGNO_POINTER_FLAG (REGNO (arg0))
1565 && ! REGNO_POINTER_FLAG (REGNO (arg1)))
1567 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1568 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1569 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1570 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1573 /* In all other cases, the first operand is an index and the
1574 second is the base. */
1578 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1579 record_address_regs (arg1, BASE_REG_CLASS, scale);
1588 /* Double the importance of a pseudo register that is incremented
1589 or decremented, since it would take two extra insns
1590 if it ends up in the wrong place. If the operand is a pseudo,
1591 show it is being used in an INC_DEC context. */
1593 #ifdef FORBIDDEN_INC_DEC_CLASSES
1594 if (GET_CODE (XEXP (x, 0)) == REG
1595 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1596 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1599 record_address_regs (XEXP (x, 0), class, 2 * scale);
1604 register struct costs *pp = &costs[REGNO (x)];
1607 pp->mem_cost += (MEMORY_MOVE_COST (Pmode) * scale) / 2;
1609 for (i = 0; i < N_REG_CLASSES; i++)
1610 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1616 register char *fmt = GET_RTX_FORMAT (code);
1618 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1620 record_address_regs (XEXP (x, i), class, scale);
1625 #ifdef FORBIDDEN_INC_DEC_CLASSES
1627 /* Return 1 if REG is valid as an auto-increment memory reference
1628 to an object of MODE. */
1631 auto_inc_dec_reg_p (reg, mode)
1633 enum machine_mode mode;
1635 #ifdef HAVE_POST_INCREMENT
1636 if (memory_address_p (mode, gen_rtx (POST_INC, Pmode, reg)))
1640 #ifdef HAVE_POST_DECREMENT
1641 if (memory_address_p (mode, gen_rtx (POST_DEC, Pmode, reg)))
1645 #ifdef HAVE_PRE_INCREMENT
1646 if (memory_address_p (mode, gen_rtx (PRE_INC, Pmode, reg)))
1650 #ifdef HAVE_PRE_DECREMENT
1651 if (memory_address_p (mode, gen_rtx (PRE_DEC, Pmode, reg)))
1659 #endif /* REGISTER_CONSTRAINTS */
1661 /* This is the `regscan' pass of the compiler, run just before cse
1662 and again just before loop.
1664 It finds the first and last use of each pseudo-register
1665 and records them in the vectors regno_first_uid, regno_last_uid
1666 and counts the number of sets in the vector reg_n_sets.
1668 REPEAT is nonzero the second time this is called. */
1670 /* Indexed by pseudo register number, gives uid of first insn using the reg
1671 (as of the time reg_scan is called). */
1673 int *regno_first_uid;
1675 /* Indexed by pseudo register number, gives uid of last insn using the reg
1676 (as of the time reg_scan is called). */
1678 int *regno_last_uid;
1680 /* Indexed by pseudo register number, gives uid of last insn using the reg
1681 or mentioning it in a note (as of the time reg_scan is called). */
1683 int *regno_last_note_uid;
1685 /* Record the number of registers we used when we allocated the above two
1686 tables. If we are called again with more than this, we must re-allocate
1689 static int highest_regno_in_uid_map;
1691 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1692 Always at least 3, since the combiner could put that many together
1693 and we want this to remain correct for all the remaining passes. */
1698 reg_scan (f, nregs, repeat)
1705 if (!repeat || nregs > highest_regno_in_uid_map)
1707 /* Leave some spare space in case more regs are allocated. */
1708 highest_regno_in_uid_map = nregs + nregs / 20;
1710 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1712 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1714 = (int *) oballoc (highest_regno_in_uid_map * sizeof (int));
1716 = (short *) oballoc (highest_regno_in_uid_map * sizeof (short));
1719 bzero ((char *) regno_first_uid, highest_regno_in_uid_map * sizeof (int));
1720 bzero ((char *) regno_last_uid, highest_regno_in_uid_map * sizeof (int));
1721 bzero ((char *) regno_last_note_uid,
1722 highest_regno_in_uid_map * sizeof (int));
1723 bzero ((char *) reg_n_sets, highest_regno_in_uid_map * sizeof (short));
1727 for (insn = f; insn; insn = NEXT_INSN (insn))
1728 if (GET_CODE (insn) == INSN
1729 || GET_CODE (insn) == CALL_INSN
1730 || GET_CODE (insn) == JUMP_INSN)
1732 if (GET_CODE (PATTERN (insn)) == PARALLEL
1733 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1734 max_parallel = XVECLEN (PATTERN (insn), 0);
1735 reg_scan_mark_refs (PATTERN (insn), insn, 0);
1737 if (REG_NOTES (insn))
1738 reg_scan_mark_refs (REG_NOTES (insn), insn, 1);
1742 /* X is the expression to scan. INSN is the insn it appears in.
1743 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */
1746 reg_scan_mark_refs (x, insn, note_flag)
1751 register enum rtx_code code = GET_CODE (x);
1770 register int regno = REGNO (x);
1772 regno_last_note_uid[regno] = INSN_UID (insn);
1774 regno_last_uid[regno] = INSN_UID (insn);
1775 if (regno_first_uid[regno] == 0)
1776 regno_first_uid[regno] = INSN_UID (insn);
1782 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag);
1784 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1789 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag);
1793 /* Count a set of the destination if it is a register. */
1794 for (dest = SET_DEST (x);
1795 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
1796 || GET_CODE (dest) == ZERO_EXTEND;
1797 dest = XEXP (dest, 0))
1800 if (GET_CODE (dest) == REG)
1801 reg_n_sets[REGNO (dest)]++;
1803 /* If this is setting a pseudo from another pseudo or the sum of a
1804 pseudo and a constant integer and the other pseudo is known to be
1805 a pointer, set the destination to be a pointer as well.
1807 Likewise if it is setting the destination from an address or from a
1808 value equivalent to an address or to the sum of an address and
1811 But don't do any of this if the pseudo corresponds to a user
1812 variable since it should have already been set as a pointer based
1815 if (GET_CODE (SET_DEST (x)) == REG
1816 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
1817 && ! REG_USERVAR_P (SET_DEST (x))
1818 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
1819 && ((GET_CODE (SET_SRC (x)) == REG
1820 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
1821 || ((GET_CODE (SET_SRC (x)) == PLUS
1822 || GET_CODE (SET_SRC (x)) == LO_SUM)
1823 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
1824 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
1825 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
1826 || GET_CODE (SET_SRC (x)) == CONST
1827 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
1828 || GET_CODE (SET_SRC (x)) == LABEL_REF
1829 || (GET_CODE (SET_SRC (x)) == HIGH
1830 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
1831 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
1832 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
1833 || ((GET_CODE (SET_SRC (x)) == PLUS
1834 || GET_CODE (SET_SRC (x)) == LO_SUM)
1835 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
1836 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
1837 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
1838 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
1839 && (GET_CODE (XEXP (note, 0)) == CONST
1840 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
1841 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
1842 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
1844 /* ... fall through ... */
1848 register char *fmt = GET_RTX_FORMAT (code);
1850 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1853 reg_scan_mark_refs (XEXP (x, i), insn, note_flag);
1854 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
1857 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1858 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag);
1865 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1869 reg_class_subset_p (c1, c2)
1870 register enum reg_class c1;
1871 register enum reg_class c2;
1873 if (c1 == c2) return 1;
1878 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
1879 reg_class_contents[(int)c2],
1884 /* Return nonzero if there is a register that is in both C1 and C2. */
1887 reg_classes_intersect_p (c1, c2)
1888 register enum reg_class c1;
1889 register enum reg_class c2;
1896 if (c1 == c2) return 1;
1898 if (c1 == ALL_REGS || c2 == ALL_REGS)
1901 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
1902 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
1904 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);