1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
31 #include "hard-reg-set.h"
33 #include "basic-block.h"
36 #include "insn-config.h"
44 #ifndef REGISTER_MOVE_COST
45 #define REGISTER_MOVE_COST(x, y) 2
48 static void init_reg_sets_1 PARAMS ((void));
49 static void init_reg_modes PARAMS ((void));
51 /* If we have auto-increment or auto-decrement and we can have secondary
52 reloads, we are not allowed to use classes requiring secondary
53 reloads for pseudos auto-incremented since reload can't handle it. */
56 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
57 #define FORBIDDEN_INC_DEC_CLASSES
61 /* Register tables used by many passes. */
63 /* Indexed by hard register number, contains 1 for registers
64 that are fixed use (stack pointer, pc, frame pointer, etc.).
65 These are the registers that cannot be used to allocate
66 a pseudo reg for general use. */
68 char fixed_regs[FIRST_PSEUDO_REGISTER];
70 /* Same info as a HARD_REG_SET. */
72 HARD_REG_SET fixed_reg_set;
74 /* Data for initializing the above. */
76 static char initial_fixed_regs[] = FIXED_REGISTERS;
78 /* Indexed by hard register number, contains 1 for registers
79 that are fixed use or are clobbered by function calls.
80 These are the registers that cannot be used to allocate
81 a pseudo reg whose life crosses calls unless we are able
82 to save/restore them across the calls. */
84 char call_used_regs[FIRST_PSEUDO_REGISTER];
86 /* Same info as a HARD_REG_SET. */
88 HARD_REG_SET call_used_reg_set;
90 /* HARD_REG_SET of registers we want to avoid caller saving. */
91 HARD_REG_SET losing_caller_save_reg_set;
93 /* Data for initializing the above. */
95 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
97 /* Indexed by hard register number, contains 1 for registers that are
98 fixed use or call used registers that cannot hold quantities across
99 calls even if we are willing to save and restore them. call fixed
100 registers are a subset of call used registers. */
102 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
104 /* The same info as a HARD_REG_SET. */
106 HARD_REG_SET call_fixed_reg_set;
108 /* Number of non-fixed registers. */
110 int n_non_fixed_regs;
112 /* Indexed by hard register number, contains 1 for registers
113 that are being used for global register decls.
114 These must be exempt from ordinary flow analysis
115 and are also considered fixed. */
117 char global_regs[FIRST_PSEUDO_REGISTER];
119 /* Table of register numbers in the order in which to try to use them. */
120 #ifdef REG_ALLOC_ORDER
121 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
123 /* The inverse of reg_alloc_order. */
124 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
127 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
129 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
131 /* The same information, but as an array of unsigned ints. We copy from
132 these unsigned ints to the table above. We do this so the tm.h files
133 do not have to be aware of the wordsize for machines with <= 64 regs. */
136 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
138 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
139 = REG_CLASS_CONTENTS;
141 /* For each reg class, number of regs it contains. */
143 unsigned int reg_class_size[N_REG_CLASSES];
145 /* For each reg class, table listing all the containing classes. */
147 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
149 /* For each reg class, table listing all the classes contained in it. */
151 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
153 /* For each pair of reg classes,
154 a largest reg class contained in their union. */
156 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
158 /* For each pair of reg classes,
159 the smallest reg class containing their union. */
161 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
163 /* Array containing all of the register names. Unless
164 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
166 #ifdef DEBUG_REGISTER_NAMES
167 const char * reg_names[] = REGISTER_NAMES;
170 /* For each hard register, the widest mode object that it can contain.
171 This will be a MODE_INT mode if the register can hold integers. Otherwise
172 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
175 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
177 /* Maximum cost of moving from a register in one class to a register in
178 another class. Based on REGISTER_MOVE_COST. */
180 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
182 /* Similar, but here we don't have to move if the first index is a subset
183 of the second so in that case the cost is zero. */
185 static int may_move_in_cost[N_REG_CLASSES][N_REG_CLASSES];
187 /* Similar, but here we don't have to move if the first index is a superset
188 of the second so in that case the cost is zero. */
190 static int may_move_out_cost[N_REG_CLASSES][N_REG_CLASSES];
192 #ifdef FORBIDDEN_INC_DEC_CLASSES
194 /* These are the classes that regs which are auto-incremented or decremented
197 static int forbidden_inc_dec_class[N_REG_CLASSES];
199 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
202 static char *in_inc_dec;
204 #endif /* FORBIDDEN_INC_DEC_CLASSES */
206 #ifdef CLASS_CANNOT_CHANGE_MODE
208 /* These are the classes containing only registers that can be used in
209 a SUBREG expression that changes the mode of the register in some
210 way that is illegal. */
212 static int class_can_change_mode[N_REG_CLASSES];
214 /* Registers, including pseudos, which change modes in some way that
217 static regset reg_changes_mode;
219 #endif /* CLASS_CANNOT_CHANGE_MODE */
221 #ifdef HAVE_SECONDARY_RELOADS
223 /* Sample MEM values for use by memory_move_secondary_cost. */
225 static rtx top_of_stack[MAX_MACHINE_MODE];
227 #endif /* HAVE_SECONDARY_RELOADS */
229 /* Linked list of reg_info structures allocated for reg_n_info array.
230 Grouping all of the allocated structures together in one lump
231 means only one call to bzero to clear them, rather than n smaller
233 struct reg_info_data {
234 struct reg_info_data *next; /* next set of reg_info structures */
235 size_t min_index; /* minimum index # */
236 size_t max_index; /* maximum index # */
237 char used_p; /* non-zero if this has been used previously */
238 reg_info data[1]; /* beginning of the reg_info data */
241 static struct reg_info_data *reg_info_head;
243 /* No more global register variables may be declared; true once
244 regclass has been initialized. */
246 static int no_global_reg_vars = 0;
249 /* Function called only once to initialize the above data on reg usage.
250 Once this is done, various switches may override. */
257 /* First copy the register information from the initial int form into
260 for (i = 0; i < N_REG_CLASSES; i++)
262 CLEAR_HARD_REG_SET (reg_class_contents[i]);
264 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
265 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
266 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
267 SET_HARD_REG_BIT (reg_class_contents[i], j);
270 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
271 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
272 bzero (global_regs, sizeof global_regs);
274 /* Do any additional initialization regsets may need */
275 INIT_ONCE_REG_SET ();
277 #ifdef REG_ALLOC_ORDER
278 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
279 inv_reg_alloc_order[reg_alloc_order[i]] = i;
283 /* After switches have been processed, which perhaps alter
284 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
289 register unsigned int i, j;
291 /* This macro allows the fixed or call-used registers
292 and the register classes to depend on target flags. */
294 #ifdef CONDITIONAL_REGISTER_USAGE
295 CONDITIONAL_REGISTER_USAGE;
298 /* Compute number of hard regs in each class. */
300 bzero ((char *) reg_class_size, sizeof reg_class_size);
301 for (i = 0; i < N_REG_CLASSES; i++)
302 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
303 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
306 /* Initialize the table of subunions.
307 reg_class_subunion[I][J] gets the largest-numbered reg-class
308 that is contained in the union of classes I and J. */
310 for (i = 0; i < N_REG_CLASSES; i++)
312 for (j = 0; j < N_REG_CLASSES; j++)
315 register /* Declare it register if it's a scalar. */
320 COPY_HARD_REG_SET (c, reg_class_contents[i]);
321 IOR_HARD_REG_SET (c, reg_class_contents[j]);
322 for (k = 0; k < N_REG_CLASSES; k++)
324 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
329 /* keep the largest subclass */ /* SPEE 900308 */
330 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
331 reg_class_contents[(int) reg_class_subunion[i][j]],
333 reg_class_subunion[i][j] = (enum reg_class) k;
340 /* Initialize the table of superunions.
341 reg_class_superunion[I][J] gets the smallest-numbered reg-class
342 containing the union of classes I and J. */
344 for (i = 0; i < N_REG_CLASSES; i++)
346 for (j = 0; j < N_REG_CLASSES; j++)
349 register /* Declare it register if it's a scalar. */
354 COPY_HARD_REG_SET (c, reg_class_contents[i]);
355 IOR_HARD_REG_SET (c, reg_class_contents[j]);
356 for (k = 0; k < N_REG_CLASSES; k++)
357 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
360 reg_class_superunion[i][j] = (enum reg_class) k;
364 /* Initialize the tables of subclasses and superclasses of each reg class.
365 First clear the whole table, then add the elements as they are found. */
367 for (i = 0; i < N_REG_CLASSES; i++)
369 for (j = 0; j < N_REG_CLASSES; j++)
371 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
372 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
376 for (i = 0; i < N_REG_CLASSES; i++)
378 if (i == (int) NO_REGS)
381 for (j = i + 1; j < N_REG_CLASSES; j++)
385 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
389 /* Reg class I is a subclass of J.
390 Add J to the table of superclasses of I. */
391 p = ®_class_superclasses[i][0];
392 while (*p != LIM_REG_CLASSES) p++;
393 *p = (enum reg_class) j;
394 /* Add I to the table of superclasses of J. */
395 p = ®_class_subclasses[j][0];
396 while (*p != LIM_REG_CLASSES) p++;
397 *p = (enum reg_class) i;
401 /* Initialize "constant" tables. */
403 CLEAR_HARD_REG_SET (fixed_reg_set);
404 CLEAR_HARD_REG_SET (call_used_reg_set);
405 CLEAR_HARD_REG_SET (call_fixed_reg_set);
407 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
409 n_non_fixed_regs = 0;
411 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
414 SET_HARD_REG_BIT (fixed_reg_set, i);
418 if (call_used_regs[i])
419 SET_HARD_REG_BIT (call_used_reg_set, i);
420 if (call_fixed_regs[i])
421 SET_HARD_REG_BIT (call_fixed_reg_set, i);
422 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
423 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
426 /* Initialize the move cost table. Find every subset of each class
427 and take the maximum cost of moving any subset to any other. */
429 for (i = 0; i < N_REG_CLASSES; i++)
430 for (j = 0; j < N_REG_CLASSES; j++)
432 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
433 enum reg_class *p1, *p2;
435 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
437 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
439 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
442 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
444 for (p2 = ®_class_subclasses[j][0];
445 *p2 != LIM_REG_CLASSES; p2++)
447 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
450 move_cost[i][j] = cost;
452 if (reg_class_subset_p (i, j))
453 may_move_in_cost[i][j] = 0;
455 may_move_in_cost[i][j] = cost;
457 if (reg_class_subset_p (j, i))
458 may_move_out_cost[i][j] = 0;
460 may_move_out_cost[i][j] = cost;
463 #ifdef CLASS_CANNOT_CHANGE_MODE
466 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]);
468 for (i = 0; i < N_REG_CLASSES; i++)
470 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
471 class_can_change_mode [i] = 0;
474 class_can_change_mode [i] = 1;
477 #endif /* CLASS_CANNOT_CHANGE_MODE */
480 /* Compute the table of register modes.
481 These values are used to record death information for individual registers
482 (as opposed to a multi-register mode). */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
493 /* If we couldn't find a valid mode, just use the previous mode.
494 ??? One situation in which we need to do this is on the mips where
495 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
496 to use DF mode for the even registers and VOIDmode for the odd
497 (for the cpu models where the odd ones are inaccessible). */
498 if (reg_raw_mode[i] == VOIDmode)
499 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
503 /* Finish initializing the register sets and
504 initialize the register modes. */
509 /* This finishes what was started by init_reg_sets, but couldn't be done
510 until after register usage was specified. */
515 #ifdef HAVE_SECONDARY_RELOADS
517 /* Make some fake stack-frame MEM references for use in
518 memory_move_secondary_cost. */
521 for (i = 0; i < MAX_MACHINE_MODE; i++)
522 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
523 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
528 #ifdef HAVE_SECONDARY_RELOADS
530 /* Compute extra cost of moving registers to/from memory due to reloads.
531 Only needed if secondary reloads are required for memory moves. */
534 memory_move_secondary_cost (mode, class, in)
535 enum machine_mode mode;
536 enum reg_class class;
539 enum reg_class altclass;
540 int partial_cost = 0;
541 /* We need a memory reference to feed to SECONDARY... macros. */
542 /* mem may be unused even if the SECONDARY_ macros are defined. */
543 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
548 #ifdef SECONDARY_INPUT_RELOAD_CLASS
549 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
556 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
557 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
563 if (altclass == NO_REGS)
567 partial_cost = REGISTER_MOVE_COST (altclass, class);
569 partial_cost = REGISTER_MOVE_COST (class, altclass);
571 if (class == altclass)
572 /* This isn't simply a copy-to-temporary situation. Can't guess
573 what it is, so MEMORY_MOVE_COST really ought not to be calling
576 I'm tempted to put in an abort here, but returning this will
577 probably only give poor estimates, which is what we would've
578 had before this code anyways. */
581 /* Check if the secondary reload register will also need a
583 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
587 /* Return a machine mode that is legitimate for hard reg REGNO and large
588 enough to save nregs. If we can't find one, return VOIDmode. */
591 choose_hard_reg_mode (regno, nregs)
592 unsigned int regno ATTRIBUTE_UNUSED;
595 enum machine_mode found_mode = VOIDmode, mode;
597 /* We first look for the largest integer mode that can be validly
598 held in REGNO. If none, we look for the largest floating-point mode.
599 If we still didn't find a valid mode, try CCmode. */
601 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
603 mode = GET_MODE_WIDER_MODE (mode))
604 if (HARD_REGNO_NREGS (regno, mode) == nregs
605 && HARD_REGNO_MODE_OK (regno, mode))
608 if (found_mode != VOIDmode)
611 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
613 mode = GET_MODE_WIDER_MODE (mode))
614 if (HARD_REGNO_NREGS (regno, mode) == nregs
615 && HARD_REGNO_MODE_OK (regno, mode))
618 if (found_mode != VOIDmode)
621 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
622 && HARD_REGNO_MODE_OK (regno, CCmode))
625 /* We can't find a mode valid for this register. */
629 /* Specify the usage characteristics of the register named NAME.
630 It should be a fixed register if FIXED and a
631 call-used register if CALL_USED. */
634 fix_register (name, fixed, call_used)
636 int fixed, call_used;
640 /* Decode the name and update the primary form of
641 the register info. */
643 if ((i = decode_reg_name (name)) >= 0)
645 if ((i == STACK_POINTER_REGNUM
646 #ifdef HARD_FRAME_POINTER_REGNUM
647 || i == HARD_FRAME_POINTER_REGNUM
649 || i == FRAME_POINTER_REGNUM
652 && (fixed == 0 || call_used == 0))
654 static const char * const what_option[2][2] = {
655 { "call-saved", "call-used" },
656 { "no-such-option", "fixed" }};
658 error ("can't use '%s' as a %s register", name,
659 what_option[fixed][call_used]);
663 fixed_regs[i] = fixed;
664 call_used_regs[i] = call_used;
669 warning ("unknown register name: %s", name);
673 /* Mark register number I as global. */
679 if (fixed_regs[i] == 0 && no_global_reg_vars)
680 error ("global register variable follows a function definition");
684 warning ("register used for two global register variables");
688 if (call_used_regs[i] && ! fixed_regs[i])
689 warning ("call-clobbered register used for global register variable");
693 /* If already fixed, nothing else to do. */
697 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
700 SET_HARD_REG_BIT (fixed_reg_set, i);
701 SET_HARD_REG_BIT (call_used_reg_set, i);
702 SET_HARD_REG_BIT (call_fixed_reg_set, i);
705 /* Now the data and code for the `regclass' pass, which happens
706 just before local-alloc. */
708 /* The `costs' struct records the cost of using a hard register of each class
709 and of using memory for each pseudo. We use this data to set up
710 register class preferences. */
714 int cost[N_REG_CLASSES];
718 /* Structure used to record preferrences of given pseudo. */
721 /* (enum reg_class) prefclass is the preferred class. */
724 /* altclass is a register class that we should use for allocating
725 pseudo if no register in the preferred class is available.
726 If no register in this class is available, memory is preferred.
728 It might appear to be more general to have a bitmask of classes here,
729 but since it is recommended that there be a class corresponding to the
730 union of most major pair of classes, that generality is not required. */
734 /* Record the cost of each class for each pseudo. */
736 static struct costs *costs;
738 /* Initialized once, and used to initialize cost values for each insn. */
740 static struct costs init_cost;
742 /* Record preferrences of each pseudo.
743 This is available after `regclass' is run. */
745 static struct reg_pref *reg_pref;
747 /* Allocated buffers for reg_pref. */
749 static struct reg_pref *reg_pref_buffer;
751 /* Account for the fact that insns within a loop are executed very commonly,
752 but don't keep doing this as loops go too deep. */
754 static int loop_cost;
756 static rtx scan_one_insn PARAMS ((rtx, int));
757 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
758 static void dump_regclass PARAMS ((FILE *));
759 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
761 struct costs *, struct reg_pref *));
762 static int copy_cost PARAMS ((rtx, enum machine_mode,
763 enum reg_class, int));
764 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
765 #ifdef FORBIDDEN_INC_DEC_CLASSES
766 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
768 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
770 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
771 This function is sometimes called before the info has been computed.
772 When that happens, just return GENERAL_REGS, which is innocuous. */
775 reg_preferred_class (regno)
780 return (enum reg_class) reg_pref[regno].prefclass;
784 reg_alternate_class (regno)
790 return (enum reg_class) reg_pref[regno].altclass;
793 /* Initialize some global data for this pass. */
800 init_cost.mem_cost = 10000;
801 for (i = 0; i < N_REG_CLASSES; i++)
802 init_cost.cost[i] = 10000;
804 /* This prevents dump_flow_info from losing if called
805 before regclass is run. */
808 /* No more global register variables may be declared. */
809 no_global_reg_vars = 1;
812 /* Dump register costs. */
817 static const char *const reg_class_names[] = REG_CLASS_NAMES;
819 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
821 enum reg_class class;
824 fprintf (dump, " Register %i costs:", i);
825 for (class = 0; class < N_REG_CLASSES; class++)
826 fprintf (dump, " %s:%i", reg_class_names[(int) class],
827 costs[i].cost[class]);
828 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
834 /* Calculate the costs of insn operands. */
837 record_operand_costs (insn, op_costs, reg_pref)
839 struct costs *op_costs;
840 struct reg_pref *reg_pref;
842 const char *constraints[MAX_RECOG_OPERANDS];
843 enum machine_mode modes[MAX_RECOG_OPERANDS];
846 for (i = 0; i < recog_data.n_operands; i++)
848 constraints[i] = recog_data.constraints[i];
849 modes[i] = recog_data.operand_mode[i];
852 /* If we get here, we are set up to record the costs of all the
853 operands for this insn. Start by initializing the costs.
854 Then handle any address registers. Finally record the desired
855 classes for any pseudos, doing it twice if some pair of
856 operands are commutative. */
858 for (i = 0; i < recog_data.n_operands; i++)
860 op_costs[i] = init_cost;
862 if (GET_CODE (recog_data.operand[i]) == SUBREG)
864 rtx inner = SUBREG_REG (recog_data.operand[i]);
865 #ifdef CLASS_CANNOT_CHANGE_MODE
866 if (GET_CODE (inner) == REG
867 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner)))
868 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner));
870 recog_data.operand[i] = inner;
873 if (GET_CODE (recog_data.operand[i]) == MEM)
874 record_address_regs (XEXP (recog_data.operand[i], 0),
875 BASE_REG_CLASS, loop_cost * 2);
876 else if (constraints[i][0] == 'p')
877 record_address_regs (recog_data.operand[i],
878 BASE_REG_CLASS, loop_cost * 2);
881 /* Check for commutative in a separate loop so everything will
882 have been initialized. We must do this even if one operand
883 is a constant--see addsi3 in m68k.md. */
885 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
886 if (constraints[i][0] == '%')
888 const char *xconstraints[MAX_RECOG_OPERANDS];
891 /* Handle commutative operands by swapping the constraints.
892 We assume the modes are the same. */
894 for (j = 0; j < recog_data.n_operands; j++)
895 xconstraints[j] = constraints[j];
897 xconstraints[i] = constraints[i+1];
898 xconstraints[i+1] = constraints[i];
899 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
900 recog_data.operand, modes,
901 xconstraints, insn, op_costs, reg_pref);
904 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
905 recog_data.operand, modes,
906 constraints, insn, op_costs, reg_pref);
909 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
910 time it would save code to put a certain register in a certain class.
911 PASS, when nonzero, inhibits some optimizations which need only be done
913 Return the last insn processed, so that the scan can be continued from
917 scan_one_insn (insn, pass)
921 enum rtx_code code = GET_CODE (insn);
922 enum rtx_code pat_code;
925 struct costs op_costs[MAX_RECOG_OPERANDS];
927 if (GET_RTX_CLASS (code) != 'i')
930 pat_code = GET_CODE (PATTERN (insn));
932 || pat_code == CLOBBER
933 || pat_code == ASM_INPUT
934 || pat_code == ADDR_VEC
935 || pat_code == ADDR_DIFF_VEC)
938 set = single_set (insn);
941 /* If this insn loads a parameter from its stack slot, then
942 it represents a savings, rather than a cost, if the
943 parameter is stored in memory. Record this fact. */
945 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
946 && GET_CODE (SET_SRC (set)) == MEM
947 && (note = find_reg_note (insn, REG_EQUIV,
949 && GET_CODE (XEXP (note, 0)) == MEM)
951 costs[REGNO (SET_DEST (set))].mem_cost
952 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
955 record_address_regs (XEXP (SET_SRC (set), 0),
956 BASE_REG_CLASS, loop_cost * 2);
960 /* Improve handling of two-address insns such as
961 (set X (ashift CONST Y)) where CONST must be made to
962 match X. Change it into two insns: (set X CONST)
963 (set X (ashift X Y)). If we left this for reloading, it
964 would probably get three insns because X and Y might go
965 in the same place. This prevents X and Y from receiving
968 We can only do this if the modes of operands 0 and 1
969 (which might not be the same) are tieable and we only need
970 do this during our first pass. */
972 if (pass == 0 && optimize
973 && recog_data.n_operands >= 3
974 && recog_data.constraints[1][0] == '0'
975 && recog_data.constraints[1][1] == 0
976 && CONSTANT_P (recog_data.operand[1])
977 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
978 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
979 && GET_CODE (recog_data.operand[0]) == REG
980 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
981 recog_data.operand_mode[1]))
983 rtx previnsn = prev_real_insn (insn);
985 = gen_lowpart (recog_data.operand_mode[1],
986 recog_data.operand[0]);
988 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
990 /* If this insn was the start of a basic block,
991 include the new insn in that block.
992 We need not check for code_label here;
993 while a basic block can start with a code_label,
994 INSN could not be at the beginning of that block. */
995 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
998 for (b = 0; b < n_basic_blocks; b++)
999 if (insn == BLOCK_HEAD (b))
1000 BLOCK_HEAD (b) = newinsn;
1003 /* This makes one more setting of new insns's dest. */
1004 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1006 *recog_data.operand_loc[1] = recog_data.operand[0];
1007 for (i = recog_data.n_dups - 1; i >= 0; i--)
1008 if (recog_data.dup_num[i] == 1)
1009 *recog_data.dup_loc[i] = recog_data.operand[0];
1011 return PREV_INSN (newinsn);
1014 record_operand_costs (insn, op_costs, reg_pref);
1016 /* Now add the cost for each operand to the total costs for
1019 for (i = 0; i < recog_data.n_operands; i++)
1020 if (GET_CODE (recog_data.operand[i]) == REG
1021 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1023 int regno = REGNO (recog_data.operand[i]);
1024 struct costs *p = &costs[regno], *q = &op_costs[i];
1026 p->mem_cost += q->mem_cost * loop_cost;
1027 for (j = 0; j < N_REG_CLASSES; j++)
1028 p->cost[j] += q->cost[j] * loop_cost;
1034 /* This is a pass of the compiler that scans all instructions
1035 and calculates the preferred class for each pseudo-register.
1036 This information can be accessed later by calling `reg_preferred_class'.
1037 This pass comes just before local register allocation. */
1040 regclass (f, nregs, dump)
1051 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1053 #ifdef CLASS_CANNOT_CHANGE_MODE
1054 reg_changes_mode = BITMAP_XMALLOC();
1057 #ifdef FORBIDDEN_INC_DEC_CLASSES
1059 in_inc_dec = (char *) xmalloc (nregs);
1061 /* Initialize information about which register classes can be used for
1062 pseudos that are auto-incremented or auto-decremented. It would
1063 seem better to put this in init_reg_sets, but we need to be able
1064 to allocate rtx, which we can't do that early. */
1066 for (i = 0; i < N_REG_CLASSES; i++)
1068 rtx r = gen_rtx_REG (VOIDmode, 0);
1069 enum machine_mode m;
1072 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1073 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1077 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1078 m = (enum machine_mode) ((int) m + 1))
1079 if (HARD_REGNO_MODE_OK (j, m))
1083 /* If a register is not directly suitable for an
1084 auto-increment or decrement addressing mode and
1085 requires secondary reloads, disallow its class from
1086 being used in such addresses. */
1089 #ifdef SECONDARY_RELOAD_CLASS
1090 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1093 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1094 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1097 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1098 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1103 && ! auto_inc_dec_reg_p (r, m))
1104 forbidden_inc_dec_class[i] = 1;
1108 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1110 /* Normally we scan the insns once and determine the best class to use for
1111 each register. However, if -fexpensive_optimizations are on, we do so
1112 twice, the second time using the tentative best classes to guide the
1115 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1120 fprintf (dump, "\n\nPass %i\n\n",pass);
1121 /* Zero out our accumulation of the cost of each class for each reg. */
1123 bzero ((char *) costs, nregs * sizeof (struct costs));
1125 #ifdef FORBIDDEN_INC_DEC_CLASSES
1126 bzero (in_inc_dec, nregs);
1129 /* Scan the instructions and record each time it would
1130 save code to put a certain register in a certain class. */
1135 for (insn = f; insn; insn = NEXT_INSN (insn))
1136 insn = scan_one_insn (insn, pass);
1139 for (index = 0; index < n_basic_blocks; index++)
1141 basic_block bb = BASIC_BLOCK (index);
1143 /* Show that an insn inside a loop is likely to be executed three
1144 times more than insns outside a loop. This is much more
1145 aggressive than the assumptions made elsewhere and is being
1146 tried as an experiment. */
1150 loop_cost = 1 << (2 * MIN (bb->loop_depth, 5));
1151 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1153 insn = scan_one_insn (insn, pass);
1154 if (insn == bb->end)
1159 /* Now for each register look at how desirable each class is
1160 and find which class is preferred. Store that in
1161 `prefclass'. Record in `altclass' the largest register
1162 class any of whose registers is better than memory. */
1165 reg_pref = reg_pref_buffer;
1169 dump_regclass (dump);
1170 fprintf (dump,"\n");
1172 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1174 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1175 enum reg_class best = ALL_REGS, alt = NO_REGS;
1176 /* This is an enum reg_class, but we call it an int
1177 to save lots of casts. */
1179 register struct costs *p = &costs[i];
1181 /* In non-optimizing compilation REG_N_REFS is not initialized
1183 if (optimize && !REG_N_REFS (i))
1186 for (class = (int) ALL_REGS - 1; class > 0; class--)
1188 /* Ignore classes that are too small for this operand or
1189 invalid for a operand that was auto-incremented. */
1190 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1191 > reg_class_size[class]
1192 #ifdef FORBIDDEN_INC_DEC_CLASSES
1193 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1195 #ifdef CLASS_CANNOT_CHANGE_MODE
1196 || (REGNO_REG_SET_P (reg_changes_mode, i)
1197 && ! class_can_change_mode [class])
1201 else if (p->cost[class] < best_cost)
1203 best_cost = p->cost[class];
1204 best = (enum reg_class) class;
1206 else if (p->cost[class] == best_cost)
1207 best = reg_class_subunion[(int)best][class];
1210 /* Record the alternate register class; i.e., a class for which
1211 every register in it is better than using memory. If adding a
1212 class would make a smaller class (i.e., no union of just those
1213 classes exists), skip that class. The major unions of classes
1214 should be provided as a register class. Don't do this if we
1215 will be doing it again later. */
1217 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1218 for (class = 0; class < N_REG_CLASSES; class++)
1219 if (p->cost[class] < p->mem_cost
1220 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1221 > reg_class_size[(int) alt])
1222 #ifdef FORBIDDEN_INC_DEC_CLASSES
1223 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1225 #ifdef CLASS_CANNOT_CHANGE_MODE
1226 && ! (REGNO_REG_SET_P (reg_changes_mode, i)
1227 && ! class_can_change_mode [class])
1230 alt = reg_class_subunion[(int) alt][class];
1232 /* If we don't add any classes, nothing to try. */
1237 && (reg_pref[i].prefclass != (int) best
1238 || reg_pref[i].altclass != (int) alt))
1240 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1241 fprintf (dump, " Register %i", i);
1242 if (alt == ALL_REGS || best == ALL_REGS)
1243 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1244 else if (alt == NO_REGS)
1245 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1247 fprintf (dump, " pref %s, else %s\n",
1248 reg_class_names[(int) best],
1249 reg_class_names[(int) alt]);
1252 /* We cast to (int) because (char) hits bugs in some compilers. */
1253 reg_pref[i].prefclass = (int) best;
1254 reg_pref[i].altclass = (int) alt;
1258 #ifdef FORBIDDEN_INC_DEC_CLASSES
1261 #ifdef CLASS_CANNOT_CHANGE_MODE
1262 BITMAP_XFREE (reg_changes_mode);
1267 /* Record the cost of using memory or registers of various classes for
1268 the operands in INSN.
1270 N_ALTS is the number of alternatives.
1272 N_OPS is the number of operands.
1274 OPS is an array of the operands.
1276 MODES are the modes of the operands, in case any are VOIDmode.
1278 CONSTRAINTS are the constraints to use for the operands. This array
1279 is modified by this procedure.
1281 This procedure works alternative by alternative. For each alternative
1282 we assume that we will be able to allocate all pseudos to their ideal
1283 register class and calculate the cost of using that alternative. Then
1284 we compute for each operand that is a pseudo-register, the cost of
1285 having the pseudo allocated to each register class and using it in that
1286 alternative. To this cost is added the cost of the alternative.
1288 The cost of each class for this insn is its lowest cost among all the
1292 record_reg_classes (n_alts, n_ops, ops, modes,
1293 constraints, insn, op_costs, reg_pref)
1297 enum machine_mode *modes;
1298 const char **constraints;
1300 struct costs *op_costs;
1301 struct reg_pref *reg_pref;
1307 /* Process each alternative, each time minimizing an operand's cost with
1308 the cost for each operand in that alternative. */
1310 for (alt = 0; alt < n_alts; alt++)
1312 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1315 enum reg_class classes[MAX_RECOG_OPERANDS];
1316 int allows_mem[MAX_RECOG_OPERANDS];
1319 for (i = 0; i < n_ops; i++)
1321 const char *p = constraints[i];
1323 enum machine_mode mode = modes[i];
1324 int allows_addr = 0;
1328 /* Initially show we know nothing about the register class. */
1329 classes[i] = NO_REGS;
1332 /* If this operand has no constraints at all, we can conclude
1333 nothing about it since anything is valid. */
1337 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1338 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1343 /* If this alternative is only relevant when this operand
1344 matches a previous operand, we do different things depending
1345 on whether this operand is a pseudo-reg or not. We must process
1346 any modifiers for the operand before we can make this test. */
1348 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1351 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1353 /* Copy class and whether memory is allowed from the matching
1354 alternative. Then perform any needed cost computations
1355 and/or adjustments. */
1357 classes[i] = classes[j];
1358 allows_mem[i] = allows_mem[j];
1360 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1362 /* If this matches the other operand, we have no added
1364 if (rtx_equal_p (ops[j], op))
1367 /* If we can put the other operand into a register, add to
1368 the cost of this alternative the cost to copy this
1369 operand to the register used for the other operand. */
1371 else if (classes[j] != NO_REGS)
1372 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1374 else if (GET_CODE (ops[j]) != REG
1375 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1377 /* This op is a pseudo but the one it matches is not. */
1379 /* If we can't put the other operand into a register, this
1380 alternative can't be used. */
1382 if (classes[j] == NO_REGS)
1385 /* Otherwise, add to the cost of this alternative the cost
1386 to copy the other operand to the register used for this
1390 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1394 /* The costs of this operand are not the same as the other
1395 operand since move costs are not symmetric. Moreover,
1396 if we cannot tie them, this alternative needs to do a
1397 copy, which is one instruction. */
1399 struct costs *pp = &this_op_costs[i];
1401 for (class = 0; class < N_REG_CLASSES; class++)
1403 = ((recog_data.operand_type[i] != OP_OUT
1404 ? may_move_in_cost[class][(int) classes[i]]
1406 + (recog_data.operand_type[i] != OP_IN
1407 ? may_move_out_cost[(int) classes[i]][class]
1410 /* If the alternative actually allows memory, make things
1411 a bit cheaper since we won't need an extra insn to
1415 = ((recog_data.operand_type[i] != OP_IN
1416 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1418 + (recog_data.operand_type[i] != OP_OUT
1419 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1420 : 0) - allows_mem[i]);
1422 /* If we have assigned a class to this register in our
1423 first pass, add a cost to this alternative corresponding
1424 to what we would add if this register were not in the
1425 appropriate class. */
1429 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1430 [(int) classes[i]]);
1432 if (REGNO (ops[i]) != REGNO (ops[j])
1433 && ! find_reg_note (insn, REG_DEAD, op))
1436 /* This is in place of ordinary cost computation
1437 for this operand, so skip to the end of the
1438 alternative (should be just one character). */
1439 while (*p && *p++ != ',')
1447 /* Scan all the constraint letters. See if the operand matches
1448 any of the constraints. Collect the valid register classes
1449 and see if this operand accepts memory. */
1451 while (*p && (c = *p++) != ',')
1455 /* Ignore the next letter for this pass. */
1461 case '!': case '#': case '&':
1462 case '0': case '1': case '2': case '3': case '4':
1463 case '5': case '6': case '7': case '8': case '9':
1468 win = address_operand (op, GET_MODE (op));
1469 /* We know this operand is an address, so we want it to be
1470 allocated to a register that can be the base of an
1471 address, ie BASE_REG_CLASS. */
1473 = reg_class_subunion[(int) classes[i]]
1474 [(int) BASE_REG_CLASS];
1477 case 'm': case 'o': case 'V':
1478 /* It doesn't seem worth distinguishing between offsettable
1479 and non-offsettable addresses here. */
1481 if (GET_CODE (op) == MEM)
1486 if (GET_CODE (op) == MEM
1487 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1488 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1493 if (GET_CODE (op) == MEM
1494 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1495 || GET_CODE (XEXP (op, 0)) == POST_INC))
1500 #ifndef REAL_ARITHMETIC
1501 /* Match any floating double constant, but only if
1502 we can examine the bits of it reliably. */
1503 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1504 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1505 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1508 if (GET_CODE (op) == CONST_DOUBLE)
1513 if (GET_CODE (op) == CONST_DOUBLE)
1519 if (GET_CODE (op) == CONST_DOUBLE
1520 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1525 if (GET_CODE (op) == CONST_INT
1526 || (GET_CODE (op) == CONST_DOUBLE
1527 && GET_MODE (op) == VOIDmode))
1531 #ifdef LEGITIMATE_PIC_OPERAND_P
1532 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1539 if (GET_CODE (op) == CONST_INT
1540 || (GET_CODE (op) == CONST_DOUBLE
1541 && GET_MODE (op) == VOIDmode))
1553 if (GET_CODE (op) == CONST_INT
1554 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1562 #ifdef EXTRA_CONSTRAINT
1568 if (EXTRA_CONSTRAINT (op, c))
1574 if (GET_CODE (op) == MEM
1576 #ifdef LEGITIMATE_PIC_OPERAND_P
1577 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1584 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1589 = reg_class_subunion[(int) classes[i]]
1590 [(int) REG_CLASS_FROM_LETTER (c)];
1595 /* How we account for this operand now depends on whether it is a
1596 pseudo register or not. If it is, we first check if any
1597 register classes are valid. If not, we ignore this alternative,
1598 since we want to assume that all pseudos get allocated for
1599 register preferencing. If some register class is valid, compute
1600 the costs of moving the pseudo into that class. */
1602 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1604 if (classes[i] == NO_REGS)
1606 /* We must always fail if the operand is a REG, but
1607 we did not find a suitable class.
1609 Otherwise we may perform an uninitialized read
1610 from this_op_costs after the `continue' statement
1616 struct costs *pp = &this_op_costs[i];
1618 for (class = 0; class < N_REG_CLASSES; class++)
1620 = ((recog_data.operand_type[i] != OP_OUT
1621 ? may_move_in_cost[class][(int) classes[i]]
1623 + (recog_data.operand_type[i] != OP_IN
1624 ? may_move_out_cost[(int) classes[i]][class]
1627 /* If the alternative actually allows memory, make things
1628 a bit cheaper since we won't need an extra insn to
1632 = ((recog_data.operand_type[i] != OP_IN
1633 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1635 + (recog_data.operand_type[i] != OP_OUT
1636 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1637 : 0) - allows_mem[i]);
1639 /* If we have assigned a class to this register in our
1640 first pass, add a cost to this alternative corresponding
1641 to what we would add if this register were not in the
1642 appropriate class. */
1646 += (may_move_in_cost[(unsigned char) reg_pref[REGNO (op)].prefclass]
1647 [(int) classes[i]]);
1651 /* Otherwise, if this alternative wins, either because we
1652 have already determined that or if we have a hard register of
1653 the proper class, there is no cost for this alternative. */
1656 || (GET_CODE (op) == REG
1657 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1660 /* If registers are valid, the cost of this alternative includes
1661 copying the object to and/or from a register. */
1663 else if (classes[i] != NO_REGS)
1665 if (recog_data.operand_type[i] != OP_OUT)
1666 alt_cost += copy_cost (op, mode, classes[i], 1);
1668 if (recog_data.operand_type[i] != OP_IN)
1669 alt_cost += copy_cost (op, mode, classes[i], 0);
1672 /* The only other way this alternative can be used is if this is a
1673 constant that could be placed into memory. */
1675 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1676 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1684 /* Finally, update the costs with the information we've calculated
1685 about this alternative. */
1687 for (i = 0; i < n_ops; i++)
1688 if (GET_CODE (ops[i]) == REG
1689 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1691 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1692 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1694 pp->mem_cost = MIN (pp->mem_cost,
1695 (qq->mem_cost + alt_cost) * scale);
1697 for (class = 0; class < N_REG_CLASSES; class++)
1698 pp->cost[class] = MIN (pp->cost[class],
1699 (qq->cost[class] + alt_cost) * scale);
1703 /* If this insn is a single set copying operand 1 to operand 0
1704 and one operand is a pseudo with the other a hard reg or a pseudo
1705 that prefers a register that is in its own register class then
1706 we may want to adjust the cost of that register class to -1.
1708 Avoid the adjustment if the source does not die to avoid stressing of
1709 register allocator by preferrencing two coliding registers into single
1712 Also avoid the adjustment if a copy between registers of the class
1713 is expensive (ten times the cost of a default copy is considered
1714 arbitrarily expensive). This avoids losing when the preferred class
1715 is very expensive as the source of a copy instruction. */
1717 if ((set = single_set (insn)) != 0
1718 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1719 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1720 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1721 for (i = 0; i <= 1; i++)
1722 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1724 unsigned int regno = REGNO (ops[!i]);
1725 enum machine_mode mode = GET_MODE (ops[!i]);
1729 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1731 enum reg_class pref = reg_pref[regno].prefclass;
1733 if ((reg_class_size[(unsigned char) pref]
1734 == CLASS_MAX_NREGS (pref, mode))
1735 && REGISTER_MOVE_COST (pref, pref) < 10 * 2)
1736 op_costs[i].cost[(unsigned char) pref] = -1;
1738 else if (regno < FIRST_PSEUDO_REGISTER)
1739 for (class = 0; class < N_REG_CLASSES; class++)
1740 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1741 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1743 if (reg_class_size[class] == 1)
1744 op_costs[i].cost[class] = -1;
1747 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1749 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1754 if (nr == HARD_REGNO_NREGS (regno,mode))
1755 op_costs[i].cost[class] = -1;
1761 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1762 TO_P is zero) a register of class CLASS in mode MODE.
1764 X must not be a pseudo. */
1767 copy_cost (x, mode, class, to_p)
1769 enum machine_mode mode ATTRIBUTE_UNUSED;
1770 enum reg_class class;
1771 int to_p ATTRIBUTE_UNUSED;
1773 #ifdef HAVE_SECONDARY_RELOADS
1774 enum reg_class secondary_class = NO_REGS;
1777 /* If X is a SCRATCH, there is actually nothing to move since we are
1778 assuming optimal allocation. */
1780 if (GET_CODE (x) == SCRATCH)
1783 /* Get the class we will actually use for a reload. */
1784 class = PREFERRED_RELOAD_CLASS (x, class);
1786 #ifdef HAVE_SECONDARY_RELOADS
1787 /* If we need a secondary reload (we assume here that we are using
1788 the secondary reload as an intermediate, not a scratch register), the
1789 cost is that to load the input into the intermediate register, then
1790 to copy them. We use a special value of TO_P to avoid recursion. */
1792 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1794 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1797 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1799 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1802 if (secondary_class != NO_REGS)
1803 return (move_cost[(int) secondary_class][(int) class]
1804 + copy_cost (x, mode, secondary_class, 2));
1805 #endif /* HAVE_SECONDARY_RELOADS */
1807 /* For memory, use the memory move cost, for (hard) registers, use the
1808 cost to move between the register classes, and use 2 for everything
1809 else (constants). */
1811 if (GET_CODE (x) == MEM || class == NO_REGS)
1812 return MEMORY_MOVE_COST (mode, class, to_p);
1814 else if (GET_CODE (x) == REG)
1815 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1818 /* If this is a constant, we may eventually want to call rtx_cost here. */
1822 /* Record the pseudo registers we must reload into hard registers
1823 in a subexpression of a memory address, X.
1825 CLASS is the class that the register needs to be in and is either
1826 BASE_REG_CLASS or INDEX_REG_CLASS.
1828 SCALE is twice the amount to multiply the cost by (it is twice so we
1829 can represent half-cost adjustments). */
1832 record_address_regs (x, class, scale)
1834 enum reg_class class;
1837 register enum rtx_code code = GET_CODE (x);
1850 /* When we have an address that is a sum,
1851 we must determine whether registers are "base" or "index" regs.
1852 If there is a sum of two registers, we must choose one to be
1853 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1854 to make a good choice most of the time. We only need to do this
1855 on machines that can have two registers in an address and where
1856 the base and index register classes are different.
1858 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1859 that seems bogus since it should only be set when we are sure
1860 the register is being used as a pointer. */
1863 rtx arg0 = XEXP (x, 0);
1864 rtx arg1 = XEXP (x, 1);
1865 register enum rtx_code code0 = GET_CODE (arg0);
1866 register enum rtx_code code1 = GET_CODE (arg1);
1868 /* Look inside subregs. */
1869 if (code0 == SUBREG)
1870 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1871 if (code1 == SUBREG)
1872 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1874 /* If this machine only allows one register per address, it must
1875 be in the first operand. */
1877 if (MAX_REGS_PER_ADDRESS == 1)
1878 record_address_regs (arg0, class, scale);
1880 /* If index and base registers are the same on this machine, just
1881 record registers in any non-constant operands. We assume here,
1882 as well as in the tests below, that all addresses are in
1885 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1887 record_address_regs (arg0, class, scale);
1888 if (! CONSTANT_P (arg1))
1889 record_address_regs (arg1, class, scale);
1892 /* If the second operand is a constant integer, it doesn't change
1893 what class the first operand must be. */
1895 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1896 record_address_regs (arg0, class, scale);
1898 /* If the second operand is a symbolic constant, the first operand
1899 must be an index register. */
1901 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1902 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1904 /* If both operands are registers but one is already a hard register
1905 of index or base class, give the other the class that the hard
1908 #ifdef REG_OK_FOR_BASE_P
1909 else if (code0 == REG && code1 == REG
1910 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1911 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1912 record_address_regs (arg1,
1913 REG_OK_FOR_BASE_P (arg0)
1914 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1916 else if (code0 == REG && code1 == REG
1917 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1918 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1919 record_address_regs (arg0,
1920 REG_OK_FOR_BASE_P (arg1)
1921 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1925 /* If one operand is known to be a pointer, it must be the base
1926 with the other operand the index. Likewise if the other operand
1929 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1932 record_address_regs (arg0, BASE_REG_CLASS, scale);
1933 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1935 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1938 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1939 record_address_regs (arg1, BASE_REG_CLASS, scale);
1942 /* Otherwise, count equal chances that each might be a base
1943 or index register. This case should be rare. */
1947 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1948 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1949 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1950 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1959 /* Double the importance of a pseudo register that is incremented
1960 or decremented, since it would take two extra insns
1961 if it ends up in the wrong place. If the operand is a pseudo,
1962 show it is being used in an INC_DEC context. */
1964 #ifdef FORBIDDEN_INC_DEC_CLASSES
1965 if (GET_CODE (XEXP (x, 0)) == REG
1966 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1967 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1970 record_address_regs (XEXP (x, 0), class, 2 * scale);
1975 register struct costs *pp = &costs[REGNO (x)];
1978 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1980 for (i = 0; i < N_REG_CLASSES; i++)
1981 pp->cost[i] += (may_move_in_cost[i][(int) class] * scale) / 2;
1987 register const char *fmt = GET_RTX_FORMAT (code);
1989 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1991 record_address_regs (XEXP (x, i), class, scale);
1996 #ifdef FORBIDDEN_INC_DEC_CLASSES
1998 /* Return 1 if REG is valid as an auto-increment memory reference
1999 to an object of MODE. */
2002 auto_inc_dec_reg_p (reg, mode)
2004 enum machine_mode mode;
2006 if (HAVE_POST_INCREMENT
2007 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2010 if (HAVE_POST_DECREMENT
2011 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2014 if (HAVE_PRE_INCREMENT
2015 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2018 if (HAVE_PRE_DECREMENT
2019 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2026 static short *renumber;
2027 static size_t regno_allocated;
2028 static unsigned int reg_n_max;
2030 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2031 reg_scan and flow_analysis that are indexed by the register number. If
2032 NEW_P is non zero, initialize all of the registers, otherwise only
2033 initialize the new registers allocated. The same table is kept from
2034 function to function, only reallocating it when we need more room. If
2035 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2038 allocate_reg_info (num_regs, new_p, renumber_p)
2044 size_t size_renumber;
2045 size_t min = (new_p) ? 0 : reg_n_max;
2046 struct reg_info_data *reg_data;
2048 if (num_regs > regno_allocated)
2050 size_t old_allocated = regno_allocated;
2052 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2053 size_renumber = regno_allocated * sizeof (short);
2057 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2058 renumber = (short *) xmalloc (size_renumber);
2059 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2060 * sizeof (struct reg_pref));
2065 VARRAY_GROW (reg_n_info, regno_allocated);
2067 if (new_p) /* if we're zapping everything, no need to realloc */
2069 free ((char *)renumber);
2070 free ((char *)reg_pref);
2071 renumber = (short *) xmalloc (size_renumber);
2072 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2073 * sizeof (struct reg_pref));
2078 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2079 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2081 * sizeof (struct reg_pref));
2085 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2086 + sizeof (struct reg_info_data) - sizeof (reg_info);
2087 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2088 reg_data->min_index = old_allocated;
2089 reg_data->max_index = regno_allocated - 1;
2090 reg_data->next = reg_info_head;
2091 reg_info_head = reg_data;
2094 reg_n_max = num_regs;
2097 /* Loop through each of the segments allocated for the actual
2098 reg_info pages, and set up the pointers, zero the pages, etc. */
2099 for (reg_data = reg_info_head;
2100 reg_data && reg_data->max_index >= min;
2101 reg_data = reg_data->next)
2103 size_t min_index = reg_data->min_index;
2104 size_t max_index = reg_data->max_index;
2105 size_t max = MIN (max_index, num_regs);
2106 size_t local_min = min - min_index;
2109 if (reg_data->min_index > num_regs)
2112 if (min < min_index)
2114 if (!reg_data->used_p) /* page just allocated with calloc */
2115 reg_data->used_p = 1; /* no need to zero */
2117 bzero ((char *) ®_data->data[local_min],
2118 sizeof (reg_info) * (max - min_index - local_min + 1));
2120 for (i = min_index+local_min; i <= max; i++)
2122 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2123 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2125 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2126 reg_pref_buffer[i].altclass = (char) NO_REGS;
2131 /* If {pref,alt}class have already been allocated, update the pointers to
2132 the newly realloced ones. */
2134 reg_pref = reg_pref_buffer;
2137 reg_renumber = renumber;
2139 /* Tell the regset code about the new number of registers */
2140 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2143 /* Free up the space allocated by allocate_reg_info. */
2149 struct reg_info_data *reg_data;
2150 struct reg_info_data *reg_next;
2152 VARRAY_FREE (reg_n_info);
2153 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2155 reg_next = reg_data->next;
2156 free ((char *)reg_data);
2159 free (reg_pref_buffer);
2160 reg_pref_buffer = (struct reg_pref *)0;
2161 reg_info_head = (struct reg_info_data *)0;
2162 renumber = (short *)0;
2164 regno_allocated = 0;
2168 /* This is the `regscan' pass of the compiler, run just before cse
2169 and again just before loop.
2171 It finds the first and last use of each pseudo-register
2172 and records them in the vectors regno_first_uid, regno_last_uid
2173 and counts the number of sets in the vector reg_n_sets.
2175 REPEAT is nonzero the second time this is called. */
2177 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2178 Always at least 3, since the combiner could put that many together
2179 and we want this to remain correct for all the remaining passes. */
2184 reg_scan (f, nregs, repeat)
2187 int repeat ATTRIBUTE_UNUSED;
2191 allocate_reg_info (nregs, TRUE, FALSE);
2194 for (insn = f; insn; insn = NEXT_INSN (insn))
2195 if (GET_CODE (insn) == INSN
2196 || GET_CODE (insn) == CALL_INSN
2197 || GET_CODE (insn) == JUMP_INSN)
2199 if (GET_CODE (PATTERN (insn)) == PARALLEL
2200 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2201 max_parallel = XVECLEN (PATTERN (insn), 0);
2202 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2204 if (REG_NOTES (insn))
2205 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2209 /* Update 'regscan' information by looking at the insns
2210 from FIRST to LAST. Some new REGs have been created,
2211 and any REG with number greater than OLD_MAX_REGNO is
2212 such a REG. We only update information for those. */
2215 reg_scan_update (first, last, old_max_regno)
2218 unsigned int old_max_regno;
2222 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2224 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2225 if (GET_CODE (insn) == INSN
2226 || GET_CODE (insn) == CALL_INSN
2227 || GET_CODE (insn) == JUMP_INSN)
2229 if (GET_CODE (PATTERN (insn)) == PARALLEL
2230 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2231 max_parallel = XVECLEN (PATTERN (insn), 0);
2232 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2234 if (REG_NOTES (insn))
2235 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2239 /* X is the expression to scan. INSN is the insn it appears in.
2240 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2241 We should only record information for REGs with numbers
2242 greater than or equal to MIN_REGNO. */
2245 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2249 unsigned int min_regno;
2251 register enum rtx_code code;
2255 code = GET_CODE (x);
2271 unsigned int regno = REGNO (x);
2273 if (regno >= min_regno)
2275 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2277 REGNO_LAST_UID (regno) = INSN_UID (insn);
2278 if (REGNO_FIRST_UID (regno) == 0)
2279 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2286 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2288 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2293 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2297 /* Count a set of the destination if it is a register. */
2298 for (dest = SET_DEST (x);
2299 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2300 || GET_CODE (dest) == ZERO_EXTEND;
2301 dest = XEXP (dest, 0))
2304 if (GET_CODE (dest) == REG
2305 && REGNO (dest) >= min_regno)
2306 REG_N_SETS (REGNO (dest))++;
2308 /* If this is setting a pseudo from another pseudo or the sum of a
2309 pseudo and a constant integer and the other pseudo is known to be
2310 a pointer, set the destination to be a pointer as well.
2312 Likewise if it is setting the destination from an address or from a
2313 value equivalent to an address or to the sum of an address and
2316 But don't do any of this if the pseudo corresponds to a user
2317 variable since it should have already been set as a pointer based
2320 if (GET_CODE (SET_DEST (x)) == REG
2321 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2322 && REGNO (SET_DEST (x)) >= min_regno
2323 /* If the destination pseudo is set more than once, then other
2324 sets might not be to a pointer value (consider access to a
2325 union in two threads of control in the presense of global
2326 optimizations). So only set REGNO_POINTER_FLAG on the destination
2327 pseudo if this is the only set of that pseudo. */
2328 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2329 && ! REG_USERVAR_P (SET_DEST (x))
2330 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2331 && ((GET_CODE (SET_SRC (x)) == REG
2332 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2333 || ((GET_CODE (SET_SRC (x)) == PLUS
2334 || GET_CODE (SET_SRC (x)) == LO_SUM)
2335 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2336 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2337 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2338 || GET_CODE (SET_SRC (x)) == CONST
2339 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2340 || GET_CODE (SET_SRC (x)) == LABEL_REF
2341 || (GET_CODE (SET_SRC (x)) == HIGH
2342 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2343 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2344 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2345 || ((GET_CODE (SET_SRC (x)) == PLUS
2346 || GET_CODE (SET_SRC (x)) == LO_SUM)
2347 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2348 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2349 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2350 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2351 && (GET_CODE (XEXP (note, 0)) == CONST
2352 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2353 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2354 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2356 /* ... fall through ... */
2360 register const char *fmt = GET_RTX_FORMAT (code);
2362 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2365 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2366 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2369 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2370 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2377 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2381 reg_class_subset_p (c1, c2)
2382 register enum reg_class c1;
2383 register enum reg_class c2;
2385 if (c1 == c2) return 1;
2390 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2391 reg_class_contents[(int)c2],
2396 /* Return nonzero if there is a register that is in both C1 and C2. */
2399 reg_classes_intersect_p (c1, c2)
2400 register enum reg_class c1;
2401 register enum reg_class c2;
2408 if (c1 == c2) return 1;
2410 if (c1 == ALL_REGS || c2 == ALL_REGS)
2413 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2414 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2416 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2423 /* Release any memory allocated by register sets. */
2426 regset_release_memory ()
2428 bitmap_release_memory ();