1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
32 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 #include "insn-config.h"
45 #ifndef REGISTER_MOVE_COST
46 #define REGISTER_MOVE_COST(m, x, y) 2
49 static void init_reg_sets_1 PARAMS ((void));
50 static void init_reg_modes PARAMS ((void));
52 /* If we have auto-increment or auto-decrement and we can have secondary
53 reloads, we are not allowed to use classes requiring secondary
54 reloads for pseudos auto-incremented since reload can't handle it. */
57 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
58 #define FORBIDDEN_INC_DEC_CLASSES
62 /* Register tables used by many passes. */
64 /* Indexed by hard register number, contains 1 for registers
65 that are fixed use (stack pointer, pc, frame pointer, etc.).
66 These are the registers that cannot be used to allocate
67 a pseudo reg for general use. */
69 char fixed_regs[FIRST_PSEUDO_REGISTER];
71 /* Same info as a HARD_REG_SET. */
73 HARD_REG_SET fixed_reg_set;
75 /* Data for initializing the above. */
77 static char initial_fixed_regs[] = FIXED_REGISTERS;
79 /* Indexed by hard register number, contains 1 for registers
80 that are fixed use or are clobbered by function calls.
81 These are the registers that cannot be used to allocate
82 a pseudo reg whose life crosses calls unless we are able
83 to save/restore them across the calls. */
85 char call_used_regs[FIRST_PSEUDO_REGISTER];
87 /* Same info as a HARD_REG_SET. */
89 HARD_REG_SET call_used_reg_set;
91 /* HARD_REG_SET of registers we want to avoid caller saving. */
92 HARD_REG_SET losing_caller_save_reg_set;
94 /* Data for initializing the above. */
96 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
98 /* Indexed by hard register number, contains 1 for registers that are
99 fixed use or call used registers that cannot hold quantities across
100 calls even if we are willing to save and restore them. call fixed
101 registers are a subset of call used registers. */
103 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
105 /* The same info as a HARD_REG_SET. */
107 HARD_REG_SET call_fixed_reg_set;
109 /* Number of non-fixed registers. */
111 int n_non_fixed_regs;
113 /* Indexed by hard register number, contains 1 for registers
114 that are being used for global register decls.
115 These must be exempt from ordinary flow analysis
116 and are also considered fixed. */
118 char global_regs[FIRST_PSEUDO_REGISTER];
120 /* Contains 1 for registers that are set or clobbered by calls. */
121 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
122 for someone's bright idea to have call_used_regs strictly include
123 fixed_regs. Which leaves us guessing as to the set of fixed_regs
124 that are actually preserved. We know for sure that those associated
125 with the local stack frame are safe, but scant others. */
127 HARD_REG_SET regs_invalidated_by_call;
129 /* Table of register numbers in the order in which to try to use them. */
130 #ifdef REG_ALLOC_ORDER
131 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
133 /* The inverse of reg_alloc_order. */
134 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
137 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
139 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
141 /* The same information, but as an array of unsigned ints. We copy from
142 these unsigned ints to the table above. We do this so the tm.h files
143 do not have to be aware of the wordsize for machines with <= 64 regs. */
146 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
148 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
149 = REG_CLASS_CONTENTS;
151 /* For each reg class, number of regs it contains. */
153 unsigned int reg_class_size[N_REG_CLASSES];
155 /* For each reg class, table listing all the containing classes. */
157 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
159 /* For each reg class, table listing all the classes contained in it. */
161 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
163 /* For each pair of reg classes,
164 a largest reg class contained in their union. */
166 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
168 /* For each pair of reg classes,
169 the smallest reg class containing their union. */
171 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
173 /* Array containing all of the register names. Unless
174 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
176 #ifdef DEBUG_REGISTER_NAMES
177 const char * reg_names[] = REGISTER_NAMES;
180 /* For each hard register, the widest mode object that it can contain.
181 This will be a MODE_INT mode if the register can hold integers. Otherwise
182 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
185 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
187 /* 1 if class does contain register of given mode. */
189 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
191 /* Maximum cost of moving from a register in one class to a register in
192 another class. Based on REGISTER_MOVE_COST. */
194 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
196 /* Similar, but here we don't have to move if the first index is a subset
197 of the second so in that case the cost is zero. */
199 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
201 /* Similar, but here we don't have to move if the first index is a superset
202 of the second so in that case the cost is zero. */
204 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
206 #ifdef FORBIDDEN_INC_DEC_CLASSES
208 /* These are the classes that regs which are auto-incremented or decremented
211 static int forbidden_inc_dec_class[N_REG_CLASSES];
213 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
216 static char *in_inc_dec;
218 #endif /* FORBIDDEN_INC_DEC_CLASSES */
220 #ifdef CLASS_CANNOT_CHANGE_MODE
222 /* These are the classes containing only registers that can be used in
223 a SUBREG expression that changes the mode of the register in some
224 way that is illegal. */
226 static int class_can_change_mode[N_REG_CLASSES];
228 /* Registers, including pseudos, which change modes in some way that
231 static regset reg_changes_mode;
233 #endif /* CLASS_CANNOT_CHANGE_MODE */
235 #ifdef HAVE_SECONDARY_RELOADS
237 /* Sample MEM values for use by memory_move_secondary_cost. */
239 static rtx top_of_stack[MAX_MACHINE_MODE];
241 #endif /* HAVE_SECONDARY_RELOADS */
243 /* Linked list of reg_info structures allocated for reg_n_info array.
244 Grouping all of the allocated structures together in one lump
245 means only one call to bzero to clear them, rather than n smaller
247 struct reg_info_data {
248 struct reg_info_data *next; /* next set of reg_info structures */
249 size_t min_index; /* minimum index # */
250 size_t max_index; /* maximum index # */
251 char used_p; /* non-zero if this has been used previously */
252 reg_info data[1]; /* beginning of the reg_info data */
255 static struct reg_info_data *reg_info_head;
257 /* No more global register variables may be declared; true once
258 regclass has been initialized. */
260 static int no_global_reg_vars = 0;
263 /* Function called only once to initialize the above data on reg usage.
264 Once this is done, various switches may override. */
271 /* First copy the register information from the initial int form into
274 for (i = 0; i < N_REG_CLASSES; i++)
276 CLEAR_HARD_REG_SET (reg_class_contents[i]);
278 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
279 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
280 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
281 SET_HARD_REG_BIT (reg_class_contents[i], j);
284 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
285 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
286 memset (global_regs, 0, sizeof global_regs);
288 /* Do any additional initialization regsets may need */
289 INIT_ONCE_REG_SET ();
291 #ifdef REG_ALLOC_ORDER
292 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
293 inv_reg_alloc_order[reg_alloc_order[i]] = i;
297 /* After switches have been processed, which perhaps alter
298 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
303 register unsigned int i, j;
304 register unsigned int /* enum machine_mode */ m;
305 char allocatable_regs_of_mode [MAX_MACHINE_MODE];
307 /* This macro allows the fixed or call-used registers
308 and the register classes to depend on target flags. */
310 #ifdef CONDITIONAL_REGISTER_USAGE
311 CONDITIONAL_REGISTER_USAGE;
314 /* Compute number of hard regs in each class. */
316 memset ((char *) reg_class_size, 0, sizeof reg_class_size);
317 for (i = 0; i < N_REG_CLASSES; i++)
318 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
319 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
322 /* Initialize the table of subunions.
323 reg_class_subunion[I][J] gets the largest-numbered reg-class
324 that is contained in the union of classes I and J. */
326 for (i = 0; i < N_REG_CLASSES; i++)
328 for (j = 0; j < N_REG_CLASSES; j++)
331 register /* Declare it register if it's a scalar. */
336 COPY_HARD_REG_SET (c, reg_class_contents[i]);
337 IOR_HARD_REG_SET (c, reg_class_contents[j]);
338 for (k = 0; k < N_REG_CLASSES; k++)
340 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
345 /* keep the largest subclass */ /* SPEE 900308 */
346 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
347 reg_class_contents[(int) reg_class_subunion[i][j]],
349 reg_class_subunion[i][j] = (enum reg_class) k;
356 /* Initialize the table of superunions.
357 reg_class_superunion[I][J] gets the smallest-numbered reg-class
358 containing the union of classes I and J. */
360 for (i = 0; i < N_REG_CLASSES; i++)
362 for (j = 0; j < N_REG_CLASSES; j++)
365 register /* Declare it register if it's a scalar. */
370 COPY_HARD_REG_SET (c, reg_class_contents[i]);
371 IOR_HARD_REG_SET (c, reg_class_contents[j]);
372 for (k = 0; k < N_REG_CLASSES; k++)
373 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
376 reg_class_superunion[i][j] = (enum reg_class) k;
380 /* Initialize the tables of subclasses and superclasses of each reg class.
381 First clear the whole table, then add the elements as they are found. */
383 for (i = 0; i < N_REG_CLASSES; i++)
385 for (j = 0; j < N_REG_CLASSES; j++)
387 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
388 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
392 for (i = 0; i < N_REG_CLASSES; i++)
394 if (i == (int) NO_REGS)
397 for (j = i + 1; j < N_REG_CLASSES; j++)
401 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
405 /* Reg class I is a subclass of J.
406 Add J to the table of superclasses of I. */
407 p = ®_class_superclasses[i][0];
408 while (*p != LIM_REG_CLASSES) p++;
409 *p = (enum reg_class) j;
410 /* Add I to the table of superclasses of J. */
411 p = ®_class_subclasses[j][0];
412 while (*p != LIM_REG_CLASSES) p++;
413 *p = (enum reg_class) i;
417 /* Initialize "constant" tables. */
419 CLEAR_HARD_REG_SET (fixed_reg_set);
420 CLEAR_HARD_REG_SET (call_used_reg_set);
421 CLEAR_HARD_REG_SET (call_fixed_reg_set);
422 CLEAR_HARD_REG_SET (regs_invalidated_by_call);
424 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
426 n_non_fixed_regs = 0;
428 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
431 SET_HARD_REG_BIT (fixed_reg_set, i);
435 if (call_used_regs[i])
436 SET_HARD_REG_BIT (call_used_reg_set, i);
437 if (call_fixed_regs[i])
438 SET_HARD_REG_BIT (call_fixed_reg_set, i);
439 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
440 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
442 /* There are a couple of fixed registers that we know are safe to
443 exclude from being clobbered by calls:
445 The frame pointer is always preserved across calls. The arg pointer
446 is if it is fixed. The stack pointer usually is, unless
447 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present.
448 If we are generating PIC code, the PIC offset table register is
449 preserved across calls, though the target can override that. */
451 if (i == STACK_POINTER_REGNUM || i == FRAME_POINTER_REGNUM)
453 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
454 else if (i == HARD_FRAME_POINTER_REGNUM)
457 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
458 else if (i == ARG_POINTER_REGNUM && fixed_regs[i])
461 #ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
462 else if (i == PIC_OFFSET_TABLE_REGNUM && flag_pic)
465 else if (call_used_regs[i] || global_regs[i])
466 SET_HARD_REG_BIT (regs_invalidated_by_call, i);
469 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
470 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode));
471 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
472 for (i = 0; i < N_REG_CLASSES; i++)
473 if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i])
474 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
475 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
476 && HARD_REGNO_MODE_OK (j, m))
478 contains_reg_of_mode [i][m] = 1;
479 allocatable_regs_of_mode [m] = 1;
483 /* Initialize the move cost table. Find every subset of each class
484 and take the maximum cost of moving any subset to any other. */
486 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
487 if (allocatable_regs_of_mode [m])
489 for (i = 0; i < N_REG_CLASSES; i++)
490 if (contains_reg_of_mode [i][m])
491 for (j = 0; j < N_REG_CLASSES; j++)
494 enum reg_class *p1, *p2;
496 if (!contains_reg_of_mode [j][m])
498 move_cost[m][i][j] = 65536;
499 may_move_in_cost[m][i][j] = 65536;
500 may_move_out_cost[m][i][j] = 65536;
504 cost = i == j ? 2 : REGISTER_MOVE_COST (m, i, j);
506 for (p2 = ®_class_subclasses[j][0];
507 *p2 != LIM_REG_CLASSES;
509 if (*p2 != i && contains_reg_of_mode [*p2][m])
510 cost = MAX (cost, move_cost [m][i][*p2]);
512 for (p1 = ®_class_subclasses[i][0];
513 *p1 != LIM_REG_CLASSES;
515 if (*p1 != j && contains_reg_of_mode [*p1][m])
516 cost = MAX (cost, move_cost [m][*p1][j]);
518 move_cost[m][i][j] = cost;
520 if (reg_class_subset_p (i, j))
521 may_move_in_cost[m][i][j] = 0;
523 may_move_in_cost[m][i][j] = cost;
525 if (reg_class_subset_p (j, i))
526 may_move_out_cost[m][i][j] = 0;
528 may_move_out_cost[m][i][j] = cost;
532 for (j = 0; j < N_REG_CLASSES; j++)
534 move_cost[m][i][j] = 65536;
535 may_move_in_cost[m][i][j] = 65536;
536 may_move_out_cost[m][i][j] = 65536;
540 #ifdef CLASS_CANNOT_CHANGE_MODE
543 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]);
545 for (i = 0; i < N_REG_CLASSES; i++)
547 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
548 class_can_change_mode [i] = 0;
551 class_can_change_mode [i] = 1;
554 #endif /* CLASS_CANNOT_CHANGE_MODE */
557 /* Compute the table of register modes.
558 These values are used to record death information for individual registers
559 (as opposed to a multi-register mode). */
566 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
568 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
570 /* If we couldn't find a valid mode, just use the previous mode.
571 ??? One situation in which we need to do this is on the mips where
572 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
573 to use DF mode for the even registers and VOIDmode for the odd
574 (for the cpu models where the odd ones are inaccessible). */
575 if (reg_raw_mode[i] == VOIDmode)
576 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
580 /* Finish initializing the register sets and
581 initialize the register modes. */
586 /* This finishes what was started by init_reg_sets, but couldn't be done
587 until after register usage was specified. */
592 #ifdef HAVE_SECONDARY_RELOADS
594 /* Make some fake stack-frame MEM references for use in
595 memory_move_secondary_cost. */
598 for (i = 0; i < MAX_MACHINE_MODE; i++)
599 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
600 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
605 #ifdef HAVE_SECONDARY_RELOADS
607 /* Compute extra cost of moving registers to/from memory due to reloads.
608 Only needed if secondary reloads are required for memory moves. */
611 memory_move_secondary_cost (mode, class, in)
612 enum machine_mode mode;
613 enum reg_class class;
616 enum reg_class altclass;
617 int partial_cost = 0;
618 /* We need a memory reference to feed to SECONDARY... macros. */
619 /* mem may be unused even if the SECONDARY_ macros are defined. */
620 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
625 #ifdef SECONDARY_INPUT_RELOAD_CLASS
626 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
633 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
634 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
640 if (altclass == NO_REGS)
644 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
646 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
648 if (class == altclass)
649 /* This isn't simply a copy-to-temporary situation. Can't guess
650 what it is, so MEMORY_MOVE_COST really ought not to be calling
653 I'm tempted to put in an abort here, but returning this will
654 probably only give poor estimates, which is what we would've
655 had before this code anyways. */
658 /* Check if the secondary reload register will also need a
660 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
664 /* Return a machine mode that is legitimate for hard reg REGNO and large
665 enough to save nregs. If we can't find one, return VOIDmode. */
668 choose_hard_reg_mode (regno, nregs)
669 unsigned int regno ATTRIBUTE_UNUSED;
672 unsigned int /* enum machine_mode */ m;
673 enum machine_mode found_mode = VOIDmode, mode;
675 /* We first look for the largest integer mode that can be validly
676 held in REGNO. If none, we look for the largest floating-point mode.
677 If we still didn't find a valid mode, try CCmode. */
679 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
681 mode = GET_MODE_WIDER_MODE (mode))
682 if (HARD_REGNO_NREGS (regno, mode) == nregs
683 && HARD_REGNO_MODE_OK (regno, mode))
686 if (found_mode != VOIDmode)
689 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
691 mode = GET_MODE_WIDER_MODE (mode))
692 if (HARD_REGNO_NREGS (regno, mode) == nregs
693 && HARD_REGNO_MODE_OK (regno, mode))
696 if (found_mode != VOIDmode)
699 /* Iterate over all of the CCmodes. */
700 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m)
702 mode = (enum machine_mode) m;
703 if (HARD_REGNO_NREGS (regno, mode) == nregs
704 && HARD_REGNO_MODE_OK (regno, mode))
708 /* We can't find a mode valid for this register. */
712 /* Specify the usage characteristics of the register named NAME.
713 It should be a fixed register if FIXED and a
714 call-used register if CALL_USED. */
717 fix_register (name, fixed, call_used)
719 int fixed, call_used;
723 /* Decode the name and update the primary form of
724 the register info. */
726 if ((i = decode_reg_name (name)) >= 0)
728 if ((i == STACK_POINTER_REGNUM
729 #ifdef HARD_FRAME_POINTER_REGNUM
730 || i == HARD_FRAME_POINTER_REGNUM
732 || i == FRAME_POINTER_REGNUM
735 && (fixed == 0 || call_used == 0))
737 static const char * const what_option[2][2] = {
738 { "call-saved", "call-used" },
739 { "no-such-option", "fixed" }};
741 error ("can't use '%s' as a %s register", name,
742 what_option[fixed][call_used]);
746 fixed_regs[i] = fixed;
747 call_used_regs[i] = call_used;
752 warning ("unknown register name: %s", name);
756 /* Mark register number I as global. */
762 if (fixed_regs[i] == 0 && no_global_reg_vars)
763 error ("global register variable follows a function definition");
767 warning ("register used for two global register variables");
771 if (call_used_regs[i] && ! fixed_regs[i])
772 warning ("call-clobbered register used for global register variable");
776 /* If already fixed, nothing else to do. */
780 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
783 SET_HARD_REG_BIT (fixed_reg_set, i);
784 SET_HARD_REG_BIT (call_used_reg_set, i);
785 SET_HARD_REG_BIT (call_fixed_reg_set, i);
788 /* Now the data and code for the `regclass' pass, which happens
789 just before local-alloc. */
791 /* The `costs' struct records the cost of using a hard register of each class
792 and of using memory for each pseudo. We use this data to set up
793 register class preferences. */
797 int cost[N_REG_CLASSES];
801 /* Structure used to record preferrences of given pseudo. */
804 /* (enum reg_class) prefclass is the preferred class. */
807 /* altclass is a register class that we should use for allocating
808 pseudo if no register in the preferred class is available.
809 If no register in this class is available, memory is preferred.
811 It might appear to be more general to have a bitmask of classes here,
812 but since it is recommended that there be a class corresponding to the
813 union of most major pair of classes, that generality is not required. */
817 /* Record the cost of each class for each pseudo. */
819 static struct costs *costs;
821 /* Initialized once, and used to initialize cost values for each insn. */
823 static struct costs init_cost;
825 /* Record preferrences of each pseudo.
826 This is available after `regclass' is run. */
828 static struct reg_pref *reg_pref;
830 /* Allocated buffers for reg_pref. */
832 static struct reg_pref *reg_pref_buffer;
834 /* Frequency of executions of current insn. */
836 static int frequency;
838 static rtx scan_one_insn PARAMS ((rtx, int));
839 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
840 static void dump_regclass PARAMS ((FILE *));
841 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
843 struct costs *, struct reg_pref *));
844 static int copy_cost PARAMS ((rtx, enum machine_mode,
845 enum reg_class, int));
846 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
847 #ifdef FORBIDDEN_INC_DEC_CLASSES
848 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
850 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
852 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
853 This function is sometimes called before the info has been computed.
854 When that happens, just return GENERAL_REGS, which is innocuous. */
857 reg_preferred_class (regno)
862 return (enum reg_class) reg_pref[regno].prefclass;
866 reg_alternate_class (regno)
872 return (enum reg_class) reg_pref[regno].altclass;
875 /* Initialize some global data for this pass. */
882 init_cost.mem_cost = 10000;
883 for (i = 0; i < N_REG_CLASSES; i++)
884 init_cost.cost[i] = 10000;
886 /* This prevents dump_flow_info from losing if called
887 before regclass is run. */
890 /* No more global register variables may be declared. */
891 no_global_reg_vars = 1;
894 /* Dump register costs. */
899 static const char *const reg_class_names[] = REG_CLASS_NAMES;
901 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
903 int /* enum reg_class */ class;
906 fprintf (dump, " Register %i costs:", i);
907 for (class = 0; class < (int) N_REG_CLASSES; class++)
908 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)]
909 #ifdef FORBIDDEN_INC_DEC_CLASSES
911 || !forbidden_inc_dec_class[(enum reg_class) class])
913 #ifdef CLASS_CANNOT_CHANGE_MODE
914 && (!REGNO_REG_SET_P (reg_changes_mode, i)
915 || class_can_change_mode [(enum reg_class) class])
918 fprintf (dump, " %s:%i", reg_class_names[class],
919 costs[i].cost[(enum reg_class) class]);
920 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
926 /* Calculate the costs of insn operands. */
929 record_operand_costs (insn, op_costs, reg_pref)
931 struct costs *op_costs;
932 struct reg_pref *reg_pref;
934 const char *constraints[MAX_RECOG_OPERANDS];
935 enum machine_mode modes[MAX_RECOG_OPERANDS];
938 for (i = 0; i < recog_data.n_operands; i++)
940 constraints[i] = recog_data.constraints[i];
941 modes[i] = recog_data.operand_mode[i];
944 /* If we get here, we are set up to record the costs of all the
945 operands for this insn. Start by initializing the costs.
946 Then handle any address registers. Finally record the desired
947 classes for any pseudos, doing it twice if some pair of
948 operands are commutative. */
950 for (i = 0; i < recog_data.n_operands; i++)
952 op_costs[i] = init_cost;
954 if (GET_CODE (recog_data.operand[i]) == SUBREG)
956 rtx inner = SUBREG_REG (recog_data.operand[i]);
957 #ifdef CLASS_CANNOT_CHANGE_MODE
958 if (GET_CODE (inner) == REG
959 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner)))
960 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner));
962 recog_data.operand[i] = inner;
965 if (GET_CODE (recog_data.operand[i]) == MEM)
966 record_address_regs (XEXP (recog_data.operand[i], 0),
967 BASE_REG_CLASS, frequency * 2);
968 else if (constraints[i][0] == 'p')
969 record_address_regs (recog_data.operand[i],
970 BASE_REG_CLASS, frequency * 2);
973 /* Check for commutative in a separate loop so everything will
974 have been initialized. We must do this even if one operand
975 is a constant--see addsi3 in m68k.md. */
977 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
978 if (constraints[i][0] == '%')
980 const char *xconstraints[MAX_RECOG_OPERANDS];
983 /* Handle commutative operands by swapping the constraints.
984 We assume the modes are the same. */
986 for (j = 0; j < recog_data.n_operands; j++)
987 xconstraints[j] = constraints[j];
989 xconstraints[i] = constraints[i+1];
990 xconstraints[i+1] = constraints[i];
991 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
992 recog_data.operand, modes,
993 xconstraints, insn, op_costs, reg_pref);
996 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
997 recog_data.operand, modes,
998 constraints, insn, op_costs, reg_pref);
1001 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
1002 time it would save code to put a certain register in a certain class.
1003 PASS, when nonzero, inhibits some optimizations which need only be done
1005 Return the last insn processed, so that the scan can be continued from
1009 scan_one_insn (insn, pass)
1013 enum rtx_code code = GET_CODE (insn);
1014 enum rtx_code pat_code;
1017 struct costs op_costs[MAX_RECOG_OPERANDS];
1019 if (GET_RTX_CLASS (code) != 'i')
1022 pat_code = GET_CODE (PATTERN (insn));
1024 || pat_code == CLOBBER
1025 || pat_code == ASM_INPUT
1026 || pat_code == ADDR_VEC
1027 || pat_code == ADDR_DIFF_VEC)
1030 set = single_set (insn);
1031 extract_insn (insn);
1033 /* If this insn loads a parameter from its stack slot, then
1034 it represents a savings, rather than a cost, if the
1035 parameter is stored in memory. Record this fact. */
1037 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
1038 && GET_CODE (SET_SRC (set)) == MEM
1039 && (note = find_reg_note (insn, REG_EQUIV,
1041 && GET_CODE (XEXP (note, 0)) == MEM)
1043 costs[REGNO (SET_DEST (set))].mem_cost
1044 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1047 record_address_regs (XEXP (SET_SRC (set), 0),
1048 BASE_REG_CLASS, frequency * 2);
1052 /* Improve handling of two-address insns such as
1053 (set X (ashift CONST Y)) where CONST must be made to
1054 match X. Change it into two insns: (set X CONST)
1055 (set X (ashift X Y)). If we left this for reloading, it
1056 would probably get three insns because X and Y might go
1057 in the same place. This prevents X and Y from receiving
1060 We can only do this if the modes of operands 0 and 1
1061 (which might not be the same) are tieable and we only need
1062 do this during our first pass. */
1064 if (pass == 0 && optimize
1065 && recog_data.n_operands >= 3
1066 && recog_data.constraints[1][0] == '0'
1067 && recog_data.constraints[1][1] == 0
1068 && CONSTANT_P (recog_data.operand[1])
1069 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
1070 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
1071 && GET_CODE (recog_data.operand[0]) == REG
1072 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
1073 recog_data.operand_mode[1]))
1075 rtx previnsn = prev_real_insn (insn);
1077 = gen_lowpart (recog_data.operand_mode[1],
1078 recog_data.operand[0]);
1080 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
1082 /* If this insn was the start of a basic block,
1083 include the new insn in that block.
1084 We need not check for code_label here;
1085 while a basic block can start with a code_label,
1086 INSN could not be at the beginning of that block. */
1087 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1090 for (b = 0; b < n_basic_blocks; b++)
1091 if (insn == BLOCK_HEAD (b))
1092 BLOCK_HEAD (b) = newinsn;
1095 /* This makes one more setting of new insns's dest. */
1096 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1097 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1098 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1100 *recog_data.operand_loc[1] = recog_data.operand[0];
1101 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1102 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1103 for (i = recog_data.n_dups - 1; i >= 0; i--)
1104 if (recog_data.dup_num[i] == 1)
1106 *recog_data.dup_loc[i] = recog_data.operand[0];
1107 REG_N_REFS (REGNO (recog_data.operand[0]))++;
1108 REG_FREQ (REGNO (recog_data.operand[0])) += frequency;
1111 return PREV_INSN (newinsn);
1114 record_operand_costs (insn, op_costs, reg_pref);
1116 /* Now add the cost for each operand to the total costs for
1119 for (i = 0; i < recog_data.n_operands; i++)
1120 if (GET_CODE (recog_data.operand[i]) == REG
1121 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1123 int regno = REGNO (recog_data.operand[i]);
1124 struct costs *p = &costs[regno], *q = &op_costs[i];
1126 p->mem_cost += q->mem_cost * frequency;
1127 for (j = 0; j < N_REG_CLASSES; j++)
1128 p->cost[j] += q->cost[j] * frequency;
1134 /* This is a pass of the compiler that scans all instructions
1135 and calculates the preferred class for each pseudo-register.
1136 This information can be accessed later by calling `reg_preferred_class'.
1137 This pass comes just before local register allocation. */
1140 regclass (f, nregs, dump)
1151 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1153 #ifdef CLASS_CANNOT_CHANGE_MODE
1154 reg_changes_mode = BITMAP_XMALLOC();
1157 #ifdef FORBIDDEN_INC_DEC_CLASSES
1159 in_inc_dec = (char *) xmalloc (nregs);
1161 /* Initialize information about which register classes can be used for
1162 pseudos that are auto-incremented or auto-decremented. It would
1163 seem better to put this in init_reg_sets, but we need to be able
1164 to allocate rtx, which we can't do that early. */
1166 for (i = 0; i < N_REG_CLASSES; i++)
1168 rtx r = gen_rtx_REG (VOIDmode, 0);
1169 enum machine_mode m;
1172 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1173 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1177 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1178 m = (enum machine_mode) ((int) m + 1))
1179 if (HARD_REGNO_MODE_OK (j, m))
1183 /* If a register is not directly suitable for an
1184 auto-increment or decrement addressing mode and
1185 requires secondary reloads, disallow its class from
1186 being used in such addresses. */
1189 #ifdef SECONDARY_RELOAD_CLASS
1190 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1193 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1194 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1197 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1198 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1203 && ! auto_inc_dec_reg_p (r, m))
1204 forbidden_inc_dec_class[i] = 1;
1208 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1210 /* Normally we scan the insns once and determine the best class to use for
1211 each register. However, if -fexpensive_optimizations are on, we do so
1212 twice, the second time using the tentative best classes to guide the
1215 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1220 fprintf (dump, "\n\nPass %i\n\n",pass);
1221 /* Zero out our accumulation of the cost of each class for each reg. */
1223 memset ((char *) costs, 0, nregs * sizeof (struct costs));
1225 #ifdef FORBIDDEN_INC_DEC_CLASSES
1226 memset (in_inc_dec, 0, nregs);
1229 /* Scan the instructions and record each time it would
1230 save code to put a certain register in a certain class. */
1235 for (insn = f; insn; insn = NEXT_INSN (insn))
1236 insn = scan_one_insn (insn, pass);
1239 for (index = 0; index < n_basic_blocks; index++)
1241 basic_block bb = BASIC_BLOCK (index);
1243 /* Show that an insn inside a loop is likely to be executed three
1244 times more than insns outside a loop. This is much more
1245 aggressive than the assumptions made elsewhere and is being
1246 tried as an experiment. */
1250 frequency = bb->frequency ? bb->frequency : 1;
1251 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1253 insn = scan_one_insn (insn, pass);
1254 if (insn == bb->end)
1259 /* Now for each register look at how desirable each class is
1260 and find which class is preferred. Store that in
1261 `prefclass'. Record in `altclass' the largest register
1262 class any of whose registers is better than memory. */
1265 reg_pref = reg_pref_buffer;
1269 dump_regclass (dump);
1270 fprintf (dump,"\n");
1272 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1274 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1275 enum reg_class best = ALL_REGS, alt = NO_REGS;
1276 /* This is an enum reg_class, but we call it an int
1277 to save lots of casts. */
1279 register struct costs *p = &costs[i];
1281 /* In non-optimizing compilation REG_N_REFS is not initialized
1283 if (optimize && !REG_N_REFS (i))
1286 for (class = (int) ALL_REGS - 1; class > 0; class--)
1288 /* Ignore classes that are too small for this operand or
1289 invalid for a operand that was auto-incremented. */
1290 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1291 #ifdef FORBIDDEN_INC_DEC_CLASSES
1292 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1294 #ifdef CLASS_CANNOT_CHANGE_MODE
1295 || (REGNO_REG_SET_P (reg_changes_mode, i)
1296 && ! class_can_change_mode [class])
1300 else if (p->cost[class] < best_cost)
1302 best_cost = p->cost[class];
1303 best = (enum reg_class) class;
1305 else if (p->cost[class] == best_cost)
1306 best = reg_class_subunion[(int)best][class];
1309 /* Record the alternate register class; i.e., a class for which
1310 every register in it is better than using memory. If adding a
1311 class would make a smaller class (i.e., no union of just those
1312 classes exists), skip that class. The major unions of classes
1313 should be provided as a register class. Don't do this if we
1314 will be doing it again later. */
1316 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1317 for (class = 0; class < N_REG_CLASSES; class++)
1318 if (p->cost[class] < p->mem_cost
1319 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1320 > reg_class_size[(int) alt])
1321 #ifdef FORBIDDEN_INC_DEC_CLASSES
1322 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1324 #ifdef CLASS_CANNOT_CHANGE_MODE
1325 && ! (REGNO_REG_SET_P (reg_changes_mode, i)
1326 && ! class_can_change_mode [class])
1329 alt = reg_class_subunion[(int) alt][class];
1331 /* If we don't add any classes, nothing to try. */
1336 && (reg_pref[i].prefclass != (int) best
1337 || reg_pref[i].altclass != (int) alt))
1339 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1340 fprintf (dump, " Register %i", i);
1341 if (alt == ALL_REGS || best == ALL_REGS)
1342 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1343 else if (alt == NO_REGS)
1344 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1346 fprintf (dump, " pref %s, else %s\n",
1347 reg_class_names[(int) best],
1348 reg_class_names[(int) alt]);
1351 /* We cast to (int) because (char) hits bugs in some compilers. */
1352 reg_pref[i].prefclass = (int) best;
1353 reg_pref[i].altclass = (int) alt;
1357 #ifdef FORBIDDEN_INC_DEC_CLASSES
1360 #ifdef CLASS_CANNOT_CHANGE_MODE
1361 BITMAP_XFREE (reg_changes_mode);
1366 /* Record the cost of using memory or registers of various classes for
1367 the operands in INSN.
1369 N_ALTS is the number of alternatives.
1371 N_OPS is the number of operands.
1373 OPS is an array of the operands.
1375 MODES are the modes of the operands, in case any are VOIDmode.
1377 CONSTRAINTS are the constraints to use for the operands. This array
1378 is modified by this procedure.
1380 This procedure works alternative by alternative. For each alternative
1381 we assume that we will be able to allocate all pseudos to their ideal
1382 register class and calculate the cost of using that alternative. Then
1383 we compute for each operand that is a pseudo-register, the cost of
1384 having the pseudo allocated to each register class and using it in that
1385 alternative. To this cost is added the cost of the alternative.
1387 The cost of each class for this insn is its lowest cost among all the
1391 record_reg_classes (n_alts, n_ops, ops, modes,
1392 constraints, insn, op_costs, reg_pref)
1396 enum machine_mode *modes;
1397 const char **constraints;
1399 struct costs *op_costs;
1400 struct reg_pref *reg_pref;
1406 /* Process each alternative, each time minimizing an operand's cost with
1407 the cost for each operand in that alternative. */
1409 for (alt = 0; alt < n_alts; alt++)
1411 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1414 enum reg_class classes[MAX_RECOG_OPERANDS];
1415 int allows_mem[MAX_RECOG_OPERANDS];
1418 for (i = 0; i < n_ops; i++)
1420 const char *p = constraints[i];
1422 enum machine_mode mode = modes[i];
1423 int allows_addr = 0;
1427 /* Initially show we know nothing about the register class. */
1428 classes[i] = NO_REGS;
1431 /* If this operand has no constraints at all, we can conclude
1432 nothing about it since anything is valid. */
1436 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1437 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]);
1442 /* If this alternative is only relevant when this operand
1443 matches a previous operand, we do different things depending
1444 on whether this operand is a pseudo-reg or not. We must process
1445 any modifiers for the operand before we can make this test. */
1447 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1450 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1452 /* Copy class and whether memory is allowed from the matching
1453 alternative. Then perform any needed cost computations
1454 and/or adjustments. */
1456 classes[i] = classes[j];
1457 allows_mem[i] = allows_mem[j];
1459 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1461 /* If this matches the other operand, we have no added
1463 if (rtx_equal_p (ops[j], op))
1466 /* If we can put the other operand into a register, add to
1467 the cost of this alternative the cost to copy this
1468 operand to the register used for the other operand. */
1470 else if (classes[j] != NO_REGS)
1471 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1473 else if (GET_CODE (ops[j]) != REG
1474 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1476 /* This op is a pseudo but the one it matches is not. */
1478 /* If we can't put the other operand into a register, this
1479 alternative can't be used. */
1481 if (classes[j] == NO_REGS)
1484 /* Otherwise, add to the cost of this alternative the cost
1485 to copy the other operand to the register used for this
1489 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1493 /* The costs of this operand are not the same as the other
1494 operand since move costs are not symmetric. Moreover,
1495 if we cannot tie them, this alternative needs to do a
1496 copy, which is one instruction. */
1498 struct costs *pp = &this_op_costs[i];
1500 for (class = 0; class < N_REG_CLASSES; class++)
1502 = ((recog_data.operand_type[i] != OP_OUT
1503 ? may_move_in_cost[mode][class][(int) classes[i]]
1505 + (recog_data.operand_type[i] != OP_IN
1506 ? may_move_out_cost[mode][(int) classes[i]][class]
1509 /* If the alternative actually allows memory, make things
1510 a bit cheaper since we won't need an extra insn to
1514 = ((recog_data.operand_type[i] != OP_IN
1515 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1517 + (recog_data.operand_type[i] != OP_OUT
1518 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1519 : 0) - allows_mem[i]);
1521 /* If we have assigned a class to this register in our
1522 first pass, add a cost to this alternative corresponding
1523 to what we would add if this register were not in the
1524 appropriate class. */
1528 += (may_move_in_cost[mode]
1529 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1530 [(int) classes[i]]);
1532 if (REGNO (ops[i]) != REGNO (ops[j])
1533 && ! find_reg_note (insn, REG_DEAD, op))
1536 /* This is in place of ordinary cost computation
1537 for this operand, so skip to the end of the
1538 alternative (should be just one character). */
1539 while (*p && *p++ != ',')
1547 /* Scan all the constraint letters. See if the operand matches
1548 any of the constraints. Collect the valid register classes
1549 and see if this operand accepts memory. */
1551 while (*p && (c = *p++) != ',')
1555 /* Ignore the next letter for this pass. */
1561 case '!': case '#': case '&':
1562 case '0': case '1': case '2': case '3': case '4':
1563 case '5': case '6': case '7': case '8': case '9':
1568 win = address_operand (op, GET_MODE (op));
1569 /* We know this operand is an address, so we want it to be
1570 allocated to a register that can be the base of an
1571 address, ie BASE_REG_CLASS. */
1573 = reg_class_subunion[(int) classes[i]]
1574 [(int) BASE_REG_CLASS];
1577 case 'm': case 'o': case 'V':
1578 /* It doesn't seem worth distinguishing between offsettable
1579 and non-offsettable addresses here. */
1581 if (GET_CODE (op) == MEM)
1586 if (GET_CODE (op) == MEM
1587 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1588 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1593 if (GET_CODE (op) == MEM
1594 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1595 || GET_CODE (XEXP (op, 0)) == POST_INC))
1600 #ifndef REAL_ARITHMETIC
1601 /* Match any floating double constant, but only if
1602 we can examine the bits of it reliably. */
1603 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1604 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1605 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1608 if (GET_CODE (op) == CONST_DOUBLE)
1613 if (GET_CODE (op) == CONST_DOUBLE)
1619 if (GET_CODE (op) == CONST_DOUBLE
1620 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1625 if (GET_CODE (op) == CONST_INT
1626 || (GET_CODE (op) == CONST_DOUBLE
1627 && GET_MODE (op) == VOIDmode))
1631 #ifdef LEGITIMATE_PIC_OPERAND_P
1632 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1639 if (GET_CODE (op) == CONST_INT
1640 || (GET_CODE (op) == CONST_DOUBLE
1641 && GET_MODE (op) == VOIDmode))
1653 if (GET_CODE (op) == CONST_INT
1654 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1663 if (GET_CODE (op) == MEM
1665 #ifdef LEGITIMATE_PIC_OPERAND_P
1666 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1673 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1677 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1679 = reg_class_subunion[(int) classes[i]]
1680 [(int) REG_CLASS_FROM_LETTER (c)];
1681 #ifdef EXTRA_CONSTRAINT
1682 else if (EXTRA_CONSTRAINT (op, c))
1690 /* How we account for this operand now depends on whether it is a
1691 pseudo register or not. If it is, we first check if any
1692 register classes are valid. If not, we ignore this alternative,
1693 since we want to assume that all pseudos get allocated for
1694 register preferencing. If some register class is valid, compute
1695 the costs of moving the pseudo into that class. */
1697 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1699 if (classes[i] == NO_REGS)
1701 /* We must always fail if the operand is a REG, but
1702 we did not find a suitable class.
1704 Otherwise we may perform an uninitialized read
1705 from this_op_costs after the `continue' statement
1711 struct costs *pp = &this_op_costs[i];
1713 for (class = 0; class < N_REG_CLASSES; class++)
1715 = ((recog_data.operand_type[i] != OP_OUT
1716 ? may_move_in_cost[mode][class][(int) classes[i]]
1718 + (recog_data.operand_type[i] != OP_IN
1719 ? may_move_out_cost[mode][(int) classes[i]][class]
1722 /* If the alternative actually allows memory, make things
1723 a bit cheaper since we won't need an extra insn to
1727 = ((recog_data.operand_type[i] != OP_IN
1728 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1730 + (recog_data.operand_type[i] != OP_OUT
1731 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1732 : 0) - allows_mem[i]);
1734 /* If we have assigned a class to this register in our
1735 first pass, add a cost to this alternative corresponding
1736 to what we would add if this register were not in the
1737 appropriate class. */
1741 += (may_move_in_cost[mode]
1742 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1743 [(int) classes[i]]);
1747 /* Otherwise, if this alternative wins, either because we
1748 have already determined that or if we have a hard register of
1749 the proper class, there is no cost for this alternative. */
1752 || (GET_CODE (op) == REG
1753 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1756 /* If registers are valid, the cost of this alternative includes
1757 copying the object to and/or from a register. */
1759 else if (classes[i] != NO_REGS)
1761 if (recog_data.operand_type[i] != OP_OUT)
1762 alt_cost += copy_cost (op, mode, classes[i], 1);
1764 if (recog_data.operand_type[i] != OP_IN)
1765 alt_cost += copy_cost (op, mode, classes[i], 0);
1768 /* The only other way this alternative can be used is if this is a
1769 constant that could be placed into memory. */
1771 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1772 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1780 /* Finally, update the costs with the information we've calculated
1781 about this alternative. */
1783 for (i = 0; i < n_ops; i++)
1784 if (GET_CODE (ops[i]) == REG
1785 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1787 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1788 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1790 pp->mem_cost = MIN (pp->mem_cost,
1791 (qq->mem_cost + alt_cost) * scale);
1793 for (class = 0; class < N_REG_CLASSES; class++)
1794 pp->cost[class] = MIN (pp->cost[class],
1795 (qq->cost[class] + alt_cost) * scale);
1799 /* If this insn is a single set copying operand 1 to operand 0
1800 and one operand is a pseudo with the other a hard reg or a pseudo
1801 that prefers a register that is in its own register class then
1802 we may want to adjust the cost of that register class to -1.
1804 Avoid the adjustment if the source does not die to avoid stressing of
1805 register allocator by preferrencing two coliding registers into single
1808 Also avoid the adjustment if a copy between registers of the class
1809 is expensive (ten times the cost of a default copy is considered
1810 arbitrarily expensive). This avoids losing when the preferred class
1811 is very expensive as the source of a copy instruction. */
1813 if ((set = single_set (insn)) != 0
1814 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1815 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1816 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1817 for (i = 0; i <= 1; i++)
1818 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1820 unsigned int regno = REGNO (ops[!i]);
1821 enum machine_mode mode = GET_MODE (ops[!i]);
1825 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1827 enum reg_class pref = reg_pref[regno].prefclass;
1829 if ((reg_class_size[(unsigned char) pref]
1830 == CLASS_MAX_NREGS (pref, mode))
1831 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1832 op_costs[i].cost[(unsigned char) pref] = -1;
1834 else if (regno < FIRST_PSEUDO_REGISTER)
1835 for (class = 0; class < N_REG_CLASSES; class++)
1836 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1837 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1839 if (reg_class_size[class] == 1)
1840 op_costs[i].cost[class] = -1;
1843 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1845 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1850 if (nr == HARD_REGNO_NREGS (regno,mode))
1851 op_costs[i].cost[class] = -1;
1857 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1858 TO_P is zero) a register of class CLASS in mode MODE.
1860 X must not be a pseudo. */
1863 copy_cost (x, mode, class, to_p)
1865 enum machine_mode mode ATTRIBUTE_UNUSED;
1866 enum reg_class class;
1867 int to_p ATTRIBUTE_UNUSED;
1869 #ifdef HAVE_SECONDARY_RELOADS
1870 enum reg_class secondary_class = NO_REGS;
1873 /* If X is a SCRATCH, there is actually nothing to move since we are
1874 assuming optimal allocation. */
1876 if (GET_CODE (x) == SCRATCH)
1879 /* Get the class we will actually use for a reload. */
1880 class = PREFERRED_RELOAD_CLASS (x, class);
1882 #ifdef HAVE_SECONDARY_RELOADS
1883 /* If we need a secondary reload (we assume here that we are using
1884 the secondary reload as an intermediate, not a scratch register), the
1885 cost is that to load the input into the intermediate register, then
1886 to copy them. We use a special value of TO_P to avoid recursion. */
1888 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1890 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1893 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1895 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1898 if (secondary_class != NO_REGS)
1899 return (move_cost[mode][(int) secondary_class][(int) class]
1900 + copy_cost (x, mode, secondary_class, 2));
1901 #endif /* HAVE_SECONDARY_RELOADS */
1903 /* For memory, use the memory move cost, for (hard) registers, use the
1904 cost to move between the register classes, and use 2 for everything
1905 else (constants). */
1907 if (GET_CODE (x) == MEM || class == NO_REGS)
1908 return MEMORY_MOVE_COST (mode, class, to_p);
1910 else if (GET_CODE (x) == REG)
1911 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1914 /* If this is a constant, we may eventually want to call rtx_cost here. */
1915 return COSTS_N_INSNS (1);
1918 /* Record the pseudo registers we must reload into hard registers
1919 in a subexpression of a memory address, X.
1921 CLASS is the class that the register needs to be in and is either
1922 BASE_REG_CLASS or INDEX_REG_CLASS.
1924 SCALE is twice the amount to multiply the cost by (it is twice so we
1925 can represent half-cost adjustments). */
1928 record_address_regs (x, class, scale)
1930 enum reg_class class;
1933 register enum rtx_code code = GET_CODE (x);
1946 /* When we have an address that is a sum,
1947 we must determine whether registers are "base" or "index" regs.
1948 If there is a sum of two registers, we must choose one to be
1949 the "base". Luckily, we can use the REG_POINTER to make a good
1950 choice most of the time. We only need to do this on machines
1951 that can have two registers in an address and where the base
1952 and index register classes are different.
1954 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1955 that seems bogus since it should only be set when we are sure
1956 the register is being used as a pointer. */
1959 rtx arg0 = XEXP (x, 0);
1960 rtx arg1 = XEXP (x, 1);
1961 register enum rtx_code code0 = GET_CODE (arg0);
1962 register enum rtx_code code1 = GET_CODE (arg1);
1964 /* Look inside subregs. */
1965 if (code0 == SUBREG)
1966 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1967 if (code1 == SUBREG)
1968 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1970 /* If this machine only allows one register per address, it must
1971 be in the first operand. */
1973 if (MAX_REGS_PER_ADDRESS == 1)
1974 record_address_regs (arg0, class, scale);
1976 /* If index and base registers are the same on this machine, just
1977 record registers in any non-constant operands. We assume here,
1978 as well as in the tests below, that all addresses are in
1981 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1983 record_address_regs (arg0, class, scale);
1984 if (! CONSTANT_P (arg1))
1985 record_address_regs (arg1, class, scale);
1988 /* If the second operand is a constant integer, it doesn't change
1989 what class the first operand must be. */
1991 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1992 record_address_regs (arg0, class, scale);
1994 /* If the second operand is a symbolic constant, the first operand
1995 must be an index register. */
1997 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1998 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2000 /* If both operands are registers but one is already a hard register
2001 of index or base class, give the other the class that the hard
2004 #ifdef REG_OK_FOR_BASE_P
2005 else if (code0 == REG && code1 == REG
2006 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
2007 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
2008 record_address_regs (arg1,
2009 REG_OK_FOR_BASE_P (arg0)
2010 ? INDEX_REG_CLASS : BASE_REG_CLASS,
2012 else if (code0 == REG && code1 == REG
2013 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
2014 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
2015 record_address_regs (arg0,
2016 REG_OK_FOR_BASE_P (arg1)
2017 ? INDEX_REG_CLASS : BASE_REG_CLASS,
2021 /* If one operand is known to be a pointer, it must be the base
2022 with the other operand the index. Likewise if the other operand
2025 else if ((code0 == REG && REG_POINTER (arg0))
2028 record_address_regs (arg0, BASE_REG_CLASS, scale);
2029 record_address_regs (arg1, INDEX_REG_CLASS, scale);
2031 else if ((code1 == REG && REG_POINTER (arg1))
2034 record_address_regs (arg0, INDEX_REG_CLASS, scale);
2035 record_address_regs (arg1, BASE_REG_CLASS, scale);
2038 /* Otherwise, count equal chances that each might be a base
2039 or index register. This case should be rare. */
2043 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
2044 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
2045 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
2046 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
2051 /* Double the importance of a pseudo register that is incremented
2052 or decremented, since it would take two extra insns
2053 if it ends up in the wrong place. */
2056 record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale);
2057 if (REG_P (XEXP (XEXP (x, 1), 1)))
2058 record_address_regs (XEXP (XEXP (x, 1), 1),
2059 INDEX_REG_CLASS, 2 * scale);
2066 /* Double the importance of a pseudo register that is incremented
2067 or decremented, since it would take two extra insns
2068 if it ends up in the wrong place. If the operand is a pseudo,
2069 show it is being used in an INC_DEC context. */
2071 #ifdef FORBIDDEN_INC_DEC_CLASSES
2072 if (GET_CODE (XEXP (x, 0)) == REG
2073 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2074 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2077 record_address_regs (XEXP (x, 0), class, 2 * scale);
2082 register struct costs *pp = &costs[REGNO (x)];
2085 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2087 for (i = 0; i < N_REG_CLASSES; i++)
2088 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2094 register const char *fmt = GET_RTX_FORMAT (code);
2096 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2098 record_address_regs (XEXP (x, i), class, scale);
2103 #ifdef FORBIDDEN_INC_DEC_CLASSES
2105 /* Return 1 if REG is valid as an auto-increment memory reference
2106 to an object of MODE. */
2109 auto_inc_dec_reg_p (reg, mode)
2111 enum machine_mode mode;
2113 if (HAVE_POST_INCREMENT
2114 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2117 if (HAVE_POST_DECREMENT
2118 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2121 if (HAVE_PRE_INCREMENT
2122 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2125 if (HAVE_PRE_DECREMENT
2126 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2133 static short *renumber;
2134 static size_t regno_allocated;
2135 static unsigned int reg_n_max;
2137 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2138 reg_scan and flow_analysis that are indexed by the register number. If
2139 NEW_P is non zero, initialize all of the registers, otherwise only
2140 initialize the new registers allocated. The same table is kept from
2141 function to function, only reallocating it when we need more room. If
2142 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2145 allocate_reg_info (num_regs, new_p, renumber_p)
2151 size_t size_renumber;
2152 size_t min = (new_p) ? 0 : reg_n_max;
2153 struct reg_info_data *reg_data;
2155 if (num_regs > regno_allocated)
2157 size_t old_allocated = regno_allocated;
2159 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2160 size_renumber = regno_allocated * sizeof (short);
2164 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2165 renumber = (short *) xmalloc (size_renumber);
2166 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2167 * sizeof (struct reg_pref));
2172 VARRAY_GROW (reg_n_info, regno_allocated);
2174 if (new_p) /* if we're zapping everything, no need to realloc */
2176 free ((char *)renumber);
2177 free ((char *)reg_pref);
2178 renumber = (short *) xmalloc (size_renumber);
2179 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2180 * sizeof (struct reg_pref));
2185 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2186 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2188 * sizeof (struct reg_pref));
2192 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2193 + sizeof (struct reg_info_data) - sizeof (reg_info);
2194 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2195 reg_data->min_index = old_allocated;
2196 reg_data->max_index = regno_allocated - 1;
2197 reg_data->next = reg_info_head;
2198 reg_info_head = reg_data;
2201 reg_n_max = num_regs;
2204 /* Loop through each of the segments allocated for the actual
2205 reg_info pages, and set up the pointers, zero the pages, etc. */
2206 for (reg_data = reg_info_head;
2207 reg_data && reg_data->max_index >= min;
2208 reg_data = reg_data->next)
2210 size_t min_index = reg_data->min_index;
2211 size_t max_index = reg_data->max_index;
2212 size_t max = MIN (max_index, num_regs);
2213 size_t local_min = min - min_index;
2216 if (reg_data->min_index > num_regs)
2219 if (min < min_index)
2221 if (!reg_data->used_p) /* page just allocated with calloc */
2222 reg_data->used_p = 1; /* no need to zero */
2224 memset ((char *) ®_data->data[local_min], 0,
2225 sizeof (reg_info) * (max - min_index - local_min + 1));
2227 for (i = min_index+local_min; i <= max; i++)
2229 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
2230 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2232 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2233 reg_pref_buffer[i].altclass = (char) NO_REGS;
2238 /* If {pref,alt}class have already been allocated, update the pointers to
2239 the newly realloced ones. */
2241 reg_pref = reg_pref_buffer;
2244 reg_renumber = renumber;
2246 /* Tell the regset code about the new number of registers */
2247 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2250 /* Free up the space allocated by allocate_reg_info. */
2256 struct reg_info_data *reg_data;
2257 struct reg_info_data *reg_next;
2259 VARRAY_FREE (reg_n_info);
2260 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2262 reg_next = reg_data->next;
2263 free ((char *)reg_data);
2266 free (reg_pref_buffer);
2267 reg_pref_buffer = (struct reg_pref *)0;
2268 reg_info_head = (struct reg_info_data *)0;
2269 renumber = (short *)0;
2271 regno_allocated = 0;
2275 /* This is the `regscan' pass of the compiler, run just before cse
2276 and again just before loop.
2278 It finds the first and last use of each pseudo-register
2279 and records them in the vectors regno_first_uid, regno_last_uid
2280 and counts the number of sets in the vector reg_n_sets.
2282 REPEAT is nonzero the second time this is called. */
2284 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2285 Always at least 3, since the combiner could put that many together
2286 and we want this to remain correct for all the remaining passes.
2287 This corresponds to the maximum number of times note_stores will call
2288 a function for any insn. */
2292 /* Used as a temporary to record the largest number of registers in
2293 PARALLEL in a SET_DEST. This is added to max_parallel. */
2295 static int max_set_parallel;
2298 reg_scan (f, nregs, repeat)
2301 int repeat ATTRIBUTE_UNUSED;
2305 allocate_reg_info (nregs, TRUE, FALSE);
2307 max_set_parallel = 0;
2309 for (insn = f; insn; insn = NEXT_INSN (insn))
2310 if (GET_CODE (insn) == INSN
2311 || GET_CODE (insn) == CALL_INSN
2312 || GET_CODE (insn) == JUMP_INSN)
2314 if (GET_CODE (PATTERN (insn)) == PARALLEL
2315 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2316 max_parallel = XVECLEN (PATTERN (insn), 0);
2317 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2319 if (REG_NOTES (insn))
2320 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2323 max_parallel += max_set_parallel;
2326 /* Update 'regscan' information by looking at the insns
2327 from FIRST to LAST. Some new REGs have been created,
2328 and any REG with number greater than OLD_MAX_REGNO is
2329 such a REG. We only update information for those. */
2332 reg_scan_update (first, last, old_max_regno)
2335 unsigned int old_max_regno;
2339 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2341 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2342 if (GET_CODE (insn) == INSN
2343 || GET_CODE (insn) == CALL_INSN
2344 || GET_CODE (insn) == JUMP_INSN)
2346 if (GET_CODE (PATTERN (insn)) == PARALLEL
2347 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2348 max_parallel = XVECLEN (PATTERN (insn), 0);
2349 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2351 if (REG_NOTES (insn))
2352 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2356 /* X is the expression to scan. INSN is the insn it appears in.
2357 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2358 We should only record information for REGs with numbers
2359 greater than or equal to MIN_REGNO. */
2362 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2366 unsigned int min_regno;
2368 register enum rtx_code code;
2372 code = GET_CODE (x);
2388 unsigned int regno = REGNO (x);
2390 if (regno >= min_regno)
2392 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2394 REGNO_LAST_UID (regno) = INSN_UID (insn);
2395 if (REGNO_FIRST_UID (regno) == 0)
2396 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2403 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2405 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2410 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2414 /* Count a set of the destination if it is a register. */
2415 for (dest = SET_DEST (x);
2416 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2417 || GET_CODE (dest) == ZERO_EXTEND;
2418 dest = XEXP (dest, 0))
2421 /* For a PARALLEL, record the number of things (less the usual one for a
2422 SET) that are set. */
2423 if (GET_CODE (dest) == PARALLEL)
2424 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2426 if (GET_CODE (dest) == REG
2427 && REGNO (dest) >= min_regno)
2428 REG_N_SETS (REGNO (dest))++;
2430 /* If this is setting a pseudo from another pseudo or the sum of a
2431 pseudo and a constant integer and the other pseudo is known to be
2432 a pointer, set the destination to be a pointer as well.
2434 Likewise if it is setting the destination from an address or from a
2435 value equivalent to an address or to the sum of an address and
2438 But don't do any of this if the pseudo corresponds to a user
2439 variable since it should have already been set as a pointer based
2442 if (GET_CODE (SET_DEST (x)) == REG
2443 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2444 && REGNO (SET_DEST (x)) >= min_regno
2445 /* If the destination pseudo is set more than once, then other
2446 sets might not be to a pointer value (consider access to a
2447 union in two threads of control in the presense of global
2448 optimizations). So only set REG_POINTER on the destination
2449 pseudo if this is the only set of that pseudo. */
2450 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2451 && ! REG_USERVAR_P (SET_DEST (x))
2452 && ! REG_POINTER (SET_DEST (x))
2453 && ((GET_CODE (SET_SRC (x)) == REG
2454 && REG_POINTER (SET_SRC (x)))
2455 || ((GET_CODE (SET_SRC (x)) == PLUS
2456 || GET_CODE (SET_SRC (x)) == LO_SUM)
2457 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2458 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2459 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2460 || GET_CODE (SET_SRC (x)) == CONST
2461 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2462 || GET_CODE (SET_SRC (x)) == LABEL_REF
2463 || (GET_CODE (SET_SRC (x)) == HIGH
2464 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2465 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2466 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2467 || ((GET_CODE (SET_SRC (x)) == PLUS
2468 || GET_CODE (SET_SRC (x)) == LO_SUM)
2469 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2470 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2471 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2472 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2473 && (GET_CODE (XEXP (note, 0)) == CONST
2474 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2475 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2476 REG_POINTER (SET_DEST (x)) = 1;
2478 /* ... fall through ... */
2482 register const char *fmt = GET_RTX_FORMAT (code);
2484 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2487 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2488 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2491 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2492 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2499 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2503 reg_class_subset_p (c1, c2)
2504 register enum reg_class c1;
2505 register enum reg_class c2;
2507 if (c1 == c2) return 1;
2512 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2513 reg_class_contents[(int)c2],
2518 /* Return nonzero if there is a register that is in both C1 and C2. */
2521 reg_classes_intersect_p (c1, c2)
2522 register enum reg_class c1;
2523 register enum reg_class c2;
2530 if (c1 == c2) return 1;
2532 if (c1 == ALL_REGS || c2 == ALL_REGS)
2535 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2536 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2538 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2545 /* Release any memory allocated by register sets. */
2548 regset_release_memory ()
2550 bitmap_release_memory ();