1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
30 #include "hard-reg-set.h"
32 #include "basic-block.h"
35 #include "insn-config.h"
42 #ifndef REGISTER_MOVE_COST
43 #define REGISTER_MOVE_COST(x, y) 2
46 static void init_reg_sets_1 PROTO((void));
47 static void init_reg_modes PROTO((void));
49 /* If we have auto-increment or auto-decrement and we can have secondary
50 reloads, we are not allowed to use classes requiring secondary
51 reloads for pseudos auto-incremented since reload can't handle it. */
54 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
55 #define FORBIDDEN_INC_DEC_CLASSES
59 /* Register tables used by many passes. */
61 /* Indexed by hard register number, contains 1 for registers
62 that are fixed use (stack pointer, pc, frame pointer, etc.).
63 These are the registers that cannot be used to allocate
64 a pseudo reg for general use. */
66 char fixed_regs[FIRST_PSEUDO_REGISTER];
68 /* Same info as a HARD_REG_SET. */
70 HARD_REG_SET fixed_reg_set;
72 /* Data for initializing the above. */
74 static char initial_fixed_regs[] = FIXED_REGISTERS;
76 /* Indexed by hard register number, contains 1 for registers
77 that are fixed use or are clobbered by function calls.
78 These are the registers that cannot be used to allocate
79 a pseudo reg whose life crosses calls unless we are able
80 to save/restore them across the calls. */
82 char call_used_regs[FIRST_PSEUDO_REGISTER];
84 /* Same info as a HARD_REG_SET. */
86 HARD_REG_SET call_used_reg_set;
88 /* HARD_REG_SET of registers we want to avoid caller saving. */
89 HARD_REG_SET losing_caller_save_reg_set;
91 /* Data for initializing the above. */
93 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
95 /* Indexed by hard register number, contains 1 for registers that are
96 fixed use or call used registers that cannot hold quantities across
97 calls even if we are willing to save and restore them. call fixed
98 registers are a subset of call used registers. */
100 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
102 /* The same info as a HARD_REG_SET. */
104 HARD_REG_SET call_fixed_reg_set;
106 /* Number of non-fixed registers. */
108 int n_non_fixed_regs;
110 /* Indexed by hard register number, contains 1 for registers
111 that are being used for global register decls.
112 These must be exempt from ordinary flow analysis
113 and are also considered fixed. */
115 char global_regs[FIRST_PSEUDO_REGISTER];
117 /* Table of register numbers in the order in which to try to use them. */
118 #ifdef REG_ALLOC_ORDER
119 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
122 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
124 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
126 /* The same information, but as an array of unsigned ints. We copy from
127 these unsigned ints to the table above. We do this so the tm.h files
128 do not have to be aware of the wordsize for machines with <= 64 regs. */
131 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
133 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
134 = REG_CLASS_CONTENTS;
136 /* For each reg class, number of regs it contains. */
138 int reg_class_size[N_REG_CLASSES];
140 /* For each reg class, table listing all the containing classes. */
142 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
144 /* For each reg class, table listing all the classes contained in it. */
146 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
148 /* For each pair of reg classes,
149 a largest reg class contained in their union. */
151 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
153 /* For each pair of reg classes,
154 the smallest reg class containing their union. */
156 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
158 /* Array containing all of the register names */
160 char *reg_names[] = REGISTER_NAMES;
162 /* For each hard register, the widest mode object that it can contain.
163 This will be a MODE_INT mode if the register can hold integers. Otherwise
164 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
167 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
169 /* Maximum cost of moving from a register in one class to a register in
170 another class. Based on REGISTER_MOVE_COST. */
172 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
174 /* Similar, but here we don't have to move if the first index is a subset
175 of the second so in that case the cost is zero. */
177 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
179 #ifdef FORBIDDEN_INC_DEC_CLASSES
181 /* These are the classes that regs which are auto-incremented or decremented
184 static int forbidden_inc_dec_class[N_REG_CLASSES];
186 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
189 static char *in_inc_dec;
191 #endif /* FORBIDDEN_INC_DEC_CLASSES */
193 #ifdef HAVE_SECONDARY_RELOADS
195 /* Sample MEM values for use by memory_move_secondary_cost. */
197 static rtx top_of_stack[MAX_MACHINE_MODE];
199 #endif /* HAVE_SECONDARY_RELOADS */
201 /* Linked list of reg_info structures allocated for reg_n_info array.
202 Grouping all of the allocated structures together in one lump
203 means only one call to bzero to clear them, rather than n smaller
205 struct reg_info_data {
206 struct reg_info_data *next; /* next set of reg_info structures */
207 size_t min_index; /* minimum index # */
208 size_t max_index; /* maximum index # */
209 char used_p; /* non-zero if this has been used previously */
210 reg_info data[1]; /* beginning of the reg_info data */
213 static struct reg_info_data *reg_info_head;
216 /* Function called only once to initialize the above data on reg usage.
217 Once this is done, various switches may override. */
224 /* First copy the register information from the initial int form into
227 for (i = 0; i < N_REG_CLASSES; i++)
229 CLEAR_HARD_REG_SET (reg_class_contents[i]);
231 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
232 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
233 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
234 SET_HARD_REG_BIT (reg_class_contents[i], j);
237 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
238 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
239 bzero (global_regs, sizeof global_regs);
241 /* Do any additional initialization regsets may need */
242 INIT_ONCE_REG_SET ();
245 /* After switches have been processed, which perhaps alter
246 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
251 register unsigned int i, j;
253 /* This macro allows the fixed or call-used registers
254 and the register classes to depend on target flags. */
256 #ifdef CONDITIONAL_REGISTER_USAGE
257 CONDITIONAL_REGISTER_USAGE;
260 /* Compute number of hard regs in each class. */
262 bzero ((char *) reg_class_size, sizeof reg_class_size);
263 for (i = 0; i < N_REG_CLASSES; i++)
264 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
265 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
268 /* Initialize the table of subunions.
269 reg_class_subunion[I][J] gets the largest-numbered reg-class
270 that is contained in the union of classes I and J. */
272 for (i = 0; i < N_REG_CLASSES; i++)
274 for (j = 0; j < N_REG_CLASSES; j++)
277 register /* Declare it register if it's a scalar. */
282 COPY_HARD_REG_SET (c, reg_class_contents[i]);
283 IOR_HARD_REG_SET (c, reg_class_contents[j]);
284 for (k = 0; k < N_REG_CLASSES; k++)
286 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
291 /* keep the largest subclass */ /* SPEE 900308 */
292 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
293 reg_class_contents[(int) reg_class_subunion[i][j]],
295 reg_class_subunion[i][j] = (enum reg_class) k;
302 /* Initialize the table of superunions.
303 reg_class_superunion[I][J] gets the smallest-numbered reg-class
304 containing the union of classes I and J. */
306 for (i = 0; i < N_REG_CLASSES; i++)
308 for (j = 0; j < N_REG_CLASSES; j++)
311 register /* Declare it register if it's a scalar. */
316 COPY_HARD_REG_SET (c, reg_class_contents[i]);
317 IOR_HARD_REG_SET (c, reg_class_contents[j]);
318 for (k = 0; k < N_REG_CLASSES; k++)
319 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
322 reg_class_superunion[i][j] = (enum reg_class) k;
326 /* Initialize the tables of subclasses and superclasses of each reg class.
327 First clear the whole table, then add the elements as they are found. */
329 for (i = 0; i < N_REG_CLASSES; i++)
331 for (j = 0; j < N_REG_CLASSES; j++)
333 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
334 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
338 for (i = 0; i < N_REG_CLASSES; i++)
340 if (i == (int) NO_REGS)
343 for (j = i + 1; j < N_REG_CLASSES; j++)
347 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
351 /* Reg class I is a subclass of J.
352 Add J to the table of superclasses of I. */
353 p = ®_class_superclasses[i][0];
354 while (*p != LIM_REG_CLASSES) p++;
355 *p = (enum reg_class) j;
356 /* Add I to the table of superclasses of J. */
357 p = ®_class_subclasses[j][0];
358 while (*p != LIM_REG_CLASSES) p++;
359 *p = (enum reg_class) i;
363 /* Initialize "constant" tables. */
365 CLEAR_HARD_REG_SET (fixed_reg_set);
366 CLEAR_HARD_REG_SET (call_used_reg_set);
367 CLEAR_HARD_REG_SET (call_fixed_reg_set);
369 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
371 n_non_fixed_regs = 0;
373 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
376 SET_HARD_REG_BIT (fixed_reg_set, i);
380 if (call_used_regs[i])
381 SET_HARD_REG_BIT (call_used_reg_set, i);
382 if (call_fixed_regs[i])
383 SET_HARD_REG_BIT (call_fixed_reg_set, i);
384 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
385 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
388 /* Initialize the move cost table. Find every subset of each class
389 and take the maximum cost of moving any subset to any other. */
391 for (i = 0; i < N_REG_CLASSES; i++)
392 for (j = 0; j < N_REG_CLASSES; j++)
394 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
395 enum reg_class *p1, *p2;
397 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
399 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
401 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
404 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
406 for (p2 = ®_class_subclasses[j][0];
407 *p2 != LIM_REG_CLASSES; p2++)
409 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
412 move_cost[i][j] = cost;
414 if (reg_class_subset_p (i, j))
417 may_move_cost[i][j] = cost;
421 /* Compute the table of register modes.
422 These values are used to record death information for individual registers
423 (as opposed to a multi-register mode). */
430 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
432 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
434 /* If we couldn't find a valid mode, just use the previous mode.
435 ??? One situation in which we need to do this is on the mips where
436 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
437 to use DF mode for the even registers and VOIDmode for the odd
438 (for the cpu models where the odd ones are inaccessible). */
439 if (reg_raw_mode[i] == VOIDmode)
440 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
444 /* Finish initializing the register sets and
445 initialize the register modes. */
450 /* This finishes what was started by init_reg_sets, but couldn't be done
451 until after register usage was specified. */
456 #ifdef HAVE_SECONDARY_RELOADS
458 /* Make some fake stack-frame MEM references for use in
459 memory_move_secondary_cost. */
461 for (i = 0; i < MAX_MACHINE_MODE; i++)
462 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
463 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
468 #ifdef HAVE_SECONDARY_RELOADS
470 /* Compute extra cost of moving registers to/from memory due to reloads.
471 Only needed if secondary reloads are required for memory moves. */
474 memory_move_secondary_cost (mode, class, in)
475 enum machine_mode mode;
476 enum reg_class class;
479 enum reg_class altclass;
480 int partial_cost = 0;
481 /* We need a memory reference to feed to SECONDARY... macros. */
482 rtx mem = top_of_stack[(int) mode];
486 #ifdef SECONDARY_INPUT_RELOAD_CLASS
487 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
494 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
495 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
501 if (altclass == NO_REGS)
505 partial_cost = REGISTER_MOVE_COST (altclass, class);
507 partial_cost = REGISTER_MOVE_COST (class, altclass);
509 if (class == altclass)
510 /* This isn't simply a copy-to-temporary situation. Can't guess
511 what it is, so MEMORY_MOVE_COST really ought not to be calling
514 I'm tempted to put in an abort here, but returning this will
515 probably only give poor estimates, which is what we would've
516 had before this code anyways. */
519 /* Check if the secondary reload register will also need a
521 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
525 /* Return a machine mode that is legitimate for hard reg REGNO and large
526 enough to save nregs. If we can't find one, return VOIDmode. */
529 choose_hard_reg_mode (regno, nregs)
533 enum machine_mode found_mode = VOIDmode, mode;
535 /* We first look for the largest integer mode that can be validly
536 held in REGNO. If none, we look for the largest floating-point mode.
537 If we still didn't find a valid mode, try CCmode. */
539 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
541 mode = GET_MODE_WIDER_MODE (mode))
542 if (HARD_REGNO_NREGS (regno, mode) == nregs
543 && HARD_REGNO_MODE_OK (regno, mode))
546 if (found_mode != VOIDmode)
549 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
551 mode = GET_MODE_WIDER_MODE (mode))
552 if (HARD_REGNO_NREGS (regno, mode) == nregs
553 && HARD_REGNO_MODE_OK (regno, mode))
556 if (found_mode != VOIDmode)
559 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
560 && HARD_REGNO_MODE_OK (regno, CCmode))
563 /* We can't find a mode valid for this register. */
567 /* Specify the usage characteristics of the register named NAME.
568 It should be a fixed register if FIXED and a
569 call-used register if CALL_USED. */
572 fix_register (name, fixed, call_used)
574 int fixed, call_used;
578 /* Decode the name and update the primary form of
579 the register info. */
581 if ((i = decode_reg_name (name)) >= 0)
583 if ((i == STACK_POINTER_REGNUM
584 #ifdef HARD_FRAME_POINTER_REGNUM
585 || i == HARD_FRAME_POINTER_REGNUM
587 || i == FRAME_POINTER_REGNUM
590 && (fixed == 0 || call_used == 0))
592 static const char * const what_option[2][2] = {
593 { "call-saved", "call-used" },
594 { "no-such-option", "fixed" }};
596 error ("can't use '%s' as a %s register", name,
597 what_option[fixed][call_used]);
601 fixed_regs[i] = fixed;
602 call_used_regs[i] = call_used;
607 warning ("unknown register name: %s", name);
611 /* Mark register number I as global. */
619 warning ("register used for two global register variables");
623 if (call_used_regs[i] && ! fixed_regs[i])
624 warning ("call-clobbered register used for global register variable");
628 /* If already fixed, nothing else to do. */
632 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
635 SET_HARD_REG_BIT (fixed_reg_set, i);
636 SET_HARD_REG_BIT (call_used_reg_set, i);
637 SET_HARD_REG_BIT (call_fixed_reg_set, i);
640 /* Now the data and code for the `regclass' pass, which happens
641 just before local-alloc. */
643 /* The `costs' struct records the cost of using a hard register of each class
644 and of using memory for each pseudo. We use this data to set up
645 register class preferences. */
649 int cost[N_REG_CLASSES];
653 /* Record the cost of each class for each pseudo. */
655 static struct costs *costs;
657 /* Initialized once, and used to initialize cost values for each insn. */
659 static struct costs init_cost;
661 /* Record the same data by operand number, accumulated for each alternative
662 in an insn. The contribution to a pseudo is that of the minimum-cost
665 static struct costs op_costs[MAX_RECOG_OPERANDS];
667 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
668 This is available after `regclass' is run. */
670 static char *prefclass;
672 /* altclass[R] is a register class that we should use for allocating
673 pseudo number R if no register in the preferred class is available.
674 If no register in this class is available, memory is preferred.
676 It might appear to be more general to have a bitmask of classes here,
677 but since it is recommended that there be a class corresponding to the
678 union of most major pair of classes, that generality is not required.
680 This is available after `regclass' is run. */
682 static char *altclass;
684 /* Allocated buffers for prefclass and altclass. */
685 static char *prefclass_buffer;
686 static char *altclass_buffer;
688 /* Record the depth of loops that we are in. */
690 static int loop_depth;
692 /* Account for the fact that insns within a loop are executed very commonly,
693 but don't keep doing this as loops go too deep. */
695 static int loop_cost;
697 static rtx scan_one_insn PROTO((rtx, int));
698 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
699 char *, const char **, rtx));
700 static int copy_cost PROTO((rtx, enum machine_mode,
701 enum reg_class, int));
702 static void record_address_regs PROTO((rtx, enum reg_class, int));
703 #ifdef FORBIDDEN_INC_DEC_CLASSES
704 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
706 static void reg_scan_mark_refs PROTO((rtx, rtx, int, int));
708 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
709 This function is sometimes called before the info has been computed.
710 When that happens, just return GENERAL_REGS, which is innocuous. */
713 reg_preferred_class (regno)
718 return (enum reg_class) prefclass[regno];
722 reg_alternate_class (regno)
728 return (enum reg_class) altclass[regno];
731 /* Initialize some global data for this pass. */
738 init_cost.mem_cost = 10000;
739 for (i = 0; i < N_REG_CLASSES; i++)
740 init_cost.cost[i] = 10000;
742 /* This prevents dump_flow_info from losing if called
743 before regclass is run. */
747 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
748 time it would save code to put a certain register in a certain class.
749 PASS, when nonzero, inhibits some optimizations which need only be done
751 Return the last insn processed, so that the scan can be continued from
755 scan_one_insn (insn, pass)
759 enum rtx_code code = GET_CODE (insn);
760 enum rtx_code pat_code;
761 const char *constraints[MAX_RECOG_OPERANDS];
762 enum machine_mode modes[MAX_RECOG_OPERANDS];
763 char subreg_changes_size[MAX_RECOG_OPERANDS];
767 /* Show that an insn inside a loop is likely to be executed three
768 times more than insns outside a loop. This is much more aggressive
769 than the assumptions made elsewhere and is being tried as an
774 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
775 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
776 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
777 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
782 if (GET_RTX_CLASS (code) != 'i')
785 pat_code = GET_CODE (PATTERN (insn));
787 || pat_code == CLOBBER
788 || pat_code == ASM_INPUT
789 || pat_code == ADDR_VEC
790 || pat_code == ADDR_DIFF_VEC)
793 set = single_set (insn);
796 for (i = 0; i < recog_data.n_operands; i++)
798 constraints[i] = recog_data.constraints[i];
799 modes[i] = recog_data.operand_mode[i];
801 memset (subreg_changes_size, 0, sizeof (subreg_changes_size));
803 /* If this insn loads a parameter from its stack slot, then
804 it represents a savings, rather than a cost, if the
805 parameter is stored in memory. Record this fact. */
807 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
808 && GET_CODE (SET_SRC (set)) == MEM
809 && (note = find_reg_note (insn, REG_EQUIV,
811 && GET_CODE (XEXP (note, 0)) == MEM)
813 costs[REGNO (SET_DEST (set))].mem_cost
814 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
817 record_address_regs (XEXP (SET_SRC (set), 0),
818 BASE_REG_CLASS, loop_cost * 2);
822 /* Improve handling of two-address insns such as
823 (set X (ashift CONST Y)) where CONST must be made to
824 match X. Change it into two insns: (set X CONST)
825 (set X (ashift X Y)). If we left this for reloading, it
826 would probably get three insns because X and Y might go
827 in the same place. This prevents X and Y from receiving
830 We can only do this if the modes of operands 0 and 1
831 (which might not be the same) are tieable and we only need
832 do this during our first pass. */
834 if (pass == 0 && optimize
835 && recog_data.n_operands >= 3
836 && recog_data.constraints[1][0] == '0'
837 && recog_data.constraints[1][1] == 0
838 && CONSTANT_P (recog_data.operand[1])
839 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
840 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
841 && GET_CODE (recog_data.operand[0]) == REG
842 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
843 recog_data.operand_mode[1]))
845 rtx previnsn = prev_real_insn (insn);
847 = gen_lowpart (recog_data.operand_mode[1],
848 recog_data.operand[0]);
850 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
852 /* If this insn was the start of a basic block,
853 include the new insn in that block.
854 We need not check for code_label here;
855 while a basic block can start with a code_label,
856 INSN could not be at the beginning of that block. */
857 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
860 for (b = 0; b < n_basic_blocks; b++)
861 if (insn == BLOCK_HEAD (b))
862 BLOCK_HEAD (b) = newinsn;
865 /* This makes one more setting of new insns's dest. */
866 REG_N_SETS (REGNO (recog_data.operand[0]))++;
868 *recog_data.operand_loc[1] = recog_data.operand[0];
869 for (i = recog_data.n_dups - 1; i >= 0; i--)
870 if (recog_data.dup_num[i] == 1)
871 *recog_data.dup_loc[i] = recog_data.operand[0];
873 return PREV_INSN (newinsn);
876 /* If we get here, we are set up to record the costs of all the
877 operands for this insn. Start by initializing the costs.
878 Then handle any address registers. Finally record the desired
879 classes for any pseudos, doing it twice if some pair of
880 operands are commutative. */
882 for (i = 0; i < recog_data.n_operands; i++)
884 op_costs[i] = init_cost;
886 if (GET_CODE (recog_data.operand[i]) == SUBREG)
888 rtx inner = SUBREG_REG (recog_data.operand[i]);
889 if (GET_MODE_SIZE (modes[i]) != GET_MODE_SIZE (GET_MODE (inner)))
890 subreg_changes_size[i] = 1;
891 recog_data.operand[i] = inner;
894 if (GET_CODE (recog_data.operand[i]) == MEM)
895 record_address_regs (XEXP (recog_data.operand[i], 0),
896 BASE_REG_CLASS, loop_cost * 2);
897 else if (constraints[i][0] == 'p')
898 record_address_regs (recog_data.operand[i],
899 BASE_REG_CLASS, loop_cost * 2);
902 /* Check for commutative in a separate loop so everything will
903 have been initialized. We must do this even if one operand
904 is a constant--see addsi3 in m68k.md. */
906 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
907 if (constraints[i][0] == '%')
909 const char *xconstraints[MAX_RECOG_OPERANDS];
912 /* Handle commutative operands by swapping the constraints.
913 We assume the modes are the same. */
915 for (j = 0; j < recog_data.n_operands; j++)
916 xconstraints[j] = constraints[j];
918 xconstraints[i] = constraints[i+1];
919 xconstraints[i+1] = constraints[i];
920 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
921 recog_data.operand, modes, subreg_changes_size,
925 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
926 recog_data.operand, modes, subreg_changes_size,
929 /* Now add the cost for each operand to the total costs for
932 for (i = 0; i < recog_data.n_operands; i++)
933 if (GET_CODE (recog_data.operand[i]) == REG
934 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
936 int regno = REGNO (recog_data.operand[i]);
937 struct costs *p = &costs[regno], *q = &op_costs[i];
939 p->mem_cost += q->mem_cost * loop_cost;
940 for (j = 0; j < N_REG_CLASSES; j++)
941 p->cost[j] += q->cost[j] * loop_cost;
947 /* This is a pass of the compiler that scans all instructions
948 and calculates the preferred class for each pseudo-register.
949 This information can be accessed later by calling `reg_preferred_class'.
950 This pass comes just before local register allocation. */
957 #ifdef REGISTER_CONSTRAINTS
964 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
966 #ifdef FORBIDDEN_INC_DEC_CLASSES
968 in_inc_dec = (char *) alloca (nregs);
970 /* Initialize information about which register classes can be used for
971 pseudos that are auto-incremented or auto-decremented. It would
972 seem better to put this in init_reg_sets, but we need to be able
973 to allocate rtx, which we can't do that early. */
975 for (i = 0; i < N_REG_CLASSES; i++)
977 rtx r = gen_rtx_REG (VOIDmode, 0);
981 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
982 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
986 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
987 m = (enum machine_mode) ((int) m + 1))
988 if (HARD_REGNO_MODE_OK (j, m))
992 /* If a register is not directly suitable for an
993 auto-increment or decrement addressing mode and
994 requires secondary reloads, disallow its class from
995 being used in such addresses. */
998 #ifdef SECONDARY_RELOAD_CLASS
999 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1002 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1003 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1006 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1007 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1012 && ! auto_inc_dec_reg_p (r, m))
1013 forbidden_inc_dec_class[i] = 1;
1017 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1019 /* Normally we scan the insns once and determine the best class to use for
1020 each register. However, if -fexpensive_optimizations are on, we do so
1021 twice, the second time using the tentative best classes to guide the
1024 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1026 /* Zero out our accumulation of the cost of each class for each reg. */
1028 bzero ((char *) costs, nregs * sizeof (struct costs));
1030 #ifdef FORBIDDEN_INC_DEC_CLASSES
1031 bzero (in_inc_dec, nregs);
1034 loop_depth = 0, loop_cost = 1;
1036 /* Scan the instructions and record each time it would
1037 save code to put a certain register in a certain class. */
1039 for (insn = f; insn; insn = NEXT_INSN (insn))
1041 insn = scan_one_insn (insn, pass);
1044 /* Now for each register look at how desirable each class is
1045 and find which class is preferred. Store that in
1046 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
1047 class any of whose registers is better than memory. */
1051 prefclass = prefclass_buffer;
1052 altclass = altclass_buffer;
1055 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1057 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1058 enum reg_class best = ALL_REGS, alt = NO_REGS;
1059 /* This is an enum reg_class, but we call it an int
1060 to save lots of casts. */
1062 register struct costs *p = &costs[i];
1064 for (class = (int) ALL_REGS - 1; class > 0; class--)
1066 /* Ignore classes that are too small for this operand or
1067 invalid for a operand that was auto-incremented. */
1068 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1069 > reg_class_size[class]
1070 #ifdef FORBIDDEN_INC_DEC_CLASSES
1071 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1075 else if (p->cost[class] < best_cost)
1077 best_cost = p->cost[class];
1078 best = (enum reg_class) class;
1080 else if (p->cost[class] == best_cost)
1081 best = reg_class_subunion[(int)best][class];
1084 /* Record the alternate register class; i.e., a class for which
1085 every register in it is better than using memory. If adding a
1086 class would make a smaller class (i.e., no union of just those
1087 classes exists), skip that class. The major unions of classes
1088 should be provided as a register class. Don't do this if we
1089 will be doing it again later. */
1091 if (pass == 1 || ! flag_expensive_optimizations)
1092 for (class = 0; class < N_REG_CLASSES; class++)
1093 if (p->cost[class] < p->mem_cost
1094 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1095 > reg_class_size[(int) alt])
1096 #ifdef FORBIDDEN_INC_DEC_CLASSES
1097 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1100 alt = reg_class_subunion[(int) alt][class];
1102 /* If we don't add any classes, nothing to try. */
1106 /* We cast to (int) because (char) hits bugs in some compilers. */
1107 prefclass[i] = (int) best;
1108 altclass[i] = (int) alt;
1111 #endif /* REGISTER_CONSTRAINTS */
1116 #ifdef REGISTER_CONSTRAINTS
1118 /* Record the cost of using memory or registers of various classes for
1119 the operands in INSN.
1121 N_ALTS is the number of alternatives.
1123 N_OPS is the number of operands.
1125 OPS is an array of the operands.
1127 MODES are the modes of the operands, in case any are VOIDmode.
1129 CONSTRAINTS are the constraints to use for the operands. This array
1130 is modified by this procedure.
1132 This procedure works alternative by alternative. For each alternative
1133 we assume that we will be able to allocate all pseudos to their ideal
1134 register class and calculate the cost of using that alternative. Then
1135 we compute for each operand that is a pseudo-register, the cost of
1136 having the pseudo allocated to each register class and using it in that
1137 alternative. To this cost is added the cost of the alternative.
1139 The cost of each class for this insn is its lowest cost among all the
1143 record_reg_classes (n_alts, n_ops, ops, modes, subreg_changes_size,
1148 enum machine_mode *modes;
1149 char *subreg_changes_size;
1150 const char **constraints;
1157 /* Process each alternative, each time minimizing an operand's cost with
1158 the cost for each operand in that alternative. */
1160 for (alt = 0; alt < n_alts; alt++)
1162 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1165 enum reg_class classes[MAX_RECOG_OPERANDS];
1168 for (i = 0; i < n_ops; i++)
1170 const char *p = constraints[i];
1172 enum machine_mode mode = modes[i];
1173 int allows_addr = 0;
1178 /* Initially show we know nothing about the register class. */
1179 classes[i] = NO_REGS;
1181 /* If this operand has no constraints at all, we can conclude
1182 nothing about it since anything is valid. */
1186 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1187 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1192 /* If this alternative is only relevant when this operand
1193 matches a previous operand, we do different things depending
1194 on whether this operand is a pseudo-reg or not. We must process
1195 any modifiers for the operand before we can make this test. */
1197 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1200 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1203 classes[i] = classes[j];
1205 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1207 /* If this matches the other operand, we have no added
1209 if (rtx_equal_p (ops[j], op))
1212 /* If we can put the other operand into a register, add to
1213 the cost of this alternative the cost to copy this
1214 operand to the register used for the other operand. */
1216 else if (classes[j] != NO_REGS)
1217 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1219 else if (GET_CODE (ops[j]) != REG
1220 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1222 /* This op is a pseudo but the one it matches is not. */
1224 /* If we can't put the other operand into a register, this
1225 alternative can't be used. */
1227 if (classes[j] == NO_REGS)
1230 /* Otherwise, add to the cost of this alternative the cost
1231 to copy the other operand to the register used for this
1235 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1239 /* The costs of this operand are the same as that of the
1240 other operand. However, if we cannot tie them, this
1241 alternative needs to do a copy, which is one
1244 this_op_costs[i] = this_op_costs[j];
1245 if (REGNO (ops[i]) != REGNO (ops[j])
1246 && ! find_reg_note (insn, REG_DEAD, op))
1249 /* This is in place of ordinary cost computation
1250 for this operand, so skip to the end of the
1251 alternative (should be just one character). */
1252 while (*p && *p++ != ',')
1260 /* Scan all the constraint letters. See if the operand matches
1261 any of the constraints. Collect the valid register classes
1262 and see if this operand accepts memory. */
1264 while (*p && (c = *p++) != ',')
1268 /* Ignore the next letter for this pass. */
1274 case '!': case '#': case '&':
1275 case '0': case '1': case '2': case '3': case '4':
1276 case '5': case '6': case '7': case '8': case '9':
1281 win = address_operand (op, GET_MODE (op));
1282 /* We know this operand is an address, so we want it to be
1283 allocated to a register that can be the base of an
1284 address, ie BASE_REG_CLASS. */
1286 = reg_class_subunion[(int) classes[i]]
1287 [(int) BASE_REG_CLASS];
1290 case 'm': case 'o': case 'V':
1291 /* It doesn't seem worth distinguishing between offsettable
1292 and non-offsettable addresses here. */
1294 if (GET_CODE (op) == MEM)
1299 if (GET_CODE (op) == MEM
1300 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1301 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1306 if (GET_CODE (op) == MEM
1307 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1308 || GET_CODE (XEXP (op, 0)) == POST_INC))
1313 #ifndef REAL_ARITHMETIC
1314 /* Match any floating double constant, but only if
1315 we can examine the bits of it reliably. */
1316 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1317 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1318 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1321 if (GET_CODE (op) == CONST_DOUBLE)
1326 if (GET_CODE (op) == CONST_DOUBLE)
1332 if (GET_CODE (op) == CONST_DOUBLE
1333 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1338 if (GET_CODE (op) == CONST_INT
1339 || (GET_CODE (op) == CONST_DOUBLE
1340 && GET_MODE (op) == VOIDmode))
1344 #ifdef LEGITIMATE_PIC_OPERAND_P
1345 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1352 if (GET_CODE (op) == CONST_INT
1353 || (GET_CODE (op) == CONST_DOUBLE
1354 && GET_MODE (op) == VOIDmode))
1366 if (GET_CODE (op) == CONST_INT
1367 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1375 #ifdef EXTRA_CONSTRAINT
1381 if (EXTRA_CONSTRAINT (op, c))
1387 if (GET_CODE (op) == MEM
1389 #ifdef LEGITIMATE_PIC_OPERAND_P
1390 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1397 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1402 = reg_class_subunion[(int) classes[i]]
1403 [(int) REG_CLASS_FROM_LETTER (c)];
1408 #ifdef CLASS_CANNOT_CHANGE_SIZE
1409 /* If we noted a subreg earlier, and the selected class is a
1410 subclass of CLASS_CANNOT_CHANGE_SIZE, zap it. */
1411 if (subreg_changes_size[i]
1412 && (reg_class_subunion[(int) CLASS_CANNOT_CHANGE_SIZE]
1414 == CLASS_CANNOT_CHANGE_SIZE))
1415 classes[i] = NO_REGS;
1418 /* How we account for this operand now depends on whether it is a
1419 pseudo register or not. If it is, we first check if any
1420 register classes are valid. If not, we ignore this alternative,
1421 since we want to assume that all pseudos get allocated for
1422 register preferencing. If some register class is valid, compute
1423 the costs of moving the pseudo into that class. */
1425 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1427 if (classes[i] == NO_REGS)
1429 /* We must always fail if the operand is a REG, but
1430 we did not find a suitable class.
1432 Otherwise we may perform an uninitialized read
1433 from this_op_costs after the `continue' statement
1439 struct costs *pp = &this_op_costs[i];
1441 for (class = 0; class < N_REG_CLASSES; class++)
1442 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1444 /* If the alternative actually allows memory, make things
1445 a bit cheaper since we won't need an extra insn to
1448 pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1)
1451 /* If we have assigned a class to this register in our
1452 first pass, add a cost to this alternative corresponding
1453 to what we would add if this register were not in the
1454 appropriate class. */
1458 += may_move_cost[(unsigned char)prefclass[REGNO (op)]][(int) classes[i]];
1462 /* Otherwise, if this alternative wins, either because we
1463 have already determined that or if we have a hard register of
1464 the proper class, there is no cost for this alternative. */
1467 || (GET_CODE (op) == REG
1468 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1471 /* If registers are valid, the cost of this alternative includes
1472 copying the object to and/or from a register. */
1474 else if (classes[i] != NO_REGS)
1476 if (recog_data.operand_type[i] != OP_OUT)
1477 alt_cost += copy_cost (op, mode, classes[i], 1);
1479 if (recog_data.operand_type[i] != OP_IN)
1480 alt_cost += copy_cost (op, mode, classes[i], 0);
1483 /* The only other way this alternative can be used is if this is a
1484 constant that could be placed into memory. */
1486 else if (CONSTANT_P (op) && (allows_addr || allows_mem))
1487 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1495 /* Finally, update the costs with the information we've calculated
1496 about this alternative. */
1498 for (i = 0; i < n_ops; i++)
1499 if (GET_CODE (ops[i]) == REG
1500 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1502 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1503 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1505 pp->mem_cost = MIN (pp->mem_cost,
1506 (qq->mem_cost + alt_cost) * scale);
1508 for (class = 0; class < N_REG_CLASSES; class++)
1509 pp->cost[class] = MIN (pp->cost[class],
1510 (qq->cost[class] + alt_cost) * scale);
1514 /* If this insn is a single set copying operand 1 to operand 0
1515 and one is a pseudo with the other a hard reg that is in its
1516 own register class, set the cost of that register class to -1. */
1518 if ((set = single_set (insn)) != 0
1519 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1520 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1521 for (i = 0; i <= 1; i++)
1522 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1524 int regno = REGNO (ops[!i]);
1525 enum machine_mode mode = GET_MODE (ops[!i]);
1529 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1530 && (reg_class_size[(unsigned char)prefclass[regno]]
1531 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1532 op_costs[i].cost[(unsigned char)prefclass[regno]] = -1;
1533 else if (regno < FIRST_PSEUDO_REGISTER)
1534 for (class = 0; class < N_REG_CLASSES; class++)
1535 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1536 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1538 if (reg_class_size[class] == 1)
1539 op_costs[i].cost[class] = -1;
1542 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1544 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1548 if (nr == HARD_REGNO_NREGS(regno,mode))
1549 op_costs[i].cost[class] = -1;
1555 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1556 TO_P is zero) a register of class CLASS in mode MODE.
1558 X must not be a pseudo. */
1561 copy_cost (x, mode, class, to_p)
1563 enum machine_mode mode;
1564 enum reg_class class;
1567 #ifdef HAVE_SECONDARY_RELOADS
1568 enum reg_class secondary_class = NO_REGS;
1571 /* If X is a SCRATCH, there is actually nothing to move since we are
1572 assuming optimal allocation. */
1574 if (GET_CODE (x) == SCRATCH)
1577 /* Get the class we will actually use for a reload. */
1578 class = PREFERRED_RELOAD_CLASS (x, class);
1580 #ifdef HAVE_SECONDARY_RELOADS
1581 /* If we need a secondary reload (we assume here that we are using
1582 the secondary reload as an intermediate, not a scratch register), the
1583 cost is that to load the input into the intermediate register, then
1584 to copy them. We use a special value of TO_P to avoid recursion. */
1586 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1588 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1591 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1593 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1596 if (secondary_class != NO_REGS)
1597 return (move_cost[(int) secondary_class][(int) class]
1598 + copy_cost (x, mode, secondary_class, 2));
1599 #endif /* HAVE_SECONDARY_RELOADS */
1601 /* For memory, use the memory move cost, for (hard) registers, use the
1602 cost to move between the register classes, and use 2 for everything
1603 else (constants). */
1605 if (GET_CODE (x) == MEM || class == NO_REGS)
1606 return MEMORY_MOVE_COST (mode, class, to_p);
1608 else if (GET_CODE (x) == REG)
1609 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1612 /* If this is a constant, we may eventually want to call rtx_cost here. */
1616 /* Record the pseudo registers we must reload into hard registers
1617 in a subexpression of a memory address, X.
1619 CLASS is the class that the register needs to be in and is either
1620 BASE_REG_CLASS or INDEX_REG_CLASS.
1622 SCALE is twice the amount to multiply the cost by (it is twice so we
1623 can represent half-cost adjustments). */
1626 record_address_regs (x, class, scale)
1628 enum reg_class class;
1631 register enum rtx_code code = GET_CODE (x);
1644 /* When we have an address that is a sum,
1645 we must determine whether registers are "base" or "index" regs.
1646 If there is a sum of two registers, we must choose one to be
1647 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1648 to make a good choice most of the time. We only need to do this
1649 on machines that can have two registers in an address and where
1650 the base and index register classes are different.
1652 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1653 that seems bogus since it should only be set when we are sure
1654 the register is being used as a pointer. */
1657 rtx arg0 = XEXP (x, 0);
1658 rtx arg1 = XEXP (x, 1);
1659 register enum rtx_code code0 = GET_CODE (arg0);
1660 register enum rtx_code code1 = GET_CODE (arg1);
1662 /* Look inside subregs. */
1663 if (code0 == SUBREG)
1664 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1665 if (code1 == SUBREG)
1666 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1668 /* If this machine only allows one register per address, it must
1669 be in the first operand. */
1671 if (MAX_REGS_PER_ADDRESS == 1)
1672 record_address_regs (arg0, class, scale);
1674 /* If index and base registers are the same on this machine, just
1675 record registers in any non-constant operands. We assume here,
1676 as well as in the tests below, that all addresses are in
1679 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1681 record_address_regs (arg0, class, scale);
1682 if (! CONSTANT_P (arg1))
1683 record_address_regs (arg1, class, scale);
1686 /* If the second operand is a constant integer, it doesn't change
1687 what class the first operand must be. */
1689 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1690 record_address_regs (arg0, class, scale);
1692 /* If the second operand is a symbolic constant, the first operand
1693 must be an index register. */
1695 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1696 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1698 /* If both operands are registers but one is already a hard register
1699 of index or base class, give the other the class that the hard
1702 #ifdef REG_OK_FOR_BASE_P
1703 else if (code0 == REG && code1 == REG
1704 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1705 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1706 record_address_regs (arg1,
1707 REG_OK_FOR_BASE_P (arg0)
1708 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1710 else if (code0 == REG && code1 == REG
1711 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1712 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1713 record_address_regs (arg0,
1714 REG_OK_FOR_BASE_P (arg1)
1715 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1719 /* If one operand is known to be a pointer, it must be the base
1720 with the other operand the index. Likewise if the other operand
1723 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1726 record_address_regs (arg0, BASE_REG_CLASS, scale);
1727 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1729 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1732 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1733 record_address_regs (arg1, BASE_REG_CLASS, scale);
1736 /* Otherwise, count equal chances that each might be a base
1737 or index register. This case should be rare. */
1741 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1742 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1743 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1744 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1753 /* Double the importance of a pseudo register that is incremented
1754 or decremented, since it would take two extra insns
1755 if it ends up in the wrong place. If the operand is a pseudo,
1756 show it is being used in an INC_DEC context. */
1758 #ifdef FORBIDDEN_INC_DEC_CLASSES
1759 if (GET_CODE (XEXP (x, 0)) == REG
1760 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1761 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1764 record_address_regs (XEXP (x, 0), class, 2 * scale);
1769 register struct costs *pp = &costs[REGNO (x)];
1772 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1774 for (i = 0; i < N_REG_CLASSES; i++)
1775 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1781 register const char *fmt = GET_RTX_FORMAT (code);
1783 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1785 record_address_regs (XEXP (x, i), class, scale);
1790 #ifdef FORBIDDEN_INC_DEC_CLASSES
1792 /* Return 1 if REG is valid as an auto-increment memory reference
1793 to an object of MODE. */
1796 auto_inc_dec_reg_p (reg, mode)
1798 enum machine_mode mode;
1800 if (HAVE_POST_INCREMENT
1801 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1804 if (HAVE_POST_DECREMENT
1805 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1808 if (HAVE_PRE_INCREMENT
1809 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1812 if (HAVE_PRE_DECREMENT
1813 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1820 #endif /* REGISTER_CONSTRAINTS */
1822 static short *renumber = (short *)0;
1823 static size_t regno_allocated = 0;
1825 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1826 reg_scan and flow_analysis that are indexed by the register number. If
1827 NEW_P is non zero, initialize all of the registers, otherwise only
1828 initialize the new registers allocated. The same table is kept from
1829 function to function, only reallocating it when we need more room. If
1830 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1833 allocate_reg_info (num_regs, new_p, renumber_p)
1839 size_t size_renumber;
1840 size_t min = (new_p) ? 0 : reg_n_max;
1841 struct reg_info_data *reg_data;
1842 struct reg_info_data *reg_next;
1844 if (num_regs > regno_allocated)
1846 size_t old_allocated = regno_allocated;
1848 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1849 size_renumber = regno_allocated * sizeof (short);
1853 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
1854 renumber = (short *) xmalloc (size_renumber);
1855 prefclass_buffer = (char *) xmalloc (regno_allocated);
1856 altclass_buffer = (char *) xmalloc (regno_allocated);
1861 VARRAY_GROW (reg_n_info, regno_allocated);
1863 if (new_p) /* if we're zapping everything, no need to realloc */
1865 free ((char *)renumber);
1866 free ((char *)prefclass_buffer);
1867 free ((char *)altclass_buffer);
1868 renumber = (short *) xmalloc (size_renumber);
1869 prefclass_buffer = (char *) xmalloc (regno_allocated);
1870 altclass_buffer = (char *) xmalloc (regno_allocated);
1875 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1876 prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer,
1879 altclass_buffer = (char *) xrealloc ((char *)altclass_buffer,
1884 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
1885 + sizeof (struct reg_info_data) - sizeof (reg_info);
1886 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
1887 reg_data->min_index = old_allocated;
1888 reg_data->max_index = regno_allocated - 1;
1889 reg_data->next = reg_info_head;
1890 reg_info_head = reg_data;
1893 reg_n_max = num_regs;
1896 /* Loop through each of the segments allocated for the actual
1897 reg_info pages, and set up the pointers, zero the pages, etc. */
1898 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1900 size_t min_index = reg_data->min_index;
1901 size_t max_index = reg_data->max_index;
1903 reg_next = reg_data->next;
1904 if (min <= max_index)
1906 size_t max = max_index;
1907 size_t local_min = min - min_index;
1910 if (min < min_index)
1912 if (!reg_data->used_p) /* page just allocated with calloc */
1913 reg_data->used_p = 1; /* no need to zero */
1915 bzero ((char *) ®_data->data[local_min],
1916 sizeof (reg_info) * (max - min_index - local_min + 1));
1918 for (i = min_index+local_min; i <= max; i++)
1920 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
1921 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
1923 prefclass_buffer[i] = (char) NO_REGS;
1924 altclass_buffer[i] = (char) NO_REGS;
1930 /* If {pref,alt}class have already been allocated, update the pointers to
1931 the newly realloced ones. */
1934 prefclass = prefclass_buffer;
1935 altclass = altclass_buffer;
1939 reg_renumber = renumber;
1941 /* Tell the regset code about the new number of registers */
1942 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
1945 /* Free up the space allocated by allocate_reg_info. */
1951 struct reg_info_data *reg_data;
1952 struct reg_info_data *reg_next;
1954 VARRAY_FREE (reg_n_info);
1955 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1957 reg_next = reg_data->next;
1958 free ((char *)reg_data);
1961 free (prefclass_buffer);
1962 free (altclass_buffer);
1963 prefclass_buffer = (char *)0;
1964 altclass_buffer = (char *)0;
1965 reg_info_head = (struct reg_info_data *)0;
1966 renumber = (short *)0;
1968 regno_allocated = 0;
1972 /* This is the `regscan' pass of the compiler, run just before cse
1973 and again just before loop.
1975 It finds the first and last use of each pseudo-register
1976 and records them in the vectors regno_first_uid, regno_last_uid
1977 and counts the number of sets in the vector reg_n_sets.
1979 REPEAT is nonzero the second time this is called. */
1981 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1982 Always at least 3, since the combiner could put that many together
1983 and we want this to remain correct for all the remaining passes. */
1988 reg_scan (f, nregs, repeat)
1995 allocate_reg_info (nregs, TRUE, FALSE);
1998 for (insn = f; insn; insn = NEXT_INSN (insn))
1999 if (GET_CODE (insn) == INSN
2000 || GET_CODE (insn) == CALL_INSN
2001 || GET_CODE (insn) == JUMP_INSN)
2003 if (GET_CODE (PATTERN (insn)) == PARALLEL
2004 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2005 max_parallel = XVECLEN (PATTERN (insn), 0);
2006 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2008 if (REG_NOTES (insn))
2009 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2013 /* Update 'regscan' information by looking at the insns
2014 from FIRST to LAST. Some new REGs have been created,
2015 and any REG with number greater than OLD_MAX_REGNO is
2016 such a REG. We only update information for those. */
2019 reg_scan_update(first, last, old_max_regno)
2026 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2028 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2029 if (GET_CODE (insn) == INSN
2030 || GET_CODE (insn) == CALL_INSN
2031 || GET_CODE (insn) == JUMP_INSN)
2033 if (GET_CODE (PATTERN (insn)) == PARALLEL
2034 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2035 max_parallel = XVECLEN (PATTERN (insn), 0);
2036 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2038 if (REG_NOTES (insn))
2039 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2043 /* X is the expression to scan. INSN is the insn it appears in.
2044 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2045 We should only record information for REGs with numbers
2046 greater than or equal to MIN_REGNO. */
2049 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2055 register enum rtx_code code;
2059 code = GET_CODE (x);
2075 register int regno = REGNO (x);
2077 if (regno >= min_regno)
2079 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2081 REGNO_LAST_UID (regno) = INSN_UID (insn);
2082 if (REGNO_FIRST_UID (regno) == 0)
2083 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2090 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2092 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2097 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2101 /* Count a set of the destination if it is a register. */
2102 for (dest = SET_DEST (x);
2103 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2104 || GET_CODE (dest) == ZERO_EXTEND;
2105 dest = XEXP (dest, 0))
2108 if (GET_CODE (dest) == REG
2109 && REGNO (dest) >= min_regno)
2110 REG_N_SETS (REGNO (dest))++;
2112 /* If this is setting a pseudo from another pseudo or the sum of a
2113 pseudo and a constant integer and the other pseudo is known to be
2114 a pointer, set the destination to be a pointer as well.
2116 Likewise if it is setting the destination from an address or from a
2117 value equivalent to an address or to the sum of an address and
2120 But don't do any of this if the pseudo corresponds to a user
2121 variable since it should have already been set as a pointer based
2124 if (GET_CODE (SET_DEST (x)) == REG
2125 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2126 && REGNO (SET_DEST (x)) >= min_regno
2127 /* If the destination pseudo is set more than once, then other
2128 sets might not be to a pointer value (consider access to a
2129 union in two threads of control in the presense of global
2130 optimizations). So only set REGNO_POINTER_FLAG on the destination
2131 pseudo if this is the only set of that pseudo. */
2132 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2133 && ! REG_USERVAR_P (SET_DEST (x))
2134 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2135 && ((GET_CODE (SET_SRC (x)) == REG
2136 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2137 || ((GET_CODE (SET_SRC (x)) == PLUS
2138 || GET_CODE (SET_SRC (x)) == LO_SUM)
2139 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2140 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2141 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2142 || GET_CODE (SET_SRC (x)) == CONST
2143 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2144 || GET_CODE (SET_SRC (x)) == LABEL_REF
2145 || (GET_CODE (SET_SRC (x)) == HIGH
2146 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2147 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2148 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2149 || ((GET_CODE (SET_SRC (x)) == PLUS
2150 || GET_CODE (SET_SRC (x)) == LO_SUM)
2151 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2152 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2153 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2154 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2155 && (GET_CODE (XEXP (note, 0)) == CONST
2156 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2157 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2158 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2160 /* ... fall through ... */
2164 register const char *fmt = GET_RTX_FORMAT (code);
2166 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2169 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2170 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2173 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2174 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2181 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2185 reg_class_subset_p (c1, c2)
2186 register enum reg_class c1;
2187 register enum reg_class c2;
2189 if (c1 == c2) return 1;
2194 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2195 reg_class_contents[(int)c2],
2200 /* Return nonzero if there is a register that is in both C1 and C2. */
2203 reg_classes_intersect_p (c1, c2)
2204 register enum reg_class c1;
2205 register enum reg_class c2;
2212 if (c1 == c2) return 1;
2214 if (c1 == ALL_REGS || c2 == ALL_REGS)
2217 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2218 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2220 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2227 /* Release any memory allocated by register sets. */
2230 regset_release_memory ()
2232 bitmap_release_memory ();