1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
29 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "insn-config.h"
40 #ifndef REGISTER_MOVE_COST
41 #define REGISTER_MOVE_COST(x, y) 2
44 /* If we have auto-increment or auto-decrement and we can have secondary
45 reloads, we are not allowed to use classes requiring secondary
46 reloads for pseudos auto-incremented since reload can't handle it. */
49 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
50 #define FORBIDDEN_INC_DEC_CLASSES
54 /* Register tables used by many passes. */
56 /* Indexed by hard register number, contains 1 for registers
57 that are fixed use (stack pointer, pc, frame pointer, etc.).
58 These are the registers that cannot be used to allocate
59 a pseudo reg for general use. */
61 char fixed_regs[FIRST_PSEUDO_REGISTER];
63 /* Same info as a HARD_REG_SET. */
65 HARD_REG_SET fixed_reg_set;
67 /* Data for initializing the above. */
69 static char initial_fixed_regs[] = FIXED_REGISTERS;
71 /* Indexed by hard register number, contains 1 for registers
72 that are fixed use or are clobbered by function calls.
73 These are the registers that cannot be used to allocate
74 a pseudo reg whose life crosses calls unless we are able
75 to save/restore them across the calls. */
77 char call_used_regs[FIRST_PSEUDO_REGISTER];
79 /* Same info as a HARD_REG_SET. */
81 HARD_REG_SET call_used_reg_set;
83 /* HARD_REG_SET of registers we want to avoid caller saving. */
84 HARD_REG_SET losing_caller_save_reg_set;
86 /* Data for initializing the above. */
88 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
90 /* Indexed by hard register number, contains 1 for registers that are
91 fixed use or call used registers that cannot hold quantities across
92 calls even if we are willing to save and restore them. call fixed
93 registers are a subset of call used registers. */
95 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
97 /* The same info as a HARD_REG_SET. */
99 HARD_REG_SET call_fixed_reg_set;
101 /* Number of non-fixed registers. */
103 int n_non_fixed_regs;
105 /* Indexed by hard register number, contains 1 for registers
106 that are being used for global register decls.
107 These must be exempt from ordinary flow analysis
108 and are also considered fixed. */
110 char global_regs[FIRST_PSEUDO_REGISTER];
112 /* Table of register numbers in the order in which to try to use them. */
113 #ifdef REG_ALLOC_ORDER
114 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
117 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
119 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
121 /* The same information, but as an array of unsigned ints. We copy from
122 these unsigned ints to the table above. We do this so the tm.h files
123 do not have to be aware of the wordsize for machines with <= 64 regs. */
126 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
128 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
129 = REG_CLASS_CONTENTS;
131 /* For each reg class, number of regs it contains. */
133 int reg_class_size[N_REG_CLASSES];
135 /* For each reg class, table listing all the containing classes. */
137 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
139 /* For each reg class, table listing all the classes contained in it. */
141 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
143 /* For each pair of reg classes,
144 a largest reg class contained in their union. */
146 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
148 /* For each pair of reg classes,
149 the smallest reg class containing their union. */
151 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
153 /* Array containing all of the register names */
155 char *reg_names[] = REGISTER_NAMES;
157 /* For each hard register, the widest mode object that it can contain.
158 This will be a MODE_INT mode if the register can hold integers. Otherwise
159 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
162 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
164 /* Maximum cost of moving from a register in one class to a register in
165 another class. Based on REGISTER_MOVE_COST. */
167 static int move_cost[N_REG_CLASSES][N_REG_CLASSES];
169 /* Similar, but here we don't have to move if the first index is a subset
170 of the second so in that case the cost is zero. */
172 static int may_move_cost[N_REG_CLASSES][N_REG_CLASSES];
174 #ifdef FORBIDDEN_INC_DEC_CLASSES
176 /* These are the classes that regs which are auto-incremented or decremented
179 static int forbidden_inc_dec_class[N_REG_CLASSES];
181 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
184 static char *in_inc_dec;
186 #endif /* FORBIDDEN_INC_DEC_CLASSES */
188 #ifdef HAVE_SECONDARY_RELOADS
190 /* Sample MEM values for use by memory_move_secondary_cost. */
192 static rtx top_of_stack[MAX_MACHINE_MODE];
194 #endif /* HAVE_SECONDARY_RELOADS */
196 /* Linked list of reg_info structures allocated for reg_n_info array.
197 Grouping all of the allocated structures together in one lump
198 means only one call to bzero to clear them, rather than n smaller
200 struct reg_info_data {
201 struct reg_info_data *next; /* next set of reg_info structures */
202 size_t min_index; /* minimum index # */
203 size_t max_index; /* maximum index # */
204 char used_p; /* non-zero if this has been used previously */
205 reg_info data[1]; /* beginning of the reg_info data */
208 static struct reg_info_data *reg_info_head;
211 /* Function called only once to initialize the above data on reg usage.
212 Once this is done, various switches may override. */
219 /* First copy the register information from the initial int form into
222 for (i = 0; i < N_REG_CLASSES; i++)
224 CLEAR_HARD_REG_SET (reg_class_contents[i]);
226 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
227 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
228 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
229 SET_HARD_REG_BIT (reg_class_contents[i], j);
232 bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
233 bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
234 bzero (global_regs, sizeof global_regs);
236 /* Compute number of hard regs in each class. */
238 bzero ((char *) reg_class_size, sizeof reg_class_size);
239 for (i = 0; i < N_REG_CLASSES; i++)
240 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
241 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
244 /* Initialize the table of subunions.
245 reg_class_subunion[I][J] gets the largest-numbered reg-class
246 that is contained in the union of classes I and J. */
248 for (i = 0; i < N_REG_CLASSES; i++)
250 for (j = 0; j < N_REG_CLASSES; j++)
253 register /* Declare it register if it's a scalar. */
258 COPY_HARD_REG_SET (c, reg_class_contents[i]);
259 IOR_HARD_REG_SET (c, reg_class_contents[j]);
260 for (k = 0; k < N_REG_CLASSES; k++)
262 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
267 /* keep the largest subclass */ /* SPEE 900308 */
268 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
269 reg_class_contents[(int) reg_class_subunion[i][j]],
271 reg_class_subunion[i][j] = (enum reg_class) k;
278 /* Initialize the table of superunions.
279 reg_class_superunion[I][J] gets the smallest-numbered reg-class
280 containing the union of classes I and J. */
282 for (i = 0; i < N_REG_CLASSES; i++)
284 for (j = 0; j < N_REG_CLASSES; j++)
287 register /* Declare it register if it's a scalar. */
292 COPY_HARD_REG_SET (c, reg_class_contents[i]);
293 IOR_HARD_REG_SET (c, reg_class_contents[j]);
294 for (k = 0; k < N_REG_CLASSES; k++)
295 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
298 reg_class_superunion[i][j] = (enum reg_class) k;
302 /* Initialize the tables of subclasses and superclasses of each reg class.
303 First clear the whole table, then add the elements as they are found. */
305 for (i = 0; i < N_REG_CLASSES; i++)
307 for (j = 0; j < N_REG_CLASSES; j++)
309 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
310 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
314 for (i = 0; i < N_REG_CLASSES; i++)
316 if (i == (int) NO_REGS)
319 for (j = i + 1; j < N_REG_CLASSES; j++)
323 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
327 /* Reg class I is a subclass of J.
328 Add J to the table of superclasses of I. */
329 p = ®_class_superclasses[i][0];
330 while (*p != LIM_REG_CLASSES) p++;
331 *p = (enum reg_class) j;
332 /* Add I to the table of superclasses of J. */
333 p = ®_class_subclasses[j][0];
334 while (*p != LIM_REG_CLASSES) p++;
335 *p = (enum reg_class) i;
339 /* Do any additional initialization regsets may need */
340 INIT_ONCE_REG_SET ();
343 /* After switches have been processed, which perhaps alter
344 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
349 register unsigned int i, j;
351 /* This macro allows the fixed or call-used registers
352 to depend on target flags. */
354 #ifdef CONDITIONAL_REGISTER_USAGE
355 CONDITIONAL_REGISTER_USAGE;
358 /* Initialize "constant" tables. */
360 CLEAR_HARD_REG_SET (fixed_reg_set);
361 CLEAR_HARD_REG_SET (call_used_reg_set);
362 CLEAR_HARD_REG_SET (call_fixed_reg_set);
364 bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
366 n_non_fixed_regs = 0;
368 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
371 SET_HARD_REG_BIT (fixed_reg_set, i);
375 if (call_used_regs[i])
376 SET_HARD_REG_BIT (call_used_reg_set, i);
377 if (call_fixed_regs[i])
378 SET_HARD_REG_BIT (call_fixed_reg_set, i);
379 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
380 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
383 /* Initialize the move cost table. Find every subset of each class
384 and take the maximum cost of moving any subset to any other. */
386 for (i = 0; i < N_REG_CLASSES; i++)
387 for (j = 0; j < N_REG_CLASSES; j++)
389 int cost = i == j ? 2 : REGISTER_MOVE_COST (i, j);
390 enum reg_class *p1, *p2;
392 for (p2 = ®_class_subclasses[j][0]; *p2 != LIM_REG_CLASSES; p2++)
394 cost = MAX (cost, REGISTER_MOVE_COST (i, *p2));
396 for (p1 = ®_class_subclasses[i][0]; *p1 != LIM_REG_CLASSES; p1++)
399 cost = MAX (cost, REGISTER_MOVE_COST (*p1, j));
401 for (p2 = ®_class_subclasses[j][0];
402 *p2 != LIM_REG_CLASSES; p2++)
404 cost = MAX (cost, REGISTER_MOVE_COST (*p1, *p2));
407 move_cost[i][j] = cost;
409 if (reg_class_subset_p (i, j))
412 may_move_cost[i][j] = cost;
416 /* Compute the table of register modes.
417 These values are used to record death information for individual registers
418 (as opposed to a multi-register mode). */
425 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
427 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
429 /* If we couldn't find a valid mode, just use the previous mode.
430 ??? One situation in which we need to do this is on the mips where
431 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
432 to use DF mode for the even registers and VOIDmode for the odd
433 (for the cpu models where the odd ones are inaccessible). */
434 if (reg_raw_mode[i] == VOIDmode)
435 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
439 /* Finish initializing the register sets and
440 initialize the register modes. */
445 /* This finishes what was started by init_reg_sets, but couldn't be done
446 until after register usage was specified. */
451 #ifdef HAVE_SECONDARY_RELOADS
453 /* Make some fake stack-frame MEM references for use in
454 memory_move_secondary_cost. */
456 for (i = 0; i < MAX_MACHINE_MODE; i++)
457 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
462 #ifdef HAVE_SECONDARY_RELOADS
464 /* Compute extra cost of moving registers to/from memory due to reloads.
465 Only needed if secondary reloads are required for memory moves. */
468 memory_move_secondary_cost (mode, class, in)
469 enum machine_mode mode;
470 enum reg_class class;
473 enum reg_class altclass;
474 int partial_cost = 0;
475 /* We need a memory reference to feed to SECONDARY... macros. */
476 rtx mem = top_of_stack[(int) mode];
480 #ifdef SECONDARY_INPUT_RELOAD_CLASS
481 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
488 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
489 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
495 if (altclass == NO_REGS)
499 partial_cost = REGISTER_MOVE_COST (altclass, class);
501 partial_cost = REGISTER_MOVE_COST (class, altclass);
503 if (class == altclass)
504 /* This isn't simply a copy-to-temporary situation. Can't guess
505 what it is, so MEMORY_MOVE_COST really ought not to be calling
508 I'm tempted to put in an abort here, but returning this will
509 probably only give poor estimates, which is what we would've
510 had before this code anyways. */
513 /* Check if the secondary reload register will also need a
515 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
519 /* Return a machine mode that is legitimate for hard reg REGNO and large
520 enough to save nregs. If we can't find one, return VOIDmode. */
523 choose_hard_reg_mode (regno, nregs)
527 enum machine_mode found_mode = VOIDmode, mode;
529 /* We first look for the largest integer mode that can be validly
530 held in REGNO. If none, we look for the largest floating-point mode.
531 If we still didn't find a valid mode, try CCmode. */
533 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
535 mode = GET_MODE_WIDER_MODE (mode))
536 if (HARD_REGNO_NREGS (regno, mode) == nregs
537 && HARD_REGNO_MODE_OK (regno, mode))
540 if (found_mode != VOIDmode)
543 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
545 mode = GET_MODE_WIDER_MODE (mode))
546 if (HARD_REGNO_NREGS (regno, mode) == nregs
547 && HARD_REGNO_MODE_OK (regno, mode))
550 if (found_mode != VOIDmode)
553 if (HARD_REGNO_NREGS (regno, CCmode) == nregs
554 && HARD_REGNO_MODE_OK (regno, CCmode))
557 /* We can't find a mode valid for this register. */
561 /* Specify the usage characteristics of the register named NAME.
562 It should be a fixed register if FIXED and a
563 call-used register if CALL_USED. */
566 fix_register (name, fixed, call_used)
568 int fixed, call_used;
572 /* Decode the name and update the primary form of
573 the register info. */
575 if ((i = decode_reg_name (name)) >= 0)
577 if ((i == STACK_POINTER_REGNUM
578 #ifdef HARD_FRAME_POINTER_REGNUM
579 || i == HARD_FRAME_POINTER_REGNUM
581 || i == FRAME_POINTER_REGNUM
584 && (fixed == 0 || call_used == 0))
586 static char* what_option[2][2] = {
587 { "call-saved", "call-used" },
588 { "no-such-option", "fixed" }};
590 error ("can't use '%s' as a %s register", name,
591 what_option[fixed][call_used]);
595 fixed_regs[i] = fixed;
596 call_used_regs[i] = call_used;
601 warning ("unknown register name: %s", name);
605 /* Mark register number I as global. */
613 warning ("register used for two global register variables");
617 if (call_used_regs[i] && ! fixed_regs[i])
618 warning ("call-clobbered register used for global register variable");
622 /* If already fixed, nothing else to do. */
626 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
629 SET_HARD_REG_BIT (fixed_reg_set, i);
630 SET_HARD_REG_BIT (call_used_reg_set, i);
631 SET_HARD_REG_BIT (call_fixed_reg_set, i);
634 /* Now the data and code for the `regclass' pass, which happens
635 just before local-alloc. */
637 /* The `costs' struct records the cost of using a hard register of each class
638 and of using memory for each pseudo. We use this data to set up
639 register class preferences. */
643 int cost[N_REG_CLASSES];
647 /* Record the cost of each class for each pseudo. */
649 static struct costs *costs;
651 /* Initialized once, and used to initialize cost values for each insn. */
653 static struct costs init_cost;
655 /* Record the same data by operand number, accumulated for each alternative
656 in an insn. The contribution to a pseudo is that of the minimum-cost
659 static struct costs op_costs[MAX_RECOG_OPERANDS];
661 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
662 This is available after `regclass' is run. */
664 static char *prefclass;
666 /* altclass[R] is a register class that we should use for allocating
667 pseudo number R if no register in the preferred class is available.
668 If no register in this class is available, memory is preferred.
670 It might appear to be more general to have a bitmask of classes here,
671 but since it is recommended that there be a class corresponding to the
672 union of most major pair of classes, that generality is not required.
674 This is available after `regclass' is run. */
676 static char *altclass;
678 /* Allocated buffers for prefclass and altclass. */
679 static char *prefclass_buffer;
680 static char *altclass_buffer;
682 /* Record the depth of loops that we are in. */
684 static int loop_depth;
686 /* Account for the fact that insns within a loop are executed very commonly,
687 but don't keep doing this as loops go too deep. */
689 static int loop_cost;
691 static int n_occurrences PROTO((int, char *));
692 static rtx scan_one_insn PROTO((rtx, int));
693 static void record_reg_classes PROTO((int, int, rtx *, enum machine_mode *,
695 static int copy_cost PROTO((rtx, enum machine_mode,
696 enum reg_class, int));
697 static void record_address_regs PROTO((rtx, enum reg_class, int));
698 #ifdef FORBIDDEN_INC_DEC_CLASSES
699 static int auto_inc_dec_reg_p PROTO((rtx, enum machine_mode));
701 static void reg_scan_mark_refs PROTO((rtx, rtx, int, int));
703 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
704 This function is sometimes called before the info has been computed.
705 When that happens, just return GENERAL_REGS, which is innocuous. */
708 reg_preferred_class (regno)
713 return (enum reg_class) prefclass[regno];
717 reg_alternate_class (regno)
723 return (enum reg_class) altclass[regno];
726 /* Initialize some global data for this pass. */
733 init_cost.mem_cost = 10000;
734 for (i = 0; i < N_REG_CLASSES; i++)
735 init_cost.cost[i] = 10000;
737 /* This prevents dump_flow_info from losing if called
738 before regclass is run. */
742 /* Return the number of times character C occurs in string S. */
754 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
755 time it would save code to put a certain register in a certain class.
756 PASS, when nonzero, inhibits some optimizations which need only be done
758 Return the last insn processed, so that the scan can be continued from
762 scan_one_insn (insn, pass)
766 enum rtx_code code = GET_CODE (insn);
767 enum rtx_code pat_code;
768 char *constraints[MAX_RECOG_OPERANDS];
769 enum machine_mode modes[MAX_RECOG_OPERANDS];
773 /* Show that an insn inside a loop is likely to be executed three
774 times more than insns outside a loop. This is much more aggressive
775 than the assumptions made elsewhere and is being tried as an
780 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
781 loop_depth++, loop_cost = 1 << (2 * MIN (loop_depth, 5));
782 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
783 loop_depth--, loop_cost = 1 << (2 * MIN (loop_depth, 5));
788 if (GET_RTX_CLASS (code) != 'i')
791 pat_code = GET_CODE (PATTERN (insn));
793 || pat_code == CLOBBER
794 || pat_code == ASM_INPUT
795 || pat_code == ADDR_VEC
796 || pat_code == ADDR_DIFF_VEC)
799 set = single_set (insn);
802 for (i = 0; i < recog_n_operands; i++)
804 constraints[i] = recog_constraints[i];
805 modes[i] = recog_operand_mode[i];
808 /* If this insn loads a parameter from its stack slot, then
809 it represents a savings, rather than a cost, if the
810 parameter is stored in memory. Record this fact. */
812 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
813 && GET_CODE (SET_SRC (set)) == MEM
814 && (note = find_reg_note (insn, REG_EQUIV,
816 && GET_CODE (XEXP (note, 0)) == MEM)
818 costs[REGNO (SET_DEST (set))].mem_cost
819 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
822 record_address_regs (XEXP (SET_SRC (set), 0),
823 BASE_REG_CLASS, loop_cost * 2);
827 /* Improve handling of two-address insns such as
828 (set X (ashift CONST Y)) where CONST must be made to
829 match X. Change it into two insns: (set X CONST)
830 (set X (ashift X Y)). If we left this for reloading, it
831 would probably get three insns because X and Y might go
832 in the same place. This prevents X and Y from receiving
835 We can only do this if the modes of operands 0 and 1
836 (which might not be the same) are tieable and we only need
837 do this during our first pass. */
839 if (pass == 0 && optimize
840 && recog_n_operands >= 3
841 && recog_constraints[1][0] == '0'
842 && recog_constraints[1][1] == 0
843 && CONSTANT_P (recog_operand[1])
844 && ! rtx_equal_p (recog_operand[0], recog_operand[1])
845 && ! rtx_equal_p (recog_operand[0], recog_operand[2])
846 && GET_CODE (recog_operand[0]) == REG
847 && MODES_TIEABLE_P (GET_MODE (recog_operand[0]),
848 recog_operand_mode[1]))
850 rtx previnsn = prev_real_insn (insn);
852 = gen_lowpart (recog_operand_mode[1],
855 = emit_insn_before (gen_move_insn (dest,
859 /* If this insn was the start of a basic block,
860 include the new insn in that block.
861 We need not check for code_label here;
862 while a basic block can start with a code_label,
863 INSN could not be at the beginning of that block. */
864 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
867 for (b = 0; b < n_basic_blocks; b++)
868 if (insn == basic_block_head[b])
869 basic_block_head[b] = newinsn;
872 /* This makes one more setting of new insns's dest. */
873 REG_N_SETS (REGNO (recog_operand[0]))++;
875 *recog_operand_loc[1] = recog_operand[0];
876 for (i = recog_n_dups - 1; i >= 0; i--)
877 if (recog_dup_num[i] == 1)
878 *recog_dup_loc[i] = recog_operand[0];
880 return PREV_INSN (newinsn);
883 /* If we get here, we are set up to record the costs of all the
884 operands for this insn. Start by initializing the costs.
885 Then handle any address registers. Finally record the desired
886 classes for any pseudos, doing it twice if some pair of
887 operands are commutative. */
889 for (i = 0; i < recog_n_operands; i++)
891 op_costs[i] = init_cost;
893 if (GET_CODE (recog_operand[i]) == SUBREG)
894 recog_operand[i] = SUBREG_REG (recog_operand[i]);
896 if (GET_CODE (recog_operand[i]) == MEM)
897 record_address_regs (XEXP (recog_operand[i], 0),
898 BASE_REG_CLASS, loop_cost * 2);
899 else if (constraints[i][0] == 'p')
900 record_address_regs (recog_operand[i],
901 BASE_REG_CLASS, loop_cost * 2);
904 /* Check for commutative in a separate loop so everything will
905 have been initialized. We must do this even if one operand
906 is a constant--see addsi3 in m68k.md. */
908 for (i = 0; i < recog_n_operands - 1; i++)
909 if (constraints[i][0] == '%')
911 char *xconstraints[MAX_RECOG_OPERANDS];
914 /* Handle commutative operands by swapping the constraints.
915 We assume the modes are the same. */
917 for (j = 0; j < recog_n_operands; j++)
918 xconstraints[j] = constraints[j];
920 xconstraints[i] = constraints[i+1];
921 xconstraints[i+1] = constraints[i];
922 record_reg_classes (recog_n_alternatives, recog_n_operands,
923 recog_operand, modes, xconstraints,
927 record_reg_classes (recog_n_alternatives, recog_n_operands, recog_operand,
928 modes, constraints, insn);
930 /* Now add the cost for each operand to the total costs for
933 for (i = 0; i < recog_n_operands; i++)
934 if (GET_CODE (recog_operand[i]) == REG
935 && REGNO (recog_operand[i]) >= FIRST_PSEUDO_REGISTER)
937 int regno = REGNO (recog_operand[i]);
938 struct costs *p = &costs[regno], *q = &op_costs[i];
940 p->mem_cost += q->mem_cost * loop_cost;
941 for (j = 0; j < N_REG_CLASSES; j++)
942 p->cost[j] += q->cost[j] * loop_cost;
948 /* This is a pass of the compiler that scans all instructions
949 and calculates the preferred class for each pseudo-register.
950 This information can be accessed later by calling `reg_preferred_class'.
951 This pass comes just before local register allocation. */
958 #ifdef REGISTER_CONSTRAINTS
965 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
967 #ifdef FORBIDDEN_INC_DEC_CLASSES
969 in_inc_dec = (char *) alloca (nregs);
971 /* Initialize information about which register classes can be used for
972 pseudos that are auto-incremented or auto-decremented. It would
973 seem better to put this in init_reg_sets, but we need to be able
974 to allocate rtx, which we can't do that early. */
976 for (i = 0; i < N_REG_CLASSES; i++)
978 rtx r = gen_rtx_REG (VOIDmode, 0);
982 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
983 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
987 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
988 m = (enum machine_mode) ((int) m + 1))
989 if (HARD_REGNO_MODE_OK (j, m))
993 /* If a register is not directly suitable for an
994 auto-increment or decrement addressing mode and
995 requires secondary reloads, disallow its class from
996 being used in such addresses. */
999 #ifdef SECONDARY_RELOAD_CLASS
1000 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1003 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1004 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1007 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1008 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1013 && ! auto_inc_dec_reg_p (r, m))
1014 forbidden_inc_dec_class[i] = 1;
1018 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1020 /* Normally we scan the insns once and determine the best class to use for
1021 each register. However, if -fexpensive_optimizations are on, we do so
1022 twice, the second time using the tentative best classes to guide the
1025 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1027 /* Zero out our accumulation of the cost of each class for each reg. */
1029 bzero ((char *) costs, nregs * sizeof (struct costs));
1031 #ifdef FORBIDDEN_INC_DEC_CLASSES
1032 bzero (in_inc_dec, nregs);
1035 loop_depth = 0, loop_cost = 1;
1037 /* Scan the instructions and record each time it would
1038 save code to put a certain register in a certain class. */
1040 for (insn = f; insn; insn = NEXT_INSN (insn))
1042 insn = scan_one_insn (insn, pass);
1045 /* Now for each register look at how desirable each class is
1046 and find which class is preferred. Store that in
1047 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
1048 class any of whose registers is better than memory. */
1052 prefclass = prefclass_buffer;
1053 altclass = altclass_buffer;
1056 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1058 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1059 enum reg_class best = ALL_REGS, alt = NO_REGS;
1060 /* This is an enum reg_class, but we call it an int
1061 to save lots of casts. */
1063 register struct costs *p = &costs[i];
1065 for (class = (int) ALL_REGS - 1; class > 0; class--)
1067 /* Ignore classes that are too small for this operand or
1068 invalid for a operand that was auto-incremented. */
1069 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i))
1070 > reg_class_size[class]
1071 #ifdef FORBIDDEN_INC_DEC_CLASSES
1072 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1076 else if (p->cost[class] < best_cost)
1078 best_cost = p->cost[class];
1079 best = (enum reg_class) class;
1081 else if (p->cost[class] == best_cost)
1082 best = reg_class_subunion[(int)best][class];
1085 /* Record the alternate register class; i.e., a class for which
1086 every register in it is better than using memory. If adding a
1087 class would make a smaller class (i.e., no union of just those
1088 classes exists), skip that class. The major unions of classes
1089 should be provided as a register class. Don't do this if we
1090 will be doing it again later. */
1092 if (pass == 1 || ! flag_expensive_optimizations)
1093 for (class = 0; class < N_REG_CLASSES; class++)
1094 if (p->cost[class] < p->mem_cost
1095 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1096 > reg_class_size[(int) alt])
1097 #ifdef FORBIDDEN_INC_DEC_CLASSES
1098 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1101 alt = reg_class_subunion[(int) alt][class];
1103 /* If we don't add any classes, nothing to try. */
1107 /* We cast to (int) because (char) hits bugs in some compilers. */
1108 prefclass[i] = (int) best;
1109 altclass[i] = (int) alt;
1112 #endif /* REGISTER_CONSTRAINTS */
1117 #ifdef REGISTER_CONSTRAINTS
1119 /* Record the cost of using memory or registers of various classes for
1120 the operands in INSN.
1122 N_ALTS is the number of alternatives.
1124 N_OPS is the number of operands.
1126 OPS is an array of the operands.
1128 MODES are the modes of the operands, in case any are VOIDmode.
1130 CONSTRAINTS are the constraints to use for the operands. This array
1131 is modified by this procedure.
1133 This procedure works alternative by alternative. For each alternative
1134 we assume that we will be able to allocate all pseudos to their ideal
1135 register class and calculate the cost of using that alternative. Then
1136 we compute for each operand that is a pseudo-register, the cost of
1137 having the pseudo allocated to each register class and using it in that
1138 alternative. To this cost is added the cost of the alternative.
1140 The cost of each class for this insn is its lowest cost among all the
1144 record_reg_classes (n_alts, n_ops, ops, modes, constraints, insn)
1148 enum machine_mode *modes;
1156 /* Process each alternative, each time minimizing an operand's cost with
1157 the cost for each operand in that alternative. */
1159 for (alt = 0; alt < n_alts; alt++)
1161 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1164 enum reg_class classes[MAX_RECOG_OPERANDS];
1167 for (i = 0; i < n_ops; i++)
1169 char *p = constraints[i];
1171 enum machine_mode mode = modes[i];
1176 /* Initially show we know nothing about the register class. */
1177 classes[i] = NO_REGS;
1179 /* If this operand has no constraints at all, we can conclude
1180 nothing about it since anything is valid. */
1184 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1185 bzero ((char *) &this_op_costs[i], sizeof this_op_costs[i]);
1190 /* If this alternative is only relevant when this operand
1191 matches a previous operand, we do different things depending
1192 on whether this operand is a pseudo-reg or not. We must process
1193 any modifiers for the operand before we can make this test. */
1195 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1198 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1201 classes[i] = classes[j];
1203 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1205 /* If this matches the other operand, we have no added
1207 if (rtx_equal_p (ops[j], op))
1210 /* If we can put the other operand into a register, add to
1211 the cost of this alternative the cost to copy this
1212 operand to the register used for the other operand. */
1214 else if (classes[j] != NO_REGS)
1215 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1217 else if (GET_CODE (ops[j]) != REG
1218 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1220 /* This op is a pseudo but the one it matches is not. */
1222 /* If we can't put the other operand into a register, this
1223 alternative can't be used. */
1225 if (classes[j] == NO_REGS)
1228 /* Otherwise, add to the cost of this alternative the cost
1229 to copy the other operand to the register used for this
1233 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1237 /* The costs of this operand are the same as that of the
1238 other operand. However, if we cannot tie them, this
1239 alternative needs to do a copy, which is one
1242 this_op_costs[i] = this_op_costs[j];
1243 if (REGNO (ops[i]) != REGNO (ops[j])
1244 && ! find_reg_note (insn, REG_DEAD, op))
1247 /* This is in place of ordinary cost computation
1248 for this operand, so skip to the end of the
1249 alternative (should be just one character). */
1250 while (*p && *p++ != ',')
1258 /* Scan all the constraint letters. See if the operand matches
1259 any of the constraints. Collect the valid register classes
1260 and see if this operand accepts memory. */
1262 while (*p && (c = *p++) != ',')
1266 /* Ignore the next letter for this pass. */
1272 case '!': case '#': case '&':
1273 case '0': case '1': case '2': case '3': case '4':
1274 case '5': case '6': case '7': case '8': case '9':
1278 case 'm': case 'o': case 'V':
1279 /* It doesn't seem worth distinguishing between offsettable
1280 and non-offsettable addresses here. */
1282 if (GET_CODE (op) == MEM)
1287 if (GET_CODE (op) == MEM
1288 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1289 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1294 if (GET_CODE (op) == MEM
1295 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1296 || GET_CODE (XEXP (op, 0)) == POST_INC))
1301 #ifndef REAL_ARITHMETIC
1302 /* Match any floating double constant, but only if
1303 we can examine the bits of it reliably. */
1304 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1305 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1306 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1309 if (GET_CODE (op) == CONST_DOUBLE)
1314 if (GET_CODE (op) == CONST_DOUBLE)
1320 if (GET_CODE (op) == CONST_DOUBLE
1321 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1326 if (GET_CODE (op) == CONST_INT
1327 || (GET_CODE (op) == CONST_DOUBLE
1328 && GET_MODE (op) == VOIDmode))
1332 #ifdef LEGITIMATE_PIC_OPERAND_P
1333 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1340 if (GET_CODE (op) == CONST_INT
1341 || (GET_CODE (op) == CONST_DOUBLE
1342 && GET_MODE (op) == VOIDmode))
1354 if (GET_CODE (op) == CONST_INT
1355 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1363 #ifdef EXTRA_CONSTRAINT
1369 if (EXTRA_CONSTRAINT (op, c))
1375 if (GET_CODE (op) == MEM
1377 #ifdef LEGITIMATE_PIC_OPERAND_P
1378 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1385 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1390 = reg_class_subunion[(int) classes[i]]
1391 [(int) REG_CLASS_FROM_LETTER (c)];
1396 /* How we account for this operand now depends on whether it is a
1397 pseudo register or not. If it is, we first check if any
1398 register classes are valid. If not, we ignore this alternative,
1399 since we want to assume that all pseudos get allocated for
1400 register preferencing. If some register class is valid, compute
1401 the costs of moving the pseudo into that class. */
1403 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1405 if (classes[i] == NO_REGS)
1409 struct costs *pp = &this_op_costs[i];
1411 for (class = 0; class < N_REG_CLASSES; class++)
1412 pp->cost[class] = may_move_cost[class][(int) classes[i]];
1414 /* If the alternative actually allows memory, make things
1415 a bit cheaper since we won't need an extra insn to
1418 pp->mem_cost = (MEMORY_MOVE_COST (mode, classes[i], 1)
1421 /* If we have assigned a class to this register in our
1422 first pass, add a cost to this alternative corresponding
1423 to what we would add if this register were not in the
1424 appropriate class. */
1428 += may_move_cost[(unsigned char)prefclass[REGNO (op)]][(int) classes[i]];
1432 /* Otherwise, if this alternative wins, either because we
1433 have already determined that or if we have a hard register of
1434 the proper class, there is no cost for this alternative. */
1437 || (GET_CODE (op) == REG
1438 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1441 /* If registers are valid, the cost of this alternative includes
1442 copying the object to and/or from a register. */
1444 else if (classes[i] != NO_REGS)
1446 if (recog_op_type[i] != OP_OUT)
1447 alt_cost += copy_cost (op, mode, classes[i], 1);
1449 if (recog_op_type[i] != OP_IN)
1450 alt_cost += copy_cost (op, mode, classes[i], 0);
1453 /* The only other way this alternative can be used is if this is a
1454 constant that could be placed into memory. */
1456 else if (CONSTANT_P (op) && allows_mem)
1457 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1465 /* Finally, update the costs with the information we've calculated
1466 about this alternative. */
1468 for (i = 0; i < n_ops; i++)
1469 if (GET_CODE (ops[i]) == REG
1470 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1472 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1473 int scale = 1 + (recog_op_type[i] == OP_INOUT);
1475 pp->mem_cost = MIN (pp->mem_cost,
1476 (qq->mem_cost + alt_cost) * scale);
1478 for (class = 0; class < N_REG_CLASSES; class++)
1479 pp->cost[class] = MIN (pp->cost[class],
1480 (qq->cost[class] + alt_cost) * scale);
1484 /* If this insn is a single set copying operand 1 to operand 0
1485 and one is a pseudo with the other a hard reg that is in its
1486 own register class, set the cost of that register class to -1. */
1488 if ((set = single_set (insn)) != 0
1489 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1490 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG)
1491 for (i = 0; i <= 1; i++)
1492 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1494 int regno = REGNO (ops[!i]);
1495 enum machine_mode mode = GET_MODE (ops[!i]);
1499 if (regno >= FIRST_PSEUDO_REGISTER && prefclass != 0
1500 && (reg_class_size[(unsigned char)prefclass[regno]]
1501 == CLASS_MAX_NREGS (prefclass[regno], mode)))
1502 op_costs[i].cost[(unsigned char)prefclass[regno]] = -1;
1503 else if (regno < FIRST_PSEUDO_REGISTER)
1504 for (class = 0; class < N_REG_CLASSES; class++)
1505 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1506 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1508 if (reg_class_size[class] == 1)
1509 op_costs[i].cost[class] = -1;
1512 for (nr = 0; nr < HARD_REGNO_NREGS(regno, mode); nr++)
1514 if (!TEST_HARD_REG_BIT (reg_class_contents[class], regno + nr))
1518 if (nr == HARD_REGNO_NREGS(regno,mode))
1519 op_costs[i].cost[class] = -1;
1525 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1526 TO_P is zero) a register of class CLASS in mode MODE.
1528 X must not be a pseudo. */
1531 copy_cost (x, mode, class, to_p)
1533 enum machine_mode mode;
1534 enum reg_class class;
1537 #ifdef HAVE_SECONDARY_RELOADS
1538 enum reg_class secondary_class = NO_REGS;
1541 /* If X is a SCRATCH, there is actually nothing to move since we are
1542 assuming optimal allocation. */
1544 if (GET_CODE (x) == SCRATCH)
1547 /* Get the class we will actually use for a reload. */
1548 class = PREFERRED_RELOAD_CLASS (x, class);
1550 #ifdef HAVE_SECONDARY_RELOADS
1551 /* If we need a secondary reload (we assume here that we are using
1552 the secondary reload as an intermediate, not a scratch register), the
1553 cost is that to load the input into the intermediate register, then
1554 to copy them. We use a special value of TO_P to avoid recursion. */
1556 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1558 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1561 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1563 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1566 if (secondary_class != NO_REGS)
1567 return (move_cost[(int) secondary_class][(int) class]
1568 + copy_cost (x, mode, secondary_class, 2));
1569 #endif /* HAVE_SECONDARY_RELOADS */
1571 /* For memory, use the memory move cost, for (hard) registers, use the
1572 cost to move between the register classes, and use 2 for everything
1573 else (constants). */
1575 if (GET_CODE (x) == MEM || class == NO_REGS)
1576 return MEMORY_MOVE_COST (mode, class, to_p);
1578 else if (GET_CODE (x) == REG)
1579 return move_cost[(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1582 /* If this is a constant, we may eventually want to call rtx_cost here. */
1586 /* Record the pseudo registers we must reload into hard registers
1587 in a subexpression of a memory address, X.
1589 CLASS is the class that the register needs to be in and is either
1590 BASE_REG_CLASS or INDEX_REG_CLASS.
1592 SCALE is twice the amount to multiply the cost by (it is twice so we
1593 can represent half-cost adjustments). */
1596 record_address_regs (x, class, scale)
1598 enum reg_class class;
1601 register enum rtx_code code = GET_CODE (x);
1614 /* When we have an address that is a sum,
1615 we must determine whether registers are "base" or "index" regs.
1616 If there is a sum of two registers, we must choose one to be
1617 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1618 to make a good choice most of the time. We only need to do this
1619 on machines that can have two registers in an address and where
1620 the base and index register classes are different.
1622 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1623 that seems bogus since it should only be set when we are sure
1624 the register is being used as a pointer. */
1627 rtx arg0 = XEXP (x, 0);
1628 rtx arg1 = XEXP (x, 1);
1629 register enum rtx_code code0 = GET_CODE (arg0);
1630 register enum rtx_code code1 = GET_CODE (arg1);
1632 /* Look inside subregs. */
1633 if (code0 == SUBREG)
1634 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1635 if (code1 == SUBREG)
1636 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1638 /* If this machine only allows one register per address, it must
1639 be in the first operand. */
1641 if (MAX_REGS_PER_ADDRESS == 1)
1642 record_address_regs (arg0, class, scale);
1644 /* If index and base registers are the same on this machine, just
1645 record registers in any non-constant operands. We assume here,
1646 as well as in the tests below, that all addresses are in
1649 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1651 record_address_regs (arg0, class, scale);
1652 if (! CONSTANT_P (arg1))
1653 record_address_regs (arg1, class, scale);
1656 /* If the second operand is a constant integer, it doesn't change
1657 what class the first operand must be. */
1659 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1660 record_address_regs (arg0, class, scale);
1662 /* If the second operand is a symbolic constant, the first operand
1663 must be an index register. */
1665 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1666 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1668 /* If both operands are registers but one is already a hard register
1669 of index or base class, give the other the class that the hard
1672 #ifdef REG_OK_FOR_BASE_P
1673 else if (code0 == REG && code1 == REG
1674 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1675 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1676 record_address_regs (arg1,
1677 REG_OK_FOR_BASE_P (arg0)
1678 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1680 else if (code0 == REG && code1 == REG
1681 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1682 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1683 record_address_regs (arg0,
1684 REG_OK_FOR_BASE_P (arg1)
1685 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1689 /* If one operand is known to be a pointer, it must be the base
1690 with the other operand the index. Likewise if the other operand
1693 else if ((code0 == REG && REGNO_POINTER_FLAG (REGNO (arg0)))
1696 record_address_regs (arg0, BASE_REG_CLASS, scale);
1697 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1699 else if ((code1 == REG && REGNO_POINTER_FLAG (REGNO (arg1)))
1702 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1703 record_address_regs (arg1, BASE_REG_CLASS, scale);
1706 /* Otherwise, count equal chances that each might be a base
1707 or index register. This case should be rare. */
1711 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1712 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
1713 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
1714 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
1723 /* Double the importance of a pseudo register that is incremented
1724 or decremented, since it would take two extra insns
1725 if it ends up in the wrong place. If the operand is a pseudo,
1726 show it is being used in an INC_DEC context. */
1728 #ifdef FORBIDDEN_INC_DEC_CLASSES
1729 if (GET_CODE (XEXP (x, 0)) == REG
1730 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
1731 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
1734 record_address_regs (XEXP (x, 0), class, 2 * scale);
1739 register struct costs *pp = &costs[REGNO (x)];
1742 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
1744 for (i = 0; i < N_REG_CLASSES; i++)
1745 pp->cost[i] += (may_move_cost[i][(int) class] * scale) / 2;
1751 register char *fmt = GET_RTX_FORMAT (code);
1753 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1755 record_address_regs (XEXP (x, i), class, scale);
1760 #ifdef FORBIDDEN_INC_DEC_CLASSES
1762 /* Return 1 if REG is valid as an auto-increment memory reference
1763 to an object of MODE. */
1766 auto_inc_dec_reg_p (reg, mode)
1768 enum machine_mode mode;
1770 #ifdef HAVE_POST_INCREMENT
1771 if (memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
1775 #ifdef HAVE_POST_DECREMENT
1776 if (memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
1780 #ifdef HAVE_PRE_INCREMENT
1781 if (memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
1785 #ifdef HAVE_PRE_DECREMENT
1786 if (memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
1794 #endif /* REGISTER_CONSTRAINTS */
1796 static short *renumber = (short *)0;
1797 static size_t regno_allocated = 0;
1799 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1800 reg_scan and flow_analysis that are indexed by the register number. If
1801 NEW_P is non zero, initialize all of the registers, otherwise only
1802 initialize the new registers allocated. The same table is kept from
1803 function to function, only reallocating it when we need more room. If
1804 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1807 allocate_reg_info (num_regs, new_p, renumber_p)
1813 size_t size_renumber;
1814 size_t min = (new_p) ? 0 : reg_n_max;
1815 struct reg_info_data *reg_data;
1816 struct reg_info_data *reg_next;
1818 if (num_regs > regno_allocated)
1820 size_t old_allocated = regno_allocated;
1822 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
1823 size_renumber = regno_allocated * sizeof (short);
1827 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
1828 renumber = (short *) xmalloc (size_renumber);
1829 prefclass_buffer = (char *) xmalloc (regno_allocated);
1830 altclass_buffer = (char *) xmalloc (regno_allocated);
1835 VARRAY_GROW (reg_n_info, regno_allocated);
1837 if (new_p) /* if we're zapping everything, no need to realloc */
1839 free ((char *)renumber);
1840 free ((char *)prefclass_buffer);
1841 free ((char *)altclass_buffer);
1842 renumber = (short *) xmalloc (size_renumber);
1843 prefclass_buffer = (char *) xmalloc (regno_allocated);
1844 altclass_buffer = (char *) xmalloc (regno_allocated);
1849 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
1850 prefclass_buffer = (char *) xrealloc ((char *)prefclass_buffer,
1853 altclass_buffer = (char *) xrealloc ((char *)altclass_buffer,
1858 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
1859 + sizeof (struct reg_info_data) - sizeof (reg_info);
1860 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
1861 reg_data->min_index = old_allocated;
1862 reg_data->max_index = regno_allocated - 1;
1863 reg_data->next = reg_info_head;
1864 reg_info_head = reg_data;
1867 reg_n_max = num_regs;
1870 /* Loop through each of the segments allocated for the actual
1871 reg_info pages, and set up the pointers, zero the pages, etc. */
1872 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1874 size_t min_index = reg_data->min_index;
1875 size_t max_index = reg_data->max_index;
1877 reg_next = reg_data->next;
1878 if (min <= max_index)
1880 size_t max = max_index;
1881 size_t local_min = min - min_index;
1884 if (min < min_index)
1886 if (!reg_data->used_p) /* page just allocated with calloc */
1887 reg_data->used_p = 1; /* no need to zero */
1889 bzero ((char *) ®_data->data[local_min],
1890 sizeof (reg_info) * (max - min_index - local_min + 1));
1892 for (i = min_index+local_min; i <= max; i++)
1894 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index];
1895 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
1897 prefclass_buffer[i] = (char) NO_REGS;
1898 altclass_buffer[i] = (char) NO_REGS;
1904 /* If {pref,alt}class have already been allocated, update the pointers to
1905 the newly realloced ones. */
1908 prefclass = prefclass_buffer;
1909 altclass = altclass_buffer;
1913 reg_renumber = renumber;
1915 /* Tell the regset code about the new number of registers */
1916 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
1919 /* Free up the space allocated by allocate_reg_info. */
1925 struct reg_info_data *reg_data;
1926 struct reg_info_data *reg_next;
1928 VARRAY_FREE (reg_n_info);
1929 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
1931 reg_next = reg_data->next;
1932 free ((char *)reg_data);
1935 free (prefclass_buffer);
1936 free (altclass_buffer);
1937 prefclass_buffer = (char *)0;
1938 altclass_buffer = (char *)0;
1939 reg_info_head = (struct reg_info_data *)0;
1940 renumber = (short *)0;
1942 regno_allocated = 0;
1946 /* This is the `regscan' pass of the compiler, run just before cse
1947 and again just before loop.
1949 It finds the first and last use of each pseudo-register
1950 and records them in the vectors regno_first_uid, regno_last_uid
1951 and counts the number of sets in the vector reg_n_sets.
1953 REPEAT is nonzero the second time this is called. */
1955 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1956 Always at least 3, since the combiner could put that many together
1957 and we want this to remain correct for all the remaining passes. */
1962 reg_scan (f, nregs, repeat)
1969 allocate_reg_info (nregs, TRUE, FALSE);
1972 for (insn = f; insn; insn = NEXT_INSN (insn))
1973 if (GET_CODE (insn) == INSN
1974 || GET_CODE (insn) == CALL_INSN
1975 || GET_CODE (insn) == JUMP_INSN)
1977 if (GET_CODE (PATTERN (insn)) == PARALLEL
1978 && XVECLEN (PATTERN (insn), 0) > max_parallel)
1979 max_parallel = XVECLEN (PATTERN (insn), 0);
1980 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
1982 if (REG_NOTES (insn))
1983 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
1987 /* Update 'regscan' information by looking at the insns
1988 from FIRST to LAST. Some new REGs have been created,
1989 and any REG with number greater than OLD_MAX_REGNO is
1990 such a REG. We only update information for those. */
1993 reg_scan_update(first, last, old_max_regno)
2000 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2002 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2003 if (GET_CODE (insn) == INSN
2004 || GET_CODE (insn) == CALL_INSN
2005 || GET_CODE (insn) == JUMP_INSN)
2007 if (GET_CODE (PATTERN (insn)) == PARALLEL
2008 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2009 max_parallel = XVECLEN (PATTERN (insn), 0);
2010 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2012 if (REG_NOTES (insn))
2013 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2017 /* X is the expression to scan. INSN is the insn it appears in.
2018 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2019 We should only record information for REGs with numbers
2020 greater than or equal to MIN_REGNO. */
2023 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2029 register enum rtx_code code;
2033 code = GET_CODE (x);
2049 register int regno = REGNO (x);
2051 if (regno >= min_regno)
2053 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2055 REGNO_LAST_UID (regno) = INSN_UID (insn);
2056 if (REGNO_FIRST_UID (regno) == 0)
2057 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2064 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2066 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2071 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2075 /* Count a set of the destination if it is a register. */
2076 for (dest = SET_DEST (x);
2077 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2078 || GET_CODE (dest) == ZERO_EXTEND;
2079 dest = XEXP (dest, 0))
2082 if (GET_CODE (dest) == REG
2083 && REGNO (dest) >= min_regno)
2084 REG_N_SETS (REGNO (dest))++;
2086 /* If this is setting a pseudo from another pseudo or the sum of a
2087 pseudo and a constant integer and the other pseudo is known to be
2088 a pointer, set the destination to be a pointer as well.
2090 Likewise if it is setting the destination from an address or from a
2091 value equivalent to an address or to the sum of an address and
2094 But don't do any of this if the pseudo corresponds to a user
2095 variable since it should have already been set as a pointer based
2098 if (GET_CODE (SET_DEST (x)) == REG
2099 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2100 && REGNO (SET_DEST (x)) >= min_regno
2101 /* If the destination pseudo is set more than once, then other
2102 sets might not be to a pointer value (consider access to a
2103 union in two threads of control in the presense of global
2104 optimizations). So only set REGNO_POINTER_FLAG on the destination
2105 pseudo if this is the only set of that pseudo. */
2106 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2107 && ! REG_USERVAR_P (SET_DEST (x))
2108 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x)))
2109 && ((GET_CODE (SET_SRC (x)) == REG
2110 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x))))
2111 || ((GET_CODE (SET_SRC (x)) == PLUS
2112 || GET_CODE (SET_SRC (x)) == LO_SUM)
2113 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2114 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2115 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x), 0))))
2116 || GET_CODE (SET_SRC (x)) == CONST
2117 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2118 || GET_CODE (SET_SRC (x)) == LABEL_REF
2119 || (GET_CODE (SET_SRC (x)) == HIGH
2120 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2121 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2122 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2123 || ((GET_CODE (SET_SRC (x)) == PLUS
2124 || GET_CODE (SET_SRC (x)) == LO_SUM)
2125 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2126 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2127 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2128 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2129 && (GET_CODE (XEXP (note, 0)) == CONST
2130 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2131 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2132 REGNO_POINTER_FLAG (REGNO (SET_DEST (x))) = 1;
2134 /* ... fall through ... */
2138 register char *fmt = GET_RTX_FORMAT (code);
2140 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2143 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2144 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2147 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2148 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2155 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2159 reg_class_subset_p (c1, c2)
2160 register enum reg_class c1;
2161 register enum reg_class c2;
2163 if (c1 == c2) return 1;
2168 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2169 reg_class_contents[(int)c2],
2174 /* Return nonzero if there is a register that is in both C1 and C2. */
2177 reg_classes_intersect_p (c1, c2)
2178 register enum reg_class c1;
2179 register enum reg_class c2;
2186 if (c1 == c2) return 1;
2188 if (c1 == ALL_REGS || c2 == ALL_REGS)
2191 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2192 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2194 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2201 /* Release any memory allocated by register sets. */
2204 regset_release_memory ()
2206 if (basic_block_live_at_start)
2208 free_regset_vector (basic_block_live_at_start, n_basic_blocks);
2209 basic_block_live_at_start = 0;
2212 FREE_REG_SET (regs_live_at_setjmp);
2213 bitmap_release_memory ();