1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 91-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
27 #include "insn-attr.h"
28 #include "insn-flags.h"
29 #include "insn-codes.h"
32 #include "hard-reg-set.h"
37 #include "basic-block.h"
41 #ifndef STACK_PUSH_CODE
42 #ifdef STACK_GROWS_DOWNWARD
43 #define STACK_PUSH_CODE PRE_DEC
45 #define STACK_PUSH_CODE PRE_INC
49 #ifndef STACK_POP_CODE
50 #ifdef STACK_GROWS_DOWNWARD
51 #define STACK_POP_CODE POST_INC
53 #define STACK_POP_CODE POST_DEC
57 static void validate_replace_rtx_1 PROTO((rtx *, rtx, rtx, rtx));
58 static rtx *find_single_use_1 PROTO((rtx, rtx *));
59 static rtx *find_constant_term_loc PROTO((rtx *));
60 static int insn_invalid_p PROTO((rtx));
62 /* Nonzero means allow operands to be volatile.
63 This should be 0 if you are generating rtl, such as if you are calling
64 the functions in optabs.c and expmed.c (most of the time).
65 This should be 1 if all valid insns need to be recognized,
66 such as in regclass.c and final.c and reload.c.
68 init_recog and init_recog_no_volatile are responsible for setting this. */
72 struct recog_data recog_data;
74 /* Contains a vector of operand_alternative structures for every operand.
75 Set up by preprocess_constraints. */
76 struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
78 /* On return from `constrain_operands', indicate which alternative
81 int which_alternative;
83 /* Nonzero after end of reload pass.
84 Set to 1 or 0 by toplev.c.
85 Controls the significance of (SUBREG (MEM)). */
89 /* Initialize data used by the function `recog'.
90 This must be called once in the compilation of a function
91 before any insn recognition may be done in the function. */
94 init_recog_no_volatile ()
105 /* Try recognizing the instruction INSN,
106 and return the code number that results.
107 Remember the code so that repeated calls do not
108 need to spend the time for actual rerecognition.
110 This function is the normal interface to instruction recognition.
111 The automatically-generated function `recog' is normally called
112 through this one. (The only exception is in combine.c.) */
115 recog_memoized (insn)
118 if (INSN_CODE (insn) < 0)
119 INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR);
120 return INSN_CODE (insn);
123 /* Check that X is an insn-body for an `asm' with operands
124 and that the operands mentioned in it are legitimate. */
127 check_asm_operands (x)
132 const char **constraints;
135 /* Post-reload, be more strict with things. */
136 if (reload_completed)
138 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
139 extract_insn (make_insn_raw (x));
140 constrain_operands (1);
141 return which_alternative >= 0;
144 noperands = asm_noperands (x);
150 operands = (rtx *) alloca (noperands * sizeof (rtx));
151 constraints = (const char **) alloca (noperands * sizeof (char *));
153 decode_asm_operands (x, operands, NULL_PTR, constraints, NULL_PTR);
155 for (i = 0; i < noperands; i++)
157 const char *c = constraints[i];
160 if (ISDIGIT ((unsigned char)c[0]) && c[1] == '\0')
161 c = constraints[c[0] - '0'];
163 if (! asm_operand_ok (operands[i], c))
170 /* Static data for the next two routines. */
172 typedef struct change_t
180 static change_t *changes;
181 static int changes_allocated;
183 static int num_changes = 0;
185 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
186 at which NEW will be placed. If OBJECT is zero, no validation is done,
187 the change is simply made.
189 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
190 will be called with the address and mode as parameters. If OBJECT is
191 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
194 IN_GROUP is non-zero if this is part of a group of changes that must be
195 performed as a group. In that case, the changes will be stored. The
196 function `apply_change_group' will validate and apply the changes.
198 If IN_GROUP is zero, this is a single change. Try to recognize the insn
199 or validate the memory reference with the change applied. If the result
200 is not valid for the machine, suppress the change and return zero.
201 Otherwise, perform the change and return 1. */
204 validate_change (object, loc, new, in_group)
212 if (old == new || rtx_equal_p (old, new))
215 if (in_group == 0 && num_changes != 0)
220 /* Save the information describing this change. */
221 if (num_changes >= changes_allocated)
223 if (changes_allocated == 0)
224 /* This value allows for repeated substitutions inside complex
225 indexed addresses, or changes in up to 5 insns. */
226 changes_allocated = MAX_RECOG_OPERANDS * 5;
228 changes_allocated *= 2;
231 (change_t*) xrealloc (changes,
232 sizeof (change_t) * changes_allocated);
235 changes[num_changes].object = object;
236 changes[num_changes].loc = loc;
237 changes[num_changes].old = old;
239 if (object && GET_CODE (object) != MEM)
241 /* Set INSN_CODE to force rerecognition of insn. Save old code in
243 changes[num_changes].old_code = INSN_CODE (object);
244 INSN_CODE (object) = -1;
249 /* If we are making a group of changes, return 1. Otherwise, validate the
250 change group we made. */
255 return apply_change_group ();
258 /* This subroutine of apply_change_group verifies whether the changes to INSN
259 were valid; i.e. whether INSN can still be recognized. */
262 insn_invalid_p (insn)
265 int icode = recog_memoized (insn);
266 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
268 if (is_asm && ! check_asm_operands (PATTERN (insn)))
270 if (! is_asm && icode < 0)
273 /* After reload, verify that all constraints are satisfied. */
274 if (reload_completed)
278 if (! constrain_operands (1))
285 /* Apply a group of changes previously issued with `validate_change'.
286 Return 1 if all changes are valid, zero otherwise. */
289 apply_change_group ()
293 /* The changes have been applied and all INSN_CODEs have been reset to force
296 The changes are valid if we aren't given an object, or if we are
297 given a MEM and it still is a valid address, or if this is in insn
298 and it is recognized. In the latter case, if reload has completed,
299 we also require that the operands meet the constraints for
302 for (i = 0; i < num_changes; i++)
304 rtx object = changes[i].object;
309 if (GET_CODE (object) == MEM)
311 if (! memory_address_p (GET_MODE (object), XEXP (object, 0)))
314 else if (insn_invalid_p (object))
316 rtx pat = PATTERN (object);
318 /* Perhaps we couldn't recognize the insn because there were
319 extra CLOBBERs at the end. If so, try to re-recognize
320 without the last CLOBBER (later iterations will cause each of
321 them to be eliminated, in turn). But don't do this if we
322 have an ASM_OPERAND. */
323 if (GET_CODE (pat) == PARALLEL
324 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
325 && asm_noperands (PATTERN (object)) < 0)
329 if (XVECLEN (pat, 0) == 2)
330 newpat = XVECEXP (pat, 0, 0);
336 = gen_rtx_PARALLEL (VOIDmode,
337 gen_rtvec (XVECLEN (pat, 0) - 1));
338 for (j = 0; j < XVECLEN (newpat, 0); j++)
339 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
342 /* Add a new change to this group to replace the pattern
343 with this new pattern. Then consider this change
344 as having succeeded. The change we added will
345 cause the entire call to fail if things remain invalid.
347 Note that this can lose if a later change than the one
348 we are processing specified &XVECEXP (PATTERN (object), 0, X)
349 but this shouldn't occur. */
351 validate_change (object, &PATTERN (object), newpat, 1);
353 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
354 /* If this insn is a CLOBBER or USE, it is always valid, but is
362 if (i == num_changes)
374 /* Return the number of changes so far in the current group. */
377 num_validated_changes ()
382 /* Retract the changes numbered NUM and up. */
390 /* Back out all the changes. Do this in the opposite order in which
392 for (i = num_changes - 1; i >= num; i--)
394 *changes[i].loc = changes[i].old;
395 if (changes[i].object && GET_CODE (changes[i].object) != MEM)
396 INSN_CODE (changes[i].object) = changes[i].old_code;
401 /* Replace every occurrence of FROM in X with TO. Mark each change with
402 validate_change passing OBJECT. */
405 validate_replace_rtx_1 (loc, from, to, object)
407 rtx from, to, object;
410 register const char *fmt;
411 register rtx x = *loc;
412 enum rtx_code code = GET_CODE (x);
414 /* X matches FROM if it is the same rtx or they are both referring to the
415 same register in the same mode. Avoid calling rtx_equal_p unless the
416 operands look similar. */
419 || (GET_CODE (x) == REG && GET_CODE (from) == REG
420 && GET_MODE (x) == GET_MODE (from)
421 && REGNO (x) == REGNO (from))
422 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
423 && rtx_equal_p (x, from)))
425 validate_change (object, loc, to, 1);
429 /* For commutative or comparison operations, try replacing each argument
430 separately and seeing if we made any changes. If so, put a constant
432 if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
434 int prev_changes = num_changes;
436 validate_replace_rtx_1 (&XEXP (x, 0), from, to, object);
437 validate_replace_rtx_1 (&XEXP (x, 1), from, to, object);
438 if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0)))
440 validate_change (object, loc,
441 gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code
442 : swap_condition (code),
443 GET_MODE (x), XEXP (x, 1),
451 /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already
452 done the substitution, otherwise we won't. */
457 /* If we have a PLUS whose second operand is now a CONST_INT, use
458 plus_constant to try to simplify it. */
459 if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to)
460 validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)),
465 if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from)
467 validate_change (object, loc,
468 plus_constant (XEXP (x, 0), - INTVAL (to)),
476 /* In these cases, the operation to be performed depends on the mode
477 of the operand. If we are replacing the operand with a VOIDmode
478 constant, we lose the information. So try to simplify the operation
479 in that case. If it fails, substitute in something that we know
480 won't be recognized. */
481 if (GET_MODE (to) == VOIDmode
482 && (XEXP (x, 0) == from
483 || (GET_CODE (XEXP (x, 0)) == REG && GET_CODE (from) == REG
484 && GET_MODE (XEXP (x, 0)) == GET_MODE (from)
485 && REGNO (XEXP (x, 0)) == REGNO (from))))
487 rtx new = simplify_unary_operation (code, GET_MODE (x), to,
490 new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
492 validate_change (object, loc, new, 1);
498 /* If we have a SUBREG of a register that we are replacing and we are
499 replacing it with a MEM, make a new MEM and try replacing the
500 SUBREG with it. Don't do this if the MEM has a mode-dependent address
501 or if we would be widening it. */
503 if (SUBREG_REG (x) == from
504 && GET_CODE (from) == REG
505 && GET_CODE (to) == MEM
506 && ! mode_dependent_address_p (XEXP (to, 0))
507 && ! MEM_VOLATILE_P (to)
508 && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to)))
510 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
511 enum machine_mode mode = GET_MODE (x);
514 if (BYTES_BIG_ENDIAN)
515 offset += (MIN (UNITS_PER_WORD,
516 GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
517 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
519 new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset));
520 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to);
521 MEM_COPY_ATTRIBUTES (new, to);
522 validate_change (object, loc, new, 1);
529 /* If we are replacing a register with memory, try to change the memory
530 to be the mode required for memory in extract operations (this isn't
531 likely to be an insertion operation; if it was, nothing bad will
532 happen, we might just fail in some cases). */
534 if (XEXP (x, 0) == from && GET_CODE (from) == REG && GET_CODE (to) == MEM
535 && GET_CODE (XEXP (x, 1)) == CONST_INT
536 && GET_CODE (XEXP (x, 2)) == CONST_INT
537 && ! mode_dependent_address_p (XEXP (to, 0))
538 && ! MEM_VOLATILE_P (to))
540 enum machine_mode wanted_mode = VOIDmode;
541 enum machine_mode is_mode = GET_MODE (to);
542 int pos = INTVAL (XEXP (x, 2));
545 if (code == ZERO_EXTRACT)
547 wanted_mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
548 if (wanted_mode == VOIDmode)
549 wanted_mode = word_mode;
553 if (code == SIGN_EXTRACT)
555 wanted_mode = insn_data[(int) CODE_FOR_extv].operand[1].mode;
556 if (wanted_mode == VOIDmode)
557 wanted_mode = word_mode;
561 /* If we have a narrower mode, we can do something. */
562 if (wanted_mode != VOIDmode
563 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
565 int offset = pos / BITS_PER_UNIT;
568 /* If the bytes and bits are counted differently, we
569 must adjust the offset. */
570 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
571 offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode)
574 pos %= GET_MODE_BITSIZE (wanted_mode);
576 newmem = gen_rtx_MEM (wanted_mode,
577 plus_constant (XEXP (to, 0), offset));
578 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (to);
579 MEM_COPY_ATTRIBUTES (newmem, to);
581 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
582 validate_change (object, &XEXP (x, 0), newmem, 1);
592 /* For commutative or comparison operations we've already performed
593 replacements. Don't try to perform them again. */
594 if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c')
596 fmt = GET_RTX_FORMAT (code);
597 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
600 validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
601 else if (fmt[i] == 'E')
602 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
603 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object);
608 /* Try replacing every occurrence of FROM in INSN with TO. After all
609 changes have been made, validate by seeing if INSN is still valid. */
612 validate_replace_rtx (from, to, insn)
615 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
616 return apply_change_group ();
619 /* Try replacing every occurrence of FROM in INSN with TO. After all
620 changes have been made, validate by seeing if INSN is still valid. */
623 validate_replace_rtx_group (from, to, insn)
626 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
629 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
630 SET_DESTs. After all changes have been made, validate by seeing if
631 INSN is still valid. */
634 validate_replace_src (from, to, insn)
637 if ((GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
638 || GET_CODE (PATTERN (insn)) != SET)
641 validate_replace_rtx_1 (&SET_SRC (PATTERN (insn)), from, to, insn);
642 if (GET_CODE (SET_DEST (PATTERN (insn))) == MEM)
643 validate_replace_rtx_1 (&XEXP (SET_DEST (PATTERN (insn)), 0),
645 return apply_change_group ();
649 /* Return 1 if the insn using CC0 set by INSN does not contain
650 any ordered tests applied to the condition codes.
651 EQ and NE tests do not count. */
654 next_insn_tests_no_inequality (insn)
657 register rtx next = next_cc0_user (insn);
659 /* If there is no next insn, we have to take the conservative choice. */
663 return ((GET_CODE (next) == JUMP_INSN
664 || GET_CODE (next) == INSN
665 || GET_CODE (next) == CALL_INSN)
666 && ! inequality_comparisons_p (PATTERN (next)));
669 #if 0 /* This is useless since the insn that sets the cc's
670 must be followed immediately by the use of them. */
671 /* Return 1 if the CC value set up by INSN is not used. */
674 next_insns_test_no_inequality (insn)
677 register rtx next = NEXT_INSN (insn);
679 for (; next != 0; next = NEXT_INSN (next))
681 if (GET_CODE (next) == CODE_LABEL
682 || GET_CODE (next) == BARRIER)
684 if (GET_CODE (next) == NOTE)
686 if (inequality_comparisons_p (PATTERN (next)))
688 if (sets_cc0_p (PATTERN (next)) == 1)
690 if (! reg_mentioned_p (cc0_rtx, PATTERN (next)))
698 /* This is used by find_single_use to locate an rtx that contains exactly one
699 use of DEST, which is typically either a REG or CC0. It returns a
700 pointer to the innermost rtx expression containing DEST. Appearances of
701 DEST that are being used to totally replace it are not counted. */
704 find_single_use_1 (dest, loc)
709 enum rtx_code code = GET_CODE (x);
726 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
727 of a REG that occupies all of the REG, the insn uses DEST if
728 it is mentioned in the destination or the source. Otherwise, we
729 need just check the source. */
730 if (GET_CODE (SET_DEST (x)) != CC0
731 && GET_CODE (SET_DEST (x)) != PC
732 && GET_CODE (SET_DEST (x)) != REG
733 && ! (GET_CODE (SET_DEST (x)) == SUBREG
734 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
735 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
736 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
737 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
738 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
741 return find_single_use_1 (dest, &SET_SRC (x));
745 return find_single_use_1 (dest, &XEXP (x, 0));
751 /* If it wasn't one of the common cases above, check each expression and
752 vector of this code. Look for a unique usage of DEST. */
754 fmt = GET_RTX_FORMAT (code);
755 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
759 if (dest == XEXP (x, i)
760 || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG
761 && REGNO (dest) == REGNO (XEXP (x, i))))
764 this_result = find_single_use_1 (dest, &XEXP (x, i));
767 result = this_result;
768 else if (this_result)
769 /* Duplicate usage. */
772 else if (fmt[i] == 'E')
776 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
778 if (XVECEXP (x, i, j) == dest
779 || (GET_CODE (dest) == REG
780 && GET_CODE (XVECEXP (x, i, j)) == REG
781 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
784 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
787 result = this_result;
788 else if (this_result)
797 /* See if DEST, produced in INSN, is used only a single time in the
798 sequel. If so, return a pointer to the innermost rtx expression in which
801 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
803 This routine will return usually zero either before flow is called (because
804 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
805 note can't be trusted).
807 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
808 care about REG_DEAD notes or LOG_LINKS.
810 Otherwise, we find the single use by finding an insn that has a
811 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
812 only referenced once in that insn, we know that it must be the first
813 and last insn referencing DEST. */
816 find_single_use (dest, insn, ploc)
828 next = NEXT_INSN (insn);
830 || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN))
833 result = find_single_use_1 (dest, &PATTERN (next));
840 if (reload_completed || reload_in_progress || GET_CODE (dest) != REG)
843 for (next = next_nonnote_insn (insn);
844 next != 0 && GET_CODE (next) != CODE_LABEL;
845 next = next_nonnote_insn (next))
846 if (GET_RTX_CLASS (GET_CODE (next)) == 'i' && dead_or_set_p (next, dest))
848 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
849 if (XEXP (link, 0) == insn)
854 result = find_single_use_1 (dest, &PATTERN (next));
864 /* Return 1 if OP is a valid general operand for machine mode MODE.
865 This is either a register reference, a memory reference,
866 or a constant. In the case of a memory reference, the address
867 is checked for general validity for the target machine.
869 Register and memory references must have mode MODE in order to be valid,
870 but some constants have no machine mode and are valid for any mode.
872 If MODE is VOIDmode, OP is checked for validity for whatever mode
875 The main use of this function is as a predicate in match_operand
876 expressions in the machine description.
878 For an explanation of this function's behavior for registers of
879 class NO_REGS, see the comment for `register_operand'. */
882 general_operand (op, mode)
884 enum machine_mode mode;
886 register enum rtx_code code = GET_CODE (op);
887 int mode_altering_drug = 0;
889 if (mode == VOIDmode)
890 mode = GET_MODE (op);
892 /* Don't accept CONST_INT or anything similar
893 if the caller wants something floating. */
894 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
895 && GET_MODE_CLASS (mode) != MODE_INT
896 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
900 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode)
901 #ifdef LEGITIMATE_PIC_OPERAND_P
902 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
904 && LEGITIMATE_CONSTANT_P (op));
906 /* Except for certain constants with VOIDmode, already checked for,
907 OP's mode must match MODE if MODE specifies a mode. */
909 if (GET_MODE (op) != mode)
914 #ifdef INSN_SCHEDULING
915 /* On machines that have insn scheduling, we want all memory
916 reference to be explicit, so outlaw paradoxical SUBREGs. */
917 if (GET_CODE (SUBREG_REG (op)) == MEM
918 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
922 op = SUBREG_REG (op);
923 code = GET_CODE (op);
925 /* No longer needed, since (SUBREG (MEM...))
926 will load the MEM into a reload reg in the MEM's own mode. */
927 mode_altering_drug = 1;
932 /* A register whose class is NO_REGS is not a general operand. */
933 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
934 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS);
938 register rtx y = XEXP (op, 0);
939 if (! volatile_ok && MEM_VOLATILE_P (op))
941 if (GET_CODE (y) == ADDRESSOF)
943 /* Use the mem's mode, since it will be reloaded thus. */
944 mode = GET_MODE (op);
945 GO_IF_LEGITIMATE_ADDRESS (mode, y, win);
948 /* Pretend this is an operand for now; we'll run force_operand
949 on its replacement in fixup_var_refs_1. */
950 if (code == ADDRESSOF)
956 if (mode_altering_drug)
957 return ! mode_dependent_address_p (XEXP (op, 0));
961 /* Return 1 if OP is a valid memory address for a memory reference
964 The main use of this function is as a predicate in match_operand
965 expressions in the machine description. */
968 address_operand (op, mode)
970 enum machine_mode mode;
972 return memory_address_p (mode, op);
975 /* Return 1 if OP is a register reference of mode MODE.
976 If MODE is VOIDmode, accept a register in any mode.
978 The main use of this function is as a predicate in match_operand
979 expressions in the machine description.
981 As a special exception, registers whose class is NO_REGS are
982 not accepted by `register_operand'. The reason for this change
983 is to allow the representation of special architecture artifacts
984 (such as a condition code register) without extending the rtl
985 definitions. Since registers of class NO_REGS cannot be used
986 as registers in any case where register classes are examined,
987 it is most consistent to keep this function from accepting them. */
990 register_operand (op, mode)
992 enum machine_mode mode;
994 if (GET_MODE (op) != mode && mode != VOIDmode)
997 if (GET_CODE (op) == SUBREG)
999 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1000 because it is guaranteed to be reloaded into one.
1001 Just make sure the MEM is valid in itself.
1002 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1003 but currently it does result from (SUBREG (REG)...) where the
1004 reg went on the stack.) */
1005 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1006 return general_operand (op, mode);
1008 #ifdef CLASS_CANNOT_CHANGE_SIZE
1009 if (GET_CODE (SUBREG_REG (op)) == REG
1010 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER
1011 && TEST_HARD_REG_BIT (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
1012 REGNO (SUBREG_REG (op)))
1013 && (GET_MODE_SIZE (mode)
1014 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
1015 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT
1016 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT)
1020 op = SUBREG_REG (op);
1023 /* We don't consider registers whose class is NO_REGS
1024 to be a register operand. */
1025 return (GET_CODE (op) == REG
1026 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1027 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1030 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1031 or a hard register. */
1034 scratch_operand (op, mode)
1036 enum machine_mode mode;
1038 return (GET_MODE (op) == mode
1039 && (GET_CODE (op) == SCRATCH
1040 || (GET_CODE (op) == REG
1041 && REGNO (op) < FIRST_PSEUDO_REGISTER)));
1044 /* Return 1 if OP is a valid immediate operand for mode MODE.
1046 The main use of this function is as a predicate in match_operand
1047 expressions in the machine description. */
1050 immediate_operand (op, mode)
1052 enum machine_mode mode;
1054 /* Don't accept CONST_INT or anything similar
1055 if the caller wants something floating. */
1056 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1057 && GET_MODE_CLASS (mode) != MODE_INT
1058 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1061 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
1062 result in 0/1. It seems a safe assumption that this is
1063 in range for everyone. */
1064 if (GET_CODE (op) == CONSTANT_P_RTX)
1067 return (CONSTANT_P (op)
1068 && (GET_MODE (op) == mode || mode == VOIDmode
1069 || GET_MODE (op) == VOIDmode)
1070 #ifdef LEGITIMATE_PIC_OPERAND_P
1071 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1073 && LEGITIMATE_CONSTANT_P (op));
1076 /* Returns 1 if OP is an operand that is a CONST_INT. */
1079 const_int_operand (op, mode)
1081 enum machine_mode mode ATTRIBUTE_UNUSED;
1083 return GET_CODE (op) == CONST_INT;
1086 /* Returns 1 if OP is an operand that is a constant integer or constant
1087 floating-point number. */
1090 const_double_operand (op, mode)
1092 enum machine_mode mode;
1094 /* Don't accept CONST_INT or anything similar
1095 if the caller wants something floating. */
1096 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1097 && GET_MODE_CLASS (mode) != MODE_INT
1098 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1101 return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT)
1102 && (mode == VOIDmode || GET_MODE (op) == mode
1103 || GET_MODE (op) == VOIDmode));
1106 /* Return 1 if OP is a general operand that is not an immediate operand. */
1109 nonimmediate_operand (op, mode)
1111 enum machine_mode mode;
1113 return (general_operand (op, mode) && ! CONSTANT_P (op));
1116 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1119 nonmemory_operand (op, mode)
1121 enum machine_mode mode;
1123 if (CONSTANT_P (op))
1125 /* Don't accept CONST_INT or anything similar
1126 if the caller wants something floating. */
1127 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1128 && GET_MODE_CLASS (mode) != MODE_INT
1129 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1132 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode)
1133 #ifdef LEGITIMATE_PIC_OPERAND_P
1134 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1136 && LEGITIMATE_CONSTANT_P (op));
1139 if (GET_MODE (op) != mode && mode != VOIDmode)
1142 if (GET_CODE (op) == SUBREG)
1144 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1145 because it is guaranteed to be reloaded into one.
1146 Just make sure the MEM is valid in itself.
1147 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1148 but currently it does result from (SUBREG (REG)...) where the
1149 reg went on the stack.) */
1150 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1151 return general_operand (op, mode);
1152 op = SUBREG_REG (op);
1155 /* We don't consider registers whose class is NO_REGS
1156 to be a register operand. */
1157 return (GET_CODE (op) == REG
1158 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1159 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1162 /* Return 1 if OP is a valid operand that stands for pushing a
1163 value of mode MODE onto the stack.
1165 The main use of this function is as a predicate in match_operand
1166 expressions in the machine description. */
1169 push_operand (op, mode)
1171 enum machine_mode mode;
1173 if (GET_CODE (op) != MEM)
1176 if (mode != VOIDmode && GET_MODE (op) != mode)
1181 if (GET_CODE (op) != STACK_PUSH_CODE)
1184 return XEXP (op, 0) == stack_pointer_rtx;
1187 /* Return 1 if OP is a valid operand that stands for popping a
1188 value of mode MODE off the stack.
1190 The main use of this function is as a predicate in match_operand
1191 expressions in the machine description. */
1194 pop_operand (op, mode)
1196 enum machine_mode mode;
1198 if (GET_CODE (op) != MEM)
1201 if (mode != VOIDmode && GET_MODE (op) != mode)
1206 if (GET_CODE (op) != STACK_POP_CODE)
1209 return XEXP (op, 0) == stack_pointer_rtx;
1212 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1215 memory_address_p (mode, addr)
1216 enum machine_mode mode;
1219 if (GET_CODE (addr) == ADDRESSOF)
1222 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1229 /* Return 1 if OP is a valid memory reference with mode MODE,
1230 including a valid address.
1232 The main use of this function is as a predicate in match_operand
1233 expressions in the machine description. */
1236 memory_operand (op, mode)
1238 enum machine_mode mode;
1242 if (! reload_completed)
1243 /* Note that no SUBREG is a memory operand before end of reload pass,
1244 because (SUBREG (MEM...)) forces reloading into a register. */
1245 return GET_CODE (op) == MEM && general_operand (op, mode);
1247 if (mode != VOIDmode && GET_MODE (op) != mode)
1251 if (GET_CODE (inner) == SUBREG)
1252 inner = SUBREG_REG (inner);
1254 return (GET_CODE (inner) == MEM && general_operand (op, mode));
1257 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1258 that is, a memory reference whose address is a general_operand. */
1261 indirect_operand (op, mode)
1263 enum machine_mode mode;
1265 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1266 if (! reload_completed
1267 && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM)
1269 register int offset = SUBREG_WORD (op) * UNITS_PER_WORD;
1270 rtx inner = SUBREG_REG (op);
1272 if (BYTES_BIG_ENDIAN)
1273 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op)))
1274 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner))));
1276 if (mode != VOIDmode && GET_MODE (op) != mode)
1279 /* The only way that we can have a general_operand as the resulting
1280 address is if OFFSET is zero and the address already is an operand
1281 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1284 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1285 || (GET_CODE (XEXP (inner, 0)) == PLUS
1286 && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT
1287 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1288 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1291 return (GET_CODE (op) == MEM
1292 && memory_operand (op, mode)
1293 && general_operand (XEXP (op, 0), Pmode));
1296 /* Return 1 if this is a comparison operator. This allows the use of
1297 MATCH_OPERATOR to recognize all the branch insns. */
1300 comparison_operator (op, mode)
1302 enum machine_mode mode;
1304 return ((mode == VOIDmode || GET_MODE (op) == mode)
1305 && GET_RTX_CLASS (GET_CODE (op)) == '<');
1308 /* If BODY is an insn body that uses ASM_OPERANDS,
1309 return the number of operands (both input and output) in the insn.
1310 Otherwise return -1. */
1313 asm_noperands (body)
1316 if (GET_CODE (body) == ASM_OPERANDS)
1317 /* No output operands: return number of input operands. */
1318 return ASM_OPERANDS_INPUT_LENGTH (body);
1319 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1320 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1321 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1;
1322 else if (GET_CODE (body) == PARALLEL
1323 && GET_CODE (XVECEXP (body, 0, 0)) == SET
1324 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
1326 /* Multiple output operands, or 1 output plus some clobbers:
1327 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1331 /* Count backwards through CLOBBERs to determine number of SETs. */
1332 for (i = XVECLEN (body, 0); i > 0; i--)
1334 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1336 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1340 /* N_SETS is now number of output operands. */
1343 /* Verify that all the SETs we have
1344 came from a single original asm_operands insn
1345 (so that invalid combinations are blocked). */
1346 for (i = 0; i < n_sets; i++)
1348 rtx elt = XVECEXP (body, 0, i);
1349 if (GET_CODE (elt) != SET)
1351 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1353 /* If these ASM_OPERANDS rtx's came from different original insns
1354 then they aren't allowed together. */
1355 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1356 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0))))
1359 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)))
1362 else if (GET_CODE (body) == PARALLEL
1363 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1365 /* 0 outputs, but some clobbers:
1366 body is [(asm_operands ...) (clobber (reg ...))...]. */
1369 /* Make sure all the other parallel things really are clobbers. */
1370 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1371 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1374 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
1380 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1381 copy its operands (both input and output) into the vector OPERANDS,
1382 the locations of the operands within the insn into the vector OPERAND_LOCS,
1383 and the constraints for the operands into CONSTRAINTS.
1384 Write the modes of the operands into MODES.
1385 Return the assembler-template.
1387 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1388 we don't store that info. */
1391 decode_asm_operands (body, operands, operand_locs, constraints, modes)
1395 const char **constraints;
1396 enum machine_mode *modes;
1402 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1404 rtx asmop = SET_SRC (body);
1405 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1407 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1;
1409 for (i = 1; i < noperands; i++)
1412 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1);
1414 operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1);
1416 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1);
1418 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1);
1421 /* The output is in the SET.
1422 Its constraint is in the ASM_OPERANDS itself. */
1424 operands[0] = SET_DEST (body);
1426 operand_locs[0] = &SET_DEST (body);
1428 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1430 modes[0] = GET_MODE (SET_DEST (body));
1431 template = ASM_OPERANDS_TEMPLATE (asmop);
1433 else if (GET_CODE (body) == ASM_OPERANDS)
1436 /* No output operands: BODY is (asm_operands ....). */
1438 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop);
1440 /* The input operands are found in the 1st element vector. */
1441 /* Constraints for inputs are in the 2nd element vector. */
1442 for (i = 0; i < noperands; i++)
1445 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1447 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1449 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1451 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1453 template = ASM_OPERANDS_TEMPLATE (asmop);
1455 else if (GET_CODE (body) == PARALLEL
1456 && GET_CODE (XVECEXP (body, 0, 0)) == SET)
1458 rtx asmop = SET_SRC (XVECEXP (body, 0, 0));
1459 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1460 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1461 int nout = 0; /* Does not include CLOBBERs. */
1463 /* At least one output, plus some CLOBBERs. */
1465 /* The outputs are in the SETs.
1466 Their constraints are in the ASM_OPERANDS itself. */
1467 for (i = 0; i < nparallel; i++)
1469 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1470 break; /* Past last SET */
1473 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1475 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1477 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1479 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1483 for (i = 0; i < nin; i++)
1486 operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i);
1488 operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i);
1490 constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1492 modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1495 template = ASM_OPERANDS_TEMPLATE (asmop);
1497 else if (GET_CODE (body) == PARALLEL
1498 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1500 /* No outputs, but some CLOBBERs. */
1502 rtx asmop = XVECEXP (body, 0, 0);
1503 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1505 for (i = 0; i < nin; i++)
1508 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1510 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1512 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1514 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1517 template = ASM_OPERANDS_TEMPLATE (asmop);
1523 /* Check if an asm_operand matches it's constraints.
1524 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1527 asm_operand_ok (op, constraint)
1529 const char *constraint;
1533 /* Use constrain_operands after reload. */
1534 if (reload_completed)
1539 switch (*constraint++)
1552 case '0': case '1': case '2': case '3': case '4':
1553 case '5': case '6': case '7': case '8': case '9':
1554 /* For best results, our caller should have given us the
1555 proper matching constraint, but we can't actually fail
1556 the check if they didn't. Indicate that results are
1562 if (address_operand (op, VOIDmode))
1567 case 'V': /* non-offsettable */
1568 if (memory_operand (op, VOIDmode))
1572 case 'o': /* offsettable */
1573 if (offsettable_nonstrict_memref_p (op))
1578 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1579 excepting those that expand_call created. Further, on some
1580 machines which do not have generalized auto inc/dec, an inc/dec
1581 is not a memory_operand.
1583 Match any memory and hope things are resolved after reload. */
1585 if (GET_CODE (op) == MEM
1587 || GET_CODE (XEXP (op, 0)) == PRE_DEC
1588 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1593 if (GET_CODE (op) == MEM
1595 || GET_CODE (XEXP (op, 0)) == PRE_INC
1596 || GET_CODE (XEXP (op, 0)) == POST_INC))
1601 #ifndef REAL_ARITHMETIC
1602 /* Match any floating double constant, but only if
1603 we can examine the bits of it reliably. */
1604 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1605 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1606 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1612 if (GET_CODE (op) == CONST_DOUBLE)
1617 if (GET_CODE (op) == CONST_DOUBLE
1618 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G'))
1622 if (GET_CODE (op) == CONST_DOUBLE
1623 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H'))
1628 if (GET_CODE (op) == CONST_INT
1629 || (GET_CODE (op) == CONST_DOUBLE
1630 && GET_MODE (op) == VOIDmode))
1636 #ifdef LEGITIMATE_PIC_OPERAND_P
1637 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1644 if (GET_CODE (op) == CONST_INT
1645 || (GET_CODE (op) == CONST_DOUBLE
1646 && GET_MODE (op) == VOIDmode))
1651 if (GET_CODE (op) == CONST_INT
1652 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'))
1656 if (GET_CODE (op) == CONST_INT
1657 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J'))
1661 if (GET_CODE (op) == CONST_INT
1662 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
1666 if (GET_CODE (op) == CONST_INT
1667 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'))
1671 if (GET_CODE (op) == CONST_INT
1672 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M'))
1676 if (GET_CODE (op) == CONST_INT
1677 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N'))
1681 if (GET_CODE (op) == CONST_INT
1682 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'))
1686 if (GET_CODE (op) == CONST_INT
1687 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'))
1695 if (general_operand (op, VOIDmode))
1699 #ifdef EXTRA_CONSTRAINT
1701 if (EXTRA_CONSTRAINT (op, 'Q'))
1705 if (EXTRA_CONSTRAINT (op, 'R'))
1709 if (EXTRA_CONSTRAINT (op, 'S'))
1713 if (EXTRA_CONSTRAINT (op, 'T'))
1717 if (EXTRA_CONSTRAINT (op, 'U'))
1724 if (GET_MODE (op) == BLKmode)
1726 if (register_operand (op, VOIDmode))
1735 /* Given an rtx *P, if it is a sum containing an integer constant term,
1736 return the location (type rtx *) of the pointer to that constant term.
1737 Otherwise, return a null pointer. */
1740 find_constant_term_loc (p)
1744 register enum rtx_code code = GET_CODE (*p);
1746 /* If *P IS such a constant term, P is its location. */
1748 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1752 /* Otherwise, if not a sum, it has no constant term. */
1754 if (GET_CODE (*p) != PLUS)
1757 /* If one of the summands is constant, return its location. */
1759 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1760 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1763 /* Otherwise, check each summand for containing a constant term. */
1765 if (XEXP (*p, 0) != 0)
1767 tem = find_constant_term_loc (&XEXP (*p, 0));
1772 if (XEXP (*p, 1) != 0)
1774 tem = find_constant_term_loc (&XEXP (*p, 1));
1782 /* Return 1 if OP is a memory reference
1783 whose address contains no side effects
1784 and remains valid after the addition
1785 of a positive integer less than the
1786 size of the object being referenced.
1788 We assume that the original address is valid and do not check it.
1790 This uses strict_memory_address_p as a subroutine, so
1791 don't use it before reload. */
1794 offsettable_memref_p (op)
1797 return ((GET_CODE (op) == MEM)
1798 && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)));
1801 /* Similar, but don't require a strictly valid mem ref:
1802 consider pseudo-regs valid as index or base regs. */
1805 offsettable_nonstrict_memref_p (op)
1808 return ((GET_CODE (op) == MEM)
1809 && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0)));
1812 /* Return 1 if Y is a memory address which contains no side effects
1813 and would remain valid after the addition of a positive integer
1814 less than the size of that mode.
1816 We assume that the original address is valid and do not check it.
1817 We do check that it is valid for narrower modes.
1819 If STRICTP is nonzero, we require a strictly valid address,
1820 for the sake of use in reload.c. */
1823 offsettable_address_p (strictp, mode, y)
1825 enum machine_mode mode;
1828 register enum rtx_code ycode = GET_CODE (y);
1832 int (*addressp) PROTO ((enum machine_mode, rtx)) =
1833 (strictp ? strict_memory_address_p : memory_address_p);
1835 if (CONSTANT_ADDRESS_P (y))
1838 /* Adjusting an offsettable address involves changing to a narrower mode.
1839 Make sure that's OK. */
1841 if (mode_dependent_address_p (y))
1844 /* If the expression contains a constant term,
1845 see if it remains valid when max possible offset is added. */
1847 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
1852 *y2 = plus_constant (*y2, GET_MODE_SIZE (mode) - 1);
1853 /* Use QImode because an odd displacement may be automatically invalid
1854 for any wider mode. But it should be valid for a single byte. */
1855 good = (*addressp) (QImode, y);
1857 /* In any case, restore old contents of memory. */
1862 if (ycode == PRE_DEC || ycode == PRE_INC
1863 || ycode == POST_DEC || ycode == POST_INC)
1866 /* The offset added here is chosen as the maximum offset that
1867 any instruction could need to add when operating on something
1868 of the specified mode. We assume that if Y and Y+c are
1869 valid addresses then so is Y+d for all 0<d<c. */
1871 z = plus_constant_for_output (y, GET_MODE_SIZE (mode) - 1);
1873 /* Use QImode because an odd displacement may be automatically invalid
1874 for any wider mode. But it should be valid for a single byte. */
1875 return (*addressp) (QImode, z);
1878 /* Return 1 if ADDR is an address-expression whose effect depends
1879 on the mode of the memory reference it is used in.
1881 Autoincrement addressing is a typical example of mode-dependence
1882 because the amount of the increment depends on the mode. */
1885 mode_dependent_address_p (addr)
1886 rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
1888 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
1890 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1891 win: ATTRIBUTE_UNUSED_LABEL
1895 /* Return 1 if OP is a general operand
1896 other than a memory ref with a mode dependent address. */
1899 mode_independent_operand (op, mode)
1900 enum machine_mode mode;
1905 if (! general_operand (op, mode))
1908 if (GET_CODE (op) != MEM)
1911 addr = XEXP (op, 0);
1912 GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose);
1914 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1915 lose: ATTRIBUTE_UNUSED_LABEL
1919 /* Given an operand OP that is a valid memory reference
1920 which satisfies offsettable_memref_p,
1921 return a new memory reference whose address has been adjusted by OFFSET.
1922 OFFSET should be positive and less than the size of the object referenced.
1926 adj_offsettable_operand (op, offset)
1930 register enum rtx_code code = GET_CODE (op);
1934 register rtx y = XEXP (op, 0);
1937 if (CONSTANT_ADDRESS_P (y))
1939 new = gen_rtx_MEM (GET_MODE (op),
1940 plus_constant_for_output (y, offset));
1941 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op);
1945 if (GET_CODE (y) == PLUS)
1948 register rtx *const_loc;
1952 const_loc = find_constant_term_loc (&z);
1955 *const_loc = plus_constant_for_output (*const_loc, offset);
1960 new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset));
1961 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op);
1967 /* Analyze INSN and fill in recog_data. */
1976 rtx body = PATTERN (insn);
1978 recog_data.n_operands = 0;
1979 recog_data.n_alternatives = 0;
1980 recog_data.n_dups = 0;
1982 switch (GET_CODE (body))
1994 recog_data.n_operands = noperands = asm_noperands (body);
1997 /* This insn is an `asm' with operands. */
1999 /* expand_asm_operands makes sure there aren't too many operands. */
2000 if (noperands > MAX_RECOG_OPERANDS)
2003 /* Now get the operand values and constraints out of the insn. */
2004 decode_asm_operands (body, recog_data.operand,
2005 recog_data.operand_loc,
2006 recog_data.constraints,
2007 recog_data.operand_mode);
2010 const char *p = recog_data.constraints[0];
2011 recog_data.n_alternatives = 1;
2013 recog_data.n_alternatives += (*p++ == ',');
2015 #ifndef REGISTER_CONSTRAINTS
2016 bzero (recog_data.operand_address_p,
2017 sizeof recog_data.operand_address_p);
2025 /* Ordinary insn: recognize it, get the operands via insn_extract
2026 and get the constraints. */
2028 icode = recog_memoized (insn);
2030 fatal_insn_not_found (insn);
2032 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2033 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2034 recog_data.n_dups = insn_data[icode].n_dups;
2036 insn_extract (insn);
2038 for (i = 0; i < noperands; i++)
2040 #ifdef REGISTER_CONSTRAINTS
2041 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2043 recog_data.operand_address_p[i]
2044 = insn_data[icode].operand[i].address_p;
2046 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2049 for (i = 0; i < noperands; i++)
2050 recog_data.operand_type[i]
2051 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2052 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2055 if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES)
2059 /* After calling extract_insn, you can use this function to extract some
2060 information from the constraint strings into a more usable form.
2061 The collected data is stored in recog_op_alt. */
2063 preprocess_constraints ()
2067 memset (recog_op_alt, 0, sizeof recog_op_alt);
2068 for (i = 0; i < recog_data.n_operands; i++)
2071 struct operand_alternative *op_alt;
2072 const char *p = recog_data.constraints[i];
2074 op_alt = recog_op_alt[i];
2076 for (j = 0; j < recog_data.n_alternatives; j++)
2078 op_alt[j].class = NO_REGS;
2079 op_alt[j].constraint = p;
2080 op_alt[j].matches = -1;
2081 op_alt[j].matched = -1;
2083 if (*p == '\0' || *p == ',')
2085 op_alt[j].anything_ok = 1;
2095 while (c != ',' && c != '\0');
2096 if (c == ',' || c == '\0')
2101 case '=': case '+': case '*': case '%':
2102 case 'E': case 'F': case 'G': case 'H':
2103 case 's': case 'i': case 'n':
2104 case 'I': case 'J': case 'K': case 'L':
2105 case 'M': case 'N': case 'O': case 'P':
2106 #ifdef EXTRA_CONSTRAINT
2107 case 'Q': case 'R': case 'S': case 'T': case 'U':
2109 /* These don't say anything we care about. */
2113 op_alt[j].reject += 6;
2116 op_alt[j].reject += 600;
2119 op_alt[j].earlyclobber = 1;
2122 case '0': case '1': case '2': case '3': case '4':
2123 case '5': case '6': case '7': case '8': case '9':
2124 op_alt[j].matches = c - '0';
2125 op_alt[op_alt[j].matches].matched = i;
2129 op_alt[j].memory_ok = 1;
2132 op_alt[j].decmem_ok = 1;
2135 op_alt[j].incmem_ok = 1;
2138 op_alt[j].nonoffmem_ok = 1;
2141 op_alt[j].offmem_ok = 1;
2144 op_alt[j].anything_ok = 1;
2148 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) BASE_REG_CLASS];
2152 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS];
2156 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
2164 #ifdef REGISTER_CONSTRAINTS
2166 /* Check the operands of an insn against the insn's operand constraints
2167 and return 1 if they are valid.
2168 The information about the insn's operands, constraints, operand modes
2169 etc. is obtained from the global variables set up by extract_insn.
2171 WHICH_ALTERNATIVE is set to a number which indicates which
2172 alternative of constraints was matched: 0 for the first alternative,
2173 1 for the next, etc.
2175 In addition, when two operands are match
2176 and it happens that the output operand is (reg) while the
2177 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2178 make the output operand look like the input.
2179 This is because the output operand is the one the template will print.
2181 This is used in final, just before printing the assembler code and by
2182 the routines that determine an insn's attribute.
2184 If STRICT is a positive non-zero value, it means that we have been
2185 called after reload has been completed. In that case, we must
2186 do all checks strictly. If it is zero, it means that we have been called
2187 before reload has completed. In that case, we first try to see if we can
2188 find an alternative that matches strictly. If not, we try again, this
2189 time assuming that reload will fix up the insn. This provides a "best
2190 guess" for the alternative and is used to compute attributes of insns prior
2191 to reload. A negative value of STRICT is used for this internal call. */
2199 constrain_operands (strict)
2202 const char *constraints[MAX_RECOG_OPERANDS];
2203 int matching_operands[MAX_RECOG_OPERANDS];
2204 int earlyclobber[MAX_RECOG_OPERANDS];
2207 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2208 int funny_match_index;
2210 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2213 for (c = 0; c < recog_data.n_operands; c++)
2215 constraints[c] = recog_data.constraints[c];
2216 matching_operands[c] = -1;
2219 which_alternative = 0;
2221 while (which_alternative < recog_data.n_alternatives)
2225 funny_match_index = 0;
2227 for (opno = 0; opno < recog_data.n_operands; opno++)
2229 register rtx op = recog_data.operand[opno];
2230 enum machine_mode mode = GET_MODE (op);
2231 register const char *p = constraints[opno];
2236 earlyclobber[opno] = 0;
2238 /* A unary operator may be accepted by the predicate, but it
2239 is irrelevant for matching constraints. */
2240 if (GET_RTX_CLASS (GET_CODE (op)) == '1')
2243 if (GET_CODE (op) == SUBREG)
2245 if (GET_CODE (SUBREG_REG (op)) == REG
2246 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2247 offset = SUBREG_WORD (op);
2248 op = SUBREG_REG (op);
2251 /* An empty constraint or empty alternative
2252 allows anything which matched the pattern. */
2253 if (*p == 0 || *p == ',')
2256 while (*p && (c = *p++) != ',')
2259 case '?': case '!': case '*': case '%':
2264 /* Ignore rest of this alternative as far as
2265 constraint checking is concerned. */
2266 while (*p && *p != ',')
2271 earlyclobber[opno] = 1;
2274 case '0': case '1': case '2': case '3': case '4':
2275 case '5': case '6': case '7': case '8': case '9':
2277 /* This operand must be the same as a previous one.
2278 This kind of constraint is used for instructions such
2279 as add when they take only two operands.
2281 Note that the lower-numbered operand is passed first.
2283 If we are not testing strictly, assume that this constraint
2284 will be satisfied. */
2289 rtx op1 = recog_data.operand[c - '0'];
2290 rtx op2 = recog_data.operand[opno];
2292 /* A unary operator may be accepted by the predicate,
2293 but it is irrelevant for matching constraints. */
2294 if (GET_RTX_CLASS (GET_CODE (op1)) == '1')
2295 op1 = XEXP (op1, 0);
2296 if (GET_RTX_CLASS (GET_CODE (op2)) == '1')
2297 op2 = XEXP (op2, 0);
2299 val = operands_match_p (op1, op2);
2302 matching_operands[opno] = c - '0';
2303 matching_operands[c - '0'] = opno;
2307 /* If output is *x and input is *--x,
2308 arrange later to change the output to *--x as well,
2309 since the output op is the one that will be printed. */
2310 if (val == 2 && strict > 0)
2312 funny_match[funny_match_index].this = opno;
2313 funny_match[funny_match_index++].other = c - '0';
2318 /* p is used for address_operands. When we are called by
2319 gen_reload, no one will have checked that the address is
2320 strictly valid, i.e., that all pseudos requiring hard regs
2321 have gotten them. */
2323 || (strict_memory_address_p (recog_data.operand_mode[opno],
2328 /* No need to check general_operand again;
2329 it was done in insn-recog.c. */
2331 /* Anything goes unless it is a REG and really has a hard reg
2332 but the hard reg is not in the class GENERAL_REGS. */
2334 || GENERAL_REGS == ALL_REGS
2335 || GET_CODE (op) != REG
2336 || (reload_in_progress
2337 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2338 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2345 && GET_CODE (op) == REG
2346 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2347 || (strict == 0 && GET_CODE (op) == SCRATCH)
2348 || (GET_CODE (op) == REG
2349 && ((GENERAL_REGS == ALL_REGS
2350 && REGNO (op) < FIRST_PSEUDO_REGISTER)
2351 || reg_fits_class_p (op, GENERAL_REGS,
2357 /* This is used for a MATCH_SCRATCH in the cases when
2358 we don't actually need anything. So anything goes
2364 if (GET_CODE (op) == MEM
2365 /* Before reload, accept what reload can turn into mem. */
2366 || (strict < 0 && CONSTANT_P (op))
2367 /* During reload, accept a pseudo */
2368 || (reload_in_progress && GET_CODE (op) == REG
2369 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2374 if (GET_CODE (op) == MEM
2375 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
2376 || GET_CODE (XEXP (op, 0)) == POST_DEC))
2381 if (GET_CODE (op) == MEM
2382 && (GET_CODE (XEXP (op, 0)) == PRE_INC
2383 || GET_CODE (XEXP (op, 0)) == POST_INC))
2388 #ifndef REAL_ARITHMETIC
2389 /* Match any CONST_DOUBLE, but only if
2390 we can examine the bits of it reliably. */
2391 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2392 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
2393 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
2396 if (GET_CODE (op) == CONST_DOUBLE)
2401 if (GET_CODE (op) == CONST_DOUBLE)
2407 if (GET_CODE (op) == CONST_DOUBLE
2408 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
2413 if (GET_CODE (op) == CONST_INT
2414 || (GET_CODE (op) == CONST_DOUBLE
2415 && GET_MODE (op) == VOIDmode))
2418 if (CONSTANT_P (op))
2423 if (GET_CODE (op) == CONST_INT
2424 || (GET_CODE (op) == CONST_DOUBLE
2425 && GET_MODE (op) == VOIDmode))
2437 if (GET_CODE (op) == CONST_INT
2438 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
2442 #ifdef EXTRA_CONSTRAINT
2448 if (EXTRA_CONSTRAINT (op, c))
2454 if (GET_CODE (op) == MEM
2455 && ((strict > 0 && ! offsettable_memref_p (op))
2457 && !(CONSTANT_P (op) || GET_CODE (op) == MEM))
2458 || (reload_in_progress
2459 && !(GET_CODE (op) == REG
2460 && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
2465 if ((strict > 0 && offsettable_memref_p (op))
2466 || (strict == 0 && offsettable_nonstrict_memref_p (op))
2467 /* Before reload, accept what reload can handle. */
2469 && (CONSTANT_P (op) || GET_CODE (op) == MEM))
2470 /* During reload, accept a pseudo */
2471 || (reload_in_progress && GET_CODE (op) == REG
2472 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2479 && GET_CODE (op) == REG
2480 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2481 || (strict == 0 && GET_CODE (op) == SCRATCH)
2482 || (GET_CODE (op) == REG
2483 && reg_fits_class_p (op, REG_CLASS_FROM_LETTER (c),
2488 constraints[opno] = p;
2489 /* If this operand did not win somehow,
2490 this alternative loses. */
2494 /* This alternative won; the operands are ok.
2495 Change whichever operands this alternative says to change. */
2500 /* See if any earlyclobber operand conflicts with some other
2504 for (eopno = 0; eopno < recog_data.n_operands; eopno++)
2505 /* Ignore earlyclobber operands now in memory,
2506 because we would often report failure when we have
2507 two memory operands, one of which was formerly a REG. */
2508 if (earlyclobber[eopno]
2509 && GET_CODE (recog_data.operand[eopno]) == REG)
2510 for (opno = 0; opno < recog_data.n_operands; opno++)
2511 if ((GET_CODE (recog_data.operand[opno]) == MEM
2512 || recog_data.operand_type[opno] != OP_OUT)
2514 /* Ignore things like match_operator operands. */
2515 && *recog_data.constraints[opno] != 0
2516 && ! (matching_operands[opno] == eopno
2517 && operands_match_p (recog_data.operand[opno],
2518 recog_data.operand[eopno]))
2519 && ! safe_from_earlyclobber (recog_data.operand[opno],
2520 recog_data.operand[eopno]))
2525 while (--funny_match_index >= 0)
2527 recog_data.operand[funny_match[funny_match_index].other]
2528 = recog_data.operand[funny_match[funny_match_index].this];
2535 which_alternative++;
2538 /* If we are about to reject this, but we are not to test strictly,
2539 try a very loose test. Only return failure if it fails also. */
2541 return constrain_operands (-1);
2546 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2547 is a hard reg in class CLASS when its regno is offset by OFFSET
2548 and changed to mode MODE.
2549 If REG occupies multiple hard regs, all of them must be in CLASS. */
2552 reg_fits_class_p (operand, class, offset, mode)
2554 register enum reg_class class;
2556 enum machine_mode mode;
2558 register int regno = REGNO (operand);
2559 if (regno < FIRST_PSEUDO_REGISTER
2560 && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2565 for (sr = HARD_REGNO_NREGS (regno, mode) - 1;
2567 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2576 #endif /* REGISTER_CONSTRAINTS */
2578 /* Do the splitting of insns in the block B. Only try to actually split if
2579 DO_SPLIT is true; otherwise, just remove nops. */
2582 split_block_insns (b, do_split)
2588 for (insn = BLOCK_HEAD (b);; insn = next)
2592 /* Can't use `next_real_insn' because that
2593 might go across CODE_LABELS and short-out basic blocks. */
2594 next = NEXT_INSN (insn);
2595 if (GET_CODE (insn) != INSN)
2597 if (insn == BLOCK_END (b))
2603 /* Don't split no-op move insns. These should silently disappear
2604 later in final. Splitting such insns would break the code
2605 that handles REG_NO_CONFLICT blocks. */
2606 set = single_set (insn);
2607 if (set && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
2609 if (insn == BLOCK_END (b))
2612 /* Nops get in the way while scheduling, so delete them now if
2613 register allocation has already been done. It is too risky
2614 to try to do this before register allocation, and there are
2615 unlikely to be very many nops then anyways. */
2616 if (reload_completed)
2619 PUT_CODE (insn, NOTE);
2620 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2621 NOTE_SOURCE_FILE (insn) = 0;
2629 /* Split insns here to get max fine-grain parallelism. */
2630 rtx first = PREV_INSN (insn);
2631 rtx notes = REG_NOTES (insn);
2632 rtx last = try_split (PATTERN (insn), insn, 1);
2636 /* try_split returns the NOTE that INSN became. */
2637 first = NEXT_INSN (first);
2638 #ifdef INSN_SCHEDULING
2639 update_life_info (notes, first, last, insn, insn);
2641 PUT_CODE (insn, NOTE);
2642 NOTE_SOURCE_FILE (insn) = 0;
2643 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2644 if (insn == BLOCK_HEAD (b))
2645 BLOCK_HEAD (b) = first;
2646 if (insn == BLOCK_END (b))
2648 BLOCK_END (b) = last;
2654 if (insn == BLOCK_END (b))
2659 #ifdef HAVE_peephole2
2660 /* Return the Nth non-note insn after INSN, or return NULL_RTX if it does
2661 not exist. Used by the recognizer to find the next insn to match in a
2662 multi-insn pattern. */
2664 recog_next_insn (insn, n)
2668 while (insn != NULL_RTX && n > 0)
2670 insn = next_nonnote_insn (insn);
2672 if (insn == NULL_RTX)
2675 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
2684 /* Perform the peephole2 optimization pass. */
2686 peephole2_optimize (dump_file)
2687 FILE *dump_file ATTRIBUTE_UNUSED;
2690 rtx epilogue_insn = 0;
2692 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
2694 if (GET_CODE (insn) == NOTE
2695 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_EPILOGUE_BEG)
2697 epilogue_insn = insn;
2702 init_resource_info (epilogue_insn);
2704 for (insn = get_insns (); insn != NULL;
2705 insn = next_nonnote_insn (insn))
2707 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN)
2710 rtx before = PREV_INSN (insn);
2712 rtx try = peephole2_insns (PATTERN (insn), insn, &last_insn);
2715 replace_insns (insn, last_insn, try, NULL_RTX);
2716 insn = NEXT_INSN (before);
2721 free_resource_info ();