1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "insn-config.h"
28 #include "insn-attr.h"
29 #include "hard-reg-set.h"
36 #include "basic-block.h"
40 #ifndef STACK_PUSH_CODE
41 #ifdef STACK_GROWS_DOWNWARD
42 #define STACK_PUSH_CODE PRE_DEC
44 #define STACK_PUSH_CODE PRE_INC
48 #ifndef STACK_POP_CODE
49 #ifdef STACK_GROWS_DOWNWARD
50 #define STACK_POP_CODE POST_INC
52 #define STACK_POP_CODE POST_DEC
56 static void validate_replace_rtx_1 PARAMS ((rtx *, rtx, rtx, rtx));
57 static rtx *find_single_use_1 PARAMS ((rtx, rtx *));
58 static rtx *find_constant_term_loc PARAMS ((rtx *));
59 static void validate_replace_src_1 PARAMS ((rtx *, void *));
61 /* Nonzero means allow operands to be volatile.
62 This should be 0 if you are generating rtl, such as if you are calling
63 the functions in optabs.c and expmed.c (most of the time).
64 This should be 1 if all valid insns need to be recognized,
65 such as in regclass.c and final.c and reload.c.
67 init_recog and init_recog_no_volatile are responsible for setting this. */
71 struct recog_data recog_data;
73 /* Contains a vector of operand_alternative structures for every operand.
74 Set up by preprocess_constraints. */
75 struct operand_alternative recog_op_alt[MAX_RECOG_OPERANDS][MAX_RECOG_ALTERNATIVES];
77 /* On return from `constrain_operands', indicate which alternative
80 int which_alternative;
82 /* Nonzero after end of reload pass.
83 Set to 1 or 0 by toplev.c.
84 Controls the significance of (SUBREG (MEM)). */
88 /* Initialize data used by the function `recog'.
89 This must be called once in the compilation of a function
90 before any insn recognition may be done in the function. */
93 init_recog_no_volatile ()
104 /* Try recognizing the instruction INSN,
105 and return the code number that results.
106 Remember the code so that repeated calls do not
107 need to spend the time for actual rerecognition.
109 This function is the normal interface to instruction recognition.
110 The automatically-generated function `recog' is normally called
111 through this one. (The only exception is in combine.c.) */
114 recog_memoized_1 (insn)
117 if (INSN_CODE (insn) < 0)
118 INSN_CODE (insn) = recog (PATTERN (insn), insn, NULL_PTR);
119 return INSN_CODE (insn);
122 /* Check that X is an insn-body for an `asm' with operands
123 and that the operands mentioned in it are legitimate. */
126 check_asm_operands (x)
131 const char **constraints;
134 /* Post-reload, be more strict with things. */
135 if (reload_completed)
137 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
138 extract_insn (make_insn_raw (x));
139 constrain_operands (1);
140 return which_alternative >= 0;
143 noperands = asm_noperands (x);
149 operands = (rtx *) alloca (noperands * sizeof (rtx));
150 constraints = (const char **) alloca (noperands * sizeof (char *));
152 decode_asm_operands (x, operands, NULL_PTR, constraints, NULL_PTR);
154 for (i = 0; i < noperands; i++)
156 const char *c = constraints[i];
159 if (ISDIGIT ((unsigned char)c[0]) && c[1] == '\0')
160 c = constraints[c[0] - '0'];
162 if (! asm_operand_ok (operands[i], c))
169 /* Static data for the next two routines. */
171 typedef struct change_t
179 static change_t *changes;
180 static int changes_allocated;
182 static int num_changes = 0;
184 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
185 at which NEW will be placed. If OBJECT is zero, no validation is done,
186 the change is simply made.
188 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
189 will be called with the address and mode as parameters. If OBJECT is
190 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
193 IN_GROUP is non-zero if this is part of a group of changes that must be
194 performed as a group. In that case, the changes will be stored. The
195 function `apply_change_group' will validate and apply the changes.
197 If IN_GROUP is zero, this is a single change. Try to recognize the insn
198 or validate the memory reference with the change applied. If the result
199 is not valid for the machine, suppress the change and return zero.
200 Otherwise, perform the change and return 1. */
203 validate_change (object, loc, new, in_group)
211 if (old == new || rtx_equal_p (old, new))
214 if (in_group == 0 && num_changes != 0)
219 /* Save the information describing this change. */
220 if (num_changes >= changes_allocated)
222 if (changes_allocated == 0)
223 /* This value allows for repeated substitutions inside complex
224 indexed addresses, or changes in up to 5 insns. */
225 changes_allocated = MAX_RECOG_OPERANDS * 5;
227 changes_allocated *= 2;
230 (change_t*) xrealloc (changes,
231 sizeof (change_t) * changes_allocated);
234 changes[num_changes].object = object;
235 changes[num_changes].loc = loc;
236 changes[num_changes].old = old;
238 if (object && GET_CODE (object) != MEM)
240 /* Set INSN_CODE to force rerecognition of insn. Save old code in
242 changes[num_changes].old_code = INSN_CODE (object);
243 INSN_CODE (object) = -1;
248 /* If we are making a group of changes, return 1. Otherwise, validate the
249 change group we made. */
254 return apply_change_group ();
257 /* This subroutine of apply_change_group verifies whether the changes to INSN
258 were valid; i.e. whether INSN can still be recognized. */
261 insn_invalid_p (insn)
264 rtx pat = PATTERN (insn);
265 int num_clobbers = 0;
266 /* If we are before reload and the pattern is a SET, see if we can add
268 int icode = recog (pat, insn,
269 (GET_CODE (pat) == SET
270 && ! reload_completed && ! reload_in_progress)
271 ? &num_clobbers : NULL_PTR);
272 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0;
275 /* If this is an asm and the operand aren't legal, then fail. Likewise if
276 this is not an asm and the insn wasn't recognized. */
277 if ((is_asm && ! check_asm_operands (PATTERN (insn)))
278 || (!is_asm && icode < 0))
281 /* If we have to add CLOBBERs, fail if we have to add ones that reference
282 hard registers since our callers can't know if they are live or not.
283 Otherwise, add them. */
284 if (num_clobbers > 0)
288 if (added_clobbers_hard_reg_p (icode))
291 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1));
292 XVECEXP (newpat, 0, 0) = pat;
293 add_clobbers (newpat, icode);
294 PATTERN (insn) = pat = newpat;
297 /* After reload, verify that all constraints are satisfied. */
298 if (reload_completed)
302 if (! constrain_operands (1))
306 INSN_CODE (insn) = icode;
310 /* Apply a group of changes previously issued with `validate_change'.
311 Return 1 if all changes are valid, zero otherwise. */
314 apply_change_group ()
318 /* The changes have been applied and all INSN_CODEs have been reset to force
321 The changes are valid if we aren't given an object, or if we are
322 given a MEM and it still is a valid address, or if this is in insn
323 and it is recognized. In the latter case, if reload has completed,
324 we also require that the operands meet the constraints for
327 for (i = 0; i < num_changes; i++)
329 rtx object = changes[i].object;
334 if (GET_CODE (object) == MEM)
336 if (! memory_address_p (GET_MODE (object), XEXP (object, 0)))
339 else if (insn_invalid_p (object))
341 rtx pat = PATTERN (object);
343 /* Perhaps we couldn't recognize the insn because there were
344 extra CLOBBERs at the end. If so, try to re-recognize
345 without the last CLOBBER (later iterations will cause each of
346 them to be eliminated, in turn). But don't do this if we
347 have an ASM_OPERAND. */
348 if (GET_CODE (pat) == PARALLEL
349 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER
350 && asm_noperands (PATTERN (object)) < 0)
354 if (XVECLEN (pat, 0) == 2)
355 newpat = XVECEXP (pat, 0, 0);
361 = gen_rtx_PARALLEL (VOIDmode,
362 rtvec_alloc (XVECLEN (pat, 0) - 1));
363 for (j = 0; j < XVECLEN (newpat, 0); j++)
364 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j);
367 /* Add a new change to this group to replace the pattern
368 with this new pattern. Then consider this change
369 as having succeeded. The change we added will
370 cause the entire call to fail if things remain invalid.
372 Note that this can lose if a later change than the one
373 we are processing specified &XVECEXP (PATTERN (object), 0, X)
374 but this shouldn't occur. */
376 validate_change (object, &PATTERN (object), newpat, 1);
378 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)
379 /* If this insn is a CLOBBER or USE, it is always valid, but is
387 if (i == num_changes)
399 /* Return the number of changes so far in the current group. */
402 num_validated_changes ()
407 /* Retract the changes numbered NUM and up. */
415 /* Back out all the changes. Do this in the opposite order in which
417 for (i = num_changes - 1; i >= num; i--)
419 *changes[i].loc = changes[i].old;
420 if (changes[i].object && GET_CODE (changes[i].object) != MEM)
421 INSN_CODE (changes[i].object) = changes[i].old_code;
426 /* Replace every occurrence of FROM in X with TO. Mark each change with
427 validate_change passing OBJECT. */
430 validate_replace_rtx_1 (loc, from, to, object)
432 rtx from, to, object;
435 register const char *fmt;
436 register rtx x = *loc;
442 /* X matches FROM if it is the same rtx or they are both referring to the
443 same register in the same mode. Avoid calling rtx_equal_p unless the
444 operands look similar. */
447 || (GET_CODE (x) == REG && GET_CODE (from) == REG
448 && GET_MODE (x) == GET_MODE (from)
449 && REGNO (x) == REGNO (from))
450 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from)
451 && rtx_equal_p (x, from)))
453 validate_change (object, loc, to, 1);
457 /* For commutative or comparison operations, try replacing each argument
458 separately and seeing if we made any changes. If so, put a constant
460 if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
462 int prev_changes = num_changes;
464 validate_replace_rtx_1 (&XEXP (x, 0), from, to, object);
465 validate_replace_rtx_1 (&XEXP (x, 1), from, to, object);
466 if (prev_changes != num_changes && CONSTANT_P (XEXP (x, 0)))
468 validate_change (object, loc,
469 gen_rtx_fmt_ee (GET_RTX_CLASS (code) == 'c' ? code
470 : swap_condition (code),
471 GET_MODE (x), XEXP (x, 1),
479 /* Note that if CODE's RTX_CLASS is "c" or "<" we will have already
480 done the substitution, otherwise we won't. */
485 /* If we have a PLUS whose second operand is now a CONST_INT, use
486 plus_constant to try to simplify it. */
487 if (GET_CODE (XEXP (x, 1)) == CONST_INT && XEXP (x, 1) == to)
488 validate_change (object, loc, plus_constant (XEXP (x, 0), INTVAL (to)),
493 if (GET_CODE (to) == CONST_INT && XEXP (x, 1) == from)
495 validate_change (object, loc,
496 plus_constant (XEXP (x, 0), - INTVAL (to)),
504 /* In these cases, the operation to be performed depends on the mode
505 of the operand. If we are replacing the operand with a VOIDmode
506 constant, we lose the information. So try to simplify the operation
508 if (GET_MODE (to) == VOIDmode
509 && (rtx_equal_p (XEXP (x, 0), from)
510 || (GET_CODE (XEXP (x, 0)) == SUBREG
511 && rtx_equal_p (SUBREG_REG (XEXP (x, 0)), from))))
515 /* If there is a subreg involved, crop to the portion of the
516 constant that we are interested in. */
517 if (GET_CODE (XEXP (x, 0)) == SUBREG)
519 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) <= UNITS_PER_WORD)
520 to = operand_subword (to, SUBREG_WORD (XEXP (x, 0)),
522 else if (GET_MODE_CLASS (GET_MODE (from)) == MODE_INT
523 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
524 <= HOST_BITS_PER_WIDE_INT))
526 int i = SUBREG_WORD (XEXP (x, 0)) * BITS_PER_WORD;
528 unsigned HOST_WIDE_INT vall;
530 if (GET_CODE (to) == CONST_INT)
533 valh = (HOST_WIDE_INT) vall < 0 ? ~0 : 0;
537 vall = CONST_DOUBLE_LOW (to);
538 valh = CONST_DOUBLE_HIGH (to);
541 if (WORDS_BIG_ENDIAN)
542 i = (GET_MODE_BITSIZE (GET_MODE (from))
543 - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - i);
544 if (i > 0 && i < HOST_BITS_PER_WIDE_INT)
545 vall = vall >> i | valh << (HOST_BITS_PER_WIDE_INT - i);
546 else if (i >= HOST_BITS_PER_WIDE_INT)
547 vall = valh >> (i - HOST_BITS_PER_WIDE_INT);
548 to = GEN_INT (trunc_int_for_mode (vall,
549 GET_MODE (XEXP (x, 0))));
552 to = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
555 /* If the above didn't fail, perform the extension from the
556 mode of the operand (and not the mode of FROM). */
558 new = simplify_unary_operation (code, GET_MODE (x), to,
559 GET_MODE (XEXP (x, 0)));
561 /* If any of the above failed, substitute in something that
562 we know won't be recognized. */
564 new = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
566 validate_change (object, loc, new, 1);
572 /* In case we are replacing by constant, attempt to simplify it to non-SUBREG
573 expression. We can't do this later, since the information about inner mode
575 if (CONSTANT_P (to) && rtx_equal_p (SUBREG_REG (x), from))
577 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD
578 && GET_MODE_SIZE (GET_MODE (from)) > UNITS_PER_WORD
579 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
581 rtx temp = operand_subword (to, SUBREG_WORD (x),
585 validate_change (object, loc, temp, 1);
589 if (subreg_lowpart_p (x))
591 rtx new = gen_lowpart_if_possible (GET_MODE (x), to);
594 validate_change (object, loc, new, 1);
599 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
600 since we are saying that the high bits don't matter. */
601 if (GET_MODE (to) == VOIDmode
602 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (from)))
604 validate_change (object, loc, to, 1);
609 /* Changing mode twice with SUBREG => just change it once,
610 or not at all if changing back to starting mode. */
611 if (GET_CODE (to) == SUBREG
612 && rtx_equal_p (SUBREG_REG (x), from))
614 if (GET_MODE (x) == GET_MODE (SUBREG_REG (to))
615 && SUBREG_WORD (x) == 0 && SUBREG_WORD (to) == 0)
617 validate_change (object, loc, SUBREG_REG (to), 1);
621 validate_change (object, loc,
622 gen_rtx_SUBREG (GET_MODE (x), SUBREG_REG (to),
623 SUBREG_WORD (x) + SUBREG_WORD (to)), 1);
627 /* If we have a SUBREG of a register that we are replacing and we are
628 replacing it with a MEM, make a new MEM and try replacing the
629 SUBREG with it. Don't do this if the MEM has a mode-dependent address
630 or if we would be widening it. */
632 if (GET_CODE (from) == REG
633 && GET_CODE (to) == MEM
634 && rtx_equal_p (SUBREG_REG (x), from)
635 && ! mode_dependent_address_p (XEXP (to, 0))
636 && ! MEM_VOLATILE_P (to)
637 && GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (GET_MODE (to)))
639 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
640 enum machine_mode mode = GET_MODE (x);
643 if (BYTES_BIG_ENDIAN)
644 offset += (MIN (UNITS_PER_WORD,
645 GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
646 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
648 new = gen_rtx_MEM (mode, plus_constant (XEXP (to, 0), offset));
649 MEM_COPY_ATTRIBUTES (new, to);
650 validate_change (object, loc, new, 1);
657 /* If we are replacing a register with memory, try to change the memory
658 to be the mode required for memory in extract operations (this isn't
659 likely to be an insertion operation; if it was, nothing bad will
660 happen, we might just fail in some cases). */
662 if (GET_CODE (from) == REG && GET_CODE (to) == MEM
663 && rtx_equal_p (XEXP (x, 0), from)
664 && GET_CODE (XEXP (x, 1)) == CONST_INT
665 && GET_CODE (XEXP (x, 2)) == CONST_INT
666 && ! mode_dependent_address_p (XEXP (to, 0))
667 && ! MEM_VOLATILE_P (to))
669 enum machine_mode wanted_mode = VOIDmode;
670 enum machine_mode is_mode = GET_MODE (to);
671 int pos = INTVAL (XEXP (x, 2));
674 if (code == ZERO_EXTRACT)
676 wanted_mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
677 if (wanted_mode == VOIDmode)
678 wanted_mode = word_mode;
682 if (code == SIGN_EXTRACT)
684 wanted_mode = insn_data[(int) CODE_FOR_extv].operand[1].mode;
685 if (wanted_mode == VOIDmode)
686 wanted_mode = word_mode;
690 /* If we have a narrower mode, we can do something. */
691 if (wanted_mode != VOIDmode
692 && GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode))
694 int offset = pos / BITS_PER_UNIT;
697 /* If the bytes and bits are counted differently, we
698 must adjust the offset. */
699 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN)
700 offset = (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode)
703 pos %= GET_MODE_BITSIZE (wanted_mode);
705 newmem = gen_rtx_MEM (wanted_mode,
706 plus_constant (XEXP (to, 0), offset));
707 MEM_COPY_ATTRIBUTES (newmem, to);
709 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1);
710 validate_change (object, &XEXP (x, 0), newmem, 1);
720 /* For commutative or comparison operations we've already performed
721 replacements. Don't try to perform them again. */
722 if (GET_RTX_CLASS (code) != '<' && GET_RTX_CLASS (code) != 'c')
724 fmt = GET_RTX_FORMAT (code);
725 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
728 validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
729 else if (fmt[i] == 'E')
730 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
731 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object);
736 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
737 with TO. After all changes have been made, validate by seeing
738 if INSN is still valid. */
741 validate_replace_rtx_subexp (from, to, insn, loc)
742 rtx from, to, insn, *loc;
744 validate_replace_rtx_1 (loc, from, to, insn);
745 return apply_change_group ();
748 /* Try replacing every occurrence of FROM in INSN with TO. After all
749 changes have been made, validate by seeing if INSN is still valid. */
752 validate_replace_rtx (from, to, insn)
755 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
756 return apply_change_group ();
759 /* Try replacing every occurrence of FROM in INSN with TO. */
762 validate_replace_rtx_group (from, to, insn)
765 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn);
768 /* Function called by note_uses to replace used subexpressions. */
769 struct validate_replace_src_data
771 rtx from; /* Old RTX */
772 rtx to; /* New RTX */
773 rtx insn; /* Insn in which substitution is occurring. */
777 validate_replace_src_1 (x, data)
781 struct validate_replace_src_data *d
782 = (struct validate_replace_src_data *) data;
784 validate_replace_rtx_1 (x, d->from, d->to, d->insn);
787 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
788 SET_DESTs. After all changes have been made, validate by seeing if
789 INSN is still valid. */
792 validate_replace_src (from, to, insn)
795 struct validate_replace_src_data d;
800 note_uses (&PATTERN (insn), validate_replace_src_1, &d);
801 return apply_change_group ();
805 /* Return 1 if the insn using CC0 set by INSN does not contain
806 any ordered tests applied to the condition codes.
807 EQ and NE tests do not count. */
810 next_insn_tests_no_inequality (insn)
813 register rtx next = next_cc0_user (insn);
815 /* If there is no next insn, we have to take the conservative choice. */
819 return ((GET_CODE (next) == JUMP_INSN
820 || GET_CODE (next) == INSN
821 || GET_CODE (next) == CALL_INSN)
822 && ! inequality_comparisons_p (PATTERN (next)));
825 #if 0 /* This is useless since the insn that sets the cc's
826 must be followed immediately by the use of them. */
827 /* Return 1 if the CC value set up by INSN is not used. */
830 next_insns_test_no_inequality (insn)
833 register rtx next = NEXT_INSN (insn);
835 for (; next != 0; next = NEXT_INSN (next))
837 if (GET_CODE (next) == CODE_LABEL
838 || GET_CODE (next) == BARRIER)
840 if (GET_CODE (next) == NOTE)
842 if (inequality_comparisons_p (PATTERN (next)))
844 if (sets_cc0_p (PATTERN (next)) == 1)
846 if (! reg_mentioned_p (cc0_rtx, PATTERN (next)))
854 /* This is used by find_single_use to locate an rtx that contains exactly one
855 use of DEST, which is typically either a REG or CC0. It returns a
856 pointer to the innermost rtx expression containing DEST. Appearances of
857 DEST that are being used to totally replace it are not counted. */
860 find_single_use_1 (dest, loc)
865 enum rtx_code code = GET_CODE (x);
882 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
883 of a REG that occupies all of the REG, the insn uses DEST if
884 it is mentioned in the destination or the source. Otherwise, we
885 need just check the source. */
886 if (GET_CODE (SET_DEST (x)) != CC0
887 && GET_CODE (SET_DEST (x)) != PC
888 && GET_CODE (SET_DEST (x)) != REG
889 && ! (GET_CODE (SET_DEST (x)) == SUBREG
890 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG
891 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
892 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
893 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
894 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
897 return find_single_use_1 (dest, &SET_SRC (x));
901 return find_single_use_1 (dest, &XEXP (x, 0));
907 /* If it wasn't one of the common cases above, check each expression and
908 vector of this code. Look for a unique usage of DEST. */
910 fmt = GET_RTX_FORMAT (code);
911 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
915 if (dest == XEXP (x, i)
916 || (GET_CODE (dest) == REG && GET_CODE (XEXP (x, i)) == REG
917 && REGNO (dest) == REGNO (XEXP (x, i))))
920 this_result = find_single_use_1 (dest, &XEXP (x, i));
923 result = this_result;
924 else if (this_result)
925 /* Duplicate usage. */
928 else if (fmt[i] == 'E')
932 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
934 if (XVECEXP (x, i, j) == dest
935 || (GET_CODE (dest) == REG
936 && GET_CODE (XVECEXP (x, i, j)) == REG
937 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
940 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
943 result = this_result;
944 else if (this_result)
953 /* See if DEST, produced in INSN, is used only a single time in the
954 sequel. If so, return a pointer to the innermost rtx expression in which
957 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
959 This routine will return usually zero either before flow is called (because
960 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
961 note can't be trusted).
963 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
964 care about REG_DEAD notes or LOG_LINKS.
966 Otherwise, we find the single use by finding an insn that has a
967 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
968 only referenced once in that insn, we know that it must be the first
969 and last insn referencing DEST. */
972 find_single_use (dest, insn, ploc)
984 next = NEXT_INSN (insn);
986 || (GET_CODE (next) != INSN && GET_CODE (next) != JUMP_INSN))
989 result = find_single_use_1 (dest, &PATTERN (next));
996 if (reload_completed || reload_in_progress || GET_CODE (dest) != REG)
999 for (next = next_nonnote_insn (insn);
1000 next != 0 && GET_CODE (next) != CODE_LABEL;
1001 next = next_nonnote_insn (next))
1002 if (INSN_P (next) && dead_or_set_p (next, dest))
1004 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
1005 if (XEXP (link, 0) == insn)
1010 result = find_single_use_1 (dest, &PATTERN (next));
1020 /* Return 1 if OP is a valid general operand for machine mode MODE.
1021 This is either a register reference, a memory reference,
1022 or a constant. In the case of a memory reference, the address
1023 is checked for general validity for the target machine.
1025 Register and memory references must have mode MODE in order to be valid,
1026 but some constants have no machine mode and are valid for any mode.
1028 If MODE is VOIDmode, OP is checked for validity for whatever mode
1031 The main use of this function is as a predicate in match_operand
1032 expressions in the machine description.
1034 For an explanation of this function's behavior for registers of
1035 class NO_REGS, see the comment for `register_operand'. */
1038 general_operand (op, mode)
1040 enum machine_mode mode;
1042 register enum rtx_code code = GET_CODE (op);
1043 int mode_altering_drug = 0;
1045 if (mode == VOIDmode)
1046 mode = GET_MODE (op);
1048 /* Don't accept CONST_INT or anything similar
1049 if the caller wants something floating. */
1050 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1051 && GET_MODE_CLASS (mode) != MODE_INT
1052 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1055 if (CONSTANT_P (op))
1056 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1057 || mode == VOIDmode)
1058 #ifdef LEGITIMATE_PIC_OPERAND_P
1059 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1061 && LEGITIMATE_CONSTANT_P (op));
1063 /* Except for certain constants with VOIDmode, already checked for,
1064 OP's mode must match MODE if MODE specifies a mode. */
1066 if (GET_MODE (op) != mode)
1071 #ifdef INSN_SCHEDULING
1072 /* On machines that have insn scheduling, we want all memory
1073 reference to be explicit, so outlaw paradoxical SUBREGs. */
1074 if (GET_CODE (SUBREG_REG (op)) == MEM
1075 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))))
1079 op = SUBREG_REG (op);
1080 code = GET_CODE (op);
1082 /* No longer needed, since (SUBREG (MEM...))
1083 will load the MEM into a reload reg in the MEM's own mode. */
1084 mode_altering_drug = 1;
1089 /* A register whose class is NO_REGS is not a general operand. */
1090 return (REGNO (op) >= FIRST_PSEUDO_REGISTER
1091 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS);
1095 register rtx y = XEXP (op, 0);
1097 if (! volatile_ok && MEM_VOLATILE_P (op))
1100 if (GET_CODE (y) == ADDRESSOF)
1103 /* Use the mem's mode, since it will be reloaded thus. */
1104 mode = GET_MODE (op);
1105 GO_IF_LEGITIMATE_ADDRESS (mode, y, win);
1108 /* Pretend this is an operand for now; we'll run force_operand
1109 on its replacement in fixup_var_refs_1. */
1110 if (code == ADDRESSOF)
1116 if (mode_altering_drug)
1117 return ! mode_dependent_address_p (XEXP (op, 0));
1121 /* Return 1 if OP is a valid memory address for a memory reference
1124 The main use of this function is as a predicate in match_operand
1125 expressions in the machine description. */
1128 address_operand (op, mode)
1130 enum machine_mode mode;
1132 return memory_address_p (mode, op);
1135 /* Return 1 if OP is a register reference of mode MODE.
1136 If MODE is VOIDmode, accept a register in any mode.
1138 The main use of this function is as a predicate in match_operand
1139 expressions in the machine description.
1141 As a special exception, registers whose class is NO_REGS are
1142 not accepted by `register_operand'. The reason for this change
1143 is to allow the representation of special architecture artifacts
1144 (such as a condition code register) without extending the rtl
1145 definitions. Since registers of class NO_REGS cannot be used
1146 as registers in any case where register classes are examined,
1147 it is most consistent to keep this function from accepting them. */
1150 register_operand (op, mode)
1152 enum machine_mode mode;
1154 if (GET_MODE (op) != mode && mode != VOIDmode)
1157 if (GET_CODE (op) == SUBREG)
1159 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1160 because it is guaranteed to be reloaded into one.
1161 Just make sure the MEM is valid in itself.
1162 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1163 but currently it does result from (SUBREG (REG)...) where the
1164 reg went on the stack.) */
1165 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1166 return general_operand (op, mode);
1168 #ifdef CLASS_CANNOT_CHANGE_MODE
1169 if (GET_CODE (SUBREG_REG (op)) == REG
1170 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER
1171 && (TEST_HARD_REG_BIT
1172 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
1173 REGNO (SUBREG_REG (op))))
1174 && CLASS_CANNOT_CHANGE_MODE_P (mode, GET_MODE (SUBREG_REG (op)))
1175 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_INT
1176 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op))) != MODE_COMPLEX_FLOAT)
1180 op = SUBREG_REG (op);
1183 /* If we have an ADDRESSOF, consider it valid since it will be
1184 converted into something that will not be a MEM. */
1185 if (GET_CODE (op) == ADDRESSOF)
1188 /* We don't consider registers whose class is NO_REGS
1189 to be a register operand. */
1190 return (GET_CODE (op) == REG
1191 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1192 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1195 /* Return 1 for a register in Pmode; ignore the tested mode. */
1198 pmode_register_operand (op, mode)
1200 enum machine_mode mode ATTRIBUTE_UNUSED;
1202 return register_operand (op, Pmode);
1205 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1206 or a hard register. */
1209 scratch_operand (op, mode)
1211 enum machine_mode mode;
1213 if (GET_MODE (op) != mode && mode != VOIDmode)
1216 return (GET_CODE (op) == SCRATCH
1217 || (GET_CODE (op) == REG
1218 && REGNO (op) < FIRST_PSEUDO_REGISTER));
1221 /* Return 1 if OP is a valid immediate operand for mode MODE.
1223 The main use of this function is as a predicate in match_operand
1224 expressions in the machine description. */
1227 immediate_operand (op, mode)
1229 enum machine_mode mode;
1231 /* Don't accept CONST_INT or anything similar
1232 if the caller wants something floating. */
1233 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1234 && GET_MODE_CLASS (mode) != MODE_INT
1235 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1238 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
1239 result in 0/1. It seems a safe assumption that this is
1240 in range for everyone. */
1241 if (GET_CODE (op) == CONSTANT_P_RTX)
1244 return (CONSTANT_P (op)
1245 && (GET_MODE (op) == mode || mode == VOIDmode
1246 || GET_MODE (op) == VOIDmode)
1247 #ifdef LEGITIMATE_PIC_OPERAND_P
1248 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1250 && LEGITIMATE_CONSTANT_P (op));
1253 /* Returns 1 if OP is an operand that is a CONST_INT. */
1256 const_int_operand (op, mode)
1258 enum machine_mode mode ATTRIBUTE_UNUSED;
1260 return GET_CODE (op) == CONST_INT;
1263 /* Returns 1 if OP is an operand that is a constant integer or constant
1264 floating-point number. */
1267 const_double_operand (op, mode)
1269 enum machine_mode mode;
1271 /* Don't accept CONST_INT or anything similar
1272 if the caller wants something floating. */
1273 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1274 && GET_MODE_CLASS (mode) != MODE_INT
1275 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1278 return ((GET_CODE (op) == CONST_DOUBLE || GET_CODE (op) == CONST_INT)
1279 && (mode == VOIDmode || GET_MODE (op) == mode
1280 || GET_MODE (op) == VOIDmode));
1283 /* Return 1 if OP is a general operand that is not an immediate operand. */
1286 nonimmediate_operand (op, mode)
1288 enum machine_mode mode;
1290 return (general_operand (op, mode) && ! CONSTANT_P (op));
1293 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1296 nonmemory_operand (op, mode)
1298 enum machine_mode mode;
1300 if (CONSTANT_P (op))
1302 /* Don't accept CONST_INT or anything similar
1303 if the caller wants something floating. */
1304 if (GET_MODE (op) == VOIDmode && mode != VOIDmode
1305 && GET_MODE_CLASS (mode) != MODE_INT
1306 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT)
1309 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode
1310 || mode == VOIDmode)
1311 #ifdef LEGITIMATE_PIC_OPERAND_P
1312 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1314 && LEGITIMATE_CONSTANT_P (op));
1317 if (GET_MODE (op) != mode && mode != VOIDmode)
1320 if (GET_CODE (op) == SUBREG)
1322 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1323 because it is guaranteed to be reloaded into one.
1324 Just make sure the MEM is valid in itself.
1325 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1326 but currently it does result from (SUBREG (REG)...) where the
1327 reg went on the stack.) */
1328 if (! reload_completed && GET_CODE (SUBREG_REG (op)) == MEM)
1329 return general_operand (op, mode);
1330 op = SUBREG_REG (op);
1333 /* We don't consider registers whose class is NO_REGS
1334 to be a register operand. */
1335 return (GET_CODE (op) == REG
1336 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
1337 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
1340 /* Return 1 if OP is a valid operand that stands for pushing a
1341 value of mode MODE onto the stack.
1343 The main use of this function is as a predicate in match_operand
1344 expressions in the machine description. */
1347 push_operand (op, mode)
1349 enum machine_mode mode;
1351 unsigned int rounded_size = GET_MODE_SIZE (mode);
1353 #ifdef PUSH_ROUNDING
1354 rounded_size = PUSH_ROUNDING (rounded_size);
1357 if (GET_CODE (op) != MEM)
1360 if (mode != VOIDmode && GET_MODE (op) != mode)
1365 if (rounded_size == GET_MODE_SIZE (mode))
1367 if (GET_CODE (op) != STACK_PUSH_CODE)
1372 if (GET_CODE (op) != PRE_MODIFY
1373 || GET_CODE (XEXP (op, 1)) != PLUS
1374 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0)
1375 || GET_CODE (XEXP (XEXP (op, 1), 1)) != CONST_INT
1376 #ifdef STACK_GROWS_DOWNWARD
1377 || INTVAL (XEXP (XEXP (op, 1), 1)) != - (int) rounded_size
1379 || INTVAL (XEXP (XEXP (op, 1), 1)) != rounded_size
1385 return XEXP (op, 0) == stack_pointer_rtx;
1388 /* Return 1 if OP is a valid operand that stands for popping a
1389 value of mode MODE off the stack.
1391 The main use of this function is as a predicate in match_operand
1392 expressions in the machine description. */
1395 pop_operand (op, mode)
1397 enum machine_mode mode;
1399 if (GET_CODE (op) != MEM)
1402 if (mode != VOIDmode && GET_MODE (op) != mode)
1407 if (GET_CODE (op) != STACK_POP_CODE)
1410 return XEXP (op, 0) == stack_pointer_rtx;
1413 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1416 memory_address_p (mode, addr)
1417 enum machine_mode mode ATTRIBUTE_UNUSED;
1420 if (GET_CODE (addr) == ADDRESSOF)
1423 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win);
1430 /* Return 1 if OP is a valid memory reference with mode MODE,
1431 including a valid address.
1433 The main use of this function is as a predicate in match_operand
1434 expressions in the machine description. */
1437 memory_operand (op, mode)
1439 enum machine_mode mode;
1443 if (! reload_completed)
1444 /* Note that no SUBREG is a memory operand before end of reload pass,
1445 because (SUBREG (MEM...)) forces reloading into a register. */
1446 return GET_CODE (op) == MEM && general_operand (op, mode);
1448 if (mode != VOIDmode && GET_MODE (op) != mode)
1452 if (GET_CODE (inner) == SUBREG)
1453 inner = SUBREG_REG (inner);
1455 return (GET_CODE (inner) == MEM && general_operand (op, mode));
1458 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1459 that is, a memory reference whose address is a general_operand. */
1462 indirect_operand (op, mode)
1464 enum machine_mode mode;
1466 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1467 if (! reload_completed
1468 && GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == MEM)
1470 register int offset = SUBREG_WORD (op) * UNITS_PER_WORD;
1471 rtx inner = SUBREG_REG (op);
1473 if (BYTES_BIG_ENDIAN)
1474 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (op)))
1475 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (inner))));
1477 if (mode != VOIDmode && GET_MODE (op) != mode)
1480 /* The only way that we can have a general_operand as the resulting
1481 address is if OFFSET is zero and the address already is an operand
1482 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1485 return ((offset == 0 && general_operand (XEXP (inner, 0), Pmode))
1486 || (GET_CODE (XEXP (inner, 0)) == PLUS
1487 && GET_CODE (XEXP (XEXP (inner, 0), 1)) == CONST_INT
1488 && INTVAL (XEXP (XEXP (inner, 0), 1)) == -offset
1489 && general_operand (XEXP (XEXP (inner, 0), 0), Pmode)));
1492 return (GET_CODE (op) == MEM
1493 && memory_operand (op, mode)
1494 && general_operand (XEXP (op, 0), Pmode));
1497 /* Return 1 if this is a comparison operator. This allows the use of
1498 MATCH_OPERATOR to recognize all the branch insns. */
1501 comparison_operator (op, mode)
1503 enum machine_mode mode;
1505 return ((mode == VOIDmode || GET_MODE (op) == mode)
1506 && GET_RTX_CLASS (GET_CODE (op)) == '<');
1509 /* If BODY is an insn body that uses ASM_OPERANDS,
1510 return the number of operands (both input and output) in the insn.
1511 Otherwise return -1. */
1514 asm_noperands (body)
1517 switch (GET_CODE (body))
1520 /* No output operands: return number of input operands. */
1521 return ASM_OPERANDS_INPUT_LENGTH (body);
1523 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1524 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1525 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body)) + 1;
1529 if (GET_CODE (XVECEXP (body, 0, 0)) == SET
1530 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
1532 /* Multiple output operands, or 1 output plus some clobbers:
1533 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1537 /* Count backwards through CLOBBERs to determine number of SETs. */
1538 for (i = XVECLEN (body, 0); i > 0; i--)
1540 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET)
1542 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER)
1546 /* N_SETS is now number of output operands. */
1549 /* Verify that all the SETs we have
1550 came from a single original asm_operands insn
1551 (so that invalid combinations are blocked). */
1552 for (i = 0; i < n_sets; i++)
1554 rtx elt = XVECEXP (body, 0, i);
1555 if (GET_CODE (elt) != SET)
1557 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS)
1559 /* If these ASM_OPERANDS rtx's came from different original insns
1560 then they aren't allowed together. */
1561 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt))
1562 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body, 0, 0))))
1565 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body, 0, 0)))
1568 else if (GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1570 /* 0 outputs, but some clobbers:
1571 body is [(asm_operands ...) (clobber (reg ...))...]. */
1574 /* Make sure all the other parallel things really are clobbers. */
1575 for (i = XVECLEN (body, 0) - 1; i > 0; i--)
1576 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER)
1579 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body, 0, 0));
1588 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1589 copy its operands (both input and output) into the vector OPERANDS,
1590 the locations of the operands within the insn into the vector OPERAND_LOCS,
1591 and the constraints for the operands into CONSTRAINTS.
1592 Write the modes of the operands into MODES.
1593 Return the assembler-template.
1595 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1596 we don't store that info. */
1599 decode_asm_operands (body, operands, operand_locs, constraints, modes)
1603 const char **constraints;
1604 enum machine_mode *modes;
1608 const char *template = 0;
1610 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
1612 rtx asmop = SET_SRC (body);
1613 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1615 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop) + 1;
1617 for (i = 1; i < noperands; i++)
1620 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i - 1);
1622 operands[i] = ASM_OPERANDS_INPUT (asmop, i - 1);
1624 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i - 1);
1626 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i - 1);
1629 /* The output is in the SET.
1630 Its constraint is in the ASM_OPERANDS itself. */
1632 operands[0] = SET_DEST (body);
1634 operand_locs[0] = &SET_DEST (body);
1636 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop);
1638 modes[0] = GET_MODE (SET_DEST (body));
1639 template = ASM_OPERANDS_TEMPLATE (asmop);
1641 else if (GET_CODE (body) == ASM_OPERANDS)
1644 /* No output operands: BODY is (asm_operands ....). */
1646 noperands = ASM_OPERANDS_INPUT_LENGTH (asmop);
1648 /* The input operands are found in the 1st element vector. */
1649 /* Constraints for inputs are in the 2nd element vector. */
1650 for (i = 0; i < noperands; i++)
1653 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1655 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1657 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1659 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1661 template = ASM_OPERANDS_TEMPLATE (asmop);
1663 else if (GET_CODE (body) == PARALLEL
1664 && GET_CODE (XVECEXP (body, 0, 0)) == SET)
1666 rtx asmop = SET_SRC (XVECEXP (body, 0, 0));
1667 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */
1668 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1669 int nout = 0; /* Does not include CLOBBERs. */
1671 /* At least one output, plus some CLOBBERs. */
1673 /* The outputs are in the SETs.
1674 Their constraints are in the ASM_OPERANDS itself. */
1675 for (i = 0; i < nparallel; i++)
1677 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER)
1678 break; /* Past last SET */
1681 operands[i] = SET_DEST (XVECEXP (body, 0, i));
1683 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i));
1685 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1);
1687 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i)));
1691 for (i = 0; i < nin; i++)
1694 operand_locs[i + nout] = &ASM_OPERANDS_INPUT (asmop, i);
1696 operands[i + nout] = ASM_OPERANDS_INPUT (asmop, i);
1698 constraints[i + nout] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1700 modes[i + nout] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1703 template = ASM_OPERANDS_TEMPLATE (asmop);
1705 else if (GET_CODE (body) == PARALLEL
1706 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
1708 /* No outputs, but some CLOBBERs. */
1710 rtx asmop = XVECEXP (body, 0, 0);
1711 int nin = ASM_OPERANDS_INPUT_LENGTH (asmop);
1713 for (i = 0; i < nin; i++)
1716 operand_locs[i] = &ASM_OPERANDS_INPUT (asmop, i);
1718 operands[i] = ASM_OPERANDS_INPUT (asmop, i);
1720 constraints[i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i);
1722 modes[i] = ASM_OPERANDS_INPUT_MODE (asmop, i);
1725 template = ASM_OPERANDS_TEMPLATE (asmop);
1731 /* Check if an asm_operand matches it's constraints.
1732 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1735 asm_operand_ok (op, constraint)
1737 const char *constraint;
1741 /* Use constrain_operands after reload. */
1742 if (reload_completed)
1747 char c = *constraint++;
1761 case '0': case '1': case '2': case '3': case '4':
1762 case '5': case '6': case '7': case '8': case '9':
1763 /* For best results, our caller should have given us the
1764 proper matching constraint, but we can't actually fail
1765 the check if they didn't. Indicate that results are
1771 if (address_operand (op, VOIDmode))
1776 case 'V': /* non-offsettable */
1777 if (memory_operand (op, VOIDmode))
1781 case 'o': /* offsettable */
1782 if (offsettable_nonstrict_memref_p (op))
1787 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1788 excepting those that expand_call created. Further, on some
1789 machines which do not have generalized auto inc/dec, an inc/dec
1790 is not a memory_operand.
1792 Match any memory and hope things are resolved after reload. */
1794 if (GET_CODE (op) == MEM
1796 || GET_CODE (XEXP (op, 0)) == PRE_DEC
1797 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1802 if (GET_CODE (op) == MEM
1804 || GET_CODE (XEXP (op, 0)) == PRE_INC
1805 || GET_CODE (XEXP (op, 0)) == POST_INC))
1810 #ifndef REAL_ARITHMETIC
1811 /* Match any floating double constant, but only if
1812 we can examine the bits of it reliably. */
1813 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1814 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1815 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1821 if (GET_CODE (op) == CONST_DOUBLE)
1826 if (GET_CODE (op) == CONST_DOUBLE
1827 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'G'))
1831 if (GET_CODE (op) == CONST_DOUBLE
1832 && CONST_DOUBLE_OK_FOR_LETTER_P (op, 'H'))
1837 if (GET_CODE (op) == CONST_INT
1838 || (GET_CODE (op) == CONST_DOUBLE
1839 && GET_MODE (op) == VOIDmode))
1845 #ifdef LEGITIMATE_PIC_OPERAND_P
1846 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1853 if (GET_CODE (op) == CONST_INT
1854 || (GET_CODE (op) == CONST_DOUBLE
1855 && GET_MODE (op) == VOIDmode))
1860 if (GET_CODE (op) == CONST_INT
1861 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'))
1865 if (GET_CODE (op) == CONST_INT
1866 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'J'))
1870 if (GET_CODE (op) == CONST_INT
1871 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'K'))
1875 if (GET_CODE (op) == CONST_INT
1876 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'))
1880 if (GET_CODE (op) == CONST_INT
1881 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'M'))
1885 if (GET_CODE (op) == CONST_INT
1886 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'N'))
1890 if (GET_CODE (op) == CONST_INT
1891 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'))
1895 if (GET_CODE (op) == CONST_INT
1896 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'))
1904 if (general_operand (op, VOIDmode))
1909 /* For all other letters, we first check for a register class,
1910 otherwise it is an EXTRA_CONSTRAINT. */
1911 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1914 if (GET_MODE (op) == BLKmode)
1916 if (register_operand (op, VOIDmode))
1919 #ifdef EXTRA_CONSTRAINT
1920 if (EXTRA_CONSTRAINT (op, c))
1930 /* Given an rtx *P, if it is a sum containing an integer constant term,
1931 return the location (type rtx *) of the pointer to that constant term.
1932 Otherwise, return a null pointer. */
1935 find_constant_term_loc (p)
1939 register enum rtx_code code = GET_CODE (*p);
1941 /* If *P IS such a constant term, P is its location. */
1943 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF
1947 /* Otherwise, if not a sum, it has no constant term. */
1949 if (GET_CODE (*p) != PLUS)
1952 /* If one of the summands is constant, return its location. */
1954 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0))
1955 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1)))
1958 /* Otherwise, check each summand for containing a constant term. */
1960 if (XEXP (*p, 0) != 0)
1962 tem = find_constant_term_loc (&XEXP (*p, 0));
1967 if (XEXP (*p, 1) != 0)
1969 tem = find_constant_term_loc (&XEXP (*p, 1));
1977 /* Return 1 if OP is a memory reference
1978 whose address contains no side effects
1979 and remains valid after the addition
1980 of a positive integer less than the
1981 size of the object being referenced.
1983 We assume that the original address is valid and do not check it.
1985 This uses strict_memory_address_p as a subroutine, so
1986 don't use it before reload. */
1989 offsettable_memref_p (op)
1992 return ((GET_CODE (op) == MEM)
1993 && offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)));
1996 /* Similar, but don't require a strictly valid mem ref:
1997 consider pseudo-regs valid as index or base regs. */
2000 offsettable_nonstrict_memref_p (op)
2003 return ((GET_CODE (op) == MEM)
2004 && offsettable_address_p (0, GET_MODE (op), XEXP (op, 0)));
2007 /* Return 1 if Y is a memory address which contains no side effects
2008 and would remain valid after the addition of a positive integer
2009 less than the size of that mode.
2011 We assume that the original address is valid and do not check it.
2012 We do check that it is valid for narrower modes.
2014 If STRICTP is nonzero, we require a strictly valid address,
2015 for the sake of use in reload.c. */
2018 offsettable_address_p (strictp, mode, y)
2020 enum machine_mode mode;
2023 register enum rtx_code ycode = GET_CODE (y);
2027 int (*addressp) PARAMS ((enum machine_mode, rtx)) =
2028 (strictp ? strict_memory_address_p : memory_address_p);
2029 unsigned int mode_sz = GET_MODE_SIZE (mode);
2031 if (CONSTANT_ADDRESS_P (y))
2034 /* Adjusting an offsettable address involves changing to a narrower mode.
2035 Make sure that's OK. */
2037 if (mode_dependent_address_p (y))
2040 /* ??? How much offset does an offsettable BLKmode reference need?
2041 Clearly that depends on the situation in which it's being used.
2042 However, the current situation in which we test 0xffffffff is
2043 less than ideal. Caveat user. */
2045 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT;
2047 /* If the expression contains a constant term,
2048 see if it remains valid when max possible offset is added. */
2050 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1)))
2055 *y2 = plus_constant (*y2, mode_sz - 1);
2056 /* Use QImode because an odd displacement may be automatically invalid
2057 for any wider mode. But it should be valid for a single byte. */
2058 good = (*addressp) (QImode, y);
2060 /* In any case, restore old contents of memory. */
2065 if (GET_RTX_CLASS (ycode) == 'a')
2068 /* The offset added here is chosen as the maximum offset that
2069 any instruction could need to add when operating on something
2070 of the specified mode. We assume that if Y and Y+c are
2071 valid addresses then so is Y+d for all 0<d<c. */
2073 z = plus_constant_for_output (y, mode_sz - 1);
2075 /* Use QImode because an odd displacement may be automatically invalid
2076 for any wider mode. But it should be valid for a single byte. */
2077 return (*addressp) (QImode, z);
2080 /* Return 1 if ADDR is an address-expression whose effect depends
2081 on the mode of the memory reference it is used in.
2083 Autoincrement addressing is a typical example of mode-dependence
2084 because the amount of the increment depends on the mode. */
2087 mode_dependent_address_p (addr)
2088 rtx addr ATTRIBUTE_UNUSED; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
2090 GO_IF_MODE_DEPENDENT_ADDRESS (addr, win);
2092 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
2093 win: ATTRIBUTE_UNUSED_LABEL
2097 /* Return 1 if OP is a general operand
2098 other than a memory ref with a mode dependent address. */
2101 mode_independent_operand (op, mode)
2102 enum machine_mode mode;
2107 if (! general_operand (op, mode))
2110 if (GET_CODE (op) != MEM)
2113 addr = XEXP (op, 0);
2114 GO_IF_MODE_DEPENDENT_ADDRESS (addr, lose);
2116 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
2117 lose: ATTRIBUTE_UNUSED_LABEL
2121 /* Given an operand OP that is a valid memory reference which
2122 satisfies offsettable_memref_p, return a new memory reference whose
2123 address has been adjusted by OFFSET. OFFSET should be positive and
2124 less than the size of the object referenced. */
2127 adj_offsettable_operand (op, offset)
2131 register enum rtx_code code = GET_CODE (op);
2135 register rtx y = XEXP (op, 0);
2138 if (CONSTANT_ADDRESS_P (y))
2140 new = gen_rtx_MEM (GET_MODE (op),
2141 plus_constant_for_output (y, offset));
2142 MEM_COPY_ATTRIBUTES (new, op);
2146 if (GET_CODE (y) == PLUS)
2149 register rtx *const_loc;
2153 const_loc = find_constant_term_loc (&z);
2156 *const_loc = plus_constant_for_output (*const_loc, offset);
2161 new = gen_rtx_MEM (GET_MODE (op), plus_constant_for_output (y, offset));
2162 MEM_COPY_ATTRIBUTES (new, op);
2168 /* Like extract_insn, but save insn extracted and don't extract again, when
2169 called again for the same insn expecting that recog_data still contain the
2170 valid information. This is used primary by gen_attr infrastructure that
2171 often does extract insn again and again. */
2173 extract_insn_cached (insn)
2176 if (recog_data.insn == insn && INSN_CODE (insn) >= 0)
2178 extract_insn (insn);
2179 recog_data.insn = insn;
2181 /* Do cached extract_insn, constrain_operand and complain about failures.
2182 Used by insn_attrtab. */
2184 extract_constrain_insn_cached (insn)
2187 extract_insn_cached (insn);
2188 if (which_alternative == -1
2189 && !constrain_operands (reload_completed))
2190 fatal_insn_not_found (insn);
2192 /* Do cached constrain_operand and complain about failures. */
2194 constrain_operands_cached (strict)
2197 if (which_alternative == -1)
2198 return constrain_operands (strict);
2203 /* Analyze INSN and fill in recog_data. */
2212 rtx body = PATTERN (insn);
2214 recog_data.insn = NULL;
2215 recog_data.n_operands = 0;
2216 recog_data.n_alternatives = 0;
2217 recog_data.n_dups = 0;
2218 which_alternative = -1;
2220 switch (GET_CODE (body))
2230 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS)
2235 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET
2236 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS)
2237 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS)
2243 recog_data.n_operands = noperands = asm_noperands (body);
2246 /* This insn is an `asm' with operands. */
2248 /* expand_asm_operands makes sure there aren't too many operands. */
2249 if (noperands > MAX_RECOG_OPERANDS)
2252 /* Now get the operand values and constraints out of the insn. */
2253 decode_asm_operands (body, recog_data.operand,
2254 recog_data.operand_loc,
2255 recog_data.constraints,
2256 recog_data.operand_mode);
2259 const char *p = recog_data.constraints[0];
2260 recog_data.n_alternatives = 1;
2262 recog_data.n_alternatives += (*p++ == ',');
2266 fatal_insn_not_found (insn);
2270 /* Ordinary insn: recognize it, get the operands via insn_extract
2271 and get the constraints. */
2273 icode = recog_memoized (insn);
2275 fatal_insn_not_found (insn);
2277 recog_data.n_operands = noperands = insn_data[icode].n_operands;
2278 recog_data.n_alternatives = insn_data[icode].n_alternatives;
2279 recog_data.n_dups = insn_data[icode].n_dups;
2281 insn_extract (insn);
2283 for (i = 0; i < noperands; i++)
2285 recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
2286 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
2287 /* VOIDmode match_operands gets mode from their real operand. */
2288 if (recog_data.operand_mode[i] == VOIDmode)
2289 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]);
2292 for (i = 0; i < noperands; i++)
2293 recog_data.operand_type[i]
2294 = (recog_data.constraints[i][0] == '=' ? OP_OUT
2295 : recog_data.constraints[i][0] == '+' ? OP_INOUT
2298 if (recog_data.n_alternatives > MAX_RECOG_ALTERNATIVES)
2302 /* After calling extract_insn, you can use this function to extract some
2303 information from the constraint strings into a more usable form.
2304 The collected data is stored in recog_op_alt. */
2306 preprocess_constraints ()
2310 memset (recog_op_alt, 0, sizeof recog_op_alt);
2311 for (i = 0; i < recog_data.n_operands; i++)
2314 struct operand_alternative *op_alt;
2315 const char *p = recog_data.constraints[i];
2317 op_alt = recog_op_alt[i];
2319 for (j = 0; j < recog_data.n_alternatives; j++)
2321 op_alt[j].class = NO_REGS;
2322 op_alt[j].constraint = p;
2323 op_alt[j].matches = -1;
2324 op_alt[j].matched = -1;
2326 if (*p == '\0' || *p == ',')
2328 op_alt[j].anything_ok = 1;
2338 while (c != ',' && c != '\0');
2339 if (c == ',' || c == '\0')
2344 case '=': case '+': case '*': case '%':
2345 case 'E': case 'F': case 'G': case 'H':
2346 case 's': case 'i': case 'n':
2347 case 'I': case 'J': case 'K': case 'L':
2348 case 'M': case 'N': case 'O': case 'P':
2349 /* These don't say anything we care about. */
2353 op_alt[j].reject += 6;
2356 op_alt[j].reject += 600;
2359 op_alt[j].earlyclobber = 1;
2362 case '0': case '1': case '2': case '3': case '4':
2363 case '5': case '6': case '7': case '8': case '9':
2364 op_alt[j].matches = c - '0';
2365 recog_op_alt[op_alt[j].matches][j].matched = i;
2369 op_alt[j].memory_ok = 1;
2372 op_alt[j].decmem_ok = 1;
2375 op_alt[j].incmem_ok = 1;
2378 op_alt[j].nonoffmem_ok = 1;
2381 op_alt[j].offmem_ok = 1;
2384 op_alt[j].anything_ok = 1;
2388 op_alt[j].is_address = 1;
2389 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) BASE_REG_CLASS];
2393 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) GENERAL_REGS];
2397 op_alt[j].class = reg_class_subunion[(int) op_alt[j].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
2405 /* Check the operands of an insn against the insn's operand constraints
2406 and return 1 if they are valid.
2407 The information about the insn's operands, constraints, operand modes
2408 etc. is obtained from the global variables set up by extract_insn.
2410 WHICH_ALTERNATIVE is set to a number which indicates which
2411 alternative of constraints was matched: 0 for the first alternative,
2412 1 for the next, etc.
2414 In addition, when two operands are match
2415 and it happens that the output operand is (reg) while the
2416 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2417 make the output operand look like the input.
2418 This is because the output operand is the one the template will print.
2420 This is used in final, just before printing the assembler code and by
2421 the routines that determine an insn's attribute.
2423 If STRICT is a positive non-zero value, it means that we have been
2424 called after reload has been completed. In that case, we must
2425 do all checks strictly. If it is zero, it means that we have been called
2426 before reload has completed. In that case, we first try to see if we can
2427 find an alternative that matches strictly. If not, we try again, this
2428 time assuming that reload will fix up the insn. This provides a "best
2429 guess" for the alternative and is used to compute attributes of insns prior
2430 to reload. A negative value of STRICT is used for this internal call. */
2438 constrain_operands (strict)
2441 const char *constraints[MAX_RECOG_OPERANDS];
2442 int matching_operands[MAX_RECOG_OPERANDS];
2443 int earlyclobber[MAX_RECOG_OPERANDS];
2446 struct funny_match funny_match[MAX_RECOG_OPERANDS];
2447 int funny_match_index;
2449 which_alternative = 0;
2450 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0)
2453 for (c = 0; c < recog_data.n_operands; c++)
2455 constraints[c] = recog_data.constraints[c];
2456 matching_operands[c] = -1;
2463 funny_match_index = 0;
2465 for (opno = 0; opno < recog_data.n_operands; opno++)
2467 register rtx op = recog_data.operand[opno];
2468 enum machine_mode mode = GET_MODE (op);
2469 register const char *p = constraints[opno];
2474 earlyclobber[opno] = 0;
2476 /* A unary operator may be accepted by the predicate, but it
2477 is irrelevant for matching constraints. */
2478 if (GET_RTX_CLASS (GET_CODE (op)) == '1')
2481 if (GET_CODE (op) == SUBREG)
2483 if (GET_CODE (SUBREG_REG (op)) == REG
2484 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
2485 offset = SUBREG_WORD (op);
2486 op = SUBREG_REG (op);
2489 /* An empty constraint or empty alternative
2490 allows anything which matched the pattern. */
2491 if (*p == 0 || *p == ',')
2494 while (*p && (c = *p++) != ',')
2497 case '?': case '!': case '*': case '%':
2502 /* Ignore rest of this alternative as far as
2503 constraint checking is concerned. */
2504 while (*p && *p != ',')
2509 earlyclobber[opno] = 1;
2512 case '0': case '1': case '2': case '3': case '4':
2513 case '5': case '6': case '7': case '8': case '9':
2515 /* This operand must be the same as a previous one.
2516 This kind of constraint is used for instructions such
2517 as add when they take only two operands.
2519 Note that the lower-numbered operand is passed first.
2521 If we are not testing strictly, assume that this constraint
2522 will be satisfied. */
2527 rtx op1 = recog_data.operand[c - '0'];
2528 rtx op2 = recog_data.operand[opno];
2530 /* A unary operator may be accepted by the predicate,
2531 but it is irrelevant for matching constraints. */
2532 if (GET_RTX_CLASS (GET_CODE (op1)) == '1')
2533 op1 = XEXP (op1, 0);
2534 if (GET_RTX_CLASS (GET_CODE (op2)) == '1')
2535 op2 = XEXP (op2, 0);
2537 val = operands_match_p (op1, op2);
2540 matching_operands[opno] = c - '0';
2541 matching_operands[c - '0'] = opno;
2545 /* If output is *x and input is *--x,
2546 arrange later to change the output to *--x as well,
2547 since the output op is the one that will be printed. */
2548 if (val == 2 && strict > 0)
2550 funny_match[funny_match_index].this = opno;
2551 funny_match[funny_match_index++].other = c - '0';
2556 /* p is used for address_operands. When we are called by
2557 gen_reload, no one will have checked that the address is
2558 strictly valid, i.e., that all pseudos requiring hard regs
2559 have gotten them. */
2561 || (strict_memory_address_p (recog_data.operand_mode[opno],
2566 /* No need to check general_operand again;
2567 it was done in insn-recog.c. */
2569 /* Anything goes unless it is a REG and really has a hard reg
2570 but the hard reg is not in the class GENERAL_REGS. */
2572 || GENERAL_REGS == ALL_REGS
2573 || GET_CODE (op) != REG
2574 || (reload_in_progress
2575 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2576 || reg_fits_class_p (op, GENERAL_REGS, offset, mode))
2581 /* This is used for a MATCH_SCRATCH in the cases when
2582 we don't actually need anything. So anything goes
2588 if (GET_CODE (op) == MEM
2589 /* Before reload, accept what reload can turn into mem. */
2590 || (strict < 0 && CONSTANT_P (op))
2591 /* During reload, accept a pseudo */
2592 || (reload_in_progress && GET_CODE (op) == REG
2593 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2598 if (GET_CODE (op) == MEM
2599 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
2600 || GET_CODE (XEXP (op, 0)) == POST_DEC))
2605 if (GET_CODE (op) == MEM
2606 && (GET_CODE (XEXP (op, 0)) == PRE_INC
2607 || GET_CODE (XEXP (op, 0)) == POST_INC))
2612 #ifndef REAL_ARITHMETIC
2613 /* Match any CONST_DOUBLE, but only if
2614 we can examine the bits of it reliably. */
2615 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2616 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
2617 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
2620 if (GET_CODE (op) == CONST_DOUBLE)
2625 if (GET_CODE (op) == CONST_DOUBLE)
2631 if (GET_CODE (op) == CONST_DOUBLE
2632 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
2637 if (GET_CODE (op) == CONST_INT
2638 || (GET_CODE (op) == CONST_DOUBLE
2639 && GET_MODE (op) == VOIDmode))
2642 if (CONSTANT_P (op))
2647 if (GET_CODE (op) == CONST_INT
2648 || (GET_CODE (op) == CONST_DOUBLE
2649 && GET_MODE (op) == VOIDmode))
2661 if (GET_CODE (op) == CONST_INT
2662 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
2667 if (GET_CODE (op) == MEM
2668 && ((strict > 0 && ! offsettable_memref_p (op))
2670 && !(CONSTANT_P (op) || GET_CODE (op) == MEM))
2671 || (reload_in_progress
2672 && !(GET_CODE (op) == REG
2673 && REGNO (op) >= FIRST_PSEUDO_REGISTER))))
2678 if ((strict > 0 && offsettable_memref_p (op))
2679 || (strict == 0 && offsettable_nonstrict_memref_p (op))
2680 /* Before reload, accept what reload can handle. */
2682 && (CONSTANT_P (op) || GET_CODE (op) == MEM))
2683 /* During reload, accept a pseudo */
2684 || (reload_in_progress && GET_CODE (op) == REG
2685 && REGNO (op) >= FIRST_PSEUDO_REGISTER))
2691 enum reg_class class;
2693 class = (c == 'r' ? GENERAL_REGS : REG_CLASS_FROM_LETTER (c));
2694 if (class != NO_REGS)
2698 && GET_CODE (op) == REG
2699 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
2700 || (strict == 0 && GET_CODE (op) == SCRATCH)
2701 || (GET_CODE (op) == REG
2702 && reg_fits_class_p (op, class, offset, mode)))
2705 #ifdef EXTRA_CONSTRAINT
2706 else if (EXTRA_CONSTRAINT (op, c))
2713 constraints[opno] = p;
2714 /* If this operand did not win somehow,
2715 this alternative loses. */
2719 /* This alternative won; the operands are ok.
2720 Change whichever operands this alternative says to change. */
2725 /* See if any earlyclobber operand conflicts with some other
2729 for (eopno = 0; eopno < recog_data.n_operands; eopno++)
2730 /* Ignore earlyclobber operands now in memory,
2731 because we would often report failure when we have
2732 two memory operands, one of which was formerly a REG. */
2733 if (earlyclobber[eopno]
2734 && GET_CODE (recog_data.operand[eopno]) == REG)
2735 for (opno = 0; opno < recog_data.n_operands; opno++)
2736 if ((GET_CODE (recog_data.operand[opno]) == MEM
2737 || recog_data.operand_type[opno] != OP_OUT)
2739 /* Ignore things like match_operator operands. */
2740 && *recog_data.constraints[opno] != 0
2741 && ! (matching_operands[opno] == eopno
2742 && operands_match_p (recog_data.operand[opno],
2743 recog_data.operand[eopno]))
2744 && ! safe_from_earlyclobber (recog_data.operand[opno],
2745 recog_data.operand[eopno]))
2750 while (--funny_match_index >= 0)
2752 recog_data.operand[funny_match[funny_match_index].other]
2753 = recog_data.operand[funny_match[funny_match_index].this];
2760 which_alternative++;
2762 while (which_alternative < recog_data.n_alternatives);
2764 which_alternative = -1;
2765 /* If we are about to reject this, but we are not to test strictly,
2766 try a very loose test. Only return failure if it fails also. */
2768 return constrain_operands (-1);
2773 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2774 is a hard reg in class CLASS when its regno is offset by OFFSET
2775 and changed to mode MODE.
2776 If REG occupies multiple hard regs, all of them must be in CLASS. */
2779 reg_fits_class_p (operand, class, offset, mode)
2781 register enum reg_class class;
2783 enum machine_mode mode;
2785 register int regno = REGNO (operand);
2786 if (regno < FIRST_PSEUDO_REGISTER
2787 && TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2792 for (sr = HARD_REGNO_NREGS (regno, mode) - 1;
2794 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) class],
2803 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2806 split_all_insns (upd_life)
2813 blocks = sbitmap_alloc (n_basic_blocks);
2814 sbitmap_zero (blocks);
2817 for (i = n_basic_blocks - 1; i >= 0; --i)
2819 basic_block bb = BASIC_BLOCK (i);
2822 for (insn = bb->head; insn ; insn = next)
2826 /* Can't use `next_real_insn' because that might go across
2827 CODE_LABELS and short-out basic blocks. */
2828 next = NEXT_INSN (insn);
2829 if (! INSN_P (insn))
2832 /* Don't split no-op move insns. These should silently
2833 disappear later in final. Splitting such insns would
2834 break the code that handles REG_NO_CONFLICT blocks. */
2836 else if ((set = single_set (insn)) != NULL
2837 && rtx_equal_p (SET_SRC (set), SET_DEST (set)))
2839 /* Nops get in the way while scheduling, so delete them
2840 now if register allocation has already been done. It
2841 is too risky to try to do this before register
2842 allocation, and there are unlikely to be very many
2843 nops then anyways. */
2844 if (reload_completed)
2846 PUT_CODE (insn, NOTE);
2847 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2848 NOTE_SOURCE_FILE (insn) = 0;
2853 /* Split insns here to get max fine-grain parallelism. */
2854 rtx first = PREV_INSN (insn);
2855 rtx last = try_split (PATTERN (insn), insn, 1);
2859 SET_BIT (blocks, i);
2862 /* try_split returns the NOTE that INSN became. */
2863 PUT_CODE (insn, NOTE);
2864 NOTE_SOURCE_FILE (insn) = 0;
2865 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
2867 /* ??? Coddle to md files that generate subregs in post-
2868 reload splitters instead of computing the proper
2870 if (reload_completed && first != last)
2872 first = NEXT_INSN (first);
2876 cleanup_subreg_operands (first);
2879 first = NEXT_INSN (first);
2883 if (insn == bb->end)
2891 if (insn == bb->end)
2895 /* ??? When we're called from just after reload, the CFG is in bad
2896 shape, and we may have fallen off the end. This could be fixed
2897 by having reload not try to delete unreachable code. Otherwise
2898 assert we found the end insn. */
2899 if (insn == NULL && upd_life)
2903 if (changed && upd_life)
2905 compute_bb_for_insn (get_max_uid ());
2906 count_or_remove_death_notes (blocks, 1);
2907 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
2910 sbitmap_free (blocks);
2913 #ifdef HAVE_peephole2
2914 struct peep2_insn_data
2920 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
2921 static int peep2_current;
2923 /* A non-insn marker indicating the last insn of the block.
2924 The live_before regset for this element is correct, indicating
2925 global_live_at_end for the block. */
2926 #define PEEP2_EOB pc_rtx
2928 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2929 does not exist. Used by the recognizer to find the next insn to match
2930 in a multi-insn pattern. */
2936 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2940 if (n >= MAX_INSNS_PER_PEEP2 + 1)
2941 n -= MAX_INSNS_PER_PEEP2 + 1;
2943 if (peep2_insn_data[n].insn == PEEP2_EOB)
2945 return peep2_insn_data[n].insn;
2948 /* Return true if REGNO is dead before the Nth non-note insn
2952 peep2_regno_dead_p (ofs, regno)
2956 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2959 ofs += peep2_current;
2960 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2961 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2963 if (peep2_insn_data[ofs].insn == NULL_RTX)
2966 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno);
2969 /* Similarly for a REG. */
2972 peep2_reg_dead_p (ofs, reg)
2978 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2981 ofs += peep2_current;
2982 if (ofs >= MAX_INSNS_PER_PEEP2 + 1)
2983 ofs -= MAX_INSNS_PER_PEEP2 + 1;
2985 if (peep2_insn_data[ofs].insn == NULL_RTX)
2988 regno = REGNO (reg);
2989 n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
2991 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno + n))
2996 /* Try to find a hard register of mode MODE, matching the register class in
2997 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2998 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2999 in which case the only condition is that the register must be available
3000 before CURRENT_INSN.
3001 Registers that already have bits set in REG_SET will not be considered.
3003 If an appropriate register is available, it will be returned and the
3004 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3008 peep2_find_free_register (from, to, class_str, mode, reg_set)
3010 const char *class_str;
3011 enum machine_mode mode;
3012 HARD_REG_SET *reg_set;
3014 static int search_ofs;
3015 enum reg_class class;
3019 if (from >= MAX_INSNS_PER_PEEP2 + 1 || to >= MAX_INSNS_PER_PEEP2 + 1)
3022 from += peep2_current;
3023 if (from >= MAX_INSNS_PER_PEEP2 + 1)
3024 from -= MAX_INSNS_PER_PEEP2 + 1;
3025 to += peep2_current;
3026 if (to >= MAX_INSNS_PER_PEEP2 + 1)
3027 to -= MAX_INSNS_PER_PEEP2 + 1;
3029 if (peep2_insn_data[from].insn == NULL_RTX)
3031 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
3035 HARD_REG_SET this_live;
3037 if (++from >= MAX_INSNS_PER_PEEP2 + 1)
3039 if (peep2_insn_data[from].insn == NULL_RTX)
3041 REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
3042 IOR_HARD_REG_SET (live, this_live);
3045 class = (class_str[0] == 'r' ? GENERAL_REGS
3046 : REG_CLASS_FROM_LETTER (class_str[0]));
3048 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3050 int raw_regno, regno, success, j;
3052 /* Distribute the free registers as much as possible. */
3053 raw_regno = search_ofs + i;
3054 if (raw_regno >= FIRST_PSEUDO_REGISTER)
3055 raw_regno -= FIRST_PSEUDO_REGISTER;
3056 #ifdef REG_ALLOC_ORDER
3057 regno = reg_alloc_order[raw_regno];
3062 /* Don't allocate fixed registers. */
3063 if (fixed_regs[regno])
3065 /* Make sure the register is of the right class. */
3066 if (! TEST_HARD_REG_BIT (reg_class_contents[class], regno))
3068 /* And can support the mode we need. */
3069 if (! HARD_REGNO_MODE_OK (regno, mode))
3071 /* And that we don't create an extra save/restore. */
3072 if (! call_used_regs[regno] && ! regs_ever_live[regno])
3074 /* And we don't clobber traceback for noreturn functions. */
3075 if ((regno == FRAME_POINTER_REGNUM || regno == HARD_FRAME_POINTER_REGNUM)
3076 && (! reload_completed || frame_pointer_needed))
3080 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
3082 if (TEST_HARD_REG_BIT (*reg_set, regno + j)
3083 || TEST_HARD_REG_BIT (live, regno + j))
3091 for (j = HARD_REGNO_NREGS (regno, mode) - 1; j >= 0; j--)
3092 SET_HARD_REG_BIT (*reg_set, regno + j);
3094 /* Start the next search with the next register. */
3095 if (++raw_regno >= FIRST_PSEUDO_REGISTER)
3097 search_ofs = raw_regno;
3099 return gen_rtx_REG (mode, regno);
3107 /* Perform the peephole2 optimization pass. */
3110 peephole2_optimize (dump_file)
3111 FILE *dump_file ATTRIBUTE_UNUSED;
3113 regset_head rs_heads[MAX_INSNS_PER_PEEP2 + 2];
3117 #ifdef HAVE_conditional_execution
3122 /* Initialize the regsets we're going to use. */
3123 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3124 peep2_insn_data[i].live_before = INITIALIZE_REG_SET (rs_heads[i]);
3125 live = INITIALIZE_REG_SET (rs_heads[i]);
3127 #ifdef HAVE_conditional_execution
3128 blocks = sbitmap_alloc (n_basic_blocks);
3129 sbitmap_zero (blocks);
3132 count_or_remove_death_notes (NULL, 1);
3135 for (b = n_basic_blocks - 1; b >= 0; --b)
3137 basic_block bb = BASIC_BLOCK (b);
3138 struct propagate_block_info *pbi;
3140 /* Indicate that all slots except the last holds invalid data. */
3141 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i)
3142 peep2_insn_data[i].insn = NULL_RTX;
3144 /* Indicate that the last slot contains live_after data. */
3145 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB;
3146 peep2_current = MAX_INSNS_PER_PEEP2;
3148 /* Start up propagation. */
3149 COPY_REG_SET (live, bb->global_live_at_end);
3150 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
3152 #ifdef HAVE_conditional_execution
3153 pbi = init_propagate_block_info (bb, live, NULL, NULL, 0);
3155 pbi = init_propagate_block_info (bb, live, NULL, NULL, PROP_DEATH_NOTES);
3158 for (insn = bb->end; ; insn = prev)
3160 prev = PREV_INSN (insn);
3166 /* Record this insn. */
3167 if (--peep2_current < 0)
3168 peep2_current = MAX_INSNS_PER_PEEP2;
3169 peep2_insn_data[peep2_current].insn = insn;
3170 propagate_one_insn (pbi, insn);
3171 COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
3173 /* Match the peephole. */
3174 try = peephole2_insns (PATTERN (insn), insn, &match_len);
3177 i = match_len + peep2_current;
3178 if (i >= MAX_INSNS_PER_PEEP2 + 1)
3179 i -= MAX_INSNS_PER_PEEP2 + 1;
3181 /* Replace the old sequence with the new. */
3182 flow_delete_insn_chain (insn, peep2_insn_data[i].insn);
3183 try = emit_insn_after (try, prev);
3185 /* Adjust the basic block boundaries. */
3186 if (peep2_insn_data[i].insn == bb->end)
3188 if (insn == bb->head)
3189 bb->head = NEXT_INSN (prev);
3191 #ifdef HAVE_conditional_execution
3192 /* With conditional execution, we cannot back up the
3193 live information so easily, since the conditional
3194 death data structures are not so self-contained.
3195 So record that we've made a modification to this
3196 block and update life information at the end. */
3197 SET_BIT (blocks, b);
3200 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3201 peep2_insn_data[i].insn = NULL_RTX;
3202 peep2_insn_data[peep2_current].insn = PEEP2_EOB;
3204 /* Back up lifetime information past the end of the
3205 newly created sequence. */
3206 if (++i >= MAX_INSNS_PER_PEEP2 + 1)
3208 COPY_REG_SET (live, peep2_insn_data[i].live_before);
3210 /* Update life information for the new sequence. */
3216 i = MAX_INSNS_PER_PEEP2;
3217 peep2_insn_data[i].insn = try;
3218 propagate_one_insn (pbi, try);
3219 COPY_REG_SET (peep2_insn_data[i].live_before, live);
3221 try = PREV_INSN (try);
3223 while (try != prev);
3225 /* ??? Should verify that LIVE now matches what we
3226 had before the new sequence. */
3233 if (insn == bb->head)
3237 free_propagate_block_info (pbi);
3240 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
3241 FREE_REG_SET (peep2_insn_data[i].live_before);
3242 FREE_REG_SET (live);
3244 #ifdef HAVE_conditional_execution
3245 count_or_remove_death_notes (blocks, 1);
3246 update_life_info (blocks, UPDATE_LIFE_LOCAL, PROP_DEATH_NOTES);
3247 sbitmap_free (blocks);
3250 #endif /* HAVE_peephole2 */