1 /* Swing Modulo Scheduling implementation.
2 Copyright (C) 2004, 2005, 2006
3 Free Software Foundation, Inc.
4 Contributed by Ayal Zaks and Mustafa Hagog <zaks,mustafa@il.ibm.com>
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "insn-attr.h"
40 #include "sched-int.h"
42 #include "cfglayout.h"
51 #include "tree-pass.h"
53 #ifdef INSN_SCHEDULING
55 /* This file contains the implementation of the Swing Modulo Scheduler,
56 described in the following references:
57 [1] J. Llosa, A. Gonzalez, E. Ayguade, M. Valero., and J. Eckhardt.
58 Lifetime--sensitive modulo scheduling in a production environment.
59 IEEE Trans. on Comps., 50(3), March 2001
60 [2] J. Llosa, A. Gonzalez, E. Ayguade, and M. Valero.
61 Swing Modulo Scheduling: A Lifetime Sensitive Approach.
62 PACT '96 , pages 80-87, October 1996 (Boston - Massachusetts - USA).
64 The basic structure is:
65 1. Build a data-dependence graph (DDG) for each loop.
66 2. Use the DDG to order the insns of a loop (not in topological order
67 necessarily, but rather) trying to place each insn after all its
68 predecessors _or_ after all its successors.
69 3. Compute MII: a lower bound on the number of cycles to schedule the loop.
70 4. Use the ordering to perform list-scheduling of the loop:
71 1. Set II = MII. We will try to schedule the loop within II cycles.
72 2. Try to schedule the insns one by one according to the ordering.
73 For each insn compute an interval of cycles by considering already-
74 scheduled preds and succs (and associated latencies); try to place
75 the insn in the cycles of this window checking for potential
76 resource conflicts (using the DFA interface).
77 Note: this is different from the cycle-scheduling of schedule_insns;
78 here the insns are not scheduled monotonically top-down (nor bottom-
80 3. If failed in scheduling all insns - bump II++ and try again, unless
81 II reaches an upper bound MaxII, in which case report failure.
82 5. If we succeeded in scheduling the loop within II cycles, we now
83 generate prolog and epilog, decrease the counter of the loop, and
84 perform modulo variable expansion for live ranges that span more than
85 II cycles (i.e. use register copies to prevent a def from overwriting
86 itself before reaching the use).
90 /* This page defines partial-schedule structures and functions for
93 typedef struct partial_schedule *partial_schedule_ptr;
94 typedef struct ps_insn *ps_insn_ptr;
96 /* The minimum (absolute) cycle that a node of ps was scheduled in. */
97 #define PS_MIN_CYCLE(ps) (((partial_schedule_ptr)(ps))->min_cycle)
99 /* The maximum (absolute) cycle that a node of ps was scheduled in. */
100 #define PS_MAX_CYCLE(ps) (((partial_schedule_ptr)(ps))->max_cycle)
102 /* Perform signed modulo, always returning a non-negative value. */
103 #define SMODULO(x,y) ((x) % (y) < 0 ? ((x) % (y) + (y)) : (x) % (y))
105 /* The number of different iterations the nodes in ps span, assuming
106 the stage boundaries are placed efficiently. */
107 #define PS_STAGE_COUNT(ps) ((PS_MAX_CYCLE (ps) - PS_MIN_CYCLE (ps) \
108 + 1 + (ps)->ii - 1) / (ps)->ii)
110 /* A single instruction in the partial schedule. */
113 /* The corresponding DDG_NODE. */
116 /* The (absolute) cycle in which the PS instruction is scheduled.
117 Same as SCHED_TIME (node). */
120 /* The next/prev PS_INSN in the same row. */
121 ps_insn_ptr next_in_row,
124 /* The number of nodes in the same row that come after this node. */
128 /* Holds the partial schedule as an array of II rows. Each entry of the
129 array points to a linked list of PS_INSNs, which represents the
130 instructions that are scheduled for that row. */
131 struct partial_schedule
133 int ii; /* Number of rows in the partial schedule. */
134 int history; /* Threshold for conflict checking using DFA. */
136 /* rows[i] points to linked list of insns scheduled in row i (0<=i<ii). */
139 /* The earliest absolute cycle of an insn in the partial schedule. */
142 /* The latest absolute cycle of an insn in the partial schedule. */
145 ddg_ptr g; /* The DDG of the insns in the partial schedule. */
148 /* We use this to record all the register replacements we do in
149 the kernel so we can undo SMS if it is not profitable. */
150 struct undo_replace_buff_elem
155 struct undo_replace_buff_elem *next;
160 static partial_schedule_ptr create_partial_schedule (int ii, ddg_ptr, int history);
161 static void free_partial_schedule (partial_schedule_ptr);
162 static void reset_partial_schedule (partial_schedule_ptr, int new_ii);
163 void print_partial_schedule (partial_schedule_ptr, FILE *);
164 static int kernel_number_of_cycles (rtx first_insn, rtx last_insn);
165 static ps_insn_ptr ps_add_node_check_conflicts (partial_schedule_ptr,
166 ddg_node_ptr node, int cycle,
167 sbitmap must_precede,
168 sbitmap must_follow);
169 static void rotate_partial_schedule (partial_schedule_ptr, int);
170 void set_row_column_for_ps (partial_schedule_ptr);
171 static bool ps_unschedule_node (partial_schedule_ptr, ddg_node_ptr );
174 /* This page defines constants and structures for the modulo scheduling
177 /* As in haifa-sched.c: */
178 /* issue_rate is the number of insns that can be scheduled in the same
179 machine cycle. It can be defined in the config/mach/mach.h file,
180 otherwise we set it to 1. */
182 static int issue_rate;
184 static int sms_order_nodes (ddg_ptr, int, int * result);
185 static void set_node_sched_params (ddg_ptr);
186 static partial_schedule_ptr sms_schedule_by_order (ddg_ptr, int, int, int *);
187 static void permute_partial_schedule (partial_schedule_ptr ps, rtx last);
188 static void generate_prolog_epilog (partial_schedule_ptr ,struct loop * loop, rtx);
189 static void duplicate_insns_of_cycles (partial_schedule_ptr ps,
190 int from_stage, int to_stage,
193 #define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
194 #define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
195 #define SCHED_FIRST_REG_MOVE(x) \
196 (((node_sched_params_ptr)(x)->aux.info)->first_reg_move)
197 #define SCHED_NREG_MOVES(x) \
198 (((node_sched_params_ptr)(x)->aux.info)->nreg_moves)
199 #define SCHED_ROW(x) (((node_sched_params_ptr)(x)->aux.info)->row)
200 #define SCHED_STAGE(x) (((node_sched_params_ptr)(x)->aux.info)->stage)
201 #define SCHED_COLUMN(x) (((node_sched_params_ptr)(x)->aux.info)->column)
203 /* The scheduling parameters held for each node. */
204 typedef struct node_sched_params
206 int asap; /* A lower-bound on the absolute scheduling cycle. */
207 int time; /* The absolute scheduling cycle (time >= asap). */
209 /* The following field (first_reg_move) is a pointer to the first
210 register-move instruction added to handle the modulo-variable-expansion
211 of the register defined by this node. This register-move copies the
212 original register defined by the node. */
215 /* The number of register-move instructions added, immediately preceding
219 int row; /* Holds time % ii. */
220 int stage; /* Holds time / ii. */
222 /* The column of a node inside the ps. If nodes u, v are on the same row,
223 u will precede v if column (u) < column (v). */
225 } *node_sched_params_ptr;
228 /* The following three functions are copied from the current scheduler
229 code in order to use sched_analyze() for computing the dependencies.
230 They are used when initializing the sched_info structure. */
232 sms_print_insn (rtx insn, int aligned ATTRIBUTE_UNUSED)
236 sprintf (tmp, "i%4d", INSN_UID (insn));
241 compute_jump_reg_dependencies (rtx insn ATTRIBUTE_UNUSED,
242 regset cond_exec ATTRIBUTE_UNUSED,
243 regset used ATTRIBUTE_UNUSED,
244 regset set ATTRIBUTE_UNUSED)
248 static struct sched_info sms_sched_info =
257 compute_jump_reg_dependencies,
262 NULL, NULL, NULL, NULL, NULL,
263 #ifdef ENABLE_CHECKING
270 /* Return the register decremented and tested in INSN,
271 or zero if it is not a decrement-and-branch insn. */
274 doloop_register_get (rtx insn ATTRIBUTE_UNUSED)
276 #ifdef HAVE_doloop_end
277 rtx pattern, reg, condition;
282 pattern = PATTERN (insn);
283 condition = doloop_condition_get (pattern);
287 if (REG_P (XEXP (condition, 0)))
288 reg = XEXP (condition, 0);
289 else if (GET_CODE (XEXP (condition, 0)) == PLUS
290 && REG_P (XEXP (XEXP (condition, 0), 0)))
291 reg = XEXP (XEXP (condition, 0), 0);
301 /* Check if COUNT_REG is set to a constant in the PRE_HEADER block, so
302 that the number of iterations is a compile-time constant. If so,
303 return the rtx that sets COUNT_REG to a constant, and set COUNT to
304 this constant. Otherwise return 0. */
306 const_iteration_count (rtx count_reg, basic_block pre_header,
307 HOST_WIDEST_INT * count)
315 get_ebb_head_tail (pre_header, pre_header, &head, &tail);
317 for (insn = tail; insn != PREV_INSN (head); insn = PREV_INSN (insn))
318 if (INSN_P (insn) && single_set (insn) &&
319 rtx_equal_p (count_reg, SET_DEST (single_set (insn))))
321 rtx pat = single_set (insn);
323 if (GET_CODE (SET_SRC (pat)) == CONST_INT)
325 *count = INTVAL (SET_SRC (pat));
335 /* A very simple resource-based lower bound on the initiation interval.
336 ??? Improve the accuracy of this bound by considering the
337 utilization of various units. */
341 return (g->num_nodes / issue_rate);
345 /* Points to the array that contains the sched data for each node. */
346 static node_sched_params_ptr node_sched_params;
348 /* Allocate sched_params for each node and initialize it. Assumes that
349 the aux field of each node contain the asap bound (computed earlier),
350 and copies it into the sched_params field. */
352 set_node_sched_params (ddg_ptr g)
356 /* Allocate for each node in the DDG a place to hold the "sched_data". */
357 /* Initialize ASAP/ALAP/HIGHT to zero. */
358 node_sched_params = (node_sched_params_ptr)
359 xcalloc (g->num_nodes,
360 sizeof (struct node_sched_params));
362 /* Set the pointer of the general data of the node to point to the
363 appropriate sched_params structure. */
364 for (i = 0; i < g->num_nodes; i++)
366 /* Watch out for aliasing problems? */
367 node_sched_params[i].asap = g->nodes[i].aux.count;
368 g->nodes[i].aux.info = &node_sched_params[i];
373 print_node_sched_params (FILE * file, int num_nodes)
379 for (i = 0; i < num_nodes; i++)
381 node_sched_params_ptr nsp = &node_sched_params[i];
382 rtx reg_move = nsp->first_reg_move;
385 fprintf (file, "Node %d:\n", i);
386 fprintf (file, " asap = %d:\n", nsp->asap);
387 fprintf (file, " time = %d:\n", nsp->time);
388 fprintf (file, " nreg_moves = %d:\n", nsp->nreg_moves);
389 for (j = 0; j < nsp->nreg_moves; j++)
391 fprintf (file, " reg_move = ");
392 print_rtl_single (file, reg_move);
393 reg_move = PREV_INSN (reg_move);
398 /* Calculate an upper bound for II. SMS should not schedule the loop if it
399 requires more cycles than this bound. Currently set to the sum of the
400 longest latency edge for each node. Reset based on experiments. */
402 calculate_maxii (ddg_ptr g)
407 for (i = 0; i < g->num_nodes; i++)
409 ddg_node_ptr u = &g->nodes[i];
411 int max_edge_latency = 0;
413 for (e = u->out; e; e = e->next_out)
414 max_edge_latency = MAX (max_edge_latency, e->latency);
416 maxii += max_edge_latency;
422 Breaking intra-loop register anti-dependences:
423 Each intra-loop register anti-dependence implies a cross-iteration true
424 dependence of distance 1. Therefore, we can remove such false dependencies
425 and figure out if the partial schedule broke them by checking if (for a
426 true-dependence of distance 1): SCHED_TIME (def) < SCHED_TIME (use) and
427 if so generate a register move. The number of such moves is equal to:
428 SCHED_TIME (use) - SCHED_TIME (def) { 0 broken
429 nreg_moves = ----------------------------------- + 1 - { dependence.
432 static struct undo_replace_buff_elem *
433 generate_reg_moves (partial_schedule_ptr ps)
438 struct undo_replace_buff_elem *reg_move_replaces = NULL;
440 for (i = 0; i < g->num_nodes; i++)
442 ddg_node_ptr u = &g->nodes[i];
444 int nreg_moves = 0, i_reg_move;
445 sbitmap *uses_of_defs;
447 rtx prev_reg, old_reg;
449 /* Compute the number of reg_moves needed for u, by looking at life
450 ranges started at u (excluding self-loops). */
451 for (e = u->out; e; e = e->next_out)
452 if (e->type == TRUE_DEP && e->dest != e->src)
454 int nreg_moves4e = (SCHED_TIME (e->dest) - SCHED_TIME (e->src)) / ii;
456 if (e->distance == 1)
457 nreg_moves4e = (SCHED_TIME (e->dest) - SCHED_TIME (e->src) + ii) / ii;
459 /* If dest precedes src in the schedule of the kernel, then dest
460 will read before src writes and we can save one reg_copy. */
461 if (SCHED_ROW (e->dest) == SCHED_ROW (e->src)
462 && SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
465 nreg_moves = MAX (nreg_moves, nreg_moves4e);
471 /* Every use of the register defined by node may require a different
472 copy of this register, depending on the time the use is scheduled.
473 Set a bitmap vector, telling which nodes use each copy of this
475 uses_of_defs = sbitmap_vector_alloc (nreg_moves, g->num_nodes);
476 sbitmap_vector_zero (uses_of_defs, nreg_moves);
477 for (e = u->out; e; e = e->next_out)
478 if (e->type == TRUE_DEP && e->dest != e->src)
480 int dest_copy = (SCHED_TIME (e->dest) - SCHED_TIME (e->src)) / ii;
482 if (e->distance == 1)
483 dest_copy = (SCHED_TIME (e->dest) - SCHED_TIME (e->src) + ii) / ii;
485 if (SCHED_ROW (e->dest) == SCHED_ROW (e->src)
486 && SCHED_COLUMN (e->dest) < SCHED_COLUMN (e->src))
490 SET_BIT (uses_of_defs[dest_copy - 1], e->dest->cuid);
493 /* Now generate the reg_moves, attaching relevant uses to them. */
494 SCHED_NREG_MOVES (u) = nreg_moves;
495 old_reg = prev_reg = copy_rtx (SET_DEST (single_set (u->insn)));
496 last_reg_move = u->insn;
498 for (i_reg_move = 0; i_reg_move < nreg_moves; i_reg_move++)
500 unsigned int i_use = 0;
501 rtx new_reg = gen_reg_rtx (GET_MODE (prev_reg));
502 rtx reg_move = gen_move_insn (new_reg, prev_reg);
503 sbitmap_iterator sbi;
505 add_insn_before (reg_move, last_reg_move);
506 last_reg_move = reg_move;
508 if (!SCHED_FIRST_REG_MOVE (u))
509 SCHED_FIRST_REG_MOVE (u) = reg_move;
511 EXECUTE_IF_SET_IN_SBITMAP (uses_of_defs[i_reg_move], 0, i_use, sbi)
513 struct undo_replace_buff_elem *rep;
515 rep = (struct undo_replace_buff_elem *)
516 xcalloc (1, sizeof (struct undo_replace_buff_elem));
517 rep->insn = g->nodes[i_use].insn;
518 rep->orig_reg = old_reg;
519 rep->new_reg = new_reg;
521 if (! reg_move_replaces)
522 reg_move_replaces = rep;
525 rep->next = reg_move_replaces;
526 reg_move_replaces = rep;
529 replace_rtx (g->nodes[i_use].insn, old_reg, new_reg);
534 sbitmap_vector_free (uses_of_defs);
536 return reg_move_replaces;
539 /* We call this when we want to undo the SMS schedule for a given loop.
540 One of the things that we do is to delete the register moves generated
541 for the sake of SMS; this function deletes the register move instructions
542 recorded in the undo buffer. */
544 undo_generate_reg_moves (partial_schedule_ptr ps,
545 struct undo_replace_buff_elem *reg_move_replaces)
549 for (i = 0; i < ps->g->num_nodes; i++)
551 ddg_node_ptr u = &ps->g->nodes[i];
553 rtx crr = SCHED_FIRST_REG_MOVE (u);
555 for (j = 0; j < SCHED_NREG_MOVES (u); j++)
557 prev = PREV_INSN (crr);
561 SCHED_FIRST_REG_MOVE (u) = NULL_RTX;
564 while (reg_move_replaces)
566 struct undo_replace_buff_elem *rep = reg_move_replaces;
568 reg_move_replaces = reg_move_replaces->next;
569 replace_rtx (rep->insn, rep->new_reg, rep->orig_reg);
573 /* Free memory allocated for the undo buffer. */
575 free_undo_replace_buff (struct undo_replace_buff_elem *reg_move_replaces)
578 while (reg_move_replaces)
580 struct undo_replace_buff_elem *rep = reg_move_replaces;
582 reg_move_replaces = reg_move_replaces->next;
587 /* Bump the SCHED_TIMEs of all nodes to start from zero. Set the values
588 of SCHED_ROW and SCHED_STAGE. */
590 normalize_sched_times (partial_schedule_ptr ps)
594 int amount = PS_MIN_CYCLE (ps);
597 /* Don't include the closing branch assuming that it is the last node. */
598 for (i = 0; i < g->num_nodes - 1; i++)
600 ddg_node_ptr u = &g->nodes[i];
601 int normalized_time = SCHED_TIME (u) - amount;
603 gcc_assert (normalized_time >= 0);
605 SCHED_TIME (u) = normalized_time;
606 SCHED_ROW (u) = normalized_time % ii;
607 SCHED_STAGE (u) = normalized_time / ii;
611 /* Set SCHED_COLUMN of each node according to its position in PS. */
613 set_columns_for_ps (partial_schedule_ptr ps)
617 for (row = 0; row < ps->ii; row++)
619 ps_insn_ptr cur_insn = ps->rows[row];
622 for (; cur_insn; cur_insn = cur_insn->next_in_row)
623 SCHED_COLUMN (cur_insn->node) = column++;
627 /* Permute the insns according to their order in PS, from row 0 to
628 row ii-1, and position them right before LAST. This schedules
629 the insns of the loop kernel. */
631 permute_partial_schedule (partial_schedule_ptr ps, rtx last)
637 for (row = 0; row < ii ; row++)
638 for (ps_ij = ps->rows[row]; ps_ij; ps_ij = ps_ij->next_in_row)
639 if (PREV_INSN (last) != ps_ij->node->insn)
640 reorder_insns_nobb (ps_ij->node->first_note, ps_ij->node->insn,
644 /* As part of undoing SMS we return to the original ordering of the
645 instructions inside the loop kernel. Given the partial schedule PS, this
646 function returns the ordering of the instruction according to their CUID
647 in the DDG (PS->G), which is the original order of the instruction before
650 undo_permute_partial_schedule (partial_schedule_ptr ps, rtx last)
654 for (i = 0 ; i < ps->g->num_nodes; i++)
655 if (last == ps->g->nodes[i].insn
656 || last == ps->g->nodes[i].first_note)
658 else if (PREV_INSN (last) != ps->g->nodes[i].insn)
659 reorder_insns_nobb (ps->g->nodes[i].first_note, ps->g->nodes[i].insn,
663 /* Used to generate the prologue & epilogue. Duplicate the subset of
664 nodes whose stages are between FROM_STAGE and TO_STAGE (inclusive
665 of both), together with a prefix/suffix of their reg_moves. */
667 duplicate_insns_of_cycles (partial_schedule_ptr ps, int from_stage,
668 int to_stage, int for_prolog)
673 for (row = 0; row < ps->ii; row++)
674 for (ps_ij = ps->rows[row]; ps_ij; ps_ij = ps_ij->next_in_row)
676 ddg_node_ptr u_node = ps_ij->node;
678 rtx reg_move = NULL_RTX;
682 /* SCHED_STAGE (u_node) >= from_stage == 0. Generate increasing
683 number of reg_moves starting with the second occurrence of
684 u_node, which is generated if its SCHED_STAGE <= to_stage. */
685 i_reg_moves = to_stage - SCHED_STAGE (u_node) + 1;
686 i_reg_moves = MAX (i_reg_moves, 0);
687 i_reg_moves = MIN (i_reg_moves, SCHED_NREG_MOVES (u_node));
689 /* The reg_moves start from the *first* reg_move backwards. */
692 reg_move = SCHED_FIRST_REG_MOVE (u_node);
693 for (j = 1; j < i_reg_moves; j++)
694 reg_move = PREV_INSN (reg_move);
697 else /* It's for the epilog. */
699 /* SCHED_STAGE (u_node) <= to_stage. Generate all reg_moves,
700 starting to decrease one stage after u_node no longer occurs;
701 that is, generate all reg_moves until
702 SCHED_STAGE (u_node) == from_stage - 1. */
703 i_reg_moves = SCHED_NREG_MOVES (u_node)
704 - (from_stage - SCHED_STAGE (u_node) - 1);
705 i_reg_moves = MAX (i_reg_moves, 0);
706 i_reg_moves = MIN (i_reg_moves, SCHED_NREG_MOVES (u_node));
708 /* The reg_moves start from the *last* reg_move forwards. */
711 reg_move = SCHED_FIRST_REG_MOVE (u_node);
712 for (j = 1; j < SCHED_NREG_MOVES (u_node); j++)
713 reg_move = PREV_INSN (reg_move);
717 for (j = 0; j < i_reg_moves; j++, reg_move = NEXT_INSN (reg_move))
718 emit_insn (copy_rtx (PATTERN (reg_move)));
719 if (SCHED_STAGE (u_node) >= from_stage
720 && SCHED_STAGE (u_node) <= to_stage)
721 duplicate_insn_chain (u_node->first_note, u_node->insn);
726 /* Generate the instructions (including reg_moves) for prolog & epilog. */
728 generate_prolog_epilog (partial_schedule_ptr ps, struct loop * loop, rtx count_reg)
731 int last_stage = PS_STAGE_COUNT (ps) - 1;
734 /* Generate the prolog, inserting its insns on the loop-entry edge. */
738 /* Generate a subtract instruction at the beginning of the prolog to
739 adjust the loop count by STAGE_COUNT. */
740 emit_insn (gen_sub2_insn (count_reg, GEN_INT (last_stage)));
742 for (i = 0; i < last_stage; i++)
743 duplicate_insns_of_cycles (ps, 0, i, 1);
745 /* Put the prolog on the entry edge. */
746 e = loop_preheader_edge (loop);
747 split_edge_and_insert (e, get_insns());
751 /* Generate the epilog, inserting its insns on the loop-exit edge. */
754 for (i = 0; i < last_stage; i++)
755 duplicate_insns_of_cycles (ps, i + 1, last_stage, 0);
757 /* Put the epilogue on the exit edge. */
758 gcc_assert (single_exit (loop));
759 e = single_exit (loop);
760 split_edge_and_insert (e, get_insns());
764 /* Return true if all the BBs of the loop are empty except the
767 loop_single_full_bb_p (struct loop *loop)
770 basic_block *bbs = get_loop_body (loop);
772 for (i = 0; i < loop->num_nodes ; i++)
775 bool empty_bb = true;
777 if (bbs[i] == loop->header)
780 /* Make sure that basic blocks other than the header
781 have only notes labels or jumps. */
782 get_ebb_head_tail (bbs[i], bbs[i], &head, &tail);
783 for (; head != NEXT_INSN (tail); head = NEXT_INSN (head))
785 if (NOTE_P (head) || LABEL_P (head)
786 || (INSN_P (head) && JUMP_P (head)))
802 /* A simple loop from SMS point of view; it is a loop that is composed of
803 either a single basic block or two BBs - a header and a latch. */
804 #define SIMPLE_SMS_LOOP_P(loop) ((loop->num_nodes < 3 ) \
805 && (EDGE_COUNT (loop->latch->preds) == 1) \
806 && (EDGE_COUNT (loop->latch->succs) == 1))
808 /* Return true if the loop is in its canonical form and false if not.
809 i.e. SIMPLE_SMS_LOOP_P and have one preheader block, and single exit. */
811 loop_canon_p (struct loop *loop)
814 if (loop->inner || ! loop->outer)
817 if (!single_exit (loop))
821 fprintf (dump_file, "SMS loop many exits ");
826 if (! SIMPLE_SMS_LOOP_P (loop) && ! loop_single_full_bb_p (loop))
830 fprintf (dump_file, "SMS loop many BBs. ");
838 /* If there are more than one entry for the loop,
839 make it one by splitting the first entry edge and
840 redirecting the others to the new BB. */
842 canon_loop (struct loop *loop)
847 /* Avoid annoying special cases of edges going to exit
849 FOR_EACH_EDGE (e, i, EXIT_BLOCK_PTR->preds)
850 if ((e->flags & EDGE_FALLTHRU) && (EDGE_COUNT (e->src->succs) > 1))
853 if (loop->latch == loop->header
854 || EDGE_COUNT (loop->latch->succs) > 1)
856 FOR_EACH_EDGE (e, i, loop->header->preds)
857 if (e->src == loop->latch)
863 /* Main entry point, perform SMS scheduling on the loops of the function
864 that consist of single basic blocks. */
868 static int passes = 0;
873 unsigned i,num_loops;
874 partial_schedule_ptr ps;
876 basic_block bb = NULL;
877 /* vars to the versioning only if needed*/
879 basic_block condition_bb = NULL;
881 gcov_type trip_count = 0;
883 loop_optimizer_init (LOOPS_HAVE_PREHEADERS
884 | LOOPS_HAVE_MARKED_SINGLE_EXITS);
886 return; /* There are no loops to schedule. */
888 /* Initialize issue_rate. */
889 if (targetm.sched.issue_rate)
891 int temp = reload_completed;
893 reload_completed = 1;
894 issue_rate = targetm.sched.issue_rate ();
895 reload_completed = temp;
900 /* Initialize the scheduler. */
901 current_sched_info = &sms_sched_info;
904 /* Init Data Flow analysis, to be used in interloop dep calculation. */
905 df = df_init (DF_HARD_REGS | DF_EQUIV_NOTES | DF_SUBREGS);
906 df_rd_add_problem (df, 0);
907 df_ru_add_problem (df, 0);
908 df_chain_add_problem (df, DF_DU_CHAIN | DF_UD_CHAIN);
912 df_dump (df, dump_file);
914 /* Allocate memory to hold the DDG array one entry for each loop.
915 We use loop->num as index into this array. */
916 g_arr = XCNEWVEC (ddg_ptr, current_loops->num);
919 /* Build DDGs for all the relevant loops and hold them in G_ARR
920 indexed by the loop index. */
921 for (i = 0; i < current_loops->num; i++)
925 struct loop *loop = current_loops->parray[i];
928 if ((passes++ > MAX_SMS_LOOP_NUMBER) && (MAX_SMS_LOOP_NUMBER != -1))
931 fprintf (dump_file, "SMS reached MAX_PASSES... \n");
936 if (! loop_canon_p (loop))
939 if (! loop_single_full_bb_p (loop))
944 get_ebb_head_tail (bb, bb, &head, &tail);
945 latch_edge = loop_latch_edge (loop);
946 gcc_assert (single_exit (loop));
947 if (single_exit (loop)->count)
948 trip_count = latch_edge->count / single_exit (loop)->count;
950 /* Perfrom SMS only on loops that their average count is above threshold. */
952 if ( latch_edge->count
953 && (latch_edge->count < single_exit (loop)->count * SMS_LOOP_AVERAGE_COUNT_THRESHOLD))
957 fprintf (dump_file, "SMS single-bb-loop\n");
958 if (profile_info && flag_branch_probabilities)
960 fprintf (dump_file, "SMS loop-count ");
961 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
962 (HOST_WIDEST_INT) bb->count);
963 fprintf (dump_file, "\n");
964 fprintf (dump_file, "SMS trip-count ");
965 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
966 (HOST_WIDEST_INT) trip_count);
967 fprintf (dump_file, "\n");
968 fprintf (dump_file, "SMS profile-sum-max ");
969 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
970 (HOST_WIDEST_INT) profile_info->sum_max);
971 fprintf (dump_file, "\n");
977 /* Make sure this is a doloop. */
978 if ( !(count_reg = doloop_register_get (tail)))
981 /* Don't handle BBs with calls or barriers, or !single_set insns. */
982 for (insn = head; insn != NEXT_INSN (tail); insn = NEXT_INSN (insn))
985 || (INSN_P (insn) && !JUMP_P (insn)
986 && !single_set (insn) && GET_CODE (PATTERN (insn)) != USE))
989 if (insn != NEXT_INSN (tail))
994 fprintf (dump_file, "SMS loop-with-call\n");
995 else if (BARRIER_P (insn))
996 fprintf (dump_file, "SMS loop-with-barrier\n");
998 fprintf (dump_file, "SMS loop-with-not-single-set\n");
999 print_rtl_single (dump_file, insn);
1005 if (! (g = create_ddg (bb, df, 0)))
1008 fprintf (dump_file, "SMS doloop\n");
1015 /* Release Data Flow analysis data structures. */
1019 /* We don't want to perform SMS on new loops - created by versioning. */
1020 num_loops = current_loops->num;
1021 /* Go over the built DDGs and perfrom SMS for each one of them. */
1022 for (i = 0; i < num_loops; i++)
1025 rtx count_reg, count_init;
1027 unsigned stage_count = 0;
1028 HOST_WIDEST_INT loop_count = 0;
1029 struct loop *loop = current_loops->parray[i];
1031 if (! (g = g_arr[i]))
1035 print_ddg (dump_file, g);
1037 get_ebb_head_tail (loop->header, loop->header, &head, &tail);
1039 latch_edge = loop_latch_edge (loop);
1040 gcc_assert (single_exit (loop));
1041 if (single_exit (loop)->count)
1042 trip_count = latch_edge->count / single_exit (loop)->count;
1046 fprintf (dump_file, "SMS single-bb-loop\n");
1047 if (profile_info && flag_branch_probabilities)
1049 fprintf (dump_file, "SMS loop-count ");
1050 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
1051 (HOST_WIDEST_INT) bb->count);
1052 fprintf (dump_file, "\n");
1053 fprintf (dump_file, "SMS profile-sum-max ");
1054 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
1055 (HOST_WIDEST_INT) profile_info->sum_max);
1056 fprintf (dump_file, "\n");
1058 fprintf (dump_file, "SMS doloop\n");
1059 fprintf (dump_file, "SMS built-ddg %d\n", g->num_nodes);
1060 fprintf (dump_file, "SMS num-loads %d\n", g->num_loads);
1061 fprintf (dump_file, "SMS num-stores %d\n", g->num_stores);
1065 /* In case of th loop have doloop register it gets special
1067 count_init = NULL_RTX;
1068 if ((count_reg = doloop_register_get (tail)))
1070 basic_block pre_header;
1072 pre_header = loop_preheader_edge (loop)->src;
1073 count_init = const_iteration_count (count_reg, pre_header,
1076 gcc_assert (count_reg);
1078 if (dump_file && count_init)
1080 fprintf (dump_file, "SMS const-doloop ");
1081 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC,
1083 fprintf (dump_file, "\n");
1086 node_order = XNEWVEC (int, g->num_nodes);
1088 mii = 1; /* Need to pass some estimate of mii. */
1089 rec_mii = sms_order_nodes (g, mii, node_order);
1090 mii = MAX (res_MII (g), rec_mii);
1091 maxii = (calculate_maxii (g) * SMS_MAX_II_FACTOR) / 100;
1094 fprintf (dump_file, "SMS iis %d %d %d (rec_mii, mii, maxii)\n",
1095 rec_mii, mii, maxii);
1097 /* After sms_order_nodes and before sms_schedule_by_order, to copy over
1099 set_node_sched_params (g);
1101 ps = sms_schedule_by_order (g, mii, maxii, node_order);
1104 stage_count = PS_STAGE_COUNT (ps);
1106 /* Stage count of 1 means that there is no interleaving between
1107 iterations, let the scheduling passes do the job. */
1109 || (count_init && (loop_count <= stage_count))
1110 || (flag_branch_probabilities && (trip_count <= stage_count)))
1114 fprintf (dump_file, "SMS failed... \n");
1115 fprintf (dump_file, "SMS sched-failed (stage-count=%d, loop-count=", stage_count);
1116 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, loop_count);
1117 fprintf (dump_file, ", trip-count=");
1118 fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
1119 fprintf (dump_file, ")\n");
1125 int orig_cycles = kernel_number_of_cycles (BB_HEAD (g->bb), BB_END (g->bb));
1127 struct undo_replace_buff_elem *reg_move_replaces;
1132 "SMS succeeded %d %d (with ii, sc)\n", ps->ii,
1134 print_partial_schedule (ps, dump_file);
1136 "SMS Branch (%d) will later be scheduled at cycle %d.\n",
1137 g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
1140 /* Set the stage boundaries. If the DDG is built with closing_branch_deps,
1141 the closing_branch was scheduled and should appear in the last (ii-1)
1142 row. Otherwise, we are free to schedule the branch, and we let nodes
1143 that were scheduled at the first PS_MIN_CYCLE cycle appear in the first
1144 row; this should reduce stage_count to minimum. */
1145 normalize_sched_times (ps);
1146 rotate_partial_schedule (ps, PS_MIN_CYCLE (ps));
1147 set_columns_for_ps (ps);
1149 /* Generate the kernel just to be able to measure its cycles. */
1150 permute_partial_schedule (ps, g->closing_branch->first_note);
1151 reg_move_replaces = generate_reg_moves (ps);
1153 /* Get the number of cycles the new kernel expect to execute in. */
1154 new_cycles = kernel_number_of_cycles (BB_HEAD (g->bb), BB_END (g->bb));
1156 /* Get back to the original loop so we can do loop versioning. */
1157 undo_permute_partial_schedule (ps, g->closing_branch->first_note);
1158 if (reg_move_replaces)
1159 undo_generate_reg_moves (ps, reg_move_replaces);
1161 if ( new_cycles >= orig_cycles)
1163 /* SMS is not profitable so undo the permutation and reg move generation
1164 and return the kernel to its original state. */
1166 fprintf (dump_file, "Undoing SMS because it is not profitable.\n");
1173 /* case the BCT count is not known , Do loop-versioning */
1174 if (count_reg && ! count_init)
1176 rtx comp_rtx = gen_rtx_fmt_ee (GT, VOIDmode, count_reg,
1177 GEN_INT(stage_count));
1179 nloop = loop_version (loop, comp_rtx, &condition_bb, true);
1182 /* Set new iteration count of loop kernel. */
1183 if (count_reg && count_init)
1184 SET_SRC (single_set (count_init)) = GEN_INT (loop_count
1187 /* Now apply the scheduled kernel to the RTL of the loop. */
1188 permute_partial_schedule (ps, g->closing_branch->first_note);
1190 /* Mark this loop as software pipelined so the later
1191 scheduling passes doesn't touch it. */
1192 if (! flag_resched_modulo_sched)
1193 g->bb->flags |= BB_DISABLE_SCHEDULE;
1194 /* The life-info is not valid any more. */
1195 g->bb->flags |= BB_DIRTY;
1197 reg_move_replaces = generate_reg_moves (ps);
1199 print_node_sched_params (dump_file, g->num_nodes);
1200 /* Generate prolog and epilog. */
1201 if (count_reg && !count_init)
1202 generate_prolog_epilog (ps, loop, count_reg);
1204 generate_prolog_epilog (ps, loop, NULL_RTX);
1206 free_undo_replace_buff (reg_move_replaces);
1209 free_partial_schedule (ps);
1210 free (node_sched_params);
1217 /* Release scheduler data, needed until now because of DFA. */
1219 loop_optimizer_finalize ();
1222 /* The SMS scheduling algorithm itself
1223 -----------------------------------
1224 Input: 'O' an ordered list of insns of a loop.
1225 Output: A scheduling of the loop - kernel, prolog, and epilogue.
1227 'Q' is the empty Set
1228 'PS' is the partial schedule; it holds the currently scheduled nodes with
1230 'PSP' previously scheduled predecessors.
1231 'PSS' previously scheduled successors.
1232 't(u)' the cycle where u is scheduled.
1233 'l(u)' is the latency of u.
1234 'd(v,u)' is the dependence distance from v to u.
1235 'ASAP(u)' the earliest time at which u could be scheduled as computed in
1236 the node ordering phase.
1237 'check_hardware_resources_conflicts(u, PS, c)'
1238 run a trace around cycle/slot through DFA model
1239 to check resource conflicts involving instruction u
1240 at cycle c given the partial schedule PS.
1241 'add_to_partial_schedule_at_time(u, PS, c)'
1242 Add the node/instruction u to the partial schedule
1244 'calculate_register_pressure(PS)'
1245 Given a schedule of instructions, calculate the register
1246 pressure it implies. One implementation could be the
1247 maximum number of overlapping live ranges.
1248 'maxRP' The maximum allowed register pressure, it is usually derived from the number
1249 registers available in the hardware.
1253 3. for each node u in O in pre-computed order
1254 4. if (PSP(u) != Q && PSS(u) == Q) then
1255 5. Early_start(u) = max ( t(v) + l(v) - d(v,u)*II ) over all every v in PSP(u).
1256 6. start = Early_start; end = Early_start + II - 1; step = 1
1257 11. else if (PSP(u) == Q && PSS(u) != Q) then
1258 12. Late_start(u) = min ( t(v) - l(v) + d(v,u)*II ) over all every v in PSS(u).
1259 13. start = Late_start; end = Late_start - II + 1; step = -1
1260 14. else if (PSP(u) != Q && PSS(u) != Q) then
1261 15. Early_start(u) = max ( t(v) + l(v) - d(v,u)*II ) over all every v in PSP(u).
1262 16. Late_start(u) = min ( t(v) - l(v) + d(v,u)*II ) over all every v in PSS(u).
1263 17. start = Early_start;
1264 18. end = min(Early_start + II - 1 , Late_start);
1266 20. else "if (PSP(u) == Q && PSS(u) == Q)"
1267 21. start = ASAP(u); end = start + II - 1; step = 1
1271 24. for (c = start ; c != end ; c += step)
1272 25. if check_hardware_resources_conflicts(u, PS, c) then
1273 26. add_to_partial_schedule_at_time(u, PS, c)
1278 31. if (success == false) then
1280 33. if (II > maxII) then
1281 34. finish - failed to schedule
1286 39. if (calculate_register_pressure(PS) > maxRP) then
1289 42. compute epilogue & prologue
1290 43. finish - succeeded to schedule
1293 /* A limit on the number of cycles that resource conflicts can span. ??? Should
1294 be provided by DFA, and be dependent on the type of insn scheduled. Currently
1295 set to 0 to save compile time. */
1296 #define DFA_HISTORY SMS_DFA_HISTORY
1298 /* Given the partial schedule PS, this function calculates and returns the
1299 cycles in which we can schedule the node with the given index I.
1300 NOTE: Here we do the backtracking in SMS, in some special cases. We have
1301 noticed that there are several cases in which we fail to SMS the loop
1302 because the sched window of a node is empty due to tight data-deps. In
1303 such cases we want to unschedule some of the predecessors/successors
1304 until we get non-empty scheduling window. It returns -1 if the
1305 scheduling window is empty and zero otherwise. */
1308 get_sched_window (partial_schedule_ptr ps, int *nodes_order, int i,
1309 sbitmap sched_nodes, int ii, int *start_p, int *step_p, int *end_p)
1311 int start, step, end;
1313 int u = nodes_order [i];
1314 ddg_node_ptr u_node = &ps->g->nodes[u];
1315 sbitmap psp = sbitmap_alloc (ps->g->num_nodes);
1316 sbitmap pss = sbitmap_alloc (ps->g->num_nodes);
1317 sbitmap u_node_preds = NODE_PREDECESSORS (u_node);
1318 sbitmap u_node_succs = NODE_SUCCESSORS (u_node);
1322 /* 1. compute sched window for u (start, end, step). */
1325 psp_not_empty = sbitmap_a_and_b_cg (psp, u_node_preds, sched_nodes);
1326 pss_not_empty = sbitmap_a_and_b_cg (pss, u_node_succs, sched_nodes);
1328 if (psp_not_empty && !pss_not_empty)
1330 int early_start = INT_MIN;
1333 for (e = u_node->in; e != 0; e = e->next_in)
1335 ddg_node_ptr v_node = e->src;
1336 if (TEST_BIT (sched_nodes, v_node->cuid))
1338 int node_st = SCHED_TIME (v_node)
1339 + e->latency - (e->distance * ii);
1341 early_start = MAX (early_start, node_st);
1343 if (e->data_type == MEM_DEP)
1344 end = MIN (end, SCHED_TIME (v_node) + ii - 1);
1347 start = early_start;
1348 end = MIN (end, early_start + ii);
1352 else if (!psp_not_empty && pss_not_empty)
1354 int late_start = INT_MAX;
1357 for (e = u_node->out; e != 0; e = e->next_out)
1359 ddg_node_ptr v_node = e->dest;
1360 if (TEST_BIT (sched_nodes, v_node->cuid))
1362 late_start = MIN (late_start,
1363 SCHED_TIME (v_node) - e->latency
1364 + (e->distance * ii));
1365 if (e->data_type == MEM_DEP)
1366 end = MAX (end, SCHED_TIME (v_node) - ii + 1);
1370 end = MAX (end, late_start - ii);
1374 else if (psp_not_empty && pss_not_empty)
1376 int early_start = INT_MIN;
1377 int late_start = INT_MAX;
1381 for (e = u_node->in; e != 0; e = e->next_in)
1383 ddg_node_ptr v_node = e->src;
1385 if (TEST_BIT (sched_nodes, v_node->cuid))
1387 early_start = MAX (early_start,
1388 SCHED_TIME (v_node) + e->latency
1389 - (e->distance * ii));
1390 if (e->data_type == MEM_DEP)
1391 end = MIN (end, SCHED_TIME (v_node) + ii - 1);
1394 for (e = u_node->out; e != 0; e = e->next_out)
1396 ddg_node_ptr v_node = e->dest;
1398 if (TEST_BIT (sched_nodes, v_node->cuid))
1400 late_start = MIN (late_start,
1401 SCHED_TIME (v_node) - e->latency
1402 + (e->distance * ii));
1403 if (e->data_type == MEM_DEP)
1404 start = MAX (start, SCHED_TIME (v_node) - ii + 1);
1407 start = MAX (start, early_start);
1408 end = MIN (end, MIN (early_start + ii, late_start + 1));
1411 else /* psp is empty && pss is empty. */
1413 start = SCHED_ASAP (u_node);
1424 if ((start >= end && step == 1) || (start <= end && step == -1))
1430 /* This function implements the scheduling algorithm for SMS according to the
1432 static partial_schedule_ptr
1433 sms_schedule_by_order (ddg_ptr g, int mii, int maxii, int *nodes_order)
1437 int try_again_with_larger_ii = true;
1438 int num_nodes = g->num_nodes;
1440 int start, end, step; /* Place together into one struct? */
1441 sbitmap sched_nodes = sbitmap_alloc (num_nodes);
1442 sbitmap must_precede = sbitmap_alloc (num_nodes);
1443 sbitmap must_follow = sbitmap_alloc (num_nodes);
1444 sbitmap tobe_scheduled = sbitmap_alloc (num_nodes);
1446 partial_schedule_ptr ps = create_partial_schedule (ii, g, DFA_HISTORY);
1448 sbitmap_ones (tobe_scheduled);
1449 sbitmap_zero (sched_nodes);
1451 while ((! sbitmap_equal (tobe_scheduled, sched_nodes)
1452 || try_again_with_larger_ii ) && ii < maxii)
1455 bool unscheduled_nodes = false;
1458 fprintf(dump_file, "Starting with ii=%d\n", ii);
1459 if (try_again_with_larger_ii)
1461 try_again_with_larger_ii = false;
1462 sbitmap_zero (sched_nodes);
1465 for (i = 0; i < num_nodes; i++)
1467 int u = nodes_order[i];
1468 ddg_node_ptr u_node = &ps->g->nodes[u];
1469 rtx insn = u_node->insn;
1473 RESET_BIT (tobe_scheduled, u);
1477 if (JUMP_P (insn)) /* Closing branch handled later. */
1479 RESET_BIT (tobe_scheduled, u);
1483 if (TEST_BIT (sched_nodes, u))
1486 /* Try to get non-empty scheduling window. */
1488 while (get_sched_window (ps, nodes_order, i, sched_nodes, ii, &start, &step, &end) < 0
1491 unscheduled_nodes = true;
1492 if (TEST_BIT (NODE_PREDECESSORS (u_node), nodes_order[j - 1])
1493 || TEST_BIT (NODE_SUCCESSORS (u_node), nodes_order[j - 1]))
1495 ps_unschedule_node (ps, &ps->g->nodes[nodes_order[j - 1]]);
1496 RESET_BIT (sched_nodes, nodes_order [j - 1]);
1502 /* ??? Try backtracking instead of immediately ii++? */
1504 try_again_with_larger_ii = true;
1505 reset_partial_schedule (ps, ii);
1508 /* 2. Try scheduling u in window. */
1510 fprintf(dump_file, "Trying to schedule node %d in (%d .. %d) step %d\n",
1511 u, start, end, step);
1513 /* use must_follow & must_precede bitmaps to determine order
1514 of nodes within the cycle. */
1515 sbitmap_zero (must_precede);
1516 sbitmap_zero (must_follow);
1517 for (e = u_node->in; e != 0; e = e->next_in)
1518 if (TEST_BIT (sched_nodes, e->src->cuid)
1519 && e->latency == (ii * e->distance)
1520 && start == SCHED_TIME (e->src))
1521 SET_BIT (must_precede, e->src->cuid);
1523 for (e = u_node->out; e != 0; e = e->next_out)
1524 if (TEST_BIT (sched_nodes, e->dest->cuid)
1525 && e->latency == (ii * e->distance)
1526 && end == SCHED_TIME (e->dest))
1527 SET_BIT (must_follow, e->dest->cuid);
1530 if ((step > 0 && start < end) || (step < 0 && start > end))
1531 for (c = start; c != end; c += step)
1535 psi = ps_add_node_check_conflicts (ps, u_node, c,
1541 SCHED_TIME (u_node) = c;
1542 SET_BIT (sched_nodes, u);
1545 fprintf(dump_file, "Schedule in %d\n", c);
1551 /* ??? Try backtracking instead of immediately ii++? */
1553 try_again_with_larger_ii = true;
1554 reset_partial_schedule (ps, ii);
1557 if (unscheduled_nodes)
1560 /* ??? If (success), check register pressure estimates. */
1561 } /* Continue with next node. */
1562 } /* While try_again_with_larger_ii. */
1564 sbitmap_free (sched_nodes);
1565 sbitmap_free (must_precede);
1566 sbitmap_free (must_follow);
1567 sbitmap_free (tobe_scheduled);
1571 free_partial_schedule (ps);
1578 /* This page implements the algorithm for ordering the nodes of a DDG
1579 for modulo scheduling, activated through the
1580 "int sms_order_nodes (ddg_ptr, int mii, int * result)" API. */
1582 #define ORDER_PARAMS(x) ((struct node_order_params *) (x)->aux.info)
1583 #define ASAP(x) (ORDER_PARAMS ((x))->asap)
1584 #define ALAP(x) (ORDER_PARAMS ((x))->alap)
1585 #define HEIGHT(x) (ORDER_PARAMS ((x))->height)
1586 #define MOB(x) (ALAP ((x)) - ASAP ((x)))
1587 #define DEPTH(x) (ASAP ((x)))
1589 typedef struct node_order_params * nopa;
1591 static void order_nodes_of_sccs (ddg_all_sccs_ptr, int * result);
1592 static int order_nodes_in_scc (ddg_ptr, sbitmap, sbitmap, int*, int);
1593 static nopa calculate_order_params (ddg_ptr, int mii);
1594 static int find_max_asap (ddg_ptr, sbitmap);
1595 static int find_max_hv_min_mob (ddg_ptr, sbitmap);
1596 static int find_max_dv_min_mob (ddg_ptr, sbitmap);
1598 enum sms_direction {BOTTOMUP, TOPDOWN};
1600 struct node_order_params
1607 /* Check if NODE_ORDER contains a permutation of 0 .. NUM_NODES-1. */
1609 check_nodes_order (int *node_order, int num_nodes)
1612 sbitmap tmp = sbitmap_alloc (num_nodes);
1616 for (i = 0; i < num_nodes; i++)
1618 int u = node_order[i];
1620 gcc_assert (u < num_nodes && u >= 0 && !TEST_BIT (tmp, u));
1628 /* Order the nodes of G for scheduling and pass the result in
1629 NODE_ORDER. Also set aux.count of each node to ASAP.
1630 Return the recMII for the given DDG. */
1632 sms_order_nodes (ddg_ptr g, int mii, int * node_order)
1636 ddg_all_sccs_ptr sccs = create_ddg_all_sccs (g);
1638 nopa nops = calculate_order_params (g, mii);
1640 order_nodes_of_sccs (sccs, node_order);
1642 if (sccs->num_sccs > 0)
1643 /* First SCC has the largest recurrence_length. */
1644 rec_mii = sccs->sccs[0]->recurrence_length;
1646 /* Save ASAP before destroying node_order_params. */
1647 for (i = 0; i < g->num_nodes; i++)
1649 ddg_node_ptr v = &g->nodes[i];
1650 v->aux.count = ASAP (v);
1654 free_ddg_all_sccs (sccs);
1655 check_nodes_order (node_order, g->num_nodes);
1661 order_nodes_of_sccs (ddg_all_sccs_ptr all_sccs, int * node_order)
1664 ddg_ptr g = all_sccs->ddg;
1665 int num_nodes = g->num_nodes;
1666 sbitmap prev_sccs = sbitmap_alloc (num_nodes);
1667 sbitmap on_path = sbitmap_alloc (num_nodes);
1668 sbitmap tmp = sbitmap_alloc (num_nodes);
1669 sbitmap ones = sbitmap_alloc (num_nodes);
1671 sbitmap_zero (prev_sccs);
1672 sbitmap_ones (ones);
1674 /* Perfrom the node ordering starting from the SCC with the highest recMII.
1675 For each SCC order the nodes according to their ASAP/ALAP/HEIGHT etc. */
1676 for (i = 0; i < all_sccs->num_sccs; i++)
1678 ddg_scc_ptr scc = all_sccs->sccs[i];
1680 /* Add nodes on paths from previous SCCs to the current SCC. */
1681 find_nodes_on_paths (on_path, g, prev_sccs, scc->nodes);
1682 sbitmap_a_or_b (tmp, scc->nodes, on_path);
1684 /* Add nodes on paths from the current SCC to previous SCCs. */
1685 find_nodes_on_paths (on_path, g, scc->nodes, prev_sccs);
1686 sbitmap_a_or_b (tmp, tmp, on_path);
1688 /* Remove nodes of previous SCCs from current extended SCC. */
1689 sbitmap_difference (tmp, tmp, prev_sccs);
1691 pos = order_nodes_in_scc (g, prev_sccs, tmp, node_order, pos);
1692 /* Above call to order_nodes_in_scc updated prev_sccs |= tmp. */
1695 /* Handle the remaining nodes that do not belong to any scc. Each call
1696 to order_nodes_in_scc handles a single connected component. */
1697 while (pos < g->num_nodes)
1699 sbitmap_difference (tmp, ones, prev_sccs);
1700 pos = order_nodes_in_scc (g, prev_sccs, tmp, node_order, pos);
1702 sbitmap_free (prev_sccs);
1703 sbitmap_free (on_path);
1705 sbitmap_free (ones);
1708 /* MII is needed if we consider backarcs (that do not close recursive cycles). */
1709 static struct node_order_params *
1710 calculate_order_params (ddg_ptr g, int mii ATTRIBUTE_UNUSED)
1714 int num_nodes = g->num_nodes;
1716 /* Allocate a place to hold ordering params for each node in the DDG. */
1717 nopa node_order_params_arr;
1719 /* Initialize of ASAP/ALAP/HEIGHT to zero. */
1720 node_order_params_arr = (nopa) xcalloc (num_nodes,
1721 sizeof (struct node_order_params));
1723 /* Set the aux pointer of each node to point to its order_params structure. */
1724 for (u = 0; u < num_nodes; u++)
1725 g->nodes[u].aux.info = &node_order_params_arr[u];
1727 /* Disregarding a backarc from each recursive cycle to obtain a DAG,
1728 calculate ASAP, ALAP, mobility, distance, and height for each node
1729 in the dependence (direct acyclic) graph. */
1731 /* We assume that the nodes in the array are in topological order. */
1734 for (u = 0; u < num_nodes; u++)
1736 ddg_node_ptr u_node = &g->nodes[u];
1739 for (e = u_node->in; e; e = e->next_in)
1740 if (e->distance == 0)
1741 ASAP (u_node) = MAX (ASAP (u_node),
1742 ASAP (e->src) + e->latency);
1743 max_asap = MAX (max_asap, ASAP (u_node));
1746 for (u = num_nodes - 1; u > -1; u--)
1748 ddg_node_ptr u_node = &g->nodes[u];
1750 ALAP (u_node) = max_asap;
1751 HEIGHT (u_node) = 0;
1752 for (e = u_node->out; e; e = e->next_out)
1753 if (e->distance == 0)
1755 ALAP (u_node) = MIN (ALAP (u_node),
1756 ALAP (e->dest) - e->latency);
1757 HEIGHT (u_node) = MAX (HEIGHT (u_node),
1758 HEIGHT (e->dest) + e->latency);
1762 return node_order_params_arr;
1766 find_max_asap (ddg_ptr g, sbitmap nodes)
1771 sbitmap_iterator sbi;
1773 EXECUTE_IF_SET_IN_SBITMAP (nodes, 0, u, sbi)
1775 ddg_node_ptr u_node = &g->nodes[u];
1777 if (max_asap < ASAP (u_node))
1779 max_asap = ASAP (u_node);
1787 find_max_hv_min_mob (ddg_ptr g, sbitmap nodes)
1791 int min_mob = INT_MAX;
1793 sbitmap_iterator sbi;
1795 EXECUTE_IF_SET_IN_SBITMAP (nodes, 0, u, sbi)
1797 ddg_node_ptr u_node = &g->nodes[u];
1799 if (max_hv < HEIGHT (u_node))
1801 max_hv = HEIGHT (u_node);
1802 min_mob = MOB (u_node);
1805 else if ((max_hv == HEIGHT (u_node))
1806 && (min_mob > MOB (u_node)))
1808 min_mob = MOB (u_node);
1816 find_max_dv_min_mob (ddg_ptr g, sbitmap nodes)
1820 int min_mob = INT_MAX;
1822 sbitmap_iterator sbi;
1824 EXECUTE_IF_SET_IN_SBITMAP (nodes, 0, u, sbi)
1826 ddg_node_ptr u_node = &g->nodes[u];
1828 if (max_dv < DEPTH (u_node))
1830 max_dv = DEPTH (u_node);
1831 min_mob = MOB (u_node);
1834 else if ((max_dv == DEPTH (u_node))
1835 && (min_mob > MOB (u_node)))
1837 min_mob = MOB (u_node);
1844 /* Places the nodes of SCC into the NODE_ORDER array starting
1845 at position POS, according to the SMS ordering algorithm.
1846 NODES_ORDERED (in&out parameter) holds the bitset of all nodes in
1847 the NODE_ORDER array, starting from position zero. */
1849 order_nodes_in_scc (ddg_ptr g, sbitmap nodes_ordered, sbitmap scc,
1850 int * node_order, int pos)
1852 enum sms_direction dir;
1853 int num_nodes = g->num_nodes;
1854 sbitmap workset = sbitmap_alloc (num_nodes);
1855 sbitmap tmp = sbitmap_alloc (num_nodes);
1856 sbitmap zero_bitmap = sbitmap_alloc (num_nodes);
1857 sbitmap predecessors = sbitmap_alloc (num_nodes);
1858 sbitmap successors = sbitmap_alloc (num_nodes);
1860 sbitmap_zero (predecessors);
1861 find_predecessors (predecessors, g, nodes_ordered);
1863 sbitmap_zero (successors);
1864 find_successors (successors, g, nodes_ordered);
1867 if (sbitmap_a_and_b_cg (tmp, predecessors, scc))
1869 sbitmap_copy (workset, tmp);
1872 else if (sbitmap_a_and_b_cg (tmp, successors, scc))
1874 sbitmap_copy (workset, tmp);
1881 sbitmap_zero (workset);
1882 if ((u = find_max_asap (g, scc)) >= 0)
1883 SET_BIT (workset, u);
1887 sbitmap_zero (zero_bitmap);
1888 while (!sbitmap_equal (workset, zero_bitmap))
1891 ddg_node_ptr v_node;
1892 sbitmap v_node_preds;
1893 sbitmap v_node_succs;
1897 while (!sbitmap_equal (workset, zero_bitmap))
1899 v = find_max_hv_min_mob (g, workset);
1900 v_node = &g->nodes[v];
1901 node_order[pos++] = v;
1902 v_node_succs = NODE_SUCCESSORS (v_node);
1903 sbitmap_a_and_b (tmp, v_node_succs, scc);
1905 /* Don't consider the already ordered successors again. */
1906 sbitmap_difference (tmp, tmp, nodes_ordered);
1907 sbitmap_a_or_b (workset, workset, tmp);
1908 RESET_BIT (workset, v);
1909 SET_BIT (nodes_ordered, v);
1912 sbitmap_zero (predecessors);
1913 find_predecessors (predecessors, g, nodes_ordered);
1914 sbitmap_a_and_b (workset, predecessors, scc);
1918 while (!sbitmap_equal (workset, zero_bitmap))
1920 v = find_max_dv_min_mob (g, workset);
1921 v_node = &g->nodes[v];
1922 node_order[pos++] = v;
1923 v_node_preds = NODE_PREDECESSORS (v_node);
1924 sbitmap_a_and_b (tmp, v_node_preds, scc);
1926 /* Don't consider the already ordered predecessors again. */
1927 sbitmap_difference (tmp, tmp, nodes_ordered);
1928 sbitmap_a_or_b (workset, workset, tmp);
1929 RESET_BIT (workset, v);
1930 SET_BIT (nodes_ordered, v);
1933 sbitmap_zero (successors);
1934 find_successors (successors, g, nodes_ordered);
1935 sbitmap_a_and_b (workset, successors, scc);
1939 sbitmap_free (workset);
1940 sbitmap_free (zero_bitmap);
1941 sbitmap_free (predecessors);
1942 sbitmap_free (successors);
1947 /* This page contains functions for manipulating partial-schedules during
1948 modulo scheduling. */
1950 /* Create a partial schedule and allocate a memory to hold II rows. */
1952 static partial_schedule_ptr
1953 create_partial_schedule (int ii, ddg_ptr g, int history)
1955 partial_schedule_ptr ps = XNEW (struct partial_schedule);
1956 ps->rows = (ps_insn_ptr *) xcalloc (ii, sizeof (ps_insn_ptr));
1958 ps->history = history;
1959 ps->min_cycle = INT_MAX;
1960 ps->max_cycle = INT_MIN;
1966 /* Free the PS_INSNs in rows array of the given partial schedule.
1967 ??? Consider caching the PS_INSN's. */
1969 free_ps_insns (partial_schedule_ptr ps)
1973 for (i = 0; i < ps->ii; i++)
1977 ps_insn_ptr ps_insn = ps->rows[i]->next_in_row;
1980 ps->rows[i] = ps_insn;
1986 /* Free all the memory allocated to the partial schedule. */
1989 free_partial_schedule (partial_schedule_ptr ps)
1998 /* Clear the rows array with its PS_INSNs, and create a new one with
2002 reset_partial_schedule (partial_schedule_ptr ps, int new_ii)
2007 if (new_ii == ps->ii)
2009 ps->rows = (ps_insn_ptr *) xrealloc (ps->rows, new_ii
2010 * sizeof (ps_insn_ptr));
2011 memset (ps->rows, 0, new_ii * sizeof (ps_insn_ptr));
2013 ps->min_cycle = INT_MAX;
2014 ps->max_cycle = INT_MIN;
2017 /* Prints the partial schedule as an ii rows array, for each rows
2018 print the ids of the insns in it. */
2020 print_partial_schedule (partial_schedule_ptr ps, FILE *dump)
2024 for (i = 0; i < ps->ii; i++)
2026 ps_insn_ptr ps_i = ps->rows[i];
2028 fprintf (dump, "\n[CYCLE %d ]: ", i);
2031 fprintf (dump, "%d, ",
2032 INSN_UID (ps_i->node->insn));
2033 ps_i = ps_i->next_in_row;
2038 /* Creates an object of PS_INSN and initializes it to the given parameters. */
2040 create_ps_insn (ddg_node_ptr node, int rest_count, int cycle)
2042 ps_insn_ptr ps_i = XNEW (struct ps_insn);
2045 ps_i->next_in_row = NULL;
2046 ps_i->prev_in_row = NULL;
2047 ps_i->row_rest_count = rest_count;
2048 ps_i->cycle = cycle;
2054 /* Removes the given PS_INSN from the partial schedule. Returns false if the
2055 node is not found in the partial schedule, else returns true. */
2057 remove_node_from_ps (partial_schedule_ptr ps, ps_insn_ptr ps_i)
2064 row = SMODULO (ps_i->cycle, ps->ii);
2065 if (! ps_i->prev_in_row)
2067 if (ps_i != ps->rows[row])
2070 ps->rows[row] = ps_i->next_in_row;
2072 ps->rows[row]->prev_in_row = NULL;
2076 ps_i->prev_in_row->next_in_row = ps_i->next_in_row;
2077 if (ps_i->next_in_row)
2078 ps_i->next_in_row->prev_in_row = ps_i->prev_in_row;
2084 /* Unlike what literature describes for modulo scheduling (which focuses
2085 on VLIW machines) the order of the instructions inside a cycle is
2086 important. Given the bitmaps MUST_FOLLOW and MUST_PRECEDE we know
2087 where the current instruction should go relative to the already
2088 scheduled instructions in the given cycle. Go over these
2089 instructions and find the first possible column to put it in. */
2091 ps_insn_find_column (partial_schedule_ptr ps, ps_insn_ptr ps_i,
2092 sbitmap must_precede, sbitmap must_follow)
2094 ps_insn_ptr next_ps_i;
2095 ps_insn_ptr first_must_follow = NULL;
2096 ps_insn_ptr last_must_precede = NULL;
2102 row = SMODULO (ps_i->cycle, ps->ii);
2104 /* Find the first must follow and the last must precede
2105 and insert the node immediately after the must precede
2106 but make sure that it there is no must follow after it. */
2107 for (next_ps_i = ps->rows[row];
2109 next_ps_i = next_ps_i->next_in_row)
2111 if (TEST_BIT (must_follow, next_ps_i->node->cuid)
2112 && ! first_must_follow)
2113 first_must_follow = next_ps_i;
2114 if (TEST_BIT (must_precede, next_ps_i->node->cuid))
2116 /* If we have already met a node that must follow, then
2117 there is no possible column. */
2118 if (first_must_follow)
2121 last_must_precede = next_ps_i;
2125 /* Now insert the node after INSERT_AFTER_PSI. */
2127 if (! last_must_precede)
2129 ps_i->next_in_row = ps->rows[row];
2130 ps_i->prev_in_row = NULL;
2131 if (ps_i->next_in_row)
2132 ps_i->next_in_row->prev_in_row = ps_i;
2133 ps->rows[row] = ps_i;
2137 ps_i->next_in_row = last_must_precede->next_in_row;
2138 last_must_precede->next_in_row = ps_i;
2139 ps_i->prev_in_row = last_must_precede;
2140 if (ps_i->next_in_row)
2141 ps_i->next_in_row->prev_in_row = ps_i;
2147 /* Advances the PS_INSN one column in its current row; returns false
2148 in failure and true in success. Bit N is set in MUST_FOLLOW if
2149 the node with cuid N must be come after the node pointed to by
2150 PS_I when scheduled in the same cycle. */
2152 ps_insn_advance_column (partial_schedule_ptr ps, ps_insn_ptr ps_i,
2153 sbitmap must_follow)
2155 ps_insn_ptr prev, next;
2157 ddg_node_ptr next_node;
2162 row = SMODULO (ps_i->cycle, ps->ii);
2164 if (! ps_i->next_in_row)
2167 next_node = ps_i->next_in_row->node;
2169 /* Check if next_in_row is dependent on ps_i, both having same sched
2170 times (typically ANTI_DEP). If so, ps_i cannot skip over it. */
2171 if (TEST_BIT (must_follow, next_node->cuid))
2174 /* Advance PS_I over its next_in_row in the doubly linked list. */
2175 prev = ps_i->prev_in_row;
2176 next = ps_i->next_in_row;
2178 if (ps_i == ps->rows[row])
2179 ps->rows[row] = next;
2181 ps_i->next_in_row = next->next_in_row;
2183 if (next->next_in_row)
2184 next->next_in_row->prev_in_row = ps_i;
2186 next->next_in_row = ps_i;
2187 ps_i->prev_in_row = next;
2189 next->prev_in_row = prev;
2191 prev->next_in_row = next;
2196 /* Inserts a DDG_NODE to the given partial schedule at the given cycle.
2197 Returns 0 if this is not possible and a PS_INSN otherwise. Bit N is
2198 set in MUST_PRECEDE/MUST_FOLLOW if the node with cuid N must be come
2199 before/after (respectively) the node pointed to by PS_I when scheduled
2200 in the same cycle. */
2202 add_node_to_ps (partial_schedule_ptr ps, ddg_node_ptr node, int cycle,
2203 sbitmap must_precede, sbitmap must_follow)
2207 int row = SMODULO (cycle, ps->ii);
2210 && ps->rows[row]->row_rest_count >= issue_rate)
2214 rest_count += ps->rows[row]->row_rest_count;
2216 ps_i = create_ps_insn (node, rest_count, cycle);
2218 /* Finds and inserts PS_I according to MUST_FOLLOW and
2220 if (! ps_insn_find_column (ps, ps_i, must_precede, must_follow))
2229 /* Advance time one cycle. Assumes DFA is being used. */
2231 advance_one_cycle (void)
2233 if (targetm.sched.dfa_pre_cycle_insn)
2234 state_transition (curr_state,
2235 targetm.sched.dfa_pre_cycle_insn ());
2237 state_transition (curr_state, NULL);
2239 if (targetm.sched.dfa_post_cycle_insn)
2240 state_transition (curr_state,
2241 targetm.sched.dfa_post_cycle_insn ());
2244 /* Given the kernel of a loop (from FIRST_INSN to LAST_INSN), finds
2245 the number of cycles according to DFA that the kernel fits in,
2246 we use this to check if we done well with SMS after we add
2247 register moves. In some cases register moves overhead makes
2248 it even worse than the original loop. We want SMS to be performed
2249 when it gives less cycles after register moves are added. */
2251 kernel_number_of_cycles (rtx first_insn, rtx last_insn)
2255 int can_issue_more = issue_rate;
2257 state_reset (curr_state);
2259 for (insn = first_insn;
2260 insn != NULL_RTX && insn != last_insn;
2261 insn = NEXT_INSN (insn))
2263 if (! INSN_P (insn) || GET_CODE (PATTERN (insn)) == USE)
2266 /* Check if there is room for the current insn. */
2267 if (!can_issue_more || state_dead_lock_p (curr_state))
2270 advance_one_cycle ();
2271 can_issue_more = issue_rate;
2274 /* Update the DFA state and return with failure if the DFA found
2275 recource conflicts. */
2276 if (state_transition (curr_state, insn) >= 0)
2279 advance_one_cycle ();
2280 can_issue_more = issue_rate;
2283 if (targetm.sched.variable_issue)
2285 targetm.sched.variable_issue (sched_dump, sched_verbose,
2286 insn, can_issue_more);
2287 /* A naked CLOBBER or USE generates no instruction, so don't
2288 let them consume issue slots. */
2289 else if (GET_CODE (PATTERN (insn)) != USE
2290 && GET_CODE (PATTERN (insn)) != CLOBBER)
2296 /* Checks if PS has resource conflicts according to DFA, starting from
2297 FROM cycle to TO cycle; returns true if there are conflicts and false
2298 if there are no conflicts. Assumes DFA is being used. */
2300 ps_has_conflicts (partial_schedule_ptr ps, int from, int to)
2304 state_reset (curr_state);
2306 for (cycle = from; cycle <= to; cycle++)
2308 ps_insn_ptr crr_insn;
2309 /* Holds the remaining issue slots in the current row. */
2310 int can_issue_more = issue_rate;
2312 /* Walk through the DFA for the current row. */
2313 for (crr_insn = ps->rows[SMODULO (cycle, ps->ii)];
2315 crr_insn = crr_insn->next_in_row)
2317 rtx insn = crr_insn->node->insn;
2322 /* Check if there is room for the current insn. */
2323 if (!can_issue_more || state_dead_lock_p (curr_state))
2326 /* Update the DFA state and return with failure if the DFA found
2327 recource conflicts. */
2328 if (state_transition (curr_state, insn) >= 0)
2331 if (targetm.sched.variable_issue)
2333 targetm.sched.variable_issue (sched_dump, sched_verbose,
2334 insn, can_issue_more);
2335 /* A naked CLOBBER or USE generates no instruction, so don't
2336 let them consume issue slots. */
2337 else if (GET_CODE (PATTERN (insn)) != USE
2338 && GET_CODE (PATTERN (insn)) != CLOBBER)
2342 /* Advance the DFA to the next cycle. */
2343 advance_one_cycle ();
2348 /* Checks if the given node causes resource conflicts when added to PS at
2349 cycle C. If not the node is added to PS and returned; otherwise zero
2350 is returned. Bit N is set in MUST_PRECEDE/MUST_FOLLOW if the node with
2351 cuid N must be come before/after (respectively) the node pointed to by
2352 PS_I when scheduled in the same cycle. */
2354 ps_add_node_check_conflicts (partial_schedule_ptr ps, ddg_node_ptr n,
2355 int c, sbitmap must_precede,
2356 sbitmap must_follow)
2358 int has_conflicts = 0;
2361 /* First add the node to the PS, if this succeeds check for
2362 conflicts, trying different issue slots in the same row. */
2363 if (! (ps_i = add_node_to_ps (ps, n, c, must_precede, must_follow)))
2364 return NULL; /* Failed to insert the node at the given cycle. */
2366 has_conflicts = ps_has_conflicts (ps, c, c)
2368 && ps_has_conflicts (ps,
2372 /* Try different issue slots to find one that the given node can be
2373 scheduled in without conflicts. */
2374 while (has_conflicts)
2376 if (! ps_insn_advance_column (ps, ps_i, must_follow))
2378 has_conflicts = ps_has_conflicts (ps, c, c)
2380 && ps_has_conflicts (ps,
2387 remove_node_from_ps (ps, ps_i);
2391 ps->min_cycle = MIN (ps->min_cycle, c);
2392 ps->max_cycle = MAX (ps->max_cycle, c);
2396 /* Rotate the rows of PS such that insns scheduled at time
2397 START_CYCLE will appear in row 0. Updates max/min_cycles. */
2399 rotate_partial_schedule (partial_schedule_ptr ps, int start_cycle)
2401 int i, row, backward_rotates;
2402 int last_row = ps->ii - 1;
2404 if (start_cycle == 0)
2407 backward_rotates = SMODULO (start_cycle, ps->ii);
2409 /* Revisit later and optimize this into a single loop. */
2410 for (i = 0; i < backward_rotates; i++)
2412 ps_insn_ptr first_row = ps->rows[0];
2414 for (row = 0; row < last_row; row++)
2415 ps->rows[row] = ps->rows[row+1];
2417 ps->rows[last_row] = first_row;
2420 ps->max_cycle -= start_cycle;
2421 ps->min_cycle -= start_cycle;
2424 /* Remove the node N from the partial schedule PS; because we restart the DFA
2425 each time we want to check for resource conflicts; this is equivalent to
2426 unscheduling the node N. */
2428 ps_unschedule_node (partial_schedule_ptr ps, ddg_node_ptr n)
2431 int row = SMODULO (SCHED_TIME (n), ps->ii);
2433 if (row < 0 || row > ps->ii)
2436 for (ps_i = ps->rows[row];
2437 ps_i && ps_i->node != n;
2438 ps_i = ps_i->next_in_row);
2442 return remove_node_from_ps (ps, ps_i);
2444 #endif /* INSN_SCHEDULING */
2447 gate_handle_sms (void)
2449 return (optimize > 0 && flag_modulo_sched);
2453 /* Run instruction scheduler. */
2454 /* Perform SMS module scheduling. */
2456 rest_of_handle_sms (void)
2458 #ifdef INSN_SCHEDULING
2461 /* We want to be able to create new pseudos. */
2463 /* Collect loop information to be used in SMS. */
2464 cfg_layout_initialize (CLEANUP_UPDATE_LIFE);
2467 /* Update the life information, because we add pseudos. */
2468 max_regno = max_reg_num ();
2469 allocate_reg_info (max_regno, FALSE, FALSE);
2470 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES,
2473 | PROP_KILL_DEAD_CODE
2474 | PROP_SCAN_DEAD_CODE));
2478 /* Finalize layout changes. */
2480 if (bb->next_bb != EXIT_BLOCK_PTR)
2481 bb->aux = bb->next_bb;
2482 cfg_layout_finalize ();
2483 free_dominance_info (CDI_DOMINATORS);
2484 #endif /* INSN_SCHEDULING */
2488 struct tree_opt_pass pass_sms =
2491 gate_handle_sms, /* gate */
2492 rest_of_handle_sms, /* execute */
2495 0, /* static_pass_number */
2497 0, /* properties_required */
2498 0, /* properties_provided */
2499 0, /* properties_destroyed */
2500 TODO_dump_func, /* todo_flags_start */
2502 TODO_ggc_collect, /* todo_flags_finish */