2 Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
31 #include "insn-config.h"
33 #include "basic-block.h"
37 #include "tree-pass.h"
41 /* We want target macros for the mode switching code to be able to refer
42 to instruction attribute values. */
43 #include "insn-attr.h"
45 #ifdef OPTIMIZE_MODE_SWITCHING
47 /* The algorithm for setting the modes consists of scanning the insn list
48 and finding all the insns which require a specific mode. Each insn gets
49 a unique struct seginfo element. These structures are inserted into a list
50 for each basic block. For each entity, there is an array of bb_info over
51 the flow graph basic blocks (local var 'bb_info'), and contains a list
52 of all insns within that basic block, in the order they are encountered.
54 For each entity, any basic block WITHOUT any insns requiring a specific
55 mode are given a single entry, without a mode. (Each basic block
56 in the flow graph must have at least one entry in the segment table.)
58 The LCM algorithm is then run over the flow graph to determine where to
59 place the sets to the highest-priority value in respect of first the first
60 insn in any one block. Any adjustments required to the transparency
61 vectors are made, then the next iteration starts for the next-lower
62 priority mode, till for each entity all modes are exhausted.
64 More details are located in the code for optimize_mode_switching(). */
66 /* This structure contains the information for each insn which requires
67 either single or double mode to be set.
68 MODE is the mode this insn must be executed in.
69 INSN_PTR is the insn to be executed (may be the note that marks the
70 beginning of a basic block).
71 BBNUM is the flow graph basic block this insn occurs in.
72 NEXT is the next insn in the same basic block. */
79 HARD_REG_SET regs_live;
84 struct seginfo *seginfo;
88 /* These bitmaps are used for the LCM algorithm. */
90 static sbitmap *antic;
91 static sbitmap *transp;
94 static struct seginfo * new_seginfo (int, rtx, int, HARD_REG_SET);
95 static void add_seginfo (struct bb_info *, struct seginfo *);
96 static void reg_dies (rtx, HARD_REG_SET *);
97 static void reg_becomes_live (rtx, rtx, void *);
98 static void make_preds_opaque (basic_block, int);
101 /* This function will allocate a new BBINFO structure, initialized
102 with the MODE, INSN, and basic block BB parameters. */
104 static struct seginfo *
105 new_seginfo (int mode, rtx insn, int bb, HARD_REG_SET regs_live)
108 ptr = XNEW (struct seginfo);
110 ptr->insn_ptr = insn;
113 COPY_HARD_REG_SET (ptr->regs_live, regs_live);
117 /* Add a seginfo element to the end of a list.
118 HEAD is a pointer to the list beginning.
119 INFO is the structure to be linked in. */
122 add_seginfo (struct bb_info *head, struct seginfo *info)
126 if (head->seginfo == NULL)
127 head->seginfo = info;
131 while (ptr->next != NULL)
137 /* Make all predecessors of basic block B opaque, recursively, till we hit
138 some that are already non-transparent, or an edge where aux is set; that
139 denotes that a mode set is to be done on that edge.
140 J is the bit number in the bitmaps that corresponds to the entity that
141 we are currently handling mode-switching for. */
144 make_preds_opaque (basic_block b, int j)
149 FOR_EACH_EDGE (e, ei, b->preds)
151 basic_block pb = e->src;
153 if (e->aux || ! TEST_BIT (transp[pb->index], j))
156 RESET_BIT (transp[pb->index], j);
157 make_preds_opaque (pb, j);
161 /* Record in LIVE that register REG died. */
164 reg_dies (rtx reg, HARD_REG_SET *live)
172 if (regno < FIRST_PSEUDO_REGISTER)
173 remove_from_hard_reg_set (live, GET_MODE (reg), regno);
176 /* Record in LIVE that register REG became live.
177 This is called via note_stores. */
180 reg_becomes_live (rtx reg, rtx setter ATTRIBUTE_UNUSED, void *live)
184 if (GET_CODE (reg) == SUBREG)
185 reg = SUBREG_REG (reg);
191 if (regno < FIRST_PSEUDO_REGISTER)
192 add_to_hard_reg_set ((HARD_REG_SET *) live, GET_MODE (reg), regno);
195 /* Make sure if MODE_ENTRY is defined the MODE_EXIT is defined
197 #if defined (MODE_ENTRY) != defined (MODE_EXIT)
198 #error "Both MODE_ENTRY and MODE_EXIT must be defined"
201 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
202 /* Split the fallthrough edge to the exit block, so that we can note
203 that there NORMAL_MODE is required. Return the new block if it's
204 inserted before the exit block. Otherwise return null. */
207 create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
211 basic_block pre_exit;
213 /* The only non-call predecessor at this stage is a block with a
214 fallthrough edge; there can be at most one, but there could be
215 none at all, e.g. when exit is called. */
217 FOR_EACH_EDGE (eg, ei, EXIT_BLOCK_PTR->preds)
218 if (eg->flags & EDGE_FALLTHRU)
220 basic_block src_bb = eg->src;
221 rtx last_insn, ret_reg;
223 gcc_assert (!pre_exit);
224 /* If this function returns a value at the end, we have to
225 insert the final mode switch before the return value copy
226 to its hard register. */
227 if (EDGE_COUNT (EXIT_BLOCK_PTR->preds) == 1
228 && NONJUMP_INSN_P ((last_insn = BB_END (src_bb)))
229 && GET_CODE (PATTERN (last_insn)) == USE
230 && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG)
232 int ret_start = REGNO (ret_reg);
233 int nregs = hard_regno_nregs[ret_start][GET_MODE (ret_reg)];
234 int ret_end = ret_start + nregs;
236 int maybe_builtin_apply = 0;
237 int forced_late_switch = 0;
238 rtx before_return_copy;
242 rtx return_copy = PREV_INSN (last_insn);
243 rtx return_copy_pat, copy_reg;
244 int copy_start, copy_num;
247 if (INSN_P (return_copy))
249 if (GET_CODE (PATTERN (return_copy)) == USE
250 && GET_CODE (XEXP (PATTERN (return_copy), 0)) == REG
251 && (FUNCTION_VALUE_REGNO_P
252 (REGNO (XEXP (PATTERN (return_copy), 0)))))
254 maybe_builtin_apply = 1;
255 last_insn = return_copy;
258 if (GET_CODE (PATTERN (return_copy)) == ASM_INPUT
259 && strcmp (XSTR (PATTERN (return_copy), 0), "") == 0)
261 last_insn = return_copy;
264 /* If the return register is not (in its entirety)
265 likely spilled, the return copy might be
266 partially or completely optimized away. */
267 return_copy_pat = single_set (return_copy);
268 if (!return_copy_pat)
270 return_copy_pat = PATTERN (return_copy);
271 if (GET_CODE (return_copy_pat) != CLOBBER)
275 /* This might be (clobber (reg [<result>]))
276 when not optimizing. Then check if
277 the previous insn is the clobber for
278 the return register. */
279 copy_reg = SET_DEST (return_copy_pat);
280 if (GET_CODE (copy_reg) == REG
281 && !HARD_REGISTER_NUM_P (REGNO (copy_reg)))
283 if (INSN_P (PREV_INSN (return_copy)))
285 return_copy = PREV_INSN (return_copy);
286 return_copy_pat = PATTERN (return_copy);
287 if (GET_CODE (return_copy_pat) != CLOBBER)
293 copy_reg = SET_DEST (return_copy_pat);
294 if (GET_CODE (copy_reg) == REG)
295 copy_start = REGNO (copy_reg);
296 else if (GET_CODE (copy_reg) == SUBREG
297 && GET_CODE (SUBREG_REG (copy_reg)) == REG)
298 copy_start = REGNO (SUBREG_REG (copy_reg));
301 if (copy_start >= FIRST_PSEUDO_REGISTER)
304 = hard_regno_nregs[copy_start][GET_MODE (copy_reg)];
306 /* If the return register is not likely spilled, - as is
307 the case for floating point on SH4 - then it might
308 be set by an arithmetic operation that needs a
309 different mode than the exit block. */
310 for (j = n_entities - 1; j >= 0; j--)
312 int e = entity_map[j];
313 int mode = MODE_NEEDED (e, return_copy);
315 if (mode != num_modes[e] && mode != MODE_EXIT (e))
320 /* For the SH4, floating point loads depend on fpscr,
321 thus we might need to put the final mode switch
322 after the return value copy. That is still OK,
323 because a floating point return value does not
324 conflict with address reloads. */
325 if (copy_start >= ret_start
326 && copy_start + copy_num <= ret_end
327 && OBJECT_P (SET_SRC (return_copy_pat)))
328 forced_late_switch = 1;
332 if (copy_start >= ret_start
333 && copy_start + copy_num <= ret_end)
335 else if (!maybe_builtin_apply
336 || !FUNCTION_VALUE_REGNO_P (copy_start))
338 last_insn = return_copy;
340 /* ??? Exception handling can lead to the return value
341 copy being already separated from the return value use,
343 Similarly, conditionally returning without a value,
344 and conditionally using builtin_return can lead to an
346 if (return_copy == BB_HEAD (src_bb))
351 last_insn = return_copy;
355 /* If we didn't see a full return value copy, verify that there
356 is a plausible reason for this. If some, but not all of the
357 return register is likely spilled, we can expect that there
358 is a copy for the likely spilled part. */
360 || forced_late_switch
362 || !(CLASS_LIKELY_SPILLED_P
363 (REGNO_REG_CLASS (ret_start)))
365 != hard_regno_nregs[ret_start][GET_MODE (ret_reg)])
366 /* For multi-hard-register floating point
367 values, sometimes the likely-spilled part
368 is ordinarily copied first, then the other
369 part is set with an arithmetic operation.
370 This doesn't actually cause reload
371 failures, so let it pass. */
372 || (GET_MODE_CLASS (GET_MODE (ret_reg)) != MODE_INT
375 if (INSN_P (last_insn))
378 = emit_note_before (NOTE_INSN_DELETED, last_insn);
379 /* Instructions preceding LAST_INSN in the same block might
380 require a different mode than MODE_EXIT, so if we might
381 have such instructions, keep them in a separate block
383 if (last_insn != BB_HEAD (src_bb))
384 src_bb = split_block (src_bb,
385 PREV_INSN (before_return_copy))->dest;
388 before_return_copy = last_insn;
389 pre_exit = split_block (src_bb, before_return_copy)->src;
393 pre_exit = split_edge (eg);
401 /* Find all insns that need a particular mode setting, and insert the
402 necessary mode switches. Return true if we did work. */
405 optimize_mode_switching (void)
412 struct edge_list *edge_list;
413 static const int num_modes[] = NUM_MODES_FOR_MODE_SWITCHING;
414 #define N_ENTITIES ARRAY_SIZE (num_modes)
415 int entity_map[N_ENTITIES];
416 struct bb_info *bb_info[N_ENTITIES];
419 int max_num_modes = 0;
421 basic_block post_entry ATTRIBUTE_UNUSED, pre_exit ATTRIBUTE_UNUSED;
423 for (e = N_ENTITIES - 1, n_entities = 0; e >= 0; e--)
424 if (OPTIMIZE_MODE_SWITCHING (e))
426 int entry_exit_extra = 0;
428 /* Create the list of segments within each basic block.
429 If NORMAL_MODE is defined, allow for two extra
430 blocks split from the entry and exit block. */
431 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
432 entry_exit_extra = 3;
435 = XCNEWVEC (struct bb_info, last_basic_block + entry_exit_extra);
436 entity_map[n_entities++] = e;
437 if (num_modes[e] > max_num_modes)
438 max_num_modes = num_modes[e];
444 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
445 /* Split the edge from the entry block, so that we can note that
446 there NORMAL_MODE is supplied. */
447 post_entry = split_edge (single_succ_edge (ENTRY_BLOCK_PTR));
448 pre_exit = create_pre_exit (n_entities, entity_map, num_modes);
453 /* Create the bitmap vectors. */
455 antic = sbitmap_vector_alloc (last_basic_block, n_entities);
456 transp = sbitmap_vector_alloc (last_basic_block, n_entities);
457 comp = sbitmap_vector_alloc (last_basic_block, n_entities);
459 sbitmap_vector_ones (transp, last_basic_block);
461 for (j = n_entities - 1; j >= 0; j--)
463 int e = entity_map[j];
464 int no_mode = num_modes[e];
465 struct bb_info *info = bb_info[j];
467 /* Determine what the first use (if any) need for a mode of entity E is.
468 This will be the mode that is anticipatable for this block.
469 Also compute the initial transparency settings. */
473 int last_mode = no_mode;
474 HARD_REG_SET live_now;
476 REG_SET_TO_HARD_REG_SET (live_now, df_get_live_in (bb));
478 /* Pretend the mode is clobbered across abnormal edges. */
482 FOR_EACH_EDGE (e, ei, bb->preds)
483 if (e->flags & EDGE_COMPLEX)
487 ptr = new_seginfo (no_mode, BB_HEAD (bb), bb->index, live_now);
488 add_seginfo (info + bb->index, ptr);
489 RESET_BIT (transp[bb->index], j);
493 for (insn = BB_HEAD (bb);
494 insn != NULL && insn != NEXT_INSN (BB_END (bb));
495 insn = NEXT_INSN (insn))
499 int mode = MODE_NEEDED (e, insn);
502 if (mode != no_mode && mode != last_mode)
505 ptr = new_seginfo (mode, insn, bb->index, live_now);
506 add_seginfo (info + bb->index, ptr);
507 RESET_BIT (transp[bb->index], j);
510 last_mode = MODE_AFTER (last_mode, insn);
512 /* Update LIVE_NOW. */
513 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
514 if (REG_NOTE_KIND (link) == REG_DEAD)
515 reg_dies (XEXP (link, 0), &live_now);
517 note_stores (PATTERN (insn), reg_becomes_live, &live_now);
518 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
519 if (REG_NOTE_KIND (link) == REG_UNUSED)
520 reg_dies (XEXP (link, 0), &live_now);
524 info[bb->index].computing = last_mode;
525 /* Check for blocks without ANY mode requirements. */
526 if (last_mode == no_mode)
528 ptr = new_seginfo (no_mode, BB_END (bb), bb->index, live_now);
529 add_seginfo (info + bb->index, ptr);
532 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
534 int mode = MODE_ENTRY (e);
540 /* By always making this nontransparent, we save
541 an extra check in make_preds_opaque. We also
542 need this to avoid confusing pre_edge_lcm when
543 antic is cleared but transp and comp are set. */
544 RESET_BIT (transp[bb->index], j);
546 /* Insert a fake computing definition of MODE into entry
547 blocks which compute no mode. This represents the mode on
549 info[bb->index].computing = mode;
552 info[pre_exit->index].seginfo->mode = MODE_EXIT (e);
555 #endif /* NORMAL_MODE */
558 kill = sbitmap_vector_alloc (last_basic_block, n_entities);
559 for (i = 0; i < max_num_modes; i++)
561 int current_mode[N_ENTITIES];
565 /* Set the anticipatable and computing arrays. */
566 sbitmap_vector_zero (antic, last_basic_block);
567 sbitmap_vector_zero (comp, last_basic_block);
568 for (j = n_entities - 1; j >= 0; j--)
570 int m = current_mode[j] = MODE_PRIORITY_TO_MODE (entity_map[j], i);
571 struct bb_info *info = bb_info[j];
575 if (info[bb->index].seginfo->mode == m)
576 SET_BIT (antic[bb->index], j);
578 if (info[bb->index].computing == m)
579 SET_BIT (comp[bb->index], j);
583 /* Calculate the optimal locations for the
584 placement mode switches to modes with priority I. */
587 sbitmap_not (kill[bb->index], transp[bb->index]);
588 edge_list = pre_edge_lcm (n_entities, transp, comp, antic,
589 kill, &insert, &delete);
591 for (j = n_entities - 1; j >= 0; j--)
593 /* Insert all mode sets that have been inserted by lcm. */
594 int no_mode = num_modes[entity_map[j]];
596 /* Wherever we have moved a mode setting upwards in the flow graph,
597 the blocks between the new setting site and the now redundant
598 computation ceases to be transparent for any lower-priority
599 mode of the same entity. First set the aux field of each
600 insertion site edge non-transparent, then propagate the new
601 non-transparency from the redundant computation upwards till
602 we hit an insertion site or an already non-transparent block. */
603 for (e = NUM_EDGES (edge_list) - 1; e >= 0; e--)
605 edge eg = INDEX_EDGE (edge_list, e);
608 HARD_REG_SET live_at_edge;
613 if (! TEST_BIT (insert[e], j))
618 mode = current_mode[j];
621 REG_SET_TO_HARD_REG_SET (live_at_edge, df_get_live_out (src_bb));
624 EMIT_MODE_SET (entity_map[j], mode, live_at_edge);
625 mode_set = get_insns ();
628 /* Do not bother to insert empty sequence. */
629 if (mode_set == NULL_RTX)
632 /* We should not get an abnormal edge here. */
633 gcc_assert (! (eg->flags & EDGE_ABNORMAL));
636 insert_insn_on_edge (mode_set, eg);
639 FOR_EACH_BB_REVERSE (bb)
640 if (TEST_BIT (delete[bb->index], j))
642 make_preds_opaque (bb, j);
643 /* Cancel the 'deleted' mode set. */
644 bb_info[j][bb->index].seginfo->mode = no_mode;
648 sbitmap_vector_free (delete);
649 sbitmap_vector_free (insert);
650 clear_aux_for_edges ();
651 free_edge_list (edge_list);
654 /* Now output the remaining mode sets in all the segments. */
655 for (j = n_entities - 1; j >= 0; j--)
657 int no_mode = num_modes[entity_map[j]];
659 FOR_EACH_BB_REVERSE (bb)
661 struct seginfo *ptr, *next;
662 for (ptr = bb_info[j][bb->index].seginfo; ptr; ptr = next)
665 if (ptr->mode != no_mode)
670 EMIT_MODE_SET (entity_map[j], ptr->mode, ptr->regs_live);
671 mode_set = get_insns ();
674 /* Insert MODE_SET only if it is nonempty. */
675 if (mode_set != NULL_RTX)
678 if (NOTE_INSN_BASIC_BLOCK_P (ptr->insn_ptr))
679 emit_insn_after (mode_set, ptr->insn_ptr);
681 emit_insn_before (mode_set, ptr->insn_ptr);
692 /* Finished. Free up all the things we've allocated. */
693 sbitmap_vector_free (kill);
694 sbitmap_vector_free (antic);
695 sbitmap_vector_free (transp);
696 sbitmap_vector_free (comp);
699 commit_edge_insertions ();
701 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
702 cleanup_cfg (CLEANUP_NO_INSN_DEL);
704 if (!need_commit && !emited)
711 #endif /* OPTIMIZE_MODE_SWITCHING */
714 gate_mode_switching (void)
716 #ifdef OPTIMIZE_MODE_SWITCHING
724 rest_of_handle_mode_switching (void)
726 #ifdef OPTIMIZE_MODE_SWITCHING
728 optimize_mode_switching ();
730 #endif /* OPTIMIZE_MODE_SWITCHING */
735 struct tree_opt_pass pass_mode_switching =
737 "mode-sw", /* name */
738 gate_mode_switching, /* gate */
739 rest_of_handle_mode_switching, /* execute */
742 0, /* static_pass_number */
743 TV_MODE_SWITCH, /* tv_id */
744 0, /* properties_required */
745 0, /* properties_provided */
746 0, /* properties_destroyed */
747 0, /* todo_flags_start */
749 TODO_dump_func, /* todo_flags_finish */