1 @c Copyright (C) 1988, 89, 92, 93, 94, 96, 1998, 2000 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Patterns:: How to write instruction patterns.
23 * Example:: An explained example of a @code{define_insn} pattern.
24 * RTL Template:: The RTL template defines what insns match a pattern.
25 * Output Template:: The output template says how to make assembler code
27 * Output Statement:: For more generality, write C code to output
29 * Constraints:: When not all operands are general operands.
30 * Standard Names:: Names mark patterns to use for code generation.
31 * Pattern Ordering:: When the order of patterns makes a difference.
32 * Dependent Patterns:: Having one pattern may make you need another.
33 * Jump Patterns:: Special considerations for patterns for jump insns.
34 * Insn Canonicalizations::Canonicalization of Instructions
35 * Expander Definitions::Generating a sequence of several RTL insns
36 for a standard operation.
37 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
38 * Peephole Definitions::Defining machine-specific peephole optimizations.
39 * Insn Attributes:: Specifying the value of attributes for generated insns.
40 * Conditional Execution::Generating @code{define_insn} patterns for
42 * Constant Definitions::Defining symbolic constants that can be used in the
47 @section Everything about Instruction Patterns
49 @cindex instruction patterns
52 Each instruction pattern contains an incomplete RTL expression, with pieces
53 to be filled in later, operand constraints that restrict how the pieces can
54 be filled in, and an output pattern or C code to generate the assembler
55 output, all wrapped up in a @code{define_insn} expression.
57 A @code{define_insn} is an RTL expression containing four or five operands:
61 An optional name. The presence of a name indicate that this instruction
62 pattern can perform a certain standard job for the RTL-generation
63 pass of the compiler. This pass knows certain names and will use
64 the instruction patterns with those names, if the names are defined
65 in the machine description.
67 The absence of a name is indicated by writing an empty string
68 where the name should go. Nameless instruction patterns are never
69 used for generating RTL code, but they may permit several simpler insns
70 to be combined later on.
72 Names that are not thus known and used in RTL-generation have no
73 effect; they are equivalent to no name at all.
75 For the purpose of debugging the compiler, you may also specify a
76 name beginning with the @samp{*} character. Such a name is used only
77 for identifying the instruction in RTL dumps; it is entirely equivalent
78 to having a nameless pattern for all other purposes.
81 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
82 RTL expressions which show what the instruction should look like. It is
83 incomplete because it may contain @code{match_operand},
84 @code{match_operator}, and @code{match_dup} expressions that stand for
85 operands of the instruction.
87 If the vector has only one element, that element is the template for the
88 instruction pattern. If the vector has multiple elements, then the
89 instruction pattern is a @code{parallel} expression containing the
93 @cindex pattern conditions
94 @cindex conditions, in patterns
95 A condition. This is a string which contains a C expression that is
96 the final test to decide whether an insn body matches this pattern.
98 @cindex named patterns and conditions
99 For a named pattern, the condition (if present) may not depend on
100 the data in the insn being matched, but only the target-machine-type
101 flags. The compiler needs to test these conditions during
102 initialization in order to learn exactly which named instructions are
103 available in a particular run.
106 For nameless patterns, the condition is applied only when matching an
107 individual insn, and only after the insn has matched the pattern's
108 recognition template. The insn's operands may be found in the vector
112 The @dfn{output template}: a string that says how to output matching
113 insns as assembler code. @samp{%} in this string specifies where
114 to substitute the value of an operand. @xref{Output Template}.
116 When simple substitution isn't general enough, you can specify a piece
117 of C code to compute the output. @xref{Output Statement}.
120 Optionally, a vector containing the values of attributes for insns matching
121 this pattern. @xref{Insn Attributes}.
125 @section Example of @code{define_insn}
126 @cindex @code{define_insn} example
128 Here is an actual example of an instruction pattern, for the 68000/68020.
133 (match_operand:SI 0 "general_operand" "rm"))]
136 @{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
138 return \"cmpl #0,%0\"; @}")
141 This is an instruction that sets the condition codes based on the value of
142 a general operand. It has no condition, so any insn whose RTL description
143 has the form shown may be handled according to this pattern. The name
144 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
145 pass that, when it is necessary to test such a value, an insn to do so
146 can be constructed using this pattern.
148 The output control string is a piece of C code which chooses which
149 output template to return based on the kind of operand and the specific
150 type of CPU for which code is being generated.
152 @samp{"rm"} is an operand constraint. Its meaning is explained below.
155 @section RTL Template
156 @cindex RTL insn template
157 @cindex generating insns
158 @cindex insns, generating
159 @cindex recognizing insns
160 @cindex insns, recognizing
162 The RTL template is used to define which insns match the particular pattern
163 and how to find their operands. For named patterns, the RTL template also
164 says how to construct an insn from specified operands.
166 Construction involves substituting specified operands into a copy of the
167 template. Matching involves determining the values that serve as the
168 operands in the insn being matched. Both of these activities are
169 controlled by special expression types that direct matching and
170 substitution of the operands.
173 @findex match_operand
174 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
175 This expression is a placeholder for operand number @var{n} of
176 the insn. When constructing an insn, operand number @var{n}
177 will be substituted at this point. When matching an insn, whatever
178 appears at this position in the insn will be taken as operand
179 number @var{n}; but it must satisfy @var{predicate} or this instruction
180 pattern will not match at all.
182 Operand numbers must be chosen consecutively counting from zero in
183 each instruction pattern. There may be only one @code{match_operand}
184 expression in the pattern for each operand number. Usually operands
185 are numbered in the order of appearance in @code{match_operand}
186 expressions. In the case of a @code{define_expand}, any operand numbers
187 used only in @code{match_dup} expressions have higher values than all
188 other operand numbers.
190 @var{predicate} is a string that is the name of a C function that accepts two
191 arguments, an expression and a machine mode. During matching, the
192 function will be called with the putative operand as the expression and
193 @var{m} as the mode argument (if @var{m} is not specified,
194 @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
195 any mode). If it returns zero, this instruction pattern fails to match.
196 @var{predicate} may be an empty string; then it means no test is to be done
197 on the operand, so anything which occurs in this position is valid.
199 Most of the time, @var{predicate} will reject modes other than @var{m}---but
200 not always. For example, the predicate @code{address_operand} uses
201 @var{m} as the mode of memory ref that the address should be valid for.
202 Many predicates accept @code{const_int} nodes even though their mode is
205 @var{constraint} controls reloading and the choice of the best register
206 class to use for a value, as explained later (@pxref{Constraints}).
208 People are often unclear on the difference between the constraint and the
209 predicate. The predicate helps decide whether a given insn matches the
210 pattern. The constraint plays no role in this decision; instead, it
211 controls various decisions in the case of an insn which does match.
213 @findex general_operand
214 On CISC machines, the most common @var{predicate} is
215 @code{"general_operand"}. This function checks that the putative
216 operand is either a constant, a register or a memory reference, and that
217 it is valid for mode @var{m}.
219 @findex register_operand
220 For an operand that must be a register, @var{predicate} should be
221 @code{"register_operand"}. Using @code{"general_operand"} would be
222 valid, since the reload pass would copy any non-register operands
223 through registers, but this would make GNU CC do extra work, it would
224 prevent invariant operands (such as constant) from being removed from
225 loops, and it would prevent the register allocator from doing the best
226 possible job. On RISC machines, it is usually most efficient to allow
227 @var{predicate} to accept only objects that the constraints allow.
229 @findex immediate_operand
230 For an operand that must be a constant, you must be sure to either use
231 @code{"immediate_operand"} for @var{predicate}, or make the instruction
232 pattern's extra condition require a constant, or both. You cannot
233 expect the constraints to do this work! If the constraints allow only
234 constants, but the predicate allows something else, the compiler will
235 crash when that case arises.
237 @findex match_scratch
238 @item (match_scratch:@var{m} @var{n} @var{constraint})
239 This expression is also a placeholder for operand number @var{n}
240 and indicates that operand must be a @code{scratch} or @code{reg}
243 When matching patterns, this is equivalent to
246 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
249 but, when generating RTL, it produces a (@code{scratch}:@var{m})
252 If the last few expressions in a @code{parallel} are @code{clobber}
253 expressions whose operands are either a hard register or
254 @code{match_scratch}, the combiner can add or delete them when
255 necessary. @xref{Side Effects}.
258 @item (match_dup @var{n})
259 This expression is also a placeholder for operand number @var{n}.
260 It is used when the operand needs to appear more than once in the
263 In construction, @code{match_dup} acts just like @code{match_operand}:
264 the operand is substituted into the insn being constructed. But in
265 matching, @code{match_dup} behaves differently. It assumes that operand
266 number @var{n} has already been determined by a @code{match_operand}
267 appearing earlier in the recognition template, and it matches only an
268 identical-looking expression.
270 @findex match_operator
271 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
272 This pattern is a kind of placeholder for a variable RTL expression
275 When constructing an insn, it stands for an RTL expression whose
276 expression code is taken from that of operand @var{n}, and whose
277 operands are constructed from the patterns @var{operands}.
279 When matching an expression, it matches an expression if the function
280 @var{predicate} returns nonzero on that expression @emph{and} the
281 patterns @var{operands} match the operands of the expression.
283 Suppose that the function @code{commutative_operator} is defined as
284 follows, to match any expression whose operator is one of the
285 commutative arithmetic operators of RTL and whose mode is @var{mode}:
289 commutative_operator (x, mode)
291 enum machine_mode mode;
293 enum rtx_code code = GET_CODE (x);
294 if (GET_MODE (x) != mode)
296 return (GET_RTX_CLASS (code) == 'c'
297 || code == EQ || code == NE);
301 Then the following pattern will match any RTL expression consisting
302 of a commutative operator applied to two general operands:
305 (match_operator:SI 3 "commutative_operator"
306 [(match_operand:SI 1 "general_operand" "g")
307 (match_operand:SI 2 "general_operand" "g")])
310 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
311 because the expressions to be matched all contain two operands.
313 When this pattern does match, the two operands of the commutative
314 operator are recorded as operands 1 and 2 of the insn. (This is done
315 by the two instances of @code{match_operand}.) Operand 3 of the insn
316 will be the entire commutative expression: use @code{GET_CODE
317 (operands[3])} to see which commutative operator was used.
319 The machine mode @var{m} of @code{match_operator} works like that of
320 @code{match_operand}: it is passed as the second argument to the
321 predicate function, and that function is solely responsible for
322 deciding whether the expression to be matched ``has'' that mode.
324 When constructing an insn, argument 3 of the gen-function will specify
325 the operation (i.e. the expression code) for the expression to be
326 made. It should be an RTL expression, whose expression code is copied
327 into a new expression whose operands are arguments 1 and 2 of the
328 gen-function. The subexpressions of argument 3 are not used;
329 only its expression code matters.
331 When @code{match_operator} is used in a pattern for matching an insn,
332 it usually best if the operand number of the @code{match_operator}
333 is higher than that of the actual operands of the insn. This improves
334 register allocation because the register allocator often looks at
335 operands 1 and 2 of insns to see if it can do register tying.
337 There is no way to specify constraints in @code{match_operator}. The
338 operand of the insn which corresponds to the @code{match_operator}
339 never has any constraints because it is never reloaded as a whole.
340 However, if parts of its @var{operands} are matched by
341 @code{match_operand} patterns, those parts may have constraints of
345 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
346 Like @code{match_dup}, except that it applies to operators instead of
347 operands. When constructing an insn, operand number @var{n} will be
348 substituted at this point. But in matching, @code{match_op_dup} behaves
349 differently. It assumes that operand number @var{n} has already been
350 determined by a @code{match_operator} appearing earlier in the
351 recognition template, and it matches only an identical-looking
354 @findex match_parallel
355 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
356 This pattern is a placeholder for an insn that consists of a
357 @code{parallel} expression with a variable number of elements. This
358 expression should only appear at the top level of an insn pattern.
360 When constructing an insn, operand number @var{n} will be substituted at
361 this point. When matching an insn, it matches if the body of the insn
362 is a @code{parallel} expression with at least as many elements as the
363 vector of @var{subpat} expressions in the @code{match_parallel}, if each
364 @var{subpat} matches the corresponding element of the @code{parallel},
365 @emph{and} the function @var{predicate} returns nonzero on the
366 @code{parallel} that is the body of the insn. It is the responsibility
367 of the predicate to validate elements of the @code{parallel} beyond
368 those listed in the @code{match_parallel}.@refill
370 A typical use of @code{match_parallel} is to match load and store
371 multiple expressions, which can contain a variable number of elements
372 in a @code{parallel}. For example,
373 @c the following is *still* going over. need to change the code.
374 @c also need to work on grouping of this example. --mew 1feb93
378 [(match_parallel 0 "load_multiple_operation"
379 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
380 (match_operand:SI 2 "memory_operand" "m"))
382 (clobber (reg:SI 179))])]
387 This example comes from @file{a29k.md}. The function
388 @code{load_multiple_operations} is defined in @file{a29k.c} and checks
389 that subsequent elements in the @code{parallel} are the same as the
390 @code{set} in the pattern, except that they are referencing subsequent
391 registers and memory locations.
393 An insn that matches this pattern might look like:
397 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
399 (clobber (reg:SI 179))
401 (mem:SI (plus:SI (reg:SI 100)
404 (mem:SI (plus:SI (reg:SI 100)
408 @findex match_par_dup
409 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
410 Like @code{match_op_dup}, but for @code{match_parallel} instead of
411 @code{match_operator}.
414 @item (match_insn @var{predicate})
415 Match a complete insn. Unlike the other @code{match_*} recognizers,
416 @code{match_insn} does not take an operand number.
418 The machine mode @var{m} of @code{match_insn} works like that of
419 @code{match_operand}: it is passed as the second argument to the
420 predicate function, and that function is solely responsible for
421 deciding whether the expression to be matched ``has'' that mode.
424 @item (match_insn2 @var{n} @var{predicate})
425 Match a complete insn.
427 The machine mode @var{m} of @code{match_insn2} works like that of
428 @code{match_operand}: it is passed as the second argument to the
429 predicate function, and that function is solely responsible for
430 deciding whether the expression to be matched ``has'' that mode.
434 @node Output Template
435 @section Output Templates and Operand Substitution
436 @cindex output templates
437 @cindex operand substitution
439 @cindex @samp{%} in template
441 The @dfn{output template} is a string which specifies how to output the
442 assembler code for an instruction pattern. Most of the template is a
443 fixed string which is output literally. The character @samp{%} is used
444 to specify where to substitute an operand; it can also be used to
445 identify places where different variants of the assembler require
448 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
449 operand @var{n} at that point in the string.
451 @samp{%} followed by a letter and a digit says to output an operand in an
452 alternate fashion. Four letters have standard, built-in meanings described
453 below. The machine description macro @code{PRINT_OPERAND} can define
454 additional letters with nonstandard meanings.
456 @samp{%c@var{digit}} can be used to substitute an operand that is a
457 constant value without the syntax that normally indicates an immediate
460 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
461 the constant is negated before printing.
463 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
464 memory reference, with the actual operand treated as the address. This may
465 be useful when outputting a ``load address'' instruction, because often the
466 assembler syntax for such an instruction requires you to write the operand
467 as if it were a memory reference.
469 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
472 @samp{%=} outputs a number which is unique to each instruction in the
473 entire compilation. This is useful for making local labels to be
474 referred to more than once in a single template that generates multiple
475 assembler instructions.
477 @samp{%} followed by a punctuation character specifies a substitution that
478 does not use an operand. Only one case is standard: @samp{%%} outputs a
479 @samp{%} into the assembler code. Other nonstandard cases can be
480 defined in the @code{PRINT_OPERAND} macro. You must also define
481 which punctuation characters are valid with the
482 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
486 The template may generate multiple assembler instructions. Write the text
487 for the instructions, with @samp{\;} between them.
489 @cindex matching operands
490 When the RTL contains two operands which are required by constraint to match
491 each other, the output template must refer only to the lower-numbered operand.
492 Matching operands are not always identical, and the rest of the compiler
493 arranges to put the proper RTL expression for printing into the lower-numbered
496 One use of nonstandard letters or punctuation following @samp{%} is to
497 distinguish between different assembler languages for the same machine; for
498 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
499 requires periods in most opcode names, while MIT syntax does not. For
500 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
501 syntax. The same file of patterns is used for both kinds of output syntax,
502 but the character sequence @samp{%.} is used in each place where Motorola
503 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
504 defines the sequence to output a period; the macro for MIT syntax defines
507 @cindex @code{#} in template
508 As a special case, a template consisting of the single character @code{#}
509 instructs the compiler to first split the insn, and then output the
510 resulting instructions separately. This helps eliminate redundancy in the
511 output templates. If you have a @code{define_insn} that needs to emit
512 multiple assembler instructions, and there is an matching @code{define_split}
513 already defined, then you can simply use @code{#} as the output template
514 instead of writing an output template that emits the multiple assembler
517 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
518 of the form @samp{@{option0|option1|option2@}} in the templates. These
519 describe multiple variants of assembler language syntax.
520 @xref{Instruction Output}.
522 @node Output Statement
523 @section C Statements for Assembler Output
524 @cindex output statements
525 @cindex C statements for assembler output
526 @cindex generating assembler output
528 Often a single fixed template string cannot produce correct and efficient
529 assembler code for all the cases that are recognized by a single
530 instruction pattern. For example, the opcodes may depend on the kinds of
531 operands; or some unfortunate combinations of operands may require extra
532 machine instructions.
534 If the output control string starts with a @samp{@@}, then it is actually
535 a series of templates, each on a separate line. (Blank lines and
536 leading spaces and tabs are ignored.) The templates correspond to the
537 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
538 if a target machine has a two-address add instruction @samp{addr} to add
539 into a register and another @samp{addm} to add a register to memory, you
540 might write this pattern:
543 (define_insn "addsi3"
544 [(set (match_operand:SI 0 "general_operand" "=r,m")
545 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
546 (match_operand:SI 2 "general_operand" "g,r")))]
553 @cindex @code{*} in template
554 @cindex asterisk in template
555 If the output control string starts with a @samp{*}, then it is not an
556 output template but rather a piece of C program that should compute a
557 template. It should execute a @code{return} statement to return the
558 template-string you want. Most such templates use C string literals, which
559 require doublequote characters to delimit them. To include these
560 doublequote characters in the string, prefix each one with @samp{\}.
562 The operands may be found in the array @code{operands}, whose C data type
565 It is very common to select different ways of generating assembler code
566 based on whether an immediate operand is within a certain range. Be
567 careful when doing this, because the result of @code{INTVAL} is an
568 integer on the host machine. If the host machine has more bits in an
569 @code{int} than the target machine has in the mode in which the constant
570 will be used, then some of the bits you get from @code{INTVAL} will be
571 superfluous. For proper results, you must carefully disregard the
572 values of those bits.
574 @findex output_asm_insn
575 It is possible to output an assembler instruction and then go on to output
576 or compute more of them, using the subroutine @code{output_asm_insn}. This
577 receives two arguments: a template-string and a vector of operands. The
578 vector may be @code{operands}, or it may be another array of @code{rtx}
579 that you declare locally and initialize yourself.
581 @findex which_alternative
582 When an insn pattern has multiple alternatives in its constraints, often
583 the appearance of the assembler code is determined mostly by which alternative
584 was matched. When this is so, the C code can test the variable
585 @code{which_alternative}, which is the ordinal number of the alternative
586 that was actually satisfied (0 for the first, 1 for the second alternative,
589 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
590 for registers and @samp{clrmem} for memory locations. Here is how
591 a pattern could use @code{which_alternative} to choose between them:
595 [(set (match_operand:SI 0 "general_operand" "=r,m")
599 return (which_alternative == 0
600 ? \"clrreg %0\" : \"clrmem %0\");
604 The example above, where the assembler code to generate was
605 @emph{solely} determined by the alternative, could also have been specified
606 as follows, having the output control string start with a @samp{@@}:
611 [(set (match_operand:SI 0 "general_operand" "=r,m")
621 @c Most of this node appears by itself (in a different place) even
622 @c when the INTERNALS flag is clear. Passages that require the full
623 @c manual's context are conditionalized to appear only in the full manual.
626 @section Operand Constraints
627 @cindex operand constraints
630 Each @code{match_operand} in an instruction pattern can specify a
631 constraint for the type of operands allowed.
635 @section Constraints for @code{asm} Operands
636 @cindex operand constraints, @code{asm}
637 @cindex constraints, @code{asm}
638 @cindex @code{asm} constraints
640 Here are specific details on what constraint letters you can use with
643 Constraints can say whether
644 an operand may be in a register, and which kinds of register; whether the
645 operand can be a memory reference, and which kinds of address; whether the
646 operand may be an immediate constant, and which possible values it may
647 have. Constraints can also require two operands to match.
651 * Simple Constraints:: Basic use of constraints.
652 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
653 * Class Preferences:: Constraints guide which hard register to put things in.
654 * Modifiers:: More precise control over effects of constraints.
655 * Machine Constraints:: Existing constraints for some particular machines.
661 * Simple Constraints:: Basic use of constraints.
662 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
663 * Modifiers:: More precise control over effects of constraints.
664 * Machine Constraints:: Special constraints for some particular machines.
668 @node Simple Constraints
669 @subsection Simple Constraints
670 @cindex simple constraints
672 The simplest kind of constraint is a string full of letters, each of
673 which describes one kind of operand that is permitted. Here are
674 the letters that are allowed:
678 Whitespace characters are ignored and can be inserted at any position
679 except the first. This enables each alternative for different operands to
680 be visually aligned in the machine description even if they have different
681 number of constraints and modifiers.
683 @cindex @samp{m} in constraint
684 @cindex memory references in constraints
686 A memory operand is allowed, with any kind of address that the machine
689 @cindex offsettable address
690 @cindex @samp{o} in constraint
692 A memory operand is allowed, but only if the address is
693 @dfn{offsettable}. This means that adding a small integer (actually,
694 the width in bytes of the operand, as determined by its machine mode)
695 may be added to the address and the result is also a valid memory
698 @cindex autoincrement/decrement addressing
699 For example, an address which is constant is offsettable; so is an
700 address that is the sum of a register and a constant (as long as a
701 slightly larger constant is also within the range of address-offsets
702 supported by the machine); but an autoincrement or autodecrement
703 address is not offsettable. More complicated indirect/indexed
704 addresses may or may not be offsettable depending on the other
705 addressing modes that the machine supports.
707 Note that in an output operand which can be matched by another
708 operand, the constraint letter @samp{o} is valid only when accompanied
709 by both @samp{<} (if the target machine has predecrement addressing)
710 and @samp{>} (if the target machine has preincrement addressing).
712 @cindex @samp{V} in constraint
714 A memory operand that is not offsettable. In other words, anything that
715 would fit the @samp{m} constraint but not the @samp{o} constraint.
717 @cindex @samp{<} in constraint
719 A memory operand with autodecrement addressing (either predecrement or
720 postdecrement) is allowed.
722 @cindex @samp{>} in constraint
724 A memory operand with autoincrement addressing (either preincrement or
725 postincrement) is allowed.
727 @cindex @samp{r} in constraint
728 @cindex registers in constraints
730 A register operand is allowed provided that it is in a general
733 @cindex constants in constraints
734 @cindex @samp{i} in constraint
736 An immediate integer operand (one with constant value) is allowed.
737 This includes symbolic constants whose values will be known only at
740 @cindex @samp{n} in constraint
742 An immediate integer operand with a known numeric value is allowed.
743 Many systems cannot support assembly-time constants for operands less
744 than a word wide. Constraints for these operands should use @samp{n}
745 rather than @samp{i}.
747 @cindex @samp{I} in constraint
748 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
749 Other letters in the range @samp{I} through @samp{P} may be defined in
750 a machine-dependent fashion to permit immediate integer operands with
751 explicit integer values in specified ranges. For example, on the
752 68000, @samp{I} is defined to stand for the range of values 1 to 8.
753 This is the range permitted as a shift count in the shift
756 @cindex @samp{E} in constraint
758 An immediate floating operand (expression code @code{const_double}) is
759 allowed, but only if the target floating point format is the same as
760 that of the host machine (on which the compiler is running).
762 @cindex @samp{F} in constraint
764 An immediate floating operand (expression code @code{const_double}) is
767 @cindex @samp{G} in constraint
768 @cindex @samp{H} in constraint
769 @item @samp{G}, @samp{H}
770 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
771 permit immediate floating operands in particular ranges of values.
773 @cindex @samp{s} in constraint
775 An immediate integer operand whose value is not an explicit integer is
778 This might appear strange; if an insn allows a constant operand with a
779 value not known at compile time, it certainly must allow any known
780 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
781 better code to be generated.
783 For example, on the 68000 in a fullword instruction it is possible to
784 use an immediate operand; but if the immediate value is between -128
785 and 127, better code results from loading the value into a register and
786 using the register. This is because the load into the register can be
787 done with a @samp{moveq} instruction. We arrange for this to happen
788 by defining the letter @samp{K} to mean ``any integer outside the
789 range -128 to 127'', and then specifying @samp{Ks} in the operand
792 @cindex @samp{g} in constraint
794 Any register, memory or immediate integer operand is allowed, except for
795 registers that are not general registers.
797 @cindex @samp{X} in constraint
800 Any operand whatsoever is allowed, even if it does not satisfy
801 @code{general_operand}. This is normally used in the constraint of
802 a @code{match_scratch} when certain alternatives will not actually
803 require a scratch register.
806 Any operand whatsoever is allowed.
809 @cindex @samp{0} in constraint
810 @cindex digits in constraint
811 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
812 An operand that matches the specified operand number is allowed. If a
813 digit is used together with letters within the same alternative, the
814 digit should come last.
816 @cindex matching constraint
817 @cindex constraint, matching
818 This is called a @dfn{matching constraint} and what it really means is
819 that the assembler has only a single operand that fills two roles
821 considered separate in the RTL insn. For example, an add insn has two
822 input operands and one output operand in the RTL, but on most CISC
825 which @code{asm} distinguishes. For example, an add instruction uses
826 two input operands and an output operand, but on most CISC
828 machines an add instruction really has only two operands, one of them an
829 input-output operand:
835 Matching constraints are used in these circumstances.
836 More precisely, the two operands that match must include one input-only
837 operand and one output-only operand. Moreover, the digit must be a
838 smaller number than the number of the operand that uses it in the
842 For operands to match in a particular case usually means that they
843 are identical-looking RTL expressions. But in a few special cases
844 specific kinds of dissimilarity are allowed. For example, @code{*x}
845 as an input operand will match @code{*x++} as an output operand.
846 For proper results in such cases, the output template should always
847 use the output-operand's number when printing the operand.
850 @cindex load address instruction
851 @cindex push address instruction
852 @cindex address constraints
853 @cindex @samp{p} in constraint
855 An operand that is a valid memory address is allowed. This is
856 for ``load address'' and ``push address'' instructions.
858 @findex address_operand
859 @samp{p} in the constraint must be accompanied by @code{address_operand}
860 as the predicate in the @code{match_operand}. This predicate interprets
861 the mode specified in the @code{match_operand} as the mode of the memory
862 reference for which the address would be valid.
864 @cindex other register constraints
865 @cindex extensible constraints
866 @item @var{other letters}
867 Other letters can be defined in machine-dependent fashion to stand for
868 particular classes of registers or other arbitrary operand types.
869 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
870 for data, address and floating point registers.
873 The machine description macro @code{REG_CLASS_FROM_LETTER} has first
874 cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
875 then @code{EXTRA_CONSTRAINT} is evaluated.
877 A typical use for @code{EXTRA_CONSTRANT} would be to distinguish certain
878 types of memory references that affect other insn operands.
883 In order to have valid assembler code, each operand must satisfy
884 its constraint. But a failure to do so does not prevent the pattern
885 from applying to an insn. Instead, it directs the compiler to modify
886 the code so that the constraint will be satisfied. Usually this is
887 done by copying an operand into a register.
889 Contrast, therefore, the two instruction patterns that follow:
893 [(set (match_operand:SI 0 "general_operand" "=r")
894 (plus:SI (match_dup 0)
895 (match_operand:SI 1 "general_operand" "r")))]
901 which has two operands, one of which must appear in two places, and
905 [(set (match_operand:SI 0 "general_operand" "=r")
906 (plus:SI (match_operand:SI 1 "general_operand" "0")
907 (match_operand:SI 2 "general_operand" "r")))]
913 which has three operands, two of which are required by a constraint to be
914 identical. If we are considering an insn of the form
917 (insn @var{n} @var{prev} @var{next}
919 (plus:SI (reg:SI 6) (reg:SI 109)))
924 the first pattern would not apply at all, because this insn does not
925 contain two identical subexpressions in the right place. The pattern would
926 say, ``That does not look like an add instruction; try other patterns.''
927 The second pattern would say, ``Yes, that's an add instruction, but there
928 is something wrong with it.'' It would direct the reload pass of the
929 compiler to generate additional insns to make the constraint true. The
930 results might look like this:
933 (insn @var{n2} @var{prev} @var{n}
934 (set (reg:SI 3) (reg:SI 6))
937 (insn @var{n} @var{n2} @var{next}
939 (plus:SI (reg:SI 3) (reg:SI 109)))
943 It is up to you to make sure that each operand, in each pattern, has
944 constraints that can handle any RTL expression that could be present for
945 that operand. (When multiple alternatives are in use, each pattern must,
946 for each possible combination of operand expressions, have at least one
947 alternative which can handle that combination of operands.) The
948 constraints don't need to @emph{allow} any possible operand---when this is
949 the case, they do not constrain---but they must at least point the way to
950 reloading any possible operand so that it will fit.
954 If the constraint accepts whatever operands the predicate permits,
955 there is no problem: reloading is never necessary for this operand.
957 For example, an operand whose constraints permit everything except
958 registers is safe provided its predicate rejects registers.
960 An operand whose predicate accepts only constant values is safe
961 provided its constraints include the letter @samp{i}. If any possible
962 constant value is accepted, then nothing less than @samp{i} will do;
963 if the predicate is more selective, then the constraints may also be
967 Any operand expression can be reloaded by copying it into a register.
968 So if an operand's constraints allow some kind of register, it is
969 certain to be safe. It need not permit all classes of registers; the
970 compiler knows how to copy a register into another register of the
971 proper class in order to make an instruction valid.
973 @cindex nonoffsettable memory reference
974 @cindex memory reference, nonoffsettable
976 A nonoffsettable memory reference can be reloaded by copying the
977 address into a register. So if the constraint uses the letter
978 @samp{o}, all memory references are taken care of.
981 A constant operand can be reloaded by allocating space in memory to
982 hold it as preinitialized data. Then the memory reference can be used
983 in place of the constant. So if the constraint uses the letters
984 @samp{o} or @samp{m}, constant operands are not a problem.
987 If the constraint permits a constant and a pseudo register used in an insn
988 was not allocated to a hard register and is equivalent to a constant,
989 the register will be replaced with the constant. If the predicate does
990 not permit a constant and the insn is re-recognized for some reason, the
991 compiler will crash. Thus the predicate must always recognize any
992 objects allowed by the constraint.
995 If the operand's predicate can recognize registers, but the constraint does
996 not permit them, it can make the compiler crash. When this operand happens
997 to be a register, the reload pass will be stymied, because it does not know
998 how to copy a register temporarily into memory.
1000 If the predicate accepts a unary operator, the constraint applies to the
1001 operand. For example, the MIPS processor at ISA level 3 supports an
1002 instruction which adds two registers in @code{SImode} to produce a
1003 @code{DImode} result, but only if the registers are correctly sign
1004 extended. This predicate for the input operands accepts a
1005 @code{sign_extend} of an @code{SImode} register. Write the constraint
1006 to indicate the type of register that is required for the operand of the
1010 @node Multi-Alternative
1011 @subsection Multiple Alternative Constraints
1012 @cindex multiple alternative constraints
1014 Sometimes a single instruction has multiple alternative sets of possible
1015 operands. For example, on the 68000, a logical-or instruction can combine
1016 register or an immediate value into memory, or it can combine any kind of
1017 operand into a register; but it cannot combine one memory location into
1020 These constraints are represented as multiple alternatives. An alternative
1021 can be described by a series of letters for each operand. The overall
1022 constraint for an operand is made from the letters for this operand
1023 from the first alternative, a comma, the letters for this operand from
1024 the second alternative, a comma, and so on until the last alternative.
1026 Here is how it is done for fullword logical-or on the 68000:
1029 (define_insn "iorsi3"
1030 [(set (match_operand:SI 0 "general_operand" "=m,d")
1031 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1032 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1036 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1037 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1038 2. The second alternative has @samp{d} (data register) for operand 0,
1039 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1040 @samp{%} in the constraints apply to all the alternatives; their
1041 meaning is explained in the next section (@pxref{Class Preferences}).
1044 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1045 If all the operands fit any one alternative, the instruction is valid.
1046 Otherwise, for each alternative, the compiler counts how many instructions
1047 must be added to copy the operands so that that alternative applies.
1048 The alternative requiring the least copying is chosen. If two alternatives
1049 need the same amount of copying, the one that comes first is chosen.
1050 These choices can be altered with the @samp{?} and @samp{!} characters:
1053 @cindex @samp{?} in constraint
1054 @cindex question mark
1056 Disparage slightly the alternative that the @samp{?} appears in,
1057 as a choice when no alternative applies exactly. The compiler regards
1058 this alternative as one unit more costly for each @samp{?} that appears
1061 @cindex @samp{!} in constraint
1062 @cindex exclamation point
1064 Disparage severely the alternative that the @samp{!} appears in.
1065 This alternative can still be used if it fits without reloading,
1066 but if reloading is needed, some other alternative will be used.
1070 When an insn pattern has multiple alternatives in its constraints, often
1071 the appearance of the assembler code is determined mostly by which
1072 alternative was matched. When this is so, the C code for writing the
1073 assembler code can use the variable @code{which_alternative}, which is
1074 the ordinal number of the alternative that was actually satisfied (0 for
1075 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1079 @node Class Preferences
1080 @subsection Register Class Preferences
1081 @cindex class preference constraints
1082 @cindex register class preference constraints
1084 @cindex voting between constraint alternatives
1085 The operand constraints have another function: they enable the compiler
1086 to decide which kind of hardware register a pseudo register is best
1087 allocated to. The compiler examines the constraints that apply to the
1088 insns that use the pseudo register, looking for the machine-dependent
1089 letters such as @samp{d} and @samp{a} that specify classes of registers.
1090 The pseudo register is put in whichever class gets the most ``votes''.
1091 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1092 favor of a general register. The machine description says which registers
1093 are considered general.
1095 Of course, on some machines all registers are equivalent, and no register
1096 classes are defined. Then none of this complexity is relevant.
1100 @subsection Constraint Modifier Characters
1101 @cindex modifiers in constraints
1102 @cindex constraint modifier characters
1104 @c prevent bad page break with this line
1105 Here are constraint modifier characters.
1108 @cindex @samp{=} in constraint
1110 Means that this operand is write-only for this instruction: the previous
1111 value is discarded and replaced by output data.
1113 @cindex @samp{+} in constraint
1115 Means that this operand is both read and written by the instruction.
1117 When the compiler fixes up the operands to satisfy the constraints,
1118 it needs to know which operands are inputs to the instruction and
1119 which are outputs from it. @samp{=} identifies an output; @samp{+}
1120 identifies an operand that is both input and output; all other operands
1121 are assumed to be input only.
1123 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1124 first character of the constraint string.
1126 @cindex @samp{&} in constraint
1127 @cindex earlyclobber operand
1129 Means (in a particular alternative) that this operand is an
1130 @dfn{earlyclobber} operand, which is modified before the instruction is
1131 finished using the input operands. Therefore, this operand may not lie
1132 in a register that is used as an input operand or as part of any memory
1135 @samp{&} applies only to the alternative in which it is written. In
1136 constraints with multiple alternatives, sometimes one alternative
1137 requires @samp{&} while others do not. See, for example, the
1138 @samp{movdf} insn of the 68000.
1140 An input operand can be tied to an earlyclobber operand if its only
1141 use as an input occurs before the early result is written. Adding
1142 alternatives of this form often allows GCC to produce better code
1143 when only some of the inputs can be affected by the earlyclobber.
1144 See, for example, the @samp{mulsi3} insn of the ARM.
1146 @samp{&} does not obviate the need to write @samp{=}.
1148 @cindex @samp{%} in constraint
1150 Declares the instruction to be commutative for this operand and the
1151 following operand. This means that the compiler may interchange the
1152 two operands if that is the cheapest way to make all operands fit the
1155 This is often used in patterns for addition instructions
1156 that really have only two operands: the result must go in one of the
1157 arguments. Here for example, is how the 68000 halfword-add
1158 instruction is defined:
1161 (define_insn "addhi3"
1162 [(set (match_operand:HI 0 "general_operand" "=m,r")
1163 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1164 (match_operand:HI 2 "general_operand" "di,g")))]
1169 @cindex @samp{#} in constraint
1171 Says that all following characters, up to the next comma, are to be
1172 ignored as a constraint. They are significant only for choosing
1173 register preferences.
1176 @cindex @samp{*} in constraint
1178 Says that the following character should be ignored when choosing
1179 register preferences. @samp{*} has no effect on the meaning of the
1180 constraint as a constraint, and no effect on reloading.
1182 Here is an example: the 68000 has an instruction to sign-extend a
1183 halfword in a data register, and can also sign-extend a value by
1184 copying it into an address register. While either kind of register is
1185 acceptable, the constraints on an address-register destination are
1186 less strict, so it is best if register allocation makes an address
1187 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1188 constraint letter (for data register) is ignored when computing
1189 register preferences.
1192 (define_insn "extendhisi2"
1193 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1195 (match_operand:HI 1 "general_operand" "0,g")))]
1201 @node Machine Constraints
1202 @subsection Constraints for Particular Machines
1203 @cindex machine specific constraints
1204 @cindex constraints, machine specific
1206 Whenever possible, you should use the general-purpose constraint letters
1207 in @code{asm} arguments, since they will convey meaning more readily to
1208 people reading your code. Failing that, use the constraint letters
1209 that usually have very similar meanings across architectures. The most
1210 commonly used constraints are @samp{m} and @samp{r} (for memory and
1211 general-purpose registers respectively; @pxref{Simple Constraints}), and
1212 @samp{I}, usually the letter indicating the most common
1213 immediate-constant format.
1215 For each machine architecture, the @file{config/@var{machine}.h} file
1216 defines additional constraints. These constraints are used by the
1217 compiler itself for instruction generation, as well as for @code{asm}
1218 statements; therefore, some of the constraints are not particularly
1219 interesting for @code{asm}. The constraints are defined through these
1223 @item REG_CLASS_FROM_LETTER
1224 Register class constraints (usually lower case).
1226 @item CONST_OK_FOR_LETTER_P
1227 Immediate constant constraints, for non-floating point constants of
1228 word size or smaller precision (usually upper case).
1230 @item CONST_DOUBLE_OK_FOR_LETTER_P
1231 Immediate constant constraints, for all floating point constants and for
1232 constants of greater than word size precision (usually upper case).
1234 @item EXTRA_CONSTRAINT
1235 Special cases of registers or memory. This macro is not required, and
1236 is only defined for some machines.
1239 Inspecting these macro definitions in the compiler source for your
1240 machine is the best way to be certain you have the right constraints.
1241 However, here is a summary of the machine-dependent constraints
1242 available on some particular machines.
1245 @item ARM family---@file{arm.h}
1248 Floating-point register
1251 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1255 Floating-point constant that would satisfy the constraint @samp{F} if it
1259 Integer that is valid as an immediate operand in a data processing
1260 instruction. That is, an integer in the range 0 to 255 rotated by a
1264 Integer in the range -4095 to 4095
1267 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1270 Integer that satisfies constraint @samp{I} when negated (twos complement)
1273 Integer in the range 0 to 32
1276 A memory reference where the exact address is in a single register
1277 (`@samp{m}' is preferable for @code{asm} statements)
1280 An item in the constant pool
1283 A symbol in the text segment of the current file
1286 @item AMD 29000 family---@file{a29k.h}
1292 Byte Pointer (@samp{BP}) register
1298 Special purpose register
1301 First accumulator register
1304 Other accumulator register
1307 Floating point register
1310 Constant greater than 0, less than 0x100
1313 Constant greater than 0, less than 0x10000
1316 Constant whose high 24 bits are on (1)
1319 16 bit constant whose high 8 bits are on (1)
1322 32 bit constant whose high 16 bits are on (1)
1325 32 bit negative constant that fits in 8 bits
1328 The constant 0x80000000 or, on the 29050, any 32 bit constant
1329 whose low 16 bits are 0.
1332 16 bit negative constant that fits in 8 bits
1336 A floating point constant (in @code{asm} statements, use the machine
1337 independent @samp{E} or @samp{F} instead)
1340 @item AVR family---@file{avr.h}
1343 Registers from r0 to r15
1346 Registers from r16 to r23
1349 Registers from r16 to r31
1352 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1355 Pointer register (r26 - r31)
1358 Base pointer register (r28 - r31)
1361 Stack pointer register (SPH:SPL)
1364 Temporary register r0
1367 Register pair X (r27:r26)
1370 Register pair Y (r29:r28)
1373 Register pair Z (r31:r30)
1376 Constant greater than -1, less than 64
1379 Constant greater than -64, less than 1
1388 Constant that fits in 8 bits
1394 Constant integer 8, 16, or 24
1400 A floating point constant 0.0
1403 @item IBM RS6000---@file{rs6000.h}
1406 Address base register
1409 Floating point register
1412 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1421 @samp{LINK} register
1424 @samp{CR} register (condition register) number 0
1427 @samp{CR} register (condition register)
1430 @samp{FPMEM} stack memory for FPR-GPR transfers
1433 Signed 16 bit constant
1436 Unsigned 16 bit constant shifted left 16 bits (use @samp{L} instead for
1437 @code{SImode} constants)
1440 Unsigned 16 bit constant
1443 Signed 16 bit constant shifted left 16 bits
1446 Constant larger than 31
1455 Constant whose negation is a signed 16 bit constant
1458 Floating point constant that can be loaded into a register with one
1459 instruction per word
1462 Memory operand that is an offset from a register (@samp{m} is preferable
1463 for @code{asm} statements)
1469 Constant suitable as a 64-bit mask operand
1472 Constant suitable as a 32-bit mask operand
1475 System V Release 4 small data area reference
1478 @item Intel 386---@file{i386.h}
1481 @samp{a}, @code{b}, @code{c}, or @code{d} register
1484 @samp{a}, or @code{d} register (for 64-bit ints)
1487 Floating point register
1490 First (top of stack) floating point register
1493 Second floating point register
1514 Constant in range 0 to 31 (for 32 bit shifts)
1517 Constant in range 0 to 63 (for 64 bit shifts)
1526 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1529 Constant in range 0 to 255 (for @code{out} instruction)
1532 Standard 80387 floating point constant
1535 @item Intel 960---@file{i960.h}
1538 Floating point register (@code{fp0} to @code{fp3})
1541 Local register (@code{r0} to @code{r15})
1544 Global register (@code{g0} to @code{g15})
1547 Any local or global register
1550 Integers from 0 to 31
1556 Integers from -31 to 0
1565 @item MIPS---@file{mips.h}
1568 General-purpose integer register
1571 Floating-point register (if available)
1580 @samp{Hi} or @samp{Lo} register
1583 General-purpose integer register
1586 Floating-point status register
1589 Signed 16 bit constant (for arithmetic instructions)
1595 Zero-extended 16-bit constant (for logic instructions)
1598 Constant with low 16 bits zero (can be loaded with @code{lui})
1601 32 bit constant which requires two instructions to load (a constant
1602 which is not @samp{I}, @samp{K}, or @samp{L})
1605 Negative 16 bit constant
1611 Positive 16 bit constant
1617 Memory reference that can be loaded with more than one instruction
1618 (@samp{m} is preferable for @code{asm} statements)
1621 Memory reference that can be loaded with one instruction
1622 (@samp{m} is preferable for @code{asm} statements)
1625 Memory reference in external OSF/rose PIC format
1626 (@samp{m} is preferable for @code{asm} statements)
1629 @item Motorola 680x0---@file{m68k.h}
1638 68881 floating-point register, if available
1641 Sun FPA (floating-point) register, if available
1644 First 16 Sun FPA registers, if available
1647 Integer in the range 1 to 8
1650 16 bit signed number
1653 Signed number whose magnitude is greater than 0x80
1656 Integer in the range -8 to -1
1659 Signed number whose magnitude is greater than 0x100
1662 Floating point constant that is not a 68881 constant
1665 Floating point constant that can be used by Sun FPA
1668 @item Motorola 68HC11 & 68HC12 families---@file{m68hc11.h}
1683 Temporary soft register _.tmp
1686 A soft register _.d1 to _.d31
1689 Stack pointer register
1698 Pseudo register 'z' (replaced by 'x' or 'y' at the end)
1701 An address register: x, y or z
1704 An address register: x or y
1707 Register pair (x:d) to form a 32-bit value
1710 Constants in the range -65536 to 65535
1713 Constants whose 16-bit low part is zero
1716 Constant integer 1 or -1
1722 Constants in the range -8 to 2
1727 @item SPARC---@file{sparc.h}
1730 Floating-point register that can hold 32 or 64 bit values.
1733 Floating-point register that can hold 64 or 128 bit values.
1736 Signed 13 bit constant
1742 32 bit constant with the low 12 bits clear (a constant that can be
1743 loaded with the @code{sethi} instruction)
1749 Signed 13 bit constant, sign-extended to 32 or 64 bits
1752 Floating-point constant whose integral representation can
1753 be moved into an integer register using a single sethi
1757 Floating-point constant whose integral representation can
1758 be moved into an integer register using a single mov
1762 Floating-point constant whose integral representation can
1763 be moved into an integer register using a high/lo_sum
1764 instruction sequence
1767 Memory address aligned to an 8-byte boundary
1774 @item TMS320C3x/C4x---@file{c4x.h}
1777 Auxiliary (address) register (ar0-ar7)
1780 Stack pointer register (sp)
1783 Standard (32 bit) precision integer register
1786 Extended (40 bit) precision register (r0-r11)
1789 Block count register (bk)
1792 Extended (40 bit) precision low register (r0-r7)
1795 Extended (40 bit) precision register (r0-r1)
1798 Extended (40 bit) precision register (r2-r3)
1801 Repeat count register (rc)
1804 Index register (ir0-ir1)
1807 Status (condition code) register (st)
1810 Data page register (dp)
1816 Immediate 16 bit floating-point constant
1819 Signed 16 bit constant
1822 Signed 8 bit constant
1825 Signed 5 bit constant
1828 Unsigned 16 bit constant
1831 Unsigned 8 bit constant
1834 Ones complement of unsigned 16 bit constant
1837 High 16 bit constant (32 bit constant with 16 LSBs zero)
1840 Indirect memory reference with signed 8 bit or index register displacement
1843 Indirect memory reference with unsigned 5 bit displacement
1846 Indirect memory reference with 1 bit or index register displacement
1849 Direct memory reference
1858 @node Standard Names
1859 @section Standard Pattern Names For Generation
1860 @cindex standard pattern names
1861 @cindex pattern names
1862 @cindex names, pattern
1864 Here is a table of the instruction names that are meaningful in the RTL
1865 generation pass of the compiler. Giving one of these names to an
1866 instruction pattern tells the RTL generation pass that it can use the
1867 pattern to accomplish a certain task.
1870 @cindex @code{mov@var{m}} instruction pattern
1871 @item @samp{mov@var{m}}
1872 Here @var{m} stands for a two-letter machine mode name, in lower case.
1873 This instruction pattern moves data with that machine mode from operand
1874 1 to operand 0. For example, @samp{movsi} moves full-word data.
1876 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
1877 own mode is wider than @var{m}, the effect of this instruction is
1878 to store the specified value in the part of the register that corresponds
1879 to mode @var{m}. The effect on the rest of the register is undefined.
1881 This class of patterns is special in several ways. First of all, each
1882 of these names up to and including full word size @emph{must} be defined,
1883 because there is no other way to copy a datum from one place to another.
1884 If there are patterns accepting operands in larger modes,
1885 @samp{mov@var{m}} must be defined for integer modes of those sizes.
1887 Second, these patterns are not used solely in the RTL generation pass.
1888 Even the reload pass can generate move insns to copy values from stack
1889 slots into temporary registers. When it does so, one of the operands is
1890 a hard register and the other is an operand that can need to be reloaded
1894 Therefore, when given such a pair of operands, the pattern must generate
1895 RTL which needs no reloading and needs no temporary registers---no
1896 registers other than the operands. For example, if you support the
1897 pattern with a @code{define_expand}, then in such a case the
1898 @code{define_expand} mustn't call @code{force_reg} or any other such
1899 function which might generate new pseudo registers.
1901 This requirement exists even for subword modes on a RISC machine where
1902 fetching those modes from memory normally requires several insns and
1903 some temporary registers. Look in @file{spur.md} to see how the
1904 requirement can be satisfied.
1906 @findex change_address
1907 During reload a memory reference with an invalid address may be passed
1908 as an operand. Such an address will be replaced with a valid address
1909 later in the reload pass. In this case, nothing may be done with the
1910 address except to use it as it stands. If it is copied, it will not be
1911 replaced with a valid address. No attempt should be made to make such
1912 an address into a valid address and no routine (such as
1913 @code{change_address}) that will do so may be called. Note that
1914 @code{general_operand} will fail when applied to such an address.
1916 @findex reload_in_progress
1917 The global variable @code{reload_in_progress} (which must be explicitly
1918 declared if required) can be used to determine whether such special
1919 handling is required.
1921 The variety of operands that have reloads depends on the rest of the
1922 machine description, but typically on a RISC machine these can only be
1923 pseudo registers that did not get hard registers, while on other
1924 machines explicit memory references will get optional reloads.
1926 If a scratch register is required to move an object to or from memory,
1927 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
1929 If there are cases needing
1930 scratch registers after reload, you must define
1931 @code{SECONDARY_INPUT_RELOAD_CLASS} and perhaps also
1932 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
1933 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
1934 them. @xref{Register Classes}.
1936 @findex no_new_pseudos
1937 The global variable @code{no_new_pseudos} can be used to determine if it
1938 is unsafe to create new pseudo registers. If this variable is nonzero, then
1939 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
1941 The constraints on a @samp{mov@var{m}} must permit moving any hard
1942 register to any other hard register provided that
1943 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
1944 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
1946 It is obligatory to support floating point @samp{mov@var{m}}
1947 instructions into and out of any registers that can hold fixed point
1948 values, because unions and structures (which have modes @code{SImode} or
1949 @code{DImode}) can be in those registers and they may have floating
1952 There may also be a need to support fixed point @samp{mov@var{m}}
1953 instructions in and out of floating point registers. Unfortunately, I
1954 have forgotten why this was so, and I don't know whether it is still
1955 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
1956 floating point registers, then the constraints of the fixed point
1957 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
1958 reload into a floating point register.
1960 @cindex @code{reload_in} instruction pattern
1961 @cindex @code{reload_out} instruction pattern
1962 @item @samp{reload_in@var{m}}
1963 @itemx @samp{reload_out@var{m}}
1964 Like @samp{mov@var{m}}, but used when a scratch register is required to
1965 move between operand 0 and operand 1. Operand 2 describes the scratch
1966 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
1967 macro in @pxref{Register Classes}.
1969 @cindex @code{movstrict@var{m}} instruction pattern
1970 @item @samp{movstrict@var{m}}
1971 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
1972 with mode @var{m} of a register whose natural mode is wider,
1973 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
1974 any of the register except the part which belongs to mode @var{m}.
1976 @cindex @code{load_multiple} instruction pattern
1977 @item @samp{load_multiple}
1978 Load several consecutive memory locations into consecutive registers.
1979 Operand 0 is the first of the consecutive registers, operand 1
1980 is the first memory location, and operand 2 is a constant: the
1981 number of consecutive registers.
1983 Define this only if the target machine really has such an instruction;
1984 do not define this if the most efficient way of loading consecutive
1985 registers from memory is to do them one at a time.
1987 On some machines, there are restrictions as to which consecutive
1988 registers can be stored into memory, such as particular starting or
1989 ending register numbers or only a range of valid counts. For those
1990 machines, use a @code{define_expand} (@pxref{Expander Definitions})
1991 and make the pattern fail if the restrictions are not met.
1993 Write the generated insn as a @code{parallel} with elements being a
1994 @code{set} of one register from the appropriate memory location (you may
1995 also need @code{use} or @code{clobber} elements). Use a
1996 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
1997 @file{a29k.md} and @file{rs6000.md} for examples of the use of this insn
2000 @cindex @samp{store_multiple} instruction pattern
2001 @item @samp{store_multiple}
2002 Similar to @samp{load_multiple}, but store several consecutive registers
2003 into consecutive memory locations. Operand 0 is the first of the
2004 consecutive memory locations, operand 1 is the first register, and
2005 operand 2 is a constant: the number of consecutive registers.
2007 @cindex @code{add@var{m}3} instruction pattern
2008 @item @samp{add@var{m}3}
2009 Add operand 2 and operand 1, storing the result in operand 0. All operands
2010 must have mode @var{m}. This can be used even on two-address machines, by
2011 means of constraints requiring operands 1 and 0 to be the same location.
2013 @cindex @code{sub@var{m}3} instruction pattern
2014 @cindex @code{mul@var{m}3} instruction pattern
2015 @cindex @code{div@var{m}3} instruction pattern
2016 @cindex @code{udiv@var{m}3} instruction pattern
2017 @cindex @code{mod@var{m}3} instruction pattern
2018 @cindex @code{umod@var{m}3} instruction pattern
2019 @cindex @code{smin@var{m}3} instruction pattern
2020 @cindex @code{smax@var{m}3} instruction pattern
2021 @cindex @code{umin@var{m}3} instruction pattern
2022 @cindex @code{umax@var{m}3} instruction pattern
2023 @cindex @code{and@var{m}3} instruction pattern
2024 @cindex @code{ior@var{m}3} instruction pattern
2025 @cindex @code{xor@var{m}3} instruction pattern
2026 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
2027 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
2028 @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
2029 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
2030 Similar, for other arithmetic operations.
2032 @cindex @code{mulhisi3} instruction pattern
2033 @item @samp{mulhisi3}
2034 Multiply operands 1 and 2, which have mode @code{HImode}, and store
2035 a @code{SImode} product in operand 0.
2037 @cindex @code{mulqihi3} instruction pattern
2038 @cindex @code{mulsidi3} instruction pattern
2039 @item @samp{mulqihi3}, @samp{mulsidi3}
2040 Similar widening-multiplication instructions of other widths.
2042 @cindex @code{umulqihi3} instruction pattern
2043 @cindex @code{umulhisi3} instruction pattern
2044 @cindex @code{umulsidi3} instruction pattern
2045 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
2046 Similar widening-multiplication instructions that do unsigned
2049 @cindex @code{smul@var{m}3_highpart} instruction pattern
2050 @item @samp{smul@var{m}3_highpart}
2051 Perform a signed multiplication of operands 1 and 2, which have mode
2052 @var{m}, and store the most significant half of the product in operand 0.
2053 The least significant half of the product is discarded.
2055 @cindex @code{umul@var{m}3_highpart} instruction pattern
2056 @item @samp{umul@var{m}3_highpart}
2057 Similar, but the multiplication is unsigned.
2059 @cindex @code{divmod@var{m}4} instruction pattern
2060 @item @samp{divmod@var{m}4}
2061 Signed division that produces both a quotient and a remainder.
2062 Operand 1 is divided by operand 2 to produce a quotient stored
2063 in operand 0 and a remainder stored in operand 3.
2065 For machines with an instruction that produces both a quotient and a
2066 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
2067 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
2068 allows optimization in the relatively common case when both the quotient
2069 and remainder are computed.
2071 If an instruction that just produces a quotient or just a remainder
2072 exists and is more efficient than the instruction that produces both,
2073 write the output routine of @samp{divmod@var{m}4} to call
2074 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
2075 quotient or remainder and generate the appropriate instruction.
2077 @cindex @code{udivmod@var{m}4} instruction pattern
2078 @item @samp{udivmod@var{m}4}
2079 Similar, but does unsigned division.
2081 @cindex @code{ashl@var{m}3} instruction pattern
2082 @item @samp{ashl@var{m}3}
2083 Arithmetic-shift operand 1 left by a number of bits specified by operand
2084 2, and store the result in operand 0. Here @var{m} is the mode of
2085 operand 0 and operand 1; operand 2's mode is specified by the
2086 instruction pattern, and the compiler will convert the operand to that
2087 mode before generating the instruction.
2089 @cindex @code{ashr@var{m}3} instruction pattern
2090 @cindex @code{lshr@var{m}3} instruction pattern
2091 @cindex @code{rotl@var{m}3} instruction pattern
2092 @cindex @code{rotr@var{m}3} instruction pattern
2093 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
2094 Other shift and rotate instructions, analogous to the
2095 @code{ashl@var{m}3} instructions.
2097 @cindex @code{neg@var{m}2} instruction pattern
2098 @item @samp{neg@var{m}2}
2099 Negate operand 1 and store the result in operand 0.
2101 @cindex @code{abs@var{m}2} instruction pattern
2102 @item @samp{abs@var{m}2}
2103 Store the absolute value of operand 1 into operand 0.
2105 @cindex @code{sqrt@var{m}2} instruction pattern
2106 @item @samp{sqrt@var{m}2}
2107 Store the square root of operand 1 into operand 0.
2109 The @code{sqrt} built-in function of C always uses the mode which
2110 corresponds to the C data type @code{double}.
2112 @cindex @code{ffs@var{m}2} instruction pattern
2113 @item @samp{ffs@var{m}2}
2114 Store into operand 0 one plus the index of the least significant 1-bit
2115 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
2116 of operand 0; operand 1's mode is specified by the instruction
2117 pattern, and the compiler will convert the operand to that mode before
2118 generating the instruction.
2120 The @code{ffs} built-in function of C always uses the mode which
2121 corresponds to the C data type @code{int}.
2123 @cindex @code{one_cmpl@var{m}2} instruction pattern
2124 @item @samp{one_cmpl@var{m}2}
2125 Store the bitwise-complement of operand 1 into operand 0.
2127 @cindex @code{cmp@var{m}} instruction pattern
2128 @item @samp{cmp@var{m}}
2129 Compare operand 0 and operand 1, and set the condition codes.
2130 The RTL pattern should look like this:
2133 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
2134 (match_operand:@var{m} 1 @dots{})))
2137 @cindex @code{tst@var{m}} instruction pattern
2138 @item @samp{tst@var{m}}
2139 Compare operand 0 against zero, and set the condition codes.
2140 The RTL pattern should look like this:
2143 (set (cc0) (match_operand:@var{m} 0 @dots{}))
2146 @samp{tst@var{m}} patterns should not be defined for machines that do
2147 not use @code{(cc0)}. Doing so would confuse the optimizer since it
2148 would no longer be clear which @code{set} operations were comparisons.
2149 The @samp{cmp@var{m}} patterns should be used instead.
2151 @cindex @code{movstr@var{m}} instruction pattern
2152 @item @samp{movstr@var{m}}
2153 Block move instruction. The addresses of the destination and source
2154 strings are the first two operands, and both are in mode @code{Pmode}.
2156 The number of bytes to move is the third operand, in mode @var{m}.
2157 Usually, you specify @code{word_mode} for @var{m}. However, if you can
2158 generate better code knowing the range of valid lengths is smaller than
2159 those representable in a full word, you should provide a pattern with a
2160 mode corresponding to the range of values you can handle efficiently
2161 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
2162 that appear negative) and also a pattern with @code{word_mode}.
2164 The fourth operand is the known shared alignment of the source and
2165 destination, in the form of a @code{const_int} rtx. Thus, if the
2166 compiler knows that both source and destination are word-aligned,
2167 it may provide the value 4 for this operand.
2169 Descriptions of multiple @code{movstr@var{m}} patterns can only be
2170 beneficial if the patterns for smaller modes have fewer restrictions
2171 on their first, second and fourth operands. Note that the mode @var{m}
2172 in @code{movstr@var{m}} does not impose any restriction on the mode of
2173 individually moved data units in the block.
2175 These patterns need not give special consideration to the possibility
2176 that the source and destination strings might overlap.
2178 @cindex @code{clrstr@var{m}} instruction pattern
2179 @item @samp{clrstr@var{m}}
2180 Block clear instruction. The addresses of the destination string is the
2181 first operand, in mode @code{Pmode}. The number of bytes to clear is
2182 the second operand, in mode @var{m}. See @samp{movstr@var{m}} for
2183 a discussion of the choice of mode.
2185 The third operand is the known alignment of the destination, in the form
2186 of a @code{const_int} rtx. Thus, if the compiler knows that the
2187 destination is word-aligned, it may provide the value 4 for this
2190 The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}.
2192 @cindex @code{cmpstr@var{m}} instruction pattern
2193 @item @samp{cmpstr@var{m}}
2194 Block compare instruction, with five operands. Operand 0 is the output;
2195 it has mode @var{m}. The remaining four operands are like the operands
2196 of @samp{movstr@var{m}}. The two memory blocks specified are compared
2197 byte by byte in lexicographic order. The effect of the instruction is
2198 to store a value in operand 0 whose sign indicates the result of the
2201 @cindex @code{strlen@var{m}} instruction pattern
2202 @item @samp{strlen@var{m}}
2203 Compute the length of a string, with three operands.
2204 Operand 0 is the result (of mode @var{m}), operand 1 is
2205 a @code{mem} referring to the first character of the string,
2206 operand 2 is the character to search for (normally zero),
2207 and operand 3 is a constant describing the known alignment
2208 of the beginning of the string.
2210 @cindex @code{float@var{mn}2} instruction pattern
2211 @item @samp{float@var{m}@var{n}2}
2212 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
2213 floating point mode @var{n} and store in operand 0 (which has mode
2216 @cindex @code{floatuns@var{mn}2} instruction pattern
2217 @item @samp{floatuns@var{m}@var{n}2}
2218 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
2219 to floating point mode @var{n} and store in operand 0 (which has mode
2222 @cindex @code{fix@var{mn}2} instruction pattern
2223 @item @samp{fix@var{m}@var{n}2}
2224 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2225 point mode @var{n} as a signed number and store in operand 0 (which
2226 has mode @var{n}). This instruction's result is defined only when
2227 the value of operand 1 is an integer.
2229 @cindex @code{fixuns@var{mn}2} instruction pattern
2230 @item @samp{fixuns@var{m}@var{n}2}
2231 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2232 point mode @var{n} as an unsigned number and store in operand 0 (which
2233 has mode @var{n}). This instruction's result is defined only when the
2234 value of operand 1 is an integer.
2236 @cindex @code{ftrunc@var{m}2} instruction pattern
2237 @item @samp{ftrunc@var{m}2}
2238 Convert operand 1 (valid for floating point mode @var{m}) to an
2239 integer value, still represented in floating point mode @var{m}, and
2240 store it in operand 0 (valid for floating point mode @var{m}).
2242 @cindex @code{fix_trunc@var{mn}2} instruction pattern
2243 @item @samp{fix_trunc@var{m}@var{n}2}
2244 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
2245 of mode @var{m} by converting the value to an integer.
2247 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
2248 @item @samp{fixuns_trunc@var{m}@var{n}2}
2249 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
2250 value of mode @var{m} by converting the value to an integer.
2252 @cindex @code{trunc@var{mn}2} instruction pattern
2253 @item @samp{trunc@var{m}@var{n}2}
2254 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
2255 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2256 point or both floating point.
2258 @cindex @code{extend@var{mn}2} instruction pattern
2259 @item @samp{extend@var{m}@var{n}2}
2260 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2261 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2262 point or both floating point.
2264 @cindex @code{zero_extend@var{mn}2} instruction pattern
2265 @item @samp{zero_extend@var{m}@var{n}2}
2266 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2267 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2270 @cindex @code{extv} instruction pattern
2272 Extract a bit field from operand 1 (a register or memory operand), where
2273 operand 2 specifies the width in bits and operand 3 the starting bit,
2274 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
2275 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
2276 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
2277 be valid for @code{word_mode}.
2279 The RTL generation pass generates this instruction only with constants
2280 for operands 2 and 3.
2282 The bit-field value is sign-extended to a full word integer
2283 before it is stored in operand 0.
2285 @cindex @code{extzv} instruction pattern
2287 Like @samp{extv} except that the bit-field value is zero-extended.
2289 @cindex @code{insv} instruction pattern
2291 Store operand 3 (which must be valid for @code{word_mode}) into a bit
2292 field in operand 0, where operand 1 specifies the width in bits and
2293 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
2294 @code{word_mode}; often @code{word_mode} is allowed only for registers.
2295 Operands 1 and 2 must be valid for @code{word_mode}.
2297 The RTL generation pass generates this instruction only with constants
2298 for operands 1 and 2.
2300 @cindex @code{mov@var{mode}cc} instruction pattern
2301 @item @samp{mov@var{mode}cc}
2302 Conditionally move operand 2 or operand 3 into operand 0 according to the
2303 comparison in operand 1. If the comparison is true, operand 2 is moved
2304 into operand 0, otherwise operand 3 is moved.
2306 The mode of the operands being compared need not be the same as the operands
2307 being moved. Some machines, sparc64 for example, have instructions that
2308 conditionally move an integer value based on the floating point condition
2309 codes and vice versa.
2311 If the machine does not have conditional move instructions, do not
2312 define these patterns.
2314 @cindex @code{s@var{cond}} instruction pattern
2315 @item @samp{s@var{cond}}
2316 Store zero or nonzero in the operand according to the condition codes.
2317 Value stored is nonzero iff the condition @var{cond} is true.
2318 @var{cond} is the name of a comparison operation expression code, such
2319 as @code{eq}, @code{lt} or @code{leu}.
2321 You specify the mode that the operand must have when you write the
2322 @code{match_operand} expression. The compiler automatically sees
2323 which mode you have used and supplies an operand of that mode.
2325 The value stored for a true condition must have 1 as its low bit, or
2326 else must be negative. Otherwise the instruction is not suitable and
2327 you should omit it from the machine description. You describe to the
2328 compiler exactly which value is stored by defining the macro
2329 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
2330 found that can be used for all the @samp{s@var{cond}} patterns, you
2331 should omit those operations from the machine description.
2333 These operations may fail, but should do so only in relatively
2334 uncommon cases; if they would fail for common cases involving
2335 integer comparisons, it is best to omit these patterns.
2337 If these operations are omitted, the compiler will usually generate code
2338 that copies the constant one to the target and branches around an
2339 assignment of zero to the target. If this code is more efficient than
2340 the potential instructions used for the @samp{s@var{cond}} pattern
2341 followed by those required to convert the result into a 1 or a zero in
2342 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
2343 the machine description.
2345 @cindex @code{b@var{cond}} instruction pattern
2346 @item @samp{b@var{cond}}
2347 Conditional branch instruction. Operand 0 is a @code{label_ref} that
2348 refers to the label to jump to. Jump if the condition codes meet
2349 condition @var{cond}.
2351 Some machines do not follow the model assumed here where a comparison
2352 instruction is followed by a conditional branch instruction. In that
2353 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
2354 simply store the operands away and generate all the required insns in a
2355 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
2356 branch operations. All calls to expand @samp{b@var{cond}} patterns are
2357 immediately preceded by calls to expand either a @samp{cmp@var{m}}
2358 pattern or a @samp{tst@var{m}} pattern.
2360 Machines that use a pseudo register for the condition code value, or
2361 where the mode used for the comparison depends on the condition being
2362 tested, should also use the above mechanism. @xref{Jump Patterns}.
2364 The above discussion also applies to the @samp{mov@var{mode}cc} and
2365 @samp{s@var{cond}} patterns.
2367 @cindex @code{jump} instruction pattern
2369 A jump inside a function; an unconditional branch. Operand 0 is the
2370 @code{label_ref} of the label to jump to. This pattern name is mandatory
2373 @cindex @code{call} instruction pattern
2375 Subroutine call instruction returning no value. Operand 0 is the
2376 function to call; operand 1 is the number of bytes of arguments pushed
2377 as a @code{const_int}; operand 2 is the number of registers used as
2380 On most machines, operand 2 is not actually stored into the RTL
2381 pattern. It is supplied for the sake of some RISC machines which need
2382 to put this information into the assembler code; they can put it in
2383 the RTL instead of operand 1.
2385 Operand 0 should be a @code{mem} RTX whose address is the address of the
2386 function. Note, however, that this address can be a @code{symbol_ref}
2387 expression even if it would not be a legitimate memory address on the
2388 target machine. If it is also not a valid argument for a call
2389 instruction, the pattern for this operation should be a
2390 @code{define_expand} (@pxref{Expander Definitions}) that places the
2391 address into a register and uses that register in the call instruction.
2393 @cindex @code{call_value} instruction pattern
2394 @item @samp{call_value}
2395 Subroutine call instruction returning a value. Operand 0 is the hard
2396 register in which the value is returned. There are three more
2397 operands, the same as the three operands of the @samp{call}
2398 instruction (but with numbers increased by one).
2400 Subroutines that return @code{BLKmode} objects use the @samp{call}
2403 @cindex @code{call_pop} instruction pattern
2404 @cindex @code{call_value_pop} instruction pattern
2405 @item @samp{call_pop}, @samp{call_value_pop}
2406 Similar to @samp{call} and @samp{call_value}, except used if defined and
2407 if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel}
2408 that contains both the function call and a @code{set} to indicate the
2409 adjustment made to the frame pointer.
2411 For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these
2412 patterns increases the number of functions for which the frame pointer
2413 can be eliminated, if desired.
2415 @cindex @code{untyped_call} instruction pattern
2416 @item @samp{untyped_call}
2417 Subroutine call instruction returning a value of any type. Operand 0 is
2418 the function to call; operand 1 is a memory location where the result of
2419 calling the function is to be stored; operand 2 is a @code{parallel}
2420 expression where each element is a @code{set} expression that indicates
2421 the saving of a function return value into the result block.
2423 This instruction pattern should be defined to support
2424 @code{__builtin_apply} on machines where special instructions are needed
2425 to call a subroutine with arbitrary arguments or to save the value
2426 returned. This instruction pattern is required on machines that have
2427 multiple registers that can hold a return value (i.e.
2428 @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
2430 @cindex @code{return} instruction pattern
2432 Subroutine return instruction. This instruction pattern name should be
2433 defined only if a single instruction can do all the work of returning
2436 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
2437 RTL generation phase. In this case it is to support machines where
2438 multiple instructions are usually needed to return from a function, but
2439 some class of functions only requires one instruction to implement a
2440 return. Normally, the applicable functions are those which do not need
2441 to save any registers or allocate stack space.
2443 @findex reload_completed
2444 @findex leaf_function_p
2445 For such machines, the condition specified in this pattern should only
2446 be true when @code{reload_completed} is non-zero and the function's
2447 epilogue would only be a single instruction. For machines with register
2448 windows, the routine @code{leaf_function_p} may be used to determine if
2449 a register window push is required.
2451 Machines that have conditional return instructions should define patterns
2457 (if_then_else (match_operator
2458 0 "comparison_operator"
2459 [(cc0) (const_int 0)])
2466 where @var{condition} would normally be the same condition specified on the
2467 named @samp{return} pattern.
2469 @cindex @code{untyped_return} instruction pattern
2470 @item @samp{untyped_return}
2471 Untyped subroutine return instruction. This instruction pattern should
2472 be defined to support @code{__builtin_return} on machines where special
2473 instructions are needed to return a value of any type.
2475 Operand 0 is a memory location where the result of calling a function
2476 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
2477 expression where each element is a @code{set} expression that indicates
2478 the restoring of a function return value from the result block.
2480 @cindex @code{nop} instruction pattern
2482 No-op instruction. This instruction pattern name should always be defined
2483 to output a no-op in assembler code. @code{(const_int 0)} will do as an
2486 @cindex @code{indirect_jump} instruction pattern
2487 @item @samp{indirect_jump}
2488 An instruction to jump to an address which is operand zero.
2489 This pattern name is mandatory on all machines.
2491 @cindex @code{casesi} instruction pattern
2493 Instruction to jump through a dispatch table, including bounds checking.
2494 This instruction takes five operands:
2498 The index to dispatch on, which has mode @code{SImode}.
2501 The lower bound for indices in the table, an integer constant.
2504 The total range of indices in the table---the largest index
2505 minus the smallest one (both inclusive).
2508 A label that precedes the table itself.
2511 A label to jump to if the index has a value outside the bounds.
2512 (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
2513 then an out-of-bounds index drops through to the code following
2514 the jump table instead of jumping to this label. In that case,
2515 this label is not actually used by the @samp{casesi} instruction,
2516 but it is always provided as an operand.)
2519 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
2520 @code{jump_insn}. The number of elements in the table is one plus the
2521 difference between the upper bound and the lower bound.
2523 @cindex @code{tablejump} instruction pattern
2524 @item @samp{tablejump}
2525 Instruction to jump to a variable address. This is a low-level
2526 capability which can be used to implement a dispatch table when there
2527 is no @samp{casesi} pattern.
2529 This pattern requires two operands: the address or offset, and a label
2530 which should immediately precede the jump table. If the macro
2531 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
2532 operand is an offset which counts from the address of the table; otherwise,
2533 it is an absolute address to jump to. In either case, the first operand has
2536 The @samp{tablejump} insn is always the last insn before the jump
2537 table it uses. Its assembler code normally has no need to use the
2538 second operand, but you should incorporate it in the RTL pattern so
2539 that the jump optimizer will not delete the table as unreachable code.
2541 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
2542 @item @samp{canonicalize_funcptr_for_compare}
2543 Canonicalize the function pointer in operand 1 and store the result
2546 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
2547 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
2548 and also has mode @code{Pmode}.
2550 Canonicalization of a function pointer usually involves computing
2551 the address of the function which would be called if the function
2552 pointer were used in an indirect call.
2554 Only define this pattern if function pointers on the target machine
2555 can have different values but still call the same function when
2556 used in an indirect call.
2558 @cindex @code{save_stack_block} instruction pattern
2559 @cindex @code{save_stack_function} instruction pattern
2560 @cindex @code{save_stack_nonlocal} instruction pattern
2561 @cindex @code{restore_stack_block} instruction pattern
2562 @cindex @code{restore_stack_function} instruction pattern
2563 @cindex @code{restore_stack_nonlocal} instruction pattern
2564 @item @samp{save_stack_block}
2565 @itemx @samp{save_stack_function}
2566 @itemx @samp{save_stack_nonlocal}
2567 @itemx @samp{restore_stack_block}
2568 @itemx @samp{restore_stack_function}
2569 @itemx @samp{restore_stack_nonlocal}
2570 Most machines save and restore the stack pointer by copying it to or
2571 from an object of mode @code{Pmode}. Do not define these patterns on
2574 Some machines require special handling for stack pointer saves and
2575 restores. On those machines, define the patterns corresponding to the
2576 non-standard cases by using a @code{define_expand} (@pxref{Expander
2577 Definitions}) that produces the required insns. The three types of
2578 saves and restores are:
2582 @samp{save_stack_block} saves the stack pointer at the start of a block
2583 that allocates a variable-sized object, and @samp{restore_stack_block}
2584 restores the stack pointer when the block is exited.
2587 @samp{save_stack_function} and @samp{restore_stack_function} do a
2588 similar job for the outermost block of a function and are used when the
2589 function allocates variable-sized objects or calls @code{alloca}. Only
2590 the epilogue uses the restored stack pointer, allowing a simpler save or
2591 restore sequence on some machines.
2594 @samp{save_stack_nonlocal} is used in functions that contain labels
2595 branched to by nested functions. It saves the stack pointer in such a
2596 way that the inner function can use @samp{restore_stack_nonlocal} to
2597 restore the stack pointer. The compiler generates code to restore the
2598 frame and argument pointer registers, but some machines require saving
2599 and restoring additional data such as register window information or
2600 stack backchains. Place insns in these patterns to save and restore any
2604 When saving the stack pointer, operand 0 is the save area and operand 1
2605 is the stack pointer. The mode used to allocate the save area defaults
2606 to @code{Pmode} but you can override that choice by defining the
2607 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
2608 specify an integral mode, or @code{VOIDmode} if no save area is needed
2609 for a particular type of save (either because no save is needed or
2610 because a machine-specific save area can be used). Operand 0 is the
2611 stack pointer and operand 1 is the save area for restore operations. If
2612 @samp{save_stack_block} is defined, operand 0 must not be
2613 @code{VOIDmode} since these saves can be arbitrarily nested.
2615 A save area is a @code{mem} that is at a constant offset from
2616 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
2617 nonlocal gotos and a @code{reg} in the other two cases.
2619 @cindex @code{allocate_stack} instruction pattern
2620 @item @samp{allocate_stack}
2621 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
2622 the stack pointer to create space for dynamically allocated data.
2624 Store the resultant pointer to this space into operand 0. If you
2625 are allocating space from the main stack, do this by emitting a
2626 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
2627 If you are allocating the space elsewhere, generate code to copy the
2628 location of the space to operand 0. In the latter case, you must
2629 ensure this space gets freed when the corresponding space on the main
2632 Do not define this pattern if all that must be done is the subtraction.
2633 Some machines require other operations such as stack probes or
2634 maintaining the back chain. Define this pattern to emit those
2635 operations in addition to updating the stack pointer.
2637 @cindex @code{probe} instruction pattern
2639 Some machines require instructions to be executed after space is
2640 allocated from the stack, for example to generate a reference at
2641 the bottom of the stack.
2643 If you need to emit instructions before the stack has been adjusted,
2644 put them into the @samp{allocate_stack} pattern. Otherwise, define
2645 this pattern to emit the required instructions.
2647 No operands are provided.
2649 @cindex @code{check_stack} instruction pattern
2650 @item @samp{check_stack}
2651 If stack checking cannot be done on your system by probing the stack with
2652 a load or store instruction (@pxref{Stack Checking}), define this pattern
2653 to perform the needed check and signaling an error if the stack
2654 has overflowed. The single operand is the location in the stack furthest
2655 from the current stack pointer that you need to validate. Normally,
2656 on machines where this pattern is needed, you would obtain the stack
2657 limit from a global or thread-specific variable or register.
2659 @cindex @code{nonlocal_goto} instruction pattern
2660 @item @samp{nonlocal_goto}
2661 Emit code to generate a non-local goto, e.g., a jump from one function
2662 to a label in an outer function. This pattern has four arguments,
2663 each representing a value to be used in the jump. The first
2664 argument is to be loaded into the frame pointer, the second is
2665 the address to branch to (code to dispatch to the actual label),
2666 the third is the address of a location where the stack is saved,
2667 and the last is the address of the label, to be placed in the
2668 location for the incoming static chain.
2670 On most machines you need not define this pattern, since GNU CC will
2671 already generate the correct code, which is to load the frame pointer
2672 and static chain, restore the stack (using the
2673 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
2674 to the dispatcher. You need only define this pattern if this code will
2675 not work on your machine.
2677 @cindex @code{nonlocal_goto_receiver} instruction pattern
2678 @item @samp{nonlocal_goto_receiver}
2679 This pattern, if defined, contains code needed at the target of a
2680 nonlocal goto after the code already generated by GNU CC. You will not
2681 normally need to define this pattern. A typical reason why you might
2682 need this pattern is if some value, such as a pointer to a global table,
2683 must be restored when the frame pointer is restored. Note that a nonlocal
2684 goto only occurs within a unit-of-translation, so a global table pointer
2685 that is shared by all functions of a given module need not be restored.
2686 There are no arguments.
2688 @cindex @code{exception_receiver} instruction pattern
2689 @item @samp{exception_receiver}
2690 This pattern, if defined, contains code needed at the site of an
2691 exception handler that isn't needed at the site of a nonlocal goto. You
2692 will not normally need to define this pattern. A typical reason why you
2693 might need this pattern is if some value, such as a pointer to a global
2694 table, must be restored after control flow is branched to the handler of
2695 an exception. There are no arguments.
2697 @cindex @code{builtin_setjmp_setup} instruction pattern
2698 @item @samp{builtin_setjmp_setup}
2699 This pattern, if defined, contains additional code needed to initialize
2700 the @code{jmp_buf}. You will not normally need to define this pattern.
2701 A typical reason why you might need this pattern is if some value, such
2702 as a pointer to a global table, must be restored. Though it is
2703 preferred that the pointer value be recalculated if possible (given the
2704 address of a label for instance). The single argument is a pointer to
2705 the @code{jmp_buf}. Note that the buffer is five words long and that
2706 the first three are normally used by the generic mechanism.
2708 @cindex @code{builtin_setjmp_receiver} instruction pattern
2709 @item @samp{builtin_setjmp_receiver}
2710 This pattern, if defined, contains code needed at the site of an
2711 builtin setjmp that isn't needed at the site of a nonlocal goto. You
2712 will not normally need to define this pattern. A typical reason why you
2713 might need this pattern is if some value, such as a pointer to a global
2714 table, must be restored. It takes one argument, which is the label
2715 to which builtin_longjmp transfered control; this pattern may be emitted
2716 at a small offset from that label.
2718 @cindex @code{builtin_longjmp} instruction pattern
2719 @item @samp{builtin_longjmp}
2720 This pattern, if defined, performs the entire action of the longjmp.
2721 You will not normally need to define this pattern unless you also define
2722 @code{builtin_setjmp_setup}. The single argument is a pointer to the
2725 @cindex @code{eh_epilogue} instruction pattern
2726 @item @samp{eh_epilogue}
2727 This pattern, if defined, affects the way @code{__builtin_eh_return},
2728 and thence @code{__throw} are built. It is intended to allow communication
2729 between the exception handling machinery and the normal epilogue code
2732 The pattern takes three arguments. The first is the exception context
2733 pointer. This will have already been copied to the function return
2734 register appropriate for a pointer; normally this can be ignored. The
2735 second argument is an offset to be added to the stack pointer. It will
2736 have been copied to some arbitrary call-clobbered hard reg so that it
2737 will survive until after reload to when the normal epilogue is generated.
2738 The final argument is the address of the exception handler to which
2739 the function should return. This will normally need to copied by the
2740 pattern to some special register.
2742 This pattern must be defined if @code{RETURN_ADDR_RTX} does not yield
2743 something that can be reliably and permanently modified, i.e. a fixed
2744 hard register or a stack memory reference.
2746 @cindex @code{prologue} instruction pattern
2747 @item @samp{prologue}
2748 This pattern, if defined, emits RTL for entry to a function. The function
2749 entry is responsible for setting up the stack frame, initializing the frame
2750 pointer register, saving callee saved registers, etc.
2752 Using a prologue pattern is generally preferred over defining
2753 @code{FUNCTION_PROLOGUE} to emit assembly code for the prologue.
2755 The @code{prologue} pattern is particularly useful for targets which perform
2756 instruction scheduling.
2758 @cindex @code{epilogue} instruction pattern
2759 @item @samp{epilogue}
2760 This pattern, if defined, emits RTL for exit from a function. The function
2761 exit is responsible for deallocating the stack frame, restoring callee saved
2762 registers and emitting the return instruction.
2764 Using an epilogue pattern is generally preferred over defining
2765 @code{FUNCTION_EPILOGUE} to emit assembly code for the prologue.
2767 The @code{epilogue} pattern is particularly useful for targets which perform
2768 instruction scheduling or which have delay slots for their return instruction.
2770 @cindex @code{sibcall_epilogue} instruction pattern
2771 @item @samp{sibcall_epilogue}
2772 This pattern, if defined, emits RTL for exit from a function without the final
2773 branch back to the calling function. This pattern will be emitted before any
2774 sibling call (aka tail call) sites.
2776 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
2777 parameter passing or any stack slots for arguments passed to the current
2780 @cindex @code{trap} instruction pattern
2782 This pattern, if defined, signals an error, typically by causing some
2783 kind of signal to be raised. Among other places, it is used by the Java
2784 frontend to signal `invalid array index' exceptions.
2786 @cindex @code{conditional_trap} instruction pattern
2787 @item @samp{conditional_trap}
2788 Conditional trap instruction. Operand 0 is a piece of RTL which
2789 performs a comparison. Operand 1 is the trap code, an integer.
2791 A typical @code{conditional_trap} pattern looks like
2794 (define_insn "conditional_trap"
2795 [(trap_if (match_operator 0 "trap_operator"
2796 [(cc0) (const_int 0)])
2797 (match_operand 1 "const_int_operand" "i"))]
2804 @node Pattern Ordering
2805 @section When the Order of Patterns Matters
2806 @cindex Pattern Ordering
2807 @cindex Ordering of Patterns
2809 Sometimes an insn can match more than one instruction pattern. Then the
2810 pattern that appears first in the machine description is the one used.
2811 Therefore, more specific patterns (patterns that will match fewer things)
2812 and faster instructions (those that will produce better code when they
2813 do match) should usually go first in the description.
2815 In some cases the effect of ordering the patterns can be used to hide
2816 a pattern when it is not valid. For example, the 68000 has an
2817 instruction for converting a fullword to floating point and another
2818 for converting a byte to floating point. An instruction converting
2819 an integer to floating point could match either one. We put the
2820 pattern to convert the fullword first to make sure that one will
2821 be used rather than the other. (Otherwise a large integer might
2822 be generated as a single-byte immediate quantity, which would not work.)
2823 Instead of using this pattern ordering it would be possible to make the
2824 pattern for convert-a-byte smart enough to deal properly with any
2827 @node Dependent Patterns
2828 @section Interdependence of Patterns
2829 @cindex Dependent Patterns
2830 @cindex Interdependence of Patterns
2832 Every machine description must have a named pattern for each of the
2833 conditional branch names @samp{b@var{cond}}. The recognition template
2834 must always have the form
2838 (if_then_else (@var{cond} (cc0) (const_int 0))
2839 (label_ref (match_operand 0 "" ""))
2844 In addition, every machine description must have an anonymous pattern
2845 for each of the possible reverse-conditional branches. Their templates
2850 (if_then_else (@var{cond} (cc0) (const_int 0))
2852 (label_ref (match_operand 0 "" ""))))
2856 They are necessary because jump optimization can turn direct-conditional
2857 branches into reverse-conditional branches.
2859 It is often convenient to use the @code{match_operator} construct to
2860 reduce the number of patterns that must be specified for branches. For
2866 (if_then_else (match_operator 0 "comparison_operator"
2867 [(cc0) (const_int 0)])
2869 (label_ref (match_operand 1 "" ""))))]
2874 In some cases machines support instructions identical except for the
2875 machine mode of one or more operands. For example, there may be
2876 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
2880 (set (match_operand:SI 0 @dots{})
2881 (extend:SI (match_operand:HI 1 @dots{})))
2883 (set (match_operand:SI 0 @dots{})
2884 (extend:SI (match_operand:QI 1 @dots{})))
2888 Constant integers do not specify a machine mode, so an instruction to
2889 extend a constant value could match either pattern. The pattern it
2890 actually will match is the one that appears first in the file. For correct
2891 results, this must be the one for the widest possible mode (@code{HImode},
2892 here). If the pattern matches the @code{QImode} instruction, the results
2893 will be incorrect if the constant value does not actually fit that mode.
2895 Such instructions to extend constants are rarely generated because they are
2896 optimized away, but they do occasionally happen in nonoptimized
2899 If a constraint in a pattern allows a constant, the reload pass may
2900 replace a register with a constant permitted by the constraint in some
2901 cases. Similarly for memory references. Because of this substitution,
2902 you should not provide separate patterns for increment and decrement
2903 instructions. Instead, they should be generated from the same pattern
2904 that supports register-register add insns by examining the operands and
2905 generating the appropriate machine instruction.
2908 @section Defining Jump Instruction Patterns
2909 @cindex jump instruction patterns
2910 @cindex defining jump instruction patterns
2912 For most machines, GNU CC assumes that the machine has a condition code.
2913 A comparison insn sets the condition code, recording the results of both
2914 signed and unsigned comparison of the given operands. A separate branch
2915 insn tests the condition code and branches or not according its value.
2916 The branch insns come in distinct signed and unsigned flavors. Many
2917 common machines, such as the Vax, the 68000 and the 32000, work this
2920 Some machines have distinct signed and unsigned compare instructions, and
2921 only one set of conditional branch instructions. The easiest way to handle
2922 these machines is to treat them just like the others until the final stage
2923 where assembly code is written. At this time, when outputting code for the
2924 compare instruction, peek ahead at the following branch using
2925 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
2926 being output, in the output-writing code in an instruction pattern.) If
2927 the RTL says that is an unsigned branch, output an unsigned compare;
2928 otherwise output a signed compare. When the branch itself is output, you
2929 can treat signed and unsigned branches identically.
2931 The reason you can do this is that GNU CC always generates a pair of
2932 consecutive RTL insns, possibly separated by @code{note} insns, one to
2933 set the condition code and one to test it, and keeps the pair inviolate
2936 To go with this technique, you must define the machine-description macro
2937 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
2938 compare instruction is superfluous.
2940 Some machines have compare-and-branch instructions and no condition code.
2941 A similar technique works for them. When it is time to ``output'' a
2942 compare instruction, record its operands in two static variables. When
2943 outputting the branch-on-condition-code instruction that follows, actually
2944 output a compare-and-branch instruction that uses the remembered operands.
2946 It also works to define patterns for compare-and-branch instructions.
2947 In optimizing compilation, the pair of compare and branch instructions
2948 will be combined according to these patterns. But this does not happen
2949 if optimization is not requested. So you must use one of the solutions
2950 above in addition to any special patterns you define.
2952 In many RISC machines, most instructions do not affect the condition
2953 code and there may not even be a separate condition code register. On
2954 these machines, the restriction that the definition and use of the
2955 condition code be adjacent insns is not necessary and can prevent
2956 important optimizations. For example, on the IBM RS/6000, there is a
2957 delay for taken branches unless the condition code register is set three
2958 instructions earlier than the conditional branch. The instruction
2959 scheduler cannot perform this optimization if it is not permitted to
2960 separate the definition and use of the condition code register.
2962 On these machines, do not use @code{(cc0)}, but instead use a register
2963 to represent the condition code. If there is a specific condition code
2964 register in the machine, use a hard register. If the condition code or
2965 comparison result can be placed in any general register, or if there are
2966 multiple condition registers, use a pseudo register.
2968 @findex prev_cc0_setter
2969 @findex next_cc0_user
2970 On some machines, the type of branch instruction generated may depend on
2971 the way the condition code was produced; for example, on the 68k and
2972 Sparc, setting the condition code directly from an add or subtract
2973 instruction does not clear the overflow bit the way that a test
2974 instruction does, so a different branch instruction must be used for
2975 some conditional branches. For machines that use @code{(cc0)}, the set
2976 and use of the condition code must be adjacent (separated only by
2977 @code{note} insns) allowing flags in @code{cc_status} to be used.
2978 (@xref{Condition Code}.) Also, the comparison and branch insns can be
2979 located from each other by using the functions @code{prev_cc0_setter}
2980 and @code{next_cc0_user}.
2982 However, this is not true on machines that do not use @code{(cc0)}. On
2983 those machines, no assumptions can be made about the adjacency of the
2984 compare and branch insns and the above methods cannot be used. Instead,
2985 we use the machine mode of the condition code register to record
2986 different formats of the condition code register.
2988 Registers used to store the condition code value should have a mode that
2989 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
2990 additional modes are required (as for the add example mentioned above in
2991 the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
2992 additional modes required (@pxref{Condition Code}). Also define
2993 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
2995 If it is known during RTL generation that a different mode will be
2996 required (for example, if the machine has separate compare instructions
2997 for signed and unsigned quantities, like most IBM processors), they can
2998 be specified at that time.
3000 If the cases that require different modes would be made by instruction
3001 combination, the macro @code{SELECT_CC_MODE} determines which machine
3002 mode should be used for the comparison result. The patterns should be
3003 written using that mode. To support the case of the add on the Sparc
3004 discussed above, we have the pattern
3008 [(set (reg:CC_NOOV 0)
3010 (plus:SI (match_operand:SI 0 "register_operand" "%r")
3011 (match_operand:SI 1 "arith_operand" "rI"))
3017 The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
3018 for comparisons whose argument is a @code{plus}.
3020 @node Insn Canonicalizations
3021 @section Canonicalization of Instructions
3022 @cindex canonicalization of instructions
3023 @cindex insn canonicalization
3025 There are often cases where multiple RTL expressions could represent an
3026 operation performed by a single machine instruction. This situation is
3027 most commonly encountered with logical, branch, and multiply-accumulate
3028 instructions. In such cases, the compiler attempts to convert these
3029 multiple RTL expressions into a single canonical form to reduce the
3030 number of insn patterns required.
3032 In addition to algebraic simplifications, following canonicalizations
3037 For commutative and comparison operators, a constant is always made the
3038 second operand. If a machine only supports a constant as the second
3039 operand, only patterns that match a constant in the second operand need
3042 @cindex @code{neg}, canonicalization of
3043 @cindex @code{not}, canonicalization of
3044 @cindex @code{mult}, canonicalization of
3045 @cindex @code{plus}, canonicalization of
3046 @cindex @code{minus}, canonicalization of
3047 For these operators, if only one operand is a @code{neg}, @code{not},
3048 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
3051 @cindex @code{compare}, canonicalization of
3053 For the @code{compare} operator, a constant is always the second operand
3054 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
3055 machines, there are rare cases where the compiler might want to construct
3056 a @code{compare} with a constant as the first operand. However, these
3057 cases are not common enough for it to be worthwhile to provide a pattern
3058 matching a constant as the first operand unless the machine actually has
3059 such an instruction.
3061 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
3062 @code{minus} is made the first operand under the same conditions as
3066 @code{(minus @var{x} (const_int @var{n}))} is converted to
3067 @code{(plus @var{x} (const_int @var{-n}))}.
3070 Within address computations (i.e., inside @code{mem}), a left shift is
3071 converted into the appropriate multiplication by a power of two.
3073 @cindex @code{ior}, canonicalization of
3074 @cindex @code{and}, canonicalization of
3075 @cindex De Morgan's law
3077 De`Morgan's Law is used to move bitwise negation inside a bitwise
3078 logical-and or logical-or operation. If this results in only one
3079 operand being a @code{not} expression, it will be the first one.
3081 A machine that has an instruction that performs a bitwise logical-and of one
3082 operand with the bitwise negation of the other should specify the pattern
3083 for that instruction as
3087 [(set (match_operand:@var{m} 0 @dots{})
3088 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3089 (match_operand:@var{m} 2 @dots{})))]
3095 Similarly, a pattern for a ``NAND'' instruction should be written
3099 [(set (match_operand:@var{m} 0 @dots{})
3100 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3101 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
3106 In both cases, it is not necessary to include patterns for the many
3107 logically equivalent RTL expressions.
3109 @cindex @code{xor}, canonicalization of
3111 The only possible RTL expressions involving both bitwise exclusive-or
3112 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
3113 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.@refill
3116 The sum of three items, one of which is a constant, will only appear in
3120 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
3124 On machines that do not use @code{cc0},
3125 @code{(compare @var{x} (const_int 0))} will be converted to
3128 @cindex @code{zero_extract}, canonicalization of
3129 @cindex @code{sign_extract}, canonicalization of
3131 Equality comparisons of a group of bits (usually a single bit) with zero
3132 will be written using @code{zero_extract} rather than the equivalent
3133 @code{and} or @code{sign_extract} operations.
3137 @node Expander Definitions
3138 @section Defining RTL Sequences for Code Generation
3139 @cindex expander definitions
3140 @cindex code generation RTL sequences
3141 @cindex defining RTL sequences for code generation
3143 On some target machines, some standard pattern names for RTL generation
3144 cannot be handled with single insn, but a sequence of RTL insns can
3145 represent them. For these target machines, you can write a
3146 @code{define_expand} to specify how to generate the sequence of RTL.
3148 @findex define_expand
3149 A @code{define_expand} is an RTL expression that looks almost like a
3150 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
3151 only for RTL generation and it can produce more than one RTL insn.
3153 A @code{define_expand} RTX has four operands:
3157 The name. Each @code{define_expand} must have a name, since the only
3158 use for it is to refer to it by name.
3161 The RTL template. This is a vector of RTL expressions representing
3162 a sequence of separate instructions. Unlike @code{define_insn}, there
3163 is no implicit surrounding @code{PARALLEL}.
3166 The condition, a string containing a C expression. This expression is
3167 used to express how the availability of this pattern depends on
3168 subclasses of target machine, selected by command-line options when GNU
3169 CC is run. This is just like the condition of a @code{define_insn} that
3170 has a standard name. Therefore, the condition (if present) may not
3171 depend on the data in the insn being matched, but only the
3172 target-machine-type flags. The compiler needs to test these conditions
3173 during initialization in order to learn exactly which named instructions
3174 are available in a particular run.
3177 The preparation statements, a string containing zero or more C
3178 statements which are to be executed before RTL code is generated from
3181 Usually these statements prepare temporary registers for use as
3182 internal operands in the RTL template, but they can also generate RTL
3183 insns directly by calling routines such as @code{emit_insn}, etc.
3184 Any such insns precede the ones that come from the RTL template.
3187 Every RTL insn emitted by a @code{define_expand} must match some
3188 @code{define_insn} in the machine description. Otherwise, the compiler
3189 will crash when trying to generate code for the insn or trying to optimize
3192 The RTL template, in addition to controlling generation of RTL insns,
3193 also describes the operands that need to be specified when this pattern
3194 is used. In particular, it gives a predicate for each operand.
3196 A true operand, which needs to be specified in order to generate RTL from
3197 the pattern, should be described with a @code{match_operand} in its first
3198 occurrence in the RTL template. This enters information on the operand's
3199 predicate into the tables that record such things. GNU CC uses the
3200 information to preload the operand into a register if that is required for
3201 valid RTL code. If the operand is referred to more than once, subsequent
3202 references should use @code{match_dup}.
3204 The RTL template may also refer to internal ``operands'' which are
3205 temporary registers or labels used only within the sequence made by the
3206 @code{define_expand}. Internal operands are substituted into the RTL
3207 template with @code{match_dup}, never with @code{match_operand}. The
3208 values of the internal operands are not passed in as arguments by the
3209 compiler when it requests use of this pattern. Instead, they are computed
3210 within the pattern, in the preparation statements. These statements
3211 compute the values and store them into the appropriate elements of
3212 @code{operands} so that @code{match_dup} can find them.
3214 There are two special macros defined for use in the preparation statements:
3215 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
3222 Use the @code{DONE} macro to end RTL generation for the pattern. The
3223 only RTL insns resulting from the pattern on this occasion will be
3224 those already emitted by explicit calls to @code{emit_insn} within the
3225 preparation statements; the RTL template will not be generated.
3229 Make the pattern fail on this occasion. When a pattern fails, it means
3230 that the pattern was not truly available. The calling routines in the
3231 compiler will try other strategies for code generation using other patterns.
3233 Failure is currently supported only for binary (addition, multiplication,
3234 shifting, etc.) and bitfield (@code{extv}, @code{extzv}, and @code{insv})
3238 Here is an example, the definition of left-shift for the SPUR chip:
3242 (define_expand "ashlsi3"
3243 [(set (match_operand:SI 0 "register_operand" "")
3247 (match_operand:SI 1 "register_operand" "")
3248 (match_operand:SI 2 "nonmemory_operand" "")))]
3257 if (GET_CODE (operands[2]) != CONST_INT
3258 || (unsigned) INTVAL (operands[2]) > 3)
3265 This example uses @code{define_expand} so that it can generate an RTL insn
3266 for shifting when the shift-count is in the supported range of 0 to 3 but
3267 fail in other cases where machine insns aren't available. When it fails,
3268 the compiler tries another strategy using different patterns (such as, a
3271 If the compiler were able to handle nontrivial condition-strings in
3272 patterns with names, then it would be possible to use a
3273 @code{define_insn} in that case. Here is another case (zero-extension
3274 on the 68000) which makes more use of the power of @code{define_expand}:
3277 (define_expand "zero_extendhisi2"
3278 [(set (match_operand:SI 0 "general_operand" "")
3280 (set (strict_low_part
3284 (match_operand:HI 1 "general_operand" ""))]
3286 "operands[1] = make_safe_from (operands[1], operands[0]);")
3290 @findex make_safe_from
3291 Here two RTL insns are generated, one to clear the entire output operand
3292 and the other to copy the input operand into its low half. This sequence
3293 is incorrect if the input operand refers to [the old value of] the output
3294 operand, so the preparation statement makes sure this isn't so. The
3295 function @code{make_safe_from} copies the @code{operands[1]} into a
3296 temporary register if it refers to @code{operands[0]}. It does this
3297 by emitting another RTL insn.
3299 Finally, a third example shows the use of an internal operand.
3300 Zero-extension on the SPUR chip is done by @code{and}-ing the result
3301 against a halfword mask. But this mask cannot be represented by a
3302 @code{const_int} because the constant value is too large to be legitimate
3303 on this machine. So it must be copied into a register with
3304 @code{force_reg} and then the register used in the @code{and}.
3307 (define_expand "zero_extendhisi2"
3308 [(set (match_operand:SI 0 "register_operand" "")
3310 (match_operand:HI 1 "register_operand" "")
3315 = force_reg (SImode, GEN_INT (65535)); ")
3318 @strong{Note:} If the @code{define_expand} is used to serve a
3319 standard binary or unary arithmetic operation or a bitfield operation,
3320 then the last insn it generates must not be a @code{code_label},
3321 @code{barrier} or @code{note}. It must be an @code{insn},
3322 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
3323 at the end, emit an insn to copy the result of the operation into
3324 itself. Such an insn will generate no code, but it can avoid problems
3325 in the compiler.@refill
3327 @node Insn Splitting
3328 @section Defining How to Split Instructions
3329 @cindex insn splitting
3330 @cindex instruction splitting
3331 @cindex splitting instructions
3333 There are two cases where you should specify how to split a pattern into
3334 multiple insns. On machines that have instructions requiring delay
3335 slots (@pxref{Delay Slots}) or that have instructions whose output is
3336 not available for multiple cycles (@pxref{Function Units}), the compiler
3337 phases that optimize these cases need to be able to move insns into
3338 one-instruction delay slots. However, some insns may generate more than one
3339 machine instruction. These insns cannot be placed into a delay slot.
3341 Often you can rewrite the single insn as a list of individual insns,
3342 each corresponding to one machine instruction. The disadvantage of
3343 doing so is that it will cause the compilation to be slower and require
3344 more space. If the resulting insns are too complex, it may also
3345 suppress some optimizations. The compiler splits the insn if there is a
3346 reason to believe that it might improve instruction or delay slot
3349 The insn combiner phase also splits putative insns. If three insns are
3350 merged into one insn with a complex expression that cannot be matched by
3351 some @code{define_insn} pattern, the combiner phase attempts to split
3352 the complex pattern into two insns that are recognized. Usually it can
3353 break the complex pattern into two patterns by splitting out some
3354 subexpression. However, in some other cases, such as performing an
3355 addition of a large constant in two insns on a RISC machine, the way to
3356 split the addition into two insns is machine-dependent.
3358 @findex define_split
3359 The @code{define_split} definition tells the compiler how to split a
3360 complex insn into several simpler insns. It looks like this:
3364 [@var{insn-pattern}]
3366 [@var{new-insn-pattern-1}
3367 @var{new-insn-pattern-2}
3369 "@var{preparation statements}")
3372 @var{insn-pattern} is a pattern that needs to be split and
3373 @var{condition} is the final condition to be tested, as in a
3374 @code{define_insn}. When an insn matching @var{insn-pattern} and
3375 satisfying @var{condition} is found, it is replaced in the insn list
3376 with the insns given by @var{new-insn-pattern-1},
3377 @var{new-insn-pattern-2}, etc.
3379 The @var{preparation statements} are similar to those statements that
3380 are specified for @code{define_expand} (@pxref{Expander Definitions})
3381 and are executed before the new RTL is generated to prepare for the
3382 generated code or emit some insns whose pattern is not fixed. Unlike
3383 those in @code{define_expand}, however, these statements must not
3384 generate any new pseudo-registers. Once reload has completed, they also
3385 must not allocate any space in the stack frame.
3387 Patterns are matched against @var{insn-pattern} in two different
3388 circumstances. If an insn needs to be split for delay slot scheduling
3389 or insn scheduling, the insn is already known to be valid, which means
3390 that it must have been matched by some @code{define_insn} and, if
3391 @code{reload_completed} is non-zero, is known to satisfy the constraints
3392 of that @code{define_insn}. In that case, the new insn patterns must
3393 also be insns that are matched by some @code{define_insn} and, if
3394 @code{reload_completed} is non-zero, must also satisfy the constraints
3395 of those definitions.
3397 As an example of this usage of @code{define_split}, consider the following
3398 example from @file{a29k.md}, which splits a @code{sign_extend} from
3399 @code{HImode} to @code{SImode} into a pair of shift insns:
3403 [(set (match_operand:SI 0 "gen_reg_operand" "")
3404 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
3407 (ashift:SI (match_dup 1)
3410 (ashiftrt:SI (match_dup 0)
3413 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
3416 When the combiner phase tries to split an insn pattern, it is always the
3417 case that the pattern is @emph{not} matched by any @code{define_insn}.
3418 The combiner pass first tries to split a single @code{set} expression
3419 and then the same @code{set} expression inside a @code{parallel}, but
3420 followed by a @code{clobber} of a pseudo-reg to use as a scratch
3421 register. In these cases, the combiner expects exactly two new insn
3422 patterns to be generated. It will verify that these patterns match some
3423 @code{define_insn} definitions, so you need not do this test in the
3424 @code{define_split} (of course, there is no point in writing a
3425 @code{define_split} that will never produce insns that match).
3427 Here is an example of this use of @code{define_split}, taken from
3432 [(set (match_operand:SI 0 "gen_reg_operand" "")
3433 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
3434 (match_operand:SI 2 "non_add_cint_operand" "")))]
3436 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
3437 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
3440 int low = INTVAL (operands[2]) & 0xffff;
3441 int high = (unsigned) INTVAL (operands[2]) >> 16;
3444 high++, low |= 0xffff0000;
3446 operands[3] = GEN_INT (high << 16);
3447 operands[4] = GEN_INT (low);
3451 Here the predicate @code{non_add_cint_operand} matches any
3452 @code{const_int} that is @emph{not} a valid operand of a single add
3453 insn. The add with the smaller displacement is written so that it
3454 can be substituted into the address of a subsequent operation.
3456 An example that uses a scratch register, from the same file, generates
3457 an equality comparison of a register and a large constant:
3461 [(set (match_operand:CC 0 "cc_reg_operand" "")
3462 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3463 (match_operand:SI 2 "non_short_cint_operand" "")))
3464 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
3465 "find_single_use (operands[0], insn, 0)
3466 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3467 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3468 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3469 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3472 /* Get the constant we are comparing against, C, and see what it
3473 looks like sign-extended to 16 bits. Then see what constant
3474 could be XOR'ed with C to get the sign-extended value. */
3476 int c = INTVAL (operands[2]);
3477 int sextc = (c << 16) >> 16;
3478 int xorv = c ^ sextc;
3480 operands[4] = GEN_INT (xorv);
3481 operands[5] = GEN_INT (sextc);
3485 To avoid confusion, don't write a single @code{define_split} that
3486 accepts some insns that match some @code{define_insn} as well as some
3487 insns that don't. Instead, write two separate @code{define_split}
3488 definitions, one for the insns that are valid and one for the insns that
3491 For the common case where the pattern of a define_split exactly matches the
3492 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
3496 (define_insn_and_split
3497 [@var{insn-pattern}]
3499 "@var{output-template}"
3500 "@var{split-condition}"
3501 [@var{new-insn-pattern-1}
3502 @var{new-insn-pattern-2}
3504 "@var{preparation statements}"
3505 [@var{insn-attributes}])
3509 @var{insn-pattern}, @var{condition}, @var{output-template}, and
3510 @var{insn-attributes} are used as in @code{define_insn}. The
3511 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
3512 in a @code{define_split}. The @var{split-condition} is also used as in
3513 @code{define_split}, with the additional behavior that if the condition starts
3514 with @samp{&&}, the condition used for the split will be the constructed as a
3515 logical "and" of the split condition with the insn condition. For example,
3519 (define_insn_and_split "zero_extendhisi2_and"
3520 [(set (match_operand:SI 0 "register_operand" "=r")
3521 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3522 (clobber (reg:CC 17))]
3523 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3525 "&& reload_completed"
3526 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3527 (clobber (reg:CC 17))])]
3529 [(set_attr "type" "alu1")])
3533 In this case, the actual split condition will be
3534 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed."
3536 The @code{define_insn_and_split} construction provides exactly the same
3537 functionality as two separate @code{define_insn} and @code{define_split}
3538 patterns. It exists for compactness, and as a maintenance tool to prevent
3539 having to ensure the two patterns' templates match.
3541 @node Peephole Definitions
3542 @section Machine-Specific Peephole Optimizers
3543 @cindex peephole optimizer definitions
3544 @cindex defining peephole optimizers
3546 In addition to instruction patterns the @file{md} file may contain
3547 definitions of machine-specific peephole optimizations.
3549 The combiner does not notice certain peephole optimizations when the data
3550 flow in the program does not suggest that it should try them. For example,
3551 sometimes two consecutive insns related in purpose can be combined even
3552 though the second one does not appear to use a register computed in the
3553 first one. A machine-specific peephole optimizer can detect such
3556 There are two forms of peephole definitions that may be used. The
3557 original @code{define_peephole} is run at assembly output time to
3558 match insns and substitute assembly text. Use of @code{define_peephole}
3561 A newer @code{define_peephole2} matches insns and substitutes new
3562 insns. The @code{peephole2} pass is run after register allocation
3563 but before scheduling, which may result in much better code for
3564 targets that do scheduling.
3567 * define_peephole:: RTL to Text Peephole Optimizers
3568 * define_peephole2:: RTL to RTL Peephole Optimizers
3571 @node define_peephole
3572 @subsection RTL to Text Peephole Optimizers
3573 @findex define_peephole
3576 A definition looks like this:
3580 [@var{insn-pattern-1}
3581 @var{insn-pattern-2}
3585 "@var{optional insn-attributes}")
3589 The last string operand may be omitted if you are not using any
3590 machine-specific information in this machine description. If present,
3591 it must obey the same rules as in a @code{define_insn}.
3593 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
3594 consecutive insns. The optimization applies to a sequence of insns when
3595 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
3596 the next, and so on.@refill
3598 Each of the insns matched by a peephole must also match a
3599 @code{define_insn}. Peepholes are checked only at the last stage just
3600 before code generation, and only optionally. Therefore, any insn which
3601 would match a peephole but no @code{define_insn} will cause a crash in code
3602 generation in an unoptimized compilation, or at various optimization
3605 The operands of the insns are matched with @code{match_operands},
3606 @code{match_operator}, and @code{match_dup}, as usual. What is not
3607 usual is that the operand numbers apply to all the insn patterns in the
3608 definition. So, you can check for identical operands in two insns by
3609 using @code{match_operand} in one insn and @code{match_dup} in the
3612 The operand constraints used in @code{match_operand} patterns do not have
3613 any direct effect on the applicability of the peephole, but they will
3614 be validated afterward, so make sure your constraints are general enough
3615 to apply whenever the peephole matches. If the peephole matches
3616 but the constraints are not satisfied, the compiler will crash.
3618 It is safe to omit constraints in all the operands of the peephole; or
3619 you can write constraints which serve as a double-check on the criteria
3622 Once a sequence of insns matches the patterns, the @var{condition} is
3623 checked. This is a C expression which makes the final decision whether to
3624 perform the optimization (we do so if the expression is nonzero). If
3625 @var{condition} is omitted (in other words, the string is empty) then the
3626 optimization is applied to every sequence of insns that matches the
3629 The defined peephole optimizations are applied after register allocation
3630 is complete. Therefore, the peephole definition can check which
3631 operands have ended up in which kinds of registers, just by looking at
3634 @findex prev_active_insn
3635 The way to refer to the operands in @var{condition} is to write
3636 @code{operands[@var{i}]} for operand number @var{i} (as matched by
3637 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
3638 to refer to the last of the insns being matched; use
3639 @code{prev_active_insn} to find the preceding insns.
3641 @findex dead_or_set_p
3642 When optimizing computations with intermediate results, you can use
3643 @var{condition} to match only when the intermediate results are not used
3644 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
3645 @var{op})}, where @var{insn} is the insn in which you expect the value
3646 to be used for the last time (from the value of @code{insn}, together
3647 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
3648 value (from @code{operands[@var{i}]}).@refill
3650 Applying the optimization means replacing the sequence of insns with one
3651 new insn. The @var{template} controls ultimate output of assembler code
3652 for this combined insn. It works exactly like the template of a
3653 @code{define_insn}. Operand numbers in this template are the same ones
3654 used in matching the original sequence of insns.
3656 The result of a defined peephole optimizer does not need to match any of
3657 the insn patterns in the machine description; it does not even have an
3658 opportunity to match them. The peephole optimizer definition itself serves
3659 as the insn pattern to control how the insn is output.
3661 Defined peephole optimizers are run as assembler code is being output,
3662 so the insns they produce are never combined or rearranged in any way.
3664 Here is an example, taken from the 68000 machine description:
3668 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
3669 (set (match_operand:DF 0 "register_operand" "=f")
3670 (match_operand:DF 1 "register_operand" "ad"))]
3671 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
3675 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
3677 output_asm_insn (\"move.l %1,(sp)\", xoperands);
3678 output_asm_insn (\"move.l %1,-(sp)\", operands);
3679 return \"fmove.d (sp)+,%0\";
3681 output_asm_insn (\"movel %1,sp@@\", xoperands);
3682 output_asm_insn (\"movel %1,sp@@-\", operands);
3683 return \"fmoved sp@@+,%0\";
3690 The effect of this optimization is to change
3716 If a peephole matches a sequence including one or more jump insns, you must
3717 take account of the flags such as @code{CC_REVERSED} which specify that the
3718 condition codes are represented in an unusual manner. The compiler
3719 automatically alters any ordinary conditional jumps which occur in such
3720 situations, but the compiler cannot alter jumps which have been replaced by
3721 peephole optimizations. So it is up to you to alter the assembler code
3722 that the peephole produces. Supply C code to write the assembler output,
3723 and in this C code check the condition code status flags and change the
3724 assembler code as appropriate.
3727 @var{insn-pattern-1} and so on look @emph{almost} like the second
3728 operand of @code{define_insn}. There is one important difference: the
3729 second operand of @code{define_insn} consists of one or more RTX's
3730 enclosed in square brackets. Usually, there is only one: then the same
3731 action can be written as an element of a @code{define_peephole}. But
3732 when there are multiple actions in a @code{define_insn}, they are
3733 implicitly enclosed in a @code{parallel}. Then you must explicitly
3734 write the @code{parallel}, and the square brackets within it, in the
3735 @code{define_peephole}. Thus, if an insn pattern looks like this,
3738 (define_insn "divmodsi4"
3739 [(set (match_operand:SI 0 "general_operand" "=d")
3740 (div:SI (match_operand:SI 1 "general_operand" "0")
3741 (match_operand:SI 2 "general_operand" "dmsK")))
3742 (set (match_operand:SI 3 "general_operand" "=d")
3743 (mod:SI (match_dup 1) (match_dup 2)))]
3745 "divsl%.l %2,%3:%0")
3749 then the way to mention this insn in a peephole is as follows:
3755 [(set (match_operand:SI 0 "general_operand" "=d")
3756 (div:SI (match_operand:SI 1 "general_operand" "0")
3757 (match_operand:SI 2 "general_operand" "dmsK")))
3758 (set (match_operand:SI 3 "general_operand" "=d")
3759 (mod:SI (match_dup 1) (match_dup 2)))])
3764 @node define_peephole2
3765 @subsection RTL to RTL Peephole Optimizers
3766 @findex define_peephole2
3768 The @code{define_peephole2} definition tells the compiler how to
3769 substitute one sequence of instructions for another sequence,
3770 what additional scratch registers may be needed and what their
3775 [@var{insn-pattern-1}
3776 @var{insn-pattern-2}
3779 [@var{new-insn-pattern-1}
3780 @var{new-insn-pattern-2}
3782 "@var{preparation statements}")
3785 The definition is almost identical to @code{define_split}
3786 (@pxref{Insn Splitting}) except that the pattern to match is not a
3787 single instruction, but a sequence of instructions.
3789 It is possible to request additional scratch registers for use in the
3790 output template. If appropriate registers are not free, the pattern
3791 will simply not match.
3793 @findex match_scratch
3795 Scratch registers are requested with a @code{match_scratch} pattern at
3796 the top level of the input pattern. The allocated register (initially) will
3797 be dead at the point requested within the original sequence. If the scratch
3798 is used at more than a single point, a @code{match_dup} pattern at the
3799 top level of the input pattern marks the last position in the input sequence
3800 at which the register must be available.
3802 Here is an example from the IA-32 machine description:
3806 [(match_scratch:SI 2 "r")
3807 (parallel [(set (match_operand:SI 0 "register_operand" "")
3808 (match_operator:SI 3 "arith_or_logical_operator"
3810 (match_operand:SI 1 "memory_operand" "")]))
3811 (clobber (reg:CC 17))])]
3812 "! optimize_size && ! TARGET_READ_MODIFY"
3813 [(set (match_dup 2) (match_dup 1))
3814 (parallel [(set (match_dup 0)
3815 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
3816 (clobber (reg:CC 17))])]
3821 This pattern tries to split a load from its use in the hopes that we'll be
3822 able to schedule around the memory load latency. It allocates a single
3823 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
3824 to be live only at the point just before the arithmetic.
3826 A real example requiring extended scratch lifetimes is harder to come by,
3827 so here's a silly made-up example:
3831 [(match_scratch:SI 4 "r")
3832 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
3833 (set (match_operand:SI 2 "" "") (match_dup 1))
3835 (set (match_operand:SI 3 "" "") (match_dup 1))]
3836 "@var{determine 1 does not overlap 0 and 2}"
3837 [(set (match_dup 4) (match_dup 1))
3838 (set (match_dup 0) (match_dup 4))
3839 (set (match_dup 2) (match_dup 4))]
3840 (set (match_dup 3) (match_dup 4))]
3845 If we had not added the @code{(match_dup 4)} in the middle of the input
3846 sequence, it might have been the case that the register we chose at the
3847 beginning of the sequence is killed by the first or second @code{set}.
3849 @node Insn Attributes
3850 @section Instruction Attributes
3851 @cindex insn attributes
3852 @cindex instruction attributes
3854 In addition to describing the instruction supported by the target machine,
3855 the @file{md} file also defines a group of @dfn{attributes} and a set of
3856 values for each. Every generated insn is assigned a value for each attribute.
3857 One possible attribute would be the effect that the insn has on the machine's
3858 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
3859 to track the condition codes.
3862 * Defining Attributes:: Specifying attributes and their values.
3863 * Expressions:: Valid expressions for attribute values.
3864 * Tagging Insns:: Assigning attribute values to insns.
3865 * Attr Example:: An example of assigning attributes.
3866 * Insn Lengths:: Computing the length of insns.
3867 * Constant Attributes:: Defining attributes that are constant.
3868 * Delay Slots:: Defining delay slots required for a machine.
3869 * Function Units:: Specifying information for insn scheduling.
3872 @node Defining Attributes
3873 @subsection Defining Attributes and their Values
3874 @cindex defining attributes and their values
3875 @cindex attributes, defining
3878 The @code{define_attr} expression is used to define each attribute required
3879 by the target machine. It looks like:
3882 (define_attr @var{name} @var{list-of-values} @var{default})
3885 @var{name} is a string specifying the name of the attribute being defined.
3887 @var{list-of-values} is either a string that specifies a comma-separated
3888 list of values that can be assigned to the attribute, or a null string to
3889 indicate that the attribute takes numeric values.
3891 @var{default} is an attribute expression that gives the value of this
3892 attribute for insns that match patterns whose definition does not include
3893 an explicit value for this attribute. @xref{Attr Example}, for more
3894 information on the handling of defaults. @xref{Constant Attributes},
3895 for information on attributes that do not depend on any particular insn.
3898 For each defined attribute, a number of definitions are written to the
3899 @file{insn-attr.h} file. For cases where an explicit set of values is
3900 specified for an attribute, the following are defined:
3904 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
3907 An enumeral class is defined for @samp{attr_@var{name}} with
3908 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
3909 the attribute name and value are first converted to upper case.
3912 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
3913 returns the attribute value for that insn.
3916 For example, if the following is present in the @file{md} file:
3919 (define_attr "type" "branch,fp,load,store,arith" @dots{})
3923 the following lines will be written to the file @file{insn-attr.h}.
3926 #define HAVE_ATTR_type
3927 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
3928 TYPE_STORE, TYPE_ARITH@};
3929 extern enum attr_type get_attr_type ();
3932 If the attribute takes numeric values, no @code{enum} type will be
3933 defined and the function to obtain the attribute's value will return
3937 @subsection Attribute Expressions
3938 @cindex attribute expressions
3940 RTL expressions used to define attributes use the codes described above
3941 plus a few specific to attribute definitions, to be discussed below.
3942 Attribute value expressions must have one of the following forms:
3945 @cindex @code{const_int} and attributes
3946 @item (const_int @var{i})
3947 The integer @var{i} specifies the value of a numeric attribute. @var{i}
3948 must be non-negative.
3950 The value of a numeric attribute can be specified either with a
3951 @code{const_int}, or as an integer represented as a string in
3952 @code{const_string}, @code{eq_attr} (see below), @code{attr},
3953 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
3954 overrides on specific instructions (@pxref{Tagging Insns}).
3956 @cindex @code{const_string} and attributes
3957 @item (const_string @var{value})
3958 The string @var{value} specifies a constant attribute value.
3959 If @var{value} is specified as @samp{"*"}, it means that the default value of
3960 the attribute is to be used for the insn containing this expression.
3961 @samp{"*"} obviously cannot be used in the @var{default} expression
3962 of a @code{define_attr}.@refill
3964 If the attribute whose value is being specified is numeric, @var{value}
3965 must be a string containing a non-negative integer (normally
3966 @code{const_int} would be used in this case). Otherwise, it must
3967 contain one of the valid values for the attribute.
3969 @cindex @code{if_then_else} and attributes
3970 @item (if_then_else @var{test} @var{true-value} @var{false-value})
3971 @var{test} specifies an attribute test, whose format is defined below.
3972 The value of this expression is @var{true-value} if @var{test} is true,
3973 otherwise it is @var{false-value}.
3975 @cindex @code{cond} and attributes
3976 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
3977 The first operand of this expression is a vector containing an even
3978 number of expressions and consisting of pairs of @var{test} and @var{value}
3979 expressions. The value of the @code{cond} expression is that of the
3980 @var{value} corresponding to the first true @var{test} expression. If
3981 none of the @var{test} expressions are true, the value of the @code{cond}
3982 expression is that of the @var{default} expression.
3985 @var{test} expressions can have one of the following forms:
3988 @cindex @code{const_int} and attribute tests
3989 @item (const_int @var{i})
3990 This test is true if @var{i} is non-zero and false otherwise.
3992 @cindex @code{not} and attributes
3993 @cindex @code{ior} and attributes
3994 @cindex @code{and} and attributes
3995 @item (not @var{test})
3996 @itemx (ior @var{test1} @var{test2})
3997 @itemx (and @var{test1} @var{test2})
3998 These tests are true if the indicated logical function is true.
4000 @cindex @code{match_operand} and attributes
4001 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
4002 This test is true if operand @var{n} of the insn whose attribute value
4003 is being determined has mode @var{m} (this part of the test is ignored
4004 if @var{m} is @code{VOIDmode}) and the function specified by the string
4005 @var{pred} returns a non-zero value when passed operand @var{n} and mode
4006 @var{m} (this part of the test is ignored if @var{pred} is the null
4009 The @var{constraints} operand is ignored and should be the null string.
4011 @cindex @code{le} and attributes
4012 @cindex @code{leu} and attributes
4013 @cindex @code{lt} and attributes
4014 @cindex @code{gt} and attributes
4015 @cindex @code{gtu} and attributes
4016 @cindex @code{ge} and attributes
4017 @cindex @code{geu} and attributes
4018 @cindex @code{ne} and attributes
4019 @cindex @code{eq} and attributes
4020 @cindex @code{plus} and attributes
4021 @cindex @code{minus} and attributes
4022 @cindex @code{mult} and attributes
4023 @cindex @code{div} and attributes
4024 @cindex @code{mod} and attributes
4025 @cindex @code{abs} and attributes
4026 @cindex @code{neg} and attributes
4027 @cindex @code{ashift} and attributes
4028 @cindex @code{lshiftrt} and attributes
4029 @cindex @code{ashiftrt} and attributes
4030 @item (le @var{arith1} @var{arith2})
4031 @itemx (leu @var{arith1} @var{arith2})
4032 @itemx (lt @var{arith1} @var{arith2})
4033 @itemx (ltu @var{arith1} @var{arith2})
4034 @itemx (gt @var{arith1} @var{arith2})
4035 @itemx (gtu @var{arith1} @var{arith2})
4036 @itemx (ge @var{arith1} @var{arith2})
4037 @itemx (geu @var{arith1} @var{arith2})
4038 @itemx (ne @var{arith1} @var{arith2})
4039 @itemx (eq @var{arith1} @var{arith2})
4040 These tests are true if the indicated comparison of the two arithmetic
4041 expressions is true. Arithmetic expressions are formed with
4042 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
4043 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
4044 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.@refill
4047 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
4048 Lengths},for additional forms). @code{symbol_ref} is a string
4049 denoting a C expression that yields an @code{int} when evaluated by the
4050 @samp{get_attr_@dots{}} routine. It should normally be a global
4054 @item (eq_attr @var{name} @var{value})
4055 @var{name} is a string specifying the name of an attribute.
4057 @var{value} is a string that is either a valid value for attribute
4058 @var{name}, a comma-separated list of values, or @samp{!} followed by a
4059 value or list. If @var{value} does not begin with a @samp{!}, this
4060 test is true if the value of the @var{name} attribute of the current
4061 insn is in the list specified by @var{value}. If @var{value} begins
4062 with a @samp{!}, this test is true if the attribute's value is
4063 @emph{not} in the specified list.
4068 (eq_attr "type" "load,store")
4075 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
4078 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
4079 value of the compiler variable @code{which_alternative}
4080 (@pxref{Output Statement}) and the values must be small integers. For
4084 (eq_attr "alternative" "2,3")
4091 (ior (eq (symbol_ref "which_alternative") (const_int 2))
4092 (eq (symbol_ref "which_alternative") (const_int 3)))
4095 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
4096 where the value of the attribute being tested is known for all insns matching
4097 a particular pattern. This is by far the most common case.@refill
4100 @item (attr_flag @var{name})
4101 The value of an @code{attr_flag} expression is true if the flag
4102 specified by @var{name} is true for the @code{insn} currently being
4105 @var{name} is a string specifying one of a fixed set of flags to test.
4106 Test the flags @code{forward} and @code{backward} to determine the
4107 direction of a conditional branch. Test the flags @code{very_likely},
4108 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
4109 if a conditional branch is expected to be taken.
4111 If the @code{very_likely} flag is true, then the @code{likely} flag is also
4112 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
4114 This example describes a conditional branch delay slot which
4115 can be nullified for forward branches that are taken (annul-true) or
4116 for backward branches which are not taken (annul-false).
4119 (define_delay (eq_attr "type" "cbranch")
4120 [(eq_attr "in_branch_delay" "true")
4121 (and (eq_attr "in_branch_delay" "true")
4122 (attr_flag "forward"))
4123 (and (eq_attr "in_branch_delay" "true")
4124 (attr_flag "backward"))])
4127 The @code{forward} and @code{backward} flags are false if the current
4128 @code{insn} being scheduled is not a conditional branch.
4130 The @code{very_likely} and @code{likely} flags are true if the
4131 @code{insn} being scheduled is not a conditional branch.
4132 The @code{very_unlikely} and @code{unlikely} flags are false if the
4133 @code{insn} being scheduled is not a conditional branch.
4135 @code{attr_flag} is only used during delay slot scheduling and has no
4136 meaning to other passes of the compiler.
4139 @item (attr @var{name})
4140 The value of another attribute is returned. This is most useful
4141 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
4142 produce more efficient code for non-numeric attributes.
4146 @subsection Assigning Attribute Values to Insns
4147 @cindex tagging insns
4148 @cindex assigning attribute values to insns
4150 The value assigned to an attribute of an insn is primarily determined by
4151 which pattern is matched by that insn (or which @code{define_peephole}
4152 generated it). Every @code{define_insn} and @code{define_peephole} can
4153 have an optional last argument to specify the values of attributes for
4154 matching insns. The value of any attribute not specified in a particular
4155 insn is set to the default value for that attribute, as specified in its
4156 @code{define_attr}. Extensive use of default values for attributes
4157 permits the specification of the values for only one or two attributes
4158 in the definition of most insn patterns, as seen in the example in the
4159 next section.@refill
4161 The optional last argument of @code{define_insn} and
4162 @code{define_peephole} is a vector of expressions, each of which defines
4163 the value for a single attribute. The most general way of assigning an
4164 attribute's value is to use a @code{set} expression whose first operand is an
4165 @code{attr} expression giving the name of the attribute being set. The
4166 second operand of the @code{set} is an attribute expression
4167 (@pxref{Expressions}) giving the value of the attribute.@refill
4169 When the attribute value depends on the @samp{alternative} attribute
4170 (i.e., which is the applicable alternative in the constraint of the
4171 insn), the @code{set_attr_alternative} expression can be used. It
4172 allows the specification of a vector of attribute expressions, one for
4176 When the generality of arbitrary attribute expressions is not required,
4177 the simpler @code{set_attr} expression can be used, which allows
4178 specifying a string giving either a single attribute value or a list
4179 of attribute values, one for each alternative.
4181 The form of each of the above specifications is shown below. In each case,
4182 @var{name} is a string specifying the attribute to be set.
4185 @item (set_attr @var{name} @var{value-string})
4186 @var{value-string} is either a string giving the desired attribute value,
4187 or a string containing a comma-separated list giving the values for
4188 succeeding alternatives. The number of elements must match the number
4189 of alternatives in the constraint of the insn pattern.
4191 Note that it may be useful to specify @samp{*} for some alternative, in
4192 which case the attribute will assume its default value for insns matching
4195 @findex set_attr_alternative
4196 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
4197 Depending on the alternative of the insn, the value will be one of the
4198 specified values. This is a shorthand for using a @code{cond} with
4199 tests on the @samp{alternative} attribute.
4202 @item (set (attr @var{name}) @var{value})
4203 The first operand of this @code{set} must be the special RTL expression
4204 @code{attr}, whose sole operand is a string giving the name of the
4205 attribute being set. @var{value} is the value of the attribute.
4208 The following shows three different ways of representing the same
4209 attribute value specification:
4212 (set_attr "type" "load,store,arith")
4214 (set_attr_alternative "type"
4215 [(const_string "load") (const_string "store")
4216 (const_string "arith")])
4219 (cond [(eq_attr "alternative" "1") (const_string "load")
4220 (eq_attr "alternative" "2") (const_string "store")]
4221 (const_string "arith")))
4225 @findex define_asm_attributes
4226 The @code{define_asm_attributes} expression provides a mechanism to
4227 specify the attributes assigned to insns produced from an @code{asm}
4228 statement. It has the form:
4231 (define_asm_attributes [@var{attr-sets}])
4235 where @var{attr-sets} is specified the same as for both the
4236 @code{define_insn} and the @code{define_peephole} expressions.
4238 These values will typically be the ``worst case'' attribute values. For
4239 example, they might indicate that the condition code will be clobbered.
4241 A specification for a @code{length} attribute is handled specially. The
4242 way to compute the length of an @code{asm} insn is to multiply the
4243 length specified in the expression @code{define_asm_attributes} by the
4244 number of machine instructions specified in the @code{asm} statement,
4245 determined by counting the number of semicolons and newlines in the
4246 string. Therefore, the value of the @code{length} attribute specified
4247 in a @code{define_asm_attributes} should be the maximum possible length
4248 of a single machine instruction.
4251 @subsection Example of Attribute Specifications
4252 @cindex attribute specifications example
4253 @cindex attribute specifications
4255 The judicious use of defaulting is important in the efficient use of
4256 insn attributes. Typically, insns are divided into @dfn{types} and an
4257 attribute, customarily called @code{type}, is used to represent this
4258 value. This attribute is normally used only to define the default value
4259 for other attributes. An example will clarify this usage.
4261 Assume we have a RISC machine with a condition code and in which only
4262 full-word operations are performed in registers. Let us assume that we
4263 can divide all insns into loads, stores, (integer) arithmetic
4264 operations, floating point operations, and branches.
4266 Here we will concern ourselves with determining the effect of an insn on
4267 the condition code and will limit ourselves to the following possible
4268 effects: The condition code can be set unpredictably (clobbered), not
4269 be changed, be set to agree with the results of the operation, or only
4270 changed if the item previously set into the condition code has been
4273 Here is part of a sample @file{md} file for such a machine:
4276 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
4278 (define_attr "cc" "clobber,unchanged,set,change0"
4279 (cond [(eq_attr "type" "load")
4280 (const_string "change0")
4281 (eq_attr "type" "store,branch")
4282 (const_string "unchanged")
4283 (eq_attr "type" "arith")
4284 (if_then_else (match_operand:SI 0 "" "")
4285 (const_string "set")
4286 (const_string "clobber"))]
4287 (const_string "clobber")))
4290 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
4291 (match_operand:SI 1 "general_operand" "r,m,r"))]
4297 [(set_attr "type" "arith,load,store")])
4300 Note that we assume in the above example that arithmetic operations
4301 performed on quantities smaller than a machine word clobber the condition
4302 code since they will set the condition code to a value corresponding to the
4306 @subsection Computing the Length of an Insn
4307 @cindex insn lengths, computing
4308 @cindex computing the length of an insn
4310 For many machines, multiple types of branch instructions are provided, each
4311 for different length branch displacements. In most cases, the assembler
4312 will choose the correct instruction to use. However, when the assembler
4313 cannot do so, GCC can when a special attribute, the @samp{length}
4314 attribute, is defined. This attribute must be defined to have numeric
4315 values by specifying a null string in its @code{define_attr}.
4317 In the case of the @samp{length} attribute, two additional forms of
4318 arithmetic terms are allowed in test expressions:
4321 @cindex @code{match_dup} and attributes
4322 @item (match_dup @var{n})
4323 This refers to the address of operand @var{n} of the current insn, which
4324 must be a @code{label_ref}.
4326 @cindex @code{pc} and attributes
4328 This refers to the address of the @emph{current} insn. It might have
4329 been more consistent with other usage to make this the address of the
4330 @emph{next} insn but this would be confusing because the length of the
4331 current insn is to be computed.
4334 @cindex @code{addr_vec}, length of
4335 @cindex @code{addr_diff_vec}, length of
4336 For normal insns, the length will be determined by value of the
4337 @samp{length} attribute. In the case of @code{addr_vec} and
4338 @code{addr_diff_vec} insn patterns, the length is computed as
4339 the number of vectors multiplied by the size of each vector.
4341 Lengths are measured in addressable storage units (bytes).
4343 The following macros can be used to refine the length computation:
4346 @findex FIRST_INSN_ADDRESS
4347 @item FIRST_INSN_ADDRESS
4348 When the @code{length} insn attribute is used, this macro specifies the
4349 value to be assigned to the address of the first insn in a function. If
4350 not specified, 0 is used.
4352 @findex ADJUST_INSN_LENGTH
4353 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
4354 If defined, modifies the length assigned to instruction @var{insn} as a
4355 function of the context in which it is used. @var{length} is an lvalue
4356 that contains the initially computed length of the insn and should be
4357 updated with the correct length of the insn.
4359 This macro will normally not be required. A case in which it is
4360 required is the ROMP. On this machine, the size of an @code{addr_vec}
4361 insn must be increased by two to compensate for the fact that alignment
4365 @findex get_attr_length
4366 The routine that returns @code{get_attr_length} (the value of the
4367 @code{length} attribute) can be used by the output routine to
4368 determine the form of the branch instruction to be written, as the
4369 example below illustrates.
4371 As an example of the specification of variable-length branches, consider
4372 the IBM 360. If we adopt the convention that a register will be set to
4373 the starting address of a function, we can jump to labels within 4k of
4374 the start using a four-byte instruction. Otherwise, we need a six-byte
4375 sequence to load the address from memory and then branch to it.
4377 On such a machine, a pattern for a branch instruction might be specified
4383 (label_ref (match_operand 0 "" "")))]
4387 return (get_attr_length (insn) == 4
4388 ? \"b %l0\" : \"l r15,=a(%l0); br r15\");
4390 [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
4395 @node Constant Attributes
4396 @subsection Constant Attributes
4397 @cindex constant attributes
4399 A special form of @code{define_attr}, where the expression for the
4400 default value is a @code{const} expression, indicates an attribute that
4401 is constant for a given run of the compiler. Constant attributes may be
4402 used to specify which variety of processor is used. For example,
4405 (define_attr "cpu" "m88100,m88110,m88000"
4407 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
4408 (symbol_ref "TARGET_88110") (const_string "m88110")]
4409 (const_string "m88000"))))
4411 (define_attr "memory" "fast,slow"
4413 (if_then_else (symbol_ref "TARGET_FAST_MEM")
4414 (const_string "fast")
4415 (const_string "slow"))))
4418 The routine generated for constant attributes has no parameters as it
4419 does not depend on any particular insn. RTL expressions used to define
4420 the value of a constant attribute may use the @code{symbol_ref} form,
4421 but may not use either the @code{match_operand} form or @code{eq_attr}
4422 forms involving insn attributes.
4425 @subsection Delay Slot Scheduling
4426 @cindex delay slots, defining
4428 The insn attribute mechanism can be used to specify the requirements for
4429 delay slots, if any, on a target machine. An instruction is said to
4430 require a @dfn{delay slot} if some instructions that are physically
4431 after the instruction are executed as if they were located before it.
4432 Classic examples are branch and call instructions, which often execute
4433 the following instruction before the branch or call is performed.
4435 On some machines, conditional branch instructions can optionally
4436 @dfn{annul} instructions in the delay slot. This means that the
4437 instruction will not be executed for certain branch outcomes. Both
4438 instructions that annul if the branch is true and instructions that
4439 annul if the branch is false are supported.
4441 Delay slot scheduling differs from instruction scheduling in that
4442 determining whether an instruction needs a delay slot is dependent only
4443 on the type of instruction being generated, not on data flow between the
4444 instructions. See the next section for a discussion of data-dependent
4445 instruction scheduling.
4447 @findex define_delay
4448 The requirement of an insn needing one or more delay slots is indicated
4449 via the @code{define_delay} expression. It has the following form:
4452 (define_delay @var{test}
4453 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
4454 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
4458 @var{test} is an attribute test that indicates whether this
4459 @code{define_delay} applies to a particular insn. If so, the number of
4460 required delay slots is determined by the length of the vector specified
4461 as the second argument. An insn placed in delay slot @var{n} must
4462 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
4463 attribute test that specifies which insns may be annulled if the branch
4464 is true. Similarly, @var{annul-false-n} specifies which insns in the
4465 delay slot may be annulled if the branch is false. If annulling is not
4466 supported for that delay slot, @code{(nil)} should be coded.@refill
4468 For example, in the common case where branch and call insns require
4469 a single delay slot, which may contain any insn other than a branch or
4470 call, the following would be placed in the @file{md} file:
4473 (define_delay (eq_attr "type" "branch,call")
4474 [(eq_attr "type" "!branch,call") (nil) (nil)])
4477 Multiple @code{define_delay} expressions may be specified. In this
4478 case, each such expression specifies different delay slot requirements
4479 and there must be no insn for which tests in two @code{define_delay}
4480 expressions are both true.
4482 For example, if we have a machine that requires one delay slot for branches
4483 but two for calls, no delay slot can contain a branch or call insn,
4484 and any valid insn in the delay slot for the branch can be annulled if the
4485 branch is true, we might represent this as follows:
4488 (define_delay (eq_attr "type" "branch")
4489 [(eq_attr "type" "!branch,call")
4490 (eq_attr "type" "!branch,call")
4493 (define_delay (eq_attr "type" "call")
4494 [(eq_attr "type" "!branch,call") (nil) (nil)
4495 (eq_attr "type" "!branch,call") (nil) (nil)])
4497 @c the above is *still* too long. --mew 4feb93
4499 @node Function Units
4500 @subsection Specifying Function Units
4501 @cindex function units, for scheduling
4503 On most RISC machines, there are instructions whose results are not
4504 available for a specific number of cycles. Common cases are instructions
4505 that load data from memory. On many machines, a pipeline stall will result
4506 if the data is referenced too soon after the load instruction.
4508 In addition, many newer microprocessors have multiple function units, usually
4509 one for integer and one for floating point, and often will incur pipeline
4510 stalls when a result that is needed is not yet ready.
4512 The descriptions in this section allow the specification of how much
4513 time must elapse between the execution of an instruction and the time
4514 when its result is used. It also allows specification of when the
4515 execution of an instruction will delay execution of similar instructions
4516 due to function unit conflicts.
4518 For the purposes of the specifications in this section, a machine is
4519 divided into @dfn{function units}, each of which execute a specific
4520 class of instructions in first-in-first-out order. Function units that
4521 accept one instruction each cycle and allow a result to be used in the
4522 succeeding instruction (usually via forwarding) need not be specified.
4523 Classic RISC microprocessors will normally have a single function unit,
4524 which we can call @samp{memory}. The newer ``superscalar'' processors
4525 will often have function units for floating point operations, usually at
4526 least a floating point adder and multiplier.
4528 @findex define_function_unit
4529 Each usage of a function units by a class of insns is specified with a
4530 @code{define_function_unit} expression, which looks like this:
4533 (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
4534 @var{test} @var{ready-delay} @var{issue-delay}
4535 [@var{conflict-list}])
4538 @var{name} is a string giving the name of the function unit.
4540 @var{multiplicity} is an integer specifying the number of identical
4541 units in the processor. If more than one unit is specified, they will
4542 be scheduled independently. Only truly independent units should be
4543 counted; a pipelined unit should be specified as a single unit. (The
4544 only common example of a machine that has multiple function units for a
4545 single instruction class that are truly independent and not pipelined
4546 are the two multiply and two increment units of the CDC 6600.)
4548 @var{simultaneity} specifies the maximum number of insns that can be
4549 executing in each instance of the function unit simultaneously or zero
4550 if the unit is pipelined and has no limit.
4552 All @code{define_function_unit} definitions referring to function unit
4553 @var{name} must have the same name and values for @var{multiplicity} and
4556 @var{test} is an attribute test that selects the insns we are describing
4557 in this definition. Note that an insn may use more than one function
4558 unit and a function unit may be specified in more than one
4559 @code{define_function_unit}.
4561 @var{ready-delay} is an integer that specifies the number of cycles
4562 after which the result of the instruction can be used without
4563 introducing any stalls.
4565 @var{issue-delay} is an integer that specifies the number of cycles
4566 after the instruction matching the @var{test} expression begins using
4567 this unit until a subsequent instruction can begin. A cost of @var{N}
4568 indicates an @var{N-1} cycle delay. A subsequent instruction may also
4569 be delayed if an earlier instruction has a longer @var{ready-delay}
4570 value. This blocking effect is computed using the @var{simultaneity},
4571 @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms.
4572 For a normal non-pipelined function unit, @var{simultaneity} is one, the
4573 unit is taken to block for the @var{ready-delay} cycles of the executing
4574 insn, and smaller values of @var{issue-delay} are ignored.
4576 @var{conflict-list} is an optional list giving detailed conflict costs
4577 for this unit. If specified, it is a list of condition test expressions
4578 to be applied to insns chosen to execute in @var{name} following the
4579 particular insn matching @var{test} that is already executing in
4580 @var{name}. For each insn in the list, @var{issue-delay} specifies the
4581 conflict cost; for insns not in the list, the cost is zero. If not
4582 specified, @var{conflict-list} defaults to all instructions that use the
4585 Typical uses of this vector are where a floating point function unit can
4586 pipeline either single- or double-precision operations, but not both, or
4587 where a memory unit can pipeline loads, but not stores, etc.
4589 As an example, consider a classic RISC machine where the result of a
4590 load instruction is not available for two cycles (a single ``delay''
4591 instruction is required) and where only one load instruction can be executed
4592 simultaneously. This would be specified as:
4595 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
4598 For the case of a floating point function unit that can pipeline either
4599 single or double precision, but not both, the following could be specified:
4602 (define_function_unit
4603 "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
4604 (define_function_unit
4605 "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])
4608 @strong{Note:} The scheduler attempts to avoid function unit conflicts
4609 and uses all the specifications in the @code{define_function_unit}
4610 expression. It has recently come to our attention that these
4611 specifications may not allow modeling of some of the newer
4612 ``superscalar'' processors that have insns using multiple pipelined
4613 units. These insns will cause a potential conflict for the second unit
4614 used during their execution and there is no way of representing that
4615 conflict. We welcome any examples of how function unit conflicts work
4616 in such processors and suggestions for their representation.
4619 @node Conditional Execution
4620 @section Conditional Execution
4621 @cindex conditional execution
4624 A number of architectures provide for some form of conditional
4625 execution, or predication. The hallmark of this feature is the
4626 ability to nullify most of the instructions in the instruction set.
4627 When the instruction set is large and not entirely symmetric, it
4628 can be quite tedious to describe these forms directly in the
4629 @file{.md} file. An alternative is the @code{define_cond_exec} template.
4631 @findex define_cond_exec
4634 [@var{predicate-pattern}]
4636 "@var{output template}")
4639 @var{predicate-pattern} is the condition that must be true for the
4640 insn to be executed at runtime and should match a relational operator.
4641 One can use @code{match_operator} to match several relational operators
4642 at once. Any @code{match_operand} operands must have no more than one
4645 @var{condition} is a C expression that must be true for the generated
4648 @findex current_insn_predicate
4649 @var{output template} is a string similar to the @code{define_insn}
4650 output template (@pxref{Output Template}), except that the @samp{*}
4651 and @samp{@@} special cases do not apply. This is only useful if the
4652 assembly text for the predicate is a simple prefix to the main insn.
4653 In order to handle the general case, there is a global variable
4654 @code{current_insn_predicate} that will contain the entire predicate
4655 if the current insn is predicated, and will otherwise be @code{NULL}.
4657 When @code{define_cond_exec} is used, an implicit reference to
4658 the @code{predicable} instruction attribute is made.
4659 @xref{Insn Attributes}. This attribute must be boolean (i.e. have
4660 exactly two elements in its @var{list-of-values}). Further, it must
4661 not be used with complex expressions. That is, the default and all
4662 uses in the insns must be a simple constant, not dependent on the
4663 alternative or anything else.
4665 For each @code{define_insn} for which the @code{predicable}
4666 attribute is true, a new @code{define_insn} pattern will be
4667 generated that matches a predicated version of the instruction.
4671 (define_insn "addsi"
4672 [(set (match_operand:SI 0 "register_operand" "r")
4673 (plus:SI (match_operand:SI 1 "register_operand" "r")
4674 (match_operand:SI 2 "register_operand" "r")))]
4679 [(ne (match_operand:CC 0 "register_operand" "c")
4686 generates a new pattern
4691 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
4692 (set (match_operand:SI 0 "register_operand" "r")
4693 (plus:SI (match_operand:SI 1 "register_operand" "r")
4694 (match_operand:SI 2 "register_operand" "r"))))]
4695 "(@var{test2}) && (@var{test1})"
4696 "(%3) add %2,%1,%0")
4699 @node Constant Definitions
4700 @section Constant Definitions
4701 @cindex constant definitions
4702 @findex define_constants
4704 Using literal constants inside instruction patterns reduces legibility and
4705 can be a maintenance problem.
4707 To overcome this problem, you may use the @code{define_constants}
4708 expression. It contains a vector of name-value pairs. From that
4709 point on, wherever any of the names appears in the MD file, it is as
4710 if the corresponding value had been written instead. You may use
4711 @code{define_constants} multiple times; each appearance adds more
4712 constants to the table. It is an error to redefine a constant with
4715 To come back to the a29k load multiple example, instead of
4719 [(match_parallel 0 "load_multiple_operation"
4720 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
4721 (match_operand:SI 2 "memory_operand" "m"))
4723 (clobber (reg:SI 179))])]
4739 [(match_parallel 0 "load_multiple_operation"
4740 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
4741 (match_operand:SI 2 "memory_operand" "m"))
4743 (clobber (reg:SI R_CR))])]
4748 The constants that are defined with a define_constant are also output
4749 in the insn-codes.h header file as #defines.