1 @c Copyright (C) 1988, 89, 92, 93, 94, 96, 1998, 2000 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Patterns:: How to write instruction patterns.
23 * Example:: An explained example of a @code{define_insn} pattern.
24 * RTL Template:: The RTL template defines what insns match a pattern.
25 * Output Template:: The output template says how to make assembler code
27 * Output Statement:: For more generality, write C code to output
29 * Constraints:: When not all operands are general operands.
30 * Standard Names:: Names mark patterns to use for code generation.
31 * Pattern Ordering:: When the order of patterns makes a difference.
32 * Dependent Patterns:: Having one pattern may make you need another.
33 * Jump Patterns:: Special considerations for patterns for jump insns.
34 * Insn Canonicalizations::Canonicalization of Instructions
35 * Expander Definitions::Generating a sequence of several RTL insns
36 for a standard operation.
37 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
38 * Peephole Definitions::Defining machine-specific peephole optimizations.
39 * Insn Attributes:: Specifying the value of attributes for generated insns.
40 * Conditional Execution::Generating @code{define_insn} patterns for
45 @section Everything about Instruction Patterns
47 @cindex instruction patterns
50 Each instruction pattern contains an incomplete RTL expression, with pieces
51 to be filled in later, operand constraints that restrict how the pieces can
52 be filled in, and an output pattern or C code to generate the assembler
53 output, all wrapped up in a @code{define_insn} expression.
55 A @code{define_insn} is an RTL expression containing four or five operands:
59 An optional name. The presence of a name indicate that this instruction
60 pattern can perform a certain standard job for the RTL-generation
61 pass of the compiler. This pass knows certain names and will use
62 the instruction patterns with those names, if the names are defined
63 in the machine description.
65 The absence of a name is indicated by writing an empty string
66 where the name should go. Nameless instruction patterns are never
67 used for generating RTL code, but they may permit several simpler insns
68 to be combined later on.
70 Names that are not thus known and used in RTL-generation have no
71 effect; they are equivalent to no name at all.
73 For the purpose of debugging the compiler, you may also specify a
74 name beginning with the @samp{*} character. Such a name is used only
75 for identifying the instruction in RTL dumps; it is entirely equivalent
76 to having a nameless pattern for all other purposes.
79 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
80 RTL expressions which show what the instruction should look like. It is
81 incomplete because it may contain @code{match_operand},
82 @code{match_operator}, and @code{match_dup} expressions that stand for
83 operands of the instruction.
85 If the vector has only one element, that element is the template for the
86 instruction pattern. If the vector has multiple elements, then the
87 instruction pattern is a @code{parallel} expression containing the
91 @cindex pattern conditions
92 @cindex conditions, in patterns
93 A condition. This is a string which contains a C expression that is
94 the final test to decide whether an insn body matches this pattern.
96 @cindex named patterns and conditions
97 For a named pattern, the condition (if present) may not depend on
98 the data in the insn being matched, but only the target-machine-type
99 flags. The compiler needs to test these conditions during
100 initialization in order to learn exactly which named instructions are
101 available in a particular run.
104 For nameless patterns, the condition is applied only when matching an
105 individual insn, and only after the insn has matched the pattern's
106 recognition template. The insn's operands may be found in the vector
110 The @dfn{output template}: a string that says how to output matching
111 insns as assembler code. @samp{%} in this string specifies where
112 to substitute the value of an operand. @xref{Output Template}.
114 When simple substitution isn't general enough, you can specify a piece
115 of C code to compute the output. @xref{Output Statement}.
118 Optionally, a vector containing the values of attributes for insns matching
119 this pattern. @xref{Insn Attributes}.
123 @section Example of @code{define_insn}
124 @cindex @code{define_insn} example
126 Here is an actual example of an instruction pattern, for the 68000/68020.
131 (match_operand:SI 0 "general_operand" "rm"))]
134 @{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
136 return \"cmpl #0,%0\"; @}")
139 This is an instruction that sets the condition codes based on the value of
140 a general operand. It has no condition, so any insn whose RTL description
141 has the form shown may be handled according to this pattern. The name
142 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
143 pass that, when it is necessary to test such a value, an insn to do so
144 can be constructed using this pattern.
146 The output control string is a piece of C code which chooses which
147 output template to return based on the kind of operand and the specific
148 type of CPU for which code is being generated.
150 @samp{"rm"} is an operand constraint. Its meaning is explained below.
153 @section RTL Template
154 @cindex RTL insn template
155 @cindex generating insns
156 @cindex insns, generating
157 @cindex recognizing insns
158 @cindex insns, recognizing
160 The RTL template is used to define which insns match the particular pattern
161 and how to find their operands. For named patterns, the RTL template also
162 says how to construct an insn from specified operands.
164 Construction involves substituting specified operands into a copy of the
165 template. Matching involves determining the values that serve as the
166 operands in the insn being matched. Both of these activities are
167 controlled by special expression types that direct matching and
168 substitution of the operands.
171 @findex match_operand
172 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
173 This expression is a placeholder for operand number @var{n} of
174 the insn. When constructing an insn, operand number @var{n}
175 will be substituted at this point. When matching an insn, whatever
176 appears at this position in the insn will be taken as operand
177 number @var{n}; but it must satisfy @var{predicate} or this instruction
178 pattern will not match at all.
180 Operand numbers must be chosen consecutively counting from zero in
181 each instruction pattern. There may be only one @code{match_operand}
182 expression in the pattern for each operand number. Usually operands
183 are numbered in the order of appearance in @code{match_operand}
184 expressions. In the case of a @code{define_expand}, any operand numbers
185 used only in @code{match_dup} expressions have higher values than all
186 other operand numbers.
188 @var{predicate} is a string that is the name of a C function that accepts two
189 arguments, an expression and a machine mode. During matching, the
190 function will be called with the putative operand as the expression and
191 @var{m} as the mode argument (if @var{m} is not specified,
192 @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
193 any mode). If it returns zero, this instruction pattern fails to match.
194 @var{predicate} may be an empty string; then it means no test is to be done
195 on the operand, so anything which occurs in this position is valid.
197 Most of the time, @var{predicate} will reject modes other than @var{m}---but
198 not always. For example, the predicate @code{address_operand} uses
199 @var{m} as the mode of memory ref that the address should be valid for.
200 Many predicates accept @code{const_int} nodes even though their mode is
203 @var{constraint} controls reloading and the choice of the best register
204 class to use for a value, as explained later (@pxref{Constraints}).
206 People are often unclear on the difference between the constraint and the
207 predicate. The predicate helps decide whether a given insn matches the
208 pattern. The constraint plays no role in this decision; instead, it
209 controls various decisions in the case of an insn which does match.
211 @findex general_operand
212 On CISC machines, the most common @var{predicate} is
213 @code{"general_operand"}. This function checks that the putative
214 operand is either a constant, a register or a memory reference, and that
215 it is valid for mode @var{m}.
217 @findex register_operand
218 For an operand that must be a register, @var{predicate} should be
219 @code{"register_operand"}. Using @code{"general_operand"} would be
220 valid, since the reload pass would copy any non-register operands
221 through registers, but this would make GNU CC do extra work, it would
222 prevent invariant operands (such as constant) from being removed from
223 loops, and it would prevent the register allocator from doing the best
224 possible job. On RISC machines, it is usually most efficient to allow
225 @var{predicate} to accept only objects that the constraints allow.
227 @findex immediate_operand
228 For an operand that must be a constant, you must be sure to either use
229 @code{"immediate_operand"} for @var{predicate}, or make the instruction
230 pattern's extra condition require a constant, or both. You cannot
231 expect the constraints to do this work! If the constraints allow only
232 constants, but the predicate allows something else, the compiler will
233 crash when that case arises.
235 @findex match_scratch
236 @item (match_scratch:@var{m} @var{n} @var{constraint})
237 This expression is also a placeholder for operand number @var{n}
238 and indicates that operand must be a @code{scratch} or @code{reg}
241 When matching patterns, this is equivalent to
244 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
247 but, when generating RTL, it produces a (@code{scratch}:@var{m})
250 If the last few expressions in a @code{parallel} are @code{clobber}
251 expressions whose operands are either a hard register or
252 @code{match_scratch}, the combiner can add or delete them when
253 necessary. @xref{Side Effects}.
256 @item (match_dup @var{n})
257 This expression is also a placeholder for operand number @var{n}.
258 It is used when the operand needs to appear more than once in the
261 In construction, @code{match_dup} acts just like @code{match_operand}:
262 the operand is substituted into the insn being constructed. But in
263 matching, @code{match_dup} behaves differently. It assumes that operand
264 number @var{n} has already been determined by a @code{match_operand}
265 appearing earlier in the recognition template, and it matches only an
266 identical-looking expression.
268 @findex match_operator
269 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
270 This pattern is a kind of placeholder for a variable RTL expression
273 When constructing an insn, it stands for an RTL expression whose
274 expression code is taken from that of operand @var{n}, and whose
275 operands are constructed from the patterns @var{operands}.
277 When matching an expression, it matches an expression if the function
278 @var{predicate} returns nonzero on that expression @emph{and} the
279 patterns @var{operands} match the operands of the expression.
281 Suppose that the function @code{commutative_operator} is defined as
282 follows, to match any expression whose operator is one of the
283 commutative arithmetic operators of RTL and whose mode is @var{mode}:
287 commutative_operator (x, mode)
289 enum machine_mode mode;
291 enum rtx_code code = GET_CODE (x);
292 if (GET_MODE (x) != mode)
294 return (GET_RTX_CLASS (code) == 'c'
295 || code == EQ || code == NE);
299 Then the following pattern will match any RTL expression consisting
300 of a commutative operator applied to two general operands:
303 (match_operator:SI 3 "commutative_operator"
304 [(match_operand:SI 1 "general_operand" "g")
305 (match_operand:SI 2 "general_operand" "g")])
308 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
309 because the expressions to be matched all contain two operands.
311 When this pattern does match, the two operands of the commutative
312 operator are recorded as operands 1 and 2 of the insn. (This is done
313 by the two instances of @code{match_operand}.) Operand 3 of the insn
314 will be the entire commutative expression: use @code{GET_CODE
315 (operands[3])} to see which commutative operator was used.
317 The machine mode @var{m} of @code{match_operator} works like that of
318 @code{match_operand}: it is passed as the second argument to the
319 predicate function, and that function is solely responsible for
320 deciding whether the expression to be matched ``has'' that mode.
322 When constructing an insn, argument 3 of the gen-function will specify
323 the operation (i.e. the expression code) for the expression to be
324 made. It should be an RTL expression, whose expression code is copied
325 into a new expression whose operands are arguments 1 and 2 of the
326 gen-function. The subexpressions of argument 3 are not used;
327 only its expression code matters.
329 When @code{match_operator} is used in a pattern for matching an insn,
330 it usually best if the operand number of the @code{match_operator}
331 is higher than that of the actual operands of the insn. This improves
332 register allocation because the register allocator often looks at
333 operands 1 and 2 of insns to see if it can do register tying.
335 There is no way to specify constraints in @code{match_operator}. The
336 operand of the insn which corresponds to the @code{match_operator}
337 never has any constraints because it is never reloaded as a whole.
338 However, if parts of its @var{operands} are matched by
339 @code{match_operand} patterns, those parts may have constraints of
343 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
344 Like @code{match_dup}, except that it applies to operators instead of
345 operands. When constructing an insn, operand number @var{n} will be
346 substituted at this point. But in matching, @code{match_op_dup} behaves
347 differently. It assumes that operand number @var{n} has already been
348 determined by a @code{match_operator} appearing earlier in the
349 recognition template, and it matches only an identical-looking
352 @findex match_parallel
353 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
354 This pattern is a placeholder for an insn that consists of a
355 @code{parallel} expression with a variable number of elements. This
356 expression should only appear at the top level of an insn pattern.
358 When constructing an insn, operand number @var{n} will be substituted at
359 this point. When matching an insn, it matches if the body of the insn
360 is a @code{parallel} expression with at least as many elements as the
361 vector of @var{subpat} expressions in the @code{match_parallel}, if each
362 @var{subpat} matches the corresponding element of the @code{parallel},
363 @emph{and} the function @var{predicate} returns nonzero on the
364 @code{parallel} that is the body of the insn. It is the responsibility
365 of the predicate to validate elements of the @code{parallel} beyond
366 those listed in the @code{match_parallel}.@refill
368 A typical use of @code{match_parallel} is to match load and store
369 multiple expressions, which can contain a variable number of elements
370 in a @code{parallel}. For example,
371 @c the following is *still* going over. need to change the code.
372 @c also need to work on grouping of this example. --mew 1feb93
376 [(match_parallel 0 "load_multiple_operation"
377 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
378 (match_operand:SI 2 "memory_operand" "m"))
380 (clobber (reg:SI 179))])]
385 This example comes from @file{a29k.md}. The function
386 @code{load_multiple_operations} is defined in @file{a29k.c} and checks
387 that subsequent elements in the @code{parallel} are the same as the
388 @code{set} in the pattern, except that they are referencing subsequent
389 registers and memory locations.
391 An insn that matches this pattern might look like:
395 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
397 (clobber (reg:SI 179))
399 (mem:SI (plus:SI (reg:SI 100)
402 (mem:SI (plus:SI (reg:SI 100)
406 @findex match_par_dup
407 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
408 Like @code{match_op_dup}, but for @code{match_parallel} instead of
409 @code{match_operator}.
412 @item (match_insn @var{predicate})
413 Match a complete insn. Unlike the other @code{match_*} recognizers,
414 @code{match_insn} does not take an operand number.
416 The machine mode @var{m} of @code{match_insn} works like that of
417 @code{match_operand}: it is passed as the second argument to the
418 predicate function, and that function is solely responsible for
419 deciding whether the expression to be matched ``has'' that mode.
422 @item (match_insn2 @var{n} @var{predicate})
423 Match a complete insn.
425 The machine mode @var{m} of @code{match_insn2} works like that of
426 @code{match_operand}: it is passed as the second argument to the
427 predicate function, and that function is solely responsible for
428 deciding whether the expression to be matched ``has'' that mode.
432 @node Output Template
433 @section Output Templates and Operand Substitution
434 @cindex output templates
435 @cindex operand substitution
437 @cindex @samp{%} in template
439 The @dfn{output template} is a string which specifies how to output the
440 assembler code for an instruction pattern. Most of the template is a
441 fixed string which is output literally. The character @samp{%} is used
442 to specify where to substitute an operand; it can also be used to
443 identify places where different variants of the assembler require
446 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
447 operand @var{n} at that point in the string.
449 @samp{%} followed by a letter and a digit says to output an operand in an
450 alternate fashion. Four letters have standard, built-in meanings described
451 below. The machine description macro @code{PRINT_OPERAND} can define
452 additional letters with nonstandard meanings.
454 @samp{%c@var{digit}} can be used to substitute an operand that is a
455 constant value without the syntax that normally indicates an immediate
458 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
459 the constant is negated before printing.
461 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
462 memory reference, with the actual operand treated as the address. This may
463 be useful when outputting a ``load address'' instruction, because often the
464 assembler syntax for such an instruction requires you to write the operand
465 as if it were a memory reference.
467 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
470 @samp{%=} outputs a number which is unique to each instruction in the
471 entire compilation. This is useful for making local labels to be
472 referred to more than once in a single template that generates multiple
473 assembler instructions.
475 @samp{%} followed by a punctuation character specifies a substitution that
476 does not use an operand. Only one case is standard: @samp{%%} outputs a
477 @samp{%} into the assembler code. Other nonstandard cases can be
478 defined in the @code{PRINT_OPERAND} macro. You must also define
479 which punctuation characters are valid with the
480 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
484 The template may generate multiple assembler instructions. Write the text
485 for the instructions, with @samp{\;} between them.
487 @cindex matching operands
488 When the RTL contains two operands which are required by constraint to match
489 each other, the output template must refer only to the lower-numbered operand.
490 Matching operands are not always identical, and the rest of the compiler
491 arranges to put the proper RTL expression for printing into the lower-numbered
494 One use of nonstandard letters or punctuation following @samp{%} is to
495 distinguish between different assembler languages for the same machine; for
496 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
497 requires periods in most opcode names, while MIT syntax does not. For
498 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
499 syntax. The same file of patterns is used for both kinds of output syntax,
500 but the character sequence @samp{%.} is used in each place where Motorola
501 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
502 defines the sequence to output a period; the macro for MIT syntax defines
505 @cindex @code{#} in template
506 As a special case, a template consisting of the single character @code{#}
507 instructs the compiler to first split the insn, and then output the
508 resulting instructions separately. This helps eliminate redundancy in the
509 output templates. If you have a @code{define_insn} that needs to emit
510 multiple assembler instructions, and there is an matching @code{define_split}
511 already defined, then you can simply use @code{#} as the output template
512 instead of writing an output template that emits the multiple assembler
515 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
516 of the form @samp{@{option0|option1|option2@}} in the templates. These
517 describe multiple variants of assembler language syntax.
518 @xref{Instruction Output}.
520 @node Output Statement
521 @section C Statements for Assembler Output
522 @cindex output statements
523 @cindex C statements for assembler output
524 @cindex generating assembler output
526 Often a single fixed template string cannot produce correct and efficient
527 assembler code for all the cases that are recognized by a single
528 instruction pattern. For example, the opcodes may depend on the kinds of
529 operands; or some unfortunate combinations of operands may require extra
530 machine instructions.
532 If the output control string starts with a @samp{@@}, then it is actually
533 a series of templates, each on a separate line. (Blank lines and
534 leading spaces and tabs are ignored.) The templates correspond to the
535 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
536 if a target machine has a two-address add instruction @samp{addr} to add
537 into a register and another @samp{addm} to add a register to memory, you
538 might write this pattern:
541 (define_insn "addsi3"
542 [(set (match_operand:SI 0 "general_operand" "=r,m")
543 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
544 (match_operand:SI 2 "general_operand" "g,r")))]
551 @cindex @code{*} in template
552 @cindex asterisk in template
553 If the output control string starts with a @samp{*}, then it is not an
554 output template but rather a piece of C program that should compute a
555 template. It should execute a @code{return} statement to return the
556 template-string you want. Most such templates use C string literals, which
557 require doublequote characters to delimit them. To include these
558 doublequote characters in the string, prefix each one with @samp{\}.
560 The operands may be found in the array @code{operands}, whose C data type
563 It is very common to select different ways of generating assembler code
564 based on whether an immediate operand is within a certain range. Be
565 careful when doing this, because the result of @code{INTVAL} is an
566 integer on the host machine. If the host machine has more bits in an
567 @code{int} than the target machine has in the mode in which the constant
568 will be used, then some of the bits you get from @code{INTVAL} will be
569 superfluous. For proper results, you must carefully disregard the
570 values of those bits.
572 @findex output_asm_insn
573 It is possible to output an assembler instruction and then go on to output
574 or compute more of them, using the subroutine @code{output_asm_insn}. This
575 receives two arguments: a template-string and a vector of operands. The
576 vector may be @code{operands}, or it may be another array of @code{rtx}
577 that you declare locally and initialize yourself.
579 @findex which_alternative
580 When an insn pattern has multiple alternatives in its constraints, often
581 the appearance of the assembler code is determined mostly by which alternative
582 was matched. When this is so, the C code can test the variable
583 @code{which_alternative}, which is the ordinal number of the alternative
584 that was actually satisfied (0 for the first, 1 for the second alternative,
587 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
588 for registers and @samp{clrmem} for memory locations. Here is how
589 a pattern could use @code{which_alternative} to choose between them:
593 [(set (match_operand:SI 0 "general_operand" "=r,m")
597 return (which_alternative == 0
598 ? \"clrreg %0\" : \"clrmem %0\");
602 The example above, where the assembler code to generate was
603 @emph{solely} determined by the alternative, could also have been specified
604 as follows, having the output control string start with a @samp{@@}:
609 [(set (match_operand:SI 0 "general_operand" "=r,m")
619 @c Most of this node appears by itself (in a different place) even
620 @c when the INTERNALS flag is clear. Passages that require the full
621 @c manual's context are conditionalized to appear only in the full manual.
624 @section Operand Constraints
625 @cindex operand constraints
628 Each @code{match_operand} in an instruction pattern can specify a
629 constraint for the type of operands allowed.
633 @section Constraints for @code{asm} Operands
634 @cindex operand constraints, @code{asm}
635 @cindex constraints, @code{asm}
636 @cindex @code{asm} constraints
638 Here are specific details on what constraint letters you can use with
641 Constraints can say whether
642 an operand may be in a register, and which kinds of register; whether the
643 operand can be a memory reference, and which kinds of address; whether the
644 operand may be an immediate constant, and which possible values it may
645 have. Constraints can also require two operands to match.
649 * Simple Constraints:: Basic use of constraints.
650 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
651 * Class Preferences:: Constraints guide which hard register to put things in.
652 * Modifiers:: More precise control over effects of constraints.
653 * Machine Constraints:: Existing constraints for some particular machines.
659 * Simple Constraints:: Basic use of constraints.
660 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
661 * Modifiers:: More precise control over effects of constraints.
662 * Machine Constraints:: Special constraints for some particular machines.
666 @node Simple Constraints
667 @subsection Simple Constraints
668 @cindex simple constraints
670 The simplest kind of constraint is a string full of letters, each of
671 which describes one kind of operand that is permitted. Here are
672 the letters that are allowed:
676 Whitespace characters are ignored and can be inserted at any position
677 except the first. This enables each alternative for different operands to
678 be visually aligned in the machine description even if they have different
679 number of constraints and modifiers.
681 @cindex @samp{m} in constraint
682 @cindex memory references in constraints
684 A memory operand is allowed, with any kind of address that the machine
687 @cindex offsettable address
688 @cindex @samp{o} in constraint
690 A memory operand is allowed, but only if the address is
691 @dfn{offsettable}. This means that adding a small integer (actually,
692 the width in bytes of the operand, as determined by its machine mode)
693 may be added to the address and the result is also a valid memory
696 @cindex autoincrement/decrement addressing
697 For example, an address which is constant is offsettable; so is an
698 address that is the sum of a register and a constant (as long as a
699 slightly larger constant is also within the range of address-offsets
700 supported by the machine); but an autoincrement or autodecrement
701 address is not offsettable. More complicated indirect/indexed
702 addresses may or may not be offsettable depending on the other
703 addressing modes that the machine supports.
705 Note that in an output operand which can be matched by another
706 operand, the constraint letter @samp{o} is valid only when accompanied
707 by both @samp{<} (if the target machine has predecrement addressing)
708 and @samp{>} (if the target machine has preincrement addressing).
710 @cindex @samp{V} in constraint
712 A memory operand that is not offsettable. In other words, anything that
713 would fit the @samp{m} constraint but not the @samp{o} constraint.
715 @cindex @samp{<} in constraint
717 A memory operand with autodecrement addressing (either predecrement or
718 postdecrement) is allowed.
720 @cindex @samp{>} in constraint
722 A memory operand with autoincrement addressing (either preincrement or
723 postincrement) is allowed.
725 @cindex @samp{r} in constraint
726 @cindex registers in constraints
728 A register operand is allowed provided that it is in a general
731 @cindex constants in constraints
732 @cindex @samp{i} in constraint
734 An immediate integer operand (one with constant value) is allowed.
735 This includes symbolic constants whose values will be known only at
738 @cindex @samp{n} in constraint
740 An immediate integer operand with a known numeric value is allowed.
741 Many systems cannot support assembly-time constants for operands less
742 than a word wide. Constraints for these operands should use @samp{n}
743 rather than @samp{i}.
745 @cindex @samp{I} in constraint
746 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
747 Other letters in the range @samp{I} through @samp{P} may be defined in
748 a machine-dependent fashion to permit immediate integer operands with
749 explicit integer values in specified ranges. For example, on the
750 68000, @samp{I} is defined to stand for the range of values 1 to 8.
751 This is the range permitted as a shift count in the shift
754 @cindex @samp{E} in constraint
756 An immediate floating operand (expression code @code{const_double}) is
757 allowed, but only if the target floating point format is the same as
758 that of the host machine (on which the compiler is running).
760 @cindex @samp{F} in constraint
762 An immediate floating operand (expression code @code{const_double}) is
765 @cindex @samp{G} in constraint
766 @cindex @samp{H} in constraint
767 @item @samp{G}, @samp{H}
768 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
769 permit immediate floating operands in particular ranges of values.
771 @cindex @samp{s} in constraint
773 An immediate integer operand whose value is not an explicit integer is
776 This might appear strange; if an insn allows a constant operand with a
777 value not known at compile time, it certainly must allow any known
778 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
779 better code to be generated.
781 For example, on the 68000 in a fullword instruction it is possible to
782 use an immediate operand; but if the immediate value is between -128
783 and 127, better code results from loading the value into a register and
784 using the register. This is because the load into the register can be
785 done with a @samp{moveq} instruction. We arrange for this to happen
786 by defining the letter @samp{K} to mean ``any integer outside the
787 range -128 to 127'', and then specifying @samp{Ks} in the operand
790 @cindex @samp{g} in constraint
792 Any register, memory or immediate integer operand is allowed, except for
793 registers that are not general registers.
795 @cindex @samp{X} in constraint
798 Any operand whatsoever is allowed, even if it does not satisfy
799 @code{general_operand}. This is normally used in the constraint of
800 a @code{match_scratch} when certain alternatives will not actually
801 require a scratch register.
804 Any operand whatsoever is allowed.
807 @cindex @samp{0} in constraint
808 @cindex digits in constraint
809 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
810 An operand that matches the specified operand number is allowed. If a
811 digit is used together with letters within the same alternative, the
812 digit should come last.
814 @cindex matching constraint
815 @cindex constraint, matching
816 This is called a @dfn{matching constraint} and what it really means is
817 that the assembler has only a single operand that fills two roles
819 considered separate in the RTL insn. For example, an add insn has two
820 input operands and one output operand in the RTL, but on most CISC
823 which @code{asm} distinguishes. For example, an add instruction uses
824 two input operands and an output operand, but on most CISC
826 machines an add instruction really has only two operands, one of them an
827 input-output operand:
833 Matching constraints are used in these circumstances.
834 More precisely, the two operands that match must include one input-only
835 operand and one output-only operand. Moreover, the digit must be a
836 smaller number than the number of the operand that uses it in the
840 For operands to match in a particular case usually means that they
841 are identical-looking RTL expressions. But in a few special cases
842 specific kinds of dissimilarity are allowed. For example, @code{*x}
843 as an input operand will match @code{*x++} as an output operand.
844 For proper results in such cases, the output template should always
845 use the output-operand's number when printing the operand.
848 @cindex load address instruction
849 @cindex push address instruction
850 @cindex address constraints
851 @cindex @samp{p} in constraint
853 An operand that is a valid memory address is allowed. This is
854 for ``load address'' and ``push address'' instructions.
856 @findex address_operand
857 @samp{p} in the constraint must be accompanied by @code{address_operand}
858 as the predicate in the @code{match_operand}. This predicate interprets
859 the mode specified in the @code{match_operand} as the mode of the memory
860 reference for which the address would be valid.
862 @cindex other register constraints
863 @cindex extensible constraints
864 @item @var{other letters}
865 Other letters can be defined in machine-dependent fashion to stand for
866 particular classes of registers or other arbitrary operand types.
867 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
868 for data, address and floating point registers.
871 The machine description macro @code{REG_CLASS_FROM_LETTER} has first
872 cut at the otherwise unused letters. If it evaluates to @code{NO_REGS},
873 then @code{EXTRA_CONSTRAINT} is evaluated.
875 A typical use for @code{EXTRA_CONSTRANT} would be to distinguish certain
876 types of memory references that affect other insn operands.
881 In order to have valid assembler code, each operand must satisfy
882 its constraint. But a failure to do so does not prevent the pattern
883 from applying to an insn. Instead, it directs the compiler to modify
884 the code so that the constraint will be satisfied. Usually this is
885 done by copying an operand into a register.
887 Contrast, therefore, the two instruction patterns that follow:
891 [(set (match_operand:SI 0 "general_operand" "=r")
892 (plus:SI (match_dup 0)
893 (match_operand:SI 1 "general_operand" "r")))]
899 which has two operands, one of which must appear in two places, and
903 [(set (match_operand:SI 0 "general_operand" "=r")
904 (plus:SI (match_operand:SI 1 "general_operand" "0")
905 (match_operand:SI 2 "general_operand" "r")))]
911 which has three operands, two of which are required by a constraint to be
912 identical. If we are considering an insn of the form
915 (insn @var{n} @var{prev} @var{next}
917 (plus:SI (reg:SI 6) (reg:SI 109)))
922 the first pattern would not apply at all, because this insn does not
923 contain two identical subexpressions in the right place. The pattern would
924 say, ``That does not look like an add instruction; try other patterns.''
925 The second pattern would say, ``Yes, that's an add instruction, but there
926 is something wrong with it.'' It would direct the reload pass of the
927 compiler to generate additional insns to make the constraint true. The
928 results might look like this:
931 (insn @var{n2} @var{prev} @var{n}
932 (set (reg:SI 3) (reg:SI 6))
935 (insn @var{n} @var{n2} @var{next}
937 (plus:SI (reg:SI 3) (reg:SI 109)))
941 It is up to you to make sure that each operand, in each pattern, has
942 constraints that can handle any RTL expression that could be present for
943 that operand. (When multiple alternatives are in use, each pattern must,
944 for each possible combination of operand expressions, have at least one
945 alternative which can handle that combination of operands.) The
946 constraints don't need to @emph{allow} any possible operand---when this is
947 the case, they do not constrain---but they must at least point the way to
948 reloading any possible operand so that it will fit.
952 If the constraint accepts whatever operands the predicate permits,
953 there is no problem: reloading is never necessary for this operand.
955 For example, an operand whose constraints permit everything except
956 registers is safe provided its predicate rejects registers.
958 An operand whose predicate accepts only constant values is safe
959 provided its constraints include the letter @samp{i}. If any possible
960 constant value is accepted, then nothing less than @samp{i} will do;
961 if the predicate is more selective, then the constraints may also be
965 Any operand expression can be reloaded by copying it into a register.
966 So if an operand's constraints allow some kind of register, it is
967 certain to be safe. It need not permit all classes of registers; the
968 compiler knows how to copy a register into another register of the
969 proper class in order to make an instruction valid.
971 @cindex nonoffsettable memory reference
972 @cindex memory reference, nonoffsettable
974 A nonoffsettable memory reference can be reloaded by copying the
975 address into a register. So if the constraint uses the letter
976 @samp{o}, all memory references are taken care of.
979 A constant operand can be reloaded by allocating space in memory to
980 hold it as preinitialized data. Then the memory reference can be used
981 in place of the constant. So if the constraint uses the letters
982 @samp{o} or @samp{m}, constant operands are not a problem.
985 If the constraint permits a constant and a pseudo register used in an insn
986 was not allocated to a hard register and is equivalent to a constant,
987 the register will be replaced with the constant. If the predicate does
988 not permit a constant and the insn is re-recognized for some reason, the
989 compiler will crash. Thus the predicate must always recognize any
990 objects allowed by the constraint.
993 If the operand's predicate can recognize registers, but the constraint does
994 not permit them, it can make the compiler crash. When this operand happens
995 to be a register, the reload pass will be stymied, because it does not know
996 how to copy a register temporarily into memory.
998 If the predicate accepts a unary operator, the constraint applies to the
999 operand. For example, the MIPS processor at ISA level 3 supports an
1000 instruction which adds two registers in @code{SImode} to produce a
1001 @code{DImode} result, but only if the registers are correctly sign
1002 extended. This predicate for the input operands accepts a
1003 @code{sign_extend} of an @code{SImode} register. Write the constraint
1004 to indicate the type of register that is required for the operand of the
1008 @node Multi-Alternative
1009 @subsection Multiple Alternative Constraints
1010 @cindex multiple alternative constraints
1012 Sometimes a single instruction has multiple alternative sets of possible
1013 operands. For example, on the 68000, a logical-or instruction can combine
1014 register or an immediate value into memory, or it can combine any kind of
1015 operand into a register; but it cannot combine one memory location into
1018 These constraints are represented as multiple alternatives. An alternative
1019 can be described by a series of letters for each operand. The overall
1020 constraint for an operand is made from the letters for this operand
1021 from the first alternative, a comma, the letters for this operand from
1022 the second alternative, a comma, and so on until the last alternative.
1024 Here is how it is done for fullword logical-or on the 68000:
1027 (define_insn "iorsi3"
1028 [(set (match_operand:SI 0 "general_operand" "=m,d")
1029 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1030 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1034 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1035 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1036 2. The second alternative has @samp{d} (data register) for operand 0,
1037 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1038 @samp{%} in the constraints apply to all the alternatives; their
1039 meaning is explained in the next section (@pxref{Class Preferences}).
1042 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1043 If all the operands fit any one alternative, the instruction is valid.
1044 Otherwise, for each alternative, the compiler counts how many instructions
1045 must be added to copy the operands so that that alternative applies.
1046 The alternative requiring the least copying is chosen. If two alternatives
1047 need the same amount of copying, the one that comes first is chosen.
1048 These choices can be altered with the @samp{?} and @samp{!} characters:
1051 @cindex @samp{?} in constraint
1052 @cindex question mark
1054 Disparage slightly the alternative that the @samp{?} appears in,
1055 as a choice when no alternative applies exactly. The compiler regards
1056 this alternative as one unit more costly for each @samp{?} that appears
1059 @cindex @samp{!} in constraint
1060 @cindex exclamation point
1062 Disparage severely the alternative that the @samp{!} appears in.
1063 This alternative can still be used if it fits without reloading,
1064 but if reloading is needed, some other alternative will be used.
1068 When an insn pattern has multiple alternatives in its constraints, often
1069 the appearance of the assembler code is determined mostly by which
1070 alternative was matched. When this is so, the C code for writing the
1071 assembler code can use the variable @code{which_alternative}, which is
1072 the ordinal number of the alternative that was actually satisfied (0 for
1073 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1077 @node Class Preferences
1078 @subsection Register Class Preferences
1079 @cindex class preference constraints
1080 @cindex register class preference constraints
1082 @cindex voting between constraint alternatives
1083 The operand constraints have another function: they enable the compiler
1084 to decide which kind of hardware register a pseudo register is best
1085 allocated to. The compiler examines the constraints that apply to the
1086 insns that use the pseudo register, looking for the machine-dependent
1087 letters such as @samp{d} and @samp{a} that specify classes of registers.
1088 The pseudo register is put in whichever class gets the most ``votes''.
1089 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1090 favor of a general register. The machine description says which registers
1091 are considered general.
1093 Of course, on some machines all registers are equivalent, and no register
1094 classes are defined. Then none of this complexity is relevant.
1098 @subsection Constraint Modifier Characters
1099 @cindex modifiers in constraints
1100 @cindex constraint modifier characters
1102 @c prevent bad page break with this line
1103 Here are constraint modifier characters.
1106 @cindex @samp{=} in constraint
1108 Means that this operand is write-only for this instruction: the previous
1109 value is discarded and replaced by output data.
1111 @cindex @samp{+} in constraint
1113 Means that this operand is both read and written by the instruction.
1115 When the compiler fixes up the operands to satisfy the constraints,
1116 it needs to know which operands are inputs to the instruction and
1117 which are outputs from it. @samp{=} identifies an output; @samp{+}
1118 identifies an operand that is both input and output; all other operands
1119 are assumed to be input only.
1121 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1122 first character of the constraint string.
1124 @cindex @samp{&} in constraint
1125 @cindex earlyclobber operand
1127 Means (in a particular alternative) that this operand is an
1128 @dfn{earlyclobber} operand, which is modified before the instruction is
1129 finished using the input operands. Therefore, this operand may not lie
1130 in a register that is used as an input operand or as part of any memory
1133 @samp{&} applies only to the alternative in which it is written. In
1134 constraints with multiple alternatives, sometimes one alternative
1135 requires @samp{&} while others do not. See, for example, the
1136 @samp{movdf} insn of the 68000.
1138 An input operand can be tied to an earlyclobber operand if its only
1139 use as an input occurs before the early result is written. Adding
1140 alternatives of this form often allows GCC to produce better code
1141 when only some of the inputs can be affected by the earlyclobber.
1142 See, for example, the @samp{mulsi3} insn of the ARM.
1144 @samp{&} does not obviate the need to write @samp{=}.
1146 @cindex @samp{%} in constraint
1148 Declares the instruction to be commutative for this operand and the
1149 following operand. This means that the compiler may interchange the
1150 two operands if that is the cheapest way to make all operands fit the
1153 This is often used in patterns for addition instructions
1154 that really have only two operands: the result must go in one of the
1155 arguments. Here for example, is how the 68000 halfword-add
1156 instruction is defined:
1159 (define_insn "addhi3"
1160 [(set (match_operand:HI 0 "general_operand" "=m,r")
1161 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1162 (match_operand:HI 2 "general_operand" "di,g")))]
1167 @cindex @samp{#} in constraint
1169 Says that all following characters, up to the next comma, are to be
1170 ignored as a constraint. They are significant only for choosing
1171 register preferences.
1174 @cindex @samp{*} in constraint
1176 Says that the following character should be ignored when choosing
1177 register preferences. @samp{*} has no effect on the meaning of the
1178 constraint as a constraint, and no effect on reloading.
1180 Here is an example: the 68000 has an instruction to sign-extend a
1181 halfword in a data register, and can also sign-extend a value by
1182 copying it into an address register. While either kind of register is
1183 acceptable, the constraints on an address-register destination are
1184 less strict, so it is best if register allocation makes an address
1185 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1186 constraint letter (for data register) is ignored when computing
1187 register preferences.
1190 (define_insn "extendhisi2"
1191 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1193 (match_operand:HI 1 "general_operand" "0,g")))]
1199 @node Machine Constraints
1200 @subsection Constraints for Particular Machines
1201 @cindex machine specific constraints
1202 @cindex constraints, machine specific
1204 Whenever possible, you should use the general-purpose constraint letters
1205 in @code{asm} arguments, since they will convey meaning more readily to
1206 people reading your code. Failing that, use the constraint letters
1207 that usually have very similar meanings across architectures. The most
1208 commonly used constraints are @samp{m} and @samp{r} (for memory and
1209 general-purpose registers respectively; @pxref{Simple Constraints}), and
1210 @samp{I}, usually the letter indicating the most common
1211 immediate-constant format.
1213 For each machine architecture, the @file{config/@var{machine}.h} file
1214 defines additional constraints. These constraints are used by the
1215 compiler itself for instruction generation, as well as for @code{asm}
1216 statements; therefore, some of the constraints are not particularly
1217 interesting for @code{asm}. The constraints are defined through these
1221 @item REG_CLASS_FROM_LETTER
1222 Register class constraints (usually lower case).
1224 @item CONST_OK_FOR_LETTER_P
1225 Immediate constant constraints, for non-floating point constants of
1226 word size or smaller precision (usually upper case).
1228 @item CONST_DOUBLE_OK_FOR_LETTER_P
1229 Immediate constant constraints, for all floating point constants and for
1230 constants of greater than word size precision (usually upper case).
1232 @item EXTRA_CONSTRAINT
1233 Special cases of registers or memory. This macro is not required, and
1234 is only defined for some machines.
1237 Inspecting these macro definitions in the compiler source for your
1238 machine is the best way to be certain you have the right constraints.
1239 However, here is a summary of the machine-dependent constraints
1240 available on some particular machines.
1243 @item ARM family---@file{arm.h}
1246 Floating-point register
1249 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1253 Floating-point constant that would satisfy the constraint @samp{F} if it
1257 Integer that is valid as an immediate operand in a data processing
1258 instruction. That is, an integer in the range 0 to 255 rotated by a
1262 Integer in the range -4095 to 4095
1265 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1268 Integer that satisfies constraint @samp{I} when negated (twos complement)
1271 Integer in the range 0 to 32
1274 A memory reference where the exact address is in a single register
1275 (`@samp{m}' is preferable for @code{asm} statements)
1278 An item in the constant pool
1281 A symbol in the text segment of the current file
1284 @item AMD 29000 family---@file{a29k.h}
1290 Byte Pointer (@samp{BP}) register
1296 Special purpose register
1299 First accumulator register
1302 Other accumulator register
1305 Floating point register
1308 Constant greater than 0, less than 0x100
1311 Constant greater than 0, less than 0x10000
1314 Constant whose high 24 bits are on (1)
1317 16 bit constant whose high 8 bits are on (1)
1320 32 bit constant whose high 16 bits are on (1)
1323 32 bit negative constant that fits in 8 bits
1326 The constant 0x80000000 or, on the 29050, any 32 bit constant
1327 whose low 16 bits are 0.
1330 16 bit negative constant that fits in 8 bits
1334 A floating point constant (in @code{asm} statements, use the machine
1335 independent @samp{E} or @samp{F} instead)
1338 @item AVR family---@file{avr.h}
1341 Registers from r0 to r15
1344 Registers from r16 to r23
1347 Registers from r16 to r31
1350 Register from r24 to r31. This registers can be used in @samp{addw} command
1353 Pointer register (r26 - r31)
1356 Base pointer register (r28 - r31)
1359 Temporary register r0
1362 Register pair X (r27:r26)
1365 Register pair Y (r29:r28)
1368 Register pair Z (r31:r30)
1371 Constant greater than -1, less than 64
1374 Constant greater than -64, less than 1
1383 Constant that fits in 8 bits
1395 A floating point constant 0.0
1398 @item IBM RS6000---@file{rs6000.h}
1401 Address base register
1404 Floating point register
1407 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1416 @samp{LINK} register
1419 @samp{CR} register (condition register) number 0
1422 @samp{CR} register (condition register)
1425 @samp{FPMEM} stack memory for FPR-GPR transfers
1428 Signed 16 bit constant
1431 Unsigned 16 bit constant shifted left 16 bits (use @samp{L} instead for
1432 @code{SImode} constants)
1435 Unsigned 16 bit constant
1438 Signed 16 bit constant shifted left 16 bits
1441 Constant larger than 31
1450 Constant whose negation is a signed 16 bit constant
1453 Floating point constant that can be loaded into a register with one
1454 instruction per word
1457 Memory operand that is an offset from a register (@samp{m} is preferable
1458 for @code{asm} statements)
1464 Constant suitable as a 64-bit mask operand
1467 Constant suitable as a 32-bit mask operand
1470 System V Release 4 small data area reference
1473 @item Intel 386---@file{i386.h}
1476 @samp{a}, @code{b}, @code{c}, or @code{d} register
1479 @samp{a}, or @code{d} register (for 64-bit ints)
1482 Floating point register
1485 First (top of stack) floating point register
1488 Second floating point register
1509 Constant in range 0 to 31 (for 32 bit shifts)
1512 Constant in range 0 to 63 (for 64 bit shifts)
1521 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1524 Constant in range 0 to 255 (for @code{out} instruction)
1527 Standard 80387 floating point constant
1530 @item Intel 960---@file{i960.h}
1533 Floating point register (@code{fp0} to @code{fp3})
1536 Local register (@code{r0} to @code{r15})
1539 Global register (@code{g0} to @code{g15})
1542 Any local or global register
1545 Integers from 0 to 31
1551 Integers from -31 to 0
1560 @item MIPS---@file{mips.h}
1563 General-purpose integer register
1566 Floating-point register (if available)
1575 @samp{Hi} or @samp{Lo} register
1578 General-purpose integer register
1581 Floating-point status register
1584 Signed 16 bit constant (for arithmetic instructions)
1590 Zero-extended 16-bit constant (for logic instructions)
1593 Constant with low 16 bits zero (can be loaded with @code{lui})
1596 32 bit constant which requires two instructions to load (a constant
1597 which is not @samp{I}, @samp{K}, or @samp{L})
1600 Negative 16 bit constant
1606 Positive 16 bit constant
1612 Memory reference that can be loaded with more than one instruction
1613 (@samp{m} is preferable for @code{asm} statements)
1616 Memory reference that can be loaded with one instruction
1617 (@samp{m} is preferable for @code{asm} statements)
1620 Memory reference in external OSF/rose PIC format
1621 (@samp{m} is preferable for @code{asm} statements)
1624 @item Motorola 680x0---@file{m68k.h}
1633 68881 floating-point register, if available
1636 Sun FPA (floating-point) register, if available
1639 First 16 Sun FPA registers, if available
1642 Integer in the range 1 to 8
1645 16 bit signed number
1648 Signed number whose magnitude is greater than 0x80
1651 Integer in the range -8 to -1
1654 Signed number whose magnitude is greater than 0x100
1657 Floating point constant that is not a 68881 constant
1660 Floating point constant that can be used by Sun FPA
1664 @item SPARC---@file{sparc.h}
1667 Floating-point register that can hold 32 or 64 bit values.
1670 Floating-point register that can hold 64 or 128 bit values.
1673 Signed 13 bit constant
1679 32 bit constant with the low 12 bits clear (a constant that can be
1680 loaded with the @code{sethi} instruction)
1686 Signed 13 bit constant, sign-extended to 32 or 64 bits
1689 Floating-point constant whose integral representation can
1690 be moved into an integer register using a single sethi
1694 Floating-point constant whose integral representation can
1695 be moved into an integer register using a single mov
1699 Floating-point constant whose integral representation can
1700 be moved into an integer register using a high/lo_sum
1701 instruction sequence
1704 Memory address aligned to an 8-byte boundary
1711 @item TMS320C3x/C4x---@file{c4x.h}
1714 Auxiliary (address) register (ar0-ar7)
1717 Stack pointer register (sp)
1720 Standard (32 bit) precision integer register
1723 Extended (40 bit) precision register (r0-r11)
1726 Block count register (bk)
1729 Extended (40 bit) precision low register (r0-r7)
1732 Extended (40 bit) precision register (r0-r1)
1735 Extended (40 bit) precision register (r2-r3)
1738 Repeat count register (rc)
1741 Index register (ir0-ir1)
1744 Status (condition code) register (st)
1747 Data page register (dp)
1753 Immediate 16 bit floating-point constant
1756 Signed 16 bit constant
1759 Signed 8 bit constant
1762 Signed 5 bit constant
1765 Unsigned 16 bit constant
1768 Unsigned 8 bit constant
1771 Ones complement of unsigned 16 bit constant
1774 High 16 bit constant (32 bit constant with 16 LSBs zero)
1777 Indirect memory reference with signed 8 bit or index register displacement
1780 Indirect memory reference with unsigned 5 bit displacement
1783 Indirect memory reference with 1 bit or index register displacement
1786 Direct memory reference
1795 @node Standard Names
1796 @section Standard Pattern Names For Generation
1797 @cindex standard pattern names
1798 @cindex pattern names
1799 @cindex names, pattern
1801 Here is a table of the instruction names that are meaningful in the RTL
1802 generation pass of the compiler. Giving one of these names to an
1803 instruction pattern tells the RTL generation pass that it can use the
1804 pattern to accomplish a certain task.
1807 @cindex @code{mov@var{m}} instruction pattern
1808 @item @samp{mov@var{m}}
1809 Here @var{m} stands for a two-letter machine mode name, in lower case.
1810 This instruction pattern moves data with that machine mode from operand
1811 1 to operand 0. For example, @samp{movsi} moves full-word data.
1813 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
1814 own mode is wider than @var{m}, the effect of this instruction is
1815 to store the specified value in the part of the register that corresponds
1816 to mode @var{m}. The effect on the rest of the register is undefined.
1818 This class of patterns is special in several ways. First of all, each
1819 of these names up to and including full word size @emph{must} be defined,
1820 because there is no other way to copy a datum from one place to another.
1821 If there are patterns accepting operands in larger modes,
1822 @samp{mov@var{m}} must be defined for integer modes of those sizes.
1824 Second, these patterns are not used solely in the RTL generation pass.
1825 Even the reload pass can generate move insns to copy values from stack
1826 slots into temporary registers. When it does so, one of the operands is
1827 a hard register and the other is an operand that can need to be reloaded
1831 Therefore, when given such a pair of operands, the pattern must generate
1832 RTL which needs no reloading and needs no temporary registers---no
1833 registers other than the operands. For example, if you support the
1834 pattern with a @code{define_expand}, then in such a case the
1835 @code{define_expand} mustn't call @code{force_reg} or any other such
1836 function which might generate new pseudo registers.
1838 This requirement exists even for subword modes on a RISC machine where
1839 fetching those modes from memory normally requires several insns and
1840 some temporary registers. Look in @file{spur.md} to see how the
1841 requirement can be satisfied.
1843 @findex change_address
1844 During reload a memory reference with an invalid address may be passed
1845 as an operand. Such an address will be replaced with a valid address
1846 later in the reload pass. In this case, nothing may be done with the
1847 address except to use it as it stands. If it is copied, it will not be
1848 replaced with a valid address. No attempt should be made to make such
1849 an address into a valid address and no routine (such as
1850 @code{change_address}) that will do so may be called. Note that
1851 @code{general_operand} will fail when applied to such an address.
1853 @findex reload_in_progress
1854 The global variable @code{reload_in_progress} (which must be explicitly
1855 declared if required) can be used to determine whether such special
1856 handling is required.
1858 The variety of operands that have reloads depends on the rest of the
1859 machine description, but typically on a RISC machine these can only be
1860 pseudo registers that did not get hard registers, while on other
1861 machines explicit memory references will get optional reloads.
1863 If a scratch register is required to move an object to or from memory,
1864 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
1866 If there are cases needing
1867 scratch registers after reload, you must define
1868 @code{SECONDARY_INPUT_RELOAD_CLASS} and perhaps also
1869 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
1870 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
1871 them. @xref{Register Classes}.
1873 @findex no_new_pseudos
1874 The global variable @code{no_new_pseudos} can be used to determine if it
1875 is unsafe to create new pseudo registers. If this variable is nonzero, then
1876 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
1878 The constraints on a @samp{mov@var{m}} must permit moving any hard
1879 register to any other hard register provided that
1880 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
1881 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
1883 It is obligatory to support floating point @samp{mov@var{m}}
1884 instructions into and out of any registers that can hold fixed point
1885 values, because unions and structures (which have modes @code{SImode} or
1886 @code{DImode}) can be in those registers and they may have floating
1889 There may also be a need to support fixed point @samp{mov@var{m}}
1890 instructions in and out of floating point registers. Unfortunately, I
1891 have forgotten why this was so, and I don't know whether it is still
1892 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
1893 floating point registers, then the constraints of the fixed point
1894 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
1895 reload into a floating point register.
1897 @cindex @code{reload_in} instruction pattern
1898 @cindex @code{reload_out} instruction pattern
1899 @item @samp{reload_in@var{m}}
1900 @itemx @samp{reload_out@var{m}}
1901 Like @samp{mov@var{m}}, but used when a scratch register is required to
1902 move between operand 0 and operand 1. Operand 2 describes the scratch
1903 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
1904 macro in @pxref{Register Classes}.
1906 @cindex @code{movstrict@var{m}} instruction pattern
1907 @item @samp{movstrict@var{m}}
1908 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
1909 with mode @var{m} of a register whose natural mode is wider,
1910 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
1911 any of the register except the part which belongs to mode @var{m}.
1913 @cindex @code{load_multiple} instruction pattern
1914 @item @samp{load_multiple}
1915 Load several consecutive memory locations into consecutive registers.
1916 Operand 0 is the first of the consecutive registers, operand 1
1917 is the first memory location, and operand 2 is a constant: the
1918 number of consecutive registers.
1920 Define this only if the target machine really has such an instruction;
1921 do not define this if the most efficient way of loading consecutive
1922 registers from memory is to do them one at a time.
1924 On some machines, there are restrictions as to which consecutive
1925 registers can be stored into memory, such as particular starting or
1926 ending register numbers or only a range of valid counts. For those
1927 machines, use a @code{define_expand} (@pxref{Expander Definitions})
1928 and make the pattern fail if the restrictions are not met.
1930 Write the generated insn as a @code{parallel} with elements being a
1931 @code{set} of one register from the appropriate memory location (you may
1932 also need @code{use} or @code{clobber} elements). Use a
1933 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
1934 @file{a29k.md} and @file{rs6000.md} for examples of the use of this insn
1937 @cindex @samp{store_multiple} instruction pattern
1938 @item @samp{store_multiple}
1939 Similar to @samp{load_multiple}, but store several consecutive registers
1940 into consecutive memory locations. Operand 0 is the first of the
1941 consecutive memory locations, operand 1 is the first register, and
1942 operand 2 is a constant: the number of consecutive registers.
1944 @cindex @code{add@var{m}3} instruction pattern
1945 @item @samp{add@var{m}3}
1946 Add operand 2 and operand 1, storing the result in operand 0. All operands
1947 must have mode @var{m}. This can be used even on two-address machines, by
1948 means of constraints requiring operands 1 and 0 to be the same location.
1950 @cindex @code{sub@var{m}3} instruction pattern
1951 @cindex @code{mul@var{m}3} instruction pattern
1952 @cindex @code{div@var{m}3} instruction pattern
1953 @cindex @code{udiv@var{m}3} instruction pattern
1954 @cindex @code{mod@var{m}3} instruction pattern
1955 @cindex @code{umod@var{m}3} instruction pattern
1956 @cindex @code{smin@var{m}3} instruction pattern
1957 @cindex @code{smax@var{m}3} instruction pattern
1958 @cindex @code{umin@var{m}3} instruction pattern
1959 @cindex @code{umax@var{m}3} instruction pattern
1960 @cindex @code{and@var{m}3} instruction pattern
1961 @cindex @code{ior@var{m}3} instruction pattern
1962 @cindex @code{xor@var{m}3} instruction pattern
1963 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
1964 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
1965 @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
1966 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
1967 Similar, for other arithmetic operations.
1969 @cindex @code{mulhisi3} instruction pattern
1970 @item @samp{mulhisi3}
1971 Multiply operands 1 and 2, which have mode @code{HImode}, and store
1972 a @code{SImode} product in operand 0.
1974 @cindex @code{mulqihi3} instruction pattern
1975 @cindex @code{mulsidi3} instruction pattern
1976 @item @samp{mulqihi3}, @samp{mulsidi3}
1977 Similar widening-multiplication instructions of other widths.
1979 @cindex @code{umulqihi3} instruction pattern
1980 @cindex @code{umulhisi3} instruction pattern
1981 @cindex @code{umulsidi3} instruction pattern
1982 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
1983 Similar widening-multiplication instructions that do unsigned
1986 @cindex @code{smul@var{m}3_highpart} instruction pattern
1987 @item @samp{smul@var{m}3_highpart}
1988 Perform a signed multiplication of operands 1 and 2, which have mode
1989 @var{m}, and store the most significant half of the product in operand 0.
1990 The least significant half of the product is discarded.
1992 @cindex @code{umul@var{m}3_highpart} instruction pattern
1993 @item @samp{umul@var{m}3_highpart}
1994 Similar, but the multiplication is unsigned.
1996 @cindex @code{divmod@var{m}4} instruction pattern
1997 @item @samp{divmod@var{m}4}
1998 Signed division that produces both a quotient and a remainder.
1999 Operand 1 is divided by operand 2 to produce a quotient stored
2000 in operand 0 and a remainder stored in operand 3.
2002 For machines with an instruction that produces both a quotient and a
2003 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
2004 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
2005 allows optimization in the relatively common case when both the quotient
2006 and remainder are computed.
2008 If an instruction that just produces a quotient or just a remainder
2009 exists and is more efficient than the instruction that produces both,
2010 write the output routine of @samp{divmod@var{m}4} to call
2011 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
2012 quotient or remainder and generate the appropriate instruction.
2014 @cindex @code{udivmod@var{m}4} instruction pattern
2015 @item @samp{udivmod@var{m}4}
2016 Similar, but does unsigned division.
2018 @cindex @code{ashl@var{m}3} instruction pattern
2019 @item @samp{ashl@var{m}3}
2020 Arithmetic-shift operand 1 left by a number of bits specified by operand
2021 2, and store the result in operand 0. Here @var{m} is the mode of
2022 operand 0 and operand 1; operand 2's mode is specified by the
2023 instruction pattern, and the compiler will convert the operand to that
2024 mode before generating the instruction.
2026 @cindex @code{ashr@var{m}3} instruction pattern
2027 @cindex @code{lshr@var{m}3} instruction pattern
2028 @cindex @code{rotl@var{m}3} instruction pattern
2029 @cindex @code{rotr@var{m}3} instruction pattern
2030 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
2031 Other shift and rotate instructions, analogous to the
2032 @code{ashl@var{m}3} instructions.
2034 @cindex @code{neg@var{m}2} instruction pattern
2035 @item @samp{neg@var{m}2}
2036 Negate operand 1 and store the result in operand 0.
2038 @cindex @code{abs@var{m}2} instruction pattern
2039 @item @samp{abs@var{m}2}
2040 Store the absolute value of operand 1 into operand 0.
2042 @cindex @code{sqrt@var{m}2} instruction pattern
2043 @item @samp{sqrt@var{m}2}
2044 Store the square root of operand 1 into operand 0.
2046 The @code{sqrt} built-in function of C always uses the mode which
2047 corresponds to the C data type @code{double}.
2049 @cindex @code{ffs@var{m}2} instruction pattern
2050 @item @samp{ffs@var{m}2}
2051 Store into operand 0 one plus the index of the least significant 1-bit
2052 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
2053 of operand 0; operand 1's mode is specified by the instruction
2054 pattern, and the compiler will convert the operand to that mode before
2055 generating the instruction.
2057 The @code{ffs} built-in function of C always uses the mode which
2058 corresponds to the C data type @code{int}.
2060 @cindex @code{one_cmpl@var{m}2} instruction pattern
2061 @item @samp{one_cmpl@var{m}2}
2062 Store the bitwise-complement of operand 1 into operand 0.
2064 @cindex @code{cmp@var{m}} instruction pattern
2065 @item @samp{cmp@var{m}}
2066 Compare operand 0 and operand 1, and set the condition codes.
2067 The RTL pattern should look like this:
2070 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
2071 (match_operand:@var{m} 1 @dots{})))
2074 @cindex @code{tst@var{m}} instruction pattern
2075 @item @samp{tst@var{m}}
2076 Compare operand 0 against zero, and set the condition codes.
2077 The RTL pattern should look like this:
2080 (set (cc0) (match_operand:@var{m} 0 @dots{}))
2083 @samp{tst@var{m}} patterns should not be defined for machines that do
2084 not use @code{(cc0)}. Doing so would confuse the optimizer since it
2085 would no longer be clear which @code{set} operations were comparisons.
2086 The @samp{cmp@var{m}} patterns should be used instead.
2088 @cindex @code{movstr@var{m}} instruction pattern
2089 @item @samp{movstr@var{m}}
2090 Block move instruction. The addresses of the destination and source
2091 strings are the first two operands, and both are in mode @code{Pmode}.
2093 The number of bytes to move is the third operand, in mode @var{m}.
2094 Usually, you specify @code{word_mode} for @var{m}. However, if you can
2095 generate better code knowing the range of valid lengths is smaller than
2096 those representable in a full word, you should provide a pattern with a
2097 mode corresponding to the range of values you can handle efficiently
2098 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
2099 that appear negative) and also a pattern with @code{word_mode}.
2101 The fourth operand is the known shared alignment of the source and
2102 destination, in the form of a @code{const_int} rtx. Thus, if the
2103 compiler knows that both source and destination are word-aligned,
2104 it may provide the value 4 for this operand.
2106 Descriptions of multiple @code{movstr@var{m}} patterns can only be
2107 beneficial if the patterns for smaller modes have fewer restrictions
2108 on their first, second and fourth operands. Note that the mode @var{m}
2109 in @code{movstr@var{m}} does not impose any restriction on the mode of
2110 individually moved data units in the block.
2112 These patterns need not give special consideration to the possibility
2113 that the source and destination strings might overlap.
2115 @cindex @code{clrstr@var{m}} instruction pattern
2116 @item @samp{clrstr@var{m}}
2117 Block clear instruction. The addresses of the destination string is the
2118 first operand, in mode @code{Pmode}. The number of bytes to clear is
2119 the second operand, in mode @var{m}. See @samp{movstr@var{m}} for
2120 a discussion of the choice of mode.
2122 The third operand is the known alignment of the destination, in the form
2123 of a @code{const_int} rtx. Thus, if the compiler knows that the
2124 destination is word-aligned, it may provide the value 4 for this
2127 The use for multiple @code{clrstr@var{m}} is as for @code{movstr@var{m}}.
2129 @cindex @code{cmpstr@var{m}} instruction pattern
2130 @item @samp{cmpstr@var{m}}
2131 Block compare instruction, with five operands. Operand 0 is the output;
2132 it has mode @var{m}. The remaining four operands are like the operands
2133 of @samp{movstr@var{m}}. The two memory blocks specified are compared
2134 byte by byte in lexicographic order. The effect of the instruction is
2135 to store a value in operand 0 whose sign indicates the result of the
2138 @cindex @code{strlen@var{m}} instruction pattern
2139 @item @samp{strlen@var{m}}
2140 Compute the length of a string, with three operands.
2141 Operand 0 is the result (of mode @var{m}), operand 1 is
2142 a @code{mem} referring to the first character of the string,
2143 operand 2 is the character to search for (normally zero),
2144 and operand 3 is a constant describing the known alignment
2145 of the beginning of the string.
2147 @cindex @code{float@var{mn}2} instruction pattern
2148 @item @samp{float@var{m}@var{n}2}
2149 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
2150 floating point mode @var{n} and store in operand 0 (which has mode
2153 @cindex @code{floatuns@var{mn}2} instruction pattern
2154 @item @samp{floatuns@var{m}@var{n}2}
2155 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
2156 to floating point mode @var{n} and store in operand 0 (which has mode
2159 @cindex @code{fix@var{mn}2} instruction pattern
2160 @item @samp{fix@var{m}@var{n}2}
2161 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2162 point mode @var{n} as a signed number and store in operand 0 (which
2163 has mode @var{n}). This instruction's result is defined only when
2164 the value of operand 1 is an integer.
2166 @cindex @code{fixuns@var{mn}2} instruction pattern
2167 @item @samp{fixuns@var{m}@var{n}2}
2168 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2169 point mode @var{n} as an unsigned number and store in operand 0 (which
2170 has mode @var{n}). This instruction's result is defined only when the
2171 value of operand 1 is an integer.
2173 @cindex @code{ftrunc@var{m}2} instruction pattern
2174 @item @samp{ftrunc@var{m}2}
2175 Convert operand 1 (valid for floating point mode @var{m}) to an
2176 integer value, still represented in floating point mode @var{m}, and
2177 store it in operand 0 (valid for floating point mode @var{m}).
2179 @cindex @code{fix_trunc@var{mn}2} instruction pattern
2180 @item @samp{fix_trunc@var{m}@var{n}2}
2181 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
2182 of mode @var{m} by converting the value to an integer.
2184 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
2185 @item @samp{fixuns_trunc@var{m}@var{n}2}
2186 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
2187 value of mode @var{m} by converting the value to an integer.
2189 @cindex @code{trunc@var{mn}2} instruction pattern
2190 @item @samp{trunc@var{m}@var{n}2}
2191 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
2192 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2193 point or both floating point.
2195 @cindex @code{extend@var{mn}2} instruction pattern
2196 @item @samp{extend@var{m}@var{n}2}
2197 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2198 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2199 point or both floating point.
2201 @cindex @code{zero_extend@var{mn}2} instruction pattern
2202 @item @samp{zero_extend@var{m}@var{n}2}
2203 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2204 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2207 @cindex @code{extv} instruction pattern
2209 Extract a bit field from operand 1 (a register or memory operand), where
2210 operand 2 specifies the width in bits and operand 3 the starting bit,
2211 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
2212 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
2213 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
2214 be valid for @code{word_mode}.
2216 The RTL generation pass generates this instruction only with constants
2217 for operands 2 and 3.
2219 The bit-field value is sign-extended to a full word integer
2220 before it is stored in operand 0.
2222 @cindex @code{extzv} instruction pattern
2224 Like @samp{extv} except that the bit-field value is zero-extended.
2226 @cindex @code{insv} instruction pattern
2228 Store operand 3 (which must be valid for @code{word_mode}) into a bit
2229 field in operand 0, where operand 1 specifies the width in bits and
2230 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
2231 @code{word_mode}; often @code{word_mode} is allowed only for registers.
2232 Operands 1 and 2 must be valid for @code{word_mode}.
2234 The RTL generation pass generates this instruction only with constants
2235 for operands 1 and 2.
2237 @cindex @code{mov@var{mode}cc} instruction pattern
2238 @item @samp{mov@var{mode}cc}
2239 Conditionally move operand 2 or operand 3 into operand 0 according to the
2240 comparison in operand 1. If the comparison is true, operand 2 is moved
2241 into operand 0, otherwise operand 3 is moved.
2243 The mode of the operands being compared need not be the same as the operands
2244 being moved. Some machines, sparc64 for example, have instructions that
2245 conditionally move an integer value based on the floating point condition
2246 codes and vice versa.
2248 If the machine does not have conditional move instructions, do not
2249 define these patterns.
2251 @cindex @code{s@var{cond}} instruction pattern
2252 @item @samp{s@var{cond}}
2253 Store zero or nonzero in the operand according to the condition codes.
2254 Value stored is nonzero iff the condition @var{cond} is true.
2255 @var{cond} is the name of a comparison operation expression code, such
2256 as @code{eq}, @code{lt} or @code{leu}.
2258 You specify the mode that the operand must have when you write the
2259 @code{match_operand} expression. The compiler automatically sees
2260 which mode you have used and supplies an operand of that mode.
2262 The value stored for a true condition must have 1 as its low bit, or
2263 else must be negative. Otherwise the instruction is not suitable and
2264 you should omit it from the machine description. You describe to the
2265 compiler exactly which value is stored by defining the macro
2266 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
2267 found that can be used for all the @samp{s@var{cond}} patterns, you
2268 should omit those operations from the machine description.
2270 These operations may fail, but should do so only in relatively
2271 uncommon cases; if they would fail for common cases involving
2272 integer comparisons, it is best to omit these patterns.
2274 If these operations are omitted, the compiler will usually generate code
2275 that copies the constant one to the target and branches around an
2276 assignment of zero to the target. If this code is more efficient than
2277 the potential instructions used for the @samp{s@var{cond}} pattern
2278 followed by those required to convert the result into a 1 or a zero in
2279 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
2280 the machine description.
2282 @cindex @code{b@var{cond}} instruction pattern
2283 @item @samp{b@var{cond}}
2284 Conditional branch instruction. Operand 0 is a @code{label_ref} that
2285 refers to the label to jump to. Jump if the condition codes meet
2286 condition @var{cond}.
2288 Some machines do not follow the model assumed here where a comparison
2289 instruction is followed by a conditional branch instruction. In that
2290 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
2291 simply store the operands away and generate all the required insns in a
2292 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
2293 branch operations. All calls to expand @samp{b@var{cond}} patterns are
2294 immediately preceded by calls to expand either a @samp{cmp@var{m}}
2295 pattern or a @samp{tst@var{m}} pattern.
2297 Machines that use a pseudo register for the condition code value, or
2298 where the mode used for the comparison depends on the condition being
2299 tested, should also use the above mechanism. @xref{Jump Patterns}.
2301 The above discussion also applies to the @samp{mov@var{mode}cc} and
2302 @samp{s@var{cond}} patterns.
2304 @cindex @code{jump} instruction pattern
2306 A jump inside a function; an unconditional branch. Operand 0 is the
2307 @code{label_ref} of the label to jump to. This pattern name is mandatory
2310 @cindex @code{call} instruction pattern
2312 Subroutine call instruction returning no value. Operand 0 is the
2313 function to call; operand 1 is the number of bytes of arguments pushed
2314 as a @code{const_int}; operand 2 is the number of registers used as
2317 On most machines, operand 2 is not actually stored into the RTL
2318 pattern. It is supplied for the sake of some RISC machines which need
2319 to put this information into the assembler code; they can put it in
2320 the RTL instead of operand 1.
2322 Operand 0 should be a @code{mem} RTX whose address is the address of the
2323 function. Note, however, that this address can be a @code{symbol_ref}
2324 expression even if it would not be a legitimate memory address on the
2325 target machine. If it is also not a valid argument for a call
2326 instruction, the pattern for this operation should be a
2327 @code{define_expand} (@pxref{Expander Definitions}) that places the
2328 address into a register and uses that register in the call instruction.
2330 @cindex @code{call_value} instruction pattern
2331 @item @samp{call_value}
2332 Subroutine call instruction returning a value. Operand 0 is the hard
2333 register in which the value is returned. There are three more
2334 operands, the same as the three operands of the @samp{call}
2335 instruction (but with numbers increased by one).
2337 Subroutines that return @code{BLKmode} objects use the @samp{call}
2340 @cindex @code{call_pop} instruction pattern
2341 @cindex @code{call_value_pop} instruction pattern
2342 @item @samp{call_pop}, @samp{call_value_pop}
2343 Similar to @samp{call} and @samp{call_value}, except used if defined and
2344 if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel}
2345 that contains both the function call and a @code{set} to indicate the
2346 adjustment made to the frame pointer.
2348 For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these
2349 patterns increases the number of functions for which the frame pointer
2350 can be eliminated, if desired.
2352 @cindex @code{untyped_call} instruction pattern
2353 @item @samp{untyped_call}
2354 Subroutine call instruction returning a value of any type. Operand 0 is
2355 the function to call; operand 1 is a memory location where the result of
2356 calling the function is to be stored; operand 2 is a @code{parallel}
2357 expression where each element is a @code{set} expression that indicates
2358 the saving of a function return value into the result block.
2360 This instruction pattern should be defined to support
2361 @code{__builtin_apply} on machines where special instructions are needed
2362 to call a subroutine with arbitrary arguments or to save the value
2363 returned. This instruction pattern is required on machines that have
2364 multiple registers that can hold a return value (i.e.
2365 @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
2367 @cindex @code{return} instruction pattern
2369 Subroutine return instruction. This instruction pattern name should be
2370 defined only if a single instruction can do all the work of returning
2373 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
2374 RTL generation phase. In this case it is to support machines where
2375 multiple instructions are usually needed to return from a function, but
2376 some class of functions only requires one instruction to implement a
2377 return. Normally, the applicable functions are those which do not need
2378 to save any registers or allocate stack space.
2380 @findex reload_completed
2381 @findex leaf_function_p
2382 For such machines, the condition specified in this pattern should only
2383 be true when @code{reload_completed} is non-zero and the function's
2384 epilogue would only be a single instruction. For machines with register
2385 windows, the routine @code{leaf_function_p} may be used to determine if
2386 a register window push is required.
2388 Machines that have conditional return instructions should define patterns
2394 (if_then_else (match_operator
2395 0 "comparison_operator"
2396 [(cc0) (const_int 0)])
2403 where @var{condition} would normally be the same condition specified on the
2404 named @samp{return} pattern.
2406 @cindex @code{untyped_return} instruction pattern
2407 @item @samp{untyped_return}
2408 Untyped subroutine return instruction. This instruction pattern should
2409 be defined to support @code{__builtin_return} on machines where special
2410 instructions are needed to return a value of any type.
2412 Operand 0 is a memory location where the result of calling a function
2413 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
2414 expression where each element is a @code{set} expression that indicates
2415 the restoring of a function return value from the result block.
2417 @cindex @code{nop} instruction pattern
2419 No-op instruction. This instruction pattern name should always be defined
2420 to output a no-op in assembler code. @code{(const_int 0)} will do as an
2423 @cindex @code{indirect_jump} instruction pattern
2424 @item @samp{indirect_jump}
2425 An instruction to jump to an address which is operand zero.
2426 This pattern name is mandatory on all machines.
2428 @cindex @code{casesi} instruction pattern
2430 Instruction to jump through a dispatch table, including bounds checking.
2431 This instruction takes five operands:
2435 The index to dispatch on, which has mode @code{SImode}.
2438 The lower bound for indices in the table, an integer constant.
2441 The total range of indices in the table---the largest index
2442 minus the smallest one (both inclusive).
2445 A label that precedes the table itself.
2448 A label to jump to if the index has a value outside the bounds.
2449 (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
2450 then an out-of-bounds index drops through to the code following
2451 the jump table instead of jumping to this label. In that case,
2452 this label is not actually used by the @samp{casesi} instruction,
2453 but it is always provided as an operand.)
2456 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
2457 @code{jump_insn}. The number of elements in the table is one plus the
2458 difference between the upper bound and the lower bound.
2460 @cindex @code{tablejump} instruction pattern
2461 @item @samp{tablejump}
2462 Instruction to jump to a variable address. This is a low-level
2463 capability which can be used to implement a dispatch table when there
2464 is no @samp{casesi} pattern.
2466 This pattern requires two operands: the address or offset, and a label
2467 which should immediately precede the jump table. If the macro
2468 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
2469 operand is an offset which counts from the address of the table; otherwise,
2470 it is an absolute address to jump to. In either case, the first operand has
2473 The @samp{tablejump} insn is always the last insn before the jump
2474 table it uses. Its assembler code normally has no need to use the
2475 second operand, but you should incorporate it in the RTL pattern so
2476 that the jump optimizer will not delete the table as unreachable code.
2478 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
2479 @item @samp{canonicalize_funcptr_for_compare}
2480 Canonicalize the function pointer in operand 1 and store the result
2483 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
2484 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
2485 and also has mode @code{Pmode}.
2487 Canonicalization of a function pointer usually involves computing
2488 the address of the function which would be called if the function
2489 pointer were used in an indirect call.
2491 Only define this pattern if function pointers on the target machine
2492 can have different values but still call the same function when
2493 used in an indirect call.
2495 @cindex @code{save_stack_block} instruction pattern
2496 @cindex @code{save_stack_function} instruction pattern
2497 @cindex @code{save_stack_nonlocal} instruction pattern
2498 @cindex @code{restore_stack_block} instruction pattern
2499 @cindex @code{restore_stack_function} instruction pattern
2500 @cindex @code{restore_stack_nonlocal} instruction pattern
2501 @item @samp{save_stack_block}
2502 @itemx @samp{save_stack_function}
2503 @itemx @samp{save_stack_nonlocal}
2504 @itemx @samp{restore_stack_block}
2505 @itemx @samp{restore_stack_function}
2506 @itemx @samp{restore_stack_nonlocal}
2507 Most machines save and restore the stack pointer by copying it to or
2508 from an object of mode @code{Pmode}. Do not define these patterns on
2511 Some machines require special handling for stack pointer saves and
2512 restores. On those machines, define the patterns corresponding to the
2513 non-standard cases by using a @code{define_expand} (@pxref{Expander
2514 Definitions}) that produces the required insns. The three types of
2515 saves and restores are:
2519 @samp{save_stack_block} saves the stack pointer at the start of a block
2520 that allocates a variable-sized object, and @samp{restore_stack_block}
2521 restores the stack pointer when the block is exited.
2524 @samp{save_stack_function} and @samp{restore_stack_function} do a
2525 similar job for the outermost block of a function and are used when the
2526 function allocates variable-sized objects or calls @code{alloca}. Only
2527 the epilogue uses the restored stack pointer, allowing a simpler save or
2528 restore sequence on some machines.
2531 @samp{save_stack_nonlocal} is used in functions that contain labels
2532 branched to by nested functions. It saves the stack pointer in such a
2533 way that the inner function can use @samp{restore_stack_nonlocal} to
2534 restore the stack pointer. The compiler generates code to restore the
2535 frame and argument pointer registers, but some machines require saving
2536 and restoring additional data such as register window information or
2537 stack backchains. Place insns in these patterns to save and restore any
2541 When saving the stack pointer, operand 0 is the save area and operand 1
2542 is the stack pointer. The mode used to allocate the save area defaults
2543 to @code{Pmode} but you can override that choice by defining the
2544 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
2545 specify an integral mode, or @code{VOIDmode} if no save area is needed
2546 for a particular type of save (either because no save is needed or
2547 because a machine-specific save area can be used). Operand 0 is the
2548 stack pointer and operand 1 is the save area for restore operations. If
2549 @samp{save_stack_block} is defined, operand 0 must not be
2550 @code{VOIDmode} since these saves can be arbitrarily nested.
2552 A save area is a @code{mem} that is at a constant offset from
2553 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
2554 nonlocal gotos and a @code{reg} in the other two cases.
2556 @cindex @code{allocate_stack} instruction pattern
2557 @item @samp{allocate_stack}
2558 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
2559 the stack pointer to create space for dynamically allocated data.
2561 Store the resultant pointer to this space into operand 0. If you
2562 are allocating space from the main stack, do this by emitting a
2563 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
2564 If you are allocating the space elsewhere, generate code to copy the
2565 location of the space to operand 0. In the latter case, you must
2566 ensure this space gets freed when the corresponding space on the main
2569 Do not define this pattern if all that must be done is the subtraction.
2570 Some machines require other operations such as stack probes or
2571 maintaining the back chain. Define this pattern to emit those
2572 operations in addition to updating the stack pointer.
2574 @cindex @code{probe} instruction pattern
2576 Some machines require instructions to be executed after space is
2577 allocated from the stack, for example to generate a reference at
2578 the bottom of the stack.
2580 If you need to emit instructions before the stack has been adjusted,
2581 put them into the @samp{allocate_stack} pattern. Otherwise, define
2582 this pattern to emit the required instructions.
2584 No operands are provided.
2586 @cindex @code{check_stack} instruction pattern
2587 @item @samp{check_stack}
2588 If stack checking cannot be done on your system by probing the stack with
2589 a load or store instruction (@pxref{Stack Checking}), define this pattern
2590 to perform the needed check and signaling an error if the stack
2591 has overflowed. The single operand is the location in the stack furthest
2592 from the current stack pointer that you need to validate. Normally,
2593 on machines where this pattern is needed, you would obtain the stack
2594 limit from a global or thread-specific variable or register.
2596 @cindex @code{nonlocal_goto} instruction pattern
2597 @item @samp{nonlocal_goto}
2598 Emit code to generate a non-local goto, e.g., a jump from one function
2599 to a label in an outer function. This pattern has four arguments,
2600 each representing a value to be used in the jump. The first
2601 argument is to be loaded into the frame pointer, the second is
2602 the address to branch to (code to dispatch to the actual label),
2603 the third is the address of a location where the stack is saved,
2604 and the last is the address of the label, to be placed in the
2605 location for the incoming static chain.
2607 On most machines you need not define this pattern, since GNU CC will
2608 already generate the correct code, which is to load the frame pointer
2609 and static chain, restore the stack (using the
2610 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
2611 to the dispatcher. You need only define this pattern if this code will
2612 not work on your machine.
2614 @cindex @code{nonlocal_goto_receiver} instruction pattern
2615 @item @samp{nonlocal_goto_receiver}
2616 This pattern, if defined, contains code needed at the target of a
2617 nonlocal goto after the code already generated by GNU CC. You will not
2618 normally need to define this pattern. A typical reason why you might
2619 need this pattern is if some value, such as a pointer to a global table,
2620 must be restored when the frame pointer is restored. Note that a nonlocal
2621 goto only occurs within a unit-of-translation, so a global table pointer
2622 that is shared by all functions of a given module need not be restored.
2623 There are no arguments.
2625 @cindex @code{exception_receiver} instruction pattern
2626 @item @samp{exception_receiver}
2627 This pattern, if defined, contains code needed at the site of an
2628 exception handler that isn't needed at the site of a nonlocal goto. You
2629 will not normally need to define this pattern. A typical reason why you
2630 might need this pattern is if some value, such as a pointer to a global
2631 table, must be restored after control flow is branched to the handler of
2632 an exception. There are no arguments.
2634 @cindex @code{builtin_setjmp_setup} instruction pattern
2635 @item @samp{builtin_setjmp_setup}
2636 This pattern, if defined, contains additional code needed to initialize
2637 the @code{jmp_buf}. You will not normally need to define this pattern.
2638 A typical reason why you might need this pattern is if some value, such
2639 as a pointer to a global table, must be restored. Though it is
2640 preferred that the pointer value be recalculated if possible (given the
2641 address of a label for instance). The single argument is a pointer to
2642 the @code{jmp_buf}. Note that the buffer is five words long and that
2643 the first three are normally used by the generic mechanism.
2645 @cindex @code{builtin_setjmp_receiver} instruction pattern
2646 @item @samp{builtin_setjmp_receiver}
2647 This pattern, if defined, contains code needed at the site of an
2648 builtin setjmp that isn't needed at the site of a nonlocal goto. You
2649 will not normally need to define this pattern. A typical reason why you
2650 might need this pattern is if some value, such as a pointer to a global
2651 table, must be restored. It takes one argument, which is the label
2652 to which builtin_longjmp transfered control; this pattern may be emitted
2653 at a small offset from that label.
2655 @cindex @code{builtin_longjmp} instruction pattern
2656 @item @samp{builtin_longjmp}
2657 This pattern, if defined, performs the entire action of the longjmp.
2658 You will not normally need to define this pattern unless you also define
2659 @code{builtin_setjmp_setup}. The single argument is a pointer to the
2662 @cindex @code{eh_epilogue} instruction pattern
2663 @item @samp{eh_epilogue}
2664 This pattern, if defined, affects the way @code{__builtin_eh_return},
2665 and thence @code{__throw} are built. It is intended to allow communication
2666 between the exception handling machinery and the normal epilogue code
2669 The pattern takes three arguments. The first is the exception context
2670 pointer. This will have already been copied to the function return
2671 register appropriate for a pointer; normally this can be ignored. The
2672 second argument is an offset to be added to the stack pointer. It will
2673 have been copied to some arbitrary call-clobbered hard reg so that it
2674 will survive until after reload to when the normal epilogue is generated.
2675 The final argument is the address of the exception handler to which
2676 the function should return. This will normally need to copied by the
2677 pattern to some special register.
2679 This pattern must be defined if @code{RETURN_ADDR_RTX} does not yield
2680 something that can be reliably and permanently modified, i.e. a fixed
2681 hard register or a stack memory reference.
2683 @cindex @code{prologue} instruction pattern
2684 @item @samp{prologue}
2685 This pattern, if defined, emits RTL for entry to a function. The function
2686 entry is responsible for setting up the stack frame, initializing the frame
2687 pointer register, saving callee saved registers, etc.
2689 Using a prologue pattern is generally preferred over defining
2690 @code{FUNCTION_PROLOGUE} to emit assembly code for the prologue.
2692 The @code{prologue} pattern is particularly useful for targets which perform
2693 instruction scheduling.
2695 @cindex @code{epilogue} instruction pattern
2696 @item @samp{epilogue}
2697 This pattern, if defined, emits RTL for exit from a function. The function
2698 exit is responsible for deallocating the stack frame, restoring callee saved
2699 registers and emitting the return instruction.
2701 Using an epilogue pattern is generally preferred over defining
2702 @code{FUNCTION_EPILOGUE} to emit assembly code for the prologue.
2704 The @code{epilogue} pattern is particularly useful for targets which perform
2705 instruction scheduling or which have delay slots for their return instruction.
2707 @cindex @code{sibcall_epilogue} instruction pattern
2708 @item @samp{sibcall_epilogue}
2709 This pattern, if defined, emits RTL for exit from a function without the final
2710 branch back to the calling function. This pattern will be emitted before any
2711 sibling call (aka tail call) sites.
2713 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
2714 parameter passing or any stack slots for arguments passed to the current
2717 @cindex @code{trap} instruction pattern
2719 This pattern, if defined, signals an error, typically by causing some
2720 kind of signal to be raised. Among other places, it is used by the Java
2721 frontend to signal `invalid array index' exceptions.
2723 @cindex @code{conditional_trap} instruction pattern
2724 @item @samp{conditional_trap}
2725 Conditional trap instruction. Operand 0 is a piece of RTL which
2726 performs a comparison. Operand 1 is the trap code, an integer.
2728 A typical @code{conditional_trap} pattern looks like
2731 (define_insn "conditional_trap"
2732 [(trap_if (match_operator 0 "trap_operator"
2733 [(cc0) (const_int 0)])
2734 (match_operand 1 "const_int_operand" "i"))]
2741 @node Pattern Ordering
2742 @section When the Order of Patterns Matters
2743 @cindex Pattern Ordering
2744 @cindex Ordering of Patterns
2746 Sometimes an insn can match more than one instruction pattern. Then the
2747 pattern that appears first in the machine description is the one used.
2748 Therefore, more specific patterns (patterns that will match fewer things)
2749 and faster instructions (those that will produce better code when they
2750 do match) should usually go first in the description.
2752 In some cases the effect of ordering the patterns can be used to hide
2753 a pattern when it is not valid. For example, the 68000 has an
2754 instruction for converting a fullword to floating point and another
2755 for converting a byte to floating point. An instruction converting
2756 an integer to floating point could match either one. We put the
2757 pattern to convert the fullword first to make sure that one will
2758 be used rather than the other. (Otherwise a large integer might
2759 be generated as a single-byte immediate quantity, which would not work.)
2760 Instead of using this pattern ordering it would be possible to make the
2761 pattern for convert-a-byte smart enough to deal properly with any
2764 @node Dependent Patterns
2765 @section Interdependence of Patterns
2766 @cindex Dependent Patterns
2767 @cindex Interdependence of Patterns
2769 Every machine description must have a named pattern for each of the
2770 conditional branch names @samp{b@var{cond}}. The recognition template
2771 must always have the form
2775 (if_then_else (@var{cond} (cc0) (const_int 0))
2776 (label_ref (match_operand 0 "" ""))
2781 In addition, every machine description must have an anonymous pattern
2782 for each of the possible reverse-conditional branches. Their templates
2787 (if_then_else (@var{cond} (cc0) (const_int 0))
2789 (label_ref (match_operand 0 "" ""))))
2793 They are necessary because jump optimization can turn direct-conditional
2794 branches into reverse-conditional branches.
2796 It is often convenient to use the @code{match_operator} construct to
2797 reduce the number of patterns that must be specified for branches. For
2803 (if_then_else (match_operator 0 "comparison_operator"
2804 [(cc0) (const_int 0)])
2806 (label_ref (match_operand 1 "" ""))))]
2811 In some cases machines support instructions identical except for the
2812 machine mode of one or more operands. For example, there may be
2813 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
2817 (set (match_operand:SI 0 @dots{})
2818 (extend:SI (match_operand:HI 1 @dots{})))
2820 (set (match_operand:SI 0 @dots{})
2821 (extend:SI (match_operand:QI 1 @dots{})))
2825 Constant integers do not specify a machine mode, so an instruction to
2826 extend a constant value could match either pattern. The pattern it
2827 actually will match is the one that appears first in the file. For correct
2828 results, this must be the one for the widest possible mode (@code{HImode},
2829 here). If the pattern matches the @code{QImode} instruction, the results
2830 will be incorrect if the constant value does not actually fit that mode.
2832 Such instructions to extend constants are rarely generated because they are
2833 optimized away, but they do occasionally happen in nonoptimized
2836 If a constraint in a pattern allows a constant, the reload pass may
2837 replace a register with a constant permitted by the constraint in some
2838 cases. Similarly for memory references. Because of this substitution,
2839 you should not provide separate patterns for increment and decrement
2840 instructions. Instead, they should be generated from the same pattern
2841 that supports register-register add insns by examining the operands and
2842 generating the appropriate machine instruction.
2845 @section Defining Jump Instruction Patterns
2846 @cindex jump instruction patterns
2847 @cindex defining jump instruction patterns
2849 For most machines, GNU CC assumes that the machine has a condition code.
2850 A comparison insn sets the condition code, recording the results of both
2851 signed and unsigned comparison of the given operands. A separate branch
2852 insn tests the condition code and branches or not according its value.
2853 The branch insns come in distinct signed and unsigned flavors. Many
2854 common machines, such as the Vax, the 68000 and the 32000, work this
2857 Some machines have distinct signed and unsigned compare instructions, and
2858 only one set of conditional branch instructions. The easiest way to handle
2859 these machines is to treat them just like the others until the final stage
2860 where assembly code is written. At this time, when outputting code for the
2861 compare instruction, peek ahead at the following branch using
2862 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
2863 being output, in the output-writing code in an instruction pattern.) If
2864 the RTL says that is an unsigned branch, output an unsigned compare;
2865 otherwise output a signed compare. When the branch itself is output, you
2866 can treat signed and unsigned branches identically.
2868 The reason you can do this is that GNU CC always generates a pair of
2869 consecutive RTL insns, possibly separated by @code{note} insns, one to
2870 set the condition code and one to test it, and keeps the pair inviolate
2873 To go with this technique, you must define the machine-description macro
2874 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
2875 compare instruction is superfluous.
2877 Some machines have compare-and-branch instructions and no condition code.
2878 A similar technique works for them. When it is time to ``output'' a
2879 compare instruction, record its operands in two static variables. When
2880 outputting the branch-on-condition-code instruction that follows, actually
2881 output a compare-and-branch instruction that uses the remembered operands.
2883 It also works to define patterns for compare-and-branch instructions.
2884 In optimizing compilation, the pair of compare and branch instructions
2885 will be combined according to these patterns. But this does not happen
2886 if optimization is not requested. So you must use one of the solutions
2887 above in addition to any special patterns you define.
2889 In many RISC machines, most instructions do not affect the condition
2890 code and there may not even be a separate condition code register. On
2891 these machines, the restriction that the definition and use of the
2892 condition code be adjacent insns is not necessary and can prevent
2893 important optimizations. For example, on the IBM RS/6000, there is a
2894 delay for taken branches unless the condition code register is set three
2895 instructions earlier than the conditional branch. The instruction
2896 scheduler cannot perform this optimization if it is not permitted to
2897 separate the definition and use of the condition code register.
2899 On these machines, do not use @code{(cc0)}, but instead use a register
2900 to represent the condition code. If there is a specific condition code
2901 register in the machine, use a hard register. If the condition code or
2902 comparison result can be placed in any general register, or if there are
2903 multiple condition registers, use a pseudo register.
2905 @findex prev_cc0_setter
2906 @findex next_cc0_user
2907 On some machines, the type of branch instruction generated may depend on
2908 the way the condition code was produced; for example, on the 68k and
2909 Sparc, setting the condition code directly from an add or subtract
2910 instruction does not clear the overflow bit the way that a test
2911 instruction does, so a different branch instruction must be used for
2912 some conditional branches. For machines that use @code{(cc0)}, the set
2913 and use of the condition code must be adjacent (separated only by
2914 @code{note} insns) allowing flags in @code{cc_status} to be used.
2915 (@xref{Condition Code}.) Also, the comparison and branch insns can be
2916 located from each other by using the functions @code{prev_cc0_setter}
2917 and @code{next_cc0_user}.
2919 However, this is not true on machines that do not use @code{(cc0)}. On
2920 those machines, no assumptions can be made about the adjacency of the
2921 compare and branch insns and the above methods cannot be used. Instead,
2922 we use the machine mode of the condition code register to record
2923 different formats of the condition code register.
2925 Registers used to store the condition code value should have a mode that
2926 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
2927 additional modes are required (as for the add example mentioned above in
2928 the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
2929 additional modes required (@pxref{Condition Code}). Also define
2930 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
2932 If it is known during RTL generation that a different mode will be
2933 required (for example, if the machine has separate compare instructions
2934 for signed and unsigned quantities, like most IBM processors), they can
2935 be specified at that time.
2937 If the cases that require different modes would be made by instruction
2938 combination, the macro @code{SELECT_CC_MODE} determines which machine
2939 mode should be used for the comparison result. The patterns should be
2940 written using that mode. To support the case of the add on the Sparc
2941 discussed above, we have the pattern
2945 [(set (reg:CC_NOOV 0)
2947 (plus:SI (match_operand:SI 0 "register_operand" "%r")
2948 (match_operand:SI 1 "arith_operand" "rI"))
2954 The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
2955 for comparisons whose argument is a @code{plus}.
2957 @node Insn Canonicalizations
2958 @section Canonicalization of Instructions
2959 @cindex canonicalization of instructions
2960 @cindex insn canonicalization
2962 There are often cases where multiple RTL expressions could represent an
2963 operation performed by a single machine instruction. This situation is
2964 most commonly encountered with logical, branch, and multiply-accumulate
2965 instructions. In such cases, the compiler attempts to convert these
2966 multiple RTL expressions into a single canonical form to reduce the
2967 number of insn patterns required.
2969 In addition to algebraic simplifications, following canonicalizations
2974 For commutative and comparison operators, a constant is always made the
2975 second operand. If a machine only supports a constant as the second
2976 operand, only patterns that match a constant in the second operand need
2979 @cindex @code{neg}, canonicalization of
2980 @cindex @code{not}, canonicalization of
2981 @cindex @code{mult}, canonicalization of
2982 @cindex @code{plus}, canonicalization of
2983 @cindex @code{minus}, canonicalization of
2984 For these operators, if only one operand is a @code{neg}, @code{not},
2985 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
2988 @cindex @code{compare}, canonicalization of
2990 For the @code{compare} operator, a constant is always the second operand
2991 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
2992 machines, there are rare cases where the compiler might want to construct
2993 a @code{compare} with a constant as the first operand. However, these
2994 cases are not common enough for it to be worthwhile to provide a pattern
2995 matching a constant as the first operand unless the machine actually has
2996 such an instruction.
2998 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
2999 @code{minus} is made the first operand under the same conditions as
3003 @code{(minus @var{x} (const_int @var{n}))} is converted to
3004 @code{(plus @var{x} (const_int @var{-n}))}.
3007 Within address computations (i.e., inside @code{mem}), a left shift is
3008 converted into the appropriate multiplication by a power of two.
3010 @cindex @code{ior}, canonicalization of
3011 @cindex @code{and}, canonicalization of
3012 @cindex De Morgan's law
3014 De`Morgan's Law is used to move bitwise negation inside a bitwise
3015 logical-and or logical-or operation. If this results in only one
3016 operand being a @code{not} expression, it will be the first one.
3018 A machine that has an instruction that performs a bitwise logical-and of one
3019 operand with the bitwise negation of the other should specify the pattern
3020 for that instruction as
3024 [(set (match_operand:@var{m} 0 @dots{})
3025 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3026 (match_operand:@var{m} 2 @dots{})))]
3032 Similarly, a pattern for a ``NAND'' instruction should be written
3036 [(set (match_operand:@var{m} 0 @dots{})
3037 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
3038 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
3043 In both cases, it is not necessary to include patterns for the many
3044 logically equivalent RTL expressions.
3046 @cindex @code{xor}, canonicalization of
3048 The only possible RTL expressions involving both bitwise exclusive-or
3049 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
3050 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.@refill
3053 The sum of three items, one of which is a constant, will only appear in
3057 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
3061 On machines that do not use @code{cc0},
3062 @code{(compare @var{x} (const_int 0))} will be converted to
3065 @cindex @code{zero_extract}, canonicalization of
3066 @cindex @code{sign_extract}, canonicalization of
3068 Equality comparisons of a group of bits (usually a single bit) with zero
3069 will be written using @code{zero_extract} rather than the equivalent
3070 @code{and} or @code{sign_extract} operations.
3074 @node Expander Definitions
3075 @section Defining RTL Sequences for Code Generation
3076 @cindex expander definitions
3077 @cindex code generation RTL sequences
3078 @cindex defining RTL sequences for code generation
3080 On some target machines, some standard pattern names for RTL generation
3081 cannot be handled with single insn, but a sequence of RTL insns can
3082 represent them. For these target machines, you can write a
3083 @code{define_expand} to specify how to generate the sequence of RTL.
3085 @findex define_expand
3086 A @code{define_expand} is an RTL expression that looks almost like a
3087 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
3088 only for RTL generation and it can produce more than one RTL insn.
3090 A @code{define_expand} RTX has four operands:
3094 The name. Each @code{define_expand} must have a name, since the only
3095 use for it is to refer to it by name.
3098 The RTL template. This is a vector of RTL expressions representing
3099 a sequence of separate instructions. Unlike @code{define_insn}, there
3100 is no implicit surrounding @code{PARALLEL}.
3103 The condition, a string containing a C expression. This expression is
3104 used to express how the availability of this pattern depends on
3105 subclasses of target machine, selected by command-line options when GNU
3106 CC is run. This is just like the condition of a @code{define_insn} that
3107 has a standard name. Therefore, the condition (if present) may not
3108 depend on the data in the insn being matched, but only the
3109 target-machine-type flags. The compiler needs to test these conditions
3110 during initialization in order to learn exactly which named instructions
3111 are available in a particular run.
3114 The preparation statements, a string containing zero or more C
3115 statements which are to be executed before RTL code is generated from
3118 Usually these statements prepare temporary registers for use as
3119 internal operands in the RTL template, but they can also generate RTL
3120 insns directly by calling routines such as @code{emit_insn}, etc.
3121 Any such insns precede the ones that come from the RTL template.
3124 Every RTL insn emitted by a @code{define_expand} must match some
3125 @code{define_insn} in the machine description. Otherwise, the compiler
3126 will crash when trying to generate code for the insn or trying to optimize
3129 The RTL template, in addition to controlling generation of RTL insns,
3130 also describes the operands that need to be specified when this pattern
3131 is used. In particular, it gives a predicate for each operand.
3133 A true operand, which needs to be specified in order to generate RTL from
3134 the pattern, should be described with a @code{match_operand} in its first
3135 occurrence in the RTL template. This enters information on the operand's
3136 predicate into the tables that record such things. GNU CC uses the
3137 information to preload the operand into a register if that is required for
3138 valid RTL code. If the operand is referred to more than once, subsequent
3139 references should use @code{match_dup}.
3141 The RTL template may also refer to internal ``operands'' which are
3142 temporary registers or labels used only within the sequence made by the
3143 @code{define_expand}. Internal operands are substituted into the RTL
3144 template with @code{match_dup}, never with @code{match_operand}. The
3145 values of the internal operands are not passed in as arguments by the
3146 compiler when it requests use of this pattern. Instead, they are computed
3147 within the pattern, in the preparation statements. These statements
3148 compute the values and store them into the appropriate elements of
3149 @code{operands} so that @code{match_dup} can find them.
3151 There are two special macros defined for use in the preparation statements:
3152 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
3159 Use the @code{DONE} macro to end RTL generation for the pattern. The
3160 only RTL insns resulting from the pattern on this occasion will be
3161 those already emitted by explicit calls to @code{emit_insn} within the
3162 preparation statements; the RTL template will not be generated.
3166 Make the pattern fail on this occasion. When a pattern fails, it means
3167 that the pattern was not truly available. The calling routines in the
3168 compiler will try other strategies for code generation using other patterns.
3170 Failure is currently supported only for binary (addition, multiplication,
3171 shifting, etc.) and bitfield (@code{extv}, @code{extzv}, and @code{insv})
3175 Here is an example, the definition of left-shift for the SPUR chip:
3179 (define_expand "ashlsi3"
3180 [(set (match_operand:SI 0 "register_operand" "")
3184 (match_operand:SI 1 "register_operand" "")
3185 (match_operand:SI 2 "nonmemory_operand" "")))]
3194 if (GET_CODE (operands[2]) != CONST_INT
3195 || (unsigned) INTVAL (operands[2]) > 3)
3202 This example uses @code{define_expand} so that it can generate an RTL insn
3203 for shifting when the shift-count is in the supported range of 0 to 3 but
3204 fail in other cases where machine insns aren't available. When it fails,
3205 the compiler tries another strategy using different patterns (such as, a
3208 If the compiler were able to handle nontrivial condition-strings in
3209 patterns with names, then it would be possible to use a
3210 @code{define_insn} in that case. Here is another case (zero-extension
3211 on the 68000) which makes more use of the power of @code{define_expand}:
3214 (define_expand "zero_extendhisi2"
3215 [(set (match_operand:SI 0 "general_operand" "")
3217 (set (strict_low_part
3221 (match_operand:HI 1 "general_operand" ""))]
3223 "operands[1] = make_safe_from (operands[1], operands[0]);")
3227 @findex make_safe_from
3228 Here two RTL insns are generated, one to clear the entire output operand
3229 and the other to copy the input operand into its low half. This sequence
3230 is incorrect if the input operand refers to [the old value of] the output
3231 operand, so the preparation statement makes sure this isn't so. The
3232 function @code{make_safe_from} copies the @code{operands[1]} into a
3233 temporary register if it refers to @code{operands[0]}. It does this
3234 by emitting another RTL insn.
3236 Finally, a third example shows the use of an internal operand.
3237 Zero-extension on the SPUR chip is done by @code{and}-ing the result
3238 against a halfword mask. But this mask cannot be represented by a
3239 @code{const_int} because the constant value is too large to be legitimate
3240 on this machine. So it must be copied into a register with
3241 @code{force_reg} and then the register used in the @code{and}.
3244 (define_expand "zero_extendhisi2"
3245 [(set (match_operand:SI 0 "register_operand" "")
3247 (match_operand:HI 1 "register_operand" "")
3252 = force_reg (SImode, GEN_INT (65535)); ")
3255 @strong{Note:} If the @code{define_expand} is used to serve a
3256 standard binary or unary arithmetic operation or a bitfield operation,
3257 then the last insn it generates must not be a @code{code_label},
3258 @code{barrier} or @code{note}. It must be an @code{insn},
3259 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
3260 at the end, emit an insn to copy the result of the operation into
3261 itself. Such an insn will generate no code, but it can avoid problems
3262 in the compiler.@refill
3264 @node Insn Splitting
3265 @section Defining How to Split Instructions
3266 @cindex insn splitting
3267 @cindex instruction splitting
3268 @cindex splitting instructions
3270 There are two cases where you should specify how to split a pattern into
3271 multiple insns. On machines that have instructions requiring delay
3272 slots (@pxref{Delay Slots}) or that have instructions whose output is
3273 not available for multiple cycles (@pxref{Function Units}), the compiler
3274 phases that optimize these cases need to be able to move insns into
3275 one-instruction delay slots. However, some insns may generate more than one
3276 machine instruction. These insns cannot be placed into a delay slot.
3278 Often you can rewrite the single insn as a list of individual insns,
3279 each corresponding to one machine instruction. The disadvantage of
3280 doing so is that it will cause the compilation to be slower and require
3281 more space. If the resulting insns are too complex, it may also
3282 suppress some optimizations. The compiler splits the insn if there is a
3283 reason to believe that it might improve instruction or delay slot
3286 The insn combiner phase also splits putative insns. If three insns are
3287 merged into one insn with a complex expression that cannot be matched by
3288 some @code{define_insn} pattern, the combiner phase attempts to split
3289 the complex pattern into two insns that are recognized. Usually it can
3290 break the complex pattern into two patterns by splitting out some
3291 subexpression. However, in some other cases, such as performing an
3292 addition of a large constant in two insns on a RISC machine, the way to
3293 split the addition into two insns is machine-dependent.
3295 @findex define_split
3296 The @code{define_split} definition tells the compiler how to split a
3297 complex insn into several simpler insns. It looks like this:
3301 [@var{insn-pattern}]
3303 [@var{new-insn-pattern-1}
3304 @var{new-insn-pattern-2}
3306 "@var{preparation statements}")
3309 @var{insn-pattern} is a pattern that needs to be split and
3310 @var{condition} is the final condition to be tested, as in a
3311 @code{define_insn}. When an insn matching @var{insn-pattern} and
3312 satisfying @var{condition} is found, it is replaced in the insn list
3313 with the insns given by @var{new-insn-pattern-1},
3314 @var{new-insn-pattern-2}, etc.
3316 The @var{preparation statements} are similar to those statements that
3317 are specified for @code{define_expand} (@pxref{Expander Definitions})
3318 and are executed before the new RTL is generated to prepare for the
3319 generated code or emit some insns whose pattern is not fixed. Unlike
3320 those in @code{define_expand}, however, these statements must not
3321 generate any new pseudo-registers. Once reload has completed, they also
3322 must not allocate any space in the stack frame.
3324 Patterns are matched against @var{insn-pattern} in two different
3325 circumstances. If an insn needs to be split for delay slot scheduling
3326 or insn scheduling, the insn is already known to be valid, which means
3327 that it must have been matched by some @code{define_insn} and, if
3328 @code{reload_completed} is non-zero, is known to satisfy the constraints
3329 of that @code{define_insn}. In that case, the new insn patterns must
3330 also be insns that are matched by some @code{define_insn} and, if
3331 @code{reload_completed} is non-zero, must also satisfy the constraints
3332 of those definitions.
3334 As an example of this usage of @code{define_split}, consider the following
3335 example from @file{a29k.md}, which splits a @code{sign_extend} from
3336 @code{HImode} to @code{SImode} into a pair of shift insns:
3340 [(set (match_operand:SI 0 "gen_reg_operand" "")
3341 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
3344 (ashift:SI (match_dup 1)
3347 (ashiftrt:SI (match_dup 0)
3350 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
3353 When the combiner phase tries to split an insn pattern, it is always the
3354 case that the pattern is @emph{not} matched by any @code{define_insn}.
3355 The combiner pass first tries to split a single @code{set} expression
3356 and then the same @code{set} expression inside a @code{parallel}, but
3357 followed by a @code{clobber} of a pseudo-reg to use as a scratch
3358 register. In these cases, the combiner expects exactly two new insn
3359 patterns to be generated. It will verify that these patterns match some
3360 @code{define_insn} definitions, so you need not do this test in the
3361 @code{define_split} (of course, there is no point in writing a
3362 @code{define_split} that will never produce insns that match).
3364 Here is an example of this use of @code{define_split}, taken from
3369 [(set (match_operand:SI 0 "gen_reg_operand" "")
3370 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
3371 (match_operand:SI 2 "non_add_cint_operand" "")))]
3373 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
3374 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
3377 int low = INTVAL (operands[2]) & 0xffff;
3378 int high = (unsigned) INTVAL (operands[2]) >> 16;
3381 high++, low |= 0xffff0000;
3383 operands[3] = GEN_INT (high << 16);
3384 operands[4] = GEN_INT (low);
3388 Here the predicate @code{non_add_cint_operand} matches any
3389 @code{const_int} that is @emph{not} a valid operand of a single add
3390 insn. The add with the smaller displacement is written so that it
3391 can be substituted into the address of a subsequent operation.
3393 An example that uses a scratch register, from the same file, generates
3394 an equality comparison of a register and a large constant:
3398 [(set (match_operand:CC 0 "cc_reg_operand" "")
3399 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3400 (match_operand:SI 2 "non_short_cint_operand" "")))
3401 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
3402 "find_single_use (operands[0], insn, 0)
3403 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3404 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3405 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3406 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3409 /* Get the constant we are comparing against, C, and see what it
3410 looks like sign-extended to 16 bits. Then see what constant
3411 could be XOR'ed with C to get the sign-extended value. */
3413 int c = INTVAL (operands[2]);
3414 int sextc = (c << 16) >> 16;
3415 int xorv = c ^ sextc;
3417 operands[4] = GEN_INT (xorv);
3418 operands[5] = GEN_INT (sextc);
3422 To avoid confusion, don't write a single @code{define_split} that
3423 accepts some insns that match some @code{define_insn} as well as some
3424 insns that don't. Instead, write two separate @code{define_split}
3425 definitions, one for the insns that are valid and one for the insns that
3428 For the common case where the pattern of a define_split exactly matches the
3429 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
3433 (define_insn_and_split
3434 [@var{insn-pattern}]
3436 "@var{output-template}"
3437 "@var{split-condition}"
3438 [@var{new-insn-pattern-1}
3439 @var{new-insn-pattern-2}
3441 "@var{preparation statements}"
3442 [@var{insn-attributes}])
3446 @var{insn-pattern}, @var{condition}, @var{output-template}, and
3447 @var{insn-attributes} are used as in @code{define_insn}. The
3448 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
3449 in a @code{define_split}. The @var{split-condition} is also used as in
3450 @code{define_split}, with the additional behavior that if the condition starts
3451 with @samp{&&}, the condition used for the split will be the constructed as a
3452 logical "and" of the split condition with the insn condition. For example,
3456 (define_insn_and_split "zero_extendhisi2_and"
3457 [(set (match_operand:SI 0 "register_operand" "=r")
3458 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3459 (clobber (reg:CC 17))]
3460 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3462 "&& reload_completed"
3463 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3464 (clobber (reg:CC 17))])]
3466 [(set_attr "type" "alu1")])
3470 In this case, the actual split condition will be
3471 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed."
3473 The @code{define_insn_and_split} construction provides exactly the same
3474 functionality as two separate @code{define_insn} and @code{define_split}
3475 patterns. It exists for compactness, and as a maintenance tool to prevent
3476 having to ensure the two patterns' templates match.
3478 @node Peephole Definitions
3479 @section Machine-Specific Peephole Optimizers
3480 @cindex peephole optimizer definitions
3481 @cindex defining peephole optimizers
3483 In addition to instruction patterns the @file{md} file may contain
3484 definitions of machine-specific peephole optimizations.
3486 The combiner does not notice certain peephole optimizations when the data
3487 flow in the program does not suggest that it should try them. For example,
3488 sometimes two consecutive insns related in purpose can be combined even
3489 though the second one does not appear to use a register computed in the
3490 first one. A machine-specific peephole optimizer can detect such
3493 There are two forms of peephole definitions that may be used. The
3494 original @code{define_peephole} is run at assembly output time to
3495 match insns and substitute assembly text. Use of @code{define_peephole}
3498 A newer @code{define_peephole2} matches insns and substitutes new
3499 insns. The @code{peephole2} pass is run after register allocation
3500 but before scheduling, which may result in much better code for
3501 targets that do scheduling.
3504 * define_peephole:: RTL to Text Peephole Optimizers
3505 * define_peephole2:: RTL to RTL Peephole Optimizers
3508 @node define_peephole
3509 @subsection RTL to Text Peephole Optimizers
3510 @findex define_peephole
3513 A definition looks like this:
3517 [@var{insn-pattern-1}
3518 @var{insn-pattern-2}
3522 "@var{optional insn-attributes}")
3526 The last string operand may be omitted if you are not using any
3527 machine-specific information in this machine description. If present,
3528 it must obey the same rules as in a @code{define_insn}.
3530 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
3531 consecutive insns. The optimization applies to a sequence of insns when
3532 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
3533 the next, and so on.@refill
3535 Each of the insns matched by a peephole must also match a
3536 @code{define_insn}. Peepholes are checked only at the last stage just
3537 before code generation, and only optionally. Therefore, any insn which
3538 would match a peephole but no @code{define_insn} will cause a crash in code
3539 generation in an unoptimized compilation, or at various optimization
3542 The operands of the insns are matched with @code{match_operands},
3543 @code{match_operator}, and @code{match_dup}, as usual. What is not
3544 usual is that the operand numbers apply to all the insn patterns in the
3545 definition. So, you can check for identical operands in two insns by
3546 using @code{match_operand} in one insn and @code{match_dup} in the
3549 The operand constraints used in @code{match_operand} patterns do not have
3550 any direct effect on the applicability of the peephole, but they will
3551 be validated afterward, so make sure your constraints are general enough
3552 to apply whenever the peephole matches. If the peephole matches
3553 but the constraints are not satisfied, the compiler will crash.
3555 It is safe to omit constraints in all the operands of the peephole; or
3556 you can write constraints which serve as a double-check on the criteria
3559 Once a sequence of insns matches the patterns, the @var{condition} is
3560 checked. This is a C expression which makes the final decision whether to
3561 perform the optimization (we do so if the expression is nonzero). If
3562 @var{condition} is omitted (in other words, the string is empty) then the
3563 optimization is applied to every sequence of insns that matches the
3566 The defined peephole optimizations are applied after register allocation
3567 is complete. Therefore, the peephole definition can check which
3568 operands have ended up in which kinds of registers, just by looking at
3571 @findex prev_active_insn
3572 The way to refer to the operands in @var{condition} is to write
3573 @code{operands[@var{i}]} for operand number @var{i} (as matched by
3574 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
3575 to refer to the last of the insns being matched; use
3576 @code{prev_active_insn} to find the preceding insns.
3578 @findex dead_or_set_p
3579 When optimizing computations with intermediate results, you can use
3580 @var{condition} to match only when the intermediate results are not used
3581 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
3582 @var{op})}, where @var{insn} is the insn in which you expect the value
3583 to be used for the last time (from the value of @code{insn}, together
3584 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
3585 value (from @code{operands[@var{i}]}).@refill
3587 Applying the optimization means replacing the sequence of insns with one
3588 new insn. The @var{template} controls ultimate output of assembler code
3589 for this combined insn. It works exactly like the template of a
3590 @code{define_insn}. Operand numbers in this template are the same ones
3591 used in matching the original sequence of insns.
3593 The result of a defined peephole optimizer does not need to match any of
3594 the insn patterns in the machine description; it does not even have an
3595 opportunity to match them. The peephole optimizer definition itself serves
3596 as the insn pattern to control how the insn is output.
3598 Defined peephole optimizers are run as assembler code is being output,
3599 so the insns they produce are never combined or rearranged in any way.
3601 Here is an example, taken from the 68000 machine description:
3605 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
3606 (set (match_operand:DF 0 "register_operand" "=f")
3607 (match_operand:DF 1 "register_operand" "ad"))]
3608 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
3612 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
3614 output_asm_insn (\"move.l %1,(sp)\", xoperands);
3615 output_asm_insn (\"move.l %1,-(sp)\", operands);
3616 return \"fmove.d (sp)+,%0\";
3618 output_asm_insn (\"movel %1,sp@@\", xoperands);
3619 output_asm_insn (\"movel %1,sp@@-\", operands);
3620 return \"fmoved sp@@+,%0\";
3627 The effect of this optimization is to change
3653 If a peephole matches a sequence including one or more jump insns, you must
3654 take account of the flags such as @code{CC_REVERSED} which specify that the
3655 condition codes are represented in an unusual manner. The compiler
3656 automatically alters any ordinary conditional jumps which occur in such
3657 situations, but the compiler cannot alter jumps which have been replaced by
3658 peephole optimizations. So it is up to you to alter the assembler code
3659 that the peephole produces. Supply C code to write the assembler output,
3660 and in this C code check the condition code status flags and change the
3661 assembler code as appropriate.
3664 @var{insn-pattern-1} and so on look @emph{almost} like the second
3665 operand of @code{define_insn}. There is one important difference: the
3666 second operand of @code{define_insn} consists of one or more RTX's
3667 enclosed in square brackets. Usually, there is only one: then the same
3668 action can be written as an element of a @code{define_peephole}. But
3669 when there are multiple actions in a @code{define_insn}, they are
3670 implicitly enclosed in a @code{parallel}. Then you must explicitly
3671 write the @code{parallel}, and the square brackets within it, in the
3672 @code{define_peephole}. Thus, if an insn pattern looks like this,
3675 (define_insn "divmodsi4"
3676 [(set (match_operand:SI 0 "general_operand" "=d")
3677 (div:SI (match_operand:SI 1 "general_operand" "0")
3678 (match_operand:SI 2 "general_operand" "dmsK")))
3679 (set (match_operand:SI 3 "general_operand" "=d")
3680 (mod:SI (match_dup 1) (match_dup 2)))]
3682 "divsl%.l %2,%3:%0")
3686 then the way to mention this insn in a peephole is as follows:
3692 [(set (match_operand:SI 0 "general_operand" "=d")
3693 (div:SI (match_operand:SI 1 "general_operand" "0")
3694 (match_operand:SI 2 "general_operand" "dmsK")))
3695 (set (match_operand:SI 3 "general_operand" "=d")
3696 (mod:SI (match_dup 1) (match_dup 2)))])
3701 @node define_peephole2
3702 @subsection RTL to RTL Peephole Optimizers
3703 @findex define_peephole2
3705 The @code{define_peephole2} definition tells the compiler how to
3706 substitute one sequence of instructions for another sequence,
3707 what additional scratch registers may be needed and what their
3712 [@var{insn-pattern-1}
3713 @var{insn-pattern-2}
3716 [@var{new-insn-pattern-1}
3717 @var{new-insn-pattern-2}
3719 "@var{preparation statements}")
3722 The definition is almost identical to @code{define_split}
3723 (@pxref{Insn Splitting}) except that the pattern to match is not a
3724 single instruction, but a sequence of instructions.
3726 It is possible to request additional scratch registers for use in the
3727 output template. If appropriate registers are not free, the pattern
3728 will simply not match.
3730 @findex match_scratch
3732 Scratch registers are requested with a @code{match_scratch} pattern at
3733 the top level of the input pattern. The allocated register (initially) will
3734 be dead at the point requested within the original sequence. If the scratch
3735 is used at more than a single point, a @code{match_dup} pattern at the
3736 top level of the input pattern marks the last position in the input sequence
3737 at which the register must be available.
3739 Here is an example from the IA-32 machine description:
3743 [(match_scratch:SI 2 "r")
3744 (parallel [(set (match_operand:SI 0 "register_operand" "")
3745 (match_operator:SI 3 "arith_or_logical_operator"
3747 (match_operand:SI 1 "memory_operand" "")]))
3748 (clobber (reg:CC 17))])]
3749 "! optimize_size && ! TARGET_READ_MODIFY"
3750 [(set (match_dup 2) (match_dup 1))
3751 (parallel [(set (match_dup 0)
3752 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
3753 (clobber (reg:CC 17))])]
3758 This pattern tries to split a load from its use in the hopes that we'll be
3759 able to schedule around the memory load latency. It allocates a single
3760 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
3761 to be live only at the point just before the arithmetic.
3763 A real example requiring extended scratch lifetimes is harder to come by,
3764 so here's a silly made-up example:
3768 [(match_scratch:SI 4 "r")
3769 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
3770 (set (match_operand:SI 2 "" "") (match_dup 1))
3772 (set (match_operand:SI 3 "" "") (match_dup 1))]
3773 "@var{determine 1 does not overlap 0 and 2}"
3774 [(set (match_dup 4) (match_dup 1))
3775 (set (match_dup 0) (match_dup 4))
3776 (set (match_dup 2) (match_dup 4))]
3777 (set (match_dup 3) (match_dup 4))]
3782 If we had not added the @code{(match_dup 4)} in the middle of the input
3783 sequence, it might have been the case that the register we chose at the
3784 beginning of the sequence is killed by the first or second @code{set}.
3786 @node Insn Attributes
3787 @section Instruction Attributes
3788 @cindex insn attributes
3789 @cindex instruction attributes
3791 In addition to describing the instruction supported by the target machine,
3792 the @file{md} file also defines a group of @dfn{attributes} and a set of
3793 values for each. Every generated insn is assigned a value for each attribute.
3794 One possible attribute would be the effect that the insn has on the machine's
3795 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
3796 to track the condition codes.
3799 * Defining Attributes:: Specifying attributes and their values.
3800 * Expressions:: Valid expressions for attribute values.
3801 * Tagging Insns:: Assigning attribute values to insns.
3802 * Attr Example:: An example of assigning attributes.
3803 * Insn Lengths:: Computing the length of insns.
3804 * Constant Attributes:: Defining attributes that are constant.
3805 * Delay Slots:: Defining delay slots required for a machine.
3806 * Function Units:: Specifying information for insn scheduling.
3809 @node Defining Attributes
3810 @subsection Defining Attributes and their Values
3811 @cindex defining attributes and their values
3812 @cindex attributes, defining
3815 The @code{define_attr} expression is used to define each attribute required
3816 by the target machine. It looks like:
3819 (define_attr @var{name} @var{list-of-values} @var{default})
3822 @var{name} is a string specifying the name of the attribute being defined.
3824 @var{list-of-values} is either a string that specifies a comma-separated
3825 list of values that can be assigned to the attribute, or a null string to
3826 indicate that the attribute takes numeric values.
3828 @var{default} is an attribute expression that gives the value of this
3829 attribute for insns that match patterns whose definition does not include
3830 an explicit value for this attribute. @xref{Attr Example}, for more
3831 information on the handling of defaults. @xref{Constant Attributes},
3832 for information on attributes that do not depend on any particular insn.
3835 For each defined attribute, a number of definitions are written to the
3836 @file{insn-attr.h} file. For cases where an explicit set of values is
3837 specified for an attribute, the following are defined:
3841 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
3844 An enumeral class is defined for @samp{attr_@var{name}} with
3845 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
3846 the attribute name and value are first converted to upper case.
3849 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
3850 returns the attribute value for that insn.
3853 For example, if the following is present in the @file{md} file:
3856 (define_attr "type" "branch,fp,load,store,arith" @dots{})
3860 the following lines will be written to the file @file{insn-attr.h}.
3863 #define HAVE_ATTR_type
3864 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
3865 TYPE_STORE, TYPE_ARITH@};
3866 extern enum attr_type get_attr_type ();
3869 If the attribute takes numeric values, no @code{enum} type will be
3870 defined and the function to obtain the attribute's value will return
3874 @subsection Attribute Expressions
3875 @cindex attribute expressions
3877 RTL expressions used to define attributes use the codes described above
3878 plus a few specific to attribute definitions, to be discussed below.
3879 Attribute value expressions must have one of the following forms:
3882 @cindex @code{const_int} and attributes
3883 @item (const_int @var{i})
3884 The integer @var{i} specifies the value of a numeric attribute. @var{i}
3885 must be non-negative.
3887 The value of a numeric attribute can be specified either with a
3888 @code{const_int}, or as an integer represented as a string in
3889 @code{const_string}, @code{eq_attr} (see below), @code{attr},
3890 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
3891 overrides on specific instructions (@pxref{Tagging Insns}).
3893 @cindex @code{const_string} and attributes
3894 @item (const_string @var{value})
3895 The string @var{value} specifies a constant attribute value.
3896 If @var{value} is specified as @samp{"*"}, it means that the default value of
3897 the attribute is to be used for the insn containing this expression.
3898 @samp{"*"} obviously cannot be used in the @var{default} expression
3899 of a @code{define_attr}.@refill
3901 If the attribute whose value is being specified is numeric, @var{value}
3902 must be a string containing a non-negative integer (normally
3903 @code{const_int} would be used in this case). Otherwise, it must
3904 contain one of the valid values for the attribute.
3906 @cindex @code{if_then_else} and attributes
3907 @item (if_then_else @var{test} @var{true-value} @var{false-value})
3908 @var{test} specifies an attribute test, whose format is defined below.
3909 The value of this expression is @var{true-value} if @var{test} is true,
3910 otherwise it is @var{false-value}.
3912 @cindex @code{cond} and attributes
3913 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
3914 The first operand of this expression is a vector containing an even
3915 number of expressions and consisting of pairs of @var{test} and @var{value}
3916 expressions. The value of the @code{cond} expression is that of the
3917 @var{value} corresponding to the first true @var{test} expression. If
3918 none of the @var{test} expressions are true, the value of the @code{cond}
3919 expression is that of the @var{default} expression.
3922 @var{test} expressions can have one of the following forms:
3925 @cindex @code{const_int} and attribute tests
3926 @item (const_int @var{i})
3927 This test is true if @var{i} is non-zero and false otherwise.
3929 @cindex @code{not} and attributes
3930 @cindex @code{ior} and attributes
3931 @cindex @code{and} and attributes
3932 @item (not @var{test})
3933 @itemx (ior @var{test1} @var{test2})
3934 @itemx (and @var{test1} @var{test2})
3935 These tests are true if the indicated logical function is true.
3937 @cindex @code{match_operand} and attributes
3938 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
3939 This test is true if operand @var{n} of the insn whose attribute value
3940 is being determined has mode @var{m} (this part of the test is ignored
3941 if @var{m} is @code{VOIDmode}) and the function specified by the string
3942 @var{pred} returns a non-zero value when passed operand @var{n} and mode
3943 @var{m} (this part of the test is ignored if @var{pred} is the null
3946 The @var{constraints} operand is ignored and should be the null string.
3948 @cindex @code{le} and attributes
3949 @cindex @code{leu} and attributes
3950 @cindex @code{lt} and attributes
3951 @cindex @code{gt} and attributes
3952 @cindex @code{gtu} and attributes
3953 @cindex @code{ge} and attributes
3954 @cindex @code{geu} and attributes
3955 @cindex @code{ne} and attributes
3956 @cindex @code{eq} and attributes
3957 @cindex @code{plus} and attributes
3958 @cindex @code{minus} and attributes
3959 @cindex @code{mult} and attributes
3960 @cindex @code{div} and attributes
3961 @cindex @code{mod} and attributes
3962 @cindex @code{abs} and attributes
3963 @cindex @code{neg} and attributes
3964 @cindex @code{ashift} and attributes
3965 @cindex @code{lshiftrt} and attributes
3966 @cindex @code{ashiftrt} and attributes
3967 @item (le @var{arith1} @var{arith2})
3968 @itemx (leu @var{arith1} @var{arith2})
3969 @itemx (lt @var{arith1} @var{arith2})
3970 @itemx (ltu @var{arith1} @var{arith2})
3971 @itemx (gt @var{arith1} @var{arith2})
3972 @itemx (gtu @var{arith1} @var{arith2})
3973 @itemx (ge @var{arith1} @var{arith2})
3974 @itemx (geu @var{arith1} @var{arith2})
3975 @itemx (ne @var{arith1} @var{arith2})
3976 @itemx (eq @var{arith1} @var{arith2})
3977 These tests are true if the indicated comparison of the two arithmetic
3978 expressions is true. Arithmetic expressions are formed with
3979 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
3980 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
3981 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.@refill
3984 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
3985 Lengths},for additional forms). @code{symbol_ref} is a string
3986 denoting a C expression that yields an @code{int} when evaluated by the
3987 @samp{get_attr_@dots{}} routine. It should normally be a global
3991 @item (eq_attr @var{name} @var{value})
3992 @var{name} is a string specifying the name of an attribute.
3994 @var{value} is a string that is either a valid value for attribute
3995 @var{name}, a comma-separated list of values, or @samp{!} followed by a
3996 value or list. If @var{value} does not begin with a @samp{!}, this
3997 test is true if the value of the @var{name} attribute of the current
3998 insn is in the list specified by @var{value}. If @var{value} begins
3999 with a @samp{!}, this test is true if the attribute's value is
4000 @emph{not} in the specified list.
4005 (eq_attr "type" "load,store")
4012 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
4015 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
4016 value of the compiler variable @code{which_alternative}
4017 (@pxref{Output Statement}) and the values must be small integers. For
4021 (eq_attr "alternative" "2,3")
4028 (ior (eq (symbol_ref "which_alternative") (const_int 2))
4029 (eq (symbol_ref "which_alternative") (const_int 3)))
4032 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
4033 where the value of the attribute being tested is known for all insns matching
4034 a particular pattern. This is by far the most common case.@refill
4037 @item (attr_flag @var{name})
4038 The value of an @code{attr_flag} expression is true if the flag
4039 specified by @var{name} is true for the @code{insn} currently being
4042 @var{name} is a string specifying one of a fixed set of flags to test.
4043 Test the flags @code{forward} and @code{backward} to determine the
4044 direction of a conditional branch. Test the flags @code{very_likely},
4045 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
4046 if a conditional branch is expected to be taken.
4048 If the @code{very_likely} flag is true, then the @code{likely} flag is also
4049 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
4051 This example describes a conditional branch delay slot which
4052 can be nullified for forward branches that are taken (annul-true) or
4053 for backward branches which are not taken (annul-false).
4056 (define_delay (eq_attr "type" "cbranch")
4057 [(eq_attr "in_branch_delay" "true")
4058 (and (eq_attr "in_branch_delay" "true")
4059 (attr_flag "forward"))
4060 (and (eq_attr "in_branch_delay" "true")
4061 (attr_flag "backward"))])
4064 The @code{forward} and @code{backward} flags are false if the current
4065 @code{insn} being scheduled is not a conditional branch.
4067 The @code{very_likely} and @code{likely} flags are true if the
4068 @code{insn} being scheduled is not a conditional branch.
4069 The @code{very_unlikely} and @code{unlikely} flags are false if the
4070 @code{insn} being scheduled is not a conditional branch.
4072 @code{attr_flag} is only used during delay slot scheduling and has no
4073 meaning to other passes of the compiler.
4076 @item (attr @var{name})
4077 The value of another attribute is returned. This is most useful
4078 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
4079 produce more efficient code for non-numeric attributes.
4083 @subsection Assigning Attribute Values to Insns
4084 @cindex tagging insns
4085 @cindex assigning attribute values to insns
4087 The value assigned to an attribute of an insn is primarily determined by
4088 which pattern is matched by that insn (or which @code{define_peephole}
4089 generated it). Every @code{define_insn} and @code{define_peephole} can
4090 have an optional last argument to specify the values of attributes for
4091 matching insns. The value of any attribute not specified in a particular
4092 insn is set to the default value for that attribute, as specified in its
4093 @code{define_attr}. Extensive use of default values for attributes
4094 permits the specification of the values for only one or two attributes
4095 in the definition of most insn patterns, as seen in the example in the
4096 next section.@refill
4098 The optional last argument of @code{define_insn} and
4099 @code{define_peephole} is a vector of expressions, each of which defines
4100 the value for a single attribute. The most general way of assigning an
4101 attribute's value is to use a @code{set} expression whose first operand is an
4102 @code{attr} expression giving the name of the attribute being set. The
4103 second operand of the @code{set} is an attribute expression
4104 (@pxref{Expressions}) giving the value of the attribute.@refill
4106 When the attribute value depends on the @samp{alternative} attribute
4107 (i.e., which is the applicable alternative in the constraint of the
4108 insn), the @code{set_attr_alternative} expression can be used. It
4109 allows the specification of a vector of attribute expressions, one for
4113 When the generality of arbitrary attribute expressions is not required,
4114 the simpler @code{set_attr} expression can be used, which allows
4115 specifying a string giving either a single attribute value or a list
4116 of attribute values, one for each alternative.
4118 The form of each of the above specifications is shown below. In each case,
4119 @var{name} is a string specifying the attribute to be set.
4122 @item (set_attr @var{name} @var{value-string})
4123 @var{value-string} is either a string giving the desired attribute value,
4124 or a string containing a comma-separated list giving the values for
4125 succeeding alternatives. The number of elements must match the number
4126 of alternatives in the constraint of the insn pattern.
4128 Note that it may be useful to specify @samp{*} for some alternative, in
4129 which case the attribute will assume its default value for insns matching
4132 @findex set_attr_alternative
4133 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
4134 Depending on the alternative of the insn, the value will be one of the
4135 specified values. This is a shorthand for using a @code{cond} with
4136 tests on the @samp{alternative} attribute.
4139 @item (set (attr @var{name}) @var{value})
4140 The first operand of this @code{set} must be the special RTL expression
4141 @code{attr}, whose sole operand is a string giving the name of the
4142 attribute being set. @var{value} is the value of the attribute.
4145 The following shows three different ways of representing the same
4146 attribute value specification:
4149 (set_attr "type" "load,store,arith")
4151 (set_attr_alternative "type"
4152 [(const_string "load") (const_string "store")
4153 (const_string "arith")])
4156 (cond [(eq_attr "alternative" "1") (const_string "load")
4157 (eq_attr "alternative" "2") (const_string "store")]
4158 (const_string "arith")))
4162 @findex define_asm_attributes
4163 The @code{define_asm_attributes} expression provides a mechanism to
4164 specify the attributes assigned to insns produced from an @code{asm}
4165 statement. It has the form:
4168 (define_asm_attributes [@var{attr-sets}])
4172 where @var{attr-sets} is specified the same as for both the
4173 @code{define_insn} and the @code{define_peephole} expressions.
4175 These values will typically be the ``worst case'' attribute values. For
4176 example, they might indicate that the condition code will be clobbered.
4178 A specification for a @code{length} attribute is handled specially. The
4179 way to compute the length of an @code{asm} insn is to multiply the
4180 length specified in the expression @code{define_asm_attributes} by the
4181 number of machine instructions specified in the @code{asm} statement,
4182 determined by counting the number of semicolons and newlines in the
4183 string. Therefore, the value of the @code{length} attribute specified
4184 in a @code{define_asm_attributes} should be the maximum possible length
4185 of a single machine instruction.
4188 @subsection Example of Attribute Specifications
4189 @cindex attribute specifications example
4190 @cindex attribute specifications
4192 The judicious use of defaulting is important in the efficient use of
4193 insn attributes. Typically, insns are divided into @dfn{types} and an
4194 attribute, customarily called @code{type}, is used to represent this
4195 value. This attribute is normally used only to define the default value
4196 for other attributes. An example will clarify this usage.
4198 Assume we have a RISC machine with a condition code and in which only
4199 full-word operations are performed in registers. Let us assume that we
4200 can divide all insns into loads, stores, (integer) arithmetic
4201 operations, floating point operations, and branches.
4203 Here we will concern ourselves with determining the effect of an insn on
4204 the condition code and will limit ourselves to the following possible
4205 effects: The condition code can be set unpredictably (clobbered), not
4206 be changed, be set to agree with the results of the operation, or only
4207 changed if the item previously set into the condition code has been
4210 Here is part of a sample @file{md} file for such a machine:
4213 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
4215 (define_attr "cc" "clobber,unchanged,set,change0"
4216 (cond [(eq_attr "type" "load")
4217 (const_string "change0")
4218 (eq_attr "type" "store,branch")
4219 (const_string "unchanged")
4220 (eq_attr "type" "arith")
4221 (if_then_else (match_operand:SI 0 "" "")
4222 (const_string "set")
4223 (const_string "clobber"))]
4224 (const_string "clobber")))
4227 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
4228 (match_operand:SI 1 "general_operand" "r,m,r"))]
4234 [(set_attr "type" "arith,load,store")])
4237 Note that we assume in the above example that arithmetic operations
4238 performed on quantities smaller than a machine word clobber the condition
4239 code since they will set the condition code to a value corresponding to the
4243 @subsection Computing the Length of an Insn
4244 @cindex insn lengths, computing
4245 @cindex computing the length of an insn
4247 For many machines, multiple types of branch instructions are provided, each
4248 for different length branch displacements. In most cases, the assembler
4249 will choose the correct instruction to use. However, when the assembler
4250 cannot do so, GCC can when a special attribute, the @samp{length}
4251 attribute, is defined. This attribute must be defined to have numeric
4252 values by specifying a null string in its @code{define_attr}.
4254 In the case of the @samp{length} attribute, two additional forms of
4255 arithmetic terms are allowed in test expressions:
4258 @cindex @code{match_dup} and attributes
4259 @item (match_dup @var{n})
4260 This refers to the address of operand @var{n} of the current insn, which
4261 must be a @code{label_ref}.
4263 @cindex @code{pc} and attributes
4265 This refers to the address of the @emph{current} insn. It might have
4266 been more consistent with other usage to make this the address of the
4267 @emph{next} insn but this would be confusing because the length of the
4268 current insn is to be computed.
4271 @cindex @code{addr_vec}, length of
4272 @cindex @code{addr_diff_vec}, length of
4273 For normal insns, the length will be determined by value of the
4274 @samp{length} attribute. In the case of @code{addr_vec} and
4275 @code{addr_diff_vec} insn patterns, the length is computed as
4276 the number of vectors multiplied by the size of each vector.
4278 Lengths are measured in addressable storage units (bytes).
4280 The following macros can be used to refine the length computation:
4283 @findex FIRST_INSN_ADDRESS
4284 @item FIRST_INSN_ADDRESS
4285 When the @code{length} insn attribute is used, this macro specifies the
4286 value to be assigned to the address of the first insn in a function. If
4287 not specified, 0 is used.
4289 @findex ADJUST_INSN_LENGTH
4290 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
4291 If defined, modifies the length assigned to instruction @var{insn} as a
4292 function of the context in which it is used. @var{length} is an lvalue
4293 that contains the initially computed length of the insn and should be
4294 updated with the correct length of the insn.
4296 This macro will normally not be required. A case in which it is
4297 required is the ROMP. On this machine, the size of an @code{addr_vec}
4298 insn must be increased by two to compensate for the fact that alignment
4302 @findex get_attr_length
4303 The routine that returns @code{get_attr_length} (the value of the
4304 @code{length} attribute) can be used by the output routine to
4305 determine the form of the branch instruction to be written, as the
4306 example below illustrates.
4308 As an example of the specification of variable-length branches, consider
4309 the IBM 360. If we adopt the convention that a register will be set to
4310 the starting address of a function, we can jump to labels within 4k of
4311 the start using a four-byte instruction. Otherwise, we need a six-byte
4312 sequence to load the address from memory and then branch to it.
4314 On such a machine, a pattern for a branch instruction might be specified
4320 (label_ref (match_operand 0 "" "")))]
4324 return (get_attr_length (insn) == 4
4325 ? \"b %l0\" : \"l r15,=a(%l0); br r15\");
4327 [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
4332 @node Constant Attributes
4333 @subsection Constant Attributes
4334 @cindex constant attributes
4336 A special form of @code{define_attr}, where the expression for the
4337 default value is a @code{const} expression, indicates an attribute that
4338 is constant for a given run of the compiler. Constant attributes may be
4339 used to specify which variety of processor is used. For example,
4342 (define_attr "cpu" "m88100,m88110,m88000"
4344 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
4345 (symbol_ref "TARGET_88110") (const_string "m88110")]
4346 (const_string "m88000"))))
4348 (define_attr "memory" "fast,slow"
4350 (if_then_else (symbol_ref "TARGET_FAST_MEM")
4351 (const_string "fast")
4352 (const_string "slow"))))
4355 The routine generated for constant attributes has no parameters as it
4356 does not depend on any particular insn. RTL expressions used to define
4357 the value of a constant attribute may use the @code{symbol_ref} form,
4358 but may not use either the @code{match_operand} form or @code{eq_attr}
4359 forms involving insn attributes.
4362 @subsection Delay Slot Scheduling
4363 @cindex delay slots, defining
4365 The insn attribute mechanism can be used to specify the requirements for
4366 delay slots, if any, on a target machine. An instruction is said to
4367 require a @dfn{delay slot} if some instructions that are physically
4368 after the instruction are executed as if they were located before it.
4369 Classic examples are branch and call instructions, which often execute
4370 the following instruction before the branch or call is performed.
4372 On some machines, conditional branch instructions can optionally
4373 @dfn{annul} instructions in the delay slot. This means that the
4374 instruction will not be executed for certain branch outcomes. Both
4375 instructions that annul if the branch is true and instructions that
4376 annul if the branch is false are supported.
4378 Delay slot scheduling differs from instruction scheduling in that
4379 determining whether an instruction needs a delay slot is dependent only
4380 on the type of instruction being generated, not on data flow between the
4381 instructions. See the next section for a discussion of data-dependent
4382 instruction scheduling.
4384 @findex define_delay
4385 The requirement of an insn needing one or more delay slots is indicated
4386 via the @code{define_delay} expression. It has the following form:
4389 (define_delay @var{test}
4390 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
4391 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
4395 @var{test} is an attribute test that indicates whether this
4396 @code{define_delay} applies to a particular insn. If so, the number of
4397 required delay slots is determined by the length of the vector specified
4398 as the second argument. An insn placed in delay slot @var{n} must
4399 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
4400 attribute test that specifies which insns may be annulled if the branch
4401 is true. Similarly, @var{annul-false-n} specifies which insns in the
4402 delay slot may be annulled if the branch is false. If annulling is not
4403 supported for that delay slot, @code{(nil)} should be coded.@refill
4405 For example, in the common case where branch and call insns require
4406 a single delay slot, which may contain any insn other than a branch or
4407 call, the following would be placed in the @file{md} file:
4410 (define_delay (eq_attr "type" "branch,call")
4411 [(eq_attr "type" "!branch,call") (nil) (nil)])
4414 Multiple @code{define_delay} expressions may be specified. In this
4415 case, each such expression specifies different delay slot requirements
4416 and there must be no insn for which tests in two @code{define_delay}
4417 expressions are both true.
4419 For example, if we have a machine that requires one delay slot for branches
4420 but two for calls, no delay slot can contain a branch or call insn,
4421 and any valid insn in the delay slot for the branch can be annulled if the
4422 branch is true, we might represent this as follows:
4425 (define_delay (eq_attr "type" "branch")
4426 [(eq_attr "type" "!branch,call")
4427 (eq_attr "type" "!branch,call")
4430 (define_delay (eq_attr "type" "call")
4431 [(eq_attr "type" "!branch,call") (nil) (nil)
4432 (eq_attr "type" "!branch,call") (nil) (nil)])
4434 @c the above is *still* too long. --mew 4feb93
4436 @node Function Units
4437 @subsection Specifying Function Units
4438 @cindex function units, for scheduling
4440 On most RISC machines, there are instructions whose results are not
4441 available for a specific number of cycles. Common cases are instructions
4442 that load data from memory. On many machines, a pipeline stall will result
4443 if the data is referenced too soon after the load instruction.
4445 In addition, many newer microprocessors have multiple function units, usually
4446 one for integer and one for floating point, and often will incur pipeline
4447 stalls when a result that is needed is not yet ready.
4449 The descriptions in this section allow the specification of how much
4450 time must elapse between the execution of an instruction and the time
4451 when its result is used. It also allows specification of when the
4452 execution of an instruction will delay execution of similar instructions
4453 due to function unit conflicts.
4455 For the purposes of the specifications in this section, a machine is
4456 divided into @dfn{function units}, each of which execute a specific
4457 class of instructions in first-in-first-out order. Function units that
4458 accept one instruction each cycle and allow a result to be used in the
4459 succeeding instruction (usually via forwarding) need not be specified.
4460 Classic RISC microprocessors will normally have a single function unit,
4461 which we can call @samp{memory}. The newer ``superscalar'' processors
4462 will often have function units for floating point operations, usually at
4463 least a floating point adder and multiplier.
4465 @findex define_function_unit
4466 Each usage of a function units by a class of insns is specified with a
4467 @code{define_function_unit} expression, which looks like this:
4470 (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
4471 @var{test} @var{ready-delay} @var{issue-delay}
4472 [@var{conflict-list}])
4475 @var{name} is a string giving the name of the function unit.
4477 @var{multiplicity} is an integer specifying the number of identical
4478 units in the processor. If more than one unit is specified, they will
4479 be scheduled independently. Only truly independent units should be
4480 counted; a pipelined unit should be specified as a single unit. (The
4481 only common example of a machine that has multiple function units for a
4482 single instruction class that are truly independent and not pipelined
4483 are the two multiply and two increment units of the CDC 6600.)
4485 @var{simultaneity} specifies the maximum number of insns that can be
4486 executing in each instance of the function unit simultaneously or zero
4487 if the unit is pipelined and has no limit.
4489 All @code{define_function_unit} definitions referring to function unit
4490 @var{name} must have the same name and values for @var{multiplicity} and
4493 @var{test} is an attribute test that selects the insns we are describing
4494 in this definition. Note that an insn may use more than one function
4495 unit and a function unit may be specified in more than one
4496 @code{define_function_unit}.
4498 @var{ready-delay} is an integer that specifies the number of cycles
4499 after which the result of the instruction can be used without
4500 introducing any stalls.
4502 @var{issue-delay} is an integer that specifies the number of cycles
4503 after the instruction matching the @var{test} expression begins using
4504 this unit until a subsequent instruction can begin. A cost of @var{N}
4505 indicates an @var{N-1} cycle delay. A subsequent instruction may also
4506 be delayed if an earlier instruction has a longer @var{ready-delay}
4507 value. This blocking effect is computed using the @var{simultaneity},
4508 @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms.
4509 For a normal non-pipelined function unit, @var{simultaneity} is one, the
4510 unit is taken to block for the @var{ready-delay} cycles of the executing
4511 insn, and smaller values of @var{issue-delay} are ignored.
4513 @var{conflict-list} is an optional list giving detailed conflict costs
4514 for this unit. If specified, it is a list of condition test expressions
4515 to be applied to insns chosen to execute in @var{name} following the
4516 particular insn matching @var{test} that is already executing in
4517 @var{name}. For each insn in the list, @var{issue-delay} specifies the
4518 conflict cost; for insns not in the list, the cost is zero. If not
4519 specified, @var{conflict-list} defaults to all instructions that use the
4522 Typical uses of this vector are where a floating point function unit can
4523 pipeline either single- or double-precision operations, but not both, or
4524 where a memory unit can pipeline loads, but not stores, etc.
4526 As an example, consider a classic RISC machine where the result of a
4527 load instruction is not available for two cycles (a single ``delay''
4528 instruction is required) and where only one load instruction can be executed
4529 simultaneously. This would be specified as:
4532 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
4535 For the case of a floating point function unit that can pipeline either
4536 single or double precision, but not both, the following could be specified:
4539 (define_function_unit
4540 "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
4541 (define_function_unit
4542 "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])
4545 @strong{Note:} The scheduler attempts to avoid function unit conflicts
4546 and uses all the specifications in the @code{define_function_unit}
4547 expression. It has recently come to our attention that these
4548 specifications may not allow modeling of some of the newer
4549 ``superscalar'' processors that have insns using multiple pipelined
4550 units. These insns will cause a potential conflict for the second unit
4551 used during their execution and there is no way of representing that
4552 conflict. We welcome any examples of how function unit conflicts work
4553 in such processors and suggestions for their representation.
4556 @node Conditional Execution
4557 @section Conditional Execution
4558 @cindex conditional execution
4561 A number of architectures provide for some form of conditional
4562 execution, or predication. The hallmark of this feature is the
4563 ability to nullify most of the instructions in the instruction set.
4564 When the instruction set is large and not entirely symmetric, it
4565 can be quite tedious to describe these forms directly in the
4566 @file{.md} file. An alternative is the @code{define_cond_exec} template.
4568 @findex define_cond_exec
4571 [@var{predicate-pattern}]
4573 "@var{output template}")
4576 @var{predicate-pattern} is the condition that must be true for the
4577 insn to be executed at runtime and should match a relational operator.
4578 One can use @code{match_operator} to match several relational operators
4579 at once. Any @code{match_operand} operands must have no more than one
4582 @var{condition} is a C expression that must be true for the generated
4585 @findex current_insn_predicate
4586 @var{output template} is a string similar to the @code{define_insn}
4587 output template (@pxref{Output Template}), except that the @samp{*}
4588 and @samp{@@} special cases do not apply. This is only useful if the
4589 assembly text for the predicate is a simple prefix to the main insn.
4590 In order to handle the general case, there is a global variable
4591 @code{current_insn_predicate} that will contain the entire predicate
4592 if the current insn is predicated, and will otherwise be @code{NULL}.
4594 When @code{define_cond_exec} is used, an implicit reference to
4595 the @code{predicable} instruction attribute is made.
4596 @xref{Insn Attributes}. This attribute must be boolean (i.e. have
4597 exactly two elements in its @var{list-of-values}). Further, it must
4598 not be used with complex expressions. That is, the default and all
4599 uses in the insns must be a simple constant, not dependent on the
4600 alternative or anything else.
4602 For each @code{define_insn} for which the @code{predicable}
4603 attribute is true, a new @code{define_insn} pattern will be
4604 generated that matches a predicated version of the instruction.
4608 (define_insn "addsi"
4609 [(set (match_operand:SI 0 "register_operand" "r")
4610 (plus:SI (match_operand:SI 1 "register_operand" "r")
4611 (match_operand:SI 2 "register_operand" "r")))]
4616 [(ne (match_operand:CC 0 "register_operand" "c")
4623 generates a new pattern
4628 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
4629 (set (match_operand:SI 0 "register_operand" "r")
4630 (plus:SI (match_operand:SI 1 "register_operand" "r")
4631 (match_operand:SI 2 "register_operand" "r"))))]
4632 "(@var{test2}) && (@var{test1})"
4633 "(%3) add %2,%1,%0")