1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 88, 89, 91-4, 1995 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
42 #include "insn-config.h"
43 #include "insn-flags.h"
45 #include "hard-reg-set.h"
51 /* Vector mapping INSN_UIDs to luids.
52 The luids are like uids but increase monotonically always.
53 We use them to see whether a jump comes from outside a given loop. */
57 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
58 number the insn is contained in. */
62 /* 1 + largest uid of any insn. */
66 /* 1 + luid of last insn. */
70 /* Number of loops detected in current function. Used as index to the
73 static int max_loop_num;
75 /* Indexed by loop number, contains the first and last insn of each loop. */
77 static rtx *loop_number_loop_starts, *loop_number_loop_ends;
79 /* For each loop, gives the containing loop number, -1 if none. */
83 /* Indexed by loop number, contains a nonzero value if the "loop" isn't
84 really a loop (an insn outside the loop branches into it). */
86 static char *loop_invalid;
88 /* Indexed by loop number, links together all LABEL_REFs which refer to
89 code labels outside the loop. Used by routines that need to know all
90 loop exits, such as final_biv_value and final_giv_value.
92 This does not include loop exits due to return instructions. This is
93 because all bivs and givs are pseudos, and hence must be dead after a
94 return, so the presense of a return does not affect any of the
95 optimizations that use this info. It is simpler to just not include return
96 instructions on this list. */
98 rtx *loop_number_exit_labels;
100 /* Indexed by loop number, counts the number of LABEL_REFs on
101 loop_number_exit_labels for this loop and all loops nested inside it. */
103 int *loop_number_exit_count;
105 /* Holds the number of loop iterations. It is zero if the number could not be
106 calculated. Must be unsigned since the number of iterations can
107 be as high as 2^wordsize-1. For loops with a wider iterator, this number
108 will will be zero if the number of loop iterations is too large for an
109 unsigned integer to hold. */
111 unsigned HOST_WIDE_INT loop_n_iterations;
113 /* Nonzero if there is a subroutine call in the current loop.
114 (unknown_address_altered is also nonzero in this case.) */
116 static int loop_has_call;
118 /* Nonzero if there is a volatile memory reference in the current
121 static int loop_has_volatile;
123 /* Added loop_continue which is the NOTE_INSN_LOOP_CONT of the
124 current loop. A continue statement will generate a branch to
125 NEXT_INSN (loop_continue). */
127 static rtx loop_continue;
129 /* Indexed by register number, contains the number of times the reg
130 is set during the loop being scanned.
131 During code motion, a negative value indicates a reg that has been
132 made a candidate; in particular -2 means that it is an candidate that
133 we know is equal to a constant and -1 means that it is an candidate
134 not known equal to a constant.
135 After code motion, regs moved have 0 (which is accurate now)
136 while the failed candidates have the original number of times set.
138 Therefore, at all times, == 0 indicates an invariant register;
139 < 0 a conditionally invariant one. */
141 static short *n_times_set;
143 /* Original value of n_times_set; same except that this value
144 is not set negative for a reg whose sets have been made candidates
145 and not set to 0 for a reg that is moved. */
147 static short *n_times_used;
149 /* Index by register number, 1 indicates that the register
150 cannot be moved or strength reduced. */
152 static char *may_not_optimize;
154 /* Nonzero means reg N has already been moved out of one loop.
155 This reduces the desire to move it out of another. */
157 static char *moved_once;
159 /* Array of MEMs that are stored in this loop. If there are too many to fit
160 here, we just turn on unknown_address_altered. */
162 #define NUM_STORES 20
163 static rtx loop_store_mems[NUM_STORES];
165 /* Index of first available slot in above array. */
166 static int loop_store_mems_idx;
168 /* Nonzero if we don't know what MEMs were changed in the current loop.
169 This happens if the loop contains a call (in which case `loop_has_call'
170 will also be set) or if we store into more than NUM_STORES MEMs. */
172 static int unknown_address_altered;
174 /* Count of movable (i.e. invariant) instructions discovered in the loop. */
175 static int num_movables;
177 /* Count of memory write instructions discovered in the loop. */
178 static int num_mem_sets;
180 /* Number of loops contained within the current one, including itself. */
181 static int loops_enclosed;
183 /* Bound on pseudo register number before loop optimization.
184 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
185 int max_reg_before_loop;
187 /* This obstack is used in product_cheap_p to allocate its rtl. It
188 may call gen_reg_rtx which, in turn, may reallocate regno_reg_rtx.
189 If we used the same obstack that it did, we would be deallocating
192 static struct obstack temp_obstack;
194 /* This is where the pointer to the obstack being used for RTL is stored. */
196 extern struct obstack *rtl_obstack;
198 #define obstack_chunk_alloc xmalloc
199 #define obstack_chunk_free free
201 extern char *oballoc ();
203 /* During the analysis of a loop, a chain of `struct movable's
204 is made to record all the movable insns found.
205 Then the entire chain can be scanned to decide which to move. */
209 rtx insn; /* A movable insn */
210 rtx set_src; /* The expression this reg is set from. */
211 rtx set_dest; /* The destination of this SET. */
212 rtx dependencies; /* When INSN is libcall, this is an EXPR_LIST
213 of any registers used within the LIBCALL. */
214 int consec; /* Number of consecutive following insns
215 that must be moved with this one. */
216 int regno; /* The register it sets */
217 short lifetime; /* lifetime of that register;
218 may be adjusted when matching movables
219 that load the same value are found. */
220 short savings; /* Number of insns we can move for this reg,
221 including other movables that force this
222 or match this one. */
223 unsigned int cond : 1; /* 1 if only conditionally movable */
224 unsigned int force : 1; /* 1 means MUST move this insn */
225 unsigned int global : 1; /* 1 means reg is live outside this loop */
226 /* If PARTIAL is 1, GLOBAL means something different:
227 that the reg is live outside the range from where it is set
228 to the following label. */
229 unsigned int done : 1; /* 1 inhibits further processing of this */
231 unsigned int partial : 1; /* 1 means this reg is used for zero-extending.
232 In particular, moving it does not make it
234 unsigned int move_insn : 1; /* 1 means that we call emit_move_insn to
235 load SRC, rather than copying INSN. */
236 unsigned int is_equiv : 1; /* 1 means a REG_EQUIV is present on INSN. */
237 enum machine_mode savemode; /* Nonzero means it is a mode for a low part
238 that we should avoid changing when clearing
239 the rest of the reg. */
240 struct movable *match; /* First entry for same value */
241 struct movable *forces; /* An insn that must be moved if this is */
242 struct movable *next;
245 FILE *loop_dump_stream;
247 /* Forward declarations. */
249 static void find_and_verify_loops ();
250 static void mark_loop_jump ();
251 static void prescan_loop ();
252 static int reg_in_basic_block_p ();
253 static int consec_sets_invariant_p ();
254 static rtx libcall_other_reg ();
255 static int labels_in_range_p ();
256 static void count_loop_regs_set ();
257 static void note_addr_stored ();
258 static int loop_reg_used_before_p ();
259 static void scan_loop ();
260 static void replace_call_address ();
261 static rtx skip_consec_insns ();
262 static int libcall_benefit ();
263 static void ignore_some_movables ();
264 static void force_movables ();
265 static void combine_movables ();
266 static int rtx_equal_for_loop_p ();
267 static void move_movables ();
268 static void strength_reduce ();
269 static int valid_initial_value_p ();
270 static void find_mem_givs ();
271 static void record_biv ();
272 static void check_final_value ();
273 static void record_giv ();
274 static void update_giv_derive ();
275 static int basic_induction_var ();
276 static rtx simplify_giv_expr ();
277 static int general_induction_var ();
278 static int consec_sets_giv ();
279 static int check_dbra_loop ();
280 static rtx express_from ();
281 static int combine_givs_p ();
282 static void combine_givs ();
283 static int product_cheap_p ();
284 static int maybe_eliminate_biv ();
285 static int maybe_eliminate_biv_1 ();
286 static int last_use_this_basic_block ();
287 static void record_initial ();
288 static void update_reg_last_use ();
290 /* Relative gain of eliminating various kinds of operations. */
297 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
298 copy the value of the strength reduced giv to its original register. */
304 char *free_point = (char *) oballoc (1);
305 rtx reg = gen_rtx (REG, word_mode, LAST_VIRTUAL_REGISTER + 1);
307 add_cost = rtx_cost (gen_rtx (PLUS, word_mode, reg, reg), SET);
309 /* We multiply by 2 to reconcile the difference in scale between
310 these two ways of computing costs. Otherwise the cost of a copy
311 will be far less than the cost of an add. */
315 /* Free the objects we just allocated. */
318 /* Initialize the obstack used for rtl in product_cheap_p. */
319 gcc_obstack_init (&temp_obstack);
322 /* Entry point of this file. Perform loop optimization
323 on the current function. F is the first insn of the function
324 and DUMPFILE is a stream for output of a trace of actions taken
325 (or 0 if none should be output). */
328 loop_optimize (f, dumpfile)
329 /* f is the first instruction of a chain of insns for one function */
337 loop_dump_stream = dumpfile;
339 init_recog_no_volatile ();
340 init_alias_analysis ();
342 max_reg_before_loop = max_reg_num ();
344 moved_once = (char *) alloca (max_reg_before_loop);
345 bzero (moved_once, max_reg_before_loop);
349 /* Count the number of loops. */
352 for (insn = f; insn; insn = NEXT_INSN (insn))
354 if (GET_CODE (insn) == NOTE
355 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
359 /* Don't waste time if no loops. */
360 if (max_loop_num == 0)
363 /* Get size to use for tables indexed by uids.
364 Leave some space for labels allocated by find_and_verify_loops. */
365 max_uid_for_loop = get_max_uid () + 1 + max_loop_num * 32;
367 uid_luid = (int *) alloca (max_uid_for_loop * sizeof (int));
368 uid_loop_num = (int *) alloca (max_uid_for_loop * sizeof (int));
370 bzero ((char *) uid_luid, max_uid_for_loop * sizeof (int));
371 bzero ((char *) uid_loop_num, max_uid_for_loop * sizeof (int));
373 /* Allocate tables for recording each loop. We set each entry, so they need
375 loop_number_loop_starts = (rtx *) alloca (max_loop_num * sizeof (rtx));
376 loop_number_loop_ends = (rtx *) alloca (max_loop_num * sizeof (rtx));
377 loop_outer_loop = (int *) alloca (max_loop_num * sizeof (int));
378 loop_invalid = (char *) alloca (max_loop_num * sizeof (char));
379 loop_number_exit_labels = (rtx *) alloca (max_loop_num * sizeof (rtx));
380 loop_number_exit_count = (int *) alloca (max_loop_num * sizeof (int));
382 /* Find and process each loop.
383 First, find them, and record them in order of their beginnings. */
384 find_and_verify_loops (f);
386 /* Now find all register lifetimes. This must be done after
387 find_and_verify_loops, because it might reorder the insns in the
389 reg_scan (f, max_reg_num (), 1);
391 /* See if we went too far. */
392 if (get_max_uid () > max_uid_for_loop)
395 /* Compute the mapping from uids to luids.
396 LUIDs are numbers assigned to insns, like uids,
397 except that luids increase monotonically through the code.
398 Don't assign luids to line-number NOTEs, so that the distance in luids
399 between two insns is not affected by -g. */
401 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
404 if (GET_CODE (insn) != NOTE
405 || NOTE_LINE_NUMBER (insn) <= 0)
406 uid_luid[INSN_UID (insn)] = ++i;
408 /* Give a line number note the same luid as preceding insn. */
409 uid_luid[INSN_UID (insn)] = i;
414 /* Don't leave gaps in uid_luid for insns that have been
415 deleted. It is possible that the first or last insn
416 using some register has been deleted by cross-jumping.
417 Make sure that uid_luid for that former insn's uid
418 points to the general area where that insn used to be. */
419 for (i = 0; i < max_uid_for_loop; i++)
421 uid_luid[0] = uid_luid[i];
422 if (uid_luid[0] != 0)
425 for (i = 0; i < max_uid_for_loop; i++)
426 if (uid_luid[i] == 0)
427 uid_luid[i] = uid_luid[i - 1];
429 /* Create a mapping from loops to BLOCK tree nodes. */
430 if (flag_unroll_loops && write_symbols != NO_DEBUG)
431 find_loop_tree_blocks ();
433 /* Now scan the loops, last ones first, since this means inner ones are done
434 before outer ones. */
435 for (i = max_loop_num-1; i >= 0; i--)
436 if (! loop_invalid[i] && loop_number_loop_ends[i])
437 scan_loop (loop_number_loop_starts[i], loop_number_loop_ends[i],
440 /* If debugging and unrolling loops, we must replicate the tree nodes
441 corresponding to the blocks inside the loop, so that the original one
442 to one mapping will remain. */
443 if (flag_unroll_loops && write_symbols != NO_DEBUG)
444 unroll_block_trees ();
447 /* Optimize one loop whose start is LOOP_START and end is END.
448 LOOP_START is the NOTE_INSN_LOOP_BEG and END is the matching
449 NOTE_INSN_LOOP_END. */
451 /* ??? Could also move memory writes out of loops if the destination address
452 is invariant, the source is invariant, the memory write is not volatile,
453 and if we can prove that no read inside the loop can read this address
454 before the write occurs. If there is a read of this address after the
455 write, then we can also mark the memory read as invariant. */
458 scan_loop (loop_start, end, nregs)
464 /* 1 if we are scanning insns that could be executed zero times. */
466 /* 1 if we are scanning insns that might never be executed
467 due to a subroutine call which might exit before they are reached. */
469 /* For a rotated loop that is entered near the bottom,
470 this is the label at the top. Otherwise it is zero. */
472 /* Jump insn that enters the loop, or 0 if control drops in. */
473 rtx loop_entry_jump = 0;
474 /* Place in the loop where control enters. */
476 /* Number of insns in the loop. */
481 /* The SET from an insn, if it is the only SET in the insn. */
483 /* Chain describing insns movable in current loop. */
484 struct movable *movables = 0;
485 /* Last element in `movables' -- so we can add elements at the end. */
486 struct movable *last_movable = 0;
487 /* Ratio of extra register life span we can justify
488 for saving an instruction. More if loop doesn't call subroutines
489 since in that case saving an insn makes more difference
490 and more registers are available. */
492 /* If we have calls, contains the insn in which a register was used
493 if it was used exactly once; contains const0_rtx if it was used more
495 rtx *reg_single_usage = 0;
496 /* Nonzero if we are scanning instructions in a sub-loop. */
499 n_times_set = (short *) alloca (nregs * sizeof (short));
500 n_times_used = (short *) alloca (nregs * sizeof (short));
501 may_not_optimize = (char *) alloca (nregs);
503 /* Determine whether this loop starts with a jump down to a test at
504 the end. This will occur for a small number of loops with a test
505 that is too complex to duplicate in front of the loop.
507 We search for the first insn or label in the loop, skipping NOTEs.
508 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
509 (because we might have a loop executed only once that contains a
510 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
511 (in case we have a degenerate loop).
513 Note that if we mistakenly think that a loop is entered at the top
514 when, in fact, it is entered at the exit test, the only effect will be
515 slightly poorer optimization. Making the opposite error can generate
516 incorrect code. Since very few loops now start with a jump to the
517 exit test, the code here to detect that case is very conservative. */
519 for (p = NEXT_INSN (loop_start);
521 && GET_CODE (p) != CODE_LABEL && GET_RTX_CLASS (GET_CODE (p)) != 'i'
522 && (GET_CODE (p) != NOTE
523 || (NOTE_LINE_NUMBER (p) != NOTE_INSN_LOOP_BEG
524 && NOTE_LINE_NUMBER (p) != NOTE_INSN_LOOP_END));
530 /* Set up variables describing this loop. */
531 prescan_loop (loop_start, end);
532 threshold = (loop_has_call ? 1 : 2) * (1 + n_non_fixed_regs);
534 /* If loop has a jump before the first label,
535 the true entry is the target of that jump.
536 Start scan from there.
537 But record in LOOP_TOP the place where the end-test jumps
538 back to so we can scan that after the end of the loop. */
539 if (GET_CODE (p) == JUMP_INSN)
543 /* Loop entry must be unconditional jump (and not a RETURN) */
545 && JUMP_LABEL (p) != 0
546 /* Check to see whether the jump actually
547 jumps out of the loop (meaning it's no loop).
548 This case can happen for things like
549 do {..} while (0). If this label was generated previously
550 by loop, we can't tell anything about it and have to reject
552 && INSN_UID (JUMP_LABEL (p)) < max_uid_for_loop
553 && INSN_LUID (JUMP_LABEL (p)) >= INSN_LUID (loop_start)
554 && INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (end))
556 loop_top = next_label (scan_start);
557 scan_start = JUMP_LABEL (p);
561 /* If SCAN_START was an insn created by loop, we don't know its luid
562 as required by loop_reg_used_before_p. So skip such loops. (This
563 test may never be true, but it's best to play it safe.)
565 Also, skip loops where we do not start scanning at a label. This
566 test also rejects loops starting with a JUMP_INSN that failed the
569 if (INSN_UID (scan_start) >= max_uid_for_loop
570 || GET_CODE (scan_start) != CODE_LABEL)
572 if (loop_dump_stream)
573 fprintf (loop_dump_stream, "\nLoop from %d to %d is phony.\n\n",
574 INSN_UID (loop_start), INSN_UID (end));
578 /* Count number of times each reg is set during this loop.
579 Set may_not_optimize[I] if it is not safe to move out
580 the setting of register I. If this loop has calls, set
581 reg_single_usage[I]. */
583 bzero ((char *) n_times_set, nregs * sizeof (short));
584 bzero (may_not_optimize, nregs);
588 reg_single_usage = (rtx *) alloca (nregs * sizeof (rtx));
589 bzero ((char *) reg_single_usage, nregs * sizeof (rtx));
592 count_loop_regs_set (loop_top ? loop_top : loop_start, end,
593 may_not_optimize, reg_single_usage, &insn_count, nregs);
595 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
596 may_not_optimize[i] = 1, n_times_set[i] = 1;
597 bcopy ((char *) n_times_set, (char *) n_times_used, nregs * sizeof (short));
599 if (loop_dump_stream)
601 fprintf (loop_dump_stream, "\nLoop from %d to %d: %d real insns.\n",
602 INSN_UID (loop_start), INSN_UID (end), insn_count);
604 fprintf (loop_dump_stream, "Continue at insn %d.\n",
605 INSN_UID (loop_continue));
608 /* Scan through the loop finding insns that are safe to move.
609 Set n_times_set negative for the reg being set, so that
610 this reg will be considered invariant for subsequent insns.
611 We consider whether subsequent insns use the reg
612 in deciding whether it is worth actually moving.
614 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
615 and therefore it is possible that the insns we are scanning
616 would never be executed. At such times, we must make sure
617 that it is safe to execute the insn once instead of zero times.
618 When MAYBE_NEVER is 0, all insns will be executed at least once
619 so that is not a problem. */
625 /* At end of a straight-in loop, we are done.
626 At end of a loop entered at the bottom, scan the top. */
639 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
640 && find_reg_note (p, REG_LIBCALL, NULL_RTX))
642 else if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
643 && find_reg_note (p, REG_RETVAL, NULL_RTX))
646 if (GET_CODE (p) == INSN
647 && (set = single_set (p))
648 && GET_CODE (SET_DEST (set)) == REG
649 && ! may_not_optimize[REGNO (SET_DEST (set))])
654 rtx src = SET_SRC (set);
655 rtx dependencies = 0;
657 /* Figure out what to use as a source of this insn. If a REG_EQUIV
658 note is given or if a REG_EQUAL note with a constant operand is
659 specified, use it as the source and mark that we should move
660 this insn by calling emit_move_insn rather that duplicating the
663 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
665 temp = find_reg_note (p, REG_EQUIV, NULL_RTX);
667 src = XEXP (temp, 0), move_insn = 1;
670 temp = find_reg_note (p, REG_EQUAL, NULL_RTX);
671 if (temp && CONSTANT_P (XEXP (temp, 0)))
672 src = XEXP (temp, 0), move_insn = 1;
673 if (temp && find_reg_note (p, REG_RETVAL, NULL_RTX))
675 src = XEXP (temp, 0);
676 /* A libcall block can use regs that don't appear in
677 the equivalent expression. To move the libcall,
678 we must move those regs too. */
679 dependencies = libcall_other_reg (p, src);
683 /* Don't try to optimize a register that was made
684 by loop-optimization for an inner loop.
685 We don't know its life-span, so we can't compute the benefit. */
686 if (REGNO (SET_DEST (set)) >= max_reg_before_loop)
688 /* In order to move a register, we need to have one of three cases:
689 (1) it is used only in the same basic block as the set
690 (2) it is not a user variable and it is not used in the
691 exit test (this can cause the variable to be used
692 before it is set just like a user-variable).
693 (3) the set is guaranteed to be executed once the loop starts,
694 and the reg is not used until after that. */
695 else if (! ((! maybe_never
696 && ! loop_reg_used_before_p (set, p, loop_start,
698 || (! REG_USERVAR_P (SET_DEST (set))
699 && ! REG_LOOP_TEST_P (SET_DEST (set)))
700 || reg_in_basic_block_p (p, SET_DEST (set))))
702 else if ((tem = invariant_p (src))
703 && (dependencies == 0
704 || (tem2 = invariant_p (dependencies)) != 0)
705 && (n_times_set[REGNO (SET_DEST (set))] == 1
707 = consec_sets_invariant_p (SET_DEST (set),
708 n_times_set[REGNO (SET_DEST (set))],
710 /* If the insn can cause a trap (such as divide by zero),
711 can't move it unless it's guaranteed to be executed
712 once loop is entered. Even a function call might
713 prevent the trap insn from being reached
714 (since it might exit!) */
715 && ! ((maybe_never || call_passed)
716 && may_trap_p (src)))
718 register struct movable *m;
719 register int regno = REGNO (SET_DEST (set));
721 /* A potential lossage is where we have a case where two insns
722 can be combined as long as they are both in the loop, but
723 we move one of them outside the loop. For large loops,
724 this can lose. The most common case of this is the address
725 of a function being called.
727 Therefore, if this register is marked as being used exactly
728 once if we are in a loop with calls (a "large loop"), see if
729 we can replace the usage of this register with the source
730 of this SET. If we can, delete this insn.
732 Don't do this if P has a REG_RETVAL note or if we have
733 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
735 if (reg_single_usage && reg_single_usage[regno] != 0
736 && reg_single_usage[regno] != const0_rtx
737 && regno_first_uid[regno] == INSN_UID (p)
738 && (regno_last_uid[regno]
739 == INSN_UID (reg_single_usage[regno]))
740 && n_times_set[REGNO (SET_DEST (set))] == 1
741 && ! side_effects_p (SET_SRC (set))
742 && ! find_reg_note (p, REG_RETVAL, NULL_RTX)
743 #ifdef SMALL_REGISTER_CLASSES
744 && ! (GET_CODE (SET_SRC (set)) == REG
745 && REGNO (SET_SRC (set)) < FIRST_PSEUDO_REGISTER)
747 /* This test is not redundant; SET_SRC (set) might be
748 a call-clobbered register and the life of REGNO
749 might span a call. */
750 && ! modified_between_p (SET_SRC (set), p,
751 reg_single_usage[regno])
752 && no_labels_between_p (p, reg_single_usage[regno])
753 && validate_replace_rtx (SET_DEST (set), SET_SRC (set),
754 reg_single_usage[regno]))
756 /* Replace any usage in a REG_EQUAL note. Must copy the
757 new source, so that we don't get rtx sharing between the
758 SET_SOURCE and REG_NOTES of insn p. */
759 REG_NOTES (reg_single_usage[regno])
760 = replace_rtx (REG_NOTES (reg_single_usage[regno]),
761 SET_DEST (set), copy_rtx (SET_SRC (set)));
764 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
765 NOTE_SOURCE_FILE (p) = 0;
766 n_times_set[regno] = 0;
770 m = (struct movable *) alloca (sizeof (struct movable));
774 m->dependencies = dependencies;
775 m->set_dest = SET_DEST (set);
777 m->consec = n_times_set[REGNO (SET_DEST (set))] - 1;
781 m->move_insn = move_insn;
782 m->is_equiv = (find_reg_note (p, REG_EQUIV, NULL_RTX) != 0);
783 m->savemode = VOIDmode;
785 /* Set M->cond if either invariant_p or consec_sets_invariant_p
786 returned 2 (only conditionally invariant). */
787 m->cond = ((tem | tem1 | tem2) > 1);
788 m->global = (uid_luid[regno_last_uid[regno]] > INSN_LUID (end)
789 || uid_luid[regno_first_uid[regno]] < INSN_LUID (loop_start));
791 m->lifetime = (uid_luid[regno_last_uid[regno]]
792 - uid_luid[regno_first_uid[regno]]);
793 m->savings = n_times_used[regno];
794 if (find_reg_note (p, REG_RETVAL, NULL_RTX))
795 m->savings += libcall_benefit (p);
796 n_times_set[regno] = move_insn ? -2 : -1;
797 /* Add M to the end of the chain MOVABLES. */
801 last_movable->next = m;
806 /* Skip this insn, not checking REG_LIBCALL notes. */
807 p = next_nonnote_insn (p);
808 /* Skip the consecutive insns, if there are any. */
809 p = skip_consec_insns (p, m->consec);
810 /* Back up to the last insn of the consecutive group. */
811 p = prev_nonnote_insn (p);
813 /* We must now reset m->move_insn, m->is_equiv, and possibly
814 m->set_src to correspond to the effects of all the
816 temp = find_reg_note (p, REG_EQUIV, NULL_RTX);
818 m->set_src = XEXP (temp, 0), m->move_insn = 1;
821 temp = find_reg_note (p, REG_EQUAL, NULL_RTX);
822 if (temp && CONSTANT_P (XEXP (temp, 0)))
823 m->set_src = XEXP (temp, 0), m->move_insn = 1;
828 m->is_equiv = (find_reg_note (p, REG_EQUIV, NULL_RTX) != 0);
831 /* If this register is always set within a STRICT_LOW_PART
832 or set to zero, then its high bytes are constant.
833 So clear them outside the loop and within the loop
834 just load the low bytes.
835 We must check that the machine has an instruction to do so.
836 Also, if the value loaded into the register
837 depends on the same register, this cannot be done. */
838 else if (SET_SRC (set) == const0_rtx
839 && GET_CODE (NEXT_INSN (p)) == INSN
840 && (set1 = single_set (NEXT_INSN (p)))
841 && GET_CODE (set1) == SET
842 && (GET_CODE (SET_DEST (set1)) == STRICT_LOW_PART)
843 && (GET_CODE (XEXP (SET_DEST (set1), 0)) == SUBREG)
844 && (SUBREG_REG (XEXP (SET_DEST (set1), 0))
846 && !reg_mentioned_p (SET_DEST (set), SET_SRC (set1)))
848 register int regno = REGNO (SET_DEST (set));
849 if (n_times_set[regno] == 2)
851 register struct movable *m;
852 m = (struct movable *) alloca (sizeof (struct movable));
855 m->set_dest = SET_DEST (set);
863 /* If the insn may not be executed on some cycles,
864 we can't clear the whole reg; clear just high part.
865 Not even if the reg is used only within this loop.
872 Clearing x before the inner loop could clobber a value
873 being saved from the last time around the outer loop.
874 However, if the reg is not used outside this loop
875 and all uses of the register are in the same
876 basic block as the store, there is no problem.
878 If this insn was made by loop, we don't know its
879 INSN_LUID and hence must make a conservative
881 m->global = (INSN_UID (p) >= max_uid_for_loop
882 || (uid_luid[regno_last_uid[regno]]
884 || (uid_luid[regno_first_uid[regno]]
886 || (labels_in_range_p
887 (p, uid_luid[regno_first_uid[regno]])));
888 if (maybe_never && m->global)
889 m->savemode = GET_MODE (SET_SRC (set1));
891 m->savemode = VOIDmode;
895 m->lifetime = (uid_luid[regno_last_uid[regno]]
896 - uid_luid[regno_first_uid[regno]]);
898 n_times_set[regno] = -1;
899 /* Add M to the end of the chain MOVABLES. */
903 last_movable->next = m;
908 /* Past a call insn, we get to insns which might not be executed
909 because the call might exit. This matters for insns that trap.
910 Call insns inside a REG_LIBCALL/REG_RETVAL block always return,
911 so they don't count. */
912 else if (GET_CODE (p) == CALL_INSN && ! in_libcall)
914 /* Past a label or a jump, we get to insns for which we
915 can't count on whether or how many times they will be
916 executed during each iteration. Therefore, we can
917 only move out sets of trivial variables
918 (those not used after the loop). */
919 /* Similar code appears twice in strength_reduce. */
920 else if ((GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN)
921 /* If we enter the loop in the middle, and scan around to the
922 beginning, don't set maybe_never for that. This must be an
923 unconditional jump, otherwise the code at the top of the
924 loop might never be executed. Unconditional jumps are
925 followed a by barrier then loop end. */
926 && ! (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p) == loop_top
927 && NEXT_INSN (NEXT_INSN (p)) == end
928 && simplejump_p (p)))
930 else if (GET_CODE (p) == NOTE)
932 /* At the virtual top of a converted loop, insns are again known to
933 be executed: logically, the loop begins here even though the exit
934 code has been duplicated. */
935 if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP && loop_depth == 0)
936 maybe_never = call_passed = 0;
937 else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG)
939 else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)
944 /* If one movable subsumes another, ignore that other. */
946 ignore_some_movables (movables);
948 /* For each movable insn, see if the reg that it loads
949 leads when it dies right into another conditionally movable insn.
950 If so, record that the second insn "forces" the first one,
951 since the second can be moved only if the first is. */
953 force_movables (movables);
955 /* See if there are multiple movable insns that load the same value.
956 If there are, make all but the first point at the first one
957 through the `match' field, and add the priorities of them
958 all together as the priority of the first. */
960 combine_movables (movables, nregs);
962 /* Now consider each movable insn to decide whether it is worth moving.
963 Store 0 in n_times_set for each reg that is moved. */
965 move_movables (movables, threshold,
966 insn_count, loop_start, end, nregs);
968 /* Now candidates that still are negative are those not moved.
969 Change n_times_set to indicate that those are not actually invariant. */
970 for (i = 0; i < nregs; i++)
971 if (n_times_set[i] < 0)
972 n_times_set[i] = n_times_used[i];
974 if (flag_strength_reduce)
975 strength_reduce (scan_start, end, loop_top,
976 insn_count, loop_start, end);
979 /* Add elements to *OUTPUT to record all the pseudo-regs
980 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
983 record_excess_regs (in_this, not_in_this, output)
984 rtx in_this, not_in_this;
991 code = GET_CODE (in_this);
1005 if (REGNO (in_this) >= FIRST_PSEUDO_REGISTER
1006 && ! reg_mentioned_p (in_this, not_in_this))
1007 *output = gen_rtx (EXPR_LIST, VOIDmode, in_this, *output);
1011 fmt = GET_RTX_FORMAT (code);
1012 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1019 for (j = 0; j < XVECLEN (in_this, i); j++)
1020 record_excess_regs (XVECEXP (in_this, i, j), not_in_this, output);
1024 record_excess_regs (XEXP (in_this, i), not_in_this, output);
1030 /* Check what regs are referred to in the libcall block ending with INSN,
1031 aside from those mentioned in the equivalent value.
1032 If there are none, return 0.
1033 If there are one or more, return an EXPR_LIST containing all of them. */
1036 libcall_other_reg (insn, equiv)
1039 rtx note = find_reg_note (insn, REG_RETVAL, NULL_RTX);
1040 rtx p = XEXP (note, 0);
1043 /* First, find all the regs used in the libcall block
1044 that are not mentioned as inputs to the result. */
1048 if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN
1049 || GET_CODE (p) == CALL_INSN)
1050 record_excess_regs (PATTERN (p), equiv, &output);
1057 /* Return 1 if all uses of REG
1058 are between INSN and the end of the basic block. */
1061 reg_in_basic_block_p (insn, reg)
1064 int regno = REGNO (reg);
1067 if (regno_first_uid[regno] != INSN_UID (insn))
1070 /* Search this basic block for the already recorded last use of the reg. */
1071 for (p = insn; p; p = NEXT_INSN (p))
1073 switch (GET_CODE (p))
1080 /* Ordinary insn: if this is the last use, we win. */
1081 if (regno_last_uid[regno] == INSN_UID (p))
1086 /* Jump insn: if this is the last use, we win. */
1087 if (regno_last_uid[regno] == INSN_UID (p))
1089 /* Otherwise, it's the end of the basic block, so we lose. */
1094 /* It's the end of the basic block, so we lose. */
1099 /* The "last use" doesn't follow the "first use"?? */
1103 /* Compute the benefit of eliminating the insns in the block whose
1104 last insn is LAST. This may be a group of insns used to compute a
1105 value directly or can contain a library call. */
1108 libcall_benefit (last)
1114 for (insn = XEXP (find_reg_note (last, REG_RETVAL, NULL_RTX), 0);
1115 insn != last; insn = NEXT_INSN (insn))
1117 if (GET_CODE (insn) == CALL_INSN)
1118 benefit += 10; /* Assume at least this many insns in a library
1120 else if (GET_CODE (insn) == INSN
1121 && GET_CODE (PATTERN (insn)) != USE
1122 && GET_CODE (PATTERN (insn)) != CLOBBER)
1129 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1132 skip_consec_insns (insn, count)
1136 for (; count > 0; count--)
1140 /* If first insn of libcall sequence, skip to end. */
1141 /* Do this at start of loop, since INSN is guaranteed to
1143 if (GET_CODE (insn) != NOTE
1144 && (temp = find_reg_note (insn, REG_LIBCALL, NULL_RTX)))
1145 insn = XEXP (temp, 0);
1147 do insn = NEXT_INSN (insn);
1148 while (GET_CODE (insn) == NOTE);
1154 /* Ignore any movable whose insn falls within a libcall
1155 which is part of another movable.
1156 We make use of the fact that the movable for the libcall value
1157 was made later and so appears later on the chain. */
1160 ignore_some_movables (movables)
1161 struct movable *movables;
1163 register struct movable *m, *m1;
1165 for (m = movables; m; m = m->next)
1167 /* Is this a movable for the value of a libcall? */
1168 rtx note = find_reg_note (m->insn, REG_RETVAL, NULL_RTX);
1172 /* Check for earlier movables inside that range,
1173 and mark them invalid. We cannot use LUIDs here because
1174 insns created by loop.c for prior loops don't have LUIDs.
1175 Rather than reject all such insns from movables, we just
1176 explicitly check each insn in the libcall (since invariant
1177 libcalls aren't that common). */
1178 for (insn = XEXP (note, 0); insn != m->insn; insn = NEXT_INSN (insn))
1179 for (m1 = movables; m1 != m; m1 = m1->next)
1180 if (m1->insn == insn)
1186 /* For each movable insn, see if the reg that it loads
1187 leads when it dies right into another conditionally movable insn.
1188 If so, record that the second insn "forces" the first one,
1189 since the second can be moved only if the first is. */
1192 force_movables (movables)
1193 struct movable *movables;
1195 register struct movable *m, *m1;
1196 for (m1 = movables; m1; m1 = m1->next)
1197 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1198 if (!m1->partial && !m1->done)
1200 int regno = m1->regno;
1201 for (m = m1->next; m; m = m->next)
1202 /* ??? Could this be a bug? What if CSE caused the
1203 register of M1 to be used after this insn?
1204 Since CSE does not update regno_last_uid,
1205 this insn M->insn might not be where it dies.
1206 But very likely this doesn't matter; what matters is
1207 that M's reg is computed from M1's reg. */
1208 if (INSN_UID (m->insn) == regno_last_uid[regno]
1211 if (m != 0 && m->set_src == m1->set_dest
1212 /* If m->consec, m->set_src isn't valid. */
1216 /* Increase the priority of the moving the first insn
1217 since it permits the second to be moved as well. */
1221 m1->lifetime += m->lifetime;
1222 m1->savings += m1->savings;
1227 /* Find invariant expressions that are equal and can be combined into
1231 combine_movables (movables, nregs)
1232 struct movable *movables;
1235 register struct movable *m;
1236 char *matched_regs = (char *) alloca (nregs);
1237 enum machine_mode mode;
1239 /* Regs that are set more than once are not allowed to match
1240 or be matched. I'm no longer sure why not. */
1241 /* Perhaps testing m->consec_sets would be more appropriate here? */
1243 for (m = movables; m; m = m->next)
1244 if (m->match == 0 && n_times_used[m->regno] == 1 && !m->partial)
1246 register struct movable *m1;
1247 int regno = m->regno;
1249 bzero (matched_regs, nregs);
1250 matched_regs[regno] = 1;
1252 for (m1 = movables; m1; m1 = m1->next)
1253 if (m != m1 && m1->match == 0 && n_times_used[m1->regno] == 1
1254 /* A reg used outside the loop mustn't be eliminated. */
1256 /* A reg used for zero-extending mustn't be eliminated. */
1258 && (matched_regs[m1->regno]
1261 /* Can combine regs with different modes loaded from the
1262 same constant only if the modes are the same or
1263 if both are integer modes with M wider or the same
1264 width as M1. The check for integer is redundant, but
1265 safe, since the only case of differing destination
1266 modes with equal sources is when both sources are
1267 VOIDmode, i.e., CONST_INT. */
1268 (GET_MODE (m->set_dest) == GET_MODE (m1->set_dest)
1269 || (GET_MODE_CLASS (GET_MODE (m->set_dest)) == MODE_INT
1270 && GET_MODE_CLASS (GET_MODE (m1->set_dest)) == MODE_INT
1271 && (GET_MODE_BITSIZE (GET_MODE (m->set_dest))
1272 >= GET_MODE_BITSIZE (GET_MODE (m1->set_dest)))))
1273 /* See if the source of M1 says it matches M. */
1274 && ((GET_CODE (m1->set_src) == REG
1275 && matched_regs[REGNO (m1->set_src)])
1276 || rtx_equal_for_loop_p (m->set_src, m1->set_src,
1278 && ((m->dependencies == m1->dependencies)
1279 || rtx_equal_p (m->dependencies, m1->dependencies)))
1281 m->lifetime += m1->lifetime;
1282 m->savings += m1->savings;
1285 matched_regs[m1->regno] = 1;
1289 /* Now combine the regs used for zero-extension.
1290 This can be done for those not marked `global'
1291 provided their lives don't overlap. */
1293 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != VOIDmode;
1294 mode = GET_MODE_WIDER_MODE (mode))
1296 register struct movable *m0 = 0;
1298 /* Combine all the registers for extension from mode MODE.
1299 Don't combine any that are used outside this loop. */
1300 for (m = movables; m; m = m->next)
1301 if (m->partial && ! m->global
1302 && mode == GET_MODE (SET_SRC (PATTERN (NEXT_INSN (m->insn)))))
1304 register struct movable *m1;
1305 int first = uid_luid[regno_first_uid[m->regno]];
1306 int last = uid_luid[regno_last_uid[m->regno]];
1310 /* First one: don't check for overlap, just record it. */
1315 /* Make sure they extend to the same mode.
1316 (Almost always true.) */
1317 if (GET_MODE (m->set_dest) != GET_MODE (m0->set_dest))
1320 /* We already have one: check for overlap with those
1321 already combined together. */
1322 for (m1 = movables; m1 != m; m1 = m1->next)
1323 if (m1 == m0 || (m1->partial && m1->match == m0))
1324 if (! (uid_luid[regno_first_uid[m1->regno]] > last
1325 || uid_luid[regno_last_uid[m1->regno]] < first))
1328 /* No overlap: we can combine this with the others. */
1329 m0->lifetime += m->lifetime;
1330 m0->savings += m->savings;
1339 /* Return 1 if regs X and Y will become the same if moved. */
1342 regs_match_p (x, y, movables)
1344 struct movable *movables;
1348 struct movable *mx, *my;
1350 for (mx = movables; mx; mx = mx->next)
1351 if (mx->regno == xn)
1354 for (my = movables; my; my = my->next)
1355 if (my->regno == yn)
1359 && ((mx->match == my->match && mx->match != 0)
1361 || mx == my->match));
1364 /* Return 1 if X and Y are identical-looking rtx's.
1365 This is the Lisp function EQUAL for rtx arguments.
1367 If two registers are matching movables or a movable register and an
1368 equivalent constant, consider them equal. */
1371 rtx_equal_for_loop_p (x, y, movables)
1373 struct movable *movables;
1377 register struct movable *m;
1378 register enum rtx_code code;
1383 if (x == 0 || y == 0)
1386 code = GET_CODE (x);
1388 /* If we have a register and a constant, they may sometimes be
1390 if (GET_CODE (x) == REG && n_times_set[REGNO (x)] == -2
1392 for (m = movables; m; m = m->next)
1393 if (m->move_insn && m->regno == REGNO (x)
1394 && rtx_equal_p (m->set_src, y))
1397 else if (GET_CODE (y) == REG && n_times_set[REGNO (y)] == -2
1399 for (m = movables; m; m = m->next)
1400 if (m->move_insn && m->regno == REGNO (y)
1401 && rtx_equal_p (m->set_src, x))
1404 /* Otherwise, rtx's of different codes cannot be equal. */
1405 if (code != GET_CODE (y))
1408 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1409 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1411 if (GET_MODE (x) != GET_MODE (y))
1414 /* These three types of rtx's can be compared nonrecursively. */
1416 return (REGNO (x) == REGNO (y) || regs_match_p (x, y, movables));
1418 if (code == LABEL_REF)
1419 return XEXP (x, 0) == XEXP (y, 0);
1420 if (code == SYMBOL_REF)
1421 return XSTR (x, 0) == XSTR (y, 0);
1423 /* Compare the elements. If any pair of corresponding elements
1424 fail to match, return 0 for the whole things. */
1426 fmt = GET_RTX_FORMAT (code);
1427 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1432 if (XWINT (x, i) != XWINT (y, i))
1437 if (XINT (x, i) != XINT (y, i))
1442 /* Two vectors must have the same length. */
1443 if (XVECLEN (x, i) != XVECLEN (y, i))
1446 /* And the corresponding elements must match. */
1447 for (j = 0; j < XVECLEN (x, i); j++)
1448 if (rtx_equal_for_loop_p (XVECEXP (x, i, j), XVECEXP (y, i, j), movables) == 0)
1453 if (rtx_equal_for_loop_p (XEXP (x, i), XEXP (y, i), movables) == 0)
1458 if (strcmp (XSTR (x, i), XSTR (y, i)))
1463 /* These are just backpointers, so they don't matter. */
1469 /* It is believed that rtx's at this level will never
1470 contain anything but integers and other rtx's,
1471 except for within LABEL_REFs and SYMBOL_REFs. */
1479 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1480 insns in INSNS which use thet reference. */
1483 add_label_notes (x, insns)
1487 enum rtx_code code = GET_CODE (x);
1492 if (code == LABEL_REF && !LABEL_REF_NONLOCAL_P (x))
1494 rtx next = next_real_insn (XEXP (x, 0));
1496 /* Don't record labels that refer to dispatch tables.
1497 This is not necessary, since the tablejump references the same label.
1498 And if we did record them, flow.c would make worse code. */
1500 || ! (GET_CODE (next) == JUMP_INSN
1501 && (GET_CODE (PATTERN (next)) == ADDR_VEC
1502 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC)))
1504 for (insn = insns; insn; insn = NEXT_INSN (insn))
1505 if (reg_mentioned_p (XEXP (x, 0), insn))
1506 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_LABEL, XEXP (x, 0),
1512 fmt = GET_RTX_FORMAT (code);
1513 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1516 add_label_notes (XEXP (x, i), insns);
1517 else if (fmt[i] == 'E')
1518 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1519 add_label_notes (XVECEXP (x, i, j), insns);
1523 /* Scan MOVABLES, and move the insns that deserve to be moved.
1524 If two matching movables are combined, replace one reg with the
1525 other throughout. */
1528 move_movables (movables, threshold, insn_count, loop_start, end, nregs)
1529 struct movable *movables;
1537 register struct movable *m;
1539 /* Map of pseudo-register replacements to handle combining
1540 when we move several insns that load the same value
1541 into different pseudo-registers. */
1542 rtx *reg_map = (rtx *) alloca (nregs * sizeof (rtx));
1543 char *already_moved = (char *) alloca (nregs);
1545 bzero (already_moved, nregs);
1546 bzero ((char *) reg_map, nregs * sizeof (rtx));
1550 for (m = movables; m; m = m->next)
1552 /* Describe this movable insn. */
1554 if (loop_dump_stream)
1556 fprintf (loop_dump_stream, "Insn %d: regno %d (life %d), ",
1557 INSN_UID (m->insn), m->regno, m->lifetime);
1559 fprintf (loop_dump_stream, "consec %d, ", m->consec);
1561 fprintf (loop_dump_stream, "cond ");
1563 fprintf (loop_dump_stream, "force ");
1565 fprintf (loop_dump_stream, "global ");
1567 fprintf (loop_dump_stream, "done ");
1569 fprintf (loop_dump_stream, "move-insn ");
1571 fprintf (loop_dump_stream, "matches %d ",
1572 INSN_UID (m->match->insn));
1574 fprintf (loop_dump_stream, "forces %d ",
1575 INSN_UID (m->forces->insn));
1578 /* Count movables. Value used in heuristics in strength_reduce. */
1581 /* Ignore the insn if it's already done (it matched something else).
1582 Otherwise, see if it is now safe to move. */
1586 || (1 == invariant_p (m->set_src)
1587 && (m->dependencies == 0
1588 || 1 == invariant_p (m->dependencies))
1590 || 1 == consec_sets_invariant_p (m->set_dest,
1593 && (! m->forces || m->forces->done))
1597 int savings = m->savings;
1599 /* We have an insn that is safe to move.
1600 Compute its desirability. */
1605 if (loop_dump_stream)
1606 fprintf (loop_dump_stream, "savings %d ", savings);
1608 if (moved_once[regno])
1612 if (loop_dump_stream)
1613 fprintf (loop_dump_stream, "halved since already moved ");
1616 /* An insn MUST be moved if we already moved something else
1617 which is safe only if this one is moved too: that is,
1618 if already_moved[REGNO] is nonzero. */
1620 /* An insn is desirable to move if the new lifetime of the
1621 register is no more than THRESHOLD times the old lifetime.
1622 If it's not desirable, it means the loop is so big
1623 that moving won't speed things up much,
1624 and it is liable to make register usage worse. */
1626 /* It is also desirable to move if it can be moved at no
1627 extra cost because something else was already moved. */
1629 if (already_moved[regno]
1630 || (threshold * savings * m->lifetime) >= insn_count
1631 || (m->forces && m->forces->done
1632 && n_times_used[m->forces->regno] == 1))
1635 register struct movable *m1;
1638 /* Now move the insns that set the reg. */
1640 if (m->partial && m->match)
1644 /* Find the end of this chain of matching regs.
1645 Thus, we load each reg in the chain from that one reg.
1646 And that reg is loaded with 0 directly,
1647 since it has ->match == 0. */
1648 for (m1 = m; m1->match; m1 = m1->match);
1649 newpat = gen_move_insn (SET_DEST (PATTERN (m->insn)),
1650 SET_DEST (PATTERN (m1->insn)));
1651 i1 = emit_insn_before (newpat, loop_start);
1653 /* Mark the moved, invariant reg as being allowed to
1654 share a hard reg with the other matching invariant. */
1655 REG_NOTES (i1) = REG_NOTES (m->insn);
1656 r1 = SET_DEST (PATTERN (m->insn));
1657 r2 = SET_DEST (PATTERN (m1->insn));
1658 regs_may_share = gen_rtx (EXPR_LIST, VOIDmode, r1,
1659 gen_rtx (EXPR_LIST, VOIDmode, r2,
1661 delete_insn (m->insn);
1666 if (loop_dump_stream)
1667 fprintf (loop_dump_stream, " moved to %d", INSN_UID (i1));
1669 /* If we are to re-generate the item being moved with a
1670 new move insn, first delete what we have and then emit
1671 the move insn before the loop. */
1672 else if (m->move_insn)
1676 for (count = m->consec; count >= 0; count--)
1678 /* If this is the first insn of a library call sequence,
1680 if (GET_CODE (p) != NOTE
1681 && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX)))
1684 /* If this is the last insn of a libcall sequence, then
1685 delete every insn in the sequence except the last.
1686 The last insn is handled in the normal manner. */
1687 if (GET_CODE (p) != NOTE
1688 && (temp = find_reg_note (p, REG_RETVAL, NULL_RTX)))
1690 temp = XEXP (temp, 0);
1692 temp = delete_insn (temp);
1695 p = delete_insn (p);
1696 while (p && GET_CODE (p) == NOTE)
1701 emit_move_insn (m->set_dest, m->set_src);
1702 temp = get_insns ();
1705 add_label_notes (m->set_src, temp);
1707 i1 = emit_insns_before (temp, loop_start);
1708 if (! find_reg_note (i1, REG_EQUAL, NULL_RTX))
1710 = gen_rtx (EXPR_LIST,
1711 m->is_equiv ? REG_EQUIV : REG_EQUAL,
1712 m->set_src, REG_NOTES (i1));
1714 if (loop_dump_stream)
1715 fprintf (loop_dump_stream, " moved to %d", INSN_UID (i1));
1717 /* The more regs we move, the less we like moving them. */
1722 for (count = m->consec; count >= 0; count--)
1726 /* If first insn of libcall sequence, skip to end. */
1727 /* Do this at start of loop, since p is guaranteed to
1729 if (GET_CODE (p) != NOTE
1730 && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX)))
1733 /* If last insn of libcall sequence, move all
1734 insns except the last before the loop. The last
1735 insn is handled in the normal manner. */
1736 if (GET_CODE (p) != NOTE
1737 && (temp = find_reg_note (p, REG_RETVAL, NULL_RTX)))
1741 rtx fn_address_insn = 0;
1744 for (temp = XEXP (temp, 0); temp != p;
1745 temp = NEXT_INSN (temp))
1751 if (GET_CODE (temp) == NOTE)
1754 body = PATTERN (temp);
1756 /* Find the next insn after TEMP,
1757 not counting USE or NOTE insns. */
1758 for (next = NEXT_INSN (temp); next != p;
1759 next = NEXT_INSN (next))
1760 if (! (GET_CODE (next) == INSN
1761 && GET_CODE (PATTERN (next)) == USE)
1762 && GET_CODE (next) != NOTE)
1765 /* If that is the call, this may be the insn
1766 that loads the function address.
1768 Extract the function address from the insn
1769 that loads it into a register.
1770 If this insn was cse'd, we get incorrect code.
1772 So emit a new move insn that copies the
1773 function address into the register that the
1774 call insn will use. flow.c will delete any
1775 redundant stores that we have created. */
1776 if (GET_CODE (next) == CALL_INSN
1777 && GET_CODE (body) == SET
1778 && GET_CODE (SET_DEST (body)) == REG
1779 && (n = find_reg_note (temp, REG_EQUAL,
1782 fn_reg = SET_SRC (body);
1783 if (GET_CODE (fn_reg) != REG)
1784 fn_reg = SET_DEST (body);
1785 fn_address = XEXP (n, 0);
1786 fn_address_insn = temp;
1788 /* We have the call insn.
1789 If it uses the register we suspect it might,
1790 load it with the correct address directly. */
1791 if (GET_CODE (temp) == CALL_INSN
1793 && reg_referenced_p (fn_reg, body))
1794 emit_insn_after (gen_move_insn (fn_reg,
1798 if (GET_CODE (temp) == CALL_INSN)
1800 i1 = emit_call_insn_before (body, loop_start);
1801 /* Because the USAGE information potentially
1802 contains objects other than hard registers
1803 we need to copy it. */
1804 if (CALL_INSN_FUNCTION_USAGE (temp))
1805 CALL_INSN_FUNCTION_USAGE (i1) =
1806 copy_rtx (CALL_INSN_FUNCTION_USAGE (temp));
1809 i1 = emit_insn_before (body, loop_start);
1812 if (temp == fn_address_insn)
1813 fn_address_insn = i1;
1814 REG_NOTES (i1) = REG_NOTES (temp);
1818 if (m->savemode != VOIDmode)
1820 /* P sets REG to zero; but we should clear only
1821 the bits that are not covered by the mode
1823 rtx reg = m->set_dest;
1829 (GET_MODE (reg), and_optab, reg,
1830 GEN_INT ((((HOST_WIDE_INT) 1
1831 << GET_MODE_BITSIZE (m->savemode)))
1833 reg, 1, OPTAB_LIB_WIDEN);
1837 emit_move_insn (reg, tem);
1838 sequence = gen_sequence ();
1840 i1 = emit_insn_before (sequence, loop_start);
1842 else if (GET_CODE (p) == CALL_INSN)
1844 i1 = emit_call_insn_before (PATTERN (p), loop_start);
1845 /* Because the USAGE information potentially
1846 contains objects other than hard registers
1847 we need to copy it. */
1848 if (CALL_INSN_FUNCTION_USAGE (p))
1849 CALL_INSN_FUNCTION_USAGE (i1) =
1850 copy_rtx (CALL_INSN_FUNCTION_USAGE (p));
1853 i1 = emit_insn_before (PATTERN (p), loop_start);
1855 REG_NOTES (i1) = REG_NOTES (p);
1857 /* If there is a REG_EQUAL note present whose value is
1858 not loop invariant, then delete it, since it may
1859 cause problems with later optimization passes.
1860 It is possible for cse to create such notes
1861 like this as a result of record_jump_cond. */
1863 if ((temp = find_reg_note (i1, REG_EQUAL, NULL_RTX))
1864 && ! invariant_p (XEXP (temp, 0)))
1865 remove_note (i1, temp);
1870 if (loop_dump_stream)
1871 fprintf (loop_dump_stream, " moved to %d",
1875 /* This isn't needed because REG_NOTES is copied
1876 below and is wrong since P might be a PARALLEL. */
1877 if (REG_NOTES (i1) == 0
1878 && ! m->partial /* But not if it's a zero-extend clr. */
1879 && ! m->global /* and not if used outside the loop
1880 (since it might get set outside). */
1881 && CONSTANT_P (SET_SRC (PATTERN (p))))
1883 = gen_rtx (EXPR_LIST, REG_EQUAL,
1884 SET_SRC (PATTERN (p)), REG_NOTES (i1));
1887 /* If library call, now fix the REG_NOTES that contain
1888 insn pointers, namely REG_LIBCALL on FIRST
1889 and REG_RETVAL on I1. */
1890 if (temp = find_reg_note (i1, REG_RETVAL, NULL_RTX))
1892 XEXP (temp, 0) = first;
1893 temp = find_reg_note (first, REG_LIBCALL, NULL_RTX);
1894 XEXP (temp, 0) = i1;
1898 do p = NEXT_INSN (p);
1899 while (p && GET_CODE (p) == NOTE);
1902 /* The more regs we move, the less we like moving them. */
1906 /* Any other movable that loads the same register
1908 already_moved[regno] = 1;
1910 /* This reg has been moved out of one loop. */
1911 moved_once[regno] = 1;
1913 /* The reg set here is now invariant. */
1915 n_times_set[regno] = 0;
1919 /* Change the length-of-life info for the register
1920 to say it lives at least the full length of this loop.
1921 This will help guide optimizations in outer loops. */
1923 if (uid_luid[regno_first_uid[regno]] > INSN_LUID (loop_start))
1924 /* This is the old insn before all the moved insns.
1925 We can't use the moved insn because it is out of range
1926 in uid_luid. Only the old insns have luids. */
1927 regno_first_uid[regno] = INSN_UID (loop_start);
1928 if (uid_luid[regno_last_uid[regno]] < INSN_LUID (end))
1929 regno_last_uid[regno] = INSN_UID (end);
1931 /* Combine with this moved insn any other matching movables. */
1934 for (m1 = movables; m1; m1 = m1->next)
1939 /* Schedule the reg loaded by M1
1940 for replacement so that shares the reg of M.
1941 If the modes differ (only possible in restricted
1942 circumstances, make a SUBREG. */
1943 if (GET_MODE (m->set_dest) == GET_MODE (m1->set_dest))
1944 reg_map[m1->regno] = m->set_dest;
1947 = gen_lowpart_common (GET_MODE (m1->set_dest),
1950 /* Get rid of the matching insn
1951 and prevent further processing of it. */
1954 /* if library call, delete all insn except last, which
1956 if (temp = find_reg_note (m1->insn, REG_RETVAL,
1959 for (temp = XEXP (temp, 0); temp != m1->insn;
1960 temp = NEXT_INSN (temp))
1963 delete_insn (m1->insn);
1965 /* Any other movable that loads the same register
1967 already_moved[m1->regno] = 1;
1969 /* The reg merged here is now invariant,
1970 if the reg it matches is invariant. */
1972 n_times_set[m1->regno] = 0;
1975 else if (loop_dump_stream)
1976 fprintf (loop_dump_stream, "not desirable");
1978 else if (loop_dump_stream && !m->match)
1979 fprintf (loop_dump_stream, "not safe");
1981 if (loop_dump_stream)
1982 fprintf (loop_dump_stream, "\n");
1986 new_start = loop_start;
1988 /* Go through all the instructions in the loop, making
1989 all the register substitutions scheduled in REG_MAP. */
1990 for (p = new_start; p != end; p = NEXT_INSN (p))
1991 if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN
1992 || GET_CODE (p) == CALL_INSN)
1994 replace_regs (PATTERN (p), reg_map, nregs, 0);
1995 replace_regs (REG_NOTES (p), reg_map, nregs, 0);
2001 /* Scan X and replace the address of any MEM in it with ADDR.
2002 REG is the address that MEM should have before the replacement. */
2005 replace_call_address (x, reg, addr)
2008 register enum rtx_code code;
2014 code = GET_CODE (x);
2028 /* Short cut for very common case. */
2029 replace_call_address (XEXP (x, 1), reg, addr);
2033 /* Short cut for very common case. */
2034 replace_call_address (XEXP (x, 0), reg, addr);
2038 /* If this MEM uses a reg other than the one we expected,
2039 something is wrong. */
2040 if (XEXP (x, 0) != reg)
2046 fmt = GET_RTX_FORMAT (code);
2047 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2050 replace_call_address (XEXP (x, i), reg, addr);
2054 for (j = 0; j < XVECLEN (x, i); j++)
2055 replace_call_address (XVECEXP (x, i, j), reg, addr);
2061 /* Return the number of memory refs to addresses that vary
2065 count_nonfixed_reads (x)
2068 register enum rtx_code code;
2076 code = GET_CODE (x);
2090 return ((invariant_p (XEXP (x, 0)) != 1)
2091 + count_nonfixed_reads (XEXP (x, 0)));
2095 fmt = GET_RTX_FORMAT (code);
2096 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2099 value += count_nonfixed_reads (XEXP (x, i));
2103 for (j = 0; j < XVECLEN (x, i); j++)
2104 value += count_nonfixed_reads (XVECEXP (x, i, j));
2112 /* P is an instruction that sets a register to the result of a ZERO_EXTEND.
2113 Replace it with an instruction to load just the low bytes
2114 if the machine supports such an instruction,
2115 and insert above LOOP_START an instruction to clear the register. */
2118 constant_high_bytes (p, loop_start)
2122 register int insn_code_number;
2124 /* Try to change (SET (REG ...) (ZERO_EXTEND (..:B ...)))
2125 to (SET (STRICT_LOW_PART (SUBREG:B (REG...))) ...). */
2127 new = gen_rtx (SET, VOIDmode,
2128 gen_rtx (STRICT_LOW_PART, VOIDmode,
2129 gen_rtx (SUBREG, GET_MODE (XEXP (SET_SRC (PATTERN (p)), 0)),
2130 SET_DEST (PATTERN (p)),
2132 XEXP (SET_SRC (PATTERN (p)), 0));
2133 insn_code_number = recog (new, p);
2135 if (insn_code_number)
2139 /* Clear destination register before the loop. */
2140 emit_insn_before (gen_rtx (SET, VOIDmode,
2141 SET_DEST (PATTERN (p)),
2145 /* Inside the loop, just load the low part. */
2151 /* Scan a loop setting the variables `unknown_address_altered',
2152 `num_mem_sets', `loop_continue', loops_enclosed', `loop_has_call',
2153 and `loop_has_volatile'.
2154 Also, fill in the array `loop_store_mems'. */
2157 prescan_loop (start, end)
2160 register int level = 1;
2163 unknown_address_altered = 0;
2165 loop_has_volatile = 0;
2166 loop_store_mems_idx = 0;
2172 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
2173 insn = NEXT_INSN (insn))
2175 if (GET_CODE (insn) == NOTE)
2177 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
2180 /* Count number of loops contained in this one. */
2183 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
2192 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_CONT)
2195 loop_continue = insn;
2198 else if (GET_CODE (insn) == CALL_INSN)
2200 unknown_address_altered = 1;
2205 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN)
2207 if (volatile_refs_p (PATTERN (insn)))
2208 loop_has_volatile = 1;
2210 note_stores (PATTERN (insn), note_addr_stored);
2216 /* Scan the function looking for loops. Record the start and end of each loop.
2217 Also mark as invalid loops any loops that contain a setjmp or are branched
2218 to from outside the loop. */
2221 find_and_verify_loops (f)
2225 int current_loop = -1;
2229 /* If there are jumps to undefined labels,
2230 treat them as jumps out of any/all loops.
2231 This also avoids writing past end of tables when there are no loops. */
2232 uid_loop_num[0] = -1;
2234 /* Find boundaries of loops, mark which loops are contained within
2235 loops, and invalidate loops that have setjmp. */
2237 for (insn = f; insn; insn = NEXT_INSN (insn))
2239 if (GET_CODE (insn) == NOTE)
2240 switch (NOTE_LINE_NUMBER (insn))
2242 case NOTE_INSN_LOOP_BEG:
2243 loop_number_loop_starts[++next_loop] = insn;
2244 loop_number_loop_ends[next_loop] = 0;
2245 loop_outer_loop[next_loop] = current_loop;
2246 loop_invalid[next_loop] = 0;
2247 loop_number_exit_labels[next_loop] = 0;
2248 loop_number_exit_count[next_loop] = 0;
2249 current_loop = next_loop;
2252 case NOTE_INSN_SETJMP:
2253 /* In this case, we must invalidate our current loop and any
2255 for (loop = current_loop; loop != -1; loop = loop_outer_loop[loop])
2257 loop_invalid[loop] = 1;
2258 if (loop_dump_stream)
2259 fprintf (loop_dump_stream,
2260 "\nLoop at %d ignored due to setjmp.\n",
2261 INSN_UID (loop_number_loop_starts[loop]));
2265 case NOTE_INSN_LOOP_END:
2266 if (current_loop == -1)
2269 loop_number_loop_ends[current_loop] = insn;
2270 current_loop = loop_outer_loop[current_loop];
2275 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2276 enclosing loop, but this doesn't matter. */
2277 uid_loop_num[INSN_UID (insn)] = current_loop;
2280 /* Any loop containing a label used in an initializer must be invalidated,
2281 because it can be jumped into from anywhere. */
2283 for (label = forced_labels; label; label = XEXP (label, 1))
2287 for (loop_num = uid_loop_num[INSN_UID (XEXP (label, 0))];
2289 loop_num = loop_outer_loop[loop_num])
2290 loop_invalid[loop_num] = 1;
2293 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2294 loop that it is not contained within, that loop is marked invalid.
2295 If any INSN or CALL_INSN uses a label's address, then the loop containing
2296 that label is marked invalid, because it could be jumped into from
2299 Also look for blocks of code ending in an unconditional branch that
2300 exits the loop. If such a block is surrounded by a conditional
2301 branch around the block, move the block elsewhere (see below) and
2302 invert the jump to point to the code block. This may eliminate a
2303 label in our loop and will simplify processing by both us and a
2304 possible second cse pass. */
2306 for (insn = f; insn; insn = NEXT_INSN (insn))
2307 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
2309 int this_loop_num = uid_loop_num[INSN_UID (insn)];
2311 if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
2313 rtx note = find_reg_note (insn, REG_LABEL, NULL_RTX);
2318 for (loop_num = uid_loop_num[INSN_UID (XEXP (note, 0))];
2320 loop_num = loop_outer_loop[loop_num])
2321 loop_invalid[loop_num] = 1;
2325 if (GET_CODE (insn) != JUMP_INSN)
2328 mark_loop_jump (PATTERN (insn), this_loop_num);
2330 /* See if this is an unconditional branch outside the loop. */
2331 if (this_loop_num != -1
2332 && (GET_CODE (PATTERN (insn)) == RETURN
2333 || (simplejump_p (insn)
2334 && (uid_loop_num[INSN_UID (JUMP_LABEL (insn))]
2336 && get_max_uid () < max_uid_for_loop)
2339 rtx our_next = next_real_insn (insn);
2341 int outer_loop = -1;
2343 /* Go backwards until we reach the start of the loop, a label,
2345 for (p = PREV_INSN (insn);
2346 GET_CODE (p) != CODE_LABEL
2347 && ! (GET_CODE (p) == NOTE
2348 && NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG)
2349 && GET_CODE (p) != JUMP_INSN;
2353 /* Check for the case where we have a jump to an inner nested
2354 loop, and do not perform the optimization in that case. */
2356 if (JUMP_LABEL (insn))
2358 dest_loop = uid_loop_num[INSN_UID (JUMP_LABEL (insn))];
2359 if (dest_loop != -1)
2361 for (outer_loop = dest_loop; outer_loop != -1;
2362 outer_loop = loop_outer_loop[outer_loop])
2363 if (outer_loop == this_loop_num)
2368 /* Make sure that the target of P is within the current loop. */
2370 if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p)
2371 && uid_loop_num[INSN_UID (JUMP_LABEL (p))] != this_loop_num)
2372 outer_loop = this_loop_num;
2374 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2375 we have a block of code to try to move.
2377 We look backward and then forward from the target of INSN
2378 to find a BARRIER at the same loop depth as the target.
2379 If we find such a BARRIER, we make a new label for the start
2380 of the block, invert the jump in P and point it to that label,
2381 and move the block of code to the spot we found. */
2383 if (outer_loop == -1
2384 && GET_CODE (p) == JUMP_INSN
2385 && JUMP_LABEL (p) != 0
2386 /* Just ignore jumps to labels that were never emitted.
2387 These always indicate compilation errors. */
2388 && INSN_UID (JUMP_LABEL (p)) != 0
2390 && ! simplejump_p (p)
2391 && next_real_insn (JUMP_LABEL (p)) == our_next)
2394 = JUMP_LABEL (insn) ? JUMP_LABEL (insn) : get_last_insn ();
2395 int target_loop_num = uid_loop_num[INSN_UID (target)];
2398 for (loc = target; loc; loc = PREV_INSN (loc))
2399 if (GET_CODE (loc) == BARRIER
2400 && uid_loop_num[INSN_UID (loc)] == target_loop_num)
2404 for (loc = target; loc; loc = NEXT_INSN (loc))
2405 if (GET_CODE (loc) == BARRIER
2406 && uid_loop_num[INSN_UID (loc)] == target_loop_num)
2411 rtx cond_label = JUMP_LABEL (p);
2412 rtx new_label = get_label_after (p);
2414 /* Ensure our label doesn't go away. */
2415 LABEL_NUSES (cond_label)++;
2417 /* Verify that uid_loop_num is large enough and that
2419 if (invert_jump (p, new_label))
2423 /* Include the BARRIER after INSN and copy the
2425 new_label = squeeze_notes (new_label, NEXT_INSN (insn));
2426 reorder_insns (new_label, NEXT_INSN (insn), loc);
2428 /* All those insns are now in TARGET_LOOP_NUM. */
2429 for (q = new_label; q != NEXT_INSN (NEXT_INSN (insn));
2431 uid_loop_num[INSN_UID (q)] = target_loop_num;
2433 /* The label jumped to by INSN is no longer a loop exit.
2434 Unless INSN does not have a label (e.g., it is a
2435 RETURN insn), search loop_number_exit_labels to find
2436 its label_ref, and remove it. Also turn off
2437 LABEL_OUTSIDE_LOOP_P bit. */
2438 if (JUMP_LABEL (insn))
2443 r = loop_number_exit_labels[this_loop_num];
2444 r; q = r, r = LABEL_NEXTREF (r))
2445 if (XEXP (r, 0) == JUMP_LABEL (insn))
2447 LABEL_OUTSIDE_LOOP_P (r) = 0;
2449 LABEL_NEXTREF (q) = LABEL_NEXTREF (r);
2451 loop_number_exit_labels[this_loop_num]
2452 = LABEL_NEXTREF (r);
2456 for (loop_num = this_loop_num;
2457 loop_num != -1 && loop_num != target_loop_num;
2458 loop_num = loop_outer_loop[loop_num])
2459 loop_number_exit_count[loop_num]--;
2461 /* If we didn't find it, then something is wrong. */
2466 /* P is now a jump outside the loop, so it must be put
2467 in loop_number_exit_labels, and marked as such.
2468 The easiest way to do this is to just call
2469 mark_loop_jump again for P. */
2470 mark_loop_jump (PATTERN (p), this_loop_num);
2472 /* If INSN now jumps to the insn after it,
2474 if (JUMP_LABEL (insn) != 0
2475 && (next_real_insn (JUMP_LABEL (insn))
2476 == next_real_insn (insn)))
2480 /* Continue the loop after where the conditional
2481 branch used to jump, since the only branch insn
2482 in the block (if it still remains) is an inter-loop
2483 branch and hence needs no processing. */
2484 insn = NEXT_INSN (cond_label);
2486 if (--LABEL_NUSES (cond_label) == 0)
2487 delete_insn (cond_label);
2489 /* This loop will be continued with NEXT_INSN (insn). */
2490 insn = PREV_INSN (insn);
2497 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2498 loops it is contained in, mark the target loop invalid.
2500 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2503 mark_loop_jump (x, loop_num)
2511 switch (GET_CODE (x))
2524 /* There could be a label reference in here. */
2525 mark_loop_jump (XEXP (x, 0), loop_num);
2531 mark_loop_jump (XEXP (x, 0), loop_num);
2532 mark_loop_jump (XEXP (x, 1), loop_num);
2537 mark_loop_jump (XEXP (x, 0), loop_num);
2541 dest_loop = uid_loop_num[INSN_UID (XEXP (x, 0))];
2543 /* Link together all labels that branch outside the loop. This
2544 is used by final_[bg]iv_value and the loop unrolling code. Also
2545 mark this LABEL_REF so we know that this branch should predict
2548 /* A check to make sure the label is not in an inner nested loop,
2549 since this does not count as a loop exit. */
2550 if (dest_loop != -1)
2552 for (outer_loop = dest_loop; outer_loop != -1;
2553 outer_loop = loop_outer_loop[outer_loop])
2554 if (outer_loop == loop_num)
2560 if (loop_num != -1 && outer_loop == -1)
2562 LABEL_OUTSIDE_LOOP_P (x) = 1;
2563 LABEL_NEXTREF (x) = loop_number_exit_labels[loop_num];
2564 loop_number_exit_labels[loop_num] = x;
2566 for (outer_loop = loop_num;
2567 outer_loop != -1 && outer_loop != dest_loop;
2568 outer_loop = loop_outer_loop[outer_loop])
2569 loop_number_exit_count[outer_loop]++;
2572 /* If this is inside a loop, but not in the current loop or one enclosed
2573 by it, it invalidates at least one loop. */
2575 if (dest_loop == -1)
2578 /* We must invalidate every nested loop containing the target of this
2579 label, except those that also contain the jump insn. */
2581 for (; dest_loop != -1; dest_loop = loop_outer_loop[dest_loop])
2583 /* Stop when we reach a loop that also contains the jump insn. */
2584 for (outer_loop = loop_num; outer_loop != -1;
2585 outer_loop = loop_outer_loop[outer_loop])
2586 if (dest_loop == outer_loop)
2589 /* If we get here, we know we need to invalidate a loop. */
2590 if (loop_dump_stream && ! loop_invalid[dest_loop])
2591 fprintf (loop_dump_stream,
2592 "\nLoop at %d ignored due to multiple entry points.\n",
2593 INSN_UID (loop_number_loop_starts[dest_loop]));
2595 loop_invalid[dest_loop] = 1;
2600 /* If this is not setting pc, ignore. */
2601 if (SET_DEST (x) == pc_rtx)
2602 mark_loop_jump (SET_SRC (x), loop_num);
2606 mark_loop_jump (XEXP (x, 1), loop_num);
2607 mark_loop_jump (XEXP (x, 2), loop_num);
2612 for (i = 0; i < XVECLEN (x, 0); i++)
2613 mark_loop_jump (XVECEXP (x, 0, i), loop_num);
2617 for (i = 0; i < XVECLEN (x, 1); i++)
2618 mark_loop_jump (XVECEXP (x, 1, i), loop_num);
2622 /* Treat anything else (such as a symbol_ref)
2623 as a branch out of this loop, but not into any loop. */
2627 loop_number_exit_labels[loop_num] = x;
2629 for (outer_loop = loop_num; outer_loop != -1;
2630 outer_loop = loop_outer_loop[outer_loop])
2631 loop_number_exit_count[outer_loop]++;
2637 /* Return nonzero if there is a label in the range from
2638 insn INSN to and including the insn whose luid is END
2639 INSN must have an assigned luid (i.e., it must not have
2640 been previously created by loop.c). */
2643 labels_in_range_p (insn, end)
2647 while (insn && INSN_LUID (insn) <= end)
2649 if (GET_CODE (insn) == CODE_LABEL)
2651 insn = NEXT_INSN (insn);
2657 /* Record that a memory reference X is being set. */
2660 note_addr_stored (x)
2665 if (x == 0 || GET_CODE (x) != MEM)
2668 /* Count number of memory writes.
2669 This affects heuristics in strength_reduce. */
2672 /* BLKmode MEM means all memory is clobbered. */
2673 if (GET_MODE (x) == BLKmode)
2674 unknown_address_altered = 1;
2676 if (unknown_address_altered)
2679 for (i = 0; i < loop_store_mems_idx; i++)
2680 if (rtx_equal_p (XEXP (loop_store_mems[i], 0), XEXP (x, 0))
2681 && MEM_IN_STRUCT_P (x) == MEM_IN_STRUCT_P (loop_store_mems[i]))
2683 /* We are storing at the same address as previously noted. Save the
2685 if (GET_MODE_SIZE (GET_MODE (x))
2686 > GET_MODE_SIZE (GET_MODE (loop_store_mems[i])))
2687 loop_store_mems[i] = x;
2691 if (i == NUM_STORES)
2692 unknown_address_altered = 1;
2694 else if (i == loop_store_mems_idx)
2695 loop_store_mems[loop_store_mems_idx++] = x;
2698 /* Return nonzero if the rtx X is invariant over the current loop.
2700 The value is 2 if we refer to something only conditionally invariant.
2702 If `unknown_address_altered' is nonzero, no memory ref is invariant.
2703 Otherwise, a memory ref is invariant if it does not conflict with
2704 anything stored in `loop_store_mems'. */
2711 register enum rtx_code code;
2713 int conditional = 0;
2717 code = GET_CODE (x);
2727 /* A LABEL_REF is normally invariant, however, if we are unrolling
2728 loops, and this label is inside the loop, then it isn't invariant.
2729 This is because each unrolled copy of the loop body will have
2730 a copy of this label. If this was invariant, then an insn loading
2731 the address of this label into a register might get moved outside
2732 the loop, and then each loop body would end up using the same label.
2734 We don't know the loop bounds here though, so just fail for all
2736 if (flag_unroll_loops)
2743 case UNSPEC_VOLATILE:
2747 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
2748 since the reg might be set by initialization within the loop. */
2749 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
2750 || x == arg_pointer_rtx)
2753 && REGNO (x) < FIRST_PSEUDO_REGISTER && call_used_regs[REGNO (x)])
2755 if (n_times_set[REGNO (x)] < 0)
2757 return n_times_set[REGNO (x)] == 0;
2760 /* Volatile memory references must be rejected. Do this before
2761 checking for read-only items, so that volatile read-only items
2762 will be rejected also. */
2763 if (MEM_VOLATILE_P (x))
2766 /* Read-only items (such as constants in a constant pool) are
2767 invariant if their address is. */
2768 if (RTX_UNCHANGING_P (x))
2771 /* If we filled the table (or had a subroutine call), any location
2772 in memory could have been clobbered. */
2773 if (unknown_address_altered)
2776 /* See if there is any dependence between a store and this load. */
2777 for (i = loop_store_mems_idx - 1; i >= 0; i--)
2778 if (true_dependence (loop_store_mems[i], x))
2781 /* It's not invalidated by a store in memory
2782 but we must still verify the address is invariant. */
2786 /* Don't mess with insns declared volatile. */
2787 if (MEM_VOLATILE_P (x))
2791 fmt = GET_RTX_FORMAT (code);
2792 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2796 int tem = invariant_p (XEXP (x, i));
2802 else if (fmt[i] == 'E')
2805 for (j = 0; j < XVECLEN (x, i); j++)
2807 int tem = invariant_p (XVECEXP (x, i, j));
2817 return 1 + conditional;
2821 /* Return nonzero if all the insns in the loop that set REG
2822 are INSN and the immediately following insns,
2823 and if each of those insns sets REG in an invariant way
2824 (not counting uses of REG in them).
2826 The value is 2 if some of these insns are only conditionally invariant.
2828 We assume that INSN itself is the first set of REG
2829 and that its source is invariant. */
2832 consec_sets_invariant_p (reg, n_sets, insn)
2836 register rtx p = insn;
2837 register int regno = REGNO (reg);
2839 /* Number of sets we have to insist on finding after INSN. */
2840 int count = n_sets - 1;
2841 int old = n_times_set[regno];
2845 /* If N_SETS hit the limit, we can't rely on its value. */
2849 n_times_set[regno] = 0;
2853 register enum rtx_code code;
2857 code = GET_CODE (p);
2859 /* If library call, skip to end of of it. */
2860 if (code == INSN && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX)))
2865 && (set = single_set (p))
2866 && GET_CODE (SET_DEST (set)) == REG
2867 && REGNO (SET_DEST (set)) == regno)
2869 this = invariant_p (SET_SRC (set));
2872 else if (temp = find_reg_note (p, REG_EQUAL, NULL_RTX))
2874 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
2875 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
2877 this = (CONSTANT_P (XEXP (temp, 0))
2878 || (find_reg_note (p, REG_RETVAL, NULL_RTX)
2879 && invariant_p (XEXP (temp, 0))));
2886 else if (code != NOTE)
2888 n_times_set[regno] = old;
2893 n_times_set[regno] = old;
2894 /* If invariant_p ever returned 2, we return 2. */
2895 return 1 + (value & 2);
2899 /* I don't think this condition is sufficient to allow INSN
2900 to be moved, so we no longer test it. */
2902 /* Return 1 if all insns in the basic block of INSN and following INSN
2903 that set REG are invariant according to TABLE. */
2906 all_sets_invariant_p (reg, insn, table)
2910 register rtx p = insn;
2911 register int regno = REGNO (reg);
2915 register enum rtx_code code;
2917 code = GET_CODE (p);
2918 if (code == CODE_LABEL || code == JUMP_INSN)
2920 if (code == INSN && GET_CODE (PATTERN (p)) == SET
2921 && GET_CODE (SET_DEST (PATTERN (p))) == REG
2922 && REGNO (SET_DEST (PATTERN (p))) == regno)
2924 if (!invariant_p (SET_SRC (PATTERN (p)), table))
2931 /* Look at all uses (not sets) of registers in X. For each, if it is
2932 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
2933 a different insn, set USAGE[REGNO] to const0_rtx. */
2936 find_single_use_in_loop (insn, x, usage)
2941 enum rtx_code code = GET_CODE (x);
2942 char *fmt = GET_RTX_FORMAT (code);
2947 = (usage[REGNO (x)] != 0 && usage[REGNO (x)] != insn)
2948 ? const0_rtx : insn;
2950 else if (code == SET)
2952 /* Don't count SET_DEST if it is a REG; otherwise count things
2953 in SET_DEST because if a register is partially modified, it won't
2954 show up as a potential movable so we don't care how USAGE is set
2956 if (GET_CODE (SET_DEST (x)) != REG)
2957 find_single_use_in_loop (insn, SET_DEST (x), usage);
2958 find_single_use_in_loop (insn, SET_SRC (x), usage);
2961 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2963 if (fmt[i] == 'e' && XEXP (x, i) != 0)
2964 find_single_use_in_loop (insn, XEXP (x, i), usage);
2965 else if (fmt[i] == 'E')
2966 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2967 find_single_use_in_loop (insn, XVECEXP (x, i, j), usage);
2971 /* Increment N_TIMES_SET at the index of each register
2972 that is modified by an insn between FROM and TO.
2973 If the value of an element of N_TIMES_SET becomes 127 or more,
2974 stop incrementing it, to avoid overflow.
2976 Store in SINGLE_USAGE[I] the single insn in which register I is
2977 used, if it is only used once. Otherwise, it is set to 0 (for no
2978 uses) or const0_rtx for more than one use. This parameter may be zero,
2979 in which case this processing is not done.
2981 Store in *COUNT_PTR the number of actual instruction
2982 in the loop. We use this to decide what is worth moving out. */
2984 /* last_set[n] is nonzero iff reg n has been set in the current basic block.
2985 In that case, it is the insn that last set reg n. */
2988 count_loop_regs_set (from, to, may_not_move, single_usage, count_ptr, nregs)
2989 register rtx from, to;
2995 register rtx *last_set = (rtx *) alloca (nregs * sizeof (rtx));
2997 register int count = 0;
3000 bzero ((char *) last_set, nregs * sizeof (rtx));
3001 for (insn = from; insn != to; insn = NEXT_INSN (insn))
3003 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
3007 /* If requested, record registers that have exactly one use. */
3010 find_single_use_in_loop (insn, PATTERN (insn), single_usage);
3012 /* Include uses in REG_EQUAL notes. */
3013 if (REG_NOTES (insn))
3014 find_single_use_in_loop (insn, REG_NOTES (insn), single_usage);
3017 if (GET_CODE (PATTERN (insn)) == CLOBBER
3018 && GET_CODE (XEXP (PATTERN (insn), 0)) == REG)
3019 /* Don't move a reg that has an explicit clobber.
3020 We might do so sometimes, but it's not worth the pain. */
3021 may_not_move[REGNO (XEXP (PATTERN (insn), 0))] = 1;
3023 if (GET_CODE (PATTERN (insn)) == SET
3024 || GET_CODE (PATTERN (insn)) == CLOBBER)
3026 dest = SET_DEST (PATTERN (insn));
3027 while (GET_CODE (dest) == SUBREG
3028 || GET_CODE (dest) == ZERO_EXTRACT
3029 || GET_CODE (dest) == SIGN_EXTRACT
3030 || GET_CODE (dest) == STRICT_LOW_PART)
3031 dest = XEXP (dest, 0);
3032 if (GET_CODE (dest) == REG)
3034 register int regno = REGNO (dest);
3035 /* If this is the first setting of this reg
3036 in current basic block, and it was set before,
3037 it must be set in two basic blocks, so it cannot
3038 be moved out of the loop. */
3039 if (n_times_set[regno] > 0 && last_set[regno] == 0)
3040 may_not_move[regno] = 1;
3041 /* If this is not first setting in current basic block,
3042 see if reg was used in between previous one and this.
3043 If so, neither one can be moved. */
3044 if (last_set[regno] != 0
3045 && reg_used_between_p (dest, last_set[regno], insn))
3046 may_not_move[regno] = 1;
3047 if (n_times_set[regno] < 127)
3048 ++n_times_set[regno];
3049 last_set[regno] = insn;
3052 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
3055 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
3057 register rtx x = XVECEXP (PATTERN (insn), 0, i);
3058 if (GET_CODE (x) == CLOBBER && GET_CODE (XEXP (x, 0)) == REG)
3059 /* Don't move a reg that has an explicit clobber.
3060 It's not worth the pain to try to do it correctly. */
3061 may_not_move[REGNO (XEXP (x, 0))] = 1;
3063 if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
3065 dest = SET_DEST (x);
3066 while (GET_CODE (dest) == SUBREG
3067 || GET_CODE (dest) == ZERO_EXTRACT
3068 || GET_CODE (dest) == SIGN_EXTRACT
3069 || GET_CODE (dest) == STRICT_LOW_PART)
3070 dest = XEXP (dest, 0);
3071 if (GET_CODE (dest) == REG)
3073 register int regno = REGNO (dest);
3074 if (n_times_set[regno] > 0 && last_set[regno] == 0)
3075 may_not_move[regno] = 1;
3076 if (last_set[regno] != 0
3077 && reg_used_between_p (dest, last_set[regno], insn))
3078 may_not_move[regno] = 1;
3079 if (n_times_set[regno] < 127)
3080 ++n_times_set[regno];
3081 last_set[regno] = insn;
3088 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
3089 bzero ((char *) last_set, nregs * sizeof (rtx));
3094 /* Given a loop that is bounded by LOOP_START and LOOP_END
3095 and that is entered at SCAN_START,
3096 return 1 if the register set in SET contained in insn INSN is used by
3097 any insn that precedes INSN in cyclic order starting
3098 from the loop entry point.
3100 We don't want to use INSN_LUID here because if we restrict INSN to those
3101 that have a valid INSN_LUID, it means we cannot move an invariant out
3102 from an inner loop past two loops. */
3105 loop_reg_used_before_p (set, insn, loop_start, scan_start, loop_end)
3106 rtx set, insn, loop_start, scan_start, loop_end;
3108 rtx reg = SET_DEST (set);
3111 /* Scan forward checking for register usage. If we hit INSN, we
3112 are done. Otherwise, if we hit LOOP_END, wrap around to LOOP_START. */
3113 for (p = scan_start; p != insn; p = NEXT_INSN (p))
3115 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
3116 && reg_overlap_mentioned_p (reg, PATTERN (p)))
3126 /* A "basic induction variable" or biv is a pseudo reg that is set
3127 (within this loop) only by incrementing or decrementing it. */
3128 /* A "general induction variable" or giv is a pseudo reg whose
3129 value is a linear function of a biv. */
3131 /* Bivs are recognized by `basic_induction_var';
3132 Givs by `general_induct_var'. */
3134 /* Indexed by register number, indicates whether or not register is an
3135 induction variable, and if so what type. */
3137 enum iv_mode *reg_iv_type;
3139 /* Indexed by register number, contains pointer to `struct induction'
3140 if register is an induction variable. This holds general info for
3141 all induction variables. */
3143 struct induction **reg_iv_info;
3145 /* Indexed by register number, contains pointer to `struct iv_class'
3146 if register is a basic induction variable. This holds info describing
3147 the class (a related group) of induction variables that the biv belongs
3150 struct iv_class **reg_biv_class;
3152 /* The head of a list which links together (via the next field)
3153 every iv class for the current loop. */
3155 struct iv_class *loop_iv_list;
3157 /* Communication with routines called via `note_stores'. */
3159 static rtx note_insn;
3161 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3163 static rtx addr_placeholder;
3165 /* ??? Unfinished optimizations, and possible future optimizations,
3166 for the strength reduction code. */
3168 /* ??? There is one more optimization you might be interested in doing: to
3169 allocate pseudo registers for frequently-accessed memory locations.
3170 If the same memory location is referenced each time around, it might
3171 be possible to copy it into a register before and out after.
3172 This is especially useful when the memory location is a variable which
3173 is in a stack slot because somewhere its address is taken. If the
3174 loop doesn't contain a function call and the variable isn't volatile,
3175 it is safe to keep the value in a register for the duration of the
3176 loop. One tricky thing is that the copying of the value back from the
3177 register has to be done on all exits from the loop. You need to check that
3178 all the exits from the loop go to the same place. */
3180 /* ??? The interaction of biv elimination, and recognition of 'constant'
3181 bivs, may cause problems. */
3183 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3184 performance problems.
3186 Perhaps don't eliminate things that can be combined with an addressing
3187 mode. Find all givs that have the same biv, mult_val, and add_val;
3188 then for each giv, check to see if its only use dies in a following
3189 memory address. If so, generate a new memory address and check to see
3190 if it is valid. If it is valid, then store the modified memory address,
3191 otherwise, mark the giv as not done so that it will get its own iv. */
3193 /* ??? Could try to optimize branches when it is known that a biv is always
3196 /* ??? When replace a biv in a compare insn, we should replace with closest
3197 giv so that an optimized branch can still be recognized by the combiner,
3198 e.g. the VAX acb insn. */
3200 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3201 was rerun in loop_optimize whenever a register was added or moved.
3202 Also, some of the optimizations could be a little less conservative. */
3204 /* Perform strength reduction and induction variable elimination. */
3206 /* Pseudo registers created during this function will be beyond the last
3207 valid index in several tables including n_times_set and regno_last_uid.
3208 This does not cause a problem here, because the added registers cannot be
3209 givs outside of their loop, and hence will never be reconsidered.
3210 But scan_loop must check regnos to make sure they are in bounds. */
3213 strength_reduce (scan_start, end, loop_top, insn_count,
3214 loop_start, loop_end)
3227 /* This is 1 if current insn is not executed at least once for every loop
3229 int not_every_iteration = 0;
3230 /* This is 1 if current insn may be executed more than once for every
3232 int maybe_multiple = 0;
3233 /* Temporary list pointers for traversing loop_iv_list. */
3234 struct iv_class *bl, **backbl;
3235 /* Ratio of extra register life span we can justify
3236 for saving an instruction. More if loop doesn't call subroutines
3237 since in that case saving an insn makes more difference
3238 and more registers are available. */
3239 /* ??? could set this to last value of threshold in move_movables */
3240 int threshold = (loop_has_call ? 1 : 2) * (3 + n_non_fixed_regs);
3241 /* Map of pseudo-register replacements. */
3245 rtx end_insert_before;
3248 reg_iv_type = (enum iv_mode *) alloca (max_reg_before_loop
3249 * sizeof (enum iv_mode *));
3250 bzero ((char *) reg_iv_type, max_reg_before_loop * sizeof (enum iv_mode *));
3251 reg_iv_info = (struct induction **)
3252 alloca (max_reg_before_loop * sizeof (struct induction *));
3253 bzero ((char *) reg_iv_info, (max_reg_before_loop
3254 * sizeof (struct induction *)));
3255 reg_biv_class = (struct iv_class **)
3256 alloca (max_reg_before_loop * sizeof (struct iv_class *));
3257 bzero ((char *) reg_biv_class, (max_reg_before_loop
3258 * sizeof (struct iv_class *)));
3261 addr_placeholder = gen_reg_rtx (Pmode);
3263 /* Save insn immediately after the loop_end. Insns inserted after loop_end
3264 must be put before this insn, so that they will appear in the right
3265 order (i.e. loop order).
3267 If loop_end is the end of the current function, then emit a
3268 NOTE_INSN_DELETED after loop_end and set end_insert_before to the
3270 if (NEXT_INSN (loop_end) != 0)
3271 end_insert_before = NEXT_INSN (loop_end);
3273 end_insert_before = emit_note_after (NOTE_INSN_DELETED, loop_end);
3275 /* Scan through loop to find all possible bivs. */
3281 /* At end of a straight-in loop, we are done.
3282 At end of a loop entered at the bottom, scan the top. */
3283 if (p == scan_start)
3291 if (p == scan_start)
3295 if (GET_CODE (p) == INSN
3296 && (set = single_set (p))
3297 && GET_CODE (SET_DEST (set)) == REG)
3299 dest_reg = SET_DEST (set);
3300 if (REGNO (dest_reg) < max_reg_before_loop
3301 && REGNO (dest_reg) >= FIRST_PSEUDO_REGISTER
3302 && reg_iv_type[REGNO (dest_reg)] != NOT_BASIC_INDUCT)
3304 if (basic_induction_var (SET_SRC (set), GET_MODE (SET_SRC (set)),
3305 dest_reg, p, &inc_val, &mult_val))
3307 /* It is a possible basic induction variable.
3308 Create and initialize an induction structure for it. */
3311 = (struct induction *) alloca (sizeof (struct induction));
3313 record_biv (v, p, dest_reg, inc_val, mult_val,
3314 not_every_iteration, maybe_multiple);
3315 reg_iv_type[REGNO (dest_reg)] = BASIC_INDUCT;
3317 else if (REGNO (dest_reg) < max_reg_before_loop)
3318 reg_iv_type[REGNO (dest_reg)] = NOT_BASIC_INDUCT;
3322 /* Past CODE_LABEL, we get to insns that may be executed multiple
3323 times. The only way we can be sure that they can't is if every
3324 every jump insn between here and the end of the loop either
3325 returns, exits the loop, is a forward jump, or is a jump
3326 to the loop start. */
3328 if (GET_CODE (p) == CODE_LABEL)
3336 insn = NEXT_INSN (insn);
3337 if (insn == scan_start)
3345 if (insn == scan_start)
3349 if (GET_CODE (insn) == JUMP_INSN
3350 && GET_CODE (PATTERN (insn)) != RETURN
3351 && (! condjump_p (insn)
3352 || (JUMP_LABEL (insn) != 0
3353 && JUMP_LABEL (insn) != scan_start
3354 && (INSN_UID (JUMP_LABEL (insn)) >= max_uid_for_loop
3355 || INSN_UID (insn) >= max_uid_for_loop
3356 || (INSN_LUID (JUMP_LABEL (insn))
3357 < INSN_LUID (insn))))))
3365 /* Past a jump, we get to insns for which we can't count
3366 on whether they will be executed during each iteration. */
3367 /* This code appears twice in strength_reduce. There is also similar
3368 code in scan_loop. */
3369 if (GET_CODE (p) == JUMP_INSN
3370 /* If we enter the loop in the middle, and scan around to the
3371 beginning, don't set not_every_iteration for that.
3372 This can be any kind of jump, since we want to know if insns
3373 will be executed if the loop is executed. */
3374 && ! (JUMP_LABEL (p) == loop_top
3375 && ((NEXT_INSN (NEXT_INSN (p)) == loop_end && simplejump_p (p))
3376 || (NEXT_INSN (p) == loop_end && condjump_p (p)))))
3380 /* If this is a jump outside the loop, then it also doesn't
3381 matter. Check to see if the target of this branch is on the
3382 loop_number_exits_labels list. */
3384 for (label = loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]];
3386 label = LABEL_NEXTREF (label))
3387 if (XEXP (label, 0) == JUMP_LABEL (p))
3391 not_every_iteration = 1;
3394 else if (GET_CODE (p) == NOTE)
3396 /* At the virtual top of a converted loop, insns are again known to
3397 be executed each iteration: logically, the loop begins here
3398 even though the exit code has been duplicated. */
3399 if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP && loop_depth == 0)
3400 not_every_iteration = 0;
3401 else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG)
3403 else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)
3407 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3408 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3409 or not an insn is known to be executed each iteration of the
3410 loop, whether or not any iterations are known to occur.
3412 Therefore, if we have just passed a label and have no more labels
3413 between here and the test insn of the loop, we know these insns
3414 will be executed each iteration. */
3416 if (not_every_iteration && GET_CODE (p) == CODE_LABEL
3417 && no_labels_between_p (p, loop_end))
3418 not_every_iteration = 0;
3421 /* Scan loop_iv_list to remove all regs that proved not to be bivs.
3422 Make a sanity check against n_times_set. */
3423 for (backbl = &loop_iv_list, bl = *backbl; bl; bl = bl->next)
3425 if (reg_iv_type[bl->regno] != BASIC_INDUCT
3426 /* Above happens if register modified by subreg, etc. */
3427 /* Make sure it is not recognized as a basic induction var: */
3428 || n_times_set[bl->regno] != bl->biv_count
3429 /* If never incremented, it is invariant that we decided not to
3430 move. So leave it alone. */
3431 || ! bl->incremented)
3433 if (loop_dump_stream)
3434 fprintf (loop_dump_stream, "Reg %d: biv discarded, %s\n",
3436 (reg_iv_type[bl->regno] != BASIC_INDUCT
3437 ? "not induction variable"
3438 : (! bl->incremented ? "never incremented"
3441 reg_iv_type[bl->regno] = NOT_BASIC_INDUCT;
3448 if (loop_dump_stream)
3449 fprintf (loop_dump_stream, "Reg %d: biv verified\n", bl->regno);
3453 /* Exit if there are no bivs. */
3456 /* Can still unroll the loop anyways, but indicate that there is no
3457 strength reduction info available. */
3458 if (flag_unroll_loops)
3459 unroll_loop (loop_end, insn_count, loop_start, end_insert_before, 0);
3464 /* Find initial value for each biv by searching backwards from loop_start,
3465 halting at first label. Also record any test condition. */
3468 for (p = loop_start; p && GET_CODE (p) != CODE_LABEL; p = PREV_INSN (p))
3472 if (GET_CODE (p) == CALL_INSN)
3475 if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN
3476 || GET_CODE (p) == CALL_INSN)
3477 note_stores (PATTERN (p), record_initial);
3479 /* Record any test of a biv that branches around the loop if no store
3480 between it and the start of loop. We only care about tests with
3481 constants and registers and only certain of those. */
3482 if (GET_CODE (p) == JUMP_INSN
3483 && JUMP_LABEL (p) != 0
3484 && next_real_insn (JUMP_LABEL (p)) == next_real_insn (loop_end)
3485 && (test = get_condition_for_loop (p)) != 0
3486 && GET_CODE (XEXP (test, 0)) == REG
3487 && REGNO (XEXP (test, 0)) < max_reg_before_loop
3488 && (bl = reg_biv_class[REGNO (XEXP (test, 0))]) != 0
3489 && valid_initial_value_p (XEXP (test, 1), p, call_seen, loop_start)
3490 && bl->init_insn == 0)
3492 /* If an NE test, we have an initial value! */
3493 if (GET_CODE (test) == NE)
3496 bl->init_set = gen_rtx (SET, VOIDmode,
3497 XEXP (test, 0), XEXP (test, 1));
3500 bl->initial_test = test;
3504 /* Look at the each biv and see if we can say anything better about its
3505 initial value from any initializing insns set up above. (This is done
3506 in two passes to avoid missing SETs in a PARALLEL.) */
3507 for (bl = loop_iv_list; bl; bl = bl->next)
3511 if (! bl->init_insn)
3514 src = SET_SRC (bl->init_set);
3516 if (loop_dump_stream)
3517 fprintf (loop_dump_stream,
3518 "Biv %d initialized at insn %d: initial value ",
3519 bl->regno, INSN_UID (bl->init_insn));
3521 if ((GET_MODE (src) == GET_MODE (regno_reg_rtx[bl->regno])
3522 || GET_MODE (src) == VOIDmode)
3523 && valid_initial_value_p (src, bl->init_insn, call_seen, loop_start))
3525 bl->initial_value = src;
3527 if (loop_dump_stream)
3529 if (GET_CODE (src) == CONST_INT)
3530 fprintf (loop_dump_stream, "%d\n", INTVAL (src));
3533 print_rtl (loop_dump_stream, src);
3534 fprintf (loop_dump_stream, "\n");
3540 /* Biv initial value is not simple move,
3541 so let it keep initial value of "itself". */
3543 if (loop_dump_stream)
3544 fprintf (loop_dump_stream, "is complex\n");
3548 /* Search the loop for general induction variables. */
3550 /* A register is a giv if: it is only set once, it is a function of a
3551 biv and a constant (or invariant), and it is not a biv. */
3553 not_every_iteration = 0;
3559 /* At end of a straight-in loop, we are done.
3560 At end of a loop entered at the bottom, scan the top. */
3561 if (p == scan_start)
3569 if (p == scan_start)
3573 /* Look for a general induction variable in a register. */
3574 if (GET_CODE (p) == INSN
3575 && (set = single_set (p))
3576 && GET_CODE (SET_DEST (set)) == REG
3577 && ! may_not_optimize[REGNO (SET_DEST (set))])
3585 dest_reg = SET_DEST (set);
3586 if (REGNO (dest_reg) < FIRST_PSEUDO_REGISTER)
3589 if (/* SET_SRC is a giv. */
3590 ((benefit = general_induction_var (SET_SRC (set),
3593 /* Equivalent expression is a giv. */
3594 || ((regnote = find_reg_note (p, REG_EQUAL, NULL_RTX))
3595 && (benefit = general_induction_var (XEXP (regnote, 0),
3597 &add_val, &mult_val))))
3598 /* Don't try to handle any regs made by loop optimization.
3599 We have nothing on them in regno_first_uid, etc. */
3600 && REGNO (dest_reg) < max_reg_before_loop
3601 /* Don't recognize a BASIC_INDUCT_VAR here. */
3602 && dest_reg != src_reg
3603 /* This must be the only place where the register is set. */
3604 && (n_times_set[REGNO (dest_reg)] == 1
3605 /* or all sets must be consecutive and make a giv. */
3606 || (benefit = consec_sets_giv (benefit, p,
3608 &add_val, &mult_val))))
3612 = (struct induction *) alloca (sizeof (struct induction));
3615 /* If this is a library call, increase benefit. */
3616 if (find_reg_note (p, REG_RETVAL, NULL_RTX))
3617 benefit += libcall_benefit (p);
3619 /* Skip the consecutive insns, if there are any. */
3620 for (count = n_times_set[REGNO (dest_reg)] - 1;
3623 /* If first insn of libcall sequence, skip to end.
3624 Do this at start of loop, since INSN is guaranteed to
3626 if (GET_CODE (p) != NOTE
3627 && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX)))
3630 do p = NEXT_INSN (p);
3631 while (GET_CODE (p) == NOTE);
3634 record_giv (v, p, src_reg, dest_reg, mult_val, add_val, benefit,
3635 DEST_REG, not_every_iteration, NULL_PTR, loop_start,
3641 #ifndef DONT_REDUCE_ADDR
3642 /* Look for givs which are memory addresses. */
3643 /* This resulted in worse code on a VAX 8600. I wonder if it
3645 if (GET_CODE (p) == INSN)
3646 find_mem_givs (PATTERN (p), p, not_every_iteration, loop_start,
3650 /* Update the status of whether giv can derive other givs. This can
3651 change when we pass a label or an insn that updates a biv. */
3652 if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN
3653 || GET_CODE (p) == CODE_LABEL)
3654 update_giv_derive (p);
3656 /* Past a jump, we get to insns for which we can't count
3657 on whether they will be executed during each iteration. */
3658 /* This code appears twice in strength_reduce. There is also similar
3659 code in scan_loop. */
3660 if (GET_CODE (p) == JUMP_INSN
3661 /* If we enter the loop in the middle, and scan around to the
3662 beginning, don't set not_every_iteration for that.
3663 This can be any kind of jump, since we want to know if insns
3664 will be executed if the loop is executed. */
3665 && ! (JUMP_LABEL (p) == loop_top
3666 && ((NEXT_INSN (NEXT_INSN (p)) == loop_end && simplejump_p (p))
3667 || (NEXT_INSN (p) == loop_end && condjump_p (p)))))
3671 /* If this is a jump outside the loop, then it also doesn't
3672 matter. Check to see if the target of this branch is on the
3673 loop_number_exits_labels list. */
3675 for (label = loop_number_exit_labels[uid_loop_num[INSN_UID (loop_start)]];
3677 label = LABEL_NEXTREF (label))
3678 if (XEXP (label, 0) == JUMP_LABEL (p))
3682 not_every_iteration = 1;
3685 else if (GET_CODE (p) == NOTE)
3687 /* At the virtual top of a converted loop, insns are again known to
3688 be executed each iteration: logically, the loop begins here
3689 even though the exit code has been duplicated. */
3690 if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_VTOP && loop_depth == 0)
3691 not_every_iteration = 0;
3692 else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG)
3694 else if (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)
3698 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3699 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3700 or not an insn is known to be executed each iteration of the
3701 loop, whether or not any iterations are known to occur.
3703 Therefore, if we have just passed a label and have no more labels
3704 between here and the test insn of the loop, we know these insns
3705 will be executed each iteration. */
3707 if (not_every_iteration && GET_CODE (p) == CODE_LABEL
3708 && no_labels_between_p (p, loop_end))
3709 not_every_iteration = 0;
3712 /* Try to calculate and save the number of loop iterations. This is
3713 set to zero if the actual number can not be calculated. This must
3714 be called after all giv's have been identified, since otherwise it may
3715 fail if the iteration variable is a giv. */
3717 loop_n_iterations = loop_iterations (loop_start, loop_end);
3719 /* Now for each giv for which we still don't know whether or not it is
3720 replaceable, check to see if it is replaceable because its final value
3721 can be calculated. This must be done after loop_iterations is called,
3722 so that final_giv_value will work correctly. */
3724 for (bl = loop_iv_list; bl; bl = bl->next)
3726 struct induction *v;
3728 for (v = bl->giv; v; v = v->next_iv)
3729 if (! v->replaceable && ! v->not_replaceable)
3730 check_final_value (v, loop_start, loop_end);
3733 /* Try to prove that the loop counter variable (if any) is always
3734 nonnegative; if so, record that fact with a REG_NONNEG note
3735 so that "decrement and branch until zero" insn can be used. */
3736 check_dbra_loop (loop_end, insn_count, loop_start);
3738 /* Create reg_map to hold substitutions for replaceable giv regs. */
3739 reg_map = (rtx *) alloca (max_reg_before_loop * sizeof (rtx));
3740 bzero ((char *) reg_map, max_reg_before_loop * sizeof (rtx));
3742 /* Examine each iv class for feasibility of strength reduction/induction
3743 variable elimination. */
3745 for (bl = loop_iv_list; bl; bl = bl->next)
3747 struct induction *v;
3750 rtx final_value = 0;
3752 /* Test whether it will be possible to eliminate this biv
3753 provided all givs are reduced. This is possible if either
3754 the reg is not used outside the loop, or we can compute
3755 what its final value will be.
3757 For architectures with a decrement_and_branch_until_zero insn,
3758 don't do this if we put a REG_NONNEG note on the endtest for
3761 /* Compare against bl->init_insn rather than loop_start.
3762 We aren't concerned with any uses of the biv between
3763 init_insn and loop_start since these won't be affected
3764 by the value of the biv elsewhere in the function, so
3765 long as init_insn doesn't use the biv itself.
3766 March 14, 1989 -- self@bayes.arc.nasa.gov */
3768 if ((uid_luid[regno_last_uid[bl->regno]] < INSN_LUID (loop_end)
3770 && INSN_UID (bl->init_insn) < max_uid_for_loop
3771 && uid_luid[regno_first_uid[bl->regno]] >= INSN_LUID (bl->init_insn)
3772 #ifdef HAVE_decrement_and_branch_until_zero
3775 && ! reg_mentioned_p (bl->biv->dest_reg, SET_SRC (bl->init_set)))
3776 || ((final_value = final_biv_value (bl, loop_start, loop_end))
3777 #ifdef HAVE_decrement_and_branch_until_zero
3781 bl->eliminable = maybe_eliminate_biv (bl, loop_start, end, 0,
3782 threshold, insn_count);
3785 if (loop_dump_stream)
3787 fprintf (loop_dump_stream,
3788 "Cannot eliminate biv %d.\n",
3790 fprintf (loop_dump_stream,
3791 "First use: insn %d, last use: insn %d.\n",
3792 regno_first_uid[bl->regno],
3793 regno_last_uid[bl->regno]);
3797 /* Combine all giv's for this iv_class. */
3800 /* This will be true at the end, if all givs which depend on this
3801 biv have been strength reduced.
3802 We can't (currently) eliminate the biv unless this is so. */
3805 /* Check each giv in this class to see if we will benefit by reducing
3806 it. Skip giv's combined with others. */
3807 for (v = bl->giv; v; v = v->next_iv)
3809 struct induction *tv;
3811 if (v->ignore || v->same)
3814 benefit = v->benefit;
3816 /* Reduce benefit if not replaceable, since we will insert
3817 a move-insn to replace the insn that calculates this giv.
3818 Don't do this unless the giv is a user variable, since it
3819 will often be marked non-replaceable because of the duplication
3820 of the exit code outside the loop. In such a case, the copies
3821 we insert are dead and will be deleted. So they don't have
3822 a cost. Similar situations exist. */
3823 /* ??? The new final_[bg]iv_value code does a much better job
3824 of finding replaceable giv's, and hence this code may no longer
3826 if (! v->replaceable && ! bl->eliminable
3827 && REG_USERVAR_P (v->dest_reg))
3828 benefit -= copy_cost;
3830 /* Decrease the benefit to count the add-insns that we will
3831 insert to increment the reduced reg for the giv. */
3832 benefit -= add_cost * bl->biv_count;
3834 /* Decide whether to strength-reduce this giv or to leave the code
3835 unchanged (recompute it from the biv each time it is used).
3836 This decision can be made independently for each giv. */
3838 /* ??? Perhaps attempt to guess whether autoincrement will handle
3839 some of the new add insns; if so, can increase BENEFIT
3840 (undo the subtraction of add_cost that was done above). */
3842 /* If an insn is not to be strength reduced, then set its ignore
3843 flag, and clear all_reduced. */
3845 /* A giv that depends on a reversed biv must be reduced if it is
3846 used after the loop exit, otherwise, it would have the wrong
3847 value after the loop exit. To make it simple, just reduce all
3848 of such giv's whether or not we know they are used after the loop
3851 if (v->lifetime * threshold * benefit < insn_count
3854 if (loop_dump_stream)
3855 fprintf (loop_dump_stream,
3856 "giv of insn %d not worth while, %d vs %d.\n",
3858 v->lifetime * threshold * benefit, insn_count);
3864 /* Check that we can increment the reduced giv without a
3865 multiply insn. If not, reject it. */
3867 for (tv = bl->biv; tv; tv = tv->next_iv)
3868 if (tv->mult_val == const1_rtx
3869 && ! product_cheap_p (tv->add_val, v->mult_val))
3871 if (loop_dump_stream)
3872 fprintf (loop_dump_stream,
3873 "giv of insn %d: would need a multiply.\n",
3874 INSN_UID (v->insn));
3882 /* Reduce each giv that we decided to reduce. */
3884 for (v = bl->giv; v; v = v->next_iv)
3886 struct induction *tv;
3887 if (! v->ignore && v->same == 0)
3889 int auto_inc_opt = 0;
3891 v->new_reg = gen_reg_rtx (v->mode);
3894 /* If the target has auto-increment addressing modes, and
3895 this is an address giv, then try to put the increment
3896 immediately after its use, so that flow can create an
3897 auto-increment addressing mode. */
3898 if (v->giv_type == DEST_ADDR && bl->biv_count == 1
3899 && bl->biv->always_executed
3900 && ! bl->biv->maybe_multiple
3901 && v->always_executed && ! v->maybe_multiple)
3903 /* If other giv's have been combined with this one, then
3904 this will work only if all uses of the other giv's occur
3905 before this giv's insn. This is difficult to check.
3907 We simplify this by looking for the common case where
3908 there is one DEST_REG giv, and this giv's insn is the
3909 last use of the dest_reg of that DEST_REG giv. If the
3910 the increment occurs after the address giv, then we can
3911 perform the optimization. (Otherwise, the increment
3912 would have to go before other_giv, and we would not be
3913 able to combine it with the address giv to get an
3914 auto-inc address.) */
3915 if (v->combined_with)
3917 struct induction *other_giv = 0;
3919 for (tv = bl->giv; tv; tv = tv->next_iv)
3927 if (! tv && other_giv
3928 && (regno_last_uid[REGNO (other_giv->dest_reg)]
3929 == INSN_UID (v->insn))
3930 && INSN_LUID (v->insn) < INSN_LUID (bl->biv->insn))
3933 /* Check for case where increment is before the the address
3935 else if (INSN_LUID (v->insn) > INSN_LUID (bl->biv->insn))
3941 /* We can't put an insn immediately after one setting
3942 cc0, or immediately before one using cc0. */
3943 if ((auto_inc_opt == 1 && sets_cc0_p (PATTERN (v->insn)))
3944 || (auto_inc_opt == -1
3945 && sets_cc0_p (PATTERN (prev_nonnote_insn (v->insn)))))
3950 v->auto_inc_opt = 1;
3954 /* For each place where the biv is incremented, add an insn
3955 to increment the new, reduced reg for the giv. */
3956 for (tv = bl->biv; tv; tv = tv->next_iv)
3961 insert_before = tv->insn;
3962 else if (auto_inc_opt == 1)
3963 insert_before = NEXT_INSN (v->insn);
3965 insert_before = v->insn;
3967 if (tv->mult_val == const1_rtx)
3968 emit_iv_add_mult (tv->add_val, v->mult_val,
3969 v->new_reg, v->new_reg, insert_before);
3970 else /* tv->mult_val == const0_rtx */
3971 /* A multiply is acceptable here
3972 since this is presumed to be seldom executed. */
3973 emit_iv_add_mult (tv->add_val, v->mult_val,
3974 v->add_val, v->new_reg, insert_before);
3977 /* Add code at loop start to initialize giv's reduced reg. */
3979 emit_iv_add_mult (bl->initial_value, v->mult_val,
3980 v->add_val, v->new_reg, loop_start);
3984 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
3987 For each giv register that can be reduced now: if replaceable,
3988 substitute reduced reg wherever the old giv occurs;
3989 else add new move insn "giv_reg = reduced_reg".
3991 Also check for givs whose first use is their definition and whose
3992 last use is the definition of another giv. If so, it is likely
3993 dead and should not be used to eliminate a biv. */
3994 for (v = bl->giv; v; v = v->next_iv)
3996 if (v->same && v->same->ignore)
4002 if (v->giv_type == DEST_REG
4003 && regno_first_uid[REGNO (v->dest_reg)] == INSN_UID (v->insn))
4005 struct induction *v1;
4007 for (v1 = bl->giv; v1; v1 = v1->next_iv)
4008 if (regno_last_uid[REGNO (v->dest_reg)] == INSN_UID (v1->insn))
4012 /* Update expression if this was combined, in case other giv was
4015 v->new_reg = replace_rtx (v->new_reg,
4016 v->same->dest_reg, v->same->new_reg);
4018 if (v->giv_type == DEST_ADDR)
4019 /* Store reduced reg as the address in the memref where we found
4021 validate_change (v->insn, v->location, v->new_reg, 0);
4022 else if (v->replaceable)
4024 reg_map[REGNO (v->dest_reg)] = v->new_reg;
4027 /* I can no longer duplicate the original problem. Perhaps
4028 this is unnecessary now? */
4030 /* Replaceable; it isn't strictly necessary to delete the old
4031 insn and emit a new one, because v->dest_reg is now dead.
4033 However, especially when unrolling loops, the special
4034 handling for (set REG0 REG1) in the second cse pass may
4035 make v->dest_reg live again. To avoid this problem, emit
4036 an insn to set the original giv reg from the reduced giv.
4037 We can not delete the original insn, since it may be part
4038 of a LIBCALL, and the code in flow that eliminates dead
4039 libcalls will fail if it is deleted. */
4040 emit_insn_after (gen_move_insn (v->dest_reg, v->new_reg),
4046 /* Not replaceable; emit an insn to set the original giv reg from
4047 the reduced giv, same as above. */
4048 emit_insn_after (gen_move_insn (v->dest_reg, v->new_reg),
4052 /* When a loop is reversed, givs which depend on the reversed
4053 biv, and which are live outside the loop, must be set to their
4054 correct final value. This insn is only needed if the giv is
4055 not replaceable. The correct final value is the same as the
4056 value that the giv starts the reversed loop with. */
4057 if (bl->reversed && ! v->replaceable)
4058 emit_iv_add_mult (bl->initial_value, v->mult_val,
4059 v->add_val, v->dest_reg, end_insert_before);
4060 else if (v->final_value)
4064 /* If the loop has multiple exits, emit the insn before the
4065 loop to ensure that it will always be executed no matter
4066 how the loop exits. Otherwise, emit the insn after the loop,
4067 since this is slightly more efficient. */
4068 if (loop_number_exit_count[uid_loop_num[INSN_UID (loop_start)]])
4069 insert_before = loop_start;
4071 insert_before = end_insert_before;
4072 emit_insn_before (gen_move_insn (v->dest_reg, v->final_value),
4076 /* If the insn to set the final value of the giv was emitted
4077 before the loop, then we must delete the insn inside the loop
4078 that sets it. If this is a LIBCALL, then we must delete
4079 every insn in the libcall. Note, however, that
4080 final_giv_value will only succeed when there are multiple
4081 exits if the giv is dead at each exit, hence it does not
4082 matter that the original insn remains because it is dead
4084 /* Delete the insn inside the loop that sets the giv since
4085 the giv is now set before (or after) the loop. */
4086 delete_insn (v->insn);
4090 if (loop_dump_stream)
4092 fprintf (loop_dump_stream, "giv at %d reduced to ",
4093 INSN_UID (v->insn));
4094 print_rtl (loop_dump_stream, v->new_reg);
4095 fprintf (loop_dump_stream, "\n");
4099 /* All the givs based on the biv bl have been reduced if they
4102 /* For each giv not marked as maybe dead that has been combined with a
4103 second giv, clear any "maybe dead" mark on that second giv.
4104 v->new_reg will either be or refer to the register of the giv it
4107 Doing this clearing avoids problems in biv elimination where a
4108 giv's new_reg is a complex value that can't be put in the insn but
4109 the giv combined with (with a reg as new_reg) is marked maybe_dead.
4110 Since the register will be used in either case, we'd prefer it be
4111 used from the simpler giv. */
4113 for (v = bl->giv; v; v = v->next_iv)
4114 if (! v->maybe_dead && v->same)
4115 v->same->maybe_dead = 0;
4117 /* Try to eliminate the biv, if it is a candidate.
4118 This won't work if ! all_reduced,
4119 since the givs we planned to use might not have been reduced.
4121 We have to be careful that we didn't initially think we could eliminate
4122 this biv because of a giv that we now think may be dead and shouldn't
4123 be used as a biv replacement.
4125 Also, there is the possibility that we may have a giv that looks
4126 like it can be used to eliminate a biv, but the resulting insn
4127 isn't valid. This can happen, for example, on the 88k, where a
4128 JUMP_INSN can compare a register only with zero. Attempts to
4129 replace it with a compare with a constant will fail.
4131 Note that in cases where this call fails, we may have replaced some
4132 of the occurrences of the biv with a giv, but no harm was done in
4133 doing so in the rare cases where it can occur. */
4135 if (all_reduced == 1 && bl->eliminable
4136 && maybe_eliminate_biv (bl, loop_start, end, 1,
4137 threshold, insn_count))
4140 /* ?? If we created a new test to bypass the loop entirely,
4141 or otherwise drop straight in, based on this test, then
4142 we might want to rewrite it also. This way some later
4143 pass has more hope of removing the initialization of this
4146 /* If final_value != 0, then the biv may be used after loop end
4147 and we must emit an insn to set it just in case.
4149 Reversed bivs already have an insn after the loop setting their
4150 value, so we don't need another one. We can't calculate the
4151 proper final value for such a biv here anyways. */
4152 if (final_value != 0 && ! bl->reversed)
4156 /* If the loop has multiple exits, emit the insn before the
4157 loop to ensure that it will always be executed no matter
4158 how the loop exits. Otherwise, emit the insn after the
4159 loop, since this is slightly more efficient. */
4160 if (loop_number_exit_count[uid_loop_num[INSN_UID (loop_start)]])
4161 insert_before = loop_start;
4163 insert_before = end_insert_before;
4165 emit_insn_before (gen_move_insn (bl->biv->dest_reg, final_value),
4170 /* Delete all of the instructions inside the loop which set
4171 the biv, as they are all dead. If is safe to delete them,
4172 because an insn setting a biv will never be part of a libcall. */
4173 /* However, deleting them will invalidate the regno_last_uid info,
4174 so keeping them around is more convenient. Final_biv_value
4175 will only succeed when there are multiple exits if the biv
4176 is dead at each exit, hence it does not matter that the original
4177 insn remains, because it is dead anyways. */
4178 for (v = bl->biv; v; v = v->next_iv)
4179 delete_insn (v->insn);
4182 if (loop_dump_stream)
4183 fprintf (loop_dump_stream, "Reg %d: biv eliminated\n",
4188 /* Go through all the instructions in the loop, making all the
4189 register substitutions scheduled in REG_MAP. */
4191 for (p = loop_start; p != end; p = NEXT_INSN (p))
4192 if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN
4193 || GET_CODE (p) == CALL_INSN)
4195 replace_regs (PATTERN (p), reg_map, max_reg_before_loop, 0);
4196 replace_regs (REG_NOTES (p), reg_map, max_reg_before_loop, 0);
4200 /* Unroll loops from within strength reduction so that we can use the
4201 induction variable information that strength_reduce has already
4204 if (flag_unroll_loops)
4205 unroll_loop (loop_end, insn_count, loop_start, end_insert_before, 1);
4207 if (loop_dump_stream)
4208 fprintf (loop_dump_stream, "\n");
4211 /* Return 1 if X is a valid source for an initial value (or as value being
4212 compared against in an initial test).
4214 X must be either a register or constant and must not be clobbered between
4215 the current insn and the start of the loop.
4217 INSN is the insn containing X. */
4220 valid_initial_value_p (x, insn, call_seen, loop_start)
4229 /* Only consider pseudos we know about initialized in insns whose luids
4231 if (GET_CODE (x) != REG
4232 || REGNO (x) >= max_reg_before_loop)
4235 /* Don't use call-clobbered registers across a call which clobbers it. On
4236 some machines, don't use any hard registers at all. */
4237 if (REGNO (x) < FIRST_PSEUDO_REGISTER
4238 #ifndef SMALL_REGISTER_CLASSES
4239 && call_used_regs[REGNO (x)] && call_seen
4244 /* Don't use registers that have been clobbered before the start of the
4246 if (reg_set_between_p (x, insn, loop_start))
4252 /* Scan X for memory refs and check each memory address
4253 as a possible giv. INSN is the insn whose pattern X comes from.
4254 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
4255 every loop iteration. */
4258 find_mem_givs (x, insn, not_every_iteration, loop_start, loop_end)
4261 int not_every_iteration;
4262 rtx loop_start, loop_end;
4265 register enum rtx_code code;
4271 code = GET_CODE (x);
4295 benefit = general_induction_var (XEXP (x, 0),
4296 &src_reg, &add_val, &mult_val);
4298 /* Don't make a DEST_ADDR giv with mult_val == 1 && add_val == 0.
4299 Such a giv isn't useful. */
4300 if (benefit > 0 && (mult_val != const1_rtx || add_val != const0_rtx))
4302 /* Found one; record it. */
4304 = (struct induction *) oballoc (sizeof (struct induction));
4306 record_giv (v, insn, src_reg, addr_placeholder, mult_val,
4307 add_val, benefit, DEST_ADDR, not_every_iteration,
4308 &XEXP (x, 0), loop_start, loop_end);
4310 v->mem_mode = GET_MODE (x);
4316 /* Recursively scan the subexpressions for other mem refs. */
4318 fmt = GET_RTX_FORMAT (code);
4319 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4321 find_mem_givs (XEXP (x, i), insn, not_every_iteration, loop_start,
4323 else if (fmt[i] == 'E')
4324 for (j = 0; j < XVECLEN (x, i); j++)
4325 find_mem_givs (XVECEXP (x, i, j), insn, not_every_iteration,
4326 loop_start, loop_end);
4329 /* Fill in the data about one biv update.
4330 V is the `struct induction' in which we record the biv. (It is
4331 allocated by the caller, with alloca.)
4332 INSN is the insn that sets it.
4333 DEST_REG is the biv's reg.
4335 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
4336 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
4337 being set to INC_VAL.
4339 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
4340 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
4341 can be executed more than once per iteration. If MAYBE_MULTIPLE
4342 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
4343 executed exactly once per iteration. */
4346 record_biv (v, insn, dest_reg, inc_val, mult_val,
4347 not_every_iteration, maybe_multiple)
4348 struct induction *v;
4353 int not_every_iteration;
4356 struct iv_class *bl;
4359 v->src_reg = dest_reg;
4360 v->dest_reg = dest_reg;
4361 v->mult_val = mult_val;
4362 v->add_val = inc_val;
4363 v->mode = GET_MODE (dest_reg);
4364 v->always_computable = ! not_every_iteration;
4365 v->always_executed = ! not_every_iteration;
4366 v->maybe_multiple = maybe_multiple;
4368 /* Add this to the reg's iv_class, creating a class
4369 if this is the first incrementation of the reg. */
4371 bl = reg_biv_class[REGNO (dest_reg)];
4374 /* Create and initialize new iv_class. */
4376 bl = (struct iv_class *) oballoc (sizeof (struct iv_class));
4378 bl->regno = REGNO (dest_reg);
4384 /* Set initial value to the reg itself. */
4385 bl->initial_value = dest_reg;
4386 /* We haven't seen the initializing insn yet */
4389 bl->initial_test = 0;
4390 bl->incremented = 0;
4394 bl->total_benefit = 0;
4396 /* Add this class to loop_iv_list. */
4397 bl->next = loop_iv_list;
4400 /* Put it in the array of biv register classes. */
4401 reg_biv_class[REGNO (dest_reg)] = bl;
4404 /* Update IV_CLASS entry for this biv. */
4405 v->next_iv = bl->biv;
4408 if (mult_val == const1_rtx)
4409 bl->incremented = 1;
4411 if (loop_dump_stream)
4413 fprintf (loop_dump_stream,
4414 "Insn %d: possible biv, reg %d,",
4415 INSN_UID (insn), REGNO (dest_reg));
4416 if (GET_CODE (inc_val) == CONST_INT)
4417 fprintf (loop_dump_stream, " const = %d\n",
4421 fprintf (loop_dump_stream, " const = ");
4422 print_rtl (loop_dump_stream, inc_val);
4423 fprintf (loop_dump_stream, "\n");
4428 /* Fill in the data about one giv.
4429 V is the `struct induction' in which we record the giv. (It is
4430 allocated by the caller, with alloca.)
4431 INSN is the insn that sets it.
4432 BENEFIT estimates the savings from deleting this insn.
4433 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
4434 into a register or is used as a memory address.
4436 SRC_REG is the biv reg which the giv is computed from.
4437 DEST_REG is the giv's reg (if the giv is stored in a reg).
4438 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
4439 LOCATION points to the place where this giv's value appears in INSN. */
4442 record_giv (v, insn, src_reg, dest_reg, mult_val, add_val, benefit,
4443 type, not_every_iteration, location, loop_start, loop_end)
4444 struct induction *v;
4448 rtx mult_val, add_val;
4451 int not_every_iteration;
4453 rtx loop_start, loop_end;
4455 struct induction *b;
4456 struct iv_class *bl;
4457 rtx set = single_set (insn);
4461 v->src_reg = src_reg;
4463 v->dest_reg = dest_reg;
4464 v->mult_val = mult_val;
4465 v->add_val = add_val;
4466 v->benefit = benefit;
4467 v->location = location;
4469 v->combined_with = 0;
4470 v->maybe_multiple = 0;
4472 v->derive_adjustment = 0;
4478 v->auto_inc_opt = 0;
4480 /* The v->always_computable field is used in update_giv_derive, to
4481 determine whether a giv can be used to derive another giv. For a
4482 DEST_REG giv, INSN computes a new value for the giv, so its value
4483 isn't computable if INSN insn't executed every iteration.
4484 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
4485 it does not compute a new value. Hence the value is always computable
4486 regardless of whether INSN is executed each iteration. */
4488 if (type == DEST_ADDR)
4489 v->always_computable = 1;
4491 v->always_computable = ! not_every_iteration;
4493 v->always_executed = ! not_every_iteration;
4495 if (type == DEST_ADDR)
4497 v->mode = GET_MODE (*location);
4501 else /* type == DEST_REG */
4503 v->mode = GET_MODE (SET_DEST (set));
4505 v->lifetime = (uid_luid[regno_last_uid[REGNO (dest_reg)]]
4506 - uid_luid[regno_first_uid[REGNO (dest_reg)]]);
4508 v->times_used = n_times_used[REGNO (dest_reg)];
4510 /* If the lifetime is zero, it means that this register is
4511 really a dead store. So mark this as a giv that can be
4512 ignored. This will not prevent the biv from being eliminated. */
4513 if (v->lifetime == 0)
4516 reg_iv_type[REGNO (dest_reg)] = GENERAL_INDUCT;
4517 reg_iv_info[REGNO (dest_reg)] = v;
4520 /* Add the giv to the class of givs computed from one biv. */
4522 bl = reg_biv_class[REGNO (src_reg)];
4525 v->next_iv = bl->giv;
4527 /* Don't count DEST_ADDR. This is supposed to count the number of
4528 insns that calculate givs. */
4529 if (type == DEST_REG)
4531 bl->total_benefit += benefit;
4534 /* Fatal error, biv missing for this giv? */
4537 if (type == DEST_ADDR)
4541 /* The giv can be replaced outright by the reduced register only if all
4542 of the following conditions are true:
4543 - the insn that sets the giv is always executed on any iteration
4544 on which the giv is used at all
4545 (there are two ways to deduce this:
4546 either the insn is executed on every iteration,
4547 or all uses follow that insn in the same basic block),
4548 - the giv is not used outside the loop
4549 - no assignments to the biv occur during the giv's lifetime. */
4551 if (regno_first_uid[REGNO (dest_reg)] == INSN_UID (insn)
4552 /* Previous line always fails if INSN was moved by loop opt. */
4553 && uid_luid[regno_last_uid[REGNO (dest_reg)]] < INSN_LUID (loop_end)
4554 && (! not_every_iteration
4555 || last_use_this_basic_block (dest_reg, insn)))
4557 /* Now check that there are no assignments to the biv within the
4558 giv's lifetime. This requires two separate checks. */
4560 /* Check each biv update, and fail if any are between the first
4561 and last use of the giv.
4563 If this loop contains an inner loop that was unrolled, then
4564 the insn modifying the biv may have been emitted by the loop
4565 unrolling code, and hence does not have a valid luid. Just
4566 mark the biv as not replaceable in this case. It is not very
4567 useful as a biv, because it is used in two different loops.
4568 It is very unlikely that we would be able to optimize the giv
4569 using this biv anyways. */
4572 for (b = bl->biv; b; b = b->next_iv)
4574 if (INSN_UID (b->insn) >= max_uid_for_loop
4575 || ((uid_luid[INSN_UID (b->insn)]
4576 >= uid_luid[regno_first_uid[REGNO (dest_reg)]])
4577 && (uid_luid[INSN_UID (b->insn)]
4578 <= uid_luid[regno_last_uid[REGNO (dest_reg)]])))
4581 v->not_replaceable = 1;
4586 /* If there are any backwards branches that go from after the
4587 biv update to before it, then this giv is not replaceable. */
4589 for (b = bl->biv; b; b = b->next_iv)
4590 if (back_branch_in_range_p (b->insn, loop_start, loop_end))
4593 v->not_replaceable = 1;
4599 /* May still be replaceable, we don't have enough info here to
4602 v->not_replaceable = 0;
4606 if (loop_dump_stream)
4608 if (type == DEST_REG)
4609 fprintf (loop_dump_stream, "Insn %d: giv reg %d",
4610 INSN_UID (insn), REGNO (dest_reg));
4612 fprintf (loop_dump_stream, "Insn %d: dest address",
4615 fprintf (loop_dump_stream, " src reg %d benefit %d",
4616 REGNO (src_reg), v->benefit);
4617 fprintf (loop_dump_stream, " used %d lifetime %d",
4618 v->times_used, v->lifetime);
4621 fprintf (loop_dump_stream, " replaceable");
4623 if (GET_CODE (mult_val) == CONST_INT)
4624 fprintf (loop_dump_stream, " mult %d",
4628 fprintf (loop_dump_stream, " mult ");
4629 print_rtl (loop_dump_stream, mult_val);
4632 if (GET_CODE (add_val) == CONST_INT)
4633 fprintf (loop_dump_stream, " add %d",
4637 fprintf (loop_dump_stream, " add ");
4638 print_rtl (loop_dump_stream, add_val);
4642 if (loop_dump_stream)
4643 fprintf (loop_dump_stream, "\n");
4648 /* All this does is determine whether a giv can be made replaceable because
4649 its final value can be calculated. This code can not be part of record_giv
4650 above, because final_giv_value requires that the number of loop iterations
4651 be known, and that can not be accurately calculated until after all givs
4652 have been identified. */
4655 check_final_value (v, loop_start, loop_end)
4656 struct induction *v;
4657 rtx loop_start, loop_end;
4659 struct iv_class *bl;
4660 rtx final_value = 0;
4662 bl = reg_biv_class[REGNO (v->src_reg)];
4664 /* DEST_ADDR givs will never reach here, because they are always marked
4665 replaceable above in record_giv. */
4667 /* The giv can be replaced outright by the reduced register only if all
4668 of the following conditions are true:
4669 - the insn that sets the giv is always executed on any iteration
4670 on which the giv is used at all
4671 (there are two ways to deduce this:
4672 either the insn is executed on every iteration,
4673 or all uses follow that insn in the same basic block),
4674 - its final value can be calculated (this condition is different
4675 than the one above in record_giv)
4676 - no assignments to the biv occur during the giv's lifetime. */
4679 /* This is only called now when replaceable is known to be false. */
4680 /* Clear replaceable, so that it won't confuse final_giv_value. */
4684 if ((final_value = final_giv_value (v, loop_start, loop_end))
4685 && (v->always_computable || last_use_this_basic_block (v->dest_reg, v->insn)))
4687 int biv_increment_seen = 0;
4693 /* When trying to determine whether or not a biv increment occurs
4694 during the lifetime of the giv, we can ignore uses of the variable
4695 outside the loop because final_value is true. Hence we can not
4696 use regno_last_uid and regno_first_uid as above in record_giv. */
4698 /* Search the loop to determine whether any assignments to the
4699 biv occur during the giv's lifetime. Start with the insn
4700 that sets the giv, and search around the loop until we come
4701 back to that insn again.
4703 Also fail if there is a jump within the giv's lifetime that jumps
4704 to somewhere outside the lifetime but still within the loop. This
4705 catches spaghetti code where the execution order is not linear, and
4706 hence the above test fails. Here we assume that the giv lifetime
4707 does not extend from one iteration of the loop to the next, so as
4708 to make the test easier. Since the lifetime isn't known yet,
4709 this requires two loops. See also record_giv above. */
4711 last_giv_use = v->insn;
4717 p = NEXT_INSN (loop_start);
4721 if (GET_CODE (p) == INSN || GET_CODE (p) == JUMP_INSN
4722 || GET_CODE (p) == CALL_INSN)
4724 if (biv_increment_seen)
4726 if (reg_mentioned_p (v->dest_reg, PATTERN (p)))
4729 v->not_replaceable = 1;
4733 else if (GET_CODE (PATTERN (p)) == SET
4734 && SET_DEST (PATTERN (p)) == v->src_reg)
4735 biv_increment_seen = 1;
4736 else if (reg_mentioned_p (v->dest_reg, PATTERN (p)))
4741 /* Now that the lifetime of the giv is known, check for branches
4742 from within the lifetime to outside the lifetime if it is still
4752 p = NEXT_INSN (loop_start);
4753 if (p == last_giv_use)
4756 if (GET_CODE (p) == JUMP_INSN && JUMP_LABEL (p)
4757 && LABEL_NAME (JUMP_LABEL (p))
4758 && ((INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (v->insn)
4759 && INSN_LUID (JUMP_LABEL (p)) > INSN_LUID (loop_start))
4760 || (INSN_LUID (JUMP_LABEL (p)) > INSN_LUID (last_giv_use)
4761 && INSN_LUID (JUMP_LABEL (p)) < INSN_LUID (loop_end))))
4764 v->not_replaceable = 1;
4766 if (loop_dump_stream)
4767 fprintf (loop_dump_stream,
4768 "Found branch outside giv lifetime.\n");
4775 /* If it is replaceable, then save the final value. */
4777 v->final_value = final_value;
4780 if (loop_dump_stream && v->replaceable)
4781 fprintf (loop_dump_stream, "Insn %d: giv reg %d final_value replaceable\n",
4782 INSN_UID (v->insn), REGNO (v->dest_reg));
4785 /* Update the status of whether a giv can derive other givs.
4787 We need to do something special if there is or may be an update to the biv
4788 between the time the giv is defined and the time it is used to derive
4791 In addition, a giv that is only conditionally set is not allowed to
4792 derive another giv once a label has been passed.
4794 The cases we look at are when a label or an update to a biv is passed. */
4797 update_giv_derive (p)
4800 struct iv_class *bl;
4801 struct induction *biv, *giv;
4805 /* Search all IV classes, then all bivs, and finally all givs.
4807 There are three cases we are concerned with. First we have the situation
4808 of a giv that is only updated conditionally. In that case, it may not
4809 derive any givs after a label is passed.
4811 The second case is when a biv update occurs, or may occur, after the
4812 definition of a giv. For certain biv updates (see below) that are
4813 known to occur between the giv definition and use, we can adjust the
4814 giv definition. For others, or when the biv update is conditional,
4815 we must prevent the giv from deriving any other givs. There are two
4816 sub-cases within this case.
4818 If this is a label, we are concerned with any biv update that is done
4819 conditionally, since it may be done after the giv is defined followed by
4820 a branch here (actually, we need to pass both a jump and a label, but
4821 this extra tracking doesn't seem worth it).
4823 If this is a jump, we are concerned about any biv update that may be
4824 executed multiple times. We are actually only concerned about
4825 backward jumps, but it is probably not worth performing the test
4826 on the jump again here.
4828 If this is a biv update, we must adjust the giv status to show that a
4829 subsequent biv update was performed. If this adjustment cannot be done,
4830 the giv cannot derive further givs. */
4832 for (bl = loop_iv_list; bl; bl = bl->next)
4833 for (biv = bl->biv; biv; biv = biv->next_iv)
4834 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
4837 for (giv = bl->giv; giv; giv = giv->next_iv)
4839 /* If cant_derive is already true, there is no point in
4840 checking all of these conditions again. */
4841 if (giv->cant_derive)
4844 /* If this giv is conditionally set and we have passed a label,
4845 it cannot derive anything. */
4846 if (GET_CODE (p) == CODE_LABEL && ! giv->always_computable)
4847 giv->cant_derive = 1;
4849 /* Skip givs that have mult_val == 0, since
4850 they are really invariants. Also skip those that are
4851 replaceable, since we know their lifetime doesn't contain
4853 else if (giv->mult_val == const0_rtx || giv->replaceable)
4856 /* The only way we can allow this giv to derive another
4857 is if this is a biv increment and we can form the product
4858 of biv->add_val and giv->mult_val. In this case, we will
4859 be able to compute a compensation. */
4860 else if (biv->insn == p)
4864 if (biv->mult_val == const1_rtx)
4865 tem = simplify_giv_expr (gen_rtx (MULT, giv->mode,
4870 if (tem && giv->derive_adjustment)
4871 tem = simplify_giv_expr (gen_rtx (PLUS, giv->mode, tem,
4872 giv->derive_adjustment),
4875 giv->derive_adjustment = tem;
4877 giv->cant_derive = 1;
4879 else if ((GET_CODE (p) == CODE_LABEL && ! biv->always_computable)
4880 || (GET_CODE (p) == JUMP_INSN && biv->maybe_multiple))
4881 giv->cant_derive = 1;
4886 /* Check whether an insn is an increment legitimate for a basic induction var.
4887 X is the source of insn P, or a part of it.
4888 MODE is the mode in which X should be interpreted.
4890 DEST_REG is the putative biv, also the destination of the insn.
4891 We accept patterns of these forms:
4892 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
4893 REG = INVARIANT + REG
4895 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
4896 and store the additive term into *INC_VAL.
4898 If X is an assignment of an invariant into DEST_REG, we set
4899 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
4901 We also want to detect a BIV when it corresponds to a variable
4902 whose mode was promoted via PROMOTED_MODE. In that case, an increment
4903 of the variable may be a PLUS that adds a SUBREG of that variable to
4904 an invariant and then sign- or zero-extends the result of the PLUS
4907 Most GIVs in such cases will be in the promoted mode, since that is the
4908 probably the natural computation mode (and almost certainly the mode
4909 used for addresses) on the machine. So we view the pseudo-reg containing
4910 the variable as the BIV, as if it were simply incremented.
4912 Note that treating the entire pseudo as a BIV will result in making
4913 simple increments to any GIVs based on it. However, if the variable
4914 overflows in its declared mode but not its promoted mode, the result will
4915 be incorrect. This is acceptable if the variable is signed, since
4916 overflows in such cases are undefined, but not if it is unsigned, since
4917 those overflows are defined. So we only check for SIGN_EXTEND and
4920 If we cannot find a biv, we return 0. */
4923 basic_induction_var (x, mode, dest_reg, p, inc_val, mult_val)
4925 enum machine_mode mode;
4931 register enum rtx_code code;
4935 code = GET_CODE (x);
4939 if (XEXP (x, 0) == dest_reg
4940 || (GET_CODE (XEXP (x, 0)) == SUBREG
4941 && SUBREG_PROMOTED_VAR_P (XEXP (x, 0))
4942 && SUBREG_REG (XEXP (x, 0)) == dest_reg))
4944 else if (XEXP (x, 1) == dest_reg
4945 || (GET_CODE (XEXP (x, 1)) == SUBREG
4946 && SUBREG_PROMOTED_VAR_P (XEXP (x, 1))
4947 && SUBREG_REG (XEXP (x, 1)) == dest_reg))
4952 if (invariant_p (arg) != 1)
4955 *inc_val = convert_modes (GET_MODE (dest_reg), GET_MODE (x), arg, 0);
4956 *mult_val = const1_rtx;
4960 /* If this is a SUBREG for a promoted variable, check the inner
4962 if (SUBREG_PROMOTED_VAR_P (x))
4963 return basic_induction_var (SUBREG_REG (x), GET_MODE (SUBREG_REG (x)),
4964 dest_reg, p, inc_val, mult_val);
4967 /* If this register is assigned in the previous insn, look at its
4968 source, but don't go outside the loop or past a label. */
4970 for (insn = PREV_INSN (p);
4971 (insn && GET_CODE (insn) == NOTE
4972 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG);
4973 insn = PREV_INSN (insn))
4977 set = single_set (insn);
4980 && (SET_DEST (set) == x
4981 || (GET_CODE (SET_DEST (set)) == SUBREG
4982 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
4984 && SUBREG_REG (SET_DEST (set)) == x)))
4985 return basic_induction_var (SET_SRC (set),
4986 (GET_MODE (SET_SRC (set)) == VOIDmode
4988 : GET_MODE (SET_SRC (set))),
4991 /* ... fall through ... */
4993 /* Can accept constant setting of biv only when inside inner most loop.
4994 Otherwise, a biv of an inner loop may be incorrectly recognized
4995 as a biv of the outer loop,
4996 causing code to be moved INTO the inner loop. */
4998 if (invariant_p (x) != 1)
5003 if (loops_enclosed == 1)
5005 /* Possible bug here? Perhaps we don't know the mode of X. */
5006 *inc_val = convert_modes (GET_MODE (dest_reg), mode, x, 0);
5007 *mult_val = const0_rtx;
5014 return basic_induction_var (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5015 dest_reg, p, inc_val, mult_val);
5017 /* Similar, since this can be a sign extension. */
5018 for (insn = PREV_INSN (p);
5019 (insn && GET_CODE (insn) == NOTE
5020 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_LOOP_BEG);
5021 insn = PREV_INSN (insn))
5025 set = single_set (insn);
5027 if (set && SET_DEST (set) == XEXP (x, 0)
5028 && GET_CODE (XEXP (x, 1)) == CONST_INT
5029 && INTVAL (XEXP (x, 1)) >= 0
5030 && GET_CODE (SET_SRC (set)) == ASHIFT
5031 && XEXP (x, 1) == XEXP (SET_SRC (set), 1))
5032 return basic_induction_var (XEXP (SET_SRC (set), 0),
5033 GET_MODE (XEXP (x, 0)),
5034 dest_reg, insn, inc_val, mult_val);
5042 /* A general induction variable (giv) is any quantity that is a linear
5043 function of a basic induction variable,
5044 i.e. giv = biv * mult_val + add_val.
5045 The coefficients can be any loop invariant quantity.
5046 A giv need not be computed directly from the biv;
5047 it can be computed by way of other givs. */
5049 /* Determine whether X computes a giv.
5050 If it does, return a nonzero value
5051 which is the benefit from eliminating the computation of X;
5052 set *SRC_REG to the register of the biv that it is computed from;
5053 set *ADD_VAL and *MULT_VAL to the coefficients,
5054 such that the value of X is biv * mult + add; */
5057 general_induction_var (x, src_reg, add_val, mult_val)
5067 /* If this is an invariant, forget it, it isn't a giv. */
5068 if (invariant_p (x) == 1)
5071 /* See if the expression could be a giv and get its form.
5072 Mark our place on the obstack in case we don't find a giv. */
5073 storage = (char *) oballoc (0);
5074 x = simplify_giv_expr (x, &benefit);
5081 switch (GET_CODE (x))
5085 /* Since this is now an invariant and wasn't before, it must be a giv
5086 with MULT_VAL == 0. It doesn't matter which BIV we associate this
5088 *src_reg = loop_iv_list->biv->dest_reg;
5089 *mult_val = const0_rtx;
5094 /* This is equivalent to a BIV. */
5096 *mult_val = const1_rtx;
5097 *add_val = const0_rtx;
5101 /* Either (plus (biv) (invar)) or
5102 (plus (mult (biv) (invar_1)) (invar_2)). */
5103 if (GET_CODE (XEXP (x, 0)) == MULT)
5105 *src_reg = XEXP (XEXP (x, 0), 0);
5106 *mult_val = XEXP (XEXP (x, 0), 1);
5110 *src_reg = XEXP (x, 0);
5111 *mult_val = const1_rtx;
5113 *add_val = XEXP (x, 1);
5117 /* ADD_VAL is zero. */
5118 *src_reg = XEXP (x, 0);
5119 *mult_val = XEXP (x, 1);
5120 *add_val = const0_rtx;
5127 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
5128 unless they are CONST_INT). */
5129 if (GET_CODE (*add_val) == USE)
5130 *add_val = XEXP (*add_val, 0);
5131 if (GET_CODE (*mult_val) == USE)
5132 *mult_val = XEXP (*mult_val, 0);
5134 benefit += rtx_cost (orig_x, SET);
5136 /* Always return some benefit if this is a giv so it will be detected
5137 as such. This allows elimination of bivs that might otherwise
5138 not be eliminated. */
5139 return benefit == 0 ? 1 : benefit;
5142 /* Given an expression, X, try to form it as a linear function of a biv.
5143 We will canonicalize it to be of the form
5144 (plus (mult (BIV) (invar_1))
5146 with possible degeneracies.
5148 The invariant expressions must each be of a form that can be used as a
5149 machine operand. We surround then with a USE rtx (a hack, but localized
5150 and certainly unambiguous!) if not a CONST_INT for simplicity in this
5151 routine; it is the caller's responsibility to strip them.
5153 If no such canonicalization is possible (i.e., two biv's are used or an
5154 expression that is neither invariant nor a biv or giv), this routine
5157 For a non-zero return, the result will have a code of CONST_INT, USE,
5158 REG (for a BIV), PLUS, or MULT. No other codes will occur.
5160 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
5163 simplify_giv_expr (x, benefit)
5167 enum machine_mode mode = GET_MODE (x);
5171 /* If this is not an integer mode, or if we cannot do arithmetic in this
5172 mode, this can't be a giv. */
5173 if (mode != VOIDmode
5174 && (GET_MODE_CLASS (mode) != MODE_INT
5175 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT))
5178 switch (GET_CODE (x))
5181 arg0 = simplify_giv_expr (XEXP (x, 0), benefit);
5182 arg1 = simplify_giv_expr (XEXP (x, 1), benefit);
5183 if (arg0 == 0 || arg1 == 0)
5186 /* Put constant last, CONST_INT last if both constant. */
5187 if ((GET_CODE (arg0) == USE
5188 || GET_CODE (arg0) == CONST_INT)
5189 && GET_CODE (arg1) != CONST_INT)
5190 tem = arg0, arg0 = arg1, arg1 = tem;
5192 /* Handle addition of zero, then addition of an invariant. */
5193 if (arg1 == const0_rtx)
5195 else if (GET_CODE (arg1) == CONST_INT || GET_CODE (arg1) == USE)
5196 switch (GET_CODE (arg0))
5200 /* Both invariant. Only valid if sum is machine operand.
5201 First strip off possible USE on first operand. */
5202 if (GET_CODE (arg0) == USE)
5203 arg0 = XEXP (arg0, 0);
5206 if (CONSTANT_P (arg0) && GET_CODE (arg1) == CONST_INT)
5208 tem = plus_constant (arg0, INTVAL (arg1));
5209 if (GET_CODE (tem) != CONST_INT)
5210 tem = gen_rtx (USE, mode, tem);
5217 /* biv + invar or mult + invar. Return sum. */
5218 return gen_rtx (PLUS, mode, arg0, arg1);
5221 /* (a + invar_1) + invar_2. Associate. */
5222 return simplify_giv_expr (gen_rtx (PLUS, mode,
5224 gen_rtx (PLUS, mode,
5225 XEXP (arg0, 1), arg1)),
5232 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
5233 MULT to reduce cases. */
5234 if (GET_CODE (arg0) == REG)
5235 arg0 = gen_rtx (MULT, mode, arg0, const1_rtx);
5236 if (GET_CODE (arg1) == REG)
5237 arg1 = gen_rtx (MULT, mode, arg1, const1_rtx);
5239 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
5240 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
5241 Recurse to associate the second PLUS. */
5242 if (GET_CODE (arg1) == MULT)
5243 tem = arg0, arg0 = arg1, arg1 = tem;
5245 if (GET_CODE (arg1) == PLUS)
5246 return simplify_giv_expr (gen_rtx (PLUS, mode,
5247 gen_rtx (PLUS, mode,
5248 arg0, XEXP (arg1, 0)),
5252 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
5253 if (GET_CODE (arg0) != MULT || GET_CODE (arg1) != MULT)
5256 if (XEXP (arg0, 0) != XEXP (arg1, 0))
5259 return simplify_giv_expr (gen_rtx (MULT, mode,
5261 gen_rtx (PLUS, mode,
5267 /* Handle "a - b" as "a + b * (-1)". */
5268 return simplify_giv_expr (gen_rtx (PLUS, mode,
5270 gen_rtx (MULT, mode,
5271 XEXP (x, 1), constm1_rtx)),
5275 arg0 = simplify_giv_expr (XEXP (x, 0), benefit);
5276 arg1 = simplify_giv_expr (XEXP (x, 1), benefit);
5277 if (arg0 == 0 || arg1 == 0)
5280 /* Put constant last, CONST_INT last if both constant. */
5281 if ((GET_CODE (arg0) == USE || GET_CODE (arg0) == CONST_INT)
5282 && GET_CODE (arg1) != CONST_INT)
5283 tem = arg0, arg0 = arg1, arg1 = tem;
5285 /* If second argument is not now constant, not giv. */
5286 if (GET_CODE (arg1) != USE && GET_CODE (arg1) != CONST_INT)
5289 /* Handle multiply by 0 or 1. */
5290 if (arg1 == const0_rtx)
5293 else if (arg1 == const1_rtx)
5296 switch (GET_CODE (arg0))
5299 /* biv * invar. Done. */
5300 return gen_rtx (MULT, mode, arg0, arg1);
5303 /* Product of two constants. */
5304 return GEN_INT (INTVAL (arg0) * INTVAL (arg1));
5307 /* invar * invar. Not giv. */
5311 /* (a * invar_1) * invar_2. Associate. */
5312 return simplify_giv_expr (gen_rtx (MULT, mode,
5314 gen_rtx (MULT, mode,
5315 XEXP (arg0, 1), arg1)),
5319 /* (a + invar_1) * invar_2. Distribute. */
5320 return simplify_giv_expr (gen_rtx (PLUS, mode,
5321 gen_rtx (MULT, mode,
5322 XEXP (arg0, 0), arg1),
5323 gen_rtx (MULT, mode,
5324 XEXP (arg0, 1), arg1)),
5332 /* Shift by constant is multiply by power of two. */
5333 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5336 return simplify_giv_expr (gen_rtx (MULT, mode,
5338 GEN_INT ((HOST_WIDE_INT) 1
5339 << INTVAL (XEXP (x, 1)))),
5343 /* "-a" is "a * (-1)" */
5344 return simplify_giv_expr (gen_rtx (MULT, mode, XEXP (x, 0), constm1_rtx),
5348 /* "~a" is "-a - 1". Silly, but easy. */
5349 return simplify_giv_expr (gen_rtx (MINUS, mode,
5350 gen_rtx (NEG, mode, XEXP (x, 0)),
5355 /* Already in proper form for invariant. */
5359 /* If this is a new register, we can't deal with it. */
5360 if (REGNO (x) >= max_reg_before_loop)
5363 /* Check for biv or giv. */
5364 switch (reg_iv_type[REGNO (x)])
5368 case GENERAL_INDUCT:
5370 struct induction *v = reg_iv_info[REGNO (x)];
5372 /* Form expression from giv and add benefit. Ensure this giv
5373 can derive another and subtract any needed adjustment if so. */
5374 *benefit += v->benefit;
5378 tem = gen_rtx (PLUS, mode, gen_rtx (MULT, mode,
5379 v->src_reg, v->mult_val),
5381 if (v->derive_adjustment)
5382 tem = gen_rtx (MINUS, mode, tem, v->derive_adjustment);
5383 return simplify_giv_expr (tem, benefit);
5387 /* Fall through to general case. */
5389 /* If invariant, return as USE (unless CONST_INT).
5390 Otherwise, not giv. */
5391 if (GET_CODE (x) == USE)
5394 if (invariant_p (x) == 1)
5396 if (GET_CODE (x) == CONST_INT)
5399 return gen_rtx (USE, mode, x);
5406 /* Help detect a giv that is calculated by several consecutive insns;
5410 The caller has already identified the first insn P as having a giv as dest;
5411 we check that all other insns that set the same register follow
5412 immediately after P, that they alter nothing else,
5413 and that the result of the last is still a giv.
5415 The value is 0 if the reg set in P is not really a giv.
5416 Otherwise, the value is the amount gained by eliminating
5417 all the consecutive insns that compute the value.
5419 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
5420 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
5422 The coefficients of the ultimate giv value are stored in
5423 *MULT_VAL and *ADD_VAL. */
5426 consec_sets_giv (first_benefit, p, src_reg, dest_reg,
5441 /* Indicate that this is a giv so that we can update the value produced in
5442 each insn of the multi-insn sequence.
5444 This induction structure will be used only by the call to
5445 general_induction_var below, so we can allocate it on our stack.
5446 If this is a giv, our caller will replace the induct var entry with
5447 a new induction structure. */
5449 = (struct induction *) alloca (sizeof (struct induction));
5450 v->src_reg = src_reg;
5451 v->mult_val = *mult_val;
5452 v->add_val = *add_val;
5453 v->benefit = first_benefit;
5455 v->derive_adjustment = 0;
5457 reg_iv_type[REGNO (dest_reg)] = GENERAL_INDUCT;
5458 reg_iv_info[REGNO (dest_reg)] = v;
5460 count = n_times_set[REGNO (dest_reg)] - 1;
5465 code = GET_CODE (p);
5467 /* If libcall, skip to end of call sequence. */
5468 if (code == INSN && (temp = find_reg_note (p, REG_LIBCALL, NULL_RTX)))
5472 && (set = single_set (p))
5473 && GET_CODE (SET_DEST (set)) == REG
5474 && SET_DEST (set) == dest_reg
5475 && ((benefit = general_induction_var (SET_SRC (set), &src_reg,
5477 /* Giv created by equivalent expression. */
5478 || ((temp = find_reg_note (p, REG_EQUAL, NULL_RTX))
5479 && (benefit = general_induction_var (XEXP (temp, 0), &src_reg,
5480 add_val, mult_val))))
5481 && src_reg == v->src_reg)
5483 if (find_reg_note (p, REG_RETVAL, NULL_RTX))
5484 benefit += libcall_benefit (p);
5487 v->mult_val = *mult_val;
5488 v->add_val = *add_val;
5489 v->benefit = benefit;
5491 else if (code != NOTE)
5493 /* Allow insns that set something other than this giv to a
5494 constant. Such insns are needed on machines which cannot
5495 include long constants and should not disqualify a giv. */
5497 && (set = single_set (p))
5498 && SET_DEST (set) != dest_reg
5499 && CONSTANT_P (SET_SRC (set)))
5502 reg_iv_type[REGNO (dest_reg)] = UNKNOWN_INDUCT;
5510 /* Return an rtx, if any, that expresses giv G2 as a function of the register
5511 represented by G1. If no such expression can be found, or it is clear that
5512 it cannot possibly be a valid address, 0 is returned.
5514 To perform the computation, we note that
5517 where `v' is the biv.
5519 So G2 = (c/a) * G1 + (d - b*c/a) */
5523 express_from (g1, g2)
5524 struct induction *g1, *g2;
5528 /* The value that G1 will be multiplied by must be a constant integer. Also,
5529 the only chance we have of getting a valid address is if b*c/a (see above
5530 for notation) is also an integer. */
5531 if (GET_CODE (g1->mult_val) != CONST_INT
5532 || GET_CODE (g2->mult_val) != CONST_INT
5533 || GET_CODE (g1->add_val) != CONST_INT
5534 || g1->mult_val == const0_rtx
5535 || INTVAL (g2->mult_val) % INTVAL (g1->mult_val) != 0)
5538 mult = GEN_INT (INTVAL (g2->mult_val) / INTVAL (g1->mult_val));
5539 add = plus_constant (g2->add_val, - INTVAL (g1->add_val) * INTVAL (mult));
5541 /* Form simplified final result. */
5542 if (mult == const0_rtx)
5544 else if (mult == const1_rtx)
5545 mult = g1->dest_reg;
5547 mult = gen_rtx (MULT, g2->mode, g1->dest_reg, mult);
5549 if (add == const0_rtx)
5552 return gen_rtx (PLUS, g2->mode, mult, add);
5556 /* Return 1 if giv G2 can be combined with G1. This means that G2 can use
5557 (either directly or via an address expression) a register used to represent
5558 G1. Set g2->new_reg to a represtation of G1 (normally just
5562 combine_givs_p (g1, g2)
5563 struct induction *g1, *g2;
5567 /* If these givs are identical, they can be combined. */
5568 if (rtx_equal_p (g1->mult_val, g2->mult_val)
5569 && rtx_equal_p (g1->add_val, g2->add_val))
5571 g2->new_reg = g1->dest_reg;
5576 /* If G2 can be expressed as a function of G1 and that function is valid
5577 as an address and no more expensive than using a register for G2,
5578 the expression of G2 in terms of G1 can be used. */
5579 if (g2->giv_type == DEST_ADDR
5580 && (tem = express_from (g1, g2)) != 0
5581 && memory_address_p (g2->mem_mode, tem)
5582 && ADDRESS_COST (tem) <= ADDRESS_COST (*g2->location))
5592 #ifdef GIV_SORT_CRITERION
5593 /* Compare two givs and sort the most desirable one for combinations first.
5594 This is used only in one qsort call below. */
5598 struct induction **x, **y;
5600 GIV_SORT_CRITERION (*x, *y);
5606 /* Check all pairs of givs for iv_class BL and see if any can be combined with
5607 any other. If so, point SAME to the giv combined with and set NEW_REG to
5608 be an expression (in terms of the other giv's DEST_REG) equivalent to the
5609 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
5613 struct iv_class *bl;
5615 struct induction *g1, *g2, **giv_array, *temp_iv;
5616 int i, j, giv_count, pass;
5618 /* Count givs, because bl->giv_count is incorrect here. */
5620 for (g1 = bl->giv; g1; g1 = g1->next_iv)
5624 = (struct induction **) alloca (giv_count * sizeof (struct induction *));
5626 for (g1 = bl->giv; g1; g1 = g1->next_iv)
5627 giv_array[i++] = g1;
5629 #ifdef GIV_SORT_CRITERION
5630 /* Sort the givs if GIV_SORT_CRITERION is defined.
5631 This is usually defined for processors which lack
5632 negative register offsets so more givs may be combined. */
5634 if (loop_dump_stream)
5635 fprintf (loop_dump_stream, "%d givs counted, sorting...\n", giv_count);
5637 qsort (giv_array, giv_count, sizeof (struct induction *), giv_sort);
5640 for (i = 0; i < giv_count; i++)
5643 for (pass = 0; pass <= 1; pass++)
5644 for (j = 0; j < giv_count; j++)
5648 /* First try to combine with replaceable givs, then all givs. */
5649 && (g1->replaceable || pass == 1)
5650 /* If either has already been combined or is to be ignored, can't
5652 && ! g1->ignore && ! g2->ignore && ! g1->same && ! g2->same
5653 /* If something has been based on G2, G2 cannot itself be based
5654 on something else. */
5655 && ! g2->combined_with
5656 && combine_givs_p (g1, g2))
5658 /* g2->new_reg set by `combine_givs_p' */
5660 g1->combined_with = 1;
5661 g1->benefit += g2->benefit;
5662 /* ??? The new final_[bg]iv_value code does a much better job
5663 of finding replaceable giv's, and hence this code may no
5664 longer be necessary. */
5665 if (! g2->replaceable && REG_USERVAR_P (g2->dest_reg))
5666 g1->benefit -= copy_cost;
5667 g1->lifetime += g2->lifetime;
5668 g1->times_used += g2->times_used;
5670 if (loop_dump_stream)
5671 fprintf (loop_dump_stream, "giv at %d combined with giv at %d\n",
5672 INSN_UID (g2->insn), INSN_UID (g1->insn));
5678 /* EMIT code before INSERT_BEFORE to set REG = B * M + A. */
5681 emit_iv_add_mult (b, m, a, reg, insert_before)
5682 rtx b; /* initial value of basic induction variable */
5683 rtx m; /* multiplicative constant */
5684 rtx a; /* additive constant */
5685 rtx reg; /* destination register */
5691 /* Prevent unexpected sharing of these rtx. */
5695 /* Increase the lifetime of any invariants moved further in code. */
5696 update_reg_last_use (a, insert_before);
5697 update_reg_last_use (b, insert_before);
5698 update_reg_last_use (m, insert_before);
5701 result = expand_mult_add (b, reg, m, a, GET_MODE (reg), 0);
5703 emit_move_insn (reg, result);
5704 seq = gen_sequence ();
5707 emit_insn_before (seq, insert_before);
5710 /* Test whether A * B can be computed without
5711 an actual multiply insn. Value is 1 if so. */
5714 product_cheap_p (a, b)
5720 struct obstack *old_rtl_obstack = rtl_obstack;
5721 char *storage = (char *) obstack_alloc (&temp_obstack, 0);
5724 /* If only one is constant, make it B. */
5725 if (GET_CODE (a) == CONST_INT)
5726 tmp = a, a = b, b = tmp;
5728 /* If first constant, both constant, so don't need multiply. */
5729 if (GET_CODE (a) == CONST_INT)
5732 /* If second not constant, neither is constant, so would need multiply. */
5733 if (GET_CODE (b) != CONST_INT)
5736 /* One operand is constant, so might not need multiply insn. Generate the
5737 code for the multiply and see if a call or multiply, or long sequence
5738 of insns is generated. */
5740 rtl_obstack = &temp_obstack;
5742 expand_mult (GET_MODE (a), a, b, NULL_RTX, 0);
5743 tmp = gen_sequence ();
5746 if (GET_CODE (tmp) == SEQUENCE)
5748 if (XVEC (tmp, 0) == 0)
5750 else if (XVECLEN (tmp, 0) > 3)
5753 for (i = 0; i < XVECLEN (tmp, 0); i++)
5755 rtx insn = XVECEXP (tmp, 0, i);
5757 if (GET_CODE (insn) != INSN
5758 || (GET_CODE (PATTERN (insn)) == SET
5759 && GET_CODE (SET_SRC (PATTERN (insn))) == MULT)
5760 || (GET_CODE (PATTERN (insn)) == PARALLEL
5761 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET
5762 && GET_CODE (SET_SRC (XVECEXP (PATTERN (insn), 0, 0))) == MULT))
5769 else if (GET_CODE (tmp) == SET
5770 && GET_CODE (SET_SRC (tmp)) == MULT)
5772 else if (GET_CODE (tmp) == PARALLEL
5773 && GET_CODE (XVECEXP (tmp, 0, 0)) == SET
5774 && GET_CODE (SET_SRC (XVECEXP (tmp, 0, 0))) == MULT)
5777 /* Free any storage we obtained in generating this multiply and restore rtl
5778 allocation to its normal obstack. */
5779 obstack_free (&temp_obstack, storage);
5780 rtl_obstack = old_rtl_obstack;
5785 /* Check to see if loop can be terminated by a "decrement and branch until
5786 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
5787 Also try reversing an increment loop to a decrement loop
5788 to see if the optimization can be performed.
5789 Value is nonzero if optimization was performed. */
5791 /* This is useful even if the architecture doesn't have such an insn,
5792 because it might change a loops which increments from 0 to n to a loop
5793 which decrements from n to 0. A loop that decrements to zero is usually
5794 faster than one that increments from zero. */
5796 /* ??? This could be rewritten to use some of the loop unrolling procedures,
5797 such as approx_final_value, biv_total_increment, loop_iterations, and
5798 final_[bg]iv_value. */
5801 check_dbra_loop (loop_end, insn_count, loop_start)
5806 struct iv_class *bl;
5813 rtx before_comparison;
5816 /* If last insn is a conditional branch, and the insn before tests a
5817 register value, try to optimize it. Otherwise, we can't do anything. */
5819 comparison = get_condition_for_loop (PREV_INSN (loop_end));
5820 if (comparison == 0)
5823 /* Check all of the bivs to see if the compare uses one of them.
5824 Skip biv's set more than once because we can't guarantee that
5825 it will be zero on the last iteration. Also skip if the biv is
5826 used between its update and the test insn. */
5828 for (bl = loop_iv_list; bl; bl = bl->next)
5830 if (bl->biv_count == 1
5831 && bl->biv->dest_reg == XEXP (comparison, 0)
5832 && ! reg_used_between_p (regno_reg_rtx[bl->regno], bl->biv->insn,
5833 PREV_INSN (PREV_INSN (loop_end))))
5840 /* Look for the case where the basic induction variable is always
5841 nonnegative, and equals zero on the last iteration.
5842 In this case, add a reg_note REG_NONNEG, which allows the
5843 m68k DBRA instruction to be used. */
5845 if (((GET_CODE (comparison) == GT
5846 && GET_CODE (XEXP (comparison, 1)) == CONST_INT
5847 && INTVAL (XEXP (comparison, 1)) == -1)
5848 || (GET_CODE (comparison) == NE && XEXP (comparison, 1) == const0_rtx))
5849 && GET_CODE (bl->biv->add_val) == CONST_INT
5850 && INTVAL (bl->biv->add_val) < 0)
5852 /* Initial value must be greater than 0,
5853 init_val % -dec_value == 0 to ensure that it equals zero on
5854 the last iteration */
5856 if (GET_CODE (bl->initial_value) == CONST_INT
5857 && INTVAL (bl->initial_value) > 0
5858 && (INTVAL (bl->initial_value) %
5859 (-INTVAL (bl->biv->add_val))) == 0)
5861 /* register always nonnegative, add REG_NOTE to branch */
5862 REG_NOTES (PREV_INSN (loop_end))
5863 = gen_rtx (EXPR_LIST, REG_NONNEG, NULL_RTX,
5864 REG_NOTES (PREV_INSN (loop_end)));
5870 /* If the decrement is 1 and the value was tested as >= 0 before
5871 the loop, then we can safely optimize. */
5872 for (p = loop_start; p; p = PREV_INSN (p))
5874 if (GET_CODE (p) == CODE_LABEL)
5876 if (GET_CODE (p) != JUMP_INSN)
5879 before_comparison = get_condition_for_loop (p);
5880 if (before_comparison
5881 && XEXP (before_comparison, 0) == bl->biv->dest_reg
5882 && GET_CODE (before_comparison) == LT
5883 && XEXP (before_comparison, 1) == const0_rtx
5884 && ! reg_set_between_p (bl->biv->dest_reg, p, loop_start)
5885 && INTVAL (bl->biv->add_val) == -1)
5887 REG_NOTES (PREV_INSN (loop_end))
5888 = gen_rtx (EXPR_LIST, REG_NONNEG, NULL_RTX,
5889 REG_NOTES (PREV_INSN (loop_end)));
5896 else if (num_mem_sets <= 1)
5898 /* Try to change inc to dec, so can apply above optimization. */
5900 all registers modified are induction variables or invariant,
5901 all memory references have non-overlapping addresses
5902 (obviously true if only one write)
5903 allow 2 insns for the compare/jump at the end of the loop. */
5904 /* Also, we must avoid any instructions which use both the reversed
5905 biv and another biv. Such instructions will fail if the loop is
5906 reversed. We meet this condition by requiring that either
5907 no_use_except_counting is true, or else that there is only
5909 int num_nonfixed_reads = 0;
5910 /* 1 if the iteration var is used only to count iterations. */
5911 int no_use_except_counting = 0;
5912 /* 1 if the loop has no memory store, or it has a single memory store
5913 which is reversible. */
5914 int reversible_mem_store = 1;
5916 for (p = loop_start; p != loop_end; p = NEXT_INSN (p))
5917 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
5918 num_nonfixed_reads += count_nonfixed_reads (PATTERN (p));
5920 if (bl->giv_count == 0
5921 && ! loop_number_exit_count[uid_loop_num[INSN_UID (loop_start)]])
5923 rtx bivreg = regno_reg_rtx[bl->regno];
5925 /* If there are no givs for this biv, and the only exit is the
5926 fall through at the end of the the loop, then
5927 see if perhaps there are no uses except to count. */
5928 no_use_except_counting = 1;
5929 for (p = loop_start; p != loop_end; p = NEXT_INSN (p))
5930 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
5932 rtx set = single_set (p);
5934 if (set && GET_CODE (SET_DEST (set)) == REG
5935 && REGNO (SET_DEST (set)) == bl->regno)
5936 /* An insn that sets the biv is okay. */
5938 else if (p == prev_nonnote_insn (prev_nonnote_insn (loop_end))
5939 || p == prev_nonnote_insn (loop_end))
5940 /* Don't bother about the end test. */
5942 else if (reg_mentioned_p (bivreg, PATTERN (p)))
5943 /* Any other use of the biv is no good. */
5945 no_use_except_counting = 0;
5951 /* If the loop has a single store, and the destination address is
5952 invariant, then we can't reverse the loop, because this address
5953 might then have the wrong value at loop exit.
5954 This would work if the source was invariant also, however, in that
5955 case, the insn should have been moved out of the loop. */
5957 if (num_mem_sets == 1)
5958 reversible_mem_store
5959 = (! unknown_address_altered
5960 && ! invariant_p (XEXP (loop_store_mems[0], 0)));
5962 /* This code only acts for innermost loops. Also it simplifies
5963 the memory address check by only reversing loops with
5964 zero or one memory access.
5965 Two memory accesses could involve parts of the same array,
5966 and that can't be reversed. */
5968 if (num_nonfixed_reads <= 1
5970 && !loop_has_volatile
5971 && reversible_mem_store
5972 && (no_use_except_counting
5973 || ((bl->giv_count + bl->biv_count + num_mem_sets
5974 + num_movables + 2 == insn_count)
5975 && (bl == loop_iv_list && bl->next == 0))))
5979 /* Loop can be reversed. */
5980 if (loop_dump_stream)
5981 fprintf (loop_dump_stream, "Can reverse loop\n");
5983 /* Now check other conditions:
5984 initial_value must be zero,
5985 final_value % add_val == 0, so that when reversed, the
5986 biv will be zero on the last iteration.
5988 This test can probably be improved since +/- 1 in the constant
5989 can be obtained by changing LT to LE and vice versa; this is
5992 if (comparison && bl->initial_value == const0_rtx
5993 && GET_CODE (XEXP (comparison, 1)) == CONST_INT
5994 /* LE gets turned into LT */
5995 && GET_CODE (comparison) == LT
5996 && (INTVAL (XEXP (comparison, 1))
5997 % INTVAL (bl->biv->add_val)) == 0)
5999 /* Register will always be nonnegative, with value
6000 0 on last iteration if loop reversed */
6002 /* Save some info needed to produce the new insns. */
6003 reg = bl->biv->dest_reg;
6004 jump_label = XEXP (SET_SRC (PATTERN (PREV_INSN (loop_end))), 1);
6005 new_add_val = GEN_INT (- INTVAL (bl->biv->add_val));
6007 final_value = XEXP (comparison, 1);
6008 start_value = GEN_INT (INTVAL (XEXP (comparison, 1))
6009 - INTVAL (bl->biv->add_val));
6011 /* Initialize biv to start_value before loop start.
6012 The old initializing insn will be deleted as a
6013 dead store by flow.c. */
6014 emit_insn_before (gen_move_insn (reg, start_value), loop_start);
6016 /* Add insn to decrement register, and delete insn
6017 that incremented the register. */
6018 p = emit_insn_before (gen_add2_insn (reg, new_add_val),
6020 delete_insn (bl->biv->insn);
6022 /* Update biv info to reflect its new status. */
6024 bl->initial_value = start_value;
6025 bl->biv->add_val = new_add_val;
6027 /* Inc LABEL_NUSES so that delete_insn will
6028 not delete the label. */
6029 LABEL_NUSES (XEXP (jump_label, 0)) ++;
6031 /* Emit an insn after the end of the loop to set the biv's
6032 proper exit value if it is used anywhere outside the loop. */
6033 if ((regno_last_uid[bl->regno]
6034 != INSN_UID (PREV_INSN (PREV_INSN (loop_end))))
6036 || regno_first_uid[bl->regno] != INSN_UID (bl->init_insn))
6037 emit_insn_after (gen_move_insn (reg, final_value),
6040 /* Delete compare/branch at end of loop. */
6041 delete_insn (PREV_INSN (loop_end));
6042 delete_insn (PREV_INSN (loop_end));
6044 /* Add new compare/branch insn at end of loop. */
6046 emit_cmp_insn (reg, const0_rtx, GE, NULL_RTX,
6047 GET_MODE (reg), 0, 0);
6048 emit_jump_insn (gen_bge (XEXP (jump_label, 0)));
6049 tem = gen_sequence ();
6051 emit_jump_insn_before (tem, loop_end);
6053 for (tem = PREV_INSN (loop_end);
6054 tem && GET_CODE (tem) != JUMP_INSN; tem = PREV_INSN (tem))
6058 JUMP_LABEL (tem) = XEXP (jump_label, 0);
6060 /* Increment of LABEL_NUSES done above. */
6061 /* Register is now always nonnegative,
6062 so add REG_NONNEG note to the branch. */
6063 REG_NOTES (tem) = gen_rtx (EXPR_LIST, REG_NONNEG, NULL_RTX,
6069 /* Mark that this biv has been reversed. Each giv which depends
6070 on this biv, and which is also live past the end of the loop
6071 will have to be fixed up. */
6075 if (loop_dump_stream)
6076 fprintf (loop_dump_stream,
6077 "Reversed loop and added reg_nonneg\n");
6087 /* Verify whether the biv BL appears to be eliminable,
6088 based on the insns in the loop that refer to it.
6089 LOOP_START is the first insn of the loop, and END is the end insn.
6091 If ELIMINATE_P is non-zero, actually do the elimination.
6093 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
6094 determine whether invariant insns should be placed inside or at the
6095 start of the loop. */
6098 maybe_eliminate_biv (bl, loop_start, end, eliminate_p, threshold, insn_count)
6099 struct iv_class *bl;
6103 int threshold, insn_count;
6105 rtx reg = bl->biv->dest_reg;
6108 /* Scan all insns in the loop, stopping if we find one that uses the
6109 biv in a way that we cannot eliminate. */
6111 for (p = loop_start; p != end; p = NEXT_INSN (p))
6113 enum rtx_code code = GET_CODE (p);
6114 rtx where = threshold >= insn_count ? loop_start : p;
6116 if ((code == INSN || code == JUMP_INSN || code == CALL_INSN)
6117 && reg_mentioned_p (reg, PATTERN (p))
6118 && ! maybe_eliminate_biv_1 (PATTERN (p), p, bl, eliminate_p, where))
6120 if (loop_dump_stream)
6121 fprintf (loop_dump_stream,
6122 "Cannot eliminate biv %d: biv used in insn %d.\n",
6123 bl->regno, INSN_UID (p));
6130 if (loop_dump_stream)
6131 fprintf (loop_dump_stream, "biv %d %s eliminated.\n",
6132 bl->regno, eliminate_p ? "was" : "can be");
6139 /* If BL appears in X (part of the pattern of INSN), see if we can
6140 eliminate its use. If so, return 1. If not, return 0.
6142 If BIV does not appear in X, return 1.
6144 If ELIMINATE_P is non-zero, actually do the elimination. WHERE indicates
6145 where extra insns should be added. Depending on how many items have been
6146 moved out of the loop, it will either be before INSN or at the start of
6150 maybe_eliminate_biv_1 (x, insn, bl, eliminate_p, where)
6152 struct iv_class *bl;
6156 enum rtx_code code = GET_CODE (x);
6157 rtx reg = bl->biv->dest_reg;
6158 enum machine_mode mode = GET_MODE (reg);
6159 struct induction *v;
6168 /* If we haven't already been able to do something with this BIV,
6169 we can't eliminate it. */
6175 /* If this sets the BIV, it is not a problem. */
6176 if (SET_DEST (x) == reg)
6179 /* If this is an insn that defines a giv, it is also ok because
6180 it will go away when the giv is reduced. */
6181 for (v = bl->giv; v; v = v->next_iv)
6182 if (v->giv_type == DEST_REG && SET_DEST (x) == v->dest_reg)
6186 if (SET_DEST (x) == cc0_rtx && SET_SRC (x) == reg)
6188 /* Can replace with any giv that was reduced and
6189 that has (MULT_VAL != 0) and (ADD_VAL == 0).
6190 Require a constant for MULT_VAL, so we know it's nonzero.
6191 ??? We disable this optimization to avoid potential
6194 for (v = bl->giv; v; v = v->next_iv)
6195 if (CONSTANT_P (v->mult_val) && v->mult_val != const0_rtx
6196 && v->add_val == const0_rtx
6197 && ! v->ignore && ! v->maybe_dead && v->always_computable
6201 /* If the giv V had the auto-inc address optimization applied
6202 to it, and INSN occurs between the giv insn and the biv
6203 insn, then we must adjust the value used here.
6204 This is rare, so we don't bother to do so. */
6206 && ((INSN_LUID (v->insn) < INSN_LUID (insn)
6207 && INSN_LUID (insn) < INSN_LUID (bl->biv->insn))
6208 || (INSN_LUID (v->insn) > INSN_LUID (insn)
6209 && INSN_LUID (insn) > INSN_LUID (bl->biv->insn))))
6215 /* If the giv has the opposite direction of change,
6216 then reverse the comparison. */
6217 if (INTVAL (v->mult_val) < 0)
6218 new = gen_rtx (COMPARE, GET_MODE (v->new_reg),
6219 const0_rtx, v->new_reg);
6223 /* We can probably test that giv's reduced reg. */
6224 if (validate_change (insn, &SET_SRC (x), new, 0))
6228 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
6229 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
6230 Require a constant for MULT_VAL, so we know it's nonzero.
6231 ??? Do this only if ADD_VAL is a pointer to avoid a potential
6232 overflow problem. */
6234 for (v = bl->giv; v; v = v->next_iv)
6235 if (CONSTANT_P (v->mult_val) && v->mult_val != const0_rtx
6236 && ! v->ignore && ! v->maybe_dead && v->always_computable
6238 && (GET_CODE (v->add_val) == SYMBOL_REF
6239 || GET_CODE (v->add_val) == LABEL_REF
6240 || GET_CODE (v->add_val) == CONST
6241 || (GET_CODE (v->add_val) == REG
6242 && REGNO_POINTER_FLAG (REGNO (v->add_val)))))
6244 /* If the giv V had the auto-inc address optimization applied
6245 to it, and INSN occurs between the giv insn and the biv
6246 insn, then we must adjust the value used here.
6247 This is rare, so we don't bother to do so. */
6249 && ((INSN_LUID (v->insn) < INSN_LUID (insn)
6250 && INSN_LUID (insn) < INSN_LUID (bl->biv->insn))
6251 || (INSN_LUID (v->insn) > INSN_LUID (insn)
6252 && INSN_LUID (insn) > INSN_LUID (bl->biv->insn))))
6258 /* If the giv has the opposite direction of change,
6259 then reverse the comparison. */
6260 if (INTVAL (v->mult_val) < 0)
6261 new = gen_rtx (COMPARE, VOIDmode, copy_rtx (v->add_val),
6264 new = gen_rtx (COMPARE, VOIDmode, v->new_reg,
6265 copy_rtx (v->add_val));
6267 /* Replace biv with the giv's reduced register. */
6268 update_reg_last_use (v->add_val, insn);
6269 if (validate_change (insn, &SET_SRC (PATTERN (insn)), new, 0))
6272 /* Insn doesn't support that constant or invariant. Copy it
6273 into a register (it will be a loop invariant.) */
6274 tem = gen_reg_rtx (GET_MODE (v->new_reg));
6276 emit_insn_before (gen_move_insn (tem, copy_rtx (v->add_val)),
6279 if (validate_change (insn, &SET_SRC (PATTERN (insn)),
6280 gen_rtx (COMPARE, VOIDmode,
6281 v->new_reg, tem), 0))
6290 case GT: case GE: case GTU: case GEU:
6291 case LT: case LE: case LTU: case LEU:
6292 /* See if either argument is the biv. */
6293 if (XEXP (x, 0) == reg)
6294 arg = XEXP (x, 1), arg_operand = 1;
6295 else if (XEXP (x, 1) == reg)
6296 arg = XEXP (x, 0), arg_operand = 0;
6300 if (CONSTANT_P (arg))
6302 /* First try to replace with any giv that has constant positive
6303 mult_val and constant add_val. We might be able to support
6304 negative mult_val, but it seems complex to do it in general. */
6306 for (v = bl->giv; v; v = v->next_iv)
6307 if (CONSTANT_P (v->mult_val) && INTVAL (v->mult_val) > 0
6308 && (GET_CODE (v->add_val) == SYMBOL_REF
6309 || GET_CODE (v->add_val) == LABEL_REF
6310 || GET_CODE (v->add_val) == CONST
6311 || (GET_CODE (v->add_val) == REG
6312 && REGNO_POINTER_FLAG (REGNO (v->add_val))))
6313 && ! v->ignore && ! v->maybe_dead && v->always_computable
6316 /* If the giv V had the auto-inc address optimization applied
6317 to it, and INSN occurs between the giv insn and the biv
6318 insn, then we must adjust the value used here.
6319 This is rare, so we don't bother to do so. */
6321 && ((INSN_LUID (v->insn) < INSN_LUID (insn)
6322 && INSN_LUID (insn) < INSN_LUID (bl->biv->insn))
6323 || (INSN_LUID (v->insn) > INSN_LUID (insn)
6324 && INSN_LUID (insn) > INSN_LUID (bl->biv->insn))))
6330 /* Replace biv with the giv's reduced reg. */
6331 XEXP (x, 1-arg_operand) = v->new_reg;
6333 /* If all constants are actually constant integers and
6334 the derived constant can be directly placed in the COMPARE,
6336 if (GET_CODE (arg) == CONST_INT
6337 && GET_CODE (v->mult_val) == CONST_INT
6338 && GET_CODE (v->add_val) == CONST_INT
6339 && validate_change (insn, &XEXP (x, arg_operand),
6340 GEN_INT (INTVAL (arg)
6341 * INTVAL (v->mult_val)
6342 + INTVAL (v->add_val)), 0))
6345 /* Otherwise, load it into a register. */
6346 tem = gen_reg_rtx (mode);
6347 emit_iv_add_mult (arg, v->mult_val, v->add_val, tem, where);
6348 if (validate_change (insn, &XEXP (x, arg_operand), tem, 0))
6351 /* If that failed, put back the change we made above. */
6352 XEXP (x, 1-arg_operand) = reg;
6355 /* Look for giv with positive constant mult_val and nonconst add_val.
6356 Insert insns to calculate new compare value.
6357 ??? Turn this off due to possible overflow. */
6359 for (v = bl->giv; v; v = v->next_iv)
6360 if (CONSTANT_P (v->mult_val) && INTVAL (v->mult_val) > 0
6361 && ! v->ignore && ! v->maybe_dead && v->always_computable
6367 /* If the giv V had the auto-inc address optimization applied
6368 to it, and INSN occurs between the giv insn and the biv
6369 insn, then we must adjust the value used here.
6370 This is rare, so we don't bother to do so. */
6372 && ((INSN_LUID (v->insn) < INSN_LUID (insn)
6373 && INSN_LUID (insn) < INSN_LUID (bl->biv->insn))
6374 || (INSN_LUID (v->insn) > INSN_LUID (insn)
6375 && INSN_LUID (insn) > INSN_LUID (bl->biv->insn))))
6381 tem = gen_reg_rtx (mode);
6383 /* Replace biv with giv's reduced register. */
6384 validate_change (insn, &XEXP (x, 1 - arg_operand),
6387 /* Compute value to compare against. */
6388 emit_iv_add_mult (arg, v->mult_val, v->add_val, tem, where);
6389 /* Use it in this insn. */
6390 validate_change (insn, &XEXP (x, arg_operand), tem, 1);
6391 if (apply_change_group ())
6395 else if (GET_CODE (arg) == REG || GET_CODE (arg) == MEM)
6397 if (invariant_p (arg) == 1)
6399 /* Look for giv with constant positive mult_val and nonconst
6400 add_val. Insert insns to compute new compare value.
6401 ??? Turn this off due to possible overflow. */
6403 for (v = bl->giv; v; v = v->next_iv)
6404 if (CONSTANT_P (v->mult_val) && INTVAL (v->mult_val) > 0
6405 && ! v->ignore && ! v->maybe_dead && v->always_computable
6411 /* If the giv V had the auto-inc address optimization applied
6412 to it, and INSN occurs between the giv insn and the biv
6413 insn, then we must adjust the value used here.
6414 This is rare, so we don't bother to do so. */
6416 && ((INSN_LUID (v->insn) < INSN_LUID (insn)
6417 && INSN_LUID (insn) < INSN_LUID (bl->biv->insn))
6418 || (INSN_LUID (v->insn) > INSN_LUID (insn)
6419 && INSN_LUID (insn) > INSN_LUID (bl->biv->insn))))
6425 tem = gen_reg_rtx (mode);
6427 /* Replace biv with giv's reduced register. */
6428 validate_change (insn, &XEXP (x, 1 - arg_operand),
6431 /* Compute value to compare against. */
6432 emit_iv_add_mult (arg, v->mult_val, v->add_val,
6434 validate_change (insn, &XEXP (x, arg_operand), tem, 1);
6435 if (apply_change_group ())
6440 /* This code has problems. Basically, you can't know when
6441 seeing if we will eliminate BL, whether a particular giv
6442 of ARG will be reduced. If it isn't going to be reduced,
6443 we can't eliminate BL. We can try forcing it to be reduced,
6444 but that can generate poor code.
6446 The problem is that the benefit of reducing TV, below should
6447 be increased if BL can actually be eliminated, but this means
6448 we might have to do a topological sort of the order in which
6449 we try to process biv. It doesn't seem worthwhile to do
6450 this sort of thing now. */
6453 /* Otherwise the reg compared with had better be a biv. */
6454 if (GET_CODE (arg) != REG
6455 || reg_iv_type[REGNO (arg)] != BASIC_INDUCT)
6458 /* Look for a pair of givs, one for each biv,
6459 with identical coefficients. */
6460 for (v = bl->giv; v; v = v->next_iv)
6462 struct induction *tv;
6464 if (v->ignore || v->maybe_dead || v->mode != mode)
6467 for (tv = reg_biv_class[REGNO (arg)]->giv; tv; tv = tv->next_iv)
6468 if (! tv->ignore && ! tv->maybe_dead
6469 && rtx_equal_p (tv->mult_val, v->mult_val)
6470 && rtx_equal_p (tv->add_val, v->add_val)
6471 && tv->mode == mode)
6473 /* If the giv V had the auto-inc address optimization applied
6474 to it, and INSN occurs between the giv insn and the biv
6475 insn, then we must adjust the value used here.
6476 This is rare, so we don't bother to do so. */
6478 && ((INSN_LUID (v->insn) < INSN_LUID (insn)
6479 && INSN_LUID (insn) < INSN_LUID (bl->biv->insn))
6480 || (INSN_LUID (v->insn) > INSN_LUID (insn)
6481 && INSN_LUID (insn) > INSN_LUID (bl->biv->insn))))
6487 /* Replace biv with its giv's reduced reg. */
6488 XEXP (x, 1-arg_operand) = v->new_reg;
6489 /* Replace other operand with the other giv's
6491 XEXP (x, arg_operand) = tv->new_reg;
6498 /* If we get here, the biv can't be eliminated. */
6502 /* If this address is a DEST_ADDR giv, it doesn't matter if the
6503 biv is used in it, since it will be replaced. */
6504 for (v = bl->giv; v; v = v->next_iv)
6505 if (v->giv_type == DEST_ADDR && v->location == &XEXP (x, 0))
6510 /* See if any subexpression fails elimination. */
6511 fmt = GET_RTX_FORMAT (code);
6512 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6517 if (! maybe_eliminate_biv_1 (XEXP (x, i), insn, bl,
6518 eliminate_p, where))
6523 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6524 if (! maybe_eliminate_biv_1 (XVECEXP (x, i, j), insn, bl,
6525 eliminate_p, where))
6534 /* Return nonzero if the last use of REG
6535 is in an insn following INSN in the same basic block. */
6538 last_use_this_basic_block (reg, insn)
6544 n && GET_CODE (n) != CODE_LABEL && GET_CODE (n) != JUMP_INSN;
6547 if (regno_last_uid[REGNO (reg)] == INSN_UID (n))
6553 /* Called via `note_stores' to record the initial value of a biv. Here we
6554 just record the location of the set and process it later. */
6557 record_initial (dest, set)
6561 struct iv_class *bl;
6563 if (GET_CODE (dest) != REG
6564 || REGNO (dest) >= max_reg_before_loop
6565 || reg_iv_type[REGNO (dest)] != BASIC_INDUCT)
6568 bl = reg_biv_class[REGNO (dest)];
6570 /* If this is the first set found, record it. */
6571 if (bl->init_insn == 0)
6573 bl->init_insn = note_insn;
6578 /* If any of the registers in X are "old" and currently have a last use earlier
6579 than INSN, update them to have a last use of INSN. Their actual last use
6580 will be the previous insn but it will not have a valid uid_luid so we can't
6584 update_reg_last_use (x, insn)
6588 /* Check for the case where INSN does not have a valid luid. In this case,
6589 there is no need to modify the regno_last_uid, as this can only happen
6590 when code is inserted after the loop_end to set a pseudo's final value,
6591 and hence this insn will never be the last use of x. */
6592 if (GET_CODE (x) == REG && REGNO (x) < max_reg_before_loop
6593 && INSN_UID (insn) < max_uid_for_loop
6594 && uid_luid[regno_last_uid[REGNO (x)]] < uid_luid[INSN_UID (insn)])
6595 regno_last_uid[REGNO (x)] = INSN_UID (insn);
6599 register char *fmt = GET_RTX_FORMAT (GET_CODE (x));
6600 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6603 update_reg_last_use (XEXP (x, i), insn);
6604 else if (fmt[i] == 'E')
6605 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6606 update_reg_last_use (XVECEXP (x, i, j), insn);
6611 /* Given a jump insn JUMP, return the condition that will cause it to branch
6612 to its JUMP_LABEL. If the condition cannot be understood, or is an
6613 inequality floating-point comparison which needs to be reversed, 0 will
6616 If EARLIEST is non-zero, it is a pointer to a place where the earliest
6617 insn used in locating the condition was found. If a replacement test
6618 of the condition is desired, it should be placed in front of that
6619 insn and we will be sure that the inputs are still valid.
6621 The condition will be returned in a canonical form to simplify testing by
6622 callers. Specifically:
6624 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
6625 (2) Both operands will be machine operands; (cc0) will have been replaced.
6626 (3) If an operand is a constant, it will be the second operand.
6627 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
6628 for GE, GEU, and LEU. */
6631 get_condition (jump, earliest)
6640 int reverse_code = 0;
6641 int did_reverse_condition = 0;
6643 /* If this is not a standard conditional jump, we can't parse it. */
6644 if (GET_CODE (jump) != JUMP_INSN
6645 || ! condjump_p (jump) || simplejump_p (jump))
6648 code = GET_CODE (XEXP (SET_SRC (PATTERN (jump)), 0));
6649 op0 = XEXP (XEXP (SET_SRC (PATTERN (jump)), 0), 0);
6650 op1 = XEXP (XEXP (SET_SRC (PATTERN (jump)), 0), 1);
6655 /* If this branches to JUMP_LABEL when the condition is false, reverse
6657 if (GET_CODE (XEXP (SET_SRC (PATTERN (jump)), 2)) == LABEL_REF
6658 && XEXP (XEXP (SET_SRC (PATTERN (jump)), 2), 0) == JUMP_LABEL (jump))
6659 code = reverse_condition (code), did_reverse_condition ^= 1;
6661 /* If we are comparing a register with zero, see if the register is set
6662 in the previous insn to a COMPARE or a comparison operation. Perform
6663 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
6666 while (GET_RTX_CLASS (code) == '<' && op1 == CONST0_RTX (GET_MODE (op0)))
6668 /* Set non-zero when we find something of interest. */
6672 /* If comparison with cc0, import actual comparison from compare
6676 if ((prev = prev_nonnote_insn (prev)) == 0
6677 || GET_CODE (prev) != INSN
6678 || (set = single_set (prev)) == 0
6679 || SET_DEST (set) != cc0_rtx)
6682 op0 = SET_SRC (set);
6683 op1 = CONST0_RTX (GET_MODE (op0));
6689 /* If this is a COMPARE, pick up the two things being compared. */
6690 if (GET_CODE (op0) == COMPARE)
6692 op1 = XEXP (op0, 1);
6693 op0 = XEXP (op0, 0);
6696 else if (GET_CODE (op0) != REG)
6699 /* Go back to the previous insn. Stop if it is not an INSN. We also
6700 stop if it isn't a single set or if it has a REG_INC note because
6701 we don't want to bother dealing with it. */
6703 if ((prev = prev_nonnote_insn (prev)) == 0
6704 || GET_CODE (prev) != INSN
6705 || FIND_REG_INC_NOTE (prev, 0)
6706 || (set = single_set (prev)) == 0)
6709 /* If this is setting OP0, get what it sets it to if it looks
6711 if (SET_DEST (set) == op0)
6713 enum machine_mode inner_mode = GET_MODE (SET_SRC (set));
6715 if ((GET_CODE (SET_SRC (set)) == COMPARE
6718 && GET_MODE_CLASS (inner_mode) == MODE_INT
6719 && (GET_MODE_BITSIZE (inner_mode)
6720 <= HOST_BITS_PER_WIDE_INT)
6721 && (STORE_FLAG_VALUE
6722 & ((HOST_WIDE_INT) 1
6723 << (GET_MODE_BITSIZE (inner_mode) - 1))))
6724 #ifdef FLOAT_STORE_FLAG_VALUE
6726 && GET_MODE_CLASS (inner_mode) == MODE_FLOAT
6727 && FLOAT_STORE_FLAG_VALUE < 0)
6730 && GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == '<')))
6732 else if (((code == EQ
6734 && (GET_MODE_BITSIZE (inner_mode)
6735 <= HOST_BITS_PER_WIDE_INT)
6736 && GET_MODE_CLASS (inner_mode) == MODE_INT
6737 && (STORE_FLAG_VALUE
6738 & ((HOST_WIDE_INT) 1
6739 << (GET_MODE_BITSIZE (inner_mode) - 1))))
6740 #ifdef FLOAT_STORE_FLAG_VALUE
6742 && GET_MODE_CLASS (inner_mode) == MODE_FLOAT
6743 && FLOAT_STORE_FLAG_VALUE < 0)
6746 && GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == '<')
6748 /* We might have reversed a LT to get a GE here. But this wasn't
6749 actually the comparison of data, so we don't flag that we
6750 have had to reverse the condition. */
6751 did_reverse_condition ^= 1;
6759 else if (reg_set_p (op0, prev))
6760 /* If this sets OP0, but not directly, we have to give up. */
6765 if (GET_RTX_CLASS (GET_CODE (x)) == '<')
6766 code = GET_CODE (x);
6769 code = reverse_condition (code);
6770 did_reverse_condition ^= 1;
6774 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
6780 /* If constant is first, put it last. */
6781 if (CONSTANT_P (op0))
6782 code = swap_condition (code), tem = op0, op0 = op1, op1 = tem;
6784 /* If OP0 is the result of a comparison, we weren't able to find what
6785 was really being compared, so fail. */
6786 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6789 /* Canonicalize any ordered comparison with integers involving equality
6790 if we can do computations in the relevant mode and we do not
6793 if (GET_CODE (op1) == CONST_INT
6794 && GET_MODE (op0) != VOIDmode
6795 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT)
6797 HOST_WIDE_INT const_val = INTVAL (op1);
6798 unsigned HOST_WIDE_INT uconst_val = const_val;
6799 unsigned HOST_WIDE_INT max_val
6800 = (unsigned HOST_WIDE_INT) GET_MODE_MASK (GET_MODE (op0));
6805 if (const_val != max_val >> 1)
6806 code = LT, op1 = GEN_INT (const_val + 1);
6811 != (((HOST_WIDE_INT) 1
6812 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
6813 code = GT, op1 = GEN_INT (const_val - 1);
6817 if (uconst_val != max_val)
6818 code = LTU, op1 = GEN_INT (uconst_val + 1);
6822 if (uconst_val != 0)
6823 code = GTU, op1 = GEN_INT (uconst_val - 1);
6828 /* If this was floating-point and we reversed anything other than an
6829 EQ or NE, return zero. */
6830 if (TARGET_FLOAT_FORMAT == IEEE_FLOAT_FORMAT
6831 && did_reverse_condition && code != NE && code != EQ
6833 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT)
6837 /* Never return CC0; return zero instead. */
6842 return gen_rtx (code, VOIDmode, op0, op1);
6845 /* Similar to above routine, except that we also put an invariant last
6846 unless both operands are invariants. */
6849 get_condition_for_loop (x)
6852 rtx comparison = get_condition (x, NULL_PTR);
6855 || ! invariant_p (XEXP (comparison, 0))
6856 || invariant_p (XEXP (comparison, 1)))
6859 return gen_rtx (swap_condition (GET_CODE (comparison)), VOIDmode,
6860 XEXP (comparison, 1), XEXP (comparison, 0));
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