1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991, 1992 Free Software Foundation, Inc.
4 This definition file is free software; you can redistribute it
5 and/or modify it under the terms of the GNU General Public
6 License as published by the Free Software Foundation; either
7 version 2, or (at your option) any later version.
9 This definition file is distributed in the hope that it will be
10 useful, but WITHOUT ANY WARRANTY; without even the implied
11 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 See the GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19 #define SI_TYPE_SIZE 32
22 #define __BITS4 (SI_TYPE_SIZE / 4)
23 #define __ll_B (1L << (SI_TYPE_SIZE / 2))
24 #define __ll_lowpart(t) ((USItype) (t) % __ll_B)
25 #define __ll_highpart(t) ((USItype) (t) / __ll_B)
27 /* Define auxiliary asm macros.
29 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand)
30 multiplies two USItype integers MULTIPLER and MULTIPLICAND,
31 and generates a two-part USItype product in HIGH_PROD and
34 2) __umulsidi3(a,b) multiplies two USItype integers A and B,
35 and returns a UDItype product. This is just a variant of umul_ppmm.
37 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
38 denominator) divides a two-word unsigned integer, composed by the
39 integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and
40 places the quotient in QUOTIENT and the remainder in REMAINDER.
41 HIGH_NUMERATOR must be less than DENOMINATOR for correct operation.
42 If, in addition, the most significant bit of DENOMINATOR must be 1,
43 then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1.
45 4) count_leading_zeros(count, x) counts the number of zero-bits from
46 the msb to the first non-zero bit. This is the number of steps X
47 needs to be shifted left to set the msb. Undefined for X == 0.
49 5) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
50 high_addend_2, low_addend_2) adds two two-word unsigned integers,
51 composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and
52 LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and
53 LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is
56 6) sub_ddmmss(high_difference, low_difference, high_minuend,
57 low_minuend, high_subtrahend, low_subtrahend) subtracts two
58 two-word unsigned integers, composed by HIGH_MINUEND_1 and
59 LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2
60 respectively. The result is placed in HIGH_DIFFERENCE and
61 LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
64 If any of these macros are left undefined for a particular CPU,
67 /* The CPUs come in alphabetical order below.
69 Please add support for more CPUs here, or improve the current support
71 (E.g. WE32100, i960, IBM360.) */
73 #if defined (__GNUC__) && !defined (NO_ASM)
75 /* We sometimes need to clobber "cc" with gcc2, but that would not be
76 understood by gcc1. Use cpp to avoid major code duplication. */
79 #define __AND_CLOBBER_CC
80 #else /* __GNUC__ >= 2 */
81 #define __CLOBBER_CC : "cc"
82 #define __AND_CLOBBER_CC , "cc"
83 #endif /* __GNUC__ < 2 */
85 #if defined (__a29k__) || defined (___AM29K__)
86 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
87 __asm__ ("add %1,%4,%5
89 : "=r" ((USItype)(sh)), \
90 "=&r" ((USItype)(sl)) \
91 : "%r" ((USItype)(ah)), \
92 "rI" ((USItype)(bh)), \
93 "%r" ((USItype)(al)), \
95 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
96 __asm__ ("sub %1,%4,%5
98 : "=r" ((USItype)(sh)), \
99 "=&r" ((USItype)(sl)) \
100 : "r" ((USItype)(ah)), \
101 "rI" ((USItype)(bh)), \
102 "r" ((USItype)(al)), \
103 "rI" ((USItype)(bl)))
104 #define umul_ppmm(xh, xl, m0, m1) \
106 USItype __m0 = (m0), __m1 = (m1); \
107 __asm__ ("multiplu %0,%1,%2" \
108 : "=r" ((USItype)(xl)) \
111 __asm__ ("multmu %0,%1,%2" \
112 : "=r" ((USItype)(xh)) \
116 #define udiv_qrnnd(q, r, n1, n0, d) \
117 __asm__ ("dividu %0,%3,%4" \
118 : "=r" ((USItype)(q)), \
119 "=q" ((USItype)(r)) \
120 : "1" ((USItype)(n1)), \
121 "r" ((USItype)(n0)), \
123 #define count_leading_zeros(count, x) \
124 __asm__ ("clz %0,%1" \
125 : "=r" ((USItype)(count)) \
126 : "r" ((USItype)(x)))
127 #endif /* __a29k__ */
129 #if defined (__arm__)
130 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
131 __asm__ ("adds %1,%4,%5
133 : "=r" ((USItype)(sh)), \
134 "=&r" ((USItype)(sl)) \
135 : "%r" ((USItype)(ah)), \
136 "rI" ((USItype)(bh)), \
137 "%r" ((USItype)(al)), \
138 "rI" ((USItype)(bl)))
139 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
140 __asm__ ("subs %1,%4,%5
142 : "=r" ((USItype)(sh)), \
143 "=&r" ((USItype)(sl)) \
144 : "r" ((USItype)(ah)), \
145 "rI" ((USItype)(bh)), \
146 "r" ((USItype)(al)), \
147 "rI" ((USItype)(bl)))
150 #if defined (__gmicro__)
151 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
152 __asm__ ("add.w %5,%1
154 : "=g" ((USItype)(sh)), \
155 "=&g" ((USItype)(sl)) \
156 : "%0" ((USItype)(ah)), \
157 "g" ((USItype)(bh)), \
158 "%1" ((USItype)(al)), \
160 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
161 __asm__ ("sub.w %5,%1
163 : "=g" ((USItype)(sh)), \
164 "=&g" ((USItype)(sl)) \
165 : "0" ((USItype)(ah)), \
166 "g" ((USItype)(bh)), \
167 "1" ((USItype)(al)), \
169 #define umul_ppmm(ph, pl, m0, m1) \
170 __asm__ ("mulx %3,%0,%1" \
171 : "=g" ((USItype)(ph)), \
172 "=r" ((USItype)(pl)) \
173 : "%0" ((USItype)(m0)), \
175 #define udiv_qrnnd(q, r, nh, nl, d) \
176 __asm__ ("divx %4,%0,%1" \
177 : "=g" ((USItype)(q)), \
178 "=r" ((USItype)(r)) \
179 : "1" ((USItype)(nh)), \
180 "0" ((USItype)(nl)), \
182 #define count_leading_zeros(count, x) \
183 __asm__ ("bsch/1 %1,%0" \
185 : "g" ((USItype)(x)), \
190 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
191 __asm__ ("add %4,%5,%1
193 : "=r" ((USItype)(sh)), \
194 "=&r" ((USItype)(sl)) \
195 : "%rM" ((USItype)(ah)), \
196 "rM" ((USItype)(bh)), \
197 "%rM" ((USItype)(al)), \
198 "rM" ((USItype)(bl)))
199 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
200 __asm__ ("sub %5,%4,%1
202 : "=r" ((USItype)(sh)), \
203 "=&r" ((USItype)(sl)) \
204 : "rM" ((USItype)(ah)), \
205 "rM" ((USItype)(bh)), \
206 "rM" ((USItype)(al)), \
207 "rM" ((USItype)(bl)))
208 #if defined (_PA_RISC1_1)
209 #define umul_ppmm(w1, w0, u, v) \
214 struct {USItype __w1, __w0;} __w1w0; \
216 __asm__ ("xmpyu %1,%2,%0" \
218 : "x" ((USItype)(u)), \
219 "x" ((USItype)(v))); \
220 (w1) = __t.__w1w0.__w1; \
221 (w0) = __t.__w1w0.__w0; \
230 #if defined (__i386__) || defined (__i486__)
231 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
234 : "=r" ((USItype)(sh)), \
235 "=&r" ((USItype)(sl)) \
236 : "%0" ((USItype)(ah)), \
237 "g" ((USItype)(bh)), \
238 "%1" ((USItype)(al)), \
240 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
243 : "=r" ((USItype)(sh)), \
244 "=&r" ((USItype)(sl)) \
245 : "0" ((USItype)(ah)), \
246 "g" ((USItype)(bh)), \
247 "1" ((USItype)(al)), \
249 #define umul_ppmm(w1, w0, u, v) \
251 : "=a" ((USItype)(w0)), \
252 "=d" ((USItype)(w1)) \
253 : "%0" ((USItype)(u)), \
255 #define udiv_qrnnd(q, r, n1, n0, d) \
257 : "=a" ((USItype)(q)), \
258 "=d" ((USItype)(r)) \
259 : "0" ((USItype)(n0)), \
260 "1" ((USItype)(n1)), \
262 #define count_leading_zeros(count, x) \
265 __asm__ ("bsrl %1,%0" \
266 : "=r" (__cbtmp) : "rm" ((USItype)(x))); \
267 (count) = __cbtmp ^ 31; \
273 #if defined (__i860__)
275 /* Make sure these patterns really improve the code before
276 switching them on. */
277 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
282 struct {USItype __l, __h;} __i; \
284 __a.__i.__l = (al); \
285 __a.__i.__h = (ah); \
286 __b.__i.__l = (bl); \
287 __b.__i.__h = (bh); \
288 __asm__ ("fiadd.dd %1,%2,%0" \
290 : "%f" (__a.__ll), "f" (__b.__ll)); \
291 (sh) = __s.__i.__h; \
292 (sl) = __s.__i.__l; \
294 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
299 struct {USItype __l, __h;} __i; \
301 __a.__i.__l = (al); \
302 __a.__i.__h = (ah); \
303 __b.__i.__l = (bl); \
304 __b.__i.__h = (bh); \
305 __asm__ ("fisub.dd %1,%2,%0" \
307 : "%f" (__a.__ll), "f" (__b.__ll)); \
308 (sh) = __s.__i.__h; \
309 (sl) = __s.__i.__l; \
312 #endif /* __i860__ */
314 #if defined (___IBMR2__) /* IBM RS6000 */
315 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
316 __asm__ ("a%I5 %1,%4,%5
318 : "=r" ((USItype)(sh)), \
319 "=&r" ((USItype)(sl)) \
320 : "%r" ((USItype)(ah)), \
321 "r" ((USItype)(bh)), \
322 "%r" ((USItype)(al)), \
323 "rI" ((USItype)(bl)))
324 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
325 __asm__ ("sf%I4 %1,%5,%4
327 : "=r" ((USItype)(sh)), \
328 "=&r" ((USItype)(sl)) \
329 : "r" ((USItype)(ah)), \
330 "r" ((USItype)(bh)), \
331 "rI" ((USItype)(al)), \
333 #define umul_ppmm(xh, xl, m0, m1) \
335 USItype __m0 = (m0), __m1 = (m1); \
336 __asm__ ("mul %0,%2,%3" \
337 : "=r" ((USItype)(xh)), \
338 "=q" ((USItype)(xl)) \
341 (xh) += ((((SItype) __m0 >> 31) & __m1) \
342 + (((SItype) __m1 >> 31) & __m0)); \
344 #define smul_ppmm(xh, xl, m0, m1) \
345 __asm__ ("mul %0,%2,%3" \
346 : "=r" ((USItype)(xh)), \
347 "=q" ((USItype)(xl)) \
348 : "r" ((USItype)(m0)), \
351 #define sdiv_qrnnd(q, r, nh, nl, d) \
352 __asm__ ("div %0,%2,%4" \
353 : "=r" ((USItype)(q)), "=q" ((USItype)(r)) \
354 : "r" ((USItype)(nh)), "1" ((USItype)(nl)), "r" ((USItype)(d)))
356 #define UDIV_NEEDS_NORMALIZATION 1
357 #define count_leading_zeros(count, x) \
358 __asm__ ("cntlz %0,%1" \
359 : "=r" ((USItype)(count)) \
360 : "r" ((USItype)(x)))
361 #endif /* ___IBMR2__ */
363 #if defined (__mc68000__)
364 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
365 __asm__ ("add%.l %5,%1
367 : "=d" ((USItype)(sh)), \
368 "=&d" ((USItype)(sl)) \
369 : "%0" ((USItype)(ah)), \
370 "d" ((USItype)(bh)), \
371 "%1" ((USItype)(al)), \
373 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
374 __asm__ ("sub%.l %5,%1
376 : "=d" ((USItype)(sh)), \
377 "=&d" ((USItype)(sl)) \
378 : "0" ((USItype)(ah)), \
379 "d" ((USItype)(bh)), \
380 "1" ((USItype)(al)), \
382 #if defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)
383 #define umul_ppmm(w1, w0, u, v) \
384 __asm__ ("mulu%.l %3,%1:%0" \
385 : "=d" ((USItype)(w0)), \
386 "=d" ((USItype)(w1)) \
387 : "%0" ((USItype)(u)), \
388 "dmi" ((USItype)(v)))
390 #define udiv_qrnnd(q, r, n1, n0, d) \
391 __asm__ ("divu%.l %4,%1:%0" \
392 : "=d" ((USItype)(q)), \
393 "=d" ((USItype)(r)) \
394 : "0" ((USItype)(n0)), \
395 "1" ((USItype)(n1)), \
396 "dmi" ((USItype)(d)))
398 #define sdiv_qrnnd(q, r, n1, n0, d) \
399 __asm__ ("divs%.l %4,%1:%0" \
400 : "=d" ((USItype)(q)), \
401 "=d" ((USItype)(r)) \
402 : "0" ((USItype)(n0)), \
403 "1" ((USItype)(n1)), \
404 "dmi" ((USItype)(d)))
405 #define count_leading_zeros(count, x) \
406 __asm__ ("bfffo %1{%b2:%b2},%0" \
407 : "=d" ((USItype)(count)) \
408 : "od" ((USItype)(x)), "n" (0))
409 #else /* not mc68020 */
410 #define umul_ppmm(xh, xl, a, b) \
411 __asm__ ("| Inlined umul_ppmm
437 : "=g" ((USItype)(xh)), \
438 "=g" ((USItype)(xl)) \
439 : "g" ((USItype)(a)), \
441 : "d0", "d1", "d2", "d3", "d4")
442 #define UMUL_TIME 100
443 #define UDIV_TIME 400
444 #endif /* not mc68020 */
447 #if defined (__m88000__)
448 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
449 __asm__ ("addu.co %1,%r4,%r5
450 addu.ci %0,%r2,%r3" \
451 : "=r" ((USItype)(sh)), \
452 "=&r" ((USItype)(sl)) \
453 : "%rJ" ((USItype)(ah)), \
454 "rJ" ((USItype)(bh)), \
455 "%rJ" ((USItype)(al)), \
456 "rJ" ((USItype)(bl)))
457 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
458 __asm__ ("subu.co %1,%r4,%r5
459 subu.ci %0,%r2,%r3" \
460 : "=r" ((USItype)(sh)), \
461 "=&r" ((USItype)(sl)) \
462 : "rJ" ((USItype)(ah)), \
463 "rJ" ((USItype)(bh)), \
464 "rJ" ((USItype)(al)), \
465 "rJ" ((USItype)(bl)))
467 #define UDIV_TIME 150
468 #define count_leading_zeros(count, x) \
471 __asm__ ("ff1 %0,%1" \
473 : "r" ((USItype)(x))); \
474 (count) = __cbtmp ^ 31; \
476 #if defined (__mc88110__)
477 #define umul_ppmm(w1, w0, u, v) \
478 __asm__ ("mulu.d r10,%2,%3
483 : "r" ((USItype)(u)), \
486 #define udiv_qrnnd(q, r, n1, n0, d) \
487 __asm__ ("or r10,%2,0
495 : "r" ((USItype)(n1)), \
496 "r" ((USItype)(n0)), \
500 #endif /* __m88000__ */
502 #if defined (__mips__)
503 #define umul_ppmm(w1, w0, u, v) \
504 __asm__ ("multu %2,%3
507 : "=d" ((USItype)(w0)), \
508 "=d" ((USItype)(w1)) \
509 : "d" ((USItype)(u)), \
512 #define UDIV_TIME 100
513 #endif /* __mips__ */
515 #if defined (__ns32000__)
516 #define __umulsidi3(u, v) \
518 __asm__ ("meid %2,%0" \
520 : "%0" ((USItype)(u)), \
521 "g" ((USItype)(v))); \
523 #define div_qrnnd(q, r, n1, n0, d) \
529 : "=g" ((USItype)(q)), \
530 "=g" ((USItype)(r)) \
531 : "g" ((USItype)(n0)), \
532 "g" ((USItype)(n1)), \
535 #endif /* __ns32000__ */
537 #if defined (__pyr__)
538 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
541 : "=r" ((USItype)(sh)), \
542 "=&r" ((USItype)(sl)) \
543 : "%0" ((USItype)(ah)), \
544 "g" ((USItype)(bh)), \
545 "%1" ((USItype)(al)), \
547 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
550 : "=r" ((USItype)(sh)), \
551 "=&r" ((USItype)(sl)) \
552 : "0" ((USItype)(ah)), \
553 "g" ((USItype)(bh)), \
554 "1" ((USItype)(al)), \
556 /* This insn doesn't work on ancient pyramids. */
557 #define umul_ppmm(w1, w0, u, v) \
560 struct {USItype __h, __l;} __i; \
563 __asm__ ("uemul %3,%0" \
564 : "=r" (__xx.__i.__h), \
565 "=r" (__xx.__i.__l) \
566 : "1" (__xx.__i.__l), \
567 "g" ((UDItype)(v))); \
568 (w1) = __xx.__i.__h; \
569 (w0) = __xx.__i.__l;})
572 #if defined (__ibm032__) /* RT/ROMP */
573 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
576 : "=r" ((USItype)(sh)), \
577 "=&r" ((USItype)(sl)) \
578 : "%0" ((USItype)(ah)), \
579 "r" ((USItype)(bh)), \
580 "%1" ((USItype)(al)), \
582 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
585 : "=r" ((USItype)(sh)), \
586 "=&r" ((USItype)(sl)) \
587 : "0" ((USItype)(ah)), \
588 "r" ((USItype)(bh)), \
589 "1" ((USItype)(al)), \
591 #define umul_ppmm(ph, pl, m0, m1) \
593 USItype __m0 = (m0), __m1 = (m1); \
615 : "=r" ((USItype)(ph)), \
616 "=r" ((USItype)(pl)) \
620 (ph) += ((((SItype) __m0 >> 31) & __m1) \
621 + (((SItype) __m1 >> 31) & __m0)); \
624 #define UDIV_TIME 200
625 #define count_leading_zeros(count, x) \
627 if ((x) >= 0x10000) \
628 __asm__ ("clz %0,%1" \
629 : "=r" ((USItype)(count)) \
630 : "r" ((USItype)(x) >> 16)); \
633 __asm__ ("clz %0,%1" \
634 : "=r" ((USItype)(count)) \
635 : "r" ((USItype)(x))); \
641 #if defined (__sparc__)
642 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
643 __asm__ ("addcc %4,%5,%1
645 : "=r" ((USItype)(sh)), \
646 "=&r" ((USItype)(sl)) \
647 : "%r" ((USItype)(ah)), \
648 "rI" ((USItype)(bh)), \
649 "%r" ((USItype)(al)), \
650 "rI" ((USItype)(bl)) \
652 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
653 __asm__ ("subcc %4,%5,%1
655 : "=r" ((USItype)(sh)), \
656 "=&r" ((USItype)(sl)) \
657 : "r" ((USItype)(ah)), \
658 "rI" ((USItype)(bh)), \
659 "r" ((USItype)(al)), \
660 "rI" ((USItype)(bl)) \
662 #if defined (__sparc_v8__)
663 #define umul_ppmm(w1, w0, u, v) \
664 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
665 : "=r" ((USItype)(w1)), \
666 "=r" ((USItype)(w0)) \
667 : "r" ((USItype)(u)), \
669 #define udiv_qrnnd(q, r, n1, n0, d) \
670 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
671 : "=&r" ((USItype)(q)), \
672 "=&r" ((USItype)(r)) \
673 : "r" ((USItype)(n1)), \
674 "r" ((USItype)(n0)), \
677 #if defined (__sparclite__)
678 /* This has hardware multiply but not divide. It also has two additional
679 instructions scan (ffs from high bit) and divscc. */
680 #define umul_ppmm(w1, w0, u, v) \
681 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
682 : "=r" ((USItype)(w1)), \
683 "=r" ((USItype)(w0)) \
684 : "r" ((USItype)(u)), \
686 #define udiv_qrnnd(q, r, n1, n0, d) \
687 __asm__ ("! Inlined udiv_qrnnd
688 wr %%g0,%2,%%y ! Not a delayed write for sparclite
725 1: ! End of inline udiv_qrnnd" \
726 : "=r" ((USItype)(q)), \
727 "=r" ((USItype)(r)) \
728 : "r" ((USItype)(n1)), \
729 "r" ((USItype)(n0)), \
730 "rI" ((USItype)(d)) \
731 : "%g1" __AND_CLOBBER_CC)
733 #define count_leading_zeros(count, x) \
734 __asm__ ("scan %1,0,%0" \
735 : "=r" ((USItype)(x)) \
736 : "r" ((USItype)(count)))
738 /* SPARC without integer multiplication and divide instructions.
739 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
740 #define umul_ppmm(w1, w0, u, v) \
741 __asm__ ("! Inlined umul_ppmm
742 wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
743 sra %3,31,%%g2 ! Don't move this insn
744 and %2,%%g2,%%g2 ! Don't move this insn
745 andcc %%g0,0,%%g1 ! Don't move this insn
781 : "=r" ((USItype)(w1)), \
782 "=r" ((USItype)(w0)) \
783 : "%rI" ((USItype)(u)), \
785 : "%g1", "%g2" __AND_CLOBBER_CC)
786 #define UMUL_TIME 39 /* 39 instructions */
787 /* It's quite necessary to add this much assembler for the sparc.
788 The default udiv_qrnnd (in C) is more than 10 times slower! */
789 #define udiv_qrnnd(q, r, n1, n0, d) \
790 __asm__ ("! Inlined udiv_qrnnd
794 addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
795 sub %1,%2,%1 ! this kills msb of n
796 addx %1,%1,%1 ! so this can't give carry
801 addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
803 sub %1,%2,%1 ! this kills msb of n
808 ! Got carry from n. Subtract next step to cancel this carry.
810 addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb
813 ! End of inline udiv_qrnnd" \
814 : "=&r" ((USItype)(q)), \
815 "=&r" ((USItype)(r)) \
816 : "r" ((USItype)(d)), \
817 "1" ((USItype)(n1)), \
818 "0" ((USItype)(n0)) : "%g1" __AND_CLOBBER_CC)
819 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
820 #endif /* __sparclite__ */
821 #endif /* __sparc_v8__ */
822 #endif /* __sparc__ */
824 #if defined (__vax__)
825 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
826 __asm__ ("addl2 %5,%1
828 : "=g" ((USItype)(sh)), \
829 "=&g" ((USItype)(sl)) \
830 : "%0" ((USItype)(ah)), \
831 "g" ((USItype)(bh)), \
832 "%1" ((USItype)(al)), \
834 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
835 __asm__ ("subl2 %5,%1
837 : "=g" ((USItype)(sh)), \
838 "=&g" ((USItype)(sl)) \
839 : "0" ((USItype)(ah)), \
840 "g" ((USItype)(bh)), \
841 "1" ((USItype)(al)), \
843 #define umul_ppmm(xh, xl, m0, m1) \
847 struct {USItype __l, __h;} __i; \
849 USItype __m0 = (m0), __m1 = (m1); \
850 __asm__ ("emul %1,%2,$0,%0" \
854 (xh) = __xx.__i.__h; \
855 (xl) = __xx.__i.__l; \
856 (xh) += ((((SItype) __m0 >> 31) & __m1) \
857 + (((SItype) __m1 >> 31) & __m0)); \
861 #endif /* __GNUC__ */
863 /* If this machine has no inline assembler, use C macros. */
865 #if !defined (add_ssaaaa)
866 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
870 (sh) = (ah) + (bh) + (__x < (al)); \
875 #if !defined (sub_ddmmss)
876 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
880 (sh) = (ah) - (bh) - (__x > (al)); \
885 #if !defined (umul_ppmm)
886 #define umul_ppmm(w1, w0, u, v) \
888 USItype __x0, __x1, __x2, __x3; \
889 USItype __ul, __vl, __uh, __vh; \
891 __ul = __ll_lowpart (u); \
892 __uh = __ll_highpart (u); \
893 __vl = __ll_lowpart (v); \
894 __vh = __ll_highpart (v); \
896 __x0 = (USItype) __ul * __vl; \
897 __x1 = (USItype) __ul * __vh; \
898 __x2 = (USItype) __uh * __vl; \
899 __x3 = (USItype) __uh * __vh; \
901 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
902 __x1 += __x2; /* but this indeed can */ \
903 if (__x1 < __x2) /* did we get it? */ \
904 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
906 (w1) = __x3 + __ll_highpart (__x1); \
907 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
911 #if !defined (__umulsidi3)
912 #define __umulsidi3(u, v) \
914 umul_ppmm (__w.s.high, __w.s.low, u, v); \
918 /* Define this unconditionally, so it can be used for debugging. */
919 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
921 USItype __d1, __d0, __q1, __q0; \
922 USItype __r1, __r0, __m; \
923 __d1 = __ll_highpart (d); \
924 __d0 = __ll_lowpart (d); \
926 __r1 = (n1) % __d1; \
927 __q1 = (n1) / __d1; \
928 __m = (USItype) __q1 * __d0; \
929 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
932 __q1--, __r1 += (d); \
933 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
935 __q1--, __r1 += (d); \
939 __r0 = __r1 % __d1; \
940 __q0 = __r1 / __d1; \
941 __m = (USItype) __q0 * __d0; \
942 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
945 __q0--, __r0 += (d); \
948 __q0--, __r0 += (d); \
952 (q) = (USItype) __q1 * __ll_B | __q0; \
956 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
957 __udiv_w_sdiv (defined in libgcc or elsewhere). */
958 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
959 #define udiv_qrnnd(q, r, nh, nl, d) \
962 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
967 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
968 #if !defined (udiv_qrnnd)
969 #define UDIV_NEEDS_NORMALIZATION 1
970 #define udiv_qrnnd __udiv_qrnnd_c
973 #if !defined (count_leading_zeros)
974 extern const UQItype __clz_tab[];
975 #define count_leading_zeros(count, x) \
977 USItype __xr = (x); \
980 if (SI_TYPE_SIZE <= 32) \
982 __a = __xr < (1<<2*__BITS4) \
983 ? (__xr < (1<<__BITS4) ? 0 : __BITS4) \
984 : (__xr < (1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
988 for (__a = SI_TYPE_SIZE - 8; __a > 0; __a -= 8) \
989 if (((__xr >> __a) & 0xff) != 0) \
993 (count) = SI_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
997 #ifndef UDIV_NEEDS_NORMALIZATION
998 #define UDIV_NEEDS_NORMALIZATION 0