1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "hard-reg-set.h"
68 #include "basic-block.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
78 /* Next quantity number available for allocation. */
82 /* Information we maitain about each quantity. */
85 /* The number of refs to quantity Q. */
89 /* The frequency of uses of quantity Q. */
93 /* Insn number (counting from head of basic block)
94 where quantity Q was born. -1 if birth has not been recorded. */
98 /* Insn number (counting from head of basic block)
99 where given quantity died. Due to the way tying is done,
100 and the fact that we consider in this pass only regs that die but once,
101 a quantity can die only once. Each quantity's life span
102 is a set of consecutive insns. -1 if death has not been recorded. */
106 /* Number of words needed to hold the data in given quantity.
107 This depends on its machine mode. It is used for these purposes:
108 1. It is used in computing the relative importances of qtys,
109 which determines the order in which we look for regs for them.
110 2. It is used in rules that prevent tying several registers of
111 different sizes in a way that is geometrically impossible
112 (see combine_regs). */
116 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
120 /* The register number of one pseudo register whose reg_qty value is Q.
121 This register should be the head of the chain
122 maintained in reg_next_in_qty. */
126 /* Reg class contained in (smaller than) the preferred classes of all
127 the pseudo regs that are tied in given quantity.
128 This is the preferred class for allocating that quantity. */
130 enum reg_class min_class;
132 /* Register class within which we allocate given qty if we can't get
133 its preferred class. */
135 enum reg_class alternate_class;
137 /* This holds the mode of the registers that are tied to given qty,
138 or VOIDmode if registers with differing modes are tied together. */
140 enum machine_mode mode;
142 /* the hard reg number chosen for given quantity,
143 or -1 if none was found. */
147 /* Nonzero if this quantity has been used in a SUBREG in some
148 way that is illegal. */
154 static struct qty *qty;
156 /* These fields are kept separately to speedup their clearing. */
158 /* We maintain two hard register sets that indicate suggested hard registers
159 for each quantity. The first, phys_copy_sugg, contains hard registers
160 that are tied to the quantity by a simple copy. The second contains all
161 hard registers that are tied to the quantity via an arithmetic operation.
163 The former register set is given priority for allocation. This tends to
164 eliminate copy insns. */
166 /* Element Q is a set of hard registers that are suggested for quantity Q by
169 static HARD_REG_SET *qty_phys_copy_sugg;
171 /* Element Q is a set of hard registers that are suggested for quantity Q by
174 static HARD_REG_SET *qty_phys_sugg;
176 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
178 static short *qty_phys_num_copy_sugg;
180 /* Element Q is the number of suggested registers in qty_phys_sugg. */
182 static short *qty_phys_num_sugg;
184 /* If (REG N) has been assigned a quantity number, is a register number
185 of another register assigned the same quantity number, or -1 for the
186 end of the chain. qty->first_reg point to the head of this chain. */
188 static int *reg_next_in_qty;
190 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
192 of -1 if this register cannot be allocated by local-alloc,
193 or -2 if not known yet.
195 Note that if we see a use or death of pseudo register N with
196 reg_qty[N] == -2, register N must be local to the current block. If
197 it were used in more than one block, we would have reg_qty[N] == -1.
198 This relies on the fact that if reg_basic_block[N] is >= 0, register N
199 will not appear in any other block. We save a considerable number of
200 tests by exploiting this.
202 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
207 /* The offset (in words) of register N within its quantity.
208 This can be nonzero if register N is SImode, and has been tied
209 to a subreg of a DImode register. */
211 static char *reg_offset;
213 /* Vector of substitutions of register numbers,
214 used to map pseudo regs into hardware regs.
215 This is set up as a result of register allocation.
216 Element N is the hard reg assigned to pseudo reg N,
217 or is -1 if no hard reg was assigned.
218 If N is a hard reg number, element N is N. */
222 /* Set of hard registers live at the current point in the scan
223 of the instructions in a basic block. */
225 static HARD_REG_SET regs_live;
227 /* Each set of hard registers indicates registers live at a particular
228 point in the basic block. For N even, regs_live_at[N] says which
229 hard registers are needed *after* insn N/2 (i.e., they may not
230 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
232 If an object is to conflict with the inputs of insn J but not the
233 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
234 if it is to conflict with the outputs of insn J but not the inputs of
235 insn J + 1, it is said to die at index J*2 + 1. */
237 static HARD_REG_SET *regs_live_at;
239 /* Communicate local vars `insn_number' and `insn'
240 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
241 static int this_insn_number;
242 static rtx this_insn;
246 /* Set when an attempt should be made to replace a register
247 with the associated src entry. */
251 /* Set when a REG_EQUIV note is found or created. Use to
252 keep track of what memory accesses might be created later,
259 /* Loop depth is used to recognize equivalences which appear
260 to be present within the same loop (or in an inner loop). */
264 /* The list of each instruction which initializes this register. */
269 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
270 structure for that register. */
272 static struct equivalence *reg_equiv;
274 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
275 static int recorded_label_ref;
277 static void alloc_qty PARAMS ((int, enum machine_mode, int, int));
278 static void validate_equiv_mem_from_store PARAMS ((rtx, rtx, void *));
279 static int validate_equiv_mem PARAMS ((rtx, rtx, rtx));
280 static int equiv_init_varies_p PARAMS ((rtx));
281 static int equiv_init_movable_p PARAMS ((rtx, int));
282 static int contains_replace_regs PARAMS ((rtx));
283 static int memref_referenced_p PARAMS ((rtx, rtx));
284 static int memref_used_between_p PARAMS ((rtx, rtx, rtx));
285 static void update_equiv_regs PARAMS ((void));
286 static void no_equiv PARAMS ((rtx, rtx, void *));
287 static void block_alloc PARAMS ((int));
288 static int qty_sugg_compare PARAMS ((int, int));
289 static int qty_sugg_compare_1 PARAMS ((const PTR, const PTR));
290 static int qty_compare PARAMS ((int, int));
291 static int qty_compare_1 PARAMS ((const PTR, const PTR));
292 static int combine_regs PARAMS ((rtx, rtx, int, int, rtx, int));
293 static int reg_meets_class_p PARAMS ((int, enum reg_class));
294 static void update_qty_class PARAMS ((int, int));
295 static void reg_is_set PARAMS ((rtx, rtx, void *));
296 static void reg_is_born PARAMS ((rtx, int));
297 static void wipe_dead_reg PARAMS ((rtx, int));
298 static int find_free_reg PARAMS ((enum reg_class, enum machine_mode,
299 int, int, int, int, int));
300 static void mark_life PARAMS ((int, enum machine_mode, int));
301 static void post_mark_life PARAMS ((int, enum machine_mode, int, int, int));
302 static int no_conflict_p PARAMS ((rtx, rtx, rtx));
303 static int requires_inout PARAMS ((const char *));
305 /* Allocate a new quantity (new within current basic block)
306 for register number REGNO which is born at index BIRTH
307 within the block. MODE and SIZE are info on reg REGNO. */
310 alloc_qty (regno, mode, size, birth)
312 enum machine_mode mode;
315 int qtyno = next_qty++;
317 reg_qty[regno] = qtyno;
318 reg_offset[regno] = 0;
319 reg_next_in_qty[regno] = -1;
321 qty[qtyno].first_reg = regno;
322 qty[qtyno].size = size;
323 qty[qtyno].mode = mode;
324 qty[qtyno].birth = birth;
325 qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno);
326 qty[qtyno].min_class = reg_preferred_class (regno);
327 qty[qtyno].alternate_class = reg_alternate_class (regno);
328 qty[qtyno].n_refs = REG_N_REFS (regno);
329 qty[qtyno].freq = REG_FREQ (regno);
330 qty[qtyno].changes_mode = REG_CHANGES_MODE (regno);
333 /* Main entry point of this file. */
341 /* We need to keep track of whether or not we recorded a LABEL_REF so
342 that we know if the jump optimizer needs to be rerun. */
343 recorded_label_ref = 0;
345 /* Leaf functions and non-leaf functions have different needs.
346 If defined, let the machine say what kind of ordering we
348 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
349 ORDER_REGS_FOR_LOCAL_ALLOC;
352 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
354 update_equiv_regs ();
356 /* This sets the maximum number of quantities we can have. Quantity
357 numbers start at zero and we can have one for each pseudo. */
358 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
360 /* Allocate vectors of temporary data.
361 See the declarations of these variables, above,
362 for what they mean. */
364 qty = (struct qty *) xmalloc (max_qty * sizeof (struct qty));
366 = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
367 qty_phys_num_copy_sugg = (short *) xmalloc (max_qty * sizeof (short));
368 qty_phys_sugg = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
369 qty_phys_num_sugg = (short *) xmalloc (max_qty * sizeof (short));
371 reg_qty = (int *) xmalloc (max_regno * sizeof (int));
372 reg_offset = (char *) xmalloc (max_regno * sizeof (char));
373 reg_next_in_qty = (int *) xmalloc (max_regno * sizeof (int));
375 /* Determine which pseudo-registers can be allocated by local-alloc.
376 In general, these are the registers used only in a single block and
379 We need not be concerned with which block actually uses the register
380 since we will never see it outside that block. */
382 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
384 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1)
390 /* Force loop below to initialize entire quantity array. */
393 /* Allocate each block's local registers, block by block. */
395 for (b = 0; b < n_basic_blocks; b++)
397 /* NEXT_QTY indicates which elements of the `qty_...'
398 vectors might need to be initialized because they were used
399 for the previous block; it is set to the entire array before
400 block 0. Initialize those, with explicit loop if there are few,
401 else with bzero and bcopy. Do not initialize vectors that are
402 explicit set by `alloc_qty'. */
406 for (i = 0; i < next_qty; i++)
408 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
409 qty_phys_num_copy_sugg[i] = 0;
410 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
411 qty_phys_num_sugg[i] = 0;
416 #define CLEAR(vector) \
417 memset ((char *) (vector), 0, (sizeof (*(vector))) * next_qty);
419 CLEAR (qty_phys_copy_sugg);
420 CLEAR (qty_phys_num_copy_sugg);
421 CLEAR (qty_phys_sugg);
422 CLEAR (qty_phys_num_sugg);
431 free (qty_phys_copy_sugg);
432 free (qty_phys_num_copy_sugg);
433 free (qty_phys_sugg);
434 free (qty_phys_num_sugg);
438 free (reg_next_in_qty);
440 return recorded_label_ref;
443 /* Used for communication between the following two functions: contains
444 a MEM that we wish to ensure remains unchanged. */
445 static rtx equiv_mem;
447 /* Set nonzero if EQUIV_MEM is modified. */
448 static int equiv_mem_modified;
450 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
451 Called via note_stores. */
454 validate_equiv_mem_from_store (dest, set, data)
456 rtx set ATTRIBUTE_UNUSED;
457 void *data ATTRIBUTE_UNUSED;
459 if ((GET_CODE (dest) == REG
460 && reg_overlap_mentioned_p (dest, equiv_mem))
461 || (GET_CODE (dest) == MEM
462 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
463 equiv_mem_modified = 1;
466 /* Verify that no store between START and the death of REG invalidates
467 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
468 by storing into an overlapping memory location, or with a non-const
471 Return 1 if MEMREF remains valid. */
474 validate_equiv_mem (start, reg, memref)
483 equiv_mem_modified = 0;
485 /* If the memory reference has side effects or is volatile, it isn't a
486 valid equivalence. */
487 if (side_effects_p (memref))
490 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
495 if (find_reg_note (insn, REG_DEAD, reg))
498 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
499 && ! CONST_OR_PURE_CALL_P (insn))
502 note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
504 /* If a register mentioned in MEMREF is modified via an
505 auto-increment, we lose the equivalence. Do the same if one
506 dies; although we could extend the life, it doesn't seem worth
509 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
510 if ((REG_NOTE_KIND (note) == REG_INC
511 || REG_NOTE_KIND (note) == REG_DEAD)
512 && GET_CODE (XEXP (note, 0)) == REG
513 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
520 /* Returns zero if X is known to be invariant. */
523 equiv_init_varies_p (x)
526 RTX_CODE code = GET_CODE (x);
533 return ! RTX_UNCHANGING_P (x) || equiv_init_varies_p (XEXP (x, 0));
546 return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0);
549 if (MEM_VOLATILE_P (x))
558 fmt = GET_RTX_FORMAT (code);
559 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
562 if (equiv_init_varies_p (XEXP (x, i)))
565 else if (fmt[i] == 'E')
568 for (j = 0; j < XVECLEN (x, i); j++)
569 if (equiv_init_varies_p (XVECEXP (x, i, j)))
576 /* Returns non-zero if X (used to initialize register REGNO) is movable.
577 X is only movable if the registers it uses have equivalent initializations
578 which appear to be within the same loop (or in an inner loop) and movable
579 or if they are not candidates for local_alloc and don't vary. */
582 equiv_init_movable_p (x, regno)
588 enum rtx_code code = GET_CODE (x);
593 return equiv_init_movable_p (SET_SRC (x), regno);
608 return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
609 && reg_equiv[REGNO (x)].replace)
610 || (REG_BASIC_BLOCK (REGNO (x)) < 0 && ! rtx_varies_p (x, 0));
612 case UNSPEC_VOLATILE:
616 if (MEM_VOLATILE_P (x))
625 fmt = GET_RTX_FORMAT (code);
626 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
630 if (! equiv_init_movable_p (XEXP (x, i), regno))
634 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
635 if (! equiv_init_movable_p (XVECEXP (x, i, j), regno))
643 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
646 contains_replace_regs (x)
651 enum rtx_code code = GET_CODE (x);
667 return reg_equiv[REGNO (x)].replace;
673 fmt = GET_RTX_FORMAT (code);
674 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
678 if (contains_replace_regs (XEXP (x, i)))
682 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
683 if (contains_replace_regs (XVECEXP (x, i, j)))
691 /* TRUE if X references a memory location that would be affected by a store
695 memref_referenced_p (memref, x)
701 enum rtx_code code = GET_CODE (x);
717 return (reg_equiv[REGNO (x)].replacement
718 && memref_referenced_p (memref,
719 reg_equiv[REGNO (x)].replacement));
722 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
727 /* If we are setting a MEM, it doesn't count (its address does), but any
728 other SET_DEST that has a MEM in it is referencing the MEM. */
729 if (GET_CODE (SET_DEST (x)) == MEM)
731 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
734 else if (memref_referenced_p (memref, SET_DEST (x)))
737 return memref_referenced_p (memref, SET_SRC (x));
743 fmt = GET_RTX_FORMAT (code);
744 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
748 if (memref_referenced_p (memref, XEXP (x, i)))
752 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
753 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
761 /* TRUE if some insn in the range (START, END] references a memory location
762 that would be affected by a store to MEMREF. */
765 memref_used_between_p (memref, start, end)
772 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
773 insn = NEXT_INSN (insn))
774 if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn)))
780 /* Return nonzero if the rtx X is invariant over the current function. */
782 function_invariant_p (x)
787 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
789 if (GET_CODE (x) == PLUS
790 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
791 && CONSTANT_P (XEXP (x, 1)))
796 /* Find registers that are equivalent to a single value throughout the
797 compilation (either because they can be referenced in memory or are set once
798 from a single constant). Lower their priority for a register.
800 If such a register is only referenced once, try substituting its value
801 into the using insn. If it succeeds, we can eliminate the register
810 regset_head cleared_regs;
811 int clear_regnos = 0;
813 reg_equiv = (struct equivalence *) xcalloc (max_regno, sizeof *reg_equiv);
814 INIT_REG_SET (&cleared_regs);
816 init_alias_analysis ();
818 /* Scan the insns and find which registers have equivalences. Do this
819 in a separate scan of the insns because (due to -fcse-follow-jumps)
820 a register can be set below its use. */
821 for (block = 0; block < n_basic_blocks; block++)
823 basic_block bb = BASIC_BLOCK (block);
824 loop_depth = bb->loop_depth;
826 for (insn = bb->head; insn != NEXT_INSN (bb->end); insn = NEXT_INSN (insn))
836 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
837 if (REG_NOTE_KIND (note) == REG_INC)
838 no_equiv (XEXP (note, 0), note, NULL);
840 set = single_set (insn);
842 /* If this insn contains more (or less) than a single SET,
843 only mark all destinations as having no known equivalence. */
846 note_stores (PATTERN (insn), no_equiv, NULL);
849 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
853 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
855 rtx part = XVECEXP (PATTERN (insn), 0, i);
857 note_stores (part, no_equiv, NULL);
861 dest = SET_DEST (set);
864 /* If this sets a MEM to the contents of a REG that is only used
865 in a single basic block, see if the register is always equivalent
866 to that memory location and if moving the store from INSN to the
867 insn that set REG is safe. If so, put a REG_EQUIV note on the
870 Don't add a REG_EQUIV note if the insn already has one. The existing
871 REG_EQUIV is likely more useful than the one we are adding.
873 If one of the regs in the address has reg_equiv[REGNO].replace set,
874 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
875 optimization may move the set of this register immediately before
876 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
877 the mention in the REG_EQUIV note would be to an uninitialized
879 /* ????? This test isn't good enough; we might see a MEM with a use of
880 a pseudo register before we see its setting insn that will cause
881 reg_equiv[].replace for that pseudo to be set.
882 Equivalences to MEMs should be made in another pass, after the
883 reg_equiv[].replace information has been gathered. */
885 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
886 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
887 && REG_BASIC_BLOCK (regno) >= 0
888 && REG_N_SETS (regno) == 1
889 && reg_equiv[regno].init_insns != 0
890 && reg_equiv[regno].init_insns != const0_rtx
891 && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0),
893 && ! contains_replace_regs (XEXP (dest, 0)))
895 rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0);
896 if (validate_equiv_mem (init_insn, src, dest)
897 && ! memref_used_between_p (dest, init_insn, insn))
898 REG_NOTES (init_insn)
899 = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn));
902 /* We only handle the case of a pseudo register being set
903 once, or always to the same value. */
904 /* ??? The mn10200 port breaks if we add equivalences for
905 values that need an ADDRESS_REGS register and set them equivalent
906 to a MEM of a pseudo. The actual problem is in the over-conservative
907 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
908 calculate_needs, but we traditionally work around this problem
909 here by rejecting equivalences when the destination is in a register
910 that's likely spilled. This is fragile, of course, since the
911 preferred class of a pseudo depends on all instructions that set
914 if (GET_CODE (dest) != REG
915 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
916 || reg_equiv[regno].init_insns == const0_rtx
917 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
918 && GET_CODE (src) == MEM))
920 /* This might be seting a SUBREG of a pseudo, a pseudo that is
921 also set somewhere else to a constant. */
922 note_stores (set, no_equiv, NULL);
926 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
928 /* cse sometimes generates function invariants, but doesn't put a
929 REG_EQUAL note on the insn. Since this note would be redundant,
930 there's no point creating it earlier than here. Don't do this
931 for ASM_OPERANDS since eliminate_regs doesn't support it and
932 it serves no useful purpose. */
933 if (! note && ! rtx_varies_p (src, 0)
934 && GET_CODE (src) != ASM_OPERANDS)
936 = note = gen_rtx_EXPR_LIST (REG_EQUAL, src, REG_NOTES (insn));
938 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
939 since it represents a function call */
940 if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST)
943 if (REG_N_SETS (regno) != 1
945 || rtx_varies_p (XEXP (note, 0), 0)
946 || (reg_equiv[regno].replacement
947 && ! rtx_equal_p (XEXP (note, 0),
948 reg_equiv[regno].replacement))))
950 no_equiv (dest, set, NULL);
953 /* Record this insn as initializing this register. */
954 reg_equiv[regno].init_insns
955 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns);
957 /* If this register is known to be equal to a constant, record that
958 it is always equivalent to the constant. */
959 if (note && ! rtx_varies_p (XEXP (note, 0), 0))
960 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
962 /* If this insn introduces a "constant" register, decrease the priority
963 of that register. Record this insn if the register is only used once
964 more and the equivalence value is the same as our source.
966 The latter condition is checked for two reasons: First, it is an
967 indication that it may be more efficient to actually emit the insn
968 as written (if no registers are available, reload will substitute
969 the equivalence). Secondly, it avoids problems with any registers
970 dying in this insn whose death notes would be missed.
972 If we don't have a REG_EQUIV note, see if this insn is loading
973 a register used only in one basic block from a MEM. If so, and the
974 MEM remains unchanged for the life of the register, add a REG_EQUIV
977 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
979 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
980 && GET_CODE (SET_SRC (set)) == MEM
981 && validate_equiv_mem (insn, dest, SET_SRC (set)))
982 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
987 int regno = REGNO (dest);
989 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
990 We might end up substituting the LABEL_REF for uses of the
991 pseudo here or later. That kind of transformation may turn an
992 indirect jump into a direct jump, in which case we must rerun the
993 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
994 if (GET_CODE (XEXP (note, 0)) == LABEL_REF
995 || (GET_CODE (XEXP (note, 0)) == CONST
996 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
997 && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0))
999 recorded_label_ref = 1;
1001 reg_equiv[regno].replacement = XEXP (note, 0);
1002 reg_equiv[regno].src = src;
1003 reg_equiv[regno].loop_depth = loop_depth;
1005 /* Don't mess with things live during setjmp. */
1006 if (REG_LIVE_LENGTH (regno) >= 0 && optimize)
1008 /* Note that the statement below does not affect the priority
1010 REG_LIVE_LENGTH (regno) *= 2;
1013 /* If the register is referenced exactly twice, meaning it is
1014 set once and used once, indicate that the reference may be
1015 replaced by the equivalence we computed above. Do this
1016 even if the register is only used in one block so that
1017 dependencies can be handled where the last register is
1018 used in a different block (i.e. HIGH / LO_SUM sequences)
1019 and to reduce the number of registers alive across
1022 if (REG_N_REFS (regno) == 2
1023 && (rtx_equal_p (XEXP (note, 0), src)
1024 || ! equiv_init_varies_p (src))
1025 && GET_CODE (insn) == INSN
1026 && equiv_init_movable_p (PATTERN (insn), regno))
1027 reg_equiv[regno].replace = 1;
1033 /* Now scan all regs killed in an insn to see if any of them are
1034 registers only used that once. If so, see if we can replace the
1035 reference with the equivalent from. If we can, delete the
1036 initializing reference and this register will go away. If we
1037 can't replace the reference, and the initialzing reference is
1038 within the same loop (or in an inner loop), then move the register
1039 initialization just before the use, so that they are in the same
1041 for (block = n_basic_blocks - 1; block >= 0; block--)
1043 basic_block bb = BASIC_BLOCK (block);
1045 loop_depth = bb->loop_depth;
1046 for (insn = bb->end; insn != PREV_INSN (bb->head); insn = PREV_INSN (insn))
1050 if (! INSN_P (insn))
1053 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1055 if (REG_NOTE_KIND (link) == REG_DEAD
1056 /* Make sure this insn still refers to the register. */
1057 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1059 int regno = REGNO (XEXP (link, 0));
1062 if (! reg_equiv[regno].replace
1063 || reg_equiv[regno].loop_depth < loop_depth)
1066 /* reg_equiv[REGNO].replace gets set only when
1067 REG_N_REFS[REGNO] is 2, i.e. the register is set
1068 once and used once. (If it were only set, but not used,
1069 flow would have deleted the setting insns.) Hence
1070 there can only be one insn in reg_equiv[REGNO].init_insns. */
1071 if (reg_equiv[regno].init_insns == NULL_RTX
1072 || XEXP (reg_equiv[regno].init_insns, 1) != NULL_RTX)
1074 equiv_insn = XEXP (reg_equiv[regno].init_insns, 0);
1076 /* We may not move instructions that can throw, since
1077 that changes basic block boundaries and we are not
1078 prepared to adjust the CFG to match. */
1079 if (can_throw_internal (equiv_insn))
1082 if (asm_noperands (PATTERN (equiv_insn)) < 0
1083 && validate_replace_rtx (regno_reg_rtx[regno],
1084 reg_equiv[regno].src, insn))
1090 /* Find the last note. */
1091 for (last_link = link; XEXP (last_link, 1);
1092 last_link = XEXP (last_link, 1))
1095 /* Append the REG_DEAD notes from equiv_insn. */
1096 equiv_link = REG_NOTES (equiv_insn);
1100 equiv_link = XEXP (equiv_link, 1);
1101 if (REG_NOTE_KIND (note) == REG_DEAD)
1103 remove_note (equiv_insn, note);
1104 XEXP (last_link, 1) = note;
1105 XEXP (note, 1) = NULL_RTX;
1110 remove_death (regno, insn);
1111 REG_N_REFS (regno) = 0;
1112 REG_FREQ (regno) = 0;
1113 delete_insn (equiv_insn);
1115 reg_equiv[regno].init_insns
1116 = XEXP (reg_equiv[regno].init_insns, 1);
1118 /* Move the initialization of the register to just before
1119 INSN. Update the flow information. */
1120 else if (PREV_INSN (insn) != equiv_insn)
1124 new_insn = emit_insn_before (PATTERN (equiv_insn), insn);
1125 REG_NOTES (new_insn) = REG_NOTES (equiv_insn);
1126 REG_NOTES (equiv_insn) = 0;
1128 /* Make sure this insn is recognized before reload begins,
1129 otherwise eliminate_regs_in_insn will abort. */
1130 INSN_CODE (new_insn) = INSN_CODE (equiv_insn);
1132 delete_insn (equiv_insn);
1134 XEXP (reg_equiv[regno].init_insns, 0) = new_insn;
1136 REG_BASIC_BLOCK (regno) = block >= 0 ? block : 0;
1137 REG_N_CALLS_CROSSED (regno) = 0;
1138 REG_LIVE_LENGTH (regno) = 2;
1140 if (block >= 0 && insn == BLOCK_HEAD (block))
1141 BLOCK_HEAD (block) = PREV_INSN (insn);
1143 /* Remember to clear REGNO from all basic block's live
1145 SET_REGNO_REG_SET (&cleared_regs, regno);
1153 /* Clear all dead REGNOs from all basic block's live info. */
1157 if (clear_regnos > 8)
1159 for (l = 0; l < n_basic_blocks; l++)
1161 AND_COMPL_REG_SET (BASIC_BLOCK (l)->global_live_at_start,
1163 AND_COMPL_REG_SET (BASIC_BLOCK (l)->global_live_at_end,
1168 EXECUTE_IF_SET_IN_REG_SET (&cleared_regs, 0, j,
1170 for (l = 0; l < n_basic_blocks; l++)
1172 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_start, j);
1173 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_end, j);
1179 end_alias_analysis ();
1180 CLEAR_REG_SET (&cleared_regs);
1184 /* Mark REG as having no known equivalence.
1185 Some instructions might have been proceessed before and furnished
1186 with REG_EQUIV notes for this register; these notes will have to be
1188 STORE is the piece of RTL that does the non-constant / conflicting
1189 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1190 but needs to be there because this function is called from note_stores. */
1192 no_equiv (reg, store, data)
1193 rtx reg, store ATTRIBUTE_UNUSED;
1194 void *data ATTRIBUTE_UNUSED;
1199 if (GET_CODE (reg) != REG)
1201 regno = REGNO (reg);
1202 list = reg_equiv[regno].init_insns;
1203 if (list == const0_rtx)
1205 for (; list; list = XEXP (list, 1))
1207 rtx insn = XEXP (list, 0);
1208 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
1210 reg_equiv[regno].init_insns = const0_rtx;
1211 reg_equiv[regno].replacement = NULL_RTX;
1214 /* Allocate hard regs to the pseudo regs used only within block number B.
1215 Only the pseudos that die but once can be handled. */
1224 int insn_number = 0;
1226 int max_uid = get_max_uid ();
1228 int no_conflict_combined_regno = -1;
1230 /* Count the instructions in the basic block. */
1232 insn = BLOCK_END (b);
1235 if (GET_CODE (insn) != NOTE)
1236 if (++insn_count > max_uid)
1238 if (insn == BLOCK_HEAD (b))
1240 insn = PREV_INSN (insn);
1243 /* +2 to leave room for a post_mark_life at the last insn and for
1244 the birth of a CLOBBER in the first insn. */
1245 regs_live_at = (HARD_REG_SET *) xcalloc ((2 * insn_count + 2),
1246 sizeof (HARD_REG_SET));
1248 /* Initialize table of hardware registers currently live. */
1250 REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start);
1252 /* This loop scans the instructions of the basic block
1253 and assigns quantities to registers.
1254 It computes which registers to tie. */
1256 insn = BLOCK_HEAD (b);
1259 if (GET_CODE (insn) != NOTE)
1266 rtx r0, r1 = NULL_RTX;
1267 int combined_regno = -1;
1270 this_insn_number = insn_number;
1273 extract_insn (insn);
1274 which_alternative = -1;
1276 /* Is this insn suitable for tying two registers?
1277 If so, try doing that.
1278 Suitable insns are those with at least two operands and where
1279 operand 0 is an output that is a register that is not
1282 We can tie operand 0 with some operand that dies in this insn.
1283 First look for operands that are required to be in the same
1284 register as operand 0. If we find such, only try tying that
1285 operand or one that can be put into that operand if the
1286 operation is commutative. If we don't find an operand
1287 that is required to be in the same register as operand 0,
1288 we can tie with any operand.
1290 Subregs in place of regs are also ok.
1292 If tying is done, WIN is set nonzero. */
1295 && recog_data.n_operands > 1
1296 && recog_data.constraints[0][0] == '='
1297 && recog_data.constraints[0][1] != '&')
1299 /* If non-negative, is an operand that must match operand 0. */
1300 int must_match_0 = -1;
1301 /* Counts number of alternatives that require a match with
1303 int n_matching_alts = 0;
1305 for (i = 1; i < recog_data.n_operands; i++)
1307 const char *p = recog_data.constraints[i];
1308 int this_match = requires_inout (p);
1310 n_matching_alts += this_match;
1311 if (this_match == recog_data.n_alternatives)
1315 r0 = recog_data.operand[0];
1316 for (i = 1; i < recog_data.n_operands; i++)
1318 /* Skip this operand if we found an operand that
1319 must match operand 0 and this operand isn't it
1320 and can't be made to be it by commutativity. */
1322 if (must_match_0 >= 0 && i != must_match_0
1323 && ! (i == must_match_0 + 1
1324 && recog_data.constraints[i-1][0] == '%')
1325 && ! (i == must_match_0 - 1
1326 && recog_data.constraints[i][0] == '%'))
1329 /* Likewise if each alternative has some operand that
1330 must match operand zero. In that case, skip any
1331 operand that doesn't list operand 0 since we know that
1332 the operand always conflicts with operand 0. We
1333 ignore commutatity in this case to keep things simple. */
1334 if (n_matching_alts == recog_data.n_alternatives
1335 && 0 == requires_inout (recog_data.constraints[i]))
1338 r1 = recog_data.operand[i];
1340 /* If the operand is an address, find a register in it.
1341 There may be more than one register, but we only try one
1343 if (recog_data.constraints[i][0] == 'p')
1344 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1347 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1349 /* We have two priorities for hard register preferences.
1350 If we have a move insn or an insn whose first input
1351 can only be in the same register as the output, give
1352 priority to an equivalence found from that insn. */
1354 = (r1 == recog_data.operand[i] && must_match_0 >= 0);
1356 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1357 win = combine_regs (r1, r0, may_save_copy,
1358 insn_number, insn, 0);
1365 /* Recognize an insn sequence with an ultimate result
1366 which can safely overlap one of the inputs.
1367 The sequence begins with a CLOBBER of its result,
1368 and ends with an insn that copies the result to itself
1369 and has a REG_EQUAL note for an equivalent formula.
1370 That note indicates what the inputs are.
1371 The result and the input can overlap if each insn in
1372 the sequence either doesn't mention the input
1373 or has a REG_NO_CONFLICT note to inhibit the conflict.
1375 We do the combining test at the CLOBBER so that the
1376 destination register won't have had a quantity number
1377 assigned, since that would prevent combining. */
1380 && GET_CODE (PATTERN (insn)) == CLOBBER
1381 && (r0 = XEXP (PATTERN (insn), 0),
1382 GET_CODE (r0) == REG)
1383 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1384 && XEXP (link, 0) != 0
1385 && GET_CODE (XEXP (link, 0)) == INSN
1386 && (set = single_set (XEXP (link, 0))) != 0
1387 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1388 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1391 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1392 /* Check that we have such a sequence. */
1393 && no_conflict_p (insn, r0, r1))
1394 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1395 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1396 && (r1 = XEXP (XEXP (note, 0), 0),
1397 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1398 && no_conflict_p (insn, r0, r1))
1399 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1401 /* Here we care if the operation to be computed is
1403 else if ((GET_CODE (XEXP (note, 0)) == EQ
1404 || GET_CODE (XEXP (note, 0)) == NE
1405 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1406 && (r1 = XEXP (XEXP (note, 0), 1),
1407 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1408 && no_conflict_p (insn, r0, r1))
1409 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1411 /* If we did combine something, show the register number
1412 in question so that we know to ignore its death. */
1414 no_conflict_combined_regno = REGNO (r1);
1417 /* If registers were just tied, set COMBINED_REGNO
1418 to the number of the register used in this insn
1419 that was tied to the register set in this insn.
1420 This register's qty should not be "killed". */
1424 while (GET_CODE (r1) == SUBREG)
1425 r1 = SUBREG_REG (r1);
1426 combined_regno = REGNO (r1);
1429 /* Mark the death of everything that dies in this instruction,
1430 except for anything that was just combined. */
1432 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1433 if (REG_NOTE_KIND (link) == REG_DEAD
1434 && GET_CODE (XEXP (link, 0)) == REG
1435 && combined_regno != (int) REGNO (XEXP (link, 0))
1436 && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0))
1437 || ! find_reg_note (insn, REG_NO_CONFLICT,
1439 wipe_dead_reg (XEXP (link, 0), 0);
1441 /* Allocate qty numbers for all registers local to this block
1442 that are born (set) in this instruction.
1443 A pseudo that already has a qty is not changed. */
1445 note_stores (PATTERN (insn), reg_is_set, NULL);
1447 /* If anything is set in this insn and then unused, mark it as dying
1448 after this insn, so it will conflict with our outputs. This
1449 can't match with something that combined, and it doesn't matter
1450 if it did. Do this after the calls to reg_is_set since these
1451 die after, not during, the current insn. */
1453 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1454 if (REG_NOTE_KIND (link) == REG_UNUSED
1455 && GET_CODE (XEXP (link, 0)) == REG)
1456 wipe_dead_reg (XEXP (link, 0), 1);
1458 /* If this is an insn that has a REG_RETVAL note pointing at a
1459 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1460 block, so clear any register number that combined within it. */
1461 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1462 && GET_CODE (XEXP (note, 0)) == INSN
1463 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1464 no_conflict_combined_regno = -1;
1467 /* Set the registers live after INSN_NUMBER. Note that we never
1468 record the registers live before the block's first insn, since no
1469 pseudos we care about are live before that insn. */
1471 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1472 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1474 if (insn == BLOCK_END (b))
1477 insn = NEXT_INSN (insn);
1480 /* Now every register that is local to this basic block
1481 should have been given a quantity, or else -1 meaning ignore it.
1482 Every quantity should have a known birth and death.
1484 Order the qtys so we assign them registers in order of the
1485 number of suggested registers they need so we allocate those with
1486 the most restrictive needs first. */
1488 qty_order = (int *) xmalloc (next_qty * sizeof (int));
1489 for (i = 0; i < next_qty; i++)
1492 #define EXCHANGE(I1, I2) \
1493 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1498 /* Make qty_order[2] be the one to allocate last. */
1499 if (qty_sugg_compare (0, 1) > 0)
1501 if (qty_sugg_compare (1, 2) > 0)
1504 /* ... Fall through ... */
1506 /* Put the best one to allocate in qty_order[0]. */
1507 if (qty_sugg_compare (0, 1) > 0)
1510 /* ... Fall through ... */
1514 /* Nothing to do here. */
1518 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1521 /* Try to put each quantity in a suggested physical register, if it has one.
1522 This may cause registers to be allocated that otherwise wouldn't be, but
1523 this seems acceptable in local allocation (unlike global allocation). */
1524 for (i = 0; i < next_qty; i++)
1527 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1528 qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q,
1529 0, 1, qty[q].birth, qty[q].death);
1531 qty[q].phys_reg = -1;
1534 /* Order the qtys so we assign them registers in order of
1535 decreasing length of life. Normally call qsort, but if we
1536 have only a very small number of quantities, sort them ourselves. */
1538 for (i = 0; i < next_qty; i++)
1541 #define EXCHANGE(I1, I2) \
1542 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1547 /* Make qty_order[2] be the one to allocate last. */
1548 if (qty_compare (0, 1) > 0)
1550 if (qty_compare (1, 2) > 0)
1553 /* ... Fall through ... */
1555 /* Put the best one to allocate in qty_order[0]. */
1556 if (qty_compare (0, 1) > 0)
1559 /* ... Fall through ... */
1563 /* Nothing to do here. */
1567 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1570 /* Now for each qty that is not a hardware register,
1571 look for a hardware register to put it in.
1572 First try the register class that is cheapest for this qty,
1573 if there is more than one class. */
1575 for (i = 0; i < next_qty; i++)
1578 if (qty[q].phys_reg < 0)
1580 #ifdef INSN_SCHEDULING
1581 /* These values represent the adjusted lifetime of a qty so
1582 that it conflicts with qtys which appear near the start/end
1583 of this qty's lifetime.
1585 The purpose behind extending the lifetime of this qty is to
1586 discourage the register allocator from creating false
1589 The adjustment value is chosen to indicate that this qty
1590 conflicts with all the qtys in the instructions immediately
1591 before and after the lifetime of this qty.
1593 Experiments have shown that higher values tend to hurt
1594 overall code performance.
1596 If allocation using the extended lifetime fails we will try
1597 again with the qty's unadjusted lifetime. */
1598 int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2);
1599 int fake_death = MIN (insn_number * 2 + 1,
1600 qty[q].death + 2 - qty[q].death % 2);
1603 if (N_REG_CLASSES > 1)
1605 #ifdef INSN_SCHEDULING
1606 /* We try to avoid using hard registers allocated to qtys which
1607 are born immediately after this qty or die immediately before
1610 This optimization is only appropriate when we will run
1611 a scheduling pass after reload and we are not optimizing
1613 if (flag_schedule_insns_after_reload
1615 && !SMALL_REGISTER_CLASSES)
1617 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1618 qty[q].mode, q, 0, 0,
1619 fake_birth, fake_death);
1620 if (qty[q].phys_reg >= 0)
1624 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1625 qty[q].mode, q, 0, 0,
1626 qty[q].birth, qty[q].death);
1627 if (qty[q].phys_reg >= 0)
1631 #ifdef INSN_SCHEDULING
1632 /* Similarly, avoid false dependencies. */
1633 if (flag_schedule_insns_after_reload
1635 && !SMALL_REGISTER_CLASSES
1636 && qty[q].alternate_class != NO_REGS)
1637 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1638 qty[q].mode, q, 0, 0,
1639 fake_birth, fake_death);
1641 if (qty[q].alternate_class != NO_REGS)
1642 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1643 qty[q].mode, q, 0, 0,
1644 qty[q].birth, qty[q].death);
1648 /* Now propagate the register assignments
1649 to the pseudo regs belonging to the qtys. */
1651 for (q = 0; q < next_qty; q++)
1652 if (qty[q].phys_reg >= 0)
1654 for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i])
1655 reg_renumber[i] = qty[q].phys_reg + reg_offset[i];
1659 free (regs_live_at);
1663 /* Compare two quantities' priority for getting real registers.
1664 We give shorter-lived quantities higher priority.
1665 Quantities with more references are also preferred, as are quantities that
1666 require multiple registers. This is the identical prioritization as
1667 done by global-alloc.
1669 We used to give preference to registers with *longer* lives, but using
1670 the same algorithm in both local- and global-alloc can speed up execution
1671 of some programs by as much as a factor of three! */
1673 /* Note that the quotient will never be bigger than
1674 the value of floor_log2 times the maximum number of
1675 times a register can occur in one insn (surely less than 100)
1676 weighted by frequency (max REG_FREQ_MAX).
1677 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1678 QTY_CMP_PRI is also used by qty_sugg_compare. */
1680 #define QTY_CMP_PRI(q) \
1681 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1682 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1685 qty_compare (q1, q2)
1688 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1692 qty_compare_1 (q1p, q2p)
1696 int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1697 int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1702 /* If qtys are equally good, sort by qty number,
1703 so that the results of qsort leave nothing to chance. */
1707 /* Compare two quantities' priority for getting real registers. This version
1708 is called for quantities that have suggested hard registers. First priority
1709 goes to quantities that have copy preferences, then to those that have
1710 normal preferences. Within those groups, quantities with the lower
1711 number of preferences have the highest priority. Of those, we use the same
1712 algorithm as above. */
1714 #define QTY_CMP_SUGG(q) \
1715 (qty_phys_num_copy_sugg[q] \
1716 ? qty_phys_num_copy_sugg[q] \
1717 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1720 qty_sugg_compare (q1, q2)
1723 int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1728 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1732 qty_sugg_compare_1 (q1p, q2p)
1736 int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1737 int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1742 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1746 /* If qtys are equally good, sort by qty number,
1747 so that the results of qsort leave nothing to chance. */
1754 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1755 Returns 1 if have done so, or 0 if cannot.
1757 Combining registers means marking them as having the same quantity
1758 and adjusting the offsets within the quantity if either of
1761 We don't actually combine a hard reg with a pseudo; instead
1762 we just record the hard reg as the suggestion for the pseudo's quantity.
1763 If we really combined them, we could lose if the pseudo lives
1764 across an insn that clobbers the hard reg (eg, movstr).
1766 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1767 there is no REG_DEAD note on INSN. This occurs during the processing
1768 of REG_NO_CONFLICT blocks.
1770 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1771 SETREG or if the input and output must share a register.
1772 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1774 There are elaborate checks for the validity of combining. */
1777 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1778 rtx usedreg, setreg;
1789 /* Determine the numbers and sizes of registers being used. If a subreg
1790 is present that does not change the entire register, don't consider
1791 this a copy insn. */
1793 while (GET_CODE (usedreg) == SUBREG)
1795 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1797 if (REGNO (SUBREG_REG (usedreg)) < FIRST_PSEUDO_REGISTER)
1798 offset += subreg_regno_offset (REGNO (SUBREG_REG (usedreg)),
1799 GET_MODE (SUBREG_REG (usedreg)),
1800 SUBREG_BYTE (usedreg),
1801 GET_MODE (usedreg));
1803 offset += (SUBREG_BYTE (usedreg)
1804 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg)));
1805 usedreg = SUBREG_REG (usedreg);
1807 if (GET_CODE (usedreg) != REG)
1809 ureg = REGNO (usedreg);
1810 if (ureg < FIRST_PSEUDO_REGISTER)
1811 usize = HARD_REGNO_NREGS (ureg, GET_MODE (usedreg));
1813 usize = ((GET_MODE_SIZE (GET_MODE (usedreg))
1814 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg)) - 1))
1815 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg)));
1817 while (GET_CODE (setreg) == SUBREG)
1819 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1821 if (REGNO (SUBREG_REG (setreg)) < FIRST_PSEUDO_REGISTER)
1822 offset -= subreg_regno_offset (REGNO (SUBREG_REG (setreg)),
1823 GET_MODE (SUBREG_REG (setreg)),
1824 SUBREG_BYTE (setreg),
1827 offset -= (SUBREG_BYTE (setreg)
1828 / REGMODE_NATURAL_SIZE (GET_MODE (setreg)));
1829 setreg = SUBREG_REG (setreg);
1831 if (GET_CODE (setreg) != REG)
1833 sreg = REGNO (setreg);
1834 if (sreg < FIRST_PSEUDO_REGISTER)
1835 ssize = HARD_REGNO_NREGS (sreg, GET_MODE (setreg));
1837 ssize = ((GET_MODE_SIZE (GET_MODE (setreg))
1838 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg)) - 1))
1839 / REGMODE_NATURAL_SIZE (GET_MODE (setreg)));
1841 /* If UREG is a pseudo-register that hasn't already been assigned a
1842 quantity number, it means that it is not local to this block or dies
1843 more than once. In either event, we can't do anything with it. */
1844 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1845 /* Do not combine registers unless one fits within the other. */
1846 || (offset > 0 && usize + offset > ssize)
1847 || (offset < 0 && usize + offset < ssize)
1848 /* Do not combine with a smaller already-assigned object
1849 if that smaller object is already combined with something bigger. */
1850 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1851 && usize < qty[reg_qty[ureg]].size)
1852 /* Can't combine if SREG is not a register we can allocate. */
1853 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1854 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1855 These have already been taken care of. This probably wouldn't
1856 combine anyway, but don't take any chances. */
1857 || (ureg >= FIRST_PSEUDO_REGISTER
1858 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1859 /* Don't tie something to itself. In most cases it would make no
1860 difference, but it would screw up if the reg being tied to itself
1861 also dies in this insn. */
1863 /* Don't try to connect two different hardware registers. */
1864 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1865 /* Don't connect two different machine modes if they have different
1866 implications as to which registers may be used. */
1867 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1870 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1871 qty_phys_sugg for the pseudo instead of tying them.
1873 Return "failure" so that the lifespan of UREG is terminated here;
1874 that way the two lifespans will be disjoint and nothing will prevent
1875 the pseudo reg from being given this hard reg. */
1877 if (ureg < FIRST_PSEUDO_REGISTER)
1879 /* Allocate a quantity number so we have a place to put our
1881 if (reg_qty[sreg] == -2)
1882 reg_is_born (setreg, 2 * insn_number);
1884 if (reg_qty[sreg] >= 0)
1887 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1889 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1890 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1892 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1894 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1895 qty_phys_num_sugg[reg_qty[sreg]]++;
1901 /* Similarly for SREG a hard register and UREG a pseudo register. */
1903 if (sreg < FIRST_PSEUDO_REGISTER)
1906 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1908 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1909 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1911 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1913 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1914 qty_phys_num_sugg[reg_qty[ureg]]++;
1919 /* At this point we know that SREG and UREG are both pseudos.
1920 Do nothing if SREG already has a quantity or is a register that we
1922 if (reg_qty[sreg] >= -1
1923 /* If we are not going to let any regs live across calls,
1924 don't tie a call-crossing reg to a non-call-crossing reg. */
1925 || (current_function_has_nonlocal_label
1926 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1927 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1930 /* We don't already know about SREG, so tie it to UREG
1931 if this is the last use of UREG, provided the classes they want
1934 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1935 && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class))
1937 /* Add SREG to UREG's quantity. */
1938 sqty = reg_qty[ureg];
1939 reg_qty[sreg] = sqty;
1940 reg_offset[sreg] = reg_offset[ureg] + offset;
1941 reg_next_in_qty[sreg] = qty[sqty].first_reg;
1942 qty[sqty].first_reg = sreg;
1944 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1945 update_qty_class (sqty, sreg);
1947 /* Update info about quantity SQTY. */
1948 qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg);
1949 qty[sqty].n_refs += REG_N_REFS (sreg);
1950 qty[sqty].freq += REG_FREQ (sreg);
1955 for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i])
1956 reg_offset[i] -= offset;
1958 qty[sqty].size = ssize;
1959 qty[sqty].mode = GET_MODE (setreg);
1968 /* Return 1 if the preferred class of REG allows it to be tied
1969 to a quantity or register whose class is CLASS.
1970 True if REG's reg class either contains or is contained in CLASS. */
1973 reg_meets_class_p (reg, class)
1975 enum reg_class class;
1977 enum reg_class rclass = reg_preferred_class (reg);
1978 return (reg_class_subset_p (rclass, class)
1979 || reg_class_subset_p (class, rclass));
1982 /* Update the class of QTYNO assuming that REG is being tied to it. */
1985 update_qty_class (qtyno, reg)
1989 enum reg_class rclass = reg_preferred_class (reg);
1990 if (reg_class_subset_p (rclass, qty[qtyno].min_class))
1991 qty[qtyno].min_class = rclass;
1993 rclass = reg_alternate_class (reg);
1994 if (reg_class_subset_p (rclass, qty[qtyno].alternate_class))
1995 qty[qtyno].alternate_class = rclass;
1997 if (REG_CHANGES_MODE (reg))
1998 qty[qtyno].changes_mode = 1;
2001 /* Handle something which alters the value of an rtx REG.
2003 REG is whatever is set or clobbered. SETTER is the rtx that
2004 is modifying the register.
2006 If it is not really a register, we do nothing.
2007 The file-global variables `this_insn' and `this_insn_number'
2008 carry info from `block_alloc'. */
2011 reg_is_set (reg, setter, data)
2014 void *data ATTRIBUTE_UNUSED;
2016 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2017 a hard register. These may actually not exist any more. */
2019 if (GET_CODE (reg) != SUBREG
2020 && GET_CODE (reg) != REG)
2023 /* Mark this register as being born. If it is used in a CLOBBER, mark
2024 it as being born halfway between the previous insn and this insn so that
2025 it conflicts with our inputs but not the outputs of the previous insn. */
2027 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
2030 /* Handle beginning of the life of register REG.
2031 BIRTH is the index at which this is happening. */
2034 reg_is_born (reg, birth)
2040 if (GET_CODE (reg) == SUBREG)
2042 regno = REGNO (SUBREG_REG (reg));
2043 if (regno < FIRST_PSEUDO_REGISTER)
2044 regno = subreg_hard_regno (reg, 1);
2047 regno = REGNO (reg);
2049 if (regno < FIRST_PSEUDO_REGISTER)
2051 mark_life (regno, GET_MODE (reg), 1);
2053 /* If the register was to have been born earlier that the present
2054 insn, mark it as live where it is actually born. */
2055 if (birth < 2 * this_insn_number)
2056 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
2060 if (reg_qty[regno] == -2)
2061 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2063 /* If this register has a quantity number, show that it isn't dead. */
2064 if (reg_qty[regno] >= 0)
2065 qty[reg_qty[regno]].death = -1;
2069 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2070 REG is an output that is dying (i.e., it is never used), otherwise it
2071 is an input (the normal case).
2072 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2075 wipe_dead_reg (reg, output_p)
2079 int regno = REGNO (reg);
2081 /* If this insn has multiple results,
2082 and the dead reg is used in one of the results,
2083 extend its life to after this insn,
2084 so it won't get allocated together with any other result of this insn.
2086 It is unsafe to use !single_set here since it will ignore an unused
2087 output. Just because an output is unused does not mean the compiler
2088 can assume the side effect will not occur. Consider if REG appears
2089 in the address of an output and we reload the output. If we allocate
2090 REG to the same hard register as an unused output we could set the hard
2091 register before the output reload insn. */
2092 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2093 && multiple_sets (this_insn))
2096 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2098 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2099 if (GET_CODE (set) == SET
2100 && GET_CODE (SET_DEST (set)) != REG
2101 && !rtx_equal_p (reg, SET_DEST (set))
2102 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2107 /* If this register is used in an auto-increment address, then extend its
2108 life to after this insn, so that it won't get allocated together with
2109 the result of this insn. */
2110 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2113 if (regno < FIRST_PSEUDO_REGISTER)
2115 mark_life (regno, GET_MODE (reg), 0);
2117 /* If a hard register is dying as an output, mark it as in use at
2118 the beginning of this insn (the above statement would cause this
2121 post_mark_life (regno, GET_MODE (reg), 1,
2122 2 * this_insn_number, 2 * this_insn_number + 1);
2125 else if (reg_qty[regno] >= 0)
2126 qty[reg_qty[regno]].death = 2 * this_insn_number + output_p;
2129 /* Find a block of SIZE words of hard regs in reg_class CLASS
2130 that can hold something of machine-mode MODE
2131 (but actually we test only the first of the block for holding MODE)
2132 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2133 and return the number of the first of them.
2134 Return -1 if such a block cannot be found.
2135 If QTYNO crosses calls, insist on a register preserved by calls,
2136 unless ACCEPT_CALL_CLOBBERED is nonzero.
2138 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2139 register is available. If not, return -1. */
2142 find_free_reg (class, mode, qtyno, accept_call_clobbered, just_try_suggested,
2143 born_index, dead_index)
2144 enum reg_class class;
2145 enum machine_mode mode;
2147 int accept_call_clobbered;
2148 int just_try_suggested;
2149 int born_index, dead_index;
2153 /* Declare it register if it's a scalar. */
2156 HARD_REG_SET used, first_used;
2157 #ifdef ELIMINABLE_REGS
2158 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
2161 /* Validate our parameters. */
2162 if (born_index < 0 || born_index > dead_index)
2165 /* Don't let a pseudo live in a reg across a function call
2166 if we might get a nonlocal goto. */
2167 if (current_function_has_nonlocal_label
2168 && qty[qtyno].n_calls_crossed > 0)
2171 if (accept_call_clobbered)
2172 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2173 else if (qty[qtyno].n_calls_crossed == 0)
2174 COPY_HARD_REG_SET (used, fixed_reg_set);
2176 COPY_HARD_REG_SET (used, call_used_reg_set);
2178 if (accept_call_clobbered)
2179 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2181 for (ins = born_index; ins < dead_index; ins++)
2182 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2184 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2186 /* Don't use the frame pointer reg in local-alloc even if
2187 we may omit the frame pointer, because if we do that and then we
2188 need a frame pointer, reload won't know how to move the pseudo
2189 to another hard reg. It can move only regs made by global-alloc.
2191 This is true of any register that can be eliminated. */
2192 #ifdef ELIMINABLE_REGS
2193 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
2194 SET_HARD_REG_BIT (used, eliminables[i].from);
2195 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2196 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2197 that it might be eliminated into. */
2198 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2201 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2204 #ifdef CLASS_CANNOT_CHANGE_MODE
2205 if (qty[qtyno].changes_mode)
2206 IOR_HARD_REG_SET (used,
2207 reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE]);
2210 /* Normally, the registers that can be used for the first register in
2211 a multi-register quantity are the same as those that can be used for
2212 subsequent registers. However, if just trying suggested registers,
2213 restrict our consideration to them. If there are copy-suggested
2214 register, try them. Otherwise, try the arithmetic-suggested
2216 COPY_HARD_REG_SET (first_used, used);
2218 if (just_try_suggested)
2220 if (qty_phys_num_copy_sugg[qtyno] != 0)
2221 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]);
2223 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]);
2226 /* If all registers are excluded, we can't do anything. */
2227 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2229 /* If at least one would be suitable, test each hard reg. */
2231 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2233 #ifdef REG_ALLOC_ORDER
2234 int regno = reg_alloc_order[i];
2238 if (! TEST_HARD_REG_BIT (first_used, regno)
2239 && HARD_REGNO_MODE_OK (regno, mode)
2240 && (qty[qtyno].n_calls_crossed == 0
2241 || accept_call_clobbered
2242 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
2245 int size1 = HARD_REGNO_NREGS (regno, mode);
2246 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2249 /* Mark that this register is in use between its birth and death
2251 post_mark_life (regno, mode, 1, born_index, dead_index);
2254 #ifndef REG_ALLOC_ORDER
2255 /* Skip starting points we know will lose. */
2262 /* If we are just trying suggested register, we have just tried copy-
2263 suggested registers, and there are arithmetic-suggested registers,
2266 /* If it would be profitable to allocate a call-clobbered register
2267 and save and restore it around calls, do that. */
2268 if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0
2269 && qty_phys_num_sugg[qtyno] != 0)
2271 /* Don't try the copy-suggested regs again. */
2272 qty_phys_num_copy_sugg[qtyno] = 0;
2273 return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1,
2274 born_index, dead_index);
2277 /* We need not check to see if the current function has nonlocal
2278 labels because we don't put any pseudos that are live over calls in
2279 registers in that case. */
2281 if (! accept_call_clobbered
2282 && flag_caller_saves
2283 && ! just_try_suggested
2284 && qty[qtyno].n_calls_crossed != 0
2285 && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs,
2286 qty[qtyno].n_calls_crossed))
2288 i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index);
2290 caller_save_needed = 1;
2296 /* Mark that REGNO with machine-mode MODE is live starting from the current
2297 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2301 mark_life (regno, mode, life)
2303 enum machine_mode mode;
2306 int j = HARD_REGNO_NREGS (regno, mode);
2309 SET_HARD_REG_BIT (regs_live, regno + j);
2312 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2315 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2316 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2317 to insn number DEATH (exclusive). */
2320 post_mark_life (regno, mode, life, birth, death)
2322 enum machine_mode mode;
2323 int life, birth, death;
2325 int j = HARD_REGNO_NREGS (regno, mode);
2327 /* Declare it register if it's a scalar. */
2330 HARD_REG_SET this_reg;
2332 CLEAR_HARD_REG_SET (this_reg);
2334 SET_HARD_REG_BIT (this_reg, regno + j);
2337 while (birth < death)
2339 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2343 while (birth < death)
2345 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2350 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2351 is the register being clobbered, and R1 is a register being used in
2352 the equivalent expression.
2354 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2355 in which it is used, return 1.
2357 Otherwise, return 0. */
2360 no_conflict_p (insn, r0, r1)
2361 rtx insn, r0 ATTRIBUTE_UNUSED, r1;
2364 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2367 /* If R1 is a hard register, return 0 since we handle this case
2368 when we scan the insns that actually use it. */
2371 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2372 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2373 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2376 last = XEXP (note, 0);
2378 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2381 if (find_reg_note (p, REG_DEAD, r1))
2384 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2385 some earlier optimization pass has inserted instructions into
2386 the sequence, and it is not safe to perform this optimization.
2387 Note that emit_no_conflict_block always ensures that this is
2388 true when these sequences are created. */
2389 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2396 /* Return the number of alternatives for which the constraint string P
2397 indicates that the operand must be equal to operand 0 and that no register
2406 int reg_allowed = 0;
2407 int num_matching_alts = 0;
2412 case '=': case '+': case '?':
2413 case '#': case '&': case '!':
2415 case 'm': case '<': case '>': case 'V': case 'o':
2416 case 'E': case 'F': case 'G': case 'H':
2417 case 's': case 'i': case 'n':
2418 case 'I': case 'J': case 'K': case 'L':
2419 case 'M': case 'N': case 'O': case 'P':
2421 /* These don't say anything we care about. */
2425 if (found_zero && ! reg_allowed)
2426 num_matching_alts++;
2428 found_zero = reg_allowed = 0;
2435 case '1': case '2': case '3': case '4': case '5':
2436 case '6': case '7': case '8': case '9':
2437 /* Skip the balance of the matching constraint. */
2438 while (ISDIGIT (*p))
2443 if (REG_CLASS_FROM_LETTER (c) == NO_REGS)
2452 if (found_zero && ! reg_allowed)
2453 num_matching_alts++;
2455 return num_matching_alts;
2459 dump_local_alloc (file)
2463 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2464 if (reg_renumber[i] != -1)
2465 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);