1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 88, 91, 93-6, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here cannot be reallocated by global.c if the hard
59 register is used as a spill register. So we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
66 #include "basic-block.h"
68 #include "hard-reg-set.h"
69 #include "insn-config.h"
73 /* Next quantity number available for allocation. */
77 /* In all the following vectors indexed by quantity number. */
79 /* Element Q is the hard reg number chosen for quantity Q,
80 or -1 if none was found. */
82 static short *qty_phys_reg;
84 /* We maintain two hard register sets that indicate suggested hard registers
85 for each quantity. The first, qty_phys_copy_sugg, contains hard registers
86 that are tied to the quantity by a simple copy. The second contains all
87 hard registers that are tied to the quantity via an arithmetic operation.
89 The former register set is given priority for allocation. This tends to
90 eliminate copy insns. */
92 /* Element Q is a set of hard registers that are suggested for quantity Q by
95 static HARD_REG_SET *qty_phys_copy_sugg;
97 /* Element Q is a set of hard registers that are suggested for quantity Q by
100 static HARD_REG_SET *qty_phys_sugg;
102 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
104 static short *qty_phys_num_copy_sugg;
106 /* Element Q is the number of suggested registers in qty_phys_sugg. */
108 static short *qty_phys_num_sugg;
110 /* Element Q is the number of refs to quantity Q. */
112 static int *qty_n_refs;
114 /* Element Q is a reg class contained in (smaller than) the
115 preferred classes of all the pseudo regs that are tied in quantity Q.
116 This is the preferred class for allocating that quantity. */
118 static enum reg_class *qty_min_class;
120 /* Insn number (counting from head of basic block)
121 where quantity Q was born. -1 if birth has not been recorded. */
123 static int *qty_birth;
125 /* Insn number (counting from head of basic block)
126 where quantity Q died. Due to the way tying is done,
127 and the fact that we consider in this pass only regs that die but once,
128 a quantity can die only once. Each quantity's life span
129 is a set of consecutive insns. -1 if death has not been recorded. */
131 static int *qty_death;
133 /* Number of words needed to hold the data in quantity Q.
134 This depends on its machine mode. It is used for these purposes:
135 1. It is used in computing the relative importances of qtys,
136 which determines the order in which we look for regs for them.
137 2. It is used in rules that prevent tying several registers of
138 different sizes in a way that is geometrically impossible
139 (see combine_regs). */
141 static int *qty_size;
143 /* This holds the mode of the registers that are tied to qty Q,
144 or VOIDmode if registers with differing modes are tied together. */
146 static enum machine_mode *qty_mode;
148 /* Number of times a reg tied to qty Q lives across a CALL_INSN. */
150 static int *qty_n_calls_crossed;
152 /* Register class within which we allocate qty Q if we can't get
153 its preferred class. */
155 static enum reg_class *qty_alternate_class;
157 /* Element Q is the SCRATCH expression for which this quantity is being
158 allocated or 0 if this quantity is allocating registers. */
160 static rtx *qty_scratch_rtx;
162 /* Element Q is nonzero if this quantity has been used in a SUBREG
163 that changes its size. */
165 static char *qty_changes_size;
167 /* Element Q is the register number of one pseudo register whose
168 reg_qty value is Q, or -1 is this quantity is for a SCRATCH. This
169 register should be the head of the chain maintained in reg_next_in_qty. */
171 static int *qty_first_reg;
173 /* If (REG N) has been assigned a quantity number, is a register number
174 of another register assigned the same quantity number, or -1 for the
175 end of the chain. qty_first_reg point to the head of this chain. */
177 static int *reg_next_in_qty;
179 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
181 of -1 if this register cannot be allocated by local-alloc,
182 or -2 if not known yet.
184 Note that if we see a use or death of pseudo register N with
185 reg_qty[N] == -2, register N must be local to the current block. If
186 it were used in more than one block, we would have reg_qty[N] == -1.
187 This relies on the fact that if reg_basic_block[N] is >= 0, register N
188 will not appear in any other block. We save a considerable number of
189 tests by exploiting this.
191 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
196 /* The offset (in words) of register N within its quantity.
197 This can be nonzero if register N is SImode, and has been tied
198 to a subreg of a DImode register. */
200 static char *reg_offset;
202 /* Vector of substitutions of register numbers,
203 used to map pseudo regs into hardware regs.
204 This is set up as a result of register allocation.
205 Element N is the hard reg assigned to pseudo reg N,
206 or is -1 if no hard reg was assigned.
207 If N is a hard reg number, element N is N. */
211 /* Set of hard registers live at the current point in the scan
212 of the instructions in a basic block. */
214 static HARD_REG_SET regs_live;
216 /* Each set of hard registers indicates registers live at a particular
217 point in the basic block. For N even, regs_live_at[N] says which
218 hard registers are needed *after* insn N/2 (i.e., they may not
219 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
221 If an object is to conflict with the inputs of insn J but not the
222 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
223 if it is to conflict with the outputs of insn J but not the inputs of
224 insn J + 1, it is said to die at index J*2 + 1. */
226 static HARD_REG_SET *regs_live_at;
230 int scratch_list_length;
231 static int scratch_index;
233 /* Communicate local vars `insn_number' and `insn'
234 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
235 static int this_insn_number;
236 static rtx this_insn;
238 /* Used to communicate changes made by update_equiv_regs to
239 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
240 found or created, so that we can keep track of what memory accesses might
241 be created later, e.g. by reload. */
243 static rtx *reg_equiv_replacement;
245 static void alloc_qty PROTO((int, enum machine_mode, int, int));
246 static void alloc_qty_for_scratch PROTO((rtx, int, rtx, int, int));
247 static void validate_equiv_mem_from_store PROTO((rtx, rtx));
248 static int validate_equiv_mem PROTO((rtx, rtx, rtx));
249 static int contains_replace_regs PROTO((rtx, char *));
250 static int memref_referenced_p PROTO((rtx, rtx));
251 static int memref_used_between_p PROTO((rtx, rtx, rtx));
252 static void optimize_reg_copy_1 PROTO((rtx, rtx, rtx));
253 static void optimize_reg_copy_2 PROTO((rtx, rtx, rtx));
254 static void update_equiv_regs PROTO((void));
255 static void block_alloc PROTO((int));
256 static int qty_sugg_compare PROTO((int, int));
257 static int qty_sugg_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
258 static int qty_compare PROTO((int, int));
259 static int qty_compare_1 PROTO((const GENERIC_PTR, const GENERIC_PTR));
260 static int combine_regs PROTO((rtx, rtx, int, int, rtx, int));
261 static int reg_meets_class_p PROTO((int, enum reg_class));
262 static int reg_classes_overlap_p PROTO((enum reg_class, enum reg_class,
264 static void update_qty_class PROTO((int, int));
265 static void reg_is_set PROTO((rtx, rtx));
266 static void reg_is_born PROTO((rtx, int));
267 static void wipe_dead_reg PROTO((rtx, int));
268 static int find_free_reg PROTO((enum reg_class, enum machine_mode,
269 int, int, int, int, int));
270 static void mark_life PROTO((int, enum machine_mode, int));
271 static void post_mark_life PROTO((int, enum machine_mode, int, int, int));
272 static int no_conflict_p PROTO((rtx, rtx, rtx));
273 static int requires_inout PROTO((char *));
275 /* Allocate a new quantity (new within current basic block)
276 for register number REGNO which is born at index BIRTH
277 within the block. MODE and SIZE are info on reg REGNO. */
280 alloc_qty (regno, mode, size, birth)
282 enum machine_mode mode;
285 register int qty = next_qty++;
287 reg_qty[regno] = qty;
288 reg_offset[regno] = 0;
289 reg_next_in_qty[regno] = -1;
291 qty_first_reg[qty] = regno;
292 qty_size[qty] = size;
293 qty_mode[qty] = mode;
294 qty_birth[qty] = birth;
295 qty_n_calls_crossed[qty] = REG_N_CALLS_CROSSED (regno);
296 qty_min_class[qty] = reg_preferred_class (regno);
297 qty_alternate_class[qty] = reg_alternate_class (regno);
298 qty_n_refs[qty] = REG_N_REFS (regno);
299 qty_changes_size[qty] = REG_CHANGES_SIZE (regno);
302 /* Similar to `alloc_qty', but allocates a quantity for a SCRATCH rtx
303 used as operand N in INSN. We assume here that the SCRATCH is used in
307 alloc_qty_for_scratch (scratch, n, insn, insn_code_num, insn_number)
311 int insn_code_num, insn_number;
314 enum reg_class class;
318 #ifdef REGISTER_CONSTRAINTS
319 /* If we haven't yet computed which alternative will be used, do so now.
320 Then set P to the constraints for that alternative. */
321 if (which_alternative == -1)
322 if (! constrain_operands (insn_code_num, 0))
325 for (p = insn_operand_constraint[insn_code_num][n], i = 0;
326 *p && i < which_alternative; p++)
330 /* Compute the class required for this SCRATCH. If we don't need a
331 register, the class will remain NO_REGS. If we guessed the alternative
332 number incorrectly, reload will fix things up for us. */
335 while ((c = *p++) != '\0' && c != ',')
338 case '=': case '+': case '?':
339 case '#': case '&': case '!':
341 case '0': case '1': case '2': case '3': case '4':
342 case 'm': case '<': case '>': case 'V': case 'o':
343 case 'E': case 'F': case 'G': case 'H':
344 case 's': case 'i': case 'n':
345 case 'I': case 'J': case 'K': case 'L':
346 case 'M': case 'N': case 'O': case 'P':
347 #ifdef EXTRA_CONSTRAINT
348 case 'Q': case 'R': case 'S': case 'T': case 'U':
351 /* These don't say anything we care about. */
355 /* We don't need to allocate this SCRATCH. */
359 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
364 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)];
368 if (class == NO_REGS)
371 #else /* REGISTER_CONSTRAINTS */
373 class = GENERAL_REGS;
379 qty_first_reg[qty] = -1;
380 qty_scratch_rtx[qty] = scratch;
381 qty_size[qty] = GET_MODE_SIZE (GET_MODE (scratch));
382 qty_mode[qty] = GET_MODE (scratch);
383 qty_birth[qty] = 2 * insn_number - 1;
384 qty_death[qty] = 2 * insn_number + 1;
385 qty_n_calls_crossed[qty] = 0;
386 qty_min_class[qty] = class;
387 qty_alternate_class[qty] = NO_REGS;
389 qty_changes_size[qty] = 0;
392 /* Main entry point of this file. */
400 /* Leaf functions and non-leaf functions have different needs.
401 If defined, let the machine say what kind of ordering we
403 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
404 ORDER_REGS_FOR_LOCAL_ALLOC;
407 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
409 update_equiv_regs ();
411 /* This sets the maximum number of quantities we can have. Quantity
412 numbers start at zero and we can have one for each pseudo plus the
413 number of SCRATCHes in the largest block, in the worst case. */
414 max_qty = (max_regno - FIRST_PSEUDO_REGISTER) + max_scratch;
416 /* Allocate vectors of temporary data.
417 See the declarations of these variables, above,
418 for what they mean. */
420 /* There can be up to MAX_SCRATCH * N_BASIC_BLOCKS SCRATCHes to allocate.
421 Instead of allocating this much memory from now until the end of
422 reload, only allocate space for MAX_QTY SCRATCHes. If there are more
423 reload will allocate them. */
425 scratch_list_length = max_qty;
426 scratch_list = (rtx *) xmalloc (scratch_list_length * sizeof (rtx));
427 bzero ((char *) scratch_list, scratch_list_length * sizeof (rtx));
428 scratch_block = (int *) xmalloc (scratch_list_length * sizeof (int));
429 bzero ((char *) scratch_block, scratch_list_length * sizeof (int));
432 qty_phys_reg = (short *) alloca (max_qty * sizeof (short));
434 = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
435 qty_phys_num_copy_sugg = (short *) alloca (max_qty * sizeof (short));
436 qty_phys_sugg = (HARD_REG_SET *) alloca (max_qty * sizeof (HARD_REG_SET));
437 qty_phys_num_sugg = (short *) alloca (max_qty * sizeof (short));
438 qty_birth = (int *) alloca (max_qty * sizeof (int));
439 qty_death = (int *) alloca (max_qty * sizeof (int));
440 qty_scratch_rtx = (rtx *) alloca (max_qty * sizeof (rtx));
441 qty_first_reg = (int *) alloca (max_qty * sizeof (int));
442 qty_size = (int *) alloca (max_qty * sizeof (int));
444 = (enum machine_mode *) alloca (max_qty * sizeof (enum machine_mode));
445 qty_n_calls_crossed = (int *) alloca (max_qty * sizeof (int));
447 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
449 = (enum reg_class *) alloca (max_qty * sizeof (enum reg_class));
450 qty_n_refs = (int *) alloca (max_qty * sizeof (int));
451 qty_changes_size = (char *) alloca (max_qty * sizeof (char));
453 reg_qty = (int *) alloca (max_regno * sizeof (int));
454 reg_offset = (char *) alloca (max_regno * sizeof (char));
455 reg_next_in_qty = (int *) alloca (max_regno * sizeof (int));
457 /* Allocate the reg_renumber array */
458 allocate_reg_info (max_regno, FALSE, TRUE);
460 /* Determine which pseudo-registers can be allocated by local-alloc.
461 In general, these are the registers used only in a single block and
462 which only die once. However, if a register's preferred class has only
463 a few entries, don't allocate this register here unless it is preferred
464 or nothing since retry_global_alloc won't be able to move it to
465 GENERAL_REGS if a reload register of this class is needed.
467 We need not be concerned with which block actually uses the register
468 since we will never see it outside that block. */
470 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
472 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1
473 && (reg_alternate_class (i) == NO_REGS
474 || ! CLASS_LIKELY_SPILLED_P (reg_preferred_class (i))))
480 /* Force loop below to initialize entire quantity array. */
483 /* Allocate each block's local registers, block by block. */
485 for (b = 0; b < n_basic_blocks; b++)
487 /* NEXT_QTY indicates which elements of the `qty_...'
488 vectors might need to be initialized because they were used
489 for the previous block; it is set to the entire array before
490 block 0. Initialize those, with explicit loop if there are few,
491 else with bzero and bcopy. Do not initialize vectors that are
492 explicit set by `alloc_qty'. */
496 for (i = 0; i < next_qty; i++)
498 qty_scratch_rtx[i] = 0;
499 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
500 qty_phys_num_copy_sugg[i] = 0;
501 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
502 qty_phys_num_sugg[i] = 0;
507 #define CLEAR(vector) \
508 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
510 CLEAR (qty_scratch_rtx);
511 CLEAR (qty_phys_copy_sugg);
512 CLEAR (qty_phys_num_copy_sugg);
513 CLEAR (qty_phys_sugg);
514 CLEAR (qty_phys_num_sugg);
526 /* Depth of loops we are in while in update_equiv_regs. */
527 static int loop_depth;
529 /* Used for communication between the following two functions: contains
530 a MEM that we wish to ensure remains unchanged. */
531 static rtx equiv_mem;
533 /* Set nonzero if EQUIV_MEM is modified. */
534 static int equiv_mem_modified;
536 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
537 Called via note_stores. */
540 validate_equiv_mem_from_store (dest, set)
544 if ((GET_CODE (dest) == REG
545 && reg_overlap_mentioned_p (dest, equiv_mem))
546 || (GET_CODE (dest) == MEM
547 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
548 equiv_mem_modified = 1;
551 /* Verify that no store between START and the death of REG invalidates
552 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
553 by storing into an overlapping memory location, or with a non-const
556 Return 1 if MEMREF remains valid. */
559 validate_equiv_mem (start, reg, memref)
568 equiv_mem_modified = 0;
570 /* If the memory reference has side effects or is volatile, it isn't a
571 valid equivalence. */
572 if (side_effects_p (memref))
575 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
577 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
580 if (find_reg_note (insn, REG_DEAD, reg))
583 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
584 && ! CONST_CALL_P (insn))
587 note_stores (PATTERN (insn), validate_equiv_mem_from_store);
589 /* If a register mentioned in MEMREF is modified via an
590 auto-increment, we lose the equivalence. Do the same if one
591 dies; although we could extend the life, it doesn't seem worth
594 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
595 if ((REG_NOTE_KIND (note) == REG_INC
596 || REG_NOTE_KIND (note) == REG_DEAD)
597 && GET_CODE (XEXP (note, 0)) == REG
598 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
605 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
608 contains_replace_regs (x, reg_equiv_replace)
610 char *reg_equiv_replace;
614 enum rtx_code code = GET_CODE (x);
630 return reg_equiv_replace[REGNO (x)];
633 fmt = GET_RTX_FORMAT (code);
634 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
638 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
642 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
643 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
651 /* TRUE if X references a memory location that would be affected by a store
655 memref_referenced_p (memref, x)
661 enum rtx_code code = GET_CODE (x);
677 return (reg_equiv_replacement[REGNO (x)]
678 && memref_referenced_p (memref,
679 reg_equiv_replacement[REGNO (x)]));
682 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
687 /* If we are setting a MEM, it doesn't count (its address does), but any
688 other SET_DEST that has a MEM in it is referencing the MEM. */
689 if (GET_CODE (SET_DEST (x)) == MEM)
691 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
694 else if (memref_referenced_p (memref, SET_DEST (x)))
697 return memref_referenced_p (memref, SET_SRC (x));
700 fmt = GET_RTX_FORMAT (code);
701 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
705 if (memref_referenced_p (memref, XEXP (x, i)))
709 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
710 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
718 /* TRUE if some insn in the range (START, END] references a memory location
719 that would be affected by a store to MEMREF. */
722 memref_used_between_p (memref, start, end)
729 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
730 insn = NEXT_INSN (insn))
731 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
732 && memref_referenced_p (memref, PATTERN (insn)))
738 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
741 Search forward to see if SRC dies before either it or DEST is modified,
742 but don't scan past the end of a basic block. If so, we can replace SRC
743 with DEST and let SRC die in INSN.
745 This will reduce the number of registers live in that range and may enable
746 DEST to be tied to SRC, thus often saving one register in addition to a
747 register-register copy. */
750 optimize_reg_copy_1 (insn, dest, src)
758 int sregno = REGNO (src);
759 int dregno = REGNO (dest);
762 #ifdef SMALL_REGISTER_CLASSES
763 /* We don't want to mess with hard regs if register classes are small. */
764 || (SMALL_REGISTER_CLASSES
765 && (sregno < FIRST_PSEUDO_REGISTER
766 || dregno < FIRST_PSEUDO_REGISTER))
768 /* We don't see all updates to SP if they are in an auto-inc memory
769 reference, so we must disallow this optimization on them. */
770 || sregno == STACK_POINTER_REGNUM || dregno == STACK_POINTER_REGNUM)
773 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
775 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
776 || (GET_CODE (p) == NOTE
777 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
778 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
781 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
784 if (reg_set_p (src, p) || reg_set_p (dest, p)
785 /* Don't change a USE of a register. */
786 || (GET_CODE (PATTERN (p)) == USE
787 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0))))
790 /* See if all of SRC dies in P. This test is slightly more
791 conservative than it needs to be. */
792 if ((note = find_regno_note (p, REG_DEAD, sregno)) != 0
793 && GET_MODE (XEXP (note, 0)) == GET_MODE (src))
801 /* We can do the optimization. Scan forward from INSN again,
802 replacing regs as we go. Set FAILED if a replacement can't
803 be done. In that case, we can't move the death note for SRC.
804 This should be rare. */
806 /* Set to stop at next insn. */
807 for (q = next_real_insn (insn);
808 q != next_real_insn (p);
809 q = next_real_insn (q))
811 if (reg_overlap_mentioned_p (src, PATTERN (q)))
813 /* If SRC is a hard register, we might miss some
814 overlapping registers with validate_replace_rtx,
815 so we would have to undo it. We can't if DEST is
816 present in the insn, so fail in that combination
818 if (sregno < FIRST_PSEUDO_REGISTER
819 && reg_mentioned_p (dest, PATTERN (q)))
822 /* Replace all uses and make sure that the register
823 isn't still present. */
824 else if (validate_replace_rtx (src, dest, q)
825 && (sregno >= FIRST_PSEUDO_REGISTER
826 || ! reg_overlap_mentioned_p (src,
829 /* We assume that a register is used exactly once per
830 insn in the updates below. If this is not correct,
831 no great harm is done. */
832 if (sregno >= FIRST_PSEUDO_REGISTER)
833 REG_N_REFS (sregno) -= loop_depth;
834 if (dregno >= FIRST_PSEUDO_REGISTER)
835 REG_N_REFS (dregno) += loop_depth;
839 validate_replace_rtx (dest, src, q);
844 /* Count the insns and CALL_INSNs passed. If we passed the
845 death note of DEST, show increased live length. */
850 /* If the insn in which SRC dies is a CALL_INSN, don't count it
851 as a call that has been crossed. Otherwise, count it. */
852 if (q != p && GET_CODE (q) == CALL_INSN)
859 /* If DEST dies here, remove the death note and save it for
860 later. Make sure ALL of DEST dies here; again, this is
861 overly conservative. */
863 && (dest_death = find_regno_note (q, REG_DEAD, dregno)) != 0
864 && GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest))
865 remove_note (q, dest_death);
870 if (sregno >= FIRST_PSEUDO_REGISTER)
872 if (REG_LIVE_LENGTH (sregno) >= 0)
874 REG_LIVE_LENGTH (sregno) -= length;
875 /* reg_live_length is only an approximation after
876 combine if sched is not run, so make sure that we
877 still have a reasonable value. */
878 if (REG_LIVE_LENGTH (sregno) < 2)
879 REG_LIVE_LENGTH (sregno) = 2;
882 REG_N_CALLS_CROSSED (sregno) -= n_calls;
885 if (dregno >= FIRST_PSEUDO_REGISTER)
887 if (REG_LIVE_LENGTH (dregno) >= 0)
888 REG_LIVE_LENGTH (dregno) += d_length;
890 REG_N_CALLS_CROSSED (dregno) += d_n_calls;
893 /* Move death note of SRC from P to INSN. */
894 remove_note (p, note);
895 XEXP (note, 1) = REG_NOTES (insn);
896 REG_NOTES (insn) = note;
899 /* Put death note of DEST on P if we saw it die. */
902 XEXP (dest_death, 1) = REG_NOTES (p);
903 REG_NOTES (p) = dest_death;
909 /* If SRC is a hard register which is set or killed in some other
910 way, we can't do this optimization. */
911 else if (sregno < FIRST_PSEUDO_REGISTER
912 && dead_or_set_p (p, src))
917 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
918 a sequence of insns that modify DEST followed by an insn that sets
919 SRC to DEST in which DEST dies, with no prior modification of DEST.
920 (There is no need to check if the insns in between actually modify
921 DEST. We should not have cases where DEST is not modified, but
922 the optimization is safe if no such modification is detected.)
923 In that case, we can replace all uses of DEST, starting with INSN and
924 ending with the set of SRC to DEST, with SRC. We do not do this
925 optimization if a CALL_INSN is crossed unless SRC already crosses a
926 call or if DEST dies before the copy back to SRC.
928 It is assumed that DEST and SRC are pseudos; it is too complicated to do
929 this for hard registers since the substitutions we may make might fail. */
932 optimize_reg_copy_2 (insn, dest, src)
939 int sregno = REGNO (src);
940 int dregno = REGNO (dest);
942 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p))
944 if (GET_CODE (p) == CODE_LABEL || GET_CODE (p) == JUMP_INSN
945 || (GET_CODE (p) == NOTE
946 && (NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_BEG
947 || NOTE_LINE_NUMBER (p) == NOTE_INSN_LOOP_END)))
950 if (GET_RTX_CLASS (GET_CODE (p)) != 'i')
953 set = single_set (p);
954 if (set && SET_SRC (set) == dest && SET_DEST (set) == src
955 && find_reg_note (p, REG_DEAD, dest))
957 /* We can do the optimization. Scan forward from INSN again,
958 replacing regs as we go. */
960 /* Set to stop at next insn. */
961 for (q = insn; q != NEXT_INSN (p); q = NEXT_INSN (q))
962 if (GET_RTX_CLASS (GET_CODE (q)) == 'i')
964 if (reg_mentioned_p (dest, PATTERN (q)))
966 PATTERN (q) = replace_rtx (PATTERN (q), dest, src);
968 /* We assume that a register is used exactly once per
969 insn in the updates below. If this is not correct,
970 no great harm is done. */
971 REG_N_REFS (dregno) -= loop_depth;
972 REG_N_REFS (sregno) += loop_depth;
976 if (GET_CODE (q) == CALL_INSN)
978 REG_N_CALLS_CROSSED (dregno)--;
979 REG_N_CALLS_CROSSED (sregno)++;
983 remove_note (p, find_reg_note (p, REG_DEAD, dest));
984 REG_N_DEATHS (dregno)--;
985 remove_note (insn, find_reg_note (insn, REG_DEAD, src));
986 REG_N_DEATHS (sregno)--;
990 if (reg_set_p (src, p)
991 || find_reg_note (p, REG_DEAD, dest)
992 || (GET_CODE (p) == CALL_INSN && REG_N_CALLS_CROSSED (sregno) == 0))
997 /* Find registers that are equivalent to a single value throughout the
998 compilation (either because they can be referenced in memory or are set once
999 from a single constant). Lower their priority for a register.
1001 If such a register is only referenced once, try substituting its value
1002 into the using insn. If it succeeds, we can eliminate the register
1006 update_equiv_regs ()
1008 rtx *reg_equiv_init_insn = (rtx *) alloca (max_regno * sizeof (rtx *));
1009 /* Set when an attempt should be made to replace a register with the
1010 associated reg_equiv_replacement entry at the end of this function. */
1011 char *reg_equiv_replace
1012 = (char *) alloca (max_regno * sizeof *reg_equiv_replace);
1016 reg_equiv_replacement = (rtx *) alloca (max_regno * sizeof (rtx *));
1018 bzero ((char *) reg_equiv_init_insn, max_regno * sizeof (rtx *));
1019 bzero ((char *) reg_equiv_replacement, max_regno * sizeof (rtx *));
1020 bzero ((char *) reg_equiv_replace, max_regno * sizeof *reg_equiv_replace);
1022 init_alias_analysis ();
1026 /* Scan the insns and find which registers have equivalences. Do this
1027 in a separate scan of the insns because (due to -fcse-follow-jumps)
1028 a register can be set below its use. */
1029 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1032 rtx set = single_set (insn);
1036 if (GET_CODE (insn) == NOTE)
1038 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1040 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
1044 /* If this insn contains more (or less) than a single SET, ignore it. */
1048 dest = SET_DEST (set);
1049 src = SET_SRC (set);
1051 /* If this sets a MEM to the contents of a REG that is only used
1052 in a single basic block, see if the register is always equivalent
1053 to that memory location and if moving the store from INSN to the
1054 insn that set REG is safe. If so, put a REG_EQUIV note on the
1057 Don't add a REG_EQUIV note if the insn already has one. The existing
1058 REG_EQUIV is likely more useful than the one we are adding.
1060 If one of the regs in the address is marked as reg_equiv_replace,
1061 then we can't add this REG_EQUIV note. The reg_equiv_replace
1062 optimization may move the set of this register immediately before
1063 insn, which puts it after reg_equiv_init_insn[regno], and hence
1064 the mention in the REG_EQUIV note would be to an uninitialized
1067 if (GET_CODE (dest) == MEM && GET_CODE (SET_SRC (set)) == REG
1068 && (regno = REGNO (SET_SRC (set))) >= FIRST_PSEUDO_REGISTER
1069 && REG_BASIC_BLOCK (regno) >= 0
1070 && reg_equiv_init_insn[regno] != 0
1071 && ! find_reg_note (insn, REG_EQUIV, NULL_RTX)
1072 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace)
1073 && validate_equiv_mem (reg_equiv_init_insn[regno], SET_SRC (set),
1075 && ! memref_used_between_p (SET_DEST (set),
1076 reg_equiv_init_insn[regno], insn))
1077 REG_NOTES (reg_equiv_init_insn[regno])
1078 = gen_rtx (EXPR_LIST, REG_EQUIV, dest,
1079 REG_NOTES (reg_equiv_init_insn[regno]));
1081 /* If this is a register-register copy where SRC is not dead, see if we
1083 if (flag_expensive_optimizations && GET_CODE (dest) == REG
1084 && GET_CODE (SET_SRC (set)) == REG
1085 && ! find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1086 optimize_reg_copy_1 (insn, dest, SET_SRC (set));
1088 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
1089 else if (flag_expensive_optimizations && GET_CODE (dest) == REG
1090 && REGNO (dest) >= FIRST_PSEUDO_REGISTER
1091 && GET_CODE (SET_SRC (set)) == REG
1092 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER
1093 && find_reg_note (insn, REG_DEAD, SET_SRC (set)))
1094 optimize_reg_copy_2 (insn, dest, SET_SRC (set));
1096 /* Otherwise, we only handle the case of a pseudo register being set
1097 once and only if neither the source nor the destination are
1098 in a register class that's likely to be spilled. */
1099 if (GET_CODE (dest) != REG
1100 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
1101 || REG_N_SETS (regno) != 1
1102 || CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (dest)))
1103 || (GET_CODE (src) == REG
1104 && REGNO (src) >= FIRST_PSEUDO_REGISTER
1105 && CLASS_LIKELY_SPILLED_P (reg_preferred_class (REGNO (src)))))
1108 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
1110 #ifdef DONT_RECORD_EQUIVALENCE
1111 /* Allow the target to reject promotions of some REG_EQUAL notes to
1114 In some cases this can improve register allocation if the existence
1115 of the REG_EQUIV note is likely to increase the lifetime of a register
1116 that is likely to be spilled.
1118 It may also be necessary if the target can't handle certain constant
1119 expressions appearing randomly in insns, but for whatever reason
1120 those expressions must be considered legitimate constant expressions
1121 to prevent them from being forced into memory. */
1122 if (note && DONT_RECORD_EQUIVALENCE (note))
1126 /* Record this insn as initializing this register. */
1127 reg_equiv_init_insn[regno] = insn;
1129 /* If this register is known to be equal to a constant, record that
1130 it is always equivalent to the constant. */
1131 if (note && CONSTANT_P (XEXP (note, 0)))
1132 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
1134 /* If this insn introduces a "constant" register, decrease the priority
1135 of that register. Record this insn if the register is only used once
1136 more and the equivalence value is the same as our source.
1138 The latter condition is checked for two reasons: First, it is an
1139 indication that it may be more efficient to actually emit the insn
1140 as written (if no registers are available, reload will substitute
1141 the equivalence). Secondly, it avoids problems with any registers
1142 dying in this insn whose death notes would be missed.
1144 If we don't have a REG_EQUIV note, see if this insn is loading
1145 a register used only in one basic block from a MEM. If so, and the
1146 MEM remains unchanged for the life of the register, add a REG_EQUIV
1149 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
1151 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
1152 && GET_CODE (SET_SRC (set)) == MEM
1153 && validate_equiv_mem (insn, dest, SET_SRC (set)))
1154 REG_NOTES (insn) = note = gen_rtx (EXPR_LIST, REG_EQUIV, SET_SRC (set),
1159 int regno = REGNO (dest);
1161 reg_equiv_replacement[regno] = XEXP (note, 0);
1163 /* Don't mess with things live during setjmp. */
1164 if (REG_LIVE_LENGTH (regno) >= 0)
1166 /* Note that the statement below does not affect the priority
1168 REG_LIVE_LENGTH (regno) *= 2;
1171 /* If the register is referenced exactly twice, meaning it is
1172 set once and used once, indicate that the reference may be
1173 replaced by the equivalence we computed above. If the
1174 register is only used in one basic block, this can't succeed
1175 or combine would have done it.
1177 It would be nice to use "loop_depth * 2" in the compare
1178 below. Unfortunately, LOOP_DEPTH need not be constant within
1179 a basic block so this would be too complicated.
1181 This case normally occurs when a parameter is read from
1182 memory and then used exactly once, not in a loop. */
1184 if (REG_N_REFS (regno) == 2
1185 && REG_BASIC_BLOCK (regno) < 0
1186 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
1187 reg_equiv_replace[regno] = 1;
1192 /* Now scan all regs killed in an insn to see if any of them are
1193 registers only used that once. If so, see if we can replace the
1194 reference with the equivalent from. If we can, delete the
1195 initializing reference and this register will go away. If we
1196 can't replace the reference, and the instruction is not in a
1197 loop, then move the register initialization just before the use,
1198 so that they are in the same basic block. */
1201 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1205 /* Keep track of which basic block we are in. */
1206 if (block + 1 < n_basic_blocks
1207 && basic_block_head[block + 1] == insn)
1210 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
1212 if (GET_CODE (insn) == NOTE)
1214 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
1216 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
1227 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1229 if (REG_NOTE_KIND (link) == REG_DEAD
1230 /* Make sure this insn still refers to the register. */
1231 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1233 int regno = REGNO (XEXP (link, 0));
1236 if (! reg_equiv_replace[regno])
1239 equiv_insn = reg_equiv_init_insn[regno];
1241 if (validate_replace_rtx (regno_reg_rtx[regno],
1242 reg_equiv_replacement[regno], insn))
1244 remove_death (regno, insn);
1245 REG_N_REFS (regno) = 0;
1246 PUT_CODE (equiv_insn, NOTE);
1247 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1248 NOTE_SOURCE_FILE (equiv_insn) = 0;
1250 /* If we aren't in a loop, and there are no calls in
1251 INSN or in the initialization of the register, then
1252 move the initialization of the register to just
1253 before INSN. Update the flow information. */
1255 && GET_CODE (equiv_insn) == INSN
1256 && GET_CODE (insn) == INSN
1257 && REG_BASIC_BLOCK (regno) < 0)
1261 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
1262 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
1264 PUT_CODE (equiv_insn, NOTE);
1265 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1266 NOTE_SOURCE_FILE (equiv_insn) = 0;
1267 REG_NOTES (equiv_insn) = 0;
1270 REG_BASIC_BLOCK (regno) = 0;
1272 REG_BASIC_BLOCK (regno) = block;
1273 REG_N_CALLS_CROSSED (regno) = 0;
1274 REG_LIVE_LENGTH (regno) = 2;
1276 if (block >= 0 && insn == basic_block_head[block])
1277 basic_block_head[block] = PREV_INSN (insn);
1279 for (l = 0; l < n_basic_blocks; l++)
1280 CLEAR_REGNO_REG_SET (basic_block_live_at_start[l], regno);
1287 /* Allocate hard regs to the pseudo regs used only within block number B.
1288 Only the pseudos that die but once can be handled. */
1297 int insn_number = 0;
1299 int max_uid = get_max_uid ();
1301 int no_conflict_combined_regno = -1;
1302 /* Counter to prevent allocating more SCRATCHes than can be stored
1304 int scratches_allocated = scratch_index;
1306 /* Count the instructions in the basic block. */
1308 insn = basic_block_end[b];
1311 if (GET_CODE (insn) != NOTE)
1312 if (++insn_count > max_uid)
1314 if (insn == basic_block_head[b])
1316 insn = PREV_INSN (insn);
1319 /* +2 to leave room for a post_mark_life at the last insn and for
1320 the birth of a CLOBBER in the first insn. */
1321 regs_live_at = (HARD_REG_SET *) alloca ((2 * insn_count + 2)
1322 * sizeof (HARD_REG_SET));
1323 bzero ((char *) regs_live_at, (2 * insn_count + 2) * sizeof (HARD_REG_SET));
1325 /* Initialize table of hardware registers currently live. */
1327 REG_SET_TO_HARD_REG_SET (regs_live, basic_block_live_at_start[b]);
1329 /* This loop scans the instructions of the basic block
1330 and assigns quantities to registers.
1331 It computes which registers to tie. */
1333 insn = basic_block_head[b];
1336 register rtx body = PATTERN (insn);
1338 if (GET_CODE (insn) != NOTE)
1341 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1343 register rtx link, set;
1344 register int win = 0;
1345 register rtx r0, r1;
1346 int combined_regno = -1;
1348 int insn_code_number = recog_memoized (insn);
1350 this_insn_number = insn_number;
1353 if (insn_code_number >= 0)
1354 insn_extract (insn);
1355 which_alternative = -1;
1357 /* Is this insn suitable for tying two registers?
1358 If so, try doing that.
1359 Suitable insns are those with at least two operands and where
1360 operand 0 is an output that is a register that is not
1363 We can tie operand 0 with some operand that dies in this insn.
1364 First look for operands that are required to be in the same
1365 register as operand 0. If we find such, only try tying that
1366 operand or one that can be put into that operand if the
1367 operation is commutative. If we don't find an operand
1368 that is required to be in the same register as operand 0,
1369 we can tie with any operand.
1371 Subregs in place of regs are also ok.
1373 If tying is done, WIN is set nonzero. */
1375 if (insn_code_number >= 0
1376 #ifdef REGISTER_CONSTRAINTS
1377 && insn_n_operands[insn_code_number] > 1
1378 && insn_operand_constraint[insn_code_number][0][0] == '='
1379 && insn_operand_constraint[insn_code_number][0][1] != '&'
1381 && GET_CODE (PATTERN (insn)) == SET
1382 && rtx_equal_p (SET_DEST (PATTERN (insn)), recog_operand[0])
1386 #ifdef REGISTER_CONSTRAINTS
1387 /* If non-negative, is an operand that must match operand 0. */
1388 int must_match_0 = -1;
1389 /* Counts number of alternatives that require a match with
1391 int n_matching_alts = 0;
1393 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1395 char *p = insn_operand_constraint[insn_code_number][i];
1396 int this_match = (requires_inout (p));
1398 n_matching_alts += this_match;
1399 if (this_match == insn_n_alternatives[insn_code_number])
1404 r0 = recog_operand[0];
1405 for (i = 1; i < insn_n_operands[insn_code_number]; i++)
1407 #ifdef REGISTER_CONSTRAINTS
1408 /* Skip this operand if we found an operand that
1409 must match operand 0 and this operand isn't it
1410 and can't be made to be it by commutativity. */
1412 if (must_match_0 >= 0 && i != must_match_0
1413 && ! (i == must_match_0 + 1
1414 && insn_operand_constraint[insn_code_number][i-1][0] == '%')
1415 && ! (i == must_match_0 - 1
1416 && insn_operand_constraint[insn_code_number][i][0] == '%'))
1419 /* Likewise if each alternative has some operand that
1420 must match operand zero. In that case, skip any
1421 operand that doesn't list operand 0 since we know that
1422 the operand always conflicts with operand 0. We
1423 ignore commutatity in this case to keep things simple. */
1424 if (n_matching_alts == insn_n_alternatives[insn_code_number]
1425 && (0 == requires_inout
1426 (insn_operand_constraint[insn_code_number][i])))
1430 r1 = recog_operand[i];
1432 /* If the operand is an address, find a register in it.
1433 There may be more than one register, but we only try one
1436 #ifdef REGISTER_CONSTRAINTS
1437 insn_operand_constraint[insn_code_number][i][0] == 'p'
1439 insn_operand_address_p[insn_code_number][i]
1442 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1445 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1447 /* We have two priorities for hard register preferences.
1448 If we have a move insn or an insn whose first input
1449 can only be in the same register as the output, give
1450 priority to an equivalence found from that insn. */
1452 = ((SET_DEST (body) == r0 && SET_SRC (body) == r1)
1453 #ifdef REGISTER_CONSTRAINTS
1454 || (r1 == recog_operand[i] && must_match_0 >= 0)
1458 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1459 win = combine_regs (r1, r0, may_save_copy,
1460 insn_number, insn, 0);
1467 /* Recognize an insn sequence with an ultimate result
1468 which can safely overlap one of the inputs.
1469 The sequence begins with a CLOBBER of its result,
1470 and ends with an insn that copies the result to itself
1471 and has a REG_EQUAL note for an equivalent formula.
1472 That note indicates what the inputs are.
1473 The result and the input can overlap if each insn in
1474 the sequence either doesn't mention the input
1475 or has a REG_NO_CONFLICT note to inhibit the conflict.
1477 We do the combining test at the CLOBBER so that the
1478 destination register won't have had a quantity number
1479 assigned, since that would prevent combining. */
1481 if (GET_CODE (PATTERN (insn)) == CLOBBER
1482 && (r0 = XEXP (PATTERN (insn), 0),
1483 GET_CODE (r0) == REG)
1484 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1485 && XEXP (link, 0) != 0
1486 && GET_CODE (XEXP (link, 0)) == INSN
1487 && (set = single_set (XEXP (link, 0))) != 0
1488 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1489 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1492 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1493 /* Check that we have such a sequence. */
1494 && no_conflict_p (insn, r0, r1))
1495 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1496 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1497 && (r1 = XEXP (XEXP (note, 0), 0),
1498 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1499 && no_conflict_p (insn, r0, r1))
1500 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1502 /* Here we care if the operation to be computed is
1504 else if ((GET_CODE (XEXP (note, 0)) == EQ
1505 || GET_CODE (XEXP (note, 0)) == NE
1506 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1507 && (r1 = XEXP (XEXP (note, 0), 1),
1508 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1509 && no_conflict_p (insn, r0, r1))
1510 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1512 /* If we did combine something, show the register number
1513 in question so that we know to ignore its death. */
1515 no_conflict_combined_regno = REGNO (r1);
1518 /* If registers were just tied, set COMBINED_REGNO
1519 to the number of the register used in this insn
1520 that was tied to the register set in this insn.
1521 This register's qty should not be "killed". */
1525 while (GET_CODE (r1) == SUBREG)
1526 r1 = SUBREG_REG (r1);
1527 combined_regno = REGNO (r1);
1530 /* Mark the death of everything that dies in this instruction,
1531 except for anything that was just combined. */
1533 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1534 if (REG_NOTE_KIND (link) == REG_DEAD
1535 && GET_CODE (XEXP (link, 0)) == REG
1536 && combined_regno != REGNO (XEXP (link, 0))
1537 && (no_conflict_combined_regno != REGNO (XEXP (link, 0))
1538 || ! find_reg_note (insn, REG_NO_CONFLICT, XEXP (link, 0))))
1539 wipe_dead_reg (XEXP (link, 0), 0);
1541 /* Allocate qty numbers for all registers local to this block
1542 that are born (set) in this instruction.
1543 A pseudo that already has a qty is not changed. */
1545 note_stores (PATTERN (insn), reg_is_set);
1547 /* If anything is set in this insn and then unused, mark it as dying
1548 after this insn, so it will conflict with our outputs. This
1549 can't match with something that combined, and it doesn't matter
1550 if it did. Do this after the calls to reg_is_set since these
1551 die after, not during, the current insn. */
1553 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1554 if (REG_NOTE_KIND (link) == REG_UNUSED
1555 && GET_CODE (XEXP (link, 0)) == REG)
1556 wipe_dead_reg (XEXP (link, 0), 1);
1558 /* Allocate quantities for any SCRATCH operands of this insn. */
1560 if (insn_code_number >= 0)
1561 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1562 if (GET_CODE (recog_operand[i]) == SCRATCH
1563 && scratches_allocated++ < scratch_list_length)
1564 alloc_qty_for_scratch (recog_operand[i], i, insn,
1565 insn_code_number, insn_number);
1567 /* If this is an insn that has a REG_RETVAL note pointing at a
1568 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1569 block, so clear any register number that combined within it. */
1570 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1571 && GET_CODE (XEXP (note, 0)) == INSN
1572 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1573 no_conflict_combined_regno = -1;
1576 /* Set the registers live after INSN_NUMBER. Note that we never
1577 record the registers live before the block's first insn, since no
1578 pseudos we care about are live before that insn. */
1580 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1581 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1583 if (insn == basic_block_end[b])
1586 insn = NEXT_INSN (insn);
1589 /* Now every register that is local to this basic block
1590 should have been given a quantity, or else -1 meaning ignore it.
1591 Every quantity should have a known birth and death.
1593 Order the qtys so we assign them registers in order of the
1594 number of suggested registers they need so we allocate those with
1595 the most restrictive needs first. */
1597 qty_order = (int *) alloca (next_qty * sizeof (int));
1598 for (i = 0; i < next_qty; i++)
1601 #define EXCHANGE(I1, I2) \
1602 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1607 /* Make qty_order[2] be the one to allocate last. */
1608 if (qty_sugg_compare (0, 1) > 0)
1610 if (qty_sugg_compare (1, 2) > 0)
1613 /* ... Fall through ... */
1615 /* Put the best one to allocate in qty_order[0]. */
1616 if (qty_sugg_compare (0, 1) > 0)
1619 /* ... Fall through ... */
1623 /* Nothing to do here. */
1627 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1630 /* Try to put each quantity in a suggested physical register, if it has one.
1631 This may cause registers to be allocated that otherwise wouldn't be, but
1632 this seems acceptable in local allocation (unlike global allocation). */
1633 for (i = 0; i < next_qty; i++)
1636 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1637 qty_phys_reg[q] = find_free_reg (qty_min_class[q], qty_mode[q], q,
1638 0, 1, qty_birth[q], qty_death[q]);
1640 qty_phys_reg[q] = -1;
1643 /* Order the qtys so we assign them registers in order of
1644 decreasing length of life. Normally call qsort, but if we
1645 have only a very small number of quantities, sort them ourselves. */
1647 for (i = 0; i < next_qty; i++)
1650 #define EXCHANGE(I1, I2) \
1651 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1656 /* Make qty_order[2] be the one to allocate last. */
1657 if (qty_compare (0, 1) > 0)
1659 if (qty_compare (1, 2) > 0)
1662 /* ... Fall through ... */
1664 /* Put the best one to allocate in qty_order[0]. */
1665 if (qty_compare (0, 1) > 0)
1668 /* ... Fall through ... */
1672 /* Nothing to do here. */
1676 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1679 /* Now for each qty that is not a hardware register,
1680 look for a hardware register to put it in.
1681 First try the register class that is cheapest for this qty,
1682 if there is more than one class. */
1684 for (i = 0; i < next_qty; i++)
1687 if (qty_phys_reg[q] < 0)
1689 if (N_REG_CLASSES > 1)
1691 qty_phys_reg[q] = find_free_reg (qty_min_class[q],
1692 qty_mode[q], q, 0, 0,
1693 qty_birth[q], qty_death[q]);
1694 if (qty_phys_reg[q] >= 0)
1698 if (qty_alternate_class[q] != NO_REGS)
1699 qty_phys_reg[q] = find_free_reg (qty_alternate_class[q],
1700 qty_mode[q], q, 0, 0,
1701 qty_birth[q], qty_death[q]);
1705 /* Now propagate the register assignments
1706 to the pseudo regs belonging to the qtys. */
1708 for (q = 0; q < next_qty; q++)
1709 if (qty_phys_reg[q] >= 0)
1711 for (i = qty_first_reg[q]; i >= 0; i = reg_next_in_qty[i])
1712 reg_renumber[i] = qty_phys_reg[q] + reg_offset[i];
1713 if (qty_scratch_rtx[q])
1715 if (GET_CODE (qty_scratch_rtx[q]) == REG)
1717 PUT_CODE (qty_scratch_rtx[q], REG);
1718 REGNO (qty_scratch_rtx[q]) = qty_phys_reg[q];
1720 scratch_block[scratch_index] = b;
1721 scratch_list[scratch_index++] = qty_scratch_rtx[q];
1723 /* Must clear the USED field, because it will have been set by
1724 copy_rtx_if_shared, but the leaf_register code expects that
1725 it is zero in all REG rtx. copy_rtx_if_shared does not set the
1726 used bit for REGs, but does for SCRATCHes. */
1727 qty_scratch_rtx[q]->used = 0;
1732 /* Compare two quantities' priority for getting real registers.
1733 We give shorter-lived quantities higher priority.
1734 Quantities with more references are also preferred, as are quantities that
1735 require multiple registers. This is the identical prioritization as
1736 done by global-alloc.
1738 We used to give preference to registers with *longer* lives, but using
1739 the same algorithm in both local- and global-alloc can speed up execution
1740 of some programs by as much as a factor of three! */
1742 /* Note that the quotient will never be bigger than
1743 the value of floor_log2 times the maximum number of
1744 times a register can occur in one insn (surely less than 100).
1745 Multiplying this by 10000 can't overflow.
1746 QTY_CMP_PRI is also used by qty_sugg_compare. */
1748 #define QTY_CMP_PRI(q) \
1749 ((int) (((double) (floor_log2 (qty_n_refs[q]) * qty_n_refs[q] * qty_size[q]) \
1750 / (qty_death[q] - qty_birth[q])) * 10000))
1753 qty_compare (q1, q2)
1756 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1760 qty_compare_1 (q1p, q2p)
1761 const GENERIC_PTR q1p;
1762 const GENERIC_PTR q2p;
1764 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1765 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1770 /* If qtys are equally good, sort by qty number,
1771 so that the results of qsort leave nothing to chance. */
1775 /* Compare two quantities' priority for getting real registers. This version
1776 is called for quantities that have suggested hard registers. First priority
1777 goes to quantities that have copy preferences, then to those that have
1778 normal preferences. Within those groups, quantities with the lower
1779 number of preferences have the highest priority. Of those, we use the same
1780 algorithm as above. */
1782 #define QTY_CMP_SUGG(q) \
1783 (qty_phys_num_copy_sugg[q] \
1784 ? qty_phys_num_copy_sugg[q] \
1785 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1788 qty_sugg_compare (q1, q2)
1791 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1796 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1800 qty_sugg_compare_1 (q1p, q2p)
1801 const GENERIC_PTR q1p;
1802 const GENERIC_PTR q2p;
1804 register int q1 = *(int *)q1p, q2 = *(int *)q2p;
1805 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1810 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1814 /* If qtys are equally good, sort by qty number,
1815 so that the results of qsort leave nothing to chance. */
1822 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1823 Returns 1 if have done so, or 0 if cannot.
1825 Combining registers means marking them as having the same quantity
1826 and adjusting the offsets within the quantity if either of
1829 We don't actually combine a hard reg with a pseudo; instead
1830 we just record the hard reg as the suggestion for the pseudo's quantity.
1831 If we really combined them, we could lose if the pseudo lives
1832 across an insn that clobbers the hard reg (eg, movstr).
1834 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1835 there is no REG_DEAD note on INSN. This occurs during the processing
1836 of REG_NO_CONFLICT blocks.
1838 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1839 SETREG or if the input and output must share a register.
1840 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1842 There are elaborate checks for the validity of combining. */
1846 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1847 rtx usedreg, setreg;
1853 register int ureg, sreg;
1854 register int offset = 0;
1858 /* Determine the numbers and sizes of registers being used. If a subreg
1859 is present that does not change the entire register, don't consider
1860 this a copy insn. */
1862 while (GET_CODE (usedreg) == SUBREG)
1864 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1866 offset += SUBREG_WORD (usedreg);
1867 usedreg = SUBREG_REG (usedreg);
1869 if (GET_CODE (usedreg) != REG)
1871 ureg = REGNO (usedreg);
1872 usize = REG_SIZE (usedreg);
1874 while (GET_CODE (setreg) == SUBREG)
1876 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1878 offset -= SUBREG_WORD (setreg);
1879 setreg = SUBREG_REG (setreg);
1881 if (GET_CODE (setreg) != REG)
1883 sreg = REGNO (setreg);
1884 ssize = REG_SIZE (setreg);
1886 /* If UREG is a pseudo-register that hasn't already been assigned a
1887 quantity number, it means that it is not local to this block or dies
1888 more than once. In either event, we can't do anything with it. */
1889 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1890 /* Do not combine registers unless one fits within the other. */
1891 || (offset > 0 && usize + offset > ssize)
1892 || (offset < 0 && usize + offset < ssize)
1893 /* Do not combine with a smaller already-assigned object
1894 if that smaller object is already combined with something bigger. */
1895 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1896 && usize < qty_size[reg_qty[ureg]])
1897 /* Can't combine if SREG is not a register we can allocate. */
1898 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1899 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1900 These have already been taken care of. This probably wouldn't
1901 combine anyway, but don't take any chances. */
1902 || (ureg >= FIRST_PSEUDO_REGISTER
1903 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1904 /* Don't tie something to itself. In most cases it would make no
1905 difference, but it would screw up if the reg being tied to itself
1906 also dies in this insn. */
1908 /* Don't try to connect two different hardware registers. */
1909 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1910 /* Don't connect two different machine modes if they have different
1911 implications as to which registers may be used. */
1912 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1915 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1916 qty_phys_sugg for the pseudo instead of tying them.
1918 Return "failure" so that the lifespan of UREG is terminated here;
1919 that way the two lifespans will be disjoint and nothing will prevent
1920 the pseudo reg from being given this hard reg. */
1922 if (ureg < FIRST_PSEUDO_REGISTER)
1924 /* Allocate a quantity number so we have a place to put our
1926 if (reg_qty[sreg] == -2)
1927 reg_is_born (setreg, 2 * insn_number);
1929 if (reg_qty[sreg] >= 0)
1932 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1934 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1935 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1937 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1939 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1940 qty_phys_num_sugg[reg_qty[sreg]]++;
1946 /* Similarly for SREG a hard register and UREG a pseudo register. */
1948 if (sreg < FIRST_PSEUDO_REGISTER)
1951 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1953 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1954 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1956 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1958 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1959 qty_phys_num_sugg[reg_qty[ureg]]++;
1964 /* At this point we know that SREG and UREG are both pseudos.
1965 Do nothing if SREG already has a quantity or is a register that we
1967 if (reg_qty[sreg] >= -1
1968 /* If we are not going to let any regs live across calls,
1969 don't tie a call-crossing reg to a non-call-crossing reg. */
1970 || (current_function_has_nonlocal_label
1971 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1972 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1975 /* We don't already know about SREG, so tie it to UREG
1976 if this is the last use of UREG, provided the classes they want
1979 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1980 && reg_meets_class_p (sreg, qty_min_class[reg_qty[ureg]]))
1982 /* Add SREG to UREG's quantity. */
1983 sqty = reg_qty[ureg];
1984 reg_qty[sreg] = sqty;
1985 reg_offset[sreg] = reg_offset[ureg] + offset;
1986 reg_next_in_qty[sreg] = qty_first_reg[sqty];
1987 qty_first_reg[sqty] = sreg;
1989 /* If SREG's reg class is smaller, set qty_min_class[SQTY]. */
1990 update_qty_class (sqty, sreg);
1992 /* Update info about quantity SQTY. */
1993 qty_n_calls_crossed[sqty] += REG_N_CALLS_CROSSED (sreg);
1994 qty_n_refs[sqty] += REG_N_REFS (sreg);
1999 for (i = qty_first_reg[sqty]; i >= 0; i = reg_next_in_qty[i])
2000 reg_offset[i] -= offset;
2002 qty_size[sqty] = ssize;
2003 qty_mode[sqty] = GET_MODE (setreg);
2012 /* Return 1 if the preferred class of REG allows it to be tied
2013 to a quantity or register whose class is CLASS.
2014 True if REG's reg class either contains or is contained in CLASS. */
2017 reg_meets_class_p (reg, class)
2019 enum reg_class class;
2021 register enum reg_class rclass = reg_preferred_class (reg);
2022 return (reg_class_subset_p (rclass, class)
2023 || reg_class_subset_p (class, rclass));
2026 /* Return 1 if the two specified classes have registers in common.
2027 If CALL_SAVED, then consider only call-saved registers. */
2030 reg_classes_overlap_p (c1, c2, call_saved)
2031 register enum reg_class c1;
2032 register enum reg_class c2;
2038 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2039 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2041 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2042 if (TEST_HARD_REG_BIT (c, i)
2043 && (! call_saved || ! call_used_regs[i]))
2049 /* Update the class of QTY assuming that REG is being tied to it. */
2052 update_qty_class (qty, reg)
2056 enum reg_class rclass = reg_preferred_class (reg);
2057 if (reg_class_subset_p (rclass, qty_min_class[qty]))
2058 qty_min_class[qty] = rclass;
2060 rclass = reg_alternate_class (reg);
2061 if (reg_class_subset_p (rclass, qty_alternate_class[qty]))
2062 qty_alternate_class[qty] = rclass;
2064 if (REG_CHANGES_SIZE (reg))
2065 qty_changes_size[qty] = 1;
2068 /* Handle something which alters the value of an rtx REG.
2070 REG is whatever is set or clobbered. SETTER is the rtx that
2071 is modifying the register.
2073 If it is not really a register, we do nothing.
2074 The file-global variables `this_insn' and `this_insn_number'
2075 carry info from `block_alloc'. */
2078 reg_is_set (reg, setter)
2082 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2083 a hard register. These may actually not exist any more. */
2085 if (GET_CODE (reg) != SUBREG
2086 && GET_CODE (reg) != REG)
2089 /* Mark this register as being born. If it is used in a CLOBBER, mark
2090 it as being born halfway between the previous insn and this insn so that
2091 it conflicts with our inputs but not the outputs of the previous insn. */
2093 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
2096 /* Handle beginning of the life of register REG.
2097 BIRTH is the index at which this is happening. */
2100 reg_is_born (reg, birth)
2106 if (GET_CODE (reg) == SUBREG)
2107 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
2109 regno = REGNO (reg);
2111 if (regno < FIRST_PSEUDO_REGISTER)
2113 mark_life (regno, GET_MODE (reg), 1);
2115 /* If the register was to have been born earlier that the present
2116 insn, mark it as live where it is actually born. */
2117 if (birth < 2 * this_insn_number)
2118 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
2122 if (reg_qty[regno] == -2)
2123 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2125 /* If this register has a quantity number, show that it isn't dead. */
2126 if (reg_qty[regno] >= 0)
2127 qty_death[reg_qty[regno]] = -1;
2131 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2132 REG is an output that is dying (i.e., it is never used), otherwise it
2133 is an input (the normal case).
2134 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2137 wipe_dead_reg (reg, output_p)
2141 register int regno = REGNO (reg);
2143 /* If this insn has multiple results,
2144 and the dead reg is used in one of the results,
2145 extend its life to after this insn,
2146 so it won't get allocated together with any other result of this insn. */
2147 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2148 && !single_set (this_insn))
2151 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2153 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2154 if (GET_CODE (set) == SET
2155 && GET_CODE (SET_DEST (set)) != REG
2156 && !rtx_equal_p (reg, SET_DEST (set))
2157 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2162 /* If this register is used in an auto-increment address, then extend its
2163 life to after this insn, so that it won't get allocated together with
2164 the result of this insn. */
2165 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2168 if (regno < FIRST_PSEUDO_REGISTER)
2170 mark_life (regno, GET_MODE (reg), 0);
2172 /* If a hard register is dying as an output, mark it as in use at
2173 the beginning of this insn (the above statement would cause this
2176 post_mark_life (regno, GET_MODE (reg), 1,
2177 2 * this_insn_number, 2 * this_insn_number+ 1);
2180 else if (reg_qty[regno] >= 0)
2181 qty_death[reg_qty[regno]] = 2 * this_insn_number + output_p;
2184 /* Find a block of SIZE words of hard regs in reg_class CLASS
2185 that can hold something of machine-mode MODE
2186 (but actually we test only the first of the block for holding MODE)
2187 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2188 and return the number of the first of them.
2189 Return -1 if such a block cannot be found.
2190 If QTY crosses calls, insist on a register preserved by calls,
2191 unless ACCEPT_CALL_CLOBBERED is nonzero.
2193 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2194 register is available. If not, return -1. */
2197 find_free_reg (class, mode, qty, accept_call_clobbered, just_try_suggested,
2198 born_index, dead_index)
2199 enum reg_class class;
2200 enum machine_mode mode;
2202 int accept_call_clobbered;
2203 int just_try_suggested;
2204 int born_index, dead_index;
2206 register int i, ins;
2208 register /* Declare it register if it's a scalar. */
2210 HARD_REG_SET used, first_used;
2211 #ifdef ELIMINABLE_REGS
2212 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
2215 /* Validate our parameters. */
2216 if (born_index < 0 || born_index > dead_index)
2219 /* Don't let a pseudo live in a reg across a function call
2220 if we might get a nonlocal goto. */
2221 if (current_function_has_nonlocal_label
2222 && qty_n_calls_crossed[qty] > 0)
2225 if (accept_call_clobbered)
2226 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2227 else if (qty_n_calls_crossed[qty] == 0)
2228 COPY_HARD_REG_SET (used, fixed_reg_set);
2230 COPY_HARD_REG_SET (used, call_used_reg_set);
2232 if (accept_call_clobbered)
2233 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2235 for (ins = born_index; ins < dead_index; ins++)
2236 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2238 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2240 /* Don't use the frame pointer reg in local-alloc even if
2241 we may omit the frame pointer, because if we do that and then we
2242 need a frame pointer, reload won't know how to move the pseudo
2243 to another hard reg. It can move only regs made by global-alloc.
2245 This is true of any register that can be eliminated. */
2246 #ifdef ELIMINABLE_REGS
2247 for (i = 0; i < sizeof eliminables / sizeof eliminables[0]; i++)
2248 SET_HARD_REG_BIT (used, eliminables[i].from);
2249 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2250 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2251 that it might be eliminated into. */
2252 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2255 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2258 #ifdef CLASS_CANNOT_CHANGE_SIZE
2259 if (qty_changes_size[qty])
2260 IOR_HARD_REG_SET (used,
2261 reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE]);
2264 /* Normally, the registers that can be used for the first register in
2265 a multi-register quantity are the same as those that can be used for
2266 subsequent registers. However, if just trying suggested registers,
2267 restrict our consideration to them. If there are copy-suggested
2268 register, try them. Otherwise, try the arithmetic-suggested
2270 COPY_HARD_REG_SET (first_used, used);
2272 if (just_try_suggested)
2274 if (qty_phys_num_copy_sugg[qty] != 0)
2275 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qty]);
2277 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qty]);
2280 /* If all registers are excluded, we can't do anything. */
2281 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2283 /* If at least one would be suitable, test each hard reg. */
2285 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2287 #ifdef REG_ALLOC_ORDER
2288 int regno = reg_alloc_order[i];
2292 if (! TEST_HARD_REG_BIT (first_used, regno)
2293 && HARD_REGNO_MODE_OK (regno, mode))
2296 register int size1 = HARD_REGNO_NREGS (regno, mode);
2297 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2300 /* Mark that this register is in use between its birth and death
2302 post_mark_life (regno, mode, 1, born_index, dead_index);
2305 #ifndef REG_ALLOC_ORDER
2306 i += j; /* Skip starting points we know will lose */
2313 /* If we are just trying suggested register, we have just tried copy-
2314 suggested registers, and there are arithmetic-suggested registers,
2317 /* If it would be profitable to allocate a call-clobbered register
2318 and save and restore it around calls, do that. */
2319 if (just_try_suggested && qty_phys_num_copy_sugg[qty] != 0
2320 && qty_phys_num_sugg[qty] != 0)
2322 /* Don't try the copy-suggested regs again. */
2323 qty_phys_num_copy_sugg[qty] = 0;
2324 return find_free_reg (class, mode, qty, accept_call_clobbered, 1,
2325 born_index, dead_index);
2328 /* We need not check to see if the current function has nonlocal
2329 labels because we don't put any pseudos that are live over calls in
2330 registers in that case. */
2332 if (! accept_call_clobbered
2333 && flag_caller_saves
2334 && ! just_try_suggested
2335 && qty_n_calls_crossed[qty] != 0
2336 && CALLER_SAVE_PROFITABLE (qty_n_refs[qty], qty_n_calls_crossed[qty]))
2338 i = find_free_reg (class, mode, qty, 1, 0, born_index, dead_index);
2340 caller_save_needed = 1;
2346 /* Mark that REGNO with machine-mode MODE is live starting from the current
2347 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2351 mark_life (regno, mode, life)
2353 enum machine_mode mode;
2356 register int j = HARD_REGNO_NREGS (regno, mode);
2359 SET_HARD_REG_BIT (regs_live, regno + j);
2362 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2365 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2366 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2367 to insn number DEATH (exclusive). */
2370 post_mark_life (regno, mode, life, birth, death)
2372 enum machine_mode mode;
2373 int life, birth, death;
2375 register int j = HARD_REGNO_NREGS (regno, mode);
2377 register /* Declare it register if it's a scalar. */
2379 HARD_REG_SET this_reg;
2381 CLEAR_HARD_REG_SET (this_reg);
2383 SET_HARD_REG_BIT (this_reg, regno + j);
2386 while (birth < death)
2388 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2392 while (birth < death)
2394 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2399 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2400 is the register being clobbered, and R1 is a register being used in
2401 the equivalent expression.
2403 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2404 in which it is used, return 1.
2406 Otherwise, return 0. */
2409 no_conflict_p (insn, r0, r1)
2413 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2416 /* If R1 is a hard register, return 0 since we handle this case
2417 when we scan the insns that actually use it. */
2420 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2421 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2422 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2425 last = XEXP (note, 0);
2427 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2428 if (GET_RTX_CLASS (GET_CODE (p)) == 'i')
2430 if (find_reg_note (p, REG_DEAD, r1))
2433 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2434 some earlier optimization pass has inserted instructions into
2435 the sequence, and it is not safe to perform this optimization.
2436 Note that emit_no_conflict_block always ensures that this is
2437 true when these sequences are created. */
2438 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2445 #ifdef REGISTER_CONSTRAINTS
2447 /* Return the number of alternatives for which the constraint string P
2448 indicates that the operand must be equal to operand 0 and that no register
2457 int reg_allowed = 0;
2458 int num_matching_alts = 0;
2463 case '=': case '+': case '?':
2464 case '#': case '&': case '!':
2466 case '1': case '2': case '3': case '4':
2467 case 'm': case '<': case '>': case 'V': case 'o':
2468 case 'E': case 'F': case 'G': case 'H':
2469 case 's': case 'i': case 'n':
2470 case 'I': case 'J': case 'K': case 'L':
2471 case 'M': case 'N': case 'O': case 'P':
2472 #ifdef EXTRA_CONSTRAINT
2473 case 'Q': case 'R': case 'S': case 'T': case 'U':
2476 /* These don't say anything we care about. */
2480 if (found_zero && ! reg_allowed)
2481 num_matching_alts++;
2483 found_zero = reg_allowed = 0;
2497 if (found_zero && ! reg_allowed)
2498 num_matching_alts++;
2500 return num_matching_alts;
2502 #endif /* REGISTER_CONSTRAINTS */
2505 dump_local_alloc (file)
2509 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2510 if (reg_renumber[i] != -1)
2511 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
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