1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "hard-reg-set.h"
68 #include "basic-block.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
77 /* Next quantity number available for allocation. */
81 /* Information we maitain about each quantity. */
84 /* The number of refs to quantity Q. */
88 /* Insn number (counting from head of basic block)
89 where quantity Q was born. -1 if birth has not been recorded. */
93 /* Insn number (counting from head of basic block)
94 where given quantity died. Due to the way tying is done,
95 and the fact that we consider in this pass only regs that die but once,
96 a quantity can die only once. Each quantity's life span
97 is a set of consecutive insns. -1 if death has not been recorded. */
101 /* Number of words needed to hold the data in given quantity.
102 This depends on its machine mode. It is used for these purposes:
103 1. It is used in computing the relative importances of qtys,
104 which determines the order in which we look for regs for them.
105 2. It is used in rules that prevent tying several registers of
106 different sizes in a way that is geometrically impossible
107 (see combine_regs). */
111 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
115 /* The register number of one pseudo register whose reg_qty value is Q.
116 This register should be the head of the chain
117 maintained in reg_next_in_qty. */
121 /* Reg class contained in (smaller than) the preferred classes of all
122 the pseudo regs that are tied in given quantity.
123 This is the preferred class for allocating that quantity. */
125 enum reg_class min_class;
127 /* Register class within which we allocate given qty if we can't get
128 its preferred class. */
130 enum reg_class alternate_class;
132 /* This holds the mode of the registers that are tied to given qty,
133 or VOIDmode if registers with differing modes are tied together. */
135 enum machine_mode mode;
137 /* the hard reg number chosen for given quantity,
138 or -1 if none was found. */
142 /* Nonzero if this quantity has been used in a SUBREG in some
143 way that is illegal. */
149 static struct qty *qty;
151 /* These fields are kept separately to speedup their clearing. */
153 /* We maintain two hard register sets that indicate suggested hard registers
154 for each quantity. The first, phys_copy_sugg, contains hard registers
155 that are tied to the quantity by a simple copy. The second contains all
156 hard registers that are tied to the quantity via an arithmetic operation.
158 The former register set is given priority for allocation. This tends to
159 eliminate copy insns. */
161 /* Element Q is a set of hard registers that are suggested for quantity Q by
164 static HARD_REG_SET *qty_phys_copy_sugg;
166 /* Element Q is a set of hard registers that are suggested for quantity Q by
169 static HARD_REG_SET *qty_phys_sugg;
171 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
173 static short *qty_phys_num_copy_sugg;
175 /* Element Q is the number of suggested registers in qty_phys_sugg. */
177 static short *qty_phys_num_sugg;
179 /* If (REG N) has been assigned a quantity number, is a register number
180 of another register assigned the same quantity number, or -1 for the
181 end of the chain. qty->first_reg point to the head of this chain. */
183 static int *reg_next_in_qty;
185 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
187 of -1 if this register cannot be allocated by local-alloc,
188 or -2 if not known yet.
190 Note that if we see a use or death of pseudo register N with
191 reg_qty[N] == -2, register N must be local to the current block. If
192 it were used in more than one block, we would have reg_qty[N] == -1.
193 This relies on the fact that if reg_basic_block[N] is >= 0, register N
194 will not appear in any other block. We save a considerable number of
195 tests by exploiting this.
197 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
202 /* The offset (in words) of register N within its quantity.
203 This can be nonzero if register N is SImode, and has been tied
204 to a subreg of a DImode register. */
206 static char *reg_offset;
208 /* Vector of substitutions of register numbers,
209 used to map pseudo regs into hardware regs.
210 This is set up as a result of register allocation.
211 Element N is the hard reg assigned to pseudo reg N,
212 or is -1 if no hard reg was assigned.
213 If N is a hard reg number, element N is N. */
217 /* Set of hard registers live at the current point in the scan
218 of the instructions in a basic block. */
220 static HARD_REG_SET regs_live;
222 /* Each set of hard registers indicates registers live at a particular
223 point in the basic block. For N even, regs_live_at[N] says which
224 hard registers are needed *after* insn N/2 (i.e., they may not
225 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
227 If an object is to conflict with the inputs of insn J but not the
228 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
229 if it is to conflict with the outputs of insn J but not the inputs of
230 insn J + 1, it is said to die at index J*2 + 1. */
232 static HARD_REG_SET *regs_live_at;
234 /* Communicate local vars `insn_number' and `insn'
235 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
236 static int this_insn_number;
237 static rtx this_insn;
239 /* Used to communicate changes made by update_equiv_regs to
240 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
241 found or created, so that we can keep track of what memory accesses might
242 be created later, e.g. by reload. */
244 static rtx *reg_equiv_replacement;
246 /* Used for communication between update_equiv_regs and no_equiv. */
247 static rtx *reg_equiv_init_insns;
249 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
250 static int recorded_label_ref;
252 static void alloc_qty PARAMS ((int, enum machine_mode, int, int));
253 static void validate_equiv_mem_from_store PARAMS ((rtx, rtx, void *));
254 static int validate_equiv_mem PARAMS ((rtx, rtx, rtx));
255 static int contains_replace_regs PARAMS ((rtx, char *));
256 static int memref_referenced_p PARAMS ((rtx, rtx));
257 static int memref_used_between_p PARAMS ((rtx, rtx, rtx));
258 static void update_equiv_regs PARAMS ((void));
259 static void no_equiv PARAMS ((rtx, rtx, void *));
260 static void block_alloc PARAMS ((int));
261 static int qty_sugg_compare PARAMS ((int, int));
262 static int qty_sugg_compare_1 PARAMS ((const PTR, const PTR));
263 static int qty_compare PARAMS ((int, int));
264 static int qty_compare_1 PARAMS ((const PTR, const PTR));
265 static int combine_regs PARAMS ((rtx, rtx, int, int, rtx, int));
266 static int reg_meets_class_p PARAMS ((int, enum reg_class));
267 static void update_qty_class PARAMS ((int, int));
268 static void reg_is_set PARAMS ((rtx, rtx, void *));
269 static void reg_is_born PARAMS ((rtx, int));
270 static void wipe_dead_reg PARAMS ((rtx, int));
271 static int find_free_reg PARAMS ((enum reg_class, enum machine_mode,
272 int, int, int, int, int));
273 static void mark_life PARAMS ((int, enum machine_mode, int));
274 static void post_mark_life PARAMS ((int, enum machine_mode, int, int, int));
275 static int no_conflict_p PARAMS ((rtx, rtx, rtx));
276 static int requires_inout PARAMS ((const char *));
278 /* Allocate a new quantity (new within current basic block)
279 for register number REGNO which is born at index BIRTH
280 within the block. MODE and SIZE are info on reg REGNO. */
283 alloc_qty (regno, mode, size, birth)
285 enum machine_mode mode;
288 register int qtyno = next_qty++;
290 reg_qty[regno] = qtyno;
291 reg_offset[regno] = 0;
292 reg_next_in_qty[regno] = -1;
294 qty[qtyno].first_reg = regno;
295 qty[qtyno].size = size;
296 qty[qtyno].mode = mode;
297 qty[qtyno].birth = birth;
298 qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno);
299 qty[qtyno].min_class = reg_preferred_class (regno);
300 qty[qtyno].alternate_class = reg_alternate_class (regno);
301 qty[qtyno].n_refs = REG_N_REFS (regno);
302 qty[qtyno].changes_mode = REG_CHANGES_MODE (regno);
305 /* Main entry point of this file. */
313 /* We need to keep track of whether or not we recorded a LABEL_REF so
314 that we know if the jump optimizer needs to be rerun. */
315 recorded_label_ref = 0;
317 /* Leaf functions and non-leaf functions have different needs.
318 If defined, let the machine say what kind of ordering we
320 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
321 ORDER_REGS_FOR_LOCAL_ALLOC;
324 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
326 update_equiv_regs ();
328 /* This sets the maximum number of quantities we can have. Quantity
329 numbers start at zero and we can have one for each pseudo. */
330 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
332 /* Allocate vectors of temporary data.
333 See the declarations of these variables, above,
334 for what they mean. */
336 qty = (struct qty *) xmalloc (max_qty * sizeof (struct qty));
338 = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
339 qty_phys_num_copy_sugg = (short *) xmalloc (max_qty * sizeof (short));
340 qty_phys_sugg = (HARD_REG_SET *) xmalloc (max_qty * sizeof (HARD_REG_SET));
341 qty_phys_num_sugg = (short *) xmalloc (max_qty * sizeof (short));
343 reg_qty = (int *) xmalloc (max_regno * sizeof (int));
344 reg_offset = (char *) xmalloc (max_regno * sizeof (char));
345 reg_next_in_qty = (int *) xmalloc (max_regno * sizeof (int));
347 /* Allocate the reg_renumber array. */
348 allocate_reg_info (max_regno, FALSE, TRUE);
350 /* Determine which pseudo-registers can be allocated by local-alloc.
351 In general, these are the registers used only in a single block and
354 We need not be concerned with which block actually uses the register
355 since we will never see it outside that block. */
357 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
359 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1)
365 /* Force loop below to initialize entire quantity array. */
368 /* Allocate each block's local registers, block by block. */
370 for (b = 0; b < n_basic_blocks; b++)
372 /* NEXT_QTY indicates which elements of the `qty_...'
373 vectors might need to be initialized because they were used
374 for the previous block; it is set to the entire array before
375 block 0. Initialize those, with explicit loop if there are few,
376 else with bzero and bcopy. Do not initialize vectors that are
377 explicit set by `alloc_qty'. */
381 for (i = 0; i < next_qty; i++)
383 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
384 qty_phys_num_copy_sugg[i] = 0;
385 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
386 qty_phys_num_sugg[i] = 0;
391 #define CLEAR(vector) \
392 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
394 CLEAR (qty_phys_copy_sugg);
395 CLEAR (qty_phys_num_copy_sugg);
396 CLEAR (qty_phys_sugg);
397 CLEAR (qty_phys_num_sugg);
406 free (qty_phys_copy_sugg);
407 free (qty_phys_num_copy_sugg);
408 free (qty_phys_sugg);
409 free (qty_phys_num_sugg);
413 free (reg_next_in_qty);
415 return recorded_label_ref;
418 /* Depth of loops we are in while in update_equiv_regs. */
419 static int loop_depth;
421 /* Used for communication between the following two functions: contains
422 a MEM that we wish to ensure remains unchanged. */
423 static rtx equiv_mem;
425 /* Set nonzero if EQUIV_MEM is modified. */
426 static int equiv_mem_modified;
428 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
429 Called via note_stores. */
432 validate_equiv_mem_from_store (dest, set, data)
434 rtx set ATTRIBUTE_UNUSED;
435 void *data ATTRIBUTE_UNUSED;
437 if ((GET_CODE (dest) == REG
438 && reg_overlap_mentioned_p (dest, equiv_mem))
439 || (GET_CODE (dest) == MEM
440 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
441 equiv_mem_modified = 1;
444 /* Verify that no store between START and the death of REG invalidates
445 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
446 by storing into an overlapping memory location, or with a non-const
449 Return 1 if MEMREF remains valid. */
452 validate_equiv_mem (start, reg, memref)
461 equiv_mem_modified = 0;
463 /* If the memory reference has side effects or is volatile, it isn't a
464 valid equivalence. */
465 if (side_effects_p (memref))
468 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
473 if (find_reg_note (insn, REG_DEAD, reg))
476 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
477 && ! CONST_CALL_P (insn))
480 note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
482 /* If a register mentioned in MEMREF is modified via an
483 auto-increment, we lose the equivalence. Do the same if one
484 dies; although we could extend the life, it doesn't seem worth
487 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
488 if ((REG_NOTE_KIND (note) == REG_INC
489 || REG_NOTE_KIND (note) == REG_DEAD)
490 && GET_CODE (XEXP (note, 0)) == REG
491 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
498 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
501 contains_replace_regs (x, reg_equiv_replace)
503 char *reg_equiv_replace;
507 enum rtx_code code = GET_CODE (x);
523 return reg_equiv_replace[REGNO (x)];
529 fmt = GET_RTX_FORMAT (code);
530 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
534 if (contains_replace_regs (XEXP (x, i), reg_equiv_replace))
538 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
539 if (contains_replace_regs (XVECEXP (x, i, j), reg_equiv_replace))
547 /* TRUE if X references a memory location that would be affected by a store
551 memref_referenced_p (memref, x)
557 enum rtx_code code = GET_CODE (x);
573 return (reg_equiv_replacement[REGNO (x)]
574 && memref_referenced_p (memref,
575 reg_equiv_replacement[REGNO (x)]));
578 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
583 /* If we are setting a MEM, it doesn't count (its address does), but any
584 other SET_DEST that has a MEM in it is referencing the MEM. */
585 if (GET_CODE (SET_DEST (x)) == MEM)
587 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
590 else if (memref_referenced_p (memref, SET_DEST (x)))
593 return memref_referenced_p (memref, SET_SRC (x));
599 fmt = GET_RTX_FORMAT (code);
600 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
604 if (memref_referenced_p (memref, XEXP (x, i)))
608 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
609 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
617 /* TRUE if some insn in the range (START, END] references a memory location
618 that would be affected by a store to MEMREF. */
621 memref_used_between_p (memref, start, end)
628 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
629 insn = NEXT_INSN (insn))
630 if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn)))
636 /* Return nonzero if the rtx X is invariant over the current function. */
638 function_invariant_p (x)
643 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
645 if (GET_CODE (x) == PLUS
646 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
647 && CONSTANT_P (XEXP (x, 1)))
652 /* Find registers that are equivalent to a single value throughout the
653 compilation (either because they can be referenced in memory or are set once
654 from a single constant). Lower their priority for a register.
656 If such a register is only referenced once, try substituting its value
657 into the using insn. If it succeeds, we can eliminate the register
663 /* Set when an attempt should be made to replace a register with the
664 associated reg_equiv_replacement entry at the end of this function. */
665 char *reg_equiv_replace;
669 reg_equiv_replace = (char *) xcalloc (max_regno, sizeof *reg_equiv_replace);
670 reg_equiv_init_insns = (rtx *) xcalloc (max_regno, sizeof (rtx));
671 reg_equiv_replacement = (rtx *) xcalloc (max_regno, sizeof (rtx));
673 init_alias_analysis ();
677 /* Scan the insns and find which registers have equivalences. Do this
678 in a separate scan of the insns because (due to -fcse-follow-jumps)
679 a register can be set below its use. */
680 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
687 if (GET_CODE (insn) == NOTE)
689 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
691 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
698 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
699 if (REG_NOTE_KIND (note) == REG_INC)
700 no_equiv (XEXP (note, 0), note, NULL);
702 set = single_set (insn);
704 /* If this insn contains more (or less) than a single SET,
705 only mark all destinations as having no known equivalence. */
708 note_stores (PATTERN (insn), no_equiv, NULL);
711 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
715 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
717 rtx part = XVECEXP (PATTERN (insn), 0, i);
719 note_stores (part, no_equiv, NULL);
723 dest = SET_DEST (set);
726 /* If this sets a MEM to the contents of a REG that is only used
727 in a single basic block, see if the register is always equivalent
728 to that memory location and if moving the store from INSN to the
729 insn that set REG is safe. If so, put a REG_EQUIV note on the
732 Don't add a REG_EQUIV note if the insn already has one. The existing
733 REG_EQUIV is likely more useful than the one we are adding.
735 If one of the regs in the address is marked as reg_equiv_replace,
736 then we can't add this REG_EQUIV note. The reg_equiv_replace
737 optimization may move the set of this register immediately before
738 insn, which puts it after reg_equiv_init_insns[regno], and hence
739 the mention in the REG_EQUIV note would be to an uninitialized
741 /* ????? This test isn't good enough; we might see a MEM with a use of
742 a pseudo register before we see its setting insn that will cause
743 reg_equiv_replace for that pseudo to be set.
744 Equivalences to MEMs should be made in another pass, after the
745 reg_equiv_replace information has been gathered. */
747 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
748 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
749 && REG_BASIC_BLOCK (regno) >= 0
750 && REG_N_SETS (regno) == 1
751 && reg_equiv_init_insns[regno] != 0
752 && reg_equiv_init_insns[regno] != const0_rtx
753 && ! find_reg_note (XEXP (reg_equiv_init_insns[regno], 0),
755 && ! contains_replace_regs (XEXP (dest, 0), reg_equiv_replace))
757 rtx init_insn = XEXP (reg_equiv_init_insns[regno], 0);
758 if (validate_equiv_mem (init_insn, src, dest)
759 && ! memref_used_between_p (dest, init_insn, insn))
760 REG_NOTES (init_insn)
761 = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn));
764 /* We only handle the case of a pseudo register being set
765 once, or always to the same value. */
766 /* ??? The mn10200 port breaks if we add equivalences for
767 values that need an ADDRESS_REGS register and set them equivalent
768 to a MEM of a pseudo. The actual problem is in the over-conservative
769 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
770 calculate_needs, but we traditionally work around this problem
771 here by rejecting equivalences when the destination is in a register
772 that's likely spilled. This is fragile, of course, since the
773 preferred class of a pseudo depends on all instructions that set
776 if (GET_CODE (dest) != REG
777 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
778 || reg_equiv_init_insns[regno] == const0_rtx
779 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
780 && GET_CODE (src) == MEM))
782 /* This might be seting a SUBREG of a pseudo, a pseudo that is
783 also set somewhere else to a constant. */
784 note_stores (set, no_equiv, NULL);
788 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
790 if (REG_N_SETS (regno) != 1
792 || ! function_invariant_p (XEXP (note, 0))
793 || (reg_equiv_replacement[regno]
794 && ! rtx_equal_p (XEXP (note, 0),
795 reg_equiv_replacement[regno]))))
797 no_equiv (dest, set, NULL);
800 /* Record this insn as initializing this register. */
801 reg_equiv_init_insns[regno]
802 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init_insns[regno]);
804 /* If this register is known to be equal to a constant, record that
805 it is always equivalent to the constant. */
806 if (note && function_invariant_p (XEXP (note, 0)))
807 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
809 /* If this insn introduces a "constant" register, decrease the priority
810 of that register. Record this insn if the register is only used once
811 more and the equivalence value is the same as our source.
813 The latter condition is checked for two reasons: First, it is an
814 indication that it may be more efficient to actually emit the insn
815 as written (if no registers are available, reload will substitute
816 the equivalence). Secondly, it avoids problems with any registers
817 dying in this insn whose death notes would be missed.
819 If we don't have a REG_EQUIV note, see if this insn is loading
820 a register used only in one basic block from a MEM. If so, and the
821 MEM remains unchanged for the life of the register, add a REG_EQUIV
824 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
826 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
827 && GET_CODE (SET_SRC (set)) == MEM
828 && validate_equiv_mem (insn, dest, SET_SRC (set)))
829 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
834 int regno = REGNO (dest);
836 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
837 We might end up substituting the LABEL_REF for uses of the
838 pseudo here or later. That kind of transformation may turn an
839 indirect jump into a direct jump, in which case we must rerun the
840 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
841 if (GET_CODE (XEXP (note, 0)) == LABEL_REF
842 || (GET_CODE (XEXP (note, 0)) == CONST
843 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
844 && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0))
846 recorded_label_ref = 1;
848 reg_equiv_replacement[regno] = XEXP (note, 0);
850 /* Don't mess with things live during setjmp. */
851 if (REG_LIVE_LENGTH (regno) >= 0)
853 /* Note that the statement below does not affect the priority
855 REG_LIVE_LENGTH (regno) *= 2;
858 /* If the register is referenced exactly twice, meaning it is
859 set once and used once, indicate that the reference may be
860 replaced by the equivalence we computed above. If the
861 register is only used in one basic block, this can't succeed
862 or combine would have done it.
864 It would be nice to use "loop_depth * 2" in the compare
865 below. Unfortunately, LOOP_DEPTH need not be constant within
866 a basic block so this would be too complicated.
868 This case normally occurs when a parameter is read from
869 memory and then used exactly once, not in a loop. */
871 if (REG_N_REFS (regno) == 2
872 && REG_BASIC_BLOCK (regno) < 0
873 && rtx_equal_p (XEXP (note, 0), SET_SRC (set)))
874 reg_equiv_replace[regno] = 1;
879 /* Now scan all regs killed in an insn to see if any of them are
880 registers only used that once. If so, see if we can replace the
881 reference with the equivalent from. If we can, delete the
882 initializing reference and this register will go away. If we
883 can't replace the reference, and the instruction is not in a
884 loop, then move the register initialization just before the use,
885 so that they are in the same basic block. */
888 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
892 /* Keep track of which basic block we are in. */
893 if (block + 1 < n_basic_blocks
894 && BLOCK_HEAD (block + 1) == insn)
899 if (GET_CODE (insn) == NOTE)
901 if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_BEG)
903 else if (NOTE_LINE_NUMBER (insn) == NOTE_INSN_LOOP_END)
914 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
916 if (REG_NOTE_KIND (link) == REG_DEAD
917 /* Make sure this insn still refers to the register. */
918 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
920 int regno = REGNO (XEXP (link, 0));
923 if (! reg_equiv_replace[regno])
926 /* reg_equiv_replace[REGNO] gets set only when
927 REG_N_REFS[REGNO] is 2, i.e. the register is set
928 once and used once. (If it were only set, but not used,
929 flow would have deleted the setting insns.) Hence
930 there can only be one insn in reg_equiv_init_insns. */
931 equiv_insn = XEXP (reg_equiv_init_insns[regno], 0);
933 if (validate_replace_rtx (regno_reg_rtx[regno],
934 reg_equiv_replacement[regno], insn))
936 remove_death (regno, insn);
937 REG_N_REFS (regno) = 0;
938 PUT_CODE (equiv_insn, NOTE);
939 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
940 NOTE_SOURCE_FILE (equiv_insn) = 0;
942 /* If we aren't in a loop, and there are no calls in
943 INSN or in the initialization of the register, then
944 move the initialization of the register to just
945 before INSN. Update the flow information. */
947 && GET_CODE (equiv_insn) == INSN
948 && GET_CODE (insn) == INSN
949 && REG_BASIC_BLOCK (regno) < 0)
953 emit_insn_before (copy_rtx (PATTERN (equiv_insn)), insn);
954 REG_NOTES (PREV_INSN (insn)) = REG_NOTES (equiv_insn);
955 REG_NOTES (equiv_insn) = 0;
957 PUT_CODE (equiv_insn, NOTE);
958 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
959 NOTE_SOURCE_FILE (equiv_insn) = 0;
962 REG_BASIC_BLOCK (regno) = 0;
964 REG_BASIC_BLOCK (regno) = block;
965 REG_N_CALLS_CROSSED (regno) = 0;
966 REG_LIVE_LENGTH (regno) = 2;
968 if (block >= 0 && insn == BLOCK_HEAD (block))
969 BLOCK_HEAD (block) = PREV_INSN (insn);
971 for (l = 0; l < n_basic_blocks; l++)
972 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l)->global_live_at_start,
980 end_alias_analysis ();
981 free (reg_equiv_replace);
982 free (reg_equiv_init_insns);
983 free (reg_equiv_replacement);
986 /* Mark REG as having no known equivalence.
987 Some instructions might have been proceessed before and furnished
988 with REG_EQUIV notes for this register; these notes will have to be
990 STORE is the piece of RTL that does the non-constant / conflicting
991 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
992 but needs to be there because this function is called from note_stores. */
994 no_equiv (reg, store, data)
995 rtx reg, store ATTRIBUTE_UNUSED;
996 void *data ATTRIBUTE_UNUSED;
1001 if (GET_CODE (reg) != REG)
1003 regno = REGNO (reg);
1004 list = reg_equiv_init_insns[regno];
1005 if (list == const0_rtx)
1007 for (; list; list = XEXP (list, 1))
1009 rtx insn = XEXP (list, 0);
1010 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
1012 reg_equiv_init_insns[regno] = const0_rtx;
1013 reg_equiv_replacement[regno] = NULL_RTX;
1016 /* Allocate hard regs to the pseudo regs used only within block number B.
1017 Only the pseudos that die but once can be handled. */
1026 int insn_number = 0;
1028 int max_uid = get_max_uid ();
1030 int no_conflict_combined_regno = -1;
1032 /* Count the instructions in the basic block. */
1034 insn = BLOCK_END (b);
1037 if (GET_CODE (insn) != NOTE)
1038 if (++insn_count > max_uid)
1040 if (insn == BLOCK_HEAD (b))
1042 insn = PREV_INSN (insn);
1045 /* +2 to leave room for a post_mark_life at the last insn and for
1046 the birth of a CLOBBER in the first insn. */
1047 regs_live_at = (HARD_REG_SET *) xcalloc ((2 * insn_count + 2),
1048 sizeof (HARD_REG_SET));
1050 /* Initialize table of hardware registers currently live. */
1052 REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start);
1054 /* This loop scans the instructions of the basic block
1055 and assigns quantities to registers.
1056 It computes which registers to tie. */
1058 insn = BLOCK_HEAD (b);
1061 if (GET_CODE (insn) != NOTE)
1066 register rtx link, set;
1067 register int win = 0;
1068 register rtx r0, r1 = NULL_RTX;
1069 int combined_regno = -1;
1072 this_insn_number = insn_number;
1075 extract_insn (insn);
1076 which_alternative = -1;
1078 /* Is this insn suitable for tying two registers?
1079 If so, try doing that.
1080 Suitable insns are those with at least two operands and where
1081 operand 0 is an output that is a register that is not
1084 We can tie operand 0 with some operand that dies in this insn.
1085 First look for operands that are required to be in the same
1086 register as operand 0. If we find such, only try tying that
1087 operand or one that can be put into that operand if the
1088 operation is commutative. If we don't find an operand
1089 that is required to be in the same register as operand 0,
1090 we can tie with any operand.
1092 Subregs in place of regs are also ok.
1094 If tying is done, WIN is set nonzero. */
1097 && recog_data.n_operands > 1
1098 && recog_data.constraints[0][0] == '='
1099 && recog_data.constraints[0][1] != '&')
1101 /* If non-negative, is an operand that must match operand 0. */
1102 int must_match_0 = -1;
1103 /* Counts number of alternatives that require a match with
1105 int n_matching_alts = 0;
1107 for (i = 1; i < recog_data.n_operands; i++)
1109 const char *p = recog_data.constraints[i];
1110 int this_match = (requires_inout (p));
1112 n_matching_alts += this_match;
1113 if (this_match == recog_data.n_alternatives)
1117 r0 = recog_data.operand[0];
1118 for (i = 1; i < recog_data.n_operands; i++)
1120 /* Skip this operand if we found an operand that
1121 must match operand 0 and this operand isn't it
1122 and can't be made to be it by commutativity. */
1124 if (must_match_0 >= 0 && i != must_match_0
1125 && ! (i == must_match_0 + 1
1126 && recog_data.constraints[i-1][0] == '%')
1127 && ! (i == must_match_0 - 1
1128 && recog_data.constraints[i][0] == '%'))
1131 /* Likewise if each alternative has some operand that
1132 must match operand zero. In that case, skip any
1133 operand that doesn't list operand 0 since we know that
1134 the operand always conflicts with operand 0. We
1135 ignore commutatity in this case to keep things simple. */
1136 if (n_matching_alts == recog_data.n_alternatives
1137 && 0 == requires_inout (recog_data.constraints[i]))
1140 r1 = recog_data.operand[i];
1142 /* If the operand is an address, find a register in it.
1143 There may be more than one register, but we only try one
1145 if (recog_data.constraints[i][0] == 'p')
1146 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1149 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1151 /* We have two priorities for hard register preferences.
1152 If we have a move insn or an insn whose first input
1153 can only be in the same register as the output, give
1154 priority to an equivalence found from that insn. */
1156 = (r1 == recog_data.operand[i] && must_match_0 >= 0);
1158 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1159 win = combine_regs (r1, r0, may_save_copy,
1160 insn_number, insn, 0);
1167 /* Recognize an insn sequence with an ultimate result
1168 which can safely overlap one of the inputs.
1169 The sequence begins with a CLOBBER of its result,
1170 and ends with an insn that copies the result to itself
1171 and has a REG_EQUAL note for an equivalent formula.
1172 That note indicates what the inputs are.
1173 The result and the input can overlap if each insn in
1174 the sequence either doesn't mention the input
1175 or has a REG_NO_CONFLICT note to inhibit the conflict.
1177 We do the combining test at the CLOBBER so that the
1178 destination register won't have had a quantity number
1179 assigned, since that would prevent combining. */
1182 && GET_CODE (PATTERN (insn)) == CLOBBER
1183 && (r0 = XEXP (PATTERN (insn), 0),
1184 GET_CODE (r0) == REG)
1185 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1186 && XEXP (link, 0) != 0
1187 && GET_CODE (XEXP (link, 0)) == INSN
1188 && (set = single_set (XEXP (link, 0))) != 0
1189 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1190 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1193 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1194 /* Check that we have such a sequence. */
1195 && no_conflict_p (insn, r0, r1))
1196 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1197 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1198 && (r1 = XEXP (XEXP (note, 0), 0),
1199 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1200 && no_conflict_p (insn, r0, r1))
1201 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1203 /* Here we care if the operation to be computed is
1205 else if ((GET_CODE (XEXP (note, 0)) == EQ
1206 || GET_CODE (XEXP (note, 0)) == NE
1207 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1208 && (r1 = XEXP (XEXP (note, 0), 1),
1209 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1210 && no_conflict_p (insn, r0, r1))
1211 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1213 /* If we did combine something, show the register number
1214 in question so that we know to ignore its death. */
1216 no_conflict_combined_regno = REGNO (r1);
1219 /* If registers were just tied, set COMBINED_REGNO
1220 to the number of the register used in this insn
1221 that was tied to the register set in this insn.
1222 This register's qty should not be "killed". */
1226 while (GET_CODE (r1) == SUBREG)
1227 r1 = SUBREG_REG (r1);
1228 combined_regno = REGNO (r1);
1231 /* Mark the death of everything that dies in this instruction,
1232 except for anything that was just combined. */
1234 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1235 if (REG_NOTE_KIND (link) == REG_DEAD
1236 && GET_CODE (XEXP (link, 0)) == REG
1237 && combined_regno != (int) REGNO (XEXP (link, 0))
1238 && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0))
1239 || ! find_reg_note (insn, REG_NO_CONFLICT,
1241 wipe_dead_reg (XEXP (link, 0), 0);
1243 /* Allocate qty numbers for all registers local to this block
1244 that are born (set) in this instruction.
1245 A pseudo that already has a qty is not changed. */
1247 note_stores (PATTERN (insn), reg_is_set, NULL);
1249 /* If anything is set in this insn and then unused, mark it as dying
1250 after this insn, so it will conflict with our outputs. This
1251 can't match with something that combined, and it doesn't matter
1252 if it did. Do this after the calls to reg_is_set since these
1253 die after, not during, the current insn. */
1255 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1256 if (REG_NOTE_KIND (link) == REG_UNUSED
1257 && GET_CODE (XEXP (link, 0)) == REG)
1258 wipe_dead_reg (XEXP (link, 0), 1);
1260 /* If this is an insn that has a REG_RETVAL note pointing at a
1261 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1262 block, so clear any register number that combined within it. */
1263 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1264 && GET_CODE (XEXP (note, 0)) == INSN
1265 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1266 no_conflict_combined_regno = -1;
1269 /* Set the registers live after INSN_NUMBER. Note that we never
1270 record the registers live before the block's first insn, since no
1271 pseudos we care about are live before that insn. */
1273 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1274 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1276 if (insn == BLOCK_END (b))
1279 insn = NEXT_INSN (insn);
1282 /* Now every register that is local to this basic block
1283 should have been given a quantity, or else -1 meaning ignore it.
1284 Every quantity should have a known birth and death.
1286 Order the qtys so we assign them registers in order of the
1287 number of suggested registers they need so we allocate those with
1288 the most restrictive needs first. */
1290 qty_order = (int *) xmalloc (next_qty * sizeof (int));
1291 for (i = 0; i < next_qty; i++)
1294 #define EXCHANGE(I1, I2) \
1295 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1300 /* Make qty_order[2] be the one to allocate last. */
1301 if (qty_sugg_compare (0, 1) > 0)
1303 if (qty_sugg_compare (1, 2) > 0)
1306 /* ... Fall through ... */
1308 /* Put the best one to allocate in qty_order[0]. */
1309 if (qty_sugg_compare (0, 1) > 0)
1312 /* ... Fall through ... */
1316 /* Nothing to do here. */
1320 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1323 /* Try to put each quantity in a suggested physical register, if it has one.
1324 This may cause registers to be allocated that otherwise wouldn't be, but
1325 this seems acceptable in local allocation (unlike global allocation). */
1326 for (i = 0; i < next_qty; i++)
1329 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1330 qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q,
1331 0, 1, qty[q].birth, qty[q].death);
1333 qty[q].phys_reg = -1;
1336 /* Order the qtys so we assign them registers in order of
1337 decreasing length of life. Normally call qsort, but if we
1338 have only a very small number of quantities, sort them ourselves. */
1340 for (i = 0; i < next_qty; i++)
1343 #define EXCHANGE(I1, I2) \
1344 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1349 /* Make qty_order[2] be the one to allocate last. */
1350 if (qty_compare (0, 1) > 0)
1352 if (qty_compare (1, 2) > 0)
1355 /* ... Fall through ... */
1357 /* Put the best one to allocate in qty_order[0]. */
1358 if (qty_compare (0, 1) > 0)
1361 /* ... Fall through ... */
1365 /* Nothing to do here. */
1369 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1372 /* Now for each qty that is not a hardware register,
1373 look for a hardware register to put it in.
1374 First try the register class that is cheapest for this qty,
1375 if there is more than one class. */
1377 for (i = 0; i < next_qty; i++)
1380 if (qty[q].phys_reg < 0)
1382 #ifdef INSN_SCHEDULING
1383 /* These values represent the adjusted lifetime of a qty so
1384 that it conflicts with qtys which appear near the start/end
1385 of this qty's lifetime.
1387 The purpose behind extending the lifetime of this qty is to
1388 discourage the register allocator from creating false
1391 The adjustment value is choosen to indicate that this qty
1392 conflicts with all the qtys in the instructions immediately
1393 before and after the lifetime of this qty.
1395 Experiments have shown that higher values tend to hurt
1396 overall code performance.
1398 If allocation using the extended lifetime fails we will try
1399 again with the qty's unadjusted lifetime. */
1400 int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2);
1401 int fake_death = MIN (insn_number * 2 + 1,
1402 qty[q].death + 2 - qty[q].death % 2);
1405 if (N_REG_CLASSES > 1)
1407 #ifdef INSN_SCHEDULING
1408 /* We try to avoid using hard registers allocated to qtys which
1409 are born immediately after this qty or die immediately before
1412 This optimization is only appropriate when we will run
1413 a scheduling pass after reload and we are not optimizing
1415 if (flag_schedule_insns_after_reload
1417 && !SMALL_REGISTER_CLASSES)
1419 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1420 qty[q].mode, q, 0, 0,
1421 fake_birth, fake_death);
1422 if (qty[q].phys_reg >= 0)
1426 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1427 qty[q].mode, q, 0, 0,
1428 qty[q].birth, qty[q].death);
1429 if (qty[q].phys_reg >= 0)
1433 #ifdef INSN_SCHEDULING
1434 /* Similarly, avoid false dependencies. */
1435 if (flag_schedule_insns_after_reload
1437 && !SMALL_REGISTER_CLASSES
1438 && qty[q].alternate_class != NO_REGS)
1439 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1440 qty[q].mode, q, 0, 0,
1441 fake_birth, fake_death);
1443 if (qty[q].alternate_class != NO_REGS)
1444 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1445 qty[q].mode, q, 0, 0,
1446 qty[q].birth, qty[q].death);
1450 /* Now propagate the register assignments
1451 to the pseudo regs belonging to the qtys. */
1453 for (q = 0; q < next_qty; q++)
1454 if (qty[q].phys_reg >= 0)
1456 for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i])
1457 reg_renumber[i] = qty[q].phys_reg + reg_offset[i];
1461 free (regs_live_at);
1465 /* Compare two quantities' priority for getting real registers.
1466 We give shorter-lived quantities higher priority.
1467 Quantities with more references are also preferred, as are quantities that
1468 require multiple registers. This is the identical prioritization as
1469 done by global-alloc.
1471 We used to give preference to registers with *longer* lives, but using
1472 the same algorithm in both local- and global-alloc can speed up execution
1473 of some programs by as much as a factor of three! */
1475 /* Note that the quotient will never be bigger than
1476 the value of floor_log2 times the maximum number of
1477 times a register can occur in one insn (surely less than 100).
1478 Multiplying this by 10000 can't overflow.
1479 QTY_CMP_PRI is also used by qty_sugg_compare. */
1481 #define QTY_CMP_PRI(q) \
1482 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].n_refs * qty[q].size) \
1483 / (qty[q].death - qty[q].birth)) * 10000))
1486 qty_compare (q1, q2)
1489 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1493 qty_compare_1 (q1p, q2p)
1497 register int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1498 register int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1503 /* If qtys are equally good, sort by qty number,
1504 so that the results of qsort leave nothing to chance. */
1508 /* Compare two quantities' priority for getting real registers. This version
1509 is called for quantities that have suggested hard registers. First priority
1510 goes to quantities that have copy preferences, then to those that have
1511 normal preferences. Within those groups, quantities with the lower
1512 number of preferences have the highest priority. Of those, we use the same
1513 algorithm as above. */
1515 #define QTY_CMP_SUGG(q) \
1516 (qty_phys_num_copy_sugg[q] \
1517 ? qty_phys_num_copy_sugg[q] \
1518 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1521 qty_sugg_compare (q1, q2)
1524 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1529 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1533 qty_sugg_compare_1 (q1p, q2p)
1537 register int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1538 register int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1543 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1547 /* If qtys are equally good, sort by qty number,
1548 so that the results of qsort leave nothing to chance. */
1555 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1556 Returns 1 if have done so, or 0 if cannot.
1558 Combining registers means marking them as having the same quantity
1559 and adjusting the offsets within the quantity if either of
1562 We don't actually combine a hard reg with a pseudo; instead
1563 we just record the hard reg as the suggestion for the pseudo's quantity.
1564 If we really combined them, we could lose if the pseudo lives
1565 across an insn that clobbers the hard reg (eg, movstr).
1567 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1568 there is no REG_DEAD note on INSN. This occurs during the processing
1569 of REG_NO_CONFLICT blocks.
1571 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1572 SETREG or if the input and output must share a register.
1573 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1575 There are elaborate checks for the validity of combining. */
1578 combine_regs (usedreg, setreg, may_save_copy, insn_number, insn, already_dead)
1579 rtx usedreg, setreg;
1585 register int ureg, sreg;
1586 register int offset = 0;
1590 /* Determine the numbers and sizes of registers being used. If a subreg
1591 is present that does not change the entire register, don't consider
1592 this a copy insn. */
1594 while (GET_CODE (usedreg) == SUBREG)
1596 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg))) > UNITS_PER_WORD)
1598 offset += SUBREG_WORD (usedreg);
1599 usedreg = SUBREG_REG (usedreg);
1601 if (GET_CODE (usedreg) != REG)
1603 ureg = REGNO (usedreg);
1604 usize = REG_SIZE (usedreg);
1606 while (GET_CODE (setreg) == SUBREG)
1608 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg))) > UNITS_PER_WORD)
1610 offset -= SUBREG_WORD (setreg);
1611 setreg = SUBREG_REG (setreg);
1613 if (GET_CODE (setreg) != REG)
1615 sreg = REGNO (setreg);
1616 ssize = REG_SIZE (setreg);
1618 /* If UREG is a pseudo-register that hasn't already been assigned a
1619 quantity number, it means that it is not local to this block or dies
1620 more than once. In either event, we can't do anything with it. */
1621 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1622 /* Do not combine registers unless one fits within the other. */
1623 || (offset > 0 && usize + offset > ssize)
1624 || (offset < 0 && usize + offset < ssize)
1625 /* Do not combine with a smaller already-assigned object
1626 if that smaller object is already combined with something bigger. */
1627 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1628 && usize < qty[reg_qty[ureg]].size)
1629 /* Can't combine if SREG is not a register we can allocate. */
1630 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1631 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1632 These have already been taken care of. This probably wouldn't
1633 combine anyway, but don't take any chances. */
1634 || (ureg >= FIRST_PSEUDO_REGISTER
1635 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1636 /* Don't tie something to itself. In most cases it would make no
1637 difference, but it would screw up if the reg being tied to itself
1638 also dies in this insn. */
1640 /* Don't try to connect two different hardware registers. */
1641 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1642 /* Don't connect two different machine modes if they have different
1643 implications as to which registers may be used. */
1644 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1647 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1648 qty_phys_sugg for the pseudo instead of tying them.
1650 Return "failure" so that the lifespan of UREG is terminated here;
1651 that way the two lifespans will be disjoint and nothing will prevent
1652 the pseudo reg from being given this hard reg. */
1654 if (ureg < FIRST_PSEUDO_REGISTER)
1656 /* Allocate a quantity number so we have a place to put our
1658 if (reg_qty[sreg] == -2)
1659 reg_is_born (setreg, 2 * insn_number);
1661 if (reg_qty[sreg] >= 0)
1664 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1666 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1667 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1669 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1671 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1672 qty_phys_num_sugg[reg_qty[sreg]]++;
1678 /* Similarly for SREG a hard register and UREG a pseudo register. */
1680 if (sreg < FIRST_PSEUDO_REGISTER)
1683 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1685 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1686 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1688 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1690 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1691 qty_phys_num_sugg[reg_qty[ureg]]++;
1696 /* At this point we know that SREG and UREG are both pseudos.
1697 Do nothing if SREG already has a quantity or is a register that we
1699 if (reg_qty[sreg] >= -1
1700 /* If we are not going to let any regs live across calls,
1701 don't tie a call-crossing reg to a non-call-crossing reg. */
1702 || (current_function_has_nonlocal_label
1703 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1704 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1707 /* We don't already know about SREG, so tie it to UREG
1708 if this is the last use of UREG, provided the classes they want
1711 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1712 && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class))
1714 /* Add SREG to UREG's quantity. */
1715 sqty = reg_qty[ureg];
1716 reg_qty[sreg] = sqty;
1717 reg_offset[sreg] = reg_offset[ureg] + offset;
1718 reg_next_in_qty[sreg] = qty[sqty].first_reg;
1719 qty[sqty].first_reg = sreg;
1721 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1722 update_qty_class (sqty, sreg);
1724 /* Update info about quantity SQTY. */
1725 qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg);
1726 qty[sqty].n_refs += REG_N_REFS (sreg);
1731 for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i])
1732 reg_offset[i] -= offset;
1734 qty[sqty].size = ssize;
1735 qty[sqty].mode = GET_MODE (setreg);
1744 /* Return 1 if the preferred class of REG allows it to be tied
1745 to a quantity or register whose class is CLASS.
1746 True if REG's reg class either contains or is contained in CLASS. */
1749 reg_meets_class_p (reg, class)
1751 enum reg_class class;
1753 register enum reg_class rclass = reg_preferred_class (reg);
1754 return (reg_class_subset_p (rclass, class)
1755 || reg_class_subset_p (class, rclass));
1758 /* Update the class of QTYNO assuming that REG is being tied to it. */
1761 update_qty_class (qtyno, reg)
1765 enum reg_class rclass = reg_preferred_class (reg);
1766 if (reg_class_subset_p (rclass, qty[qtyno].min_class))
1767 qty[qtyno].min_class = rclass;
1769 rclass = reg_alternate_class (reg);
1770 if (reg_class_subset_p (rclass, qty[qtyno].alternate_class))
1771 qty[qtyno].alternate_class = rclass;
1773 if (REG_CHANGES_MODE (reg))
1774 qty[qtyno].changes_mode = 1;
1777 /* Handle something which alters the value of an rtx REG.
1779 REG is whatever is set or clobbered. SETTER is the rtx that
1780 is modifying the register.
1782 If it is not really a register, we do nothing.
1783 The file-global variables `this_insn' and `this_insn_number'
1784 carry info from `block_alloc'. */
1787 reg_is_set (reg, setter, data)
1790 void *data ATTRIBUTE_UNUSED;
1792 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1793 a hard register. These may actually not exist any more. */
1795 if (GET_CODE (reg) != SUBREG
1796 && GET_CODE (reg) != REG)
1799 /* Mark this register as being born. If it is used in a CLOBBER, mark
1800 it as being born halfway between the previous insn and this insn so that
1801 it conflicts with our inputs but not the outputs of the previous insn. */
1803 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
1806 /* Handle beginning of the life of register REG.
1807 BIRTH is the index at which this is happening. */
1810 reg_is_born (reg, birth)
1816 if (GET_CODE (reg) == SUBREG)
1817 regno = REGNO (SUBREG_REG (reg)) + SUBREG_WORD (reg);
1819 regno = REGNO (reg);
1821 if (regno < FIRST_PSEUDO_REGISTER)
1823 mark_life (regno, GET_MODE (reg), 1);
1825 /* If the register was to have been born earlier that the present
1826 insn, mark it as live where it is actually born. */
1827 if (birth < 2 * this_insn_number)
1828 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
1832 if (reg_qty[regno] == -2)
1833 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
1835 /* If this register has a quantity number, show that it isn't dead. */
1836 if (reg_qty[regno] >= 0)
1837 qty[reg_qty[regno]].death = -1;
1841 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1842 REG is an output that is dying (i.e., it is never used), otherwise it
1843 is an input (the normal case).
1844 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1847 wipe_dead_reg (reg, output_p)
1851 register int regno = REGNO (reg);
1853 /* If this insn has multiple results,
1854 and the dead reg is used in one of the results,
1855 extend its life to after this insn,
1856 so it won't get allocated together with any other result of this insn.
1858 It is unsafe to use !single_set here since it will ignore an unused
1859 output. Just because an output is unused does not mean the compiler
1860 can assume the side effect will not occur. Consider if REG appears
1861 in the address of an output and we reload the output. If we allocate
1862 REG to the same hard register as an unused output we could set the hard
1863 register before the output reload insn. */
1864 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
1865 && multiple_sets (this_insn))
1868 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
1870 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
1871 if (GET_CODE (set) == SET
1872 && GET_CODE (SET_DEST (set)) != REG
1873 && !rtx_equal_p (reg, SET_DEST (set))
1874 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
1879 /* If this register is used in an auto-increment address, then extend its
1880 life to after this insn, so that it won't get allocated together with
1881 the result of this insn. */
1882 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
1885 if (regno < FIRST_PSEUDO_REGISTER)
1887 mark_life (regno, GET_MODE (reg), 0);
1889 /* If a hard register is dying as an output, mark it as in use at
1890 the beginning of this insn (the above statement would cause this
1893 post_mark_life (regno, GET_MODE (reg), 1,
1894 2 * this_insn_number, 2 * this_insn_number + 1);
1897 else if (reg_qty[regno] >= 0)
1898 qty[reg_qty[regno]].death = 2 * this_insn_number + output_p;
1901 /* Find a block of SIZE words of hard regs in reg_class CLASS
1902 that can hold something of machine-mode MODE
1903 (but actually we test only the first of the block for holding MODE)
1904 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1905 and return the number of the first of them.
1906 Return -1 if such a block cannot be found.
1907 If QTYNO crosses calls, insist on a register preserved by calls,
1908 unless ACCEPT_CALL_CLOBBERED is nonzero.
1910 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1911 register is available. If not, return -1. */
1914 find_free_reg (class, mode, qtyno, accept_call_clobbered, just_try_suggested,
1915 born_index, dead_index)
1916 enum reg_class class;
1917 enum machine_mode mode;
1919 int accept_call_clobbered;
1920 int just_try_suggested;
1921 int born_index, dead_index;
1923 register int i, ins;
1925 /* Declare it register if it's a scalar. */
1928 HARD_REG_SET used, first_used;
1929 #ifdef ELIMINABLE_REGS
1930 static struct {int from, to; } eliminables[] = ELIMINABLE_REGS;
1933 /* Validate our parameters. */
1934 if (born_index < 0 || born_index > dead_index)
1937 /* Don't let a pseudo live in a reg across a function call
1938 if we might get a nonlocal goto. */
1939 if (current_function_has_nonlocal_label
1940 && qty[qtyno].n_calls_crossed > 0)
1943 if (accept_call_clobbered)
1944 COPY_HARD_REG_SET (used, call_fixed_reg_set);
1945 else if (qty[qtyno].n_calls_crossed == 0)
1946 COPY_HARD_REG_SET (used, fixed_reg_set);
1948 COPY_HARD_REG_SET (used, call_used_reg_set);
1950 if (accept_call_clobbered)
1951 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
1953 for (ins = born_index; ins < dead_index; ins++)
1954 IOR_HARD_REG_SET (used, regs_live_at[ins]);
1956 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
1958 /* Don't use the frame pointer reg in local-alloc even if
1959 we may omit the frame pointer, because if we do that and then we
1960 need a frame pointer, reload won't know how to move the pseudo
1961 to another hard reg. It can move only regs made by global-alloc.
1963 This is true of any register that can be eliminated. */
1964 #ifdef ELIMINABLE_REGS
1965 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
1966 SET_HARD_REG_BIT (used, eliminables[i].from);
1967 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1968 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1969 that it might be eliminated into. */
1970 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
1973 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
1976 #ifdef CLASS_CANNOT_CHANGE_MODE
1977 if (qty[qtyno].changes_mode)
1978 IOR_HARD_REG_SET (used,
1979 reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE]);
1982 /* Normally, the registers that can be used for the first register in
1983 a multi-register quantity are the same as those that can be used for
1984 subsequent registers. However, if just trying suggested registers,
1985 restrict our consideration to them. If there are copy-suggested
1986 register, try them. Otherwise, try the arithmetic-suggested
1988 COPY_HARD_REG_SET (first_used, used);
1990 if (just_try_suggested)
1992 if (qty_phys_num_copy_sugg[qtyno] != 0)
1993 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]);
1995 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]);
1998 /* If all registers are excluded, we can't do anything. */
1999 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2001 /* If at least one would be suitable, test each hard reg. */
2003 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2005 #ifdef REG_ALLOC_ORDER
2006 int regno = reg_alloc_order[i];
2010 if (! TEST_HARD_REG_BIT (first_used, regno)
2011 && HARD_REGNO_MODE_OK (regno, mode)
2012 && (qty[qtyno].n_calls_crossed == 0
2013 || accept_call_clobbered
2014 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
2017 register int size1 = HARD_REGNO_NREGS (regno, mode);
2018 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2021 /* Mark that this register is in use between its birth and death
2023 post_mark_life (regno, mode, 1, born_index, dead_index);
2026 #ifndef REG_ALLOC_ORDER
2027 /* Skip starting points we know will lose. */
2034 /* If we are just trying suggested register, we have just tried copy-
2035 suggested registers, and there are arithmetic-suggested registers,
2038 /* If it would be profitable to allocate a call-clobbered register
2039 and save and restore it around calls, do that. */
2040 if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0
2041 && qty_phys_num_sugg[qtyno] != 0)
2043 /* Don't try the copy-suggested regs again. */
2044 qty_phys_num_copy_sugg[qtyno] = 0;
2045 return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1,
2046 born_index, dead_index);
2049 /* We need not check to see if the current function has nonlocal
2050 labels because we don't put any pseudos that are live over calls in
2051 registers in that case. */
2053 if (! accept_call_clobbered
2054 && flag_caller_saves
2055 && ! just_try_suggested
2056 && qty[qtyno].n_calls_crossed != 0
2057 && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs,
2058 qty[qtyno].n_calls_crossed))
2060 i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index);
2062 caller_save_needed = 1;
2068 /* Mark that REGNO with machine-mode MODE is live starting from the current
2069 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2073 mark_life (regno, mode, life)
2075 enum machine_mode mode;
2078 register int j = HARD_REGNO_NREGS (regno, mode);
2081 SET_HARD_REG_BIT (regs_live, regno + j);
2084 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2087 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2088 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2089 to insn number DEATH (exclusive). */
2092 post_mark_life (regno, mode, life, birth, death)
2094 enum machine_mode mode;
2095 int life, birth, death;
2097 register int j = HARD_REGNO_NREGS (regno, mode);
2099 /* Declare it register if it's a scalar. */
2102 HARD_REG_SET this_reg;
2104 CLEAR_HARD_REG_SET (this_reg);
2106 SET_HARD_REG_BIT (this_reg, regno + j);
2109 while (birth < death)
2111 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2115 while (birth < death)
2117 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2122 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2123 is the register being clobbered, and R1 is a register being used in
2124 the equivalent expression.
2126 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2127 in which it is used, return 1.
2129 Otherwise, return 0. */
2132 no_conflict_p (insn, r0, r1)
2133 rtx insn, r0 ATTRIBUTE_UNUSED, r1;
2136 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2139 /* If R1 is a hard register, return 0 since we handle this case
2140 when we scan the insns that actually use it. */
2143 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2144 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2145 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2148 last = XEXP (note, 0);
2150 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2153 if (find_reg_note (p, REG_DEAD, r1))
2156 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2157 some earlier optimization pass has inserted instructions into
2158 the sequence, and it is not safe to perform this optimization.
2159 Note that emit_no_conflict_block always ensures that this is
2160 true when these sequences are created. */
2161 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2168 /* Return the number of alternatives for which the constraint string P
2169 indicates that the operand must be equal to operand 0 and that no register
2178 int reg_allowed = 0;
2179 int num_matching_alts = 0;
2184 case '=': case '+': case '?':
2185 case '#': case '&': case '!':
2187 case '1': case '2': case '3': case '4': case '5':
2188 case '6': case '7': case '8': case '9':
2189 case 'm': case '<': case '>': case 'V': case 'o':
2190 case 'E': case 'F': case 'G': case 'H':
2191 case 's': case 'i': case 'n':
2192 case 'I': case 'J': case 'K': case 'L':
2193 case 'M': case 'N': case 'O': case 'P':
2195 /* These don't say anything we care about. */
2199 if (found_zero && ! reg_allowed)
2200 num_matching_alts++;
2202 found_zero = reg_allowed = 0;
2210 if (REG_CLASS_FROM_LETTER (c) == NO_REGS)
2219 if (found_zero && ! reg_allowed)
2220 num_matching_alts++;
2222 return num_matching_alts;
2226 dump_local_alloc (file)
2230 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2231 if (reg_renumber[i] != -1)
2232 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);